1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
70 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
73 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
75 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
76 static int smallest_imm_type
PARAMS ((offsetT
));
77 static offsetT offset_in_range
PARAMS ((offsetT
, int));
78 static int add_prefix
PARAMS ((unsigned int));
79 static void set_code_flag
PARAMS ((int));
80 static void set_16bit_gcc_code_flag
PARAMS ((int));
81 static void set_intel_syntax
PARAMS ((int));
82 static void set_cpu_arch
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((void));
108 static void output_disp
PARAMS ((void));
110 static void s_bss
PARAMS ((int));
113 static const char *default_arch
= DEFAULT_ARCH
;
115 /* 'md_assemble ()' gathers together information and puts it into a
122 const reg_entry
*regs
;
127 /* TM holds the template for the insn were currently assembling. */
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
134 /* OPERANDS gives the number of given operands. */
135 unsigned int operands
;
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
140 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
142 /* TYPES [i] is the type (see above #defines) which tells us how to
143 use OP[i] for the corresponding operand. */
144 unsigned int types
[MAX_OPERANDS
];
146 /* Displacement expression, immediate expression, or register for each
148 union i386_op op
[MAX_OPERANDS
];
150 /* Flags for operands. */
151 unsigned int flags
[MAX_OPERANDS
];
152 #define Operand_PCrel 1
154 /* Relocation type for operand */
155 RELOC_ENUM reloc
[MAX_OPERANDS
];
157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry
*base_reg
;
160 const reg_entry
*index_reg
;
161 unsigned int log2_scale_factor
;
163 /* SEG gives the seg_entries of this insn. They are zero unless
164 explicit segment overrides are given. */
165 const seg_entry
*seg
[2];
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes
;
170 unsigned char prefix
[MAX_PREFIXES
];
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
180 typedef struct _i386_insn i386_insn
;
182 /* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars
[] = "*%-(@";
187 const char extra_symbol_chars
[] = "*%-(";
190 #if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
195 /* This array holds the chars that always start a comment. If the
196 pre-processor is disabled, these aren't very useful. */
197 const char comment_chars
[] = "#/";
198 #define PREFIX_SEPARATOR '\\'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "";
211 /* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213 const char comment_chars
[] = "#";
214 #define PREFIX_SEPARATOR '/'
216 const char line_comment_chars
[] = "/";
219 const char line_separator_chars
[] = ";";
221 /* Chars that can be used to separate mant from exp in floating point
223 const char EXP_CHARS
[] = "eE";
225 /* Chars that mean this number is a floating point constant
228 const char FLT_CHARS
[] = "fFdDxX";
230 /* Tables for lexical analysis. */
231 static char mnemonic_chars
[256];
232 static char register_chars
[256];
233 static char operand_chars
[256];
234 static char identifier_chars
[256];
235 static char digit_chars
[256];
237 /* Lexical macros. */
238 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239 #define is_operand_char(x) (operand_chars[(unsigned char) x])
240 #define is_register_char(x) (register_chars[(unsigned char) x])
241 #define is_space_char(x) ((x) == ' ')
242 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243 #define is_digit_char(x) (digit_chars[(unsigned char) x])
245 /* All non-digit non-letter charcters that may occur in an operand. */
246 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
248 /* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
251 assembler instruction). */
252 static char save_stack
[32];
253 static char *save_stack_p
;
254 #define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256 #define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
259 /* The instruction we're assembling. */
262 /* Possible templates for current insn. */
263 static const templates
*current_templates
;
265 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
266 static expressionS disp_expressions
[2], im_expressions
[2];
268 /* Current operand we are working on. */
269 static int this_operand
;
271 /* We support four different modes. FLAG_CODE variable is used to distinguish
278 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
280 static enum flag_code flag_code
;
281 static int use_rela_relocations
= 0;
283 /* The names used to print error messages. */
284 static const char *flag_code_names
[] =
291 /* 1 for intel syntax,
293 static int intel_syntax
= 0;
295 /* 1 if register prefix % not required. */
296 static int allow_naked_reg
= 0;
298 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301 static char stackop_size
= '\0';
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings
= 0;
307 static const char *cpu_arch_name
= NULL
;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion
= 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* Interface to relax_segment.
320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
325 #define UNCOND_JUMP 0
327 #define COND_JUMP86 2
332 #define SMALL16 (SMALL | CODE16)
334 #define BIG16 (BIG | CODE16)
338 #define INLINE __inline__
344 #define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346 #define TYPE_FROM_RELAX_STATE(s) \
348 #define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
351 /* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
359 const relax_typeS md_relax_table
[] =
362 1) most positive reach of this state,
363 2) most negative reach of this state,
364 3) how many bytes this mode will have in the variable part of the frag
365 4) which index into the table to try if we can't fit into this one. */
367 /* UNCOND_JUMP states. */
368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
383 /* word conditionals add 3 bytes to frag:
384 1 extra opcode byte, 2 displacement bytes. */
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
398 static const arch_entry cpu_arch
[] = {
400 {"i186", Cpu086
|Cpu186
},
401 {"i286", Cpu086
|Cpu186
|Cpu286
},
402 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
403 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
404 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
405 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
406 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
407 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
408 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
409 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
410 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
411 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
415 const pseudo_typeS md_pseudo_table
[] =
417 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes
, 0},
420 {"align", s_align_ptwo
, 0},
422 {"arch", set_cpu_arch
, 0},
426 {"ffloat", float_cons
, 'f'},
427 {"dfloat", float_cons
, 'd'},
428 {"tfloat", float_cons
, 'x'},
430 {"noopt", s_ignore
, 0},
431 {"optim", s_ignore
, 0},
432 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
433 {"code16", set_code_flag
, CODE_16BIT
},
434 {"code32", set_code_flag
, CODE_32BIT
},
435 {"code64", set_code_flag
, CODE_64BIT
},
436 {"intel_syntax", set_intel_syntax
, 1},
437 {"att_syntax", set_intel_syntax
, 0},
438 {"file", dwarf2_directive_file
, 0},
439 {"loc", dwarf2_directive_loc
, 0},
443 /* For interface with expression (). */
444 extern char *input_line_pointer
;
446 /* Hash table for instruction mnemonic lookup. */
447 static struct hash_control
*op_hash
;
449 /* Hash table for register lookup. */
450 static struct hash_control
*reg_hash
;
453 i386_align_code (fragP
, count
)
457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
460 static const char f32_1
[] =
462 static const char f32_2
[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3
[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4
[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5
[] =
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6
[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7
[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8
[] =
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9
[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10
[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11
[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12
[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13
[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14
[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15
[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
499 static const char f16_3
[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
501 static const char f16_4
[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5
[] =
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6
[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7
[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8
[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt
[] = {
516 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
517 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
519 static const char *const f16_patt
[] = {
520 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
521 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code
== CODE_64BIT
)
529 if (count
> 0 && count
<= 15)
531 if (flag_code
== CODE_16BIT
)
533 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
534 f16_patt
[count
- 1], count
);
536 /* Adjust jump offset. */
537 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
540 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
541 f32_patt
[count
- 1], count
);
542 fragP
->fr_var
= count
;
546 static INLINE
unsigned int
547 mode_from_disp_size (t
)
550 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
554 fits_in_signed_byte (num
)
557 return (num
>= -128) && (num
<= 127);
561 fits_in_unsigned_byte (num
)
564 return (num
& 0xff) == num
;
568 fits_in_unsigned_word (num
)
571 return (num
& 0xffff) == num
;
575 fits_in_signed_word (num
)
578 return (-32768 <= num
) && (num
<= 32767);
581 fits_in_signed_long (num
)
582 offsetT num ATTRIBUTE_UNUSED
;
587 return (!(((offsetT
) -1 << 31) & num
)
588 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
590 } /* fits_in_signed_long() */
592 fits_in_unsigned_long (num
)
593 offsetT num ATTRIBUTE_UNUSED
;
598 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
600 } /* fits_in_unsigned_long() */
603 smallest_imm_type (num
)
606 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
614 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
616 return (fits_in_signed_byte (num
)
617 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
618 : fits_in_unsigned_byte (num
)
619 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
620 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
621 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
622 : fits_in_signed_long (num
)
623 ? (Imm32
| Imm32S
| Imm64
)
624 : fits_in_unsigned_long (num
)
630 offset_in_range (val
, size
)
638 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
639 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
640 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
642 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
647 /* If BFD64, sign extend val. */
648 if (!use_rela_relocations
)
649 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
650 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
652 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
654 char buf1
[40], buf2
[40];
656 sprint_value (buf1
, val
);
657 sprint_value (buf2
, val
& mask
);
658 as_warn (_("%s shortened to %s"), buf1
, buf2
);
663 /* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
673 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
674 && flag_code
== CODE_64BIT
)
682 case CS_PREFIX_OPCODE
:
683 case DS_PREFIX_OPCODE
:
684 case ES_PREFIX_OPCODE
:
685 case FS_PREFIX_OPCODE
:
686 case GS_PREFIX_OPCODE
:
687 case SS_PREFIX_OPCODE
:
691 case REPNE_PREFIX_OPCODE
:
692 case REPE_PREFIX_OPCODE
:
695 case LOCK_PREFIX_OPCODE
:
703 case ADDR_PREFIX_OPCODE
:
707 case DATA_PREFIX_OPCODE
:
712 if (i
.prefix
[q
] != 0)
714 as_bad (_("same type of prefix used twice"));
719 i
.prefix
[q
] = prefix
;
724 set_code_flag (value
)
728 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
729 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
730 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
732 as_bad (_("64bit mode not supported on this CPU."));
734 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
736 as_bad (_("32bit mode not supported on this CPU."));
742 set_16bit_gcc_code_flag (new_code_flag
)
745 flag_code
= new_code_flag
;
746 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
747 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
752 set_intel_syntax (syntax_flag
)
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg
= 0;
759 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
761 char *string
= input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "prefix") == 0)
766 else if (strcmp (string
, "noprefix") == 0)
769 as_bad (_("bad argument to syntax directive."));
770 *input_line_pointer
= e
;
772 demand_empty_rest_of_line ();
774 intel_syntax
= syntax_flag
;
776 if (ask_naked_reg
== 0)
779 allow_naked_reg
= (intel_syntax
780 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
782 /* Conservative default. */
787 allow_naked_reg
= (ask_naked_reg
< 0);
792 int dummy ATTRIBUTE_UNUSED
;
796 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
798 char *string
= input_line_pointer
;
799 int e
= get_symbol_end ();
802 for (i
= 0; cpu_arch
[i
].name
; i
++)
804 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
806 cpu_arch_name
= cpu_arch
[i
].name
;
807 cpu_arch_flags
= (cpu_arch
[i
].flags
808 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
812 if (!cpu_arch
[i
].name
)
813 as_bad (_("no such architecture: `%s'"), string
);
815 *input_line_pointer
= e
;
818 as_bad (_("missing cpu architecture"));
820 no_cond_jump_promotion
= 0;
821 if (*input_line_pointer
== ','
822 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
824 char *string
= ++input_line_pointer
;
825 int e
= get_symbol_end ();
827 if (strcmp (string
, "nojumps") == 0)
828 no_cond_jump_promotion
= 1;
829 else if (strcmp (string
, "jumps") == 0)
832 as_bad (_("no such architecture modifier: `%s'"), string
);
834 *input_line_pointer
= e
;
837 demand_empty_rest_of_line ();
844 if (!strcmp (default_arch
, "x86_64"))
845 return bfd_mach_x86_64
;
846 else if (!strcmp (default_arch
, "i386"))
847 return bfd_mach_i386_i386
;
849 as_fatal (_("Unknown architecture"));
856 const char *hash_err
;
858 /* Initialize op_hash hash table. */
859 op_hash
= hash_new ();
862 const template *optab
;
863 templates
*core_optab
;
865 /* Setup for loop. */
867 core_optab
= (templates
*) xmalloc (sizeof (templates
));
868 core_optab
->start
= optab
;
873 if (optab
->name
== NULL
874 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
876 /* different name --> ship out current template list;
877 add to hash table; & begin anew. */
878 core_optab
->end
= optab
;
879 hash_err
= hash_insert (op_hash
,
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
888 if (optab
->name
== NULL
)
890 core_optab
= (templates
*) xmalloc (sizeof (templates
));
891 core_optab
->start
= optab
;
896 /* Initialize reg_hash hash table. */
897 reg_hash
= hash_new ();
899 const reg_entry
*regtab
;
901 for (regtab
= i386_regtab
;
902 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
905 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
907 as_fatal (_("Internal Error: Can't hash %s: %s"),
913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
918 for (c
= 0; c
< 256; c
++)
923 mnemonic_chars
[c
] = c
;
924 register_chars
[c
] = c
;
925 operand_chars
[c
] = c
;
927 else if (ISLOWER (c
))
929 mnemonic_chars
[c
] = c
;
930 register_chars
[c
] = c
;
931 operand_chars
[c
] = c
;
933 else if (ISUPPER (c
))
935 mnemonic_chars
[c
] = TOLOWER (c
);
936 register_chars
[c
] = mnemonic_chars
[c
];
937 operand_chars
[c
] = c
;
940 if (ISALPHA (c
) || ISDIGIT (c
))
941 identifier_chars
[c
] = c
;
944 identifier_chars
[c
] = c
;
945 operand_chars
[c
] = c
;
950 identifier_chars
['@'] = '@';
952 digit_chars
['-'] = '-';
953 identifier_chars
['_'] = '_';
954 identifier_chars
['.'] = '.';
956 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
957 operand_chars
[(unsigned char) *p
] = *p
;
960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
963 record_alignment (text_section
, 2);
964 record_alignment (data_section
, 2);
965 record_alignment (bss_section
, 2);
971 i386_print_statistics (file
)
974 hash_print_statistics (file
, "i386 opcode", op_hash
);
975 hash_print_statistics (file
, "i386 register", reg_hash
);
980 /* Debugging routines for md_assemble. */
981 static void pi
PARAMS ((char *, i386_insn
*));
982 static void pte
PARAMS ((template *));
983 static void pt
PARAMS ((unsigned int));
984 static void pe
PARAMS ((expressionS
*));
985 static void ps
PARAMS ((symbolS
*));
994 fprintf (stdout
, "%s: template ", line
);
996 fprintf (stdout
, " address: base %s index %s scale %x\n",
997 x
->base_reg
? x
->base_reg
->reg_name
: "none",
998 x
->index_reg
? x
->index_reg
->reg_name
: "none",
999 x
->log2_scale_factor
);
1000 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1001 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1002 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1003 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1004 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1005 (x
->rex
& REX_MODE64
) != 0,
1006 (x
->rex
& REX_EXTX
) != 0,
1007 (x
->rex
& REX_EXTY
) != 0,
1008 (x
->rex
& REX_EXTZ
) != 0);
1009 for (i
= 0; i
< x
->operands
; i
++)
1011 fprintf (stdout
, " #%d: ", i
+ 1);
1013 fprintf (stdout
, "\n");
1015 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1016 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1017 if (x
->types
[i
] & Imm
)
1019 if (x
->types
[i
] & Disp
)
1020 pe (x
->op
[i
].disps
);
1029 fprintf (stdout
, " %d operands ", t
->operands
);
1030 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1031 if (t
->extension_opcode
!= None
)
1032 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1033 if (t
->opcode_modifier
& D
)
1034 fprintf (stdout
, "D");
1035 if (t
->opcode_modifier
& W
)
1036 fprintf (stdout
, "W");
1037 fprintf (stdout
, "\n");
1038 for (i
= 0; i
< t
->operands
; i
++)
1040 fprintf (stdout
, " #%d type ", i
+ 1);
1041 pt (t
->operand_types
[i
]);
1042 fprintf (stdout
, "\n");
1050 fprintf (stdout
, " operation %d\n", e
->X_op
);
1051 fprintf (stdout
, " add_number %ld (%lx)\n",
1052 (long) e
->X_add_number
, (long) e
->X_add_number
);
1053 if (e
->X_add_symbol
)
1055 fprintf (stdout
, " add_symbol ");
1056 ps (e
->X_add_symbol
);
1057 fprintf (stdout
, "\n");
1061 fprintf (stdout
, " op_symbol ");
1062 ps (e
->X_op_symbol
);
1063 fprintf (stdout
, "\n");
1071 fprintf (stdout
, "%s type %s%s",
1073 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s
)));
1083 static const type_names
[] =
1096 { BaseIndex
, "BaseIndex" },
1100 { Disp32S
, "d32s" },
1102 { InOutPortReg
, "InOutPortReg" },
1103 { ShiftCount
, "ShiftCount" },
1104 { Control
, "control reg" },
1105 { Test
, "test reg" },
1106 { Debug
, "debug reg" },
1107 { FloatReg
, "FReg" },
1108 { FloatAcc
, "FAcc" },
1112 { JumpAbsolute
, "Jump Absolute" },
1123 const struct type_name
*ty
;
1125 for (ty
= type_names
; ty
->mask
; ty
++)
1127 fprintf (stdout
, "%s, ", ty
->tname
);
1131 #endif /* DEBUG386 */
1134 tc_i386_force_relocation (fixp
)
1137 #ifdef BFD_ASSEMBLER
1138 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1139 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1144 return fixp
->fx_r_type
== 7;
1148 #ifdef BFD_ASSEMBLER
1149 static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1152 static bfd_reloc_code_real_type
1153 reloc (size
, pcrel
, sign
, other
)
1157 bfd_reloc_code_real_type other
;
1159 if (other
!= NO_RELOC
)
1165 as_bad (_("There are no unsigned pc-relative relocations"));
1168 case 1: return BFD_RELOC_8_PCREL
;
1169 case 2: return BFD_RELOC_16_PCREL
;
1170 case 4: return BFD_RELOC_32_PCREL
;
1172 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1179 case 4: return BFD_RELOC_X86_64_32S
;
1184 case 1: return BFD_RELOC_8
;
1185 case 2: return BFD_RELOC_16
;
1186 case 4: return BFD_RELOC_32
;
1187 case 8: return BFD_RELOC_64
;
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign
? "signed" : "unsigned", size
);
1194 return BFD_RELOC_NONE
;
1197 /* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1203 tc_i386_fix_adjustable (fixP
)
1206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
1209 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1210 || S_IS_WEAK (fixP
->fx_addsy
)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1218 /* adjust_reloc_syms doesn't know about the GOT. */
1219 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1220 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1221 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1222 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1223 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1224 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1225 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1226 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1231 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1232 #define BFD_RELOC_16 0
1233 #define BFD_RELOC_32 0
1234 #define BFD_RELOC_16_PCREL 0
1235 #define BFD_RELOC_32_PCREL 0
1236 #define BFD_RELOC_386_PLT32 0
1237 #define BFD_RELOC_386_GOT32 0
1238 #define BFD_RELOC_386_GOTOFF 0
1239 #define BFD_RELOC_X86_64_PLT32 0
1240 #define BFD_RELOC_X86_64_GOT32 0
1241 #define BFD_RELOC_X86_64_GOTPCREL 0
1244 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1247 intel_float_operand (mnemonic
)
1248 const char *mnemonic
;
1250 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1253 if (mnemonic
[0] == 'f')
1259 /* This is the guts of the machine-dependent assembler. LINE points to a
1260 machine dependent instruction. This function is supposed to emit
1261 the frags/bytes it assembles to. */
1268 char mnemonic
[MAX_MNEM_SIZE
];
1270 /* Initialize globals. */
1271 memset (&i
, '\0', sizeof (i
));
1272 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1273 i
.reloc
[j
] = NO_RELOC
;
1274 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1275 memset (im_expressions
, '\0', sizeof (im_expressions
));
1276 save_stack_p
= save_stack
;
1278 /* First parse an instruction mnemonic & call i386_operand for the operands.
1279 We assume that the scrubber has arranged it so that line[0] is the valid
1280 start of a (possibly prefixed) mnemonic. */
1282 line
= parse_insn (line
, mnemonic
);
1286 line
= parse_operands (line
, mnemonic
);
1290 /* Now we've parsed the mnemonic into a set of templates, and have the
1291 operands at hand. */
1293 /* All intel opcodes have reversed operands except for "bound" and
1294 "enter". We also don't reverse intersegment "jmp" and "call"
1295 instructions with 2 immediate operands so that the immediate segment
1296 precedes the offset, as it does when in AT&T mode. "enter" and the
1297 intersegment "jmp" and "call" instructions are the only ones that
1298 have two immediate operands. */
1299 if (intel_syntax
&& i
.operands
> 1
1300 && (strcmp (mnemonic
, "bound") != 0)
1301 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1307 if (i
.disp_operands
)
1310 /* Next, we find a template that matches the given insn,
1311 making sure the overlap of the given operands types is consistent
1312 with the template operand types. */
1314 if (!match_template ())
1317 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1320 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1321 i
.tm
.base_opcode
^= FloatR
;
1323 if (i
.tm
.opcode_modifier
& FWait
)
1324 if (!add_prefix (FWAIT_OPCODE
))
1327 /* Check string instruction segment overrides. */
1328 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1330 if (!check_string ())
1334 if (!process_suffix ())
1337 /* Make still unresolved immediate matches conform to size of immediate
1338 given in i.suffix. */
1339 if (!finalize_imm ())
1342 if (i
.types
[0] & Imm1
)
1343 i
.imm_operands
= 0; /* kludge for shift insns. */
1344 if (i
.types
[0] & ImplicitRegister
)
1346 if (i
.types
[1] & ImplicitRegister
)
1348 if (i
.types
[2] & ImplicitRegister
)
1351 if (i
.tm
.opcode_modifier
& ImmExt
)
1353 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1354 opcode suffix which is coded in the same place as an 8-bit
1355 immediate field would be. Here we fake an 8-bit immediate
1356 operand from the opcode suffix stored in tm.extension_opcode. */
1360 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1362 exp
= &im_expressions
[i
.imm_operands
++];
1363 i
.op
[i
.operands
].imms
= exp
;
1364 i
.types
[i
.operands
++] = Imm8
;
1365 exp
->X_op
= O_constant
;
1366 exp
->X_add_number
= i
.tm
.extension_opcode
;
1367 i
.tm
.extension_opcode
= None
;
1370 /* For insns with operands there are more diddles to do to the opcode. */
1373 if (!process_operands ())
1376 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1378 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1379 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1382 /* Handle conversion of 'int $3' --> special int3 insn. */
1383 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1385 i
.tm
.base_opcode
= INT3_OPCODE
;
1389 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1390 && i
.op
[0].disps
->X_op
== O_constant
)
1392 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1393 the absolute address given by the constant. Since ix86 jumps and
1394 calls are pc relative, we need to generate a reloc. */
1395 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1396 i
.op
[0].disps
->X_op
= O_symbol
;
1399 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1400 i
.rex
|= REX_MODE64
;
1402 /* For 8 bit registers we need an empty rex prefix. Also if the
1403 instruction already has a prefix, we need to convert old
1404 registers to new ones. */
1406 if (((i
.types
[0] & Reg8
) != 0
1407 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1408 || ((i
.types
[1] & Reg8
) != 0
1409 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1410 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1415 i
.rex
|= REX_OPCODE
;
1416 for (x
= 0; x
< 2; x
++)
1418 /* Look for 8 bit operand that uses old registers. */
1419 if ((i
.types
[x
] & Reg8
) != 0
1420 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1422 /* In case it is "hi" register, give up. */
1423 if (i
.op
[x
].regs
->reg_num
> 3)
1424 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1425 i
.op
[x
].regs
->reg_name
);
1427 /* Otherwise it is equivalent to the extended register.
1428 Since the encoding doesn't change this is merely
1429 cosmetic cleanup for debug output. */
1431 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1437 add_prefix (REX_OPCODE
| i
.rex
);
1439 /* We are ready to output the insn. */
1444 parse_insn (line
, mnemonic
)
1449 char *token_start
= l
;
1452 /* Non-zero if we found a prefix only acceptable with string insns. */
1453 const char *expecting_string_instruction
= NULL
;
1458 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1461 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1463 as_bad (_("no such instruction: `%s'"), token_start
);
1468 if (!is_space_char (*l
)
1469 && *l
!= END_OF_INSN
1470 && *l
!= PREFIX_SEPARATOR
1473 as_bad (_("invalid character %s in mnemonic"),
1474 output_invalid (*l
));
1477 if (token_start
== l
)
1479 if (*l
== PREFIX_SEPARATOR
)
1480 as_bad (_("expecting prefix; got nothing"));
1482 as_bad (_("expecting mnemonic; got nothing"));
1486 /* Look up instruction (or prefix) via hash table. */
1487 current_templates
= hash_find (op_hash
, mnemonic
);
1489 if (*l
!= END_OF_INSN
1490 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1491 && current_templates
1492 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1494 /* If we are in 16-bit mode, do not allow addr16 or data16.
1495 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1496 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1497 && flag_code
!= CODE_64BIT
1498 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1499 ^ (flag_code
== CODE_16BIT
)))
1501 as_bad (_("redundant %s prefix"),
1502 current_templates
->start
->name
);
1505 /* Add prefix, checking for repeated prefixes. */
1506 switch (add_prefix (current_templates
->start
->base_opcode
))
1511 expecting_string_instruction
= current_templates
->start
->name
;
1514 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1521 if (!current_templates
)
1523 /* See if we can get a match by trimming off a suffix. */
1526 case WORD_MNEM_SUFFIX
:
1527 case BYTE_MNEM_SUFFIX
:
1528 case QWORD_MNEM_SUFFIX
:
1529 i
.suffix
= mnem_p
[-1];
1531 current_templates
= hash_find (op_hash
, mnemonic
);
1533 case SHORT_MNEM_SUFFIX
:
1534 case LONG_MNEM_SUFFIX
:
1537 i
.suffix
= mnem_p
[-1];
1539 current_templates
= hash_find (op_hash
, mnemonic
);
1547 if (intel_float_operand (mnemonic
))
1548 i
.suffix
= SHORT_MNEM_SUFFIX
;
1550 i
.suffix
= LONG_MNEM_SUFFIX
;
1552 current_templates
= hash_find (op_hash
, mnemonic
);
1556 if (!current_templates
)
1558 as_bad (_("no such instruction: `%s'"), token_start
);
1563 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1565 /* Check for a branch hint. We allow ",pt" and ",pn" for
1566 predict taken and predict not taken respectively.
1567 I'm not sure that branch hints actually do anything on loop
1568 and jcxz insns (JumpByte) for current Pentium4 chips. They
1569 may work in the future and it doesn't hurt to accept them
1571 if (l
[0] == ',' && l
[1] == 'p')
1575 if (!add_prefix (DS_PREFIX_OPCODE
))
1579 else if (l
[2] == 'n')
1581 if (!add_prefix (CS_PREFIX_OPCODE
))
1587 /* Any other comma loses. */
1590 as_bad (_("invalid character %s in mnemonic"),
1591 output_invalid (*l
));
1595 /* Check if instruction is supported on specified architecture. */
1596 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1597 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1599 as_warn (_("`%s' is not supported on `%s'"),
1600 current_templates
->start
->name
, cpu_arch_name
);
1602 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1604 as_warn (_("use .code16 to ensure correct addressing mode"));
1607 /* Check for rep/repne without a string instruction. */
1608 if (expecting_string_instruction
1609 && !(current_templates
->start
->opcode_modifier
& IsString
))
1611 as_bad (_("expecting string instruction after `%s'"),
1612 expecting_string_instruction
);
1620 parse_operands (l
, mnemonic
)
1622 const char *mnemonic
;
1626 /* 1 if operand is pending after ','. */
1627 unsigned int expecting_operand
= 0;
1629 /* Non-zero if operand parens not balanced. */
1630 unsigned int paren_not_balanced
;
1632 while (*l
!= END_OF_INSN
)
1634 /* Skip optional white space before operand. */
1635 if (is_space_char (*l
))
1637 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1639 as_bad (_("invalid character %s before operand %d"),
1640 output_invalid (*l
),
1644 token_start
= l
; /* after white space */
1645 paren_not_balanced
= 0;
1646 while (paren_not_balanced
|| *l
!= ',')
1648 if (*l
== END_OF_INSN
)
1650 if (paren_not_balanced
)
1653 as_bad (_("unbalanced parenthesis in operand %d."),
1656 as_bad (_("unbalanced brackets in operand %d."),
1661 break; /* we are done */
1663 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1665 as_bad (_("invalid character %s in operand %d"),
1666 output_invalid (*l
),
1673 ++paren_not_balanced
;
1675 --paren_not_balanced
;
1680 ++paren_not_balanced
;
1682 --paren_not_balanced
;
1686 if (l
!= token_start
)
1687 { /* Yes, we've read in another operand. */
1688 unsigned int operand_ok
;
1689 this_operand
= i
.operands
++;
1690 if (i
.operands
> MAX_OPERANDS
)
1692 as_bad (_("spurious operands; (%d operands/instruction max)"),
1696 /* Now parse operand adding info to 'i' as we go along. */
1697 END_STRING_AND_SAVE (l
);
1701 i386_intel_operand (token_start
,
1702 intel_float_operand (mnemonic
));
1704 operand_ok
= i386_operand (token_start
);
1706 RESTORE_END_STRING (l
);
1712 if (expecting_operand
)
1714 expecting_operand_after_comma
:
1715 as_bad (_("expecting operand after ','; got nothing"));
1720 as_bad (_("expecting operand before ','; got nothing"));
1725 /* Now *l must be either ',' or END_OF_INSN. */
1728 if (*++l
== END_OF_INSN
)
1730 /* Just skip it, if it's \n complain. */
1731 goto expecting_operand_after_comma
;
1733 expecting_operand
= 1;
1742 union i386_op temp_op
;
1743 unsigned int temp_type
;
1744 RELOC_ENUM temp_reloc
;
1748 if (i
.operands
== 2)
1753 else if (i
.operands
== 3)
1758 temp_type
= i
.types
[xchg2
];
1759 i
.types
[xchg2
] = i
.types
[xchg1
];
1760 i
.types
[xchg1
] = temp_type
;
1761 temp_op
= i
.op
[xchg2
];
1762 i
.op
[xchg2
] = i
.op
[xchg1
];
1763 i
.op
[xchg1
] = temp_op
;
1764 temp_reloc
= i
.reloc
[xchg2
];
1765 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1766 i
.reloc
[xchg1
] = temp_reloc
;
1768 if (i
.mem_operands
== 2)
1770 const seg_entry
*temp_seg
;
1771 temp_seg
= i
.seg
[0];
1772 i
.seg
[0] = i
.seg
[1];
1773 i
.seg
[1] = temp_seg
;
1777 /* Try to ensure constant immediates are represented in the smallest
1782 char guess_suffix
= 0;
1786 guess_suffix
= i
.suffix
;
1787 else if (i
.reg_operands
)
1789 /* Figure out a suffix from the last register operand specified.
1790 We can't do this properly yet, ie. excluding InOutPortReg,
1791 but the following works for instructions with immediates.
1792 In any case, we can't set i.suffix yet. */
1793 for (op
= i
.operands
; --op
>= 0;)
1794 if (i
.types
[op
] & Reg
)
1796 if (i
.types
[op
] & Reg8
)
1797 guess_suffix
= BYTE_MNEM_SUFFIX
;
1798 else if (i
.types
[op
] & Reg16
)
1799 guess_suffix
= WORD_MNEM_SUFFIX
;
1800 else if (i
.types
[op
] & Reg32
)
1801 guess_suffix
= LONG_MNEM_SUFFIX
;
1802 else if (i
.types
[op
] & Reg64
)
1803 guess_suffix
= QWORD_MNEM_SUFFIX
;
1807 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1808 guess_suffix
= WORD_MNEM_SUFFIX
;
1810 for (op
= i
.operands
; --op
>= 0;)
1811 if (i
.types
[op
] & Imm
)
1813 switch (i
.op
[op
].imms
->X_op
)
1816 /* If a suffix is given, this operand may be shortened. */
1817 switch (guess_suffix
)
1819 case LONG_MNEM_SUFFIX
:
1820 i
.types
[op
] |= Imm32
| Imm64
;
1822 case WORD_MNEM_SUFFIX
:
1823 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1825 case BYTE_MNEM_SUFFIX
:
1826 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1830 /* If this operand is at most 16 bits, convert it
1831 to a signed 16 bit number before trying to see
1832 whether it will fit in an even smaller size.
1833 This allows a 16-bit operand such as $0xffe0 to
1834 be recognised as within Imm8S range. */
1835 if ((i
.types
[op
] & Imm16
)
1836 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1838 i
.op
[op
].imms
->X_add_number
=
1839 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1841 if ((i
.types
[op
] & Imm32
)
1842 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1845 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1846 ^ ((offsetT
) 1 << 31))
1847 - ((offsetT
) 1 << 31));
1849 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1851 /* We must avoid matching of Imm32 templates when 64bit
1852 only immediate is available. */
1853 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1854 i
.types
[op
] &= ~Imm32
;
1861 /* Symbols and expressions. */
1863 /* Convert symbolic operand to proper sizes for matching. */
1864 switch (guess_suffix
)
1866 case QWORD_MNEM_SUFFIX
:
1867 i
.types
[op
] = Imm64
| Imm32S
;
1869 case LONG_MNEM_SUFFIX
:
1870 i
.types
[op
] = Imm32
| Imm64
;
1872 case WORD_MNEM_SUFFIX
:
1873 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1876 case BYTE_MNEM_SUFFIX
:
1877 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1886 /* Try to use the smallest displacement type too. */
1892 for (op
= i
.operands
; --op
>= 0;)
1893 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1895 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1897 if (i
.types
[op
] & Disp16
)
1899 /* We know this operand is at most 16 bits, so
1900 convert to a signed 16 bit number before trying
1901 to see whether it will fit in an even smaller
1904 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1906 else if (i
.types
[op
] & Disp32
)
1908 /* We know this operand is at most 32 bits, so convert to a
1909 signed 32 bit number before trying to see whether it will
1910 fit in an even smaller size. */
1911 disp
&= (((offsetT
) 2 << 31) - 1);
1912 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1914 if (flag_code
== CODE_64BIT
)
1916 if (fits_in_signed_long (disp
))
1917 i
.types
[op
] |= Disp32S
;
1918 if (fits_in_unsigned_long (disp
))
1919 i
.types
[op
] |= Disp32
;
1921 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1922 && fits_in_signed_byte (disp
))
1923 i
.types
[op
] |= Disp8
;
1930 /* Points to template once we've found it. */
1932 unsigned int overlap0
, overlap1
, overlap2
;
1933 unsigned int found_reverse_match
;
1936 #define MATCH(overlap, given, template) \
1937 ((overlap & ~JumpAbsolute) \
1938 && (((given) & (BaseIndex | JumpAbsolute)) \
1939 == ((overlap) & (BaseIndex | JumpAbsolute))))
1941 /* If given types r0 and r1 are registers they must be of the same type
1942 unless the expected operand type register overlap is null.
1943 Note that Acc in a template matches every size of reg. */
1944 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1945 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1946 || ((g0) & Reg) == ((g1) & Reg) \
1947 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1952 found_reverse_match
= 0;
1953 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1955 : (i
.suffix
== WORD_MNEM_SUFFIX
1957 : (i
.suffix
== SHORT_MNEM_SUFFIX
1959 : (i
.suffix
== LONG_MNEM_SUFFIX
1961 : (i
.suffix
== QWORD_MNEM_SUFFIX
1963 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1964 ? No_xSuf
: 0))))));
1966 for (t
= current_templates
->start
;
1967 t
< current_templates
->end
;
1970 /* Must have right number of operands. */
1971 if (i
.operands
!= t
->operands
)
1974 /* Check the suffix, except for some instructions in intel mode. */
1975 if ((t
->opcode_modifier
& suffix_check
)
1977 && (t
->opcode_modifier
& IgnoreSize
))
1979 && t
->base_opcode
== 0xd9
1980 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1981 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1984 /* Do not verify operands when there are none. */
1985 else if (!t
->operands
)
1987 if (t
->cpu_flags
& ~cpu_arch_flags
)
1989 /* We've found a match; break out of loop. */
1993 overlap0
= i
.types
[0] & t
->operand_types
[0];
1994 switch (t
->operands
)
1997 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2002 overlap1
= i
.types
[1] & t
->operand_types
[1];
2003 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2004 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2005 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2006 t
->operand_types
[0],
2007 overlap1
, i
.types
[1],
2008 t
->operand_types
[1]))
2010 /* Check if other direction is valid ... */
2011 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2014 /* Try reversing direction of operands. */
2015 overlap0
= i
.types
[0] & t
->operand_types
[1];
2016 overlap1
= i
.types
[1] & t
->operand_types
[0];
2017 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2018 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2019 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2020 t
->operand_types
[1],
2021 overlap1
, i
.types
[1],
2022 t
->operand_types
[0]))
2024 /* Does not match either direction. */
2027 /* found_reverse_match holds which of D or FloatDR
2029 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2031 /* Found a forward 2 operand match here. */
2032 else if (t
->operands
== 3)
2034 /* Here we make use of the fact that there are no
2035 reverse match 3 operand instructions, and all 3
2036 operand instructions only need to be checked for
2037 register consistency between operands 2 and 3. */
2038 overlap2
= i
.types
[2] & t
->operand_types
[2];
2039 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2040 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2041 t
->operand_types
[1],
2042 overlap2
, i
.types
[2],
2043 t
->operand_types
[2]))
2047 /* Found either forward/reverse 2 or 3 operand match here:
2048 slip through to break. */
2050 if (t
->cpu_flags
& ~cpu_arch_flags
)
2052 found_reverse_match
= 0;
2055 /* We've found a match; break out of loop. */
2059 if (t
== current_templates
->end
)
2061 /* We found no match. */
2062 as_bad (_("suffix or operands invalid for `%s'"),
2063 current_templates
->start
->name
);
2067 if (!quiet_warnings
)
2070 && ((i
.types
[0] & JumpAbsolute
)
2071 != (t
->operand_types
[0] & JumpAbsolute
)))
2073 as_warn (_("indirect %s without `*'"), t
->name
);
2076 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2077 == (IsPrefix
| IgnoreSize
))
2079 /* Warn them that a data or address size prefix doesn't
2080 affect assembly of the next line of code. */
2081 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2085 /* Copy the template we found. */
2087 if (found_reverse_match
)
2089 /* If we found a reverse match we must alter the opcode
2090 direction bit. found_reverse_match holds bits to change
2091 (different for int & float insns). */
2093 i
.tm
.base_opcode
^= found_reverse_match
;
2095 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2096 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2105 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2106 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2108 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2110 as_bad (_("`%s' operand %d must use `%%es' segment"),
2115 /* There's only ever one segment override allowed per instruction.
2116 This instruction possibly has a legal segment override on the
2117 second operand, so copy the segment to where non-string
2118 instructions store it, allowing common code. */
2119 i
.seg
[0] = i
.seg
[1];
2121 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2123 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2125 as_bad (_("`%s' operand %d must use `%%es' segment"),
2137 /* If matched instruction specifies an explicit instruction mnemonic
2139 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2141 if (i
.tm
.opcode_modifier
& Size16
)
2142 i
.suffix
= WORD_MNEM_SUFFIX
;
2143 else if (i
.tm
.opcode_modifier
& Size64
)
2144 i
.suffix
= QWORD_MNEM_SUFFIX
;
2146 i
.suffix
= LONG_MNEM_SUFFIX
;
2148 else if (i
.reg_operands
)
2150 /* If there's no instruction mnemonic suffix we try to invent one
2151 based on register operands. */
2154 /* We take i.suffix from the last register operand specified,
2155 Destination register type is more significant than source
2158 for (op
= i
.operands
; --op
>= 0;)
2159 if ((i
.types
[op
] & Reg
)
2160 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2162 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2163 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2164 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2169 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2171 if (!check_byte_reg ())
2174 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2176 if (!check_long_reg ())
2179 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2181 if (!check_qword_reg ())
2184 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2186 if (!check_word_reg ())
2189 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2190 /* Do nothing if the instruction is going to ignore the prefix. */
2195 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2197 i
.suffix
= stackop_size
;
2200 /* Change the opcode based on the operand size given by i.suffix;
2201 We need not change things for byte insns. */
2203 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2205 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2209 /* For movzx and movsx, need to check the register type. */
2211 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2212 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2214 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2216 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2217 if (!add_prefix (prefix
))
2221 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2223 /* It's not a byte, select word/dword operation. */
2224 if (i
.tm
.opcode_modifier
& W
)
2226 if (i
.tm
.opcode_modifier
& ShortForm
)
2227 i
.tm
.base_opcode
|= 8;
2229 i
.tm
.base_opcode
|= 1;
2231 /* Now select between word & dword operations via the operand
2232 size prefix, except for instructions that will ignore this
2234 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2235 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2236 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2238 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2239 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2240 prefix
= ADDR_PREFIX_OPCODE
;
2242 if (!add_prefix (prefix
))
2246 if (i
.suffix
!= QWORD_MNEM_SUFFIX
&& (flag_code
== CODE_64BIT
)
2247 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2248 && (i
.tm
.opcode_modifier
& JumpByte
))
2250 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2254 /* Set mode64 for an operand. */
2255 if (i
.suffix
== QWORD_MNEM_SUFFIX
2256 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2258 i
.rex
|= REX_MODE64
;
2259 if (flag_code
< CODE_64BIT
)
2261 as_bad (_("64bit operations available only in 64bit modes."));
2266 /* Size floating point instruction. */
2267 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2269 if (i
.tm
.opcode_modifier
& FloatMF
)
2270 i
.tm
.base_opcode
^= 4;
2281 for (op
= i
.operands
; --op
>= 0;)
2283 /* If this is an eight bit register, it's OK. If it's the 16 or
2284 32 bit version of an eight bit register, we will just use the
2285 low portion, and that's OK too. */
2286 if (i
.types
[op
] & Reg8
)
2289 /* movzx and movsx should not generate this warning. */
2291 && (i
.tm
.base_opcode
== 0xfb7
2292 || i
.tm
.base_opcode
== 0xfb6
2293 || i
.tm
.base_opcode
== 0x63
2294 || i
.tm
.base_opcode
== 0xfbe
2295 || i
.tm
.base_opcode
== 0xfbf))
2298 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2300 /* Check that the template allows eight bit regs. This
2301 kills insns such as `orb $1,%edx', which maybe should be
2303 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2307 /* Prohibit these changes in the 64bit mode, since the
2308 lowering is more complicated. */
2309 if (flag_code
== CODE_64BIT
2310 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2312 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2313 i
.op
[op
].regs
->reg_name
,
2317 #if REGISTER_WARNINGS
2319 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2320 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2321 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2322 ? REGNAM_AL
- REGNAM_AX
2323 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2324 i
.op
[op
].regs
->reg_name
,
2329 /* Any other register is bad. */
2330 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2332 | Control
| Debug
| Test
2333 | FloatReg
| FloatAcc
))
2335 as_bad (_("`%%%s' not allowed with `%s%c'"),
2336 i
.op
[op
].regs
->reg_name
,
2350 for (op
= i
.operands
; --op
>= 0;)
2351 /* Reject eight bit registers, except where the template requires
2352 them. (eg. movzb) */
2353 if ((i
.types
[op
] & Reg8
) != 0
2354 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2356 as_bad (_("`%%%s' not allowed with `%s%c'"),
2357 i
.op
[op
].regs
->reg_name
,
2362 /* Warn if the e prefix on a general reg is missing. */
2363 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2364 && (i
.types
[op
] & Reg16
) != 0
2365 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2367 /* Prohibit these changes in the 64bit mode, since the
2368 lowering is more complicated. */
2369 if (flag_code
== CODE_64BIT
)
2371 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2372 i
.op
[op
].regs
->reg_name
,
2376 #if REGISTER_WARNINGS
2378 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2379 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2380 i
.op
[op
].regs
->reg_name
,
2384 /* Warn if the r prefix on a general reg is missing. */
2385 else if ((i
.types
[op
] & Reg64
) != 0
2386 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2388 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2389 i
.op
[op
].regs
->reg_name
,
2401 for (op
= i
.operands
; --op
>= 0; )
2402 /* Reject eight bit registers, except where the template requires
2403 them. (eg. movzb) */
2404 if ((i
.types
[op
] & Reg8
) != 0
2405 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2407 as_bad (_("`%%%s' not allowed with `%s%c'"),
2408 i
.op
[op
].regs
->reg_name
,
2413 /* Warn if the e prefix on a general reg is missing. */
2414 else if (((i
.types
[op
] & Reg16
) != 0
2415 || (i
.types
[op
] & Reg32
) != 0)
2416 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2418 /* Prohibit these changes in the 64bit mode, since the
2419 lowering is more complicated. */
2420 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2421 i
.op
[op
].regs
->reg_name
,
2432 for (op
= i
.operands
; --op
>= 0;)
2433 /* Reject eight bit registers, except where the template requires
2434 them. (eg. movzb) */
2435 if ((i
.types
[op
] & Reg8
) != 0
2436 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2438 as_bad (_("`%%%s' not allowed with `%s%c'"),
2439 i
.op
[op
].regs
->reg_name
,
2444 /* Warn if the e prefix on a general reg is present. */
2445 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2446 && (i
.types
[op
] & Reg32
) != 0
2447 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2449 /* Prohibit these changes in the 64bit mode, since the
2450 lowering is more complicated. */
2451 if (flag_code
== CODE_64BIT
)
2453 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2454 i
.op
[op
].regs
->reg_name
,
2459 #if REGISTER_WARNINGS
2460 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2461 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2462 i
.op
[op
].regs
->reg_name
,
2472 unsigned int overlap0
, overlap1
, overlap2
;
2474 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2475 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2476 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2477 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2478 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2482 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2484 : (i
.suffix
== WORD_MNEM_SUFFIX
2486 : (i
.suffix
== QWORD_MNEM_SUFFIX
2490 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2491 || overlap0
== (Imm16
| Imm32
)
2492 || overlap0
== (Imm16
| Imm32S
))
2494 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2497 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2498 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2499 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2501 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2505 i
.types
[0] = overlap0
;
2507 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2508 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2509 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2510 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2511 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2515 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2517 : (i
.suffix
== WORD_MNEM_SUFFIX
2519 : (i
.suffix
== QWORD_MNEM_SUFFIX
2523 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2524 || overlap1
== (Imm16
| Imm32
)
2525 || overlap1
== (Imm16
| Imm32S
))
2527 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2530 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2531 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2532 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2534 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2538 i
.types
[1] = overlap1
;
2540 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2541 assert ((overlap2
& Imm
) == 0);
2542 i
.types
[2] = overlap2
;
2550 /* Default segment register this instruction will use for memory
2551 accesses. 0 means unknown. This is only for optimizing out
2552 unnecessary segment overrides. */
2553 const seg_entry
*default_seg
= 0;
2555 /* The imul $imm, %reg instruction is converted into
2556 imul $imm, %reg, %reg, and the clr %reg instruction
2557 is converted into xor %reg, %reg. */
2558 if (i
.tm
.opcode_modifier
& regKludge
)
2560 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2561 /* Pretend we saw the extra register operand. */
2562 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2563 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2564 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2568 if (i
.tm
.opcode_modifier
& ShortForm
)
2570 /* The register or float register operand is in operand 0 or 1. */
2571 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2572 /* Register goes in low 3 bits of opcode. */
2573 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2574 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2576 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2578 /* Warn about some common errors, but press on regardless.
2579 The first case can be generated by gcc (<= 2.8.1). */
2580 if (i
.operands
== 2)
2582 /* Reversed arguments on faddp, fsubp, etc. */
2583 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2584 i
.op
[1].regs
->reg_name
,
2585 i
.op
[0].regs
->reg_name
);
2589 /* Extraneous `l' suffix on fp insn. */
2590 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2591 i
.op
[0].regs
->reg_name
);
2595 else if (i
.tm
.opcode_modifier
& Modrm
)
2597 /* The opcode is completed (modulo i.tm.extension_opcode which
2598 must be put into the modrm byte).
2599 Now, we make the modrm & index base bytes based on all the
2600 info we've collected. */
2602 default_seg
= build_modrm_byte ();
2604 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2606 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2607 && i
.op
[0].regs
->reg_num
== 1)
2609 as_bad (_("you can't `pop %%cs'"));
2612 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2613 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2616 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2620 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2622 /* For the string instructions that allow a segment override
2623 on one of their operands, the default segment is ds. */
2627 /* If a segment was explicitly specified,
2628 and the specified segment is not the default,
2629 use an opcode prefix to select it.
2630 If we never figured out what the default segment is,
2631 then default_seg will be zero at this point,
2632 and the specified segment prefix will always be used. */
2633 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2635 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2641 static const seg_entry
*
2644 const seg_entry
*default_seg
= 0;
2646 /* i.reg_operands MUST be the number of real register operands;
2647 implicit registers do not count. */
2648 if (i
.reg_operands
== 2)
2650 unsigned int source
, dest
;
2651 source
= ((i
.types
[0]
2652 & (Reg
| RegMMX
| RegXMM
2654 | Control
| Debug
| Test
))
2659 /* One of the register operands will be encoded in the i.tm.reg
2660 field, the other in the combined i.tm.mode and i.tm.regmem
2661 fields. If no form of this instruction supports a memory
2662 destination operand, then we assume the source operand may
2663 sometimes be a memory operand and so we need to store the
2664 destination in the i.rm.reg field. */
2665 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2667 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2668 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2669 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2671 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2676 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2677 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2678 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2680 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2685 { /* If it's not 2 reg operands... */
2688 unsigned int fake_zero_displacement
= 0;
2689 unsigned int op
= ((i
.types
[0] & AnyMem
)
2691 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2695 if (i
.base_reg
== 0)
2698 if (!i
.disp_operands
)
2699 fake_zero_displacement
= 1;
2700 if (i
.index_reg
== 0)
2702 /* Operand is just <disp> */
2703 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2704 && (flag_code
!= CODE_64BIT
))
2706 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2707 i
.types
[op
] &= ~Disp
;
2708 i
.types
[op
] |= Disp16
;
2710 else if (flag_code
!= CODE_64BIT
2711 || (i
.prefix
[ADDR_PREFIX
] != 0))
2713 i
.rm
.regmem
= NO_BASE_REGISTER
;
2714 i
.types
[op
] &= ~Disp
;
2715 i
.types
[op
] |= Disp32
;
2719 /* 64bit mode overwrites the 32bit absolute
2720 addressing by RIP relative addressing and
2721 absolute addressing is encoded by one of the
2722 redundant SIB forms. */
2723 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2724 i
.sib
.base
= NO_BASE_REGISTER
;
2725 i
.sib
.index
= NO_INDEX_REGISTER
;
2726 i
.types
[op
] &= ~Disp
;
2727 i
.types
[op
] |= Disp32S
;
2730 else /* !i.base_reg && i.index_reg */
2732 i
.sib
.index
= i
.index_reg
->reg_num
;
2733 i
.sib
.base
= NO_BASE_REGISTER
;
2734 i
.sib
.scale
= i
.log2_scale_factor
;
2735 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2736 i
.types
[op
] &= ~Disp
;
2737 if (flag_code
!= CODE_64BIT
)
2738 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2740 i
.types
[op
] |= Disp32S
;
2741 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2745 /* RIP addressing for 64bit mode. */
2746 else if (i
.base_reg
->reg_type
== BaseIndex
)
2748 i
.rm
.regmem
= NO_BASE_REGISTER
;
2749 i
.types
[op
] &= ~Disp
;
2750 i
.types
[op
] |= Disp32S
;
2751 i
.flags
[op
] = Operand_PCrel
;
2753 else if (i
.base_reg
->reg_type
& Reg16
)
2755 switch (i
.base_reg
->reg_num
)
2758 if (i
.index_reg
== 0)
2760 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2761 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2765 if (i
.index_reg
== 0)
2768 if ((i
.types
[op
] & Disp
) == 0)
2770 /* fake (%bp) into 0(%bp) */
2771 i
.types
[op
] |= Disp8
;
2772 fake_zero_displacement
= 1;
2775 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2776 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2778 default: /* (%si) -> 4 or (%di) -> 5 */
2779 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2781 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2783 else /* i.base_reg and 32/64 bit mode */
2785 if (flag_code
== CODE_64BIT
2786 && (i
.types
[op
] & Disp
))
2788 if (i
.types
[op
] & Disp8
)
2789 i
.types
[op
] = Disp8
| Disp32S
;
2791 i
.types
[op
] = Disp32S
;
2793 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2794 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2796 i
.sib
.base
= i
.base_reg
->reg_num
;
2797 /* x86-64 ignores REX prefix bit here to avoid decoder
2799 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2802 if (i
.disp_operands
== 0)
2804 fake_zero_displacement
= 1;
2805 i
.types
[op
] |= Disp8
;
2808 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2812 i
.sib
.scale
= i
.log2_scale_factor
;
2813 if (i
.index_reg
== 0)
2815 /* <disp>(%esp) becomes two byte modrm with no index
2816 register. We've already stored the code for esp
2817 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2818 Any base register besides %esp will not use the
2819 extra modrm byte. */
2820 i
.sib
.index
= NO_INDEX_REGISTER
;
2821 #if !SCALE1_WHEN_NO_INDEX
2822 /* Another case where we force the second modrm byte. */
2823 if (i
.log2_scale_factor
)
2824 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2829 i
.sib
.index
= i
.index_reg
->reg_num
;
2830 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2831 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2834 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2837 if (fake_zero_displacement
)
2839 /* Fakes a zero displacement assuming that i.types[op]
2840 holds the correct displacement size. */
2843 assert (i
.op
[op
].disps
== 0);
2844 exp
= &disp_expressions
[i
.disp_operands
++];
2845 i
.op
[op
].disps
= exp
;
2846 exp
->X_op
= O_constant
;
2847 exp
->X_add_number
= 0;
2848 exp
->X_add_symbol
= (symbolS
*) 0;
2849 exp
->X_op_symbol
= (symbolS
*) 0;
2853 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2854 (if any) based on i.tm.extension_opcode. Again, we must be
2855 careful to make sure that segment/control/debug/test/MMX
2856 registers are coded into the i.rm.reg field. */
2861 & (Reg
| RegMMX
| RegXMM
2863 | Control
| Debug
| Test
))
2866 & (Reg
| RegMMX
| RegXMM
2868 | Control
| Debug
| Test
))
2871 /* If there is an extension opcode to put here, the register
2872 number must be put into the regmem field. */
2873 if (i
.tm
.extension_opcode
!= None
)
2875 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2876 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2881 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2882 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2886 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2887 must set it to 3 to indicate this is a register operand
2888 in the regmem field. */
2889 if (!i
.mem_operands
)
2893 /* Fill in i.rm.reg field with extension opcode (if any). */
2894 if (i
.tm
.extension_opcode
!= None
)
2895 i
.rm
.reg
= i
.tm
.extension_opcode
;
2906 relax_substateT subtype
;
2911 if (flag_code
== CODE_16BIT
)
2915 if (i
.prefix
[DATA_PREFIX
] != 0)
2921 /* Pentium4 branch hints. */
2922 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2923 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2928 if (i
.prefix
[REX_PREFIX
] != 0)
2934 if (i
.prefixes
!= 0 && !intel_syntax
)
2935 as_warn (_("skipping prefixes on this instruction"));
2937 /* It's always a symbol; End frag & setup for relax.
2938 Make sure there is enough room in this frag for the largest
2939 instruction we may generate in md_convert_frag. This is 2
2940 bytes for the opcode and room for the prefix and largest
2942 frag_grow (prefix
+ 2 + 4);
2943 /* Prefix and 1 opcode byte go in fr_fix. */
2944 p
= frag_more (prefix
+ 1);
2945 if (i
.prefix
[DATA_PREFIX
] != 0)
2946 *p
++ = DATA_PREFIX_OPCODE
;
2947 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2948 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2949 *p
++ = i
.prefix
[SEG_PREFIX
];
2950 if (i
.prefix
[REX_PREFIX
] != 0)
2951 *p
++ = i
.prefix
[REX_PREFIX
];
2952 *p
= i
.tm
.base_opcode
;
2954 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2955 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2956 else if ((cpu_arch_flags
& Cpu386
) != 0)
2957 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2959 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2962 sym
= i
.op
[0].disps
->X_add_symbol
;
2963 off
= i
.op
[0].disps
->X_add_number
;
2965 if (i
.op
[0].disps
->X_op
!= O_constant
2966 && i
.op
[0].disps
->X_op
!= O_symbol
)
2968 /* Handle complex expressions. */
2969 sym
= make_expr_symbol (i
.op
[0].disps
);
2973 /* 1 possible extra opcode + 4 byte displacement go in var part.
2974 Pass reloc in fr_var. */
2975 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2984 if (i
.tm
.opcode_modifier
& JumpByte
)
2986 /* This is a loop or jecxz type instruction. */
2988 if (i
.prefix
[ADDR_PREFIX
] != 0)
2990 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2993 /* Pentium4 branch hints. */
2994 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2995 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2997 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3006 if (flag_code
== CODE_16BIT
)
3009 if (i
.prefix
[DATA_PREFIX
] != 0)
3011 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3021 if (i
.prefix
[REX_PREFIX
] != 0)
3023 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3027 if (i
.prefixes
!= 0 && !intel_syntax
)
3028 as_warn (_("skipping prefixes on this instruction"));
3030 p
= frag_more (1 + size
);
3031 *p
++ = i
.tm
.base_opcode
;
3033 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3034 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3038 output_interseg_jump ()
3046 if (flag_code
== CODE_16BIT
)
3050 if (i
.prefix
[DATA_PREFIX
] != 0)
3056 if (i
.prefix
[REX_PREFIX
] != 0)
3066 if (i
.prefixes
!= 0 && !intel_syntax
)
3067 as_warn (_("skipping prefixes on this instruction"));
3069 /* 1 opcode; 2 segment; offset */
3070 p
= frag_more (prefix
+ 1 + 2 + size
);
3072 if (i
.prefix
[DATA_PREFIX
] != 0)
3073 *p
++ = DATA_PREFIX_OPCODE
;
3075 if (i
.prefix
[REX_PREFIX
] != 0)
3076 *p
++ = i
.prefix
[REX_PREFIX
];
3078 *p
++ = i
.tm
.base_opcode
;
3079 if (i
.op
[1].imms
->X_op
== O_constant
)
3081 offsetT n
= i
.op
[1].imms
->X_add_number
;
3084 && !fits_in_unsigned_word (n
)
3085 && !fits_in_signed_word (n
))
3087 as_bad (_("16-bit jump out of range"));
3090 md_number_to_chars (p
, n
, size
);
3093 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3094 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3095 if (i
.op
[0].imms
->X_op
!= O_constant
)
3096 as_bad (_("can't handle non absolute segment in `%s'"),
3098 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3104 /* Tie dwarf2 debug info to the address at the start of the insn.
3105 We can't do this after the insn has been output as the current
3106 frag may have been closed off. eg. by frag_var. */
3107 dwarf2_emit_insn (0);
3110 if (i
.tm
.opcode_modifier
& Jump
)
3112 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3114 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3115 output_interseg_jump ();
3118 /* Output normal instructions here. */
3122 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3123 byte for the SSE instructions to specify a prefix they require. */
3124 if (i
.tm
.base_opcode
& 0xff0000)
3125 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3127 /* The prefix bytes. */
3129 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3135 md_number_to_chars (p
, (valueT
) *q
, 1);
3139 /* Now the opcode; be careful about word order here! */
3140 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3142 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3147 /* Put out high byte first: can't use md_number_to_chars! */
3148 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3149 *p
= i
.tm
.base_opcode
& 0xff;
3152 /* Now the modrm byte and sib byte (if present). */
3153 if (i
.tm
.opcode_modifier
& Modrm
)
3156 md_number_to_chars (p
,
3157 (valueT
) (i
.rm
.regmem
<< 0
3161 /* If i.rm.regmem == ESP (4)
3162 && i.rm.mode != (Register mode)
3164 ==> need second modrm byte. */
3165 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3167 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3170 md_number_to_chars (p
,
3171 (valueT
) (i
.sib
.base
<< 0
3173 | i
.sib
.scale
<< 6),
3178 if (i
.disp_operands
)
3190 #endif /* DEBUG386 */
3199 for (n
= 0; n
< i
.operands
; n
++)
3201 if (i
.types
[n
] & Disp
)
3203 if (i
.op
[n
].disps
->X_op
== O_constant
)
3209 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3212 if (i
.types
[n
] & Disp8
)
3214 if (i
.types
[n
] & Disp64
)
3217 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3219 p
= frag_more (size
);
3220 md_number_to_chars (p
, val
, size
);
3226 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3228 /* The PC relative address is computed relative
3229 to the instruction boundary, so in case immediate
3230 fields follows, we need to adjust the value. */
3231 if (pcrel
&& i
.imm_operands
)
3236 for (n1
= 0; n1
< i
.operands
; n1
++)
3237 if (i
.types
[n1
] & Imm
)
3239 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3242 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3244 if (i
.types
[n1
] & Imm64
)
3249 /* We should find the immediate. */
3250 if (n1
== i
.operands
)
3252 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3255 if (i
.types
[n
] & Disp32S
)
3258 if (i
.types
[n
] & (Disp16
| Disp64
))
3261 if (i
.types
[n
] & Disp64
)
3265 p
= frag_more (size
);
3266 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3267 i
.op
[n
].disps
, pcrel
,
3268 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3280 for (n
= 0; n
< i
.operands
; n
++)
3282 if (i
.types
[n
] & Imm
)
3284 if (i
.op
[n
].imms
->X_op
== O_constant
)
3290 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3293 if (i
.types
[n
] & (Imm8
| Imm8S
))
3295 else if (i
.types
[n
] & Imm64
)
3298 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3300 p
= frag_more (size
);
3301 md_number_to_chars (p
, val
, size
);
3305 /* Not absolute_section.
3306 Need a 32-bit fixup (don't support 8bit
3307 non-absolute imms). Try to support other
3309 RELOC_ENUM reloc_type
;
3313 if ((i
.types
[n
] & (Imm32S
))
3314 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3316 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3319 if (i
.types
[n
] & (Imm8
| Imm8S
))
3321 if (i
.types
[n
] & Imm64
)
3325 p
= frag_more (size
);
3326 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3327 #ifdef BFD_ASSEMBLER
3328 if (reloc_type
== BFD_RELOC_32
3330 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3331 && (i
.op
[n
].imms
->X_op
== O_symbol
3332 || (i
.op
[n
].imms
->X_op
== O_add
3333 && ((symbol_get_value_expression
3334 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3337 /* We don't support dynamic linking on x86-64 yet. */
3338 if (flag_code
== CODE_64BIT
)
3340 reloc_type
= BFD_RELOC_386_GOTPC
;
3341 i
.op
[n
].imms
->X_add_number
+= 3;
3344 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3345 i
.op
[n
].imms
, 0, reloc_type
);
3352 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3354 /* Parse operands of the form
3355 <symbol>@GOTOFF+<nnn>
3356 and similar .plt or .got references.
3358 If we find one, set up the correct relocation in RELOC and copy the
3359 input string, minus the `@GOTOFF' into a malloc'd buffer for
3360 parsing by the calling routine. Return this buffer, and if ADJUST
3361 is non-null set it to the length of the string we removed from the
3362 input line. Otherwise return NULL. */
3364 lex_got (reloc
, adjust
)
3368 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3369 static const struct {
3371 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3373 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3374 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3375 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3376 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3381 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3382 if (is_end_of_line
[(unsigned char) *cp
])
3385 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3389 len
= strlen (gotrel
[j
].str
);
3390 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3392 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3395 char *tmpbuf
, *past_reloc
;
3397 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3401 if (GOT_symbol
== NULL
)
3402 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3404 /* Replace the relocation token with ' ', so that
3405 errors like foo@GOTOFF1 will be detected. */
3407 /* The length of the first part of our input line. */
3408 first
= cp
- input_line_pointer
;
3410 /* The second part goes from after the reloc token until
3411 (and including) an end_of_line char. Don't use strlen
3412 here as the end_of_line char may not be a NUL. */
3413 past_reloc
= cp
+ 1 + len
;
3414 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3416 second
= cp
- past_reloc
;
3418 /* Allocate and copy string. The trailing NUL shouldn't
3419 be necessary, but be safe. */
3420 tmpbuf
= xmalloc (first
+ second
+ 2);
3421 memcpy (tmpbuf
, input_line_pointer
, first
);
3422 tmpbuf
[first
] = ' ';
3423 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3424 tmpbuf
[first
+ second
+ 1] = '\0';
3428 as_bad (_("@%s reloc is not supported in %s bit mode"),
3429 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3434 /* Might be a symbol version string. Don't as_bad here. */
3438 /* x86_cons_fix_new is called via the expression parsing code when a
3439 reloc is needed. We use this hook to get the correct .got reloc. */
3440 static RELOC_ENUM got_reloc
= NO_RELOC
;
3443 x86_cons_fix_new (frag
, off
, len
, exp
)
3449 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3450 got_reloc
= NO_RELOC
;
3451 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3455 x86_cons (exp
, size
)
3461 /* Handle @GOTOFF and the like in an expression. */
3463 char *gotfree_input_line
;
3466 save
= input_line_pointer
;
3467 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3468 if (gotfree_input_line
)
3469 input_line_pointer
= gotfree_input_line
;
3473 if (gotfree_input_line
)
3475 /* expression () has merrily parsed up to the end of line,
3476 or a comma - in the wrong buffer. Transfer how far
3477 input_line_pointer has moved to the right buffer. */
3478 input_line_pointer
= (save
3479 + (input_line_pointer
- gotfree_input_line
)
3481 free (gotfree_input_line
);
3489 static int i386_immediate
PARAMS ((char *));
3492 i386_immediate (imm_start
)
3495 char *save_input_line_pointer
;
3497 char *gotfree_input_line
;
3502 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3504 as_bad (_("only 1 or 2 immediate operands are allowed"));
3508 exp
= &im_expressions
[i
.imm_operands
++];
3509 i
.op
[this_operand
].imms
= exp
;
3511 if (is_space_char (*imm_start
))
3514 save_input_line_pointer
= input_line_pointer
;
3515 input_line_pointer
= imm_start
;
3518 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3519 if (gotfree_input_line
)
3520 input_line_pointer
= gotfree_input_line
;
3523 exp_seg
= expression (exp
);
3526 if (*input_line_pointer
)
3527 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3529 input_line_pointer
= save_input_line_pointer
;
3531 if (gotfree_input_line
)
3532 free (gotfree_input_line
);
3535 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3537 /* Missing or bad expr becomes absolute 0. */
3538 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3540 exp
->X_op
= O_constant
;
3541 exp
->X_add_number
= 0;
3542 exp
->X_add_symbol
= (symbolS
*) 0;
3543 exp
->X_op_symbol
= (symbolS
*) 0;
3545 else if (exp
->X_op
== O_constant
)
3547 /* Size it properly later. */
3548 i
.types
[this_operand
] |= Imm64
;
3549 /* If BFD64, sign extend val. */
3550 if (!use_rela_relocations
)
3551 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3552 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3554 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3556 #ifdef BFD_ASSEMBLER
3557 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3559 && exp_seg
!= text_section
3560 && exp_seg
!= data_section
3561 && exp_seg
!= bss_section
3562 && exp_seg
!= undefined_section
3563 #ifdef BFD_ASSEMBLER
3564 && !bfd_is_com_section (exp_seg
)
3568 #ifdef BFD_ASSEMBLER
3569 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3571 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3578 /* This is an address. The size of the address will be
3579 determined later, depending on destination register,
3580 suffix, or the default for the section. */
3581 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3587 static char *i386_scale
PARAMS ((char *));
3594 char *save
= input_line_pointer
;
3596 input_line_pointer
= scale
;
3597 val
= get_absolute_expression ();
3603 i
.log2_scale_factor
= 0;
3606 i
.log2_scale_factor
= 1;
3609 i
.log2_scale_factor
= 2;
3612 i
.log2_scale_factor
= 3;
3615 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3617 input_line_pointer
= save
;
3620 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3622 as_warn (_("scale factor of %d without an index register"),
3623 1 << i
.log2_scale_factor
);
3624 #if SCALE1_WHEN_NO_INDEX
3625 i
.log2_scale_factor
= 0;
3628 scale
= input_line_pointer
;
3629 input_line_pointer
= save
;
3633 static int i386_displacement
PARAMS ((char *, char *));
3636 i386_displacement (disp_start
, disp_end
)
3642 char *save_input_line_pointer
;
3644 char *gotfree_input_line
;
3646 int bigdisp
= Disp32
;
3648 if (flag_code
== CODE_64BIT
)
3650 if (i
.prefix
[ADDR_PREFIX
] == 0)
3653 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3655 i
.types
[this_operand
] |= bigdisp
;
3657 exp
= &disp_expressions
[i
.disp_operands
];
3658 i
.op
[this_operand
].disps
= exp
;
3660 save_input_line_pointer
= input_line_pointer
;
3661 input_line_pointer
= disp_start
;
3662 END_STRING_AND_SAVE (disp_end
);
3664 #ifndef GCC_ASM_O_HACK
3665 #define GCC_ASM_O_HACK 0
3668 END_STRING_AND_SAVE (disp_end
+ 1);
3669 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3670 && displacement_string_end
[-1] == '+')
3672 /* This hack is to avoid a warning when using the "o"
3673 constraint within gcc asm statements.
3676 #define _set_tssldt_desc(n,addr,limit,type) \
3677 __asm__ __volatile__ ( \
3679 "movw %w1,2+%0\n\t" \
3681 "movb %b1,4+%0\n\t" \
3682 "movb %4,5+%0\n\t" \
3683 "movb $0,6+%0\n\t" \
3684 "movb %h1,7+%0\n\t" \
3686 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3688 This works great except that the output assembler ends
3689 up looking a bit weird if it turns out that there is
3690 no offset. You end up producing code that looks like:
3703 So here we provide the missing zero. */
3705 *displacement_string_end
= '0';
3709 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3710 if (gotfree_input_line
)
3711 input_line_pointer
= gotfree_input_line
;
3714 exp_seg
= expression (exp
);
3717 if (*input_line_pointer
)
3718 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3720 RESTORE_END_STRING (disp_end
+ 1);
3722 RESTORE_END_STRING (disp_end
);
3723 input_line_pointer
= save_input_line_pointer
;
3725 if (gotfree_input_line
)
3726 free (gotfree_input_line
);
3729 #ifdef BFD_ASSEMBLER
3730 /* We do this to make sure that the section symbol is in
3731 the symbol table. We will ultimately change the relocation
3732 to be relative to the beginning of the section. */
3733 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3734 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3736 if (exp
->X_op
!= O_symbol
)
3738 as_bad (_("bad expression used with @%s"),
3739 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3745 if (S_IS_LOCAL (exp
->X_add_symbol
)
3746 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3747 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3748 exp
->X_op
= O_subtract
;
3749 exp
->X_op_symbol
= GOT_symbol
;
3750 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3751 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3753 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3757 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3759 /* Missing or bad expr becomes absolute 0. */
3760 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3762 exp
->X_op
= O_constant
;
3763 exp
->X_add_number
= 0;
3764 exp
->X_add_symbol
= (symbolS
*) 0;
3765 exp
->X_op_symbol
= (symbolS
*) 0;
3768 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3769 if (exp
->X_op
!= O_constant
3770 #ifdef BFD_ASSEMBLER
3771 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3773 && exp_seg
!= text_section
3774 && exp_seg
!= data_section
3775 && exp_seg
!= bss_section
3776 && exp_seg
!= undefined_section
)
3778 #ifdef BFD_ASSEMBLER
3779 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3781 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3786 else if (flag_code
== CODE_64BIT
)
3787 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3791 static int i386_index_check
PARAMS ((const char *));
3793 /* Make sure the memory operand we've been dealt is valid.
3794 Return 1 on success, 0 on a failure. */
3797 i386_index_check (operand_string
)
3798 const char *operand_string
;
3801 #if INFER_ADDR_PREFIX
3807 if (flag_code
== CODE_64BIT
)
3809 if (i
.prefix
[ADDR_PREFIX
] == 0)
3813 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3814 && (i
.base_reg
->reg_type
!= BaseIndex
3817 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3818 != (Reg64
| BaseIndex
))))
3825 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3827 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3828 != (Reg32
| BaseIndex
))))
3834 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3838 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3839 != (Reg16
| BaseIndex
)))
3841 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3842 != (Reg16
| BaseIndex
))
3844 && i
.base_reg
->reg_num
< 6
3845 && i
.index_reg
->reg_num
>= 6
3846 && i
.log2_scale_factor
== 0))))
3853 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3855 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3856 != (Reg32
| BaseIndex
))))
3862 #if INFER_ADDR_PREFIX
3863 if (flag_code
!= CODE_64BIT
3864 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3866 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3868 /* Change the size of any displacement too. At most one of
3869 Disp16 or Disp32 is set.
3870 FIXME. There doesn't seem to be any real need for separate
3871 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3872 Removing them would probably clean up the code quite a lot. */
3873 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3874 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3879 as_bad (_("`%s' is not a valid base/index expression"),
3883 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3885 flag_code_names
[flag_code
]);
3891 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3895 i386_operand (operand_string
)
3896 char *operand_string
;
3900 char *op_string
= operand_string
;
3902 if (is_space_char (*op_string
))
3905 /* We check for an absolute prefix (differentiating,
3906 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3907 if (*op_string
== ABSOLUTE_PREFIX
)
3910 if (is_space_char (*op_string
))
3912 i
.types
[this_operand
] |= JumpAbsolute
;
3915 /* Check if operand is a register. */
3916 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3917 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3919 /* Check for a segment override by searching for ':' after a
3920 segment register. */
3922 if (is_space_char (*op_string
))
3924 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3929 i
.seg
[i
.mem_operands
] = &es
;
3932 i
.seg
[i
.mem_operands
] = &cs
;
3935 i
.seg
[i
.mem_operands
] = &ss
;
3938 i
.seg
[i
.mem_operands
] = &ds
;
3941 i
.seg
[i
.mem_operands
] = &fs
;
3944 i
.seg
[i
.mem_operands
] = &gs
;
3948 /* Skip the ':' and whitespace. */
3950 if (is_space_char (*op_string
))
3953 if (!is_digit_char (*op_string
)
3954 && !is_identifier_char (*op_string
)
3955 && *op_string
!= '('
3956 && *op_string
!= ABSOLUTE_PREFIX
)
3958 as_bad (_("bad memory operand `%s'"), op_string
);
3961 /* Handle case of %es:*foo. */
3962 if (*op_string
== ABSOLUTE_PREFIX
)
3965 if (is_space_char (*op_string
))
3967 i
.types
[this_operand
] |= JumpAbsolute
;
3969 goto do_memory_reference
;
3973 as_bad (_("junk `%s' after register"), op_string
);
3976 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3977 i
.op
[this_operand
].regs
= r
;
3980 else if (*op_string
== REGISTER_PREFIX
)
3982 as_bad (_("bad register name `%s'"), op_string
);
3985 else if (*op_string
== IMMEDIATE_PREFIX
)
3988 if (i
.types
[this_operand
] & JumpAbsolute
)
3990 as_bad (_("immediate operand illegal with absolute jump"));
3993 if (!i386_immediate (op_string
))
3996 else if (is_digit_char (*op_string
)
3997 || is_identifier_char (*op_string
)
3998 || *op_string
== '(')
4000 /* This is a memory reference of some sort. */
4003 /* Start and end of displacement string expression (if found). */
4004 char *displacement_string_start
;
4005 char *displacement_string_end
;
4007 do_memory_reference
:
4008 if ((i
.mem_operands
== 1
4009 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4010 || i
.mem_operands
== 2)
4012 as_bad (_("too many memory references for `%s'"),
4013 current_templates
->start
->name
);
4017 /* Check for base index form. We detect the base index form by
4018 looking for an ')' at the end of the operand, searching
4019 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4021 base_string
= op_string
+ strlen (op_string
);
4024 if (is_space_char (*base_string
))
4027 /* If we only have a displacement, set-up for it to be parsed later. */
4028 displacement_string_start
= op_string
;
4029 displacement_string_end
= base_string
+ 1;
4031 if (*base_string
== ')')
4034 unsigned int parens_balanced
= 1;
4035 /* We've already checked that the number of left & right ()'s are
4036 equal, so this loop will not be infinite. */
4040 if (*base_string
== ')')
4042 if (*base_string
== '(')
4045 while (parens_balanced
);
4047 temp_string
= base_string
;
4049 /* Skip past '(' and whitespace. */
4051 if (is_space_char (*base_string
))
4054 if (*base_string
== ','
4055 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4056 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4058 displacement_string_end
= temp_string
;
4060 i
.types
[this_operand
] |= BaseIndex
;
4064 base_string
= end_op
;
4065 if (is_space_char (*base_string
))
4069 /* There may be an index reg or scale factor here. */
4070 if (*base_string
== ',')
4073 if (is_space_char (*base_string
))
4076 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4077 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4079 base_string
= end_op
;
4080 if (is_space_char (*base_string
))
4082 if (*base_string
== ',')
4085 if (is_space_char (*base_string
))
4088 else if (*base_string
!= ')')
4090 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4095 else if (*base_string
== REGISTER_PREFIX
)
4097 as_bad (_("bad register name `%s'"), base_string
);
4101 /* Check for scale factor. */
4102 if (*base_string
!= ')')
4104 char *end_scale
= i386_scale (base_string
);
4109 base_string
= end_scale
;
4110 if (is_space_char (*base_string
))
4112 if (*base_string
!= ')')
4114 as_bad (_("expecting `)' after scale factor in `%s'"),
4119 else if (!i
.index_reg
)
4121 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4126 else if (*base_string
!= ')')
4128 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4133 else if (*base_string
== REGISTER_PREFIX
)
4135 as_bad (_("bad register name `%s'"), base_string
);
4140 /* If there's an expression beginning the operand, parse it,
4141 assuming displacement_string_start and
4142 displacement_string_end are meaningful. */
4143 if (displacement_string_start
!= displacement_string_end
)
4145 if (!i386_displacement (displacement_string_start
,
4146 displacement_string_end
))
4150 /* Special case for (%dx) while doing input/output op. */
4152 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4154 && i
.log2_scale_factor
== 0
4155 && i
.seg
[i
.mem_operands
] == 0
4156 && (i
.types
[this_operand
] & Disp
) == 0)
4158 i
.types
[this_operand
] = InOutPortReg
;
4162 if (i386_index_check (operand_string
) == 0)
4168 /* It's not a memory operand; argh! */
4169 as_bad (_("invalid char %s beginning operand %d `%s'"),
4170 output_invalid (*op_string
),
4175 return 1; /* Normal return. */
4178 /* md_estimate_size_before_relax()
4180 Called just before relax() for rs_machine_dependent frags. The x86
4181 assembler uses these frags to handle variable size jump
4184 Any symbol that is now undefined will not become defined.
4185 Return the correct fr_subtype in the frag.
4186 Return the initial "guess for variable size of frag" to caller.
4187 The guess is actually the growth beyond the fixed part. Whatever
4188 we do to grow the fixed or variable part contributes to our
4192 md_estimate_size_before_relax (fragP
, segment
)
4196 /* We've already got fragP->fr_subtype right; all we have to do is
4197 check for un-relaxable symbols. On an ELF system, we can't relax
4198 an externally visible symbol, because it may be overridden by a
4200 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4202 || S_IS_EXTERNAL (fragP
->fr_symbol
)
4203 || S_IS_WEAK (fragP
->fr_symbol
)
4207 /* Symbol is undefined in this segment, or we need to keep a
4208 reloc so that weak symbols can be overridden. */
4209 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4210 RELOC_ENUM reloc_type
;
4211 unsigned char *opcode
;
4214 if (fragP
->fr_var
!= NO_RELOC
)
4215 reloc_type
= fragP
->fr_var
;
4217 reloc_type
= BFD_RELOC_16_PCREL
;
4219 reloc_type
= BFD_RELOC_32_PCREL
;
4221 old_fr_fix
= fragP
->fr_fix
;
4222 opcode
= (unsigned char *) fragP
->fr_opcode
;
4224 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4227 /* Make jmp (0xeb) a (d)word displacement jump. */
4229 fragP
->fr_fix
+= size
;
4230 fix_new (fragP
, old_fr_fix
, size
,
4232 fragP
->fr_offset
, 1,
4237 if (no_cond_jump_promotion
)
4242 /* Negate the condition, and branch past an
4243 unconditional jump. */
4246 /* Insert an unconditional jump. */
4248 /* We added two extra opcode bytes, and have a two byte
4250 fragP
->fr_fix
+= 2 + 2;
4251 fix_new (fragP
, old_fr_fix
+ 2, 2,
4253 fragP
->fr_offset
, 1,
4260 if (no_cond_jump_promotion
)
4263 /* This changes the byte-displacement jump 0x7N
4264 to the (d)word-displacement jump 0x0f,0x8N. */
4265 opcode
[1] = opcode
[0] + 0x10;
4266 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4267 /* We've added an opcode byte. */
4268 fragP
->fr_fix
+= 1 + size
;
4269 fix_new (fragP
, old_fr_fix
+ 1, size
,
4271 fragP
->fr_offset
, 1,
4276 BAD_CASE (fragP
->fr_subtype
);
4280 return fragP
->fr_fix
- old_fr_fix
;
4284 /* Guess size depending on current relax state. Initially the relax
4285 state will correspond to a short jump and we return 1, because
4286 the variable part of the frag (the branch offset) is one byte
4287 long. However, we can relax a section more than once and in that
4288 case we must either set fr_subtype back to the unrelaxed state,
4289 or return the value for the appropriate branch. */
4290 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4293 /* Called after relax() is finished.
4295 In: Address of frag.
4296 fr_type == rs_machine_dependent.
4297 fr_subtype is what the address relaxed to.
4299 Out: Any fixSs and constants are set up.
4300 Caller will turn frag into a ".space 0". */
4302 #ifndef BFD_ASSEMBLER
4304 md_convert_frag (headers
, sec
, fragP
)
4305 object_headers
*headers ATTRIBUTE_UNUSED
;
4306 segT sec ATTRIBUTE_UNUSED
;
4310 md_convert_frag (abfd
, sec
, fragP
)
4311 bfd
*abfd ATTRIBUTE_UNUSED
;
4312 segT sec ATTRIBUTE_UNUSED
;
4316 unsigned char *opcode
;
4317 unsigned char *where_to_put_displacement
= NULL
;
4318 offsetT target_address
;
4319 offsetT opcode_address
;
4320 unsigned int extension
= 0;
4321 offsetT displacement_from_opcode_start
;
4323 opcode
= (unsigned char *) fragP
->fr_opcode
;
4325 /* Address we want to reach in file space. */
4326 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4328 /* Address opcode resides at in file space. */
4329 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4331 /* Displacement from opcode start to fill into instruction. */
4332 displacement_from_opcode_start
= target_address
- opcode_address
;
4334 if ((fragP
->fr_subtype
& BIG
) == 0)
4336 /* Don't have to change opcode. */
4337 extension
= 1; /* 1 opcode + 1 displacement */
4338 where_to_put_displacement
= &opcode
[1];
4342 if (no_cond_jump_promotion
4343 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4344 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4346 switch (fragP
->fr_subtype
)
4348 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4349 extension
= 4; /* 1 opcode + 4 displacement */
4351 where_to_put_displacement
= &opcode
[1];
4354 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4355 extension
= 2; /* 1 opcode + 2 displacement */
4357 where_to_put_displacement
= &opcode
[1];
4360 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4361 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4362 extension
= 5; /* 2 opcode + 4 displacement */
4363 opcode
[1] = opcode
[0] + 0x10;
4364 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4365 where_to_put_displacement
= &opcode
[2];
4368 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4369 extension
= 3; /* 2 opcode + 2 displacement */
4370 opcode
[1] = opcode
[0] + 0x10;
4371 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4372 where_to_put_displacement
= &opcode
[2];
4375 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4380 where_to_put_displacement
= &opcode
[3];
4384 BAD_CASE (fragP
->fr_subtype
);
4389 /* Now put displacement after opcode. */
4390 md_number_to_chars ((char *) where_to_put_displacement
,
4391 (valueT
) (displacement_from_opcode_start
- extension
),
4392 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4393 fragP
->fr_fix
+= extension
;
4396 /* Size of byte displacement jmp. */
4397 int md_short_jump_size
= 2;
4399 /* Size of dword displacement jmp. */
4400 int md_long_jump_size
= 5;
4402 /* Size of relocation record. */
4403 const int md_reloc_size
= 8;
4406 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4408 addressT from_addr
, to_addr
;
4409 fragS
*frag ATTRIBUTE_UNUSED
;
4410 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4414 offset
= to_addr
- (from_addr
+ 2);
4415 /* Opcode for byte-disp jump. */
4416 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4417 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4421 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4423 addressT from_addr
, to_addr
;
4424 fragS
*frag ATTRIBUTE_UNUSED
;
4425 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4429 offset
= to_addr
- (from_addr
+ 5);
4430 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4431 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4434 /* Apply a fixup (fixS) to segment data, once it has been determined
4435 by our caller that we have all the info we need to fix it up.
4437 On the 386, immediates, displacements, and data pointers are all in
4438 the same (little-endian) format, so we don't need to care about which
4442 md_apply_fix3 (fixP
, valP
, seg
)
4443 /* The fix we're to put in. */
4445 /* Pointer to the value of the bits. */
4447 /* Segment fix is from. */
4448 segT seg ATTRIBUTE_UNUSED
;
4450 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4451 valueT value
= * valP
;
4453 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4456 switch (fixP
->fx_r_type
)
4462 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4465 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4468 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4473 /* This is a hack. There should be a better way to handle this.
4474 This covers for the fact that bfd_install_relocation will
4475 subtract the current location (for partial_inplace, PC relative
4476 relocations); see more below. */
4477 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4478 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4479 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4480 && fixP
->fx_addsy
&& !use_rela_relocations
)
4483 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4485 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4488 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4490 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4491 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4493 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4496 || (symbol_section_p (fixP
->fx_addsy
)
4497 && fseg
!= absolute_section
))
4498 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
4499 && !S_IS_WEAK (fixP
->fx_addsy
)
4500 && S_IS_DEFINED (fixP
->fx_addsy
)
4501 && !S_IS_COMMON (fixP
->fx_addsy
))
4503 /* Yes, we add the values in twice. This is because
4504 bfd_perform_relocation subtracts them out again. I think
4505 bfd_perform_relocation is broken, but I don't dare change
4507 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4511 #if defined (OBJ_COFF) && defined (TE_PE)
4512 /* For some reason, the PE format does not store a section
4513 address offset for a PC relative symbol. */
4514 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4515 value
+= md_pcrel_from (fixP
);
4519 /* Fix a few things - the dynamic linker expects certain values here,
4520 and we must not dissappoint it. */
4521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4522 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4524 switch (fixP
->fx_r_type
)
4526 case BFD_RELOC_386_PLT32
:
4527 case BFD_RELOC_X86_64_PLT32
:
4528 /* Make the jump instruction point to the address of the operand. At
4529 runtime we merely add the offset to the actual PLT entry. */
4532 case BFD_RELOC_386_GOTPC
:
4534 /* This is tough to explain. We end up with this one if we have
4535 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4536 * here is to obtain the absolute address of the GOT, and it is strongly
4537 * preferable from a performance point of view to avoid using a runtime
4538 * relocation for this. The actual sequence of instructions often look
4544 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4546 * The call and pop essentially return the absolute address of
4547 * the label .L66 and store it in %ebx. The linker itself will
4548 * ultimately change the first operand of the addl so that %ebx points to
4549 * the GOT, but to keep things simple, the .o file must have this operand
4550 * set so that it generates not the absolute address of .L66, but the
4551 * absolute address of itself. This allows the linker itself simply
4552 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4553 * added in, and the addend of the relocation is stored in the operand
4554 * field for the instruction itself.
4556 * Our job here is to fix the operand so that it would add the correct
4557 * offset so that %ebx would point to itself. The thing that is tricky is
4558 * that .-.L66 will point to the beginning of the instruction, so we need
4559 * to further modify the operand so that it will point to itself.
4560 * There are other cases where you have something like:
4562 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4564 * and here no correction would be required. Internally in the assembler
4565 * we treat operands of this form as not being pcrel since the '.' is
4566 * explicitly mentioned, and I wonder whether it would simplify matters
4567 * to do it this way. Who knows. In earlier versions of the PIC patches,
4568 * the pcrel_adjust field was used to store the correction, but since the
4569 * expression is not pcrel, I felt it would be confusing to do it this
4574 case BFD_RELOC_386_GOT32
:
4575 case BFD_RELOC_X86_64_GOT32
:
4576 value
= 0; /* Fully resolved at runtime. No addend. */
4578 case BFD_RELOC_386_GOTOFF
:
4579 case BFD_RELOC_X86_64_GOTPCREL
:
4582 case BFD_RELOC_VTABLE_INHERIT
:
4583 case BFD_RELOC_VTABLE_ENTRY
:
4590 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4592 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4594 /* Are we finished with this relocation now? */
4595 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4597 #ifdef BFD_ASSEMBLER
4598 else if (use_rela_relocations
)
4600 fixP
->fx_no_overflow
= 1;
4601 /* Remember value for tc_gen_reloc. */
4602 fixP
->fx_addnumber
= value
;
4606 md_number_to_chars (p
, value
, fixP
->fx_size
);
4609 #define MAX_LITTLENUMS 6
4611 /* Turn the string pointed to by litP into a floating point constant
4612 of type TYPE, and emit the appropriate bytes. The number of
4613 LITTLENUMS emitted is stored in *SIZEP. An error message is
4614 returned, or NULL on OK. */
4617 md_atof (type
, litP
, sizeP
)
4623 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4624 LITTLENUM_TYPE
*wordP
;
4646 return _("Bad call to md_atof ()");
4648 t
= atof_ieee (input_line_pointer
, type
, words
);
4650 input_line_pointer
= t
;
4652 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4653 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4654 the bigendian 386. */
4655 for (wordP
= words
+ prec
- 1; prec
--;)
4657 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4658 litP
+= sizeof (LITTLENUM_TYPE
);
4663 char output_invalid_buf
[8];
4670 sprintf (output_invalid_buf
, "'%c'", c
);
4672 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4673 return output_invalid_buf
;
4676 /* REG_STRING starts *before* REGISTER_PREFIX. */
4678 static const reg_entry
*
4679 parse_register (reg_string
, end_op
)
4683 char *s
= reg_string
;
4685 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4688 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4689 if (*s
== REGISTER_PREFIX
)
4692 if (is_space_char (*s
))
4696 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4698 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4699 return (const reg_entry
*) NULL
;
4703 /* For naked regs, make sure that we are not dealing with an identifier.
4704 This prevents confusing an identifier like `eax_var' with register
4706 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4707 return (const reg_entry
*) NULL
;
4711 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4713 /* Handle floating point regs, allowing spaces in the (i) part. */
4714 if (r
== i386_regtab
/* %st is first entry of table */)
4716 if (is_space_char (*s
))
4721 if (is_space_char (*s
))
4723 if (*s
>= '0' && *s
<= '7')
4725 r
= &i386_float_regtab
[*s
- '0'];
4727 if (is_space_char (*s
))
4735 /* We have "%st(" then garbage. */
4736 return (const reg_entry
*) NULL
;
4741 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4742 && flag_code
!= CODE_64BIT
)
4744 return (const reg_entry
*) NULL
;
4750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4751 const char *md_shortopts
= "kVQ:sq";
4753 const char *md_shortopts
= "q";
4756 struct option md_longopts
[] = {
4757 #define OPTION_32 (OPTION_MD_BASE + 0)
4758 {"32", no_argument
, NULL
, OPTION_32
},
4759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4760 #define OPTION_64 (OPTION_MD_BASE + 1)
4761 {"64", no_argument
, NULL
, OPTION_64
},
4763 {NULL
, no_argument
, NULL
, 0}
4765 size_t md_longopts_size
= sizeof (md_longopts
);
4768 md_parse_option (c
, arg
)
4770 char *arg ATTRIBUTE_UNUSED
;
4778 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4779 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4780 should be emitted or not. FIXME: Not implemented. */
4784 /* -V: SVR4 argument to print version ID. */
4786 print_version_id ();
4789 /* -k: Ignore for FreeBSD compatibility. */
4794 /* -s: On i386 Solaris, this tells the native assembler to use
4795 .stab instead of .stab.excl. We always use .stab anyhow. */
4800 const char **list
, **l
;
4802 list
= bfd_target_list ();
4803 for (l
= list
; *l
!= NULL
; l
++)
4804 if (strcmp (*l
, "elf64-x86-64") == 0)
4806 default_arch
= "x86_64";
4810 as_fatal (_("No compiled in support for x86_64"));
4817 default_arch
= "i386";
4827 md_show_usage (stream
)
4830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4831 fprintf (stream
, _("\
4833 -V print assembler version number\n\
4835 -q quieten some warnings\n\
4838 fprintf (stream
, _("\
4839 -q quieten some warnings\n"));
4843 #ifdef BFD_ASSEMBLER
4844 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4845 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4847 /* Pick the target format to use. */
4850 i386_target_format ()
4852 if (!strcmp (default_arch
, "x86_64"))
4853 set_code_flag (CODE_64BIT
);
4854 else if (!strcmp (default_arch
, "i386"))
4855 set_code_flag (CODE_32BIT
);
4857 as_fatal (_("Unknown architecture"));
4858 switch (OUTPUT_FLAVOR
)
4860 #ifdef OBJ_MAYBE_AOUT
4861 case bfd_target_aout_flavour
:
4862 return AOUT_TARGET_FORMAT
;
4864 #ifdef OBJ_MAYBE_COFF
4865 case bfd_target_coff_flavour
:
4868 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4869 case bfd_target_elf_flavour
:
4871 if (flag_code
== CODE_64BIT
)
4872 use_rela_relocations
= 1;
4873 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4882 #endif /* OBJ_MAYBE_ more than one */
4884 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4885 void i386_elf_emit_arch_note ()
4887 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4888 && cpu_arch_name
!= NULL
)
4891 asection
*seg
= now_seg
;
4892 subsegT subseg
= now_subseg
;
4893 Elf_Internal_Note i_note
;
4894 Elf_External_Note e_note
;
4895 asection
*note_secp
;
4898 /* Create the .note section. */
4899 note_secp
= subseg_new (".note", 0);
4900 bfd_set_section_flags (stdoutput
,
4902 SEC_HAS_CONTENTS
| SEC_READONLY
);
4904 /* Process the arch string. */
4905 len
= strlen (cpu_arch_name
);
4907 i_note
.namesz
= len
+ 1;
4909 i_note
.type
= NT_ARCH
;
4910 p
= frag_more (sizeof (e_note
.namesz
));
4911 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4912 p
= frag_more (sizeof (e_note
.descsz
));
4913 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4914 p
= frag_more (sizeof (e_note
.type
));
4915 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4916 p
= frag_more (len
+ 1);
4917 strcpy (p
, cpu_arch_name
);
4919 frag_align (2, 0, 0);
4921 subseg_set (seg
, subseg
);
4925 #endif /* BFD_ASSEMBLER */
4928 md_undefined_symbol (name
)
4931 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4932 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4933 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4934 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4938 if (symbol_find (name
))
4939 as_bad (_("GOT already in symbol table"));
4940 GOT_symbol
= symbol_new (name
, undefined_section
,
4941 (valueT
) 0, &zero_address_frag
);
4948 /* Round up a section size to the appropriate boundary. */
4951 md_section_align (segment
, size
)
4952 segT segment ATTRIBUTE_UNUSED
;
4955 #ifdef BFD_ASSEMBLER
4956 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4957 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4959 /* For a.out, force the section size to be aligned. If we don't do
4960 this, BFD will align it for us, but it will not write out the
4961 final bytes of the section. This may be a bug in BFD, but it is
4962 easier to fix it here since that is how the other a.out targets
4966 align
= bfd_get_section_alignment (stdoutput
, segment
);
4967 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4975 /* On the i386, PC-relative offsets are relative to the start of the
4976 next instruction. That is, the address of the offset, plus its
4977 size, since the offset is always the last part of the insn. */
4980 md_pcrel_from (fixP
)
4983 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4990 int ignore ATTRIBUTE_UNUSED
;
4994 temp
= get_absolute_expression ();
4995 subseg_set (bss_section
, (subsegT
) temp
);
4996 demand_empty_rest_of_line ();
5001 #ifdef BFD_ASSEMBLER
5004 i386_validate_fix (fixp
)
5007 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5009 /* GOTOFF relocation are nonsense in 64bit mode. */
5010 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5012 if (flag_code
!= CODE_64BIT
)
5014 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5018 if (flag_code
== CODE_64BIT
)
5020 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5027 tc_gen_reloc (section
, fixp
)
5028 asection
*section ATTRIBUTE_UNUSED
;
5032 bfd_reloc_code_real_type code
;
5034 switch (fixp
->fx_r_type
)
5036 case BFD_RELOC_X86_64_PLT32
:
5037 case BFD_RELOC_X86_64_GOT32
:
5038 case BFD_RELOC_X86_64_GOTPCREL
:
5039 case BFD_RELOC_386_PLT32
:
5040 case BFD_RELOC_386_GOT32
:
5041 case BFD_RELOC_386_GOTOFF
:
5042 case BFD_RELOC_386_GOTPC
:
5043 case BFD_RELOC_X86_64_32S
:
5045 case BFD_RELOC_VTABLE_ENTRY
:
5046 case BFD_RELOC_VTABLE_INHERIT
:
5047 code
= fixp
->fx_r_type
;
5052 switch (fixp
->fx_size
)
5055 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5056 _("can not do %d byte pc-relative relocation"),
5058 code
= BFD_RELOC_32_PCREL
;
5060 case 1: code
= BFD_RELOC_8_PCREL
; break;
5061 case 2: code
= BFD_RELOC_16_PCREL
; break;
5062 case 4: code
= BFD_RELOC_32_PCREL
; break;
5067 switch (fixp
->fx_size
)
5070 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5071 _("can not do %d byte relocation"),
5073 code
= BFD_RELOC_32
;
5075 case 1: code
= BFD_RELOC_8
; break;
5076 case 2: code
= BFD_RELOC_16
; break;
5077 case 4: code
= BFD_RELOC_32
; break;
5079 case 8: code
= BFD_RELOC_64
; break;
5086 if (code
== BFD_RELOC_32
5088 && fixp
->fx_addsy
== GOT_symbol
)
5090 /* We don't support GOTPC on 64bit targets. */
5091 if (flag_code
== CODE_64BIT
)
5093 code
= BFD_RELOC_386_GOTPC
;
5096 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5097 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5098 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5100 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5101 if (!use_rela_relocations
)
5103 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5104 vtable entry to be used in the relocation's section offset. */
5105 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5106 rel
->address
= fixp
->fx_offset
;
5109 rel
->addend
= fixp
->fx_addnumber
;
5113 /* Use the rela in 64bit mode. */
5116 if (!fixp
->fx_pcrel
)
5117 rel
->addend
= fixp
->fx_offset
;
5121 case BFD_RELOC_X86_64_PLT32
:
5122 case BFD_RELOC_X86_64_GOT32
:
5123 case BFD_RELOC_X86_64_GOTPCREL
:
5124 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5127 rel
->addend
= (section
->vma
5129 + fixp
->fx_addnumber
5130 + md_pcrel_from (fixp
));
5135 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5136 if (rel
->howto
== NULL
)
5138 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5139 _("cannot represent relocation type %s"),
5140 bfd_get_reloc_code_name (code
));
5141 /* Set howto to a garbage value so that we can keep going. */
5142 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5143 assert (rel
->howto
!= NULL
);
5149 #else /* !BFD_ASSEMBLER */
5151 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5153 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5156 relax_addressT segment_address_in_file
;
5158 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5159 Out: GNU LD relocation length code: 0, 1, or 2. */
5161 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5164 know (fixP
->fx_addsy
!= NULL
);
5166 md_number_to_chars (where
,
5167 (valueT
) (fixP
->fx_frag
->fr_address
5168 + fixP
->fx_where
- segment_address_in_file
),
5171 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5172 ? S_GET_TYPE (fixP
->fx_addsy
)
5173 : fixP
->fx_addsy
->sy_number
);
5175 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5176 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5177 where
[4] = r_symbolnum
& 0x0ff;
5178 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5179 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5180 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5183 #endif /* OBJ_AOUT or OBJ_BOUT. */
5185 #if defined (I386COFF)
5188 tc_coff_fix2rtype (fixP
)
5191 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5194 return (fixP
->fx_pcrel
?
5195 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5196 fixP
->fx_size
== 2 ? R_PCRWORD
:
5198 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5199 fixP
->fx_size
== 2 ? R_RELWORD
:
5204 tc_coff_sizemachdep (frag
)
5208 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5213 #endif /* I386COFF */
5215 #endif /* !BFD_ASSEMBLER */
5217 /* Parse operands using Intel syntax. This implements a recursive descent
5218 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5221 FIXME: We do not recognize the full operand grammar defined in the MASM
5222 documentation. In particular, all the structure/union and
5223 high-level macro operands are missing.
5225 Uppercase words are terminals, lower case words are non-terminals.
5226 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5227 bars '|' denote choices. Most grammar productions are implemented in
5228 functions called 'intel_<production>'.
5230 Initial production is 'expr'.
5236 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5238 constant digits [[ radixOverride ]]
5240 dataType BYTE | WORD | DWORD | QWORD | XWORD
5273 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5274 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5276 hexdigit a | b | c | d | e | f
5277 | A | B | C | D | E | F
5287 register specialRegister
5291 segmentRegister CS | DS | ES | FS | GS | SS
5293 specialRegister CR0 | CR2 | CR3
5294 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5295 | TR3 | TR4 | TR5 | TR6 | TR7
5297 We simplify the grammar in obvious places (e.g., register parsing is
5298 done by calling parse_register) and eliminate immediate left recursion
5299 to implement a recursive-descent parser.
5339 /* Parsing structure for the intel syntax parser. Used to implement the
5340 semantic actions for the operand grammar. */
5341 struct intel_parser_s
5343 char *op_string
; /* The string being parsed. */
5344 int got_a_float
; /* Whether the operand is a float. */
5345 int op_modifier
; /* Operand modifier. */
5346 int is_mem
; /* 1 if operand is memory reference. */
5347 const reg_entry
*reg
; /* Last register reference found. */
5348 char *disp
; /* Displacement string being built. */
5351 static struct intel_parser_s intel_parser
;
5353 /* Token structure for parsing intel syntax. */
5356 int code
; /* Token code. */
5357 const reg_entry
*reg
; /* Register entry for register tokens. */
5358 char *str
; /* String representation. */
5361 static struct intel_token cur_token
, prev_token
;
5363 /* Token codes for the intel parser. Since T_SHORT is already used
5364 by COFF, undefine it first to prevent a warning. */
5379 /* Prototypes for intel parser functions. */
5380 static int intel_match_token
PARAMS ((int code
));
5381 static void intel_get_token
PARAMS ((void));
5382 static void intel_putback_token
PARAMS ((void));
5383 static int intel_expr
PARAMS ((void));
5384 static int intel_e05
PARAMS ((void));
5385 static int intel_e05_1
PARAMS ((void));
5386 static int intel_e06
PARAMS ((void));
5387 static int intel_e06_1
PARAMS ((void));
5388 static int intel_e09
PARAMS ((void));
5389 static int intel_e09_1
PARAMS ((void));
5390 static int intel_e10
PARAMS ((void));
5391 static int intel_e10_1
PARAMS ((void));
5392 static int intel_e11
PARAMS ((void));
5395 i386_intel_operand (operand_string
, got_a_float
)
5396 char *operand_string
;
5402 /* Initialize token holders. */
5403 cur_token
.code
= prev_token
.code
= T_NIL
;
5404 cur_token
.reg
= prev_token
.reg
= NULL
;
5405 cur_token
.str
= prev_token
.str
= NULL
;
5407 /* Initialize parser structure. */
5408 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5411 strcpy (intel_parser
.op_string
, operand_string
);
5412 intel_parser
.got_a_float
= got_a_float
;
5413 intel_parser
.op_modifier
= -1;
5414 intel_parser
.is_mem
= 0;
5415 intel_parser
.reg
= NULL
;
5416 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5417 if (intel_parser
.disp
== NULL
)
5419 intel_parser
.disp
[0] = '\0';
5421 /* Read the first token and start the parser. */
5423 ret
= intel_expr ();
5427 /* If we found a memory reference, hand it over to i386_displacement
5428 to fill in the rest of the operand fields. */
5429 if (intel_parser
.is_mem
)
5431 if ((i
.mem_operands
== 1
5432 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5433 || i
.mem_operands
== 2)
5435 as_bad (_("too many memory references for '%s'"),
5436 current_templates
->start
->name
);
5441 char *s
= intel_parser
.disp
;
5444 /* Add the displacement expression. */
5446 ret
= i386_displacement (s
, s
+ strlen (s
))
5447 && i386_index_check (s
);
5451 /* Constant and OFFSET expressions are handled by i386_immediate. */
5452 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5453 || intel_parser
.reg
== NULL
)
5454 ret
= i386_immediate (intel_parser
.disp
);
5458 free (intel_parser
.disp
);
5468 /* expr SHORT e05 */
5469 if (cur_token
.code
== T_SHORT
)
5471 intel_parser
.op_modifier
= SHORT
;
5472 intel_match_token (T_SHORT
);
5474 return (intel_e05 ());
5479 return intel_e05 ();
5489 return (intel_e06 () && intel_e05_1 ());
5495 /* e05' addOp e06 e05' */
5496 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5498 strcat (intel_parser
.disp
, cur_token
.str
);
5499 intel_match_token (cur_token
.code
);
5501 return (intel_e06 () && intel_e05_1 ());
5516 return (intel_e09 () && intel_e06_1 ());
5522 /* e06' mulOp e09 e06' */
5523 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5525 strcat (intel_parser
.disp
, cur_token
.str
);
5526 intel_match_token (cur_token
.code
);
5528 return (intel_e09 () && intel_e06_1 ());
5536 /* e09 OFFSET e10 e09'
5545 /* e09 OFFSET e10 e09' */
5546 if (cur_token
.code
== T_OFFSET
)
5548 intel_parser
.is_mem
= 0;
5549 intel_parser
.op_modifier
= OFFSET_FLAT
;
5550 intel_match_token (T_OFFSET
);
5552 return (intel_e10 () && intel_e09_1 ());
5557 return (intel_e10 () && intel_e09_1 ());
5563 /* e09' PTR e10 e09' */
5564 if (cur_token
.code
== T_PTR
)
5566 if (prev_token
.code
== T_BYTE
)
5567 i
.suffix
= BYTE_MNEM_SUFFIX
;
5569 else if (prev_token
.code
== T_WORD
)
5571 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5572 i
.suffix
= SHORT_MNEM_SUFFIX
;
5574 i
.suffix
= WORD_MNEM_SUFFIX
;
5577 else if (prev_token
.code
== T_DWORD
)
5579 if (intel_parser
.got_a_float
== 1) /* "f..." */
5580 i
.suffix
= SHORT_MNEM_SUFFIX
;
5582 i
.suffix
= LONG_MNEM_SUFFIX
;
5585 else if (prev_token
.code
== T_QWORD
)
5587 if (intel_parser
.got_a_float
== 1) /* "f..." */
5588 i
.suffix
= LONG_MNEM_SUFFIX
;
5590 i
.suffix
= QWORD_MNEM_SUFFIX
;
5593 else if (prev_token
.code
== T_XWORD
)
5594 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5598 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5602 intel_match_token (T_PTR
);
5604 return (intel_e10 () && intel_e09_1 ());
5607 /* e09 : e10 e09' */
5608 else if (cur_token
.code
== ':')
5610 /* Mark as a memory operand only if it's not already known to be an
5611 offset expression. */
5612 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5613 intel_parser
.is_mem
= 1;
5615 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5630 return (intel_e11 () && intel_e10_1 ());
5636 /* e10' [ expr ] e10' */
5637 if (cur_token
.code
== '[')
5639 intel_match_token ('[');
5641 /* Mark as a memory operand only if it's not already known to be an
5642 offset expression. If it's an offset expression, we need to keep
5644 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5645 intel_parser
.is_mem
= 1;
5647 strcat (intel_parser
.disp
, "[");
5649 /* Add a '+' to the displacement string if necessary. */
5650 if (*intel_parser
.disp
!= '\0'
5651 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5652 strcat (intel_parser
.disp
, "+");
5654 if (intel_expr () && intel_match_token (']'))
5656 /* Preserve brackets when the operand is an offset expression. */
5657 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5658 strcat (intel_parser
.disp
, "]");
5660 return intel_e10_1 ();
5687 if (cur_token
.code
== '(')
5689 intel_match_token ('(');
5690 strcat (intel_parser
.disp
, "(");
5692 if (intel_expr () && intel_match_token (')'))
5694 strcat (intel_parser
.disp
, ")");
5702 else if (cur_token
.code
== '[')
5704 intel_match_token ('[');
5706 /* Mark as a memory operand only if it's not already known to be an
5707 offset expression. If it's an offset expression, we need to keep
5709 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5710 intel_parser
.is_mem
= 1;
5712 strcat (intel_parser
.disp
, "[");
5714 /* Operands for jump/call inside brackets denote absolute addresses. */
5715 if (current_templates
->start
->opcode_modifier
& Jump
5716 || current_templates
->start
->opcode_modifier
& JumpDword
5717 || current_templates
->start
->opcode_modifier
& JumpByte
5718 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5719 i
.types
[this_operand
] |= JumpAbsolute
;
5721 /* Add a '+' to the displacement string if necessary. */
5722 if (*intel_parser
.disp
!= '\0'
5723 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5724 strcat (intel_parser
.disp
, "+");
5726 if (intel_expr () && intel_match_token (']'))
5728 /* Preserve brackets when the operand is an offset expression. */
5729 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5730 strcat (intel_parser
.disp
, "]");
5743 else if (cur_token
.code
== T_BYTE
5744 || cur_token
.code
== T_WORD
5745 || cur_token
.code
== T_DWORD
5746 || cur_token
.code
== T_QWORD
5747 || cur_token
.code
== T_XWORD
)
5749 intel_match_token (cur_token
.code
);
5756 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5758 strcat (intel_parser
.disp
, cur_token
.str
);
5759 intel_match_token (cur_token
.code
);
5761 /* Mark as a memory operand only if it's not already known to be an
5762 offset expression. */
5763 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5764 intel_parser
.is_mem
= 1;
5770 else if (cur_token
.code
== T_REG
)
5772 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5774 intel_match_token (T_REG
);
5776 /* Check for segment change. */
5777 if (cur_token
.code
== ':')
5779 if (reg
->reg_type
& (SReg2
| SReg3
))
5781 switch (reg
->reg_num
)
5784 i
.seg
[i
.mem_operands
] = &es
;
5787 i
.seg
[i
.mem_operands
] = &cs
;
5790 i
.seg
[i
.mem_operands
] = &ss
;
5793 i
.seg
[i
.mem_operands
] = &ds
;
5796 i
.seg
[i
.mem_operands
] = &fs
;
5799 i
.seg
[i
.mem_operands
] = &gs
;
5805 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5810 /* Not a segment register. Check for register scaling. */
5811 else if (cur_token
.code
== '*')
5813 if (!intel_parser
.is_mem
)
5815 as_bad (_("Register scaling only allowed in memory operands."));
5819 /* What follows must be a valid scale. */
5820 if (intel_match_token ('*')
5821 && strchr ("01248", *cur_token
.str
))
5824 i
.types
[this_operand
] |= BaseIndex
;
5826 /* Set the scale after setting the register (otherwise,
5827 i386_scale will complain) */
5828 i386_scale (cur_token
.str
);
5829 intel_match_token (T_CONST
);
5833 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5839 /* No scaling. If this is a memory operand, the register is either a
5840 base register (first occurrence) or an index register (second
5842 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5844 if (i
.base_reg
&& i
.index_reg
)
5846 as_bad (_("Too many register references in memory operand.\n"));
5850 if (i
.base_reg
== NULL
)
5855 i
.types
[this_operand
] |= BaseIndex
;
5858 /* Offset modifier. Add the register to the displacement string to be
5859 parsed as an immediate expression after we're done. */
5860 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5861 strcat (intel_parser
.disp
, reg
->reg_name
);
5863 /* It's neither base nor index nor offset. */
5866 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5867 i
.op
[this_operand
].regs
= reg
;
5871 /* Since registers are not part of the displacement string (except
5872 when we're parsing offset operands), we may need to remove any
5873 preceding '+' from the displacement string. */
5874 if (*intel_parser
.disp
!= '\0'
5875 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5877 char *s
= intel_parser
.disp
;
5878 s
+= strlen (s
) - 1;
5887 else if (cur_token
.code
== T_ID
)
5889 /* Add the identifier to the displacement string. */
5890 strcat (intel_parser
.disp
, cur_token
.str
);
5891 intel_match_token (T_ID
);
5893 /* The identifier represents a memory reference only if it's not
5894 preceded by an offset modifier. */
5895 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5896 intel_parser
.is_mem
= 1;
5902 else if (cur_token
.code
== T_CONST
5903 || cur_token
.code
== '-'
5904 || cur_token
.code
== '+')
5908 /* Allow constants that start with `+' or `-'. */
5909 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5911 strcat (intel_parser
.disp
, cur_token
.str
);
5912 intel_match_token (cur_token
.code
);
5913 if (cur_token
.code
!= T_CONST
)
5915 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5921 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5922 if (save_str
== NULL
)
5924 strcpy (save_str
, cur_token
.str
);
5926 /* Get the next token to check for register scaling. */
5927 intel_match_token (cur_token
.code
);
5929 /* Check if this constant is a scaling factor for an index register. */
5930 if (cur_token
.code
== '*')
5932 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5934 if (!intel_parser
.is_mem
)
5936 as_bad (_("Register scaling only allowed in memory operands."));
5940 /* The constant is followed by `* reg', so it must be
5942 if (strchr ("01248", *save_str
))
5944 i
.index_reg
= cur_token
.reg
;
5945 i
.types
[this_operand
] |= BaseIndex
;
5947 /* Set the scale after setting the register (otherwise,
5948 i386_scale will complain) */
5949 i386_scale (save_str
);
5950 intel_match_token (T_REG
);
5952 /* Since registers are not part of the displacement
5953 string, we may need to remove any preceding '+' from
5954 the displacement string. */
5955 if (*intel_parser
.disp
!= '\0')
5957 char *s
= intel_parser
.disp
;
5958 s
+= strlen (s
) - 1;
5971 /* The constant was not used for register scaling. Since we have
5972 already consumed the token following `*' we now need to put it
5973 back in the stream. */
5975 intel_putback_token ();
5978 /* Add the constant to the displacement string. */
5979 strcat (intel_parser
.disp
, save_str
);
5985 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5989 /* Match the given token against cur_token. If they match, read the next
5990 token from the operand string. */
5992 intel_match_token (code
)
5995 if (cur_token
.code
== code
)
6002 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6007 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6012 const reg_entry
*reg
;
6013 struct intel_token new_token
;
6015 new_token
.code
= T_NIL
;
6016 new_token
.reg
= NULL
;
6017 new_token
.str
= NULL
;
6019 /* Free the memory allocated to the previous token and move
6020 cur_token to prev_token. */
6022 free (prev_token
.str
);
6024 prev_token
= cur_token
;
6026 /* Skip whitespace. */
6027 while (is_space_char (*intel_parser
.op_string
))
6028 intel_parser
.op_string
++;
6030 /* Return an empty token if we find nothing else on the line. */
6031 if (*intel_parser
.op_string
== '\0')
6033 cur_token
= new_token
;
6037 /* The new token cannot be larger than the remainder of the operand
6039 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6040 if (new_token
.str
== NULL
)
6042 new_token
.str
[0] = '\0';
6044 if (strchr ("0123456789", *intel_parser
.op_string
))
6046 char *p
= new_token
.str
;
6047 char *q
= intel_parser
.op_string
;
6048 new_token
.code
= T_CONST
;
6050 /* Allow any kind of identifier char to encompass floating point and
6051 hexadecimal numbers. */
6052 while (is_identifier_char (*q
))
6056 /* Recognize special symbol names [0-9][bf]. */
6057 if (strlen (intel_parser
.op_string
) == 2
6058 && (intel_parser
.op_string
[1] == 'b'
6059 || intel_parser
.op_string
[1] == 'f'))
6060 new_token
.code
= T_ID
;
6063 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6065 new_token
.code
= *intel_parser
.op_string
;
6066 new_token
.str
[0] = *intel_parser
.op_string
;
6067 new_token
.str
[1] = '\0';
6070 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6071 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6073 new_token
.code
= T_REG
;
6074 new_token
.reg
= reg
;
6076 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6078 new_token
.str
[0] = REGISTER_PREFIX
;
6079 new_token
.str
[1] = '\0';
6082 strcat (new_token
.str
, reg
->reg_name
);
6085 else if (is_identifier_char (*intel_parser
.op_string
))
6087 char *p
= new_token
.str
;
6088 char *q
= intel_parser
.op_string
;
6090 /* A '.' or '$' followed by an identifier char is an identifier.
6091 Otherwise, it's operator '.' followed by an expression. */
6092 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6094 new_token
.code
= *q
;
6095 new_token
.str
[0] = *q
;
6096 new_token
.str
[1] = '\0';
6100 while (is_identifier_char (*q
) || *q
== '@')
6104 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6105 new_token
.code
= T_BYTE
;
6107 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6108 new_token
.code
= T_WORD
;
6110 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6111 new_token
.code
= T_DWORD
;
6113 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6114 new_token
.code
= T_QWORD
;
6116 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6117 new_token
.code
= T_XWORD
;
6119 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6120 new_token
.code
= T_PTR
;
6122 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6123 new_token
.code
= T_SHORT
;
6125 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6127 new_token
.code
= T_OFFSET
;
6129 /* ??? This is not mentioned in the MASM grammar but gcc
6130 makes use of it with -mintel-syntax. OFFSET may be
6131 followed by FLAT: */
6132 if (strncasecmp (q
, " FLAT:", 6) == 0)
6133 strcat (new_token
.str
, " FLAT:");
6136 /* ??? This is not mentioned in the MASM grammar. */
6137 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6138 new_token
.code
= T_OFFSET
;
6141 new_token
.code
= T_ID
;
6146 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6148 intel_parser
.op_string
+= strlen (new_token
.str
);
6149 cur_token
= new_token
;
6152 /* Put cur_token back into the token stream and make cur_token point to
6155 intel_putback_token ()
6157 intel_parser
.op_string
-= strlen (cur_token
.str
);
6158 free (cur_token
.str
);
6159 cur_token
= prev_token
;
6161 /* Forget prev_token. */
6162 prev_token
.code
= T_NIL
;
6163 prev_token
.reg
= NULL
;
6164 prev_token
.str
= NULL
;