1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1093 CPU_RDPRU_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1095 CPU_MCOMMIT_FLAGS
, 0 },
1098 static const noarch_entry cpu_noarch
[] =
1100 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1101 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1102 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1103 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1104 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1105 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1106 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1110 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1113 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1131 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1132 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1134 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1135 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1136 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1137 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1141 /* Like s_lcomm_internal in gas/read.c but the alignment string
1142 is allowed to be optional. */
1145 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1152 && *input_line_pointer
== ',')
1154 align
= parse_align (needs_align
- 1);
1156 if (align
== (addressT
) -1)
1171 bss_alloc (symbolP
, size
, align
);
1176 pe_lcomm (int needs_align
)
1178 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1182 const pseudo_typeS md_pseudo_table
[] =
1184 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1185 {"align", s_align_bytes
, 0},
1187 {"align", s_align_ptwo
, 0},
1189 {"arch", set_cpu_arch
, 0},
1193 {"lcomm", pe_lcomm
, 1},
1195 {"ffloat", float_cons
, 'f'},
1196 {"dfloat", float_cons
, 'd'},
1197 {"tfloat", float_cons
, 'x'},
1199 {"slong", signed_cons
, 4},
1200 {"noopt", s_ignore
, 0},
1201 {"optim", s_ignore
, 0},
1202 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1203 {"code16", set_code_flag
, CODE_16BIT
},
1204 {"code32", set_code_flag
, CODE_32BIT
},
1206 {"code64", set_code_flag
, CODE_64BIT
},
1208 {"intel_syntax", set_intel_syntax
, 1},
1209 {"att_syntax", set_intel_syntax
, 0},
1210 {"intel_mnemonic", set_intel_mnemonic
, 1},
1211 {"att_mnemonic", set_intel_mnemonic
, 0},
1212 {"allow_index_reg", set_allow_index_reg
, 1},
1213 {"disallow_index_reg", set_allow_index_reg
, 0},
1214 {"sse_check", set_check
, 0},
1215 {"operand_check", set_check
, 1},
1216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1217 {"largecomm", handle_large_common
, 0},
1219 {"file", dwarf2_directive_file
, 0},
1220 {"loc", dwarf2_directive_loc
, 0},
1221 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1224 {"secrel32", pe_directive_secrel
, 0},
1229 /* For interface with expression (). */
1230 extern char *input_line_pointer
;
1232 /* Hash table for instruction mnemonic lookup. */
1233 static struct hash_control
*op_hash
;
1235 /* Hash table for register lookup. */
1236 static struct hash_control
*reg_hash
;
1238 /* Various efficient no-op patterns for aligning code labels.
1239 Note: Don't try to assemble the instructions in the comments.
1240 0L and 0w are not legal. */
1241 static const unsigned char f32_1
[] =
1243 static const unsigned char f32_2
[] =
1244 {0x66,0x90}; /* xchg %ax,%ax */
1245 static const unsigned char f32_3
[] =
1246 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1247 static const unsigned char f32_4
[] =
1248 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1249 static const unsigned char f32_6
[] =
1250 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1251 static const unsigned char f32_7
[] =
1252 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1253 static const unsigned char f16_3
[] =
1254 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1255 static const unsigned char f16_4
[] =
1256 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1257 static const unsigned char jump_disp8
[] =
1258 {0xeb}; /* jmp disp8 */
1259 static const unsigned char jump32_disp32
[] =
1260 {0xe9}; /* jmp disp32 */
1261 static const unsigned char jump16_disp32
[] =
1262 {0x66,0xe9}; /* jmp disp32 */
1263 /* 32-bit NOPs patterns. */
1264 static const unsigned char *const f32_patt
[] = {
1265 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1267 /* 16-bit NOPs patterns. */
1268 static const unsigned char *const f16_patt
[] = {
1269 f32_1
, f32_2
, f16_3
, f16_4
1271 /* nopl (%[re]ax) */
1272 static const unsigned char alt_3
[] =
1274 /* nopl 0(%[re]ax) */
1275 static const unsigned char alt_4
[] =
1276 {0x0f,0x1f,0x40,0x00};
1277 /* nopl 0(%[re]ax,%[re]ax,1) */
1278 static const unsigned char alt_5
[] =
1279 {0x0f,0x1f,0x44,0x00,0x00};
1280 /* nopw 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_6
[] =
1282 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopl 0L(%[re]ax) */
1284 static const unsigned char alt_7
[] =
1285 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1286 /* nopl 0L(%[re]ax,%[re]ax,1) */
1287 static const unsigned char alt_8
[] =
1288 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1289 /* nopw 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_9
[] =
1291 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_10
[] =
1294 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* data16 nopw %cs:0L(%eax,%eax,1) */
1296 static const unsigned char alt_11
[] =
1297 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* 32-bit and 64-bit NOPs patterns. */
1299 static const unsigned char *const alt_patt
[] = {
1300 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1301 alt_9
, alt_10
, alt_11
1304 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1305 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1308 i386_output_nops (char *where
, const unsigned char *const *patt
,
1309 int count
, int max_single_nop_size
)
1312 /* Place the longer NOP first. */
1315 const unsigned char *nops
;
1317 if (max_single_nop_size
< 1)
1319 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1320 max_single_nop_size
);
1324 nops
= patt
[max_single_nop_size
- 1];
1326 /* Use the smaller one if the requsted one isn't available. */
1329 max_single_nop_size
--;
1330 nops
= patt
[max_single_nop_size
- 1];
1333 last
= count
% max_single_nop_size
;
1336 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1337 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1341 nops
= patt
[last
- 1];
1344 /* Use the smaller one plus one-byte NOP if the needed one
1347 nops
= patt
[last
- 1];
1348 memcpy (where
+ offset
, nops
, last
);
1349 where
[offset
+ last
] = *patt
[0];
1352 memcpy (where
+ offset
, nops
, last
);
1357 fits_in_imm7 (offsetT num
)
1359 return (num
& 0x7f) == num
;
1363 fits_in_imm31 (offsetT num
)
1365 return (num
& 0x7fffffff) == num
;
1368 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1369 single NOP instruction LIMIT. */
1372 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1374 const unsigned char *const *patt
= NULL
;
1375 int max_single_nop_size
;
1376 /* Maximum number of NOPs before switching to jump over NOPs. */
1377 int max_number_of_nops
;
1379 switch (fragP
->fr_type
)
1388 /* We need to decide which NOP sequence to use for 32bit and
1389 64bit. When -mtune= is used:
1391 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1392 PROCESSOR_GENERIC32, f32_patt will be used.
1393 2. For the rest, alt_patt will be used.
1395 When -mtune= isn't used, alt_patt will be used if
1396 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1399 When -march= or .arch is used, we can't use anything beyond
1400 cpu_arch_isa_flags. */
1402 if (flag_code
== CODE_16BIT
)
1405 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1406 /* Limit number of NOPs to 2 in 16-bit mode. */
1407 max_number_of_nops
= 2;
1411 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1413 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1414 switch (cpu_arch_tune
)
1416 case PROCESSOR_UNKNOWN
:
1417 /* We use cpu_arch_isa_flags to check if we SHOULD
1418 optimize with nops. */
1419 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1424 case PROCESSOR_PENTIUM4
:
1425 case PROCESSOR_NOCONA
:
1426 case PROCESSOR_CORE
:
1427 case PROCESSOR_CORE2
:
1428 case PROCESSOR_COREI7
:
1429 case PROCESSOR_L1OM
:
1430 case PROCESSOR_K1OM
:
1431 case PROCESSOR_GENERIC64
:
1433 case PROCESSOR_ATHLON
:
1435 case PROCESSOR_AMDFAM10
:
1437 case PROCESSOR_ZNVER
:
1441 case PROCESSOR_I386
:
1442 case PROCESSOR_I486
:
1443 case PROCESSOR_PENTIUM
:
1444 case PROCESSOR_PENTIUMPRO
:
1445 case PROCESSOR_IAMCU
:
1446 case PROCESSOR_GENERIC32
:
1453 switch (fragP
->tc_frag_data
.tune
)
1455 case PROCESSOR_UNKNOWN
:
1456 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1457 PROCESSOR_UNKNOWN. */
1461 case PROCESSOR_I386
:
1462 case PROCESSOR_I486
:
1463 case PROCESSOR_PENTIUM
:
1464 case PROCESSOR_IAMCU
:
1466 case PROCESSOR_ATHLON
:
1468 case PROCESSOR_AMDFAM10
:
1470 case PROCESSOR_ZNVER
:
1472 case PROCESSOR_GENERIC32
:
1473 /* We use cpu_arch_isa_flags to check if we CAN optimize
1475 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1480 case PROCESSOR_PENTIUMPRO
:
1481 case PROCESSOR_PENTIUM4
:
1482 case PROCESSOR_NOCONA
:
1483 case PROCESSOR_CORE
:
1484 case PROCESSOR_CORE2
:
1485 case PROCESSOR_COREI7
:
1486 case PROCESSOR_L1OM
:
1487 case PROCESSOR_K1OM
:
1488 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1493 case PROCESSOR_GENERIC64
:
1499 if (patt
== f32_patt
)
1501 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1502 /* Limit number of NOPs to 2 for older processors. */
1503 max_number_of_nops
= 2;
1507 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1508 /* Limit number of NOPs to 7 for newer processors. */
1509 max_number_of_nops
= 7;
1514 limit
= max_single_nop_size
;
1516 if (fragP
->fr_type
== rs_fill_nop
)
1518 /* Output NOPs for .nop directive. */
1519 if (limit
> max_single_nop_size
)
1521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1522 _("invalid single nop size: %d "
1523 "(expect within [0, %d])"),
1524 limit
, max_single_nop_size
);
1529 fragP
->fr_var
= count
;
1531 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1533 /* Generate jump over NOPs. */
1534 offsetT disp
= count
- 2;
1535 if (fits_in_imm7 (disp
))
1537 /* Use "jmp disp8" if possible. */
1539 where
[0] = jump_disp8
[0];
1545 unsigned int size_of_jump
;
1547 if (flag_code
== CODE_16BIT
)
1549 where
[0] = jump16_disp32
[0];
1550 where
[1] = jump16_disp32
[1];
1555 where
[0] = jump32_disp32
[0];
1559 count
-= size_of_jump
+ 4;
1560 if (!fits_in_imm31 (count
))
1562 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1563 _("jump over nop padding out of range"));
1567 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1568 where
+= size_of_jump
+ 4;
1572 /* Generate multiple NOPs. */
1573 i386_output_nops (where
, patt
, count
, limit
);
1577 operand_type_all_zero (const union i386_operand_type
*x
)
1579 switch (ARRAY_SIZE(x
->array
))
1590 return !x
->array
[0];
1597 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1599 switch (ARRAY_SIZE(x
->array
))
1617 operand_type_equal (const union i386_operand_type
*x
,
1618 const union i386_operand_type
*y
)
1620 switch (ARRAY_SIZE(x
->array
))
1623 if (x
->array
[2] != y
->array
[2])
1627 if (x
->array
[1] != y
->array
[1])
1631 return x
->array
[0] == y
->array
[0];
1639 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1641 switch (ARRAY_SIZE(x
->array
))
1656 return !x
->array
[0];
1663 cpu_flags_equal (const union i386_cpu_flags
*x
,
1664 const union i386_cpu_flags
*y
)
1666 switch (ARRAY_SIZE(x
->array
))
1669 if (x
->array
[3] != y
->array
[3])
1673 if (x
->array
[2] != y
->array
[2])
1677 if (x
->array
[1] != y
->array
[1])
1681 return x
->array
[0] == y
->array
[0];
1689 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1691 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1692 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1695 static INLINE i386_cpu_flags
1696 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1698 switch (ARRAY_SIZE (x
.array
))
1701 x
.array
[3] &= y
.array
[3];
1704 x
.array
[2] &= y
.array
[2];
1707 x
.array
[1] &= y
.array
[1];
1710 x
.array
[0] &= y
.array
[0];
1718 static INLINE i386_cpu_flags
1719 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1721 switch (ARRAY_SIZE (x
.array
))
1724 x
.array
[3] |= y
.array
[3];
1727 x
.array
[2] |= y
.array
[2];
1730 x
.array
[1] |= y
.array
[1];
1733 x
.array
[0] |= y
.array
[0];
1741 static INLINE i386_cpu_flags
1742 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1744 switch (ARRAY_SIZE (x
.array
))
1747 x
.array
[3] &= ~y
.array
[3];
1750 x
.array
[2] &= ~y
.array
[2];
1753 x
.array
[1] &= ~y
.array
[1];
1756 x
.array
[0] &= ~y
.array
[0];
1764 #define CPU_FLAGS_ARCH_MATCH 0x1
1765 #define CPU_FLAGS_64BIT_MATCH 0x2
1767 #define CPU_FLAGS_PERFECT_MATCH \
1768 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1770 /* Return CPU flags match bits. */
1773 cpu_flags_match (const insn_template
*t
)
1775 i386_cpu_flags x
= t
->cpu_flags
;
1776 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1778 x
.bitfield
.cpu64
= 0;
1779 x
.bitfield
.cpuno64
= 0;
1781 if (cpu_flags_all_zero (&x
))
1783 /* This instruction is available on all archs. */
1784 match
|= CPU_FLAGS_ARCH_MATCH
;
1788 /* This instruction is available only on some archs. */
1789 i386_cpu_flags cpu
= cpu_arch_flags
;
1791 /* AVX512VL is no standalone feature - match it and then strip it. */
1792 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1794 x
.bitfield
.cpuavx512vl
= 0;
1796 cpu
= cpu_flags_and (x
, cpu
);
1797 if (!cpu_flags_all_zero (&cpu
))
1799 if (x
.bitfield
.cpuavx
)
1801 /* We need to check a few extra flags with AVX. */
1802 if (cpu
.bitfield
.cpuavx
1803 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1804 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1805 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1806 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1807 match
|= CPU_FLAGS_ARCH_MATCH
;
1809 else if (x
.bitfield
.cpuavx512f
)
1811 /* We need to check a few extra flags with AVX512F. */
1812 if (cpu
.bitfield
.cpuavx512f
1813 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1814 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1815 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1816 match
|= CPU_FLAGS_ARCH_MATCH
;
1819 match
|= CPU_FLAGS_ARCH_MATCH
;
1825 static INLINE i386_operand_type
1826 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1828 switch (ARRAY_SIZE (x
.array
))
1831 x
.array
[2] &= y
.array
[2];
1834 x
.array
[1] &= y
.array
[1];
1837 x
.array
[0] &= y
.array
[0];
1845 static INLINE i386_operand_type
1846 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1848 switch (ARRAY_SIZE (x
.array
))
1851 x
.array
[2] &= ~y
.array
[2];
1854 x
.array
[1] &= ~y
.array
[1];
1857 x
.array
[0] &= ~y
.array
[0];
1865 static INLINE i386_operand_type
1866 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1868 switch (ARRAY_SIZE (x
.array
))
1871 x
.array
[2] |= y
.array
[2];
1874 x
.array
[1] |= y
.array
[1];
1877 x
.array
[0] |= y
.array
[0];
1885 static INLINE i386_operand_type
1886 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1888 switch (ARRAY_SIZE (x
.array
))
1891 x
.array
[2] ^= y
.array
[2];
1894 x
.array
[1] ^= y
.array
[1];
1897 x
.array
[0] ^= y
.array
[0];
1905 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1906 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1907 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1908 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1909 static const i386_operand_type anydisp
1910 = OPERAND_TYPE_ANYDISP
;
1911 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1912 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1913 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1914 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1915 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1916 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1917 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1918 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1919 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1920 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1921 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1932 operand_type_check (i386_operand_type t
, enum operand_type c
)
1937 return t
.bitfield
.reg
;
1940 return (t
.bitfield
.imm8
1944 || t
.bitfield
.imm32s
1945 || t
.bitfield
.imm64
);
1948 return (t
.bitfield
.disp8
1949 || t
.bitfield
.disp16
1950 || t
.bitfield
.disp32
1951 || t
.bitfield
.disp32s
1952 || t
.bitfield
.disp64
);
1955 return (t
.bitfield
.disp8
1956 || t
.bitfield
.disp16
1957 || t
.bitfield
.disp32
1958 || t
.bitfield
.disp32s
1959 || t
.bitfield
.disp64
1960 || t
.bitfield
.baseindex
);
1969 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1970 between operand GIVEN and opeand WANTED for instruction template T. */
1973 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1976 return !((i
.types
[given
].bitfield
.byte
1977 && !t
->operand_types
[wanted
].bitfield
.byte
)
1978 || (i
.types
[given
].bitfield
.word
1979 && !t
->operand_types
[wanted
].bitfield
.word
)
1980 || (i
.types
[given
].bitfield
.dword
1981 && !t
->operand_types
[wanted
].bitfield
.dword
)
1982 || (i
.types
[given
].bitfield
.qword
1983 && !t
->operand_types
[wanted
].bitfield
.qword
)
1984 || (i
.types
[given
].bitfield
.tbyte
1985 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1988 /* Return 1 if there is no conflict in SIMD register between operand
1989 GIVEN and opeand WANTED for instruction template T. */
1992 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1995 return !((i
.types
[given
].bitfield
.xmmword
1996 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1997 || (i
.types
[given
].bitfield
.ymmword
1998 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1999 || (i
.types
[given
].bitfield
.zmmword
2000 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2003 /* Return 1 if there is no conflict in any size between operand GIVEN
2004 and opeand WANTED for instruction template T. */
2007 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2010 return (match_operand_size (t
, wanted
, given
)
2011 && !((i
.types
[given
].bitfield
.unspecified
2013 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2014 || (i
.types
[given
].bitfield
.fword
2015 && !t
->operand_types
[wanted
].bitfield
.fword
)
2016 /* For scalar opcode templates to allow register and memory
2017 operands at the same time, some special casing is needed
2018 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2019 down-conversion vpmov*. */
2020 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2021 && !t
->opcode_modifier
.broadcast
2022 && (t
->operand_types
[wanted
].bitfield
.byte
2023 || t
->operand_types
[wanted
].bitfield
.word
2024 || t
->operand_types
[wanted
].bitfield
.dword
2025 || t
->operand_types
[wanted
].bitfield
.qword
))
2026 ? (i
.types
[given
].bitfield
.xmmword
2027 || i
.types
[given
].bitfield
.ymmword
2028 || i
.types
[given
].bitfield
.zmmword
)
2029 : !match_simd_size(t
, wanted
, given
))));
2032 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2033 operands for instruction template T, and it has MATCH_REVERSE set if there
2034 is no size conflict on any operands for the template with operands reversed
2035 (and the template allows for reversing in the first place). */
2037 #define MATCH_STRAIGHT 1
2038 #define MATCH_REVERSE 2
2040 static INLINE
unsigned int
2041 operand_size_match (const insn_template
*t
)
2043 unsigned int j
, match
= MATCH_STRAIGHT
;
2045 /* Don't check jump instructions. */
2046 if (t
->opcode_modifier
.jump
2047 || t
->opcode_modifier
.jumpbyte
2048 || t
->opcode_modifier
.jumpdword
2049 || t
->opcode_modifier
.jumpintersegment
)
2052 /* Check memory and accumulator operand size. */
2053 for (j
= 0; j
< i
.operands
; j
++)
2055 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2056 && t
->operand_types
[j
].bitfield
.anysize
)
2059 if (t
->operand_types
[j
].bitfield
.reg
2060 && !match_operand_size (t
, j
, j
))
2066 if (t
->operand_types
[j
].bitfield
.regsimd
2067 && !match_simd_size (t
, j
, j
))
2073 if (t
->operand_types
[j
].bitfield
.acc
2074 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2080 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2087 if (!t
->opcode_modifier
.d
)
2091 i
.error
= operand_size_mismatch
;
2095 /* Check reverse. */
2096 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2098 for (j
= 0; j
< i
.operands
; j
++)
2100 unsigned int given
= i
.operands
- j
- 1;
2102 if (t
->operand_types
[j
].bitfield
.reg
2103 && !match_operand_size (t
, j
, given
))
2106 if (t
->operand_types
[j
].bitfield
.regsimd
2107 && !match_simd_size (t
, j
, given
))
2110 if (t
->operand_types
[j
].bitfield
.acc
2111 && (!match_operand_size (t
, j
, given
)
2112 || !match_simd_size (t
, j
, given
)))
2115 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2119 return match
| MATCH_REVERSE
;
2123 operand_type_match (i386_operand_type overlap
,
2124 i386_operand_type given
)
2126 i386_operand_type temp
= overlap
;
2128 temp
.bitfield
.jumpabsolute
= 0;
2129 temp
.bitfield
.unspecified
= 0;
2130 temp
.bitfield
.byte
= 0;
2131 temp
.bitfield
.word
= 0;
2132 temp
.bitfield
.dword
= 0;
2133 temp
.bitfield
.fword
= 0;
2134 temp
.bitfield
.qword
= 0;
2135 temp
.bitfield
.tbyte
= 0;
2136 temp
.bitfield
.xmmword
= 0;
2137 temp
.bitfield
.ymmword
= 0;
2138 temp
.bitfield
.zmmword
= 0;
2139 if (operand_type_all_zero (&temp
))
2142 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2143 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2147 i
.error
= operand_type_mismatch
;
2151 /* If given types g0 and g1 are registers they must be of the same type
2152 unless the expected operand type register overlap is null.
2153 Memory operand size of certain SIMD instructions is also being checked
2157 operand_type_register_match (i386_operand_type g0
,
2158 i386_operand_type t0
,
2159 i386_operand_type g1
,
2160 i386_operand_type t1
)
2162 if (!g0
.bitfield
.reg
2163 && !g0
.bitfield
.regsimd
2164 && (!operand_type_check (g0
, anymem
)
2165 || g0
.bitfield
.unspecified
2166 || !t0
.bitfield
.regsimd
))
2169 if (!g1
.bitfield
.reg
2170 && !g1
.bitfield
.regsimd
2171 && (!operand_type_check (g1
, anymem
)
2172 || g1
.bitfield
.unspecified
2173 || !t1
.bitfield
.regsimd
))
2176 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2177 && g0
.bitfield
.word
== g1
.bitfield
.word
2178 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2179 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2180 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2181 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2182 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2185 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2186 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2187 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2188 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2189 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2190 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2191 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2194 i
.error
= register_type_mismatch
;
2199 static INLINE
unsigned int
2200 register_number (const reg_entry
*r
)
2202 unsigned int nr
= r
->reg_num
;
2204 if (r
->reg_flags
& RegRex
)
2207 if (r
->reg_flags
& RegVRex
)
2213 static INLINE
unsigned int
2214 mode_from_disp_size (i386_operand_type t
)
2216 if (t
.bitfield
.disp8
)
2218 else if (t
.bitfield
.disp16
2219 || t
.bitfield
.disp32
2220 || t
.bitfield
.disp32s
)
2227 fits_in_signed_byte (addressT num
)
2229 return num
+ 0x80 <= 0xff;
2233 fits_in_unsigned_byte (addressT num
)
2239 fits_in_unsigned_word (addressT num
)
2241 return num
<= 0xffff;
2245 fits_in_signed_word (addressT num
)
2247 return num
+ 0x8000 <= 0xffff;
2251 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2256 return num
+ 0x80000000 <= 0xffffffff;
2258 } /* fits_in_signed_long() */
2261 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2266 return num
<= 0xffffffff;
2268 } /* fits_in_unsigned_long() */
2271 fits_in_disp8 (offsetT num
)
2273 int shift
= i
.memshift
;
2279 mask
= (1 << shift
) - 1;
2281 /* Return 0 if NUM isn't properly aligned. */
2285 /* Check if NUM will fit in 8bit after shift. */
2286 return fits_in_signed_byte (num
>> shift
);
2290 fits_in_imm4 (offsetT num
)
2292 return (num
& 0xf) == num
;
2295 static i386_operand_type
2296 smallest_imm_type (offsetT num
)
2298 i386_operand_type t
;
2300 operand_type_set (&t
, 0);
2301 t
.bitfield
.imm64
= 1;
2303 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2305 /* This code is disabled on the 486 because all the Imm1 forms
2306 in the opcode table are slower on the i486. They're the
2307 versions with the implicitly specified single-position
2308 displacement, which has another syntax if you really want to
2310 t
.bitfield
.imm1
= 1;
2311 t
.bitfield
.imm8
= 1;
2312 t
.bitfield
.imm8s
= 1;
2313 t
.bitfield
.imm16
= 1;
2314 t
.bitfield
.imm32
= 1;
2315 t
.bitfield
.imm32s
= 1;
2317 else if (fits_in_signed_byte (num
))
2319 t
.bitfield
.imm8
= 1;
2320 t
.bitfield
.imm8s
= 1;
2321 t
.bitfield
.imm16
= 1;
2322 t
.bitfield
.imm32
= 1;
2323 t
.bitfield
.imm32s
= 1;
2325 else if (fits_in_unsigned_byte (num
))
2327 t
.bitfield
.imm8
= 1;
2328 t
.bitfield
.imm16
= 1;
2329 t
.bitfield
.imm32
= 1;
2330 t
.bitfield
.imm32s
= 1;
2332 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2334 t
.bitfield
.imm16
= 1;
2335 t
.bitfield
.imm32
= 1;
2336 t
.bitfield
.imm32s
= 1;
2338 else if (fits_in_signed_long (num
))
2340 t
.bitfield
.imm32
= 1;
2341 t
.bitfield
.imm32s
= 1;
2343 else if (fits_in_unsigned_long (num
))
2344 t
.bitfield
.imm32
= 1;
2350 offset_in_range (offsetT val
, int size
)
2356 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2357 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2358 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2360 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2366 /* If BFD64, sign extend val for 32bit address mode. */
2367 if (flag_code
!= CODE_64BIT
2368 || i
.prefix
[ADDR_PREFIX
])
2369 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2370 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2373 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2375 char buf1
[40], buf2
[40];
2377 sprint_value (buf1
, val
);
2378 sprint_value (buf2
, val
& mask
);
2379 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2394 a. PREFIX_EXIST if attempting to add a prefix where one from the
2395 same class already exists.
2396 b. PREFIX_LOCK if lock prefix is added.
2397 c. PREFIX_REP if rep/repne prefix is added.
2398 d. PREFIX_DS if ds prefix is added.
2399 e. PREFIX_OTHER if other prefix is added.
2402 static enum PREFIX_GROUP
2403 add_prefix (unsigned int prefix
)
2405 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2408 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2409 && flag_code
== CODE_64BIT
)
2411 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2412 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2413 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2414 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2425 case DS_PREFIX_OPCODE
:
2428 case CS_PREFIX_OPCODE
:
2429 case ES_PREFIX_OPCODE
:
2430 case FS_PREFIX_OPCODE
:
2431 case GS_PREFIX_OPCODE
:
2432 case SS_PREFIX_OPCODE
:
2436 case REPNE_PREFIX_OPCODE
:
2437 case REPE_PREFIX_OPCODE
:
2442 case LOCK_PREFIX_OPCODE
:
2451 case ADDR_PREFIX_OPCODE
:
2455 case DATA_PREFIX_OPCODE
:
2459 if (i
.prefix
[q
] != 0)
2467 i
.prefix
[q
] |= prefix
;
2470 as_bad (_("same type of prefix used twice"));
2476 update_code_flag (int value
, int check
)
2478 PRINTF_LIKE ((*as_error
));
2480 flag_code
= (enum flag_code
) value
;
2481 if (flag_code
== CODE_64BIT
)
2483 cpu_arch_flags
.bitfield
.cpu64
= 1;
2484 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2488 cpu_arch_flags
.bitfield
.cpu64
= 0;
2489 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2491 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2494 as_error
= as_fatal
;
2497 (*as_error
) (_("64bit mode not supported on `%s'."),
2498 cpu_arch_name
? cpu_arch_name
: default_arch
);
2500 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2503 as_error
= as_fatal
;
2506 (*as_error
) (_("32bit mode not supported on `%s'."),
2507 cpu_arch_name
? cpu_arch_name
: default_arch
);
2509 stackop_size
= '\0';
2513 set_code_flag (int value
)
2515 update_code_flag (value
, 0);
2519 set_16bit_gcc_code_flag (int new_code_flag
)
2521 flag_code
= (enum flag_code
) new_code_flag
;
2522 if (flag_code
!= CODE_16BIT
)
2524 cpu_arch_flags
.bitfield
.cpu64
= 0;
2525 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2526 stackop_size
= LONG_MNEM_SUFFIX
;
2530 set_intel_syntax (int syntax_flag
)
2532 /* Find out if register prefixing is specified. */
2533 int ask_naked_reg
= 0;
2536 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2539 int e
= get_symbol_name (&string
);
2541 if (strcmp (string
, "prefix") == 0)
2543 else if (strcmp (string
, "noprefix") == 0)
2546 as_bad (_("bad argument to syntax directive."));
2547 (void) restore_line_pointer (e
);
2549 demand_empty_rest_of_line ();
2551 intel_syntax
= syntax_flag
;
2553 if (ask_naked_reg
== 0)
2554 allow_naked_reg
= (intel_syntax
2555 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2557 allow_naked_reg
= (ask_naked_reg
< 0);
2559 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2561 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2562 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2563 register_prefix
= allow_naked_reg
? "" : "%";
2567 set_intel_mnemonic (int mnemonic_flag
)
2569 intel_mnemonic
= mnemonic_flag
;
2573 set_allow_index_reg (int flag
)
2575 allow_index_reg
= flag
;
2579 set_check (int what
)
2581 enum check_kind
*kind
;
2586 kind
= &operand_check
;
2597 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2600 int e
= get_symbol_name (&string
);
2602 if (strcmp (string
, "none") == 0)
2604 else if (strcmp (string
, "warning") == 0)
2605 *kind
= check_warning
;
2606 else if (strcmp (string
, "error") == 0)
2607 *kind
= check_error
;
2609 as_bad (_("bad argument to %s_check directive."), str
);
2610 (void) restore_line_pointer (e
);
2613 as_bad (_("missing argument for %s_check directive"), str
);
2615 demand_empty_rest_of_line ();
2619 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2620 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2623 static const char *arch
;
2625 /* Intel LIOM is only supported on ELF. */
2631 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2632 use default_arch. */
2633 arch
= cpu_arch_name
;
2635 arch
= default_arch
;
2638 /* If we are targeting Intel MCU, we must enable it. */
2639 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2640 || new_flag
.bitfield
.cpuiamcu
)
2643 /* If we are targeting Intel L1OM, we must enable it. */
2644 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2645 || new_flag
.bitfield
.cpul1om
)
2648 /* If we are targeting Intel K1OM, we must enable it. */
2649 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2650 || new_flag
.bitfield
.cpuk1om
)
2653 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2658 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2662 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2665 int e
= get_symbol_name (&string
);
2667 i386_cpu_flags flags
;
2669 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2671 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2673 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2677 cpu_arch_name
= cpu_arch
[j
].name
;
2678 cpu_sub_arch_name
= NULL
;
2679 cpu_arch_flags
= cpu_arch
[j
].flags
;
2680 if (flag_code
== CODE_64BIT
)
2682 cpu_arch_flags
.bitfield
.cpu64
= 1;
2683 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2687 cpu_arch_flags
.bitfield
.cpu64
= 0;
2688 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2690 cpu_arch_isa
= cpu_arch
[j
].type
;
2691 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2692 if (!cpu_arch_tune_set
)
2694 cpu_arch_tune
= cpu_arch_isa
;
2695 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2700 flags
= cpu_flags_or (cpu_arch_flags
,
2703 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2705 if (cpu_sub_arch_name
)
2707 char *name
= cpu_sub_arch_name
;
2708 cpu_sub_arch_name
= concat (name
,
2710 (const char *) NULL
);
2714 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2715 cpu_arch_flags
= flags
;
2716 cpu_arch_isa_flags
= flags
;
2720 = cpu_flags_or (cpu_arch_isa_flags
,
2722 (void) restore_line_pointer (e
);
2723 demand_empty_rest_of_line ();
2728 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2730 /* Disable an ISA extension. */
2731 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2732 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2734 flags
= cpu_flags_and_not (cpu_arch_flags
,
2735 cpu_noarch
[j
].flags
);
2736 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2738 if (cpu_sub_arch_name
)
2740 char *name
= cpu_sub_arch_name
;
2741 cpu_sub_arch_name
= concat (name
, string
,
2742 (const char *) NULL
);
2746 cpu_sub_arch_name
= xstrdup (string
);
2747 cpu_arch_flags
= flags
;
2748 cpu_arch_isa_flags
= flags
;
2750 (void) restore_line_pointer (e
);
2751 demand_empty_rest_of_line ();
2755 j
= ARRAY_SIZE (cpu_arch
);
2758 if (j
>= ARRAY_SIZE (cpu_arch
))
2759 as_bad (_("no such architecture: `%s'"), string
);
2761 *input_line_pointer
= e
;
2764 as_bad (_("missing cpu architecture"));
2766 no_cond_jump_promotion
= 0;
2767 if (*input_line_pointer
== ','
2768 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2773 ++input_line_pointer
;
2774 e
= get_symbol_name (&string
);
2776 if (strcmp (string
, "nojumps") == 0)
2777 no_cond_jump_promotion
= 1;
2778 else if (strcmp (string
, "jumps") == 0)
2781 as_bad (_("no such architecture modifier: `%s'"), string
);
2783 (void) restore_line_pointer (e
);
2786 demand_empty_rest_of_line ();
2789 enum bfd_architecture
2792 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2794 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2795 || flag_code
!= CODE_64BIT
)
2796 as_fatal (_("Intel L1OM is 64bit ELF only"));
2797 return bfd_arch_l1om
;
2799 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2801 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2802 || flag_code
!= CODE_64BIT
)
2803 as_fatal (_("Intel K1OM is 64bit ELF only"));
2804 return bfd_arch_k1om
;
2806 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2808 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2809 || flag_code
== CODE_64BIT
)
2810 as_fatal (_("Intel MCU is 32bit ELF only"));
2811 return bfd_arch_iamcu
;
2814 return bfd_arch_i386
;
2820 if (!strncmp (default_arch
, "x86_64", 6))
2822 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2825 || default_arch
[6] != '\0')
2826 as_fatal (_("Intel L1OM is 64bit ELF only"));
2827 return bfd_mach_l1om
;
2829 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2831 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2832 || default_arch
[6] != '\0')
2833 as_fatal (_("Intel K1OM is 64bit ELF only"));
2834 return bfd_mach_k1om
;
2836 else if (default_arch
[6] == '\0')
2837 return bfd_mach_x86_64
;
2839 return bfd_mach_x64_32
;
2841 else if (!strcmp (default_arch
, "i386")
2842 || !strcmp (default_arch
, "iamcu"))
2844 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2846 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2847 as_fatal (_("Intel MCU is 32bit ELF only"));
2848 return bfd_mach_i386_iamcu
;
2851 return bfd_mach_i386_i386
;
2854 as_fatal (_("unknown architecture"));
2860 const char *hash_err
;
2862 /* Support pseudo prefixes like {disp32}. */
2863 lex_type
['{'] = LEX_BEGIN_NAME
;
2865 /* Initialize op_hash hash table. */
2866 op_hash
= hash_new ();
2869 const insn_template
*optab
;
2870 templates
*core_optab
;
2872 /* Setup for loop. */
2874 core_optab
= XNEW (templates
);
2875 core_optab
->start
= optab
;
2880 if (optab
->name
== NULL
2881 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2883 /* different name --> ship out current template list;
2884 add to hash table; & begin anew. */
2885 core_optab
->end
= optab
;
2886 hash_err
= hash_insert (op_hash
,
2888 (void *) core_optab
);
2891 as_fatal (_("can't hash %s: %s"),
2895 if (optab
->name
== NULL
)
2897 core_optab
= XNEW (templates
);
2898 core_optab
->start
= optab
;
2903 /* Initialize reg_hash hash table. */
2904 reg_hash
= hash_new ();
2906 const reg_entry
*regtab
;
2907 unsigned int regtab_size
= i386_regtab_size
;
2909 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2911 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2913 as_fatal (_("can't hash %s: %s"),
2919 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2924 for (c
= 0; c
< 256; c
++)
2929 mnemonic_chars
[c
] = c
;
2930 register_chars
[c
] = c
;
2931 operand_chars
[c
] = c
;
2933 else if (ISLOWER (c
))
2935 mnemonic_chars
[c
] = c
;
2936 register_chars
[c
] = c
;
2937 operand_chars
[c
] = c
;
2939 else if (ISUPPER (c
))
2941 mnemonic_chars
[c
] = TOLOWER (c
);
2942 register_chars
[c
] = mnemonic_chars
[c
];
2943 operand_chars
[c
] = c
;
2945 else if (c
== '{' || c
== '}')
2947 mnemonic_chars
[c
] = c
;
2948 operand_chars
[c
] = c
;
2951 if (ISALPHA (c
) || ISDIGIT (c
))
2952 identifier_chars
[c
] = c
;
2955 identifier_chars
[c
] = c
;
2956 operand_chars
[c
] = c
;
2961 identifier_chars
['@'] = '@';
2964 identifier_chars
['?'] = '?';
2965 operand_chars
['?'] = '?';
2967 digit_chars
['-'] = '-';
2968 mnemonic_chars
['_'] = '_';
2969 mnemonic_chars
['-'] = '-';
2970 mnemonic_chars
['.'] = '.';
2971 identifier_chars
['_'] = '_';
2972 identifier_chars
['.'] = '.';
2974 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2975 operand_chars
[(unsigned char) *p
] = *p
;
2978 if (flag_code
== CODE_64BIT
)
2980 #if defined (OBJ_COFF) && defined (TE_PE)
2981 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2984 x86_dwarf2_return_column
= 16;
2986 x86_cie_data_alignment
= -8;
2990 x86_dwarf2_return_column
= 8;
2991 x86_cie_data_alignment
= -4;
2996 i386_print_statistics (FILE *file
)
2998 hash_print_statistics (file
, "i386 opcode", op_hash
);
2999 hash_print_statistics (file
, "i386 register", reg_hash
);
3004 /* Debugging routines for md_assemble. */
3005 static void pte (insn_template
*);
3006 static void pt (i386_operand_type
);
3007 static void pe (expressionS
*);
3008 static void ps (symbolS
*);
3011 pi (const char *line
, i386_insn
*x
)
3015 fprintf (stdout
, "%s: template ", line
);
3017 fprintf (stdout
, " address: base %s index %s scale %x\n",
3018 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3019 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3020 x
->log2_scale_factor
);
3021 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3022 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3023 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3024 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3025 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3026 (x
->rex
& REX_W
) != 0,
3027 (x
->rex
& REX_R
) != 0,
3028 (x
->rex
& REX_X
) != 0,
3029 (x
->rex
& REX_B
) != 0);
3030 for (j
= 0; j
< x
->operands
; j
++)
3032 fprintf (stdout
, " #%d: ", j
+ 1);
3034 fprintf (stdout
, "\n");
3035 if (x
->types
[j
].bitfield
.reg
3036 || x
->types
[j
].bitfield
.regmmx
3037 || x
->types
[j
].bitfield
.regsimd
3038 || x
->types
[j
].bitfield
.sreg
3039 || x
->types
[j
].bitfield
.control
3040 || x
->types
[j
].bitfield
.debug
3041 || x
->types
[j
].bitfield
.test
)
3042 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3043 if (operand_type_check (x
->types
[j
], imm
))
3045 if (operand_type_check (x
->types
[j
], disp
))
3046 pe (x
->op
[j
].disps
);
3051 pte (insn_template
*t
)
3054 fprintf (stdout
, " %d operands ", t
->operands
);
3055 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3056 if (t
->extension_opcode
!= None
)
3057 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3058 if (t
->opcode_modifier
.d
)
3059 fprintf (stdout
, "D");
3060 if (t
->opcode_modifier
.w
)
3061 fprintf (stdout
, "W");
3062 fprintf (stdout
, "\n");
3063 for (j
= 0; j
< t
->operands
; j
++)
3065 fprintf (stdout
, " #%d type ", j
+ 1);
3066 pt (t
->operand_types
[j
]);
3067 fprintf (stdout
, "\n");
3074 fprintf (stdout
, " operation %d\n", e
->X_op
);
3075 fprintf (stdout
, " add_number %ld (%lx)\n",
3076 (long) e
->X_add_number
, (long) e
->X_add_number
);
3077 if (e
->X_add_symbol
)
3079 fprintf (stdout
, " add_symbol ");
3080 ps (e
->X_add_symbol
);
3081 fprintf (stdout
, "\n");
3085 fprintf (stdout
, " op_symbol ");
3086 ps (e
->X_op_symbol
);
3087 fprintf (stdout
, "\n");
3094 fprintf (stdout
, "%s type %s%s",
3096 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3097 segment_name (S_GET_SEGMENT (s
)));
3100 static struct type_name
3102 i386_operand_type mask
;
3105 const type_names
[] =
3107 { OPERAND_TYPE_REG8
, "r8" },
3108 { OPERAND_TYPE_REG16
, "r16" },
3109 { OPERAND_TYPE_REG32
, "r32" },
3110 { OPERAND_TYPE_REG64
, "r64" },
3111 { OPERAND_TYPE_ACC8
, "acc8" },
3112 { OPERAND_TYPE_ACC16
, "acc16" },
3113 { OPERAND_TYPE_ACC32
, "acc32" },
3114 { OPERAND_TYPE_ACC64
, "acc64" },
3115 { OPERAND_TYPE_IMM8
, "i8" },
3116 { OPERAND_TYPE_IMM8
, "i8s" },
3117 { OPERAND_TYPE_IMM16
, "i16" },
3118 { OPERAND_TYPE_IMM32
, "i32" },
3119 { OPERAND_TYPE_IMM32S
, "i32s" },
3120 { OPERAND_TYPE_IMM64
, "i64" },
3121 { OPERAND_TYPE_IMM1
, "i1" },
3122 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3123 { OPERAND_TYPE_DISP8
, "d8" },
3124 { OPERAND_TYPE_DISP16
, "d16" },
3125 { OPERAND_TYPE_DISP32
, "d32" },
3126 { OPERAND_TYPE_DISP32S
, "d32s" },
3127 { OPERAND_TYPE_DISP64
, "d64" },
3128 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3129 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3130 { OPERAND_TYPE_CONTROL
, "control reg" },
3131 { OPERAND_TYPE_TEST
, "test reg" },
3132 { OPERAND_TYPE_DEBUG
, "debug reg" },
3133 { OPERAND_TYPE_FLOATREG
, "FReg" },
3134 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3135 { OPERAND_TYPE_SREG
, "SReg" },
3136 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3137 { OPERAND_TYPE_REGMMX
, "rMMX" },
3138 { OPERAND_TYPE_REGXMM
, "rXMM" },
3139 { OPERAND_TYPE_REGYMM
, "rYMM" },
3140 { OPERAND_TYPE_REGZMM
, "rZMM" },
3141 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3142 { OPERAND_TYPE_ESSEG
, "es" },
3146 pt (i386_operand_type t
)
3149 i386_operand_type a
;
3151 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3153 a
= operand_type_and (t
, type_names
[j
].mask
);
3154 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3155 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3160 #endif /* DEBUG386 */
3162 static bfd_reloc_code_real_type
3163 reloc (unsigned int size
,
3166 bfd_reloc_code_real_type other
)
3168 if (other
!= NO_RELOC
)
3170 reloc_howto_type
*rel
;
3175 case BFD_RELOC_X86_64_GOT32
:
3176 return BFD_RELOC_X86_64_GOT64
;
3178 case BFD_RELOC_X86_64_GOTPLT64
:
3179 return BFD_RELOC_X86_64_GOTPLT64
;
3181 case BFD_RELOC_X86_64_PLTOFF64
:
3182 return BFD_RELOC_X86_64_PLTOFF64
;
3184 case BFD_RELOC_X86_64_GOTPC32
:
3185 other
= BFD_RELOC_X86_64_GOTPC64
;
3187 case BFD_RELOC_X86_64_GOTPCREL
:
3188 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3190 case BFD_RELOC_X86_64_TPOFF32
:
3191 other
= BFD_RELOC_X86_64_TPOFF64
;
3193 case BFD_RELOC_X86_64_DTPOFF32
:
3194 other
= BFD_RELOC_X86_64_DTPOFF64
;
3200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3201 if (other
== BFD_RELOC_SIZE32
)
3204 other
= BFD_RELOC_SIZE64
;
3207 as_bad (_("there are no pc-relative size relocations"));
3213 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3214 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3217 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3219 as_bad (_("unknown relocation (%u)"), other
);
3220 else if (size
!= bfd_get_reloc_size (rel
))
3221 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3222 bfd_get_reloc_size (rel
),
3224 else if (pcrel
&& !rel
->pc_relative
)
3225 as_bad (_("non-pc-relative relocation for pc-relative field"));
3226 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3228 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3230 as_bad (_("relocated field and relocation type differ in signedness"));
3239 as_bad (_("there are no unsigned pc-relative relocations"));
3242 case 1: return BFD_RELOC_8_PCREL
;
3243 case 2: return BFD_RELOC_16_PCREL
;
3244 case 4: return BFD_RELOC_32_PCREL
;
3245 case 8: return BFD_RELOC_64_PCREL
;
3247 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3254 case 4: return BFD_RELOC_X86_64_32S
;
3259 case 1: return BFD_RELOC_8
;
3260 case 2: return BFD_RELOC_16
;
3261 case 4: return BFD_RELOC_32
;
3262 case 8: return BFD_RELOC_64
;
3264 as_bad (_("cannot do %s %u byte relocation"),
3265 sign
> 0 ? "signed" : "unsigned", size
);
3271 /* Here we decide which fixups can be adjusted to make them relative to
3272 the beginning of the section instead of the symbol. Basically we need
3273 to make sure that the dynamic relocations are done correctly, so in
3274 some cases we force the original symbol to be used. */
3277 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3283 /* Don't adjust pc-relative references to merge sections in 64-bit
3285 if (use_rela_relocations
3286 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3290 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3291 and changed later by validate_fix. */
3292 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3293 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3296 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3297 for size relocations. */
3298 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3299 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3300 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3301 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3302 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3310 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3311 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3312 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3313 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3325 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3329 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3330 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3337 intel_float_operand (const char *mnemonic
)
3339 /* Note that the value returned is meaningful only for opcodes with (memory)
3340 operands, hence the code here is free to improperly handle opcodes that
3341 have no operands (for better performance and smaller code). */
3343 if (mnemonic
[0] != 'f')
3344 return 0; /* non-math */
3346 switch (mnemonic
[1])
3348 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3349 the fs segment override prefix not currently handled because no
3350 call path can make opcodes without operands get here */
3352 return 2 /* integer op */;
3354 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3355 return 3; /* fldcw/fldenv */
3358 if (mnemonic
[2] != 'o' /* fnop */)
3359 return 3; /* non-waiting control op */
3362 if (mnemonic
[2] == 's')
3363 return 3; /* frstor/frstpm */
3366 if (mnemonic
[2] == 'a')
3367 return 3; /* fsave */
3368 if (mnemonic
[2] == 't')
3370 switch (mnemonic
[3])
3372 case 'c': /* fstcw */
3373 case 'd': /* fstdw */
3374 case 'e': /* fstenv */
3375 case 's': /* fsts[gw] */
3381 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3382 return 0; /* fxsave/fxrstor are not really math ops */
3389 /* Build the VEX prefix. */
3392 build_vex_prefix (const insn_template
*t
)
3394 unsigned int register_specifier
;
3395 unsigned int implied_prefix
;
3396 unsigned int vector_length
;
3399 /* Check register specifier. */
3400 if (i
.vex
.register_specifier
)
3402 register_specifier
=
3403 ~register_number (i
.vex
.register_specifier
) & 0xf;
3404 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3407 register_specifier
= 0xf;
3409 /* Use 2-byte VEX prefix by swapping destination and source operand
3410 if there are more than 1 register operand. */
3411 if (i
.reg_operands
> 1
3412 && i
.vec_encoding
!= vex_encoding_vex3
3413 && i
.dir_encoding
== dir_encoding_default
3414 && i
.operands
== i
.reg_operands
3415 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3416 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3417 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3420 unsigned int xchg
= i
.operands
- 1;
3421 union i386_op temp_op
;
3422 i386_operand_type temp_type
;
3424 temp_type
= i
.types
[xchg
];
3425 i
.types
[xchg
] = i
.types
[0];
3426 i
.types
[0] = temp_type
;
3427 temp_op
= i
.op
[xchg
];
3428 i
.op
[xchg
] = i
.op
[0];
3431 gas_assert (i
.rm
.mode
== 3);
3435 i
.rm
.regmem
= i
.rm
.reg
;
3438 if (i
.tm
.opcode_modifier
.d
)
3439 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3440 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3441 else /* Use the next insn. */
3445 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3446 are no memory operands and at least 3 register ones. */
3447 if (i
.reg_operands
>= 3
3448 && i
.vec_encoding
!= vex_encoding_vex3
3449 && i
.reg_operands
== i
.operands
- i
.imm_operands
3450 && i
.tm
.opcode_modifier
.vex
3451 && i
.tm
.opcode_modifier
.commutative
3452 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3454 && i
.vex
.register_specifier
3455 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3457 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3458 union i386_op temp_op
;
3459 i386_operand_type temp_type
;
3461 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3462 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3463 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3464 &i
.types
[i
.operands
- 3]));
3465 gas_assert (i
.rm
.mode
== 3);
3467 temp_type
= i
.types
[xchg
];
3468 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3469 i
.types
[xchg
+ 1] = temp_type
;
3470 temp_op
= i
.op
[xchg
];
3471 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3472 i
.op
[xchg
+ 1] = temp_op
;
3475 xchg
= i
.rm
.regmem
| 8;
3476 i
.rm
.regmem
= ~register_specifier
& 0xf;
3477 gas_assert (!(i
.rm
.regmem
& 8));
3478 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3479 register_specifier
= ~xchg
& 0xf;
3482 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3483 vector_length
= avxscalar
;
3484 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3490 /* Determine vector length from the last multi-length vector
3493 for (op
= t
->operands
; op
--;)
3494 if (t
->operand_types
[op
].bitfield
.xmmword
3495 && t
->operand_types
[op
].bitfield
.ymmword
3496 && i
.types
[op
].bitfield
.ymmword
)
3503 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3508 case DATA_PREFIX_OPCODE
:
3511 case REPE_PREFIX_OPCODE
:
3514 case REPNE_PREFIX_OPCODE
:
3521 /* Check the REX.W bit and VEXW. */
3522 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3523 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3524 else if (i
.tm
.opcode_modifier
.vexw
)
3525 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3527 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3529 /* Use 2-byte VEX prefix if possible. */
3531 && i
.vec_encoding
!= vex_encoding_vex3
3532 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3533 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3535 /* 2-byte VEX prefix. */
3539 i
.vex
.bytes
[0] = 0xc5;
3541 /* Check the REX.R bit. */
3542 r
= (i
.rex
& REX_R
) ? 0 : 1;
3543 i
.vex
.bytes
[1] = (r
<< 7
3544 | register_specifier
<< 3
3545 | vector_length
<< 2
3550 /* 3-byte VEX prefix. */
3555 switch (i
.tm
.opcode_modifier
.vexopcode
)
3559 i
.vex
.bytes
[0] = 0xc4;
3563 i
.vex
.bytes
[0] = 0xc4;
3567 i
.vex
.bytes
[0] = 0xc4;
3571 i
.vex
.bytes
[0] = 0x8f;
3575 i
.vex
.bytes
[0] = 0x8f;
3579 i
.vex
.bytes
[0] = 0x8f;
3585 /* The high 3 bits of the second VEX byte are 1's compliment
3586 of RXB bits from REX. */
3587 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3589 i
.vex
.bytes
[2] = (w
<< 7
3590 | register_specifier
<< 3
3591 | vector_length
<< 2
3596 static INLINE bfd_boolean
3597 is_evex_encoding (const insn_template
*t
)
3599 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3600 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3601 || t
->opcode_modifier
.sae
;
3604 static INLINE bfd_boolean
3605 is_any_vex_encoding (const insn_template
*t
)
3607 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3608 || is_evex_encoding (t
);
3611 /* Build the EVEX prefix. */
3614 build_evex_prefix (void)
3616 unsigned int register_specifier
;
3617 unsigned int implied_prefix
;
3619 rex_byte vrex_used
= 0;
3621 /* Check register specifier. */
3622 if (i
.vex
.register_specifier
)
3624 gas_assert ((i
.vrex
& REX_X
) == 0);
3626 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3627 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3628 register_specifier
+= 8;
3629 /* The upper 16 registers are encoded in the fourth byte of the
3631 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3632 i
.vex
.bytes
[3] = 0x8;
3633 register_specifier
= ~register_specifier
& 0xf;
3637 register_specifier
= 0xf;
3639 /* Encode upper 16 vector index register in the fourth byte of
3641 if (!(i
.vrex
& REX_X
))
3642 i
.vex
.bytes
[3] = 0x8;
3647 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3652 case DATA_PREFIX_OPCODE
:
3655 case REPE_PREFIX_OPCODE
:
3658 case REPNE_PREFIX_OPCODE
:
3665 /* 4 byte EVEX prefix. */
3667 i
.vex
.bytes
[0] = 0x62;
3670 switch (i
.tm
.opcode_modifier
.vexopcode
)
3686 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3688 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3690 /* The fifth bit of the second EVEX byte is 1's compliment of the
3691 REX_R bit in VREX. */
3692 if (!(i
.vrex
& REX_R
))
3693 i
.vex
.bytes
[1] |= 0x10;
3697 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3699 /* When all operands are registers, the REX_X bit in REX is not
3700 used. We reuse it to encode the upper 16 registers, which is
3701 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3702 as 1's compliment. */
3703 if ((i
.vrex
& REX_B
))
3706 i
.vex
.bytes
[1] &= ~0x40;
3710 /* EVEX instructions shouldn't need the REX prefix. */
3711 i
.vrex
&= ~vrex_used
;
3712 gas_assert (i
.vrex
== 0);
3714 /* Check the REX.W bit and VEXW. */
3715 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3716 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3717 else if (i
.tm
.opcode_modifier
.vexw
)
3718 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3720 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3722 /* Encode the U bit. */
3723 implied_prefix
|= 0x4;
3725 /* The third byte of the EVEX prefix. */
3726 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3728 /* The fourth byte of the EVEX prefix. */
3729 /* The zeroing-masking bit. */
3730 if (i
.mask
&& i
.mask
->zeroing
)
3731 i
.vex
.bytes
[3] |= 0x80;
3733 /* Don't always set the broadcast bit if there is no RC. */
3736 /* Encode the vector length. */
3737 unsigned int vec_length
;
3739 if (!i
.tm
.opcode_modifier
.evex
3740 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3744 /* Determine vector length from the last multi-length vector
3747 for (op
= i
.operands
; op
--;)
3748 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3749 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3750 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3752 if (i
.types
[op
].bitfield
.zmmword
)
3754 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3757 else if (i
.types
[op
].bitfield
.ymmword
)
3759 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3762 else if (i
.types
[op
].bitfield
.xmmword
)
3764 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3767 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3769 switch (i
.broadcast
->bytes
)
3772 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3775 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3778 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3787 if (op
>= MAX_OPERANDS
)
3791 switch (i
.tm
.opcode_modifier
.evex
)
3793 case EVEXLIG
: /* LL' is ignored */
3794 vec_length
= evexlig
<< 5;
3797 vec_length
= 0 << 5;
3800 vec_length
= 1 << 5;
3803 vec_length
= 2 << 5;
3809 i
.vex
.bytes
[3] |= vec_length
;
3810 /* Encode the broadcast bit. */
3812 i
.vex
.bytes
[3] |= 0x10;
3816 if (i
.rounding
->type
!= saeonly
)
3817 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3819 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3822 if (i
.mask
&& i
.mask
->mask
)
3823 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3827 process_immext (void)
3831 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3834 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3835 with an opcode suffix which is coded in the same place as an
3836 8-bit immediate field would be.
3837 Here we check those operands and remove them afterwards. */
3840 for (x
= 0; x
< i
.operands
; x
++)
3841 if (register_number (i
.op
[x
].regs
) != x
)
3842 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3843 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3849 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3851 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3852 suffix which is coded in the same place as an 8-bit immediate
3854 Here we check those operands and remove them afterwards. */
3857 if (i
.operands
!= 3)
3860 for (x
= 0; x
< 2; x
++)
3861 if (register_number (i
.op
[x
].regs
) != x
)
3862 goto bad_register_operand
;
3864 /* Check for third operand for mwaitx/monitorx insn. */
3865 if (register_number (i
.op
[x
].regs
)
3866 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3868 bad_register_operand
:
3869 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3870 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3877 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3878 which is coded in the same place as an 8-bit immediate field
3879 would be. Here we fake an 8-bit immediate operand from the
3880 opcode suffix stored in tm.extension_opcode.
3882 AVX instructions also use this encoding, for some of
3883 3 argument instructions. */
3885 gas_assert (i
.imm_operands
<= 1
3887 || (is_any_vex_encoding (&i
.tm
)
3888 && i
.operands
<= 4)));
3890 exp
= &im_expressions
[i
.imm_operands
++];
3891 i
.op
[i
.operands
].imms
= exp
;
3892 i
.types
[i
.operands
] = imm8
;
3894 exp
->X_op
= O_constant
;
3895 exp
->X_add_number
= i
.tm
.extension_opcode
;
3896 i
.tm
.extension_opcode
= None
;
3903 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3908 as_bad (_("invalid instruction `%s' after `%s'"),
3909 i
.tm
.name
, i
.hle_prefix
);
3912 if (i
.prefix
[LOCK_PREFIX
])
3914 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3918 case HLEPrefixRelease
:
3919 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3921 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3925 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3927 as_bad (_("memory destination needed for instruction `%s'"
3928 " after `xrelease'"), i
.tm
.name
);
3935 /* Try the shortest encoding by shortening operand size. */
3938 optimize_encoding (void)
3942 if (optimize_for_space
3943 && i
.reg_operands
== 1
3944 && i
.imm_operands
== 1
3945 && !i
.types
[1].bitfield
.byte
3946 && i
.op
[0].imms
->X_op
== O_constant
3947 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3948 && ((i
.tm
.base_opcode
== 0xa8
3949 && i
.tm
.extension_opcode
== None
)
3950 || (i
.tm
.base_opcode
== 0xf6
3951 && i
.tm
.extension_opcode
== 0x0)))
3954 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3956 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3957 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3959 i
.types
[1].bitfield
.byte
= 1;
3960 /* Ignore the suffix. */
3962 if (base_regnum
>= 4
3963 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3965 /* Handle SP, BP, SI and DI registers. */
3966 if (i
.types
[1].bitfield
.word
)
3968 else if (i
.types
[1].bitfield
.dword
)
3976 else if (flag_code
== CODE_64BIT
3977 && ((i
.types
[1].bitfield
.qword
3978 && i
.reg_operands
== 1
3979 && i
.imm_operands
== 1
3980 && i
.op
[0].imms
->X_op
== O_constant
3981 && ((i
.tm
.base_opcode
== 0xb8
3982 && i
.tm
.extension_opcode
== None
3983 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3984 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3985 && (((i
.tm
.base_opcode
== 0x24
3986 || i
.tm
.base_opcode
== 0xa8)
3987 && i
.tm
.extension_opcode
== None
)
3988 || (i
.tm
.base_opcode
== 0x80
3989 && i
.tm
.extension_opcode
== 0x4)
3990 || ((i
.tm
.base_opcode
== 0xf6
3991 || (i
.tm
.base_opcode
| 1) == 0xc7)
3992 && i
.tm
.extension_opcode
== 0x0)))
3993 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3994 && i
.tm
.base_opcode
== 0x83
3995 && i
.tm
.extension_opcode
== 0x4)))
3996 || (i
.types
[0].bitfield
.qword
3997 && ((i
.reg_operands
== 2
3998 && i
.op
[0].regs
== i
.op
[1].regs
3999 && ((i
.tm
.base_opcode
== 0x30
4000 || i
.tm
.base_opcode
== 0x28)
4001 && i
.tm
.extension_opcode
== None
))
4002 || (i
.reg_operands
== 1
4004 && i
.tm
.base_opcode
== 0x30
4005 && i
.tm
.extension_opcode
== None
)))))
4008 andq $imm31, %r64 -> andl $imm31, %r32
4009 andq $imm7, %r64 -> andl $imm7, %r32
4010 testq $imm31, %r64 -> testl $imm31, %r32
4011 xorq %r64, %r64 -> xorl %r32, %r32
4012 subq %r64, %r64 -> subl %r32, %r32
4013 movq $imm31, %r64 -> movl $imm31, %r32
4014 movq $imm32, %r64 -> movl $imm32, %r32
4016 i
.tm
.opcode_modifier
.norex64
= 1;
4017 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4020 movq $imm31, %r64 -> movl $imm31, %r32
4021 movq $imm32, %r64 -> movl $imm32, %r32
4023 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4024 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4025 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4026 i
.types
[0].bitfield
.imm32
= 1;
4027 i
.types
[0].bitfield
.imm32s
= 0;
4028 i
.types
[0].bitfield
.imm64
= 0;
4029 i
.types
[1].bitfield
.dword
= 1;
4030 i
.types
[1].bitfield
.qword
= 0;
4031 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4034 movq $imm31, %r64 -> movl $imm31, %r32
4036 i
.tm
.base_opcode
= 0xb8;
4037 i
.tm
.extension_opcode
= None
;
4038 i
.tm
.opcode_modifier
.w
= 0;
4039 i
.tm
.opcode_modifier
.shortform
= 1;
4040 i
.tm
.opcode_modifier
.modrm
= 0;
4044 else if (optimize
> 1
4045 && !optimize_for_space
4046 && i
.reg_operands
== 2
4047 && i
.op
[0].regs
== i
.op
[1].regs
4048 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4049 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4050 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4053 andb %rN, %rN -> testb %rN, %rN
4054 andw %rN, %rN -> testw %rN, %rN
4055 andq %rN, %rN -> testq %rN, %rN
4056 orb %rN, %rN -> testb %rN, %rN
4057 orw %rN, %rN -> testw %rN, %rN
4058 orq %rN, %rN -> testq %rN, %rN
4060 and outside of 64-bit mode
4062 andl %rN, %rN -> testl %rN, %rN
4063 orl %rN, %rN -> testl %rN, %rN
4065 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4067 else if (i
.reg_operands
== 3
4068 && i
.op
[0].regs
== i
.op
[1].regs
4069 && !i
.types
[2].bitfield
.xmmword
4070 && (i
.tm
.opcode_modifier
.vex
4071 || ((!i
.mask
|| i
.mask
->zeroing
)
4073 && is_evex_encoding (&i
.tm
)
4074 && (i
.vec_encoding
!= vex_encoding_evex
4075 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4076 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4077 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4078 && i
.types
[2].bitfield
.ymmword
))))
4079 && ((i
.tm
.base_opcode
== 0x55
4080 || i
.tm
.base_opcode
== 0x6655
4081 || i
.tm
.base_opcode
== 0x66df
4082 || i
.tm
.base_opcode
== 0x57
4083 || i
.tm
.base_opcode
== 0x6657
4084 || i
.tm
.base_opcode
== 0x66ef
4085 || i
.tm
.base_opcode
== 0x66f8
4086 || i
.tm
.base_opcode
== 0x66f9
4087 || i
.tm
.base_opcode
== 0x66fa
4088 || i
.tm
.base_opcode
== 0x66fb
4089 || i
.tm
.base_opcode
== 0x42
4090 || i
.tm
.base_opcode
== 0x6642
4091 || i
.tm
.base_opcode
== 0x47
4092 || i
.tm
.base_opcode
== 0x6647)
4093 && i
.tm
.extension_opcode
== None
))
4096 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4098 EVEX VOP %zmmM, %zmmM, %zmmN
4099 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4100 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4101 EVEX VOP %ymmM, %ymmM, %ymmN
4102 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4103 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4104 VEX VOP %ymmM, %ymmM, %ymmN
4105 -> VEX VOP %xmmM, %xmmM, %xmmN
4106 VOP, one of vpandn and vpxor:
4107 VEX VOP %ymmM, %ymmM, %ymmN
4108 -> VEX VOP %xmmM, %xmmM, %xmmN
4109 VOP, one of vpandnd and vpandnq:
4110 EVEX VOP %zmmM, %zmmM, %zmmN
4111 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4112 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4113 EVEX VOP %ymmM, %ymmM, %ymmN
4114 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4115 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4116 VOP, one of vpxord and vpxorq:
4117 EVEX VOP %zmmM, %zmmM, %zmmN
4118 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4119 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4120 EVEX VOP %ymmM, %ymmM, %ymmN
4121 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4122 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4123 VOP, one of kxord and kxorq:
4124 VEX VOP %kM, %kM, %kN
4125 -> VEX kxorw %kM, %kM, %kN
4126 VOP, one of kandnd and kandnq:
4127 VEX VOP %kM, %kM, %kN
4128 -> VEX kandnw %kM, %kM, %kN
4130 if (is_evex_encoding (&i
.tm
))
4132 if (i
.vec_encoding
!= vex_encoding_evex
)
4134 i
.tm
.opcode_modifier
.vex
= VEX128
;
4135 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4136 i
.tm
.opcode_modifier
.evex
= 0;
4138 else if (optimize
> 1)
4139 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4143 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4145 i
.tm
.base_opcode
&= 0xff;
4146 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4149 i
.tm
.opcode_modifier
.vex
= VEX128
;
4151 if (i
.tm
.opcode_modifier
.vex
)
4152 for (j
= 0; j
< 3; j
++)
4154 i
.types
[j
].bitfield
.xmmword
= 1;
4155 i
.types
[j
].bitfield
.ymmword
= 0;
4158 else if (i
.vec_encoding
!= vex_encoding_evex
4159 && !i
.types
[0].bitfield
.zmmword
4160 && !i
.types
[1].bitfield
.zmmword
4163 && is_evex_encoding (&i
.tm
)
4164 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4165 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4166 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4167 || (i
.tm
.base_opcode
& ~4) == 0x66db
4168 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4169 && i
.tm
.extension_opcode
== None
)
4172 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4173 vmovdqu32 and vmovdqu64:
4174 EVEX VOP %xmmM, %xmmN
4175 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4176 EVEX VOP %ymmM, %ymmN
4177 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4179 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4181 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4183 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4185 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4186 VOP, one of vpand, vpandn, vpor, vpxor:
4187 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4188 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4189 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4190 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4191 EVEX VOP{d,q} mem, %xmmM, %xmmN
4192 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4193 EVEX VOP{d,q} mem, %ymmM, %ymmN
4194 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4196 for (j
= 0; j
< i
.operands
; j
++)
4197 if (operand_type_check (i
.types
[j
], disp
)
4198 && i
.op
[j
].disps
->X_op
== O_constant
)
4200 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4201 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4202 bytes, we choose EVEX Disp8 over VEX Disp32. */
4203 int evex_disp8
, vex_disp8
;
4204 unsigned int memshift
= i
.memshift
;
4205 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4207 evex_disp8
= fits_in_disp8 (n
);
4209 vex_disp8
= fits_in_disp8 (n
);
4210 if (evex_disp8
!= vex_disp8
)
4212 i
.memshift
= memshift
;
4216 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4219 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4220 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4221 i
.tm
.opcode_modifier
.vex
4222 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4223 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4224 /* VPAND, VPOR, and VPXOR are commutative. */
4225 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4226 i
.tm
.opcode_modifier
.commutative
= 1;
4227 i
.tm
.opcode_modifier
.evex
= 0;
4228 i
.tm
.opcode_modifier
.masking
= 0;
4229 i
.tm
.opcode_modifier
.broadcast
= 0;
4230 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4233 i
.types
[j
].bitfield
.disp8
4234 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4238 /* This is the guts of the machine-dependent assembler. LINE points to a
4239 machine dependent instruction. This function is supposed to emit
4240 the frags/bytes it assembles to. */
4243 md_assemble (char *line
)
4246 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4247 const insn_template
*t
;
4249 /* Initialize globals. */
4250 memset (&i
, '\0', sizeof (i
));
4251 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4252 i
.reloc
[j
] = NO_RELOC
;
4253 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4254 memset (im_expressions
, '\0', sizeof (im_expressions
));
4255 save_stack_p
= save_stack
;
4257 /* First parse an instruction mnemonic & call i386_operand for the operands.
4258 We assume that the scrubber has arranged it so that line[0] is the valid
4259 start of a (possibly prefixed) mnemonic. */
4261 line
= parse_insn (line
, mnemonic
);
4264 mnem_suffix
= i
.suffix
;
4266 line
= parse_operands (line
, mnemonic
);
4268 xfree (i
.memop1_string
);
4269 i
.memop1_string
= NULL
;
4273 /* Now we've parsed the mnemonic into a set of templates, and have the
4274 operands at hand. */
4276 /* All intel opcodes have reversed operands except for "bound" and
4277 "enter". We also don't reverse intersegment "jmp" and "call"
4278 instructions with 2 immediate operands so that the immediate segment
4279 precedes the offset, as it does when in AT&T mode. */
4282 && (strcmp (mnemonic
, "bound") != 0)
4283 && (strcmp (mnemonic
, "invlpga") != 0)
4284 && !(operand_type_check (i
.types
[0], imm
)
4285 && operand_type_check (i
.types
[1], imm
)))
4288 /* The order of the immediates should be reversed
4289 for 2 immediates extrq and insertq instructions */
4290 if (i
.imm_operands
== 2
4291 && (strcmp (mnemonic
, "extrq") == 0
4292 || strcmp (mnemonic
, "insertq") == 0))
4293 swap_2_operands (0, 1);
4298 /* Don't optimize displacement for movabs since it only takes 64bit
4301 && i
.disp_encoding
!= disp_encoding_32bit
4302 && (flag_code
!= CODE_64BIT
4303 || strcmp (mnemonic
, "movabs") != 0))
4306 /* Next, we find a template that matches the given insn,
4307 making sure the overlap of the given operands types is consistent
4308 with the template operand types. */
4310 if (!(t
= match_template (mnem_suffix
)))
4313 if (sse_check
!= check_none
4314 && !i
.tm
.opcode_modifier
.noavx
4315 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4316 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4317 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4318 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4319 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4320 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4321 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4322 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4323 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4324 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4326 (sse_check
== check_warning
4328 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4331 /* Zap movzx and movsx suffix. The suffix has been set from
4332 "word ptr" or "byte ptr" on the source operand in Intel syntax
4333 or extracted from mnemonic in AT&T syntax. But we'll use
4334 the destination register to choose the suffix for encoding. */
4335 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4337 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4338 there is no suffix, the default will be byte extension. */
4339 if (i
.reg_operands
!= 2
4342 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4347 if (i
.tm
.opcode_modifier
.fwait
)
4348 if (!add_prefix (FWAIT_OPCODE
))
4351 /* Check if REP prefix is OK. */
4352 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4354 as_bad (_("invalid instruction `%s' after `%s'"),
4355 i
.tm
.name
, i
.rep_prefix
);
4359 /* Check for lock without a lockable instruction. Destination operand
4360 must be memory unless it is xchg (0x86). */
4361 if (i
.prefix
[LOCK_PREFIX
]
4362 && (!i
.tm
.opcode_modifier
.islockable
4363 || i
.mem_operands
== 0
4364 || (i
.tm
.base_opcode
!= 0x86
4365 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4367 as_bad (_("expecting lockable instruction after `lock'"));
4371 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4372 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4374 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4378 /* Check if HLE prefix is OK. */
4379 if (i
.hle_prefix
&& !check_hle ())
4382 /* Check BND prefix. */
4383 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4384 as_bad (_("expecting valid branch instruction after `bnd'"));
4386 /* Check NOTRACK prefix. */
4387 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4388 as_bad (_("expecting indirect branch instruction after `notrack'"));
4390 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4392 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4393 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4394 else if (flag_code
!= CODE_16BIT
4395 ? i
.prefix
[ADDR_PREFIX
]
4396 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4397 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4400 /* Insert BND prefix. */
4401 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4403 if (!i
.prefix
[BND_PREFIX
])
4404 add_prefix (BND_PREFIX_OPCODE
);
4405 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4407 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4408 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4412 /* Check string instruction segment overrides. */
4413 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4415 if (!check_string ())
4417 i
.disp_operands
= 0;
4420 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4421 optimize_encoding ();
4423 if (!process_suffix ())
4426 /* Update operand types. */
4427 for (j
= 0; j
< i
.operands
; j
++)
4428 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4430 /* Make still unresolved immediate matches conform to size of immediate
4431 given in i.suffix. */
4432 if (!finalize_imm ())
4435 if (i
.types
[0].bitfield
.imm1
)
4436 i
.imm_operands
= 0; /* kludge for shift insns. */
4438 /* We only need to check those implicit registers for instructions
4439 with 3 operands or less. */
4440 if (i
.operands
<= 3)
4441 for (j
= 0; j
< i
.operands
; j
++)
4442 if (i
.types
[j
].bitfield
.inoutportreg
4443 || i
.types
[j
].bitfield
.shiftcount
4444 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4447 /* ImmExt should be processed after SSE2AVX. */
4448 if (!i
.tm
.opcode_modifier
.sse2avx
4449 && i
.tm
.opcode_modifier
.immext
)
4452 /* For insns with operands there are more diddles to do to the opcode. */
4455 if (!process_operands ())
4458 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4460 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4461 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4464 if (is_any_vex_encoding (&i
.tm
))
4466 if (!cpu_arch_flags
.bitfield
.cpui286
)
4468 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4473 if (i
.tm
.opcode_modifier
.vex
)
4474 build_vex_prefix (t
);
4476 build_evex_prefix ();
4479 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4480 instructions may define INT_OPCODE as well, so avoid this corner
4481 case for those instructions that use MODRM. */
4482 if (i
.tm
.base_opcode
== INT_OPCODE
4483 && !i
.tm
.opcode_modifier
.modrm
4484 && i
.op
[0].imms
->X_add_number
== 3)
4486 i
.tm
.base_opcode
= INT3_OPCODE
;
4490 if ((i
.tm
.opcode_modifier
.jump
4491 || i
.tm
.opcode_modifier
.jumpbyte
4492 || i
.tm
.opcode_modifier
.jumpdword
)
4493 && i
.op
[0].disps
->X_op
== O_constant
)
4495 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4496 the absolute address given by the constant. Since ix86 jumps and
4497 calls are pc relative, we need to generate a reloc. */
4498 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4499 i
.op
[0].disps
->X_op
= O_symbol
;
4502 if (i
.tm
.opcode_modifier
.rex64
)
4505 /* For 8 bit registers we need an empty rex prefix. Also if the
4506 instruction already has a prefix, we need to convert old
4507 registers to new ones. */
4509 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4510 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4511 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4512 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4513 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4514 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4519 i
.rex
|= REX_OPCODE
;
4520 for (x
= 0; x
< 2; x
++)
4522 /* Look for 8 bit operand that uses old registers. */
4523 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4524 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4526 /* In case it is "hi" register, give up. */
4527 if (i
.op
[x
].regs
->reg_num
> 3)
4528 as_bad (_("can't encode register '%s%s' in an "
4529 "instruction requiring REX prefix."),
4530 register_prefix
, i
.op
[x
].regs
->reg_name
);
4532 /* Otherwise it is equivalent to the extended register.
4533 Since the encoding doesn't change this is merely
4534 cosmetic cleanup for debug output. */
4536 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4541 if (i
.rex
== 0 && i
.rex_encoding
)
4543 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4544 that uses legacy register. If it is "hi" register, don't add
4545 the REX_OPCODE byte. */
4547 for (x
= 0; x
< 2; x
++)
4548 if (i
.types
[x
].bitfield
.reg
4549 && i
.types
[x
].bitfield
.byte
4550 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4551 && i
.op
[x
].regs
->reg_num
> 3)
4553 i
.rex_encoding
= FALSE
;
4562 add_prefix (REX_OPCODE
| i
.rex
);
4564 /* We are ready to output the insn. */
4569 parse_insn (char *line
, char *mnemonic
)
4572 char *token_start
= l
;
4575 const insn_template
*t
;
4581 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4586 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4588 as_bad (_("no such instruction: `%s'"), token_start
);
4593 if (!is_space_char (*l
)
4594 && *l
!= END_OF_INSN
4596 || (*l
!= PREFIX_SEPARATOR
4599 as_bad (_("invalid character %s in mnemonic"),
4600 output_invalid (*l
));
4603 if (token_start
== l
)
4605 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4606 as_bad (_("expecting prefix; got nothing"));
4608 as_bad (_("expecting mnemonic; got nothing"));
4612 /* Look up instruction (or prefix) via hash table. */
4613 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4615 if (*l
!= END_OF_INSN
4616 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4617 && current_templates
4618 && current_templates
->start
->opcode_modifier
.isprefix
)
4620 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4622 as_bad ((flag_code
!= CODE_64BIT
4623 ? _("`%s' is only supported in 64-bit mode")
4624 : _("`%s' is not supported in 64-bit mode")),
4625 current_templates
->start
->name
);
4628 /* If we are in 16-bit mode, do not allow addr16 or data16.
4629 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4630 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4631 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4632 && flag_code
!= CODE_64BIT
4633 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4634 ^ (flag_code
== CODE_16BIT
)))
4636 as_bad (_("redundant %s prefix"),
4637 current_templates
->start
->name
);
4640 if (current_templates
->start
->opcode_length
== 0)
4642 /* Handle pseudo prefixes. */
4643 switch (current_templates
->start
->base_opcode
)
4647 i
.disp_encoding
= disp_encoding_8bit
;
4651 i
.disp_encoding
= disp_encoding_32bit
;
4655 i
.dir_encoding
= dir_encoding_load
;
4659 i
.dir_encoding
= dir_encoding_store
;
4663 i
.vec_encoding
= vex_encoding_vex2
;
4667 i
.vec_encoding
= vex_encoding_vex3
;
4671 i
.vec_encoding
= vex_encoding_evex
;
4675 i
.rex_encoding
= TRUE
;
4679 i
.no_optimize
= TRUE
;
4687 /* Add prefix, checking for repeated prefixes. */
4688 switch (add_prefix (current_templates
->start
->base_opcode
))
4693 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4694 i
.notrack_prefix
= current_templates
->start
->name
;
4697 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4698 i
.hle_prefix
= current_templates
->start
->name
;
4699 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4700 i
.bnd_prefix
= current_templates
->start
->name
;
4702 i
.rep_prefix
= current_templates
->start
->name
;
4708 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4715 if (!current_templates
)
4717 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4718 Check if we should swap operand or force 32bit displacement in
4720 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4721 i
.dir_encoding
= dir_encoding_swap
;
4722 else if (mnem_p
- 3 == dot_p
4725 i
.disp_encoding
= disp_encoding_8bit
;
4726 else if (mnem_p
- 4 == dot_p
4730 i
.disp_encoding
= disp_encoding_32bit
;
4735 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4738 if (!current_templates
)
4741 if (mnem_p
> mnemonic
)
4743 /* See if we can get a match by trimming off a suffix. */
4746 case WORD_MNEM_SUFFIX
:
4747 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4748 i
.suffix
= SHORT_MNEM_SUFFIX
;
4751 case BYTE_MNEM_SUFFIX
:
4752 case QWORD_MNEM_SUFFIX
:
4753 i
.suffix
= mnem_p
[-1];
4755 current_templates
= (const templates
*) hash_find (op_hash
,
4758 case SHORT_MNEM_SUFFIX
:
4759 case LONG_MNEM_SUFFIX
:
4762 i
.suffix
= mnem_p
[-1];
4764 current_templates
= (const templates
*) hash_find (op_hash
,
4773 if (intel_float_operand (mnemonic
) == 1)
4774 i
.suffix
= SHORT_MNEM_SUFFIX
;
4776 i
.suffix
= LONG_MNEM_SUFFIX
;
4778 current_templates
= (const templates
*) hash_find (op_hash
,
4785 if (!current_templates
)
4787 as_bad (_("no such instruction: `%s'"), token_start
);
4792 if (current_templates
->start
->opcode_modifier
.jump
4793 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4795 /* Check for a branch hint. We allow ",pt" and ",pn" for
4796 predict taken and predict not taken respectively.
4797 I'm not sure that branch hints actually do anything on loop
4798 and jcxz insns (JumpByte) for current Pentium4 chips. They
4799 may work in the future and it doesn't hurt to accept them
4801 if (l
[0] == ',' && l
[1] == 'p')
4805 if (!add_prefix (DS_PREFIX_OPCODE
))
4809 else if (l
[2] == 'n')
4811 if (!add_prefix (CS_PREFIX_OPCODE
))
4817 /* Any other comma loses. */
4820 as_bad (_("invalid character %s in mnemonic"),
4821 output_invalid (*l
));
4825 /* Check if instruction is supported on specified architecture. */
4827 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4829 supported
|= cpu_flags_match (t
);
4830 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4832 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4833 as_warn (_("use .code16 to ensure correct addressing mode"));
4839 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4840 as_bad (flag_code
== CODE_64BIT
4841 ? _("`%s' is not supported in 64-bit mode")
4842 : _("`%s' is only supported in 64-bit mode"),
4843 current_templates
->start
->name
);
4845 as_bad (_("`%s' is not supported on `%s%s'"),
4846 current_templates
->start
->name
,
4847 cpu_arch_name
? cpu_arch_name
: default_arch
,
4848 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4854 parse_operands (char *l
, const char *mnemonic
)
4858 /* 1 if operand is pending after ','. */
4859 unsigned int expecting_operand
= 0;
4861 /* Non-zero if operand parens not balanced. */
4862 unsigned int paren_not_balanced
;
4864 while (*l
!= END_OF_INSN
)
4866 /* Skip optional white space before operand. */
4867 if (is_space_char (*l
))
4869 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4871 as_bad (_("invalid character %s before operand %d"),
4872 output_invalid (*l
),
4876 token_start
= l
; /* After white space. */
4877 paren_not_balanced
= 0;
4878 while (paren_not_balanced
|| *l
!= ',')
4880 if (*l
== END_OF_INSN
)
4882 if (paren_not_balanced
)
4885 as_bad (_("unbalanced parenthesis in operand %d."),
4888 as_bad (_("unbalanced brackets in operand %d."),
4893 break; /* we are done */
4895 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4897 as_bad (_("invalid character %s in operand %d"),
4898 output_invalid (*l
),
4905 ++paren_not_balanced
;
4907 --paren_not_balanced
;
4912 ++paren_not_balanced
;
4914 --paren_not_balanced
;
4918 if (l
!= token_start
)
4919 { /* Yes, we've read in another operand. */
4920 unsigned int operand_ok
;
4921 this_operand
= i
.operands
++;
4922 if (i
.operands
> MAX_OPERANDS
)
4924 as_bad (_("spurious operands; (%d operands/instruction max)"),
4928 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4929 /* Now parse operand adding info to 'i' as we go along. */
4930 END_STRING_AND_SAVE (l
);
4932 if (i
.mem_operands
> 1)
4934 as_bad (_("too many memory references for `%s'"),
4941 i386_intel_operand (token_start
,
4942 intel_float_operand (mnemonic
));
4944 operand_ok
= i386_att_operand (token_start
);
4946 RESTORE_END_STRING (l
);
4952 if (expecting_operand
)
4954 expecting_operand_after_comma
:
4955 as_bad (_("expecting operand after ','; got nothing"));
4960 as_bad (_("expecting operand before ','; got nothing"));
4965 /* Now *l must be either ',' or END_OF_INSN. */
4968 if (*++l
== END_OF_INSN
)
4970 /* Just skip it, if it's \n complain. */
4971 goto expecting_operand_after_comma
;
4973 expecting_operand
= 1;
4980 swap_2_operands (int xchg1
, int xchg2
)
4982 union i386_op temp_op
;
4983 i386_operand_type temp_type
;
4984 unsigned int temp_flags
;
4985 enum bfd_reloc_code_real temp_reloc
;
4987 temp_type
= i
.types
[xchg2
];
4988 i
.types
[xchg2
] = i
.types
[xchg1
];
4989 i
.types
[xchg1
] = temp_type
;
4991 temp_flags
= i
.flags
[xchg2
];
4992 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4993 i
.flags
[xchg1
] = temp_flags
;
4995 temp_op
= i
.op
[xchg2
];
4996 i
.op
[xchg2
] = i
.op
[xchg1
];
4997 i
.op
[xchg1
] = temp_op
;
4999 temp_reloc
= i
.reloc
[xchg2
];
5000 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5001 i
.reloc
[xchg1
] = temp_reloc
;
5005 if (i
.mask
->operand
== xchg1
)
5006 i
.mask
->operand
= xchg2
;
5007 else if (i
.mask
->operand
== xchg2
)
5008 i
.mask
->operand
= xchg1
;
5012 if (i
.broadcast
->operand
== xchg1
)
5013 i
.broadcast
->operand
= xchg2
;
5014 else if (i
.broadcast
->operand
== xchg2
)
5015 i
.broadcast
->operand
= xchg1
;
5019 if (i
.rounding
->operand
== xchg1
)
5020 i
.rounding
->operand
= xchg2
;
5021 else if (i
.rounding
->operand
== xchg2
)
5022 i
.rounding
->operand
= xchg1
;
5027 swap_operands (void)
5033 swap_2_operands (1, i
.operands
- 2);
5037 swap_2_operands (0, i
.operands
- 1);
5043 if (i
.mem_operands
== 2)
5045 const seg_entry
*temp_seg
;
5046 temp_seg
= i
.seg
[0];
5047 i
.seg
[0] = i
.seg
[1];
5048 i
.seg
[1] = temp_seg
;
5052 /* Try to ensure constant immediates are represented in the smallest
5057 char guess_suffix
= 0;
5061 guess_suffix
= i
.suffix
;
5062 else if (i
.reg_operands
)
5064 /* Figure out a suffix from the last register operand specified.
5065 We can't do this properly yet, ie. excluding InOutPortReg,
5066 but the following works for instructions with immediates.
5067 In any case, we can't set i.suffix yet. */
5068 for (op
= i
.operands
; --op
>= 0;)
5069 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5071 guess_suffix
= BYTE_MNEM_SUFFIX
;
5074 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5076 guess_suffix
= WORD_MNEM_SUFFIX
;
5079 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5081 guess_suffix
= LONG_MNEM_SUFFIX
;
5084 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5086 guess_suffix
= QWORD_MNEM_SUFFIX
;
5090 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5091 guess_suffix
= WORD_MNEM_SUFFIX
;
5093 for (op
= i
.operands
; --op
>= 0;)
5094 if (operand_type_check (i
.types
[op
], imm
))
5096 switch (i
.op
[op
].imms
->X_op
)
5099 /* If a suffix is given, this operand may be shortened. */
5100 switch (guess_suffix
)
5102 case LONG_MNEM_SUFFIX
:
5103 i
.types
[op
].bitfield
.imm32
= 1;
5104 i
.types
[op
].bitfield
.imm64
= 1;
5106 case WORD_MNEM_SUFFIX
:
5107 i
.types
[op
].bitfield
.imm16
= 1;
5108 i
.types
[op
].bitfield
.imm32
= 1;
5109 i
.types
[op
].bitfield
.imm32s
= 1;
5110 i
.types
[op
].bitfield
.imm64
= 1;
5112 case BYTE_MNEM_SUFFIX
:
5113 i
.types
[op
].bitfield
.imm8
= 1;
5114 i
.types
[op
].bitfield
.imm8s
= 1;
5115 i
.types
[op
].bitfield
.imm16
= 1;
5116 i
.types
[op
].bitfield
.imm32
= 1;
5117 i
.types
[op
].bitfield
.imm32s
= 1;
5118 i
.types
[op
].bitfield
.imm64
= 1;
5122 /* If this operand is at most 16 bits, convert it
5123 to a signed 16 bit number before trying to see
5124 whether it will fit in an even smaller size.
5125 This allows a 16-bit operand such as $0xffe0 to
5126 be recognised as within Imm8S range. */
5127 if ((i
.types
[op
].bitfield
.imm16
)
5128 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5130 i
.op
[op
].imms
->X_add_number
=
5131 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5134 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5135 if ((i
.types
[op
].bitfield
.imm32
)
5136 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5139 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5140 ^ ((offsetT
) 1 << 31))
5141 - ((offsetT
) 1 << 31));
5145 = operand_type_or (i
.types
[op
],
5146 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5148 /* We must avoid matching of Imm32 templates when 64bit
5149 only immediate is available. */
5150 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5151 i
.types
[op
].bitfield
.imm32
= 0;
5158 /* Symbols and expressions. */
5160 /* Convert symbolic operand to proper sizes for matching, but don't
5161 prevent matching a set of insns that only supports sizes other
5162 than those matching the insn suffix. */
5164 i386_operand_type mask
, allowed
;
5165 const insn_template
*t
;
5167 operand_type_set (&mask
, 0);
5168 operand_type_set (&allowed
, 0);
5170 for (t
= current_templates
->start
;
5171 t
< current_templates
->end
;
5173 allowed
= operand_type_or (allowed
,
5174 t
->operand_types
[op
]);
5175 switch (guess_suffix
)
5177 case QWORD_MNEM_SUFFIX
:
5178 mask
.bitfield
.imm64
= 1;
5179 mask
.bitfield
.imm32s
= 1;
5181 case LONG_MNEM_SUFFIX
:
5182 mask
.bitfield
.imm32
= 1;
5184 case WORD_MNEM_SUFFIX
:
5185 mask
.bitfield
.imm16
= 1;
5187 case BYTE_MNEM_SUFFIX
:
5188 mask
.bitfield
.imm8
= 1;
5193 allowed
= operand_type_and (mask
, allowed
);
5194 if (!operand_type_all_zero (&allowed
))
5195 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5202 /* Try to use the smallest displacement type too. */
5204 optimize_disp (void)
5208 for (op
= i
.operands
; --op
>= 0;)
5209 if (operand_type_check (i
.types
[op
], disp
))
5211 if (i
.op
[op
].disps
->X_op
== O_constant
)
5213 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5215 if (i
.types
[op
].bitfield
.disp16
5216 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5218 /* If this operand is at most 16 bits, convert
5219 to a signed 16 bit number and don't use 64bit
5221 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5222 i
.types
[op
].bitfield
.disp64
= 0;
5225 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5226 if (i
.types
[op
].bitfield
.disp32
5227 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5229 /* If this operand is at most 32 bits, convert
5230 to a signed 32 bit number and don't use 64bit
5232 op_disp
&= (((offsetT
) 2 << 31) - 1);
5233 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5234 i
.types
[op
].bitfield
.disp64
= 0;
5237 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5239 i
.types
[op
].bitfield
.disp8
= 0;
5240 i
.types
[op
].bitfield
.disp16
= 0;
5241 i
.types
[op
].bitfield
.disp32
= 0;
5242 i
.types
[op
].bitfield
.disp32s
= 0;
5243 i
.types
[op
].bitfield
.disp64
= 0;
5247 else if (flag_code
== CODE_64BIT
)
5249 if (fits_in_signed_long (op_disp
))
5251 i
.types
[op
].bitfield
.disp64
= 0;
5252 i
.types
[op
].bitfield
.disp32s
= 1;
5254 if (i
.prefix
[ADDR_PREFIX
]
5255 && fits_in_unsigned_long (op_disp
))
5256 i
.types
[op
].bitfield
.disp32
= 1;
5258 if ((i
.types
[op
].bitfield
.disp32
5259 || i
.types
[op
].bitfield
.disp32s
5260 || i
.types
[op
].bitfield
.disp16
)
5261 && fits_in_disp8 (op_disp
))
5262 i
.types
[op
].bitfield
.disp8
= 1;
5264 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5265 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5267 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5268 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5269 i
.types
[op
].bitfield
.disp8
= 0;
5270 i
.types
[op
].bitfield
.disp16
= 0;
5271 i
.types
[op
].bitfield
.disp32
= 0;
5272 i
.types
[op
].bitfield
.disp32s
= 0;
5273 i
.types
[op
].bitfield
.disp64
= 0;
5276 /* We only support 64bit displacement on constants. */
5277 i
.types
[op
].bitfield
.disp64
= 0;
5281 /* Return 1 if there is a match in broadcast bytes between operand
5282 GIVEN and instruction template T. */
5285 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5287 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5288 && i
.types
[given
].bitfield
.byte
)
5289 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5290 && i
.types
[given
].bitfield
.word
)
5291 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5292 && i
.types
[given
].bitfield
.dword
)
5293 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5294 && i
.types
[given
].bitfield
.qword
));
5297 /* Check if operands are valid for the instruction. */
5300 check_VecOperands (const insn_template
*t
)
5304 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5306 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5307 any one operand are implicity requiring AVX512VL support if the actual
5308 operand size is YMMword or XMMword. Since this function runs after
5309 template matching, there's no need to check for YMMword/XMMword in
5311 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5312 if (!cpu_flags_all_zero (&cpu
)
5313 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5314 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5316 for (op
= 0; op
< t
->operands
; ++op
)
5318 if (t
->operand_types
[op
].bitfield
.zmmword
5319 && (i
.types
[op
].bitfield
.ymmword
5320 || i
.types
[op
].bitfield
.xmmword
))
5322 i
.error
= unsupported
;
5328 /* Without VSIB byte, we can't have a vector register for index. */
5329 if (!t
->opcode_modifier
.vecsib
5331 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5332 || i
.index_reg
->reg_type
.bitfield
.ymmword
5333 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5335 i
.error
= unsupported_vector_index_register
;
5339 /* Check if default mask is allowed. */
5340 if (t
->opcode_modifier
.nodefmask
5341 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5343 i
.error
= no_default_mask
;
5347 /* For VSIB byte, we need a vector register for index, and all vector
5348 registers must be distinct. */
5349 if (t
->opcode_modifier
.vecsib
)
5352 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5353 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5354 || (t
->opcode_modifier
.vecsib
== VecSIB256
5355 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5356 || (t
->opcode_modifier
.vecsib
== VecSIB512
5357 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5359 i
.error
= invalid_vsib_address
;
5363 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5364 if (i
.reg_operands
== 2 && !i
.mask
)
5366 gas_assert (i
.types
[0].bitfield
.regsimd
);
5367 gas_assert (i
.types
[0].bitfield
.xmmword
5368 || i
.types
[0].bitfield
.ymmword
);
5369 gas_assert (i
.types
[2].bitfield
.regsimd
);
5370 gas_assert (i
.types
[2].bitfield
.xmmword
5371 || i
.types
[2].bitfield
.ymmword
);
5372 if (operand_check
== check_none
)
5374 if (register_number (i
.op
[0].regs
)
5375 != register_number (i
.index_reg
)
5376 && register_number (i
.op
[2].regs
)
5377 != register_number (i
.index_reg
)
5378 && register_number (i
.op
[0].regs
)
5379 != register_number (i
.op
[2].regs
))
5381 if (operand_check
== check_error
)
5383 i
.error
= invalid_vector_register_set
;
5386 as_warn (_("mask, index, and destination registers should be distinct"));
5388 else if (i
.reg_operands
== 1 && i
.mask
)
5390 if (i
.types
[1].bitfield
.regsimd
5391 && (i
.types
[1].bitfield
.xmmword
5392 || i
.types
[1].bitfield
.ymmword
5393 || i
.types
[1].bitfield
.zmmword
)
5394 && (register_number (i
.op
[1].regs
)
5395 == register_number (i
.index_reg
)))
5397 if (operand_check
== check_error
)
5399 i
.error
= invalid_vector_register_set
;
5402 if (operand_check
!= check_none
)
5403 as_warn (_("index and destination registers should be distinct"));
5408 /* Check if broadcast is supported by the instruction and is applied
5409 to the memory operand. */
5412 i386_operand_type type
, overlap
;
5414 /* Check if specified broadcast is supported in this instruction,
5415 and its broadcast bytes match the memory operand. */
5416 op
= i
.broadcast
->operand
;
5417 if (!t
->opcode_modifier
.broadcast
5418 || !(i
.flags
[op
] & Operand_Mem
)
5419 || (!i
.types
[op
].bitfield
.unspecified
5420 && !match_broadcast_size (t
, op
)))
5423 i
.error
= unsupported_broadcast
;
5427 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5428 * i
.broadcast
->type
);
5429 operand_type_set (&type
, 0);
5430 switch (i
.broadcast
->bytes
)
5433 type
.bitfield
.word
= 1;
5436 type
.bitfield
.dword
= 1;
5439 type
.bitfield
.qword
= 1;
5442 type
.bitfield
.xmmword
= 1;
5445 type
.bitfield
.ymmword
= 1;
5448 type
.bitfield
.zmmword
= 1;
5454 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5455 if (operand_type_all_zero (&overlap
))
5458 if (t
->opcode_modifier
.checkregsize
)
5462 type
.bitfield
.baseindex
= 1;
5463 for (j
= 0; j
< i
.operands
; ++j
)
5466 && !operand_type_register_match(i
.types
[j
],
5467 t
->operand_types
[j
],
5469 t
->operand_types
[op
]))
5474 /* If broadcast is supported in this instruction, we need to check if
5475 operand of one-element size isn't specified without broadcast. */
5476 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5478 /* Find memory operand. */
5479 for (op
= 0; op
< i
.operands
; op
++)
5480 if (i
.flags
[op
] & Operand_Mem
)
5482 gas_assert (op
< i
.operands
);
5483 /* Check size of the memory operand. */
5484 if (match_broadcast_size (t
, op
))
5486 i
.error
= broadcast_needed
;
5491 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5493 /* Check if requested masking is supported. */
5496 switch (t
->opcode_modifier
.masking
)
5500 case MERGING_MASKING
:
5501 if (i
.mask
->zeroing
)
5504 i
.error
= unsupported_masking
;
5508 case DYNAMIC_MASKING
:
5509 /* Memory destinations allow only merging masking. */
5510 if (i
.mask
->zeroing
&& i
.mem_operands
)
5512 /* Find memory operand. */
5513 for (op
= 0; op
< i
.operands
; op
++)
5514 if (i
.flags
[op
] & Operand_Mem
)
5516 gas_assert (op
< i
.operands
);
5517 if (op
== i
.operands
- 1)
5519 i
.error
= unsupported_masking
;
5529 /* Check if masking is applied to dest operand. */
5530 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5532 i
.error
= mask_not_on_destination
;
5539 if (!t
->opcode_modifier
.sae
5540 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5542 i
.error
= unsupported_rc_sae
;
5545 /* If the instruction has several immediate operands and one of
5546 them is rounding, the rounding operand should be the last
5547 immediate operand. */
5548 if (i
.imm_operands
> 1
5549 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5551 i
.error
= rc_sae_operand_not_last_imm
;
5556 /* Check vector Disp8 operand. */
5557 if (t
->opcode_modifier
.disp8memshift
5558 && i
.disp_encoding
!= disp_encoding_32bit
)
5561 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5562 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5563 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5566 const i386_operand_type
*type
= NULL
;
5569 for (op
= 0; op
< i
.operands
; op
++)
5570 if (i
.flags
[op
] & Operand_Mem
)
5572 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5573 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5574 else if (t
->operand_types
[op
].bitfield
.xmmword
5575 + t
->operand_types
[op
].bitfield
.ymmword
5576 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5577 type
= &t
->operand_types
[op
];
5578 else if (!i
.types
[op
].bitfield
.unspecified
)
5579 type
= &i
.types
[op
];
5581 else if (i
.types
[op
].bitfield
.regsimd
5582 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5584 if (i
.types
[op
].bitfield
.zmmword
)
5586 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5588 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5594 if (type
->bitfield
.zmmword
)
5596 else if (type
->bitfield
.ymmword
)
5598 else if (type
->bitfield
.xmmword
)
5602 /* For the check in fits_in_disp8(). */
5603 if (i
.memshift
== 0)
5607 for (op
= 0; op
< i
.operands
; op
++)
5608 if (operand_type_check (i
.types
[op
], disp
)
5609 && i
.op
[op
].disps
->X_op
== O_constant
)
5611 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5613 i
.types
[op
].bitfield
.disp8
= 1;
5616 i
.types
[op
].bitfield
.disp8
= 0;
5625 /* Check if operands are valid for the instruction. Update VEX
5629 VEX_check_operands (const insn_template
*t
)
5631 if (i
.vec_encoding
== vex_encoding_evex
)
5633 /* This instruction must be encoded with EVEX prefix. */
5634 if (!is_evex_encoding (t
))
5636 i
.error
= unsupported
;
5642 if (!t
->opcode_modifier
.vex
)
5644 /* This instruction template doesn't have VEX prefix. */
5645 if (i
.vec_encoding
!= vex_encoding_default
)
5647 i
.error
= unsupported
;
5653 /* Check the special Imm4 cases; must be the first operand. */
5654 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5656 if (i
.op
[0].imms
->X_op
!= O_constant
5657 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5663 /* Turn off Imm<N> so that update_imm won't complain. */
5664 operand_type_set (&i
.types
[0], 0);
5670 static const insn_template
*
5671 match_template (char mnem_suffix
)
5673 /* Points to template once we've found it. */
5674 const insn_template
*t
;
5675 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5676 i386_operand_type overlap4
;
5677 unsigned int found_reverse_match
;
5678 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5679 i386_operand_type operand_types
[MAX_OPERANDS
];
5680 int addr_prefix_disp
;
5682 unsigned int found_cpu_match
, size_match
;
5683 unsigned int check_register
;
5684 enum i386_error specific_error
= 0;
5686 #if MAX_OPERANDS != 5
5687 # error "MAX_OPERANDS must be 5."
5690 found_reverse_match
= 0;
5691 addr_prefix_disp
= -1;
5693 memset (&suffix_check
, 0, sizeof (suffix_check
));
5694 if (intel_syntax
&& i
.broadcast
)
5696 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5697 suffix_check
.no_bsuf
= 1;
5698 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5699 suffix_check
.no_wsuf
= 1;
5700 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5701 suffix_check
.no_ssuf
= 1;
5702 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5703 suffix_check
.no_lsuf
= 1;
5704 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5705 suffix_check
.no_qsuf
= 1;
5706 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5707 suffix_check
.no_ldsuf
= 1;
5709 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5712 switch (mnem_suffix
)
5714 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5715 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5716 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5717 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5718 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5722 /* Must have right number of operands. */
5723 i
.error
= number_of_operands_mismatch
;
5725 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5727 addr_prefix_disp
= -1;
5728 found_reverse_match
= 0;
5730 if (i
.operands
!= t
->operands
)
5733 /* Check processor support. */
5734 i
.error
= unsupported
;
5735 found_cpu_match
= (cpu_flags_match (t
)
5736 == CPU_FLAGS_PERFECT_MATCH
);
5737 if (!found_cpu_match
)
5740 /* Check AT&T mnemonic. */
5741 i
.error
= unsupported_with_intel_mnemonic
;
5742 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5745 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5746 i
.error
= unsupported_syntax
;
5747 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5748 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5749 || (intel64
&& t
->opcode_modifier
.amd64
)
5750 || (!intel64
&& t
->opcode_modifier
.intel64
))
5753 /* Check the suffix, except for some instructions in intel mode. */
5754 i
.error
= invalid_instruction_suffix
;
5755 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5756 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5757 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5758 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5759 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5760 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5761 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5763 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5764 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5765 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5766 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5767 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5768 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5769 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5772 size_match
= operand_size_match (t
);
5776 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5777 operand_types
[j
] = t
->operand_types
[j
];
5779 /* In general, don't allow 64-bit operands in 32-bit mode. */
5780 if (i
.suffix
== QWORD_MNEM_SUFFIX
5781 && flag_code
!= CODE_64BIT
5783 ? (!t
->opcode_modifier
.ignoresize
5784 && !t
->opcode_modifier
.broadcast
5785 && !intel_float_operand (t
->name
))
5786 : intel_float_operand (t
->name
) != 2)
5787 && ((!operand_types
[0].bitfield
.regmmx
5788 && !operand_types
[0].bitfield
.regsimd
)
5789 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5790 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5791 && (t
->base_opcode
!= 0x0fc7
5792 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5795 /* In general, don't allow 32-bit operands on pre-386. */
5796 else if (i
.suffix
== LONG_MNEM_SUFFIX
5797 && !cpu_arch_flags
.bitfield
.cpui386
5799 ? (!t
->opcode_modifier
.ignoresize
5800 && !intel_float_operand (t
->name
))
5801 : intel_float_operand (t
->name
) != 2)
5802 && ((!operand_types
[0].bitfield
.regmmx
5803 && !operand_types
[0].bitfield
.regsimd
)
5804 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5805 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5808 /* Do not verify operands when there are none. */
5812 /* We've found a match; break out of loop. */
5816 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5817 into Disp32/Disp16/Disp32 operand. */
5818 if (i
.prefix
[ADDR_PREFIX
] != 0)
5820 /* There should be only one Disp operand. */
5824 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5826 if (operand_types
[j
].bitfield
.disp16
)
5828 addr_prefix_disp
= j
;
5829 operand_types
[j
].bitfield
.disp32
= 1;
5830 operand_types
[j
].bitfield
.disp16
= 0;
5836 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5838 if (operand_types
[j
].bitfield
.disp32
)
5840 addr_prefix_disp
= j
;
5841 operand_types
[j
].bitfield
.disp32
= 0;
5842 operand_types
[j
].bitfield
.disp16
= 1;
5848 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5850 if (operand_types
[j
].bitfield
.disp64
)
5852 addr_prefix_disp
= j
;
5853 operand_types
[j
].bitfield
.disp64
= 0;
5854 operand_types
[j
].bitfield
.disp32
= 1;
5862 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5863 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5866 /* We check register size if needed. */
5867 if (t
->opcode_modifier
.checkregsize
)
5869 check_register
= (1 << t
->operands
) - 1;
5871 check_register
&= ~(1 << i
.broadcast
->operand
);
5876 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5877 switch (t
->operands
)
5880 if (!operand_type_match (overlap0
, i
.types
[0]))
5884 /* xchg %eax, %eax is a special case. It is an alias for nop
5885 only in 32bit mode and we can use opcode 0x90. In 64bit
5886 mode, we can't use 0x90 for xchg %eax, %eax since it should
5887 zero-extend %eax to %rax. */
5888 if (flag_code
== CODE_64BIT
5889 && t
->base_opcode
== 0x90
5890 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5891 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5893 /* xrelease mov %eax, <disp> is another special case. It must not
5894 match the accumulator-only encoding of mov. */
5895 if (flag_code
!= CODE_64BIT
5897 && t
->base_opcode
== 0xa0
5898 && i
.types
[0].bitfield
.acc
5899 && (i
.flags
[1] & Operand_Mem
))
5904 if (!(size_match
& MATCH_STRAIGHT
))
5906 /* Reverse direction of operands if swapping is possible in the first
5907 place (operands need to be symmetric) and
5908 - the load form is requested, and the template is a store form,
5909 - the store form is requested, and the template is a load form,
5910 - the non-default (swapped) form is requested. */
5911 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5912 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5913 && !operand_type_all_zero (&overlap1
))
5914 switch (i
.dir_encoding
)
5916 case dir_encoding_load
:
5917 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5918 || t
->opcode_modifier
.regmem
)
5922 case dir_encoding_store
:
5923 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5924 && !t
->opcode_modifier
.regmem
)
5928 case dir_encoding_swap
:
5931 case dir_encoding_default
:
5934 /* If we want store form, we skip the current load. */
5935 if ((i
.dir_encoding
== dir_encoding_store
5936 || i
.dir_encoding
== dir_encoding_swap
)
5937 && i
.mem_operands
== 0
5938 && t
->opcode_modifier
.load
)
5943 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5944 if (!operand_type_match (overlap0
, i
.types
[0])
5945 || !operand_type_match (overlap1
, i
.types
[1])
5946 || ((check_register
& 3) == 3
5947 && !operand_type_register_match (i
.types
[0],
5952 /* Check if other direction is valid ... */
5953 if (!t
->opcode_modifier
.d
)
5957 if (!(size_match
& MATCH_REVERSE
))
5959 /* Try reversing direction of operands. */
5960 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5961 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5962 if (!operand_type_match (overlap0
, i
.types
[0])
5963 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5965 && !operand_type_register_match (i
.types
[0],
5966 operand_types
[i
.operands
- 1],
5967 i
.types
[i
.operands
- 1],
5970 /* Does not match either direction. */
5973 /* found_reverse_match holds which of D or FloatR
5975 if (!t
->opcode_modifier
.d
)
5976 found_reverse_match
= 0;
5977 else if (operand_types
[0].bitfield
.tbyte
)
5978 found_reverse_match
= Opcode_FloatD
;
5979 else if (operand_types
[0].bitfield
.xmmword
5980 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5981 || operand_types
[0].bitfield
.regmmx
5982 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5983 || is_any_vex_encoding(t
))
5984 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5985 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5987 found_reverse_match
= Opcode_D
;
5988 if (t
->opcode_modifier
.floatr
)
5989 found_reverse_match
|= Opcode_FloatR
;
5993 /* Found a forward 2 operand match here. */
5994 switch (t
->operands
)
5997 overlap4
= operand_type_and (i
.types
[4],
6001 overlap3
= operand_type_and (i
.types
[3],
6005 overlap2
= operand_type_and (i
.types
[2],
6010 switch (t
->operands
)
6013 if (!operand_type_match (overlap4
, i
.types
[4])
6014 || !operand_type_register_match (i
.types
[3],
6021 if (!operand_type_match (overlap3
, i
.types
[3])
6022 || ((check_register
& 0xa) == 0xa
6023 && !operand_type_register_match (i
.types
[1],
6027 || ((check_register
& 0xc) == 0xc
6028 && !operand_type_register_match (i
.types
[2],
6035 /* Here we make use of the fact that there are no
6036 reverse match 3 operand instructions. */
6037 if (!operand_type_match (overlap2
, i
.types
[2])
6038 || ((check_register
& 5) == 5
6039 && !operand_type_register_match (i
.types
[0],
6043 || ((check_register
& 6) == 6
6044 && !operand_type_register_match (i
.types
[1],
6052 /* Found either forward/reverse 2, 3 or 4 operand match here:
6053 slip through to break. */
6055 if (!found_cpu_match
)
6058 /* Check if vector and VEX operands are valid. */
6059 if (check_VecOperands (t
) || VEX_check_operands (t
))
6061 specific_error
= i
.error
;
6065 /* We've found a match; break out of loop. */
6069 if (t
== current_templates
->end
)
6071 /* We found no match. */
6072 const char *err_msg
;
6073 switch (specific_error
? specific_error
: i
.error
)
6077 case operand_size_mismatch
:
6078 err_msg
= _("operand size mismatch");
6080 case operand_type_mismatch
:
6081 err_msg
= _("operand type mismatch");
6083 case register_type_mismatch
:
6084 err_msg
= _("register type mismatch");
6086 case number_of_operands_mismatch
:
6087 err_msg
= _("number of operands mismatch");
6089 case invalid_instruction_suffix
:
6090 err_msg
= _("invalid instruction suffix");
6093 err_msg
= _("constant doesn't fit in 4 bits");
6095 case unsupported_with_intel_mnemonic
:
6096 err_msg
= _("unsupported with Intel mnemonic");
6098 case unsupported_syntax
:
6099 err_msg
= _("unsupported syntax");
6102 as_bad (_("unsupported instruction `%s'"),
6103 current_templates
->start
->name
);
6105 case invalid_vsib_address
:
6106 err_msg
= _("invalid VSIB address");
6108 case invalid_vector_register_set
:
6109 err_msg
= _("mask, index, and destination registers must be distinct");
6111 case unsupported_vector_index_register
:
6112 err_msg
= _("unsupported vector index register");
6114 case unsupported_broadcast
:
6115 err_msg
= _("unsupported broadcast");
6117 case broadcast_needed
:
6118 err_msg
= _("broadcast is needed for operand of such type");
6120 case unsupported_masking
:
6121 err_msg
= _("unsupported masking");
6123 case mask_not_on_destination
:
6124 err_msg
= _("mask not on destination operand");
6126 case no_default_mask
:
6127 err_msg
= _("default mask isn't allowed");
6129 case unsupported_rc_sae
:
6130 err_msg
= _("unsupported static rounding/sae");
6132 case rc_sae_operand_not_last_imm
:
6134 err_msg
= _("RC/SAE operand must precede immediate operands");
6136 err_msg
= _("RC/SAE operand must follow immediate operands");
6138 case invalid_register_operand
:
6139 err_msg
= _("invalid register operand");
6142 as_bad (_("%s for `%s'"), err_msg
,
6143 current_templates
->start
->name
);
6147 if (!quiet_warnings
)
6150 && (i
.types
[0].bitfield
.jumpabsolute
6151 != operand_types
[0].bitfield
.jumpabsolute
))
6153 as_warn (_("indirect %s without `*'"), t
->name
);
6156 if (t
->opcode_modifier
.isprefix
6157 && t
->opcode_modifier
.ignoresize
)
6159 /* Warn them that a data or address size prefix doesn't
6160 affect assembly of the next line of code. */
6161 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6165 /* Copy the template we found. */
6168 if (addr_prefix_disp
!= -1)
6169 i
.tm
.operand_types
[addr_prefix_disp
]
6170 = operand_types
[addr_prefix_disp
];
6172 if (found_reverse_match
)
6174 /* If we found a reverse match we must alter the opcode direction
6175 bit and clear/flip the regmem modifier one. found_reverse_match
6176 holds bits to change (different for int & float insns). */
6178 i
.tm
.base_opcode
^= found_reverse_match
;
6180 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6181 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6183 /* Certain SIMD insns have their load forms specified in the opcode
6184 table, and hence we need to _set_ RegMem instead of clearing it.
6185 We need to avoid setting the bit though on insns like KMOVW. */
6186 i
.tm
.opcode_modifier
.regmem
6187 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6188 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6189 && !i
.tm
.opcode_modifier
.regmem
;
6198 unsigned int mem_op
= i
.flags
[0] & Operand_Mem
? 0 : 1;
6200 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6202 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6204 as_bad (_("`%s' operand %d must use `%ses' segment"),
6206 intel_syntax
? i
.tm
.operands
- mem_op
: mem_op
+ 1,
6210 /* There's only ever one segment override allowed per instruction.
6211 This instruction possibly has a legal segment override on the
6212 second operand, so copy the segment to where non-string
6213 instructions store it, allowing common code. */
6214 i
.seg
[0] = i
.seg
[1];
6216 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6218 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6220 as_bad (_("`%s' operand %d must use `%ses' segment"),
6222 intel_syntax
? i
.tm
.operands
- mem_op
- 1 : mem_op
+ 2,
6231 process_suffix (void)
6233 /* If matched instruction specifies an explicit instruction mnemonic
6235 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6236 i
.suffix
= WORD_MNEM_SUFFIX
;
6237 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6238 i
.suffix
= LONG_MNEM_SUFFIX
;
6239 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6240 i
.suffix
= QWORD_MNEM_SUFFIX
;
6241 else if (i
.reg_operands
)
6243 /* If there's no instruction mnemonic suffix we try to invent one
6244 based on register operands. */
6247 /* We take i.suffix from the last register operand specified,
6248 Destination register type is more significant than source
6249 register type. crc32 in SSE4.2 prefers source register
6251 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6253 if (i
.types
[0].bitfield
.byte
)
6254 i
.suffix
= BYTE_MNEM_SUFFIX
;
6255 else if (i
.types
[0].bitfield
.word
)
6256 i
.suffix
= WORD_MNEM_SUFFIX
;
6257 else if (i
.types
[0].bitfield
.dword
)
6258 i
.suffix
= LONG_MNEM_SUFFIX
;
6259 else if (i
.types
[0].bitfield
.qword
)
6260 i
.suffix
= QWORD_MNEM_SUFFIX
;
6267 if (i
.tm
.base_opcode
== 0xf20f38f0)
6269 /* We have to know the operand size for crc32. */
6270 as_bad (_("ambiguous memory operand size for `%s`"),
6275 for (op
= i
.operands
; --op
>= 0;)
6276 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6277 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6279 if (!i
.types
[op
].bitfield
.reg
)
6281 if (i
.types
[op
].bitfield
.byte
)
6282 i
.suffix
= BYTE_MNEM_SUFFIX
;
6283 else if (i
.types
[op
].bitfield
.word
)
6284 i
.suffix
= WORD_MNEM_SUFFIX
;
6285 else if (i
.types
[op
].bitfield
.dword
)
6286 i
.suffix
= LONG_MNEM_SUFFIX
;
6287 else if (i
.types
[op
].bitfield
.qword
)
6288 i
.suffix
= QWORD_MNEM_SUFFIX
;
6295 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6298 && i
.tm
.opcode_modifier
.ignoresize
6299 && i
.tm
.opcode_modifier
.no_bsuf
)
6301 else if (!check_byte_reg ())
6304 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6307 && i
.tm
.opcode_modifier
.ignoresize
6308 && i
.tm
.opcode_modifier
.no_lsuf
6309 && !i
.tm
.opcode_modifier
.todword
6310 && !i
.tm
.opcode_modifier
.toqword
)
6312 else if (!check_long_reg ())
6315 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6318 && i
.tm
.opcode_modifier
.ignoresize
6319 && i
.tm
.opcode_modifier
.no_qsuf
6320 && !i
.tm
.opcode_modifier
.todword
6321 && !i
.tm
.opcode_modifier
.toqword
)
6323 else if (!check_qword_reg ())
6326 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6329 && i
.tm
.opcode_modifier
.ignoresize
6330 && i
.tm
.opcode_modifier
.no_wsuf
)
6332 else if (!check_word_reg ())
6335 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6336 /* Do nothing if the instruction is going to ignore the prefix. */
6341 else if (i
.tm
.opcode_modifier
.defaultsize
6343 /* exclude fldenv/frstor/fsave/fstenv */
6344 && i
.tm
.opcode_modifier
.no_ssuf
)
6346 if (stackop_size
== LONG_MNEM_SUFFIX
6347 && i
.tm
.base_opcode
== 0xcf)
6349 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6350 .code16gcc directive to support 16-bit mode with
6351 32-bit address. For IRET without a suffix, generate
6352 16-bit IRET (opcode 0xcf) to return from an interrupt
6354 i
.suffix
= WORD_MNEM_SUFFIX
;
6355 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6358 i
.suffix
= stackop_size
;
6360 else if (intel_syntax
6362 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6363 || i
.tm
.opcode_modifier
.jumpbyte
6364 || i
.tm
.opcode_modifier
.jumpintersegment
6365 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6366 && i
.tm
.extension_opcode
<= 3)))
6371 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6373 i
.suffix
= QWORD_MNEM_SUFFIX
;
6378 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6379 i
.suffix
= LONG_MNEM_SUFFIX
;
6382 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6383 i
.suffix
= WORD_MNEM_SUFFIX
;
6392 if (i
.tm
.opcode_modifier
.w
)
6394 as_bad (_("no instruction mnemonic suffix given and "
6395 "no register operands; can't size instruction"));
6401 unsigned int suffixes
;
6403 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6404 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6406 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6408 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6410 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6412 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6415 /* There are more than suffix matches. */
6416 if (i
.tm
.opcode_modifier
.w
6417 || ((suffixes
& (suffixes
- 1))
6418 && !i
.tm
.opcode_modifier
.defaultsize
6419 && !i
.tm
.opcode_modifier
.ignoresize
))
6421 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6427 /* Change the opcode based on the operand size given by i.suffix. */
6430 /* Size floating point instruction. */
6431 case LONG_MNEM_SUFFIX
:
6432 if (i
.tm
.opcode_modifier
.floatmf
)
6434 i
.tm
.base_opcode
^= 4;
6438 case WORD_MNEM_SUFFIX
:
6439 case QWORD_MNEM_SUFFIX
:
6440 /* It's not a byte, select word/dword operation. */
6441 if (i
.tm
.opcode_modifier
.w
)
6443 if (i
.tm
.opcode_modifier
.shortform
)
6444 i
.tm
.base_opcode
|= 8;
6446 i
.tm
.base_opcode
|= 1;
6449 case SHORT_MNEM_SUFFIX
:
6450 /* Now select between word & dword operations via the operand
6451 size prefix, except for instructions that will ignore this
6453 if (i
.reg_operands
> 0
6454 && i
.types
[0].bitfield
.reg
6455 && i
.tm
.opcode_modifier
.addrprefixopreg
6456 && (i
.tm
.opcode_modifier
.immext
6457 || i
.operands
== 1))
6459 /* The address size override prefix changes the size of the
6461 if ((flag_code
== CODE_32BIT
6462 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6463 || (flag_code
!= CODE_32BIT
6464 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6465 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6468 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6469 && !i
.tm
.opcode_modifier
.ignoresize
6470 && !i
.tm
.opcode_modifier
.floatmf
6471 && !is_any_vex_encoding (&i
.tm
)
6472 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6473 || (flag_code
== CODE_64BIT
6474 && i
.tm
.opcode_modifier
.jumpbyte
)))
6476 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6478 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6479 prefix
= ADDR_PREFIX_OPCODE
;
6481 if (!add_prefix (prefix
))
6485 /* Set mode64 for an operand. */
6486 if (i
.suffix
== QWORD_MNEM_SUFFIX
6487 && flag_code
== CODE_64BIT
6488 && !i
.tm
.opcode_modifier
.norex64
6489 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6491 && ! (i
.operands
== 2
6492 && i
.tm
.base_opcode
== 0x90
6493 && i
.tm
.extension_opcode
== None
6494 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6495 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6501 if (i
.reg_operands
!= 0
6503 && i
.tm
.opcode_modifier
.addrprefixopreg
6504 && !i
.tm
.opcode_modifier
.immext
)
6506 /* Check invalid register operand when the address size override
6507 prefix changes the size of register operands. */
6509 enum { need_word
, need_dword
, need_qword
} need
;
6511 if (flag_code
== CODE_32BIT
)
6512 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6515 if (i
.prefix
[ADDR_PREFIX
])
6518 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6521 for (op
= 0; op
< i
.operands
; op
++)
6522 if (i
.types
[op
].bitfield
.reg
6523 && ((need
== need_word
6524 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6525 || (need
== need_dword
6526 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6527 || (need
== need_qword
6528 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6530 as_bad (_("invalid register operand size for `%s'"),
6540 check_byte_reg (void)
6544 for (op
= i
.operands
; --op
>= 0;)
6546 /* Skip non-register operands. */
6547 if (!i
.types
[op
].bitfield
.reg
)
6550 /* If this is an eight bit register, it's OK. If it's the 16 or
6551 32 bit version of an eight bit register, we will just use the
6552 low portion, and that's OK too. */
6553 if (i
.types
[op
].bitfield
.byte
)
6556 /* I/O port address operands are OK too. */
6557 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6560 /* crc32 doesn't generate this warning. */
6561 if (i
.tm
.base_opcode
== 0xf20f38f0)
6564 if ((i
.types
[op
].bitfield
.word
6565 || i
.types
[op
].bitfield
.dword
6566 || i
.types
[op
].bitfield
.qword
)
6567 && i
.op
[op
].regs
->reg_num
< 4
6568 /* Prohibit these changes in 64bit mode, since the lowering
6569 would be more complicated. */
6570 && flag_code
!= CODE_64BIT
)
6572 #if REGISTER_WARNINGS
6573 if (!quiet_warnings
)
6574 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6576 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6577 ? REGNAM_AL
- REGNAM_AX
6578 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6580 i
.op
[op
].regs
->reg_name
,
6585 /* Any other register is bad. */
6586 if (i
.types
[op
].bitfield
.reg
6587 || i
.types
[op
].bitfield
.regmmx
6588 || i
.types
[op
].bitfield
.regsimd
6589 || i
.types
[op
].bitfield
.sreg
6590 || i
.types
[op
].bitfield
.control
6591 || i
.types
[op
].bitfield
.debug
6592 || i
.types
[op
].bitfield
.test
)
6594 as_bad (_("`%s%s' not allowed with `%s%c'"),
6596 i
.op
[op
].regs
->reg_name
,
6606 check_long_reg (void)
6610 for (op
= i
.operands
; --op
>= 0;)
6611 /* Skip non-register operands. */
6612 if (!i
.types
[op
].bitfield
.reg
)
6614 /* Reject eight bit registers, except where the template requires
6615 them. (eg. movzb) */
6616 else if (i
.types
[op
].bitfield
.byte
6617 && (i
.tm
.operand_types
[op
].bitfield
.reg
6618 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6619 && (i
.tm
.operand_types
[op
].bitfield
.word
6620 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6622 as_bad (_("`%s%s' not allowed with `%s%c'"),
6624 i
.op
[op
].regs
->reg_name
,
6629 /* Warn if the e prefix on a general reg is missing. */
6630 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6631 && i
.types
[op
].bitfield
.word
6632 && (i
.tm
.operand_types
[op
].bitfield
.reg
6633 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6634 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6636 /* Prohibit these changes in the 64bit mode, since the
6637 lowering is more complicated. */
6638 if (flag_code
== CODE_64BIT
)
6640 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6641 register_prefix
, i
.op
[op
].regs
->reg_name
,
6645 #if REGISTER_WARNINGS
6646 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6648 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6649 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6652 /* Warn if the r prefix on a general reg is present. */
6653 else if (i
.types
[op
].bitfield
.qword
6654 && (i
.tm
.operand_types
[op
].bitfield
.reg
6655 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6656 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6659 && i
.tm
.opcode_modifier
.toqword
6660 && !i
.types
[0].bitfield
.regsimd
)
6662 /* Convert to QWORD. We want REX byte. */
6663 i
.suffix
= QWORD_MNEM_SUFFIX
;
6667 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6668 register_prefix
, i
.op
[op
].regs
->reg_name
,
6677 check_qword_reg (void)
6681 for (op
= i
.operands
; --op
>= 0; )
6682 /* Skip non-register operands. */
6683 if (!i
.types
[op
].bitfield
.reg
)
6685 /* Reject eight bit registers, except where the template requires
6686 them. (eg. movzb) */
6687 else if (i
.types
[op
].bitfield
.byte
6688 && (i
.tm
.operand_types
[op
].bitfield
.reg
6689 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6690 && (i
.tm
.operand_types
[op
].bitfield
.word
6691 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6693 as_bad (_("`%s%s' not allowed with `%s%c'"),
6695 i
.op
[op
].regs
->reg_name
,
6700 /* Warn if the r prefix on a general reg is missing. */
6701 else if ((i
.types
[op
].bitfield
.word
6702 || i
.types
[op
].bitfield
.dword
)
6703 && (i
.tm
.operand_types
[op
].bitfield
.reg
6704 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6705 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6707 /* Prohibit these changes in the 64bit mode, since the
6708 lowering is more complicated. */
6710 && i
.tm
.opcode_modifier
.todword
6711 && !i
.types
[0].bitfield
.regsimd
)
6713 /* Convert to DWORD. We don't want REX byte. */
6714 i
.suffix
= LONG_MNEM_SUFFIX
;
6718 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6719 register_prefix
, i
.op
[op
].regs
->reg_name
,
6728 check_word_reg (void)
6731 for (op
= i
.operands
; --op
>= 0;)
6732 /* Skip non-register operands. */
6733 if (!i
.types
[op
].bitfield
.reg
)
6735 /* Reject eight bit registers, except where the template requires
6736 them. (eg. movzb) */
6737 else if (i
.types
[op
].bitfield
.byte
6738 && (i
.tm
.operand_types
[op
].bitfield
.reg
6739 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6740 && (i
.tm
.operand_types
[op
].bitfield
.word
6741 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6743 as_bad (_("`%s%s' not allowed with `%s%c'"),
6745 i
.op
[op
].regs
->reg_name
,
6750 /* Warn if the e or r prefix on a general reg is present. */
6751 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6752 && (i
.types
[op
].bitfield
.dword
6753 || i
.types
[op
].bitfield
.qword
)
6754 && (i
.tm
.operand_types
[op
].bitfield
.reg
6755 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6756 && i
.tm
.operand_types
[op
].bitfield
.word
)
6758 /* Prohibit these changes in the 64bit mode, since the
6759 lowering is more complicated. */
6760 if (flag_code
== CODE_64BIT
)
6762 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6763 register_prefix
, i
.op
[op
].regs
->reg_name
,
6767 #if REGISTER_WARNINGS
6768 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6770 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6771 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6778 update_imm (unsigned int j
)
6780 i386_operand_type overlap
= i
.types
[j
];
6781 if ((overlap
.bitfield
.imm8
6782 || overlap
.bitfield
.imm8s
6783 || overlap
.bitfield
.imm16
6784 || overlap
.bitfield
.imm32
6785 || overlap
.bitfield
.imm32s
6786 || overlap
.bitfield
.imm64
)
6787 && !operand_type_equal (&overlap
, &imm8
)
6788 && !operand_type_equal (&overlap
, &imm8s
)
6789 && !operand_type_equal (&overlap
, &imm16
)
6790 && !operand_type_equal (&overlap
, &imm32
)
6791 && !operand_type_equal (&overlap
, &imm32s
)
6792 && !operand_type_equal (&overlap
, &imm64
))
6796 i386_operand_type temp
;
6798 operand_type_set (&temp
, 0);
6799 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6801 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6802 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6804 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6805 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6806 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6808 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6809 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6812 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6815 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6816 || operand_type_equal (&overlap
, &imm16_32
)
6817 || operand_type_equal (&overlap
, &imm16_32s
))
6819 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6824 if (!operand_type_equal (&overlap
, &imm8
)
6825 && !operand_type_equal (&overlap
, &imm8s
)
6826 && !operand_type_equal (&overlap
, &imm16
)
6827 && !operand_type_equal (&overlap
, &imm32
)
6828 && !operand_type_equal (&overlap
, &imm32s
)
6829 && !operand_type_equal (&overlap
, &imm64
))
6831 as_bad (_("no instruction mnemonic suffix given; "
6832 "can't determine immediate size"));
6836 i
.types
[j
] = overlap
;
6846 /* Update the first 2 immediate operands. */
6847 n
= i
.operands
> 2 ? 2 : i
.operands
;
6850 for (j
= 0; j
< n
; j
++)
6851 if (update_imm (j
) == 0)
6854 /* The 3rd operand can't be immediate operand. */
6855 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6862 process_operands (void)
6864 /* Default segment register this instruction will use for memory
6865 accesses. 0 means unknown. This is only for optimizing out
6866 unnecessary segment overrides. */
6867 const seg_entry
*default_seg
= 0;
6869 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6871 unsigned int dupl
= i
.operands
;
6872 unsigned int dest
= dupl
- 1;
6875 /* The destination must be an xmm register. */
6876 gas_assert (i
.reg_operands
6877 && MAX_OPERANDS
> dupl
6878 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6880 if (i
.tm
.operand_types
[0].bitfield
.acc
6881 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6883 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6885 /* Keep xmm0 for instructions with VEX prefix and 3
6887 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6888 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6893 /* We remove the first xmm0 and keep the number of
6894 operands unchanged, which in fact duplicates the
6896 for (j
= 1; j
< i
.operands
; j
++)
6898 i
.op
[j
- 1] = i
.op
[j
];
6899 i
.types
[j
- 1] = i
.types
[j
];
6900 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6901 i
.flags
[j
- 1] = i
.flags
[j
];
6905 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6907 gas_assert ((MAX_OPERANDS
- 1) > dupl
6908 && (i
.tm
.opcode_modifier
.vexsources
6911 /* Add the implicit xmm0 for instructions with VEX prefix
6913 for (j
= i
.operands
; j
> 0; j
--)
6915 i
.op
[j
] = i
.op
[j
- 1];
6916 i
.types
[j
] = i
.types
[j
- 1];
6917 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6918 i
.flags
[j
] = i
.flags
[j
- 1];
6921 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6922 i
.types
[0] = regxmm
;
6923 i
.tm
.operand_types
[0] = regxmm
;
6926 i
.reg_operands
+= 2;
6931 i
.op
[dupl
] = i
.op
[dest
];
6932 i
.types
[dupl
] = i
.types
[dest
];
6933 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6934 i
.flags
[dupl
] = i
.flags
[dest
];
6943 i
.op
[dupl
] = i
.op
[dest
];
6944 i
.types
[dupl
] = i
.types
[dest
];
6945 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6946 i
.flags
[dupl
] = i
.flags
[dest
];
6949 if (i
.tm
.opcode_modifier
.immext
)
6952 else if (i
.tm
.operand_types
[0].bitfield
.acc
6953 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6957 for (j
= 1; j
< i
.operands
; j
++)
6959 i
.op
[j
- 1] = i
.op
[j
];
6960 i
.types
[j
- 1] = i
.types
[j
];
6962 /* We need to adjust fields in i.tm since they are used by
6963 build_modrm_byte. */
6964 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6966 i
.flags
[j
- 1] = i
.flags
[j
];
6973 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6975 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6977 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6978 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6979 regnum
= register_number (i
.op
[1].regs
);
6980 first_reg_in_group
= regnum
& ~3;
6981 last_reg_in_group
= first_reg_in_group
+ 3;
6982 if (regnum
!= first_reg_in_group
)
6983 as_warn (_("source register `%s%s' implicitly denotes"
6984 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6985 register_prefix
, i
.op
[1].regs
->reg_name
,
6986 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6987 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6990 else if (i
.tm
.opcode_modifier
.regkludge
)
6992 /* The imul $imm, %reg instruction is converted into
6993 imul $imm, %reg, %reg, and the clr %reg instruction
6994 is converted into xor %reg, %reg. */
6996 unsigned int first_reg_op
;
6998 if (operand_type_check (i
.types
[0], reg
))
7002 /* Pretend we saw the extra register operand. */
7003 gas_assert (i
.reg_operands
== 1
7004 && i
.op
[first_reg_op
+ 1].regs
== 0);
7005 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7006 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7011 if (i
.tm
.opcode_modifier
.modrm
)
7013 /* The opcode is completed (modulo i.tm.extension_opcode which
7014 must be put into the modrm byte). Now, we make the modrm and
7015 index base bytes based on all the info we've collected. */
7017 default_seg
= build_modrm_byte ();
7019 else if (i
.types
[0].bitfield
.sreg
)
7021 if (flag_code
!= CODE_64BIT
7022 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7023 && i
.op
[0].regs
->reg_num
== 1
7024 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7025 && i
.op
[0].regs
->reg_num
< 4)
7027 as_bad (_("you can't `%s %s%s'"),
7028 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7031 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7033 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7034 i
.tm
.opcode_length
= 2;
7036 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7038 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7042 else if (i
.tm
.opcode_modifier
.isstring
)
7044 /* For the string instructions that allow a segment override
7045 on one of their operands, the default segment is ds. */
7048 else if (i
.tm
.opcode_modifier
.shortform
)
7050 /* The register or float register operand is in operand
7052 unsigned int op
= !i
.tm
.operand_types
[0].bitfield
.reg
;
7054 /* Register goes in low 3 bits of opcode. */
7055 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7056 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7058 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7060 /* Warn about some common errors, but press on regardless.
7061 The first case can be generated by gcc (<= 2.8.1). */
7062 if (i
.operands
== 2)
7064 /* Reversed arguments on faddp, fsubp, etc. */
7065 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7066 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7067 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7071 /* Extraneous `l' suffix on fp insn. */
7072 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7073 register_prefix
, i
.op
[0].regs
->reg_name
);
7078 if (i
.tm
.base_opcode
== 0x8d /* lea */
7081 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7083 /* If a segment was explicitly specified, and the specified segment
7084 is not the default, use an opcode prefix to select it. If we
7085 never figured out what the default segment is, then default_seg
7086 will be zero at this point, and the specified segment prefix will
7088 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7090 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7096 static const seg_entry
*
7097 build_modrm_byte (void)
7099 const seg_entry
*default_seg
= 0;
7100 unsigned int source
, dest
;
7103 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7106 unsigned int nds
, reg_slot
;
7109 dest
= i
.operands
- 1;
7112 /* There are 2 kinds of instructions:
7113 1. 5 operands: 4 register operands or 3 register operands
7114 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7115 VexW0 or VexW1. The destination must be either XMM, YMM or
7117 2. 4 operands: 4 register operands or 3 register operands
7118 plus 1 memory operand, with VexXDS. */
7119 gas_assert ((i
.reg_operands
== 4
7120 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7121 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7122 && i
.tm
.opcode_modifier
.vexw
7123 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7125 /* If VexW1 is set, the first non-immediate operand is the source and
7126 the second non-immediate one is encoded in the immediate operand. */
7127 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7129 source
= i
.imm_operands
;
7130 reg_slot
= i
.imm_operands
+ 1;
7134 source
= i
.imm_operands
+ 1;
7135 reg_slot
= i
.imm_operands
;
7138 if (i
.imm_operands
== 0)
7140 /* When there is no immediate operand, generate an 8bit
7141 immediate operand to encode the first operand. */
7142 exp
= &im_expressions
[i
.imm_operands
++];
7143 i
.op
[i
.operands
].imms
= exp
;
7144 i
.types
[i
.operands
] = imm8
;
7147 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7148 exp
->X_op
= O_constant
;
7149 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7150 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7154 gas_assert (i
.imm_operands
== 1);
7155 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7156 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7158 /* Turn on Imm8 again so that output_imm will generate it. */
7159 i
.types
[0].bitfield
.imm8
= 1;
7161 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7162 i
.op
[0].imms
->X_add_number
7163 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7164 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7167 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7168 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7173 /* i.reg_operands MUST be the number of real register operands;
7174 implicit registers do not count. If there are 3 register
7175 operands, it must be a instruction with VexNDS. For a
7176 instruction with VexNDD, the destination register is encoded
7177 in VEX prefix. If there are 4 register operands, it must be
7178 a instruction with VEX prefix and 3 sources. */
7179 if (i
.mem_operands
== 0
7180 && ((i
.reg_operands
== 2
7181 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7182 || (i
.reg_operands
== 3
7183 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7184 || (i
.reg_operands
== 4 && vex_3_sources
)))
7192 /* When there are 3 operands, one of them may be immediate,
7193 which may be the first or the last operand. Otherwise,
7194 the first operand must be shift count register (cl) or it
7195 is an instruction with VexNDS. */
7196 gas_assert (i
.imm_operands
== 1
7197 || (i
.imm_operands
== 0
7198 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7199 || i
.types
[0].bitfield
.shiftcount
)));
7200 if (operand_type_check (i
.types
[0], imm
)
7201 || i
.types
[0].bitfield
.shiftcount
)
7207 /* When there are 4 operands, the first two must be 8bit
7208 immediate operands. The source operand will be the 3rd
7211 For instructions with VexNDS, if the first operand
7212 an imm8, the source operand is the 2nd one. If the last
7213 operand is imm8, the source operand is the first one. */
7214 gas_assert ((i
.imm_operands
== 2
7215 && i
.types
[0].bitfield
.imm8
7216 && i
.types
[1].bitfield
.imm8
)
7217 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7218 && i
.imm_operands
== 1
7219 && (i
.types
[0].bitfield
.imm8
7220 || i
.types
[i
.operands
- 1].bitfield
.imm8
7222 if (i
.imm_operands
== 2)
7226 if (i
.types
[0].bitfield
.imm8
)
7233 if (is_evex_encoding (&i
.tm
))
7235 /* For EVEX instructions, when there are 5 operands, the
7236 first one must be immediate operand. If the second one
7237 is immediate operand, the source operand is the 3th
7238 one. If the last one is immediate operand, the source
7239 operand is the 2nd one. */
7240 gas_assert (i
.imm_operands
== 2
7241 && i
.tm
.opcode_modifier
.sae
7242 && operand_type_check (i
.types
[0], imm
));
7243 if (operand_type_check (i
.types
[1], imm
))
7245 else if (operand_type_check (i
.types
[4], imm
))
7259 /* RC/SAE operand could be between DEST and SRC. That happens
7260 when one operand is GPR and the other one is XMM/YMM/ZMM
7262 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7265 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7267 /* For instructions with VexNDS, the register-only source
7268 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7269 register. It is encoded in VEX prefix. */
7271 i386_operand_type op
;
7274 /* Check register-only source operand when two source
7275 operands are swapped. */
7276 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7277 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7285 op
= i
.tm
.operand_types
[vvvv
];
7286 if ((dest
+ 1) >= i
.operands
7287 || ((!op
.bitfield
.reg
7288 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7289 && !op
.bitfield
.regsimd
7290 && !operand_type_equal (&op
, ®mask
)))
7292 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7298 /* One of the register operands will be encoded in the i.rm.reg
7299 field, the other in the combined i.rm.mode and i.rm.regmem
7300 fields. If no form of this instruction supports a memory
7301 destination operand, then we assume the source operand may
7302 sometimes be a memory operand and so we need to store the
7303 destination in the i.rm.reg field. */
7304 if (!i
.tm
.opcode_modifier
.regmem
7305 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7307 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7308 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7309 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7310 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7311 i
.has_regmmx
= TRUE
;
7312 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7313 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7315 if (i
.types
[dest
].bitfield
.zmmword
7316 || i
.types
[source
].bitfield
.zmmword
)
7317 i
.has_regzmm
= TRUE
;
7318 else if (i
.types
[dest
].bitfield
.ymmword
7319 || i
.types
[source
].bitfield
.ymmword
)
7320 i
.has_regymm
= TRUE
;
7322 i
.has_regxmm
= TRUE
;
7324 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7326 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7328 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7330 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7335 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7336 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7337 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7339 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7341 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7343 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7346 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7348 if (!i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.control
)
7351 add_prefix (LOCK_PREFIX_OPCODE
);
7355 { /* If it's not 2 reg operands... */
7360 unsigned int fake_zero_displacement
= 0;
7363 for (op
= 0; op
< i
.operands
; op
++)
7364 if (i
.flags
[op
] & Operand_Mem
)
7366 gas_assert (op
< i
.operands
);
7368 if (i
.tm
.opcode_modifier
.vecsib
)
7370 if (i
.index_reg
->reg_num
== RegIZ
)
7373 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7376 i
.sib
.base
= NO_BASE_REGISTER
;
7377 i
.sib
.scale
= i
.log2_scale_factor
;
7378 i
.types
[op
].bitfield
.disp8
= 0;
7379 i
.types
[op
].bitfield
.disp16
= 0;
7380 i
.types
[op
].bitfield
.disp64
= 0;
7381 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7383 /* Must be 32 bit */
7384 i
.types
[op
].bitfield
.disp32
= 1;
7385 i
.types
[op
].bitfield
.disp32s
= 0;
7389 i
.types
[op
].bitfield
.disp32
= 0;
7390 i
.types
[op
].bitfield
.disp32s
= 1;
7393 i
.sib
.index
= i
.index_reg
->reg_num
;
7394 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7396 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7402 if (i
.base_reg
== 0)
7405 if (!i
.disp_operands
)
7406 fake_zero_displacement
= 1;
7407 if (i
.index_reg
== 0)
7409 i386_operand_type newdisp
;
7411 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7412 /* Operand is just <disp> */
7413 if (flag_code
== CODE_64BIT
)
7415 /* 64bit mode overwrites the 32bit absolute
7416 addressing by RIP relative addressing and
7417 absolute addressing is encoded by one of the
7418 redundant SIB forms. */
7419 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7420 i
.sib
.base
= NO_BASE_REGISTER
;
7421 i
.sib
.index
= NO_INDEX_REGISTER
;
7422 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7424 else if ((flag_code
== CODE_16BIT
)
7425 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7427 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7432 i
.rm
.regmem
= NO_BASE_REGISTER
;
7435 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7436 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7438 else if (!i
.tm
.opcode_modifier
.vecsib
)
7440 /* !i.base_reg && i.index_reg */
7441 if (i
.index_reg
->reg_num
== RegIZ
)
7442 i
.sib
.index
= NO_INDEX_REGISTER
;
7444 i
.sib
.index
= i
.index_reg
->reg_num
;
7445 i
.sib
.base
= NO_BASE_REGISTER
;
7446 i
.sib
.scale
= i
.log2_scale_factor
;
7447 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7448 i
.types
[op
].bitfield
.disp8
= 0;
7449 i
.types
[op
].bitfield
.disp16
= 0;
7450 i
.types
[op
].bitfield
.disp64
= 0;
7451 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7453 /* Must be 32 bit */
7454 i
.types
[op
].bitfield
.disp32
= 1;
7455 i
.types
[op
].bitfield
.disp32s
= 0;
7459 i
.types
[op
].bitfield
.disp32
= 0;
7460 i
.types
[op
].bitfield
.disp32s
= 1;
7462 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7466 /* RIP addressing for 64bit mode. */
7467 else if (i
.base_reg
->reg_num
== RegIP
)
7469 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7470 i
.rm
.regmem
= NO_BASE_REGISTER
;
7471 i
.types
[op
].bitfield
.disp8
= 0;
7472 i
.types
[op
].bitfield
.disp16
= 0;
7473 i
.types
[op
].bitfield
.disp32
= 0;
7474 i
.types
[op
].bitfield
.disp32s
= 1;
7475 i
.types
[op
].bitfield
.disp64
= 0;
7476 i
.flags
[op
] |= Operand_PCrel
;
7477 if (! i
.disp_operands
)
7478 fake_zero_displacement
= 1;
7480 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7482 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7483 switch (i
.base_reg
->reg_num
)
7486 if (i
.index_reg
== 0)
7488 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7489 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7493 if (i
.index_reg
== 0)
7496 if (operand_type_check (i
.types
[op
], disp
) == 0)
7498 /* fake (%bp) into 0(%bp) */
7499 i
.types
[op
].bitfield
.disp8
= 1;
7500 fake_zero_displacement
= 1;
7503 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7504 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7506 default: /* (%si) -> 4 or (%di) -> 5 */
7507 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7509 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7511 else /* i.base_reg and 32/64 bit mode */
7513 if (flag_code
== CODE_64BIT
7514 && operand_type_check (i
.types
[op
], disp
))
7516 i
.types
[op
].bitfield
.disp16
= 0;
7517 i
.types
[op
].bitfield
.disp64
= 0;
7518 if (i
.prefix
[ADDR_PREFIX
] == 0)
7520 i
.types
[op
].bitfield
.disp32
= 0;
7521 i
.types
[op
].bitfield
.disp32s
= 1;
7525 i
.types
[op
].bitfield
.disp32
= 1;
7526 i
.types
[op
].bitfield
.disp32s
= 0;
7530 if (!i
.tm
.opcode_modifier
.vecsib
)
7531 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7532 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7534 i
.sib
.base
= i
.base_reg
->reg_num
;
7535 /* x86-64 ignores REX prefix bit here to avoid decoder
7537 if (!(i
.base_reg
->reg_flags
& RegRex
)
7538 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7539 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7541 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7543 fake_zero_displacement
= 1;
7544 i
.types
[op
].bitfield
.disp8
= 1;
7546 i
.sib
.scale
= i
.log2_scale_factor
;
7547 if (i
.index_reg
== 0)
7549 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7550 /* <disp>(%esp) becomes two byte modrm with no index
7551 register. We've already stored the code for esp
7552 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7553 Any base register besides %esp will not use the
7554 extra modrm byte. */
7555 i
.sib
.index
= NO_INDEX_REGISTER
;
7557 else if (!i
.tm
.opcode_modifier
.vecsib
)
7559 if (i
.index_reg
->reg_num
== RegIZ
)
7560 i
.sib
.index
= NO_INDEX_REGISTER
;
7562 i
.sib
.index
= i
.index_reg
->reg_num
;
7563 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7564 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7569 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7570 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7574 if (!fake_zero_displacement
7578 fake_zero_displacement
= 1;
7579 if (i
.disp_encoding
== disp_encoding_8bit
)
7580 i
.types
[op
].bitfield
.disp8
= 1;
7582 i
.types
[op
].bitfield
.disp32
= 1;
7584 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7588 if (fake_zero_displacement
)
7590 /* Fakes a zero displacement assuming that i.types[op]
7591 holds the correct displacement size. */
7594 gas_assert (i
.op
[op
].disps
== 0);
7595 exp
= &disp_expressions
[i
.disp_operands
++];
7596 i
.op
[op
].disps
= exp
;
7597 exp
->X_op
= O_constant
;
7598 exp
->X_add_number
= 0;
7599 exp
->X_add_symbol
= (symbolS
*) 0;
7600 exp
->X_op_symbol
= (symbolS
*) 0;
7608 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7610 if (operand_type_check (i
.types
[0], imm
))
7611 i
.vex
.register_specifier
= NULL
;
7614 /* VEX.vvvv encodes one of the sources when the first
7615 operand is not an immediate. */
7616 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7617 i
.vex
.register_specifier
= i
.op
[0].regs
;
7619 i
.vex
.register_specifier
= i
.op
[1].regs
;
7622 /* Destination is a XMM register encoded in the ModRM.reg
7624 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7625 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7628 /* ModRM.rm and VEX.B encodes the other source. */
7629 if (!i
.mem_operands
)
7633 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7634 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7636 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7638 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7642 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7644 i
.vex
.register_specifier
= i
.op
[2].regs
;
7645 if (!i
.mem_operands
)
7648 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7649 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7653 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7654 (if any) based on i.tm.extension_opcode. Again, we must be
7655 careful to make sure that segment/control/debug/test/MMX
7656 registers are coded into the i.rm.reg field. */
7657 else if (i
.reg_operands
)
7660 unsigned int vex_reg
= ~0;
7662 for (op
= 0; op
< i
.operands
; op
++)
7664 if (i
.types
[op
].bitfield
.reg
7665 || i
.types
[op
].bitfield
.regbnd
7666 || i
.types
[op
].bitfield
.regmask
7667 || i
.types
[op
].bitfield
.sreg
7668 || i
.types
[op
].bitfield
.control
7669 || i
.types
[op
].bitfield
.debug
7670 || i
.types
[op
].bitfield
.test
)
7672 if (i
.types
[op
].bitfield
.regsimd
)
7674 if (i
.types
[op
].bitfield
.zmmword
)
7675 i
.has_regzmm
= TRUE
;
7676 else if (i
.types
[op
].bitfield
.ymmword
)
7677 i
.has_regymm
= TRUE
;
7679 i
.has_regxmm
= TRUE
;
7682 if (i
.types
[op
].bitfield
.regmmx
)
7684 i
.has_regmmx
= TRUE
;
7691 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7693 /* For instructions with VexNDS, the register-only
7694 source operand is encoded in VEX prefix. */
7695 gas_assert (mem
!= (unsigned int) ~0);
7700 gas_assert (op
< i
.operands
);
7704 /* Check register-only source operand when two source
7705 operands are swapped. */
7706 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7707 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7711 gas_assert (mem
== (vex_reg
+ 1)
7712 && op
< i
.operands
);
7717 gas_assert (vex_reg
< i
.operands
);
7721 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7723 /* For instructions with VexNDD, the register destination
7724 is encoded in VEX prefix. */
7725 if (i
.mem_operands
== 0)
7727 /* There is no memory operand. */
7728 gas_assert ((op
+ 2) == i
.operands
);
7733 /* There are only 2 non-immediate operands. */
7734 gas_assert (op
< i
.imm_operands
+ 2
7735 && i
.operands
== i
.imm_operands
+ 2);
7736 vex_reg
= i
.imm_operands
+ 1;
7740 gas_assert (op
< i
.operands
);
7742 if (vex_reg
!= (unsigned int) ~0)
7744 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7746 if ((!type
->bitfield
.reg
7747 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7748 && !type
->bitfield
.regsimd
7749 && !operand_type_equal (type
, ®mask
))
7752 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7755 /* Don't set OP operand twice. */
7758 /* If there is an extension opcode to put here, the
7759 register number must be put into the regmem field. */
7760 if (i
.tm
.extension_opcode
!= None
)
7762 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7763 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7765 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7770 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7771 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7773 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7778 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7779 must set it to 3 to indicate this is a register operand
7780 in the regmem field. */
7781 if (!i
.mem_operands
)
7785 /* Fill in i.rm.reg field with extension opcode (if any). */
7786 if (i
.tm
.extension_opcode
!= None
)
7787 i
.rm
.reg
= i
.tm
.extension_opcode
;
7793 output_branch (void)
7799 relax_substateT subtype
;
7803 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7804 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7807 if (i
.prefix
[DATA_PREFIX
] != 0)
7813 /* Pentium4 branch hints. */
7814 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7815 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7820 if (i
.prefix
[REX_PREFIX
] != 0)
7826 /* BND prefixed jump. */
7827 if (i
.prefix
[BND_PREFIX
] != 0)
7829 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7833 if (i
.prefixes
!= 0 && !intel_syntax
)
7834 as_warn (_("skipping prefixes on this instruction"));
7836 /* It's always a symbol; End frag & setup for relax.
7837 Make sure there is enough room in this frag for the largest
7838 instruction we may generate in md_convert_frag. This is 2
7839 bytes for the opcode and room for the prefix and largest
7841 frag_grow (prefix
+ 2 + 4);
7842 /* Prefix and 1 opcode byte go in fr_fix. */
7843 p
= frag_more (prefix
+ 1);
7844 if (i
.prefix
[DATA_PREFIX
] != 0)
7845 *p
++ = DATA_PREFIX_OPCODE
;
7846 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7847 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7848 *p
++ = i
.prefix
[SEG_PREFIX
];
7849 if (i
.prefix
[REX_PREFIX
] != 0)
7850 *p
++ = i
.prefix
[REX_PREFIX
];
7851 *p
= i
.tm
.base_opcode
;
7853 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7854 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7855 else if (cpu_arch_flags
.bitfield
.cpui386
)
7856 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7858 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7861 sym
= i
.op
[0].disps
->X_add_symbol
;
7862 off
= i
.op
[0].disps
->X_add_number
;
7864 if (i
.op
[0].disps
->X_op
!= O_constant
7865 && i
.op
[0].disps
->X_op
!= O_symbol
)
7867 /* Handle complex expressions. */
7868 sym
= make_expr_symbol (i
.op
[0].disps
);
7872 /* 1 possible extra opcode + 4 byte displacement go in var part.
7873 Pass reloc in fr_var. */
7874 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7878 /* Return TRUE iff PLT32 relocation should be used for branching to
7882 need_plt32_p (symbolS
*s
)
7884 /* PLT32 relocation is ELF only. */
7889 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7890 krtld support it. */
7894 /* Since there is no need to prepare for PLT branch on x86-64, we
7895 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7896 be used as a marker for 32-bit PC-relative branches. */
7900 /* Weak or undefined symbol need PLT32 relocation. */
7901 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7904 /* Non-global symbol doesn't need PLT32 relocation. */
7905 if (! S_IS_EXTERNAL (s
))
7908 /* Other global symbols need PLT32 relocation. NB: Symbol with
7909 non-default visibilities are treated as normal global symbol
7910 so that PLT32 relocation can be used as a marker for 32-bit
7911 PC-relative branches. It is useful for linker relaxation. */
7922 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7924 if (i
.tm
.opcode_modifier
.jumpbyte
)
7926 /* This is a loop or jecxz type instruction. */
7928 if (i
.prefix
[ADDR_PREFIX
] != 0)
7930 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7933 /* Pentium4 branch hints. */
7934 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7935 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7937 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7946 if (flag_code
== CODE_16BIT
)
7949 if (i
.prefix
[DATA_PREFIX
] != 0)
7951 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7961 if (i
.prefix
[REX_PREFIX
] != 0)
7963 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7967 /* BND prefixed jump. */
7968 if (i
.prefix
[BND_PREFIX
] != 0)
7970 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7974 if (i
.prefixes
!= 0 && !intel_syntax
)
7975 as_warn (_("skipping prefixes on this instruction"));
7977 p
= frag_more (i
.tm
.opcode_length
+ size
);
7978 switch (i
.tm
.opcode_length
)
7981 *p
++ = i
.tm
.base_opcode
>> 8;
7984 *p
++ = i
.tm
.base_opcode
;
7990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7992 && jump_reloc
== NO_RELOC
7993 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7994 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7997 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7999 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8000 i
.op
[0].disps
, 1, jump_reloc
);
8002 /* All jumps handled here are signed, but don't use a signed limit
8003 check for 32 and 16 bit jumps as we want to allow wrap around at
8004 4G and 64k respectively. */
8006 fixP
->fx_signed
= 1;
8010 output_interseg_jump (void)
8018 if (flag_code
== CODE_16BIT
)
8022 if (i
.prefix
[DATA_PREFIX
] != 0)
8028 if (i
.prefix
[REX_PREFIX
] != 0)
8038 if (i
.prefixes
!= 0 && !intel_syntax
)
8039 as_warn (_("skipping prefixes on this instruction"));
8041 /* 1 opcode; 2 segment; offset */
8042 p
= frag_more (prefix
+ 1 + 2 + size
);
8044 if (i
.prefix
[DATA_PREFIX
] != 0)
8045 *p
++ = DATA_PREFIX_OPCODE
;
8047 if (i
.prefix
[REX_PREFIX
] != 0)
8048 *p
++ = i
.prefix
[REX_PREFIX
];
8050 *p
++ = i
.tm
.base_opcode
;
8051 if (i
.op
[1].imms
->X_op
== O_constant
)
8053 offsetT n
= i
.op
[1].imms
->X_add_number
;
8056 && !fits_in_unsigned_word (n
)
8057 && !fits_in_signed_word (n
))
8059 as_bad (_("16-bit jump out of range"));
8062 md_number_to_chars (p
, n
, size
);
8065 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8066 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8067 if (i
.op
[0].imms
->X_op
!= O_constant
)
8068 as_bad (_("can't handle non absolute segment in `%s'"),
8070 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8073 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8078 asection
*seg
= now_seg
;
8079 subsegT subseg
= now_subseg
;
8081 unsigned int alignment
, align_size_1
;
8082 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8083 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8084 unsigned int padding
;
8086 if (!IS_ELF
|| !x86_used_note
)
8089 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8091 /* The .note.gnu.property section layout:
8093 Field Length Contents
8096 n_descsz 4 The note descriptor size
8097 n_type 4 NT_GNU_PROPERTY_TYPE_0
8099 n_desc n_descsz The program property array
8103 /* Create the .note.gnu.property section. */
8104 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8105 bfd_set_section_flags (sec
,
8112 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8123 bfd_set_section_alignment (sec
, alignment
);
8124 elf_section_type (sec
) = SHT_NOTE
;
8126 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8128 isa_1_descsz_raw
= 4 + 4 + 4;
8129 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8130 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8132 feature_2_descsz_raw
= isa_1_descsz
;
8133 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8135 feature_2_descsz_raw
+= 4 + 4 + 4;
8136 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8137 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8140 descsz
= feature_2_descsz
;
8141 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8142 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8144 /* Write n_namsz. */
8145 md_number_to_chars (p
, (valueT
) 4, 4);
8147 /* Write n_descsz. */
8148 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8151 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8154 memcpy (p
+ 4 * 3, "GNU", 4);
8156 /* Write 4-byte type. */
8157 md_number_to_chars (p
+ 4 * 4,
8158 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8160 /* Write 4-byte data size. */
8161 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8163 /* Write 4-byte data. */
8164 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8166 /* Zero out paddings. */
8167 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8169 memset (p
+ 4 * 7, 0, padding
);
8171 /* Write 4-byte type. */
8172 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8173 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8175 /* Write 4-byte data size. */
8176 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8178 /* Write 4-byte data. */
8179 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8180 (valueT
) x86_feature_2_used
, 4);
8182 /* Zero out paddings. */
8183 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8185 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8187 /* We probably can't restore the current segment, for there likely
8190 subseg_set (seg
, subseg
);
8195 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8196 const char *frag_now_ptr
)
8198 unsigned int len
= 0;
8200 if (start_frag
!= frag_now
)
8202 const fragS
*fr
= start_frag
;
8207 } while (fr
&& fr
!= frag_now
);
8210 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8216 fragS
*insn_start_frag
;
8217 offsetT insn_start_off
;
8219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8220 if (IS_ELF
&& x86_used_note
)
8222 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8223 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8224 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8225 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8226 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8227 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8228 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8230 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8231 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8233 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8235 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8239 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8240 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8241 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8242 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8243 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8244 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8245 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8246 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8247 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8248 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8249 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8250 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8251 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8252 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8253 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8254 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8255 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8256 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8257 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8258 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8259 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8260 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8261 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8262 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8263 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8264 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8265 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8266 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8267 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8268 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8269 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8270 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8271 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8273 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8274 || i
.tm
.cpu_flags
.bitfield
.cpu287
8275 || i
.tm
.cpu_flags
.bitfield
.cpu387
8276 || i
.tm
.cpu_flags
.bitfield
.cpu687
8277 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8278 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8279 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8280 Xfence instructions. */
8281 if (i
.tm
.base_opcode
!= 0xf18
8282 && i
.tm
.base_opcode
!= 0xf0d
8283 && i
.tm
.base_opcode
!= 0xfaef8
8285 || i
.tm
.cpu_flags
.bitfield
.cpummx
8286 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8287 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8288 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8290 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8292 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8294 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8295 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8296 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8297 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8298 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8299 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8300 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8301 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8302 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8306 /* Tie dwarf2 debug info to the address at the start of the insn.
8307 We can't do this after the insn has been output as the current
8308 frag may have been closed off. eg. by frag_var. */
8309 dwarf2_emit_insn (0);
8311 insn_start_frag
= frag_now
;
8312 insn_start_off
= frag_now_fix ();
8315 if (i
.tm
.opcode_modifier
.jump
)
8317 else if (i
.tm
.opcode_modifier
.jumpbyte
8318 || i
.tm
.opcode_modifier
.jumpdword
)
8320 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8321 output_interseg_jump ();
8324 /* Output normal instructions here. */
8328 unsigned int prefix
;
8331 && (i
.tm
.base_opcode
== 0xfaee8
8332 || i
.tm
.base_opcode
== 0xfaef0
8333 || i
.tm
.base_opcode
== 0xfaef8))
8335 /* Encode lfence, mfence, and sfence as
8336 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8337 offsetT val
= 0x240483f0ULL
;
8339 md_number_to_chars (p
, val
, 5);
8343 /* Some processors fail on LOCK prefix. This options makes
8344 assembler ignore LOCK prefix and serves as a workaround. */
8345 if (omit_lock_prefix
)
8347 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8349 i
.prefix
[LOCK_PREFIX
] = 0;
8352 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8353 don't need the explicit prefix. */
8354 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8356 switch (i
.tm
.opcode_length
)
8359 if (i
.tm
.base_opcode
& 0xff000000)
8361 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8362 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8363 || prefix
!= REPE_PREFIX_OPCODE
8364 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8365 add_prefix (prefix
);
8369 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8371 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8372 add_prefix (prefix
);
8378 /* Check for pseudo prefixes. */
8379 as_bad_where (insn_start_frag
->fr_file
,
8380 insn_start_frag
->fr_line
,
8381 _("pseudo prefix without instruction"));
8387 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8388 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8389 R_X86_64_GOTTPOFF relocation so that linker can safely
8390 perform IE->LE optimization. */
8391 if (x86_elf_abi
== X86_64_X32_ABI
8393 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8394 && i
.prefix
[REX_PREFIX
] == 0)
8395 add_prefix (REX_OPCODE
);
8398 /* The prefix bytes. */
8399 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8401 FRAG_APPEND_1_CHAR (*q
);
8405 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8410 /* REX byte is encoded in VEX prefix. */
8414 FRAG_APPEND_1_CHAR (*q
);
8417 /* There should be no other prefixes for instructions
8422 /* For EVEX instructions i.vrex should become 0 after
8423 build_evex_prefix. For VEX instructions upper 16 registers
8424 aren't available, so VREX should be 0. */
8427 /* Now the VEX prefix. */
8428 p
= frag_more (i
.vex
.length
);
8429 for (j
= 0; j
< i
.vex
.length
; j
++)
8430 p
[j
] = i
.vex
.bytes
[j
];
8433 /* Now the opcode; be careful about word order here! */
8434 if (i
.tm
.opcode_length
== 1)
8436 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8440 switch (i
.tm
.opcode_length
)
8444 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8445 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8449 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8459 /* Put out high byte first: can't use md_number_to_chars! */
8460 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8461 *p
= i
.tm
.base_opcode
& 0xff;
8464 /* Now the modrm byte and sib byte (if present). */
8465 if (i
.tm
.opcode_modifier
.modrm
)
8467 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8470 /* If i.rm.regmem == ESP (4)
8471 && i.rm.mode != (Register mode)
8473 ==> need second modrm byte. */
8474 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8476 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8477 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8479 | i
.sib
.scale
<< 6));
8482 if (i
.disp_operands
)
8483 output_disp (insn_start_frag
, insn_start_off
);
8486 output_imm (insn_start_frag
, insn_start_off
);
8489 * frag_now_fix () returning plain abs_section_offset when we're in the
8490 * absolute section, and abs_section_offset not getting updated as data
8491 * gets added to the frag breaks the logic below.
8493 if (now_seg
!= absolute_section
)
8495 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8497 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8505 pi ("" /*line*/, &i
);
8507 #endif /* DEBUG386 */
8510 /* Return the size of the displacement operand N. */
8513 disp_size (unsigned int n
)
8517 if (i
.types
[n
].bitfield
.disp64
)
8519 else if (i
.types
[n
].bitfield
.disp8
)
8521 else if (i
.types
[n
].bitfield
.disp16
)
8526 /* Return the size of the immediate operand N. */
8529 imm_size (unsigned int n
)
8532 if (i
.types
[n
].bitfield
.imm64
)
8534 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8536 else if (i
.types
[n
].bitfield
.imm16
)
8542 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8547 for (n
= 0; n
< i
.operands
; n
++)
8549 if (operand_type_check (i
.types
[n
], disp
))
8551 if (i
.op
[n
].disps
->X_op
== O_constant
)
8553 int size
= disp_size (n
);
8554 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8556 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8558 p
= frag_more (size
);
8559 md_number_to_chars (p
, val
, size
);
8563 enum bfd_reloc_code_real reloc_type
;
8564 int size
= disp_size (n
);
8565 int sign
= i
.types
[n
].bitfield
.disp32s
;
8566 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8569 /* We can't have 8 bit displacement here. */
8570 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8572 /* The PC relative address is computed relative
8573 to the instruction boundary, so in case immediate
8574 fields follows, we need to adjust the value. */
8575 if (pcrel
&& i
.imm_operands
)
8580 for (n1
= 0; n1
< i
.operands
; n1
++)
8581 if (operand_type_check (i
.types
[n1
], imm
))
8583 /* Only one immediate is allowed for PC
8584 relative address. */
8585 gas_assert (sz
== 0);
8587 i
.op
[n
].disps
->X_add_number
-= sz
;
8589 /* We should find the immediate. */
8590 gas_assert (sz
!= 0);
8593 p
= frag_more (size
);
8594 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8596 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8597 && (((reloc_type
== BFD_RELOC_32
8598 || reloc_type
== BFD_RELOC_X86_64_32S
8599 || (reloc_type
== BFD_RELOC_64
8601 && (i
.op
[n
].disps
->X_op
== O_symbol
8602 || (i
.op
[n
].disps
->X_op
== O_add
8603 && ((symbol_get_value_expression
8604 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8606 || reloc_type
== BFD_RELOC_32_PCREL
))
8610 reloc_type
= BFD_RELOC_386_GOTPC
;
8611 i
.op
[n
].imms
->X_add_number
+=
8612 encoding_length (insn_start_frag
, insn_start_off
, p
);
8614 else if (reloc_type
== BFD_RELOC_64
)
8615 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8617 /* Don't do the adjustment for x86-64, as there
8618 the pcrel addressing is relative to the _next_
8619 insn, and that is taken care of in other code. */
8620 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8622 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8623 size
, i
.op
[n
].disps
, pcrel
,
8625 /* Check for "call/jmp *mem", "mov mem, %reg",
8626 "test %reg, mem" and "binop mem, %reg" where binop
8627 is one of adc, add, and, cmp, or, sbb, sub, xor
8628 instructions without data prefix. Always generate
8629 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8630 if (i
.prefix
[DATA_PREFIX
] == 0
8631 && (generate_relax_relocations
8634 && i
.rm
.regmem
== 5))
8636 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8637 && ((i
.operands
== 1
8638 && i
.tm
.base_opcode
== 0xff
8639 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8641 && (i
.tm
.base_opcode
== 0x8b
8642 || i
.tm
.base_opcode
== 0x85
8643 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8647 fixP
->fx_tcbit
= i
.rex
!= 0;
8649 && (i
.base_reg
->reg_num
== RegIP
))
8650 fixP
->fx_tcbit2
= 1;
8653 fixP
->fx_tcbit2
= 1;
8661 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8666 for (n
= 0; n
< i
.operands
; n
++)
8668 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8669 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8672 if (operand_type_check (i
.types
[n
], imm
))
8674 if (i
.op
[n
].imms
->X_op
== O_constant
)
8676 int size
= imm_size (n
);
8679 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8681 p
= frag_more (size
);
8682 md_number_to_chars (p
, val
, size
);
8686 /* Not absolute_section.
8687 Need a 32-bit fixup (don't support 8bit
8688 non-absolute imms). Try to support other
8690 enum bfd_reloc_code_real reloc_type
;
8691 int size
= imm_size (n
);
8694 if (i
.types
[n
].bitfield
.imm32s
8695 && (i
.suffix
== QWORD_MNEM_SUFFIX
8696 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8701 p
= frag_more (size
);
8702 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8704 /* This is tough to explain. We end up with this one if we
8705 * have operands that look like
8706 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8707 * obtain the absolute address of the GOT, and it is strongly
8708 * preferable from a performance point of view to avoid using
8709 * a runtime relocation for this. The actual sequence of
8710 * instructions often look something like:
8715 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8717 * The call and pop essentially return the absolute address
8718 * of the label .L66 and store it in %ebx. The linker itself
8719 * will ultimately change the first operand of the addl so
8720 * that %ebx points to the GOT, but to keep things simple, the
8721 * .o file must have this operand set so that it generates not
8722 * the absolute address of .L66, but the absolute address of
8723 * itself. This allows the linker itself simply treat a GOTPC
8724 * relocation as asking for a pcrel offset to the GOT to be
8725 * added in, and the addend of the relocation is stored in the
8726 * operand field for the instruction itself.
8728 * Our job here is to fix the operand so that it would add
8729 * the correct offset so that %ebx would point to itself. The
8730 * thing that is tricky is that .-.L66 will point to the
8731 * beginning of the instruction, so we need to further modify
8732 * the operand so that it will point to itself. There are
8733 * other cases where you have something like:
8735 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8737 * and here no correction would be required. Internally in
8738 * the assembler we treat operands of this form as not being
8739 * pcrel since the '.' is explicitly mentioned, and I wonder
8740 * whether it would simplify matters to do it this way. Who
8741 * knows. In earlier versions of the PIC patches, the
8742 * pcrel_adjust field was used to store the correction, but
8743 * since the expression is not pcrel, I felt it would be
8744 * confusing to do it this way. */
8746 if ((reloc_type
== BFD_RELOC_32
8747 || reloc_type
== BFD_RELOC_X86_64_32S
8748 || reloc_type
== BFD_RELOC_64
)
8750 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8751 && (i
.op
[n
].imms
->X_op
== O_symbol
8752 || (i
.op
[n
].imms
->X_op
== O_add
8753 && ((symbol_get_value_expression
8754 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8758 reloc_type
= BFD_RELOC_386_GOTPC
;
8760 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8762 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8763 i
.op
[n
].imms
->X_add_number
+=
8764 encoding_length (insn_start_frag
, insn_start_off
, p
);
8766 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8767 i
.op
[n
].imms
, 0, reloc_type
);
8773 /* x86_cons_fix_new is called via the expression parsing code when a
8774 reloc is needed. We use this hook to get the correct .got reloc. */
8775 static int cons_sign
= -1;
8778 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8779 expressionS
*exp
, bfd_reloc_code_real_type r
)
8781 r
= reloc (len
, 0, cons_sign
, r
);
8784 if (exp
->X_op
== O_secrel
)
8786 exp
->X_op
= O_symbol
;
8787 r
= BFD_RELOC_32_SECREL
;
8791 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8794 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8795 purpose of the `.dc.a' internal pseudo-op. */
8798 x86_address_bytes (void)
8800 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8802 return stdoutput
->arch_info
->bits_per_address
/ 8;
8805 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8807 # define lex_got(reloc, adjust, types) NULL
8809 /* Parse operands of the form
8810 <symbol>@GOTOFF+<nnn>
8811 and similar .plt or .got references.
8813 If we find one, set up the correct relocation in RELOC and copy the
8814 input string, minus the `@GOTOFF' into a malloc'd buffer for
8815 parsing by the calling routine. Return this buffer, and if ADJUST
8816 is non-null set it to the length of the string we removed from the
8817 input line. Otherwise return NULL. */
8819 lex_got (enum bfd_reloc_code_real
*rel
,
8821 i386_operand_type
*types
)
8823 /* Some of the relocations depend on the size of what field is to
8824 be relocated. But in our callers i386_immediate and i386_displacement
8825 we don't yet know the operand size (this will be set by insn
8826 matching). Hence we record the word32 relocation here,
8827 and adjust the reloc according to the real size in reloc(). */
8828 static const struct {
8831 const enum bfd_reloc_code_real rel
[2];
8832 const i386_operand_type types64
;
8834 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8835 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8837 OPERAND_TYPE_IMM32_64
},
8839 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8840 BFD_RELOC_X86_64_PLTOFF64
},
8841 OPERAND_TYPE_IMM64
},
8842 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8843 BFD_RELOC_X86_64_PLT32
},
8844 OPERAND_TYPE_IMM32_32S_DISP32
},
8845 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8846 BFD_RELOC_X86_64_GOTPLT64
},
8847 OPERAND_TYPE_IMM64_DISP64
},
8848 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8849 BFD_RELOC_X86_64_GOTOFF64
},
8850 OPERAND_TYPE_IMM64_DISP64
},
8851 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8852 BFD_RELOC_X86_64_GOTPCREL
},
8853 OPERAND_TYPE_IMM32_32S_DISP32
},
8854 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8855 BFD_RELOC_X86_64_TLSGD
},
8856 OPERAND_TYPE_IMM32_32S_DISP32
},
8857 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8858 _dummy_first_bfd_reloc_code_real
},
8859 OPERAND_TYPE_NONE
},
8860 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8861 BFD_RELOC_X86_64_TLSLD
},
8862 OPERAND_TYPE_IMM32_32S_DISP32
},
8863 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8864 BFD_RELOC_X86_64_GOTTPOFF
},
8865 OPERAND_TYPE_IMM32_32S_DISP32
},
8866 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8867 BFD_RELOC_X86_64_TPOFF32
},
8868 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8869 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8870 _dummy_first_bfd_reloc_code_real
},
8871 OPERAND_TYPE_NONE
},
8872 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8873 BFD_RELOC_X86_64_DTPOFF32
},
8874 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8875 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8876 _dummy_first_bfd_reloc_code_real
},
8877 OPERAND_TYPE_NONE
},
8878 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8879 _dummy_first_bfd_reloc_code_real
},
8880 OPERAND_TYPE_NONE
},
8881 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8882 BFD_RELOC_X86_64_GOT32
},
8883 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8884 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8885 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8886 OPERAND_TYPE_IMM32_32S_DISP32
},
8887 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8888 BFD_RELOC_X86_64_TLSDESC_CALL
},
8889 OPERAND_TYPE_IMM32_32S_DISP32
},
8894 #if defined (OBJ_MAYBE_ELF)
8899 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8900 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8903 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8905 int len
= gotrel
[j
].len
;
8906 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8908 if (gotrel
[j
].rel
[object_64bit
] != 0)
8911 char *tmpbuf
, *past_reloc
;
8913 *rel
= gotrel
[j
].rel
[object_64bit
];
8917 if (flag_code
!= CODE_64BIT
)
8919 types
->bitfield
.imm32
= 1;
8920 types
->bitfield
.disp32
= 1;
8923 *types
= gotrel
[j
].types64
;
8926 if (j
!= 0 && GOT_symbol
== NULL
)
8927 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8929 /* The length of the first part of our input line. */
8930 first
= cp
- input_line_pointer
;
8932 /* The second part goes from after the reloc token until
8933 (and including) an end_of_line char or comma. */
8934 past_reloc
= cp
+ 1 + len
;
8936 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8938 second
= cp
+ 1 - past_reloc
;
8940 /* Allocate and copy string. The trailing NUL shouldn't
8941 be necessary, but be safe. */
8942 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8943 memcpy (tmpbuf
, input_line_pointer
, first
);
8944 if (second
!= 0 && *past_reloc
!= ' ')
8945 /* Replace the relocation token with ' ', so that
8946 errors like foo@GOTOFF1 will be detected. */
8947 tmpbuf
[first
++] = ' ';
8949 /* Increment length by 1 if the relocation token is
8954 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8955 tmpbuf
[first
+ second
] = '\0';
8959 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8960 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8965 /* Might be a symbol version string. Don't as_bad here. */
8974 /* Parse operands of the form
8975 <symbol>@SECREL32+<nnn>
8977 If we find one, set up the correct relocation in RELOC and copy the
8978 input string, minus the `@SECREL32' into a malloc'd buffer for
8979 parsing by the calling routine. Return this buffer, and if ADJUST
8980 is non-null set it to the length of the string we removed from the
8981 input line. Otherwise return NULL.
8983 This function is copied from the ELF version above adjusted for PE targets. */
8986 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8987 int *adjust ATTRIBUTE_UNUSED
,
8988 i386_operand_type
*types
)
8994 const enum bfd_reloc_code_real rel
[2];
8995 const i386_operand_type types64
;
8999 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9000 BFD_RELOC_32_SECREL
},
9001 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9007 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9008 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9011 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9013 int len
= gotrel
[j
].len
;
9015 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9017 if (gotrel
[j
].rel
[object_64bit
] != 0)
9020 char *tmpbuf
, *past_reloc
;
9022 *rel
= gotrel
[j
].rel
[object_64bit
];
9028 if (flag_code
!= CODE_64BIT
)
9030 types
->bitfield
.imm32
= 1;
9031 types
->bitfield
.disp32
= 1;
9034 *types
= gotrel
[j
].types64
;
9037 /* The length of the first part of our input line. */
9038 first
= cp
- input_line_pointer
;
9040 /* The second part goes from after the reloc token until
9041 (and including) an end_of_line char or comma. */
9042 past_reloc
= cp
+ 1 + len
;
9044 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9046 second
= cp
+ 1 - past_reloc
;
9048 /* Allocate and copy string. The trailing NUL shouldn't
9049 be necessary, but be safe. */
9050 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9051 memcpy (tmpbuf
, input_line_pointer
, first
);
9052 if (second
!= 0 && *past_reloc
!= ' ')
9053 /* Replace the relocation token with ' ', so that
9054 errors like foo@SECLREL321 will be detected. */
9055 tmpbuf
[first
++] = ' ';
9056 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9057 tmpbuf
[first
+ second
] = '\0';
9061 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9062 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9067 /* Might be a symbol version string. Don't as_bad here. */
9073 bfd_reloc_code_real_type
9074 x86_cons (expressionS
*exp
, int size
)
9076 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9078 intel_syntax
= -intel_syntax
;
9081 if (size
== 4 || (object_64bit
&& size
== 8))
9083 /* Handle @GOTOFF and the like in an expression. */
9085 char *gotfree_input_line
;
9088 save
= input_line_pointer
;
9089 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9090 if (gotfree_input_line
)
9091 input_line_pointer
= gotfree_input_line
;
9095 if (gotfree_input_line
)
9097 /* expression () has merrily parsed up to the end of line,
9098 or a comma - in the wrong buffer. Transfer how far
9099 input_line_pointer has moved to the right buffer. */
9100 input_line_pointer
= (save
9101 + (input_line_pointer
- gotfree_input_line
)
9103 free (gotfree_input_line
);
9104 if (exp
->X_op
== O_constant
9105 || exp
->X_op
== O_absent
9106 || exp
->X_op
== O_illegal
9107 || exp
->X_op
== O_register
9108 || exp
->X_op
== O_big
)
9110 char c
= *input_line_pointer
;
9111 *input_line_pointer
= 0;
9112 as_bad (_("missing or invalid expression `%s'"), save
);
9113 *input_line_pointer
= c
;
9115 else if ((got_reloc
== BFD_RELOC_386_PLT32
9116 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9117 && exp
->X_op
!= O_symbol
)
9119 char c
= *input_line_pointer
;
9120 *input_line_pointer
= 0;
9121 as_bad (_("invalid PLT expression `%s'"), save
);
9122 *input_line_pointer
= c
;
9129 intel_syntax
= -intel_syntax
;
9132 i386_intel_simplify (exp
);
9138 signed_cons (int size
)
9140 if (flag_code
== CODE_64BIT
)
9148 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9155 if (exp
.X_op
== O_symbol
)
9156 exp
.X_op
= O_secrel
;
9158 emit_expr (&exp
, 4);
9160 while (*input_line_pointer
++ == ',');
9162 input_line_pointer
--;
9163 demand_empty_rest_of_line ();
9167 /* Handle Vector operations. */
9170 check_VecOperations (char *op_string
, char *op_end
)
9172 const reg_entry
*mask
;
9177 && (op_end
== NULL
|| op_string
< op_end
))
9180 if (*op_string
== '{')
9184 /* Check broadcasts. */
9185 if (strncmp (op_string
, "1to", 3) == 0)
9190 goto duplicated_vec_op
;
9193 if (*op_string
== '8')
9195 else if (*op_string
== '4')
9197 else if (*op_string
== '2')
9199 else if (*op_string
== '1'
9200 && *(op_string
+1) == '6')
9207 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9212 broadcast_op
.type
= bcst_type
;
9213 broadcast_op
.operand
= this_operand
;
9214 broadcast_op
.bytes
= 0;
9215 i
.broadcast
= &broadcast_op
;
9217 /* Check masking operation. */
9218 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9220 /* k0 can't be used for write mask. */
9221 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9223 as_bad (_("`%s%s' can't be used for write mask"),
9224 register_prefix
, mask
->reg_name
);
9230 mask_op
.mask
= mask
;
9231 mask_op
.zeroing
= 0;
9232 mask_op
.operand
= this_operand
;
9238 goto duplicated_vec_op
;
9240 i
.mask
->mask
= mask
;
9242 /* Only "{z}" is allowed here. No need to check
9243 zeroing mask explicitly. */
9244 if (i
.mask
->operand
!= this_operand
)
9246 as_bad (_("invalid write mask `%s'"), saved
);
9253 /* Check zeroing-flag for masking operation. */
9254 else if (*op_string
== 'z')
9258 mask_op
.mask
= NULL
;
9259 mask_op
.zeroing
= 1;
9260 mask_op
.operand
= this_operand
;
9265 if (i
.mask
->zeroing
)
9268 as_bad (_("duplicated `%s'"), saved
);
9272 i
.mask
->zeroing
= 1;
9274 /* Only "{%k}" is allowed here. No need to check mask
9275 register explicitly. */
9276 if (i
.mask
->operand
!= this_operand
)
9278 as_bad (_("invalid zeroing-masking `%s'"),
9287 goto unknown_vec_op
;
9289 if (*op_string
!= '}')
9291 as_bad (_("missing `}' in `%s'"), saved
);
9296 /* Strip whitespace since the addition of pseudo prefixes
9297 changed how the scrubber treats '{'. */
9298 if (is_space_char (*op_string
))
9304 /* We don't know this one. */
9305 as_bad (_("unknown vector operation: `%s'"), saved
);
9309 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9311 as_bad (_("zeroing-masking only allowed with write mask"));
9319 i386_immediate (char *imm_start
)
9321 char *save_input_line_pointer
;
9322 char *gotfree_input_line
;
9325 i386_operand_type types
;
9327 operand_type_set (&types
, ~0);
9329 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9331 as_bad (_("at most %d immediate operands are allowed"),
9332 MAX_IMMEDIATE_OPERANDS
);
9336 exp
= &im_expressions
[i
.imm_operands
++];
9337 i
.op
[this_operand
].imms
= exp
;
9339 if (is_space_char (*imm_start
))
9342 save_input_line_pointer
= input_line_pointer
;
9343 input_line_pointer
= imm_start
;
9345 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9346 if (gotfree_input_line
)
9347 input_line_pointer
= gotfree_input_line
;
9349 exp_seg
= expression (exp
);
9353 /* Handle vector operations. */
9354 if (*input_line_pointer
== '{')
9356 input_line_pointer
= check_VecOperations (input_line_pointer
,
9358 if (input_line_pointer
== NULL
)
9362 if (*input_line_pointer
)
9363 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9365 input_line_pointer
= save_input_line_pointer
;
9366 if (gotfree_input_line
)
9368 free (gotfree_input_line
);
9370 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9371 exp
->X_op
= O_illegal
;
9374 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9378 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9379 i386_operand_type types
, const char *imm_start
)
9381 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9384 as_bad (_("missing or invalid immediate expression `%s'"),
9388 else if (exp
->X_op
== O_constant
)
9390 /* Size it properly later. */
9391 i
.types
[this_operand
].bitfield
.imm64
= 1;
9392 /* If not 64bit, sign extend val. */
9393 if (flag_code
!= CODE_64BIT
9394 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9396 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9398 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9399 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9400 && exp_seg
!= absolute_section
9401 && exp_seg
!= text_section
9402 && exp_seg
!= data_section
9403 && exp_seg
!= bss_section
9404 && exp_seg
!= undefined_section
9405 && !bfd_is_com_section (exp_seg
))
9407 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9411 else if (!intel_syntax
&& exp_seg
== reg_section
)
9414 as_bad (_("illegal immediate register operand %s"), imm_start
);
9419 /* This is an address. The size of the address will be
9420 determined later, depending on destination register,
9421 suffix, or the default for the section. */
9422 i
.types
[this_operand
].bitfield
.imm8
= 1;
9423 i
.types
[this_operand
].bitfield
.imm16
= 1;
9424 i
.types
[this_operand
].bitfield
.imm32
= 1;
9425 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9426 i
.types
[this_operand
].bitfield
.imm64
= 1;
9427 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9435 i386_scale (char *scale
)
9438 char *save
= input_line_pointer
;
9440 input_line_pointer
= scale
;
9441 val
= get_absolute_expression ();
9446 i
.log2_scale_factor
= 0;
9449 i
.log2_scale_factor
= 1;
9452 i
.log2_scale_factor
= 2;
9455 i
.log2_scale_factor
= 3;
9459 char sep
= *input_line_pointer
;
9461 *input_line_pointer
= '\0';
9462 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9464 *input_line_pointer
= sep
;
9465 input_line_pointer
= save
;
9469 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9471 as_warn (_("scale factor of %d without an index register"),
9472 1 << i
.log2_scale_factor
);
9473 i
.log2_scale_factor
= 0;
9475 scale
= input_line_pointer
;
9476 input_line_pointer
= save
;
9481 i386_displacement (char *disp_start
, char *disp_end
)
9485 char *save_input_line_pointer
;
9486 char *gotfree_input_line
;
9488 i386_operand_type bigdisp
, types
= anydisp
;
9491 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9493 as_bad (_("at most %d displacement operands are allowed"),
9494 MAX_MEMORY_OPERANDS
);
9498 operand_type_set (&bigdisp
, 0);
9499 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9500 || (!current_templates
->start
->opcode_modifier
.jump
9501 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9503 bigdisp
.bitfield
.disp32
= 1;
9504 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9505 if (flag_code
== CODE_64BIT
)
9509 bigdisp
.bitfield
.disp32s
= 1;
9510 bigdisp
.bitfield
.disp64
= 1;
9513 else if ((flag_code
== CODE_16BIT
) ^ override
)
9515 bigdisp
.bitfield
.disp32
= 0;
9516 bigdisp
.bitfield
.disp16
= 1;
9521 /* For PC-relative branches, the width of the displacement
9522 is dependent upon data size, not address size. */
9523 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9524 if (flag_code
== CODE_64BIT
)
9526 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9527 bigdisp
.bitfield
.disp16
= 1;
9530 bigdisp
.bitfield
.disp32
= 1;
9531 bigdisp
.bitfield
.disp32s
= 1;
9537 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9539 : LONG_MNEM_SUFFIX
));
9540 bigdisp
.bitfield
.disp32
= 1;
9541 if ((flag_code
== CODE_16BIT
) ^ override
)
9543 bigdisp
.bitfield
.disp32
= 0;
9544 bigdisp
.bitfield
.disp16
= 1;
9548 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9551 exp
= &disp_expressions
[i
.disp_operands
];
9552 i
.op
[this_operand
].disps
= exp
;
9554 save_input_line_pointer
= input_line_pointer
;
9555 input_line_pointer
= disp_start
;
9556 END_STRING_AND_SAVE (disp_end
);
9558 #ifndef GCC_ASM_O_HACK
9559 #define GCC_ASM_O_HACK 0
9562 END_STRING_AND_SAVE (disp_end
+ 1);
9563 if (i
.types
[this_operand
].bitfield
.baseIndex
9564 && displacement_string_end
[-1] == '+')
9566 /* This hack is to avoid a warning when using the "o"
9567 constraint within gcc asm statements.
9570 #define _set_tssldt_desc(n,addr,limit,type) \
9571 __asm__ __volatile__ ( \
9573 "movw %w1,2+%0\n\t" \
9575 "movb %b1,4+%0\n\t" \
9576 "movb %4,5+%0\n\t" \
9577 "movb $0,6+%0\n\t" \
9578 "movb %h1,7+%0\n\t" \
9580 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9582 This works great except that the output assembler ends
9583 up looking a bit weird if it turns out that there is
9584 no offset. You end up producing code that looks like:
9597 So here we provide the missing zero. */
9599 *displacement_string_end
= '0';
9602 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9603 if (gotfree_input_line
)
9604 input_line_pointer
= gotfree_input_line
;
9606 exp_seg
= expression (exp
);
9609 if (*input_line_pointer
)
9610 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9612 RESTORE_END_STRING (disp_end
+ 1);
9614 input_line_pointer
= save_input_line_pointer
;
9615 if (gotfree_input_line
)
9617 free (gotfree_input_line
);
9619 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9620 exp
->X_op
= O_illegal
;
9623 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9625 RESTORE_END_STRING (disp_end
);
9631 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9632 i386_operand_type types
, const char *disp_start
)
9634 i386_operand_type bigdisp
;
9637 /* We do this to make sure that the section symbol is in
9638 the symbol table. We will ultimately change the relocation
9639 to be relative to the beginning of the section. */
9640 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9641 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9642 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9644 if (exp
->X_op
!= O_symbol
)
9647 if (S_IS_LOCAL (exp
->X_add_symbol
)
9648 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9649 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9650 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9651 exp
->X_op
= O_subtract
;
9652 exp
->X_op_symbol
= GOT_symbol
;
9653 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9654 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9655 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9656 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9658 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9661 else if (exp
->X_op
== O_absent
9662 || exp
->X_op
== O_illegal
9663 || exp
->X_op
== O_big
)
9666 as_bad (_("missing or invalid displacement expression `%s'"),
9671 else if (flag_code
== CODE_64BIT
9672 && !i
.prefix
[ADDR_PREFIX
]
9673 && exp
->X_op
== O_constant
)
9675 /* Since displacement is signed extended to 64bit, don't allow
9676 disp32 and turn off disp32s if they are out of range. */
9677 i
.types
[this_operand
].bitfield
.disp32
= 0;
9678 if (!fits_in_signed_long (exp
->X_add_number
))
9680 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9681 if (i
.types
[this_operand
].bitfield
.baseindex
)
9683 as_bad (_("0x%lx out range of signed 32bit displacement"),
9684 (long) exp
->X_add_number
);
9690 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9691 else if (exp
->X_op
!= O_constant
9692 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9693 && exp_seg
!= absolute_section
9694 && exp_seg
!= text_section
9695 && exp_seg
!= data_section
9696 && exp_seg
!= bss_section
9697 && exp_seg
!= undefined_section
9698 && !bfd_is_com_section (exp_seg
))
9700 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9705 /* Check if this is a displacement only operand. */
9706 bigdisp
= i
.types
[this_operand
];
9707 bigdisp
.bitfield
.disp8
= 0;
9708 bigdisp
.bitfield
.disp16
= 0;
9709 bigdisp
.bitfield
.disp32
= 0;
9710 bigdisp
.bitfield
.disp32s
= 0;
9711 bigdisp
.bitfield
.disp64
= 0;
9712 if (operand_type_all_zero (&bigdisp
))
9713 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9719 /* Return the active addressing mode, taking address override and
9720 registers forming the address into consideration. Update the
9721 address override prefix if necessary. */
9723 static enum flag_code
9724 i386_addressing_mode (void)
9726 enum flag_code addr_mode
;
9728 if (i
.prefix
[ADDR_PREFIX
])
9729 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9732 addr_mode
= flag_code
;
9734 #if INFER_ADDR_PREFIX
9735 if (i
.mem_operands
== 0)
9737 /* Infer address prefix from the first memory operand. */
9738 const reg_entry
*addr_reg
= i
.base_reg
;
9740 if (addr_reg
== NULL
)
9741 addr_reg
= i
.index_reg
;
9745 if (addr_reg
->reg_type
.bitfield
.dword
)
9746 addr_mode
= CODE_32BIT
;
9747 else if (flag_code
!= CODE_64BIT
9748 && addr_reg
->reg_type
.bitfield
.word
)
9749 addr_mode
= CODE_16BIT
;
9751 if (addr_mode
!= flag_code
)
9753 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9755 /* Change the size of any displacement too. At most one
9756 of Disp16 or Disp32 is set.
9757 FIXME. There doesn't seem to be any real need for
9758 separate Disp16 and Disp32 flags. The same goes for
9759 Imm16 and Imm32. Removing them would probably clean
9760 up the code quite a lot. */
9761 if (flag_code
!= CODE_64BIT
9762 && (i
.types
[this_operand
].bitfield
.disp16
9763 || i
.types
[this_operand
].bitfield
.disp32
))
9764 i
.types
[this_operand
]
9765 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9775 /* Make sure the memory operand we've been dealt is valid.
9776 Return 1 on success, 0 on a failure. */
9779 i386_index_check (const char *operand_string
)
9781 const char *kind
= "base/index";
9782 enum flag_code addr_mode
= i386_addressing_mode ();
9784 if (current_templates
->start
->opcode_modifier
.isstring
9785 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9786 && (current_templates
->end
[-1].opcode_modifier
.isstring
9789 /* Memory operands of string insns are special in that they only allow
9790 a single register (rDI, rSI, or rBX) as their memory address. */
9791 const reg_entry
*expected_reg
;
9792 static const char *di_si
[][2] =
9798 static const char *bx
[] = { "ebx", "bx", "rbx" };
9800 kind
= "string address";
9802 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9804 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9806 if (!type
.bitfield
.baseindex
9807 || ((!i
.mem_operands
!= !intel_syntax
)
9808 && current_templates
->end
[-1].operand_types
[1]
9809 .bitfield
.baseindex
))
9810 type
= current_templates
->end
[-1].operand_types
[1];
9811 expected_reg
= hash_find (reg_hash
,
9812 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9816 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9818 if (i
.base_reg
!= expected_reg
9820 || operand_type_check (i
.types
[this_operand
], disp
))
9822 /* The second memory operand must have the same size as
9826 && !((addr_mode
== CODE_64BIT
9827 && i
.base_reg
->reg_type
.bitfield
.qword
)
9828 || (addr_mode
== CODE_32BIT
9829 ? i
.base_reg
->reg_type
.bitfield
.dword
9830 : i
.base_reg
->reg_type
.bitfield
.word
)))
9833 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9835 intel_syntax
? '[' : '(',
9837 expected_reg
->reg_name
,
9838 intel_syntax
? ']' : ')');
9845 as_bad (_("`%s' is not a valid %s expression"),
9846 operand_string
, kind
);
9851 if (addr_mode
!= CODE_16BIT
)
9853 /* 32-bit/64-bit checks. */
9855 && ((addr_mode
== CODE_64BIT
9856 ? !i
.base_reg
->reg_type
.bitfield
.qword
9857 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9858 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9859 || i
.base_reg
->reg_num
== RegIZ
))
9861 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9862 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9863 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9864 && ((addr_mode
== CODE_64BIT
9865 ? !i
.index_reg
->reg_type
.bitfield
.qword
9866 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9867 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9870 /* bndmk, bndldx, and bndstx have special restrictions. */
9871 if (current_templates
->start
->base_opcode
== 0xf30f1b
9872 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9874 /* They cannot use RIP-relative addressing. */
9875 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9877 as_bad (_("`%s' cannot be used here"), operand_string
);
9881 /* bndldx and bndstx ignore their scale factor. */
9882 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9883 && i
.log2_scale_factor
)
9884 as_warn (_("register scaling is being ignored here"));
9889 /* 16-bit checks. */
9891 && (!i
.base_reg
->reg_type
.bitfield
.word
9892 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9894 && (!i
.index_reg
->reg_type
.bitfield
.word
9895 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9897 && i
.base_reg
->reg_num
< 6
9898 && i
.index_reg
->reg_num
>= 6
9899 && i
.log2_scale_factor
== 0))))
9906 /* Handle vector immediates. */
9909 RC_SAE_immediate (const char *imm_start
)
9911 unsigned int match_found
, j
;
9912 const char *pstr
= imm_start
;
9920 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9922 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9926 rc_op
.type
= RC_NamesTable
[j
].type
;
9927 rc_op
.operand
= this_operand
;
9928 i
.rounding
= &rc_op
;
9932 as_bad (_("duplicated `%s'"), imm_start
);
9935 pstr
+= RC_NamesTable
[j
].len
;
9945 as_bad (_("Missing '}': '%s'"), imm_start
);
9948 /* RC/SAE immediate string should contain nothing more. */;
9951 as_bad (_("Junk after '}': '%s'"), imm_start
);
9955 exp
= &im_expressions
[i
.imm_operands
++];
9956 i
.op
[this_operand
].imms
= exp
;
9958 exp
->X_op
= O_constant
;
9959 exp
->X_add_number
= 0;
9960 exp
->X_add_symbol
= (symbolS
*) 0;
9961 exp
->X_op_symbol
= (symbolS
*) 0;
9963 i
.types
[this_operand
].bitfield
.imm8
= 1;
9967 /* Only string instructions can have a second memory operand, so
9968 reduce current_templates to just those if it contains any. */
9970 maybe_adjust_templates (void)
9972 const insn_template
*t
;
9974 gas_assert (i
.mem_operands
== 1);
9976 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9977 if (t
->opcode_modifier
.isstring
)
9980 if (t
< current_templates
->end
)
9982 static templates aux_templates
;
9983 bfd_boolean recheck
;
9985 aux_templates
.start
= t
;
9986 for (; t
< current_templates
->end
; ++t
)
9987 if (!t
->opcode_modifier
.isstring
)
9989 aux_templates
.end
= t
;
9991 /* Determine whether to re-check the first memory operand. */
9992 recheck
= (aux_templates
.start
!= current_templates
->start
9993 || t
!= current_templates
->end
);
9995 current_templates
= &aux_templates
;
10000 if (i
.memop1_string
!= NULL
10001 && i386_index_check (i
.memop1_string
) == 0)
10003 i
.mem_operands
= 1;
10010 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10014 i386_att_operand (char *operand_string
)
10016 const reg_entry
*r
;
10018 char *op_string
= operand_string
;
10020 if (is_space_char (*op_string
))
10023 /* We check for an absolute prefix (differentiating,
10024 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10025 if (*op_string
== ABSOLUTE_PREFIX
)
10028 if (is_space_char (*op_string
))
10030 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10033 /* Check if operand is a register. */
10034 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10036 i386_operand_type temp
;
10038 /* Check for a segment override by searching for ':' after a
10039 segment register. */
10040 op_string
= end_op
;
10041 if (is_space_char (*op_string
))
10043 if (*op_string
== ':' && r
->reg_type
.bitfield
.sreg
)
10045 switch (r
->reg_num
)
10048 i
.seg
[i
.mem_operands
] = &es
;
10051 i
.seg
[i
.mem_operands
] = &cs
;
10054 i
.seg
[i
.mem_operands
] = &ss
;
10057 i
.seg
[i
.mem_operands
] = &ds
;
10060 i
.seg
[i
.mem_operands
] = &fs
;
10063 i
.seg
[i
.mem_operands
] = &gs
;
10067 /* Skip the ':' and whitespace. */
10069 if (is_space_char (*op_string
))
10072 if (!is_digit_char (*op_string
)
10073 && !is_identifier_char (*op_string
)
10074 && *op_string
!= '('
10075 && *op_string
!= ABSOLUTE_PREFIX
)
10077 as_bad (_("bad memory operand `%s'"), op_string
);
10080 /* Handle case of %es:*foo. */
10081 if (*op_string
== ABSOLUTE_PREFIX
)
10084 if (is_space_char (*op_string
))
10086 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10088 goto do_memory_reference
;
10091 /* Handle vector operations. */
10092 if (*op_string
== '{')
10094 op_string
= check_VecOperations (op_string
, NULL
);
10095 if (op_string
== NULL
)
10101 as_bad (_("junk `%s' after register"), op_string
);
10104 temp
= r
->reg_type
;
10105 temp
.bitfield
.baseindex
= 0;
10106 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10108 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10109 i
.op
[this_operand
].regs
= r
;
10112 else if (*op_string
== REGISTER_PREFIX
)
10114 as_bad (_("bad register name `%s'"), op_string
);
10117 else if (*op_string
== IMMEDIATE_PREFIX
)
10120 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10122 as_bad (_("immediate operand illegal with absolute jump"));
10125 if (!i386_immediate (op_string
))
10128 else if (RC_SAE_immediate (operand_string
))
10130 /* If it is a RC or SAE immediate, do nothing. */
10133 else if (is_digit_char (*op_string
)
10134 || is_identifier_char (*op_string
)
10135 || *op_string
== '"'
10136 || *op_string
== '(')
10138 /* This is a memory reference of some sort. */
10141 /* Start and end of displacement string expression (if found). */
10142 char *displacement_string_start
;
10143 char *displacement_string_end
;
10146 do_memory_reference
:
10147 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10149 if ((i
.mem_operands
== 1
10150 && !current_templates
->start
->opcode_modifier
.isstring
)
10151 || i
.mem_operands
== 2)
10153 as_bad (_("too many memory references for `%s'"),
10154 current_templates
->start
->name
);
10158 /* Check for base index form. We detect the base index form by
10159 looking for an ')' at the end of the operand, searching
10160 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10162 base_string
= op_string
+ strlen (op_string
);
10164 /* Handle vector operations. */
10165 vop_start
= strchr (op_string
, '{');
10166 if (vop_start
&& vop_start
< base_string
)
10168 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10170 base_string
= vop_start
;
10174 if (is_space_char (*base_string
))
10177 /* If we only have a displacement, set-up for it to be parsed later. */
10178 displacement_string_start
= op_string
;
10179 displacement_string_end
= base_string
+ 1;
10181 if (*base_string
== ')')
10184 unsigned int parens_balanced
= 1;
10185 /* We've already checked that the number of left & right ()'s are
10186 equal, so this loop will not be infinite. */
10190 if (*base_string
== ')')
10192 if (*base_string
== '(')
10195 while (parens_balanced
);
10197 temp_string
= base_string
;
10199 /* Skip past '(' and whitespace. */
10201 if (is_space_char (*base_string
))
10204 if (*base_string
== ','
10205 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10208 displacement_string_end
= temp_string
;
10210 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10214 base_string
= end_op
;
10215 if (is_space_char (*base_string
))
10219 /* There may be an index reg or scale factor here. */
10220 if (*base_string
== ',')
10223 if (is_space_char (*base_string
))
10226 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10229 base_string
= end_op
;
10230 if (is_space_char (*base_string
))
10232 if (*base_string
== ',')
10235 if (is_space_char (*base_string
))
10238 else if (*base_string
!= ')')
10240 as_bad (_("expecting `,' or `)' "
10241 "after index register in `%s'"),
10246 else if (*base_string
== REGISTER_PREFIX
)
10248 end_op
= strchr (base_string
, ',');
10251 as_bad (_("bad register name `%s'"), base_string
);
10255 /* Check for scale factor. */
10256 if (*base_string
!= ')')
10258 char *end_scale
= i386_scale (base_string
);
10263 base_string
= end_scale
;
10264 if (is_space_char (*base_string
))
10266 if (*base_string
!= ')')
10268 as_bad (_("expecting `)' "
10269 "after scale factor in `%s'"),
10274 else if (!i
.index_reg
)
10276 as_bad (_("expecting index register or scale factor "
10277 "after `,'; got '%c'"),
10282 else if (*base_string
!= ')')
10284 as_bad (_("expecting `,' or `)' "
10285 "after base register in `%s'"),
10290 else if (*base_string
== REGISTER_PREFIX
)
10292 end_op
= strchr (base_string
, ',');
10295 as_bad (_("bad register name `%s'"), base_string
);
10300 /* If there's an expression beginning the operand, parse it,
10301 assuming displacement_string_start and
10302 displacement_string_end are meaningful. */
10303 if (displacement_string_start
!= displacement_string_end
)
10305 if (!i386_displacement (displacement_string_start
,
10306 displacement_string_end
))
10310 /* Special case for (%dx) while doing input/output op. */
10312 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10313 && i
.index_reg
== 0
10314 && i
.log2_scale_factor
== 0
10315 && i
.seg
[i
.mem_operands
] == 0
10316 && !operand_type_check (i
.types
[this_operand
], disp
))
10318 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10322 if (i386_index_check (operand_string
) == 0)
10324 i
.flags
[this_operand
] |= Operand_Mem
;
10325 if (i
.mem_operands
== 0)
10326 i
.memop1_string
= xstrdup (operand_string
);
10331 /* It's not a memory operand; argh! */
10332 as_bad (_("invalid char %s beginning operand %d `%s'"),
10333 output_invalid (*op_string
),
10338 return 1; /* Normal return. */
10341 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10342 that an rs_machine_dependent frag may reach. */
10345 i386_frag_max_var (fragS
*frag
)
10347 /* The only relaxable frags are for jumps.
10348 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10349 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10350 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10355 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10357 /* STT_GNU_IFUNC symbol must go through PLT. */
10358 if ((symbol_get_bfdsym (fr_symbol
)->flags
10359 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10362 if (!S_IS_EXTERNAL (fr_symbol
))
10363 /* Symbol may be weak or local. */
10364 return !S_IS_WEAK (fr_symbol
);
10366 /* Global symbols with non-default visibility can't be preempted. */
10367 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10370 if (fr_var
!= NO_RELOC
)
10371 switch ((enum bfd_reloc_code_real
) fr_var
)
10373 case BFD_RELOC_386_PLT32
:
10374 case BFD_RELOC_X86_64_PLT32
:
10375 /* Symbol with PLT relocation may be preempted. */
10381 /* Global symbols with default visibility in a shared library may be
10382 preempted by another definition. */
10387 /* md_estimate_size_before_relax()
10389 Called just before relax() for rs_machine_dependent frags. The x86
10390 assembler uses these frags to handle variable size jump
10393 Any symbol that is now undefined will not become defined.
10394 Return the correct fr_subtype in the frag.
10395 Return the initial "guess for variable size of frag" to caller.
10396 The guess is actually the growth beyond the fixed part. Whatever
10397 we do to grow the fixed or variable part contributes to our
10401 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10403 /* We've already got fragP->fr_subtype right; all we have to do is
10404 check for un-relaxable symbols. On an ELF system, we can't relax
10405 an externally visible symbol, because it may be overridden by a
10407 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10410 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10413 #if defined (OBJ_COFF) && defined (TE_PE)
10414 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10415 && S_IS_WEAK (fragP
->fr_symbol
))
10419 /* Symbol is undefined in this segment, or we need to keep a
10420 reloc so that weak symbols can be overridden. */
10421 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10422 enum bfd_reloc_code_real reloc_type
;
10423 unsigned char *opcode
;
10426 if (fragP
->fr_var
!= NO_RELOC
)
10427 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10428 else if (size
== 2)
10429 reloc_type
= BFD_RELOC_16_PCREL
;
10430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10431 else if (need_plt32_p (fragP
->fr_symbol
))
10432 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10435 reloc_type
= BFD_RELOC_32_PCREL
;
10437 old_fr_fix
= fragP
->fr_fix
;
10438 opcode
= (unsigned char *) fragP
->fr_opcode
;
10440 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10443 /* Make jmp (0xeb) a (d)word displacement jump. */
10445 fragP
->fr_fix
+= size
;
10446 fix_new (fragP
, old_fr_fix
, size
,
10448 fragP
->fr_offset
, 1,
10454 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10456 /* Negate the condition, and branch past an
10457 unconditional jump. */
10460 /* Insert an unconditional jump. */
10462 /* We added two extra opcode bytes, and have a two byte
10464 fragP
->fr_fix
+= 2 + 2;
10465 fix_new (fragP
, old_fr_fix
+ 2, 2,
10467 fragP
->fr_offset
, 1,
10471 /* Fall through. */
10474 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10478 fragP
->fr_fix
+= 1;
10479 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10481 fragP
->fr_offset
, 1,
10482 BFD_RELOC_8_PCREL
);
10483 fixP
->fx_signed
= 1;
10487 /* This changes the byte-displacement jump 0x7N
10488 to the (d)word-displacement jump 0x0f,0x8N. */
10489 opcode
[1] = opcode
[0] + 0x10;
10490 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10491 /* We've added an opcode byte. */
10492 fragP
->fr_fix
+= 1 + size
;
10493 fix_new (fragP
, old_fr_fix
+ 1, size
,
10495 fragP
->fr_offset
, 1,
10500 BAD_CASE (fragP
->fr_subtype
);
10504 return fragP
->fr_fix
- old_fr_fix
;
10507 /* Guess size depending on current relax state. Initially the relax
10508 state will correspond to a short jump and we return 1, because
10509 the variable part of the frag (the branch offset) is one byte
10510 long. However, we can relax a section more than once and in that
10511 case we must either set fr_subtype back to the unrelaxed state,
10512 or return the value for the appropriate branch. */
10513 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10516 /* Called after relax() is finished.
10518 In: Address of frag.
10519 fr_type == rs_machine_dependent.
10520 fr_subtype is what the address relaxed to.
10522 Out: Any fixSs and constants are set up.
10523 Caller will turn frag into a ".space 0". */
10526 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10529 unsigned char *opcode
;
10530 unsigned char *where_to_put_displacement
= NULL
;
10531 offsetT target_address
;
10532 offsetT opcode_address
;
10533 unsigned int extension
= 0;
10534 offsetT displacement_from_opcode_start
;
10536 opcode
= (unsigned char *) fragP
->fr_opcode
;
10538 /* Address we want to reach in file space. */
10539 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10541 /* Address opcode resides at in file space. */
10542 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10544 /* Displacement from opcode start to fill into instruction. */
10545 displacement_from_opcode_start
= target_address
- opcode_address
;
10547 if ((fragP
->fr_subtype
& BIG
) == 0)
10549 /* Don't have to change opcode. */
10550 extension
= 1; /* 1 opcode + 1 displacement */
10551 where_to_put_displacement
= &opcode
[1];
10555 if (no_cond_jump_promotion
10556 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10557 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10558 _("long jump required"));
10560 switch (fragP
->fr_subtype
)
10562 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10563 extension
= 4; /* 1 opcode + 4 displacement */
10565 where_to_put_displacement
= &opcode
[1];
10568 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10569 extension
= 2; /* 1 opcode + 2 displacement */
10571 where_to_put_displacement
= &opcode
[1];
10574 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10575 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10576 extension
= 5; /* 2 opcode + 4 displacement */
10577 opcode
[1] = opcode
[0] + 0x10;
10578 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10579 where_to_put_displacement
= &opcode
[2];
10582 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10583 extension
= 3; /* 2 opcode + 2 displacement */
10584 opcode
[1] = opcode
[0] + 0x10;
10585 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10586 where_to_put_displacement
= &opcode
[2];
10589 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10594 where_to_put_displacement
= &opcode
[3];
10598 BAD_CASE (fragP
->fr_subtype
);
10603 /* If size if less then four we are sure that the operand fits,
10604 but if it's 4, then it could be that the displacement is larger
10606 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10608 && ((addressT
) (displacement_from_opcode_start
- extension
10609 + ((addressT
) 1 << 31))
10610 > (((addressT
) 2 << 31) - 1)))
10612 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10613 _("jump target out of range"));
10614 /* Make us emit 0. */
10615 displacement_from_opcode_start
= extension
;
10617 /* Now put displacement after opcode. */
10618 md_number_to_chars ((char *) where_to_put_displacement
,
10619 (valueT
) (displacement_from_opcode_start
- extension
),
10620 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10621 fragP
->fr_fix
+= extension
;
10624 /* Apply a fixup (fixP) to segment data, once it has been determined
10625 by our caller that we have all the info we need to fix it up.
10627 Parameter valP is the pointer to the value of the bits.
10629 On the 386, immediates, displacements, and data pointers are all in
10630 the same (little-endian) format, so we don't need to care about which
10631 we are handling. */
10634 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10636 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10637 valueT value
= *valP
;
10639 #if !defined (TE_Mach)
10640 if (fixP
->fx_pcrel
)
10642 switch (fixP
->fx_r_type
)
10648 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10651 case BFD_RELOC_X86_64_32S
:
10652 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10655 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10658 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10663 if (fixP
->fx_addsy
!= NULL
10664 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10665 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10666 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10667 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10668 && !use_rela_relocations
)
10670 /* This is a hack. There should be a better way to handle this.
10671 This covers for the fact that bfd_install_relocation will
10672 subtract the current location (for partial_inplace, PC relative
10673 relocations); see more below. */
10677 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10680 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10685 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10687 if ((sym_seg
== seg
10688 || (symbol_section_p (fixP
->fx_addsy
)
10689 && sym_seg
!= absolute_section
))
10690 && !generic_force_reloc (fixP
))
10692 /* Yes, we add the values in twice. This is because
10693 bfd_install_relocation subtracts them out again. I think
10694 bfd_install_relocation is broken, but I don't dare change
10696 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10700 #if defined (OBJ_COFF) && defined (TE_PE)
10701 /* For some reason, the PE format does not store a
10702 section address offset for a PC relative symbol. */
10703 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10704 || S_IS_WEAK (fixP
->fx_addsy
))
10705 value
+= md_pcrel_from (fixP
);
10708 #if defined (OBJ_COFF) && defined (TE_PE)
10709 if (fixP
->fx_addsy
!= NULL
10710 && S_IS_WEAK (fixP
->fx_addsy
)
10711 /* PR 16858: Do not modify weak function references. */
10712 && ! fixP
->fx_pcrel
)
10714 #if !defined (TE_PEP)
10715 /* For x86 PE weak function symbols are neither PC-relative
10716 nor do they set S_IS_FUNCTION. So the only reliable way
10717 to detect them is to check the flags of their containing
10719 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10720 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10724 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10728 /* Fix a few things - the dynamic linker expects certain values here,
10729 and we must not disappoint it. */
10730 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10731 if (IS_ELF
&& fixP
->fx_addsy
)
10732 switch (fixP
->fx_r_type
)
10734 case BFD_RELOC_386_PLT32
:
10735 case BFD_RELOC_X86_64_PLT32
:
10736 /* Make the jump instruction point to the address of the operand.
10737 At runtime we merely add the offset to the actual PLT entry.
10738 NB: Subtract the offset size only for jump instructions. */
10739 if (fixP
->fx_pcrel
)
10743 case BFD_RELOC_386_TLS_GD
:
10744 case BFD_RELOC_386_TLS_LDM
:
10745 case BFD_RELOC_386_TLS_IE_32
:
10746 case BFD_RELOC_386_TLS_IE
:
10747 case BFD_RELOC_386_TLS_GOTIE
:
10748 case BFD_RELOC_386_TLS_GOTDESC
:
10749 case BFD_RELOC_X86_64_TLSGD
:
10750 case BFD_RELOC_X86_64_TLSLD
:
10751 case BFD_RELOC_X86_64_GOTTPOFF
:
10752 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10753 value
= 0; /* Fully resolved at runtime. No addend. */
10755 case BFD_RELOC_386_TLS_LE
:
10756 case BFD_RELOC_386_TLS_LDO_32
:
10757 case BFD_RELOC_386_TLS_LE_32
:
10758 case BFD_RELOC_X86_64_DTPOFF32
:
10759 case BFD_RELOC_X86_64_DTPOFF64
:
10760 case BFD_RELOC_X86_64_TPOFF32
:
10761 case BFD_RELOC_X86_64_TPOFF64
:
10762 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10765 case BFD_RELOC_386_TLS_DESC_CALL
:
10766 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10767 value
= 0; /* Fully resolved at runtime. No addend. */
10768 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10772 case BFD_RELOC_VTABLE_INHERIT
:
10773 case BFD_RELOC_VTABLE_ENTRY
:
10780 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10782 #endif /* !defined (TE_Mach) */
10784 /* Are we finished with this relocation now? */
10785 if (fixP
->fx_addsy
== NULL
)
10787 #if defined (OBJ_COFF) && defined (TE_PE)
10788 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10791 /* Remember value for tc_gen_reloc. */
10792 fixP
->fx_addnumber
= value
;
10793 /* Clear out the frag for now. */
10797 else if (use_rela_relocations
)
10799 fixP
->fx_no_overflow
= 1;
10800 /* Remember value for tc_gen_reloc. */
10801 fixP
->fx_addnumber
= value
;
10805 md_number_to_chars (p
, value
, fixP
->fx_size
);
10809 md_atof (int type
, char *litP
, int *sizeP
)
10811 /* This outputs the LITTLENUMs in REVERSE order;
10812 in accord with the bigendian 386. */
10813 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10816 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10819 output_invalid (int c
)
10822 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10825 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10826 "(0x%x)", (unsigned char) c
);
10827 return output_invalid_buf
;
10830 /* REG_STRING starts *before* REGISTER_PREFIX. */
10832 static const reg_entry
*
10833 parse_real_register (char *reg_string
, char **end_op
)
10835 char *s
= reg_string
;
10837 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10838 const reg_entry
*r
;
10840 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10841 if (*s
== REGISTER_PREFIX
)
10844 if (is_space_char (*s
))
10847 p
= reg_name_given
;
10848 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10850 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10851 return (const reg_entry
*) NULL
;
10855 /* For naked regs, make sure that we are not dealing with an identifier.
10856 This prevents confusing an identifier like `eax_var' with register
10858 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10859 return (const reg_entry
*) NULL
;
10863 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10865 /* Handle floating point regs, allowing spaces in the (i) part. */
10866 if (r
== i386_regtab
/* %st is first entry of table */)
10868 if (!cpu_arch_flags
.bitfield
.cpu8087
10869 && !cpu_arch_flags
.bitfield
.cpu287
10870 && !cpu_arch_flags
.bitfield
.cpu387
)
10871 return (const reg_entry
*) NULL
;
10873 if (is_space_char (*s
))
10878 if (is_space_char (*s
))
10880 if (*s
>= '0' && *s
<= '7')
10882 int fpr
= *s
- '0';
10884 if (is_space_char (*s
))
10889 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10894 /* We have "%st(" then garbage. */
10895 return (const reg_entry
*) NULL
;
10899 if (r
== NULL
|| allow_pseudo_reg
)
10902 if (operand_type_all_zero (&r
->reg_type
))
10903 return (const reg_entry
*) NULL
;
10905 if ((r
->reg_type
.bitfield
.dword
10906 || (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
> 3)
10907 || r
->reg_type
.bitfield
.control
10908 || r
->reg_type
.bitfield
.debug
10909 || r
->reg_type
.bitfield
.test
)
10910 && !cpu_arch_flags
.bitfield
.cpui386
)
10911 return (const reg_entry
*) NULL
;
10913 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10914 return (const reg_entry
*) NULL
;
10916 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10918 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10919 return (const reg_entry
*) NULL
;
10921 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10923 if (r
->reg_type
.bitfield
.ymmword
)
10924 return (const reg_entry
*) NULL
;
10926 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10927 return (const reg_entry
*) NULL
;
10931 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10932 return (const reg_entry
*) NULL
;
10934 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10935 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10936 return (const reg_entry
*) NULL
;
10938 /* Upper 16 vector registers are only available with VREX in 64bit
10939 mode, and require EVEX encoding. */
10940 if (r
->reg_flags
& RegVRex
)
10942 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10943 || flag_code
!= CODE_64BIT
)
10944 return (const reg_entry
*) NULL
;
10946 i
.vec_encoding
= vex_encoding_evex
;
10949 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10950 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10951 && flag_code
!= CODE_64BIT
)
10952 return (const reg_entry
*) NULL
;
10954 if (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10955 return (const reg_entry
*) NULL
;
10960 /* REG_STRING starts *before* REGISTER_PREFIX. */
10962 static const reg_entry
*
10963 parse_register (char *reg_string
, char **end_op
)
10965 const reg_entry
*r
;
10967 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10968 r
= parse_real_register (reg_string
, end_op
);
10973 char *save
= input_line_pointer
;
10977 input_line_pointer
= reg_string
;
10978 c
= get_symbol_name (®_string
);
10979 symbolP
= symbol_find (reg_string
);
10980 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10982 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10984 know (e
->X_op
== O_register
);
10985 know (e
->X_add_number
>= 0
10986 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10987 r
= i386_regtab
+ e
->X_add_number
;
10988 if ((r
->reg_flags
& RegVRex
))
10989 i
.vec_encoding
= vex_encoding_evex
;
10990 *end_op
= input_line_pointer
;
10992 *input_line_pointer
= c
;
10993 input_line_pointer
= save
;
10999 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11001 const reg_entry
*r
;
11002 char *end
= input_line_pointer
;
11005 r
= parse_register (name
, &input_line_pointer
);
11006 if (r
&& end
<= input_line_pointer
)
11008 *nextcharP
= *input_line_pointer
;
11009 *input_line_pointer
= 0;
11010 e
->X_op
= O_register
;
11011 e
->X_add_number
= r
- i386_regtab
;
11014 input_line_pointer
= end
;
11016 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11020 md_operand (expressionS
*e
)
11023 const reg_entry
*r
;
11025 switch (*input_line_pointer
)
11027 case REGISTER_PREFIX
:
11028 r
= parse_real_register (input_line_pointer
, &end
);
11031 e
->X_op
= O_register
;
11032 e
->X_add_number
= r
- i386_regtab
;
11033 input_line_pointer
= end
;
11038 gas_assert (intel_syntax
);
11039 end
= input_line_pointer
++;
11041 if (*input_line_pointer
== ']')
11043 ++input_line_pointer
;
11044 e
->X_op_symbol
= make_expr_symbol (e
);
11045 e
->X_add_symbol
= NULL
;
11046 e
->X_add_number
= 0;
11051 e
->X_op
= O_absent
;
11052 input_line_pointer
= end
;
11059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11060 const char *md_shortopts
= "kVQ:sqnO::";
11062 const char *md_shortopts
= "qnO::";
11065 #define OPTION_32 (OPTION_MD_BASE + 0)
11066 #define OPTION_64 (OPTION_MD_BASE + 1)
11067 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11068 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11069 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11070 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11071 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11072 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11073 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11074 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11075 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11076 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11077 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11078 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11079 #define OPTION_X32 (OPTION_MD_BASE + 14)
11080 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11081 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11082 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11083 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11084 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11085 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11086 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11087 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11088 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11089 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11090 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11091 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11093 struct option md_longopts
[] =
11095 {"32", no_argument
, NULL
, OPTION_32
},
11096 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11097 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11098 {"64", no_argument
, NULL
, OPTION_64
},
11100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11101 {"x32", no_argument
, NULL
, OPTION_X32
},
11102 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11103 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11105 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11106 {"march", required_argument
, NULL
, OPTION_MARCH
},
11107 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11108 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11109 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11110 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11111 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11112 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11113 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11114 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11115 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11116 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11117 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11118 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11119 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11120 # if defined (TE_PE) || defined (TE_PEP)
11121 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11123 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11124 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11125 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11126 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11127 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11128 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11129 {NULL
, no_argument
, NULL
, 0}
11131 size_t md_longopts_size
= sizeof (md_longopts
);
11134 md_parse_option (int c
, const char *arg
)
11137 char *arch
, *next
, *saved
;
11142 optimize_align_code
= 0;
11146 quiet_warnings
= 1;
11149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11150 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11151 should be emitted or not. FIXME: Not implemented. */
11153 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11157 /* -V: SVR4 argument to print version ID. */
11159 print_version_id ();
11162 /* -k: Ignore for FreeBSD compatibility. */
11167 /* -s: On i386 Solaris, this tells the native assembler to use
11168 .stab instead of .stab.excl. We always use .stab anyhow. */
11171 case OPTION_MSHARED
:
11175 case OPTION_X86_USED_NOTE
:
11176 if (strcasecmp (arg
, "yes") == 0)
11178 else if (strcasecmp (arg
, "no") == 0)
11181 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11186 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11187 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11190 const char **list
, **l
;
11192 list
= bfd_target_list ();
11193 for (l
= list
; *l
!= NULL
; l
++)
11194 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11195 || strcmp (*l
, "coff-x86-64") == 0
11196 || strcmp (*l
, "pe-x86-64") == 0
11197 || strcmp (*l
, "pei-x86-64") == 0
11198 || strcmp (*l
, "mach-o-x86-64") == 0)
11200 default_arch
= "x86_64";
11204 as_fatal (_("no compiled in support for x86_64"));
11210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11214 const char **list
, **l
;
11216 list
= bfd_target_list ();
11217 for (l
= list
; *l
!= NULL
; l
++)
11218 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11220 default_arch
= "x86_64:32";
11224 as_fatal (_("no compiled in support for 32bit x86_64"));
11228 as_fatal (_("32bit x86_64 is only supported for ELF"));
11233 default_arch
= "i386";
11236 case OPTION_DIVIDE
:
11237 #ifdef SVR4_COMMENT_CHARS
11242 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11244 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11248 i386_comment_chars
= n
;
11254 saved
= xstrdup (arg
);
11256 /* Allow -march=+nosse. */
11262 as_fatal (_("invalid -march= option: `%s'"), arg
);
11263 next
= strchr (arch
, '+');
11266 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11268 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11271 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11274 cpu_arch_name
= cpu_arch
[j
].name
;
11275 cpu_sub_arch_name
= NULL
;
11276 cpu_arch_flags
= cpu_arch
[j
].flags
;
11277 cpu_arch_isa
= cpu_arch
[j
].type
;
11278 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11279 if (!cpu_arch_tune_set
)
11281 cpu_arch_tune
= cpu_arch_isa
;
11282 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11286 else if (*cpu_arch
[j
].name
== '.'
11287 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11289 /* ISA extension. */
11290 i386_cpu_flags flags
;
11292 flags
= cpu_flags_or (cpu_arch_flags
,
11293 cpu_arch
[j
].flags
);
11295 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11297 if (cpu_sub_arch_name
)
11299 char *name
= cpu_sub_arch_name
;
11300 cpu_sub_arch_name
= concat (name
,
11302 (const char *) NULL
);
11306 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11307 cpu_arch_flags
= flags
;
11308 cpu_arch_isa_flags
= flags
;
11312 = cpu_flags_or (cpu_arch_isa_flags
,
11313 cpu_arch
[j
].flags
);
11318 if (j
>= ARRAY_SIZE (cpu_arch
))
11320 /* Disable an ISA extension. */
11321 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11322 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11324 i386_cpu_flags flags
;
11326 flags
= cpu_flags_and_not (cpu_arch_flags
,
11327 cpu_noarch
[j
].flags
);
11328 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11330 if (cpu_sub_arch_name
)
11332 char *name
= cpu_sub_arch_name
;
11333 cpu_sub_arch_name
= concat (arch
,
11334 (const char *) NULL
);
11338 cpu_sub_arch_name
= xstrdup (arch
);
11339 cpu_arch_flags
= flags
;
11340 cpu_arch_isa_flags
= flags
;
11345 if (j
>= ARRAY_SIZE (cpu_noarch
))
11346 j
= ARRAY_SIZE (cpu_arch
);
11349 if (j
>= ARRAY_SIZE (cpu_arch
))
11350 as_fatal (_("invalid -march= option: `%s'"), arg
);
11354 while (next
!= NULL
);
11360 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11361 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11363 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11365 cpu_arch_tune_set
= 1;
11366 cpu_arch_tune
= cpu_arch
[j
].type
;
11367 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11371 if (j
>= ARRAY_SIZE (cpu_arch
))
11372 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11375 case OPTION_MMNEMONIC
:
11376 if (strcasecmp (arg
, "att") == 0)
11377 intel_mnemonic
= 0;
11378 else if (strcasecmp (arg
, "intel") == 0)
11379 intel_mnemonic
= 1;
11381 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11384 case OPTION_MSYNTAX
:
11385 if (strcasecmp (arg
, "att") == 0)
11387 else if (strcasecmp (arg
, "intel") == 0)
11390 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11393 case OPTION_MINDEX_REG
:
11394 allow_index_reg
= 1;
11397 case OPTION_MNAKED_REG
:
11398 allow_naked_reg
= 1;
11401 case OPTION_MSSE2AVX
:
11405 case OPTION_MSSE_CHECK
:
11406 if (strcasecmp (arg
, "error") == 0)
11407 sse_check
= check_error
;
11408 else if (strcasecmp (arg
, "warning") == 0)
11409 sse_check
= check_warning
;
11410 else if (strcasecmp (arg
, "none") == 0)
11411 sse_check
= check_none
;
11413 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11416 case OPTION_MOPERAND_CHECK
:
11417 if (strcasecmp (arg
, "error") == 0)
11418 operand_check
= check_error
;
11419 else if (strcasecmp (arg
, "warning") == 0)
11420 operand_check
= check_warning
;
11421 else if (strcasecmp (arg
, "none") == 0)
11422 operand_check
= check_none
;
11424 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11427 case OPTION_MAVXSCALAR
:
11428 if (strcasecmp (arg
, "128") == 0)
11429 avxscalar
= vex128
;
11430 else if (strcasecmp (arg
, "256") == 0)
11431 avxscalar
= vex256
;
11433 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11436 case OPTION_MVEXWIG
:
11437 if (strcmp (arg
, "0") == 0)
11439 else if (strcmp (arg
, "1") == 0)
11442 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11445 case OPTION_MADD_BND_PREFIX
:
11446 add_bnd_prefix
= 1;
11449 case OPTION_MEVEXLIG
:
11450 if (strcmp (arg
, "128") == 0)
11451 evexlig
= evexl128
;
11452 else if (strcmp (arg
, "256") == 0)
11453 evexlig
= evexl256
;
11454 else if (strcmp (arg
, "512") == 0)
11455 evexlig
= evexl512
;
11457 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11460 case OPTION_MEVEXRCIG
:
11461 if (strcmp (arg
, "rne") == 0)
11463 else if (strcmp (arg
, "rd") == 0)
11465 else if (strcmp (arg
, "ru") == 0)
11467 else if (strcmp (arg
, "rz") == 0)
11470 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11473 case OPTION_MEVEXWIG
:
11474 if (strcmp (arg
, "0") == 0)
11476 else if (strcmp (arg
, "1") == 0)
11479 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11482 # if defined (TE_PE) || defined (TE_PEP)
11483 case OPTION_MBIG_OBJ
:
11488 case OPTION_MOMIT_LOCK_PREFIX
:
11489 if (strcasecmp (arg
, "yes") == 0)
11490 omit_lock_prefix
= 1;
11491 else if (strcasecmp (arg
, "no") == 0)
11492 omit_lock_prefix
= 0;
11494 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11497 case OPTION_MFENCE_AS_LOCK_ADD
:
11498 if (strcasecmp (arg
, "yes") == 0)
11500 else if (strcasecmp (arg
, "no") == 0)
11503 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11506 case OPTION_MRELAX_RELOCATIONS
:
11507 if (strcasecmp (arg
, "yes") == 0)
11508 generate_relax_relocations
= 1;
11509 else if (strcasecmp (arg
, "no") == 0)
11510 generate_relax_relocations
= 0;
11512 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11515 case OPTION_MAMD64
:
11519 case OPTION_MINTEL64
:
11527 /* Turn off -Os. */
11528 optimize_for_space
= 0;
11530 else if (*arg
== 's')
11532 optimize_for_space
= 1;
11533 /* Turn on all encoding optimizations. */
11534 optimize
= INT_MAX
;
11538 optimize
= atoi (arg
);
11539 /* Turn off -Os. */
11540 optimize_for_space
= 0;
11550 #define MESSAGE_TEMPLATE \
11554 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11555 int *left_p
, const char *name
, int len
)
11557 int size
= sizeof (MESSAGE_TEMPLATE
);
11558 int left
= *left_p
;
11560 /* Reserve 2 spaces for ", " or ",\0" */
11563 /* Check if there is any room. */
11571 p
= mempcpy (p
, name
, len
);
11575 /* Output the current message now and start a new one. */
11578 fprintf (stream
, "%s\n", message
);
11580 left
= size
- (start
- message
) - len
- 2;
11582 gas_assert (left
>= 0);
11584 p
= mempcpy (p
, name
, len
);
11592 show_arch (FILE *stream
, int ext
, int check
)
11594 static char message
[] = MESSAGE_TEMPLATE
;
11595 char *start
= message
+ 27;
11597 int size
= sizeof (MESSAGE_TEMPLATE
);
11604 left
= size
- (start
- message
);
11605 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11607 /* Should it be skipped? */
11608 if (cpu_arch
[j
].skip
)
11611 name
= cpu_arch
[j
].name
;
11612 len
= cpu_arch
[j
].len
;
11615 /* It is an extension. Skip if we aren't asked to show it. */
11626 /* It is an processor. Skip if we show only extension. */
11629 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11631 /* It is an impossible processor - skip. */
11635 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11638 /* Display disabled extensions. */
11640 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11642 name
= cpu_noarch
[j
].name
;
11643 len
= cpu_noarch
[j
].len
;
11644 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11649 fprintf (stream
, "%s\n", message
);
11653 md_show_usage (FILE *stream
)
11655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11656 fprintf (stream
, _("\
11657 -Qy, -Qn ignored\n\
11658 -V print assembler version number\n\
11661 fprintf (stream
, _("\
11662 -n Do not optimize code alignment\n\
11663 -q quieten some warnings\n"));
11664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11665 fprintf (stream
, _("\
11668 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11669 || defined (TE_PE) || defined (TE_PEP))
11670 fprintf (stream
, _("\
11671 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11673 #ifdef SVR4_COMMENT_CHARS
11674 fprintf (stream
, _("\
11675 --divide do not treat `/' as a comment character\n"));
11677 fprintf (stream
, _("\
11678 --divide ignored\n"));
11680 fprintf (stream
, _("\
11681 -march=CPU[,+EXTENSION...]\n\
11682 generate code for CPU and EXTENSION, CPU is one of:\n"));
11683 show_arch (stream
, 0, 1);
11684 fprintf (stream
, _("\
11685 EXTENSION is combination of:\n"));
11686 show_arch (stream
, 1, 0);
11687 fprintf (stream
, _("\
11688 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11689 show_arch (stream
, 0, 0);
11690 fprintf (stream
, _("\
11691 -msse2avx encode SSE instructions with VEX prefix\n"));
11692 fprintf (stream
, _("\
11693 -msse-check=[none|error|warning] (default: warning)\n\
11694 check SSE instructions\n"));
11695 fprintf (stream
, _("\
11696 -moperand-check=[none|error|warning] (default: warning)\n\
11697 check operand combinations for validity\n"));
11698 fprintf (stream
, _("\
11699 -mavxscalar=[128|256] (default: 128)\n\
11700 encode scalar AVX instructions with specific vector\n\
11702 fprintf (stream
, _("\
11703 -mvexwig=[0|1] (default: 0)\n\
11704 encode VEX instructions with specific VEX.W value\n\
11705 for VEX.W bit ignored instructions\n"));
11706 fprintf (stream
, _("\
11707 -mevexlig=[128|256|512] (default: 128)\n\
11708 encode scalar EVEX instructions with specific vector\n\
11710 fprintf (stream
, _("\
11711 -mevexwig=[0|1] (default: 0)\n\
11712 encode EVEX instructions with specific EVEX.W value\n\
11713 for EVEX.W bit ignored instructions\n"));
11714 fprintf (stream
, _("\
11715 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11716 encode EVEX instructions with specific EVEX.RC value\n\
11717 for SAE-only ignored instructions\n"));
11718 fprintf (stream
, _("\
11719 -mmnemonic=[att|intel] "));
11720 if (SYSV386_COMPAT
)
11721 fprintf (stream
, _("(default: att)\n"));
11723 fprintf (stream
, _("(default: intel)\n"));
11724 fprintf (stream
, _("\
11725 use AT&T/Intel mnemonic\n"));
11726 fprintf (stream
, _("\
11727 -msyntax=[att|intel] (default: att)\n\
11728 use AT&T/Intel syntax\n"));
11729 fprintf (stream
, _("\
11730 -mindex-reg support pseudo index registers\n"));
11731 fprintf (stream
, _("\
11732 -mnaked-reg don't require `%%' prefix for registers\n"));
11733 fprintf (stream
, _("\
11734 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11735 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11736 fprintf (stream
, _("\
11737 -mshared disable branch optimization for shared code\n"));
11738 fprintf (stream
, _("\
11739 -mx86-used-note=[no|yes] "));
11740 if (DEFAULT_X86_USED_NOTE
)
11741 fprintf (stream
, _("(default: yes)\n"));
11743 fprintf (stream
, _("(default: no)\n"));
11744 fprintf (stream
, _("\
11745 generate x86 used ISA and feature properties\n"));
11747 #if defined (TE_PE) || defined (TE_PEP)
11748 fprintf (stream
, _("\
11749 -mbig-obj generate big object files\n"));
11751 fprintf (stream
, _("\
11752 -momit-lock-prefix=[no|yes] (default: no)\n\
11753 strip all lock prefixes\n"));
11754 fprintf (stream
, _("\
11755 -mfence-as-lock-add=[no|yes] (default: no)\n\
11756 encode lfence, mfence and sfence as\n\
11757 lock addl $0x0, (%%{re}sp)\n"));
11758 fprintf (stream
, _("\
11759 -mrelax-relocations=[no|yes] "));
11760 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11761 fprintf (stream
, _("(default: yes)\n"));
11763 fprintf (stream
, _("(default: no)\n"));
11764 fprintf (stream
, _("\
11765 generate relax relocations\n"));
11766 fprintf (stream
, _("\
11767 -mamd64 accept only AMD64 ISA [default]\n"));
11768 fprintf (stream
, _("\
11769 -mintel64 accept only Intel64 ISA\n"));
11772 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11773 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11774 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11776 /* Pick the target format to use. */
11779 i386_target_format (void)
11781 if (!strncmp (default_arch
, "x86_64", 6))
11783 update_code_flag (CODE_64BIT
, 1);
11784 if (default_arch
[6] == '\0')
11785 x86_elf_abi
= X86_64_ABI
;
11787 x86_elf_abi
= X86_64_X32_ABI
;
11789 else if (!strcmp (default_arch
, "i386"))
11790 update_code_flag (CODE_32BIT
, 1);
11791 else if (!strcmp (default_arch
, "iamcu"))
11793 update_code_flag (CODE_32BIT
, 1);
11794 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11796 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11797 cpu_arch_name
= "iamcu";
11798 cpu_sub_arch_name
= NULL
;
11799 cpu_arch_flags
= iamcu_flags
;
11800 cpu_arch_isa
= PROCESSOR_IAMCU
;
11801 cpu_arch_isa_flags
= iamcu_flags
;
11802 if (!cpu_arch_tune_set
)
11804 cpu_arch_tune
= cpu_arch_isa
;
11805 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11808 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11809 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11813 as_fatal (_("unknown architecture"));
11815 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11816 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11817 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11818 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11820 switch (OUTPUT_FLAVOR
)
11822 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11823 case bfd_target_aout_flavour
:
11824 return AOUT_TARGET_FORMAT
;
11826 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11827 # if defined (TE_PE) || defined (TE_PEP)
11828 case bfd_target_coff_flavour
:
11829 if (flag_code
== CODE_64BIT
)
11830 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11833 # elif defined (TE_GO32)
11834 case bfd_target_coff_flavour
:
11835 return "coff-go32";
11837 case bfd_target_coff_flavour
:
11838 return "coff-i386";
11841 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11842 case bfd_target_elf_flavour
:
11844 const char *format
;
11846 switch (x86_elf_abi
)
11849 format
= ELF_TARGET_FORMAT
;
11852 use_rela_relocations
= 1;
11854 format
= ELF_TARGET_FORMAT64
;
11856 case X86_64_X32_ABI
:
11857 use_rela_relocations
= 1;
11859 disallow_64bit_reloc
= 1;
11860 format
= ELF_TARGET_FORMAT32
;
11863 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11865 if (x86_elf_abi
!= X86_64_ABI
)
11866 as_fatal (_("Intel L1OM is 64bit only"));
11867 return ELF_TARGET_L1OM_FORMAT
;
11869 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11871 if (x86_elf_abi
!= X86_64_ABI
)
11872 as_fatal (_("Intel K1OM is 64bit only"));
11873 return ELF_TARGET_K1OM_FORMAT
;
11875 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11877 if (x86_elf_abi
!= I386_ABI
)
11878 as_fatal (_("Intel MCU is 32bit only"));
11879 return ELF_TARGET_IAMCU_FORMAT
;
11885 #if defined (OBJ_MACH_O)
11886 case bfd_target_mach_o_flavour
:
11887 if (flag_code
== CODE_64BIT
)
11889 use_rela_relocations
= 1;
11891 return "mach-o-x86-64";
11894 return "mach-o-i386";
11902 #endif /* OBJ_MAYBE_ more than one */
11905 md_undefined_symbol (char *name
)
11907 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11908 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11909 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11910 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11914 if (symbol_find (name
))
11915 as_bad (_("GOT already in symbol table"));
11916 GOT_symbol
= symbol_new (name
, undefined_section
,
11917 (valueT
) 0, &zero_address_frag
);
11924 /* Round up a section size to the appropriate boundary. */
11927 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11929 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11930 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11932 /* For a.out, force the section size to be aligned. If we don't do
11933 this, BFD will align it for us, but it will not write out the
11934 final bytes of the section. This may be a bug in BFD, but it is
11935 easier to fix it here since that is how the other a.out targets
11939 align
= bfd_section_alignment (segment
);
11940 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11947 /* On the i386, PC-relative offsets are relative to the start of the
11948 next instruction. That is, the address of the offset, plus its
11949 size, since the offset is always the last part of the insn. */
11952 md_pcrel_from (fixS
*fixP
)
11954 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11960 s_bss (int ignore ATTRIBUTE_UNUSED
)
11964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11966 obj_elf_section_change_hook ();
11968 temp
= get_absolute_expression ();
11969 subseg_set (bss_section
, (subsegT
) temp
);
11970 demand_empty_rest_of_line ();
11976 i386_validate_fix (fixS
*fixp
)
11978 if (fixp
->fx_subsy
)
11980 if (fixp
->fx_subsy
== GOT_symbol
)
11982 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11987 if (fixp
->fx_tcbit2
)
11988 fixp
->fx_r_type
= (fixp
->fx_tcbit
11989 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11990 : BFD_RELOC_X86_64_GOTPCRELX
);
11993 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11998 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
12000 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
12002 fixp
->fx_subsy
= 0;
12005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12006 else if (!object_64bit
)
12008 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
12009 && fixp
->fx_tcbit2
)
12010 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12016 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12019 bfd_reloc_code_real_type code
;
12021 switch (fixp
->fx_r_type
)
12023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12024 case BFD_RELOC_SIZE32
:
12025 case BFD_RELOC_SIZE64
:
12026 if (S_IS_DEFINED (fixp
->fx_addsy
)
12027 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12029 /* Resolve size relocation against local symbol to size of
12030 the symbol plus addend. */
12031 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12032 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12033 && !fits_in_unsigned_long (value
))
12034 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12035 _("symbol size computation overflow"));
12036 fixp
->fx_addsy
= NULL
;
12037 fixp
->fx_subsy
= NULL
;
12038 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12042 /* Fall through. */
12044 case BFD_RELOC_X86_64_PLT32
:
12045 case BFD_RELOC_X86_64_GOT32
:
12046 case BFD_RELOC_X86_64_GOTPCREL
:
12047 case BFD_RELOC_X86_64_GOTPCRELX
:
12048 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12049 case BFD_RELOC_386_PLT32
:
12050 case BFD_RELOC_386_GOT32
:
12051 case BFD_RELOC_386_GOT32X
:
12052 case BFD_RELOC_386_GOTOFF
:
12053 case BFD_RELOC_386_GOTPC
:
12054 case BFD_RELOC_386_TLS_GD
:
12055 case BFD_RELOC_386_TLS_LDM
:
12056 case BFD_RELOC_386_TLS_LDO_32
:
12057 case BFD_RELOC_386_TLS_IE_32
:
12058 case BFD_RELOC_386_TLS_IE
:
12059 case BFD_RELOC_386_TLS_GOTIE
:
12060 case BFD_RELOC_386_TLS_LE_32
:
12061 case BFD_RELOC_386_TLS_LE
:
12062 case BFD_RELOC_386_TLS_GOTDESC
:
12063 case BFD_RELOC_386_TLS_DESC_CALL
:
12064 case BFD_RELOC_X86_64_TLSGD
:
12065 case BFD_RELOC_X86_64_TLSLD
:
12066 case BFD_RELOC_X86_64_DTPOFF32
:
12067 case BFD_RELOC_X86_64_DTPOFF64
:
12068 case BFD_RELOC_X86_64_GOTTPOFF
:
12069 case BFD_RELOC_X86_64_TPOFF32
:
12070 case BFD_RELOC_X86_64_TPOFF64
:
12071 case BFD_RELOC_X86_64_GOTOFF64
:
12072 case BFD_RELOC_X86_64_GOTPC32
:
12073 case BFD_RELOC_X86_64_GOT64
:
12074 case BFD_RELOC_X86_64_GOTPCREL64
:
12075 case BFD_RELOC_X86_64_GOTPC64
:
12076 case BFD_RELOC_X86_64_GOTPLT64
:
12077 case BFD_RELOC_X86_64_PLTOFF64
:
12078 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12079 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12080 case BFD_RELOC_RVA
:
12081 case BFD_RELOC_VTABLE_ENTRY
:
12082 case BFD_RELOC_VTABLE_INHERIT
:
12084 case BFD_RELOC_32_SECREL
:
12086 code
= fixp
->fx_r_type
;
12088 case BFD_RELOC_X86_64_32S
:
12089 if (!fixp
->fx_pcrel
)
12091 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12092 code
= fixp
->fx_r_type
;
12095 /* Fall through. */
12097 if (fixp
->fx_pcrel
)
12099 switch (fixp
->fx_size
)
12102 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12103 _("can not do %d byte pc-relative relocation"),
12105 code
= BFD_RELOC_32_PCREL
;
12107 case 1: code
= BFD_RELOC_8_PCREL
; break;
12108 case 2: code
= BFD_RELOC_16_PCREL
; break;
12109 case 4: code
= BFD_RELOC_32_PCREL
; break;
12111 case 8: code
= BFD_RELOC_64_PCREL
; break;
12117 switch (fixp
->fx_size
)
12120 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12121 _("can not do %d byte relocation"),
12123 code
= BFD_RELOC_32
;
12125 case 1: code
= BFD_RELOC_8
; break;
12126 case 2: code
= BFD_RELOC_16
; break;
12127 case 4: code
= BFD_RELOC_32
; break;
12129 case 8: code
= BFD_RELOC_64
; break;
12136 if ((code
== BFD_RELOC_32
12137 || code
== BFD_RELOC_32_PCREL
12138 || code
== BFD_RELOC_X86_64_32S
)
12140 && fixp
->fx_addsy
== GOT_symbol
)
12143 code
= BFD_RELOC_386_GOTPC
;
12145 code
= BFD_RELOC_X86_64_GOTPC32
;
12147 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12149 && fixp
->fx_addsy
== GOT_symbol
)
12151 code
= BFD_RELOC_X86_64_GOTPC64
;
12154 rel
= XNEW (arelent
);
12155 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12156 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12158 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12160 if (!use_rela_relocations
)
12162 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12163 vtable entry to be used in the relocation's section offset. */
12164 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12165 rel
->address
= fixp
->fx_offset
;
12166 #if defined (OBJ_COFF) && defined (TE_PE)
12167 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12168 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12173 /* Use the rela in 64bit mode. */
12176 if (disallow_64bit_reloc
)
12179 case BFD_RELOC_X86_64_DTPOFF64
:
12180 case BFD_RELOC_X86_64_TPOFF64
:
12181 case BFD_RELOC_64_PCREL
:
12182 case BFD_RELOC_X86_64_GOTOFF64
:
12183 case BFD_RELOC_X86_64_GOT64
:
12184 case BFD_RELOC_X86_64_GOTPCREL64
:
12185 case BFD_RELOC_X86_64_GOTPC64
:
12186 case BFD_RELOC_X86_64_GOTPLT64
:
12187 case BFD_RELOC_X86_64_PLTOFF64
:
12188 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12189 _("cannot represent relocation type %s in x32 mode"),
12190 bfd_get_reloc_code_name (code
));
12196 if (!fixp
->fx_pcrel
)
12197 rel
->addend
= fixp
->fx_offset
;
12201 case BFD_RELOC_X86_64_PLT32
:
12202 case BFD_RELOC_X86_64_GOT32
:
12203 case BFD_RELOC_X86_64_GOTPCREL
:
12204 case BFD_RELOC_X86_64_GOTPCRELX
:
12205 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12206 case BFD_RELOC_X86_64_TLSGD
:
12207 case BFD_RELOC_X86_64_TLSLD
:
12208 case BFD_RELOC_X86_64_GOTTPOFF
:
12209 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12210 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12211 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12214 rel
->addend
= (section
->vma
12216 + fixp
->fx_addnumber
12217 + md_pcrel_from (fixp
));
12222 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12223 if (rel
->howto
== NULL
)
12225 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12226 _("cannot represent relocation type %s"),
12227 bfd_get_reloc_code_name (code
));
12228 /* Set howto to a garbage value so that we can keep going. */
12229 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12230 gas_assert (rel
->howto
!= NULL
);
12236 #include "tc-i386-intel.c"
12239 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12241 int saved_naked_reg
;
12242 char saved_register_dot
;
12244 saved_naked_reg
= allow_naked_reg
;
12245 allow_naked_reg
= 1;
12246 saved_register_dot
= register_chars
['.'];
12247 register_chars
['.'] = '.';
12248 allow_pseudo_reg
= 1;
12249 expression_and_evaluate (exp
);
12250 allow_pseudo_reg
= 0;
12251 register_chars
['.'] = saved_register_dot
;
12252 allow_naked_reg
= saved_naked_reg
;
12254 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12256 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12258 exp
->X_op
= O_constant
;
12259 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12260 .dw2_regnum
[flag_code
>> 1];
12263 exp
->X_op
= O_illegal
;
12268 tc_x86_frame_initial_instructions (void)
12270 static unsigned int sp_regno
[2];
12272 if (!sp_regno
[flag_code
>> 1])
12274 char *saved_input
= input_line_pointer
;
12275 char sp
[][4] = {"esp", "rsp"};
12278 input_line_pointer
= sp
[flag_code
>> 1];
12279 tc_x86_parse_to_dw2regnum (&exp
);
12280 gas_assert (exp
.X_op
== O_constant
);
12281 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12282 input_line_pointer
= saved_input
;
12285 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12286 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12290 x86_dwarf2_addr_size (void)
12292 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12293 if (x86_elf_abi
== X86_64_X32_ABI
)
12296 return bfd_arch_bits_per_address (stdoutput
) / 8;
12300 i386_elf_section_type (const char *str
, size_t len
)
12302 if (flag_code
== CODE_64BIT
12303 && len
== sizeof ("unwind") - 1
12304 && strncmp (str
, "unwind", 6) == 0)
12305 return SHT_X86_64_UNWIND
;
12312 i386_solaris_fix_up_eh_frame (segT sec
)
12314 if (flag_code
== CODE_64BIT
)
12315 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12321 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12325 exp
.X_op
= O_secrel
;
12326 exp
.X_add_symbol
= symbol
;
12327 exp
.X_add_number
= 0;
12328 emit_expr (&exp
, size
);
12332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12333 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12336 x86_64_section_letter (int letter
, const char **ptr_msg
)
12338 if (flag_code
== CODE_64BIT
)
12341 return SHF_X86_64_LARGE
;
12343 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12346 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12351 x86_64_section_word (char *str
, size_t len
)
12353 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12354 return SHF_X86_64_LARGE
;
12360 handle_large_common (int small ATTRIBUTE_UNUSED
)
12362 if (flag_code
!= CODE_64BIT
)
12364 s_comm_internal (0, elf_common_parse
);
12365 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12369 static segT lbss_section
;
12370 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12371 asection
*saved_bss_section
= bss_section
;
12373 if (lbss_section
== NULL
)
12375 flagword applicable
;
12376 segT seg
= now_seg
;
12377 subsegT subseg
= now_subseg
;
12379 /* The .lbss section is for local .largecomm symbols. */
12380 lbss_section
= subseg_new (".lbss", 0);
12381 applicable
= bfd_applicable_section_flags (stdoutput
);
12382 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12383 seg_info (lbss_section
)->bss
= 1;
12385 subseg_set (seg
, subseg
);
12388 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12389 bss_section
= lbss_section
;
12391 s_comm_internal (0, elf_common_parse
);
12393 elf_com_section_ptr
= saved_com_section_ptr
;
12394 bss_section
= saved_bss_section
;
12397 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */