1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for Intel64 ISA,
542 /* 1 for intel mnemonic,
543 0 if att mnemonic. */
544 static int intel_mnemonic
= !SYSV386_COMPAT
;
546 /* 1 if support old (<= 2.8.1) versions of gcc. */
547 static int old_gcc
= OLDGCC_COMPAT
;
549 /* 1 if pseudo registers are permitted. */
550 static int allow_pseudo_reg
= 0;
552 /* 1 if register prefix % not required. */
553 static int allow_naked_reg
= 0;
555 /* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
558 static int add_bnd_prefix
= 0;
560 /* 1 if pseudo index register, eiz/riz, is allowed . */
561 static int allow_index_reg
= 0;
563 /* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565 static int omit_lock_prefix
= 0;
567 /* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569 static int avoid_fence
= 0;
571 /* 1 if the assembler should generate relax relocations. */
573 static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
576 static enum check_kind
582 sse_check
, operand_check
= check_warning
;
584 /* Register prefix used for error message. */
585 static const char *register_prefix
= "%";
587 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590 static char stackop_size
= '\0';
592 /* Non-zero to optimize code alignment. */
593 int optimize_align_code
= 1;
595 /* Non-zero to quieten some warnings. */
596 static int quiet_warnings
= 0;
599 static const char *cpu_arch_name
= NULL
;
600 static char *cpu_sub_arch_name
= NULL
;
602 /* CPU feature flags. */
603 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
605 /* If we have selected a cpu we are generating instructions for. */
606 static int cpu_arch_tune_set
= 0;
608 /* Cpu we are generating instructions for. */
609 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
611 /* CPU feature flags of cpu we are generating instructions for. */
612 static i386_cpu_flags cpu_arch_tune_flags
;
614 /* CPU instruction set architecture used. */
615 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
617 /* CPU feature flags of instruction set architecture used. */
618 i386_cpu_flags cpu_arch_isa_flags
;
620 /* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622 static unsigned int no_cond_jump_promotion
= 0;
624 /* Encode SSE instructions with VEX prefix. */
625 static unsigned int sse2avx
;
627 /* Encode scalar AVX instructions with specific vector length. */
634 /* Encode scalar EVEX LIG instructions with specific vector length. */
642 /* Encode EVEX WIG instructions with specific evex.w. */
649 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
650 static enum rc_type evexrcig
= rne
;
652 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
653 static symbolS
*GOT_symbol
;
655 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
656 unsigned int x86_dwarf2_return_column
;
658 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659 int x86_cie_data_alignment
;
661 /* Interface to relax_segment.
662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
667 #define UNCOND_JUMP 0
669 #define COND_JUMP86 2
674 #define SMALL16 (SMALL | CODE16)
676 #define BIG16 (BIG | CODE16)
680 #define INLINE __inline__
686 #define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688 #define TYPE_FROM_RELAX_STATE(s) \
690 #define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
693 /* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
701 const relax_typeS md_relax_table
[] =
704 1) most positive reach of this state,
705 2) most negative reach of this state,
706 3) how many bytes this mode will have in the variable part of the frag
707 4) which index into the table to try if we can't fit into this one. */
709 /* UNCOND_JUMP states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
725 /* word conditionals add 3 bytes to frag:
726 1 extra opcode byte, 2 displacement bytes. */
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
740 static const arch_entry cpu_arch
[] =
742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
745 CPU_GENERIC32_FLAGS
, 0 },
746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
747 CPU_GENERIC64_FLAGS
, 0 },
748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
765 CPU_PENTIUMPRO_FLAGS
, 0 },
766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
775 CPU_NOCONA_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
781 CPU_CORE2_FLAGS
, 1 },
782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
783 CPU_CORE2_FLAGS
, 0 },
784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
785 CPU_COREI7_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
791 CPU_IAMCU_FLAGS
, 0 },
792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
797 CPU_ATHLON_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
805 CPU_AMDFAM10_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
807 CPU_BDVER1_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
809 CPU_BDVER2_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
811 CPU_BDVER3_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
813 CPU_BDVER4_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
815 CPU_ZNVER1_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
817 CPU_BTVER1_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
819 CPU_BTVER2_FLAGS
, 0 },
820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
832 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
834 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
836 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
837 CPU_SSSE3_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
839 CPU_SSE4_1_FLAGS
, 0 },
840 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
841 CPU_SSE4_2_FLAGS
, 0 },
842 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
843 CPU_SSE4_2_FLAGS
, 0 },
844 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512F_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512CD_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512ER_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512PF_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
857 CPU_AVX512DQ_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
859 CPU_AVX512BW_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
861 CPU_AVX512VL_FLAGS
, 0 },
862 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
865 CPU_VMFUNC_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVE_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
871 CPU_XSAVEOPT_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
873 CPU_XSAVEC_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
875 CPU_XSAVES_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
879 CPU_PCLMUL_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
881 CPU_PCLMUL_FLAGS
, 1 },
882 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
883 CPU_FSGSBASE_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
885 CPU_RDRND_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
899 CPU_MOVBE_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
905 CPU_LZCNT_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
911 CPU_INVPCID_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
913 CPU_CLFLUSH_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
917 CPU_SYSCALL_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
919 CPU_RDTSCP_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
921 CPU_3DNOW_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
923 CPU_3DNOWA_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
925 CPU_PADLOCK_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
931 CPU_SSE4A_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
941 CPU_RDSEED_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
943 CPU_PRFCHW_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
951 CPU_CLFLUSHOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
953 CPU_PREFETCHWT1_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
959 CPU_PCOMMIT_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
961 CPU_AVX512IFMA_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
963 CPU_AVX512VBMI_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
965 CPU_CLZERO_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
967 CPU_MWAITX_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
969 CPU_OSPKE_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
971 CPU_RDPID_FLAGS
, 0 },
974 static const noarch_entry cpu_noarch
[] =
976 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
977 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
978 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
979 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
980 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
981 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
982 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
983 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
984 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
985 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
986 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
987 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
988 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
989 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
990 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
991 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
992 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
993 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
994 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
995 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
996 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1002 /* Like s_lcomm_internal in gas/read.c but the alignment string
1003 is allowed to be optional. */
1006 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1013 && *input_line_pointer
== ',')
1015 align
= parse_align (needs_align
- 1);
1017 if (align
== (addressT
) -1)
1032 bss_alloc (symbolP
, size
, align
);
1037 pe_lcomm (int needs_align
)
1039 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1043 const pseudo_typeS md_pseudo_table
[] =
1045 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1046 {"align", s_align_bytes
, 0},
1048 {"align", s_align_ptwo
, 0},
1050 {"arch", set_cpu_arch
, 0},
1054 {"lcomm", pe_lcomm
, 1},
1056 {"ffloat", float_cons
, 'f'},
1057 {"dfloat", float_cons
, 'd'},
1058 {"tfloat", float_cons
, 'x'},
1060 {"slong", signed_cons
, 4},
1061 {"noopt", s_ignore
, 0},
1062 {"optim", s_ignore
, 0},
1063 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1064 {"code16", set_code_flag
, CODE_16BIT
},
1065 {"code32", set_code_flag
, CODE_32BIT
},
1066 {"code64", set_code_flag
, CODE_64BIT
},
1067 {"intel_syntax", set_intel_syntax
, 1},
1068 {"att_syntax", set_intel_syntax
, 0},
1069 {"intel_mnemonic", set_intel_mnemonic
, 1},
1070 {"att_mnemonic", set_intel_mnemonic
, 0},
1071 {"allow_index_reg", set_allow_index_reg
, 1},
1072 {"disallow_index_reg", set_allow_index_reg
, 0},
1073 {"sse_check", set_check
, 0},
1074 {"operand_check", set_check
, 1},
1075 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1076 {"largecomm", handle_large_common
, 0},
1078 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1079 {"loc", dwarf2_directive_loc
, 0},
1080 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1083 {"secrel32", pe_directive_secrel
, 0},
1088 /* For interface with expression (). */
1089 extern char *input_line_pointer
;
1091 /* Hash table for instruction mnemonic lookup. */
1092 static struct hash_control
*op_hash
;
1094 /* Hash table for register lookup. */
1095 static struct hash_control
*reg_hash
;
1098 i386_align_code (fragS
*fragP
, int count
)
1100 /* Various efficient no-op patterns for aligning code labels.
1101 Note: Don't try to assemble the instructions in the comments.
1102 0L and 0w are not legal. */
1103 static const unsigned char f32_1
[] =
1105 static const unsigned char f32_2
[] =
1106 {0x66,0x90}; /* xchg %ax,%ax */
1107 static const unsigned char f32_3
[] =
1108 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1109 static const unsigned char f32_4
[] =
1110 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1111 static const unsigned char f32_5
[] =
1113 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1114 static const unsigned char f32_6
[] =
1115 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1116 static const unsigned char f32_7
[] =
1117 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1118 static const unsigned char f32_8
[] =
1120 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1121 static const unsigned char f32_9
[] =
1122 {0x89,0xf6, /* movl %esi,%esi */
1123 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1124 static const unsigned char f32_10
[] =
1125 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1127 static const unsigned char f32_11
[] =
1128 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1130 static const unsigned char f32_12
[] =
1131 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1132 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1133 static const unsigned char f32_13
[] =
1134 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1135 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1136 static const unsigned char f32_14
[] =
1137 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1139 static const unsigned char f16_3
[] =
1140 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1141 static const unsigned char f16_4
[] =
1142 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1143 static const unsigned char f16_5
[] =
1145 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1146 static const unsigned char f16_6
[] =
1147 {0x89,0xf6, /* mov %si,%si */
1148 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1149 static const unsigned char f16_7
[] =
1150 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1151 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1152 static const unsigned char f16_8
[] =
1153 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1154 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1155 static const unsigned char jump_31
[] =
1156 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1157 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1158 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1159 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1160 static const unsigned char *const f32_patt
[] = {
1161 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1162 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1164 static const unsigned char *const f16_patt
[] = {
1165 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1167 /* nopl (%[re]ax) */
1168 static const unsigned char alt_3
[] =
1170 /* nopl 0(%[re]ax) */
1171 static const unsigned char alt_4
[] =
1172 {0x0f,0x1f,0x40,0x00};
1173 /* nopl 0(%[re]ax,%[re]ax,1) */
1174 static const unsigned char alt_5
[] =
1175 {0x0f,0x1f,0x44,0x00,0x00};
1176 /* nopw 0(%[re]ax,%[re]ax,1) */
1177 static const unsigned char alt_6
[] =
1178 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopl 0L(%[re]ax) */
1180 static const unsigned char alt_7
[] =
1181 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1182 /* nopl 0L(%[re]ax,%[re]ax,1) */
1183 static const unsigned char alt_8
[] =
1184 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1185 /* nopw 0L(%[re]ax,%[re]ax,1) */
1186 static const unsigned char alt_9
[] =
1187 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1188 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1189 static const unsigned char alt_10
[] =
1190 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 static const unsigned char *const alt_patt
[] = {
1192 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1196 /* Only align for at least a positive non-zero boundary. */
1197 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1200 /* We need to decide which NOP sequence to use for 32bit and
1201 64bit. When -mtune= is used:
1203 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1204 PROCESSOR_GENERIC32, f32_patt will be used.
1205 2. For the rest, alt_patt will be used.
1207 When -mtune= isn't used, alt_patt will be used if
1208 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1211 When -march= or .arch is used, we can't use anything beyond
1212 cpu_arch_isa_flags. */
1214 if (flag_code
== CODE_16BIT
)
1218 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1220 /* Adjust jump offset. */
1221 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1224 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1225 f16_patt
[count
- 1], count
);
1229 const unsigned char *const *patt
= NULL
;
1231 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1233 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1234 switch (cpu_arch_tune
)
1236 case PROCESSOR_UNKNOWN
:
1237 /* We use cpu_arch_isa_flags to check if we SHOULD
1238 optimize with nops. */
1239 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1244 case PROCESSOR_PENTIUM4
:
1245 case PROCESSOR_NOCONA
:
1246 case PROCESSOR_CORE
:
1247 case PROCESSOR_CORE2
:
1248 case PROCESSOR_COREI7
:
1249 case PROCESSOR_L1OM
:
1250 case PROCESSOR_K1OM
:
1251 case PROCESSOR_GENERIC64
:
1253 case PROCESSOR_ATHLON
:
1255 case PROCESSOR_AMDFAM10
:
1257 case PROCESSOR_ZNVER
:
1261 case PROCESSOR_I386
:
1262 case PROCESSOR_I486
:
1263 case PROCESSOR_PENTIUM
:
1264 case PROCESSOR_PENTIUMPRO
:
1265 case PROCESSOR_IAMCU
:
1266 case PROCESSOR_GENERIC32
:
1273 switch (fragP
->tc_frag_data
.tune
)
1275 case PROCESSOR_UNKNOWN
:
1276 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1277 PROCESSOR_UNKNOWN. */
1281 case PROCESSOR_I386
:
1282 case PROCESSOR_I486
:
1283 case PROCESSOR_PENTIUM
:
1284 case PROCESSOR_IAMCU
:
1286 case PROCESSOR_ATHLON
:
1288 case PROCESSOR_AMDFAM10
:
1290 case PROCESSOR_ZNVER
:
1292 case PROCESSOR_GENERIC32
:
1293 /* We use cpu_arch_isa_flags to check if we CAN optimize
1295 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1300 case PROCESSOR_PENTIUMPRO
:
1301 case PROCESSOR_PENTIUM4
:
1302 case PROCESSOR_NOCONA
:
1303 case PROCESSOR_CORE
:
1304 case PROCESSOR_CORE2
:
1305 case PROCESSOR_COREI7
:
1306 case PROCESSOR_L1OM
:
1307 case PROCESSOR_K1OM
:
1308 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1313 case PROCESSOR_GENERIC64
:
1319 if (patt
== f32_patt
)
1321 /* If the padding is less than 15 bytes, we use the normal
1322 ones. Otherwise, we use a jump instruction and adjust
1326 /* For 64bit, the limit is 3 bytes. */
1327 if (flag_code
== CODE_64BIT
1328 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1333 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1334 patt
[count
- 1], count
);
1337 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1339 /* Adjust jump offset. */
1340 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1345 /* Maximum length of an instruction is 10 byte. If the
1346 padding is greater than 10 bytes and we don't use jump,
1347 we have to break it into smaller pieces. */
1348 int padding
= count
;
1349 while (padding
> 10)
1352 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1358 patt
[padding
- 1], padding
);
1361 fragP
->fr_var
= count
;
1365 operand_type_all_zero (const union i386_operand_type
*x
)
1367 switch (ARRAY_SIZE(x
->array
))
1376 return !x
->array
[0];
1383 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1385 switch (ARRAY_SIZE(x
->array
))
1400 operand_type_equal (const union i386_operand_type
*x
,
1401 const union i386_operand_type
*y
)
1403 switch (ARRAY_SIZE(x
->array
))
1406 if (x
->array
[2] != y
->array
[2])
1409 if (x
->array
[1] != y
->array
[1])
1412 return x
->array
[0] == y
->array
[0];
1420 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1422 switch (ARRAY_SIZE(x
->array
))
1431 return !x
->array
[0];
1438 cpu_flags_equal (const union i386_cpu_flags
*x
,
1439 const union i386_cpu_flags
*y
)
1441 switch (ARRAY_SIZE(x
->array
))
1444 if (x
->array
[2] != y
->array
[2])
1447 if (x
->array
[1] != y
->array
[1])
1450 return x
->array
[0] == y
->array
[0];
1458 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1460 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1461 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1464 static INLINE i386_cpu_flags
1465 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1467 switch (ARRAY_SIZE (x
.array
))
1470 x
.array
[2] &= y
.array
[2];
1472 x
.array
[1] &= y
.array
[1];
1474 x
.array
[0] &= y
.array
[0];
1482 static INLINE i386_cpu_flags
1483 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1485 switch (ARRAY_SIZE (x
.array
))
1488 x
.array
[2] |= y
.array
[2];
1490 x
.array
[1] |= y
.array
[1];
1492 x
.array
[0] |= y
.array
[0];
1500 static INLINE i386_cpu_flags
1501 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1503 switch (ARRAY_SIZE (x
.array
))
1506 x
.array
[2] &= ~y
.array
[2];
1508 x
.array
[1] &= ~y
.array
[1];
1510 x
.array
[0] &= ~y
.array
[0];
1519 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1521 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1523 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1524 i386_cpu_flags compat_flags
;
1525 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1526 return cpu_flags_all_zero (&compat_flags
);
1532 #define CPU_FLAGS_ARCH_MATCH 0x1
1533 #define CPU_FLAGS_64BIT_MATCH 0x2
1534 #define CPU_FLAGS_AES_MATCH 0x4
1535 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1536 #define CPU_FLAGS_AVX_MATCH 0x10
1538 #define CPU_FLAGS_32BIT_MATCH \
1539 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1540 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1541 #define CPU_FLAGS_PERFECT_MATCH \
1542 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1544 /* Return CPU flags match bits. */
1547 cpu_flags_match (const insn_template
*t
)
1549 i386_cpu_flags x
= t
->cpu_flags
;
1550 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1552 x
.bitfield
.cpu64
= 0;
1553 x
.bitfield
.cpuno64
= 0;
1555 if (cpu_flags_all_zero (&x
))
1557 /* This instruction is available on all archs. */
1558 match
|= CPU_FLAGS_32BIT_MATCH
;
1562 /* This instruction is available only on some archs. */
1563 i386_cpu_flags cpu
= cpu_arch_flags
;
1565 cpu
= cpu_flags_and (x
, cpu
);
1566 if (!cpu_flags_all_zero (&cpu
))
1568 if (x
.bitfield
.cpuavx
)
1570 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1571 if (cpu
.bitfield
.cpuavx
)
1573 /* Check SSE2AVX. */
1574 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1576 match
|= (CPU_FLAGS_ARCH_MATCH
1577 | CPU_FLAGS_AVX_MATCH
);
1579 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1580 match
|= CPU_FLAGS_AES_MATCH
;
1582 if (!x
.bitfield
.cpupclmul
1583 || cpu
.bitfield
.cpupclmul
)
1584 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1588 match
|= CPU_FLAGS_ARCH_MATCH
;
1590 else if (x
.bitfield
.cpuavx512vl
)
1592 /* Match AVX512VL. */
1593 if (cpu
.bitfield
.cpuavx512vl
)
1595 /* Need another match. */
1596 cpu
.bitfield
.cpuavx512vl
= 0;
1597 if (!cpu_flags_all_zero (&cpu
))
1598 match
|= CPU_FLAGS_32BIT_MATCH
;
1600 match
|= CPU_FLAGS_ARCH_MATCH
;
1603 match
|= CPU_FLAGS_ARCH_MATCH
;
1606 match
|= CPU_FLAGS_32BIT_MATCH
;
1612 static INLINE i386_operand_type
1613 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1615 switch (ARRAY_SIZE (x
.array
))
1618 x
.array
[2] &= y
.array
[2];
1620 x
.array
[1] &= y
.array
[1];
1622 x
.array
[0] &= y
.array
[0];
1630 static INLINE i386_operand_type
1631 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1633 switch (ARRAY_SIZE (x
.array
))
1636 x
.array
[2] |= y
.array
[2];
1638 x
.array
[1] |= y
.array
[1];
1640 x
.array
[0] |= y
.array
[0];
1648 static INLINE i386_operand_type
1649 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1651 switch (ARRAY_SIZE (x
.array
))
1654 x
.array
[2] ^= y
.array
[2];
1656 x
.array
[1] ^= y
.array
[1];
1658 x
.array
[0] ^= y
.array
[0];
1666 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1667 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1668 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1669 static const i386_operand_type inoutportreg
1670 = OPERAND_TYPE_INOUTPORTREG
;
1671 static const i386_operand_type reg16_inoutportreg
1672 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1673 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1674 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1675 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1676 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1677 static const i386_operand_type anydisp
1678 = OPERAND_TYPE_ANYDISP
;
1679 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1680 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1681 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1682 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1683 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1684 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1685 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1686 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1687 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1688 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1689 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1690 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1691 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1692 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1703 operand_type_check (i386_operand_type t
, enum operand_type c
)
1708 return (t
.bitfield
.reg8
1711 || t
.bitfield
.reg64
);
1714 return (t
.bitfield
.imm8
1718 || t
.bitfield
.imm32s
1719 || t
.bitfield
.imm64
);
1722 return (t
.bitfield
.disp8
1723 || t
.bitfield
.disp16
1724 || t
.bitfield
.disp32
1725 || t
.bitfield
.disp32s
1726 || t
.bitfield
.disp64
);
1729 return (t
.bitfield
.disp8
1730 || t
.bitfield
.disp16
1731 || t
.bitfield
.disp32
1732 || t
.bitfield
.disp32s
1733 || t
.bitfield
.disp64
1734 || t
.bitfield
.baseindex
);
1743 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1744 operand J for instruction template T. */
1747 match_reg_size (const insn_template
*t
, unsigned int j
)
1749 return !((i
.types
[j
].bitfield
.byte
1750 && !t
->operand_types
[j
].bitfield
.byte
)
1751 || (i
.types
[j
].bitfield
.word
1752 && !t
->operand_types
[j
].bitfield
.word
)
1753 || (i
.types
[j
].bitfield
.dword
1754 && !t
->operand_types
[j
].bitfield
.dword
)
1755 || (i
.types
[j
].bitfield
.qword
1756 && !t
->operand_types
[j
].bitfield
.qword
));
1759 /* Return 1 if there is no conflict in any size on operand J for
1760 instruction template T. */
1763 match_mem_size (const insn_template
*t
, unsigned int j
)
1765 return (match_reg_size (t
, j
)
1766 && !((i
.types
[j
].bitfield
.unspecified
1768 && !t
->operand_types
[j
].bitfield
.unspecified
)
1769 || (i
.types
[j
].bitfield
.fword
1770 && !t
->operand_types
[j
].bitfield
.fword
)
1771 || (i
.types
[j
].bitfield
.tbyte
1772 && !t
->operand_types
[j
].bitfield
.tbyte
)
1773 || (i
.types
[j
].bitfield
.xmmword
1774 && !t
->operand_types
[j
].bitfield
.xmmword
)
1775 || (i
.types
[j
].bitfield
.ymmword
1776 && !t
->operand_types
[j
].bitfield
.ymmword
)
1777 || (i
.types
[j
].bitfield
.zmmword
1778 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1781 /* Return 1 if there is no size conflict on any operands for
1782 instruction template T. */
1785 operand_size_match (const insn_template
*t
)
1790 /* Don't check jump instructions. */
1791 if (t
->opcode_modifier
.jump
1792 || t
->opcode_modifier
.jumpbyte
1793 || t
->opcode_modifier
.jumpdword
1794 || t
->opcode_modifier
.jumpintersegment
)
1797 /* Check memory and accumulator operand size. */
1798 for (j
= 0; j
< i
.operands
; j
++)
1800 if (t
->operand_types
[j
].bitfield
.anysize
)
1803 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1809 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1818 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1821 i
.error
= operand_size_mismatch
;
1825 /* Check reverse. */
1826 gas_assert (i
.operands
== 2);
1829 for (j
= 0; j
< 2; j
++)
1831 if (t
->operand_types
[j
].bitfield
.acc
1832 && !match_reg_size (t
, j
? 0 : 1))
1835 if (i
.types
[j
].bitfield
.mem
1836 && !match_mem_size (t
, j
? 0 : 1))
1844 operand_type_match (i386_operand_type overlap
,
1845 i386_operand_type given
)
1847 i386_operand_type temp
= overlap
;
1849 temp
.bitfield
.jumpabsolute
= 0;
1850 temp
.bitfield
.unspecified
= 0;
1851 temp
.bitfield
.byte
= 0;
1852 temp
.bitfield
.word
= 0;
1853 temp
.bitfield
.dword
= 0;
1854 temp
.bitfield
.fword
= 0;
1855 temp
.bitfield
.qword
= 0;
1856 temp
.bitfield
.tbyte
= 0;
1857 temp
.bitfield
.xmmword
= 0;
1858 temp
.bitfield
.ymmword
= 0;
1859 temp
.bitfield
.zmmword
= 0;
1860 if (operand_type_all_zero (&temp
))
1863 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1864 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1868 i
.error
= operand_type_mismatch
;
1872 /* If given types g0 and g1 are registers they must be of the same type
1873 unless the expected operand type register overlap is null.
1874 Note that Acc in a template matches every size of reg. */
1877 operand_type_register_match (i386_operand_type m0
,
1878 i386_operand_type g0
,
1879 i386_operand_type t0
,
1880 i386_operand_type m1
,
1881 i386_operand_type g1
,
1882 i386_operand_type t1
)
1884 if (!operand_type_check (g0
, reg
))
1887 if (!operand_type_check (g1
, reg
))
1890 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1891 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1892 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1893 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1896 if (m0
.bitfield
.acc
)
1898 t0
.bitfield
.reg8
= 1;
1899 t0
.bitfield
.reg16
= 1;
1900 t0
.bitfield
.reg32
= 1;
1901 t0
.bitfield
.reg64
= 1;
1904 if (m1
.bitfield
.acc
)
1906 t1
.bitfield
.reg8
= 1;
1907 t1
.bitfield
.reg16
= 1;
1908 t1
.bitfield
.reg32
= 1;
1909 t1
.bitfield
.reg64
= 1;
1912 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1913 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1914 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1915 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1918 i
.error
= register_type_mismatch
;
1923 static INLINE
unsigned int
1924 register_number (const reg_entry
*r
)
1926 unsigned int nr
= r
->reg_num
;
1928 if (r
->reg_flags
& RegRex
)
1931 if (r
->reg_flags
& RegVRex
)
1937 static INLINE
unsigned int
1938 mode_from_disp_size (i386_operand_type t
)
1940 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1942 else if (t
.bitfield
.disp16
1943 || t
.bitfield
.disp32
1944 || t
.bitfield
.disp32s
)
1951 fits_in_signed_byte (addressT num
)
1953 return num
+ 0x80 <= 0xff;
1957 fits_in_unsigned_byte (addressT num
)
1963 fits_in_unsigned_word (addressT num
)
1965 return num
<= 0xffff;
1969 fits_in_signed_word (addressT num
)
1971 return num
+ 0x8000 <= 0xffff;
1975 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1980 return num
+ 0x80000000 <= 0xffffffff;
1982 } /* fits_in_signed_long() */
1985 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1990 return num
<= 0xffffffff;
1992 } /* fits_in_unsigned_long() */
1995 fits_in_vec_disp8 (offsetT num
)
1997 int shift
= i
.memshift
;
2003 mask
= (1 << shift
) - 1;
2005 /* Return 0 if NUM isn't properly aligned. */
2009 /* Check if NUM will fit in 8bit after shift. */
2010 return fits_in_signed_byte (num
>> shift
);
2014 fits_in_imm4 (offsetT num
)
2016 return (num
& 0xf) == num
;
2019 static i386_operand_type
2020 smallest_imm_type (offsetT num
)
2022 i386_operand_type t
;
2024 operand_type_set (&t
, 0);
2025 t
.bitfield
.imm64
= 1;
2027 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2029 /* This code is disabled on the 486 because all the Imm1 forms
2030 in the opcode table are slower on the i486. They're the
2031 versions with the implicitly specified single-position
2032 displacement, which has another syntax if you really want to
2034 t
.bitfield
.imm1
= 1;
2035 t
.bitfield
.imm8
= 1;
2036 t
.bitfield
.imm8s
= 1;
2037 t
.bitfield
.imm16
= 1;
2038 t
.bitfield
.imm32
= 1;
2039 t
.bitfield
.imm32s
= 1;
2041 else if (fits_in_signed_byte (num
))
2043 t
.bitfield
.imm8
= 1;
2044 t
.bitfield
.imm8s
= 1;
2045 t
.bitfield
.imm16
= 1;
2046 t
.bitfield
.imm32
= 1;
2047 t
.bitfield
.imm32s
= 1;
2049 else if (fits_in_unsigned_byte (num
))
2051 t
.bitfield
.imm8
= 1;
2052 t
.bitfield
.imm16
= 1;
2053 t
.bitfield
.imm32
= 1;
2054 t
.bitfield
.imm32s
= 1;
2056 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2058 t
.bitfield
.imm16
= 1;
2059 t
.bitfield
.imm32
= 1;
2060 t
.bitfield
.imm32s
= 1;
2062 else if (fits_in_signed_long (num
))
2064 t
.bitfield
.imm32
= 1;
2065 t
.bitfield
.imm32s
= 1;
2067 else if (fits_in_unsigned_long (num
))
2068 t
.bitfield
.imm32
= 1;
2074 offset_in_range (offsetT val
, int size
)
2080 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2081 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2082 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2084 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2090 /* If BFD64, sign extend val for 32bit address mode. */
2091 if (flag_code
!= CODE_64BIT
2092 || i
.prefix
[ADDR_PREFIX
])
2093 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2094 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2097 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2099 char buf1
[40], buf2
[40];
2101 sprint_value (buf1
, val
);
2102 sprint_value (buf2
, val
& mask
);
2103 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2117 a. PREFIX_EXIST if attempting to add a prefix where one from the
2118 same class already exists.
2119 b. PREFIX_LOCK if lock prefix is added.
2120 c. PREFIX_REP if rep/repne prefix is added.
2121 d. PREFIX_OTHER if other prefix is added.
2124 static enum PREFIX_GROUP
2125 add_prefix (unsigned int prefix
)
2127 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2130 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2131 && flag_code
== CODE_64BIT
)
2133 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2134 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2135 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2146 case CS_PREFIX_OPCODE
:
2147 case DS_PREFIX_OPCODE
:
2148 case ES_PREFIX_OPCODE
:
2149 case FS_PREFIX_OPCODE
:
2150 case GS_PREFIX_OPCODE
:
2151 case SS_PREFIX_OPCODE
:
2155 case REPNE_PREFIX_OPCODE
:
2156 case REPE_PREFIX_OPCODE
:
2161 case LOCK_PREFIX_OPCODE
:
2170 case ADDR_PREFIX_OPCODE
:
2174 case DATA_PREFIX_OPCODE
:
2178 if (i
.prefix
[q
] != 0)
2186 i
.prefix
[q
] |= prefix
;
2189 as_bad (_("same type of prefix used twice"));
2195 update_code_flag (int value
, int check
)
2197 PRINTF_LIKE ((*as_error
));
2199 flag_code
= (enum flag_code
) value
;
2200 if (flag_code
== CODE_64BIT
)
2202 cpu_arch_flags
.bitfield
.cpu64
= 1;
2203 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2207 cpu_arch_flags
.bitfield
.cpu64
= 0;
2208 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2210 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2213 as_error
= as_fatal
;
2216 (*as_error
) (_("64bit mode not supported on `%s'."),
2217 cpu_arch_name
? cpu_arch_name
: default_arch
);
2219 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2222 as_error
= as_fatal
;
2225 (*as_error
) (_("32bit mode not supported on `%s'."),
2226 cpu_arch_name
? cpu_arch_name
: default_arch
);
2228 stackop_size
= '\0';
2232 set_code_flag (int value
)
2234 update_code_flag (value
, 0);
2238 set_16bit_gcc_code_flag (int new_code_flag
)
2240 flag_code
= (enum flag_code
) new_code_flag
;
2241 if (flag_code
!= CODE_16BIT
)
2243 cpu_arch_flags
.bitfield
.cpu64
= 0;
2244 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2245 stackop_size
= LONG_MNEM_SUFFIX
;
2249 set_intel_syntax (int syntax_flag
)
2251 /* Find out if register prefixing is specified. */
2252 int ask_naked_reg
= 0;
2255 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2258 int e
= get_symbol_name (&string
);
2260 if (strcmp (string
, "prefix") == 0)
2262 else if (strcmp (string
, "noprefix") == 0)
2265 as_bad (_("bad argument to syntax directive."));
2266 (void) restore_line_pointer (e
);
2268 demand_empty_rest_of_line ();
2270 intel_syntax
= syntax_flag
;
2272 if (ask_naked_reg
== 0)
2273 allow_naked_reg
= (intel_syntax
2274 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2276 allow_naked_reg
= (ask_naked_reg
< 0);
2278 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2280 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2281 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2282 register_prefix
= allow_naked_reg
? "" : "%";
2286 set_intel_mnemonic (int mnemonic_flag
)
2288 intel_mnemonic
= mnemonic_flag
;
2292 set_allow_index_reg (int flag
)
2294 allow_index_reg
= flag
;
2298 set_check (int what
)
2300 enum check_kind
*kind
;
2305 kind
= &operand_check
;
2316 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2319 int e
= get_symbol_name (&string
);
2321 if (strcmp (string
, "none") == 0)
2323 else if (strcmp (string
, "warning") == 0)
2324 *kind
= check_warning
;
2325 else if (strcmp (string
, "error") == 0)
2326 *kind
= check_error
;
2328 as_bad (_("bad argument to %s_check directive."), str
);
2329 (void) restore_line_pointer (e
);
2332 as_bad (_("missing argument for %s_check directive"), str
);
2334 demand_empty_rest_of_line ();
2338 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2339 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2341 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2342 static const char *arch
;
2344 /* Intel LIOM is only supported on ELF. */
2350 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2351 use default_arch. */
2352 arch
= cpu_arch_name
;
2354 arch
= default_arch
;
2357 /* If we are targeting Intel MCU, we must enable it. */
2358 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2359 || new_flag
.bitfield
.cpuiamcu
)
2362 /* If we are targeting Intel L1OM, we must enable it. */
2363 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2364 || new_flag
.bitfield
.cpul1om
)
2367 /* If we are targeting Intel K1OM, we must enable it. */
2368 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2369 || new_flag
.bitfield
.cpuk1om
)
2372 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2377 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2381 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2384 int e
= get_symbol_name (&string
);
2386 i386_cpu_flags flags
;
2388 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2390 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2392 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2396 cpu_arch_name
= cpu_arch
[j
].name
;
2397 cpu_sub_arch_name
= NULL
;
2398 cpu_arch_flags
= cpu_arch
[j
].flags
;
2399 if (flag_code
== CODE_64BIT
)
2401 cpu_arch_flags
.bitfield
.cpu64
= 1;
2402 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2406 cpu_arch_flags
.bitfield
.cpu64
= 0;
2407 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2409 cpu_arch_isa
= cpu_arch
[j
].type
;
2410 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2411 if (!cpu_arch_tune_set
)
2413 cpu_arch_tune
= cpu_arch_isa
;
2414 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2419 flags
= cpu_flags_or (cpu_arch_flags
,
2422 if (!valid_iamcu_cpu_flags (&flags
))
2423 as_fatal (_("`%s' isn't valid for Intel MCU"),
2425 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2427 if (cpu_sub_arch_name
)
2429 char *name
= cpu_sub_arch_name
;
2430 cpu_sub_arch_name
= concat (name
,
2432 (const char *) NULL
);
2436 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2437 cpu_arch_flags
= flags
;
2438 cpu_arch_isa_flags
= flags
;
2440 (void) restore_line_pointer (e
);
2441 demand_empty_rest_of_line ();
2446 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2448 /* Disable an ISA entension. */
2449 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2450 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2452 flags
= cpu_flags_and_not (cpu_arch_flags
,
2453 cpu_noarch
[j
].flags
);
2454 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2456 if (cpu_sub_arch_name
)
2458 char *name
= cpu_sub_arch_name
;
2459 cpu_sub_arch_name
= concat (name
, string
,
2460 (const char *) NULL
);
2464 cpu_sub_arch_name
= xstrdup (string
);
2465 cpu_arch_flags
= flags
;
2466 cpu_arch_isa_flags
= flags
;
2468 (void) restore_line_pointer (e
);
2469 demand_empty_rest_of_line ();
2473 j
= ARRAY_SIZE (cpu_arch
);
2476 if (j
>= ARRAY_SIZE (cpu_arch
))
2477 as_bad (_("no such architecture: `%s'"), string
);
2479 *input_line_pointer
= e
;
2482 as_bad (_("missing cpu architecture"));
2484 no_cond_jump_promotion
= 0;
2485 if (*input_line_pointer
== ','
2486 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2491 ++input_line_pointer
;
2492 e
= get_symbol_name (&string
);
2494 if (strcmp (string
, "nojumps") == 0)
2495 no_cond_jump_promotion
= 1;
2496 else if (strcmp (string
, "jumps") == 0)
2499 as_bad (_("no such architecture modifier: `%s'"), string
);
2501 (void) restore_line_pointer (e
);
2504 demand_empty_rest_of_line ();
2507 enum bfd_architecture
2510 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2512 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2513 || flag_code
!= CODE_64BIT
)
2514 as_fatal (_("Intel L1OM is 64bit ELF only"));
2515 return bfd_arch_l1om
;
2517 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2519 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2520 || flag_code
!= CODE_64BIT
)
2521 as_fatal (_("Intel K1OM is 64bit ELF only"));
2522 return bfd_arch_k1om
;
2524 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2526 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2527 || flag_code
== CODE_64BIT
)
2528 as_fatal (_("Intel MCU is 32bit ELF only"));
2529 return bfd_arch_iamcu
;
2532 return bfd_arch_i386
;
2538 if (!strncmp (default_arch
, "x86_64", 6))
2540 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2542 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2543 || default_arch
[6] != '\0')
2544 as_fatal (_("Intel L1OM is 64bit ELF only"));
2545 return bfd_mach_l1om
;
2547 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2549 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2550 || default_arch
[6] != '\0')
2551 as_fatal (_("Intel K1OM is 64bit ELF only"));
2552 return bfd_mach_k1om
;
2554 else if (default_arch
[6] == '\0')
2555 return bfd_mach_x86_64
;
2557 return bfd_mach_x64_32
;
2559 else if (!strcmp (default_arch
, "i386")
2560 || !strcmp (default_arch
, "iamcu"))
2562 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2564 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2565 as_fatal (_("Intel MCU is 32bit ELF only"));
2566 return bfd_mach_i386_iamcu
;
2569 return bfd_mach_i386_i386
;
2572 as_fatal (_("unknown architecture"));
2578 const char *hash_err
;
2580 /* Initialize op_hash hash table. */
2581 op_hash
= hash_new ();
2584 const insn_template
*optab
;
2585 templates
*core_optab
;
2587 /* Setup for loop. */
2589 core_optab
= XNEW (templates
);
2590 core_optab
->start
= optab
;
2595 if (optab
->name
== NULL
2596 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2598 /* different name --> ship out current template list;
2599 add to hash table; & begin anew. */
2600 core_optab
->end
= optab
;
2601 hash_err
= hash_insert (op_hash
,
2603 (void *) core_optab
);
2606 as_fatal (_("can't hash %s: %s"),
2610 if (optab
->name
== NULL
)
2612 core_optab
= XNEW (templates
);
2613 core_optab
->start
= optab
;
2618 /* Initialize reg_hash hash table. */
2619 reg_hash
= hash_new ();
2621 const reg_entry
*regtab
;
2622 unsigned int regtab_size
= i386_regtab_size
;
2624 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2626 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2628 as_fatal (_("can't hash %s: %s"),
2634 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2639 for (c
= 0; c
< 256; c
++)
2644 mnemonic_chars
[c
] = c
;
2645 register_chars
[c
] = c
;
2646 operand_chars
[c
] = c
;
2648 else if (ISLOWER (c
))
2650 mnemonic_chars
[c
] = c
;
2651 register_chars
[c
] = c
;
2652 operand_chars
[c
] = c
;
2654 else if (ISUPPER (c
))
2656 mnemonic_chars
[c
] = TOLOWER (c
);
2657 register_chars
[c
] = mnemonic_chars
[c
];
2658 operand_chars
[c
] = c
;
2660 else if (c
== '{' || c
== '}')
2661 operand_chars
[c
] = c
;
2663 if (ISALPHA (c
) || ISDIGIT (c
))
2664 identifier_chars
[c
] = c
;
2667 identifier_chars
[c
] = c
;
2668 operand_chars
[c
] = c
;
2673 identifier_chars
['@'] = '@';
2676 identifier_chars
['?'] = '?';
2677 operand_chars
['?'] = '?';
2679 digit_chars
['-'] = '-';
2680 mnemonic_chars
['_'] = '_';
2681 mnemonic_chars
['-'] = '-';
2682 mnemonic_chars
['.'] = '.';
2683 identifier_chars
['_'] = '_';
2684 identifier_chars
['.'] = '.';
2686 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2687 operand_chars
[(unsigned char) *p
] = *p
;
2690 if (flag_code
== CODE_64BIT
)
2692 #if defined (OBJ_COFF) && defined (TE_PE)
2693 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2696 x86_dwarf2_return_column
= 16;
2698 x86_cie_data_alignment
= -8;
2702 x86_dwarf2_return_column
= 8;
2703 x86_cie_data_alignment
= -4;
2708 i386_print_statistics (FILE *file
)
2710 hash_print_statistics (file
, "i386 opcode", op_hash
);
2711 hash_print_statistics (file
, "i386 register", reg_hash
);
2716 /* Debugging routines for md_assemble. */
2717 static void pte (insn_template
*);
2718 static void pt (i386_operand_type
);
2719 static void pe (expressionS
*);
2720 static void ps (symbolS
*);
2723 pi (char *line
, i386_insn
*x
)
2727 fprintf (stdout
, "%s: template ", line
);
2729 fprintf (stdout
, " address: base %s index %s scale %x\n",
2730 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2731 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2732 x
->log2_scale_factor
);
2733 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2734 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2735 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2736 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2737 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2738 (x
->rex
& REX_W
) != 0,
2739 (x
->rex
& REX_R
) != 0,
2740 (x
->rex
& REX_X
) != 0,
2741 (x
->rex
& REX_B
) != 0);
2742 for (j
= 0; j
< x
->operands
; j
++)
2744 fprintf (stdout
, " #%d: ", j
+ 1);
2746 fprintf (stdout
, "\n");
2747 if (x
->types
[j
].bitfield
.reg8
2748 || x
->types
[j
].bitfield
.reg16
2749 || x
->types
[j
].bitfield
.reg32
2750 || x
->types
[j
].bitfield
.reg64
2751 || x
->types
[j
].bitfield
.regmmx
2752 || x
->types
[j
].bitfield
.regxmm
2753 || x
->types
[j
].bitfield
.regymm
2754 || x
->types
[j
].bitfield
.regzmm
2755 || x
->types
[j
].bitfield
.sreg2
2756 || x
->types
[j
].bitfield
.sreg3
2757 || x
->types
[j
].bitfield
.control
2758 || x
->types
[j
].bitfield
.debug
2759 || x
->types
[j
].bitfield
.test
)
2760 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2761 if (operand_type_check (x
->types
[j
], imm
))
2763 if (operand_type_check (x
->types
[j
], disp
))
2764 pe (x
->op
[j
].disps
);
2769 pte (insn_template
*t
)
2772 fprintf (stdout
, " %d operands ", t
->operands
);
2773 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2774 if (t
->extension_opcode
!= None
)
2775 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2776 if (t
->opcode_modifier
.d
)
2777 fprintf (stdout
, "D");
2778 if (t
->opcode_modifier
.w
)
2779 fprintf (stdout
, "W");
2780 fprintf (stdout
, "\n");
2781 for (j
= 0; j
< t
->operands
; j
++)
2783 fprintf (stdout
, " #%d type ", j
+ 1);
2784 pt (t
->operand_types
[j
]);
2785 fprintf (stdout
, "\n");
2792 fprintf (stdout
, " operation %d\n", e
->X_op
);
2793 fprintf (stdout
, " add_number %ld (%lx)\n",
2794 (long) e
->X_add_number
, (long) e
->X_add_number
);
2795 if (e
->X_add_symbol
)
2797 fprintf (stdout
, " add_symbol ");
2798 ps (e
->X_add_symbol
);
2799 fprintf (stdout
, "\n");
2803 fprintf (stdout
, " op_symbol ");
2804 ps (e
->X_op_symbol
);
2805 fprintf (stdout
, "\n");
2812 fprintf (stdout
, "%s type %s%s",
2814 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2815 segment_name (S_GET_SEGMENT (s
)));
2818 static struct type_name
2820 i386_operand_type mask
;
2823 const type_names
[] =
2825 { OPERAND_TYPE_REG8
, "r8" },
2826 { OPERAND_TYPE_REG16
, "r16" },
2827 { OPERAND_TYPE_REG32
, "r32" },
2828 { OPERAND_TYPE_REG64
, "r64" },
2829 { OPERAND_TYPE_IMM8
, "i8" },
2830 { OPERAND_TYPE_IMM8
, "i8s" },
2831 { OPERAND_TYPE_IMM16
, "i16" },
2832 { OPERAND_TYPE_IMM32
, "i32" },
2833 { OPERAND_TYPE_IMM32S
, "i32s" },
2834 { OPERAND_TYPE_IMM64
, "i64" },
2835 { OPERAND_TYPE_IMM1
, "i1" },
2836 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2837 { OPERAND_TYPE_DISP8
, "d8" },
2838 { OPERAND_TYPE_DISP16
, "d16" },
2839 { OPERAND_TYPE_DISP32
, "d32" },
2840 { OPERAND_TYPE_DISP32S
, "d32s" },
2841 { OPERAND_TYPE_DISP64
, "d64" },
2842 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2843 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2844 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2845 { OPERAND_TYPE_CONTROL
, "control reg" },
2846 { OPERAND_TYPE_TEST
, "test reg" },
2847 { OPERAND_TYPE_DEBUG
, "debug reg" },
2848 { OPERAND_TYPE_FLOATREG
, "FReg" },
2849 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2850 { OPERAND_TYPE_SREG2
, "SReg2" },
2851 { OPERAND_TYPE_SREG3
, "SReg3" },
2852 { OPERAND_TYPE_ACC
, "Acc" },
2853 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2854 { OPERAND_TYPE_REGMMX
, "rMMX" },
2855 { OPERAND_TYPE_REGXMM
, "rXMM" },
2856 { OPERAND_TYPE_REGYMM
, "rYMM" },
2857 { OPERAND_TYPE_REGZMM
, "rZMM" },
2858 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2859 { OPERAND_TYPE_ESSEG
, "es" },
2863 pt (i386_operand_type t
)
2866 i386_operand_type a
;
2868 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2870 a
= operand_type_and (t
, type_names
[j
].mask
);
2871 if (!operand_type_all_zero (&a
))
2872 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2877 #endif /* DEBUG386 */
2879 static bfd_reloc_code_real_type
2880 reloc (unsigned int size
,
2883 bfd_reloc_code_real_type other
)
2885 if (other
!= NO_RELOC
)
2887 reloc_howto_type
*rel
;
2892 case BFD_RELOC_X86_64_GOT32
:
2893 return BFD_RELOC_X86_64_GOT64
;
2895 case BFD_RELOC_X86_64_GOTPLT64
:
2896 return BFD_RELOC_X86_64_GOTPLT64
;
2898 case BFD_RELOC_X86_64_PLTOFF64
:
2899 return BFD_RELOC_X86_64_PLTOFF64
;
2901 case BFD_RELOC_X86_64_GOTPC32
:
2902 other
= BFD_RELOC_X86_64_GOTPC64
;
2904 case BFD_RELOC_X86_64_GOTPCREL
:
2905 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2907 case BFD_RELOC_X86_64_TPOFF32
:
2908 other
= BFD_RELOC_X86_64_TPOFF64
;
2910 case BFD_RELOC_X86_64_DTPOFF32
:
2911 other
= BFD_RELOC_X86_64_DTPOFF64
;
2917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2918 if (other
== BFD_RELOC_SIZE32
)
2921 other
= BFD_RELOC_SIZE64
;
2924 as_bad (_("there are no pc-relative size relocations"));
2930 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2931 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2934 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2936 as_bad (_("unknown relocation (%u)"), other
);
2937 else if (size
!= bfd_get_reloc_size (rel
))
2938 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2939 bfd_get_reloc_size (rel
),
2941 else if (pcrel
&& !rel
->pc_relative
)
2942 as_bad (_("non-pc-relative relocation for pc-relative field"));
2943 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2945 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2947 as_bad (_("relocated field and relocation type differ in signedness"));
2956 as_bad (_("there are no unsigned pc-relative relocations"));
2959 case 1: return BFD_RELOC_8_PCREL
;
2960 case 2: return BFD_RELOC_16_PCREL
;
2961 case 4: return BFD_RELOC_32_PCREL
;
2962 case 8: return BFD_RELOC_64_PCREL
;
2964 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2971 case 4: return BFD_RELOC_X86_64_32S
;
2976 case 1: return BFD_RELOC_8
;
2977 case 2: return BFD_RELOC_16
;
2978 case 4: return BFD_RELOC_32
;
2979 case 8: return BFD_RELOC_64
;
2981 as_bad (_("cannot do %s %u byte relocation"),
2982 sign
> 0 ? "signed" : "unsigned", size
);
2988 /* Here we decide which fixups can be adjusted to make them relative to
2989 the beginning of the section instead of the symbol. Basically we need
2990 to make sure that the dynamic relocations are done correctly, so in
2991 some cases we force the original symbol to be used. */
2994 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3000 /* Don't adjust pc-relative references to merge sections in 64-bit
3002 if (use_rela_relocations
3003 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3007 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3008 and changed later by validate_fix. */
3009 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3010 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3013 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3014 for size relocations. */
3015 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3016 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3017 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3018 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3019 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3020 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3021 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3022 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3023 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3024 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3025 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3026 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3027 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3028 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3029 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3030 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3031 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3032 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3033 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3034 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3035 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3036 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3037 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3038 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3039 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3040 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3041 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3046 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3047 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3054 intel_float_operand (const char *mnemonic
)
3056 /* Note that the value returned is meaningful only for opcodes with (memory)
3057 operands, hence the code here is free to improperly handle opcodes that
3058 have no operands (for better performance and smaller code). */
3060 if (mnemonic
[0] != 'f')
3061 return 0; /* non-math */
3063 switch (mnemonic
[1])
3065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3066 the fs segment override prefix not currently handled because no
3067 call path can make opcodes without operands get here */
3069 return 2 /* integer op */;
3071 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3072 return 3; /* fldcw/fldenv */
3075 if (mnemonic
[2] != 'o' /* fnop */)
3076 return 3; /* non-waiting control op */
3079 if (mnemonic
[2] == 's')
3080 return 3; /* frstor/frstpm */
3083 if (mnemonic
[2] == 'a')
3084 return 3; /* fsave */
3085 if (mnemonic
[2] == 't')
3087 switch (mnemonic
[3])
3089 case 'c': /* fstcw */
3090 case 'd': /* fstdw */
3091 case 'e': /* fstenv */
3092 case 's': /* fsts[gw] */
3098 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3099 return 0; /* fxsave/fxrstor are not really math ops */
3106 /* Build the VEX prefix. */
3109 build_vex_prefix (const insn_template
*t
)
3111 unsigned int register_specifier
;
3112 unsigned int implied_prefix
;
3113 unsigned int vector_length
;
3115 /* Check register specifier. */
3116 if (i
.vex
.register_specifier
)
3118 register_specifier
=
3119 ~register_number (i
.vex
.register_specifier
) & 0xf;
3120 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3123 register_specifier
= 0xf;
3125 /* Use 2-byte VEX prefix by swappping destination and source
3128 && i
.operands
== i
.reg_operands
3129 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3130 && i
.tm
.opcode_modifier
.s
3133 unsigned int xchg
= i
.operands
- 1;
3134 union i386_op temp_op
;
3135 i386_operand_type temp_type
;
3137 temp_type
= i
.types
[xchg
];
3138 i
.types
[xchg
] = i
.types
[0];
3139 i
.types
[0] = temp_type
;
3140 temp_op
= i
.op
[xchg
];
3141 i
.op
[xchg
] = i
.op
[0];
3144 gas_assert (i
.rm
.mode
== 3);
3148 i
.rm
.regmem
= i
.rm
.reg
;
3151 /* Use the next insn. */
3155 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3156 vector_length
= avxscalar
;
3158 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3160 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3165 case DATA_PREFIX_OPCODE
:
3168 case REPE_PREFIX_OPCODE
:
3171 case REPNE_PREFIX_OPCODE
:
3178 /* Use 2-byte VEX prefix if possible. */
3179 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3180 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3181 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3183 /* 2-byte VEX prefix. */
3187 i
.vex
.bytes
[0] = 0xc5;
3189 /* Check the REX.R bit. */
3190 r
= (i
.rex
& REX_R
) ? 0 : 1;
3191 i
.vex
.bytes
[1] = (r
<< 7
3192 | register_specifier
<< 3
3193 | vector_length
<< 2
3198 /* 3-byte VEX prefix. */
3203 switch (i
.tm
.opcode_modifier
.vexopcode
)
3207 i
.vex
.bytes
[0] = 0xc4;
3211 i
.vex
.bytes
[0] = 0xc4;
3215 i
.vex
.bytes
[0] = 0xc4;
3219 i
.vex
.bytes
[0] = 0x8f;
3223 i
.vex
.bytes
[0] = 0x8f;
3227 i
.vex
.bytes
[0] = 0x8f;
3233 /* The high 3 bits of the second VEX byte are 1's compliment
3234 of RXB bits from REX. */
3235 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3237 /* Check the REX.W bit. */
3238 w
= (i
.rex
& REX_W
) ? 1 : 0;
3239 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3242 i
.vex
.bytes
[2] = (w
<< 7
3243 | register_specifier
<< 3
3244 | vector_length
<< 2
3249 /* Build the EVEX prefix. */
3252 build_evex_prefix (void)
3254 unsigned int register_specifier
;
3255 unsigned int implied_prefix
;
3257 rex_byte vrex_used
= 0;
3259 /* Check register specifier. */
3260 if (i
.vex
.register_specifier
)
3262 gas_assert ((i
.vrex
& REX_X
) == 0);
3264 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3265 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3266 register_specifier
+= 8;
3267 /* The upper 16 registers are encoded in the fourth byte of the
3269 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3270 i
.vex
.bytes
[3] = 0x8;
3271 register_specifier
= ~register_specifier
& 0xf;
3275 register_specifier
= 0xf;
3277 /* Encode upper 16 vector index register in the fourth byte of
3279 if (!(i
.vrex
& REX_X
))
3280 i
.vex
.bytes
[3] = 0x8;
3285 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3290 case DATA_PREFIX_OPCODE
:
3293 case REPE_PREFIX_OPCODE
:
3296 case REPNE_PREFIX_OPCODE
:
3303 /* 4 byte EVEX prefix. */
3305 i
.vex
.bytes
[0] = 0x62;
3308 switch (i
.tm
.opcode_modifier
.vexopcode
)
3324 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3326 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3328 /* The fifth bit of the second EVEX byte is 1's compliment of the
3329 REX_R bit in VREX. */
3330 if (!(i
.vrex
& REX_R
))
3331 i
.vex
.bytes
[1] |= 0x10;
3335 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3337 /* When all operands are registers, the REX_X bit in REX is not
3338 used. We reuse it to encode the upper 16 registers, which is
3339 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3340 as 1's compliment. */
3341 if ((i
.vrex
& REX_B
))
3344 i
.vex
.bytes
[1] &= ~0x40;
3348 /* EVEX instructions shouldn't need the REX prefix. */
3349 i
.vrex
&= ~vrex_used
;
3350 gas_assert (i
.vrex
== 0);
3352 /* Check the REX.W bit. */
3353 w
= (i
.rex
& REX_W
) ? 1 : 0;
3354 if (i
.tm
.opcode_modifier
.vexw
)
3356 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3359 /* If w is not set it means we are dealing with WIG instruction. */
3362 if (evexwig
== evexw1
)
3366 /* Encode the U bit. */
3367 implied_prefix
|= 0x4;
3369 /* The third byte of the EVEX prefix. */
3370 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3372 /* The fourth byte of the EVEX prefix. */
3373 /* The zeroing-masking bit. */
3374 if (i
.mask
&& i
.mask
->zeroing
)
3375 i
.vex
.bytes
[3] |= 0x80;
3377 /* Don't always set the broadcast bit if there is no RC. */
3380 /* Encode the vector length. */
3381 unsigned int vec_length
;
3383 switch (i
.tm
.opcode_modifier
.evex
)
3385 case EVEXLIG
: /* LL' is ignored */
3386 vec_length
= evexlig
<< 5;
3389 vec_length
= 0 << 5;
3392 vec_length
= 1 << 5;
3395 vec_length
= 2 << 5;
3401 i
.vex
.bytes
[3] |= vec_length
;
3402 /* Encode the broadcast bit. */
3404 i
.vex
.bytes
[3] |= 0x10;
3408 if (i
.rounding
->type
!= saeonly
)
3409 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3411 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3414 if (i
.mask
&& i
.mask
->mask
)
3415 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3419 process_immext (void)
3423 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3426 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3427 with an opcode suffix which is coded in the same place as an
3428 8-bit immediate field would be.
3429 Here we check those operands and remove them afterwards. */
3432 for (x
= 0; x
< i
.operands
; x
++)
3433 if (register_number (i
.op
[x
].regs
) != x
)
3434 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3435 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3441 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3443 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3444 suffix which is coded in the same place as an 8-bit immediate
3446 Here we check those operands and remove them afterwards. */
3449 if (i
.operands
!= 3)
3452 for (x
= 0; x
< 2; x
++)
3453 if (register_number (i
.op
[x
].regs
) != x
)
3454 goto bad_register_operand
;
3456 /* Check for third operand for mwaitx/monitorx insn. */
3457 if (register_number (i
.op
[x
].regs
)
3458 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3460 bad_register_operand
:
3461 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3462 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3469 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3470 which is coded in the same place as an 8-bit immediate field
3471 would be. Here we fake an 8-bit immediate operand from the
3472 opcode suffix stored in tm.extension_opcode.
3474 AVX instructions also use this encoding, for some of
3475 3 argument instructions. */
3477 gas_assert (i
.imm_operands
<= 1
3479 || ((i
.tm
.opcode_modifier
.vex
3480 || i
.tm
.opcode_modifier
.evex
)
3481 && i
.operands
<= 4)));
3483 exp
= &im_expressions
[i
.imm_operands
++];
3484 i
.op
[i
.operands
].imms
= exp
;
3485 i
.types
[i
.operands
] = imm8
;
3487 exp
->X_op
= O_constant
;
3488 exp
->X_add_number
= i
.tm
.extension_opcode
;
3489 i
.tm
.extension_opcode
= None
;
3496 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3501 as_bad (_("invalid instruction `%s' after `%s'"),
3502 i
.tm
.name
, i
.hle_prefix
);
3505 if (i
.prefix
[LOCK_PREFIX
])
3507 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3511 case HLEPrefixRelease
:
3512 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3514 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3518 if (i
.mem_operands
== 0
3519 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3521 as_bad (_("memory destination needed for instruction `%s'"
3522 " after `xrelease'"), i
.tm
.name
);
3529 /* This is the guts of the machine-dependent assembler. LINE points to a
3530 machine dependent instruction. This function is supposed to emit
3531 the frags/bytes it assembles to. */
3534 md_assemble (char *line
)
3537 char mnemonic
[MAX_MNEM_SIZE
];
3538 const insn_template
*t
;
3540 /* Initialize globals. */
3541 memset (&i
, '\0', sizeof (i
));
3542 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3543 i
.reloc
[j
] = NO_RELOC
;
3544 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3545 memset (im_expressions
, '\0', sizeof (im_expressions
));
3546 save_stack_p
= save_stack
;
3548 /* First parse an instruction mnemonic & call i386_operand for the operands.
3549 We assume that the scrubber has arranged it so that line[0] is the valid
3550 start of a (possibly prefixed) mnemonic. */
3552 line
= parse_insn (line
, mnemonic
);
3556 line
= parse_operands (line
, mnemonic
);
3561 /* Now we've parsed the mnemonic into a set of templates, and have the
3562 operands at hand. */
3564 /* All intel opcodes have reversed operands except for "bound" and
3565 "enter". We also don't reverse intersegment "jmp" and "call"
3566 instructions with 2 immediate operands so that the immediate segment
3567 precedes the offset, as it does when in AT&T mode. */
3570 && (strcmp (mnemonic
, "bound") != 0)
3571 && (strcmp (mnemonic
, "invlpga") != 0)
3572 && !(operand_type_check (i
.types
[0], imm
)
3573 && operand_type_check (i
.types
[1], imm
)))
3576 /* The order of the immediates should be reversed
3577 for 2 immediates extrq and insertq instructions */
3578 if (i
.imm_operands
== 2
3579 && (strcmp (mnemonic
, "extrq") == 0
3580 || strcmp (mnemonic
, "insertq") == 0))
3581 swap_2_operands (0, 1);
3586 /* Don't optimize displacement for movabs since it only takes 64bit
3589 && i
.disp_encoding
!= disp_encoding_32bit
3590 && (flag_code
!= CODE_64BIT
3591 || strcmp (mnemonic
, "movabs") != 0))
3594 /* Next, we find a template that matches the given insn,
3595 making sure the overlap of the given operands types is consistent
3596 with the template operand types. */
3598 if (!(t
= match_template ()))
3601 if (sse_check
!= check_none
3602 && !i
.tm
.opcode_modifier
.noavx
3603 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3604 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3605 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3606 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3607 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3608 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3610 (sse_check
== check_warning
3612 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3615 /* Zap movzx and movsx suffix. The suffix has been set from
3616 "word ptr" or "byte ptr" on the source operand in Intel syntax
3617 or extracted from mnemonic in AT&T syntax. But we'll use
3618 the destination register to choose the suffix for encoding. */
3619 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3621 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3622 there is no suffix, the default will be byte extension. */
3623 if (i
.reg_operands
!= 2
3626 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3631 if (i
.tm
.opcode_modifier
.fwait
)
3632 if (!add_prefix (FWAIT_OPCODE
))
3635 /* Check if REP prefix is OK. */
3636 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3638 as_bad (_("invalid instruction `%s' after `%s'"),
3639 i
.tm
.name
, i
.rep_prefix
);
3643 /* Check for lock without a lockable instruction. Destination operand
3644 must be memory unless it is xchg (0x86). */
3645 if (i
.prefix
[LOCK_PREFIX
]
3646 && (!i
.tm
.opcode_modifier
.islockable
3647 || i
.mem_operands
== 0
3648 || (i
.tm
.base_opcode
!= 0x86
3649 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3651 as_bad (_("expecting lockable instruction after `lock'"));
3655 /* Check if HLE prefix is OK. */
3656 if (i
.hle_prefix
&& !check_hle ())
3659 /* Check BND prefix. */
3660 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3661 as_bad (_("expecting valid branch instruction after `bnd'"));
3663 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3664 && flag_code
== CODE_64BIT
3665 && i
.prefix
[ADDR_PREFIX
])
3666 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3668 /* Insert BND prefix. */
3670 && i
.tm
.opcode_modifier
.bndprefixok
3671 && !i
.prefix
[BND_PREFIX
])
3672 add_prefix (BND_PREFIX_OPCODE
);
3674 /* Check string instruction segment overrides. */
3675 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3677 if (!check_string ())
3679 i
.disp_operands
= 0;
3682 if (!process_suffix ())
3685 /* Update operand types. */
3686 for (j
= 0; j
< i
.operands
; j
++)
3687 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3689 /* Make still unresolved immediate matches conform to size of immediate
3690 given in i.suffix. */
3691 if (!finalize_imm ())
3694 if (i
.types
[0].bitfield
.imm1
)
3695 i
.imm_operands
= 0; /* kludge for shift insns. */
3697 /* We only need to check those implicit registers for instructions
3698 with 3 operands or less. */
3699 if (i
.operands
<= 3)
3700 for (j
= 0; j
< i
.operands
; j
++)
3701 if (i
.types
[j
].bitfield
.inoutportreg
3702 || i
.types
[j
].bitfield
.shiftcount
3703 || i
.types
[j
].bitfield
.acc
3704 || i
.types
[j
].bitfield
.floatacc
)
3707 /* ImmExt should be processed after SSE2AVX. */
3708 if (!i
.tm
.opcode_modifier
.sse2avx
3709 && i
.tm
.opcode_modifier
.immext
)
3712 /* For insns with operands there are more diddles to do to the opcode. */
3715 if (!process_operands ())
3718 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3720 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3721 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3724 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3726 if (flag_code
== CODE_16BIT
)
3728 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3733 if (i
.tm
.opcode_modifier
.vex
)
3734 build_vex_prefix (t
);
3736 build_evex_prefix ();
3739 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3740 instructions may define INT_OPCODE as well, so avoid this corner
3741 case for those instructions that use MODRM. */
3742 if (i
.tm
.base_opcode
== INT_OPCODE
3743 && !i
.tm
.opcode_modifier
.modrm
3744 && i
.op
[0].imms
->X_add_number
== 3)
3746 i
.tm
.base_opcode
= INT3_OPCODE
;
3750 if ((i
.tm
.opcode_modifier
.jump
3751 || i
.tm
.opcode_modifier
.jumpbyte
3752 || i
.tm
.opcode_modifier
.jumpdword
)
3753 && i
.op
[0].disps
->X_op
== O_constant
)
3755 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3756 the absolute address given by the constant. Since ix86 jumps and
3757 calls are pc relative, we need to generate a reloc. */
3758 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3759 i
.op
[0].disps
->X_op
= O_symbol
;
3762 if (i
.tm
.opcode_modifier
.rex64
)
3765 /* For 8 bit registers we need an empty rex prefix. Also if the
3766 instruction already has a prefix, we need to convert old
3767 registers to new ones. */
3769 if ((i
.types
[0].bitfield
.reg8
3770 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3771 || (i
.types
[1].bitfield
.reg8
3772 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3773 || ((i
.types
[0].bitfield
.reg8
3774 || i
.types
[1].bitfield
.reg8
)
3779 i
.rex
|= REX_OPCODE
;
3780 for (x
= 0; x
< 2; x
++)
3782 /* Look for 8 bit operand that uses old registers. */
3783 if (i
.types
[x
].bitfield
.reg8
3784 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3786 /* In case it is "hi" register, give up. */
3787 if (i
.op
[x
].regs
->reg_num
> 3)
3788 as_bad (_("can't encode register '%s%s' in an "
3789 "instruction requiring REX prefix."),
3790 register_prefix
, i
.op
[x
].regs
->reg_name
);
3792 /* Otherwise it is equivalent to the extended register.
3793 Since the encoding doesn't change this is merely
3794 cosmetic cleanup for debug output. */
3796 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3802 add_prefix (REX_OPCODE
| i
.rex
);
3804 /* We are ready to output the insn. */
3809 parse_insn (char *line
, char *mnemonic
)
3812 char *token_start
= l
;
3815 const insn_template
*t
;
3821 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3826 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3828 as_bad (_("no such instruction: `%s'"), token_start
);
3833 if (!is_space_char (*l
)
3834 && *l
!= END_OF_INSN
3836 || (*l
!= PREFIX_SEPARATOR
3839 as_bad (_("invalid character %s in mnemonic"),
3840 output_invalid (*l
));
3843 if (token_start
== l
)
3845 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3846 as_bad (_("expecting prefix; got nothing"));
3848 as_bad (_("expecting mnemonic; got nothing"));
3852 /* Look up instruction (or prefix) via hash table. */
3853 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3855 if (*l
!= END_OF_INSN
3856 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3857 && current_templates
3858 && current_templates
->start
->opcode_modifier
.isprefix
)
3860 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3862 as_bad ((flag_code
!= CODE_64BIT
3863 ? _("`%s' is only supported in 64-bit mode")
3864 : _("`%s' is not supported in 64-bit mode")),
3865 current_templates
->start
->name
);
3868 /* If we are in 16-bit mode, do not allow addr16 or data16.
3869 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3870 if ((current_templates
->start
->opcode_modifier
.size16
3871 || current_templates
->start
->opcode_modifier
.size32
)
3872 && flag_code
!= CODE_64BIT
3873 && (current_templates
->start
->opcode_modifier
.size32
3874 ^ (flag_code
== CODE_16BIT
)))
3876 as_bad (_("redundant %s prefix"),
3877 current_templates
->start
->name
);
3880 /* Add prefix, checking for repeated prefixes. */
3881 switch (add_prefix (current_templates
->start
->base_opcode
))
3886 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3887 i
.hle_prefix
= current_templates
->start
->name
;
3888 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3889 i
.bnd_prefix
= current_templates
->start
->name
;
3891 i
.rep_prefix
= current_templates
->start
->name
;
3896 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3903 if (!current_templates
)
3905 /* Check if we should swap operand or force 32bit displacement in
3907 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3909 else if (mnem_p
- 3 == dot_p
3912 i
.disp_encoding
= disp_encoding_8bit
;
3913 else if (mnem_p
- 4 == dot_p
3917 i
.disp_encoding
= disp_encoding_32bit
;
3922 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3925 if (!current_templates
)
3928 /* See if we can get a match by trimming off a suffix. */
3931 case WORD_MNEM_SUFFIX
:
3932 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3933 i
.suffix
= SHORT_MNEM_SUFFIX
;
3935 case BYTE_MNEM_SUFFIX
:
3936 case QWORD_MNEM_SUFFIX
:
3937 i
.suffix
= mnem_p
[-1];
3939 current_templates
= (const templates
*) hash_find (op_hash
,
3942 case SHORT_MNEM_SUFFIX
:
3943 case LONG_MNEM_SUFFIX
:
3946 i
.suffix
= mnem_p
[-1];
3948 current_templates
= (const templates
*) hash_find (op_hash
,
3957 if (intel_float_operand (mnemonic
) == 1)
3958 i
.suffix
= SHORT_MNEM_SUFFIX
;
3960 i
.suffix
= LONG_MNEM_SUFFIX
;
3962 current_templates
= (const templates
*) hash_find (op_hash
,
3967 if (!current_templates
)
3969 as_bad (_("no such instruction: `%s'"), token_start
);
3974 if (current_templates
->start
->opcode_modifier
.jump
3975 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3977 /* Check for a branch hint. We allow ",pt" and ",pn" for
3978 predict taken and predict not taken respectively.
3979 I'm not sure that branch hints actually do anything on loop
3980 and jcxz insns (JumpByte) for current Pentium4 chips. They
3981 may work in the future and it doesn't hurt to accept them
3983 if (l
[0] == ',' && l
[1] == 'p')
3987 if (!add_prefix (DS_PREFIX_OPCODE
))
3991 else if (l
[2] == 'n')
3993 if (!add_prefix (CS_PREFIX_OPCODE
))
3999 /* Any other comma loses. */
4002 as_bad (_("invalid character %s in mnemonic"),
4003 output_invalid (*l
));
4007 /* Check if instruction is supported on specified architecture. */
4009 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4011 supported
|= cpu_flags_match (t
);
4012 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4016 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4018 as_bad (flag_code
== CODE_64BIT
4019 ? _("`%s' is not supported in 64-bit mode")
4020 : _("`%s' is only supported in 64-bit mode"),
4021 current_templates
->start
->name
);
4024 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4026 as_bad (_("`%s' is not supported on `%s%s'"),
4027 current_templates
->start
->name
,
4028 cpu_arch_name
? cpu_arch_name
: default_arch
,
4029 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4034 if (!cpu_arch_flags
.bitfield
.cpui386
4035 && (flag_code
!= CODE_16BIT
))
4037 as_warn (_("use .code16 to ensure correct addressing mode"));
4044 parse_operands (char *l
, const char *mnemonic
)
4048 /* 1 if operand is pending after ','. */
4049 unsigned int expecting_operand
= 0;
4051 /* Non-zero if operand parens not balanced. */
4052 unsigned int paren_not_balanced
;
4054 while (*l
!= END_OF_INSN
)
4056 /* Skip optional white space before operand. */
4057 if (is_space_char (*l
))
4059 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4061 as_bad (_("invalid character %s before operand %d"),
4062 output_invalid (*l
),
4066 token_start
= l
; /* After white space. */
4067 paren_not_balanced
= 0;
4068 while (paren_not_balanced
|| *l
!= ',')
4070 if (*l
== END_OF_INSN
)
4072 if (paren_not_balanced
)
4075 as_bad (_("unbalanced parenthesis in operand %d."),
4078 as_bad (_("unbalanced brackets in operand %d."),
4083 break; /* we are done */
4085 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4087 as_bad (_("invalid character %s in operand %d"),
4088 output_invalid (*l
),
4095 ++paren_not_balanced
;
4097 --paren_not_balanced
;
4102 ++paren_not_balanced
;
4104 --paren_not_balanced
;
4108 if (l
!= token_start
)
4109 { /* Yes, we've read in another operand. */
4110 unsigned int operand_ok
;
4111 this_operand
= i
.operands
++;
4112 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4113 if (i
.operands
> MAX_OPERANDS
)
4115 as_bad (_("spurious operands; (%d operands/instruction max)"),
4119 /* Now parse operand adding info to 'i' as we go along. */
4120 END_STRING_AND_SAVE (l
);
4124 i386_intel_operand (token_start
,
4125 intel_float_operand (mnemonic
));
4127 operand_ok
= i386_att_operand (token_start
);
4129 RESTORE_END_STRING (l
);
4135 if (expecting_operand
)
4137 expecting_operand_after_comma
:
4138 as_bad (_("expecting operand after ','; got nothing"));
4143 as_bad (_("expecting operand before ','; got nothing"));
4148 /* Now *l must be either ',' or END_OF_INSN. */
4151 if (*++l
== END_OF_INSN
)
4153 /* Just skip it, if it's \n complain. */
4154 goto expecting_operand_after_comma
;
4156 expecting_operand
= 1;
4163 swap_2_operands (int xchg1
, int xchg2
)
4165 union i386_op temp_op
;
4166 i386_operand_type temp_type
;
4167 enum bfd_reloc_code_real temp_reloc
;
4169 temp_type
= i
.types
[xchg2
];
4170 i
.types
[xchg2
] = i
.types
[xchg1
];
4171 i
.types
[xchg1
] = temp_type
;
4172 temp_op
= i
.op
[xchg2
];
4173 i
.op
[xchg2
] = i
.op
[xchg1
];
4174 i
.op
[xchg1
] = temp_op
;
4175 temp_reloc
= i
.reloc
[xchg2
];
4176 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4177 i
.reloc
[xchg1
] = temp_reloc
;
4181 if (i
.mask
->operand
== xchg1
)
4182 i
.mask
->operand
= xchg2
;
4183 else if (i
.mask
->operand
== xchg2
)
4184 i
.mask
->operand
= xchg1
;
4188 if (i
.broadcast
->operand
== xchg1
)
4189 i
.broadcast
->operand
= xchg2
;
4190 else if (i
.broadcast
->operand
== xchg2
)
4191 i
.broadcast
->operand
= xchg1
;
4195 if (i
.rounding
->operand
== xchg1
)
4196 i
.rounding
->operand
= xchg2
;
4197 else if (i
.rounding
->operand
== xchg2
)
4198 i
.rounding
->operand
= xchg1
;
4203 swap_operands (void)
4209 swap_2_operands (1, i
.operands
- 2);
4212 swap_2_operands (0, i
.operands
- 1);
4218 if (i
.mem_operands
== 2)
4220 const seg_entry
*temp_seg
;
4221 temp_seg
= i
.seg
[0];
4222 i
.seg
[0] = i
.seg
[1];
4223 i
.seg
[1] = temp_seg
;
4227 /* Try to ensure constant immediates are represented in the smallest
4232 char guess_suffix
= 0;
4236 guess_suffix
= i
.suffix
;
4237 else if (i
.reg_operands
)
4239 /* Figure out a suffix from the last register operand specified.
4240 We can't do this properly yet, ie. excluding InOutPortReg,
4241 but the following works for instructions with immediates.
4242 In any case, we can't set i.suffix yet. */
4243 for (op
= i
.operands
; --op
>= 0;)
4244 if (i
.types
[op
].bitfield
.reg8
)
4246 guess_suffix
= BYTE_MNEM_SUFFIX
;
4249 else if (i
.types
[op
].bitfield
.reg16
)
4251 guess_suffix
= WORD_MNEM_SUFFIX
;
4254 else if (i
.types
[op
].bitfield
.reg32
)
4256 guess_suffix
= LONG_MNEM_SUFFIX
;
4259 else if (i
.types
[op
].bitfield
.reg64
)
4261 guess_suffix
= QWORD_MNEM_SUFFIX
;
4265 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4266 guess_suffix
= WORD_MNEM_SUFFIX
;
4268 for (op
= i
.operands
; --op
>= 0;)
4269 if (operand_type_check (i
.types
[op
], imm
))
4271 switch (i
.op
[op
].imms
->X_op
)
4274 /* If a suffix is given, this operand may be shortened. */
4275 switch (guess_suffix
)
4277 case LONG_MNEM_SUFFIX
:
4278 i
.types
[op
].bitfield
.imm32
= 1;
4279 i
.types
[op
].bitfield
.imm64
= 1;
4281 case WORD_MNEM_SUFFIX
:
4282 i
.types
[op
].bitfield
.imm16
= 1;
4283 i
.types
[op
].bitfield
.imm32
= 1;
4284 i
.types
[op
].bitfield
.imm32s
= 1;
4285 i
.types
[op
].bitfield
.imm64
= 1;
4287 case BYTE_MNEM_SUFFIX
:
4288 i
.types
[op
].bitfield
.imm8
= 1;
4289 i
.types
[op
].bitfield
.imm8s
= 1;
4290 i
.types
[op
].bitfield
.imm16
= 1;
4291 i
.types
[op
].bitfield
.imm32
= 1;
4292 i
.types
[op
].bitfield
.imm32s
= 1;
4293 i
.types
[op
].bitfield
.imm64
= 1;
4297 /* If this operand is at most 16 bits, convert it
4298 to a signed 16 bit number before trying to see
4299 whether it will fit in an even smaller size.
4300 This allows a 16-bit operand such as $0xffe0 to
4301 be recognised as within Imm8S range. */
4302 if ((i
.types
[op
].bitfield
.imm16
)
4303 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4305 i
.op
[op
].imms
->X_add_number
=
4306 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4309 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4310 if ((i
.types
[op
].bitfield
.imm32
)
4311 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4314 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4315 ^ ((offsetT
) 1 << 31))
4316 - ((offsetT
) 1 << 31));
4320 = operand_type_or (i
.types
[op
],
4321 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4323 /* We must avoid matching of Imm32 templates when 64bit
4324 only immediate is available. */
4325 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4326 i
.types
[op
].bitfield
.imm32
= 0;
4333 /* Symbols and expressions. */
4335 /* Convert symbolic operand to proper sizes for matching, but don't
4336 prevent matching a set of insns that only supports sizes other
4337 than those matching the insn suffix. */
4339 i386_operand_type mask
, allowed
;
4340 const insn_template
*t
;
4342 operand_type_set (&mask
, 0);
4343 operand_type_set (&allowed
, 0);
4345 for (t
= current_templates
->start
;
4346 t
< current_templates
->end
;
4348 allowed
= operand_type_or (allowed
,
4349 t
->operand_types
[op
]);
4350 switch (guess_suffix
)
4352 case QWORD_MNEM_SUFFIX
:
4353 mask
.bitfield
.imm64
= 1;
4354 mask
.bitfield
.imm32s
= 1;
4356 case LONG_MNEM_SUFFIX
:
4357 mask
.bitfield
.imm32
= 1;
4359 case WORD_MNEM_SUFFIX
:
4360 mask
.bitfield
.imm16
= 1;
4362 case BYTE_MNEM_SUFFIX
:
4363 mask
.bitfield
.imm8
= 1;
4368 allowed
= operand_type_and (mask
, allowed
);
4369 if (!operand_type_all_zero (&allowed
))
4370 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4377 /* Try to use the smallest displacement type too. */
4379 optimize_disp (void)
4383 for (op
= i
.operands
; --op
>= 0;)
4384 if (operand_type_check (i
.types
[op
], disp
))
4386 if (i
.op
[op
].disps
->X_op
== O_constant
)
4388 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4390 if (i
.types
[op
].bitfield
.disp16
4391 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4393 /* If this operand is at most 16 bits, convert
4394 to a signed 16 bit number and don't use 64bit
4396 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4397 i
.types
[op
].bitfield
.disp64
= 0;
4400 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4401 if (i
.types
[op
].bitfield
.disp32
4402 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4404 /* If this operand is at most 32 bits, convert
4405 to a signed 32 bit number and don't use 64bit
4407 op_disp
&= (((offsetT
) 2 << 31) - 1);
4408 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4409 i
.types
[op
].bitfield
.disp64
= 0;
4412 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4414 i
.types
[op
].bitfield
.disp8
= 0;
4415 i
.types
[op
].bitfield
.disp16
= 0;
4416 i
.types
[op
].bitfield
.disp32
= 0;
4417 i
.types
[op
].bitfield
.disp32s
= 0;
4418 i
.types
[op
].bitfield
.disp64
= 0;
4422 else if (flag_code
== CODE_64BIT
)
4424 if (fits_in_signed_long (op_disp
))
4426 i
.types
[op
].bitfield
.disp64
= 0;
4427 i
.types
[op
].bitfield
.disp32s
= 1;
4429 if (i
.prefix
[ADDR_PREFIX
]
4430 && fits_in_unsigned_long (op_disp
))
4431 i
.types
[op
].bitfield
.disp32
= 1;
4433 if ((i
.types
[op
].bitfield
.disp32
4434 || i
.types
[op
].bitfield
.disp32s
4435 || i
.types
[op
].bitfield
.disp16
)
4436 && fits_in_signed_byte (op_disp
))
4437 i
.types
[op
].bitfield
.disp8
= 1;
4439 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4440 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4442 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4443 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4444 i
.types
[op
].bitfield
.disp8
= 0;
4445 i
.types
[op
].bitfield
.disp16
= 0;
4446 i
.types
[op
].bitfield
.disp32
= 0;
4447 i
.types
[op
].bitfield
.disp32s
= 0;
4448 i
.types
[op
].bitfield
.disp64
= 0;
4451 /* We only support 64bit displacement on constants. */
4452 i
.types
[op
].bitfield
.disp64
= 0;
4456 /* Check if operands are valid for the instruction. */
4459 check_VecOperands (const insn_template
*t
)
4463 /* Without VSIB byte, we can't have a vector register for index. */
4464 if (!t
->opcode_modifier
.vecsib
4466 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4467 || i
.index_reg
->reg_type
.bitfield
.regymm
4468 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4470 i
.error
= unsupported_vector_index_register
;
4474 /* Check if default mask is allowed. */
4475 if (t
->opcode_modifier
.nodefmask
4476 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4478 i
.error
= no_default_mask
;
4482 /* For VSIB byte, we need a vector register for index, and all vector
4483 registers must be distinct. */
4484 if (t
->opcode_modifier
.vecsib
)
4487 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4488 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4489 || (t
->opcode_modifier
.vecsib
== VecSIB256
4490 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4491 || (t
->opcode_modifier
.vecsib
== VecSIB512
4492 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4494 i
.error
= invalid_vsib_address
;
4498 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4499 if (i
.reg_operands
== 2 && !i
.mask
)
4501 gas_assert (i
.types
[0].bitfield
.regxmm
4502 || i
.types
[0].bitfield
.regymm
);
4503 gas_assert (i
.types
[2].bitfield
.regxmm
4504 || i
.types
[2].bitfield
.regymm
);
4505 if (operand_check
== check_none
)
4507 if (register_number (i
.op
[0].regs
)
4508 != register_number (i
.index_reg
)
4509 && register_number (i
.op
[2].regs
)
4510 != register_number (i
.index_reg
)
4511 && register_number (i
.op
[0].regs
)
4512 != register_number (i
.op
[2].regs
))
4514 if (operand_check
== check_error
)
4516 i
.error
= invalid_vector_register_set
;
4519 as_warn (_("mask, index, and destination registers should be distinct"));
4521 else if (i
.reg_operands
== 1 && i
.mask
)
4523 if ((i
.types
[1].bitfield
.regymm
4524 || i
.types
[1].bitfield
.regzmm
)
4525 && (register_number (i
.op
[1].regs
)
4526 == register_number (i
.index_reg
)))
4528 if (operand_check
== check_error
)
4530 i
.error
= invalid_vector_register_set
;
4533 if (operand_check
!= check_none
)
4534 as_warn (_("index and destination registers should be distinct"));
4539 /* Check if broadcast is supported by the instruction and is applied
4540 to the memory operand. */
4543 int broadcasted_opnd_size
;
4545 /* Check if specified broadcast is supported in this instruction,
4546 and it's applied to memory operand of DWORD or QWORD type,
4547 depending on VecESize. */
4548 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4549 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4550 || (t
->opcode_modifier
.vecesize
== 0
4551 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4552 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4553 || (t
->opcode_modifier
.vecesize
== 1
4554 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4555 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4558 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4559 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4560 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4561 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4562 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4563 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4564 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4565 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4566 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4570 if ((broadcasted_opnd_size
== 256
4571 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4572 || (broadcasted_opnd_size
== 512
4573 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4576 i
.error
= unsupported_broadcast
;
4580 /* If broadcast is supported in this instruction, we need to check if
4581 operand of one-element size isn't specified without broadcast. */
4582 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4584 /* Find memory operand. */
4585 for (op
= 0; op
< i
.operands
; op
++)
4586 if (operand_type_check (i
.types
[op
], anymem
))
4588 gas_assert (op
< i
.operands
);
4589 /* Check size of the memory operand. */
4590 if ((t
->opcode_modifier
.vecesize
== 0
4591 && i
.types
[op
].bitfield
.dword
)
4592 || (t
->opcode_modifier
.vecesize
== 1
4593 && i
.types
[op
].bitfield
.qword
))
4595 i
.error
= broadcast_needed
;
4600 /* Check if requested masking is supported. */
4602 && (!t
->opcode_modifier
.masking
4604 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4606 i
.error
= unsupported_masking
;
4610 /* Check if masking is applied to dest operand. */
4611 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4613 i
.error
= mask_not_on_destination
;
4620 if ((i
.rounding
->type
!= saeonly
4621 && !t
->opcode_modifier
.staticrounding
)
4622 || (i
.rounding
->type
== saeonly
4623 && (t
->opcode_modifier
.staticrounding
4624 || !t
->opcode_modifier
.sae
)))
4626 i
.error
= unsupported_rc_sae
;
4629 /* If the instruction has several immediate operands and one of
4630 them is rounding, the rounding operand should be the last
4631 immediate operand. */
4632 if (i
.imm_operands
> 1
4633 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4635 i
.error
= rc_sae_operand_not_last_imm
;
4640 /* Check vector Disp8 operand. */
4641 if (t
->opcode_modifier
.disp8memshift
)
4644 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4646 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4648 for (op
= 0; op
< i
.operands
; op
++)
4649 if (operand_type_check (i
.types
[op
], disp
)
4650 && i
.op
[op
].disps
->X_op
== O_constant
)
4652 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4654 = (i
.disp_encoding
!= disp_encoding_32bit
4655 && fits_in_vec_disp8 (value
));
4656 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4659 i
.types
[op
].bitfield
.vec_disp8
= 1;
4662 /* Vector insn can only have Vec_Disp8/Disp32 in
4663 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4665 i
.types
[op
].bitfield
.disp8
= 0;
4666 if (flag_code
!= CODE_16BIT
)
4667 i
.types
[op
].bitfield
.disp16
= 0;
4670 else if (flag_code
!= CODE_16BIT
)
4672 /* One form of this instruction supports vector Disp8.
4673 Try vector Disp8 if we need to use Disp32. */
4674 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4676 i
.error
= try_vector_disp8
;
4688 /* Check if operands are valid for the instruction. Update VEX
4692 VEX_check_operands (const insn_template
*t
)
4694 /* VREX is only valid with EVEX prefix. */
4695 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4697 i
.error
= invalid_register_operand
;
4701 if (!t
->opcode_modifier
.vex
)
4704 /* Only check VEX_Imm4, which must be the first operand. */
4705 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4707 if (i
.op
[0].imms
->X_op
!= O_constant
4708 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4714 /* Turn off Imm8 so that update_imm won't complain. */
4715 i
.types
[0] = vec_imm4
;
4721 static const insn_template
*
4722 match_template (void)
4724 /* Points to template once we've found it. */
4725 const insn_template
*t
;
4726 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4727 i386_operand_type overlap4
;
4728 unsigned int found_reverse_match
;
4729 i386_opcode_modifier suffix_check
;
4730 i386_operand_type operand_types
[MAX_OPERANDS
];
4731 int addr_prefix_disp
;
4733 unsigned int found_cpu_match
;
4734 unsigned int check_register
;
4735 enum i386_error specific_error
= 0;
4737 #if MAX_OPERANDS != 5
4738 # error "MAX_OPERANDS must be 5."
4741 found_reverse_match
= 0;
4742 addr_prefix_disp
= -1;
4744 memset (&suffix_check
, 0, sizeof (suffix_check
));
4745 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4746 suffix_check
.no_bsuf
= 1;
4747 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4748 suffix_check
.no_wsuf
= 1;
4749 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4750 suffix_check
.no_ssuf
= 1;
4751 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4752 suffix_check
.no_lsuf
= 1;
4753 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4754 suffix_check
.no_qsuf
= 1;
4755 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4756 suffix_check
.no_ldsuf
= 1;
4758 /* Must have right number of operands. */
4759 i
.error
= number_of_operands_mismatch
;
4761 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4763 addr_prefix_disp
= -1;
4765 if (i
.operands
!= t
->operands
)
4768 /* Check processor support. */
4769 i
.error
= unsupported
;
4770 found_cpu_match
= (cpu_flags_match (t
)
4771 == CPU_FLAGS_PERFECT_MATCH
);
4772 if (!found_cpu_match
)
4775 /* Check old gcc support. */
4776 i
.error
= old_gcc_only
;
4777 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4780 /* Check AT&T mnemonic. */
4781 i
.error
= unsupported_with_intel_mnemonic
;
4782 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4785 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4786 i
.error
= unsupported_syntax
;
4787 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4788 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4789 || (intel64
&& t
->opcode_modifier
.amd64
)
4790 || (!intel64
&& t
->opcode_modifier
.intel64
))
4793 /* Check the suffix, except for some instructions in intel mode. */
4794 i
.error
= invalid_instruction_suffix
;
4795 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4796 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4797 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4798 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4799 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4800 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4801 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4804 if (!operand_size_match (t
))
4807 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4808 operand_types
[j
] = t
->operand_types
[j
];
4810 /* In general, don't allow 64-bit operands in 32-bit mode. */
4811 if (i
.suffix
== QWORD_MNEM_SUFFIX
4812 && flag_code
!= CODE_64BIT
4814 ? (!t
->opcode_modifier
.ignoresize
4815 && !intel_float_operand (t
->name
))
4816 : intel_float_operand (t
->name
) != 2)
4817 && ((!operand_types
[0].bitfield
.regmmx
4818 && !operand_types
[0].bitfield
.regxmm
4819 && !operand_types
[0].bitfield
.regymm
4820 && !operand_types
[0].bitfield
.regzmm
)
4821 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4822 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4823 && operand_types
[t
->operands
> 1].bitfield
.regymm
4824 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4825 && (t
->base_opcode
!= 0x0fc7
4826 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4829 /* In general, don't allow 32-bit operands on pre-386. */
4830 else if (i
.suffix
== LONG_MNEM_SUFFIX
4831 && !cpu_arch_flags
.bitfield
.cpui386
4833 ? (!t
->opcode_modifier
.ignoresize
4834 && !intel_float_operand (t
->name
))
4835 : intel_float_operand (t
->name
) != 2)
4836 && ((!operand_types
[0].bitfield
.regmmx
4837 && !operand_types
[0].bitfield
.regxmm
)
4838 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4839 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4842 /* Do not verify operands when there are none. */
4846 /* We've found a match; break out of loop. */
4850 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4851 into Disp32/Disp16/Disp32 operand. */
4852 if (i
.prefix
[ADDR_PREFIX
] != 0)
4854 /* There should be only one Disp operand. */
4858 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4860 if (operand_types
[j
].bitfield
.disp16
)
4862 addr_prefix_disp
= j
;
4863 operand_types
[j
].bitfield
.disp32
= 1;
4864 operand_types
[j
].bitfield
.disp16
= 0;
4870 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4872 if (operand_types
[j
].bitfield
.disp32
)
4874 addr_prefix_disp
= j
;
4875 operand_types
[j
].bitfield
.disp32
= 0;
4876 operand_types
[j
].bitfield
.disp16
= 1;
4882 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4884 if (operand_types
[j
].bitfield
.disp64
)
4886 addr_prefix_disp
= j
;
4887 operand_types
[j
].bitfield
.disp64
= 0;
4888 operand_types
[j
].bitfield
.disp32
= 1;
4896 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4897 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4900 /* We check register size if needed. */
4901 check_register
= t
->opcode_modifier
.checkregsize
;
4902 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4903 switch (t
->operands
)
4906 if (!operand_type_match (overlap0
, i
.types
[0]))
4910 /* xchg %eax, %eax is a special case. It is an aliase for nop
4911 only in 32bit mode and we can use opcode 0x90. In 64bit
4912 mode, we can't use 0x90 for xchg %eax, %eax since it should
4913 zero-extend %eax to %rax. */
4914 if (flag_code
== CODE_64BIT
4915 && t
->base_opcode
== 0x90
4916 && operand_type_equal (&i
.types
[0], &acc32
)
4917 && operand_type_equal (&i
.types
[1], &acc32
))
4921 /* If we swap operand in encoding, we either match
4922 the next one or reverse direction of operands. */
4923 if (t
->opcode_modifier
.s
)
4925 else if (t
->opcode_modifier
.d
)
4930 /* If we swap operand in encoding, we match the next one. */
4931 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4935 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4936 if (!operand_type_match (overlap0
, i
.types
[0])
4937 || !operand_type_match (overlap1
, i
.types
[1])
4939 && !operand_type_register_match (overlap0
, i
.types
[0],
4941 overlap1
, i
.types
[1],
4944 /* Check if other direction is valid ... */
4945 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4949 /* Try reversing direction of operands. */
4950 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4951 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4952 if (!operand_type_match (overlap0
, i
.types
[0])
4953 || !operand_type_match (overlap1
, i
.types
[1])
4955 && !operand_type_register_match (overlap0
,
4962 /* Does not match either direction. */
4965 /* found_reverse_match holds which of D or FloatDR
4967 if (t
->opcode_modifier
.d
)
4968 found_reverse_match
= Opcode_D
;
4969 else if (t
->opcode_modifier
.floatd
)
4970 found_reverse_match
= Opcode_FloatD
;
4972 found_reverse_match
= 0;
4973 if (t
->opcode_modifier
.floatr
)
4974 found_reverse_match
|= Opcode_FloatR
;
4978 /* Found a forward 2 operand match here. */
4979 switch (t
->operands
)
4982 overlap4
= operand_type_and (i
.types
[4],
4985 overlap3
= operand_type_and (i
.types
[3],
4988 overlap2
= operand_type_and (i
.types
[2],
4993 switch (t
->operands
)
4996 if (!operand_type_match (overlap4
, i
.types
[4])
4997 || !operand_type_register_match (overlap3
,
5005 if (!operand_type_match (overlap3
, i
.types
[3])
5007 && !operand_type_register_match (overlap2
,
5015 /* Here we make use of the fact that there are no
5016 reverse match 3 operand instructions, and all 3
5017 operand instructions only need to be checked for
5018 register consistency between operands 2 and 3. */
5019 if (!operand_type_match (overlap2
, i
.types
[2])
5021 && !operand_type_register_match (overlap1
,
5031 /* Found either forward/reverse 2, 3 or 4 operand match here:
5032 slip through to break. */
5034 if (!found_cpu_match
)
5036 found_reverse_match
= 0;
5040 /* Check if vector and VEX operands are valid. */
5041 if (check_VecOperands (t
) || VEX_check_operands (t
))
5043 specific_error
= i
.error
;
5047 /* We've found a match; break out of loop. */
5051 if (t
== current_templates
->end
)
5053 /* We found no match. */
5054 const char *err_msg
;
5055 switch (specific_error
? specific_error
: i
.error
)
5059 case operand_size_mismatch
:
5060 err_msg
= _("operand size mismatch");
5062 case operand_type_mismatch
:
5063 err_msg
= _("operand type mismatch");
5065 case register_type_mismatch
:
5066 err_msg
= _("register type mismatch");
5068 case number_of_operands_mismatch
:
5069 err_msg
= _("number of operands mismatch");
5071 case invalid_instruction_suffix
:
5072 err_msg
= _("invalid instruction suffix");
5075 err_msg
= _("constant doesn't fit in 4 bits");
5078 err_msg
= _("only supported with old gcc");
5080 case unsupported_with_intel_mnemonic
:
5081 err_msg
= _("unsupported with Intel mnemonic");
5083 case unsupported_syntax
:
5084 err_msg
= _("unsupported syntax");
5087 as_bad (_("unsupported instruction `%s'"),
5088 current_templates
->start
->name
);
5090 case invalid_vsib_address
:
5091 err_msg
= _("invalid VSIB address");
5093 case invalid_vector_register_set
:
5094 err_msg
= _("mask, index, and destination registers must be distinct");
5096 case unsupported_vector_index_register
:
5097 err_msg
= _("unsupported vector index register");
5099 case unsupported_broadcast
:
5100 err_msg
= _("unsupported broadcast");
5102 case broadcast_not_on_src_operand
:
5103 err_msg
= _("broadcast not on source memory operand");
5105 case broadcast_needed
:
5106 err_msg
= _("broadcast is needed for operand of such type");
5108 case unsupported_masking
:
5109 err_msg
= _("unsupported masking");
5111 case mask_not_on_destination
:
5112 err_msg
= _("mask not on destination operand");
5114 case no_default_mask
:
5115 err_msg
= _("default mask isn't allowed");
5117 case unsupported_rc_sae
:
5118 err_msg
= _("unsupported static rounding/sae");
5120 case rc_sae_operand_not_last_imm
:
5122 err_msg
= _("RC/SAE operand must precede immediate operands");
5124 err_msg
= _("RC/SAE operand must follow immediate operands");
5126 case invalid_register_operand
:
5127 err_msg
= _("invalid register operand");
5130 as_bad (_("%s for `%s'"), err_msg
,
5131 current_templates
->start
->name
);
5135 if (!quiet_warnings
)
5138 && (i
.types
[0].bitfield
.jumpabsolute
5139 != operand_types
[0].bitfield
.jumpabsolute
))
5141 as_warn (_("indirect %s without `*'"), t
->name
);
5144 if (t
->opcode_modifier
.isprefix
5145 && t
->opcode_modifier
.ignoresize
)
5147 /* Warn them that a data or address size prefix doesn't
5148 affect assembly of the next line of code. */
5149 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5153 /* Copy the template we found. */
5156 if (addr_prefix_disp
!= -1)
5157 i
.tm
.operand_types
[addr_prefix_disp
]
5158 = operand_types
[addr_prefix_disp
];
5160 if (found_reverse_match
)
5162 /* If we found a reverse match we must alter the opcode
5163 direction bit. found_reverse_match holds bits to change
5164 (different for int & float insns). */
5166 i
.tm
.base_opcode
^= found_reverse_match
;
5168 i
.tm
.operand_types
[0] = operand_types
[1];
5169 i
.tm
.operand_types
[1] = operand_types
[0];
5178 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5179 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5181 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5183 as_bad (_("`%s' operand %d must use `%ses' segment"),
5189 /* There's only ever one segment override allowed per instruction.
5190 This instruction possibly has a legal segment override on the
5191 second operand, so copy the segment to where non-string
5192 instructions store it, allowing common code. */
5193 i
.seg
[0] = i
.seg
[1];
5195 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5197 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5199 as_bad (_("`%s' operand %d must use `%ses' segment"),
5210 process_suffix (void)
5212 /* If matched instruction specifies an explicit instruction mnemonic
5214 if (i
.tm
.opcode_modifier
.size16
)
5215 i
.suffix
= WORD_MNEM_SUFFIX
;
5216 else if (i
.tm
.opcode_modifier
.size32
)
5217 i
.suffix
= LONG_MNEM_SUFFIX
;
5218 else if (i
.tm
.opcode_modifier
.size64
)
5219 i
.suffix
= QWORD_MNEM_SUFFIX
;
5220 else if (i
.reg_operands
)
5222 /* If there's no instruction mnemonic suffix we try to invent one
5223 based on register operands. */
5226 /* We take i.suffix from the last register operand specified,
5227 Destination register type is more significant than source
5228 register type. crc32 in SSE4.2 prefers source register
5230 if (i
.tm
.base_opcode
== 0xf20f38f1)
5232 if (i
.types
[0].bitfield
.reg16
)
5233 i
.suffix
= WORD_MNEM_SUFFIX
;
5234 else if (i
.types
[0].bitfield
.reg32
)
5235 i
.suffix
= LONG_MNEM_SUFFIX
;
5236 else if (i
.types
[0].bitfield
.reg64
)
5237 i
.suffix
= QWORD_MNEM_SUFFIX
;
5239 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5241 if (i
.types
[0].bitfield
.reg8
)
5242 i
.suffix
= BYTE_MNEM_SUFFIX
;
5249 if (i
.tm
.base_opcode
== 0xf20f38f1
5250 || i
.tm
.base_opcode
== 0xf20f38f0)
5252 /* We have to know the operand size for crc32. */
5253 as_bad (_("ambiguous memory operand size for `%s`"),
5258 for (op
= i
.operands
; --op
>= 0;)
5259 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5261 if (i
.types
[op
].bitfield
.reg8
)
5263 i
.suffix
= BYTE_MNEM_SUFFIX
;
5266 else if (i
.types
[op
].bitfield
.reg16
)
5268 i
.suffix
= WORD_MNEM_SUFFIX
;
5271 else if (i
.types
[op
].bitfield
.reg32
)
5273 i
.suffix
= LONG_MNEM_SUFFIX
;
5276 else if (i
.types
[op
].bitfield
.reg64
)
5278 i
.suffix
= QWORD_MNEM_SUFFIX
;
5284 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5287 && i
.tm
.opcode_modifier
.ignoresize
5288 && i
.tm
.opcode_modifier
.no_bsuf
)
5290 else if (!check_byte_reg ())
5293 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5296 && i
.tm
.opcode_modifier
.ignoresize
5297 && i
.tm
.opcode_modifier
.no_lsuf
)
5299 else if (!check_long_reg ())
5302 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5305 && i
.tm
.opcode_modifier
.ignoresize
5306 && i
.tm
.opcode_modifier
.no_qsuf
)
5308 else if (!check_qword_reg ())
5311 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5314 && i
.tm
.opcode_modifier
.ignoresize
5315 && i
.tm
.opcode_modifier
.no_wsuf
)
5317 else if (!check_word_reg ())
5320 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5321 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5322 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5324 /* Skip if the instruction has x/y/z suffix. match_template
5325 should check if it is a valid suffix. */
5327 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5328 /* Do nothing if the instruction is going to ignore the prefix. */
5333 else if (i
.tm
.opcode_modifier
.defaultsize
5335 /* exclude fldenv/frstor/fsave/fstenv */
5336 && i
.tm
.opcode_modifier
.no_ssuf
)
5338 i
.suffix
= stackop_size
;
5340 else if (intel_syntax
5342 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5343 || i
.tm
.opcode_modifier
.jumpbyte
5344 || i
.tm
.opcode_modifier
.jumpintersegment
5345 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5346 && i
.tm
.extension_opcode
<= 3)))
5351 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5353 i
.suffix
= QWORD_MNEM_SUFFIX
;
5357 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5358 i
.suffix
= LONG_MNEM_SUFFIX
;
5361 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5362 i
.suffix
= WORD_MNEM_SUFFIX
;
5371 if (i
.tm
.opcode_modifier
.w
)
5373 as_bad (_("no instruction mnemonic suffix given and "
5374 "no register operands; can't size instruction"));
5380 unsigned int suffixes
;
5382 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5383 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5385 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5387 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5389 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5391 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5394 /* There are more than suffix matches. */
5395 if (i
.tm
.opcode_modifier
.w
5396 || ((suffixes
& (suffixes
- 1))
5397 && !i
.tm
.opcode_modifier
.defaultsize
5398 && !i
.tm
.opcode_modifier
.ignoresize
))
5400 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5406 /* Change the opcode based on the operand size given by i.suffix;
5407 We don't need to change things for byte insns. */
5410 && i
.suffix
!= BYTE_MNEM_SUFFIX
5411 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5412 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5413 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5415 /* It's not a byte, select word/dword operation. */
5416 if (i
.tm
.opcode_modifier
.w
)
5418 if (i
.tm
.opcode_modifier
.shortform
)
5419 i
.tm
.base_opcode
|= 8;
5421 i
.tm
.base_opcode
|= 1;
5424 /* Now select between word & dword operations via the operand
5425 size prefix, except for instructions that will ignore this
5427 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5429 /* The address size override prefix changes the size of the
5431 if ((flag_code
== CODE_32BIT
5432 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5433 || (flag_code
!= CODE_32BIT
5434 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5435 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5438 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5439 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5440 && !i
.tm
.opcode_modifier
.ignoresize
5441 && !i
.tm
.opcode_modifier
.floatmf
5442 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5443 || (flag_code
== CODE_64BIT
5444 && i
.tm
.opcode_modifier
.jumpbyte
)))
5446 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5448 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5449 prefix
= ADDR_PREFIX_OPCODE
;
5451 if (!add_prefix (prefix
))
5455 /* Set mode64 for an operand. */
5456 if (i
.suffix
== QWORD_MNEM_SUFFIX
5457 && flag_code
== CODE_64BIT
5458 && !i
.tm
.opcode_modifier
.norex64
)
5460 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5461 need rex64. cmpxchg8b is also a special case. */
5462 if (! (i
.operands
== 2
5463 && i
.tm
.base_opcode
== 0x90
5464 && i
.tm
.extension_opcode
== None
5465 && operand_type_equal (&i
.types
[0], &acc64
)
5466 && operand_type_equal (&i
.types
[1], &acc64
))
5467 && ! (i
.operands
== 1
5468 && i
.tm
.base_opcode
== 0xfc7
5469 && i
.tm
.extension_opcode
== 1
5470 && !operand_type_check (i
.types
[0], reg
)
5471 && operand_type_check (i
.types
[0], anymem
)))
5475 /* Size floating point instruction. */
5476 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5477 if (i
.tm
.opcode_modifier
.floatmf
)
5478 i
.tm
.base_opcode
^= 4;
5485 check_byte_reg (void)
5489 for (op
= i
.operands
; --op
>= 0;)
5491 /* If this is an eight bit register, it's OK. If it's the 16 or
5492 32 bit version of an eight bit register, we will just use the
5493 low portion, and that's OK too. */
5494 if (i
.types
[op
].bitfield
.reg8
)
5497 /* I/O port address operands are OK too. */
5498 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5501 /* crc32 doesn't generate this warning. */
5502 if (i
.tm
.base_opcode
== 0xf20f38f0)
5505 if ((i
.types
[op
].bitfield
.reg16
5506 || i
.types
[op
].bitfield
.reg32
5507 || i
.types
[op
].bitfield
.reg64
)
5508 && i
.op
[op
].regs
->reg_num
< 4
5509 /* Prohibit these changes in 64bit mode, since the lowering
5510 would be more complicated. */
5511 && flag_code
!= CODE_64BIT
)
5513 #if REGISTER_WARNINGS
5514 if (!quiet_warnings
)
5515 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5517 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5518 ? REGNAM_AL
- REGNAM_AX
5519 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5521 i
.op
[op
].regs
->reg_name
,
5526 /* Any other register is bad. */
5527 if (i
.types
[op
].bitfield
.reg16
5528 || i
.types
[op
].bitfield
.reg32
5529 || i
.types
[op
].bitfield
.reg64
5530 || i
.types
[op
].bitfield
.regmmx
5531 || i
.types
[op
].bitfield
.regxmm
5532 || i
.types
[op
].bitfield
.regymm
5533 || i
.types
[op
].bitfield
.regzmm
5534 || i
.types
[op
].bitfield
.sreg2
5535 || i
.types
[op
].bitfield
.sreg3
5536 || i
.types
[op
].bitfield
.control
5537 || i
.types
[op
].bitfield
.debug
5538 || i
.types
[op
].bitfield
.test
5539 || i
.types
[op
].bitfield
.floatreg
5540 || i
.types
[op
].bitfield
.floatacc
)
5542 as_bad (_("`%s%s' not allowed with `%s%c'"),
5544 i
.op
[op
].regs
->reg_name
,
5554 check_long_reg (void)
5558 for (op
= i
.operands
; --op
>= 0;)
5559 /* Reject eight bit registers, except where the template requires
5560 them. (eg. movzb) */
5561 if (i
.types
[op
].bitfield
.reg8
5562 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5563 || i
.tm
.operand_types
[op
].bitfield
.reg32
5564 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5566 as_bad (_("`%s%s' not allowed with `%s%c'"),
5568 i
.op
[op
].regs
->reg_name
,
5573 /* Warn if the e prefix on a general reg is missing. */
5574 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5575 && i
.types
[op
].bitfield
.reg16
5576 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5577 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5579 /* Prohibit these changes in the 64bit mode, since the
5580 lowering is more complicated. */
5581 if (flag_code
== CODE_64BIT
)
5583 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5584 register_prefix
, i
.op
[op
].regs
->reg_name
,
5588 #if REGISTER_WARNINGS
5589 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5591 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5592 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5595 /* Warn if the r prefix on a general reg is present. */
5596 else if (i
.types
[op
].bitfield
.reg64
5597 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5598 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5601 && i
.tm
.opcode_modifier
.toqword
5602 && !i
.types
[0].bitfield
.regxmm
)
5604 /* Convert to QWORD. We want REX byte. */
5605 i
.suffix
= QWORD_MNEM_SUFFIX
;
5609 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5610 register_prefix
, i
.op
[op
].regs
->reg_name
,
5619 check_qword_reg (void)
5623 for (op
= i
.operands
; --op
>= 0; )
5624 /* Reject eight bit registers, except where the template requires
5625 them. (eg. movzb) */
5626 if (i
.types
[op
].bitfield
.reg8
5627 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5628 || i
.tm
.operand_types
[op
].bitfield
.reg32
5629 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5631 as_bad (_("`%s%s' not allowed with `%s%c'"),
5633 i
.op
[op
].regs
->reg_name
,
5638 /* Warn if the r prefix on a general reg is missing. */
5639 else if ((i
.types
[op
].bitfield
.reg16
5640 || i
.types
[op
].bitfield
.reg32
)
5641 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5642 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5644 /* Prohibit these changes in the 64bit mode, since the
5645 lowering is more complicated. */
5647 && i
.tm
.opcode_modifier
.todword
5648 && !i
.types
[0].bitfield
.regxmm
)
5650 /* Convert to DWORD. We don't want REX byte. */
5651 i
.suffix
= LONG_MNEM_SUFFIX
;
5655 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5656 register_prefix
, i
.op
[op
].regs
->reg_name
,
5665 check_word_reg (void)
5668 for (op
= i
.operands
; --op
>= 0;)
5669 /* Reject eight bit registers, except where the template requires
5670 them. (eg. movzb) */
5671 if (i
.types
[op
].bitfield
.reg8
5672 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5673 || i
.tm
.operand_types
[op
].bitfield
.reg32
5674 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5676 as_bad (_("`%s%s' not allowed with `%s%c'"),
5678 i
.op
[op
].regs
->reg_name
,
5683 /* Warn if the e or r prefix on a general reg is present. */
5684 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5685 && (i
.types
[op
].bitfield
.reg32
5686 || i
.types
[op
].bitfield
.reg64
)
5687 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5688 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5690 /* Prohibit these changes in the 64bit mode, since the
5691 lowering is more complicated. */
5692 if (flag_code
== CODE_64BIT
)
5694 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5695 register_prefix
, i
.op
[op
].regs
->reg_name
,
5699 #if REGISTER_WARNINGS
5700 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5702 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5703 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5710 update_imm (unsigned int j
)
5712 i386_operand_type overlap
= i
.types
[j
];
5713 if ((overlap
.bitfield
.imm8
5714 || overlap
.bitfield
.imm8s
5715 || overlap
.bitfield
.imm16
5716 || overlap
.bitfield
.imm32
5717 || overlap
.bitfield
.imm32s
5718 || overlap
.bitfield
.imm64
)
5719 && !operand_type_equal (&overlap
, &imm8
)
5720 && !operand_type_equal (&overlap
, &imm8s
)
5721 && !operand_type_equal (&overlap
, &imm16
)
5722 && !operand_type_equal (&overlap
, &imm32
)
5723 && !operand_type_equal (&overlap
, &imm32s
)
5724 && !operand_type_equal (&overlap
, &imm64
))
5728 i386_operand_type temp
;
5730 operand_type_set (&temp
, 0);
5731 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5733 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5734 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5736 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5737 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5738 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5740 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5741 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5744 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5747 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5748 || operand_type_equal (&overlap
, &imm16_32
)
5749 || operand_type_equal (&overlap
, &imm16_32s
))
5751 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5756 if (!operand_type_equal (&overlap
, &imm8
)
5757 && !operand_type_equal (&overlap
, &imm8s
)
5758 && !operand_type_equal (&overlap
, &imm16
)
5759 && !operand_type_equal (&overlap
, &imm32
)
5760 && !operand_type_equal (&overlap
, &imm32s
)
5761 && !operand_type_equal (&overlap
, &imm64
))
5763 as_bad (_("no instruction mnemonic suffix given; "
5764 "can't determine immediate size"));
5768 i
.types
[j
] = overlap
;
5778 /* Update the first 2 immediate operands. */
5779 n
= i
.operands
> 2 ? 2 : i
.operands
;
5782 for (j
= 0; j
< n
; j
++)
5783 if (update_imm (j
) == 0)
5786 /* The 3rd operand can't be immediate operand. */
5787 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5794 bad_implicit_operand (int xmm
)
5796 const char *ireg
= xmm
? "xmm0" : "ymm0";
5799 as_bad (_("the last operand of `%s' must be `%s%s'"),
5800 i
.tm
.name
, register_prefix
, ireg
);
5802 as_bad (_("the first operand of `%s' must be `%s%s'"),
5803 i
.tm
.name
, register_prefix
, ireg
);
5808 process_operands (void)
5810 /* Default segment register this instruction will use for memory
5811 accesses. 0 means unknown. This is only for optimizing out
5812 unnecessary segment overrides. */
5813 const seg_entry
*default_seg
= 0;
5815 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5817 unsigned int dupl
= i
.operands
;
5818 unsigned int dest
= dupl
- 1;
5821 /* The destination must be an xmm register. */
5822 gas_assert (i
.reg_operands
5823 && MAX_OPERANDS
> dupl
5824 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5826 if (i
.tm
.opcode_modifier
.firstxmm0
)
5828 /* The first operand is implicit and must be xmm0. */
5829 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5830 if (register_number (i
.op
[0].regs
) != 0)
5831 return bad_implicit_operand (1);
5833 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5835 /* Keep xmm0 for instructions with VEX prefix and 3
5841 /* We remove the first xmm0 and keep the number of
5842 operands unchanged, which in fact duplicates the
5844 for (j
= 1; j
< i
.operands
; j
++)
5846 i
.op
[j
- 1] = i
.op
[j
];
5847 i
.types
[j
- 1] = i
.types
[j
];
5848 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5852 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5854 gas_assert ((MAX_OPERANDS
- 1) > dupl
5855 && (i
.tm
.opcode_modifier
.vexsources
5858 /* Add the implicit xmm0 for instructions with VEX prefix
5860 for (j
= i
.operands
; j
> 0; j
--)
5862 i
.op
[j
] = i
.op
[j
- 1];
5863 i
.types
[j
] = i
.types
[j
- 1];
5864 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5867 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5868 i
.types
[0] = regxmm
;
5869 i
.tm
.operand_types
[0] = regxmm
;
5872 i
.reg_operands
+= 2;
5877 i
.op
[dupl
] = i
.op
[dest
];
5878 i
.types
[dupl
] = i
.types
[dest
];
5879 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5888 i
.op
[dupl
] = i
.op
[dest
];
5889 i
.types
[dupl
] = i
.types
[dest
];
5890 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5893 if (i
.tm
.opcode_modifier
.immext
)
5896 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5900 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5901 gas_assert (i
.reg_operands
5902 && (operand_type_equal (&i
.types
[0], ®xmm
)
5903 || operand_type_equal (&i
.types
[0], ®ymm
)
5904 || operand_type_equal (&i
.types
[0], ®zmm
)));
5905 if (register_number (i
.op
[0].regs
) != 0)
5906 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5908 for (j
= 1; j
< i
.operands
; j
++)
5910 i
.op
[j
- 1] = i
.op
[j
];
5911 i
.types
[j
- 1] = i
.types
[j
];
5913 /* We need to adjust fields in i.tm since they are used by
5914 build_modrm_byte. */
5915 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5922 else if (i
.tm
.opcode_modifier
.regkludge
)
5924 /* The imul $imm, %reg instruction is converted into
5925 imul $imm, %reg, %reg, and the clr %reg instruction
5926 is converted into xor %reg, %reg. */
5928 unsigned int first_reg_op
;
5930 if (operand_type_check (i
.types
[0], reg
))
5934 /* Pretend we saw the extra register operand. */
5935 gas_assert (i
.reg_operands
== 1
5936 && i
.op
[first_reg_op
+ 1].regs
== 0);
5937 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5938 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5943 if (i
.tm
.opcode_modifier
.shortform
)
5945 if (i
.types
[0].bitfield
.sreg2
5946 || i
.types
[0].bitfield
.sreg3
)
5948 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5949 && i
.op
[0].regs
->reg_num
== 1)
5951 as_bad (_("you can't `pop %scs'"), register_prefix
);
5954 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5955 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5960 /* The register or float register operand is in operand
5964 if (i
.types
[0].bitfield
.floatreg
5965 || operand_type_check (i
.types
[0], reg
))
5969 /* Register goes in low 3 bits of opcode. */
5970 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5971 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5973 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5975 /* Warn about some common errors, but press on regardless.
5976 The first case can be generated by gcc (<= 2.8.1). */
5977 if (i
.operands
== 2)
5979 /* Reversed arguments on faddp, fsubp, etc. */
5980 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5981 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5982 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5986 /* Extraneous `l' suffix on fp insn. */
5987 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5988 register_prefix
, i
.op
[0].regs
->reg_name
);
5993 else if (i
.tm
.opcode_modifier
.modrm
)
5995 /* The opcode is completed (modulo i.tm.extension_opcode which
5996 must be put into the modrm byte). Now, we make the modrm and
5997 index base bytes based on all the info we've collected. */
5999 default_seg
= build_modrm_byte ();
6001 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6005 else if (i
.tm
.opcode_modifier
.isstring
)
6007 /* For the string instructions that allow a segment override
6008 on one of their operands, the default segment is ds. */
6012 if (i
.tm
.base_opcode
== 0x8d /* lea */
6015 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6017 /* If a segment was explicitly specified, and the specified segment
6018 is not the default, use an opcode prefix to select it. If we
6019 never figured out what the default segment is, then default_seg
6020 will be zero at this point, and the specified segment prefix will
6022 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6024 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6030 static const seg_entry
*
6031 build_modrm_byte (void)
6033 const seg_entry
*default_seg
= 0;
6034 unsigned int source
, dest
;
6037 /* The first operand of instructions with VEX prefix and 3 sources
6038 must be VEX_Imm4. */
6039 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6042 unsigned int nds
, reg_slot
;
6045 if (i
.tm
.opcode_modifier
.veximmext
6046 && i
.tm
.opcode_modifier
.immext
)
6048 dest
= i
.operands
- 2;
6049 gas_assert (dest
== 3);
6052 dest
= i
.operands
- 1;
6055 /* There are 2 kinds of instructions:
6056 1. 5 operands: 4 register operands or 3 register operands
6057 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6058 VexW0 or VexW1. The destination must be either XMM, YMM or
6060 2. 4 operands: 4 register operands or 3 register operands
6061 plus 1 memory operand, VexXDS, and VexImmExt */
6062 gas_assert ((i
.reg_operands
== 4
6063 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6064 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6065 && (i
.tm
.opcode_modifier
.veximmext
6066 || (i
.imm_operands
== 1
6067 && i
.types
[0].bitfield
.vec_imm4
6068 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6069 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6070 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6071 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6072 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6074 if (i
.imm_operands
== 0)
6076 /* When there is no immediate operand, generate an 8bit
6077 immediate operand to encode the first operand. */
6078 exp
= &im_expressions
[i
.imm_operands
++];
6079 i
.op
[i
.operands
].imms
= exp
;
6080 i
.types
[i
.operands
] = imm8
;
6082 /* If VexW1 is set, the first operand is the source and
6083 the second operand is encoded in the immediate operand. */
6084 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6095 /* FMA swaps REG and NDS. */
6096 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6104 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6106 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6108 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6110 exp
->X_op
= O_constant
;
6111 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6112 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6116 unsigned int imm_slot
;
6118 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6120 /* If VexW0 is set, the third operand is the source and
6121 the second operand is encoded in the immediate
6128 /* VexW1 is set, the second operand is the source and
6129 the third operand is encoded in the immediate
6135 if (i
.tm
.opcode_modifier
.immext
)
6137 /* When ImmExt is set, the immdiate byte is the last
6139 imm_slot
= i
.operands
- 1;
6147 /* Turn on Imm8 so that output_imm will generate it. */
6148 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6151 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6153 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6155 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6157 i
.op
[imm_slot
].imms
->X_add_number
6158 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6159 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6162 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6163 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6165 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6167 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6172 /* i.reg_operands MUST be the number of real register operands;
6173 implicit registers do not count. If there are 3 register
6174 operands, it must be a instruction with VexNDS. For a
6175 instruction with VexNDD, the destination register is encoded
6176 in VEX prefix. If there are 4 register operands, it must be
6177 a instruction with VEX prefix and 3 sources. */
6178 if (i
.mem_operands
== 0
6179 && ((i
.reg_operands
== 2
6180 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6181 || (i
.reg_operands
== 3
6182 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6183 || (i
.reg_operands
== 4 && vex_3_sources
)))
6191 /* When there are 3 operands, one of them may be immediate,
6192 which may be the first or the last operand. Otherwise,
6193 the first operand must be shift count register (cl) or it
6194 is an instruction with VexNDS. */
6195 gas_assert (i
.imm_operands
== 1
6196 || (i
.imm_operands
== 0
6197 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6198 || i
.types
[0].bitfield
.shiftcount
)));
6199 if (operand_type_check (i
.types
[0], imm
)
6200 || i
.types
[0].bitfield
.shiftcount
)
6206 /* When there are 4 operands, the first two must be 8bit
6207 immediate operands. The source operand will be the 3rd
6210 For instructions with VexNDS, if the first operand
6211 an imm8, the source operand is the 2nd one. If the last
6212 operand is imm8, the source operand is the first one. */
6213 gas_assert ((i
.imm_operands
== 2
6214 && i
.types
[0].bitfield
.imm8
6215 && i
.types
[1].bitfield
.imm8
)
6216 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6217 && i
.imm_operands
== 1
6218 && (i
.types
[0].bitfield
.imm8
6219 || i
.types
[i
.operands
- 1].bitfield
.imm8
6221 if (i
.imm_operands
== 2)
6225 if (i
.types
[0].bitfield
.imm8
)
6232 if (i
.tm
.opcode_modifier
.evex
)
6234 /* For EVEX instructions, when there are 5 operands, the
6235 first one must be immediate operand. If the second one
6236 is immediate operand, the source operand is the 3th
6237 one. If the last one is immediate operand, the source
6238 operand is the 2nd one. */
6239 gas_assert (i
.imm_operands
== 2
6240 && i
.tm
.opcode_modifier
.sae
6241 && operand_type_check (i
.types
[0], imm
));
6242 if (operand_type_check (i
.types
[1], imm
))
6244 else if (operand_type_check (i
.types
[4], imm
))
6258 /* RC/SAE operand could be between DEST and SRC. That happens
6259 when one operand is GPR and the other one is XMM/YMM/ZMM
6261 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6264 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6266 /* For instructions with VexNDS, the register-only source
6267 operand must be 32/64bit integer, XMM, YMM or ZMM
6268 register. It is encoded in VEX prefix. We need to
6269 clear RegMem bit before calling operand_type_equal. */
6271 i386_operand_type op
;
6274 /* Check register-only source operand when two source
6275 operands are swapped. */
6276 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6277 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6285 op
= i
.tm
.operand_types
[vvvv
];
6286 op
.bitfield
.regmem
= 0;
6287 if ((dest
+ 1) >= i
.operands
6288 || (!op
.bitfield
.reg32
6289 && op
.bitfield
.reg64
6290 && !operand_type_equal (&op
, ®xmm
)
6291 && !operand_type_equal (&op
, ®ymm
)
6292 && !operand_type_equal (&op
, ®zmm
)
6293 && !operand_type_equal (&op
, ®mask
)))
6295 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6301 /* One of the register operands will be encoded in the i.tm.reg
6302 field, the other in the combined i.tm.mode and i.tm.regmem
6303 fields. If no form of this instruction supports a memory
6304 destination operand, then we assume the source operand may
6305 sometimes be a memory operand and so we need to store the
6306 destination in the i.rm.reg field. */
6307 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6308 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6310 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6311 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6312 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6314 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6316 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6318 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6323 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6324 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6325 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6327 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6329 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6331 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6334 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6336 if (!i
.types
[0].bitfield
.control
6337 && !i
.types
[1].bitfield
.control
)
6339 i
.rex
&= ~(REX_R
| REX_B
);
6340 add_prefix (LOCK_PREFIX_OPCODE
);
6344 { /* If it's not 2 reg operands... */
6349 unsigned int fake_zero_displacement
= 0;
6352 for (op
= 0; op
< i
.operands
; op
++)
6353 if (operand_type_check (i
.types
[op
], anymem
))
6355 gas_assert (op
< i
.operands
);
6357 if (i
.tm
.opcode_modifier
.vecsib
)
6359 if (i
.index_reg
->reg_num
== RegEiz
6360 || i
.index_reg
->reg_num
== RegRiz
)
6363 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6366 i
.sib
.base
= NO_BASE_REGISTER
;
6367 i
.sib
.scale
= i
.log2_scale_factor
;
6368 /* No Vec_Disp8 if there is no base. */
6369 i
.types
[op
].bitfield
.vec_disp8
= 0;
6370 i
.types
[op
].bitfield
.disp8
= 0;
6371 i
.types
[op
].bitfield
.disp16
= 0;
6372 i
.types
[op
].bitfield
.disp64
= 0;
6373 if (flag_code
!= CODE_64BIT
)
6375 /* Must be 32 bit */
6376 i
.types
[op
].bitfield
.disp32
= 1;
6377 i
.types
[op
].bitfield
.disp32s
= 0;
6381 i
.types
[op
].bitfield
.disp32
= 0;
6382 i
.types
[op
].bitfield
.disp32s
= 1;
6385 i
.sib
.index
= i
.index_reg
->reg_num
;
6386 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6388 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6394 if (i
.base_reg
== 0)
6397 if (!i
.disp_operands
)
6399 fake_zero_displacement
= 1;
6400 /* Instructions with VSIB byte need 32bit displacement
6401 if there is no base register. */
6402 if (i
.tm
.opcode_modifier
.vecsib
)
6403 i
.types
[op
].bitfield
.disp32
= 1;
6405 if (i
.index_reg
== 0)
6407 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6408 /* Operand is just <disp> */
6409 if (flag_code
== CODE_64BIT
)
6411 /* 64bit mode overwrites the 32bit absolute
6412 addressing by RIP relative addressing and
6413 absolute addressing is encoded by one of the
6414 redundant SIB forms. */
6415 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6416 i
.sib
.base
= NO_BASE_REGISTER
;
6417 i
.sib
.index
= NO_INDEX_REGISTER
;
6418 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6419 ? disp32s
: disp32
);
6421 else if ((flag_code
== CODE_16BIT
)
6422 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6424 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6425 i
.types
[op
] = disp16
;
6429 i
.rm
.regmem
= NO_BASE_REGISTER
;
6430 i
.types
[op
] = disp32
;
6433 else if (!i
.tm
.opcode_modifier
.vecsib
)
6435 /* !i.base_reg && i.index_reg */
6436 if (i
.index_reg
->reg_num
== RegEiz
6437 || i
.index_reg
->reg_num
== RegRiz
)
6438 i
.sib
.index
= NO_INDEX_REGISTER
;
6440 i
.sib
.index
= i
.index_reg
->reg_num
;
6441 i
.sib
.base
= NO_BASE_REGISTER
;
6442 i
.sib
.scale
= i
.log2_scale_factor
;
6443 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6444 /* No Vec_Disp8 if there is no base. */
6445 i
.types
[op
].bitfield
.vec_disp8
= 0;
6446 i
.types
[op
].bitfield
.disp8
= 0;
6447 i
.types
[op
].bitfield
.disp16
= 0;
6448 i
.types
[op
].bitfield
.disp64
= 0;
6449 if (flag_code
!= CODE_64BIT
)
6451 /* Must be 32 bit */
6452 i
.types
[op
].bitfield
.disp32
= 1;
6453 i
.types
[op
].bitfield
.disp32s
= 0;
6457 i
.types
[op
].bitfield
.disp32
= 0;
6458 i
.types
[op
].bitfield
.disp32s
= 1;
6460 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6464 /* RIP addressing for 64bit mode. */
6465 else if (i
.base_reg
->reg_num
== RegRip
||
6466 i
.base_reg
->reg_num
== RegEip
)
6468 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6469 i
.rm
.regmem
= NO_BASE_REGISTER
;
6470 i
.types
[op
].bitfield
.disp8
= 0;
6471 i
.types
[op
].bitfield
.disp16
= 0;
6472 i
.types
[op
].bitfield
.disp32
= 0;
6473 i
.types
[op
].bitfield
.disp32s
= 1;
6474 i
.types
[op
].bitfield
.disp64
= 0;
6475 i
.types
[op
].bitfield
.vec_disp8
= 0;
6476 i
.flags
[op
] |= Operand_PCrel
;
6477 if (! i
.disp_operands
)
6478 fake_zero_displacement
= 1;
6480 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6482 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6483 switch (i
.base_reg
->reg_num
)
6486 if (i
.index_reg
== 0)
6488 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6489 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6493 if (i
.index_reg
== 0)
6496 if (operand_type_check (i
.types
[op
], disp
) == 0)
6498 /* fake (%bp) into 0(%bp) */
6499 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6500 i
.types
[op
].bitfield
.vec_disp8
= 1;
6502 i
.types
[op
].bitfield
.disp8
= 1;
6503 fake_zero_displacement
= 1;
6506 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6507 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6509 default: /* (%si) -> 4 or (%di) -> 5 */
6510 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6512 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6514 else /* i.base_reg and 32/64 bit mode */
6516 if (flag_code
== CODE_64BIT
6517 && operand_type_check (i
.types
[op
], disp
))
6519 i386_operand_type temp
;
6520 operand_type_set (&temp
, 0);
6521 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6522 temp
.bitfield
.vec_disp8
6523 = i
.types
[op
].bitfield
.vec_disp8
;
6525 if (i
.prefix
[ADDR_PREFIX
] == 0)
6526 i
.types
[op
].bitfield
.disp32s
= 1;
6528 i
.types
[op
].bitfield
.disp32
= 1;
6531 if (!i
.tm
.opcode_modifier
.vecsib
)
6532 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6533 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6535 i
.sib
.base
= i
.base_reg
->reg_num
;
6536 /* x86-64 ignores REX prefix bit here to avoid decoder
6538 if (!(i
.base_reg
->reg_flags
& RegRex
)
6539 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6540 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6542 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6544 fake_zero_displacement
= 1;
6545 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6546 i
.types
[op
].bitfield
.vec_disp8
= 1;
6548 i
.types
[op
].bitfield
.disp8
= 1;
6550 i
.sib
.scale
= i
.log2_scale_factor
;
6551 if (i
.index_reg
== 0)
6553 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6554 /* <disp>(%esp) becomes two byte modrm with no index
6555 register. We've already stored the code for esp
6556 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6557 Any base register besides %esp will not use the
6558 extra modrm byte. */
6559 i
.sib
.index
= NO_INDEX_REGISTER
;
6561 else if (!i
.tm
.opcode_modifier
.vecsib
)
6563 if (i
.index_reg
->reg_num
== RegEiz
6564 || i
.index_reg
->reg_num
== RegRiz
)
6565 i
.sib
.index
= NO_INDEX_REGISTER
;
6567 i
.sib
.index
= i
.index_reg
->reg_num
;
6568 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6569 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6574 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6575 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6579 if (!fake_zero_displacement
6583 fake_zero_displacement
= 1;
6584 if (i
.disp_encoding
== disp_encoding_8bit
)
6585 i
.types
[op
].bitfield
.disp8
= 1;
6587 i
.types
[op
].bitfield
.disp32
= 1;
6589 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6593 if (fake_zero_displacement
)
6595 /* Fakes a zero displacement assuming that i.types[op]
6596 holds the correct displacement size. */
6599 gas_assert (i
.op
[op
].disps
== 0);
6600 exp
= &disp_expressions
[i
.disp_operands
++];
6601 i
.op
[op
].disps
= exp
;
6602 exp
->X_op
= O_constant
;
6603 exp
->X_add_number
= 0;
6604 exp
->X_add_symbol
= (symbolS
*) 0;
6605 exp
->X_op_symbol
= (symbolS
*) 0;
6613 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6615 if (operand_type_check (i
.types
[0], imm
))
6616 i
.vex
.register_specifier
= NULL
;
6619 /* VEX.vvvv encodes one of the sources when the first
6620 operand is not an immediate. */
6621 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6622 i
.vex
.register_specifier
= i
.op
[0].regs
;
6624 i
.vex
.register_specifier
= i
.op
[1].regs
;
6627 /* Destination is a XMM register encoded in the ModRM.reg
6629 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6630 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6633 /* ModRM.rm and VEX.B encodes the other source. */
6634 if (!i
.mem_operands
)
6638 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6639 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6641 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6643 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6647 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6649 i
.vex
.register_specifier
= i
.op
[2].regs
;
6650 if (!i
.mem_operands
)
6653 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6654 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6658 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6659 (if any) based on i.tm.extension_opcode. Again, we must be
6660 careful to make sure that segment/control/debug/test/MMX
6661 registers are coded into the i.rm.reg field. */
6662 else if (i
.reg_operands
)
6665 unsigned int vex_reg
= ~0;
6667 for (op
= 0; op
< i
.operands
; op
++)
6668 if (i
.types
[op
].bitfield
.reg8
6669 || i
.types
[op
].bitfield
.reg16
6670 || i
.types
[op
].bitfield
.reg32
6671 || i
.types
[op
].bitfield
.reg64
6672 || i
.types
[op
].bitfield
.regmmx
6673 || i
.types
[op
].bitfield
.regxmm
6674 || i
.types
[op
].bitfield
.regymm
6675 || i
.types
[op
].bitfield
.regbnd
6676 || i
.types
[op
].bitfield
.regzmm
6677 || i
.types
[op
].bitfield
.regmask
6678 || i
.types
[op
].bitfield
.sreg2
6679 || i
.types
[op
].bitfield
.sreg3
6680 || i
.types
[op
].bitfield
.control
6681 || i
.types
[op
].bitfield
.debug
6682 || i
.types
[op
].bitfield
.test
)
6687 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6689 /* For instructions with VexNDS, the register-only
6690 source operand is encoded in VEX prefix. */
6691 gas_assert (mem
!= (unsigned int) ~0);
6696 gas_assert (op
< i
.operands
);
6700 /* Check register-only source operand when two source
6701 operands are swapped. */
6702 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6703 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6707 gas_assert (mem
== (vex_reg
+ 1)
6708 && op
< i
.operands
);
6713 gas_assert (vex_reg
< i
.operands
);
6717 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6719 /* For instructions with VexNDD, the register destination
6720 is encoded in VEX prefix. */
6721 if (i
.mem_operands
== 0)
6723 /* There is no memory operand. */
6724 gas_assert ((op
+ 2) == i
.operands
);
6729 /* There are only 2 operands. */
6730 gas_assert (op
< 2 && i
.operands
== 2);
6735 gas_assert (op
< i
.operands
);
6737 if (vex_reg
!= (unsigned int) ~0)
6739 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6741 if (type
->bitfield
.reg32
!= 1
6742 && type
->bitfield
.reg64
!= 1
6743 && !operand_type_equal (type
, ®xmm
)
6744 && !operand_type_equal (type
, ®ymm
)
6745 && !operand_type_equal (type
, ®zmm
)
6746 && !operand_type_equal (type
, ®mask
))
6749 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6752 /* Don't set OP operand twice. */
6755 /* If there is an extension opcode to put here, the
6756 register number must be put into the regmem field. */
6757 if (i
.tm
.extension_opcode
!= None
)
6759 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6760 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6762 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6767 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6768 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6770 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6775 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6776 must set it to 3 to indicate this is a register operand
6777 in the regmem field. */
6778 if (!i
.mem_operands
)
6782 /* Fill in i.rm.reg field with extension opcode (if any). */
6783 if (i
.tm
.extension_opcode
!= None
)
6784 i
.rm
.reg
= i
.tm
.extension_opcode
;
6790 output_branch (void)
6796 relax_substateT subtype
;
6800 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6801 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6804 if (i
.prefix
[DATA_PREFIX
] != 0)
6810 /* Pentium4 branch hints. */
6811 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6812 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6817 if (i
.prefix
[REX_PREFIX
] != 0)
6823 /* BND prefixed jump. */
6824 if (i
.prefix
[BND_PREFIX
] != 0)
6826 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6830 if (i
.prefixes
!= 0 && !intel_syntax
)
6831 as_warn (_("skipping prefixes on this instruction"));
6833 /* It's always a symbol; End frag & setup for relax.
6834 Make sure there is enough room in this frag for the largest
6835 instruction we may generate in md_convert_frag. This is 2
6836 bytes for the opcode and room for the prefix and largest
6838 frag_grow (prefix
+ 2 + 4);
6839 /* Prefix and 1 opcode byte go in fr_fix. */
6840 p
= frag_more (prefix
+ 1);
6841 if (i
.prefix
[DATA_PREFIX
] != 0)
6842 *p
++ = DATA_PREFIX_OPCODE
;
6843 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6844 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6845 *p
++ = i
.prefix
[SEG_PREFIX
];
6846 if (i
.prefix
[REX_PREFIX
] != 0)
6847 *p
++ = i
.prefix
[REX_PREFIX
];
6848 *p
= i
.tm
.base_opcode
;
6850 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6851 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6852 else if (cpu_arch_flags
.bitfield
.cpui386
)
6853 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6855 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6858 sym
= i
.op
[0].disps
->X_add_symbol
;
6859 off
= i
.op
[0].disps
->X_add_number
;
6861 if (i
.op
[0].disps
->X_op
!= O_constant
6862 && i
.op
[0].disps
->X_op
!= O_symbol
)
6864 /* Handle complex expressions. */
6865 sym
= make_expr_symbol (i
.op
[0].disps
);
6869 /* 1 possible extra opcode + 4 byte displacement go in var part.
6870 Pass reloc in fr_var. */
6871 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6881 if (i
.tm
.opcode_modifier
.jumpbyte
)
6883 /* This is a loop or jecxz type instruction. */
6885 if (i
.prefix
[ADDR_PREFIX
] != 0)
6887 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6890 /* Pentium4 branch hints. */
6891 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6892 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6894 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6903 if (flag_code
== CODE_16BIT
)
6906 if (i
.prefix
[DATA_PREFIX
] != 0)
6908 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6918 if (i
.prefix
[REX_PREFIX
] != 0)
6920 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6924 /* BND prefixed jump. */
6925 if (i
.prefix
[BND_PREFIX
] != 0)
6927 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6931 if (i
.prefixes
!= 0 && !intel_syntax
)
6932 as_warn (_("skipping prefixes on this instruction"));
6934 p
= frag_more (i
.tm
.opcode_length
+ size
);
6935 switch (i
.tm
.opcode_length
)
6938 *p
++ = i
.tm
.base_opcode
>> 8;
6940 *p
++ = i
.tm
.base_opcode
;
6946 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6947 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6949 /* All jumps handled here are signed, but don't use a signed limit
6950 check for 32 and 16 bit jumps as we want to allow wrap around at
6951 4G and 64k respectively. */
6953 fixP
->fx_signed
= 1;
6957 output_interseg_jump (void)
6965 if (flag_code
== CODE_16BIT
)
6969 if (i
.prefix
[DATA_PREFIX
] != 0)
6975 if (i
.prefix
[REX_PREFIX
] != 0)
6985 if (i
.prefixes
!= 0 && !intel_syntax
)
6986 as_warn (_("skipping prefixes on this instruction"));
6988 /* 1 opcode; 2 segment; offset */
6989 p
= frag_more (prefix
+ 1 + 2 + size
);
6991 if (i
.prefix
[DATA_PREFIX
] != 0)
6992 *p
++ = DATA_PREFIX_OPCODE
;
6994 if (i
.prefix
[REX_PREFIX
] != 0)
6995 *p
++ = i
.prefix
[REX_PREFIX
];
6997 *p
++ = i
.tm
.base_opcode
;
6998 if (i
.op
[1].imms
->X_op
== O_constant
)
7000 offsetT n
= i
.op
[1].imms
->X_add_number
;
7003 && !fits_in_unsigned_word (n
)
7004 && !fits_in_signed_word (n
))
7006 as_bad (_("16-bit jump out of range"));
7009 md_number_to_chars (p
, n
, size
);
7012 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7013 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7014 if (i
.op
[0].imms
->X_op
!= O_constant
)
7015 as_bad (_("can't handle non absolute segment in `%s'"),
7017 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7023 fragS
*insn_start_frag
;
7024 offsetT insn_start_off
;
7026 /* Tie dwarf2 debug info to the address at the start of the insn.
7027 We can't do this after the insn has been output as the current
7028 frag may have been closed off. eg. by frag_var. */
7029 dwarf2_emit_insn (0);
7031 insn_start_frag
= frag_now
;
7032 insn_start_off
= frag_now_fix ();
7035 if (i
.tm
.opcode_modifier
.jump
)
7037 else if (i
.tm
.opcode_modifier
.jumpbyte
7038 || i
.tm
.opcode_modifier
.jumpdword
)
7040 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7041 output_interseg_jump ();
7044 /* Output normal instructions here. */
7048 unsigned int prefix
;
7051 && i
.tm
.base_opcode
== 0xfae
7053 && i
.imm_operands
== 1
7054 && (i
.op
[0].imms
->X_add_number
== 0xe8
7055 || i
.op
[0].imms
->X_add_number
== 0xf0
7056 || i
.op
[0].imms
->X_add_number
== 0xf8))
7058 /* Encode lfence, mfence, and sfence as
7059 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7060 offsetT val
= 0x240483f0ULL
;
7062 md_number_to_chars (p
, val
, 5);
7066 /* Some processors fail on LOCK prefix. This options makes
7067 assembler ignore LOCK prefix and serves as a workaround. */
7068 if (omit_lock_prefix
)
7070 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7072 i
.prefix
[LOCK_PREFIX
] = 0;
7075 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7076 don't need the explicit prefix. */
7077 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7079 switch (i
.tm
.opcode_length
)
7082 if (i
.tm
.base_opcode
& 0xff000000)
7084 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7089 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7091 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7092 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7095 if (prefix
!= REPE_PREFIX_OPCODE
7096 || (i
.prefix
[REP_PREFIX
]
7097 != REPE_PREFIX_OPCODE
))
7098 add_prefix (prefix
);
7101 add_prefix (prefix
);
7110 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7111 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7112 R_X86_64_GOTTPOFF relocation so that linker can safely
7113 perform IE->LE optimization. */
7114 if (x86_elf_abi
== X86_64_X32_ABI
7116 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7117 && i
.prefix
[REX_PREFIX
] == 0)
7118 add_prefix (REX_OPCODE
);
7121 /* The prefix bytes. */
7122 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7124 FRAG_APPEND_1_CHAR (*q
);
7128 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7133 /* REX byte is encoded in VEX prefix. */
7137 FRAG_APPEND_1_CHAR (*q
);
7140 /* There should be no other prefixes for instructions
7145 /* For EVEX instructions i.vrex should become 0 after
7146 build_evex_prefix. For VEX instructions upper 16 registers
7147 aren't available, so VREX should be 0. */
7150 /* Now the VEX prefix. */
7151 p
= frag_more (i
.vex
.length
);
7152 for (j
= 0; j
< i
.vex
.length
; j
++)
7153 p
[j
] = i
.vex
.bytes
[j
];
7156 /* Now the opcode; be careful about word order here! */
7157 if (i
.tm
.opcode_length
== 1)
7159 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7163 switch (i
.tm
.opcode_length
)
7167 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7168 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7172 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7182 /* Put out high byte first: can't use md_number_to_chars! */
7183 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7184 *p
= i
.tm
.base_opcode
& 0xff;
7187 /* Now the modrm byte and sib byte (if present). */
7188 if (i
.tm
.opcode_modifier
.modrm
)
7190 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7193 /* If i.rm.regmem == ESP (4)
7194 && i.rm.mode != (Register mode)
7196 ==> need second modrm byte. */
7197 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7199 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7200 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7202 | i
.sib
.scale
<< 6));
7205 if (i
.disp_operands
)
7206 output_disp (insn_start_frag
, insn_start_off
);
7209 output_imm (insn_start_frag
, insn_start_off
);
7215 pi ("" /*line*/, &i
);
7217 #endif /* DEBUG386 */
7220 /* Return the size of the displacement operand N. */
7223 disp_size (unsigned int n
)
7227 /* Vec_Disp8 has to be 8bit. */
7228 if (i
.types
[n
].bitfield
.vec_disp8
)
7230 else if (i
.types
[n
].bitfield
.disp64
)
7232 else if (i
.types
[n
].bitfield
.disp8
)
7234 else if (i
.types
[n
].bitfield
.disp16
)
7239 /* Return the size of the immediate operand N. */
7242 imm_size (unsigned int n
)
7245 if (i
.types
[n
].bitfield
.imm64
)
7247 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7249 else if (i
.types
[n
].bitfield
.imm16
)
7255 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7260 for (n
= 0; n
< i
.operands
; n
++)
7262 if (i
.types
[n
].bitfield
.vec_disp8
7263 || operand_type_check (i
.types
[n
], disp
))
7265 if (i
.op
[n
].disps
->X_op
== O_constant
)
7267 int size
= disp_size (n
);
7268 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7270 if (i
.types
[n
].bitfield
.vec_disp8
)
7272 val
= offset_in_range (val
, size
);
7273 p
= frag_more (size
);
7274 md_number_to_chars (p
, val
, size
);
7278 enum bfd_reloc_code_real reloc_type
;
7279 int size
= disp_size (n
);
7280 int sign
= i
.types
[n
].bitfield
.disp32s
;
7281 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7284 /* We can't have 8 bit displacement here. */
7285 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7287 /* The PC relative address is computed relative
7288 to the instruction boundary, so in case immediate
7289 fields follows, we need to adjust the value. */
7290 if (pcrel
&& i
.imm_operands
)
7295 for (n1
= 0; n1
< i
.operands
; n1
++)
7296 if (operand_type_check (i
.types
[n1
], imm
))
7298 /* Only one immediate is allowed for PC
7299 relative address. */
7300 gas_assert (sz
== 0);
7302 i
.op
[n
].disps
->X_add_number
-= sz
;
7304 /* We should find the immediate. */
7305 gas_assert (sz
!= 0);
7308 p
= frag_more (size
);
7309 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7311 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7312 && (((reloc_type
== BFD_RELOC_32
7313 || reloc_type
== BFD_RELOC_X86_64_32S
7314 || (reloc_type
== BFD_RELOC_64
7316 && (i
.op
[n
].disps
->X_op
== O_symbol
7317 || (i
.op
[n
].disps
->X_op
== O_add
7318 && ((symbol_get_value_expression
7319 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7321 || reloc_type
== BFD_RELOC_32_PCREL
))
7325 if (insn_start_frag
== frag_now
)
7326 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7331 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7332 for (fr
= insn_start_frag
->fr_next
;
7333 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7335 add
+= p
- frag_now
->fr_literal
;
7340 reloc_type
= BFD_RELOC_386_GOTPC
;
7341 i
.op
[n
].imms
->X_add_number
+= add
;
7343 else if (reloc_type
== BFD_RELOC_64
)
7344 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7346 /* Don't do the adjustment for x86-64, as there
7347 the pcrel addressing is relative to the _next_
7348 insn, and that is taken care of in other code. */
7349 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7351 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7352 size
, i
.op
[n
].disps
, pcrel
,
7354 /* Check for "call/jmp *mem", "mov mem, %reg",
7355 "test %reg, mem" and "binop mem, %reg" where binop
7356 is one of adc, add, and, cmp, or, sbb, sub, xor
7357 instructions. Always generate R_386_GOT32X for
7358 "sym*GOT" operand in 32-bit mode. */
7359 if ((generate_relax_relocations
7362 && i
.rm
.regmem
== 5))
7364 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7365 && ((i
.operands
== 1
7366 && i
.tm
.base_opcode
== 0xff
7367 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7369 && (i
.tm
.base_opcode
== 0x8b
7370 || i
.tm
.base_opcode
== 0x85
7371 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7375 fixP
->fx_tcbit
= i
.rex
!= 0;
7377 && (i
.base_reg
->reg_num
== RegRip
7378 || i
.base_reg
->reg_num
== RegEip
))
7379 fixP
->fx_tcbit2
= 1;
7382 fixP
->fx_tcbit2
= 1;
7390 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7395 for (n
= 0; n
< i
.operands
; n
++)
7397 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7398 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7401 if (operand_type_check (i
.types
[n
], imm
))
7403 if (i
.op
[n
].imms
->X_op
== O_constant
)
7405 int size
= imm_size (n
);
7408 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7410 p
= frag_more (size
);
7411 md_number_to_chars (p
, val
, size
);
7415 /* Not absolute_section.
7416 Need a 32-bit fixup (don't support 8bit
7417 non-absolute imms). Try to support other
7419 enum bfd_reloc_code_real reloc_type
;
7420 int size
= imm_size (n
);
7423 if (i
.types
[n
].bitfield
.imm32s
7424 && (i
.suffix
== QWORD_MNEM_SUFFIX
7425 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7430 p
= frag_more (size
);
7431 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7433 /* This is tough to explain. We end up with this one if we
7434 * have operands that look like
7435 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7436 * obtain the absolute address of the GOT, and it is strongly
7437 * preferable from a performance point of view to avoid using
7438 * a runtime relocation for this. The actual sequence of
7439 * instructions often look something like:
7444 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7446 * The call and pop essentially return the absolute address
7447 * of the label .L66 and store it in %ebx. The linker itself
7448 * will ultimately change the first operand of the addl so
7449 * that %ebx points to the GOT, but to keep things simple, the
7450 * .o file must have this operand set so that it generates not
7451 * the absolute address of .L66, but the absolute address of
7452 * itself. This allows the linker itself simply treat a GOTPC
7453 * relocation as asking for a pcrel offset to the GOT to be
7454 * added in, and the addend of the relocation is stored in the
7455 * operand field for the instruction itself.
7457 * Our job here is to fix the operand so that it would add
7458 * the correct offset so that %ebx would point to itself. The
7459 * thing that is tricky is that .-.L66 will point to the
7460 * beginning of the instruction, so we need to further modify
7461 * the operand so that it will point to itself. There are
7462 * other cases where you have something like:
7464 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7466 * and here no correction would be required. Internally in
7467 * the assembler we treat operands of this form as not being
7468 * pcrel since the '.' is explicitly mentioned, and I wonder
7469 * whether it would simplify matters to do it this way. Who
7470 * knows. In earlier versions of the PIC patches, the
7471 * pcrel_adjust field was used to store the correction, but
7472 * since the expression is not pcrel, I felt it would be
7473 * confusing to do it this way. */
7475 if ((reloc_type
== BFD_RELOC_32
7476 || reloc_type
== BFD_RELOC_X86_64_32S
7477 || reloc_type
== BFD_RELOC_64
)
7479 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7480 && (i
.op
[n
].imms
->X_op
== O_symbol
7481 || (i
.op
[n
].imms
->X_op
== O_add
7482 && ((symbol_get_value_expression
7483 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7488 if (insn_start_frag
== frag_now
)
7489 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7494 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7495 for (fr
= insn_start_frag
->fr_next
;
7496 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7498 add
+= p
- frag_now
->fr_literal
;
7502 reloc_type
= BFD_RELOC_386_GOTPC
;
7504 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7506 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7507 i
.op
[n
].imms
->X_add_number
+= add
;
7509 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7510 i
.op
[n
].imms
, 0, reloc_type
);
7516 /* x86_cons_fix_new is called via the expression parsing code when a
7517 reloc is needed. We use this hook to get the correct .got reloc. */
7518 static int cons_sign
= -1;
7521 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7522 expressionS
*exp
, bfd_reloc_code_real_type r
)
7524 r
= reloc (len
, 0, cons_sign
, r
);
7527 if (exp
->X_op
== O_secrel
)
7529 exp
->X_op
= O_symbol
;
7530 r
= BFD_RELOC_32_SECREL
;
7534 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7537 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7538 purpose of the `.dc.a' internal pseudo-op. */
7541 x86_address_bytes (void)
7543 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7545 return stdoutput
->arch_info
->bits_per_address
/ 8;
7548 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7550 # define lex_got(reloc, adjust, types) NULL
7552 /* Parse operands of the form
7553 <symbol>@GOTOFF+<nnn>
7554 and similar .plt or .got references.
7556 If we find one, set up the correct relocation in RELOC and copy the
7557 input string, minus the `@GOTOFF' into a malloc'd buffer for
7558 parsing by the calling routine. Return this buffer, and if ADJUST
7559 is non-null set it to the length of the string we removed from the
7560 input line. Otherwise return NULL. */
7562 lex_got (enum bfd_reloc_code_real
*rel
,
7564 i386_operand_type
*types
)
7566 /* Some of the relocations depend on the size of what field is to
7567 be relocated. But in our callers i386_immediate and i386_displacement
7568 we don't yet know the operand size (this will be set by insn
7569 matching). Hence we record the word32 relocation here,
7570 and adjust the reloc according to the real size in reloc(). */
7571 static const struct {
7574 const enum bfd_reloc_code_real rel
[2];
7575 const i386_operand_type types64
;
7577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7578 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7580 OPERAND_TYPE_IMM32_64
},
7582 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7583 BFD_RELOC_X86_64_PLTOFF64
},
7584 OPERAND_TYPE_IMM64
},
7585 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7586 BFD_RELOC_X86_64_PLT32
},
7587 OPERAND_TYPE_IMM32_32S_DISP32
},
7588 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7589 BFD_RELOC_X86_64_GOTPLT64
},
7590 OPERAND_TYPE_IMM64_DISP64
},
7591 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7592 BFD_RELOC_X86_64_GOTOFF64
},
7593 OPERAND_TYPE_IMM64_DISP64
},
7594 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7595 BFD_RELOC_X86_64_GOTPCREL
},
7596 OPERAND_TYPE_IMM32_32S_DISP32
},
7597 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7598 BFD_RELOC_X86_64_TLSGD
},
7599 OPERAND_TYPE_IMM32_32S_DISP32
},
7600 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7601 _dummy_first_bfd_reloc_code_real
},
7602 OPERAND_TYPE_NONE
},
7603 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7604 BFD_RELOC_X86_64_TLSLD
},
7605 OPERAND_TYPE_IMM32_32S_DISP32
},
7606 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7607 BFD_RELOC_X86_64_GOTTPOFF
},
7608 OPERAND_TYPE_IMM32_32S_DISP32
},
7609 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7610 BFD_RELOC_X86_64_TPOFF32
},
7611 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7612 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7613 _dummy_first_bfd_reloc_code_real
},
7614 OPERAND_TYPE_NONE
},
7615 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7616 BFD_RELOC_X86_64_DTPOFF32
},
7617 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7618 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7619 _dummy_first_bfd_reloc_code_real
},
7620 OPERAND_TYPE_NONE
},
7621 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7622 _dummy_first_bfd_reloc_code_real
},
7623 OPERAND_TYPE_NONE
},
7624 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7625 BFD_RELOC_X86_64_GOT32
},
7626 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7627 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7628 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7629 OPERAND_TYPE_IMM32_32S_DISP32
},
7630 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7631 BFD_RELOC_X86_64_TLSDESC_CALL
},
7632 OPERAND_TYPE_IMM32_32S_DISP32
},
7637 #if defined (OBJ_MAYBE_ELF)
7642 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7643 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7646 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7648 int len
= gotrel
[j
].len
;
7649 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7651 if (gotrel
[j
].rel
[object_64bit
] != 0)
7654 char *tmpbuf
, *past_reloc
;
7656 *rel
= gotrel
[j
].rel
[object_64bit
];
7660 if (flag_code
!= CODE_64BIT
)
7662 types
->bitfield
.imm32
= 1;
7663 types
->bitfield
.disp32
= 1;
7666 *types
= gotrel
[j
].types64
;
7669 if (j
!= 0 && GOT_symbol
== NULL
)
7670 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7672 /* The length of the first part of our input line. */
7673 first
= cp
- input_line_pointer
;
7675 /* The second part goes from after the reloc token until
7676 (and including) an end_of_line char or comma. */
7677 past_reloc
= cp
+ 1 + len
;
7679 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7681 second
= cp
+ 1 - past_reloc
;
7683 /* Allocate and copy string. The trailing NUL shouldn't
7684 be necessary, but be safe. */
7685 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7686 memcpy (tmpbuf
, input_line_pointer
, first
);
7687 if (second
!= 0 && *past_reloc
!= ' ')
7688 /* Replace the relocation token with ' ', so that
7689 errors like foo@GOTOFF1 will be detected. */
7690 tmpbuf
[first
++] = ' ';
7692 /* Increment length by 1 if the relocation token is
7697 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7698 tmpbuf
[first
+ second
] = '\0';
7702 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7703 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7708 /* Might be a symbol version string. Don't as_bad here. */
7717 /* Parse operands of the form
7718 <symbol>@SECREL32+<nnn>
7720 If we find one, set up the correct relocation in RELOC and copy the
7721 input string, minus the `@SECREL32' into a malloc'd buffer for
7722 parsing by the calling routine. Return this buffer, and if ADJUST
7723 is non-null set it to the length of the string we removed from the
7724 input line. Otherwise return NULL.
7726 This function is copied from the ELF version above adjusted for PE targets. */
7729 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7730 int *adjust ATTRIBUTE_UNUSED
,
7731 i386_operand_type
*types
)
7737 const enum bfd_reloc_code_real rel
[2];
7738 const i386_operand_type types64
;
7742 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7743 BFD_RELOC_32_SECREL
},
7744 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7750 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7751 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7754 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7756 int len
= gotrel
[j
].len
;
7758 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7760 if (gotrel
[j
].rel
[object_64bit
] != 0)
7763 char *tmpbuf
, *past_reloc
;
7765 *rel
= gotrel
[j
].rel
[object_64bit
];
7771 if (flag_code
!= CODE_64BIT
)
7773 types
->bitfield
.imm32
= 1;
7774 types
->bitfield
.disp32
= 1;
7777 *types
= gotrel
[j
].types64
;
7780 /* The length of the first part of our input line. */
7781 first
= cp
- input_line_pointer
;
7783 /* The second part goes from after the reloc token until
7784 (and including) an end_of_line char or comma. */
7785 past_reloc
= cp
+ 1 + len
;
7787 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7789 second
= cp
+ 1 - past_reloc
;
7791 /* Allocate and copy string. The trailing NUL shouldn't
7792 be necessary, but be safe. */
7793 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7794 memcpy (tmpbuf
, input_line_pointer
, first
);
7795 if (second
!= 0 && *past_reloc
!= ' ')
7796 /* Replace the relocation token with ' ', so that
7797 errors like foo@SECLREL321 will be detected. */
7798 tmpbuf
[first
++] = ' ';
7799 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7800 tmpbuf
[first
+ second
] = '\0';
7804 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7805 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7810 /* Might be a symbol version string. Don't as_bad here. */
7816 bfd_reloc_code_real_type
7817 x86_cons (expressionS
*exp
, int size
)
7819 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7821 intel_syntax
= -intel_syntax
;
7824 if (size
== 4 || (object_64bit
&& size
== 8))
7826 /* Handle @GOTOFF and the like in an expression. */
7828 char *gotfree_input_line
;
7831 save
= input_line_pointer
;
7832 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7833 if (gotfree_input_line
)
7834 input_line_pointer
= gotfree_input_line
;
7838 if (gotfree_input_line
)
7840 /* expression () has merrily parsed up to the end of line,
7841 or a comma - in the wrong buffer. Transfer how far
7842 input_line_pointer has moved to the right buffer. */
7843 input_line_pointer
= (save
7844 + (input_line_pointer
- gotfree_input_line
)
7846 free (gotfree_input_line
);
7847 if (exp
->X_op
== O_constant
7848 || exp
->X_op
== O_absent
7849 || exp
->X_op
== O_illegal
7850 || exp
->X_op
== O_register
7851 || exp
->X_op
== O_big
)
7853 char c
= *input_line_pointer
;
7854 *input_line_pointer
= 0;
7855 as_bad (_("missing or invalid expression `%s'"), save
);
7856 *input_line_pointer
= c
;
7863 intel_syntax
= -intel_syntax
;
7866 i386_intel_simplify (exp
);
7872 signed_cons (int size
)
7874 if (flag_code
== CODE_64BIT
)
7882 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7889 if (exp
.X_op
== O_symbol
)
7890 exp
.X_op
= O_secrel
;
7892 emit_expr (&exp
, 4);
7894 while (*input_line_pointer
++ == ',');
7896 input_line_pointer
--;
7897 demand_empty_rest_of_line ();
7901 /* Handle Vector operations. */
7904 check_VecOperations (char *op_string
, char *op_end
)
7906 const reg_entry
*mask
;
7911 && (op_end
== NULL
|| op_string
< op_end
))
7914 if (*op_string
== '{')
7918 /* Check broadcasts. */
7919 if (strncmp (op_string
, "1to", 3) == 0)
7924 goto duplicated_vec_op
;
7927 if (*op_string
== '8')
7928 bcst_type
= BROADCAST_1TO8
;
7929 else if (*op_string
== '4')
7930 bcst_type
= BROADCAST_1TO4
;
7931 else if (*op_string
== '2')
7932 bcst_type
= BROADCAST_1TO2
;
7933 else if (*op_string
== '1'
7934 && *(op_string
+1) == '6')
7936 bcst_type
= BROADCAST_1TO16
;
7941 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7946 broadcast_op
.type
= bcst_type
;
7947 broadcast_op
.operand
= this_operand
;
7948 i
.broadcast
= &broadcast_op
;
7950 /* Check masking operation. */
7951 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7953 /* k0 can't be used for write mask. */
7954 if (mask
->reg_num
== 0)
7956 as_bad (_("`%s' can't be used for write mask"),
7963 mask_op
.mask
= mask
;
7964 mask_op
.zeroing
= 0;
7965 mask_op
.operand
= this_operand
;
7971 goto duplicated_vec_op
;
7973 i
.mask
->mask
= mask
;
7975 /* Only "{z}" is allowed here. No need to check
7976 zeroing mask explicitly. */
7977 if (i
.mask
->operand
!= this_operand
)
7979 as_bad (_("invalid write mask `%s'"), saved
);
7986 /* Check zeroing-flag for masking operation. */
7987 else if (*op_string
== 'z')
7991 mask_op
.mask
= NULL
;
7992 mask_op
.zeroing
= 1;
7993 mask_op
.operand
= this_operand
;
7998 if (i
.mask
->zeroing
)
8001 as_bad (_("duplicated `%s'"), saved
);
8005 i
.mask
->zeroing
= 1;
8007 /* Only "{%k}" is allowed here. No need to check mask
8008 register explicitly. */
8009 if (i
.mask
->operand
!= this_operand
)
8011 as_bad (_("invalid zeroing-masking `%s'"),
8020 goto unknown_vec_op
;
8022 if (*op_string
!= '}')
8024 as_bad (_("missing `}' in `%s'"), saved
);
8031 /* We don't know this one. */
8032 as_bad (_("unknown vector operation: `%s'"), saved
);
8040 i386_immediate (char *imm_start
)
8042 char *save_input_line_pointer
;
8043 char *gotfree_input_line
;
8046 i386_operand_type types
;
8048 operand_type_set (&types
, ~0);
8050 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8052 as_bad (_("at most %d immediate operands are allowed"),
8053 MAX_IMMEDIATE_OPERANDS
);
8057 exp
= &im_expressions
[i
.imm_operands
++];
8058 i
.op
[this_operand
].imms
= exp
;
8060 if (is_space_char (*imm_start
))
8063 save_input_line_pointer
= input_line_pointer
;
8064 input_line_pointer
= imm_start
;
8066 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8067 if (gotfree_input_line
)
8068 input_line_pointer
= gotfree_input_line
;
8070 exp_seg
= expression (exp
);
8074 /* Handle vector operations. */
8075 if (*input_line_pointer
== '{')
8077 input_line_pointer
= check_VecOperations (input_line_pointer
,
8079 if (input_line_pointer
== NULL
)
8083 if (*input_line_pointer
)
8084 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8086 input_line_pointer
= save_input_line_pointer
;
8087 if (gotfree_input_line
)
8089 free (gotfree_input_line
);
8091 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8092 exp
->X_op
= O_illegal
;
8095 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8099 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8100 i386_operand_type types
, const char *imm_start
)
8102 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8105 as_bad (_("missing or invalid immediate expression `%s'"),
8109 else if (exp
->X_op
== O_constant
)
8111 /* Size it properly later. */
8112 i
.types
[this_operand
].bitfield
.imm64
= 1;
8113 /* If not 64bit, sign extend val. */
8114 if (flag_code
!= CODE_64BIT
8115 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8117 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8119 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8120 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8121 && exp_seg
!= absolute_section
8122 && exp_seg
!= text_section
8123 && exp_seg
!= data_section
8124 && exp_seg
!= bss_section
8125 && exp_seg
!= undefined_section
8126 && !bfd_is_com_section (exp_seg
))
8128 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8132 else if (!intel_syntax
&& exp_seg
== reg_section
)
8135 as_bad (_("illegal immediate register operand %s"), imm_start
);
8140 /* This is an address. The size of the address will be
8141 determined later, depending on destination register,
8142 suffix, or the default for the section. */
8143 i
.types
[this_operand
].bitfield
.imm8
= 1;
8144 i
.types
[this_operand
].bitfield
.imm16
= 1;
8145 i
.types
[this_operand
].bitfield
.imm32
= 1;
8146 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8147 i
.types
[this_operand
].bitfield
.imm64
= 1;
8148 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8156 i386_scale (char *scale
)
8159 char *save
= input_line_pointer
;
8161 input_line_pointer
= scale
;
8162 val
= get_absolute_expression ();
8167 i
.log2_scale_factor
= 0;
8170 i
.log2_scale_factor
= 1;
8173 i
.log2_scale_factor
= 2;
8176 i
.log2_scale_factor
= 3;
8180 char sep
= *input_line_pointer
;
8182 *input_line_pointer
= '\0';
8183 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8185 *input_line_pointer
= sep
;
8186 input_line_pointer
= save
;
8190 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8192 as_warn (_("scale factor of %d without an index register"),
8193 1 << i
.log2_scale_factor
);
8194 i
.log2_scale_factor
= 0;
8196 scale
= input_line_pointer
;
8197 input_line_pointer
= save
;
8202 i386_displacement (char *disp_start
, char *disp_end
)
8206 char *save_input_line_pointer
;
8207 char *gotfree_input_line
;
8209 i386_operand_type bigdisp
, types
= anydisp
;
8212 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8214 as_bad (_("at most %d displacement operands are allowed"),
8215 MAX_MEMORY_OPERANDS
);
8219 operand_type_set (&bigdisp
, 0);
8220 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8221 || (!current_templates
->start
->opcode_modifier
.jump
8222 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8224 bigdisp
.bitfield
.disp32
= 1;
8225 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8226 if (flag_code
== CODE_64BIT
)
8230 bigdisp
.bitfield
.disp32s
= 1;
8231 bigdisp
.bitfield
.disp64
= 1;
8234 else if ((flag_code
== CODE_16BIT
) ^ override
)
8236 bigdisp
.bitfield
.disp32
= 0;
8237 bigdisp
.bitfield
.disp16
= 1;
8242 /* For PC-relative branches, the width of the displacement
8243 is dependent upon data size, not address size. */
8244 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8245 if (flag_code
== CODE_64BIT
)
8247 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8248 bigdisp
.bitfield
.disp16
= 1;
8251 bigdisp
.bitfield
.disp32
= 1;
8252 bigdisp
.bitfield
.disp32s
= 1;
8258 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8260 : LONG_MNEM_SUFFIX
));
8261 bigdisp
.bitfield
.disp32
= 1;
8262 if ((flag_code
== CODE_16BIT
) ^ override
)
8264 bigdisp
.bitfield
.disp32
= 0;
8265 bigdisp
.bitfield
.disp16
= 1;
8269 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8272 exp
= &disp_expressions
[i
.disp_operands
];
8273 i
.op
[this_operand
].disps
= exp
;
8275 save_input_line_pointer
= input_line_pointer
;
8276 input_line_pointer
= disp_start
;
8277 END_STRING_AND_SAVE (disp_end
);
8279 #ifndef GCC_ASM_O_HACK
8280 #define GCC_ASM_O_HACK 0
8283 END_STRING_AND_SAVE (disp_end
+ 1);
8284 if (i
.types
[this_operand
].bitfield
.baseIndex
8285 && displacement_string_end
[-1] == '+')
8287 /* This hack is to avoid a warning when using the "o"
8288 constraint within gcc asm statements.
8291 #define _set_tssldt_desc(n,addr,limit,type) \
8292 __asm__ __volatile__ ( \
8294 "movw %w1,2+%0\n\t" \
8296 "movb %b1,4+%0\n\t" \
8297 "movb %4,5+%0\n\t" \
8298 "movb $0,6+%0\n\t" \
8299 "movb %h1,7+%0\n\t" \
8301 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8303 This works great except that the output assembler ends
8304 up looking a bit weird if it turns out that there is
8305 no offset. You end up producing code that looks like:
8318 So here we provide the missing zero. */
8320 *displacement_string_end
= '0';
8323 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8324 if (gotfree_input_line
)
8325 input_line_pointer
= gotfree_input_line
;
8327 exp_seg
= expression (exp
);
8330 if (*input_line_pointer
)
8331 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8333 RESTORE_END_STRING (disp_end
+ 1);
8335 input_line_pointer
= save_input_line_pointer
;
8336 if (gotfree_input_line
)
8338 free (gotfree_input_line
);
8340 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8341 exp
->X_op
= O_illegal
;
8344 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8346 RESTORE_END_STRING (disp_end
);
8352 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8353 i386_operand_type types
, const char *disp_start
)
8355 i386_operand_type bigdisp
;
8358 /* We do this to make sure that the section symbol is in
8359 the symbol table. We will ultimately change the relocation
8360 to be relative to the beginning of the section. */
8361 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8362 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8363 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8365 if (exp
->X_op
!= O_symbol
)
8368 if (S_IS_LOCAL (exp
->X_add_symbol
)
8369 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8370 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8371 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8372 exp
->X_op
= O_subtract
;
8373 exp
->X_op_symbol
= GOT_symbol
;
8374 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8375 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8376 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8377 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8379 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8382 else if (exp
->X_op
== O_absent
8383 || exp
->X_op
== O_illegal
8384 || exp
->X_op
== O_big
)
8387 as_bad (_("missing or invalid displacement expression `%s'"),
8392 else if (flag_code
== CODE_64BIT
8393 && !i
.prefix
[ADDR_PREFIX
]
8394 && exp
->X_op
== O_constant
)
8396 /* Since displacement is signed extended to 64bit, don't allow
8397 disp32 and turn off disp32s if they are out of range. */
8398 i
.types
[this_operand
].bitfield
.disp32
= 0;
8399 if (!fits_in_signed_long (exp
->X_add_number
))
8401 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8402 if (i
.types
[this_operand
].bitfield
.baseindex
)
8404 as_bad (_("0x%lx out range of signed 32bit displacement"),
8405 (long) exp
->X_add_number
);
8411 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8412 else if (exp
->X_op
!= O_constant
8413 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8414 && exp_seg
!= absolute_section
8415 && exp_seg
!= text_section
8416 && exp_seg
!= data_section
8417 && exp_seg
!= bss_section
8418 && exp_seg
!= undefined_section
8419 && !bfd_is_com_section (exp_seg
))
8421 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8426 /* Check if this is a displacement only operand. */
8427 bigdisp
= i
.types
[this_operand
];
8428 bigdisp
.bitfield
.disp8
= 0;
8429 bigdisp
.bitfield
.disp16
= 0;
8430 bigdisp
.bitfield
.disp32
= 0;
8431 bigdisp
.bitfield
.disp32s
= 0;
8432 bigdisp
.bitfield
.disp64
= 0;
8433 if (operand_type_all_zero (&bigdisp
))
8434 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8440 /* Make sure the memory operand we've been dealt is valid.
8441 Return 1 on success, 0 on a failure. */
8444 i386_index_check (const char *operand_string
)
8446 const char *kind
= "base/index";
8447 enum flag_code addr_mode
;
8449 if (i
.prefix
[ADDR_PREFIX
])
8450 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8453 addr_mode
= flag_code
;
8455 #if INFER_ADDR_PREFIX
8456 if (i
.mem_operands
== 0)
8458 /* Infer address prefix from the first memory operand. */
8459 const reg_entry
*addr_reg
= i
.base_reg
;
8461 if (addr_reg
== NULL
)
8462 addr_reg
= i
.index_reg
;
8466 if (addr_reg
->reg_num
== RegEip
8467 || addr_reg
->reg_num
== RegEiz
8468 || addr_reg
->reg_type
.bitfield
.reg32
)
8469 addr_mode
= CODE_32BIT
;
8470 else if (flag_code
!= CODE_64BIT
8471 && addr_reg
->reg_type
.bitfield
.reg16
)
8472 addr_mode
= CODE_16BIT
;
8474 if (addr_mode
!= flag_code
)
8476 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8478 /* Change the size of any displacement too. At most one
8479 of Disp16 or Disp32 is set.
8480 FIXME. There doesn't seem to be any real need for
8481 separate Disp16 and Disp32 flags. The same goes for
8482 Imm16 and Imm32. Removing them would probably clean
8483 up the code quite a lot. */
8484 if (flag_code
!= CODE_64BIT
8485 && (i
.types
[this_operand
].bitfield
.disp16
8486 || i
.types
[this_operand
].bitfield
.disp32
))
8487 i
.types
[this_operand
]
8488 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8495 if (current_templates
->start
->opcode_modifier
.isstring
8496 && !current_templates
->start
->opcode_modifier
.immext
8497 && (current_templates
->end
[-1].opcode_modifier
.isstring
8500 /* Memory operands of string insns are special in that they only allow
8501 a single register (rDI, rSI, or rBX) as their memory address. */
8502 const reg_entry
*expected_reg
;
8503 static const char *di_si
[][2] =
8509 static const char *bx
[] = { "ebx", "bx", "rbx" };
8511 kind
= "string address";
8513 if (current_templates
->start
->opcode_modifier
.w
)
8515 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8517 if (!type
.bitfield
.baseindex
8518 || ((!i
.mem_operands
!= !intel_syntax
)
8519 && current_templates
->end
[-1].operand_types
[1]
8520 .bitfield
.baseindex
))
8521 type
= current_templates
->end
[-1].operand_types
[1];
8522 expected_reg
= hash_find (reg_hash
,
8523 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8527 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8529 if (i
.base_reg
!= expected_reg
8531 || operand_type_check (i
.types
[this_operand
], disp
))
8533 /* The second memory operand must have the same size as
8537 && !((addr_mode
== CODE_64BIT
8538 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8539 || (addr_mode
== CODE_32BIT
8540 ? i
.base_reg
->reg_type
.bitfield
.reg32
8541 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8544 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8546 intel_syntax
? '[' : '(',
8548 expected_reg
->reg_name
,
8549 intel_syntax
? ']' : ')');
8556 as_bad (_("`%s' is not a valid %s expression"),
8557 operand_string
, kind
);
8562 if (addr_mode
!= CODE_16BIT
)
8564 /* 32-bit/64-bit checks. */
8566 && (addr_mode
== CODE_64BIT
8567 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8568 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8570 || (i
.base_reg
->reg_num
8571 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8573 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8574 && !i
.index_reg
->reg_type
.bitfield
.regymm
8575 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8576 && ((addr_mode
== CODE_64BIT
8577 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8578 || i
.index_reg
->reg_num
== RegRiz
)
8579 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8580 || i
.index_reg
->reg_num
== RegEiz
))
8581 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8586 /* 16-bit checks. */
8588 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8589 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8591 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8592 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8594 && i
.base_reg
->reg_num
< 6
8595 && i
.index_reg
->reg_num
>= 6
8596 && i
.log2_scale_factor
== 0))))
8603 /* Handle vector immediates. */
8606 RC_SAE_immediate (const char *imm_start
)
8608 unsigned int match_found
, j
;
8609 const char *pstr
= imm_start
;
8617 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8619 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8623 rc_op
.type
= RC_NamesTable
[j
].type
;
8624 rc_op
.operand
= this_operand
;
8625 i
.rounding
= &rc_op
;
8629 as_bad (_("duplicated `%s'"), imm_start
);
8632 pstr
+= RC_NamesTable
[j
].len
;
8642 as_bad (_("Missing '}': '%s'"), imm_start
);
8645 /* RC/SAE immediate string should contain nothing more. */;
8648 as_bad (_("Junk after '}': '%s'"), imm_start
);
8652 exp
= &im_expressions
[i
.imm_operands
++];
8653 i
.op
[this_operand
].imms
= exp
;
8655 exp
->X_op
= O_constant
;
8656 exp
->X_add_number
= 0;
8657 exp
->X_add_symbol
= (symbolS
*) 0;
8658 exp
->X_op_symbol
= (symbolS
*) 0;
8660 i
.types
[this_operand
].bitfield
.imm8
= 1;
8664 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8668 i386_att_operand (char *operand_string
)
8672 char *op_string
= operand_string
;
8674 if (is_space_char (*op_string
))
8677 /* We check for an absolute prefix (differentiating,
8678 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8679 if (*op_string
== ABSOLUTE_PREFIX
)
8682 if (is_space_char (*op_string
))
8684 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8687 /* Check if operand is a register. */
8688 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8690 i386_operand_type temp
;
8692 /* Check for a segment override by searching for ':' after a
8693 segment register. */
8695 if (is_space_char (*op_string
))
8697 if (*op_string
== ':'
8698 && (r
->reg_type
.bitfield
.sreg2
8699 || r
->reg_type
.bitfield
.sreg3
))
8704 i
.seg
[i
.mem_operands
] = &es
;
8707 i
.seg
[i
.mem_operands
] = &cs
;
8710 i
.seg
[i
.mem_operands
] = &ss
;
8713 i
.seg
[i
.mem_operands
] = &ds
;
8716 i
.seg
[i
.mem_operands
] = &fs
;
8719 i
.seg
[i
.mem_operands
] = &gs
;
8723 /* Skip the ':' and whitespace. */
8725 if (is_space_char (*op_string
))
8728 if (!is_digit_char (*op_string
)
8729 && !is_identifier_char (*op_string
)
8730 && *op_string
!= '('
8731 && *op_string
!= ABSOLUTE_PREFIX
)
8733 as_bad (_("bad memory operand `%s'"), op_string
);
8736 /* Handle case of %es:*foo. */
8737 if (*op_string
== ABSOLUTE_PREFIX
)
8740 if (is_space_char (*op_string
))
8742 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8744 goto do_memory_reference
;
8747 /* Handle vector operations. */
8748 if (*op_string
== '{')
8750 op_string
= check_VecOperations (op_string
, NULL
);
8751 if (op_string
== NULL
)
8757 as_bad (_("junk `%s' after register"), op_string
);
8761 temp
.bitfield
.baseindex
= 0;
8762 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8764 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8765 i
.op
[this_operand
].regs
= r
;
8768 else if (*op_string
== REGISTER_PREFIX
)
8770 as_bad (_("bad register name `%s'"), op_string
);
8773 else if (*op_string
== IMMEDIATE_PREFIX
)
8776 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8778 as_bad (_("immediate operand illegal with absolute jump"));
8781 if (!i386_immediate (op_string
))
8784 else if (RC_SAE_immediate (operand_string
))
8786 /* If it is a RC or SAE immediate, do nothing. */
8789 else if (is_digit_char (*op_string
)
8790 || is_identifier_char (*op_string
)
8791 || *op_string
== '"'
8792 || *op_string
== '(')
8794 /* This is a memory reference of some sort. */
8797 /* Start and end of displacement string expression (if found). */
8798 char *displacement_string_start
;
8799 char *displacement_string_end
;
8802 do_memory_reference
:
8803 if ((i
.mem_operands
== 1
8804 && !current_templates
->start
->opcode_modifier
.isstring
)
8805 || i
.mem_operands
== 2)
8807 as_bad (_("too many memory references for `%s'"),
8808 current_templates
->start
->name
);
8812 /* Check for base index form. We detect the base index form by
8813 looking for an ')' at the end of the operand, searching
8814 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8816 base_string
= op_string
+ strlen (op_string
);
8818 /* Handle vector operations. */
8819 vop_start
= strchr (op_string
, '{');
8820 if (vop_start
&& vop_start
< base_string
)
8822 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8824 base_string
= vop_start
;
8828 if (is_space_char (*base_string
))
8831 /* If we only have a displacement, set-up for it to be parsed later. */
8832 displacement_string_start
= op_string
;
8833 displacement_string_end
= base_string
+ 1;
8835 if (*base_string
== ')')
8838 unsigned int parens_balanced
= 1;
8839 /* We've already checked that the number of left & right ()'s are
8840 equal, so this loop will not be infinite. */
8844 if (*base_string
== ')')
8846 if (*base_string
== '(')
8849 while (parens_balanced
);
8851 temp_string
= base_string
;
8853 /* Skip past '(' and whitespace. */
8855 if (is_space_char (*base_string
))
8858 if (*base_string
== ','
8859 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8862 displacement_string_end
= temp_string
;
8864 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8868 base_string
= end_op
;
8869 if (is_space_char (*base_string
))
8873 /* There may be an index reg or scale factor here. */
8874 if (*base_string
== ',')
8877 if (is_space_char (*base_string
))
8880 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8883 base_string
= end_op
;
8884 if (is_space_char (*base_string
))
8886 if (*base_string
== ',')
8889 if (is_space_char (*base_string
))
8892 else if (*base_string
!= ')')
8894 as_bad (_("expecting `,' or `)' "
8895 "after index register in `%s'"),
8900 else if (*base_string
== REGISTER_PREFIX
)
8902 end_op
= strchr (base_string
, ',');
8905 as_bad (_("bad register name `%s'"), base_string
);
8909 /* Check for scale factor. */
8910 if (*base_string
!= ')')
8912 char *end_scale
= i386_scale (base_string
);
8917 base_string
= end_scale
;
8918 if (is_space_char (*base_string
))
8920 if (*base_string
!= ')')
8922 as_bad (_("expecting `)' "
8923 "after scale factor in `%s'"),
8928 else if (!i
.index_reg
)
8930 as_bad (_("expecting index register or scale factor "
8931 "after `,'; got '%c'"),
8936 else if (*base_string
!= ')')
8938 as_bad (_("expecting `,' or `)' "
8939 "after base register in `%s'"),
8944 else if (*base_string
== REGISTER_PREFIX
)
8946 end_op
= strchr (base_string
, ',');
8949 as_bad (_("bad register name `%s'"), base_string
);
8954 /* If there's an expression beginning the operand, parse it,
8955 assuming displacement_string_start and
8956 displacement_string_end are meaningful. */
8957 if (displacement_string_start
!= displacement_string_end
)
8959 if (!i386_displacement (displacement_string_start
,
8960 displacement_string_end
))
8964 /* Special case for (%dx) while doing input/output op. */
8966 && operand_type_equal (&i
.base_reg
->reg_type
,
8967 ®16_inoutportreg
)
8969 && i
.log2_scale_factor
== 0
8970 && i
.seg
[i
.mem_operands
] == 0
8971 && !operand_type_check (i
.types
[this_operand
], disp
))
8973 i
.types
[this_operand
] = inoutportreg
;
8977 if (i386_index_check (operand_string
) == 0)
8979 i
.types
[this_operand
].bitfield
.mem
= 1;
8984 /* It's not a memory operand; argh! */
8985 as_bad (_("invalid char %s beginning operand %d `%s'"),
8986 output_invalid (*op_string
),
8991 return 1; /* Normal return. */
8994 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8995 that an rs_machine_dependent frag may reach. */
8998 i386_frag_max_var (fragS
*frag
)
9000 /* The only relaxable frags are for jumps.
9001 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9002 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9003 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9008 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9010 /* STT_GNU_IFUNC symbol must go through PLT. */
9011 if ((symbol_get_bfdsym (fr_symbol
)->flags
9012 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9015 if (!S_IS_EXTERNAL (fr_symbol
))
9016 /* Symbol may be weak or local. */
9017 return !S_IS_WEAK (fr_symbol
);
9019 /* Global symbols with non-default visibility can't be preempted. */
9020 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9023 if (fr_var
!= NO_RELOC
)
9024 switch ((enum bfd_reloc_code_real
) fr_var
)
9026 case BFD_RELOC_386_PLT32
:
9027 case BFD_RELOC_X86_64_PLT32
:
9028 /* Symbol with PLT relocatin may be preempted. */
9034 /* Global symbols with default visibility in a shared library may be
9035 preempted by another definition. */
9040 /* md_estimate_size_before_relax()
9042 Called just before relax() for rs_machine_dependent frags. The x86
9043 assembler uses these frags to handle variable size jump
9046 Any symbol that is now undefined will not become defined.
9047 Return the correct fr_subtype in the frag.
9048 Return the initial "guess for variable size of frag" to caller.
9049 The guess is actually the growth beyond the fixed part. Whatever
9050 we do to grow the fixed or variable part contributes to our
9054 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9056 /* We've already got fragP->fr_subtype right; all we have to do is
9057 check for un-relaxable symbols. On an ELF system, we can't relax
9058 an externally visible symbol, because it may be overridden by a
9060 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9061 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9063 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9066 #if defined (OBJ_COFF) && defined (TE_PE)
9067 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9068 && S_IS_WEAK (fragP
->fr_symbol
))
9072 /* Symbol is undefined in this segment, or we need to keep a
9073 reloc so that weak symbols can be overridden. */
9074 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9075 enum bfd_reloc_code_real reloc_type
;
9076 unsigned char *opcode
;
9079 if (fragP
->fr_var
!= NO_RELOC
)
9080 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9082 reloc_type
= BFD_RELOC_16_PCREL
;
9084 reloc_type
= BFD_RELOC_32_PCREL
;
9086 old_fr_fix
= fragP
->fr_fix
;
9087 opcode
= (unsigned char *) fragP
->fr_opcode
;
9089 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9092 /* Make jmp (0xeb) a (d)word displacement jump. */
9094 fragP
->fr_fix
+= size
;
9095 fix_new (fragP
, old_fr_fix
, size
,
9097 fragP
->fr_offset
, 1,
9103 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9105 /* Negate the condition, and branch past an
9106 unconditional jump. */
9109 /* Insert an unconditional jump. */
9111 /* We added two extra opcode bytes, and have a two byte
9113 fragP
->fr_fix
+= 2 + 2;
9114 fix_new (fragP
, old_fr_fix
+ 2, 2,
9116 fragP
->fr_offset
, 1,
9123 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9128 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9130 fragP
->fr_offset
, 1,
9132 fixP
->fx_signed
= 1;
9136 /* This changes the byte-displacement jump 0x7N
9137 to the (d)word-displacement jump 0x0f,0x8N. */
9138 opcode
[1] = opcode
[0] + 0x10;
9139 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9140 /* We've added an opcode byte. */
9141 fragP
->fr_fix
+= 1 + size
;
9142 fix_new (fragP
, old_fr_fix
+ 1, size
,
9144 fragP
->fr_offset
, 1,
9149 BAD_CASE (fragP
->fr_subtype
);
9153 return fragP
->fr_fix
- old_fr_fix
;
9156 /* Guess size depending on current relax state. Initially the relax
9157 state will correspond to a short jump and we return 1, because
9158 the variable part of the frag (the branch offset) is one byte
9159 long. However, we can relax a section more than once and in that
9160 case we must either set fr_subtype back to the unrelaxed state,
9161 or return the value for the appropriate branch. */
9162 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9165 /* Called after relax() is finished.
9167 In: Address of frag.
9168 fr_type == rs_machine_dependent.
9169 fr_subtype is what the address relaxed to.
9171 Out: Any fixSs and constants are set up.
9172 Caller will turn frag into a ".space 0". */
9175 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9178 unsigned char *opcode
;
9179 unsigned char *where_to_put_displacement
= NULL
;
9180 offsetT target_address
;
9181 offsetT opcode_address
;
9182 unsigned int extension
= 0;
9183 offsetT displacement_from_opcode_start
;
9185 opcode
= (unsigned char *) fragP
->fr_opcode
;
9187 /* Address we want to reach in file space. */
9188 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9190 /* Address opcode resides at in file space. */
9191 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9193 /* Displacement from opcode start to fill into instruction. */
9194 displacement_from_opcode_start
= target_address
- opcode_address
;
9196 if ((fragP
->fr_subtype
& BIG
) == 0)
9198 /* Don't have to change opcode. */
9199 extension
= 1; /* 1 opcode + 1 displacement */
9200 where_to_put_displacement
= &opcode
[1];
9204 if (no_cond_jump_promotion
9205 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9206 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9207 _("long jump required"));
9209 switch (fragP
->fr_subtype
)
9211 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9212 extension
= 4; /* 1 opcode + 4 displacement */
9214 where_to_put_displacement
= &opcode
[1];
9217 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9218 extension
= 2; /* 1 opcode + 2 displacement */
9220 where_to_put_displacement
= &opcode
[1];
9223 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9224 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9225 extension
= 5; /* 2 opcode + 4 displacement */
9226 opcode
[1] = opcode
[0] + 0x10;
9227 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9228 where_to_put_displacement
= &opcode
[2];
9231 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9232 extension
= 3; /* 2 opcode + 2 displacement */
9233 opcode
[1] = opcode
[0] + 0x10;
9234 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9235 where_to_put_displacement
= &opcode
[2];
9238 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9243 where_to_put_displacement
= &opcode
[3];
9247 BAD_CASE (fragP
->fr_subtype
);
9252 /* If size if less then four we are sure that the operand fits,
9253 but if it's 4, then it could be that the displacement is larger
9255 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9257 && ((addressT
) (displacement_from_opcode_start
- extension
9258 + ((addressT
) 1 << 31))
9259 > (((addressT
) 2 << 31) - 1)))
9261 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9262 _("jump target out of range"));
9263 /* Make us emit 0. */
9264 displacement_from_opcode_start
= extension
;
9266 /* Now put displacement after opcode. */
9267 md_number_to_chars ((char *) where_to_put_displacement
,
9268 (valueT
) (displacement_from_opcode_start
- extension
),
9269 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9270 fragP
->fr_fix
+= extension
;
9273 /* Apply a fixup (fixP) to segment data, once it has been determined
9274 by our caller that we have all the info we need to fix it up.
9276 Parameter valP is the pointer to the value of the bits.
9278 On the 386, immediates, displacements, and data pointers are all in
9279 the same (little-endian) format, so we don't need to care about which
9283 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9285 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9286 valueT value
= *valP
;
9288 #if !defined (TE_Mach)
9291 switch (fixP
->fx_r_type
)
9297 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9300 case BFD_RELOC_X86_64_32S
:
9301 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9304 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9307 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9312 if (fixP
->fx_addsy
!= NULL
9313 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9314 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9315 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9316 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9317 && !use_rela_relocations
)
9319 /* This is a hack. There should be a better way to handle this.
9320 This covers for the fact that bfd_install_relocation will
9321 subtract the current location (for partial_inplace, PC relative
9322 relocations); see more below. */
9326 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9329 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9334 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9337 || (symbol_section_p (fixP
->fx_addsy
)
9338 && sym_seg
!= absolute_section
))
9339 && !generic_force_reloc (fixP
))
9341 /* Yes, we add the values in twice. This is because
9342 bfd_install_relocation subtracts them out again. I think
9343 bfd_install_relocation is broken, but I don't dare change
9345 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9349 #if defined (OBJ_COFF) && defined (TE_PE)
9350 /* For some reason, the PE format does not store a
9351 section address offset for a PC relative symbol. */
9352 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9353 || S_IS_WEAK (fixP
->fx_addsy
))
9354 value
+= md_pcrel_from (fixP
);
9357 #if defined (OBJ_COFF) && defined (TE_PE)
9358 if (fixP
->fx_addsy
!= NULL
9359 && S_IS_WEAK (fixP
->fx_addsy
)
9360 /* PR 16858: Do not modify weak function references. */
9361 && ! fixP
->fx_pcrel
)
9363 #if !defined (TE_PEP)
9364 /* For x86 PE weak function symbols are neither PC-relative
9365 nor do they set S_IS_FUNCTION. So the only reliable way
9366 to detect them is to check the flags of their containing
9368 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9369 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9373 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9377 /* Fix a few things - the dynamic linker expects certain values here,
9378 and we must not disappoint it. */
9379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9380 if (IS_ELF
&& fixP
->fx_addsy
)
9381 switch (fixP
->fx_r_type
)
9383 case BFD_RELOC_386_PLT32
:
9384 case BFD_RELOC_X86_64_PLT32
:
9385 /* Make the jump instruction point to the address of the operand. At
9386 runtime we merely add the offset to the actual PLT entry. */
9390 case BFD_RELOC_386_TLS_GD
:
9391 case BFD_RELOC_386_TLS_LDM
:
9392 case BFD_RELOC_386_TLS_IE_32
:
9393 case BFD_RELOC_386_TLS_IE
:
9394 case BFD_RELOC_386_TLS_GOTIE
:
9395 case BFD_RELOC_386_TLS_GOTDESC
:
9396 case BFD_RELOC_X86_64_TLSGD
:
9397 case BFD_RELOC_X86_64_TLSLD
:
9398 case BFD_RELOC_X86_64_GOTTPOFF
:
9399 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9400 value
= 0; /* Fully resolved at runtime. No addend. */
9402 case BFD_RELOC_386_TLS_LE
:
9403 case BFD_RELOC_386_TLS_LDO_32
:
9404 case BFD_RELOC_386_TLS_LE_32
:
9405 case BFD_RELOC_X86_64_DTPOFF32
:
9406 case BFD_RELOC_X86_64_DTPOFF64
:
9407 case BFD_RELOC_X86_64_TPOFF32
:
9408 case BFD_RELOC_X86_64_TPOFF64
:
9409 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9412 case BFD_RELOC_386_TLS_DESC_CALL
:
9413 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9414 value
= 0; /* Fully resolved at runtime. No addend. */
9415 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9419 case BFD_RELOC_VTABLE_INHERIT
:
9420 case BFD_RELOC_VTABLE_ENTRY
:
9427 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9429 #endif /* !defined (TE_Mach) */
9431 /* Are we finished with this relocation now? */
9432 if (fixP
->fx_addsy
== NULL
)
9434 #if defined (OBJ_COFF) && defined (TE_PE)
9435 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9438 /* Remember value for tc_gen_reloc. */
9439 fixP
->fx_addnumber
= value
;
9440 /* Clear out the frag for now. */
9444 else if (use_rela_relocations
)
9446 fixP
->fx_no_overflow
= 1;
9447 /* Remember value for tc_gen_reloc. */
9448 fixP
->fx_addnumber
= value
;
9452 md_number_to_chars (p
, value
, fixP
->fx_size
);
9456 md_atof (int type
, char *litP
, int *sizeP
)
9458 /* This outputs the LITTLENUMs in REVERSE order;
9459 in accord with the bigendian 386. */
9460 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9463 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9466 output_invalid (int c
)
9469 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9472 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9473 "(0x%x)", (unsigned char) c
);
9474 return output_invalid_buf
;
9477 /* REG_STRING starts *before* REGISTER_PREFIX. */
9479 static const reg_entry
*
9480 parse_real_register (char *reg_string
, char **end_op
)
9482 char *s
= reg_string
;
9484 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9487 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9488 if (*s
== REGISTER_PREFIX
)
9491 if (is_space_char (*s
))
9495 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9497 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9498 return (const reg_entry
*) NULL
;
9502 /* For naked regs, make sure that we are not dealing with an identifier.
9503 This prevents confusing an identifier like `eax_var' with register
9505 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9506 return (const reg_entry
*) NULL
;
9510 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9512 /* Handle floating point regs, allowing spaces in the (i) part. */
9513 if (r
== i386_regtab
/* %st is first entry of table */)
9515 if (is_space_char (*s
))
9520 if (is_space_char (*s
))
9522 if (*s
>= '0' && *s
<= '7')
9526 if (is_space_char (*s
))
9531 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9536 /* We have "%st(" then garbage. */
9537 return (const reg_entry
*) NULL
;
9541 if (r
== NULL
|| allow_pseudo_reg
)
9544 if (operand_type_all_zero (&r
->reg_type
))
9545 return (const reg_entry
*) NULL
;
9547 if ((r
->reg_type
.bitfield
.reg32
9548 || r
->reg_type
.bitfield
.sreg3
9549 || r
->reg_type
.bitfield
.control
9550 || r
->reg_type
.bitfield
.debug
9551 || r
->reg_type
.bitfield
.test
)
9552 && !cpu_arch_flags
.bitfield
.cpui386
)
9553 return (const reg_entry
*) NULL
;
9555 if (r
->reg_type
.bitfield
.floatreg
9556 && !cpu_arch_flags
.bitfield
.cpu8087
9557 && !cpu_arch_flags
.bitfield
.cpu287
9558 && !cpu_arch_flags
.bitfield
.cpu387
)
9559 return (const reg_entry
*) NULL
;
9561 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9562 return (const reg_entry
*) NULL
;
9564 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9565 return (const reg_entry
*) NULL
;
9567 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9568 return (const reg_entry
*) NULL
;
9570 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9571 return (const reg_entry
*) NULL
;
9573 if (r
->reg_type
.bitfield
.regmask
9574 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9575 return (const reg_entry
*) NULL
;
9577 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9578 if (!allow_index_reg
9579 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9580 return (const reg_entry
*) NULL
;
9582 /* Upper 16 vector register is only available with VREX in 64bit
9584 if ((r
->reg_flags
& RegVRex
))
9586 if (!cpu_arch_flags
.bitfield
.cpuvrex
9587 || flag_code
!= CODE_64BIT
)
9588 return (const reg_entry
*) NULL
;
9593 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9594 || r
->reg_type
.bitfield
.reg64
)
9595 && (!cpu_arch_flags
.bitfield
.cpulm
9596 || !operand_type_equal (&r
->reg_type
, &control
))
9597 && flag_code
!= CODE_64BIT
)
9598 return (const reg_entry
*) NULL
;
9600 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9601 return (const reg_entry
*) NULL
;
9606 /* REG_STRING starts *before* REGISTER_PREFIX. */
9608 static const reg_entry
*
9609 parse_register (char *reg_string
, char **end_op
)
9613 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9614 r
= parse_real_register (reg_string
, end_op
);
9619 char *save
= input_line_pointer
;
9623 input_line_pointer
= reg_string
;
9624 c
= get_symbol_name (®_string
);
9625 symbolP
= symbol_find (reg_string
);
9626 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9628 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9630 know (e
->X_op
== O_register
);
9631 know (e
->X_add_number
>= 0
9632 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9633 r
= i386_regtab
+ e
->X_add_number
;
9634 if ((r
->reg_flags
& RegVRex
))
9636 *end_op
= input_line_pointer
;
9638 *input_line_pointer
= c
;
9639 input_line_pointer
= save
;
9645 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9648 char *end
= input_line_pointer
;
9651 r
= parse_register (name
, &input_line_pointer
);
9652 if (r
&& end
<= input_line_pointer
)
9654 *nextcharP
= *input_line_pointer
;
9655 *input_line_pointer
= 0;
9656 e
->X_op
= O_register
;
9657 e
->X_add_number
= r
- i386_regtab
;
9660 input_line_pointer
= end
;
9662 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9666 md_operand (expressionS
*e
)
9671 switch (*input_line_pointer
)
9673 case REGISTER_PREFIX
:
9674 r
= parse_real_register (input_line_pointer
, &end
);
9677 e
->X_op
= O_register
;
9678 e
->X_add_number
= r
- i386_regtab
;
9679 input_line_pointer
= end
;
9684 gas_assert (intel_syntax
);
9685 end
= input_line_pointer
++;
9687 if (*input_line_pointer
== ']')
9689 ++input_line_pointer
;
9690 e
->X_op_symbol
= make_expr_symbol (e
);
9691 e
->X_add_symbol
= NULL
;
9692 e
->X_add_number
= 0;
9698 input_line_pointer
= end
;
9705 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9706 const char *md_shortopts
= "kVQ:sqn";
9708 const char *md_shortopts
= "qn";
9711 #define OPTION_32 (OPTION_MD_BASE + 0)
9712 #define OPTION_64 (OPTION_MD_BASE + 1)
9713 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9714 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9715 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9716 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9717 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9718 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9719 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9720 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9721 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9722 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9723 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9724 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9725 #define OPTION_X32 (OPTION_MD_BASE + 14)
9726 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9727 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9728 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9729 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9730 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9731 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9732 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9733 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9734 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9735 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9736 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9738 struct option md_longopts
[] =
9740 {"32", no_argument
, NULL
, OPTION_32
},
9741 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9742 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9743 {"64", no_argument
, NULL
, OPTION_64
},
9745 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9746 {"x32", no_argument
, NULL
, OPTION_X32
},
9747 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9749 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9750 {"march", required_argument
, NULL
, OPTION_MARCH
},
9751 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9752 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9753 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9754 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9755 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9756 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9757 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9758 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9759 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9760 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9761 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9762 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9763 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9764 # if defined (TE_PE) || defined (TE_PEP)
9765 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9767 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9768 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9769 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9770 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9771 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9772 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9773 {NULL
, no_argument
, NULL
, 0}
9775 size_t md_longopts_size
= sizeof (md_longopts
);
9778 md_parse_option (int c
, const char *arg
)
9781 char *arch
, *next
, *saved
;
9786 optimize_align_code
= 0;
9793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9794 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9795 should be emitted or not. FIXME: Not implemented. */
9799 /* -V: SVR4 argument to print version ID. */
9801 print_version_id ();
9804 /* -k: Ignore for FreeBSD compatibility. */
9809 /* -s: On i386 Solaris, this tells the native assembler to use
9810 .stab instead of .stab.excl. We always use .stab anyhow. */
9813 case OPTION_MSHARED
:
9817 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9818 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9821 const char **list
, **l
;
9823 list
= bfd_target_list ();
9824 for (l
= list
; *l
!= NULL
; l
++)
9825 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9826 || strcmp (*l
, "coff-x86-64") == 0
9827 || strcmp (*l
, "pe-x86-64") == 0
9828 || strcmp (*l
, "pei-x86-64") == 0
9829 || strcmp (*l
, "mach-o-x86-64") == 0)
9831 default_arch
= "x86_64";
9835 as_fatal (_("no compiled in support for x86_64"));
9841 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9845 const char **list
, **l
;
9847 list
= bfd_target_list ();
9848 for (l
= list
; *l
!= NULL
; l
++)
9849 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9851 default_arch
= "x86_64:32";
9855 as_fatal (_("no compiled in support for 32bit x86_64"));
9859 as_fatal (_("32bit x86_64 is only supported for ELF"));
9864 default_arch
= "i386";
9868 #ifdef SVR4_COMMENT_CHARS
9873 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9875 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9879 i386_comment_chars
= n
;
9885 saved
= xstrdup (arg
);
9887 /* Allow -march=+nosse. */
9893 as_fatal (_("invalid -march= option: `%s'"), arg
);
9894 next
= strchr (arch
, '+');
9897 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9899 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9902 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9905 cpu_arch_name
= cpu_arch
[j
].name
;
9906 cpu_sub_arch_name
= NULL
;
9907 cpu_arch_flags
= cpu_arch
[j
].flags
;
9908 cpu_arch_isa
= cpu_arch
[j
].type
;
9909 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9910 if (!cpu_arch_tune_set
)
9912 cpu_arch_tune
= cpu_arch_isa
;
9913 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9917 else if (*cpu_arch
[j
].name
== '.'
9918 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9920 /* ISA entension. */
9921 i386_cpu_flags flags
;
9923 flags
= cpu_flags_or (cpu_arch_flags
,
9926 if (!valid_iamcu_cpu_flags (&flags
))
9927 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9928 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9930 if (cpu_sub_arch_name
)
9932 char *name
= cpu_sub_arch_name
;
9933 cpu_sub_arch_name
= concat (name
,
9935 (const char *) NULL
);
9939 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9940 cpu_arch_flags
= flags
;
9941 cpu_arch_isa_flags
= flags
;
9947 if (j
>= ARRAY_SIZE (cpu_arch
))
9949 /* Disable an ISA entension. */
9950 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9951 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9953 i386_cpu_flags flags
;
9955 flags
= cpu_flags_and_not (cpu_arch_flags
,
9956 cpu_noarch
[j
].flags
);
9957 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9959 if (cpu_sub_arch_name
)
9961 char *name
= cpu_sub_arch_name
;
9962 cpu_sub_arch_name
= concat (arch
,
9963 (const char *) NULL
);
9967 cpu_sub_arch_name
= xstrdup (arch
);
9968 cpu_arch_flags
= flags
;
9969 cpu_arch_isa_flags
= flags
;
9974 if (j
>= ARRAY_SIZE (cpu_noarch
))
9975 j
= ARRAY_SIZE (cpu_arch
);
9978 if (j
>= ARRAY_SIZE (cpu_arch
))
9979 as_fatal (_("invalid -march= option: `%s'"), arg
);
9983 while (next
!= NULL
);
9989 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9990 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9992 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9994 cpu_arch_tune_set
= 1;
9995 cpu_arch_tune
= cpu_arch
[j
].type
;
9996 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10000 if (j
>= ARRAY_SIZE (cpu_arch
))
10001 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10004 case OPTION_MMNEMONIC
:
10005 if (strcasecmp (arg
, "att") == 0)
10006 intel_mnemonic
= 0;
10007 else if (strcasecmp (arg
, "intel") == 0)
10008 intel_mnemonic
= 1;
10010 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10013 case OPTION_MSYNTAX
:
10014 if (strcasecmp (arg
, "att") == 0)
10016 else if (strcasecmp (arg
, "intel") == 0)
10019 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10022 case OPTION_MINDEX_REG
:
10023 allow_index_reg
= 1;
10026 case OPTION_MNAKED_REG
:
10027 allow_naked_reg
= 1;
10030 case OPTION_MOLD_GCC
:
10034 case OPTION_MSSE2AVX
:
10038 case OPTION_MSSE_CHECK
:
10039 if (strcasecmp (arg
, "error") == 0)
10040 sse_check
= check_error
;
10041 else if (strcasecmp (arg
, "warning") == 0)
10042 sse_check
= check_warning
;
10043 else if (strcasecmp (arg
, "none") == 0)
10044 sse_check
= check_none
;
10046 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10049 case OPTION_MOPERAND_CHECK
:
10050 if (strcasecmp (arg
, "error") == 0)
10051 operand_check
= check_error
;
10052 else if (strcasecmp (arg
, "warning") == 0)
10053 operand_check
= check_warning
;
10054 else if (strcasecmp (arg
, "none") == 0)
10055 operand_check
= check_none
;
10057 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10060 case OPTION_MAVXSCALAR
:
10061 if (strcasecmp (arg
, "128") == 0)
10062 avxscalar
= vex128
;
10063 else if (strcasecmp (arg
, "256") == 0)
10064 avxscalar
= vex256
;
10066 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10069 case OPTION_MADD_BND_PREFIX
:
10070 add_bnd_prefix
= 1;
10073 case OPTION_MEVEXLIG
:
10074 if (strcmp (arg
, "128") == 0)
10075 evexlig
= evexl128
;
10076 else if (strcmp (arg
, "256") == 0)
10077 evexlig
= evexl256
;
10078 else if (strcmp (arg
, "512") == 0)
10079 evexlig
= evexl512
;
10081 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10084 case OPTION_MEVEXRCIG
:
10085 if (strcmp (arg
, "rne") == 0)
10087 else if (strcmp (arg
, "rd") == 0)
10089 else if (strcmp (arg
, "ru") == 0)
10091 else if (strcmp (arg
, "rz") == 0)
10094 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10097 case OPTION_MEVEXWIG
:
10098 if (strcmp (arg
, "0") == 0)
10100 else if (strcmp (arg
, "1") == 0)
10103 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10106 # if defined (TE_PE) || defined (TE_PEP)
10107 case OPTION_MBIG_OBJ
:
10112 case OPTION_MOMIT_LOCK_PREFIX
:
10113 if (strcasecmp (arg
, "yes") == 0)
10114 omit_lock_prefix
= 1;
10115 else if (strcasecmp (arg
, "no") == 0)
10116 omit_lock_prefix
= 0;
10118 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10121 case OPTION_MFENCE_AS_LOCK_ADD
:
10122 if (strcasecmp (arg
, "yes") == 0)
10124 else if (strcasecmp (arg
, "no") == 0)
10127 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10130 case OPTION_MRELAX_RELOCATIONS
:
10131 if (strcasecmp (arg
, "yes") == 0)
10132 generate_relax_relocations
= 1;
10133 else if (strcasecmp (arg
, "no") == 0)
10134 generate_relax_relocations
= 0;
10136 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10139 case OPTION_MAMD64
:
10143 case OPTION_MINTEL64
:
10153 #define MESSAGE_TEMPLATE \
10157 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10158 int *left_p
, const char *name
, int len
)
10160 int size
= sizeof (MESSAGE_TEMPLATE
);
10161 int left
= *left_p
;
10163 /* Reserve 2 spaces for ", " or ",\0" */
10166 /* Check if there is any room. */
10174 p
= mempcpy (p
, name
, len
);
10178 /* Output the current message now and start a new one. */
10181 fprintf (stream
, "%s\n", message
);
10183 left
= size
- (start
- message
) - len
- 2;
10185 gas_assert (left
>= 0);
10187 p
= mempcpy (p
, name
, len
);
10195 show_arch (FILE *stream
, int ext
, int check
)
10197 static char message
[] = MESSAGE_TEMPLATE
;
10198 char *start
= message
+ 27;
10200 int size
= sizeof (MESSAGE_TEMPLATE
);
10207 left
= size
- (start
- message
);
10208 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10210 /* Should it be skipped? */
10211 if (cpu_arch
[j
].skip
)
10214 name
= cpu_arch
[j
].name
;
10215 len
= cpu_arch
[j
].len
;
10218 /* It is an extension. Skip if we aren't asked to show it. */
10229 /* It is an processor. Skip if we show only extension. */
10232 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10234 /* It is an impossible processor - skip. */
10238 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10241 /* Display disabled extensions. */
10243 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10245 name
= cpu_noarch
[j
].name
;
10246 len
= cpu_noarch
[j
].len
;
10247 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10252 fprintf (stream
, "%s\n", message
);
10256 md_show_usage (FILE *stream
)
10258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10259 fprintf (stream
, _("\
10261 -V print assembler version number\n\
10264 fprintf (stream
, _("\
10265 -n Do not optimize code alignment\n\
10266 -q quieten some warnings\n"));
10267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10268 fprintf (stream
, _("\
10271 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10272 || defined (TE_PE) || defined (TE_PEP))
10273 fprintf (stream
, _("\
10274 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10276 #ifdef SVR4_COMMENT_CHARS
10277 fprintf (stream
, _("\
10278 --divide do not treat `/' as a comment character\n"));
10280 fprintf (stream
, _("\
10281 --divide ignored\n"));
10283 fprintf (stream
, _("\
10284 -march=CPU[,+EXTENSION...]\n\
10285 generate code for CPU and EXTENSION, CPU is one of:\n"));
10286 show_arch (stream
, 0, 1);
10287 fprintf (stream
, _("\
10288 EXTENSION is combination of:\n"));
10289 show_arch (stream
, 1, 0);
10290 fprintf (stream
, _("\
10291 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10292 show_arch (stream
, 0, 0);
10293 fprintf (stream
, _("\
10294 -msse2avx encode SSE instructions with VEX prefix\n"));
10295 fprintf (stream
, _("\
10296 -msse-check=[none|error|warning]\n\
10297 check SSE instructions\n"));
10298 fprintf (stream
, _("\
10299 -moperand-check=[none|error|warning]\n\
10300 check operand combinations for validity\n"));
10301 fprintf (stream
, _("\
10302 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10304 fprintf (stream
, _("\
10305 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10307 fprintf (stream
, _("\
10308 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10309 for EVEX.W bit ignored instructions\n"));
10310 fprintf (stream
, _("\
10311 -mevexrcig=[rne|rd|ru|rz]\n\
10312 encode EVEX instructions with specific EVEX.RC value\n\
10313 for SAE-only ignored instructions\n"));
10314 fprintf (stream
, _("\
10315 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10316 fprintf (stream
, _("\
10317 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10318 fprintf (stream
, _("\
10319 -mindex-reg support pseudo index registers\n"));
10320 fprintf (stream
, _("\
10321 -mnaked-reg don't require `%%' prefix for registers\n"));
10322 fprintf (stream
, _("\
10323 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10324 fprintf (stream
, _("\
10325 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10326 fprintf (stream
, _("\
10327 -mshared disable branch optimization for shared code\n"));
10328 # if defined (TE_PE) || defined (TE_PEP)
10329 fprintf (stream
, _("\
10330 -mbig-obj generate big object files\n"));
10332 fprintf (stream
, _("\
10333 -momit-lock-prefix=[no|yes]\n\
10334 strip all lock prefixes\n"));
10335 fprintf (stream
, _("\
10336 -mfence-as-lock-add=[no|yes]\n\
10337 encode lfence, mfence and sfence as\n\
10338 lock addl $0x0, (%%{re}sp)\n"));
10339 fprintf (stream
, _("\
10340 -mrelax-relocations=[no|yes]\n\
10341 generate relax relocations\n"));
10342 fprintf (stream
, _("\
10343 -mamd64 accept only AMD64 ISA\n"));
10344 fprintf (stream
, _("\
10345 -mintel64 accept only Intel64 ISA\n"));
10348 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10349 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10350 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10352 /* Pick the target format to use. */
10355 i386_target_format (void)
10357 if (!strncmp (default_arch
, "x86_64", 6))
10359 update_code_flag (CODE_64BIT
, 1);
10360 if (default_arch
[6] == '\0')
10361 x86_elf_abi
= X86_64_ABI
;
10363 x86_elf_abi
= X86_64_X32_ABI
;
10365 else if (!strcmp (default_arch
, "i386"))
10366 update_code_flag (CODE_32BIT
, 1);
10367 else if (!strcmp (default_arch
, "iamcu"))
10369 update_code_flag (CODE_32BIT
, 1);
10370 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10372 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10373 cpu_arch_name
= "iamcu";
10374 cpu_sub_arch_name
= NULL
;
10375 cpu_arch_flags
= iamcu_flags
;
10376 cpu_arch_isa
= PROCESSOR_IAMCU
;
10377 cpu_arch_isa_flags
= iamcu_flags
;
10378 if (!cpu_arch_tune_set
)
10380 cpu_arch_tune
= cpu_arch_isa
;
10381 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10385 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10389 as_fatal (_("unknown architecture"));
10391 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10392 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10393 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10394 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10396 switch (OUTPUT_FLAVOR
)
10398 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10399 case bfd_target_aout_flavour
:
10400 return AOUT_TARGET_FORMAT
;
10402 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10403 # if defined (TE_PE) || defined (TE_PEP)
10404 case bfd_target_coff_flavour
:
10405 if (flag_code
== CODE_64BIT
)
10406 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10409 # elif defined (TE_GO32)
10410 case bfd_target_coff_flavour
:
10411 return "coff-go32";
10413 case bfd_target_coff_flavour
:
10414 return "coff-i386";
10417 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10418 case bfd_target_elf_flavour
:
10420 const char *format
;
10422 switch (x86_elf_abi
)
10425 format
= ELF_TARGET_FORMAT
;
10428 use_rela_relocations
= 1;
10430 format
= ELF_TARGET_FORMAT64
;
10432 case X86_64_X32_ABI
:
10433 use_rela_relocations
= 1;
10435 disallow_64bit_reloc
= 1;
10436 format
= ELF_TARGET_FORMAT32
;
10439 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10441 if (x86_elf_abi
!= X86_64_ABI
)
10442 as_fatal (_("Intel L1OM is 64bit only"));
10443 return ELF_TARGET_L1OM_FORMAT
;
10445 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10447 if (x86_elf_abi
!= X86_64_ABI
)
10448 as_fatal (_("Intel K1OM is 64bit only"));
10449 return ELF_TARGET_K1OM_FORMAT
;
10451 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10453 if (x86_elf_abi
!= I386_ABI
)
10454 as_fatal (_("Intel MCU is 32bit only"));
10455 return ELF_TARGET_IAMCU_FORMAT
;
10461 #if defined (OBJ_MACH_O)
10462 case bfd_target_mach_o_flavour
:
10463 if (flag_code
== CODE_64BIT
)
10465 use_rela_relocations
= 1;
10467 return "mach-o-x86-64";
10470 return "mach-o-i386";
10478 #endif /* OBJ_MAYBE_ more than one */
10481 md_undefined_symbol (char *name
)
10483 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10484 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10485 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10486 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10490 if (symbol_find (name
))
10491 as_bad (_("GOT already in symbol table"));
10492 GOT_symbol
= symbol_new (name
, undefined_section
,
10493 (valueT
) 0, &zero_address_frag
);
10500 /* Round up a section size to the appropriate boundary. */
10503 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10505 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10506 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10508 /* For a.out, force the section size to be aligned. If we don't do
10509 this, BFD will align it for us, but it will not write out the
10510 final bytes of the section. This may be a bug in BFD, but it is
10511 easier to fix it here since that is how the other a.out targets
10515 align
= bfd_get_section_alignment (stdoutput
, segment
);
10516 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10523 /* On the i386, PC-relative offsets are relative to the start of the
10524 next instruction. That is, the address of the offset, plus its
10525 size, since the offset is always the last part of the insn. */
10528 md_pcrel_from (fixS
*fixP
)
10530 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10536 s_bss (int ignore ATTRIBUTE_UNUSED
)
10540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10542 obj_elf_section_change_hook ();
10544 temp
= get_absolute_expression ();
10545 subseg_set (bss_section
, (subsegT
) temp
);
10546 demand_empty_rest_of_line ();
10552 i386_validate_fix (fixS
*fixp
)
10554 if (fixp
->fx_subsy
)
10556 if (fixp
->fx_subsy
== GOT_symbol
)
10558 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10563 if (fixp
->fx_tcbit2
)
10564 fixp
->fx_r_type
= (fixp
->fx_tcbit
10565 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10566 : BFD_RELOC_X86_64_GOTPCRELX
);
10569 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10574 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10576 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10578 fixp
->fx_subsy
= 0;
10581 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10582 else if (!object_64bit
)
10584 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10585 && fixp
->fx_tcbit2
)
10586 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10592 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10595 bfd_reloc_code_real_type code
;
10597 switch (fixp
->fx_r_type
)
10599 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10600 case BFD_RELOC_SIZE32
:
10601 case BFD_RELOC_SIZE64
:
10602 if (S_IS_DEFINED (fixp
->fx_addsy
)
10603 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10605 /* Resolve size relocation against local symbol to size of
10606 the symbol plus addend. */
10607 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10608 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10609 && !fits_in_unsigned_long (value
))
10610 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10611 _("symbol size computation overflow"));
10612 fixp
->fx_addsy
= NULL
;
10613 fixp
->fx_subsy
= NULL
;
10614 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10619 case BFD_RELOC_X86_64_PLT32
:
10620 case BFD_RELOC_X86_64_GOT32
:
10621 case BFD_RELOC_X86_64_GOTPCREL
:
10622 case BFD_RELOC_X86_64_GOTPCRELX
:
10623 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10624 case BFD_RELOC_386_PLT32
:
10625 case BFD_RELOC_386_GOT32
:
10626 case BFD_RELOC_386_GOT32X
:
10627 case BFD_RELOC_386_GOTOFF
:
10628 case BFD_RELOC_386_GOTPC
:
10629 case BFD_RELOC_386_TLS_GD
:
10630 case BFD_RELOC_386_TLS_LDM
:
10631 case BFD_RELOC_386_TLS_LDO_32
:
10632 case BFD_RELOC_386_TLS_IE_32
:
10633 case BFD_RELOC_386_TLS_IE
:
10634 case BFD_RELOC_386_TLS_GOTIE
:
10635 case BFD_RELOC_386_TLS_LE_32
:
10636 case BFD_RELOC_386_TLS_LE
:
10637 case BFD_RELOC_386_TLS_GOTDESC
:
10638 case BFD_RELOC_386_TLS_DESC_CALL
:
10639 case BFD_RELOC_X86_64_TLSGD
:
10640 case BFD_RELOC_X86_64_TLSLD
:
10641 case BFD_RELOC_X86_64_DTPOFF32
:
10642 case BFD_RELOC_X86_64_DTPOFF64
:
10643 case BFD_RELOC_X86_64_GOTTPOFF
:
10644 case BFD_RELOC_X86_64_TPOFF32
:
10645 case BFD_RELOC_X86_64_TPOFF64
:
10646 case BFD_RELOC_X86_64_GOTOFF64
:
10647 case BFD_RELOC_X86_64_GOTPC32
:
10648 case BFD_RELOC_X86_64_GOT64
:
10649 case BFD_RELOC_X86_64_GOTPCREL64
:
10650 case BFD_RELOC_X86_64_GOTPC64
:
10651 case BFD_RELOC_X86_64_GOTPLT64
:
10652 case BFD_RELOC_X86_64_PLTOFF64
:
10653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10654 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10655 case BFD_RELOC_RVA
:
10656 case BFD_RELOC_VTABLE_ENTRY
:
10657 case BFD_RELOC_VTABLE_INHERIT
:
10659 case BFD_RELOC_32_SECREL
:
10661 code
= fixp
->fx_r_type
;
10663 case BFD_RELOC_X86_64_32S
:
10664 if (!fixp
->fx_pcrel
)
10666 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10667 code
= fixp
->fx_r_type
;
10671 if (fixp
->fx_pcrel
)
10673 switch (fixp
->fx_size
)
10676 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10677 _("can not do %d byte pc-relative relocation"),
10679 code
= BFD_RELOC_32_PCREL
;
10681 case 1: code
= BFD_RELOC_8_PCREL
; break;
10682 case 2: code
= BFD_RELOC_16_PCREL
; break;
10683 case 4: code
= BFD_RELOC_32_PCREL
; break;
10685 case 8: code
= BFD_RELOC_64_PCREL
; break;
10691 switch (fixp
->fx_size
)
10694 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10695 _("can not do %d byte relocation"),
10697 code
= BFD_RELOC_32
;
10699 case 1: code
= BFD_RELOC_8
; break;
10700 case 2: code
= BFD_RELOC_16
; break;
10701 case 4: code
= BFD_RELOC_32
; break;
10703 case 8: code
= BFD_RELOC_64
; break;
10710 if ((code
== BFD_RELOC_32
10711 || code
== BFD_RELOC_32_PCREL
10712 || code
== BFD_RELOC_X86_64_32S
)
10714 && fixp
->fx_addsy
== GOT_symbol
)
10717 code
= BFD_RELOC_386_GOTPC
;
10719 code
= BFD_RELOC_X86_64_GOTPC32
;
10721 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10723 && fixp
->fx_addsy
== GOT_symbol
)
10725 code
= BFD_RELOC_X86_64_GOTPC64
;
10728 rel
= XNEW (arelent
);
10729 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10730 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10732 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10734 if (!use_rela_relocations
)
10736 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10737 vtable entry to be used in the relocation's section offset. */
10738 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10739 rel
->address
= fixp
->fx_offset
;
10740 #if defined (OBJ_COFF) && defined (TE_PE)
10741 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10742 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10747 /* Use the rela in 64bit mode. */
10750 if (disallow_64bit_reloc
)
10753 case BFD_RELOC_X86_64_DTPOFF64
:
10754 case BFD_RELOC_X86_64_TPOFF64
:
10755 case BFD_RELOC_64_PCREL
:
10756 case BFD_RELOC_X86_64_GOTOFF64
:
10757 case BFD_RELOC_X86_64_GOT64
:
10758 case BFD_RELOC_X86_64_GOTPCREL64
:
10759 case BFD_RELOC_X86_64_GOTPC64
:
10760 case BFD_RELOC_X86_64_GOTPLT64
:
10761 case BFD_RELOC_X86_64_PLTOFF64
:
10762 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10763 _("cannot represent relocation type %s in x32 mode"),
10764 bfd_get_reloc_code_name (code
));
10770 if (!fixp
->fx_pcrel
)
10771 rel
->addend
= fixp
->fx_offset
;
10775 case BFD_RELOC_X86_64_PLT32
:
10776 case BFD_RELOC_X86_64_GOT32
:
10777 case BFD_RELOC_X86_64_GOTPCREL
:
10778 case BFD_RELOC_X86_64_GOTPCRELX
:
10779 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10780 case BFD_RELOC_X86_64_TLSGD
:
10781 case BFD_RELOC_X86_64_TLSLD
:
10782 case BFD_RELOC_X86_64_GOTTPOFF
:
10783 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10784 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10785 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10788 rel
->addend
= (section
->vma
10790 + fixp
->fx_addnumber
10791 + md_pcrel_from (fixp
));
10796 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10797 if (rel
->howto
== NULL
)
10799 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10800 _("cannot represent relocation type %s"),
10801 bfd_get_reloc_code_name (code
));
10802 /* Set howto to a garbage value so that we can keep going. */
10803 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10804 gas_assert (rel
->howto
!= NULL
);
10810 #include "tc-i386-intel.c"
10813 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10815 int saved_naked_reg
;
10816 char saved_register_dot
;
10818 saved_naked_reg
= allow_naked_reg
;
10819 allow_naked_reg
= 1;
10820 saved_register_dot
= register_chars
['.'];
10821 register_chars
['.'] = '.';
10822 allow_pseudo_reg
= 1;
10823 expression_and_evaluate (exp
);
10824 allow_pseudo_reg
= 0;
10825 register_chars
['.'] = saved_register_dot
;
10826 allow_naked_reg
= saved_naked_reg
;
10828 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10830 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10832 exp
->X_op
= O_constant
;
10833 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10834 .dw2_regnum
[flag_code
>> 1];
10837 exp
->X_op
= O_illegal
;
10842 tc_x86_frame_initial_instructions (void)
10844 static unsigned int sp_regno
[2];
10846 if (!sp_regno
[flag_code
>> 1])
10848 char *saved_input
= input_line_pointer
;
10849 char sp
[][4] = {"esp", "rsp"};
10852 input_line_pointer
= sp
[flag_code
>> 1];
10853 tc_x86_parse_to_dw2regnum (&exp
);
10854 gas_assert (exp
.X_op
== O_constant
);
10855 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10856 input_line_pointer
= saved_input
;
10859 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10860 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10864 x86_dwarf2_addr_size (void)
10866 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10867 if (x86_elf_abi
== X86_64_X32_ABI
)
10870 return bfd_arch_bits_per_address (stdoutput
) / 8;
10874 i386_elf_section_type (const char *str
, size_t len
)
10876 if (flag_code
== CODE_64BIT
10877 && len
== sizeof ("unwind") - 1
10878 && strncmp (str
, "unwind", 6) == 0)
10879 return SHT_X86_64_UNWIND
;
10886 i386_solaris_fix_up_eh_frame (segT sec
)
10888 if (flag_code
== CODE_64BIT
)
10889 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10895 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10899 exp
.X_op
= O_secrel
;
10900 exp
.X_add_symbol
= symbol
;
10901 exp
.X_add_number
= 0;
10902 emit_expr (&exp
, size
);
10906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10907 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10910 x86_64_section_letter (int letter
, const char **ptr_msg
)
10912 if (flag_code
== CODE_64BIT
)
10915 return SHF_X86_64_LARGE
;
10917 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10920 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10925 x86_64_section_word (char *str
, size_t len
)
10927 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10928 return SHF_X86_64_LARGE
;
10934 handle_large_common (int small ATTRIBUTE_UNUSED
)
10936 if (flag_code
!= CODE_64BIT
)
10938 s_comm_internal (0, elf_common_parse
);
10939 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10943 static segT lbss_section
;
10944 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10945 asection
*saved_bss_section
= bss_section
;
10947 if (lbss_section
== NULL
)
10949 flagword applicable
;
10950 segT seg
= now_seg
;
10951 subsegT subseg
= now_subseg
;
10953 /* The .lbss section is for local .largecomm symbols. */
10954 lbss_section
= subseg_new (".lbss", 0);
10955 applicable
= bfd_applicable_section_flags (stdoutput
);
10956 bfd_set_section_flags (stdoutput
, lbss_section
,
10957 applicable
& SEC_ALLOC
);
10958 seg_info (lbss_section
)->bss
= 1;
10960 subseg_set (seg
, subseg
);
10963 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10964 bss_section
= lbss_section
;
10966 s_comm_internal (0, elf_common_parse
);
10968 elf_com_section_ptr
= saved_com_section_ptr
;
10969 bss_section
= saved_bss_section
;
10972 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */