1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
962 CPU_PCOMMIT_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512IFMA_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512VBMI_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
968 CPU_CLZERO_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
970 CPU_MWAITX_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
972 CPU_OSPKE_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
974 CPU_RDPID_FLAGS
, 0 },
975 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
976 CPU_PTWRITE_FLAGS
, 0 },
979 static const noarch_entry cpu_noarch
[] =
981 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
982 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
983 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
984 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
985 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
986 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
987 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
988 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
989 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
990 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
991 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
992 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
993 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
994 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
995 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
996 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1002 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1003 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1007 /* Like s_lcomm_internal in gas/read.c but the alignment string
1008 is allowed to be optional. */
1011 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1018 && *input_line_pointer
== ',')
1020 align
= parse_align (needs_align
- 1);
1022 if (align
== (addressT
) -1)
1037 bss_alloc (symbolP
, size
, align
);
1042 pe_lcomm (int needs_align
)
1044 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1048 const pseudo_typeS md_pseudo_table
[] =
1050 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1051 {"align", s_align_bytes
, 0},
1053 {"align", s_align_ptwo
, 0},
1055 {"arch", set_cpu_arch
, 0},
1059 {"lcomm", pe_lcomm
, 1},
1061 {"ffloat", float_cons
, 'f'},
1062 {"dfloat", float_cons
, 'd'},
1063 {"tfloat", float_cons
, 'x'},
1065 {"slong", signed_cons
, 4},
1066 {"noopt", s_ignore
, 0},
1067 {"optim", s_ignore
, 0},
1068 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1069 {"code16", set_code_flag
, CODE_16BIT
},
1070 {"code32", set_code_flag
, CODE_32BIT
},
1071 {"code64", set_code_flag
, CODE_64BIT
},
1072 {"intel_syntax", set_intel_syntax
, 1},
1073 {"att_syntax", set_intel_syntax
, 0},
1074 {"intel_mnemonic", set_intel_mnemonic
, 1},
1075 {"att_mnemonic", set_intel_mnemonic
, 0},
1076 {"allow_index_reg", set_allow_index_reg
, 1},
1077 {"disallow_index_reg", set_allow_index_reg
, 0},
1078 {"sse_check", set_check
, 0},
1079 {"operand_check", set_check
, 1},
1080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1081 {"largecomm", handle_large_common
, 0},
1083 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1084 {"loc", dwarf2_directive_loc
, 0},
1085 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1088 {"secrel32", pe_directive_secrel
, 0},
1093 /* For interface with expression (). */
1094 extern char *input_line_pointer
;
1096 /* Hash table for instruction mnemonic lookup. */
1097 static struct hash_control
*op_hash
;
1099 /* Hash table for register lookup. */
1100 static struct hash_control
*reg_hash
;
1103 i386_align_code (fragS
*fragP
, int count
)
1105 /* Various efficient no-op patterns for aligning code labels.
1106 Note: Don't try to assemble the instructions in the comments.
1107 0L and 0w are not legal. */
1108 static const unsigned char f32_1
[] =
1110 static const unsigned char f32_2
[] =
1111 {0x66,0x90}; /* xchg %ax,%ax */
1112 static const unsigned char f32_3
[] =
1113 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1114 static const unsigned char f32_4
[] =
1115 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1116 static const unsigned char f32_5
[] =
1118 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1119 static const unsigned char f32_6
[] =
1120 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1121 static const unsigned char f32_7
[] =
1122 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1123 static const unsigned char f32_8
[] =
1125 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1126 static const unsigned char f32_9
[] =
1127 {0x89,0xf6, /* movl %esi,%esi */
1128 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1129 static const unsigned char f32_10
[] =
1130 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1131 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1132 static const unsigned char f32_11
[] =
1133 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1134 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1135 static const unsigned char f32_12
[] =
1136 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1137 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1138 static const unsigned char f32_13
[] =
1139 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1140 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1141 static const unsigned char f32_14
[] =
1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1143 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1144 static const unsigned char f16_3
[] =
1145 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1146 static const unsigned char f16_4
[] =
1147 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1148 static const unsigned char f16_5
[] =
1150 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1151 static const unsigned char f16_6
[] =
1152 {0x89,0xf6, /* mov %si,%si */
1153 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1154 static const unsigned char f16_7
[] =
1155 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1156 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1157 static const unsigned char f16_8
[] =
1158 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1159 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1160 static const unsigned char jump_31
[] =
1161 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1163 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1164 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1165 static const unsigned char *const f32_patt
[] = {
1166 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1167 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1169 static const unsigned char *const f16_patt
[] = {
1170 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1172 /* nopl (%[re]ax) */
1173 static const unsigned char alt_3
[] =
1175 /* nopl 0(%[re]ax) */
1176 static const unsigned char alt_4
[] =
1177 {0x0f,0x1f,0x40,0x00};
1178 /* nopl 0(%[re]ax,%[re]ax,1) */
1179 static const unsigned char alt_5
[] =
1180 {0x0f,0x1f,0x44,0x00,0x00};
1181 /* nopw 0(%[re]ax,%[re]ax,1) */
1182 static const unsigned char alt_6
[] =
1183 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1184 /* nopl 0L(%[re]ax) */
1185 static const unsigned char alt_7
[] =
1186 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1187 /* nopl 0L(%[re]ax,%[re]ax,1) */
1188 static const unsigned char alt_8
[] =
1189 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1190 /* nopw 0L(%[re]ax,%[re]ax,1) */
1191 static const unsigned char alt_9
[] =
1192 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1193 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1194 static const unsigned char alt_10
[] =
1195 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1196 static const unsigned char *const alt_patt
[] = {
1197 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1201 /* Only align for at least a positive non-zero boundary. */
1202 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1205 /* We need to decide which NOP sequence to use for 32bit and
1206 64bit. When -mtune= is used:
1208 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1209 PROCESSOR_GENERIC32, f32_patt will be used.
1210 2. For the rest, alt_patt will be used.
1212 When -mtune= isn't used, alt_patt will be used if
1213 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1216 When -march= or .arch is used, we can't use anything beyond
1217 cpu_arch_isa_flags. */
1219 if (flag_code
== CODE_16BIT
)
1223 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1225 /* Adjust jump offset. */
1226 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1229 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1230 f16_patt
[count
- 1], count
);
1234 const unsigned char *const *patt
= NULL
;
1236 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1238 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1239 switch (cpu_arch_tune
)
1241 case PROCESSOR_UNKNOWN
:
1242 /* We use cpu_arch_isa_flags to check if we SHOULD
1243 optimize with nops. */
1244 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1249 case PROCESSOR_PENTIUM4
:
1250 case PROCESSOR_NOCONA
:
1251 case PROCESSOR_CORE
:
1252 case PROCESSOR_CORE2
:
1253 case PROCESSOR_COREI7
:
1254 case PROCESSOR_L1OM
:
1255 case PROCESSOR_K1OM
:
1256 case PROCESSOR_GENERIC64
:
1258 case PROCESSOR_ATHLON
:
1260 case PROCESSOR_AMDFAM10
:
1262 case PROCESSOR_ZNVER
:
1266 case PROCESSOR_I386
:
1267 case PROCESSOR_I486
:
1268 case PROCESSOR_PENTIUM
:
1269 case PROCESSOR_PENTIUMPRO
:
1270 case PROCESSOR_IAMCU
:
1271 case PROCESSOR_GENERIC32
:
1278 switch (fragP
->tc_frag_data
.tune
)
1280 case PROCESSOR_UNKNOWN
:
1281 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1282 PROCESSOR_UNKNOWN. */
1286 case PROCESSOR_I386
:
1287 case PROCESSOR_I486
:
1288 case PROCESSOR_PENTIUM
:
1289 case PROCESSOR_IAMCU
:
1291 case PROCESSOR_ATHLON
:
1293 case PROCESSOR_AMDFAM10
:
1295 case PROCESSOR_ZNVER
:
1297 case PROCESSOR_GENERIC32
:
1298 /* We use cpu_arch_isa_flags to check if we CAN optimize
1300 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1305 case PROCESSOR_PENTIUMPRO
:
1306 case PROCESSOR_PENTIUM4
:
1307 case PROCESSOR_NOCONA
:
1308 case PROCESSOR_CORE
:
1309 case PROCESSOR_CORE2
:
1310 case PROCESSOR_COREI7
:
1311 case PROCESSOR_L1OM
:
1312 case PROCESSOR_K1OM
:
1313 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1318 case PROCESSOR_GENERIC64
:
1324 if (patt
== f32_patt
)
1326 /* If the padding is less than 15 bytes, we use the normal
1327 ones. Otherwise, we use a jump instruction and adjust
1331 /* For 64bit, the limit is 3 bytes. */
1332 if (flag_code
== CODE_64BIT
1333 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1338 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1339 patt
[count
- 1], count
);
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1344 /* Adjust jump offset. */
1345 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1350 /* Maximum length of an instruction is 10 byte. If the
1351 padding is greater than 10 bytes and we don't use jump,
1352 we have to break it into smaller pieces. */
1353 int padding
= count
;
1354 while (padding
> 10)
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1362 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1363 patt
[padding
- 1], padding
);
1366 fragP
->fr_var
= count
;
1370 operand_type_all_zero (const union i386_operand_type
*x
)
1372 switch (ARRAY_SIZE(x
->array
))
1383 return !x
->array
[0];
1390 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1392 switch (ARRAY_SIZE(x
->array
))
1410 operand_type_equal (const union i386_operand_type
*x
,
1411 const union i386_operand_type
*y
)
1413 switch (ARRAY_SIZE(x
->array
))
1416 if (x
->array
[2] != y
->array
[2])
1420 if (x
->array
[1] != y
->array
[1])
1424 return x
->array
[0] == y
->array
[0];
1432 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1434 switch (ARRAY_SIZE(x
->array
))
1445 return !x
->array
[0];
1452 cpu_flags_equal (const union i386_cpu_flags
*x
,
1453 const union i386_cpu_flags
*y
)
1455 switch (ARRAY_SIZE(x
->array
))
1458 if (x
->array
[2] != y
->array
[2])
1462 if (x
->array
[1] != y
->array
[1])
1466 return x
->array
[0] == y
->array
[0];
1474 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1476 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1477 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1480 static INLINE i386_cpu_flags
1481 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1483 switch (ARRAY_SIZE (x
.array
))
1486 x
.array
[2] &= y
.array
[2];
1489 x
.array
[1] &= y
.array
[1];
1492 x
.array
[0] &= y
.array
[0];
1500 static INLINE i386_cpu_flags
1501 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1503 switch (ARRAY_SIZE (x
.array
))
1506 x
.array
[2] |= y
.array
[2];
1509 x
.array
[1] |= y
.array
[1];
1512 x
.array
[0] |= y
.array
[0];
1520 static INLINE i386_cpu_flags
1521 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1523 switch (ARRAY_SIZE (x
.array
))
1526 x
.array
[2] &= ~y
.array
[2];
1529 x
.array
[1] &= ~y
.array
[1];
1532 x
.array
[0] &= ~y
.array
[0];
1540 #define CPU_FLAGS_ARCH_MATCH 0x1
1541 #define CPU_FLAGS_64BIT_MATCH 0x2
1542 #define CPU_FLAGS_AES_MATCH 0x4
1543 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1544 #define CPU_FLAGS_AVX_MATCH 0x10
1546 #define CPU_FLAGS_32BIT_MATCH \
1547 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1548 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1549 #define CPU_FLAGS_PERFECT_MATCH \
1550 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1552 /* Return CPU flags match bits. */
1555 cpu_flags_match (const insn_template
*t
)
1557 i386_cpu_flags x
= t
->cpu_flags
;
1558 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1560 x
.bitfield
.cpu64
= 0;
1561 x
.bitfield
.cpuno64
= 0;
1563 if (cpu_flags_all_zero (&x
))
1565 /* This instruction is available on all archs. */
1566 match
|= CPU_FLAGS_32BIT_MATCH
;
1570 /* This instruction is available only on some archs. */
1571 i386_cpu_flags cpu
= cpu_arch_flags
;
1573 cpu
= cpu_flags_and (x
, cpu
);
1574 if (!cpu_flags_all_zero (&cpu
))
1576 if (x
.bitfield
.cpuavx
)
1578 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1579 if (cpu
.bitfield
.cpuavx
)
1581 /* Check SSE2AVX. */
1582 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1584 match
|= (CPU_FLAGS_ARCH_MATCH
1585 | CPU_FLAGS_AVX_MATCH
);
1587 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1588 match
|= CPU_FLAGS_AES_MATCH
;
1590 if (!x
.bitfield
.cpupclmul
1591 || cpu
.bitfield
.cpupclmul
)
1592 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1596 match
|= CPU_FLAGS_ARCH_MATCH
;
1598 else if (x
.bitfield
.cpuavx512vl
)
1600 /* Match AVX512VL. */
1601 if (cpu
.bitfield
.cpuavx512vl
)
1603 /* Need another match. */
1604 cpu
.bitfield
.cpuavx512vl
= 0;
1605 if (!cpu_flags_all_zero (&cpu
))
1606 match
|= CPU_FLAGS_32BIT_MATCH
;
1608 match
|= CPU_FLAGS_ARCH_MATCH
;
1611 match
|= CPU_FLAGS_ARCH_MATCH
;
1614 match
|= CPU_FLAGS_32BIT_MATCH
;
1620 static INLINE i386_operand_type
1621 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1623 switch (ARRAY_SIZE (x
.array
))
1626 x
.array
[2] &= y
.array
[2];
1629 x
.array
[1] &= y
.array
[1];
1632 x
.array
[0] &= y
.array
[0];
1640 static INLINE i386_operand_type
1641 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1643 switch (ARRAY_SIZE (x
.array
))
1646 x
.array
[2] |= y
.array
[2];
1649 x
.array
[1] |= y
.array
[1];
1652 x
.array
[0] |= y
.array
[0];
1660 static INLINE i386_operand_type
1661 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1663 switch (ARRAY_SIZE (x
.array
))
1666 x
.array
[2] ^= y
.array
[2];
1669 x
.array
[1] ^= y
.array
[1];
1672 x
.array
[0] ^= y
.array
[0];
1680 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1681 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1682 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1683 static const i386_operand_type inoutportreg
1684 = OPERAND_TYPE_INOUTPORTREG
;
1685 static const i386_operand_type reg16_inoutportreg
1686 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1687 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1688 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1689 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1690 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1691 static const i386_operand_type anydisp
1692 = OPERAND_TYPE_ANYDISP
;
1693 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1694 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1695 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1696 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1697 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1698 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1699 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1700 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1701 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1702 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1703 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1704 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1705 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1706 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1717 operand_type_check (i386_operand_type t
, enum operand_type c
)
1722 return (t
.bitfield
.reg8
1725 || t
.bitfield
.reg64
);
1728 return (t
.bitfield
.imm8
1732 || t
.bitfield
.imm32s
1733 || t
.bitfield
.imm64
);
1736 return (t
.bitfield
.disp8
1737 || t
.bitfield
.disp16
1738 || t
.bitfield
.disp32
1739 || t
.bitfield
.disp32s
1740 || t
.bitfield
.disp64
);
1743 return (t
.bitfield
.disp8
1744 || t
.bitfield
.disp16
1745 || t
.bitfield
.disp32
1746 || t
.bitfield
.disp32s
1747 || t
.bitfield
.disp64
1748 || t
.bitfield
.baseindex
);
1757 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1758 operand J for instruction template T. */
1761 match_reg_size (const insn_template
*t
, unsigned int j
)
1763 return !((i
.types
[j
].bitfield
.byte
1764 && !t
->operand_types
[j
].bitfield
.byte
)
1765 || (i
.types
[j
].bitfield
.word
1766 && !t
->operand_types
[j
].bitfield
.word
)
1767 || (i
.types
[j
].bitfield
.dword
1768 && !t
->operand_types
[j
].bitfield
.dword
)
1769 || (i
.types
[j
].bitfield
.qword
1770 && !t
->operand_types
[j
].bitfield
.qword
));
1773 /* Return 1 if there is no conflict in any size on operand J for
1774 instruction template T. */
1777 match_mem_size (const insn_template
*t
, unsigned int j
)
1779 return (match_reg_size (t
, j
)
1780 && !((i
.types
[j
].bitfield
.unspecified
1782 && !t
->operand_types
[j
].bitfield
.unspecified
)
1783 || (i
.types
[j
].bitfield
.fword
1784 && !t
->operand_types
[j
].bitfield
.fword
)
1785 || (i
.types
[j
].bitfield
.tbyte
1786 && !t
->operand_types
[j
].bitfield
.tbyte
)
1787 || (i
.types
[j
].bitfield
.xmmword
1788 && !t
->operand_types
[j
].bitfield
.xmmword
)
1789 || (i
.types
[j
].bitfield
.ymmword
1790 && !t
->operand_types
[j
].bitfield
.ymmword
)
1791 || (i
.types
[j
].bitfield
.zmmword
1792 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1795 /* Return 1 if there is no size conflict on any operands for
1796 instruction template T. */
1799 operand_size_match (const insn_template
*t
)
1804 /* Don't check jump instructions. */
1805 if (t
->opcode_modifier
.jump
1806 || t
->opcode_modifier
.jumpbyte
1807 || t
->opcode_modifier
.jumpdword
1808 || t
->opcode_modifier
.jumpintersegment
)
1811 /* Check memory and accumulator operand size. */
1812 for (j
= 0; j
< i
.operands
; j
++)
1814 if (t
->operand_types
[j
].bitfield
.anysize
)
1817 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1823 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1832 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1835 i
.error
= operand_size_mismatch
;
1839 /* Check reverse. */
1840 gas_assert (i
.operands
== 2);
1843 for (j
= 0; j
< 2; j
++)
1845 if (t
->operand_types
[j
].bitfield
.acc
1846 && !match_reg_size (t
, j
? 0 : 1))
1849 if (i
.types
[j
].bitfield
.mem
1850 && !match_mem_size (t
, j
? 0 : 1))
1858 operand_type_match (i386_operand_type overlap
,
1859 i386_operand_type given
)
1861 i386_operand_type temp
= overlap
;
1863 temp
.bitfield
.jumpabsolute
= 0;
1864 temp
.bitfield
.unspecified
= 0;
1865 temp
.bitfield
.byte
= 0;
1866 temp
.bitfield
.word
= 0;
1867 temp
.bitfield
.dword
= 0;
1868 temp
.bitfield
.fword
= 0;
1869 temp
.bitfield
.qword
= 0;
1870 temp
.bitfield
.tbyte
= 0;
1871 temp
.bitfield
.xmmword
= 0;
1872 temp
.bitfield
.ymmword
= 0;
1873 temp
.bitfield
.zmmword
= 0;
1874 if (operand_type_all_zero (&temp
))
1877 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1878 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1882 i
.error
= operand_type_mismatch
;
1886 /* If given types g0 and g1 are registers they must be of the same type
1887 unless the expected operand type register overlap is null.
1888 Note that Acc in a template matches every size of reg. */
1891 operand_type_register_match (i386_operand_type m0
,
1892 i386_operand_type g0
,
1893 i386_operand_type t0
,
1894 i386_operand_type m1
,
1895 i386_operand_type g1
,
1896 i386_operand_type t1
)
1898 if (!operand_type_check (g0
, reg
))
1901 if (!operand_type_check (g1
, reg
))
1904 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1905 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1906 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1907 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1910 if (m0
.bitfield
.acc
)
1912 t0
.bitfield
.reg8
= 1;
1913 t0
.bitfield
.reg16
= 1;
1914 t0
.bitfield
.reg32
= 1;
1915 t0
.bitfield
.reg64
= 1;
1918 if (m1
.bitfield
.acc
)
1920 t1
.bitfield
.reg8
= 1;
1921 t1
.bitfield
.reg16
= 1;
1922 t1
.bitfield
.reg32
= 1;
1923 t1
.bitfield
.reg64
= 1;
1926 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1927 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1928 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1929 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1932 i
.error
= register_type_mismatch
;
1937 static INLINE
unsigned int
1938 register_number (const reg_entry
*r
)
1940 unsigned int nr
= r
->reg_num
;
1942 if (r
->reg_flags
& RegRex
)
1945 if (r
->reg_flags
& RegVRex
)
1951 static INLINE
unsigned int
1952 mode_from_disp_size (i386_operand_type t
)
1954 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1956 else if (t
.bitfield
.disp16
1957 || t
.bitfield
.disp32
1958 || t
.bitfield
.disp32s
)
1965 fits_in_signed_byte (addressT num
)
1967 return num
+ 0x80 <= 0xff;
1971 fits_in_unsigned_byte (addressT num
)
1977 fits_in_unsigned_word (addressT num
)
1979 return num
<= 0xffff;
1983 fits_in_signed_word (addressT num
)
1985 return num
+ 0x8000 <= 0xffff;
1989 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1994 return num
+ 0x80000000 <= 0xffffffff;
1996 } /* fits_in_signed_long() */
1999 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2004 return num
<= 0xffffffff;
2006 } /* fits_in_unsigned_long() */
2009 fits_in_vec_disp8 (offsetT num
)
2011 int shift
= i
.memshift
;
2017 mask
= (1 << shift
) - 1;
2019 /* Return 0 if NUM isn't properly aligned. */
2023 /* Check if NUM will fit in 8bit after shift. */
2024 return fits_in_signed_byte (num
>> shift
);
2028 fits_in_imm4 (offsetT num
)
2030 return (num
& 0xf) == num
;
2033 static i386_operand_type
2034 smallest_imm_type (offsetT num
)
2036 i386_operand_type t
;
2038 operand_type_set (&t
, 0);
2039 t
.bitfield
.imm64
= 1;
2041 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2043 /* This code is disabled on the 486 because all the Imm1 forms
2044 in the opcode table are slower on the i486. They're the
2045 versions with the implicitly specified single-position
2046 displacement, which has another syntax if you really want to
2048 t
.bitfield
.imm1
= 1;
2049 t
.bitfield
.imm8
= 1;
2050 t
.bitfield
.imm8s
= 1;
2051 t
.bitfield
.imm16
= 1;
2052 t
.bitfield
.imm32
= 1;
2053 t
.bitfield
.imm32s
= 1;
2055 else if (fits_in_signed_byte (num
))
2057 t
.bitfield
.imm8
= 1;
2058 t
.bitfield
.imm8s
= 1;
2059 t
.bitfield
.imm16
= 1;
2060 t
.bitfield
.imm32
= 1;
2061 t
.bitfield
.imm32s
= 1;
2063 else if (fits_in_unsigned_byte (num
))
2065 t
.bitfield
.imm8
= 1;
2066 t
.bitfield
.imm16
= 1;
2067 t
.bitfield
.imm32
= 1;
2068 t
.bitfield
.imm32s
= 1;
2070 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2072 t
.bitfield
.imm16
= 1;
2073 t
.bitfield
.imm32
= 1;
2074 t
.bitfield
.imm32s
= 1;
2076 else if (fits_in_signed_long (num
))
2078 t
.bitfield
.imm32
= 1;
2079 t
.bitfield
.imm32s
= 1;
2081 else if (fits_in_unsigned_long (num
))
2082 t
.bitfield
.imm32
= 1;
2088 offset_in_range (offsetT val
, int size
)
2094 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2095 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2096 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2098 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2104 /* If BFD64, sign extend val for 32bit address mode. */
2105 if (flag_code
!= CODE_64BIT
2106 || i
.prefix
[ADDR_PREFIX
])
2107 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2108 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2111 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2113 char buf1
[40], buf2
[40];
2115 sprint_value (buf1
, val
);
2116 sprint_value (buf2
, val
& mask
);
2117 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2131 a. PREFIX_EXIST if attempting to add a prefix where one from the
2132 same class already exists.
2133 b. PREFIX_LOCK if lock prefix is added.
2134 c. PREFIX_REP if rep/repne prefix is added.
2135 d. PREFIX_OTHER if other prefix is added.
2138 static enum PREFIX_GROUP
2139 add_prefix (unsigned int prefix
)
2141 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2144 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2145 && flag_code
== CODE_64BIT
)
2147 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2148 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2149 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2160 case CS_PREFIX_OPCODE
:
2161 case DS_PREFIX_OPCODE
:
2162 case ES_PREFIX_OPCODE
:
2163 case FS_PREFIX_OPCODE
:
2164 case GS_PREFIX_OPCODE
:
2165 case SS_PREFIX_OPCODE
:
2169 case REPNE_PREFIX_OPCODE
:
2170 case REPE_PREFIX_OPCODE
:
2175 case LOCK_PREFIX_OPCODE
:
2184 case ADDR_PREFIX_OPCODE
:
2188 case DATA_PREFIX_OPCODE
:
2192 if (i
.prefix
[q
] != 0)
2200 i
.prefix
[q
] |= prefix
;
2203 as_bad (_("same type of prefix used twice"));
2209 update_code_flag (int value
, int check
)
2211 PRINTF_LIKE ((*as_error
));
2213 flag_code
= (enum flag_code
) value
;
2214 if (flag_code
== CODE_64BIT
)
2216 cpu_arch_flags
.bitfield
.cpu64
= 1;
2217 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2221 cpu_arch_flags
.bitfield
.cpu64
= 0;
2222 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2224 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2227 as_error
= as_fatal
;
2230 (*as_error
) (_("64bit mode not supported on `%s'."),
2231 cpu_arch_name
? cpu_arch_name
: default_arch
);
2233 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2236 as_error
= as_fatal
;
2239 (*as_error
) (_("32bit mode not supported on `%s'."),
2240 cpu_arch_name
? cpu_arch_name
: default_arch
);
2242 stackop_size
= '\0';
2246 set_code_flag (int value
)
2248 update_code_flag (value
, 0);
2252 set_16bit_gcc_code_flag (int new_code_flag
)
2254 flag_code
= (enum flag_code
) new_code_flag
;
2255 if (flag_code
!= CODE_16BIT
)
2257 cpu_arch_flags
.bitfield
.cpu64
= 0;
2258 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2259 stackop_size
= LONG_MNEM_SUFFIX
;
2263 set_intel_syntax (int syntax_flag
)
2265 /* Find out if register prefixing is specified. */
2266 int ask_naked_reg
= 0;
2269 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2272 int e
= get_symbol_name (&string
);
2274 if (strcmp (string
, "prefix") == 0)
2276 else if (strcmp (string
, "noprefix") == 0)
2279 as_bad (_("bad argument to syntax directive."));
2280 (void) restore_line_pointer (e
);
2282 demand_empty_rest_of_line ();
2284 intel_syntax
= syntax_flag
;
2286 if (ask_naked_reg
== 0)
2287 allow_naked_reg
= (intel_syntax
2288 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2290 allow_naked_reg
= (ask_naked_reg
< 0);
2292 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2294 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2295 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2296 register_prefix
= allow_naked_reg
? "" : "%";
2300 set_intel_mnemonic (int mnemonic_flag
)
2302 intel_mnemonic
= mnemonic_flag
;
2306 set_allow_index_reg (int flag
)
2308 allow_index_reg
= flag
;
2312 set_check (int what
)
2314 enum check_kind
*kind
;
2319 kind
= &operand_check
;
2330 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2333 int e
= get_symbol_name (&string
);
2335 if (strcmp (string
, "none") == 0)
2337 else if (strcmp (string
, "warning") == 0)
2338 *kind
= check_warning
;
2339 else if (strcmp (string
, "error") == 0)
2340 *kind
= check_error
;
2342 as_bad (_("bad argument to %s_check directive."), str
);
2343 (void) restore_line_pointer (e
);
2346 as_bad (_("missing argument for %s_check directive"), str
);
2348 demand_empty_rest_of_line ();
2352 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2353 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2355 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2356 static const char *arch
;
2358 /* Intel LIOM is only supported on ELF. */
2364 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2365 use default_arch. */
2366 arch
= cpu_arch_name
;
2368 arch
= default_arch
;
2371 /* If we are targeting Intel MCU, we must enable it. */
2372 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2373 || new_flag
.bitfield
.cpuiamcu
)
2376 /* If we are targeting Intel L1OM, we must enable it. */
2377 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2378 || new_flag
.bitfield
.cpul1om
)
2381 /* If we are targeting Intel K1OM, we must enable it. */
2382 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2383 || new_flag
.bitfield
.cpuk1om
)
2386 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2391 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2395 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2398 int e
= get_symbol_name (&string
);
2400 i386_cpu_flags flags
;
2402 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2404 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2406 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2410 cpu_arch_name
= cpu_arch
[j
].name
;
2411 cpu_sub_arch_name
= NULL
;
2412 cpu_arch_flags
= cpu_arch
[j
].flags
;
2413 if (flag_code
== CODE_64BIT
)
2415 cpu_arch_flags
.bitfield
.cpu64
= 1;
2416 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2420 cpu_arch_flags
.bitfield
.cpu64
= 0;
2421 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2423 cpu_arch_isa
= cpu_arch
[j
].type
;
2424 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2425 if (!cpu_arch_tune_set
)
2427 cpu_arch_tune
= cpu_arch_isa
;
2428 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2433 flags
= cpu_flags_or (cpu_arch_flags
,
2436 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2438 if (cpu_sub_arch_name
)
2440 char *name
= cpu_sub_arch_name
;
2441 cpu_sub_arch_name
= concat (name
,
2443 (const char *) NULL
);
2447 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2448 cpu_arch_flags
= flags
;
2449 cpu_arch_isa_flags
= flags
;
2451 (void) restore_line_pointer (e
);
2452 demand_empty_rest_of_line ();
2457 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2459 /* Disable an ISA entension. */
2460 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2461 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2463 flags
= cpu_flags_and_not (cpu_arch_flags
,
2464 cpu_noarch
[j
].flags
);
2465 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2467 if (cpu_sub_arch_name
)
2469 char *name
= cpu_sub_arch_name
;
2470 cpu_sub_arch_name
= concat (name
, string
,
2471 (const char *) NULL
);
2475 cpu_sub_arch_name
= xstrdup (string
);
2476 cpu_arch_flags
= flags
;
2477 cpu_arch_isa_flags
= flags
;
2479 (void) restore_line_pointer (e
);
2480 demand_empty_rest_of_line ();
2484 j
= ARRAY_SIZE (cpu_arch
);
2487 if (j
>= ARRAY_SIZE (cpu_arch
))
2488 as_bad (_("no such architecture: `%s'"), string
);
2490 *input_line_pointer
= e
;
2493 as_bad (_("missing cpu architecture"));
2495 no_cond_jump_promotion
= 0;
2496 if (*input_line_pointer
== ','
2497 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2502 ++input_line_pointer
;
2503 e
= get_symbol_name (&string
);
2505 if (strcmp (string
, "nojumps") == 0)
2506 no_cond_jump_promotion
= 1;
2507 else if (strcmp (string
, "jumps") == 0)
2510 as_bad (_("no such architecture modifier: `%s'"), string
);
2512 (void) restore_line_pointer (e
);
2515 demand_empty_rest_of_line ();
2518 enum bfd_architecture
2521 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2523 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2524 || flag_code
!= CODE_64BIT
)
2525 as_fatal (_("Intel L1OM is 64bit ELF only"));
2526 return bfd_arch_l1om
;
2528 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2530 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2531 || flag_code
!= CODE_64BIT
)
2532 as_fatal (_("Intel K1OM is 64bit ELF only"));
2533 return bfd_arch_k1om
;
2535 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2537 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2538 || flag_code
== CODE_64BIT
)
2539 as_fatal (_("Intel MCU is 32bit ELF only"));
2540 return bfd_arch_iamcu
;
2543 return bfd_arch_i386
;
2549 if (!strncmp (default_arch
, "x86_64", 6))
2551 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2553 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2554 || default_arch
[6] != '\0')
2555 as_fatal (_("Intel L1OM is 64bit ELF only"));
2556 return bfd_mach_l1om
;
2558 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2560 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2561 || default_arch
[6] != '\0')
2562 as_fatal (_("Intel K1OM is 64bit ELF only"));
2563 return bfd_mach_k1om
;
2565 else if (default_arch
[6] == '\0')
2566 return bfd_mach_x86_64
;
2568 return bfd_mach_x64_32
;
2570 else if (!strcmp (default_arch
, "i386")
2571 || !strcmp (default_arch
, "iamcu"))
2573 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2575 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2576 as_fatal (_("Intel MCU is 32bit ELF only"));
2577 return bfd_mach_i386_iamcu
;
2580 return bfd_mach_i386_i386
;
2583 as_fatal (_("unknown architecture"));
2589 const char *hash_err
;
2591 /* Initialize op_hash hash table. */
2592 op_hash
= hash_new ();
2595 const insn_template
*optab
;
2596 templates
*core_optab
;
2598 /* Setup for loop. */
2600 core_optab
= XNEW (templates
);
2601 core_optab
->start
= optab
;
2606 if (optab
->name
== NULL
2607 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2609 /* different name --> ship out current template list;
2610 add to hash table; & begin anew. */
2611 core_optab
->end
= optab
;
2612 hash_err
= hash_insert (op_hash
,
2614 (void *) core_optab
);
2617 as_fatal (_("can't hash %s: %s"),
2621 if (optab
->name
== NULL
)
2623 core_optab
= XNEW (templates
);
2624 core_optab
->start
= optab
;
2629 /* Initialize reg_hash hash table. */
2630 reg_hash
= hash_new ();
2632 const reg_entry
*regtab
;
2633 unsigned int regtab_size
= i386_regtab_size
;
2635 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2637 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2639 as_fatal (_("can't hash %s: %s"),
2645 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2650 for (c
= 0; c
< 256; c
++)
2655 mnemonic_chars
[c
] = c
;
2656 register_chars
[c
] = c
;
2657 operand_chars
[c
] = c
;
2659 else if (ISLOWER (c
))
2661 mnemonic_chars
[c
] = c
;
2662 register_chars
[c
] = c
;
2663 operand_chars
[c
] = c
;
2665 else if (ISUPPER (c
))
2667 mnemonic_chars
[c
] = TOLOWER (c
);
2668 register_chars
[c
] = mnemonic_chars
[c
];
2669 operand_chars
[c
] = c
;
2671 else if (c
== '{' || c
== '}')
2672 operand_chars
[c
] = c
;
2674 if (ISALPHA (c
) || ISDIGIT (c
))
2675 identifier_chars
[c
] = c
;
2678 identifier_chars
[c
] = c
;
2679 operand_chars
[c
] = c
;
2684 identifier_chars
['@'] = '@';
2687 identifier_chars
['?'] = '?';
2688 operand_chars
['?'] = '?';
2690 digit_chars
['-'] = '-';
2691 mnemonic_chars
['_'] = '_';
2692 mnemonic_chars
['-'] = '-';
2693 mnemonic_chars
['.'] = '.';
2694 identifier_chars
['_'] = '_';
2695 identifier_chars
['.'] = '.';
2697 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2698 operand_chars
[(unsigned char) *p
] = *p
;
2701 if (flag_code
== CODE_64BIT
)
2703 #if defined (OBJ_COFF) && defined (TE_PE)
2704 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2707 x86_dwarf2_return_column
= 16;
2709 x86_cie_data_alignment
= -8;
2713 x86_dwarf2_return_column
= 8;
2714 x86_cie_data_alignment
= -4;
2719 i386_print_statistics (FILE *file
)
2721 hash_print_statistics (file
, "i386 opcode", op_hash
);
2722 hash_print_statistics (file
, "i386 register", reg_hash
);
2727 /* Debugging routines for md_assemble. */
2728 static void pte (insn_template
*);
2729 static void pt (i386_operand_type
);
2730 static void pe (expressionS
*);
2731 static void ps (symbolS
*);
2734 pi (char *line
, i386_insn
*x
)
2738 fprintf (stdout
, "%s: template ", line
);
2740 fprintf (stdout
, " address: base %s index %s scale %x\n",
2741 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2742 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2743 x
->log2_scale_factor
);
2744 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2745 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2746 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2747 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2748 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2749 (x
->rex
& REX_W
) != 0,
2750 (x
->rex
& REX_R
) != 0,
2751 (x
->rex
& REX_X
) != 0,
2752 (x
->rex
& REX_B
) != 0);
2753 for (j
= 0; j
< x
->operands
; j
++)
2755 fprintf (stdout
, " #%d: ", j
+ 1);
2757 fprintf (stdout
, "\n");
2758 if (x
->types
[j
].bitfield
.reg8
2759 || x
->types
[j
].bitfield
.reg16
2760 || x
->types
[j
].bitfield
.reg32
2761 || x
->types
[j
].bitfield
.reg64
2762 || x
->types
[j
].bitfield
.regmmx
2763 || x
->types
[j
].bitfield
.regxmm
2764 || x
->types
[j
].bitfield
.regymm
2765 || x
->types
[j
].bitfield
.regzmm
2766 || x
->types
[j
].bitfield
.sreg2
2767 || x
->types
[j
].bitfield
.sreg3
2768 || x
->types
[j
].bitfield
.control
2769 || x
->types
[j
].bitfield
.debug
2770 || x
->types
[j
].bitfield
.test
)
2771 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2772 if (operand_type_check (x
->types
[j
], imm
))
2774 if (operand_type_check (x
->types
[j
], disp
))
2775 pe (x
->op
[j
].disps
);
2780 pte (insn_template
*t
)
2783 fprintf (stdout
, " %d operands ", t
->operands
);
2784 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2785 if (t
->extension_opcode
!= None
)
2786 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2787 if (t
->opcode_modifier
.d
)
2788 fprintf (stdout
, "D");
2789 if (t
->opcode_modifier
.w
)
2790 fprintf (stdout
, "W");
2791 fprintf (stdout
, "\n");
2792 for (j
= 0; j
< t
->operands
; j
++)
2794 fprintf (stdout
, " #%d type ", j
+ 1);
2795 pt (t
->operand_types
[j
]);
2796 fprintf (stdout
, "\n");
2803 fprintf (stdout
, " operation %d\n", e
->X_op
);
2804 fprintf (stdout
, " add_number %ld (%lx)\n",
2805 (long) e
->X_add_number
, (long) e
->X_add_number
);
2806 if (e
->X_add_symbol
)
2808 fprintf (stdout
, " add_symbol ");
2809 ps (e
->X_add_symbol
);
2810 fprintf (stdout
, "\n");
2814 fprintf (stdout
, " op_symbol ");
2815 ps (e
->X_op_symbol
);
2816 fprintf (stdout
, "\n");
2823 fprintf (stdout
, "%s type %s%s",
2825 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2826 segment_name (S_GET_SEGMENT (s
)));
2829 static struct type_name
2831 i386_operand_type mask
;
2834 const type_names
[] =
2836 { OPERAND_TYPE_REG8
, "r8" },
2837 { OPERAND_TYPE_REG16
, "r16" },
2838 { OPERAND_TYPE_REG32
, "r32" },
2839 { OPERAND_TYPE_REG64
, "r64" },
2840 { OPERAND_TYPE_IMM8
, "i8" },
2841 { OPERAND_TYPE_IMM8
, "i8s" },
2842 { OPERAND_TYPE_IMM16
, "i16" },
2843 { OPERAND_TYPE_IMM32
, "i32" },
2844 { OPERAND_TYPE_IMM32S
, "i32s" },
2845 { OPERAND_TYPE_IMM64
, "i64" },
2846 { OPERAND_TYPE_IMM1
, "i1" },
2847 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2848 { OPERAND_TYPE_DISP8
, "d8" },
2849 { OPERAND_TYPE_DISP16
, "d16" },
2850 { OPERAND_TYPE_DISP32
, "d32" },
2851 { OPERAND_TYPE_DISP32S
, "d32s" },
2852 { OPERAND_TYPE_DISP64
, "d64" },
2853 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2854 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2855 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2856 { OPERAND_TYPE_CONTROL
, "control reg" },
2857 { OPERAND_TYPE_TEST
, "test reg" },
2858 { OPERAND_TYPE_DEBUG
, "debug reg" },
2859 { OPERAND_TYPE_FLOATREG
, "FReg" },
2860 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2861 { OPERAND_TYPE_SREG2
, "SReg2" },
2862 { OPERAND_TYPE_SREG3
, "SReg3" },
2863 { OPERAND_TYPE_ACC
, "Acc" },
2864 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2865 { OPERAND_TYPE_REGMMX
, "rMMX" },
2866 { OPERAND_TYPE_REGXMM
, "rXMM" },
2867 { OPERAND_TYPE_REGYMM
, "rYMM" },
2868 { OPERAND_TYPE_REGZMM
, "rZMM" },
2869 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2870 { OPERAND_TYPE_ESSEG
, "es" },
2874 pt (i386_operand_type t
)
2877 i386_operand_type a
;
2879 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2881 a
= operand_type_and (t
, type_names
[j
].mask
);
2882 if (!operand_type_all_zero (&a
))
2883 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2888 #endif /* DEBUG386 */
2890 static bfd_reloc_code_real_type
2891 reloc (unsigned int size
,
2894 bfd_reloc_code_real_type other
)
2896 if (other
!= NO_RELOC
)
2898 reloc_howto_type
*rel
;
2903 case BFD_RELOC_X86_64_GOT32
:
2904 return BFD_RELOC_X86_64_GOT64
;
2906 case BFD_RELOC_X86_64_GOTPLT64
:
2907 return BFD_RELOC_X86_64_GOTPLT64
;
2909 case BFD_RELOC_X86_64_PLTOFF64
:
2910 return BFD_RELOC_X86_64_PLTOFF64
;
2912 case BFD_RELOC_X86_64_GOTPC32
:
2913 other
= BFD_RELOC_X86_64_GOTPC64
;
2915 case BFD_RELOC_X86_64_GOTPCREL
:
2916 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2918 case BFD_RELOC_X86_64_TPOFF32
:
2919 other
= BFD_RELOC_X86_64_TPOFF64
;
2921 case BFD_RELOC_X86_64_DTPOFF32
:
2922 other
= BFD_RELOC_X86_64_DTPOFF64
;
2928 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2929 if (other
== BFD_RELOC_SIZE32
)
2932 other
= BFD_RELOC_SIZE64
;
2935 as_bad (_("there are no pc-relative size relocations"));
2941 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2942 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2945 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2947 as_bad (_("unknown relocation (%u)"), other
);
2948 else if (size
!= bfd_get_reloc_size (rel
))
2949 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2950 bfd_get_reloc_size (rel
),
2952 else if (pcrel
&& !rel
->pc_relative
)
2953 as_bad (_("non-pc-relative relocation for pc-relative field"));
2954 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2956 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2958 as_bad (_("relocated field and relocation type differ in signedness"));
2967 as_bad (_("there are no unsigned pc-relative relocations"));
2970 case 1: return BFD_RELOC_8_PCREL
;
2971 case 2: return BFD_RELOC_16_PCREL
;
2972 case 4: return BFD_RELOC_32_PCREL
;
2973 case 8: return BFD_RELOC_64_PCREL
;
2975 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2982 case 4: return BFD_RELOC_X86_64_32S
;
2987 case 1: return BFD_RELOC_8
;
2988 case 2: return BFD_RELOC_16
;
2989 case 4: return BFD_RELOC_32
;
2990 case 8: return BFD_RELOC_64
;
2992 as_bad (_("cannot do %s %u byte relocation"),
2993 sign
> 0 ? "signed" : "unsigned", size
);
2999 /* Here we decide which fixups can be adjusted to make them relative to
3000 the beginning of the section instead of the symbol. Basically we need
3001 to make sure that the dynamic relocations are done correctly, so in
3002 some cases we force the original symbol to be used. */
3005 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3011 /* Don't adjust pc-relative references to merge sections in 64-bit
3013 if (use_rela_relocations
3014 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3018 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3019 and changed later by validate_fix. */
3020 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3021 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3024 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3025 for size relocations. */
3026 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3027 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3028 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3029 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3030 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3031 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3032 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3034 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3035 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3036 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3037 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3038 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3040 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3056 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3057 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3058 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3065 intel_float_operand (const char *mnemonic
)
3067 /* Note that the value returned is meaningful only for opcodes with (memory)
3068 operands, hence the code here is free to improperly handle opcodes that
3069 have no operands (for better performance and smaller code). */
3071 if (mnemonic
[0] != 'f')
3072 return 0; /* non-math */
3074 switch (mnemonic
[1])
3076 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3077 the fs segment override prefix not currently handled because no
3078 call path can make opcodes without operands get here */
3080 return 2 /* integer op */;
3082 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3083 return 3; /* fldcw/fldenv */
3086 if (mnemonic
[2] != 'o' /* fnop */)
3087 return 3; /* non-waiting control op */
3090 if (mnemonic
[2] == 's')
3091 return 3; /* frstor/frstpm */
3094 if (mnemonic
[2] == 'a')
3095 return 3; /* fsave */
3096 if (mnemonic
[2] == 't')
3098 switch (mnemonic
[3])
3100 case 'c': /* fstcw */
3101 case 'd': /* fstdw */
3102 case 'e': /* fstenv */
3103 case 's': /* fsts[gw] */
3109 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3110 return 0; /* fxsave/fxrstor are not really math ops */
3117 /* Build the VEX prefix. */
3120 build_vex_prefix (const insn_template
*t
)
3122 unsigned int register_specifier
;
3123 unsigned int implied_prefix
;
3124 unsigned int vector_length
;
3126 /* Check register specifier. */
3127 if (i
.vex
.register_specifier
)
3129 register_specifier
=
3130 ~register_number (i
.vex
.register_specifier
) & 0xf;
3131 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3134 register_specifier
= 0xf;
3136 /* Use 2-byte VEX prefix by swappping destination and source
3139 && i
.operands
== i
.reg_operands
3140 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3141 && i
.tm
.opcode_modifier
.s
3144 unsigned int xchg
= i
.operands
- 1;
3145 union i386_op temp_op
;
3146 i386_operand_type temp_type
;
3148 temp_type
= i
.types
[xchg
];
3149 i
.types
[xchg
] = i
.types
[0];
3150 i
.types
[0] = temp_type
;
3151 temp_op
= i
.op
[xchg
];
3152 i
.op
[xchg
] = i
.op
[0];
3155 gas_assert (i
.rm
.mode
== 3);
3159 i
.rm
.regmem
= i
.rm
.reg
;
3162 /* Use the next insn. */
3166 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3167 vector_length
= avxscalar
;
3169 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3171 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3176 case DATA_PREFIX_OPCODE
:
3179 case REPE_PREFIX_OPCODE
:
3182 case REPNE_PREFIX_OPCODE
:
3189 /* Use 2-byte VEX prefix if possible. */
3190 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3191 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3192 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3194 /* 2-byte VEX prefix. */
3198 i
.vex
.bytes
[0] = 0xc5;
3200 /* Check the REX.R bit. */
3201 r
= (i
.rex
& REX_R
) ? 0 : 1;
3202 i
.vex
.bytes
[1] = (r
<< 7
3203 | register_specifier
<< 3
3204 | vector_length
<< 2
3209 /* 3-byte VEX prefix. */
3214 switch (i
.tm
.opcode_modifier
.vexopcode
)
3218 i
.vex
.bytes
[0] = 0xc4;
3222 i
.vex
.bytes
[0] = 0xc4;
3226 i
.vex
.bytes
[0] = 0xc4;
3230 i
.vex
.bytes
[0] = 0x8f;
3234 i
.vex
.bytes
[0] = 0x8f;
3238 i
.vex
.bytes
[0] = 0x8f;
3244 /* The high 3 bits of the second VEX byte are 1's compliment
3245 of RXB bits from REX. */
3246 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3248 /* Check the REX.W bit. */
3249 w
= (i
.rex
& REX_W
) ? 1 : 0;
3250 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3253 i
.vex
.bytes
[2] = (w
<< 7
3254 | register_specifier
<< 3
3255 | vector_length
<< 2
3260 /* Build the EVEX prefix. */
3263 build_evex_prefix (void)
3265 unsigned int register_specifier
;
3266 unsigned int implied_prefix
;
3268 rex_byte vrex_used
= 0;
3270 /* Check register specifier. */
3271 if (i
.vex
.register_specifier
)
3273 gas_assert ((i
.vrex
& REX_X
) == 0);
3275 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3276 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3277 register_specifier
+= 8;
3278 /* The upper 16 registers are encoded in the fourth byte of the
3280 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3281 i
.vex
.bytes
[3] = 0x8;
3282 register_specifier
= ~register_specifier
& 0xf;
3286 register_specifier
= 0xf;
3288 /* Encode upper 16 vector index register in the fourth byte of
3290 if (!(i
.vrex
& REX_X
))
3291 i
.vex
.bytes
[3] = 0x8;
3296 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3301 case DATA_PREFIX_OPCODE
:
3304 case REPE_PREFIX_OPCODE
:
3307 case REPNE_PREFIX_OPCODE
:
3314 /* 4 byte EVEX prefix. */
3316 i
.vex
.bytes
[0] = 0x62;
3319 switch (i
.tm
.opcode_modifier
.vexopcode
)
3335 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3337 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3339 /* The fifth bit of the second EVEX byte is 1's compliment of the
3340 REX_R bit in VREX. */
3341 if (!(i
.vrex
& REX_R
))
3342 i
.vex
.bytes
[1] |= 0x10;
3346 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3348 /* When all operands are registers, the REX_X bit in REX is not
3349 used. We reuse it to encode the upper 16 registers, which is
3350 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3351 as 1's compliment. */
3352 if ((i
.vrex
& REX_B
))
3355 i
.vex
.bytes
[1] &= ~0x40;
3359 /* EVEX instructions shouldn't need the REX prefix. */
3360 i
.vrex
&= ~vrex_used
;
3361 gas_assert (i
.vrex
== 0);
3363 /* Check the REX.W bit. */
3364 w
= (i
.rex
& REX_W
) ? 1 : 0;
3365 if (i
.tm
.opcode_modifier
.vexw
)
3367 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3370 /* If w is not set it means we are dealing with WIG instruction. */
3373 if (evexwig
== evexw1
)
3377 /* Encode the U bit. */
3378 implied_prefix
|= 0x4;
3380 /* The third byte of the EVEX prefix. */
3381 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3383 /* The fourth byte of the EVEX prefix. */
3384 /* The zeroing-masking bit. */
3385 if (i
.mask
&& i
.mask
->zeroing
)
3386 i
.vex
.bytes
[3] |= 0x80;
3388 /* Don't always set the broadcast bit if there is no RC. */
3391 /* Encode the vector length. */
3392 unsigned int vec_length
;
3394 switch (i
.tm
.opcode_modifier
.evex
)
3396 case EVEXLIG
: /* LL' is ignored */
3397 vec_length
= evexlig
<< 5;
3400 vec_length
= 0 << 5;
3403 vec_length
= 1 << 5;
3406 vec_length
= 2 << 5;
3412 i
.vex
.bytes
[3] |= vec_length
;
3413 /* Encode the broadcast bit. */
3415 i
.vex
.bytes
[3] |= 0x10;
3419 if (i
.rounding
->type
!= saeonly
)
3420 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3422 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3425 if (i
.mask
&& i
.mask
->mask
)
3426 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3430 process_immext (void)
3434 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3437 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3438 with an opcode suffix which is coded in the same place as an
3439 8-bit immediate field would be.
3440 Here we check those operands and remove them afterwards. */
3443 for (x
= 0; x
< i
.operands
; x
++)
3444 if (register_number (i
.op
[x
].regs
) != x
)
3445 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3446 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3452 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3454 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3455 suffix which is coded in the same place as an 8-bit immediate
3457 Here we check those operands and remove them afterwards. */
3460 if (i
.operands
!= 3)
3463 for (x
= 0; x
< 2; x
++)
3464 if (register_number (i
.op
[x
].regs
) != x
)
3465 goto bad_register_operand
;
3467 /* Check for third operand for mwaitx/monitorx insn. */
3468 if (register_number (i
.op
[x
].regs
)
3469 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3471 bad_register_operand
:
3472 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3473 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3480 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3481 which is coded in the same place as an 8-bit immediate field
3482 would be. Here we fake an 8-bit immediate operand from the
3483 opcode suffix stored in tm.extension_opcode.
3485 AVX instructions also use this encoding, for some of
3486 3 argument instructions. */
3488 gas_assert (i
.imm_operands
<= 1
3490 || ((i
.tm
.opcode_modifier
.vex
3491 || i
.tm
.opcode_modifier
.evex
)
3492 && i
.operands
<= 4)));
3494 exp
= &im_expressions
[i
.imm_operands
++];
3495 i
.op
[i
.operands
].imms
= exp
;
3496 i
.types
[i
.operands
] = imm8
;
3498 exp
->X_op
= O_constant
;
3499 exp
->X_add_number
= i
.tm
.extension_opcode
;
3500 i
.tm
.extension_opcode
= None
;
3507 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3512 as_bad (_("invalid instruction `%s' after `%s'"),
3513 i
.tm
.name
, i
.hle_prefix
);
3516 if (i
.prefix
[LOCK_PREFIX
])
3518 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3522 case HLEPrefixRelease
:
3523 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3525 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3529 if (i
.mem_operands
== 0
3530 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3532 as_bad (_("memory destination needed for instruction `%s'"
3533 " after `xrelease'"), i
.tm
.name
);
3540 /* This is the guts of the machine-dependent assembler. LINE points to a
3541 machine dependent instruction. This function is supposed to emit
3542 the frags/bytes it assembles to. */
3545 md_assemble (char *line
)
3548 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3549 const insn_template
*t
;
3551 /* Initialize globals. */
3552 memset (&i
, '\0', sizeof (i
));
3553 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3554 i
.reloc
[j
] = NO_RELOC
;
3555 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3556 memset (im_expressions
, '\0', sizeof (im_expressions
));
3557 save_stack_p
= save_stack
;
3559 /* First parse an instruction mnemonic & call i386_operand for the operands.
3560 We assume that the scrubber has arranged it so that line[0] is the valid
3561 start of a (possibly prefixed) mnemonic. */
3563 line
= parse_insn (line
, mnemonic
);
3566 mnem_suffix
= i
.suffix
;
3568 line
= parse_operands (line
, mnemonic
);
3570 xfree (i
.memop1_string
);
3571 i
.memop1_string
= NULL
;
3575 /* Now we've parsed the mnemonic into a set of templates, and have the
3576 operands at hand. */
3578 /* All intel opcodes have reversed operands except for "bound" and
3579 "enter". We also don't reverse intersegment "jmp" and "call"
3580 instructions with 2 immediate operands so that the immediate segment
3581 precedes the offset, as it does when in AT&T mode. */
3584 && (strcmp (mnemonic
, "bound") != 0)
3585 && (strcmp (mnemonic
, "invlpga") != 0)
3586 && !(operand_type_check (i
.types
[0], imm
)
3587 && operand_type_check (i
.types
[1], imm
)))
3590 /* The order of the immediates should be reversed
3591 for 2 immediates extrq and insertq instructions */
3592 if (i
.imm_operands
== 2
3593 && (strcmp (mnemonic
, "extrq") == 0
3594 || strcmp (mnemonic
, "insertq") == 0))
3595 swap_2_operands (0, 1);
3600 /* Don't optimize displacement for movabs since it only takes 64bit
3603 && i
.disp_encoding
!= disp_encoding_32bit
3604 && (flag_code
!= CODE_64BIT
3605 || strcmp (mnemonic
, "movabs") != 0))
3608 /* Next, we find a template that matches the given insn,
3609 making sure the overlap of the given operands types is consistent
3610 with the template operand types. */
3612 if (!(t
= match_template (mnem_suffix
)))
3615 if (sse_check
!= check_none
3616 && !i
.tm
.opcode_modifier
.noavx
3617 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3618 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3619 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3620 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3621 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3622 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3624 (sse_check
== check_warning
3626 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3629 /* Zap movzx and movsx suffix. The suffix has been set from
3630 "word ptr" or "byte ptr" on the source operand in Intel syntax
3631 or extracted from mnemonic in AT&T syntax. But we'll use
3632 the destination register to choose the suffix for encoding. */
3633 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3635 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3636 there is no suffix, the default will be byte extension. */
3637 if (i
.reg_operands
!= 2
3640 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3645 if (i
.tm
.opcode_modifier
.fwait
)
3646 if (!add_prefix (FWAIT_OPCODE
))
3649 /* Check if REP prefix is OK. */
3650 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3652 as_bad (_("invalid instruction `%s' after `%s'"),
3653 i
.tm
.name
, i
.rep_prefix
);
3657 /* Check for lock without a lockable instruction. Destination operand
3658 must be memory unless it is xchg (0x86). */
3659 if (i
.prefix
[LOCK_PREFIX
]
3660 && (!i
.tm
.opcode_modifier
.islockable
3661 || i
.mem_operands
== 0
3662 || (i
.tm
.base_opcode
!= 0x86
3663 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3665 as_bad (_("expecting lockable instruction after `lock'"));
3669 /* Check if HLE prefix is OK. */
3670 if (i
.hle_prefix
&& !check_hle ())
3673 /* Check BND prefix. */
3674 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3675 as_bad (_("expecting valid branch instruction after `bnd'"));
3677 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3679 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3680 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3681 else if (flag_code
!= CODE_16BIT
3682 ? i
.prefix
[ADDR_PREFIX
]
3683 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3684 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3687 /* Insert BND prefix. */
3689 && i
.tm
.opcode_modifier
.bndprefixok
3690 && !i
.prefix
[BND_PREFIX
])
3691 add_prefix (BND_PREFIX_OPCODE
);
3693 /* Check string instruction segment overrides. */
3694 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3696 if (!check_string ())
3698 i
.disp_operands
= 0;
3701 if (!process_suffix ())
3704 /* Update operand types. */
3705 for (j
= 0; j
< i
.operands
; j
++)
3706 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3708 /* Make still unresolved immediate matches conform to size of immediate
3709 given in i.suffix. */
3710 if (!finalize_imm ())
3713 if (i
.types
[0].bitfield
.imm1
)
3714 i
.imm_operands
= 0; /* kludge for shift insns. */
3716 /* We only need to check those implicit registers for instructions
3717 with 3 operands or less. */
3718 if (i
.operands
<= 3)
3719 for (j
= 0; j
< i
.operands
; j
++)
3720 if (i
.types
[j
].bitfield
.inoutportreg
3721 || i
.types
[j
].bitfield
.shiftcount
3722 || i
.types
[j
].bitfield
.acc
3723 || i
.types
[j
].bitfield
.floatacc
)
3726 /* ImmExt should be processed after SSE2AVX. */
3727 if (!i
.tm
.opcode_modifier
.sse2avx
3728 && i
.tm
.opcode_modifier
.immext
)
3731 /* For insns with operands there are more diddles to do to the opcode. */
3734 if (!process_operands ())
3737 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3739 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3740 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3743 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3745 if (flag_code
== CODE_16BIT
)
3747 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3752 if (i
.tm
.opcode_modifier
.vex
)
3753 build_vex_prefix (t
);
3755 build_evex_prefix ();
3758 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3759 instructions may define INT_OPCODE as well, so avoid this corner
3760 case for those instructions that use MODRM. */
3761 if (i
.tm
.base_opcode
== INT_OPCODE
3762 && !i
.tm
.opcode_modifier
.modrm
3763 && i
.op
[0].imms
->X_add_number
== 3)
3765 i
.tm
.base_opcode
= INT3_OPCODE
;
3769 if ((i
.tm
.opcode_modifier
.jump
3770 || i
.tm
.opcode_modifier
.jumpbyte
3771 || i
.tm
.opcode_modifier
.jumpdword
)
3772 && i
.op
[0].disps
->X_op
== O_constant
)
3774 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3775 the absolute address given by the constant. Since ix86 jumps and
3776 calls are pc relative, we need to generate a reloc. */
3777 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3778 i
.op
[0].disps
->X_op
= O_symbol
;
3781 if (i
.tm
.opcode_modifier
.rex64
)
3784 /* For 8 bit registers we need an empty rex prefix. Also if the
3785 instruction already has a prefix, we need to convert old
3786 registers to new ones. */
3788 if ((i
.types
[0].bitfield
.reg8
3789 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3790 || (i
.types
[1].bitfield
.reg8
3791 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3792 || ((i
.types
[0].bitfield
.reg8
3793 || i
.types
[1].bitfield
.reg8
)
3798 i
.rex
|= REX_OPCODE
;
3799 for (x
= 0; x
< 2; x
++)
3801 /* Look for 8 bit operand that uses old registers. */
3802 if (i
.types
[x
].bitfield
.reg8
3803 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3805 /* In case it is "hi" register, give up. */
3806 if (i
.op
[x
].regs
->reg_num
> 3)
3807 as_bad (_("can't encode register '%s%s' in an "
3808 "instruction requiring REX prefix."),
3809 register_prefix
, i
.op
[x
].regs
->reg_name
);
3811 /* Otherwise it is equivalent to the extended register.
3812 Since the encoding doesn't change this is merely
3813 cosmetic cleanup for debug output. */
3815 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3821 add_prefix (REX_OPCODE
| i
.rex
);
3823 /* We are ready to output the insn. */
3828 parse_insn (char *line
, char *mnemonic
)
3831 char *token_start
= l
;
3834 const insn_template
*t
;
3840 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3845 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3847 as_bad (_("no such instruction: `%s'"), token_start
);
3852 if (!is_space_char (*l
)
3853 && *l
!= END_OF_INSN
3855 || (*l
!= PREFIX_SEPARATOR
3858 as_bad (_("invalid character %s in mnemonic"),
3859 output_invalid (*l
));
3862 if (token_start
== l
)
3864 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3865 as_bad (_("expecting prefix; got nothing"));
3867 as_bad (_("expecting mnemonic; got nothing"));
3871 /* Look up instruction (or prefix) via hash table. */
3872 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3874 if (*l
!= END_OF_INSN
3875 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3876 && current_templates
3877 && current_templates
->start
->opcode_modifier
.isprefix
)
3879 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3881 as_bad ((flag_code
!= CODE_64BIT
3882 ? _("`%s' is only supported in 64-bit mode")
3883 : _("`%s' is not supported in 64-bit mode")),
3884 current_templates
->start
->name
);
3887 /* If we are in 16-bit mode, do not allow addr16 or data16.
3888 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3889 if ((current_templates
->start
->opcode_modifier
.size16
3890 || current_templates
->start
->opcode_modifier
.size32
)
3891 && flag_code
!= CODE_64BIT
3892 && (current_templates
->start
->opcode_modifier
.size32
3893 ^ (flag_code
== CODE_16BIT
)))
3895 as_bad (_("redundant %s prefix"),
3896 current_templates
->start
->name
);
3899 /* Add prefix, checking for repeated prefixes. */
3900 switch (add_prefix (current_templates
->start
->base_opcode
))
3905 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3906 i
.hle_prefix
= current_templates
->start
->name
;
3907 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3908 i
.bnd_prefix
= current_templates
->start
->name
;
3910 i
.rep_prefix
= current_templates
->start
->name
;
3915 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3922 if (!current_templates
)
3924 /* Check if we should swap operand or force 32bit displacement in
3926 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3928 else if (mnem_p
- 3 == dot_p
3931 i
.disp_encoding
= disp_encoding_8bit
;
3932 else if (mnem_p
- 4 == dot_p
3936 i
.disp_encoding
= disp_encoding_32bit
;
3941 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3944 if (!current_templates
)
3947 /* See if we can get a match by trimming off a suffix. */
3950 case WORD_MNEM_SUFFIX
:
3951 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3952 i
.suffix
= SHORT_MNEM_SUFFIX
;
3955 case BYTE_MNEM_SUFFIX
:
3956 case QWORD_MNEM_SUFFIX
:
3957 i
.suffix
= mnem_p
[-1];
3959 current_templates
= (const templates
*) hash_find (op_hash
,
3962 case SHORT_MNEM_SUFFIX
:
3963 case LONG_MNEM_SUFFIX
:
3966 i
.suffix
= mnem_p
[-1];
3968 current_templates
= (const templates
*) hash_find (op_hash
,
3977 if (intel_float_operand (mnemonic
) == 1)
3978 i
.suffix
= SHORT_MNEM_SUFFIX
;
3980 i
.suffix
= LONG_MNEM_SUFFIX
;
3982 current_templates
= (const templates
*) hash_find (op_hash
,
3987 if (!current_templates
)
3989 as_bad (_("no such instruction: `%s'"), token_start
);
3994 if (current_templates
->start
->opcode_modifier
.jump
3995 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3997 /* Check for a branch hint. We allow ",pt" and ",pn" for
3998 predict taken and predict not taken respectively.
3999 I'm not sure that branch hints actually do anything on loop
4000 and jcxz insns (JumpByte) for current Pentium4 chips. They
4001 may work in the future and it doesn't hurt to accept them
4003 if (l
[0] == ',' && l
[1] == 'p')
4007 if (!add_prefix (DS_PREFIX_OPCODE
))
4011 else if (l
[2] == 'n')
4013 if (!add_prefix (CS_PREFIX_OPCODE
))
4019 /* Any other comma loses. */
4022 as_bad (_("invalid character %s in mnemonic"),
4023 output_invalid (*l
));
4027 /* Check if instruction is supported on specified architecture. */
4029 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4031 supported
|= cpu_flags_match (t
);
4032 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4036 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4038 as_bad (flag_code
== CODE_64BIT
4039 ? _("`%s' is not supported in 64-bit mode")
4040 : _("`%s' is only supported in 64-bit mode"),
4041 current_templates
->start
->name
);
4044 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4046 as_bad (_("`%s' is not supported on `%s%s'"),
4047 current_templates
->start
->name
,
4048 cpu_arch_name
? cpu_arch_name
: default_arch
,
4049 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4054 if (!cpu_arch_flags
.bitfield
.cpui386
4055 && (flag_code
!= CODE_16BIT
))
4057 as_warn (_("use .code16 to ensure correct addressing mode"));
4064 parse_operands (char *l
, const char *mnemonic
)
4068 /* 1 if operand is pending after ','. */
4069 unsigned int expecting_operand
= 0;
4071 /* Non-zero if operand parens not balanced. */
4072 unsigned int paren_not_balanced
;
4074 while (*l
!= END_OF_INSN
)
4076 /* Skip optional white space before operand. */
4077 if (is_space_char (*l
))
4079 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4081 as_bad (_("invalid character %s before operand %d"),
4082 output_invalid (*l
),
4086 token_start
= l
; /* After white space. */
4087 paren_not_balanced
= 0;
4088 while (paren_not_balanced
|| *l
!= ',')
4090 if (*l
== END_OF_INSN
)
4092 if (paren_not_balanced
)
4095 as_bad (_("unbalanced parenthesis in operand %d."),
4098 as_bad (_("unbalanced brackets in operand %d."),
4103 break; /* we are done */
4105 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4107 as_bad (_("invalid character %s in operand %d"),
4108 output_invalid (*l
),
4115 ++paren_not_balanced
;
4117 --paren_not_balanced
;
4122 ++paren_not_balanced
;
4124 --paren_not_balanced
;
4128 if (l
!= token_start
)
4129 { /* Yes, we've read in another operand. */
4130 unsigned int operand_ok
;
4131 this_operand
= i
.operands
++;
4132 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4133 if (i
.operands
> MAX_OPERANDS
)
4135 as_bad (_("spurious operands; (%d operands/instruction max)"),
4139 /* Now parse operand adding info to 'i' as we go along. */
4140 END_STRING_AND_SAVE (l
);
4144 i386_intel_operand (token_start
,
4145 intel_float_operand (mnemonic
));
4147 operand_ok
= i386_att_operand (token_start
);
4149 RESTORE_END_STRING (l
);
4155 if (expecting_operand
)
4157 expecting_operand_after_comma
:
4158 as_bad (_("expecting operand after ','; got nothing"));
4163 as_bad (_("expecting operand before ','; got nothing"));
4168 /* Now *l must be either ',' or END_OF_INSN. */
4171 if (*++l
== END_OF_INSN
)
4173 /* Just skip it, if it's \n complain. */
4174 goto expecting_operand_after_comma
;
4176 expecting_operand
= 1;
4183 swap_2_operands (int xchg1
, int xchg2
)
4185 union i386_op temp_op
;
4186 i386_operand_type temp_type
;
4187 enum bfd_reloc_code_real temp_reloc
;
4189 temp_type
= i
.types
[xchg2
];
4190 i
.types
[xchg2
] = i
.types
[xchg1
];
4191 i
.types
[xchg1
] = temp_type
;
4192 temp_op
= i
.op
[xchg2
];
4193 i
.op
[xchg2
] = i
.op
[xchg1
];
4194 i
.op
[xchg1
] = temp_op
;
4195 temp_reloc
= i
.reloc
[xchg2
];
4196 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4197 i
.reloc
[xchg1
] = temp_reloc
;
4201 if (i
.mask
->operand
== xchg1
)
4202 i
.mask
->operand
= xchg2
;
4203 else if (i
.mask
->operand
== xchg2
)
4204 i
.mask
->operand
= xchg1
;
4208 if (i
.broadcast
->operand
== xchg1
)
4209 i
.broadcast
->operand
= xchg2
;
4210 else if (i
.broadcast
->operand
== xchg2
)
4211 i
.broadcast
->operand
= xchg1
;
4215 if (i
.rounding
->operand
== xchg1
)
4216 i
.rounding
->operand
= xchg2
;
4217 else if (i
.rounding
->operand
== xchg2
)
4218 i
.rounding
->operand
= xchg1
;
4223 swap_operands (void)
4229 swap_2_operands (1, i
.operands
- 2);
4233 swap_2_operands (0, i
.operands
- 1);
4239 if (i
.mem_operands
== 2)
4241 const seg_entry
*temp_seg
;
4242 temp_seg
= i
.seg
[0];
4243 i
.seg
[0] = i
.seg
[1];
4244 i
.seg
[1] = temp_seg
;
4248 /* Try to ensure constant immediates are represented in the smallest
4253 char guess_suffix
= 0;
4257 guess_suffix
= i
.suffix
;
4258 else if (i
.reg_operands
)
4260 /* Figure out a suffix from the last register operand specified.
4261 We can't do this properly yet, ie. excluding InOutPortReg,
4262 but the following works for instructions with immediates.
4263 In any case, we can't set i.suffix yet. */
4264 for (op
= i
.operands
; --op
>= 0;)
4265 if (i
.types
[op
].bitfield
.reg8
)
4267 guess_suffix
= BYTE_MNEM_SUFFIX
;
4270 else if (i
.types
[op
].bitfield
.reg16
)
4272 guess_suffix
= WORD_MNEM_SUFFIX
;
4275 else if (i
.types
[op
].bitfield
.reg32
)
4277 guess_suffix
= LONG_MNEM_SUFFIX
;
4280 else if (i
.types
[op
].bitfield
.reg64
)
4282 guess_suffix
= QWORD_MNEM_SUFFIX
;
4286 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4287 guess_suffix
= WORD_MNEM_SUFFIX
;
4289 for (op
= i
.operands
; --op
>= 0;)
4290 if (operand_type_check (i
.types
[op
], imm
))
4292 switch (i
.op
[op
].imms
->X_op
)
4295 /* If a suffix is given, this operand may be shortened. */
4296 switch (guess_suffix
)
4298 case LONG_MNEM_SUFFIX
:
4299 i
.types
[op
].bitfield
.imm32
= 1;
4300 i
.types
[op
].bitfield
.imm64
= 1;
4302 case WORD_MNEM_SUFFIX
:
4303 i
.types
[op
].bitfield
.imm16
= 1;
4304 i
.types
[op
].bitfield
.imm32
= 1;
4305 i
.types
[op
].bitfield
.imm32s
= 1;
4306 i
.types
[op
].bitfield
.imm64
= 1;
4308 case BYTE_MNEM_SUFFIX
:
4309 i
.types
[op
].bitfield
.imm8
= 1;
4310 i
.types
[op
].bitfield
.imm8s
= 1;
4311 i
.types
[op
].bitfield
.imm16
= 1;
4312 i
.types
[op
].bitfield
.imm32
= 1;
4313 i
.types
[op
].bitfield
.imm32s
= 1;
4314 i
.types
[op
].bitfield
.imm64
= 1;
4318 /* If this operand is at most 16 bits, convert it
4319 to a signed 16 bit number before trying to see
4320 whether it will fit in an even smaller size.
4321 This allows a 16-bit operand such as $0xffe0 to
4322 be recognised as within Imm8S range. */
4323 if ((i
.types
[op
].bitfield
.imm16
)
4324 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4326 i
.op
[op
].imms
->X_add_number
=
4327 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4330 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4331 if ((i
.types
[op
].bitfield
.imm32
)
4332 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4335 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4336 ^ ((offsetT
) 1 << 31))
4337 - ((offsetT
) 1 << 31));
4341 = operand_type_or (i
.types
[op
],
4342 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4344 /* We must avoid matching of Imm32 templates when 64bit
4345 only immediate is available. */
4346 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4347 i
.types
[op
].bitfield
.imm32
= 0;
4354 /* Symbols and expressions. */
4356 /* Convert symbolic operand to proper sizes for matching, but don't
4357 prevent matching a set of insns that only supports sizes other
4358 than those matching the insn suffix. */
4360 i386_operand_type mask
, allowed
;
4361 const insn_template
*t
;
4363 operand_type_set (&mask
, 0);
4364 operand_type_set (&allowed
, 0);
4366 for (t
= current_templates
->start
;
4367 t
< current_templates
->end
;
4369 allowed
= operand_type_or (allowed
,
4370 t
->operand_types
[op
]);
4371 switch (guess_suffix
)
4373 case QWORD_MNEM_SUFFIX
:
4374 mask
.bitfield
.imm64
= 1;
4375 mask
.bitfield
.imm32s
= 1;
4377 case LONG_MNEM_SUFFIX
:
4378 mask
.bitfield
.imm32
= 1;
4380 case WORD_MNEM_SUFFIX
:
4381 mask
.bitfield
.imm16
= 1;
4383 case BYTE_MNEM_SUFFIX
:
4384 mask
.bitfield
.imm8
= 1;
4389 allowed
= operand_type_and (mask
, allowed
);
4390 if (!operand_type_all_zero (&allowed
))
4391 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4398 /* Try to use the smallest displacement type too. */
4400 optimize_disp (void)
4404 for (op
= i
.operands
; --op
>= 0;)
4405 if (operand_type_check (i
.types
[op
], disp
))
4407 if (i
.op
[op
].disps
->X_op
== O_constant
)
4409 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4411 if (i
.types
[op
].bitfield
.disp16
4412 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4414 /* If this operand is at most 16 bits, convert
4415 to a signed 16 bit number and don't use 64bit
4417 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4418 i
.types
[op
].bitfield
.disp64
= 0;
4421 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4422 if (i
.types
[op
].bitfield
.disp32
4423 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4425 /* If this operand is at most 32 bits, convert
4426 to a signed 32 bit number and don't use 64bit
4428 op_disp
&= (((offsetT
) 2 << 31) - 1);
4429 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4430 i
.types
[op
].bitfield
.disp64
= 0;
4433 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4435 i
.types
[op
].bitfield
.disp8
= 0;
4436 i
.types
[op
].bitfield
.disp16
= 0;
4437 i
.types
[op
].bitfield
.disp32
= 0;
4438 i
.types
[op
].bitfield
.disp32s
= 0;
4439 i
.types
[op
].bitfield
.disp64
= 0;
4443 else if (flag_code
== CODE_64BIT
)
4445 if (fits_in_signed_long (op_disp
))
4447 i
.types
[op
].bitfield
.disp64
= 0;
4448 i
.types
[op
].bitfield
.disp32s
= 1;
4450 if (i
.prefix
[ADDR_PREFIX
]
4451 && fits_in_unsigned_long (op_disp
))
4452 i
.types
[op
].bitfield
.disp32
= 1;
4454 if ((i
.types
[op
].bitfield
.disp32
4455 || i
.types
[op
].bitfield
.disp32s
4456 || i
.types
[op
].bitfield
.disp16
)
4457 && fits_in_signed_byte (op_disp
))
4458 i
.types
[op
].bitfield
.disp8
= 1;
4460 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4461 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4463 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4464 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4465 i
.types
[op
].bitfield
.disp8
= 0;
4466 i
.types
[op
].bitfield
.disp16
= 0;
4467 i
.types
[op
].bitfield
.disp32
= 0;
4468 i
.types
[op
].bitfield
.disp32s
= 0;
4469 i
.types
[op
].bitfield
.disp64
= 0;
4472 /* We only support 64bit displacement on constants. */
4473 i
.types
[op
].bitfield
.disp64
= 0;
4477 /* Check if operands are valid for the instruction. */
4480 check_VecOperands (const insn_template
*t
)
4484 /* Without VSIB byte, we can't have a vector register for index. */
4485 if (!t
->opcode_modifier
.vecsib
4487 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4488 || i
.index_reg
->reg_type
.bitfield
.regymm
4489 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4491 i
.error
= unsupported_vector_index_register
;
4495 /* Check if default mask is allowed. */
4496 if (t
->opcode_modifier
.nodefmask
4497 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4499 i
.error
= no_default_mask
;
4503 /* For VSIB byte, we need a vector register for index, and all vector
4504 registers must be distinct. */
4505 if (t
->opcode_modifier
.vecsib
)
4508 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4509 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4510 || (t
->opcode_modifier
.vecsib
== VecSIB256
4511 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4512 || (t
->opcode_modifier
.vecsib
== VecSIB512
4513 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4515 i
.error
= invalid_vsib_address
;
4519 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4520 if (i
.reg_operands
== 2 && !i
.mask
)
4522 gas_assert (i
.types
[0].bitfield
.regxmm
4523 || i
.types
[0].bitfield
.regymm
);
4524 gas_assert (i
.types
[2].bitfield
.regxmm
4525 || i
.types
[2].bitfield
.regymm
);
4526 if (operand_check
== check_none
)
4528 if (register_number (i
.op
[0].regs
)
4529 != register_number (i
.index_reg
)
4530 && register_number (i
.op
[2].regs
)
4531 != register_number (i
.index_reg
)
4532 && register_number (i
.op
[0].regs
)
4533 != register_number (i
.op
[2].regs
))
4535 if (operand_check
== check_error
)
4537 i
.error
= invalid_vector_register_set
;
4540 as_warn (_("mask, index, and destination registers should be distinct"));
4542 else if (i
.reg_operands
== 1 && i
.mask
)
4544 if ((i
.types
[1].bitfield
.regymm
4545 || i
.types
[1].bitfield
.regzmm
)
4546 && (register_number (i
.op
[1].regs
)
4547 == register_number (i
.index_reg
)))
4549 if (operand_check
== check_error
)
4551 i
.error
= invalid_vector_register_set
;
4554 if (operand_check
!= check_none
)
4555 as_warn (_("index and destination registers should be distinct"));
4560 /* Check if broadcast is supported by the instruction and is applied
4561 to the memory operand. */
4564 int broadcasted_opnd_size
;
4566 /* Check if specified broadcast is supported in this instruction,
4567 and it's applied to memory operand of DWORD or QWORD type,
4568 depending on VecESize. */
4569 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4570 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4571 || (t
->opcode_modifier
.vecesize
== 0
4572 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4573 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4574 || (t
->opcode_modifier
.vecesize
== 1
4575 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4576 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4579 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4580 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4581 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4582 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4583 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4584 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4585 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4586 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4587 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4591 if ((broadcasted_opnd_size
== 256
4592 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4593 || (broadcasted_opnd_size
== 512
4594 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4597 i
.error
= unsupported_broadcast
;
4601 /* If broadcast is supported in this instruction, we need to check if
4602 operand of one-element size isn't specified without broadcast. */
4603 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4605 /* Find memory operand. */
4606 for (op
= 0; op
< i
.operands
; op
++)
4607 if (operand_type_check (i
.types
[op
], anymem
))
4609 gas_assert (op
< i
.operands
);
4610 /* Check size of the memory operand. */
4611 if ((t
->opcode_modifier
.vecesize
== 0
4612 && i
.types
[op
].bitfield
.dword
)
4613 || (t
->opcode_modifier
.vecesize
== 1
4614 && i
.types
[op
].bitfield
.qword
))
4616 i
.error
= broadcast_needed
;
4621 /* Check if requested masking is supported. */
4623 && (!t
->opcode_modifier
.masking
4625 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4627 i
.error
= unsupported_masking
;
4631 /* Check if masking is applied to dest operand. */
4632 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4634 i
.error
= mask_not_on_destination
;
4641 if ((i
.rounding
->type
!= saeonly
4642 && !t
->opcode_modifier
.staticrounding
)
4643 || (i
.rounding
->type
== saeonly
4644 && (t
->opcode_modifier
.staticrounding
4645 || !t
->opcode_modifier
.sae
)))
4647 i
.error
= unsupported_rc_sae
;
4650 /* If the instruction has several immediate operands and one of
4651 them is rounding, the rounding operand should be the last
4652 immediate operand. */
4653 if (i
.imm_operands
> 1
4654 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4656 i
.error
= rc_sae_operand_not_last_imm
;
4661 /* Check vector Disp8 operand. */
4662 if (t
->opcode_modifier
.disp8memshift
)
4665 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4667 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4669 for (op
= 0; op
< i
.operands
; op
++)
4670 if (operand_type_check (i
.types
[op
], disp
)
4671 && i
.op
[op
].disps
->X_op
== O_constant
)
4673 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4675 = (i
.disp_encoding
!= disp_encoding_32bit
4676 && fits_in_vec_disp8 (value
));
4677 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4680 i
.types
[op
].bitfield
.vec_disp8
= 1;
4683 /* Vector insn can only have Vec_Disp8/Disp32 in
4684 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4686 i
.types
[op
].bitfield
.disp8
= 0;
4687 if (flag_code
!= CODE_16BIT
)
4688 i
.types
[op
].bitfield
.disp16
= 0;
4691 else if (flag_code
!= CODE_16BIT
)
4693 /* One form of this instruction supports vector Disp8.
4694 Try vector Disp8 if we need to use Disp32. */
4695 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4697 i
.error
= try_vector_disp8
;
4709 /* Check if operands are valid for the instruction. Update VEX
4713 VEX_check_operands (const insn_template
*t
)
4715 /* VREX is only valid with EVEX prefix. */
4716 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4718 i
.error
= invalid_register_operand
;
4722 if (!t
->opcode_modifier
.vex
)
4725 /* Only check VEX_Imm4, which must be the first operand. */
4726 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4728 if (i
.op
[0].imms
->X_op
!= O_constant
4729 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4735 /* Turn off Imm8 so that update_imm won't complain. */
4736 i
.types
[0] = vec_imm4
;
4742 static const insn_template
*
4743 match_template (char mnem_suffix
)
4745 /* Points to template once we've found it. */
4746 const insn_template
*t
;
4747 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4748 i386_operand_type overlap4
;
4749 unsigned int found_reverse_match
;
4750 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4751 i386_operand_type operand_types
[MAX_OPERANDS
];
4752 int addr_prefix_disp
;
4754 unsigned int found_cpu_match
;
4755 unsigned int check_register
;
4756 enum i386_error specific_error
= 0;
4758 #if MAX_OPERANDS != 5
4759 # error "MAX_OPERANDS must be 5."
4762 found_reverse_match
= 0;
4763 addr_prefix_disp
= -1;
4765 memset (&suffix_check
, 0, sizeof (suffix_check
));
4766 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4767 suffix_check
.no_bsuf
= 1;
4768 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4769 suffix_check
.no_wsuf
= 1;
4770 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4771 suffix_check
.no_ssuf
= 1;
4772 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4773 suffix_check
.no_lsuf
= 1;
4774 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4775 suffix_check
.no_qsuf
= 1;
4776 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4777 suffix_check
.no_ldsuf
= 1;
4779 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4782 switch (mnem_suffix
)
4784 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4785 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4786 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4787 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4788 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4792 /* Must have right number of operands. */
4793 i
.error
= number_of_operands_mismatch
;
4795 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4797 addr_prefix_disp
= -1;
4799 if (i
.operands
!= t
->operands
)
4802 /* Check processor support. */
4803 i
.error
= unsupported
;
4804 found_cpu_match
= (cpu_flags_match (t
)
4805 == CPU_FLAGS_PERFECT_MATCH
);
4806 if (!found_cpu_match
)
4809 /* Check old gcc support. */
4810 i
.error
= old_gcc_only
;
4811 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4814 /* Check AT&T mnemonic. */
4815 i
.error
= unsupported_with_intel_mnemonic
;
4816 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4819 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4820 i
.error
= unsupported_syntax
;
4821 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4822 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4823 || (intel64
&& t
->opcode_modifier
.amd64
)
4824 || (!intel64
&& t
->opcode_modifier
.intel64
))
4827 /* Check the suffix, except for some instructions in intel mode. */
4828 i
.error
= invalid_instruction_suffix
;
4829 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4830 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4831 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4832 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4833 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4834 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4835 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4837 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4838 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4839 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4840 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4841 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4842 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4843 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4846 if (!operand_size_match (t
))
4849 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4850 operand_types
[j
] = t
->operand_types
[j
];
4852 /* In general, don't allow 64-bit operands in 32-bit mode. */
4853 if (i
.suffix
== QWORD_MNEM_SUFFIX
4854 && flag_code
!= CODE_64BIT
4856 ? (!t
->opcode_modifier
.ignoresize
4857 && !intel_float_operand (t
->name
))
4858 : intel_float_operand (t
->name
) != 2)
4859 && ((!operand_types
[0].bitfield
.regmmx
4860 && !operand_types
[0].bitfield
.regxmm
4861 && !operand_types
[0].bitfield
.regymm
4862 && !operand_types
[0].bitfield
.regzmm
)
4863 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4864 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4865 && operand_types
[t
->operands
> 1].bitfield
.regymm
4866 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4867 && (t
->base_opcode
!= 0x0fc7
4868 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4871 /* In general, don't allow 32-bit operands on pre-386. */
4872 else if (i
.suffix
== LONG_MNEM_SUFFIX
4873 && !cpu_arch_flags
.bitfield
.cpui386
4875 ? (!t
->opcode_modifier
.ignoresize
4876 && !intel_float_operand (t
->name
))
4877 : intel_float_operand (t
->name
) != 2)
4878 && ((!operand_types
[0].bitfield
.regmmx
4879 && !operand_types
[0].bitfield
.regxmm
)
4880 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4881 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4884 /* Do not verify operands when there are none. */
4888 /* We've found a match; break out of loop. */
4892 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4893 into Disp32/Disp16/Disp32 operand. */
4894 if (i
.prefix
[ADDR_PREFIX
] != 0)
4896 /* There should be only one Disp operand. */
4900 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4902 if (operand_types
[j
].bitfield
.disp16
)
4904 addr_prefix_disp
= j
;
4905 operand_types
[j
].bitfield
.disp32
= 1;
4906 operand_types
[j
].bitfield
.disp16
= 0;
4912 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4914 if (operand_types
[j
].bitfield
.disp32
)
4916 addr_prefix_disp
= j
;
4917 operand_types
[j
].bitfield
.disp32
= 0;
4918 operand_types
[j
].bitfield
.disp16
= 1;
4924 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4926 if (operand_types
[j
].bitfield
.disp64
)
4928 addr_prefix_disp
= j
;
4929 operand_types
[j
].bitfield
.disp64
= 0;
4930 operand_types
[j
].bitfield
.disp32
= 1;
4938 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4939 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4942 /* We check register size if needed. */
4943 check_register
= t
->opcode_modifier
.checkregsize
;
4944 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4945 switch (t
->operands
)
4948 if (!operand_type_match (overlap0
, i
.types
[0]))
4952 /* xchg %eax, %eax is a special case. It is an aliase for nop
4953 only in 32bit mode and we can use opcode 0x90. In 64bit
4954 mode, we can't use 0x90 for xchg %eax, %eax since it should
4955 zero-extend %eax to %rax. */
4956 if (flag_code
== CODE_64BIT
4957 && t
->base_opcode
== 0x90
4958 && operand_type_equal (&i
.types
[0], &acc32
)
4959 && operand_type_equal (&i
.types
[1], &acc32
))
4963 /* If we swap operand in encoding, we either match
4964 the next one or reverse direction of operands. */
4965 if (t
->opcode_modifier
.s
)
4967 else if (t
->opcode_modifier
.d
)
4973 /* If we swap operand in encoding, we match the next one. */
4974 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4979 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4980 if (!operand_type_match (overlap0
, i
.types
[0])
4981 || !operand_type_match (overlap1
, i
.types
[1])
4983 && !operand_type_register_match (overlap0
, i
.types
[0],
4985 overlap1
, i
.types
[1],
4988 /* Check if other direction is valid ... */
4989 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4993 /* Try reversing direction of operands. */
4994 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4995 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4996 if (!operand_type_match (overlap0
, i
.types
[0])
4997 || !operand_type_match (overlap1
, i
.types
[1])
4999 && !operand_type_register_match (overlap0
,
5006 /* Does not match either direction. */
5009 /* found_reverse_match holds which of D or FloatDR
5011 if (t
->opcode_modifier
.d
)
5012 found_reverse_match
= Opcode_D
;
5013 else if (t
->opcode_modifier
.floatd
)
5014 found_reverse_match
= Opcode_FloatD
;
5016 found_reverse_match
= 0;
5017 if (t
->opcode_modifier
.floatr
)
5018 found_reverse_match
|= Opcode_FloatR
;
5022 /* Found a forward 2 operand match here. */
5023 switch (t
->operands
)
5026 overlap4
= operand_type_and (i
.types
[4],
5030 overlap3
= operand_type_and (i
.types
[3],
5034 overlap2
= operand_type_and (i
.types
[2],
5039 switch (t
->operands
)
5042 if (!operand_type_match (overlap4
, i
.types
[4])
5043 || !operand_type_register_match (overlap3
,
5052 if (!operand_type_match (overlap3
, i
.types
[3])
5054 && !operand_type_register_match (overlap2
,
5063 /* Here we make use of the fact that there are no
5064 reverse match 3 operand instructions, and all 3
5065 operand instructions only need to be checked for
5066 register consistency between operands 2 and 3. */
5067 if (!operand_type_match (overlap2
, i
.types
[2])
5069 && !operand_type_register_match (overlap1
,
5079 /* Found either forward/reverse 2, 3 or 4 operand match here:
5080 slip through to break. */
5082 if (!found_cpu_match
)
5084 found_reverse_match
= 0;
5088 /* Check if vector and VEX operands are valid. */
5089 if (check_VecOperands (t
) || VEX_check_operands (t
))
5091 specific_error
= i
.error
;
5095 /* We've found a match; break out of loop. */
5099 if (t
== current_templates
->end
)
5101 /* We found no match. */
5102 const char *err_msg
;
5103 switch (specific_error
? specific_error
: i
.error
)
5107 case operand_size_mismatch
:
5108 err_msg
= _("operand size mismatch");
5110 case operand_type_mismatch
:
5111 err_msg
= _("operand type mismatch");
5113 case register_type_mismatch
:
5114 err_msg
= _("register type mismatch");
5116 case number_of_operands_mismatch
:
5117 err_msg
= _("number of operands mismatch");
5119 case invalid_instruction_suffix
:
5120 err_msg
= _("invalid instruction suffix");
5123 err_msg
= _("constant doesn't fit in 4 bits");
5126 err_msg
= _("only supported with old gcc");
5128 case unsupported_with_intel_mnemonic
:
5129 err_msg
= _("unsupported with Intel mnemonic");
5131 case unsupported_syntax
:
5132 err_msg
= _("unsupported syntax");
5135 as_bad (_("unsupported instruction `%s'"),
5136 current_templates
->start
->name
);
5138 case invalid_vsib_address
:
5139 err_msg
= _("invalid VSIB address");
5141 case invalid_vector_register_set
:
5142 err_msg
= _("mask, index, and destination registers must be distinct");
5144 case unsupported_vector_index_register
:
5145 err_msg
= _("unsupported vector index register");
5147 case unsupported_broadcast
:
5148 err_msg
= _("unsupported broadcast");
5150 case broadcast_not_on_src_operand
:
5151 err_msg
= _("broadcast not on source memory operand");
5153 case broadcast_needed
:
5154 err_msg
= _("broadcast is needed for operand of such type");
5156 case unsupported_masking
:
5157 err_msg
= _("unsupported masking");
5159 case mask_not_on_destination
:
5160 err_msg
= _("mask not on destination operand");
5162 case no_default_mask
:
5163 err_msg
= _("default mask isn't allowed");
5165 case unsupported_rc_sae
:
5166 err_msg
= _("unsupported static rounding/sae");
5168 case rc_sae_operand_not_last_imm
:
5170 err_msg
= _("RC/SAE operand must precede immediate operands");
5172 err_msg
= _("RC/SAE operand must follow immediate operands");
5174 case invalid_register_operand
:
5175 err_msg
= _("invalid register operand");
5178 as_bad (_("%s for `%s'"), err_msg
,
5179 current_templates
->start
->name
);
5183 if (!quiet_warnings
)
5186 && (i
.types
[0].bitfield
.jumpabsolute
5187 != operand_types
[0].bitfield
.jumpabsolute
))
5189 as_warn (_("indirect %s without `*'"), t
->name
);
5192 if (t
->opcode_modifier
.isprefix
5193 && t
->opcode_modifier
.ignoresize
)
5195 /* Warn them that a data or address size prefix doesn't
5196 affect assembly of the next line of code. */
5197 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5201 /* Copy the template we found. */
5204 if (addr_prefix_disp
!= -1)
5205 i
.tm
.operand_types
[addr_prefix_disp
]
5206 = operand_types
[addr_prefix_disp
];
5208 if (found_reverse_match
)
5210 /* If we found a reverse match we must alter the opcode
5211 direction bit. found_reverse_match holds bits to change
5212 (different for int & float insns). */
5214 i
.tm
.base_opcode
^= found_reverse_match
;
5216 i
.tm
.operand_types
[0] = operand_types
[1];
5217 i
.tm
.operand_types
[1] = operand_types
[0];
5226 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5227 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5229 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5231 as_bad (_("`%s' operand %d must use `%ses' segment"),
5237 /* There's only ever one segment override allowed per instruction.
5238 This instruction possibly has a legal segment override on the
5239 second operand, so copy the segment to where non-string
5240 instructions store it, allowing common code. */
5241 i
.seg
[0] = i
.seg
[1];
5243 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5245 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5247 as_bad (_("`%s' operand %d must use `%ses' segment"),
5258 process_suffix (void)
5260 /* If matched instruction specifies an explicit instruction mnemonic
5262 if (i
.tm
.opcode_modifier
.size16
)
5263 i
.suffix
= WORD_MNEM_SUFFIX
;
5264 else if (i
.tm
.opcode_modifier
.size32
)
5265 i
.suffix
= LONG_MNEM_SUFFIX
;
5266 else if (i
.tm
.opcode_modifier
.size64
)
5267 i
.suffix
= QWORD_MNEM_SUFFIX
;
5268 else if (i
.reg_operands
)
5270 /* If there's no instruction mnemonic suffix we try to invent one
5271 based on register operands. */
5274 /* We take i.suffix from the last register operand specified,
5275 Destination register type is more significant than source
5276 register type. crc32 in SSE4.2 prefers source register
5278 if (i
.tm
.base_opcode
== 0xf20f38f1)
5280 if (i
.types
[0].bitfield
.reg16
)
5281 i
.suffix
= WORD_MNEM_SUFFIX
;
5282 else if (i
.types
[0].bitfield
.reg32
)
5283 i
.suffix
= LONG_MNEM_SUFFIX
;
5284 else if (i
.types
[0].bitfield
.reg64
)
5285 i
.suffix
= QWORD_MNEM_SUFFIX
;
5287 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5289 if (i
.types
[0].bitfield
.reg8
)
5290 i
.suffix
= BYTE_MNEM_SUFFIX
;
5297 if (i
.tm
.base_opcode
== 0xf20f38f1
5298 || i
.tm
.base_opcode
== 0xf20f38f0)
5300 /* We have to know the operand size for crc32. */
5301 as_bad (_("ambiguous memory operand size for `%s`"),
5306 for (op
= i
.operands
; --op
>= 0;)
5307 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5309 if (i
.types
[op
].bitfield
.reg8
)
5311 i
.suffix
= BYTE_MNEM_SUFFIX
;
5314 else if (i
.types
[op
].bitfield
.reg16
)
5316 i
.suffix
= WORD_MNEM_SUFFIX
;
5319 else if (i
.types
[op
].bitfield
.reg32
)
5321 i
.suffix
= LONG_MNEM_SUFFIX
;
5324 else if (i
.types
[op
].bitfield
.reg64
)
5326 i
.suffix
= QWORD_MNEM_SUFFIX
;
5332 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5335 && i
.tm
.opcode_modifier
.ignoresize
5336 && i
.tm
.opcode_modifier
.no_bsuf
)
5338 else if (!check_byte_reg ())
5341 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5344 && i
.tm
.opcode_modifier
.ignoresize
5345 && i
.tm
.opcode_modifier
.no_lsuf
)
5347 else if (!check_long_reg ())
5350 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5353 && i
.tm
.opcode_modifier
.ignoresize
5354 && i
.tm
.opcode_modifier
.no_qsuf
)
5356 else if (!check_qword_reg ())
5359 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5362 && i
.tm
.opcode_modifier
.ignoresize
5363 && i
.tm
.opcode_modifier
.no_wsuf
)
5365 else if (!check_word_reg ())
5368 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5369 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5370 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5372 /* Skip if the instruction has x/y/z suffix. match_template
5373 should check if it is a valid suffix. */
5375 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5376 /* Do nothing if the instruction is going to ignore the prefix. */
5381 else if (i
.tm
.opcode_modifier
.defaultsize
5383 /* exclude fldenv/frstor/fsave/fstenv */
5384 && i
.tm
.opcode_modifier
.no_ssuf
)
5386 i
.suffix
= stackop_size
;
5388 else if (intel_syntax
5390 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5391 || i
.tm
.opcode_modifier
.jumpbyte
5392 || i
.tm
.opcode_modifier
.jumpintersegment
5393 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5394 && i
.tm
.extension_opcode
<= 3)))
5399 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5401 i
.suffix
= QWORD_MNEM_SUFFIX
;
5406 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5407 i
.suffix
= LONG_MNEM_SUFFIX
;
5410 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5411 i
.suffix
= WORD_MNEM_SUFFIX
;
5420 if (i
.tm
.opcode_modifier
.w
)
5422 as_bad (_("no instruction mnemonic suffix given and "
5423 "no register operands; can't size instruction"));
5429 unsigned int suffixes
;
5431 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5432 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5434 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5436 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5438 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5440 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5443 /* There are more than suffix matches. */
5444 if (i
.tm
.opcode_modifier
.w
5445 || ((suffixes
& (suffixes
- 1))
5446 && !i
.tm
.opcode_modifier
.defaultsize
5447 && !i
.tm
.opcode_modifier
.ignoresize
))
5449 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5455 /* Change the opcode based on the operand size given by i.suffix;
5456 We don't need to change things for byte insns. */
5459 && i
.suffix
!= BYTE_MNEM_SUFFIX
5460 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5461 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5462 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5464 /* It's not a byte, select word/dword operation. */
5465 if (i
.tm
.opcode_modifier
.w
)
5467 if (i
.tm
.opcode_modifier
.shortform
)
5468 i
.tm
.base_opcode
|= 8;
5470 i
.tm
.base_opcode
|= 1;
5473 /* Now select between word & dword operations via the operand
5474 size prefix, except for instructions that will ignore this
5476 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5478 /* The address size override prefix changes the size of the
5480 if ((flag_code
== CODE_32BIT
5481 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5482 || (flag_code
!= CODE_32BIT
5483 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5484 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5487 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5488 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5489 && !i
.tm
.opcode_modifier
.ignoresize
5490 && !i
.tm
.opcode_modifier
.floatmf
5491 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5492 || (flag_code
== CODE_64BIT
5493 && i
.tm
.opcode_modifier
.jumpbyte
)))
5495 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5497 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5498 prefix
= ADDR_PREFIX_OPCODE
;
5500 if (!add_prefix (prefix
))
5504 /* Set mode64 for an operand. */
5505 if (i
.suffix
== QWORD_MNEM_SUFFIX
5506 && flag_code
== CODE_64BIT
5507 && !i
.tm
.opcode_modifier
.norex64
)
5509 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5510 need rex64. cmpxchg8b is also a special case. */
5511 if (! (i
.operands
== 2
5512 && i
.tm
.base_opcode
== 0x90
5513 && i
.tm
.extension_opcode
== None
5514 && operand_type_equal (&i
.types
[0], &acc64
)
5515 && operand_type_equal (&i
.types
[1], &acc64
))
5516 && ! (i
.operands
== 1
5517 && i
.tm
.base_opcode
== 0xfc7
5518 && i
.tm
.extension_opcode
== 1
5519 && !operand_type_check (i
.types
[0], reg
)
5520 && operand_type_check (i
.types
[0], anymem
)))
5524 /* Size floating point instruction. */
5525 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5526 if (i
.tm
.opcode_modifier
.floatmf
)
5527 i
.tm
.base_opcode
^= 4;
5534 check_byte_reg (void)
5538 for (op
= i
.operands
; --op
>= 0;)
5540 /* If this is an eight bit register, it's OK. If it's the 16 or
5541 32 bit version of an eight bit register, we will just use the
5542 low portion, and that's OK too. */
5543 if (i
.types
[op
].bitfield
.reg8
)
5546 /* I/O port address operands are OK too. */
5547 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5550 /* crc32 doesn't generate this warning. */
5551 if (i
.tm
.base_opcode
== 0xf20f38f0)
5554 if ((i
.types
[op
].bitfield
.reg16
5555 || i
.types
[op
].bitfield
.reg32
5556 || i
.types
[op
].bitfield
.reg64
)
5557 && i
.op
[op
].regs
->reg_num
< 4
5558 /* Prohibit these changes in 64bit mode, since the lowering
5559 would be more complicated. */
5560 && flag_code
!= CODE_64BIT
)
5562 #if REGISTER_WARNINGS
5563 if (!quiet_warnings
)
5564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5566 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5567 ? REGNAM_AL
- REGNAM_AX
5568 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5570 i
.op
[op
].regs
->reg_name
,
5575 /* Any other register is bad. */
5576 if (i
.types
[op
].bitfield
.reg16
5577 || i
.types
[op
].bitfield
.reg32
5578 || i
.types
[op
].bitfield
.reg64
5579 || i
.types
[op
].bitfield
.regmmx
5580 || i
.types
[op
].bitfield
.regxmm
5581 || i
.types
[op
].bitfield
.regymm
5582 || i
.types
[op
].bitfield
.regzmm
5583 || i
.types
[op
].bitfield
.sreg2
5584 || i
.types
[op
].bitfield
.sreg3
5585 || i
.types
[op
].bitfield
.control
5586 || i
.types
[op
].bitfield
.debug
5587 || i
.types
[op
].bitfield
.test
5588 || i
.types
[op
].bitfield
.floatreg
5589 || i
.types
[op
].bitfield
.floatacc
)
5591 as_bad (_("`%s%s' not allowed with `%s%c'"),
5593 i
.op
[op
].regs
->reg_name
,
5603 check_long_reg (void)
5607 for (op
= i
.operands
; --op
>= 0;)
5608 /* Reject eight bit registers, except where the template requires
5609 them. (eg. movzb) */
5610 if (i
.types
[op
].bitfield
.reg8
5611 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5612 || i
.tm
.operand_types
[op
].bitfield
.reg32
5613 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5615 as_bad (_("`%s%s' not allowed with `%s%c'"),
5617 i
.op
[op
].regs
->reg_name
,
5622 /* Warn if the e prefix on a general reg is missing. */
5623 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5624 && i
.types
[op
].bitfield
.reg16
5625 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5626 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5628 /* Prohibit these changes in the 64bit mode, since the
5629 lowering is more complicated. */
5630 if (flag_code
== CODE_64BIT
)
5632 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5633 register_prefix
, i
.op
[op
].regs
->reg_name
,
5637 #if REGISTER_WARNINGS
5638 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5640 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5641 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5644 /* Warn if the r prefix on a general reg is present. */
5645 else if (i
.types
[op
].bitfield
.reg64
5646 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5647 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5650 && i
.tm
.opcode_modifier
.toqword
5651 && !i
.types
[0].bitfield
.regxmm
)
5653 /* Convert to QWORD. We want REX byte. */
5654 i
.suffix
= QWORD_MNEM_SUFFIX
;
5658 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5659 register_prefix
, i
.op
[op
].regs
->reg_name
,
5668 check_qword_reg (void)
5672 for (op
= i
.operands
; --op
>= 0; )
5673 /* Reject eight bit registers, except where the template requires
5674 them. (eg. movzb) */
5675 if (i
.types
[op
].bitfield
.reg8
5676 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5677 || i
.tm
.operand_types
[op
].bitfield
.reg32
5678 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5680 as_bad (_("`%s%s' not allowed with `%s%c'"),
5682 i
.op
[op
].regs
->reg_name
,
5687 /* Warn if the r prefix on a general reg is missing. */
5688 else if ((i
.types
[op
].bitfield
.reg16
5689 || i
.types
[op
].bitfield
.reg32
)
5690 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5691 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5693 /* Prohibit these changes in the 64bit mode, since the
5694 lowering is more complicated. */
5696 && i
.tm
.opcode_modifier
.todword
5697 && !i
.types
[0].bitfield
.regxmm
)
5699 /* Convert to DWORD. We don't want REX byte. */
5700 i
.suffix
= LONG_MNEM_SUFFIX
;
5704 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5705 register_prefix
, i
.op
[op
].regs
->reg_name
,
5714 check_word_reg (void)
5717 for (op
= i
.operands
; --op
>= 0;)
5718 /* Reject eight bit registers, except where the template requires
5719 them. (eg. movzb) */
5720 if (i
.types
[op
].bitfield
.reg8
5721 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5722 || i
.tm
.operand_types
[op
].bitfield
.reg32
5723 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5725 as_bad (_("`%s%s' not allowed with `%s%c'"),
5727 i
.op
[op
].regs
->reg_name
,
5732 /* Warn if the e or r prefix on a general reg is present. */
5733 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5734 && (i
.types
[op
].bitfield
.reg32
5735 || i
.types
[op
].bitfield
.reg64
)
5736 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5737 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5739 /* Prohibit these changes in the 64bit mode, since the
5740 lowering is more complicated. */
5741 if (flag_code
== CODE_64BIT
)
5743 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5744 register_prefix
, i
.op
[op
].regs
->reg_name
,
5748 #if REGISTER_WARNINGS
5749 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5751 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5752 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5759 update_imm (unsigned int j
)
5761 i386_operand_type overlap
= i
.types
[j
];
5762 if ((overlap
.bitfield
.imm8
5763 || overlap
.bitfield
.imm8s
5764 || overlap
.bitfield
.imm16
5765 || overlap
.bitfield
.imm32
5766 || overlap
.bitfield
.imm32s
5767 || overlap
.bitfield
.imm64
)
5768 && !operand_type_equal (&overlap
, &imm8
)
5769 && !operand_type_equal (&overlap
, &imm8s
)
5770 && !operand_type_equal (&overlap
, &imm16
)
5771 && !operand_type_equal (&overlap
, &imm32
)
5772 && !operand_type_equal (&overlap
, &imm32s
)
5773 && !operand_type_equal (&overlap
, &imm64
))
5777 i386_operand_type temp
;
5779 operand_type_set (&temp
, 0);
5780 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5782 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5783 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5785 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5786 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5787 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5789 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5790 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5793 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5796 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5797 || operand_type_equal (&overlap
, &imm16_32
)
5798 || operand_type_equal (&overlap
, &imm16_32s
))
5800 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5805 if (!operand_type_equal (&overlap
, &imm8
)
5806 && !operand_type_equal (&overlap
, &imm8s
)
5807 && !operand_type_equal (&overlap
, &imm16
)
5808 && !operand_type_equal (&overlap
, &imm32
)
5809 && !operand_type_equal (&overlap
, &imm32s
)
5810 && !operand_type_equal (&overlap
, &imm64
))
5812 as_bad (_("no instruction mnemonic suffix given; "
5813 "can't determine immediate size"));
5817 i
.types
[j
] = overlap
;
5827 /* Update the first 2 immediate operands. */
5828 n
= i
.operands
> 2 ? 2 : i
.operands
;
5831 for (j
= 0; j
< n
; j
++)
5832 if (update_imm (j
) == 0)
5835 /* The 3rd operand can't be immediate operand. */
5836 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5843 bad_implicit_operand (int xmm
)
5845 const char *ireg
= xmm
? "xmm0" : "ymm0";
5848 as_bad (_("the last operand of `%s' must be `%s%s'"),
5849 i
.tm
.name
, register_prefix
, ireg
);
5851 as_bad (_("the first operand of `%s' must be `%s%s'"),
5852 i
.tm
.name
, register_prefix
, ireg
);
5857 process_operands (void)
5859 /* Default segment register this instruction will use for memory
5860 accesses. 0 means unknown. This is only for optimizing out
5861 unnecessary segment overrides. */
5862 const seg_entry
*default_seg
= 0;
5864 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5866 unsigned int dupl
= i
.operands
;
5867 unsigned int dest
= dupl
- 1;
5870 /* The destination must be an xmm register. */
5871 gas_assert (i
.reg_operands
5872 && MAX_OPERANDS
> dupl
5873 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5875 if (i
.tm
.opcode_modifier
.firstxmm0
)
5877 /* The first operand is implicit and must be xmm0. */
5878 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5879 if (register_number (i
.op
[0].regs
) != 0)
5880 return bad_implicit_operand (1);
5882 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5884 /* Keep xmm0 for instructions with VEX prefix and 3
5890 /* We remove the first xmm0 and keep the number of
5891 operands unchanged, which in fact duplicates the
5893 for (j
= 1; j
< i
.operands
; j
++)
5895 i
.op
[j
- 1] = i
.op
[j
];
5896 i
.types
[j
- 1] = i
.types
[j
];
5897 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5901 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5903 gas_assert ((MAX_OPERANDS
- 1) > dupl
5904 && (i
.tm
.opcode_modifier
.vexsources
5907 /* Add the implicit xmm0 for instructions with VEX prefix
5909 for (j
= i
.operands
; j
> 0; j
--)
5911 i
.op
[j
] = i
.op
[j
- 1];
5912 i
.types
[j
] = i
.types
[j
- 1];
5913 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5916 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5917 i
.types
[0] = regxmm
;
5918 i
.tm
.operand_types
[0] = regxmm
;
5921 i
.reg_operands
+= 2;
5926 i
.op
[dupl
] = i
.op
[dest
];
5927 i
.types
[dupl
] = i
.types
[dest
];
5928 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5937 i
.op
[dupl
] = i
.op
[dest
];
5938 i
.types
[dupl
] = i
.types
[dest
];
5939 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5942 if (i
.tm
.opcode_modifier
.immext
)
5945 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5949 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5950 gas_assert (i
.reg_operands
5951 && (operand_type_equal (&i
.types
[0], ®xmm
)
5952 || operand_type_equal (&i
.types
[0], ®ymm
)
5953 || operand_type_equal (&i
.types
[0], ®zmm
)));
5954 if (register_number (i
.op
[0].regs
) != 0)
5955 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5957 for (j
= 1; j
< i
.operands
; j
++)
5959 i
.op
[j
- 1] = i
.op
[j
];
5960 i
.types
[j
- 1] = i
.types
[j
];
5962 /* We need to adjust fields in i.tm since they are used by
5963 build_modrm_byte. */
5964 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5971 else if (i
.tm
.opcode_modifier
.regkludge
)
5973 /* The imul $imm, %reg instruction is converted into
5974 imul $imm, %reg, %reg, and the clr %reg instruction
5975 is converted into xor %reg, %reg. */
5977 unsigned int first_reg_op
;
5979 if (operand_type_check (i
.types
[0], reg
))
5983 /* Pretend we saw the extra register operand. */
5984 gas_assert (i
.reg_operands
== 1
5985 && i
.op
[first_reg_op
+ 1].regs
== 0);
5986 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5987 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5992 if (i
.tm
.opcode_modifier
.shortform
)
5994 if (i
.types
[0].bitfield
.sreg2
5995 || i
.types
[0].bitfield
.sreg3
)
5997 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5998 && i
.op
[0].regs
->reg_num
== 1)
6000 as_bad (_("you can't `pop %scs'"), register_prefix
);
6003 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6004 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6009 /* The register or float register operand is in operand
6013 if (i
.types
[0].bitfield
.floatreg
6014 || operand_type_check (i
.types
[0], reg
))
6018 /* Register goes in low 3 bits of opcode. */
6019 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6020 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6022 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6024 /* Warn about some common errors, but press on regardless.
6025 The first case can be generated by gcc (<= 2.8.1). */
6026 if (i
.operands
== 2)
6028 /* Reversed arguments on faddp, fsubp, etc. */
6029 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6030 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6031 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6035 /* Extraneous `l' suffix on fp insn. */
6036 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6037 register_prefix
, i
.op
[0].regs
->reg_name
);
6042 else if (i
.tm
.opcode_modifier
.modrm
)
6044 /* The opcode is completed (modulo i.tm.extension_opcode which
6045 must be put into the modrm byte). Now, we make the modrm and
6046 index base bytes based on all the info we've collected. */
6048 default_seg
= build_modrm_byte ();
6050 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6054 else if (i
.tm
.opcode_modifier
.isstring
)
6056 /* For the string instructions that allow a segment override
6057 on one of their operands, the default segment is ds. */
6061 if (i
.tm
.base_opcode
== 0x8d /* lea */
6064 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6066 /* If a segment was explicitly specified, and the specified segment
6067 is not the default, use an opcode prefix to select it. If we
6068 never figured out what the default segment is, then default_seg
6069 will be zero at this point, and the specified segment prefix will
6071 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6073 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6079 static const seg_entry
*
6080 build_modrm_byte (void)
6082 const seg_entry
*default_seg
= 0;
6083 unsigned int source
, dest
;
6086 /* The first operand of instructions with VEX prefix and 3 sources
6087 must be VEX_Imm4. */
6088 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6091 unsigned int nds
, reg_slot
;
6094 if (i
.tm
.opcode_modifier
.veximmext
6095 && i
.tm
.opcode_modifier
.immext
)
6097 dest
= i
.operands
- 2;
6098 gas_assert (dest
== 3);
6101 dest
= i
.operands
- 1;
6104 /* There are 2 kinds of instructions:
6105 1. 5 operands: 4 register operands or 3 register operands
6106 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6107 VexW0 or VexW1. The destination must be either XMM, YMM or
6109 2. 4 operands: 4 register operands or 3 register operands
6110 plus 1 memory operand, VexXDS, and VexImmExt */
6111 gas_assert ((i
.reg_operands
== 4
6112 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6113 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6114 && (i
.tm
.opcode_modifier
.veximmext
6115 || (i
.imm_operands
== 1
6116 && i
.types
[0].bitfield
.vec_imm4
6117 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6118 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6119 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6120 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6121 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6123 if (i
.imm_operands
== 0)
6125 /* When there is no immediate operand, generate an 8bit
6126 immediate operand to encode the first operand. */
6127 exp
= &im_expressions
[i
.imm_operands
++];
6128 i
.op
[i
.operands
].imms
= exp
;
6129 i
.types
[i
.operands
] = imm8
;
6131 /* If VexW1 is set, the first operand is the source and
6132 the second operand is encoded in the immediate operand. */
6133 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6144 /* FMA swaps REG and NDS. */
6145 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6153 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6155 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6157 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6159 exp
->X_op
= O_constant
;
6160 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6161 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6165 unsigned int imm_slot
;
6167 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6169 /* If VexW0 is set, the third operand is the source and
6170 the second operand is encoded in the immediate
6177 /* VexW1 is set, the second operand is the source and
6178 the third operand is encoded in the immediate
6184 if (i
.tm
.opcode_modifier
.immext
)
6186 /* When ImmExt is set, the immdiate byte is the last
6188 imm_slot
= i
.operands
- 1;
6196 /* Turn on Imm8 so that output_imm will generate it. */
6197 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6200 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6202 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6204 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6206 i
.op
[imm_slot
].imms
->X_add_number
6207 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6208 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6211 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6212 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6214 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6216 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6221 /* i.reg_operands MUST be the number of real register operands;
6222 implicit registers do not count. If there are 3 register
6223 operands, it must be a instruction with VexNDS. For a
6224 instruction with VexNDD, the destination register is encoded
6225 in VEX prefix. If there are 4 register operands, it must be
6226 a instruction with VEX prefix and 3 sources. */
6227 if (i
.mem_operands
== 0
6228 && ((i
.reg_operands
== 2
6229 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6230 || (i
.reg_operands
== 3
6231 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6232 || (i
.reg_operands
== 4 && vex_3_sources
)))
6240 /* When there are 3 operands, one of them may be immediate,
6241 which may be the first or the last operand. Otherwise,
6242 the first operand must be shift count register (cl) or it
6243 is an instruction with VexNDS. */
6244 gas_assert (i
.imm_operands
== 1
6245 || (i
.imm_operands
== 0
6246 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6247 || i
.types
[0].bitfield
.shiftcount
)));
6248 if (operand_type_check (i
.types
[0], imm
)
6249 || i
.types
[0].bitfield
.shiftcount
)
6255 /* When there are 4 operands, the first two must be 8bit
6256 immediate operands. The source operand will be the 3rd
6259 For instructions with VexNDS, if the first operand
6260 an imm8, the source operand is the 2nd one. If the last
6261 operand is imm8, the source operand is the first one. */
6262 gas_assert ((i
.imm_operands
== 2
6263 && i
.types
[0].bitfield
.imm8
6264 && i
.types
[1].bitfield
.imm8
)
6265 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6266 && i
.imm_operands
== 1
6267 && (i
.types
[0].bitfield
.imm8
6268 || i
.types
[i
.operands
- 1].bitfield
.imm8
6270 if (i
.imm_operands
== 2)
6274 if (i
.types
[0].bitfield
.imm8
)
6281 if (i
.tm
.opcode_modifier
.evex
)
6283 /* For EVEX instructions, when there are 5 operands, the
6284 first one must be immediate operand. If the second one
6285 is immediate operand, the source operand is the 3th
6286 one. If the last one is immediate operand, the source
6287 operand is the 2nd one. */
6288 gas_assert (i
.imm_operands
== 2
6289 && i
.tm
.opcode_modifier
.sae
6290 && operand_type_check (i
.types
[0], imm
));
6291 if (operand_type_check (i
.types
[1], imm
))
6293 else if (operand_type_check (i
.types
[4], imm
))
6307 /* RC/SAE operand could be between DEST and SRC. That happens
6308 when one operand is GPR and the other one is XMM/YMM/ZMM
6310 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6313 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6315 /* For instructions with VexNDS, the register-only source
6316 operand must be 32/64bit integer, XMM, YMM or ZMM
6317 register. It is encoded in VEX prefix. We need to
6318 clear RegMem bit before calling operand_type_equal. */
6320 i386_operand_type op
;
6323 /* Check register-only source operand when two source
6324 operands are swapped. */
6325 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6326 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6334 op
= i
.tm
.operand_types
[vvvv
];
6335 op
.bitfield
.regmem
= 0;
6336 if ((dest
+ 1) >= i
.operands
6337 || (!op
.bitfield
.reg32
6338 && op
.bitfield
.reg64
6339 && !operand_type_equal (&op
, ®xmm
)
6340 && !operand_type_equal (&op
, ®ymm
)
6341 && !operand_type_equal (&op
, ®zmm
)
6342 && !operand_type_equal (&op
, ®mask
)))
6344 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6350 /* One of the register operands will be encoded in the i.tm.reg
6351 field, the other in the combined i.tm.mode and i.tm.regmem
6352 fields. If no form of this instruction supports a memory
6353 destination operand, then we assume the source operand may
6354 sometimes be a memory operand and so we need to store the
6355 destination in the i.rm.reg field. */
6356 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6357 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6359 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6360 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6361 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6363 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6365 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6367 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6372 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6373 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6374 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6376 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6378 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6380 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6383 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6385 if (!i
.types
[0].bitfield
.control
6386 && !i
.types
[1].bitfield
.control
)
6388 i
.rex
&= ~(REX_R
| REX_B
);
6389 add_prefix (LOCK_PREFIX_OPCODE
);
6393 { /* If it's not 2 reg operands... */
6398 unsigned int fake_zero_displacement
= 0;
6401 for (op
= 0; op
< i
.operands
; op
++)
6402 if (operand_type_check (i
.types
[op
], anymem
))
6404 gas_assert (op
< i
.operands
);
6406 if (i
.tm
.opcode_modifier
.vecsib
)
6408 if (i
.index_reg
->reg_num
== RegEiz
6409 || i
.index_reg
->reg_num
== RegRiz
)
6412 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6415 i
.sib
.base
= NO_BASE_REGISTER
;
6416 i
.sib
.scale
= i
.log2_scale_factor
;
6417 /* No Vec_Disp8 if there is no base. */
6418 i
.types
[op
].bitfield
.vec_disp8
= 0;
6419 i
.types
[op
].bitfield
.disp8
= 0;
6420 i
.types
[op
].bitfield
.disp16
= 0;
6421 i
.types
[op
].bitfield
.disp64
= 0;
6422 if (flag_code
!= CODE_64BIT
)
6424 /* Must be 32 bit */
6425 i
.types
[op
].bitfield
.disp32
= 1;
6426 i
.types
[op
].bitfield
.disp32s
= 0;
6430 i
.types
[op
].bitfield
.disp32
= 0;
6431 i
.types
[op
].bitfield
.disp32s
= 1;
6434 i
.sib
.index
= i
.index_reg
->reg_num
;
6435 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6437 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6443 if (i
.base_reg
== 0)
6446 if (!i
.disp_operands
)
6448 fake_zero_displacement
= 1;
6449 /* Instructions with VSIB byte need 32bit displacement
6450 if there is no base register. */
6451 if (i
.tm
.opcode_modifier
.vecsib
)
6452 i
.types
[op
].bitfield
.disp32
= 1;
6454 if (i
.index_reg
== 0)
6456 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6457 /* Operand is just <disp> */
6458 if (flag_code
== CODE_64BIT
)
6460 /* 64bit mode overwrites the 32bit absolute
6461 addressing by RIP relative addressing and
6462 absolute addressing is encoded by one of the
6463 redundant SIB forms. */
6464 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6465 i
.sib
.base
= NO_BASE_REGISTER
;
6466 i
.sib
.index
= NO_INDEX_REGISTER
;
6467 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6468 ? disp32s
: disp32
);
6470 else if ((flag_code
== CODE_16BIT
)
6471 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6473 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6474 i
.types
[op
] = disp16
;
6478 i
.rm
.regmem
= NO_BASE_REGISTER
;
6479 i
.types
[op
] = disp32
;
6482 else if (!i
.tm
.opcode_modifier
.vecsib
)
6484 /* !i.base_reg && i.index_reg */
6485 if (i
.index_reg
->reg_num
== RegEiz
6486 || i
.index_reg
->reg_num
== RegRiz
)
6487 i
.sib
.index
= NO_INDEX_REGISTER
;
6489 i
.sib
.index
= i
.index_reg
->reg_num
;
6490 i
.sib
.base
= NO_BASE_REGISTER
;
6491 i
.sib
.scale
= i
.log2_scale_factor
;
6492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6493 /* No Vec_Disp8 if there is no base. */
6494 i
.types
[op
].bitfield
.vec_disp8
= 0;
6495 i
.types
[op
].bitfield
.disp8
= 0;
6496 i
.types
[op
].bitfield
.disp16
= 0;
6497 i
.types
[op
].bitfield
.disp64
= 0;
6498 if (flag_code
!= CODE_64BIT
)
6500 /* Must be 32 bit */
6501 i
.types
[op
].bitfield
.disp32
= 1;
6502 i
.types
[op
].bitfield
.disp32s
= 0;
6506 i
.types
[op
].bitfield
.disp32
= 0;
6507 i
.types
[op
].bitfield
.disp32s
= 1;
6509 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6513 /* RIP addressing for 64bit mode. */
6514 else if (i
.base_reg
->reg_num
== RegRip
||
6515 i
.base_reg
->reg_num
== RegEip
)
6517 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6518 i
.rm
.regmem
= NO_BASE_REGISTER
;
6519 i
.types
[op
].bitfield
.disp8
= 0;
6520 i
.types
[op
].bitfield
.disp16
= 0;
6521 i
.types
[op
].bitfield
.disp32
= 0;
6522 i
.types
[op
].bitfield
.disp32s
= 1;
6523 i
.types
[op
].bitfield
.disp64
= 0;
6524 i
.types
[op
].bitfield
.vec_disp8
= 0;
6525 i
.flags
[op
] |= Operand_PCrel
;
6526 if (! i
.disp_operands
)
6527 fake_zero_displacement
= 1;
6529 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6531 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6532 switch (i
.base_reg
->reg_num
)
6535 if (i
.index_reg
== 0)
6537 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6538 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6542 if (i
.index_reg
== 0)
6545 if (operand_type_check (i
.types
[op
], disp
) == 0)
6547 /* fake (%bp) into 0(%bp) */
6548 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6549 i
.types
[op
].bitfield
.vec_disp8
= 1;
6551 i
.types
[op
].bitfield
.disp8
= 1;
6552 fake_zero_displacement
= 1;
6555 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6556 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6558 default: /* (%si) -> 4 or (%di) -> 5 */
6559 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6561 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6563 else /* i.base_reg and 32/64 bit mode */
6565 if (flag_code
== CODE_64BIT
6566 && operand_type_check (i
.types
[op
], disp
))
6568 i386_operand_type temp
;
6569 operand_type_set (&temp
, 0);
6570 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6571 temp
.bitfield
.vec_disp8
6572 = i
.types
[op
].bitfield
.vec_disp8
;
6574 if (i
.prefix
[ADDR_PREFIX
] == 0)
6575 i
.types
[op
].bitfield
.disp32s
= 1;
6577 i
.types
[op
].bitfield
.disp32
= 1;
6580 if (!i
.tm
.opcode_modifier
.vecsib
)
6581 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6582 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6584 i
.sib
.base
= i
.base_reg
->reg_num
;
6585 /* x86-64 ignores REX prefix bit here to avoid decoder
6587 if (!(i
.base_reg
->reg_flags
& RegRex
)
6588 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6589 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6591 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6593 fake_zero_displacement
= 1;
6594 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6595 i
.types
[op
].bitfield
.vec_disp8
= 1;
6597 i
.types
[op
].bitfield
.disp8
= 1;
6599 i
.sib
.scale
= i
.log2_scale_factor
;
6600 if (i
.index_reg
== 0)
6602 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6603 /* <disp>(%esp) becomes two byte modrm with no index
6604 register. We've already stored the code for esp
6605 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6606 Any base register besides %esp will not use the
6607 extra modrm byte. */
6608 i
.sib
.index
= NO_INDEX_REGISTER
;
6610 else if (!i
.tm
.opcode_modifier
.vecsib
)
6612 if (i
.index_reg
->reg_num
== RegEiz
6613 || i
.index_reg
->reg_num
== RegRiz
)
6614 i
.sib
.index
= NO_INDEX_REGISTER
;
6616 i
.sib
.index
= i
.index_reg
->reg_num
;
6617 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6618 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6623 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6624 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6628 if (!fake_zero_displacement
6632 fake_zero_displacement
= 1;
6633 if (i
.disp_encoding
== disp_encoding_8bit
)
6634 i
.types
[op
].bitfield
.disp8
= 1;
6636 i
.types
[op
].bitfield
.disp32
= 1;
6638 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6642 if (fake_zero_displacement
)
6644 /* Fakes a zero displacement assuming that i.types[op]
6645 holds the correct displacement size. */
6648 gas_assert (i
.op
[op
].disps
== 0);
6649 exp
= &disp_expressions
[i
.disp_operands
++];
6650 i
.op
[op
].disps
= exp
;
6651 exp
->X_op
= O_constant
;
6652 exp
->X_add_number
= 0;
6653 exp
->X_add_symbol
= (symbolS
*) 0;
6654 exp
->X_op_symbol
= (symbolS
*) 0;
6662 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6664 if (operand_type_check (i
.types
[0], imm
))
6665 i
.vex
.register_specifier
= NULL
;
6668 /* VEX.vvvv encodes one of the sources when the first
6669 operand is not an immediate. */
6670 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6671 i
.vex
.register_specifier
= i
.op
[0].regs
;
6673 i
.vex
.register_specifier
= i
.op
[1].regs
;
6676 /* Destination is a XMM register encoded in the ModRM.reg
6678 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6679 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6682 /* ModRM.rm and VEX.B encodes the other source. */
6683 if (!i
.mem_operands
)
6687 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6688 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6690 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6692 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6696 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6698 i
.vex
.register_specifier
= i
.op
[2].regs
;
6699 if (!i
.mem_operands
)
6702 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6703 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6707 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6708 (if any) based on i.tm.extension_opcode. Again, we must be
6709 careful to make sure that segment/control/debug/test/MMX
6710 registers are coded into the i.rm.reg field. */
6711 else if (i
.reg_operands
)
6714 unsigned int vex_reg
= ~0;
6716 for (op
= 0; op
< i
.operands
; op
++)
6717 if (i
.types
[op
].bitfield
.reg8
6718 || i
.types
[op
].bitfield
.reg16
6719 || i
.types
[op
].bitfield
.reg32
6720 || i
.types
[op
].bitfield
.reg64
6721 || i
.types
[op
].bitfield
.regmmx
6722 || i
.types
[op
].bitfield
.regxmm
6723 || i
.types
[op
].bitfield
.regymm
6724 || i
.types
[op
].bitfield
.regbnd
6725 || i
.types
[op
].bitfield
.regzmm
6726 || i
.types
[op
].bitfield
.regmask
6727 || i
.types
[op
].bitfield
.sreg2
6728 || i
.types
[op
].bitfield
.sreg3
6729 || i
.types
[op
].bitfield
.control
6730 || i
.types
[op
].bitfield
.debug
6731 || i
.types
[op
].bitfield
.test
)
6736 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6738 /* For instructions with VexNDS, the register-only
6739 source operand is encoded in VEX prefix. */
6740 gas_assert (mem
!= (unsigned int) ~0);
6745 gas_assert (op
< i
.operands
);
6749 /* Check register-only source operand when two source
6750 operands are swapped. */
6751 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6752 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6756 gas_assert (mem
== (vex_reg
+ 1)
6757 && op
< i
.operands
);
6762 gas_assert (vex_reg
< i
.operands
);
6766 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6768 /* For instructions with VexNDD, the register destination
6769 is encoded in VEX prefix. */
6770 if (i
.mem_operands
== 0)
6772 /* There is no memory operand. */
6773 gas_assert ((op
+ 2) == i
.operands
);
6778 /* There are only 2 operands. */
6779 gas_assert (op
< 2 && i
.operands
== 2);
6784 gas_assert (op
< i
.operands
);
6786 if (vex_reg
!= (unsigned int) ~0)
6788 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6790 if (type
->bitfield
.reg32
!= 1
6791 && type
->bitfield
.reg64
!= 1
6792 && !operand_type_equal (type
, ®xmm
)
6793 && !operand_type_equal (type
, ®ymm
)
6794 && !operand_type_equal (type
, ®zmm
)
6795 && !operand_type_equal (type
, ®mask
))
6798 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6801 /* Don't set OP operand twice. */
6804 /* If there is an extension opcode to put here, the
6805 register number must be put into the regmem field. */
6806 if (i
.tm
.extension_opcode
!= None
)
6808 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6809 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6811 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6816 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6817 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6819 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6824 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6825 must set it to 3 to indicate this is a register operand
6826 in the regmem field. */
6827 if (!i
.mem_operands
)
6831 /* Fill in i.rm.reg field with extension opcode (if any). */
6832 if (i
.tm
.extension_opcode
!= None
)
6833 i
.rm
.reg
= i
.tm
.extension_opcode
;
6839 output_branch (void)
6845 relax_substateT subtype
;
6849 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6850 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6853 if (i
.prefix
[DATA_PREFIX
] != 0)
6859 /* Pentium4 branch hints. */
6860 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6861 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6866 if (i
.prefix
[REX_PREFIX
] != 0)
6872 /* BND prefixed jump. */
6873 if (i
.prefix
[BND_PREFIX
] != 0)
6875 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6879 if (i
.prefixes
!= 0 && !intel_syntax
)
6880 as_warn (_("skipping prefixes on this instruction"));
6882 /* It's always a symbol; End frag & setup for relax.
6883 Make sure there is enough room in this frag for the largest
6884 instruction we may generate in md_convert_frag. This is 2
6885 bytes for the opcode and room for the prefix and largest
6887 frag_grow (prefix
+ 2 + 4);
6888 /* Prefix and 1 opcode byte go in fr_fix. */
6889 p
= frag_more (prefix
+ 1);
6890 if (i
.prefix
[DATA_PREFIX
] != 0)
6891 *p
++ = DATA_PREFIX_OPCODE
;
6892 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6893 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6894 *p
++ = i
.prefix
[SEG_PREFIX
];
6895 if (i
.prefix
[REX_PREFIX
] != 0)
6896 *p
++ = i
.prefix
[REX_PREFIX
];
6897 *p
= i
.tm
.base_opcode
;
6899 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6900 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6901 else if (cpu_arch_flags
.bitfield
.cpui386
)
6902 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6904 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6907 sym
= i
.op
[0].disps
->X_add_symbol
;
6908 off
= i
.op
[0].disps
->X_add_number
;
6910 if (i
.op
[0].disps
->X_op
!= O_constant
6911 && i
.op
[0].disps
->X_op
!= O_symbol
)
6913 /* Handle complex expressions. */
6914 sym
= make_expr_symbol (i
.op
[0].disps
);
6918 /* 1 possible extra opcode + 4 byte displacement go in var part.
6919 Pass reloc in fr_var. */
6920 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6930 if (i
.tm
.opcode_modifier
.jumpbyte
)
6932 /* This is a loop or jecxz type instruction. */
6934 if (i
.prefix
[ADDR_PREFIX
] != 0)
6936 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6939 /* Pentium4 branch hints. */
6940 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6941 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6943 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6952 if (flag_code
== CODE_16BIT
)
6955 if (i
.prefix
[DATA_PREFIX
] != 0)
6957 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6967 if (i
.prefix
[REX_PREFIX
] != 0)
6969 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6973 /* BND prefixed jump. */
6974 if (i
.prefix
[BND_PREFIX
] != 0)
6976 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6980 if (i
.prefixes
!= 0 && !intel_syntax
)
6981 as_warn (_("skipping prefixes on this instruction"));
6983 p
= frag_more (i
.tm
.opcode_length
+ size
);
6984 switch (i
.tm
.opcode_length
)
6987 *p
++ = i
.tm
.base_opcode
>> 8;
6990 *p
++ = i
.tm
.base_opcode
;
6996 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6997 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6999 /* All jumps handled here are signed, but don't use a signed limit
7000 check for 32 and 16 bit jumps as we want to allow wrap around at
7001 4G and 64k respectively. */
7003 fixP
->fx_signed
= 1;
7007 output_interseg_jump (void)
7015 if (flag_code
== CODE_16BIT
)
7019 if (i
.prefix
[DATA_PREFIX
] != 0)
7025 if (i
.prefix
[REX_PREFIX
] != 0)
7035 if (i
.prefixes
!= 0 && !intel_syntax
)
7036 as_warn (_("skipping prefixes on this instruction"));
7038 /* 1 opcode; 2 segment; offset */
7039 p
= frag_more (prefix
+ 1 + 2 + size
);
7041 if (i
.prefix
[DATA_PREFIX
] != 0)
7042 *p
++ = DATA_PREFIX_OPCODE
;
7044 if (i
.prefix
[REX_PREFIX
] != 0)
7045 *p
++ = i
.prefix
[REX_PREFIX
];
7047 *p
++ = i
.tm
.base_opcode
;
7048 if (i
.op
[1].imms
->X_op
== O_constant
)
7050 offsetT n
= i
.op
[1].imms
->X_add_number
;
7053 && !fits_in_unsigned_word (n
)
7054 && !fits_in_signed_word (n
))
7056 as_bad (_("16-bit jump out of range"));
7059 md_number_to_chars (p
, n
, size
);
7062 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7063 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7064 if (i
.op
[0].imms
->X_op
!= O_constant
)
7065 as_bad (_("can't handle non absolute segment in `%s'"),
7067 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7073 fragS
*insn_start_frag
;
7074 offsetT insn_start_off
;
7076 /* Tie dwarf2 debug info to the address at the start of the insn.
7077 We can't do this after the insn has been output as the current
7078 frag may have been closed off. eg. by frag_var. */
7079 dwarf2_emit_insn (0);
7081 insn_start_frag
= frag_now
;
7082 insn_start_off
= frag_now_fix ();
7085 if (i
.tm
.opcode_modifier
.jump
)
7087 else if (i
.tm
.opcode_modifier
.jumpbyte
7088 || i
.tm
.opcode_modifier
.jumpdword
)
7090 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7091 output_interseg_jump ();
7094 /* Output normal instructions here. */
7098 unsigned int prefix
;
7101 && i
.tm
.base_opcode
== 0xfae
7103 && i
.imm_operands
== 1
7104 && (i
.op
[0].imms
->X_add_number
== 0xe8
7105 || i
.op
[0].imms
->X_add_number
== 0xf0
7106 || i
.op
[0].imms
->X_add_number
== 0xf8))
7108 /* Encode lfence, mfence, and sfence as
7109 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7110 offsetT val
= 0x240483f0ULL
;
7112 md_number_to_chars (p
, val
, 5);
7116 /* Some processors fail on LOCK prefix. This options makes
7117 assembler ignore LOCK prefix and serves as a workaround. */
7118 if (omit_lock_prefix
)
7120 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7122 i
.prefix
[LOCK_PREFIX
] = 0;
7125 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7126 don't need the explicit prefix. */
7127 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7129 switch (i
.tm
.opcode_length
)
7132 if (i
.tm
.base_opcode
& 0xff000000)
7134 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7139 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7141 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7142 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7145 if (prefix
!= REPE_PREFIX_OPCODE
7146 || (i
.prefix
[REP_PREFIX
]
7147 != REPE_PREFIX_OPCODE
))
7148 add_prefix (prefix
);
7151 add_prefix (prefix
);
7160 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7161 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7162 R_X86_64_GOTTPOFF relocation so that linker can safely
7163 perform IE->LE optimization. */
7164 if (x86_elf_abi
== X86_64_X32_ABI
7166 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7167 && i
.prefix
[REX_PREFIX
] == 0)
7168 add_prefix (REX_OPCODE
);
7171 /* The prefix bytes. */
7172 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7174 FRAG_APPEND_1_CHAR (*q
);
7178 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7183 /* REX byte is encoded in VEX prefix. */
7187 FRAG_APPEND_1_CHAR (*q
);
7190 /* There should be no other prefixes for instructions
7195 /* For EVEX instructions i.vrex should become 0 after
7196 build_evex_prefix. For VEX instructions upper 16 registers
7197 aren't available, so VREX should be 0. */
7200 /* Now the VEX prefix. */
7201 p
= frag_more (i
.vex
.length
);
7202 for (j
= 0; j
< i
.vex
.length
; j
++)
7203 p
[j
] = i
.vex
.bytes
[j
];
7206 /* Now the opcode; be careful about word order here! */
7207 if (i
.tm
.opcode_length
== 1)
7209 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7213 switch (i
.tm
.opcode_length
)
7217 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7218 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7222 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7232 /* Put out high byte first: can't use md_number_to_chars! */
7233 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7234 *p
= i
.tm
.base_opcode
& 0xff;
7237 /* Now the modrm byte and sib byte (if present). */
7238 if (i
.tm
.opcode_modifier
.modrm
)
7240 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7243 /* If i.rm.regmem == ESP (4)
7244 && i.rm.mode != (Register mode)
7246 ==> need second modrm byte. */
7247 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7249 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7250 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7252 | i
.sib
.scale
<< 6));
7255 if (i
.disp_operands
)
7256 output_disp (insn_start_frag
, insn_start_off
);
7259 output_imm (insn_start_frag
, insn_start_off
);
7265 pi ("" /*line*/, &i
);
7267 #endif /* DEBUG386 */
7270 /* Return the size of the displacement operand N. */
7273 disp_size (unsigned int n
)
7277 /* Vec_Disp8 has to be 8bit. */
7278 if (i
.types
[n
].bitfield
.vec_disp8
)
7280 else if (i
.types
[n
].bitfield
.disp64
)
7282 else if (i
.types
[n
].bitfield
.disp8
)
7284 else if (i
.types
[n
].bitfield
.disp16
)
7289 /* Return the size of the immediate operand N. */
7292 imm_size (unsigned int n
)
7295 if (i
.types
[n
].bitfield
.imm64
)
7297 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7299 else if (i
.types
[n
].bitfield
.imm16
)
7305 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7310 for (n
= 0; n
< i
.operands
; n
++)
7312 if (i
.types
[n
].bitfield
.vec_disp8
7313 || operand_type_check (i
.types
[n
], disp
))
7315 if (i
.op
[n
].disps
->X_op
== O_constant
)
7317 int size
= disp_size (n
);
7318 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7320 if (i
.types
[n
].bitfield
.vec_disp8
)
7322 val
= offset_in_range (val
, size
);
7323 p
= frag_more (size
);
7324 md_number_to_chars (p
, val
, size
);
7328 enum bfd_reloc_code_real reloc_type
;
7329 int size
= disp_size (n
);
7330 int sign
= i
.types
[n
].bitfield
.disp32s
;
7331 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7334 /* We can't have 8 bit displacement here. */
7335 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7337 /* The PC relative address is computed relative
7338 to the instruction boundary, so in case immediate
7339 fields follows, we need to adjust the value. */
7340 if (pcrel
&& i
.imm_operands
)
7345 for (n1
= 0; n1
< i
.operands
; n1
++)
7346 if (operand_type_check (i
.types
[n1
], imm
))
7348 /* Only one immediate is allowed for PC
7349 relative address. */
7350 gas_assert (sz
== 0);
7352 i
.op
[n
].disps
->X_add_number
-= sz
;
7354 /* We should find the immediate. */
7355 gas_assert (sz
!= 0);
7358 p
= frag_more (size
);
7359 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7361 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7362 && (((reloc_type
== BFD_RELOC_32
7363 || reloc_type
== BFD_RELOC_X86_64_32S
7364 || (reloc_type
== BFD_RELOC_64
7366 && (i
.op
[n
].disps
->X_op
== O_symbol
7367 || (i
.op
[n
].disps
->X_op
== O_add
7368 && ((symbol_get_value_expression
7369 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7371 || reloc_type
== BFD_RELOC_32_PCREL
))
7375 if (insn_start_frag
== frag_now
)
7376 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7381 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7382 for (fr
= insn_start_frag
->fr_next
;
7383 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7385 add
+= p
- frag_now
->fr_literal
;
7390 reloc_type
= BFD_RELOC_386_GOTPC
;
7391 i
.op
[n
].imms
->X_add_number
+= add
;
7393 else if (reloc_type
== BFD_RELOC_64
)
7394 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7396 /* Don't do the adjustment for x86-64, as there
7397 the pcrel addressing is relative to the _next_
7398 insn, and that is taken care of in other code. */
7399 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7401 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7402 size
, i
.op
[n
].disps
, pcrel
,
7404 /* Check for "call/jmp *mem", "mov mem, %reg",
7405 "test %reg, mem" and "binop mem, %reg" where binop
7406 is one of adc, add, and, cmp, or, sbb, sub, xor
7407 instructions. Always generate R_386_GOT32X for
7408 "sym*GOT" operand in 32-bit mode. */
7409 if ((generate_relax_relocations
7412 && i
.rm
.regmem
== 5))
7414 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7415 && ((i
.operands
== 1
7416 && i
.tm
.base_opcode
== 0xff
7417 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7419 && (i
.tm
.base_opcode
== 0x8b
7420 || i
.tm
.base_opcode
== 0x85
7421 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7425 fixP
->fx_tcbit
= i
.rex
!= 0;
7427 && (i
.base_reg
->reg_num
== RegRip
7428 || i
.base_reg
->reg_num
== RegEip
))
7429 fixP
->fx_tcbit2
= 1;
7432 fixP
->fx_tcbit2
= 1;
7440 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7445 for (n
= 0; n
< i
.operands
; n
++)
7447 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7448 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7451 if (operand_type_check (i
.types
[n
], imm
))
7453 if (i
.op
[n
].imms
->X_op
== O_constant
)
7455 int size
= imm_size (n
);
7458 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7460 p
= frag_more (size
);
7461 md_number_to_chars (p
, val
, size
);
7465 /* Not absolute_section.
7466 Need a 32-bit fixup (don't support 8bit
7467 non-absolute imms). Try to support other
7469 enum bfd_reloc_code_real reloc_type
;
7470 int size
= imm_size (n
);
7473 if (i
.types
[n
].bitfield
.imm32s
7474 && (i
.suffix
== QWORD_MNEM_SUFFIX
7475 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7480 p
= frag_more (size
);
7481 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7483 /* This is tough to explain. We end up with this one if we
7484 * have operands that look like
7485 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7486 * obtain the absolute address of the GOT, and it is strongly
7487 * preferable from a performance point of view to avoid using
7488 * a runtime relocation for this. The actual sequence of
7489 * instructions often look something like:
7494 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7496 * The call and pop essentially return the absolute address
7497 * of the label .L66 and store it in %ebx. The linker itself
7498 * will ultimately change the first operand of the addl so
7499 * that %ebx points to the GOT, but to keep things simple, the
7500 * .o file must have this operand set so that it generates not
7501 * the absolute address of .L66, but the absolute address of
7502 * itself. This allows the linker itself simply treat a GOTPC
7503 * relocation as asking for a pcrel offset to the GOT to be
7504 * added in, and the addend of the relocation is stored in the
7505 * operand field for the instruction itself.
7507 * Our job here is to fix the operand so that it would add
7508 * the correct offset so that %ebx would point to itself. The
7509 * thing that is tricky is that .-.L66 will point to the
7510 * beginning of the instruction, so we need to further modify
7511 * the operand so that it will point to itself. There are
7512 * other cases where you have something like:
7514 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7516 * and here no correction would be required. Internally in
7517 * the assembler we treat operands of this form as not being
7518 * pcrel since the '.' is explicitly mentioned, and I wonder
7519 * whether it would simplify matters to do it this way. Who
7520 * knows. In earlier versions of the PIC patches, the
7521 * pcrel_adjust field was used to store the correction, but
7522 * since the expression is not pcrel, I felt it would be
7523 * confusing to do it this way. */
7525 if ((reloc_type
== BFD_RELOC_32
7526 || reloc_type
== BFD_RELOC_X86_64_32S
7527 || reloc_type
== BFD_RELOC_64
)
7529 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7530 && (i
.op
[n
].imms
->X_op
== O_symbol
7531 || (i
.op
[n
].imms
->X_op
== O_add
7532 && ((symbol_get_value_expression
7533 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7538 if (insn_start_frag
== frag_now
)
7539 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7544 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7545 for (fr
= insn_start_frag
->fr_next
;
7546 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7548 add
+= p
- frag_now
->fr_literal
;
7552 reloc_type
= BFD_RELOC_386_GOTPC
;
7554 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7556 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7557 i
.op
[n
].imms
->X_add_number
+= add
;
7559 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7560 i
.op
[n
].imms
, 0, reloc_type
);
7566 /* x86_cons_fix_new is called via the expression parsing code when a
7567 reloc is needed. We use this hook to get the correct .got reloc. */
7568 static int cons_sign
= -1;
7571 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7572 expressionS
*exp
, bfd_reloc_code_real_type r
)
7574 r
= reloc (len
, 0, cons_sign
, r
);
7577 if (exp
->X_op
== O_secrel
)
7579 exp
->X_op
= O_symbol
;
7580 r
= BFD_RELOC_32_SECREL
;
7584 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7587 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7588 purpose of the `.dc.a' internal pseudo-op. */
7591 x86_address_bytes (void)
7593 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7595 return stdoutput
->arch_info
->bits_per_address
/ 8;
7598 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7600 # define lex_got(reloc, adjust, types) NULL
7602 /* Parse operands of the form
7603 <symbol>@GOTOFF+<nnn>
7604 and similar .plt or .got references.
7606 If we find one, set up the correct relocation in RELOC and copy the
7607 input string, minus the `@GOTOFF' into a malloc'd buffer for
7608 parsing by the calling routine. Return this buffer, and if ADJUST
7609 is non-null set it to the length of the string we removed from the
7610 input line. Otherwise return NULL. */
7612 lex_got (enum bfd_reloc_code_real
*rel
,
7614 i386_operand_type
*types
)
7616 /* Some of the relocations depend on the size of what field is to
7617 be relocated. But in our callers i386_immediate and i386_displacement
7618 we don't yet know the operand size (this will be set by insn
7619 matching). Hence we record the word32 relocation here,
7620 and adjust the reloc according to the real size in reloc(). */
7621 static const struct {
7624 const enum bfd_reloc_code_real rel
[2];
7625 const i386_operand_type types64
;
7627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7628 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7630 OPERAND_TYPE_IMM32_64
},
7632 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7633 BFD_RELOC_X86_64_PLTOFF64
},
7634 OPERAND_TYPE_IMM64
},
7635 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7636 BFD_RELOC_X86_64_PLT32
},
7637 OPERAND_TYPE_IMM32_32S_DISP32
},
7638 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7639 BFD_RELOC_X86_64_GOTPLT64
},
7640 OPERAND_TYPE_IMM64_DISP64
},
7641 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7642 BFD_RELOC_X86_64_GOTOFF64
},
7643 OPERAND_TYPE_IMM64_DISP64
},
7644 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7645 BFD_RELOC_X86_64_GOTPCREL
},
7646 OPERAND_TYPE_IMM32_32S_DISP32
},
7647 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7648 BFD_RELOC_X86_64_TLSGD
},
7649 OPERAND_TYPE_IMM32_32S_DISP32
},
7650 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7651 _dummy_first_bfd_reloc_code_real
},
7652 OPERAND_TYPE_NONE
},
7653 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7654 BFD_RELOC_X86_64_TLSLD
},
7655 OPERAND_TYPE_IMM32_32S_DISP32
},
7656 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7657 BFD_RELOC_X86_64_GOTTPOFF
},
7658 OPERAND_TYPE_IMM32_32S_DISP32
},
7659 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7660 BFD_RELOC_X86_64_TPOFF32
},
7661 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7662 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7663 _dummy_first_bfd_reloc_code_real
},
7664 OPERAND_TYPE_NONE
},
7665 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7666 BFD_RELOC_X86_64_DTPOFF32
},
7667 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7668 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7669 _dummy_first_bfd_reloc_code_real
},
7670 OPERAND_TYPE_NONE
},
7671 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7672 _dummy_first_bfd_reloc_code_real
},
7673 OPERAND_TYPE_NONE
},
7674 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7675 BFD_RELOC_X86_64_GOT32
},
7676 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7677 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7678 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7679 OPERAND_TYPE_IMM32_32S_DISP32
},
7680 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7681 BFD_RELOC_X86_64_TLSDESC_CALL
},
7682 OPERAND_TYPE_IMM32_32S_DISP32
},
7687 #if defined (OBJ_MAYBE_ELF)
7692 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7693 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7696 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7698 int len
= gotrel
[j
].len
;
7699 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7701 if (gotrel
[j
].rel
[object_64bit
] != 0)
7704 char *tmpbuf
, *past_reloc
;
7706 *rel
= gotrel
[j
].rel
[object_64bit
];
7710 if (flag_code
!= CODE_64BIT
)
7712 types
->bitfield
.imm32
= 1;
7713 types
->bitfield
.disp32
= 1;
7716 *types
= gotrel
[j
].types64
;
7719 if (j
!= 0 && GOT_symbol
== NULL
)
7720 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7722 /* The length of the first part of our input line. */
7723 first
= cp
- input_line_pointer
;
7725 /* The second part goes from after the reloc token until
7726 (and including) an end_of_line char or comma. */
7727 past_reloc
= cp
+ 1 + len
;
7729 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7731 second
= cp
+ 1 - past_reloc
;
7733 /* Allocate and copy string. The trailing NUL shouldn't
7734 be necessary, but be safe. */
7735 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7736 memcpy (tmpbuf
, input_line_pointer
, first
);
7737 if (second
!= 0 && *past_reloc
!= ' ')
7738 /* Replace the relocation token with ' ', so that
7739 errors like foo@GOTOFF1 will be detected. */
7740 tmpbuf
[first
++] = ' ';
7742 /* Increment length by 1 if the relocation token is
7747 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7748 tmpbuf
[first
+ second
] = '\0';
7752 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7753 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7758 /* Might be a symbol version string. Don't as_bad here. */
7767 /* Parse operands of the form
7768 <symbol>@SECREL32+<nnn>
7770 If we find one, set up the correct relocation in RELOC and copy the
7771 input string, minus the `@SECREL32' into a malloc'd buffer for
7772 parsing by the calling routine. Return this buffer, and if ADJUST
7773 is non-null set it to the length of the string we removed from the
7774 input line. Otherwise return NULL.
7776 This function is copied from the ELF version above adjusted for PE targets. */
7779 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7780 int *adjust ATTRIBUTE_UNUSED
,
7781 i386_operand_type
*types
)
7787 const enum bfd_reloc_code_real rel
[2];
7788 const i386_operand_type types64
;
7792 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7793 BFD_RELOC_32_SECREL
},
7794 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7800 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7801 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7804 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7806 int len
= gotrel
[j
].len
;
7808 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7810 if (gotrel
[j
].rel
[object_64bit
] != 0)
7813 char *tmpbuf
, *past_reloc
;
7815 *rel
= gotrel
[j
].rel
[object_64bit
];
7821 if (flag_code
!= CODE_64BIT
)
7823 types
->bitfield
.imm32
= 1;
7824 types
->bitfield
.disp32
= 1;
7827 *types
= gotrel
[j
].types64
;
7830 /* The length of the first part of our input line. */
7831 first
= cp
- input_line_pointer
;
7833 /* The second part goes from after the reloc token until
7834 (and including) an end_of_line char or comma. */
7835 past_reloc
= cp
+ 1 + len
;
7837 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7839 second
= cp
+ 1 - past_reloc
;
7841 /* Allocate and copy string. The trailing NUL shouldn't
7842 be necessary, but be safe. */
7843 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7844 memcpy (tmpbuf
, input_line_pointer
, first
);
7845 if (second
!= 0 && *past_reloc
!= ' ')
7846 /* Replace the relocation token with ' ', so that
7847 errors like foo@SECLREL321 will be detected. */
7848 tmpbuf
[first
++] = ' ';
7849 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7850 tmpbuf
[first
+ second
] = '\0';
7854 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7855 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7860 /* Might be a symbol version string. Don't as_bad here. */
7866 bfd_reloc_code_real_type
7867 x86_cons (expressionS
*exp
, int size
)
7869 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7871 intel_syntax
= -intel_syntax
;
7874 if (size
== 4 || (object_64bit
&& size
== 8))
7876 /* Handle @GOTOFF and the like in an expression. */
7878 char *gotfree_input_line
;
7881 save
= input_line_pointer
;
7882 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7883 if (gotfree_input_line
)
7884 input_line_pointer
= gotfree_input_line
;
7888 if (gotfree_input_line
)
7890 /* expression () has merrily parsed up to the end of line,
7891 or a comma - in the wrong buffer. Transfer how far
7892 input_line_pointer has moved to the right buffer. */
7893 input_line_pointer
= (save
7894 + (input_line_pointer
- gotfree_input_line
)
7896 free (gotfree_input_line
);
7897 if (exp
->X_op
== O_constant
7898 || exp
->X_op
== O_absent
7899 || exp
->X_op
== O_illegal
7900 || exp
->X_op
== O_register
7901 || exp
->X_op
== O_big
)
7903 char c
= *input_line_pointer
;
7904 *input_line_pointer
= 0;
7905 as_bad (_("missing or invalid expression `%s'"), save
);
7906 *input_line_pointer
= c
;
7913 intel_syntax
= -intel_syntax
;
7916 i386_intel_simplify (exp
);
7922 signed_cons (int size
)
7924 if (flag_code
== CODE_64BIT
)
7932 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7939 if (exp
.X_op
== O_symbol
)
7940 exp
.X_op
= O_secrel
;
7942 emit_expr (&exp
, 4);
7944 while (*input_line_pointer
++ == ',');
7946 input_line_pointer
--;
7947 demand_empty_rest_of_line ();
7951 /* Handle Vector operations. */
7954 check_VecOperations (char *op_string
, char *op_end
)
7956 const reg_entry
*mask
;
7961 && (op_end
== NULL
|| op_string
< op_end
))
7964 if (*op_string
== '{')
7968 /* Check broadcasts. */
7969 if (strncmp (op_string
, "1to", 3) == 0)
7974 goto duplicated_vec_op
;
7977 if (*op_string
== '8')
7978 bcst_type
= BROADCAST_1TO8
;
7979 else if (*op_string
== '4')
7980 bcst_type
= BROADCAST_1TO4
;
7981 else if (*op_string
== '2')
7982 bcst_type
= BROADCAST_1TO2
;
7983 else if (*op_string
== '1'
7984 && *(op_string
+1) == '6')
7986 bcst_type
= BROADCAST_1TO16
;
7991 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7996 broadcast_op
.type
= bcst_type
;
7997 broadcast_op
.operand
= this_operand
;
7998 i
.broadcast
= &broadcast_op
;
8000 /* Check masking operation. */
8001 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8003 /* k0 can't be used for write mask. */
8004 if (mask
->reg_num
== 0)
8006 as_bad (_("`%s' can't be used for write mask"),
8013 mask_op
.mask
= mask
;
8014 mask_op
.zeroing
= 0;
8015 mask_op
.operand
= this_operand
;
8021 goto duplicated_vec_op
;
8023 i
.mask
->mask
= mask
;
8025 /* Only "{z}" is allowed here. No need to check
8026 zeroing mask explicitly. */
8027 if (i
.mask
->operand
!= this_operand
)
8029 as_bad (_("invalid write mask `%s'"), saved
);
8036 /* Check zeroing-flag for masking operation. */
8037 else if (*op_string
== 'z')
8041 mask_op
.mask
= NULL
;
8042 mask_op
.zeroing
= 1;
8043 mask_op
.operand
= this_operand
;
8048 if (i
.mask
->zeroing
)
8051 as_bad (_("duplicated `%s'"), saved
);
8055 i
.mask
->zeroing
= 1;
8057 /* Only "{%k}" is allowed here. No need to check mask
8058 register explicitly. */
8059 if (i
.mask
->operand
!= this_operand
)
8061 as_bad (_("invalid zeroing-masking `%s'"),
8070 goto unknown_vec_op
;
8072 if (*op_string
!= '}')
8074 as_bad (_("missing `}' in `%s'"), saved
);
8081 /* We don't know this one. */
8082 as_bad (_("unknown vector operation: `%s'"), saved
);
8090 i386_immediate (char *imm_start
)
8092 char *save_input_line_pointer
;
8093 char *gotfree_input_line
;
8096 i386_operand_type types
;
8098 operand_type_set (&types
, ~0);
8100 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8102 as_bad (_("at most %d immediate operands are allowed"),
8103 MAX_IMMEDIATE_OPERANDS
);
8107 exp
= &im_expressions
[i
.imm_operands
++];
8108 i
.op
[this_operand
].imms
= exp
;
8110 if (is_space_char (*imm_start
))
8113 save_input_line_pointer
= input_line_pointer
;
8114 input_line_pointer
= imm_start
;
8116 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8117 if (gotfree_input_line
)
8118 input_line_pointer
= gotfree_input_line
;
8120 exp_seg
= expression (exp
);
8124 /* Handle vector operations. */
8125 if (*input_line_pointer
== '{')
8127 input_line_pointer
= check_VecOperations (input_line_pointer
,
8129 if (input_line_pointer
== NULL
)
8133 if (*input_line_pointer
)
8134 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8136 input_line_pointer
= save_input_line_pointer
;
8137 if (gotfree_input_line
)
8139 free (gotfree_input_line
);
8141 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8142 exp
->X_op
= O_illegal
;
8145 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8149 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8150 i386_operand_type types
, const char *imm_start
)
8152 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8155 as_bad (_("missing or invalid immediate expression `%s'"),
8159 else if (exp
->X_op
== O_constant
)
8161 /* Size it properly later. */
8162 i
.types
[this_operand
].bitfield
.imm64
= 1;
8163 /* If not 64bit, sign extend val. */
8164 if (flag_code
!= CODE_64BIT
8165 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8167 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8169 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8170 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8171 && exp_seg
!= absolute_section
8172 && exp_seg
!= text_section
8173 && exp_seg
!= data_section
8174 && exp_seg
!= bss_section
8175 && exp_seg
!= undefined_section
8176 && !bfd_is_com_section (exp_seg
))
8178 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8182 else if (!intel_syntax
&& exp_seg
== reg_section
)
8185 as_bad (_("illegal immediate register operand %s"), imm_start
);
8190 /* This is an address. The size of the address will be
8191 determined later, depending on destination register,
8192 suffix, or the default for the section. */
8193 i
.types
[this_operand
].bitfield
.imm8
= 1;
8194 i
.types
[this_operand
].bitfield
.imm16
= 1;
8195 i
.types
[this_operand
].bitfield
.imm32
= 1;
8196 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8197 i
.types
[this_operand
].bitfield
.imm64
= 1;
8198 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8206 i386_scale (char *scale
)
8209 char *save
= input_line_pointer
;
8211 input_line_pointer
= scale
;
8212 val
= get_absolute_expression ();
8217 i
.log2_scale_factor
= 0;
8220 i
.log2_scale_factor
= 1;
8223 i
.log2_scale_factor
= 2;
8226 i
.log2_scale_factor
= 3;
8230 char sep
= *input_line_pointer
;
8232 *input_line_pointer
= '\0';
8233 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8235 *input_line_pointer
= sep
;
8236 input_line_pointer
= save
;
8240 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8242 as_warn (_("scale factor of %d without an index register"),
8243 1 << i
.log2_scale_factor
);
8244 i
.log2_scale_factor
= 0;
8246 scale
= input_line_pointer
;
8247 input_line_pointer
= save
;
8252 i386_displacement (char *disp_start
, char *disp_end
)
8256 char *save_input_line_pointer
;
8257 char *gotfree_input_line
;
8259 i386_operand_type bigdisp
, types
= anydisp
;
8262 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8264 as_bad (_("at most %d displacement operands are allowed"),
8265 MAX_MEMORY_OPERANDS
);
8269 operand_type_set (&bigdisp
, 0);
8270 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8271 || (!current_templates
->start
->opcode_modifier
.jump
8272 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8274 bigdisp
.bitfield
.disp32
= 1;
8275 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8276 if (flag_code
== CODE_64BIT
)
8280 bigdisp
.bitfield
.disp32s
= 1;
8281 bigdisp
.bitfield
.disp64
= 1;
8284 else if ((flag_code
== CODE_16BIT
) ^ override
)
8286 bigdisp
.bitfield
.disp32
= 0;
8287 bigdisp
.bitfield
.disp16
= 1;
8292 /* For PC-relative branches, the width of the displacement
8293 is dependent upon data size, not address size. */
8294 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8295 if (flag_code
== CODE_64BIT
)
8297 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8298 bigdisp
.bitfield
.disp16
= 1;
8301 bigdisp
.bitfield
.disp32
= 1;
8302 bigdisp
.bitfield
.disp32s
= 1;
8308 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8310 : LONG_MNEM_SUFFIX
));
8311 bigdisp
.bitfield
.disp32
= 1;
8312 if ((flag_code
== CODE_16BIT
) ^ override
)
8314 bigdisp
.bitfield
.disp32
= 0;
8315 bigdisp
.bitfield
.disp16
= 1;
8319 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8322 exp
= &disp_expressions
[i
.disp_operands
];
8323 i
.op
[this_operand
].disps
= exp
;
8325 save_input_line_pointer
= input_line_pointer
;
8326 input_line_pointer
= disp_start
;
8327 END_STRING_AND_SAVE (disp_end
);
8329 #ifndef GCC_ASM_O_HACK
8330 #define GCC_ASM_O_HACK 0
8333 END_STRING_AND_SAVE (disp_end
+ 1);
8334 if (i
.types
[this_operand
].bitfield
.baseIndex
8335 && displacement_string_end
[-1] == '+')
8337 /* This hack is to avoid a warning when using the "o"
8338 constraint within gcc asm statements.
8341 #define _set_tssldt_desc(n,addr,limit,type) \
8342 __asm__ __volatile__ ( \
8344 "movw %w1,2+%0\n\t" \
8346 "movb %b1,4+%0\n\t" \
8347 "movb %4,5+%0\n\t" \
8348 "movb $0,6+%0\n\t" \
8349 "movb %h1,7+%0\n\t" \
8351 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8353 This works great except that the output assembler ends
8354 up looking a bit weird if it turns out that there is
8355 no offset. You end up producing code that looks like:
8368 So here we provide the missing zero. */
8370 *displacement_string_end
= '0';
8373 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8374 if (gotfree_input_line
)
8375 input_line_pointer
= gotfree_input_line
;
8377 exp_seg
= expression (exp
);
8380 if (*input_line_pointer
)
8381 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8383 RESTORE_END_STRING (disp_end
+ 1);
8385 input_line_pointer
= save_input_line_pointer
;
8386 if (gotfree_input_line
)
8388 free (gotfree_input_line
);
8390 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8391 exp
->X_op
= O_illegal
;
8394 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8396 RESTORE_END_STRING (disp_end
);
8402 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8403 i386_operand_type types
, const char *disp_start
)
8405 i386_operand_type bigdisp
;
8408 /* We do this to make sure that the section symbol is in
8409 the symbol table. We will ultimately change the relocation
8410 to be relative to the beginning of the section. */
8411 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8412 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8413 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8415 if (exp
->X_op
!= O_symbol
)
8418 if (S_IS_LOCAL (exp
->X_add_symbol
)
8419 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8420 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8421 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8422 exp
->X_op
= O_subtract
;
8423 exp
->X_op_symbol
= GOT_symbol
;
8424 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8425 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8426 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8427 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8429 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8432 else if (exp
->X_op
== O_absent
8433 || exp
->X_op
== O_illegal
8434 || exp
->X_op
== O_big
)
8437 as_bad (_("missing or invalid displacement expression `%s'"),
8442 else if (flag_code
== CODE_64BIT
8443 && !i
.prefix
[ADDR_PREFIX
]
8444 && exp
->X_op
== O_constant
)
8446 /* Since displacement is signed extended to 64bit, don't allow
8447 disp32 and turn off disp32s if they are out of range. */
8448 i
.types
[this_operand
].bitfield
.disp32
= 0;
8449 if (!fits_in_signed_long (exp
->X_add_number
))
8451 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8452 if (i
.types
[this_operand
].bitfield
.baseindex
)
8454 as_bad (_("0x%lx out range of signed 32bit displacement"),
8455 (long) exp
->X_add_number
);
8461 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8462 else if (exp
->X_op
!= O_constant
8463 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8464 && exp_seg
!= absolute_section
8465 && exp_seg
!= text_section
8466 && exp_seg
!= data_section
8467 && exp_seg
!= bss_section
8468 && exp_seg
!= undefined_section
8469 && !bfd_is_com_section (exp_seg
))
8471 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8476 /* Check if this is a displacement only operand. */
8477 bigdisp
= i
.types
[this_operand
];
8478 bigdisp
.bitfield
.disp8
= 0;
8479 bigdisp
.bitfield
.disp16
= 0;
8480 bigdisp
.bitfield
.disp32
= 0;
8481 bigdisp
.bitfield
.disp32s
= 0;
8482 bigdisp
.bitfield
.disp64
= 0;
8483 if (operand_type_all_zero (&bigdisp
))
8484 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8490 /* Make sure the memory operand we've been dealt is valid.
8491 Return 1 on success, 0 on a failure. */
8494 i386_index_check (const char *operand_string
)
8496 const char *kind
= "base/index";
8497 enum flag_code addr_mode
;
8499 if (i
.prefix
[ADDR_PREFIX
])
8500 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8503 addr_mode
= flag_code
;
8505 #if INFER_ADDR_PREFIX
8506 if (i
.mem_operands
== 0)
8508 /* Infer address prefix from the first memory operand. */
8509 const reg_entry
*addr_reg
= i
.base_reg
;
8511 if (addr_reg
== NULL
)
8512 addr_reg
= i
.index_reg
;
8516 if (addr_reg
->reg_num
== RegEip
8517 || addr_reg
->reg_num
== RegEiz
8518 || addr_reg
->reg_type
.bitfield
.reg32
)
8519 addr_mode
= CODE_32BIT
;
8520 else if (flag_code
!= CODE_64BIT
8521 && addr_reg
->reg_type
.bitfield
.reg16
)
8522 addr_mode
= CODE_16BIT
;
8524 if (addr_mode
!= flag_code
)
8526 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8528 /* Change the size of any displacement too. At most one
8529 of Disp16 or Disp32 is set.
8530 FIXME. There doesn't seem to be any real need for
8531 separate Disp16 and Disp32 flags. The same goes for
8532 Imm16 and Imm32. Removing them would probably clean
8533 up the code quite a lot. */
8534 if (flag_code
!= CODE_64BIT
8535 && (i
.types
[this_operand
].bitfield
.disp16
8536 || i
.types
[this_operand
].bitfield
.disp32
))
8537 i
.types
[this_operand
]
8538 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8545 if (current_templates
->start
->opcode_modifier
.isstring
8546 && !current_templates
->start
->opcode_modifier
.immext
8547 && (current_templates
->end
[-1].opcode_modifier
.isstring
8550 /* Memory operands of string insns are special in that they only allow
8551 a single register (rDI, rSI, or rBX) as their memory address. */
8552 const reg_entry
*expected_reg
;
8553 static const char *di_si
[][2] =
8559 static const char *bx
[] = { "ebx", "bx", "rbx" };
8561 kind
= "string address";
8563 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8565 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8567 if (!type
.bitfield
.baseindex
8568 || ((!i
.mem_operands
!= !intel_syntax
)
8569 && current_templates
->end
[-1].operand_types
[1]
8570 .bitfield
.baseindex
))
8571 type
= current_templates
->end
[-1].operand_types
[1];
8572 expected_reg
= hash_find (reg_hash
,
8573 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8577 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8579 if (i
.base_reg
!= expected_reg
8581 || operand_type_check (i
.types
[this_operand
], disp
))
8583 /* The second memory operand must have the same size as
8587 && !((addr_mode
== CODE_64BIT
8588 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8589 || (addr_mode
== CODE_32BIT
8590 ? i
.base_reg
->reg_type
.bitfield
.reg32
8591 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8594 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8596 intel_syntax
? '[' : '(',
8598 expected_reg
->reg_name
,
8599 intel_syntax
? ']' : ')');
8606 as_bad (_("`%s' is not a valid %s expression"),
8607 operand_string
, kind
);
8612 if (addr_mode
!= CODE_16BIT
)
8614 /* 32-bit/64-bit checks. */
8616 && (addr_mode
== CODE_64BIT
8617 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8618 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8620 || (i
.base_reg
->reg_num
8621 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8623 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8624 && !i
.index_reg
->reg_type
.bitfield
.regymm
8625 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8626 && ((addr_mode
== CODE_64BIT
8627 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8628 || i
.index_reg
->reg_num
== RegRiz
)
8629 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8630 || i
.index_reg
->reg_num
== RegEiz
))
8631 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8634 /* bndmk, bndldx, and bndstx have special restrictions. */
8635 if (current_templates
->start
->base_opcode
== 0xf30f1b
8636 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8638 /* They cannot use RIP-relative addressing. */
8639 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8641 as_bad (_("`%s' cannot be used here"), operand_string
);
8645 /* bndldx and bndstx ignore their scale factor. */
8646 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8647 && i
.log2_scale_factor
)
8648 as_warn (_("register scaling is being ignored here"));
8653 /* 16-bit checks. */
8655 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8656 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8658 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8659 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8661 && i
.base_reg
->reg_num
< 6
8662 && i
.index_reg
->reg_num
>= 6
8663 && i
.log2_scale_factor
== 0))))
8670 /* Handle vector immediates. */
8673 RC_SAE_immediate (const char *imm_start
)
8675 unsigned int match_found
, j
;
8676 const char *pstr
= imm_start
;
8684 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8686 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8690 rc_op
.type
= RC_NamesTable
[j
].type
;
8691 rc_op
.operand
= this_operand
;
8692 i
.rounding
= &rc_op
;
8696 as_bad (_("duplicated `%s'"), imm_start
);
8699 pstr
+= RC_NamesTable
[j
].len
;
8709 as_bad (_("Missing '}': '%s'"), imm_start
);
8712 /* RC/SAE immediate string should contain nothing more. */;
8715 as_bad (_("Junk after '}': '%s'"), imm_start
);
8719 exp
= &im_expressions
[i
.imm_operands
++];
8720 i
.op
[this_operand
].imms
= exp
;
8722 exp
->X_op
= O_constant
;
8723 exp
->X_add_number
= 0;
8724 exp
->X_add_symbol
= (symbolS
*) 0;
8725 exp
->X_op_symbol
= (symbolS
*) 0;
8727 i
.types
[this_operand
].bitfield
.imm8
= 1;
8731 /* Only string instructions can have a second memory operand, so
8732 reduce current_templates to just those if it contains any. */
8734 maybe_adjust_templates (void)
8736 const insn_template
*t
;
8738 gas_assert (i
.mem_operands
== 1);
8740 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8741 if (t
->opcode_modifier
.isstring
)
8744 if (t
< current_templates
->end
)
8746 static templates aux_templates
;
8747 bfd_boolean recheck
;
8749 aux_templates
.start
= t
;
8750 for (; t
< current_templates
->end
; ++t
)
8751 if (!t
->opcode_modifier
.isstring
)
8753 aux_templates
.end
= t
;
8755 /* Determine whether to re-check the first memory operand. */
8756 recheck
= (aux_templates
.start
!= current_templates
->start
8757 || t
!= current_templates
->end
);
8759 current_templates
= &aux_templates
;
8764 if (i
.memop1_string
!= NULL
8765 && i386_index_check (i
.memop1_string
) == 0)
8774 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8778 i386_att_operand (char *operand_string
)
8782 char *op_string
= operand_string
;
8784 if (is_space_char (*op_string
))
8787 /* We check for an absolute prefix (differentiating,
8788 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8789 if (*op_string
== ABSOLUTE_PREFIX
)
8792 if (is_space_char (*op_string
))
8794 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8797 /* Check if operand is a register. */
8798 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8800 i386_operand_type temp
;
8802 /* Check for a segment override by searching for ':' after a
8803 segment register. */
8805 if (is_space_char (*op_string
))
8807 if (*op_string
== ':'
8808 && (r
->reg_type
.bitfield
.sreg2
8809 || r
->reg_type
.bitfield
.sreg3
))
8814 i
.seg
[i
.mem_operands
] = &es
;
8817 i
.seg
[i
.mem_operands
] = &cs
;
8820 i
.seg
[i
.mem_operands
] = &ss
;
8823 i
.seg
[i
.mem_operands
] = &ds
;
8826 i
.seg
[i
.mem_operands
] = &fs
;
8829 i
.seg
[i
.mem_operands
] = &gs
;
8833 /* Skip the ':' and whitespace. */
8835 if (is_space_char (*op_string
))
8838 if (!is_digit_char (*op_string
)
8839 && !is_identifier_char (*op_string
)
8840 && *op_string
!= '('
8841 && *op_string
!= ABSOLUTE_PREFIX
)
8843 as_bad (_("bad memory operand `%s'"), op_string
);
8846 /* Handle case of %es:*foo. */
8847 if (*op_string
== ABSOLUTE_PREFIX
)
8850 if (is_space_char (*op_string
))
8852 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8854 goto do_memory_reference
;
8857 /* Handle vector operations. */
8858 if (*op_string
== '{')
8860 op_string
= check_VecOperations (op_string
, NULL
);
8861 if (op_string
== NULL
)
8867 as_bad (_("junk `%s' after register"), op_string
);
8871 temp
.bitfield
.baseindex
= 0;
8872 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8874 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8875 i
.op
[this_operand
].regs
= r
;
8878 else if (*op_string
== REGISTER_PREFIX
)
8880 as_bad (_("bad register name `%s'"), op_string
);
8883 else if (*op_string
== IMMEDIATE_PREFIX
)
8886 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8888 as_bad (_("immediate operand illegal with absolute jump"));
8891 if (!i386_immediate (op_string
))
8894 else if (RC_SAE_immediate (operand_string
))
8896 /* If it is a RC or SAE immediate, do nothing. */
8899 else if (is_digit_char (*op_string
)
8900 || is_identifier_char (*op_string
)
8901 || *op_string
== '"'
8902 || *op_string
== '(')
8904 /* This is a memory reference of some sort. */
8907 /* Start and end of displacement string expression (if found). */
8908 char *displacement_string_start
;
8909 char *displacement_string_end
;
8912 do_memory_reference
:
8913 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8915 if ((i
.mem_operands
== 1
8916 && !current_templates
->start
->opcode_modifier
.isstring
)
8917 || i
.mem_operands
== 2)
8919 as_bad (_("too many memory references for `%s'"),
8920 current_templates
->start
->name
);
8924 /* Check for base index form. We detect the base index form by
8925 looking for an ')' at the end of the operand, searching
8926 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8928 base_string
= op_string
+ strlen (op_string
);
8930 /* Handle vector operations. */
8931 vop_start
= strchr (op_string
, '{');
8932 if (vop_start
&& vop_start
< base_string
)
8934 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8936 base_string
= vop_start
;
8940 if (is_space_char (*base_string
))
8943 /* If we only have a displacement, set-up for it to be parsed later. */
8944 displacement_string_start
= op_string
;
8945 displacement_string_end
= base_string
+ 1;
8947 if (*base_string
== ')')
8950 unsigned int parens_balanced
= 1;
8951 /* We've already checked that the number of left & right ()'s are
8952 equal, so this loop will not be infinite. */
8956 if (*base_string
== ')')
8958 if (*base_string
== '(')
8961 while (parens_balanced
);
8963 temp_string
= base_string
;
8965 /* Skip past '(' and whitespace. */
8967 if (is_space_char (*base_string
))
8970 if (*base_string
== ','
8971 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8974 displacement_string_end
= temp_string
;
8976 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8980 base_string
= end_op
;
8981 if (is_space_char (*base_string
))
8985 /* There may be an index reg or scale factor here. */
8986 if (*base_string
== ',')
8989 if (is_space_char (*base_string
))
8992 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8995 base_string
= end_op
;
8996 if (is_space_char (*base_string
))
8998 if (*base_string
== ',')
9001 if (is_space_char (*base_string
))
9004 else if (*base_string
!= ')')
9006 as_bad (_("expecting `,' or `)' "
9007 "after index register in `%s'"),
9012 else if (*base_string
== REGISTER_PREFIX
)
9014 end_op
= strchr (base_string
, ',');
9017 as_bad (_("bad register name `%s'"), base_string
);
9021 /* Check for scale factor. */
9022 if (*base_string
!= ')')
9024 char *end_scale
= i386_scale (base_string
);
9029 base_string
= end_scale
;
9030 if (is_space_char (*base_string
))
9032 if (*base_string
!= ')')
9034 as_bad (_("expecting `)' "
9035 "after scale factor in `%s'"),
9040 else if (!i
.index_reg
)
9042 as_bad (_("expecting index register or scale factor "
9043 "after `,'; got '%c'"),
9048 else if (*base_string
!= ')')
9050 as_bad (_("expecting `,' or `)' "
9051 "after base register in `%s'"),
9056 else if (*base_string
== REGISTER_PREFIX
)
9058 end_op
= strchr (base_string
, ',');
9061 as_bad (_("bad register name `%s'"), base_string
);
9066 /* If there's an expression beginning the operand, parse it,
9067 assuming displacement_string_start and
9068 displacement_string_end are meaningful. */
9069 if (displacement_string_start
!= displacement_string_end
)
9071 if (!i386_displacement (displacement_string_start
,
9072 displacement_string_end
))
9076 /* Special case for (%dx) while doing input/output op. */
9078 && operand_type_equal (&i
.base_reg
->reg_type
,
9079 ®16_inoutportreg
)
9081 && i
.log2_scale_factor
== 0
9082 && i
.seg
[i
.mem_operands
] == 0
9083 && !operand_type_check (i
.types
[this_operand
], disp
))
9085 i
.types
[this_operand
] = inoutportreg
;
9089 if (i386_index_check (operand_string
) == 0)
9091 i
.types
[this_operand
].bitfield
.mem
= 1;
9092 if (i
.mem_operands
== 0)
9093 i
.memop1_string
= xstrdup (operand_string
);
9098 /* It's not a memory operand; argh! */
9099 as_bad (_("invalid char %s beginning operand %d `%s'"),
9100 output_invalid (*op_string
),
9105 return 1; /* Normal return. */
9108 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9109 that an rs_machine_dependent frag may reach. */
9112 i386_frag_max_var (fragS
*frag
)
9114 /* The only relaxable frags are for jumps.
9115 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9116 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9117 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9122 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9124 /* STT_GNU_IFUNC symbol must go through PLT. */
9125 if ((symbol_get_bfdsym (fr_symbol
)->flags
9126 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9129 if (!S_IS_EXTERNAL (fr_symbol
))
9130 /* Symbol may be weak or local. */
9131 return !S_IS_WEAK (fr_symbol
);
9133 /* Global symbols with non-default visibility can't be preempted. */
9134 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9137 if (fr_var
!= NO_RELOC
)
9138 switch ((enum bfd_reloc_code_real
) fr_var
)
9140 case BFD_RELOC_386_PLT32
:
9141 case BFD_RELOC_X86_64_PLT32
:
9142 /* Symbol with PLT relocatin may be preempted. */
9148 /* Global symbols with default visibility in a shared library may be
9149 preempted by another definition. */
9154 /* md_estimate_size_before_relax()
9156 Called just before relax() for rs_machine_dependent frags. The x86
9157 assembler uses these frags to handle variable size jump
9160 Any symbol that is now undefined will not become defined.
9161 Return the correct fr_subtype in the frag.
9162 Return the initial "guess for variable size of frag" to caller.
9163 The guess is actually the growth beyond the fixed part. Whatever
9164 we do to grow the fixed or variable part contributes to our
9168 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9170 /* We've already got fragP->fr_subtype right; all we have to do is
9171 check for un-relaxable symbols. On an ELF system, we can't relax
9172 an externally visible symbol, because it may be overridden by a
9174 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9177 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9180 #if defined (OBJ_COFF) && defined (TE_PE)
9181 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9182 && S_IS_WEAK (fragP
->fr_symbol
))
9186 /* Symbol is undefined in this segment, or we need to keep a
9187 reloc so that weak symbols can be overridden. */
9188 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9189 enum bfd_reloc_code_real reloc_type
;
9190 unsigned char *opcode
;
9193 if (fragP
->fr_var
!= NO_RELOC
)
9194 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9196 reloc_type
= BFD_RELOC_16_PCREL
;
9198 reloc_type
= BFD_RELOC_32_PCREL
;
9200 old_fr_fix
= fragP
->fr_fix
;
9201 opcode
= (unsigned char *) fragP
->fr_opcode
;
9203 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9206 /* Make jmp (0xeb) a (d)word displacement jump. */
9208 fragP
->fr_fix
+= size
;
9209 fix_new (fragP
, old_fr_fix
, size
,
9211 fragP
->fr_offset
, 1,
9217 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9219 /* Negate the condition, and branch past an
9220 unconditional jump. */
9223 /* Insert an unconditional jump. */
9225 /* We added two extra opcode bytes, and have a two byte
9227 fragP
->fr_fix
+= 2 + 2;
9228 fix_new (fragP
, old_fr_fix
+ 2, 2,
9230 fragP
->fr_offset
, 1,
9237 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9242 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9244 fragP
->fr_offset
, 1,
9246 fixP
->fx_signed
= 1;
9250 /* This changes the byte-displacement jump 0x7N
9251 to the (d)word-displacement jump 0x0f,0x8N. */
9252 opcode
[1] = opcode
[0] + 0x10;
9253 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9254 /* We've added an opcode byte. */
9255 fragP
->fr_fix
+= 1 + size
;
9256 fix_new (fragP
, old_fr_fix
+ 1, size
,
9258 fragP
->fr_offset
, 1,
9263 BAD_CASE (fragP
->fr_subtype
);
9267 return fragP
->fr_fix
- old_fr_fix
;
9270 /* Guess size depending on current relax state. Initially the relax
9271 state will correspond to a short jump and we return 1, because
9272 the variable part of the frag (the branch offset) is one byte
9273 long. However, we can relax a section more than once and in that
9274 case we must either set fr_subtype back to the unrelaxed state,
9275 or return the value for the appropriate branch. */
9276 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9279 /* Called after relax() is finished.
9281 In: Address of frag.
9282 fr_type == rs_machine_dependent.
9283 fr_subtype is what the address relaxed to.
9285 Out: Any fixSs and constants are set up.
9286 Caller will turn frag into a ".space 0". */
9289 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9292 unsigned char *opcode
;
9293 unsigned char *where_to_put_displacement
= NULL
;
9294 offsetT target_address
;
9295 offsetT opcode_address
;
9296 unsigned int extension
= 0;
9297 offsetT displacement_from_opcode_start
;
9299 opcode
= (unsigned char *) fragP
->fr_opcode
;
9301 /* Address we want to reach in file space. */
9302 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9304 /* Address opcode resides at in file space. */
9305 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9307 /* Displacement from opcode start to fill into instruction. */
9308 displacement_from_opcode_start
= target_address
- opcode_address
;
9310 if ((fragP
->fr_subtype
& BIG
) == 0)
9312 /* Don't have to change opcode. */
9313 extension
= 1; /* 1 opcode + 1 displacement */
9314 where_to_put_displacement
= &opcode
[1];
9318 if (no_cond_jump_promotion
9319 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9320 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9321 _("long jump required"));
9323 switch (fragP
->fr_subtype
)
9325 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9326 extension
= 4; /* 1 opcode + 4 displacement */
9328 where_to_put_displacement
= &opcode
[1];
9331 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9332 extension
= 2; /* 1 opcode + 2 displacement */
9334 where_to_put_displacement
= &opcode
[1];
9337 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9338 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9339 extension
= 5; /* 2 opcode + 4 displacement */
9340 opcode
[1] = opcode
[0] + 0x10;
9341 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9342 where_to_put_displacement
= &opcode
[2];
9345 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9346 extension
= 3; /* 2 opcode + 2 displacement */
9347 opcode
[1] = opcode
[0] + 0x10;
9348 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9349 where_to_put_displacement
= &opcode
[2];
9352 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9357 where_to_put_displacement
= &opcode
[3];
9361 BAD_CASE (fragP
->fr_subtype
);
9366 /* If size if less then four we are sure that the operand fits,
9367 but if it's 4, then it could be that the displacement is larger
9369 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9371 && ((addressT
) (displacement_from_opcode_start
- extension
9372 + ((addressT
) 1 << 31))
9373 > (((addressT
) 2 << 31) - 1)))
9375 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9376 _("jump target out of range"));
9377 /* Make us emit 0. */
9378 displacement_from_opcode_start
= extension
;
9380 /* Now put displacement after opcode. */
9381 md_number_to_chars ((char *) where_to_put_displacement
,
9382 (valueT
) (displacement_from_opcode_start
- extension
),
9383 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9384 fragP
->fr_fix
+= extension
;
9387 /* Apply a fixup (fixP) to segment data, once it has been determined
9388 by our caller that we have all the info we need to fix it up.
9390 Parameter valP is the pointer to the value of the bits.
9392 On the 386, immediates, displacements, and data pointers are all in
9393 the same (little-endian) format, so we don't need to care about which
9397 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9399 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9400 valueT value
= *valP
;
9402 #if !defined (TE_Mach)
9405 switch (fixP
->fx_r_type
)
9411 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9414 case BFD_RELOC_X86_64_32S
:
9415 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9418 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9421 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9426 if (fixP
->fx_addsy
!= NULL
9427 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9428 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9429 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9430 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9431 && !use_rela_relocations
)
9433 /* This is a hack. There should be a better way to handle this.
9434 This covers for the fact that bfd_install_relocation will
9435 subtract the current location (for partial_inplace, PC relative
9436 relocations); see more below. */
9440 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9443 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9448 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9451 || (symbol_section_p (fixP
->fx_addsy
)
9452 && sym_seg
!= absolute_section
))
9453 && !generic_force_reloc (fixP
))
9455 /* Yes, we add the values in twice. This is because
9456 bfd_install_relocation subtracts them out again. I think
9457 bfd_install_relocation is broken, but I don't dare change
9459 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9463 #if defined (OBJ_COFF) && defined (TE_PE)
9464 /* For some reason, the PE format does not store a
9465 section address offset for a PC relative symbol. */
9466 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9467 || S_IS_WEAK (fixP
->fx_addsy
))
9468 value
+= md_pcrel_from (fixP
);
9471 #if defined (OBJ_COFF) && defined (TE_PE)
9472 if (fixP
->fx_addsy
!= NULL
9473 && S_IS_WEAK (fixP
->fx_addsy
)
9474 /* PR 16858: Do not modify weak function references. */
9475 && ! fixP
->fx_pcrel
)
9477 #if !defined (TE_PEP)
9478 /* For x86 PE weak function symbols are neither PC-relative
9479 nor do they set S_IS_FUNCTION. So the only reliable way
9480 to detect them is to check the flags of their containing
9482 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9483 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9487 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9491 /* Fix a few things - the dynamic linker expects certain values here,
9492 and we must not disappoint it. */
9493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9494 if (IS_ELF
&& fixP
->fx_addsy
)
9495 switch (fixP
->fx_r_type
)
9497 case BFD_RELOC_386_PLT32
:
9498 case BFD_RELOC_X86_64_PLT32
:
9499 /* Make the jump instruction point to the address of the operand. At
9500 runtime we merely add the offset to the actual PLT entry. */
9504 case BFD_RELOC_386_TLS_GD
:
9505 case BFD_RELOC_386_TLS_LDM
:
9506 case BFD_RELOC_386_TLS_IE_32
:
9507 case BFD_RELOC_386_TLS_IE
:
9508 case BFD_RELOC_386_TLS_GOTIE
:
9509 case BFD_RELOC_386_TLS_GOTDESC
:
9510 case BFD_RELOC_X86_64_TLSGD
:
9511 case BFD_RELOC_X86_64_TLSLD
:
9512 case BFD_RELOC_X86_64_GOTTPOFF
:
9513 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9514 value
= 0; /* Fully resolved at runtime. No addend. */
9516 case BFD_RELOC_386_TLS_LE
:
9517 case BFD_RELOC_386_TLS_LDO_32
:
9518 case BFD_RELOC_386_TLS_LE_32
:
9519 case BFD_RELOC_X86_64_DTPOFF32
:
9520 case BFD_RELOC_X86_64_DTPOFF64
:
9521 case BFD_RELOC_X86_64_TPOFF32
:
9522 case BFD_RELOC_X86_64_TPOFF64
:
9523 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9526 case BFD_RELOC_386_TLS_DESC_CALL
:
9527 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9528 value
= 0; /* Fully resolved at runtime. No addend. */
9529 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9533 case BFD_RELOC_VTABLE_INHERIT
:
9534 case BFD_RELOC_VTABLE_ENTRY
:
9541 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9543 #endif /* !defined (TE_Mach) */
9545 /* Are we finished with this relocation now? */
9546 if (fixP
->fx_addsy
== NULL
)
9548 #if defined (OBJ_COFF) && defined (TE_PE)
9549 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9552 /* Remember value for tc_gen_reloc. */
9553 fixP
->fx_addnumber
= value
;
9554 /* Clear out the frag for now. */
9558 else if (use_rela_relocations
)
9560 fixP
->fx_no_overflow
= 1;
9561 /* Remember value for tc_gen_reloc. */
9562 fixP
->fx_addnumber
= value
;
9566 md_number_to_chars (p
, value
, fixP
->fx_size
);
9570 md_atof (int type
, char *litP
, int *sizeP
)
9572 /* This outputs the LITTLENUMs in REVERSE order;
9573 in accord with the bigendian 386. */
9574 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9577 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9580 output_invalid (int c
)
9583 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9586 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9587 "(0x%x)", (unsigned char) c
);
9588 return output_invalid_buf
;
9591 /* REG_STRING starts *before* REGISTER_PREFIX. */
9593 static const reg_entry
*
9594 parse_real_register (char *reg_string
, char **end_op
)
9596 char *s
= reg_string
;
9598 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9601 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9602 if (*s
== REGISTER_PREFIX
)
9605 if (is_space_char (*s
))
9609 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9611 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9612 return (const reg_entry
*) NULL
;
9616 /* For naked regs, make sure that we are not dealing with an identifier.
9617 This prevents confusing an identifier like `eax_var' with register
9619 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9620 return (const reg_entry
*) NULL
;
9624 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9626 /* Handle floating point regs, allowing spaces in the (i) part. */
9627 if (r
== i386_regtab
/* %st is first entry of table */)
9629 if (is_space_char (*s
))
9634 if (is_space_char (*s
))
9636 if (*s
>= '0' && *s
<= '7')
9640 if (is_space_char (*s
))
9645 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9650 /* We have "%st(" then garbage. */
9651 return (const reg_entry
*) NULL
;
9655 if (r
== NULL
|| allow_pseudo_reg
)
9658 if (operand_type_all_zero (&r
->reg_type
))
9659 return (const reg_entry
*) NULL
;
9661 if ((r
->reg_type
.bitfield
.reg32
9662 || r
->reg_type
.bitfield
.sreg3
9663 || r
->reg_type
.bitfield
.control
9664 || r
->reg_type
.bitfield
.debug
9665 || r
->reg_type
.bitfield
.test
)
9666 && !cpu_arch_flags
.bitfield
.cpui386
)
9667 return (const reg_entry
*) NULL
;
9669 if (r
->reg_type
.bitfield
.floatreg
9670 && !cpu_arch_flags
.bitfield
.cpu8087
9671 && !cpu_arch_flags
.bitfield
.cpu287
9672 && !cpu_arch_flags
.bitfield
.cpu387
)
9673 return (const reg_entry
*) NULL
;
9675 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9676 return (const reg_entry
*) NULL
;
9678 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9679 return (const reg_entry
*) NULL
;
9681 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9682 return (const reg_entry
*) NULL
;
9684 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9685 return (const reg_entry
*) NULL
;
9687 if (r
->reg_type
.bitfield
.regmask
9688 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9689 return (const reg_entry
*) NULL
;
9691 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9692 if (!allow_index_reg
9693 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9694 return (const reg_entry
*) NULL
;
9696 /* Upper 16 vector register is only available with VREX in 64bit
9698 if ((r
->reg_flags
& RegVRex
))
9700 if (!cpu_arch_flags
.bitfield
.cpuvrex
9701 || flag_code
!= CODE_64BIT
)
9702 return (const reg_entry
*) NULL
;
9707 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9708 || r
->reg_type
.bitfield
.reg64
)
9709 && (!cpu_arch_flags
.bitfield
.cpulm
9710 || !operand_type_equal (&r
->reg_type
, &control
))
9711 && flag_code
!= CODE_64BIT
)
9712 return (const reg_entry
*) NULL
;
9714 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9715 return (const reg_entry
*) NULL
;
9720 /* REG_STRING starts *before* REGISTER_PREFIX. */
9722 static const reg_entry
*
9723 parse_register (char *reg_string
, char **end_op
)
9727 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9728 r
= parse_real_register (reg_string
, end_op
);
9733 char *save
= input_line_pointer
;
9737 input_line_pointer
= reg_string
;
9738 c
= get_symbol_name (®_string
);
9739 symbolP
= symbol_find (reg_string
);
9740 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9742 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9744 know (e
->X_op
== O_register
);
9745 know (e
->X_add_number
>= 0
9746 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9747 r
= i386_regtab
+ e
->X_add_number
;
9748 if ((r
->reg_flags
& RegVRex
))
9750 *end_op
= input_line_pointer
;
9752 *input_line_pointer
= c
;
9753 input_line_pointer
= save
;
9759 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9762 char *end
= input_line_pointer
;
9765 r
= parse_register (name
, &input_line_pointer
);
9766 if (r
&& end
<= input_line_pointer
)
9768 *nextcharP
= *input_line_pointer
;
9769 *input_line_pointer
= 0;
9770 e
->X_op
= O_register
;
9771 e
->X_add_number
= r
- i386_regtab
;
9774 input_line_pointer
= end
;
9776 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9780 md_operand (expressionS
*e
)
9785 switch (*input_line_pointer
)
9787 case REGISTER_PREFIX
:
9788 r
= parse_real_register (input_line_pointer
, &end
);
9791 e
->X_op
= O_register
;
9792 e
->X_add_number
= r
- i386_regtab
;
9793 input_line_pointer
= end
;
9798 gas_assert (intel_syntax
);
9799 end
= input_line_pointer
++;
9801 if (*input_line_pointer
== ']')
9803 ++input_line_pointer
;
9804 e
->X_op_symbol
= make_expr_symbol (e
);
9805 e
->X_add_symbol
= NULL
;
9806 e
->X_add_number
= 0;
9812 input_line_pointer
= end
;
9819 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9820 const char *md_shortopts
= "kVQ:sqn";
9822 const char *md_shortopts
= "qn";
9825 #define OPTION_32 (OPTION_MD_BASE + 0)
9826 #define OPTION_64 (OPTION_MD_BASE + 1)
9827 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9828 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9829 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9830 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9831 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9832 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9833 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9834 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9835 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9836 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9837 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9838 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9839 #define OPTION_X32 (OPTION_MD_BASE + 14)
9840 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9841 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9842 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9843 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9844 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9845 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9846 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9847 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9848 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9849 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9850 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9852 struct option md_longopts
[] =
9854 {"32", no_argument
, NULL
, OPTION_32
},
9855 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9856 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9857 {"64", no_argument
, NULL
, OPTION_64
},
9859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9860 {"x32", no_argument
, NULL
, OPTION_X32
},
9861 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9863 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9864 {"march", required_argument
, NULL
, OPTION_MARCH
},
9865 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9866 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9867 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9868 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9869 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9870 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9871 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9872 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9873 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9874 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9875 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9876 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9877 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9878 # if defined (TE_PE) || defined (TE_PEP)
9879 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9881 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9882 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9883 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9884 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9885 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9886 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9887 {NULL
, no_argument
, NULL
, 0}
9889 size_t md_longopts_size
= sizeof (md_longopts
);
9892 md_parse_option (int c
, const char *arg
)
9895 char *arch
, *next
, *saved
;
9900 optimize_align_code
= 0;
9907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9908 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9909 should be emitted or not. FIXME: Not implemented. */
9913 /* -V: SVR4 argument to print version ID. */
9915 print_version_id ();
9918 /* -k: Ignore for FreeBSD compatibility. */
9923 /* -s: On i386 Solaris, this tells the native assembler to use
9924 .stab instead of .stab.excl. We always use .stab anyhow. */
9927 case OPTION_MSHARED
:
9931 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9932 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9935 const char **list
, **l
;
9937 list
= bfd_target_list ();
9938 for (l
= list
; *l
!= NULL
; l
++)
9939 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9940 || strcmp (*l
, "coff-x86-64") == 0
9941 || strcmp (*l
, "pe-x86-64") == 0
9942 || strcmp (*l
, "pei-x86-64") == 0
9943 || strcmp (*l
, "mach-o-x86-64") == 0)
9945 default_arch
= "x86_64";
9949 as_fatal (_("no compiled in support for x86_64"));
9955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9959 const char **list
, **l
;
9961 list
= bfd_target_list ();
9962 for (l
= list
; *l
!= NULL
; l
++)
9963 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9965 default_arch
= "x86_64:32";
9969 as_fatal (_("no compiled in support for 32bit x86_64"));
9973 as_fatal (_("32bit x86_64 is only supported for ELF"));
9978 default_arch
= "i386";
9982 #ifdef SVR4_COMMENT_CHARS
9987 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9989 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9993 i386_comment_chars
= n
;
9999 saved
= xstrdup (arg
);
10001 /* Allow -march=+nosse. */
10007 as_fatal (_("invalid -march= option: `%s'"), arg
);
10008 next
= strchr (arch
, '+');
10011 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10013 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10016 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10019 cpu_arch_name
= cpu_arch
[j
].name
;
10020 cpu_sub_arch_name
= NULL
;
10021 cpu_arch_flags
= cpu_arch
[j
].flags
;
10022 cpu_arch_isa
= cpu_arch
[j
].type
;
10023 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10024 if (!cpu_arch_tune_set
)
10026 cpu_arch_tune
= cpu_arch_isa
;
10027 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10031 else if (*cpu_arch
[j
].name
== '.'
10032 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10034 /* ISA entension. */
10035 i386_cpu_flags flags
;
10037 flags
= cpu_flags_or (cpu_arch_flags
,
10038 cpu_arch
[j
].flags
);
10040 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10042 if (cpu_sub_arch_name
)
10044 char *name
= cpu_sub_arch_name
;
10045 cpu_sub_arch_name
= concat (name
,
10047 (const char *) NULL
);
10051 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10052 cpu_arch_flags
= flags
;
10053 cpu_arch_isa_flags
= flags
;
10059 if (j
>= ARRAY_SIZE (cpu_arch
))
10061 /* Disable an ISA entension. */
10062 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10063 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10065 i386_cpu_flags flags
;
10067 flags
= cpu_flags_and_not (cpu_arch_flags
,
10068 cpu_noarch
[j
].flags
);
10069 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10071 if (cpu_sub_arch_name
)
10073 char *name
= cpu_sub_arch_name
;
10074 cpu_sub_arch_name
= concat (arch
,
10075 (const char *) NULL
);
10079 cpu_sub_arch_name
= xstrdup (arch
);
10080 cpu_arch_flags
= flags
;
10081 cpu_arch_isa_flags
= flags
;
10086 if (j
>= ARRAY_SIZE (cpu_noarch
))
10087 j
= ARRAY_SIZE (cpu_arch
);
10090 if (j
>= ARRAY_SIZE (cpu_arch
))
10091 as_fatal (_("invalid -march= option: `%s'"), arg
);
10095 while (next
!= NULL
);
10101 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10102 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10104 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10106 cpu_arch_tune_set
= 1;
10107 cpu_arch_tune
= cpu_arch
[j
].type
;
10108 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10112 if (j
>= ARRAY_SIZE (cpu_arch
))
10113 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10116 case OPTION_MMNEMONIC
:
10117 if (strcasecmp (arg
, "att") == 0)
10118 intel_mnemonic
= 0;
10119 else if (strcasecmp (arg
, "intel") == 0)
10120 intel_mnemonic
= 1;
10122 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10125 case OPTION_MSYNTAX
:
10126 if (strcasecmp (arg
, "att") == 0)
10128 else if (strcasecmp (arg
, "intel") == 0)
10131 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10134 case OPTION_MINDEX_REG
:
10135 allow_index_reg
= 1;
10138 case OPTION_MNAKED_REG
:
10139 allow_naked_reg
= 1;
10142 case OPTION_MOLD_GCC
:
10146 case OPTION_MSSE2AVX
:
10150 case OPTION_MSSE_CHECK
:
10151 if (strcasecmp (arg
, "error") == 0)
10152 sse_check
= check_error
;
10153 else if (strcasecmp (arg
, "warning") == 0)
10154 sse_check
= check_warning
;
10155 else if (strcasecmp (arg
, "none") == 0)
10156 sse_check
= check_none
;
10158 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10161 case OPTION_MOPERAND_CHECK
:
10162 if (strcasecmp (arg
, "error") == 0)
10163 operand_check
= check_error
;
10164 else if (strcasecmp (arg
, "warning") == 0)
10165 operand_check
= check_warning
;
10166 else if (strcasecmp (arg
, "none") == 0)
10167 operand_check
= check_none
;
10169 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10172 case OPTION_MAVXSCALAR
:
10173 if (strcasecmp (arg
, "128") == 0)
10174 avxscalar
= vex128
;
10175 else if (strcasecmp (arg
, "256") == 0)
10176 avxscalar
= vex256
;
10178 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10181 case OPTION_MADD_BND_PREFIX
:
10182 add_bnd_prefix
= 1;
10185 case OPTION_MEVEXLIG
:
10186 if (strcmp (arg
, "128") == 0)
10187 evexlig
= evexl128
;
10188 else if (strcmp (arg
, "256") == 0)
10189 evexlig
= evexl256
;
10190 else if (strcmp (arg
, "512") == 0)
10191 evexlig
= evexl512
;
10193 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10196 case OPTION_MEVEXRCIG
:
10197 if (strcmp (arg
, "rne") == 0)
10199 else if (strcmp (arg
, "rd") == 0)
10201 else if (strcmp (arg
, "ru") == 0)
10203 else if (strcmp (arg
, "rz") == 0)
10206 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10209 case OPTION_MEVEXWIG
:
10210 if (strcmp (arg
, "0") == 0)
10212 else if (strcmp (arg
, "1") == 0)
10215 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10218 # if defined (TE_PE) || defined (TE_PEP)
10219 case OPTION_MBIG_OBJ
:
10224 case OPTION_MOMIT_LOCK_PREFIX
:
10225 if (strcasecmp (arg
, "yes") == 0)
10226 omit_lock_prefix
= 1;
10227 else if (strcasecmp (arg
, "no") == 0)
10228 omit_lock_prefix
= 0;
10230 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10233 case OPTION_MFENCE_AS_LOCK_ADD
:
10234 if (strcasecmp (arg
, "yes") == 0)
10236 else if (strcasecmp (arg
, "no") == 0)
10239 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10242 case OPTION_MRELAX_RELOCATIONS
:
10243 if (strcasecmp (arg
, "yes") == 0)
10244 generate_relax_relocations
= 1;
10245 else if (strcasecmp (arg
, "no") == 0)
10246 generate_relax_relocations
= 0;
10248 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10251 case OPTION_MAMD64
:
10255 case OPTION_MINTEL64
:
10265 #define MESSAGE_TEMPLATE \
10269 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10270 int *left_p
, const char *name
, int len
)
10272 int size
= sizeof (MESSAGE_TEMPLATE
);
10273 int left
= *left_p
;
10275 /* Reserve 2 spaces for ", " or ",\0" */
10278 /* Check if there is any room. */
10286 p
= mempcpy (p
, name
, len
);
10290 /* Output the current message now and start a new one. */
10293 fprintf (stream
, "%s\n", message
);
10295 left
= size
- (start
- message
) - len
- 2;
10297 gas_assert (left
>= 0);
10299 p
= mempcpy (p
, name
, len
);
10307 show_arch (FILE *stream
, int ext
, int check
)
10309 static char message
[] = MESSAGE_TEMPLATE
;
10310 char *start
= message
+ 27;
10312 int size
= sizeof (MESSAGE_TEMPLATE
);
10319 left
= size
- (start
- message
);
10320 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10322 /* Should it be skipped? */
10323 if (cpu_arch
[j
].skip
)
10326 name
= cpu_arch
[j
].name
;
10327 len
= cpu_arch
[j
].len
;
10330 /* It is an extension. Skip if we aren't asked to show it. */
10341 /* It is an processor. Skip if we show only extension. */
10344 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10346 /* It is an impossible processor - skip. */
10350 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10353 /* Display disabled extensions. */
10355 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10357 name
= cpu_noarch
[j
].name
;
10358 len
= cpu_noarch
[j
].len
;
10359 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10364 fprintf (stream
, "%s\n", message
);
10368 md_show_usage (FILE *stream
)
10370 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10371 fprintf (stream
, _("\
10373 -V print assembler version number\n\
10376 fprintf (stream
, _("\
10377 -n Do not optimize code alignment\n\
10378 -q quieten some warnings\n"));
10379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10380 fprintf (stream
, _("\
10383 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10384 || defined (TE_PE) || defined (TE_PEP))
10385 fprintf (stream
, _("\
10386 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10388 #ifdef SVR4_COMMENT_CHARS
10389 fprintf (stream
, _("\
10390 --divide do not treat `/' as a comment character\n"));
10392 fprintf (stream
, _("\
10393 --divide ignored\n"));
10395 fprintf (stream
, _("\
10396 -march=CPU[,+EXTENSION...]\n\
10397 generate code for CPU and EXTENSION, CPU is one of:\n"));
10398 show_arch (stream
, 0, 1);
10399 fprintf (stream
, _("\
10400 EXTENSION is combination of:\n"));
10401 show_arch (stream
, 1, 0);
10402 fprintf (stream
, _("\
10403 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10404 show_arch (stream
, 0, 0);
10405 fprintf (stream
, _("\
10406 -msse2avx encode SSE instructions with VEX prefix\n"));
10407 fprintf (stream
, _("\
10408 -msse-check=[none|error|warning]\n\
10409 check SSE instructions\n"));
10410 fprintf (stream
, _("\
10411 -moperand-check=[none|error|warning]\n\
10412 check operand combinations for validity\n"));
10413 fprintf (stream
, _("\
10414 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10416 fprintf (stream
, _("\
10417 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10419 fprintf (stream
, _("\
10420 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10421 for EVEX.W bit ignored instructions\n"));
10422 fprintf (stream
, _("\
10423 -mevexrcig=[rne|rd|ru|rz]\n\
10424 encode EVEX instructions with specific EVEX.RC value\n\
10425 for SAE-only ignored instructions\n"));
10426 fprintf (stream
, _("\
10427 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10428 fprintf (stream
, _("\
10429 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10430 fprintf (stream
, _("\
10431 -mindex-reg support pseudo index registers\n"));
10432 fprintf (stream
, _("\
10433 -mnaked-reg don't require `%%' prefix for registers\n"));
10434 fprintf (stream
, _("\
10435 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10436 fprintf (stream
, _("\
10437 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10438 fprintf (stream
, _("\
10439 -mshared disable branch optimization for shared code\n"));
10440 # if defined (TE_PE) || defined (TE_PEP)
10441 fprintf (stream
, _("\
10442 -mbig-obj generate big object files\n"));
10444 fprintf (stream
, _("\
10445 -momit-lock-prefix=[no|yes]\n\
10446 strip all lock prefixes\n"));
10447 fprintf (stream
, _("\
10448 -mfence-as-lock-add=[no|yes]\n\
10449 encode lfence, mfence and sfence as\n\
10450 lock addl $0x0, (%%{re}sp)\n"));
10451 fprintf (stream
, _("\
10452 -mrelax-relocations=[no|yes]\n\
10453 generate relax relocations\n"));
10454 fprintf (stream
, _("\
10455 -mamd64 accept only AMD64 ISA\n"));
10456 fprintf (stream
, _("\
10457 -mintel64 accept only Intel64 ISA\n"));
10460 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10461 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10462 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10464 /* Pick the target format to use. */
10467 i386_target_format (void)
10469 if (!strncmp (default_arch
, "x86_64", 6))
10471 update_code_flag (CODE_64BIT
, 1);
10472 if (default_arch
[6] == '\0')
10473 x86_elf_abi
= X86_64_ABI
;
10475 x86_elf_abi
= X86_64_X32_ABI
;
10477 else if (!strcmp (default_arch
, "i386"))
10478 update_code_flag (CODE_32BIT
, 1);
10479 else if (!strcmp (default_arch
, "iamcu"))
10481 update_code_flag (CODE_32BIT
, 1);
10482 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10484 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10485 cpu_arch_name
= "iamcu";
10486 cpu_sub_arch_name
= NULL
;
10487 cpu_arch_flags
= iamcu_flags
;
10488 cpu_arch_isa
= PROCESSOR_IAMCU
;
10489 cpu_arch_isa_flags
= iamcu_flags
;
10490 if (!cpu_arch_tune_set
)
10492 cpu_arch_tune
= cpu_arch_isa
;
10493 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10496 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10497 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10501 as_fatal (_("unknown architecture"));
10503 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10504 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10505 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10506 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10508 switch (OUTPUT_FLAVOR
)
10510 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10511 case bfd_target_aout_flavour
:
10512 return AOUT_TARGET_FORMAT
;
10514 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10515 # if defined (TE_PE) || defined (TE_PEP)
10516 case bfd_target_coff_flavour
:
10517 if (flag_code
== CODE_64BIT
)
10518 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10521 # elif defined (TE_GO32)
10522 case bfd_target_coff_flavour
:
10523 return "coff-go32";
10525 case bfd_target_coff_flavour
:
10526 return "coff-i386";
10529 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10530 case bfd_target_elf_flavour
:
10532 const char *format
;
10534 switch (x86_elf_abi
)
10537 format
= ELF_TARGET_FORMAT
;
10540 use_rela_relocations
= 1;
10542 format
= ELF_TARGET_FORMAT64
;
10544 case X86_64_X32_ABI
:
10545 use_rela_relocations
= 1;
10547 disallow_64bit_reloc
= 1;
10548 format
= ELF_TARGET_FORMAT32
;
10551 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10553 if (x86_elf_abi
!= X86_64_ABI
)
10554 as_fatal (_("Intel L1OM is 64bit only"));
10555 return ELF_TARGET_L1OM_FORMAT
;
10557 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10559 if (x86_elf_abi
!= X86_64_ABI
)
10560 as_fatal (_("Intel K1OM is 64bit only"));
10561 return ELF_TARGET_K1OM_FORMAT
;
10563 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10565 if (x86_elf_abi
!= I386_ABI
)
10566 as_fatal (_("Intel MCU is 32bit only"));
10567 return ELF_TARGET_IAMCU_FORMAT
;
10573 #if defined (OBJ_MACH_O)
10574 case bfd_target_mach_o_flavour
:
10575 if (flag_code
== CODE_64BIT
)
10577 use_rela_relocations
= 1;
10579 return "mach-o-x86-64";
10582 return "mach-o-i386";
10590 #endif /* OBJ_MAYBE_ more than one */
10593 md_undefined_symbol (char *name
)
10595 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10596 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10597 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10598 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10602 if (symbol_find (name
))
10603 as_bad (_("GOT already in symbol table"));
10604 GOT_symbol
= symbol_new (name
, undefined_section
,
10605 (valueT
) 0, &zero_address_frag
);
10612 /* Round up a section size to the appropriate boundary. */
10615 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10617 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10618 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10620 /* For a.out, force the section size to be aligned. If we don't do
10621 this, BFD will align it for us, but it will not write out the
10622 final bytes of the section. This may be a bug in BFD, but it is
10623 easier to fix it here since that is how the other a.out targets
10627 align
= bfd_get_section_alignment (stdoutput
, segment
);
10628 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10635 /* On the i386, PC-relative offsets are relative to the start of the
10636 next instruction. That is, the address of the offset, plus its
10637 size, since the offset is always the last part of the insn. */
10640 md_pcrel_from (fixS
*fixP
)
10642 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10648 s_bss (int ignore ATTRIBUTE_UNUSED
)
10652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10654 obj_elf_section_change_hook ();
10656 temp
= get_absolute_expression ();
10657 subseg_set (bss_section
, (subsegT
) temp
);
10658 demand_empty_rest_of_line ();
10664 i386_validate_fix (fixS
*fixp
)
10666 if (fixp
->fx_subsy
)
10668 if (fixp
->fx_subsy
== GOT_symbol
)
10670 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10675 if (fixp
->fx_tcbit2
)
10676 fixp
->fx_r_type
= (fixp
->fx_tcbit
10677 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10678 : BFD_RELOC_X86_64_GOTPCRELX
);
10681 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10686 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10688 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10690 fixp
->fx_subsy
= 0;
10693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10694 else if (!object_64bit
)
10696 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10697 && fixp
->fx_tcbit2
)
10698 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10704 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10707 bfd_reloc_code_real_type code
;
10709 switch (fixp
->fx_r_type
)
10711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10712 case BFD_RELOC_SIZE32
:
10713 case BFD_RELOC_SIZE64
:
10714 if (S_IS_DEFINED (fixp
->fx_addsy
)
10715 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10717 /* Resolve size relocation against local symbol to size of
10718 the symbol plus addend. */
10719 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10720 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10721 && !fits_in_unsigned_long (value
))
10722 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10723 _("symbol size computation overflow"));
10724 fixp
->fx_addsy
= NULL
;
10725 fixp
->fx_subsy
= NULL
;
10726 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10730 /* Fall through. */
10732 case BFD_RELOC_X86_64_PLT32
:
10733 case BFD_RELOC_X86_64_GOT32
:
10734 case BFD_RELOC_X86_64_GOTPCREL
:
10735 case BFD_RELOC_X86_64_GOTPCRELX
:
10736 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10737 case BFD_RELOC_386_PLT32
:
10738 case BFD_RELOC_386_GOT32
:
10739 case BFD_RELOC_386_GOT32X
:
10740 case BFD_RELOC_386_GOTOFF
:
10741 case BFD_RELOC_386_GOTPC
:
10742 case BFD_RELOC_386_TLS_GD
:
10743 case BFD_RELOC_386_TLS_LDM
:
10744 case BFD_RELOC_386_TLS_LDO_32
:
10745 case BFD_RELOC_386_TLS_IE_32
:
10746 case BFD_RELOC_386_TLS_IE
:
10747 case BFD_RELOC_386_TLS_GOTIE
:
10748 case BFD_RELOC_386_TLS_LE_32
:
10749 case BFD_RELOC_386_TLS_LE
:
10750 case BFD_RELOC_386_TLS_GOTDESC
:
10751 case BFD_RELOC_386_TLS_DESC_CALL
:
10752 case BFD_RELOC_X86_64_TLSGD
:
10753 case BFD_RELOC_X86_64_TLSLD
:
10754 case BFD_RELOC_X86_64_DTPOFF32
:
10755 case BFD_RELOC_X86_64_DTPOFF64
:
10756 case BFD_RELOC_X86_64_GOTTPOFF
:
10757 case BFD_RELOC_X86_64_TPOFF32
:
10758 case BFD_RELOC_X86_64_TPOFF64
:
10759 case BFD_RELOC_X86_64_GOTOFF64
:
10760 case BFD_RELOC_X86_64_GOTPC32
:
10761 case BFD_RELOC_X86_64_GOT64
:
10762 case BFD_RELOC_X86_64_GOTPCREL64
:
10763 case BFD_RELOC_X86_64_GOTPC64
:
10764 case BFD_RELOC_X86_64_GOTPLT64
:
10765 case BFD_RELOC_X86_64_PLTOFF64
:
10766 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10767 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10768 case BFD_RELOC_RVA
:
10769 case BFD_RELOC_VTABLE_ENTRY
:
10770 case BFD_RELOC_VTABLE_INHERIT
:
10772 case BFD_RELOC_32_SECREL
:
10774 code
= fixp
->fx_r_type
;
10776 case BFD_RELOC_X86_64_32S
:
10777 if (!fixp
->fx_pcrel
)
10779 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10780 code
= fixp
->fx_r_type
;
10783 /* Fall through. */
10785 if (fixp
->fx_pcrel
)
10787 switch (fixp
->fx_size
)
10790 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10791 _("can not do %d byte pc-relative relocation"),
10793 code
= BFD_RELOC_32_PCREL
;
10795 case 1: code
= BFD_RELOC_8_PCREL
; break;
10796 case 2: code
= BFD_RELOC_16_PCREL
; break;
10797 case 4: code
= BFD_RELOC_32_PCREL
; break;
10799 case 8: code
= BFD_RELOC_64_PCREL
; break;
10805 switch (fixp
->fx_size
)
10808 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10809 _("can not do %d byte relocation"),
10811 code
= BFD_RELOC_32
;
10813 case 1: code
= BFD_RELOC_8
; break;
10814 case 2: code
= BFD_RELOC_16
; break;
10815 case 4: code
= BFD_RELOC_32
; break;
10817 case 8: code
= BFD_RELOC_64
; break;
10824 if ((code
== BFD_RELOC_32
10825 || code
== BFD_RELOC_32_PCREL
10826 || code
== BFD_RELOC_X86_64_32S
)
10828 && fixp
->fx_addsy
== GOT_symbol
)
10831 code
= BFD_RELOC_386_GOTPC
;
10833 code
= BFD_RELOC_X86_64_GOTPC32
;
10835 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10837 && fixp
->fx_addsy
== GOT_symbol
)
10839 code
= BFD_RELOC_X86_64_GOTPC64
;
10842 rel
= XNEW (arelent
);
10843 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10844 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10846 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10848 if (!use_rela_relocations
)
10850 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10851 vtable entry to be used in the relocation's section offset. */
10852 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10853 rel
->address
= fixp
->fx_offset
;
10854 #if defined (OBJ_COFF) && defined (TE_PE)
10855 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10856 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10861 /* Use the rela in 64bit mode. */
10864 if (disallow_64bit_reloc
)
10867 case BFD_RELOC_X86_64_DTPOFF64
:
10868 case BFD_RELOC_X86_64_TPOFF64
:
10869 case BFD_RELOC_64_PCREL
:
10870 case BFD_RELOC_X86_64_GOTOFF64
:
10871 case BFD_RELOC_X86_64_GOT64
:
10872 case BFD_RELOC_X86_64_GOTPCREL64
:
10873 case BFD_RELOC_X86_64_GOTPC64
:
10874 case BFD_RELOC_X86_64_GOTPLT64
:
10875 case BFD_RELOC_X86_64_PLTOFF64
:
10876 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10877 _("cannot represent relocation type %s in x32 mode"),
10878 bfd_get_reloc_code_name (code
));
10884 if (!fixp
->fx_pcrel
)
10885 rel
->addend
= fixp
->fx_offset
;
10889 case BFD_RELOC_X86_64_PLT32
:
10890 case BFD_RELOC_X86_64_GOT32
:
10891 case BFD_RELOC_X86_64_GOTPCREL
:
10892 case BFD_RELOC_X86_64_GOTPCRELX
:
10893 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10894 case BFD_RELOC_X86_64_TLSGD
:
10895 case BFD_RELOC_X86_64_TLSLD
:
10896 case BFD_RELOC_X86_64_GOTTPOFF
:
10897 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10898 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10899 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10902 rel
->addend
= (section
->vma
10904 + fixp
->fx_addnumber
10905 + md_pcrel_from (fixp
));
10910 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10911 if (rel
->howto
== NULL
)
10913 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10914 _("cannot represent relocation type %s"),
10915 bfd_get_reloc_code_name (code
));
10916 /* Set howto to a garbage value so that we can keep going. */
10917 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10918 gas_assert (rel
->howto
!= NULL
);
10924 #include "tc-i386-intel.c"
10927 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10929 int saved_naked_reg
;
10930 char saved_register_dot
;
10932 saved_naked_reg
= allow_naked_reg
;
10933 allow_naked_reg
= 1;
10934 saved_register_dot
= register_chars
['.'];
10935 register_chars
['.'] = '.';
10936 allow_pseudo_reg
= 1;
10937 expression_and_evaluate (exp
);
10938 allow_pseudo_reg
= 0;
10939 register_chars
['.'] = saved_register_dot
;
10940 allow_naked_reg
= saved_naked_reg
;
10942 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10944 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10946 exp
->X_op
= O_constant
;
10947 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10948 .dw2_regnum
[flag_code
>> 1];
10951 exp
->X_op
= O_illegal
;
10956 tc_x86_frame_initial_instructions (void)
10958 static unsigned int sp_regno
[2];
10960 if (!sp_regno
[flag_code
>> 1])
10962 char *saved_input
= input_line_pointer
;
10963 char sp
[][4] = {"esp", "rsp"};
10966 input_line_pointer
= sp
[flag_code
>> 1];
10967 tc_x86_parse_to_dw2regnum (&exp
);
10968 gas_assert (exp
.X_op
== O_constant
);
10969 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10970 input_line_pointer
= saved_input
;
10973 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10974 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10978 x86_dwarf2_addr_size (void)
10980 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10981 if (x86_elf_abi
== X86_64_X32_ABI
)
10984 return bfd_arch_bits_per_address (stdoutput
) / 8;
10988 i386_elf_section_type (const char *str
, size_t len
)
10990 if (flag_code
== CODE_64BIT
10991 && len
== sizeof ("unwind") - 1
10992 && strncmp (str
, "unwind", 6) == 0)
10993 return SHT_X86_64_UNWIND
;
11000 i386_solaris_fix_up_eh_frame (segT sec
)
11002 if (flag_code
== CODE_64BIT
)
11003 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11009 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11013 exp
.X_op
= O_secrel
;
11014 exp
.X_add_symbol
= symbol
;
11015 exp
.X_add_number
= 0;
11016 emit_expr (&exp
, size
);
11020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11021 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11024 x86_64_section_letter (int letter
, const char **ptr_msg
)
11026 if (flag_code
== CODE_64BIT
)
11029 return SHF_X86_64_LARGE
;
11031 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11034 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11039 x86_64_section_word (char *str
, size_t len
)
11041 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11042 return SHF_X86_64_LARGE
;
11048 handle_large_common (int small ATTRIBUTE_UNUSED
)
11050 if (flag_code
!= CODE_64BIT
)
11052 s_comm_internal (0, elf_common_parse
);
11053 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11057 static segT lbss_section
;
11058 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11059 asection
*saved_bss_section
= bss_section
;
11061 if (lbss_section
== NULL
)
11063 flagword applicable
;
11064 segT seg
= now_seg
;
11065 subsegT subseg
= now_subseg
;
11067 /* The .lbss section is for local .largecomm symbols. */
11068 lbss_section
= subseg_new (".lbss", 0);
11069 applicable
= bfd_applicable_section_flags (stdoutput
);
11070 bfd_set_section_flags (stdoutput
, lbss_section
,
11071 applicable
& SEC_ALLOC
);
11072 seg_info (lbss_section
)->bss
= 1;
11074 subseg_set (seg
, subseg
);
11077 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11078 bss_section
= lbss_section
;
11080 s_comm_internal (0, elf_common_parse
);
11082 elf_com_section_ptr
= saved_com_section_ptr
;
11083 bss_section
= saved_bss_section
;
11086 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */