1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template
*match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
999 case PROCESSOR_GENERIC64
:
1000 patt
= alt_long_patt
;
1003 case PROCESSOR_ATHLON
:
1005 case PROCESSOR_AMDFAM10
:
1006 patt
= alt_short_patt
;
1008 case PROCESSOR_I386
:
1009 case PROCESSOR_I486
:
1010 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_GENERIC32
:
1018 switch (fragP
->tc_frag_data
.tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1022 PROCESSOR_UNKNOWN. */
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1030 case PROCESSOR_ATHLON
:
1032 case PROCESSOR_AMDFAM10
:
1033 case PROCESSOR_GENERIC32
:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1036 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1037 patt
= alt_short_patt
;
1041 case PROCESSOR_PENTIUMPRO
:
1042 case PROCESSOR_PENTIUM4
:
1043 case PROCESSOR_NOCONA
:
1044 case PROCESSOR_CORE
:
1045 case PROCESSOR_CORE2
:
1046 case PROCESSOR_COREI7
:
1047 case PROCESSOR_L1OM
:
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_GENERIC64
:
1054 patt
= alt_long_patt
;
1059 if (patt
== f32_patt
)
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code
== CODE_64BIT
1068 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1074 patt
[count
- 1], count
);
1077 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 /* Adjust jump offset. */
1080 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding
= count
;
1089 while (padding
> 15)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 patt
[padding
- 1], padding
);
1101 fragP
->fr_var
= count
;
1105 operand_type_all_zero (const union i386_operand_type
*x
)
1107 switch (ARRAY_SIZE(x
->array
))
1116 return !x
->array
[0];
1123 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1125 switch (ARRAY_SIZE(x
->array
))
1140 operand_type_equal (const union i386_operand_type
*x
,
1141 const union i386_operand_type
*y
)
1143 switch (ARRAY_SIZE(x
->array
))
1146 if (x
->array
[2] != y
->array
[2])
1149 if (x
->array
[1] != y
->array
[1])
1152 return x
->array
[0] == y
->array
[0];
1160 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1162 switch (ARRAY_SIZE(x
->array
))
1171 return !x
->array
[0];
1178 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1180 switch (ARRAY_SIZE(x
->array
))
1195 cpu_flags_equal (const union i386_cpu_flags
*x
,
1196 const union i386_cpu_flags
*y
)
1198 switch (ARRAY_SIZE(x
->array
))
1201 if (x
->array
[2] != y
->array
[2])
1204 if (x
->array
[1] != y
->array
[1])
1207 return x
->array
[0] == y
->array
[0];
1215 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1217 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1218 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1221 static INLINE i386_cpu_flags
1222 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] &= y
.array
[2];
1229 x
.array
[1] &= y
.array
[1];
1231 x
.array
[0] &= y
.array
[0];
1239 static INLINE i386_cpu_flags
1240 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1242 switch (ARRAY_SIZE (x
.array
))
1245 x
.array
[2] |= y
.array
[2];
1247 x
.array
[1] |= y
.array
[1];
1249 x
.array
[0] |= y
.array
[0];
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= ~y
.array
[2];
1265 x
.array
[1] &= ~y
.array
[1];
1267 x
.array
[0] &= ~y
.array
[0];
1275 #define CPU_FLAGS_ARCH_MATCH 0x1
1276 #define CPU_FLAGS_64BIT_MATCH 0x2
1277 #define CPU_FLAGS_AES_MATCH 0x4
1278 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1279 #define CPU_FLAGS_AVX_MATCH 0x10
1281 #define CPU_FLAGS_32BIT_MATCH \
1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1284 #define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1287 /* Return CPU flags match bits. */
1290 cpu_flags_match (const insn_template
*t
)
1292 i386_cpu_flags x
= t
->cpu_flags
;
1293 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1295 x
.bitfield
.cpu64
= 0;
1296 x
.bitfield
.cpuno64
= 0;
1298 if (cpu_flags_all_zero (&x
))
1300 /* This instruction is available on all archs. */
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1305 /* This instruction is available only on some archs. */
1306 i386_cpu_flags cpu
= cpu_arch_flags
;
1308 cpu
.bitfield
.cpu64
= 0;
1309 cpu
.bitfield
.cpuno64
= 0;
1310 cpu
= cpu_flags_and (x
, cpu
);
1311 if (!cpu_flags_all_zero (&cpu
))
1313 if (x
.bitfield
.cpuavx
)
1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1316 if (cpu
.bitfield
.cpuavx
)
1318 /* Check SSE2AVX. */
1319 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1321 match
|= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH
);
1324 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1325 match
|= CPU_FLAGS_AES_MATCH
;
1327 if (!x
.bitfield
.cpupclmul
1328 || cpu
.bitfield
.cpupclmul
)
1329 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1333 match
|= CPU_FLAGS_ARCH_MATCH
;
1336 match
|= CPU_FLAGS_32BIT_MATCH
;
1342 static INLINE i386_operand_type
1343 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] &= y
.array
[2];
1350 x
.array
[1] &= y
.array
[1];
1352 x
.array
[0] &= y
.array
[0];
1360 static INLINE i386_operand_type
1361 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1363 switch (ARRAY_SIZE (x
.array
))
1366 x
.array
[2] |= y
.array
[2];
1368 x
.array
[1] |= y
.array
[1];
1370 x
.array
[0] |= y
.array
[0];
1378 static INLINE i386_operand_type
1379 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1381 switch (ARRAY_SIZE (x
.array
))
1384 x
.array
[2] ^= y
.array
[2];
1386 x
.array
[1] ^= y
.array
[1];
1388 x
.array
[0] ^= y
.array
[0];
1396 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1397 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1398 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1399 static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG
;
1401 static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1403 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1404 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1405 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1406 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1407 static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP
;
1409 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1410 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1411 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1412 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1413 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1414 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1415 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1416 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1417 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1418 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1419 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1430 operand_type_check (i386_operand_type t
, enum operand_type c
)
1435 return (t
.bitfield
.reg8
1438 || t
.bitfield
.reg64
);
1441 return (t
.bitfield
.imm8
1445 || t
.bitfield
.imm32s
1446 || t
.bitfield
.imm64
);
1449 return (t
.bitfield
.disp8
1450 || t
.bitfield
.disp16
1451 || t
.bitfield
.disp32
1452 || t
.bitfield
.disp32s
1453 || t
.bitfield
.disp64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
1461 || t
.bitfield
.baseindex
);
1470 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1474 match_reg_size (const insn_template
*t
, unsigned int j
)
1476 return !((i
.types
[j
].bitfield
.byte
1477 && !t
->operand_types
[j
].bitfield
.byte
)
1478 || (i
.types
[j
].bitfield
.word
1479 && !t
->operand_types
[j
].bitfield
.word
)
1480 || (i
.types
[j
].bitfield
.dword
1481 && !t
->operand_types
[j
].bitfield
.dword
)
1482 || (i
.types
[j
].bitfield
.qword
1483 && !t
->operand_types
[j
].bitfield
.qword
));
1486 /* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1490 match_mem_size (const insn_template
*t
, unsigned int j
)
1492 return (match_reg_size (t
, j
)
1493 && !((i
.types
[j
].bitfield
.unspecified
1494 && !t
->operand_types
[j
].bitfield
.unspecified
)
1495 || (i
.types
[j
].bitfield
.fword
1496 && !t
->operand_types
[j
].bitfield
.fword
)
1497 || (i
.types
[j
].bitfield
.tbyte
1498 && !t
->operand_types
[j
].bitfield
.tbyte
)
1499 || (i
.types
[j
].bitfield
.xmmword
1500 && !t
->operand_types
[j
].bitfield
.xmmword
)
1501 || (i
.types
[j
].bitfield
.ymmword
1502 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1505 /* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1509 operand_size_match (const insn_template
*t
)
1514 /* Don't check jump instructions. */
1515 if (t
->opcode_modifier
.jump
1516 || t
->opcode_modifier
.jumpbyte
1517 || t
->opcode_modifier
.jumpdword
1518 || t
->opcode_modifier
.jumpintersegment
)
1521 /* Check memory and accumulator operand size. */
1522 for (j
= 0; j
< i
.operands
; j
++)
1524 if (t
->operand_types
[j
].bitfield
.anysize
)
1527 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1533 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1541 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1544 /* Check reverse. */
1545 gas_assert (i
.operands
== 2);
1548 for (j
= 0; j
< 2; j
++)
1550 if (t
->operand_types
[j
].bitfield
.acc
1551 && !match_reg_size (t
, j
? 0 : 1))
1557 if (i
.types
[j
].bitfield
.mem
1558 && !match_mem_size (t
, j
? 0 : 1))
1569 operand_type_match (i386_operand_type overlap
,
1570 i386_operand_type given
)
1572 i386_operand_type temp
= overlap
;
1574 temp
.bitfield
.jumpabsolute
= 0;
1575 temp
.bitfield
.unspecified
= 0;
1576 temp
.bitfield
.byte
= 0;
1577 temp
.bitfield
.word
= 0;
1578 temp
.bitfield
.dword
= 0;
1579 temp
.bitfield
.fword
= 0;
1580 temp
.bitfield
.qword
= 0;
1581 temp
.bitfield
.tbyte
= 0;
1582 temp
.bitfield
.xmmword
= 0;
1583 temp
.bitfield
.ymmword
= 0;
1584 if (operand_type_all_zero (&temp
))
1587 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1588 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1591 /* If given types g0 and g1 are registers they must be of the same type
1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1596 operand_type_register_match (i386_operand_type m0
,
1597 i386_operand_type g0
,
1598 i386_operand_type t0
,
1599 i386_operand_type m1
,
1600 i386_operand_type g1
,
1601 i386_operand_type t1
)
1603 if (!operand_type_check (g0
, reg
))
1606 if (!operand_type_check (g1
, reg
))
1609 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1610 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1611 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1612 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1615 if (m0
.bitfield
.acc
)
1617 t0
.bitfield
.reg8
= 1;
1618 t0
.bitfield
.reg16
= 1;
1619 t0
.bitfield
.reg32
= 1;
1620 t0
.bitfield
.reg64
= 1;
1623 if (m1
.bitfield
.acc
)
1625 t1
.bitfield
.reg8
= 1;
1626 t1
.bitfield
.reg16
= 1;
1627 t1
.bitfield
.reg32
= 1;
1628 t1
.bitfield
.reg64
= 1;
1631 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1632 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1633 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1634 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1637 static INLINE
unsigned int
1638 mode_from_disp_size (i386_operand_type t
)
1640 if (t
.bitfield
.disp8
)
1642 else if (t
.bitfield
.disp16
1643 || t
.bitfield
.disp32
1644 || t
.bitfield
.disp32s
)
1651 fits_in_signed_byte (offsetT num
)
1653 return (num
>= -128) && (num
<= 127);
1657 fits_in_unsigned_byte (offsetT num
)
1659 return (num
& 0xff) == num
;
1663 fits_in_unsigned_word (offsetT num
)
1665 return (num
& 0xffff) == num
;
1669 fits_in_signed_word (offsetT num
)
1671 return (-32768 <= num
) && (num
<= 32767);
1675 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1680 return (!(((offsetT
) -1 << 31) & num
)
1681 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1683 } /* fits_in_signed_long() */
1686 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1691 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1693 } /* fits_in_unsigned_long() */
1695 static i386_operand_type
1696 smallest_imm_type (offsetT num
)
1698 i386_operand_type t
;
1700 operand_type_set (&t
, 0);
1701 t
.bitfield
.imm64
= 1;
1703 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1710 t
.bitfield
.imm1
= 1;
1711 t
.bitfield
.imm8
= 1;
1712 t
.bitfield
.imm8s
= 1;
1713 t
.bitfield
.imm16
= 1;
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_signed_byte (num
))
1719 t
.bitfield
.imm8
= 1;
1720 t
.bitfield
.imm8s
= 1;
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_unsigned_byte (num
))
1727 t
.bitfield
.imm8
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1734 t
.bitfield
.imm16
= 1;
1735 t
.bitfield
.imm32
= 1;
1736 t
.bitfield
.imm32s
= 1;
1738 else if (fits_in_signed_long (num
))
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_unsigned_long (num
))
1744 t
.bitfield
.imm32
= 1;
1750 offset_in_range (offsetT val
, int size
)
1756 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1757 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1758 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1760 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1765 /* If BFD64, sign extend val. */
1766 if (!use_rela_relocations
)
1767 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1768 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1770 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1772 char buf1
[40], buf2
[40];
1774 sprint_value (buf1
, val
);
1775 sprint_value (buf2
, val
& mask
);
1776 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1781 /* Returns 0 if attempting to add a prefix where one from the same
1782 class already exists, 1 if non rep/repne added, 2 if rep/repne
1785 add_prefix (unsigned int prefix
)
1790 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1791 && flag_code
== CODE_64BIT
)
1793 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1794 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1795 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1806 case CS_PREFIX_OPCODE
:
1807 case DS_PREFIX_OPCODE
:
1808 case ES_PREFIX_OPCODE
:
1809 case FS_PREFIX_OPCODE
:
1810 case GS_PREFIX_OPCODE
:
1811 case SS_PREFIX_OPCODE
:
1815 case REPNE_PREFIX_OPCODE
:
1816 case REPE_PREFIX_OPCODE
:
1819 case LOCK_PREFIX_OPCODE
:
1827 case ADDR_PREFIX_OPCODE
:
1831 case DATA_PREFIX_OPCODE
:
1835 if (i
.prefix
[q
] != 0)
1843 i
.prefix
[q
] |= prefix
;
1846 as_bad (_("same type of prefix used twice"));
1852 set_code_flag (int value
)
1854 flag_code
= (enum flag_code
) value
;
1855 if (flag_code
== CODE_64BIT
)
1857 cpu_arch_flags
.bitfield
.cpu64
= 1;
1858 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1862 cpu_arch_flags
.bitfield
.cpu64
= 0;
1863 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1865 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1867 as_bad (_("64bit mode not supported on this CPU."));
1869 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1871 as_bad (_("32bit mode not supported on this CPU."));
1873 stackop_size
= '\0';
1877 set_16bit_gcc_code_flag (int new_code_flag
)
1879 flag_code
= (enum flag_code
) new_code_flag
;
1880 if (flag_code
!= CODE_16BIT
)
1882 cpu_arch_flags
.bitfield
.cpu64
= 0;
1883 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1884 stackop_size
= LONG_MNEM_SUFFIX
;
1888 set_intel_syntax (int syntax_flag
)
1890 /* Find out if register prefixing is specified. */
1891 int ask_naked_reg
= 0;
1894 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1896 char *string
= input_line_pointer
;
1897 int e
= get_symbol_end ();
1899 if (strcmp (string
, "prefix") == 0)
1901 else if (strcmp (string
, "noprefix") == 0)
1904 as_bad (_("bad argument to syntax directive."));
1905 *input_line_pointer
= e
;
1907 demand_empty_rest_of_line ();
1909 intel_syntax
= syntax_flag
;
1911 if (ask_naked_reg
== 0)
1912 allow_naked_reg
= (intel_syntax
1913 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1915 allow_naked_reg
= (ask_naked_reg
< 0);
1917 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1919 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1920 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1921 register_prefix
= allow_naked_reg
? "" : "%";
1925 set_intel_mnemonic (int mnemonic_flag
)
1927 intel_mnemonic
= mnemonic_flag
;
1931 set_allow_index_reg (int flag
)
1933 allow_index_reg
= flag
;
1937 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1941 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1943 char *string
= input_line_pointer
;
1944 int e
= get_symbol_end ();
1946 if (strcmp (string
, "none") == 0)
1947 sse_check
= sse_check_none
;
1948 else if (strcmp (string
, "warning") == 0)
1949 sse_check
= sse_check_warning
;
1950 else if (strcmp (string
, "error") == 0)
1951 sse_check
= sse_check_error
;
1953 as_bad (_("bad argument to sse_check directive."));
1954 *input_line_pointer
= e
;
1957 as_bad (_("missing argument for sse_check directive"));
1959 demand_empty_rest_of_line ();
1963 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1964 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1967 static const char *arch
;
1969 /* Intel LIOM is only supported on ELF. */
1975 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1976 use default_arch. */
1977 arch
= cpu_arch_name
;
1979 arch
= default_arch
;
1982 /* If we are targeting Intel L1OM, we must enable it. */
1983 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1984 || new_flag
.bitfield
.cpul1om
)
1987 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1992 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1996 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1998 char *string
= input_line_pointer
;
1999 int e
= get_symbol_end ();
2001 i386_cpu_flags flags
;
2003 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2005 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2007 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2011 cpu_arch_name
= cpu_arch
[i
].name
;
2012 cpu_sub_arch_name
= NULL
;
2013 cpu_arch_flags
= cpu_arch
[i
].flags
;
2014 if (flag_code
== CODE_64BIT
)
2016 cpu_arch_flags
.bitfield
.cpu64
= 1;
2017 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2021 cpu_arch_flags
.bitfield
.cpu64
= 0;
2022 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2024 cpu_arch_isa
= cpu_arch
[i
].type
;
2025 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2026 if (!cpu_arch_tune_set
)
2028 cpu_arch_tune
= cpu_arch_isa
;
2029 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2034 if (strncmp (string
+ 1, "no", 2))
2035 flags
= cpu_flags_or (cpu_arch_flags
,
2038 flags
= cpu_flags_and_not (cpu_arch_flags
,
2040 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2042 if (cpu_sub_arch_name
)
2044 char *name
= cpu_sub_arch_name
;
2045 cpu_sub_arch_name
= concat (name
,
2047 (const char *) NULL
);
2051 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2052 cpu_arch_flags
= flags
;
2054 *input_line_pointer
= e
;
2055 demand_empty_rest_of_line ();
2059 if (i
>= ARRAY_SIZE (cpu_arch
))
2060 as_bad (_("no such architecture: `%s'"), string
);
2062 *input_line_pointer
= e
;
2065 as_bad (_("missing cpu architecture"));
2067 no_cond_jump_promotion
= 0;
2068 if (*input_line_pointer
== ','
2069 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2071 char *string
= ++input_line_pointer
;
2072 int e
= get_symbol_end ();
2074 if (strcmp (string
, "nojumps") == 0)
2075 no_cond_jump_promotion
= 1;
2076 else if (strcmp (string
, "jumps") == 0)
2079 as_bad (_("no such architecture modifier: `%s'"), string
);
2081 *input_line_pointer
= e
;
2084 demand_empty_rest_of_line ();
2087 enum bfd_architecture
2090 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2093 || flag_code
!= CODE_64BIT
)
2094 as_fatal (_("Intel L1OM is 64bit ELF only"));
2095 return bfd_arch_l1om
;
2098 return bfd_arch_i386
;
2104 if (!strcmp (default_arch
, "x86_64"))
2106 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2108 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2109 as_fatal (_("Intel L1OM is 64bit ELF only"));
2110 return bfd_mach_l1om
;
2113 return bfd_mach_x86_64
;
2115 else if (!strcmp (default_arch
, "i386"))
2116 return bfd_mach_i386_i386
;
2118 as_fatal (_("Unknown architecture"));
2124 const char *hash_err
;
2126 /* Initialize op_hash hash table. */
2127 op_hash
= hash_new ();
2130 const insn_template
*optab
;
2131 templates
*core_optab
;
2133 /* Setup for loop. */
2135 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2136 core_optab
->start
= optab
;
2141 if (optab
->name
== NULL
2142 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2144 /* different name --> ship out current template list;
2145 add to hash table; & begin anew. */
2146 core_optab
->end
= optab
;
2147 hash_err
= hash_insert (op_hash
,
2149 (void *) core_optab
);
2152 as_fatal (_("Internal Error: Can't hash %s: %s"),
2156 if (optab
->name
== NULL
)
2158 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2159 core_optab
->start
= optab
;
2164 /* Initialize reg_hash hash table. */
2165 reg_hash
= hash_new ();
2167 const reg_entry
*regtab
;
2168 unsigned int regtab_size
= i386_regtab_size
;
2170 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2172 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2174 as_fatal (_("Internal Error: Can't hash %s: %s"),
2180 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2185 for (c
= 0; c
< 256; c
++)
2190 mnemonic_chars
[c
] = c
;
2191 register_chars
[c
] = c
;
2192 operand_chars
[c
] = c
;
2194 else if (ISLOWER (c
))
2196 mnemonic_chars
[c
] = c
;
2197 register_chars
[c
] = c
;
2198 operand_chars
[c
] = c
;
2200 else if (ISUPPER (c
))
2202 mnemonic_chars
[c
] = TOLOWER (c
);
2203 register_chars
[c
] = mnemonic_chars
[c
];
2204 operand_chars
[c
] = c
;
2207 if (ISALPHA (c
) || ISDIGIT (c
))
2208 identifier_chars
[c
] = c
;
2211 identifier_chars
[c
] = c
;
2212 operand_chars
[c
] = c
;
2217 identifier_chars
['@'] = '@';
2220 identifier_chars
['?'] = '?';
2221 operand_chars
['?'] = '?';
2223 digit_chars
['-'] = '-';
2224 mnemonic_chars
['_'] = '_';
2225 mnemonic_chars
['-'] = '-';
2226 mnemonic_chars
['.'] = '.';
2227 identifier_chars
['_'] = '_';
2228 identifier_chars
['.'] = '.';
2230 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2231 operand_chars
[(unsigned char) *p
] = *p
;
2234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2237 record_alignment (text_section
, 2);
2238 record_alignment (data_section
, 2);
2239 record_alignment (bss_section
, 2);
2243 if (flag_code
== CODE_64BIT
)
2245 x86_dwarf2_return_column
= 16;
2246 x86_cie_data_alignment
= -8;
2250 x86_dwarf2_return_column
= 8;
2251 x86_cie_data_alignment
= -4;
2256 i386_print_statistics (FILE *file
)
2258 hash_print_statistics (file
, "i386 opcode", op_hash
);
2259 hash_print_statistics (file
, "i386 register", reg_hash
);
2264 /* Debugging routines for md_assemble. */
2265 static void pte (insn_template
*);
2266 static void pt (i386_operand_type
);
2267 static void pe (expressionS
*);
2268 static void ps (symbolS
*);
2271 pi (char *line
, i386_insn
*x
)
2275 fprintf (stdout
, "%s: template ", line
);
2277 fprintf (stdout
, " address: base %s index %s scale %x\n",
2278 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2279 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2280 x
->log2_scale_factor
);
2281 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2282 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2283 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2284 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2285 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2286 (x
->rex
& REX_W
) != 0,
2287 (x
->rex
& REX_R
) != 0,
2288 (x
->rex
& REX_X
) != 0,
2289 (x
->rex
& REX_B
) != 0);
2290 for (i
= 0; i
< x
->operands
; i
++)
2292 fprintf (stdout
, " #%d: ", i
+ 1);
2294 fprintf (stdout
, "\n");
2295 if (x
->types
[i
].bitfield
.reg8
2296 || x
->types
[i
].bitfield
.reg16
2297 || x
->types
[i
].bitfield
.reg32
2298 || x
->types
[i
].bitfield
.reg64
2299 || x
->types
[i
].bitfield
.regmmx
2300 || x
->types
[i
].bitfield
.regxmm
2301 || x
->types
[i
].bitfield
.regymm
2302 || x
->types
[i
].bitfield
.sreg2
2303 || x
->types
[i
].bitfield
.sreg3
2304 || x
->types
[i
].bitfield
.control
2305 || x
->types
[i
].bitfield
.debug
2306 || x
->types
[i
].bitfield
.test
)
2307 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2308 if (operand_type_check (x
->types
[i
], imm
))
2310 if (operand_type_check (x
->types
[i
], disp
))
2311 pe (x
->op
[i
].disps
);
2316 pte (insn_template
*t
)
2319 fprintf (stdout
, " %d operands ", t
->operands
);
2320 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2321 if (t
->extension_opcode
!= None
)
2322 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2323 if (t
->opcode_modifier
.d
)
2324 fprintf (stdout
, "D");
2325 if (t
->opcode_modifier
.w
)
2326 fprintf (stdout
, "W");
2327 fprintf (stdout
, "\n");
2328 for (i
= 0; i
< t
->operands
; i
++)
2330 fprintf (stdout
, " #%d type ", i
+ 1);
2331 pt (t
->operand_types
[i
]);
2332 fprintf (stdout
, "\n");
2339 fprintf (stdout
, " operation %d\n", e
->X_op
);
2340 fprintf (stdout
, " add_number %ld (%lx)\n",
2341 (long) e
->X_add_number
, (long) e
->X_add_number
);
2342 if (e
->X_add_symbol
)
2344 fprintf (stdout
, " add_symbol ");
2345 ps (e
->X_add_symbol
);
2346 fprintf (stdout
, "\n");
2350 fprintf (stdout
, " op_symbol ");
2351 ps (e
->X_op_symbol
);
2352 fprintf (stdout
, "\n");
2359 fprintf (stdout
, "%s type %s%s",
2361 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2362 segment_name (S_GET_SEGMENT (s
)));
2365 static struct type_name
2367 i386_operand_type mask
;
2370 const type_names
[] =
2372 { OPERAND_TYPE_REG8
, "r8" },
2373 { OPERAND_TYPE_REG16
, "r16" },
2374 { OPERAND_TYPE_REG32
, "r32" },
2375 { OPERAND_TYPE_REG64
, "r64" },
2376 { OPERAND_TYPE_IMM8
, "i8" },
2377 { OPERAND_TYPE_IMM8
, "i8s" },
2378 { OPERAND_TYPE_IMM16
, "i16" },
2379 { OPERAND_TYPE_IMM32
, "i32" },
2380 { OPERAND_TYPE_IMM32S
, "i32s" },
2381 { OPERAND_TYPE_IMM64
, "i64" },
2382 { OPERAND_TYPE_IMM1
, "i1" },
2383 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2384 { OPERAND_TYPE_DISP8
, "d8" },
2385 { OPERAND_TYPE_DISP16
, "d16" },
2386 { OPERAND_TYPE_DISP32
, "d32" },
2387 { OPERAND_TYPE_DISP32S
, "d32s" },
2388 { OPERAND_TYPE_DISP64
, "d64" },
2389 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2390 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2391 { OPERAND_TYPE_CONTROL
, "control reg" },
2392 { OPERAND_TYPE_TEST
, "test reg" },
2393 { OPERAND_TYPE_DEBUG
, "debug reg" },
2394 { OPERAND_TYPE_FLOATREG
, "FReg" },
2395 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2396 { OPERAND_TYPE_SREG2
, "SReg2" },
2397 { OPERAND_TYPE_SREG3
, "SReg3" },
2398 { OPERAND_TYPE_ACC
, "Acc" },
2399 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2400 { OPERAND_TYPE_REGMMX
, "rMMX" },
2401 { OPERAND_TYPE_REGXMM
, "rXMM" },
2402 { OPERAND_TYPE_REGYMM
, "rYMM" },
2403 { OPERAND_TYPE_ESSEG
, "es" },
2407 pt (i386_operand_type t
)
2410 i386_operand_type a
;
2412 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2414 a
= operand_type_and (t
, type_names
[j
].mask
);
2415 if (!operand_type_all_zero (&a
))
2416 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2421 #endif /* DEBUG386 */
2423 static bfd_reloc_code_real_type
2424 reloc (unsigned int size
,
2427 bfd_reloc_code_real_type other
)
2429 if (other
!= NO_RELOC
)
2431 reloc_howto_type
*reloc
;
2436 case BFD_RELOC_X86_64_GOT32
:
2437 return BFD_RELOC_X86_64_GOT64
;
2439 case BFD_RELOC_X86_64_PLTOFF64
:
2440 return BFD_RELOC_X86_64_PLTOFF64
;
2442 case BFD_RELOC_X86_64_GOTPC32
:
2443 other
= BFD_RELOC_X86_64_GOTPC64
;
2445 case BFD_RELOC_X86_64_GOTPCREL
:
2446 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2448 case BFD_RELOC_X86_64_TPOFF32
:
2449 other
= BFD_RELOC_X86_64_TPOFF64
;
2451 case BFD_RELOC_X86_64_DTPOFF32
:
2452 other
= BFD_RELOC_X86_64_DTPOFF64
;
2458 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2459 if (size
== 4 && flag_code
!= CODE_64BIT
)
2462 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2464 as_bad (_("unknown relocation (%u)"), other
);
2465 else if (size
!= bfd_get_reloc_size (reloc
))
2466 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2467 bfd_get_reloc_size (reloc
),
2469 else if (pcrel
&& !reloc
->pc_relative
)
2470 as_bad (_("non-pc-relative relocation for pc-relative field"));
2471 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2473 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2475 as_bad (_("relocated field and relocation type differ in signedness"));
2484 as_bad (_("there are no unsigned pc-relative relocations"));
2487 case 1: return BFD_RELOC_8_PCREL
;
2488 case 2: return BFD_RELOC_16_PCREL
;
2489 case 4: return BFD_RELOC_32_PCREL
;
2490 case 8: return BFD_RELOC_64_PCREL
;
2492 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2499 case 4: return BFD_RELOC_X86_64_32S
;
2504 case 1: return BFD_RELOC_8
;
2505 case 2: return BFD_RELOC_16
;
2506 case 4: return BFD_RELOC_32
;
2507 case 8: return BFD_RELOC_64
;
2509 as_bad (_("cannot do %s %u byte relocation"),
2510 sign
> 0 ? "signed" : "unsigned", size
);
2516 /* Here we decide which fixups can be adjusted to make them relative to
2517 the beginning of the section instead of the symbol. Basically we need
2518 to make sure that the dynamic relocations are done correctly, so in
2519 some cases we force the original symbol to be used. */
2522 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2528 /* Don't adjust pc-relative references to merge sections in 64-bit
2530 if (use_rela_relocations
2531 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2535 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2536 and changed later by validate_fix. */
2537 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2538 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2541 /* adjust_reloc_syms doesn't know about the GOT. */
2542 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2543 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2544 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2545 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2546 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2547 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2555 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2556 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2557 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2568 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2569 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2576 intel_float_operand (const char *mnemonic
)
2578 /* Note that the value returned is meaningful only for opcodes with (memory)
2579 operands, hence the code here is free to improperly handle opcodes that
2580 have no operands (for better performance and smaller code). */
2582 if (mnemonic
[0] != 'f')
2583 return 0; /* non-math */
2585 switch (mnemonic
[1])
2587 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2588 the fs segment override prefix not currently handled because no
2589 call path can make opcodes without operands get here */
2591 return 2 /* integer op */;
2593 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2594 return 3; /* fldcw/fldenv */
2597 if (mnemonic
[2] != 'o' /* fnop */)
2598 return 3; /* non-waiting control op */
2601 if (mnemonic
[2] == 's')
2602 return 3; /* frstor/frstpm */
2605 if (mnemonic
[2] == 'a')
2606 return 3; /* fsave */
2607 if (mnemonic
[2] == 't')
2609 switch (mnemonic
[3])
2611 case 'c': /* fstcw */
2612 case 'd': /* fstdw */
2613 case 'e': /* fstenv */
2614 case 's': /* fsts[gw] */
2620 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2621 return 0; /* fxsave/fxrstor are not really math ops */
2628 /* Build the VEX prefix. */
2631 build_vex_prefix (const insn_template
*t
)
2633 unsigned int register_specifier
;
2634 unsigned int implied_prefix
;
2635 unsigned int vector_length
;
2637 /* Check register specifier. */
2638 if (i
.vex
.register_specifier
)
2640 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2641 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2642 register_specifier
+= 8;
2643 register_specifier
= ~register_specifier
& 0xf;
2646 register_specifier
= 0xf;
2648 /* Use 2-byte VEX prefix by swappping destination and source
2651 && i
.operands
== i
.reg_operands
2652 && i
.tm
.opcode_modifier
.vex0f
2653 && i
.tm
.opcode_modifier
.s
2656 unsigned int xchg
= i
.operands
- 1;
2657 union i386_op temp_op
;
2658 i386_operand_type temp_type
;
2660 temp_type
= i
.types
[xchg
];
2661 i
.types
[xchg
] = i
.types
[0];
2662 i
.types
[0] = temp_type
;
2663 temp_op
= i
.op
[xchg
];
2664 i
.op
[xchg
] = i
.op
[0];
2667 gas_assert (i
.rm
.mode
== 3);
2671 i
.rm
.regmem
= i
.rm
.reg
;
2674 /* Use the next insn. */
2678 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2680 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2685 case DATA_PREFIX_OPCODE
:
2688 case REPE_PREFIX_OPCODE
:
2691 case REPNE_PREFIX_OPCODE
:
2698 /* Use 2-byte VEX prefix if possible. */
2699 if (i
.tm
.opcode_modifier
.vex0f
2700 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2702 /* 2-byte VEX prefix. */
2706 i
.vex
.bytes
[0] = 0xc5;
2708 /* Check the REX.R bit. */
2709 r
= (i
.rex
& REX_R
) ? 0 : 1;
2710 i
.vex
.bytes
[1] = (r
<< 7
2711 | register_specifier
<< 3
2712 | vector_length
<< 2
2717 /* 3-byte VEX prefix. */
2720 if (i
.tm
.opcode_modifier
.vex0f
)
2722 else if (i
.tm
.opcode_modifier
.vex0f38
)
2724 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2730 i
.vex
.bytes
[0] = 0xc4;
2732 /* The high 3 bits of the second VEX byte are 1's compliment
2733 of RXB bits from REX. */
2734 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2736 /* Check the REX.W bit. */
2737 w
= (i
.rex
& REX_W
) ? 1 : 0;
2738 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2743 if (i
.tm
.opcode_modifier
.vexw1
)
2747 i
.vex
.bytes
[2] = (w
<< 7
2748 | register_specifier
<< 3
2749 | vector_length
<< 2
2755 process_immext (void)
2759 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2761 /* SSE3 Instructions have the fixed operands with an opcode
2762 suffix which is coded in the same place as an 8-bit immediate
2763 field would be. Here we check those operands and remove them
2767 for (x
= 0; x
< i
.operands
; x
++)
2768 if (i
.op
[x
].regs
->reg_num
!= x
)
2769 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2770 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2776 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2777 which is coded in the same place as an 8-bit immediate field
2778 would be. Here we fake an 8-bit immediate operand from the
2779 opcode suffix stored in tm.extension_opcode.
2781 AVX instructions also use this encoding, for some of
2782 3 argument instructions. */
2784 gas_assert (i
.imm_operands
== 0
2786 || (i
.tm
.opcode_modifier
.vex
2787 && i
.operands
<= 4)));
2789 exp
= &im_expressions
[i
.imm_operands
++];
2790 i
.op
[i
.operands
].imms
= exp
;
2791 i
.types
[i
.operands
] = imm8
;
2793 exp
->X_op
= O_constant
;
2794 exp
->X_add_number
= i
.tm
.extension_opcode
;
2795 i
.tm
.extension_opcode
= None
;
2798 /* This is the guts of the machine-dependent assembler. LINE points to a
2799 machine dependent instruction. This function is supposed to emit
2800 the frags/bytes it assembles to. */
2803 md_assemble (char *line
)
2806 char mnemonic
[MAX_MNEM_SIZE
];
2807 const insn_template
*t
;
2809 /* Initialize globals. */
2810 memset (&i
, '\0', sizeof (i
));
2811 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2812 i
.reloc
[j
] = NO_RELOC
;
2813 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2814 memset (im_expressions
, '\0', sizeof (im_expressions
));
2815 save_stack_p
= save_stack
;
2817 /* First parse an instruction mnemonic & call i386_operand for the operands.
2818 We assume that the scrubber has arranged it so that line[0] is the valid
2819 start of a (possibly prefixed) mnemonic. */
2821 line
= parse_insn (line
, mnemonic
);
2825 line
= parse_operands (line
, mnemonic
);
2830 /* Now we've parsed the mnemonic into a set of templates, and have the
2831 operands at hand. */
2833 /* All intel opcodes have reversed operands except for "bound" and
2834 "enter". We also don't reverse intersegment "jmp" and "call"
2835 instructions with 2 immediate operands so that the immediate segment
2836 precedes the offset, as it does when in AT&T mode. */
2839 && (strcmp (mnemonic
, "bound") != 0)
2840 && (strcmp (mnemonic
, "invlpga") != 0)
2841 && !(operand_type_check (i
.types
[0], imm
)
2842 && operand_type_check (i
.types
[1], imm
)))
2845 /* The order of the immediates should be reversed
2846 for 2 immediates extrq and insertq instructions */
2847 if (i
.imm_operands
== 2
2848 && (strcmp (mnemonic
, "extrq") == 0
2849 || strcmp (mnemonic
, "insertq") == 0))
2850 swap_2_operands (0, 1);
2855 /* Don't optimize displacement for movabs since it only takes 64bit
2858 && (flag_code
!= CODE_64BIT
2859 || strcmp (mnemonic
, "movabs") != 0))
2862 /* Next, we find a template that matches the given insn,
2863 making sure the overlap of the given operands types is consistent
2864 with the template operand types. */
2866 if (!(t
= match_template ()))
2869 if (sse_check
!= sse_check_none
2870 && !i
.tm
.opcode_modifier
.noavx
2871 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2872 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2873 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2874 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2875 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2876 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2878 (sse_check
== sse_check_warning
2880 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2883 /* Zap movzx and movsx suffix. The suffix has been set from
2884 "word ptr" or "byte ptr" on the source operand in Intel syntax
2885 or extracted from mnemonic in AT&T syntax. But we'll use
2886 the destination register to choose the suffix for encoding. */
2887 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2889 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2890 there is no suffix, the default will be byte extension. */
2891 if (i
.reg_operands
!= 2
2894 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2899 if (i
.tm
.opcode_modifier
.fwait
)
2900 if (!add_prefix (FWAIT_OPCODE
))
2903 /* Check string instruction segment overrides. */
2904 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2906 if (!check_string ())
2908 i
.disp_operands
= 0;
2911 if (!process_suffix ())
2914 /* Update operand types. */
2915 for (j
= 0; j
< i
.operands
; j
++)
2916 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2918 /* Make still unresolved immediate matches conform to size of immediate
2919 given in i.suffix. */
2920 if (!finalize_imm ())
2923 if (i
.types
[0].bitfield
.imm1
)
2924 i
.imm_operands
= 0; /* kludge for shift insns. */
2926 /* We only need to check those implicit registers for instructions
2927 with 3 operands or less. */
2928 if (i
.operands
<= 3)
2929 for (j
= 0; j
< i
.operands
; j
++)
2930 if (i
.types
[j
].bitfield
.inoutportreg
2931 || i
.types
[j
].bitfield
.shiftcount
2932 || i
.types
[j
].bitfield
.acc
2933 || i
.types
[j
].bitfield
.floatacc
)
2936 /* ImmExt should be processed after SSE2AVX. */
2937 if (!i
.tm
.opcode_modifier
.sse2avx
2938 && i
.tm
.opcode_modifier
.immext
)
2941 /* For insns with operands there are more diddles to do to the opcode. */
2944 if (!process_operands ())
2947 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2949 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2950 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2953 if (i
.tm
.opcode_modifier
.vex
)
2954 build_vex_prefix (t
);
2956 /* Handle conversion of 'int $3' --> special int3 insn. */
2957 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2959 i
.tm
.base_opcode
= INT3_OPCODE
;
2963 if ((i
.tm
.opcode_modifier
.jump
2964 || i
.tm
.opcode_modifier
.jumpbyte
2965 || i
.tm
.opcode_modifier
.jumpdword
)
2966 && i
.op
[0].disps
->X_op
== O_constant
)
2968 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2969 the absolute address given by the constant. Since ix86 jumps and
2970 calls are pc relative, we need to generate a reloc. */
2971 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2972 i
.op
[0].disps
->X_op
= O_symbol
;
2975 if (i
.tm
.opcode_modifier
.rex64
)
2978 /* For 8 bit registers we need an empty rex prefix. Also if the
2979 instruction already has a prefix, we need to convert old
2980 registers to new ones. */
2982 if ((i
.types
[0].bitfield
.reg8
2983 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2984 || (i
.types
[1].bitfield
.reg8
2985 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2986 || ((i
.types
[0].bitfield
.reg8
2987 || i
.types
[1].bitfield
.reg8
)
2992 i
.rex
|= REX_OPCODE
;
2993 for (x
= 0; x
< 2; x
++)
2995 /* Look for 8 bit operand that uses old registers. */
2996 if (i
.types
[x
].bitfield
.reg8
2997 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2999 /* In case it is "hi" register, give up. */
3000 if (i
.op
[x
].regs
->reg_num
> 3)
3001 as_bad (_("can't encode register '%s%s' in an "
3002 "instruction requiring REX prefix."),
3003 register_prefix
, i
.op
[x
].regs
->reg_name
);
3005 /* Otherwise it is equivalent to the extended register.
3006 Since the encoding doesn't change this is merely
3007 cosmetic cleanup for debug output. */
3009 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3015 add_prefix (REX_OPCODE
| i
.rex
);
3017 /* We are ready to output the insn. */
3022 parse_insn (char *line
, char *mnemonic
)
3025 char *token_start
= l
;
3028 const insn_template
*t
;
3031 /* Non-zero if we found a prefix only acceptable with string insns. */
3032 const char *expecting_string_instruction
= NULL
;
3037 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3042 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3044 as_bad (_("no such instruction: `%s'"), token_start
);
3049 if (!is_space_char (*l
)
3050 && *l
!= END_OF_INSN
3052 || (*l
!= PREFIX_SEPARATOR
3055 as_bad (_("invalid character %s in mnemonic"),
3056 output_invalid (*l
));
3059 if (token_start
== l
)
3061 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3062 as_bad (_("expecting prefix; got nothing"));
3064 as_bad (_("expecting mnemonic; got nothing"));
3068 /* Look up instruction (or prefix) via hash table. */
3069 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3071 if (*l
!= END_OF_INSN
3072 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3073 && current_templates
3074 && current_templates
->start
->opcode_modifier
.isprefix
)
3076 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3078 as_bad ((flag_code
!= CODE_64BIT
3079 ? _("`%s' is only supported in 64-bit mode")
3080 : _("`%s' is not supported in 64-bit mode")),
3081 current_templates
->start
->name
);
3084 /* If we are in 16-bit mode, do not allow addr16 or data16.
3085 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3086 if ((current_templates
->start
->opcode_modifier
.size16
3087 || current_templates
->start
->opcode_modifier
.size32
)
3088 && flag_code
!= CODE_64BIT
3089 && (current_templates
->start
->opcode_modifier
.size32
3090 ^ (flag_code
== CODE_16BIT
)))
3092 as_bad (_("redundant %s prefix"),
3093 current_templates
->start
->name
);
3096 /* Add prefix, checking for repeated prefixes. */
3097 switch (add_prefix (current_templates
->start
->base_opcode
))
3102 expecting_string_instruction
= current_templates
->start
->name
;
3105 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3112 if (!current_templates
)
3114 /* Check if we should swap operand in encoding. */
3115 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3121 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3124 if (!current_templates
)
3127 /* See if we can get a match by trimming off a suffix. */
3130 case WORD_MNEM_SUFFIX
:
3131 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3132 i
.suffix
= SHORT_MNEM_SUFFIX
;
3134 case BYTE_MNEM_SUFFIX
:
3135 case QWORD_MNEM_SUFFIX
:
3136 i
.suffix
= mnem_p
[-1];
3138 current_templates
= (const templates
*) hash_find (op_hash
,
3141 case SHORT_MNEM_SUFFIX
:
3142 case LONG_MNEM_SUFFIX
:
3145 i
.suffix
= mnem_p
[-1];
3147 current_templates
= (const templates
*) hash_find (op_hash
,
3156 if (intel_float_operand (mnemonic
) == 1)
3157 i
.suffix
= SHORT_MNEM_SUFFIX
;
3159 i
.suffix
= LONG_MNEM_SUFFIX
;
3161 current_templates
= (const templates
*) hash_find (op_hash
,
3166 if (!current_templates
)
3168 as_bad (_("no such instruction: `%s'"), token_start
);
3173 if (current_templates
->start
->opcode_modifier
.jump
3174 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3176 /* Check for a branch hint. We allow ",pt" and ",pn" for
3177 predict taken and predict not taken respectively.
3178 I'm not sure that branch hints actually do anything on loop
3179 and jcxz insns (JumpByte) for current Pentium4 chips. They
3180 may work in the future and it doesn't hurt to accept them
3182 if (l
[0] == ',' && l
[1] == 'p')
3186 if (!add_prefix (DS_PREFIX_OPCODE
))
3190 else if (l
[2] == 'n')
3192 if (!add_prefix (CS_PREFIX_OPCODE
))
3198 /* Any other comma loses. */
3201 as_bad (_("invalid character %s in mnemonic"),
3202 output_invalid (*l
));
3206 /* Check if instruction is supported on specified architecture. */
3208 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3210 supported
|= cpu_flags_match (t
);
3211 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3215 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3217 as_bad (flag_code
== CODE_64BIT
3218 ? _("`%s' is not supported in 64-bit mode")
3219 : _("`%s' is only supported in 64-bit mode"),
3220 current_templates
->start
->name
);
3223 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3225 as_bad (_("`%s' is not supported on `%s%s'"),
3226 current_templates
->start
->name
,
3227 cpu_arch_name
? cpu_arch_name
: default_arch
,
3228 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3233 if (!cpu_arch_flags
.bitfield
.cpui386
3234 && (flag_code
!= CODE_16BIT
))
3236 as_warn (_("use .code16 to ensure correct addressing mode"));
3239 /* Check for rep/repne without a string instruction. */
3240 if (expecting_string_instruction
)
3242 static templates override
;
3244 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3245 if (t
->opcode_modifier
.isstring
)
3247 if (t
>= current_templates
->end
)
3249 as_bad (_("expecting string instruction after `%s'"),
3250 expecting_string_instruction
);
3253 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3254 if (!t
->opcode_modifier
.isstring
)
3257 current_templates
= &override
;
3264 parse_operands (char *l
, const char *mnemonic
)
3268 /* 1 if operand is pending after ','. */
3269 unsigned int expecting_operand
= 0;
3271 /* Non-zero if operand parens not balanced. */
3272 unsigned int paren_not_balanced
;
3274 while (*l
!= END_OF_INSN
)
3276 /* Skip optional white space before operand. */
3277 if (is_space_char (*l
))
3279 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3281 as_bad (_("invalid character %s before operand %d"),
3282 output_invalid (*l
),
3286 token_start
= l
; /* after white space */
3287 paren_not_balanced
= 0;
3288 while (paren_not_balanced
|| *l
!= ',')
3290 if (*l
== END_OF_INSN
)
3292 if (paren_not_balanced
)
3295 as_bad (_("unbalanced parenthesis in operand %d."),
3298 as_bad (_("unbalanced brackets in operand %d."),
3303 break; /* we are done */
3305 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3307 as_bad (_("invalid character %s in operand %d"),
3308 output_invalid (*l
),
3315 ++paren_not_balanced
;
3317 --paren_not_balanced
;
3322 ++paren_not_balanced
;
3324 --paren_not_balanced
;
3328 if (l
!= token_start
)
3329 { /* Yes, we've read in another operand. */
3330 unsigned int operand_ok
;
3331 this_operand
= i
.operands
++;
3332 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3333 if (i
.operands
> MAX_OPERANDS
)
3335 as_bad (_("spurious operands; (%d operands/instruction max)"),
3339 /* Now parse operand adding info to 'i' as we go along. */
3340 END_STRING_AND_SAVE (l
);
3344 i386_intel_operand (token_start
,
3345 intel_float_operand (mnemonic
));
3347 operand_ok
= i386_att_operand (token_start
);
3349 RESTORE_END_STRING (l
);
3355 if (expecting_operand
)
3357 expecting_operand_after_comma
:
3358 as_bad (_("expecting operand after ','; got nothing"));
3363 as_bad (_("expecting operand before ','; got nothing"));
3368 /* Now *l must be either ',' or END_OF_INSN. */
3371 if (*++l
== END_OF_INSN
)
3373 /* Just skip it, if it's \n complain. */
3374 goto expecting_operand_after_comma
;
3376 expecting_operand
= 1;
3383 swap_2_operands (int xchg1
, int xchg2
)
3385 union i386_op temp_op
;
3386 i386_operand_type temp_type
;
3387 enum bfd_reloc_code_real temp_reloc
;
3389 temp_type
= i
.types
[xchg2
];
3390 i
.types
[xchg2
] = i
.types
[xchg1
];
3391 i
.types
[xchg1
] = temp_type
;
3392 temp_op
= i
.op
[xchg2
];
3393 i
.op
[xchg2
] = i
.op
[xchg1
];
3394 i
.op
[xchg1
] = temp_op
;
3395 temp_reloc
= i
.reloc
[xchg2
];
3396 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3397 i
.reloc
[xchg1
] = temp_reloc
;
3401 swap_operands (void)
3407 swap_2_operands (1, i
.operands
- 2);
3410 swap_2_operands (0, i
.operands
- 1);
3416 if (i
.mem_operands
== 2)
3418 const seg_entry
*temp_seg
;
3419 temp_seg
= i
.seg
[0];
3420 i
.seg
[0] = i
.seg
[1];
3421 i
.seg
[1] = temp_seg
;
3425 /* Try to ensure constant immediates are represented in the smallest
3430 char guess_suffix
= 0;
3434 guess_suffix
= i
.suffix
;
3435 else if (i
.reg_operands
)
3437 /* Figure out a suffix from the last register operand specified.
3438 We can't do this properly yet, ie. excluding InOutPortReg,
3439 but the following works for instructions with immediates.
3440 In any case, we can't set i.suffix yet. */
3441 for (op
= i
.operands
; --op
>= 0;)
3442 if (i
.types
[op
].bitfield
.reg8
)
3444 guess_suffix
= BYTE_MNEM_SUFFIX
;
3447 else if (i
.types
[op
].bitfield
.reg16
)
3449 guess_suffix
= WORD_MNEM_SUFFIX
;
3452 else if (i
.types
[op
].bitfield
.reg32
)
3454 guess_suffix
= LONG_MNEM_SUFFIX
;
3457 else if (i
.types
[op
].bitfield
.reg64
)
3459 guess_suffix
= QWORD_MNEM_SUFFIX
;
3463 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3464 guess_suffix
= WORD_MNEM_SUFFIX
;
3466 for (op
= i
.operands
; --op
>= 0;)
3467 if (operand_type_check (i
.types
[op
], imm
))
3469 switch (i
.op
[op
].imms
->X_op
)
3472 /* If a suffix is given, this operand may be shortened. */
3473 switch (guess_suffix
)
3475 case LONG_MNEM_SUFFIX
:
3476 i
.types
[op
].bitfield
.imm32
= 1;
3477 i
.types
[op
].bitfield
.imm64
= 1;
3479 case WORD_MNEM_SUFFIX
:
3480 i
.types
[op
].bitfield
.imm16
= 1;
3481 i
.types
[op
].bitfield
.imm32
= 1;
3482 i
.types
[op
].bitfield
.imm32s
= 1;
3483 i
.types
[op
].bitfield
.imm64
= 1;
3485 case BYTE_MNEM_SUFFIX
:
3486 i
.types
[op
].bitfield
.imm8
= 1;
3487 i
.types
[op
].bitfield
.imm8s
= 1;
3488 i
.types
[op
].bitfield
.imm16
= 1;
3489 i
.types
[op
].bitfield
.imm32
= 1;
3490 i
.types
[op
].bitfield
.imm32s
= 1;
3491 i
.types
[op
].bitfield
.imm64
= 1;
3495 /* If this operand is at most 16 bits, convert it
3496 to a signed 16 bit number before trying to see
3497 whether it will fit in an even smaller size.
3498 This allows a 16-bit operand such as $0xffe0 to
3499 be recognised as within Imm8S range. */
3500 if ((i
.types
[op
].bitfield
.imm16
)
3501 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3503 i
.op
[op
].imms
->X_add_number
=
3504 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3506 if ((i
.types
[op
].bitfield
.imm32
)
3507 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3510 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3511 ^ ((offsetT
) 1 << 31))
3512 - ((offsetT
) 1 << 31));
3515 = operand_type_or (i
.types
[op
],
3516 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3518 /* We must avoid matching of Imm32 templates when 64bit
3519 only immediate is available. */
3520 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3521 i
.types
[op
].bitfield
.imm32
= 0;
3528 /* Symbols and expressions. */
3530 /* Convert symbolic operand to proper sizes for matching, but don't
3531 prevent matching a set of insns that only supports sizes other
3532 than those matching the insn suffix. */
3534 i386_operand_type mask
, allowed
;
3535 const insn_template
*t
;
3537 operand_type_set (&mask
, 0);
3538 operand_type_set (&allowed
, 0);
3540 for (t
= current_templates
->start
;
3541 t
< current_templates
->end
;
3543 allowed
= operand_type_or (allowed
,
3544 t
->operand_types
[op
]);
3545 switch (guess_suffix
)
3547 case QWORD_MNEM_SUFFIX
:
3548 mask
.bitfield
.imm64
= 1;
3549 mask
.bitfield
.imm32s
= 1;
3551 case LONG_MNEM_SUFFIX
:
3552 mask
.bitfield
.imm32
= 1;
3554 case WORD_MNEM_SUFFIX
:
3555 mask
.bitfield
.imm16
= 1;
3557 case BYTE_MNEM_SUFFIX
:
3558 mask
.bitfield
.imm8
= 1;
3563 allowed
= operand_type_and (mask
, allowed
);
3564 if (!operand_type_all_zero (&allowed
))
3565 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3572 /* Try to use the smallest displacement type too. */
3574 optimize_disp (void)
3578 for (op
= i
.operands
; --op
>= 0;)
3579 if (operand_type_check (i
.types
[op
], disp
))
3581 if (i
.op
[op
].disps
->X_op
== O_constant
)
3583 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3585 if (i
.types
[op
].bitfield
.disp16
3586 && (disp
& ~(offsetT
) 0xffff) == 0)
3588 /* If this operand is at most 16 bits, convert
3589 to a signed 16 bit number and don't use 64bit
3591 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3592 i
.types
[op
].bitfield
.disp64
= 0;
3594 if (i
.types
[op
].bitfield
.disp32
3595 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3597 /* If this operand is at most 32 bits, convert
3598 to a signed 32 bit number and don't use 64bit
3600 disp
&= (((offsetT
) 2 << 31) - 1);
3601 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3602 i
.types
[op
].bitfield
.disp64
= 0;
3604 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3606 i
.types
[op
].bitfield
.disp8
= 0;
3607 i
.types
[op
].bitfield
.disp16
= 0;
3608 i
.types
[op
].bitfield
.disp32
= 0;
3609 i
.types
[op
].bitfield
.disp32s
= 0;
3610 i
.types
[op
].bitfield
.disp64
= 0;
3614 else if (flag_code
== CODE_64BIT
)
3616 if (fits_in_signed_long (disp
))
3618 i
.types
[op
].bitfield
.disp64
= 0;
3619 i
.types
[op
].bitfield
.disp32s
= 1;
3621 if (fits_in_unsigned_long (disp
))
3622 i
.types
[op
].bitfield
.disp32
= 1;
3624 if ((i
.types
[op
].bitfield
.disp32
3625 || i
.types
[op
].bitfield
.disp32s
3626 || i
.types
[op
].bitfield
.disp16
)
3627 && fits_in_signed_byte (disp
))
3628 i
.types
[op
].bitfield
.disp8
= 1;
3630 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3631 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3633 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3634 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3635 i
.types
[op
].bitfield
.disp8
= 0;
3636 i
.types
[op
].bitfield
.disp16
= 0;
3637 i
.types
[op
].bitfield
.disp32
= 0;
3638 i
.types
[op
].bitfield
.disp32s
= 0;
3639 i
.types
[op
].bitfield
.disp64
= 0;
3642 /* We only support 64bit displacement on constants. */
3643 i
.types
[op
].bitfield
.disp64
= 0;
3647 static const insn_template
*
3648 match_template (void)
3650 /* Points to template once we've found it. */
3651 const insn_template
*t
;
3652 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3653 i386_operand_type overlap4
;
3654 unsigned int found_reverse_match
;
3655 i386_opcode_modifier suffix_check
;
3656 i386_operand_type operand_types
[MAX_OPERANDS
];
3657 int addr_prefix_disp
;
3659 unsigned int found_cpu_match
;
3660 unsigned int check_register
;
3662 #if MAX_OPERANDS != 5
3663 # error "MAX_OPERANDS must be 5."
3666 found_reverse_match
= 0;
3667 addr_prefix_disp
= -1;
3669 memset (&suffix_check
, 0, sizeof (suffix_check
));
3670 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3671 suffix_check
.no_bsuf
= 1;
3672 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3673 suffix_check
.no_wsuf
= 1;
3674 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3675 suffix_check
.no_ssuf
= 1;
3676 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3677 suffix_check
.no_lsuf
= 1;
3678 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3679 suffix_check
.no_qsuf
= 1;
3680 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3681 suffix_check
.no_ldsuf
= 1;
3683 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3685 addr_prefix_disp
= -1;
3687 /* Must have right number of operands. */
3688 if (i
.operands
!= t
->operands
)
3691 /* Check processor support. */
3692 found_cpu_match
= (cpu_flags_match (t
)
3693 == CPU_FLAGS_PERFECT_MATCH
);
3694 if (!found_cpu_match
)
3697 /* Check old gcc support. */
3698 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3701 /* Check AT&T mnemonic. */
3702 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3705 /* Check AT&T syntax Intel syntax. */
3706 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3707 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3710 /* Check the suffix, except for some instructions in intel mode. */
3711 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3712 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3713 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3714 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3715 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3716 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3717 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3720 if (!operand_size_match (t
))
3723 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3724 operand_types
[j
] = t
->operand_types
[j
];
3726 /* In general, don't allow 64-bit operands in 32-bit mode. */
3727 if (i
.suffix
== QWORD_MNEM_SUFFIX
3728 && flag_code
!= CODE_64BIT
3730 ? (!t
->opcode_modifier
.ignoresize
3731 && !intel_float_operand (t
->name
))
3732 : intel_float_operand (t
->name
) != 2)
3733 && ((!operand_types
[0].bitfield
.regmmx
3734 && !operand_types
[0].bitfield
.regxmm
3735 && !operand_types
[0].bitfield
.regymm
)
3736 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3737 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3738 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3739 && (t
->base_opcode
!= 0x0fc7
3740 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3743 /* In general, don't allow 32-bit operands on pre-386. */
3744 else if (i
.suffix
== LONG_MNEM_SUFFIX
3745 && !cpu_arch_flags
.bitfield
.cpui386
3747 ? (!t
->opcode_modifier
.ignoresize
3748 && !intel_float_operand (t
->name
))
3749 : intel_float_operand (t
->name
) != 2)
3750 && ((!operand_types
[0].bitfield
.regmmx
3751 && !operand_types
[0].bitfield
.regxmm
)
3752 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3753 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3756 /* Do not verify operands when there are none. */
3760 /* We've found a match; break out of loop. */
3764 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3765 into Disp32/Disp16/Disp32 operand. */
3766 if (i
.prefix
[ADDR_PREFIX
] != 0)
3768 /* There should be only one Disp operand. */
3772 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3774 if (operand_types
[j
].bitfield
.disp16
)
3776 addr_prefix_disp
= j
;
3777 operand_types
[j
].bitfield
.disp32
= 1;
3778 operand_types
[j
].bitfield
.disp16
= 0;
3784 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3786 if (operand_types
[j
].bitfield
.disp32
)
3788 addr_prefix_disp
= j
;
3789 operand_types
[j
].bitfield
.disp32
= 0;
3790 operand_types
[j
].bitfield
.disp16
= 1;
3796 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3798 if (operand_types
[j
].bitfield
.disp64
)
3800 addr_prefix_disp
= j
;
3801 operand_types
[j
].bitfield
.disp64
= 0;
3802 operand_types
[j
].bitfield
.disp32
= 1;
3810 /* We check register size only if size of operands can be
3811 encoded the canonical way. */
3812 check_register
= t
->opcode_modifier
.w
;
3813 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3814 switch (t
->operands
)
3817 if (!operand_type_match (overlap0
, i
.types
[0]))
3821 /* xchg %eax, %eax is a special case. It is an aliase for nop
3822 only in 32bit mode and we can use opcode 0x90. In 64bit
3823 mode, we can't use 0x90 for xchg %eax, %eax since it should
3824 zero-extend %eax to %rax. */
3825 if (flag_code
== CODE_64BIT
3826 && t
->base_opcode
== 0x90
3827 && operand_type_equal (&i
.types
[0], &acc32
)
3828 && operand_type_equal (&i
.types
[1], &acc32
))
3832 /* If we swap operand in encoding, we either match
3833 the next one or reverse direction of operands. */
3834 if (t
->opcode_modifier
.s
)
3836 else if (t
->opcode_modifier
.d
)
3841 /* If we swap operand in encoding, we match the next one. */
3842 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3846 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3847 if (!operand_type_match (overlap0
, i
.types
[0])
3848 || !operand_type_match (overlap1
, i
.types
[1])
3850 && !operand_type_register_match (overlap0
, i
.types
[0],
3852 overlap1
, i
.types
[1],
3855 /* Check if other direction is valid ... */
3856 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3860 /* Try reversing direction of operands. */
3861 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3862 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3863 if (!operand_type_match (overlap0
, i
.types
[0])
3864 || !operand_type_match (overlap1
, i
.types
[1])
3866 && !operand_type_register_match (overlap0
,
3873 /* Does not match either direction. */
3876 /* found_reverse_match holds which of D or FloatDR
3878 if (t
->opcode_modifier
.d
)
3879 found_reverse_match
= Opcode_D
;
3880 else if (t
->opcode_modifier
.floatd
)
3881 found_reverse_match
= Opcode_FloatD
;
3883 found_reverse_match
= 0;
3884 if (t
->opcode_modifier
.floatr
)
3885 found_reverse_match
|= Opcode_FloatR
;
3889 /* Found a forward 2 operand match here. */
3890 switch (t
->operands
)
3893 overlap4
= operand_type_and (i
.types
[4],
3896 overlap3
= operand_type_and (i
.types
[3],
3899 overlap2
= operand_type_and (i
.types
[2],
3904 switch (t
->operands
)
3907 if (!operand_type_match (overlap4
, i
.types
[4])
3908 || !operand_type_register_match (overlap3
,
3916 if (!operand_type_match (overlap3
, i
.types
[3])
3918 && !operand_type_register_match (overlap2
,
3926 /* Here we make use of the fact that there are no
3927 reverse match 3 operand instructions, and all 3
3928 operand instructions only need to be checked for
3929 register consistency between operands 2 and 3. */
3930 if (!operand_type_match (overlap2
, i
.types
[2])
3932 && !operand_type_register_match (overlap1
,
3942 /* Found either forward/reverse 2, 3 or 4 operand match here:
3943 slip through to break. */
3945 if (!found_cpu_match
)
3947 found_reverse_match
= 0;
3951 /* We've found a match; break out of loop. */
3955 if (t
== current_templates
->end
)
3957 /* We found no match. */
3959 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3960 current_templates
->start
->name
);
3962 as_bad (_("suffix or operands invalid for `%s'"),
3963 current_templates
->start
->name
);
3967 if (!quiet_warnings
)
3970 && (i
.types
[0].bitfield
.jumpabsolute
3971 != operand_types
[0].bitfield
.jumpabsolute
))
3973 as_warn (_("indirect %s without `*'"), t
->name
);
3976 if (t
->opcode_modifier
.isprefix
3977 && t
->opcode_modifier
.ignoresize
)
3979 /* Warn them that a data or address size prefix doesn't
3980 affect assembly of the next line of code. */
3981 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3985 /* Copy the template we found. */
3988 if (addr_prefix_disp
!= -1)
3989 i
.tm
.operand_types
[addr_prefix_disp
]
3990 = operand_types
[addr_prefix_disp
];
3992 if (found_reverse_match
)
3994 /* If we found a reverse match we must alter the opcode
3995 direction bit. found_reverse_match holds bits to change
3996 (different for int & float insns). */
3998 i
.tm
.base_opcode
^= found_reverse_match
;
4000 i
.tm
.operand_types
[0] = operand_types
[1];
4001 i
.tm
.operand_types
[1] = operand_types
[0];
4010 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4011 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4013 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4015 as_bad (_("`%s' operand %d must use `%ses' segment"),
4021 /* There's only ever one segment override allowed per instruction.
4022 This instruction possibly has a legal segment override on the
4023 second operand, so copy the segment to where non-string
4024 instructions store it, allowing common code. */
4025 i
.seg
[0] = i
.seg
[1];
4027 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4029 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4031 as_bad (_("`%s' operand %d must use `%ses' segment"),
4042 process_suffix (void)
4044 /* If matched instruction specifies an explicit instruction mnemonic
4046 if (i
.tm
.opcode_modifier
.size16
)
4047 i
.suffix
= WORD_MNEM_SUFFIX
;
4048 else if (i
.tm
.opcode_modifier
.size32
)
4049 i
.suffix
= LONG_MNEM_SUFFIX
;
4050 else if (i
.tm
.opcode_modifier
.size64
)
4051 i
.suffix
= QWORD_MNEM_SUFFIX
;
4052 else if (i
.reg_operands
)
4054 /* If there's no instruction mnemonic suffix we try to invent one
4055 based on register operands. */
4058 /* We take i.suffix from the last register operand specified,
4059 Destination register type is more significant than source
4060 register type. crc32 in SSE4.2 prefers source register
4062 if (i
.tm
.base_opcode
== 0xf20f38f1)
4064 if (i
.types
[0].bitfield
.reg16
)
4065 i
.suffix
= WORD_MNEM_SUFFIX
;
4066 else if (i
.types
[0].bitfield
.reg32
)
4067 i
.suffix
= LONG_MNEM_SUFFIX
;
4068 else if (i
.types
[0].bitfield
.reg64
)
4069 i
.suffix
= QWORD_MNEM_SUFFIX
;
4071 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4073 if (i
.types
[0].bitfield
.reg8
)
4074 i
.suffix
= BYTE_MNEM_SUFFIX
;
4081 if (i
.tm
.base_opcode
== 0xf20f38f1
4082 || i
.tm
.base_opcode
== 0xf20f38f0)
4084 /* We have to know the operand size for crc32. */
4085 as_bad (_("ambiguous memory operand size for `%s`"),
4090 for (op
= i
.operands
; --op
>= 0;)
4091 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4093 if (i
.types
[op
].bitfield
.reg8
)
4095 i
.suffix
= BYTE_MNEM_SUFFIX
;
4098 else if (i
.types
[op
].bitfield
.reg16
)
4100 i
.suffix
= WORD_MNEM_SUFFIX
;
4103 else if (i
.types
[op
].bitfield
.reg32
)
4105 i
.suffix
= LONG_MNEM_SUFFIX
;
4108 else if (i
.types
[op
].bitfield
.reg64
)
4110 i
.suffix
= QWORD_MNEM_SUFFIX
;
4116 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4118 if (!check_byte_reg ())
4121 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4123 if (!check_long_reg ())
4126 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4129 && i
.tm
.opcode_modifier
.ignoresize
4130 && i
.tm
.opcode_modifier
.no_qsuf
)
4132 else if (!check_qword_reg ())
4135 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4137 if (!check_word_reg ())
4140 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4141 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4143 /* Skip if the instruction has x/y suffix. match_template
4144 should check if it is a valid suffix. */
4146 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4147 /* Do nothing if the instruction is going to ignore the prefix. */
4152 else if (i
.tm
.opcode_modifier
.defaultsize
4154 /* exclude fldenv/frstor/fsave/fstenv */
4155 && i
.tm
.opcode_modifier
.no_ssuf
)
4157 i
.suffix
= stackop_size
;
4159 else if (intel_syntax
4161 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4162 || i
.tm
.opcode_modifier
.jumpbyte
4163 || i
.tm
.opcode_modifier
.jumpintersegment
4164 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4165 && i
.tm
.extension_opcode
<= 3)))
4170 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4172 i
.suffix
= QWORD_MNEM_SUFFIX
;
4176 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4177 i
.suffix
= LONG_MNEM_SUFFIX
;
4180 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4181 i
.suffix
= WORD_MNEM_SUFFIX
;
4190 if (i
.tm
.opcode_modifier
.w
)
4192 as_bad (_("no instruction mnemonic suffix given and "
4193 "no register operands; can't size instruction"));
4199 unsigned int suffixes
;
4201 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4202 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4204 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4206 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4208 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4210 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4213 /* There are more than suffix matches. */
4214 if (i
.tm
.opcode_modifier
.w
4215 || ((suffixes
& (suffixes
- 1))
4216 && !i
.tm
.opcode_modifier
.defaultsize
4217 && !i
.tm
.opcode_modifier
.ignoresize
))
4219 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4225 /* Change the opcode based on the operand size given by i.suffix;
4226 We don't need to change things for byte insns. */
4229 && i
.suffix
!= BYTE_MNEM_SUFFIX
4230 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4231 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4233 /* It's not a byte, select word/dword operation. */
4234 if (i
.tm
.opcode_modifier
.w
)
4236 if (i
.tm
.opcode_modifier
.shortform
)
4237 i
.tm
.base_opcode
|= 8;
4239 i
.tm
.base_opcode
|= 1;
4242 /* Now select between word & dword operations via the operand
4243 size prefix, except for instructions that will ignore this
4245 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4247 /* The address size override prefix changes the size of the
4249 if ((flag_code
== CODE_32BIT
4250 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4251 || (flag_code
!= CODE_32BIT
4252 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4253 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4256 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4257 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4258 && !i
.tm
.opcode_modifier
.ignoresize
4259 && !i
.tm
.opcode_modifier
.floatmf
4260 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4261 || (flag_code
== CODE_64BIT
4262 && i
.tm
.opcode_modifier
.jumpbyte
)))
4264 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4266 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4267 prefix
= ADDR_PREFIX_OPCODE
;
4269 if (!add_prefix (prefix
))
4273 /* Set mode64 for an operand. */
4274 if (i
.suffix
== QWORD_MNEM_SUFFIX
4275 && flag_code
== CODE_64BIT
4276 && !i
.tm
.opcode_modifier
.norex64
)
4278 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4279 need rex64. cmpxchg8b is also a special case. */
4280 if (! (i
.operands
== 2
4281 && i
.tm
.base_opcode
== 0x90
4282 && i
.tm
.extension_opcode
== None
4283 && operand_type_equal (&i
.types
[0], &acc64
)
4284 && operand_type_equal (&i
.types
[1], &acc64
))
4285 && ! (i
.operands
== 1
4286 && i
.tm
.base_opcode
== 0xfc7
4287 && i
.tm
.extension_opcode
== 1
4288 && !operand_type_check (i
.types
[0], reg
)
4289 && operand_type_check (i
.types
[0], anymem
)))
4293 /* Size floating point instruction. */
4294 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4295 if (i
.tm
.opcode_modifier
.floatmf
)
4296 i
.tm
.base_opcode
^= 4;
4303 check_byte_reg (void)
4307 for (op
= i
.operands
; --op
>= 0;)
4309 /* If this is an eight bit register, it's OK. If it's the 16 or
4310 32 bit version of an eight bit register, we will just use the
4311 low portion, and that's OK too. */
4312 if (i
.types
[op
].bitfield
.reg8
)
4315 /* Don't generate this warning if not needed. */
4316 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4319 /* crc32 doesn't generate this warning. */
4320 if (i
.tm
.base_opcode
== 0xf20f38f0)
4323 if ((i
.types
[op
].bitfield
.reg16
4324 || i
.types
[op
].bitfield
.reg32
4325 || i
.types
[op
].bitfield
.reg64
)
4326 && i
.op
[op
].regs
->reg_num
< 4)
4328 /* Prohibit these changes in the 64bit mode, since the
4329 lowering is more complicated. */
4330 if (flag_code
== CODE_64BIT
4331 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4333 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4334 register_prefix
, i
.op
[op
].regs
->reg_name
,
4338 #if REGISTER_WARNINGS
4340 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4341 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4343 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4344 ? REGNAM_AL
- REGNAM_AX
4345 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4347 i
.op
[op
].regs
->reg_name
,
4352 /* Any other register is bad. */
4353 if (i
.types
[op
].bitfield
.reg16
4354 || i
.types
[op
].bitfield
.reg32
4355 || i
.types
[op
].bitfield
.reg64
4356 || i
.types
[op
].bitfield
.regmmx
4357 || i
.types
[op
].bitfield
.regxmm
4358 || i
.types
[op
].bitfield
.regymm
4359 || i
.types
[op
].bitfield
.sreg2
4360 || i
.types
[op
].bitfield
.sreg3
4361 || i
.types
[op
].bitfield
.control
4362 || i
.types
[op
].bitfield
.debug
4363 || i
.types
[op
].bitfield
.test
4364 || i
.types
[op
].bitfield
.floatreg
4365 || i
.types
[op
].bitfield
.floatacc
)
4367 as_bad (_("`%s%s' not allowed with `%s%c'"),
4369 i
.op
[op
].regs
->reg_name
,
4379 check_long_reg (void)
4383 for (op
= i
.operands
; --op
>= 0;)
4384 /* Reject eight bit registers, except where the template requires
4385 them. (eg. movzb) */
4386 if (i
.types
[op
].bitfield
.reg8
4387 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4388 || i
.tm
.operand_types
[op
].bitfield
.reg32
4389 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4391 as_bad (_("`%s%s' not allowed with `%s%c'"),
4393 i
.op
[op
].regs
->reg_name
,
4398 /* Warn if the e prefix on a general reg is missing. */
4399 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4400 && i
.types
[op
].bitfield
.reg16
4401 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4402 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4404 /* Prohibit these changes in the 64bit mode, since the
4405 lowering is more complicated. */
4406 if (flag_code
== CODE_64BIT
)
4408 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4409 register_prefix
, i
.op
[op
].regs
->reg_name
,
4413 #if REGISTER_WARNINGS
4415 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4417 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4419 i
.op
[op
].regs
->reg_name
,
4423 /* Warn if the r prefix on a general reg is missing. */
4424 else if (i
.types
[op
].bitfield
.reg64
4425 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4426 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4429 && i
.tm
.opcode_modifier
.toqword
4430 && !i
.types
[0].bitfield
.regxmm
)
4432 /* Convert to QWORD. We want REX byte. */
4433 i
.suffix
= QWORD_MNEM_SUFFIX
;
4437 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4438 register_prefix
, i
.op
[op
].regs
->reg_name
,
4447 check_qword_reg (void)
4451 for (op
= i
.operands
; --op
>= 0; )
4452 /* Reject eight bit registers, except where the template requires
4453 them. (eg. movzb) */
4454 if (i
.types
[op
].bitfield
.reg8
4455 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4456 || i
.tm
.operand_types
[op
].bitfield
.reg32
4457 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4459 as_bad (_("`%s%s' not allowed with `%s%c'"),
4461 i
.op
[op
].regs
->reg_name
,
4466 /* Warn if the e prefix on a general reg is missing. */
4467 else if ((i
.types
[op
].bitfield
.reg16
4468 || i
.types
[op
].bitfield
.reg32
)
4469 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4470 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4472 /* Prohibit these changes in the 64bit mode, since the
4473 lowering is more complicated. */
4475 && i
.tm
.opcode_modifier
.todword
4476 && !i
.types
[0].bitfield
.regxmm
)
4478 /* Convert to DWORD. We don't want REX byte. */
4479 i
.suffix
= LONG_MNEM_SUFFIX
;
4483 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4484 register_prefix
, i
.op
[op
].regs
->reg_name
,
4493 check_word_reg (void)
4496 for (op
= i
.operands
; --op
>= 0;)
4497 /* Reject eight bit registers, except where the template requires
4498 them. (eg. movzb) */
4499 if (i
.types
[op
].bitfield
.reg8
4500 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4501 || i
.tm
.operand_types
[op
].bitfield
.reg32
4502 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4504 as_bad (_("`%s%s' not allowed with `%s%c'"),
4506 i
.op
[op
].regs
->reg_name
,
4511 /* Warn if the e prefix on a general reg is present. */
4512 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4513 && i
.types
[op
].bitfield
.reg32
4514 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4515 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4517 /* Prohibit these changes in the 64bit mode, since the
4518 lowering is more complicated. */
4519 if (flag_code
== CODE_64BIT
)
4521 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4522 register_prefix
, i
.op
[op
].regs
->reg_name
,
4527 #if REGISTER_WARNINGS
4528 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4530 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4532 i
.op
[op
].regs
->reg_name
,
4540 update_imm (unsigned int j
)
4542 i386_operand_type overlap
= i
.types
[j
];
4543 if ((overlap
.bitfield
.imm8
4544 || overlap
.bitfield
.imm8s
4545 || overlap
.bitfield
.imm16
4546 || overlap
.bitfield
.imm32
4547 || overlap
.bitfield
.imm32s
4548 || overlap
.bitfield
.imm64
)
4549 && !operand_type_equal (&overlap
, &imm8
)
4550 && !operand_type_equal (&overlap
, &imm8s
)
4551 && !operand_type_equal (&overlap
, &imm16
)
4552 && !operand_type_equal (&overlap
, &imm32
)
4553 && !operand_type_equal (&overlap
, &imm32s
)
4554 && !operand_type_equal (&overlap
, &imm64
))
4558 i386_operand_type temp
;
4560 operand_type_set (&temp
, 0);
4561 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4563 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4564 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4566 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4567 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4568 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4570 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4571 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4574 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4577 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4578 || operand_type_equal (&overlap
, &imm16_32
)
4579 || operand_type_equal (&overlap
, &imm16_32s
))
4581 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4586 if (!operand_type_equal (&overlap
, &imm8
)
4587 && !operand_type_equal (&overlap
, &imm8s
)
4588 && !operand_type_equal (&overlap
, &imm16
)
4589 && !operand_type_equal (&overlap
, &imm32
)
4590 && !operand_type_equal (&overlap
, &imm32s
)
4591 && !operand_type_equal (&overlap
, &imm64
))
4593 as_bad (_("no instruction mnemonic suffix given; "
4594 "can't determine immediate size"));
4598 i
.types
[j
] = overlap
;
4608 /* Update the first 2 immediate operands. */
4609 n
= i
.operands
> 2 ? 2 : i
.operands
;
4612 for (j
= 0; j
< n
; j
++)
4613 if (update_imm (j
) == 0)
4616 /* The 3rd operand can't be immediate operand. */
4617 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4624 bad_implicit_operand (int xmm
)
4626 const char *reg
= xmm
? "xmm0" : "ymm0";
4628 as_bad (_("the last operand of `%s' must be `%s%s'"),
4629 i
.tm
.name
, register_prefix
, reg
);
4631 as_bad (_("the first operand of `%s' must be `%s%s'"),
4632 i
.tm
.name
, register_prefix
, reg
);
4637 process_operands (void)
4639 /* Default segment register this instruction will use for memory
4640 accesses. 0 means unknown. This is only for optimizing out
4641 unnecessary segment overrides. */
4642 const seg_entry
*default_seg
= 0;
4644 if (i
.tm
.opcode_modifier
.sse2avx
4645 && (i
.tm
.opcode_modifier
.vexnds
4646 || i
.tm
.opcode_modifier
.vexndd
))
4648 unsigned int dup
= i
.operands
;
4649 unsigned int dest
= dup
- 1;
4652 /* The destination must be an xmm register. */
4653 gas_assert (i
.reg_operands
4654 && MAX_OPERANDS
> dup
4655 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4657 if (i
.tm
.opcode_modifier
.firstxmm0
)
4659 /* The first operand is implicit and must be xmm0. */
4660 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4661 if (i
.op
[0].regs
->reg_num
!= 0)
4662 return bad_implicit_operand (1);
4664 if (i
.tm
.opcode_modifier
.vex3sources
)
4666 /* Keep xmm0 for instructions with VEX prefix and 3
4672 /* We remove the first xmm0 and keep the number of
4673 operands unchanged, which in fact duplicates the
4675 for (j
= 1; j
< i
.operands
; j
++)
4677 i
.op
[j
- 1] = i
.op
[j
];
4678 i
.types
[j
- 1] = i
.types
[j
];
4679 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4683 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4685 gas_assert ((MAX_OPERANDS
- 1) > dup
4686 && i
.tm
.opcode_modifier
.vex3sources
);
4688 /* Add the implicit xmm0 for instructions with VEX prefix
4690 for (j
= i
.operands
; j
> 0; j
--)
4692 i
.op
[j
] = i
.op
[j
- 1];
4693 i
.types
[j
] = i
.types
[j
- 1];
4694 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4697 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4698 i
.types
[0] = regxmm
;
4699 i
.tm
.operand_types
[0] = regxmm
;
4702 i
.reg_operands
+= 2;
4707 i
.op
[dup
] = i
.op
[dest
];
4708 i
.types
[dup
] = i
.types
[dest
];
4709 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4718 i
.op
[dup
] = i
.op
[dest
];
4719 i
.types
[dup
] = i
.types
[dest
];
4720 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4723 if (i
.tm
.opcode_modifier
.immext
)
4726 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4730 /* The first operand is implicit and must be xmm0/ymm0. */
4731 gas_assert (i
.reg_operands
4732 && (operand_type_equal (&i
.types
[0], ®xmm
)
4733 || operand_type_equal (&i
.types
[0], ®ymm
)));
4734 if (i
.op
[0].regs
->reg_num
!= 0)
4735 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4737 for (j
= 1; j
< i
.operands
; j
++)
4739 i
.op
[j
- 1] = i
.op
[j
];
4740 i
.types
[j
- 1] = i
.types
[j
];
4742 /* We need to adjust fields in i.tm since they are used by
4743 build_modrm_byte. */
4744 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4751 else if (i
.tm
.opcode_modifier
.regkludge
)
4753 /* The imul $imm, %reg instruction is converted into
4754 imul $imm, %reg, %reg, and the clr %reg instruction
4755 is converted into xor %reg, %reg. */
4757 unsigned int first_reg_op
;
4759 if (operand_type_check (i
.types
[0], reg
))
4763 /* Pretend we saw the extra register operand. */
4764 gas_assert (i
.reg_operands
== 1
4765 && i
.op
[first_reg_op
+ 1].regs
== 0);
4766 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4767 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4772 if (i
.tm
.opcode_modifier
.shortform
)
4774 if (i
.types
[0].bitfield
.sreg2
4775 || i
.types
[0].bitfield
.sreg3
)
4777 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4778 && i
.op
[0].regs
->reg_num
== 1)
4780 as_bad (_("you can't `pop %scs'"), register_prefix
);
4783 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4784 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4789 /* The register or float register operand is in operand
4793 if (i
.types
[0].bitfield
.floatreg
4794 || operand_type_check (i
.types
[0], reg
))
4798 /* Register goes in low 3 bits of opcode. */
4799 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4800 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4802 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4804 /* Warn about some common errors, but press on regardless.
4805 The first case can be generated by gcc (<= 2.8.1). */
4806 if (i
.operands
== 2)
4808 /* Reversed arguments on faddp, fsubp, etc. */
4809 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4810 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4811 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4815 /* Extraneous `l' suffix on fp insn. */
4816 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4817 register_prefix
, i
.op
[0].regs
->reg_name
);
4822 else if (i
.tm
.opcode_modifier
.modrm
)
4824 /* The opcode is completed (modulo i.tm.extension_opcode which
4825 must be put into the modrm byte). Now, we make the modrm and
4826 index base bytes based on all the info we've collected. */
4828 default_seg
= build_modrm_byte ();
4830 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4834 else if (i
.tm
.opcode_modifier
.isstring
)
4836 /* For the string instructions that allow a segment override
4837 on one of their operands, the default segment is ds. */
4841 if (i
.tm
.base_opcode
== 0x8d /* lea */
4844 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4846 /* If a segment was explicitly specified, and the specified segment
4847 is not the default, use an opcode prefix to select it. If we
4848 never figured out what the default segment is, then default_seg
4849 will be zero at this point, and the specified segment prefix will
4851 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4853 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4859 static const seg_entry
*
4860 build_modrm_byte (void)
4862 const seg_entry
*default_seg
= 0;
4863 unsigned int source
, dest
;
4866 /* The first operand of instructions with VEX prefix and 3 sources
4867 must be VEX_Imm4. */
4868 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4871 unsigned int nds
, reg
;
4873 if (i
.tm
.opcode_modifier
.veximmext
4874 && i
.tm
.opcode_modifier
.immext
)
4876 dest
= i
.operands
- 2;
4877 gas_assert (dest
== 3);
4880 dest
= i
.operands
- 1;
4883 /* This instruction must have 4 register operands
4884 or 3 register operands plus 1 memory operand.
4885 It must have VexNDS and VexImmExt. */
4886 gas_assert ((i
.reg_operands
== 4
4887 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4888 && i
.tm
.opcode_modifier
.vexnds
4889 && i
.tm
.opcode_modifier
.veximmext
4890 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4891 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4893 /* Generate an 8bit immediate operand to encode the register
4895 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4896 i
.op
[i
.operands
].imms
= exp
;
4897 i
.types
[i
.operands
] = imm8
;
4899 /* If VexW1 is set, the first operand is the source and
4900 the second operand is encoded in the immediate operand. */
4901 if (i
.tm
.opcode_modifier
.vexw1
)
4911 /* FMA4 swaps REG and NDS. */
4912 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4919 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4920 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4922 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4923 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4925 exp
->X_op
= O_constant
;
4927 = ((i
.op
[reg
].regs
->reg_num
4928 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4929 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4934 /* i.reg_operands MUST be the number of real register operands;
4935 implicit registers do not count. If there are 3 register
4936 operands, it must be a instruction with VexNDS. For a
4937 instruction with VexNDD, the destination register is encoded
4938 in VEX prefix. If there are 4 register operands, it must be
4939 a instruction with VEX prefix and 3 sources. */
4940 if (i
.mem_operands
== 0
4941 && ((i
.reg_operands
== 2
4942 && !i
.tm
.opcode_modifier
.vexndd
)
4943 || (i
.reg_operands
== 3
4944 && i
.tm
.opcode_modifier
.vexnds
)
4945 || (i
.reg_operands
== 4 && vex_3_sources
)))
4953 /* When there are 3 operands, one of them may be immediate,
4954 which may be the first or the last operand. Otherwise,
4955 the first operand must be shift count register (cl) or it
4956 is an instruction with VexNDS. */
4957 gas_assert (i
.imm_operands
== 1
4958 || (i
.imm_operands
== 0
4959 && (i
.tm
.opcode_modifier
.vexnds
4960 || i
.types
[0].bitfield
.shiftcount
)));
4961 if (operand_type_check (i
.types
[0], imm
)
4962 || i
.types
[0].bitfield
.shiftcount
)
4968 /* When there are 4 operands, the first two must be 8bit
4969 immediate operands. The source operand will be the 3rd
4972 For instructions with VexNDS, if the first operand
4973 an imm8, the source operand is the 2nd one. If the last
4974 operand is imm8, the source operand is the first one. */
4975 gas_assert ((i
.imm_operands
== 2
4976 && i
.types
[0].bitfield
.imm8
4977 && i
.types
[1].bitfield
.imm8
)
4978 || (i
.tm
.opcode_modifier
.vexnds
4979 && i
.imm_operands
== 1
4980 && (i
.types
[0].bitfield
.imm8
4981 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4982 if (i
.tm
.opcode_modifier
.vexnds
)
4984 if (i
.types
[0].bitfield
.imm8
)
5002 if (i
.tm
.opcode_modifier
.vexnds
)
5004 /* For instructions with VexNDS, the register-only
5005 source operand must be XMM or YMM register. It is
5006 encoded in VEX prefix. We need to clear RegMem bit
5007 before calling operand_type_equal. */
5008 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5009 op
.bitfield
.regmem
= 0;
5010 if ((dest
+ 1) >= i
.operands
5011 || (!operand_type_equal (&op
, ®xmm
)
5012 && !operand_type_equal (&op
, ®ymm
)))
5014 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5020 /* One of the register operands will be encoded in the i.tm.reg
5021 field, the other in the combined i.tm.mode and i.tm.regmem
5022 fields. If no form of this instruction supports a memory
5023 destination operand, then we assume the source operand may
5024 sometimes be a memory operand and so we need to store the
5025 destination in the i.rm.reg field. */
5026 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5027 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5029 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5030 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5031 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5033 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5038 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5039 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5040 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5042 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5045 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5047 if (!i
.types
[0].bitfield
.control
5048 && !i
.types
[1].bitfield
.control
)
5050 i
.rex
&= ~(REX_R
| REX_B
);
5051 add_prefix (LOCK_PREFIX_OPCODE
);
5055 { /* If it's not 2 reg operands... */
5060 unsigned int fake_zero_displacement
= 0;
5063 for (op
= 0; op
< i
.operands
; op
++)
5064 if (operand_type_check (i
.types
[op
], anymem
))
5066 gas_assert (op
< i
.operands
);
5070 if (i
.base_reg
== 0)
5073 if (!i
.disp_operands
)
5074 fake_zero_displacement
= 1;
5075 if (i
.index_reg
== 0)
5077 /* Operand is just <disp> */
5078 if (flag_code
== CODE_64BIT
)
5080 /* 64bit mode overwrites the 32bit absolute
5081 addressing by RIP relative addressing and
5082 absolute addressing is encoded by one of the
5083 redundant SIB forms. */
5084 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5085 i
.sib
.base
= NO_BASE_REGISTER
;
5086 i
.sib
.index
= NO_INDEX_REGISTER
;
5087 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5088 ? disp32s
: disp32
);
5090 else if ((flag_code
== CODE_16BIT
)
5091 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5093 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5094 i
.types
[op
] = disp16
;
5098 i
.rm
.regmem
= NO_BASE_REGISTER
;
5099 i
.types
[op
] = disp32
;
5102 else /* !i.base_reg && i.index_reg */
5104 if (i
.index_reg
->reg_num
== RegEiz
5105 || i
.index_reg
->reg_num
== RegRiz
)
5106 i
.sib
.index
= NO_INDEX_REGISTER
;
5108 i
.sib
.index
= i
.index_reg
->reg_num
;
5109 i
.sib
.base
= NO_BASE_REGISTER
;
5110 i
.sib
.scale
= i
.log2_scale_factor
;
5111 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5112 i
.types
[op
].bitfield
.disp8
= 0;
5113 i
.types
[op
].bitfield
.disp16
= 0;
5114 i
.types
[op
].bitfield
.disp64
= 0;
5115 if (flag_code
!= CODE_64BIT
)
5117 /* Must be 32 bit */
5118 i
.types
[op
].bitfield
.disp32
= 1;
5119 i
.types
[op
].bitfield
.disp32s
= 0;
5123 i
.types
[op
].bitfield
.disp32
= 0;
5124 i
.types
[op
].bitfield
.disp32s
= 1;
5126 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5130 /* RIP addressing for 64bit mode. */
5131 else if (i
.base_reg
->reg_num
== RegRip
||
5132 i
.base_reg
->reg_num
== RegEip
)
5134 i
.rm
.regmem
= NO_BASE_REGISTER
;
5135 i
.types
[op
].bitfield
.disp8
= 0;
5136 i
.types
[op
].bitfield
.disp16
= 0;
5137 i
.types
[op
].bitfield
.disp32
= 0;
5138 i
.types
[op
].bitfield
.disp32s
= 1;
5139 i
.types
[op
].bitfield
.disp64
= 0;
5140 i
.flags
[op
] |= Operand_PCrel
;
5141 if (! i
.disp_operands
)
5142 fake_zero_displacement
= 1;
5144 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5146 switch (i
.base_reg
->reg_num
)
5149 if (i
.index_reg
== 0)
5151 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5152 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5156 if (i
.index_reg
== 0)
5159 if (operand_type_check (i
.types
[op
], disp
) == 0)
5161 /* fake (%bp) into 0(%bp) */
5162 i
.types
[op
].bitfield
.disp8
= 1;
5163 fake_zero_displacement
= 1;
5166 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5167 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5169 default: /* (%si) -> 4 or (%di) -> 5 */
5170 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5172 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5174 else /* i.base_reg and 32/64 bit mode */
5176 if (flag_code
== CODE_64BIT
5177 && operand_type_check (i
.types
[op
], disp
))
5179 i386_operand_type temp
;
5180 operand_type_set (&temp
, 0);
5181 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5183 if (i
.prefix
[ADDR_PREFIX
] == 0)
5184 i
.types
[op
].bitfield
.disp32s
= 1;
5186 i
.types
[op
].bitfield
.disp32
= 1;
5189 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5190 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5192 i
.sib
.base
= i
.base_reg
->reg_num
;
5193 /* x86-64 ignores REX prefix bit here to avoid decoder
5195 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5198 if (i
.disp_operands
== 0)
5200 fake_zero_displacement
= 1;
5201 i
.types
[op
].bitfield
.disp8
= 1;
5204 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5208 i
.sib
.scale
= i
.log2_scale_factor
;
5209 if (i
.index_reg
== 0)
5211 /* <disp>(%esp) becomes two byte modrm with no index
5212 register. We've already stored the code for esp
5213 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5214 Any base register besides %esp will not use the
5215 extra modrm byte. */
5216 i
.sib
.index
= NO_INDEX_REGISTER
;
5220 if (i
.index_reg
->reg_num
== RegEiz
5221 || i
.index_reg
->reg_num
== RegRiz
)
5222 i
.sib
.index
= NO_INDEX_REGISTER
;
5224 i
.sib
.index
= i
.index_reg
->reg_num
;
5225 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5226 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5231 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5232 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5235 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5238 if (fake_zero_displacement
)
5240 /* Fakes a zero displacement assuming that i.types[op]
5241 holds the correct displacement size. */
5244 gas_assert (i
.op
[op
].disps
== 0);
5245 exp
= &disp_expressions
[i
.disp_operands
++];
5246 i
.op
[op
].disps
= exp
;
5247 exp
->X_op
= O_constant
;
5248 exp
->X_add_number
= 0;
5249 exp
->X_add_symbol
= (symbolS
*) 0;
5250 exp
->X_op_symbol
= (symbolS
*) 0;
5258 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5259 (if any) based on i.tm.extension_opcode. Again, we must be
5260 careful to make sure that segment/control/debug/test/MMX
5261 registers are coded into the i.rm.reg field. */
5265 unsigned int vex_reg
= ~0;
5267 for (op
= 0; op
< i
.operands
; op
++)
5268 if (i
.types
[op
].bitfield
.reg8
5269 || i
.types
[op
].bitfield
.reg16
5270 || i
.types
[op
].bitfield
.reg32
5271 || i
.types
[op
].bitfield
.reg64
5272 || i
.types
[op
].bitfield
.regmmx
5273 || i
.types
[op
].bitfield
.regxmm
5274 || i
.types
[op
].bitfield
.regymm
5275 || i
.types
[op
].bitfield
.sreg2
5276 || i
.types
[op
].bitfield
.sreg3
5277 || i
.types
[op
].bitfield
.control
5278 || i
.types
[op
].bitfield
.debug
5279 || i
.types
[op
].bitfield
.test
)
5284 else if (i
.tm
.opcode_modifier
.vexnds
)
5286 /* For instructions with VexNDS, the register-only
5287 source operand is encoded in VEX prefix. */
5288 gas_assert (mem
!= (unsigned int) ~0);
5293 gas_assert (op
< i
.operands
);
5298 gas_assert (vex_reg
< i
.operands
);
5301 else if (i
.tm
.opcode_modifier
.vexndd
)
5303 /* For instructions with VexNDD, there should be
5304 no memory operand and the register destination
5305 is encoded in VEX prefix. */
5306 gas_assert (i
.mem_operands
== 0
5307 && (op
+ 2) == i
.operands
);
5311 gas_assert (op
< i
.operands
);
5313 if (vex_reg
!= (unsigned int) ~0)
5315 gas_assert (i
.reg_operands
== 2);
5317 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5319 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5322 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5325 /* If there is an extension opcode to put here, the
5326 register number must be put into the regmem field. */
5327 if (i
.tm
.extension_opcode
!= None
)
5329 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5330 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5335 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5336 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5340 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5341 must set it to 3 to indicate this is a register operand
5342 in the regmem field. */
5343 if (!i
.mem_operands
)
5347 /* Fill in i.rm.reg field with extension opcode (if any). */
5348 if (i
.tm
.extension_opcode
!= None
)
5349 i
.rm
.reg
= i
.tm
.extension_opcode
;
5355 output_branch (void)
5360 relax_substateT subtype
;
5365 if (flag_code
== CODE_16BIT
)
5369 if (i
.prefix
[DATA_PREFIX
] != 0)
5375 /* Pentium4 branch hints. */
5376 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5377 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5382 if (i
.prefix
[REX_PREFIX
] != 0)
5388 if (i
.prefixes
!= 0 && !intel_syntax
)
5389 as_warn (_("skipping prefixes on this instruction"));
5391 /* It's always a symbol; End frag & setup for relax.
5392 Make sure there is enough room in this frag for the largest
5393 instruction we may generate in md_convert_frag. This is 2
5394 bytes for the opcode and room for the prefix and largest
5396 frag_grow (prefix
+ 2 + 4);
5397 /* Prefix and 1 opcode byte go in fr_fix. */
5398 p
= frag_more (prefix
+ 1);
5399 if (i
.prefix
[DATA_PREFIX
] != 0)
5400 *p
++ = DATA_PREFIX_OPCODE
;
5401 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5402 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5403 *p
++ = i
.prefix
[SEG_PREFIX
];
5404 if (i
.prefix
[REX_PREFIX
] != 0)
5405 *p
++ = i
.prefix
[REX_PREFIX
];
5406 *p
= i
.tm
.base_opcode
;
5408 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5409 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5410 else if (cpu_arch_flags
.bitfield
.cpui386
)
5411 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5413 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5416 sym
= i
.op
[0].disps
->X_add_symbol
;
5417 off
= i
.op
[0].disps
->X_add_number
;
5419 if (i
.op
[0].disps
->X_op
!= O_constant
5420 && i
.op
[0].disps
->X_op
!= O_symbol
)
5422 /* Handle complex expressions. */
5423 sym
= make_expr_symbol (i
.op
[0].disps
);
5427 /* 1 possible extra opcode + 4 byte displacement go in var part.
5428 Pass reloc in fr_var. */
5429 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5439 if (i
.tm
.opcode_modifier
.jumpbyte
)
5441 /* This is a loop or jecxz type instruction. */
5443 if (i
.prefix
[ADDR_PREFIX
] != 0)
5445 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5448 /* Pentium4 branch hints. */
5449 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5450 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5452 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5461 if (flag_code
== CODE_16BIT
)
5464 if (i
.prefix
[DATA_PREFIX
] != 0)
5466 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5476 if (i
.prefix
[REX_PREFIX
] != 0)
5478 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5482 if (i
.prefixes
!= 0 && !intel_syntax
)
5483 as_warn (_("skipping prefixes on this instruction"));
5485 p
= frag_more (1 + size
);
5486 *p
++ = i
.tm
.base_opcode
;
5488 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5489 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5491 /* All jumps handled here are signed, but don't use a signed limit
5492 check for 32 and 16 bit jumps as we want to allow wrap around at
5493 4G and 64k respectively. */
5495 fixP
->fx_signed
= 1;
5499 output_interseg_jump (void)
5507 if (flag_code
== CODE_16BIT
)
5511 if (i
.prefix
[DATA_PREFIX
] != 0)
5517 if (i
.prefix
[REX_PREFIX
] != 0)
5527 if (i
.prefixes
!= 0 && !intel_syntax
)
5528 as_warn (_("skipping prefixes on this instruction"));
5530 /* 1 opcode; 2 segment; offset */
5531 p
= frag_more (prefix
+ 1 + 2 + size
);
5533 if (i
.prefix
[DATA_PREFIX
] != 0)
5534 *p
++ = DATA_PREFIX_OPCODE
;
5536 if (i
.prefix
[REX_PREFIX
] != 0)
5537 *p
++ = i
.prefix
[REX_PREFIX
];
5539 *p
++ = i
.tm
.base_opcode
;
5540 if (i
.op
[1].imms
->X_op
== O_constant
)
5542 offsetT n
= i
.op
[1].imms
->X_add_number
;
5545 && !fits_in_unsigned_word (n
)
5546 && !fits_in_signed_word (n
))
5548 as_bad (_("16-bit jump out of range"));
5551 md_number_to_chars (p
, n
, size
);
5554 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5555 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5556 if (i
.op
[0].imms
->X_op
!= O_constant
)
5557 as_bad (_("can't handle non absolute segment in `%s'"),
5559 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5565 fragS
*insn_start_frag
;
5566 offsetT insn_start_off
;
5568 /* Tie dwarf2 debug info to the address at the start of the insn.
5569 We can't do this after the insn has been output as the current
5570 frag may have been closed off. eg. by frag_var. */
5571 dwarf2_emit_insn (0);
5573 insn_start_frag
= frag_now
;
5574 insn_start_off
= frag_now_fix ();
5577 if (i
.tm
.opcode_modifier
.jump
)
5579 else if (i
.tm
.opcode_modifier
.jumpbyte
5580 || i
.tm
.opcode_modifier
.jumpdword
)
5582 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5583 output_interseg_jump ();
5586 /* Output normal instructions here. */
5590 unsigned int prefix
;
5592 /* Since the VEX prefix contains the implicit prefix, we don't
5593 need the explicit prefix. */
5594 if (!i
.tm
.opcode_modifier
.vex
)
5596 switch (i
.tm
.opcode_length
)
5599 if (i
.tm
.base_opcode
& 0xff000000)
5601 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5606 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5608 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5609 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5612 if (prefix
!= REPE_PREFIX_OPCODE
5613 || (i
.prefix
[LOCKREP_PREFIX
]
5614 != REPE_PREFIX_OPCODE
))
5615 add_prefix (prefix
);
5618 add_prefix (prefix
);
5627 /* The prefix bytes. */
5628 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5630 FRAG_APPEND_1_CHAR (*q
);
5633 if (i
.tm
.opcode_modifier
.vex
)
5635 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5640 /* REX byte is encoded in VEX prefix. */
5644 FRAG_APPEND_1_CHAR (*q
);
5647 /* There should be no other prefixes for instructions
5652 /* Now the VEX prefix. */
5653 p
= frag_more (i
.vex
.length
);
5654 for (j
= 0; j
< i
.vex
.length
; j
++)
5655 p
[j
] = i
.vex
.bytes
[j
];
5658 /* Now the opcode; be careful about word order here! */
5659 if (i
.tm
.opcode_length
== 1)
5661 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5665 switch (i
.tm
.opcode_length
)
5669 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5679 /* Put out high byte first: can't use md_number_to_chars! */
5680 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5681 *p
= i
.tm
.base_opcode
& 0xff;
5684 /* Now the modrm byte and sib byte (if present). */
5685 if (i
.tm
.opcode_modifier
.modrm
)
5687 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5690 /* If i.rm.regmem == ESP (4)
5691 && i.rm.mode != (Register mode)
5693 ==> need second modrm byte. */
5694 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5696 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5697 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5699 | i
.sib
.scale
<< 6));
5702 if (i
.disp_operands
)
5703 output_disp (insn_start_frag
, insn_start_off
);
5706 output_imm (insn_start_frag
, insn_start_off
);
5712 pi ("" /*line*/, &i
);
5714 #endif /* DEBUG386 */
5717 /* Return the size of the displacement operand N. */
5720 disp_size (unsigned int n
)
5723 if (i
.types
[n
].bitfield
.disp64
)
5725 else if (i
.types
[n
].bitfield
.disp8
)
5727 else if (i
.types
[n
].bitfield
.disp16
)
5732 /* Return the size of the immediate operand N. */
5735 imm_size (unsigned int n
)
5738 if (i
.types
[n
].bitfield
.imm64
)
5740 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5742 else if (i
.types
[n
].bitfield
.imm16
)
5748 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5753 for (n
= 0; n
< i
.operands
; n
++)
5755 if (operand_type_check (i
.types
[n
], disp
))
5757 if (i
.op
[n
].disps
->X_op
== O_constant
)
5759 int size
= disp_size (n
);
5762 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5764 p
= frag_more (size
);
5765 md_number_to_chars (p
, val
, size
);
5769 enum bfd_reloc_code_real reloc_type
;
5770 int size
= disp_size (n
);
5771 int sign
= i
.types
[n
].bitfield
.disp32s
;
5772 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5774 /* We can't have 8 bit displacement here. */
5775 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5777 /* The PC relative address is computed relative
5778 to the instruction boundary, so in case immediate
5779 fields follows, we need to adjust the value. */
5780 if (pcrel
&& i
.imm_operands
)
5785 for (n1
= 0; n1
< i
.operands
; n1
++)
5786 if (operand_type_check (i
.types
[n1
], imm
))
5788 /* Only one immediate is allowed for PC
5789 relative address. */
5790 gas_assert (sz
== 0);
5792 i
.op
[n
].disps
->X_add_number
-= sz
;
5794 /* We should find the immediate. */
5795 gas_assert (sz
!= 0);
5798 p
= frag_more (size
);
5799 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5801 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5802 && (((reloc_type
== BFD_RELOC_32
5803 || reloc_type
== BFD_RELOC_X86_64_32S
5804 || (reloc_type
== BFD_RELOC_64
5806 && (i
.op
[n
].disps
->X_op
== O_symbol
5807 || (i
.op
[n
].disps
->X_op
== O_add
5808 && ((symbol_get_value_expression
5809 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5811 || reloc_type
== BFD_RELOC_32_PCREL
))
5815 if (insn_start_frag
== frag_now
)
5816 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5821 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5822 for (fr
= insn_start_frag
->fr_next
;
5823 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5825 add
+= p
- frag_now
->fr_literal
;
5830 reloc_type
= BFD_RELOC_386_GOTPC
;
5831 i
.op
[n
].imms
->X_add_number
+= add
;
5833 else if (reloc_type
== BFD_RELOC_64
)
5834 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5836 /* Don't do the adjustment for x86-64, as there
5837 the pcrel addressing is relative to the _next_
5838 insn, and that is taken care of in other code. */
5839 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5841 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5842 i
.op
[n
].disps
, pcrel
, reloc_type
);
5849 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5854 for (n
= 0; n
< i
.operands
; n
++)
5856 if (operand_type_check (i
.types
[n
], imm
))
5858 if (i
.op
[n
].imms
->X_op
== O_constant
)
5860 int size
= imm_size (n
);
5863 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5865 p
= frag_more (size
);
5866 md_number_to_chars (p
, val
, size
);
5870 /* Not absolute_section.
5871 Need a 32-bit fixup (don't support 8bit
5872 non-absolute imms). Try to support other
5874 enum bfd_reloc_code_real reloc_type
;
5875 int size
= imm_size (n
);
5878 if (i
.types
[n
].bitfield
.imm32s
5879 && (i
.suffix
== QWORD_MNEM_SUFFIX
5880 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5885 p
= frag_more (size
);
5886 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5888 /* This is tough to explain. We end up with this one if we
5889 * have operands that look like
5890 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5891 * obtain the absolute address of the GOT, and it is strongly
5892 * preferable from a performance point of view to avoid using
5893 * a runtime relocation for this. The actual sequence of
5894 * instructions often look something like:
5899 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5901 * The call and pop essentially return the absolute address
5902 * of the label .L66 and store it in %ebx. The linker itself
5903 * will ultimately change the first operand of the addl so
5904 * that %ebx points to the GOT, but to keep things simple, the
5905 * .o file must have this operand set so that it generates not
5906 * the absolute address of .L66, but the absolute address of
5907 * itself. This allows the linker itself simply treat a GOTPC
5908 * relocation as asking for a pcrel offset to the GOT to be
5909 * added in, and the addend of the relocation is stored in the
5910 * operand field for the instruction itself.
5912 * Our job here is to fix the operand so that it would add
5913 * the correct offset so that %ebx would point to itself. The
5914 * thing that is tricky is that .-.L66 will point to the
5915 * beginning of the instruction, so we need to further modify
5916 * the operand so that it will point to itself. There are
5917 * other cases where you have something like:
5919 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5921 * and here no correction would be required. Internally in
5922 * the assembler we treat operands of this form as not being
5923 * pcrel since the '.' is explicitly mentioned, and I wonder
5924 * whether it would simplify matters to do it this way. Who
5925 * knows. In earlier versions of the PIC patches, the
5926 * pcrel_adjust field was used to store the correction, but
5927 * since the expression is not pcrel, I felt it would be
5928 * confusing to do it this way. */
5930 if ((reloc_type
== BFD_RELOC_32
5931 || reloc_type
== BFD_RELOC_X86_64_32S
5932 || reloc_type
== BFD_RELOC_64
)
5934 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5935 && (i
.op
[n
].imms
->X_op
== O_symbol
5936 || (i
.op
[n
].imms
->X_op
== O_add
5937 && ((symbol_get_value_expression
5938 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5943 if (insn_start_frag
== frag_now
)
5944 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5949 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5950 for (fr
= insn_start_frag
->fr_next
;
5951 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5953 add
+= p
- frag_now
->fr_literal
;
5957 reloc_type
= BFD_RELOC_386_GOTPC
;
5959 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5961 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5962 i
.op
[n
].imms
->X_add_number
+= add
;
5964 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5965 i
.op
[n
].imms
, 0, reloc_type
);
5971 /* x86_cons_fix_new is called via the expression parsing code when a
5972 reloc is needed. We use this hook to get the correct .got reloc. */
5973 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5974 static int cons_sign
= -1;
5977 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5980 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5982 got_reloc
= NO_RELOC
;
5985 if (exp
->X_op
== O_secrel
)
5987 exp
->X_op
= O_symbol
;
5988 r
= BFD_RELOC_32_SECREL
;
5992 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5995 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5996 # define lex_got(reloc, adjust, types) NULL
5998 /* Parse operands of the form
5999 <symbol>@GOTOFF+<nnn>
6000 and similar .plt or .got references.
6002 If we find one, set up the correct relocation in RELOC and copy the
6003 input string, minus the `@GOTOFF' into a malloc'd buffer for
6004 parsing by the calling routine. Return this buffer, and if ADJUST
6005 is non-null set it to the length of the string we removed from the
6006 input line. Otherwise return NULL. */
6008 lex_got (enum bfd_reloc_code_real
*reloc
,
6010 i386_operand_type
*types
)
6012 /* Some of the relocations depend on the size of what field is to
6013 be relocated. But in our callers i386_immediate and i386_displacement
6014 we don't yet know the operand size (this will be set by insn
6015 matching). Hence we record the word32 relocation here,
6016 and adjust the reloc according to the real size in reloc(). */
6017 static const struct {
6019 const enum bfd_reloc_code_real rel
[2];
6020 const i386_operand_type types64
;
6022 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6023 BFD_RELOC_X86_64_PLTOFF64
},
6024 OPERAND_TYPE_IMM64
},
6025 { "PLT", { BFD_RELOC_386_PLT32
,
6026 BFD_RELOC_X86_64_PLT32
},
6027 OPERAND_TYPE_IMM32_32S_DISP32
},
6028 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6029 BFD_RELOC_X86_64_GOTPLT64
},
6030 OPERAND_TYPE_IMM64_DISP64
},
6031 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6032 BFD_RELOC_X86_64_GOTOFF64
},
6033 OPERAND_TYPE_IMM64_DISP64
},
6034 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6035 BFD_RELOC_X86_64_GOTPCREL
},
6036 OPERAND_TYPE_IMM32_32S_DISP32
},
6037 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6038 BFD_RELOC_X86_64_TLSGD
},
6039 OPERAND_TYPE_IMM32_32S_DISP32
},
6040 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6041 _dummy_first_bfd_reloc_code_real
},
6042 OPERAND_TYPE_NONE
},
6043 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6044 BFD_RELOC_X86_64_TLSLD
},
6045 OPERAND_TYPE_IMM32_32S_DISP32
},
6046 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6047 BFD_RELOC_X86_64_GOTTPOFF
},
6048 OPERAND_TYPE_IMM32_32S_DISP32
},
6049 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6050 BFD_RELOC_X86_64_TPOFF32
},
6051 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6052 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6053 _dummy_first_bfd_reloc_code_real
},
6054 OPERAND_TYPE_NONE
},
6055 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6056 BFD_RELOC_X86_64_DTPOFF32
},
6058 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6059 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6060 _dummy_first_bfd_reloc_code_real
},
6061 OPERAND_TYPE_NONE
},
6062 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6063 _dummy_first_bfd_reloc_code_real
},
6064 OPERAND_TYPE_NONE
},
6065 { "GOT", { BFD_RELOC_386_GOT32
,
6066 BFD_RELOC_X86_64_GOT32
},
6067 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6068 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6069 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6070 OPERAND_TYPE_IMM32_32S_DISP32
},
6071 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6072 BFD_RELOC_X86_64_TLSDESC_CALL
},
6073 OPERAND_TYPE_IMM32_32S_DISP32
},
6081 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6082 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6085 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6089 len
= strlen (gotrel
[j
].str
);
6090 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6092 if (gotrel
[j
].rel
[object_64bit
] != 0)
6095 char *tmpbuf
, *past_reloc
;
6097 *reloc
= gotrel
[j
].rel
[object_64bit
];
6103 if (flag_code
!= CODE_64BIT
)
6105 types
->bitfield
.imm32
= 1;
6106 types
->bitfield
.disp32
= 1;
6109 *types
= gotrel
[j
].types64
;
6112 if (GOT_symbol
== NULL
)
6113 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6115 /* The length of the first part of our input line. */
6116 first
= cp
- input_line_pointer
;
6118 /* The second part goes from after the reloc token until
6119 (and including) an end_of_line char or comma. */
6120 past_reloc
= cp
+ 1 + len
;
6122 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6124 second
= cp
+ 1 - past_reloc
;
6126 /* Allocate and copy string. The trailing NUL shouldn't
6127 be necessary, but be safe. */
6128 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6129 memcpy (tmpbuf
, input_line_pointer
, first
);
6130 if (second
!= 0 && *past_reloc
!= ' ')
6131 /* Replace the relocation token with ' ', so that
6132 errors like foo@GOTOFF1 will be detected. */
6133 tmpbuf
[first
++] = ' ';
6134 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6135 tmpbuf
[first
+ second
] = '\0';
6139 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6140 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6145 /* Might be a symbol version string. Don't as_bad here. */
6150 x86_cons (expressionS
*exp
, int size
)
6152 intel_syntax
= -intel_syntax
;
6154 if (size
== 4 || (object_64bit
&& size
== 8))
6156 /* Handle @GOTOFF and the like in an expression. */
6158 char *gotfree_input_line
;
6161 save
= input_line_pointer
;
6162 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6163 if (gotfree_input_line
)
6164 input_line_pointer
= gotfree_input_line
;
6168 if (gotfree_input_line
)
6170 /* expression () has merrily parsed up to the end of line,
6171 or a comma - in the wrong buffer. Transfer how far
6172 input_line_pointer has moved to the right buffer. */
6173 input_line_pointer
= (save
6174 + (input_line_pointer
- gotfree_input_line
)
6176 free (gotfree_input_line
);
6177 if (exp
->X_op
== O_constant
6178 || exp
->X_op
== O_absent
6179 || exp
->X_op
== O_illegal
6180 || exp
->X_op
== O_register
6181 || exp
->X_op
== O_big
)
6183 char c
= *input_line_pointer
;
6184 *input_line_pointer
= 0;
6185 as_bad (_("missing or invalid expression `%s'"), save
);
6186 *input_line_pointer
= c
;
6193 intel_syntax
= -intel_syntax
;
6196 i386_intel_simplify (exp
);
6200 static void signed_cons (int size
)
6202 if (flag_code
== CODE_64BIT
)
6210 pe_directive_secrel (dummy
)
6211 int dummy ATTRIBUTE_UNUSED
;
6218 if (exp
.X_op
== O_symbol
)
6219 exp
.X_op
= O_secrel
;
6221 emit_expr (&exp
, 4);
6223 while (*input_line_pointer
++ == ',');
6225 input_line_pointer
--;
6226 demand_empty_rest_of_line ();
6231 i386_immediate (char *imm_start
)
6233 char *save_input_line_pointer
;
6234 char *gotfree_input_line
;
6237 i386_operand_type types
;
6239 operand_type_set (&types
, ~0);
6241 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6243 as_bad (_("at most %d immediate operands are allowed"),
6244 MAX_IMMEDIATE_OPERANDS
);
6248 exp
= &im_expressions
[i
.imm_operands
++];
6249 i
.op
[this_operand
].imms
= exp
;
6251 if (is_space_char (*imm_start
))
6254 save_input_line_pointer
= input_line_pointer
;
6255 input_line_pointer
= imm_start
;
6257 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6258 if (gotfree_input_line
)
6259 input_line_pointer
= gotfree_input_line
;
6261 exp_seg
= expression (exp
);
6264 if (*input_line_pointer
)
6265 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6267 input_line_pointer
= save_input_line_pointer
;
6268 if (gotfree_input_line
)
6270 free (gotfree_input_line
);
6272 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6273 exp
->X_op
= O_illegal
;
6276 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6280 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6281 i386_operand_type types
, const char *imm_start
)
6283 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6285 as_bad (_("missing or invalid immediate expression `%s'"),
6289 else if (exp
->X_op
== O_constant
)
6291 /* Size it properly later. */
6292 i
.types
[this_operand
].bitfield
.imm64
= 1;
6293 /* If BFD64, sign extend val. */
6294 if (!use_rela_relocations
6295 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6297 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6299 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6300 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6301 && exp_seg
!= absolute_section
6302 && exp_seg
!= text_section
6303 && exp_seg
!= data_section
6304 && exp_seg
!= bss_section
6305 && exp_seg
!= undefined_section
6306 && !bfd_is_com_section (exp_seg
))
6308 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6312 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6314 as_bad (_("illegal immediate register operand %s"), imm_start
);
6319 /* This is an address. The size of the address will be
6320 determined later, depending on destination register,
6321 suffix, or the default for the section. */
6322 i
.types
[this_operand
].bitfield
.imm8
= 1;
6323 i
.types
[this_operand
].bitfield
.imm16
= 1;
6324 i
.types
[this_operand
].bitfield
.imm32
= 1;
6325 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6326 i
.types
[this_operand
].bitfield
.imm64
= 1;
6327 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6335 i386_scale (char *scale
)
6338 char *save
= input_line_pointer
;
6340 input_line_pointer
= scale
;
6341 val
= get_absolute_expression ();
6346 i
.log2_scale_factor
= 0;
6349 i
.log2_scale_factor
= 1;
6352 i
.log2_scale_factor
= 2;
6355 i
.log2_scale_factor
= 3;
6359 char sep
= *input_line_pointer
;
6361 *input_line_pointer
= '\0';
6362 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6364 *input_line_pointer
= sep
;
6365 input_line_pointer
= save
;
6369 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6371 as_warn (_("scale factor of %d without an index register"),
6372 1 << i
.log2_scale_factor
);
6373 i
.log2_scale_factor
= 0;
6375 scale
= input_line_pointer
;
6376 input_line_pointer
= save
;
6381 i386_displacement (char *disp_start
, char *disp_end
)
6385 char *save_input_line_pointer
;
6386 char *gotfree_input_line
;
6388 i386_operand_type bigdisp
, types
= anydisp
;
6391 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6393 as_bad (_("at most %d displacement operands are allowed"),
6394 MAX_MEMORY_OPERANDS
);
6398 operand_type_set (&bigdisp
, 0);
6399 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6400 || (!current_templates
->start
->opcode_modifier
.jump
6401 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6403 bigdisp
.bitfield
.disp32
= 1;
6404 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6405 if (flag_code
== CODE_64BIT
)
6409 bigdisp
.bitfield
.disp32s
= 1;
6410 bigdisp
.bitfield
.disp64
= 1;
6413 else if ((flag_code
== CODE_16BIT
) ^ override
)
6415 bigdisp
.bitfield
.disp32
= 0;
6416 bigdisp
.bitfield
.disp16
= 1;
6421 /* For PC-relative branches, the width of the displacement
6422 is dependent upon data size, not address size. */
6423 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6424 if (flag_code
== CODE_64BIT
)
6426 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6427 bigdisp
.bitfield
.disp16
= 1;
6430 bigdisp
.bitfield
.disp32
= 1;
6431 bigdisp
.bitfield
.disp32s
= 1;
6437 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6439 : LONG_MNEM_SUFFIX
));
6440 bigdisp
.bitfield
.disp32
= 1;
6441 if ((flag_code
== CODE_16BIT
) ^ override
)
6443 bigdisp
.bitfield
.disp32
= 0;
6444 bigdisp
.bitfield
.disp16
= 1;
6448 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6451 exp
= &disp_expressions
[i
.disp_operands
];
6452 i
.op
[this_operand
].disps
= exp
;
6454 save_input_line_pointer
= input_line_pointer
;
6455 input_line_pointer
= disp_start
;
6456 END_STRING_AND_SAVE (disp_end
);
6458 #ifndef GCC_ASM_O_HACK
6459 #define GCC_ASM_O_HACK 0
6462 END_STRING_AND_SAVE (disp_end
+ 1);
6463 if (i
.types
[this_operand
].bitfield
.baseIndex
6464 && displacement_string_end
[-1] == '+')
6466 /* This hack is to avoid a warning when using the "o"
6467 constraint within gcc asm statements.
6470 #define _set_tssldt_desc(n,addr,limit,type) \
6471 __asm__ __volatile__ ( \
6473 "movw %w1,2+%0\n\t" \
6475 "movb %b1,4+%0\n\t" \
6476 "movb %4,5+%0\n\t" \
6477 "movb $0,6+%0\n\t" \
6478 "movb %h1,7+%0\n\t" \
6480 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6482 This works great except that the output assembler ends
6483 up looking a bit weird if it turns out that there is
6484 no offset. You end up producing code that looks like:
6497 So here we provide the missing zero. */
6499 *displacement_string_end
= '0';
6502 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6503 if (gotfree_input_line
)
6504 input_line_pointer
= gotfree_input_line
;
6506 exp_seg
= expression (exp
);
6509 if (*input_line_pointer
)
6510 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6512 RESTORE_END_STRING (disp_end
+ 1);
6514 input_line_pointer
= save_input_line_pointer
;
6515 if (gotfree_input_line
)
6517 free (gotfree_input_line
);
6519 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6520 exp
->X_op
= O_illegal
;
6523 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6525 RESTORE_END_STRING (disp_end
);
6531 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6532 i386_operand_type types
, const char *disp_start
)
6534 i386_operand_type bigdisp
;
6537 /* We do this to make sure that the section symbol is in
6538 the symbol table. We will ultimately change the relocation
6539 to be relative to the beginning of the section. */
6540 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6541 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6542 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6544 if (exp
->X_op
!= O_symbol
)
6547 if (S_IS_LOCAL (exp
->X_add_symbol
)
6548 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6549 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6550 exp
->X_op
= O_subtract
;
6551 exp
->X_op_symbol
= GOT_symbol
;
6552 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6553 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6554 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6555 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6557 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6560 else if (exp
->X_op
== O_absent
6561 || exp
->X_op
== O_illegal
6562 || exp
->X_op
== O_big
)
6565 as_bad (_("missing or invalid displacement expression `%s'"),
6570 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6571 else if (exp
->X_op
!= O_constant
6572 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6573 && exp_seg
!= absolute_section
6574 && exp_seg
!= text_section
6575 && exp_seg
!= data_section
6576 && exp_seg
!= bss_section
6577 && exp_seg
!= undefined_section
6578 && !bfd_is_com_section (exp_seg
))
6580 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6585 /* Check if this is a displacement only operand. */
6586 bigdisp
= i
.types
[this_operand
];
6587 bigdisp
.bitfield
.disp8
= 0;
6588 bigdisp
.bitfield
.disp16
= 0;
6589 bigdisp
.bitfield
.disp32
= 0;
6590 bigdisp
.bitfield
.disp32s
= 0;
6591 bigdisp
.bitfield
.disp64
= 0;
6592 if (operand_type_all_zero (&bigdisp
))
6593 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6599 /* Make sure the memory operand we've been dealt is valid.
6600 Return 1 on success, 0 on a failure. */
6603 i386_index_check (const char *operand_string
)
6606 const char *kind
= "base/index";
6607 #if INFER_ADDR_PREFIX
6613 if (current_templates
->start
->opcode_modifier
.isstring
6614 && !current_templates
->start
->opcode_modifier
.immext
6615 && (current_templates
->end
[-1].opcode_modifier
.isstring
6618 /* Memory operands of string insns are special in that they only allow
6619 a single register (rDI, rSI, or rBX) as their memory address. */
6620 unsigned int expected
;
6622 kind
= "string address";
6624 if (current_templates
->start
->opcode_modifier
.w
)
6626 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6628 if (!type
.bitfield
.baseindex
6629 || ((!i
.mem_operands
!= !intel_syntax
)
6630 && current_templates
->end
[-1].operand_types
[1]
6631 .bitfield
.baseindex
))
6632 type
= current_templates
->end
[-1].operand_types
[1];
6633 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6636 expected
= 3 /* rBX */;
6638 if (!i
.base_reg
|| i
.index_reg
6639 || operand_type_check (i
.types
[this_operand
], disp
))
6641 else if (!(flag_code
== CODE_64BIT
6642 ? i
.prefix
[ADDR_PREFIX
]
6643 ? i
.base_reg
->reg_type
.bitfield
.reg32
6644 : i
.base_reg
->reg_type
.bitfield
.reg64
6645 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6646 ? i
.base_reg
->reg_type
.bitfield
.reg32
6647 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6649 else if (i
.base_reg
->reg_num
!= expected
)
6656 for (j
= 0; j
< i386_regtab_size
; ++j
)
6657 if ((flag_code
== CODE_64BIT
6658 ? i
.prefix
[ADDR_PREFIX
]
6659 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6660 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6661 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6662 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6663 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6664 && i386_regtab
[j
].reg_num
== expected
)
6666 gas_assert (j
< i386_regtab_size
);
6667 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6669 intel_syntax
? '[' : '(',
6671 i386_regtab
[j
].reg_name
,
6672 intel_syntax
? ']' : ')');
6676 else if (flag_code
== CODE_64BIT
)
6679 && ((i
.prefix
[ADDR_PREFIX
] == 0
6680 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6681 || (i
.prefix
[ADDR_PREFIX
]
6682 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6684 || i
.base_reg
->reg_num
!=
6685 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6687 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6688 || (i
.prefix
[ADDR_PREFIX
] == 0
6689 && i
.index_reg
->reg_num
!= RegRiz
6690 && !i
.index_reg
->reg_type
.bitfield
.reg64
6692 || (i
.prefix
[ADDR_PREFIX
]
6693 && i
.index_reg
->reg_num
!= RegEiz
6694 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6699 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6703 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6704 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6706 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6707 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6709 && i
.base_reg
->reg_num
< 6
6710 && i
.index_reg
->reg_num
>= 6
6711 && i
.log2_scale_factor
== 0))))
6718 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6720 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6721 && i
.index_reg
->reg_num
!= RegEiz
)
6722 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6728 #if INFER_ADDR_PREFIX
6729 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6731 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6733 /* Change the size of any displacement too. At most one of
6734 Disp16 or Disp32 is set.
6735 FIXME. There doesn't seem to be any real need for separate
6736 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6737 Removing them would probably clean up the code quite a lot. */
6738 if (flag_code
!= CODE_64BIT
6739 && (i
.types
[this_operand
].bitfield
.disp16
6740 || i
.types
[this_operand
].bitfield
.disp32
))
6741 i
.types
[this_operand
]
6742 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6747 as_bad (_("`%s' is not a valid %s expression"),
6752 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6754 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6755 ? flag_code
== CODE_32BIT
6764 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6768 i386_att_operand (char *operand_string
)
6772 char *op_string
= operand_string
;
6774 if (is_space_char (*op_string
))
6777 /* We check for an absolute prefix (differentiating,
6778 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6779 if (*op_string
== ABSOLUTE_PREFIX
)
6782 if (is_space_char (*op_string
))
6784 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6787 /* Check if operand is a register. */
6788 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6790 i386_operand_type temp
;
6792 /* Check for a segment override by searching for ':' after a
6793 segment register. */
6795 if (is_space_char (*op_string
))
6797 if (*op_string
== ':'
6798 && (r
->reg_type
.bitfield
.sreg2
6799 || r
->reg_type
.bitfield
.sreg3
))
6804 i
.seg
[i
.mem_operands
] = &es
;
6807 i
.seg
[i
.mem_operands
] = &cs
;
6810 i
.seg
[i
.mem_operands
] = &ss
;
6813 i
.seg
[i
.mem_operands
] = &ds
;
6816 i
.seg
[i
.mem_operands
] = &fs
;
6819 i
.seg
[i
.mem_operands
] = &gs
;
6823 /* Skip the ':' and whitespace. */
6825 if (is_space_char (*op_string
))
6828 if (!is_digit_char (*op_string
)
6829 && !is_identifier_char (*op_string
)
6830 && *op_string
!= '('
6831 && *op_string
!= ABSOLUTE_PREFIX
)
6833 as_bad (_("bad memory operand `%s'"), op_string
);
6836 /* Handle case of %es:*foo. */
6837 if (*op_string
== ABSOLUTE_PREFIX
)
6840 if (is_space_char (*op_string
))
6842 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6844 goto do_memory_reference
;
6848 as_bad (_("junk `%s' after register"), op_string
);
6852 temp
.bitfield
.baseindex
= 0;
6853 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6855 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6856 i
.op
[this_operand
].regs
= r
;
6859 else if (*op_string
== REGISTER_PREFIX
)
6861 as_bad (_("bad register name `%s'"), op_string
);
6864 else if (*op_string
== IMMEDIATE_PREFIX
)
6867 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6869 as_bad (_("immediate operand illegal with absolute jump"));
6872 if (!i386_immediate (op_string
))
6875 else if (is_digit_char (*op_string
)
6876 || is_identifier_char (*op_string
)
6877 || *op_string
== '(')
6879 /* This is a memory reference of some sort. */
6882 /* Start and end of displacement string expression (if found). */
6883 char *displacement_string_start
;
6884 char *displacement_string_end
;
6886 do_memory_reference
:
6887 if ((i
.mem_operands
== 1
6888 && !current_templates
->start
->opcode_modifier
.isstring
)
6889 || i
.mem_operands
== 2)
6891 as_bad (_("too many memory references for `%s'"),
6892 current_templates
->start
->name
);
6896 /* Check for base index form. We detect the base index form by
6897 looking for an ')' at the end of the operand, searching
6898 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6900 base_string
= op_string
+ strlen (op_string
);
6903 if (is_space_char (*base_string
))
6906 /* If we only have a displacement, set-up for it to be parsed later. */
6907 displacement_string_start
= op_string
;
6908 displacement_string_end
= base_string
+ 1;
6910 if (*base_string
== ')')
6913 unsigned int parens_balanced
= 1;
6914 /* We've already checked that the number of left & right ()'s are
6915 equal, so this loop will not be infinite. */
6919 if (*base_string
== ')')
6921 if (*base_string
== '(')
6924 while (parens_balanced
);
6926 temp_string
= base_string
;
6928 /* Skip past '(' and whitespace. */
6930 if (is_space_char (*base_string
))
6933 if (*base_string
== ','
6934 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6937 displacement_string_end
= temp_string
;
6939 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6943 base_string
= end_op
;
6944 if (is_space_char (*base_string
))
6948 /* There may be an index reg or scale factor here. */
6949 if (*base_string
== ',')
6952 if (is_space_char (*base_string
))
6955 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6958 base_string
= end_op
;
6959 if (is_space_char (*base_string
))
6961 if (*base_string
== ',')
6964 if (is_space_char (*base_string
))
6967 else if (*base_string
!= ')')
6969 as_bad (_("expecting `,' or `)' "
6970 "after index register in `%s'"),
6975 else if (*base_string
== REGISTER_PREFIX
)
6977 as_bad (_("bad register name `%s'"), base_string
);
6981 /* Check for scale factor. */
6982 if (*base_string
!= ')')
6984 char *end_scale
= i386_scale (base_string
);
6989 base_string
= end_scale
;
6990 if (is_space_char (*base_string
))
6992 if (*base_string
!= ')')
6994 as_bad (_("expecting `)' "
6995 "after scale factor in `%s'"),
7000 else if (!i
.index_reg
)
7002 as_bad (_("expecting index register or scale factor "
7003 "after `,'; got '%c'"),
7008 else if (*base_string
!= ')')
7010 as_bad (_("expecting `,' or `)' "
7011 "after base register in `%s'"),
7016 else if (*base_string
== REGISTER_PREFIX
)
7018 as_bad (_("bad register name `%s'"), base_string
);
7023 /* If there's an expression beginning the operand, parse it,
7024 assuming displacement_string_start and
7025 displacement_string_end are meaningful. */
7026 if (displacement_string_start
!= displacement_string_end
)
7028 if (!i386_displacement (displacement_string_start
,
7029 displacement_string_end
))
7033 /* Special case for (%dx) while doing input/output op. */
7035 && operand_type_equal (&i
.base_reg
->reg_type
,
7036 ®16_inoutportreg
)
7038 && i
.log2_scale_factor
== 0
7039 && i
.seg
[i
.mem_operands
] == 0
7040 && !operand_type_check (i
.types
[this_operand
], disp
))
7042 i
.types
[this_operand
] = inoutportreg
;
7046 if (i386_index_check (operand_string
) == 0)
7048 i
.types
[this_operand
].bitfield
.mem
= 1;
7053 /* It's not a memory operand; argh! */
7054 as_bad (_("invalid char %s beginning operand %d `%s'"),
7055 output_invalid (*op_string
),
7060 return 1; /* Normal return. */
7063 /* md_estimate_size_before_relax()
7065 Called just before relax() for rs_machine_dependent frags. The x86
7066 assembler uses these frags to handle variable size jump
7069 Any symbol that is now undefined will not become defined.
7070 Return the correct fr_subtype in the frag.
7071 Return the initial "guess for variable size of frag" to caller.
7072 The guess is actually the growth beyond the fixed part. Whatever
7073 we do to grow the fixed or variable part contributes to our
7077 md_estimate_size_before_relax (fragP
, segment
)
7081 /* We've already got fragP->fr_subtype right; all we have to do is
7082 check for un-relaxable symbols. On an ELF system, we can't relax
7083 an externally visible symbol, because it may be overridden by a
7085 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7088 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7089 || S_IS_WEAK (fragP
->fr_symbol
)
7090 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7091 & BSF_GNU_INDIRECT_FUNCTION
))))
7093 #if defined (OBJ_COFF) && defined (TE_PE)
7094 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7095 && S_IS_WEAK (fragP
->fr_symbol
))
7099 /* Symbol is undefined in this segment, or we need to keep a
7100 reloc so that weak symbols can be overridden. */
7101 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7102 enum bfd_reloc_code_real reloc_type
;
7103 unsigned char *opcode
;
7106 if (fragP
->fr_var
!= NO_RELOC
)
7107 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7109 reloc_type
= BFD_RELOC_16_PCREL
;
7111 reloc_type
= BFD_RELOC_32_PCREL
;
7113 old_fr_fix
= fragP
->fr_fix
;
7114 opcode
= (unsigned char *) fragP
->fr_opcode
;
7116 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7119 /* Make jmp (0xeb) a (d)word displacement jump. */
7121 fragP
->fr_fix
+= size
;
7122 fix_new (fragP
, old_fr_fix
, size
,
7124 fragP
->fr_offset
, 1,
7130 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7132 /* Negate the condition, and branch past an
7133 unconditional jump. */
7136 /* Insert an unconditional jump. */
7138 /* We added two extra opcode bytes, and have a two byte
7140 fragP
->fr_fix
+= 2 + 2;
7141 fix_new (fragP
, old_fr_fix
+ 2, 2,
7143 fragP
->fr_offset
, 1,
7150 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7155 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7157 fragP
->fr_offset
, 1,
7159 fixP
->fx_signed
= 1;
7163 /* This changes the byte-displacement jump 0x7N
7164 to the (d)word-displacement jump 0x0f,0x8N. */
7165 opcode
[1] = opcode
[0] + 0x10;
7166 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7167 /* We've added an opcode byte. */
7168 fragP
->fr_fix
+= 1 + size
;
7169 fix_new (fragP
, old_fr_fix
+ 1, size
,
7171 fragP
->fr_offset
, 1,
7176 BAD_CASE (fragP
->fr_subtype
);
7180 return fragP
->fr_fix
- old_fr_fix
;
7183 /* Guess size depending on current relax state. Initially the relax
7184 state will correspond to a short jump and we return 1, because
7185 the variable part of the frag (the branch offset) is one byte
7186 long. However, we can relax a section more than once and in that
7187 case we must either set fr_subtype back to the unrelaxed state,
7188 or return the value for the appropriate branch. */
7189 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7192 /* Called after relax() is finished.
7194 In: Address of frag.
7195 fr_type == rs_machine_dependent.
7196 fr_subtype is what the address relaxed to.
7198 Out: Any fixSs and constants are set up.
7199 Caller will turn frag into a ".space 0". */
7202 md_convert_frag (abfd
, sec
, fragP
)
7203 bfd
*abfd ATTRIBUTE_UNUSED
;
7204 segT sec ATTRIBUTE_UNUSED
;
7207 unsigned char *opcode
;
7208 unsigned char *where_to_put_displacement
= NULL
;
7209 offsetT target_address
;
7210 offsetT opcode_address
;
7211 unsigned int extension
= 0;
7212 offsetT displacement_from_opcode_start
;
7214 opcode
= (unsigned char *) fragP
->fr_opcode
;
7216 /* Address we want to reach in file space. */
7217 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7219 /* Address opcode resides at in file space. */
7220 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7222 /* Displacement from opcode start to fill into instruction. */
7223 displacement_from_opcode_start
= target_address
- opcode_address
;
7225 if ((fragP
->fr_subtype
& BIG
) == 0)
7227 /* Don't have to change opcode. */
7228 extension
= 1; /* 1 opcode + 1 displacement */
7229 where_to_put_displacement
= &opcode
[1];
7233 if (no_cond_jump_promotion
7234 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7235 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7236 _("long jump required"));
7238 switch (fragP
->fr_subtype
)
7240 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7241 extension
= 4; /* 1 opcode + 4 displacement */
7243 where_to_put_displacement
= &opcode
[1];
7246 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7247 extension
= 2; /* 1 opcode + 2 displacement */
7249 where_to_put_displacement
= &opcode
[1];
7252 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7253 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7254 extension
= 5; /* 2 opcode + 4 displacement */
7255 opcode
[1] = opcode
[0] + 0x10;
7256 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7257 where_to_put_displacement
= &opcode
[2];
7260 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7261 extension
= 3; /* 2 opcode + 2 displacement */
7262 opcode
[1] = opcode
[0] + 0x10;
7263 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7264 where_to_put_displacement
= &opcode
[2];
7267 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7272 where_to_put_displacement
= &opcode
[3];
7276 BAD_CASE (fragP
->fr_subtype
);
7281 /* If size if less then four we are sure that the operand fits,
7282 but if it's 4, then it could be that the displacement is larger
7284 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7286 && ((addressT
) (displacement_from_opcode_start
- extension
7287 + ((addressT
) 1 << 31))
7288 > (((addressT
) 2 << 31) - 1)))
7290 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7291 _("jump target out of range"));
7292 /* Make us emit 0. */
7293 displacement_from_opcode_start
= extension
;
7295 /* Now put displacement after opcode. */
7296 md_number_to_chars ((char *) where_to_put_displacement
,
7297 (valueT
) (displacement_from_opcode_start
- extension
),
7298 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7299 fragP
->fr_fix
+= extension
;
7302 /* Apply a fixup (fixS) to segment data, once it has been determined
7303 by our caller that we have all the info we need to fix it up.
7305 On the 386, immediates, displacements, and data pointers are all in
7306 the same (little-endian) format, so we don't need to care about which
7310 md_apply_fix (fixP
, valP
, seg
)
7311 /* The fix we're to put in. */
7313 /* Pointer to the value of the bits. */
7315 /* Segment fix is from. */
7316 segT seg ATTRIBUTE_UNUSED
;
7318 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7319 valueT value
= *valP
;
7321 #if !defined (TE_Mach)
7324 switch (fixP
->fx_r_type
)
7330 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7333 case BFD_RELOC_X86_64_32S
:
7334 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7337 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7340 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7345 if (fixP
->fx_addsy
!= NULL
7346 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7347 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7348 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7349 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7350 && !use_rela_relocations
)
7352 /* This is a hack. There should be a better way to handle this.
7353 This covers for the fact that bfd_install_relocation will
7354 subtract the current location (for partial_inplace, PC relative
7355 relocations); see more below. */
7359 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7362 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7367 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7370 || (symbol_section_p (fixP
->fx_addsy
)
7371 && sym_seg
!= absolute_section
))
7372 && !generic_force_reloc (fixP
))
7374 /* Yes, we add the values in twice. This is because
7375 bfd_install_relocation subtracts them out again. I think
7376 bfd_install_relocation is broken, but I don't dare change
7378 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7382 #if defined (OBJ_COFF) && defined (TE_PE)
7383 /* For some reason, the PE format does not store a
7384 section address offset for a PC relative symbol. */
7385 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7386 || S_IS_WEAK (fixP
->fx_addsy
))
7387 value
+= md_pcrel_from (fixP
);
7390 #if defined (OBJ_COFF) && defined (TE_PE)
7391 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7393 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7397 /* Fix a few things - the dynamic linker expects certain values here,
7398 and we must not disappoint it. */
7399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7400 if (IS_ELF
&& fixP
->fx_addsy
)
7401 switch (fixP
->fx_r_type
)
7403 case BFD_RELOC_386_PLT32
:
7404 case BFD_RELOC_X86_64_PLT32
:
7405 /* Make the jump instruction point to the address of the operand. At
7406 runtime we merely add the offset to the actual PLT entry. */
7410 case BFD_RELOC_386_TLS_GD
:
7411 case BFD_RELOC_386_TLS_LDM
:
7412 case BFD_RELOC_386_TLS_IE_32
:
7413 case BFD_RELOC_386_TLS_IE
:
7414 case BFD_RELOC_386_TLS_GOTIE
:
7415 case BFD_RELOC_386_TLS_GOTDESC
:
7416 case BFD_RELOC_X86_64_TLSGD
:
7417 case BFD_RELOC_X86_64_TLSLD
:
7418 case BFD_RELOC_X86_64_GOTTPOFF
:
7419 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7420 value
= 0; /* Fully resolved at runtime. No addend. */
7422 case BFD_RELOC_386_TLS_LE
:
7423 case BFD_RELOC_386_TLS_LDO_32
:
7424 case BFD_RELOC_386_TLS_LE_32
:
7425 case BFD_RELOC_X86_64_DTPOFF32
:
7426 case BFD_RELOC_X86_64_DTPOFF64
:
7427 case BFD_RELOC_X86_64_TPOFF32
:
7428 case BFD_RELOC_X86_64_TPOFF64
:
7429 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7432 case BFD_RELOC_386_TLS_DESC_CALL
:
7433 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7434 value
= 0; /* Fully resolved at runtime. No addend. */
7435 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7439 case BFD_RELOC_386_GOT32
:
7440 case BFD_RELOC_X86_64_GOT32
:
7441 value
= 0; /* Fully resolved at runtime. No addend. */
7444 case BFD_RELOC_VTABLE_INHERIT
:
7445 case BFD_RELOC_VTABLE_ENTRY
:
7452 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7454 #endif /* !defined (TE_Mach) */
7456 /* Are we finished with this relocation now? */
7457 if (fixP
->fx_addsy
== NULL
)
7459 #if defined (OBJ_COFF) && defined (TE_PE)
7460 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7463 /* Remember value for tc_gen_reloc. */
7464 fixP
->fx_addnumber
= value
;
7465 /* Clear out the frag for now. */
7469 else if (use_rela_relocations
)
7471 fixP
->fx_no_overflow
= 1;
7472 /* Remember value for tc_gen_reloc. */
7473 fixP
->fx_addnumber
= value
;
7477 md_number_to_chars (p
, value
, fixP
->fx_size
);
7481 md_atof (int type
, char *litP
, int *sizeP
)
7483 /* This outputs the LITTLENUMs in REVERSE order;
7484 in accord with the bigendian 386. */
7485 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7488 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7491 output_invalid (int c
)
7494 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7497 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7498 "(0x%x)", (unsigned char) c
);
7499 return output_invalid_buf
;
7502 /* REG_STRING starts *before* REGISTER_PREFIX. */
7504 static const reg_entry
*
7505 parse_real_register (char *reg_string
, char **end_op
)
7507 char *s
= reg_string
;
7509 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7512 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7513 if (*s
== REGISTER_PREFIX
)
7516 if (is_space_char (*s
))
7520 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7522 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7523 return (const reg_entry
*) NULL
;
7527 /* For naked regs, make sure that we are not dealing with an identifier.
7528 This prevents confusing an identifier like `eax_var' with register
7530 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7531 return (const reg_entry
*) NULL
;
7535 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7537 /* Handle floating point regs, allowing spaces in the (i) part. */
7538 if (r
== i386_regtab
/* %st is first entry of table */)
7540 if (is_space_char (*s
))
7545 if (is_space_char (*s
))
7547 if (*s
>= '0' && *s
<= '7')
7551 if (is_space_char (*s
))
7556 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7561 /* We have "%st(" then garbage. */
7562 return (const reg_entry
*) NULL
;
7566 if (r
== NULL
|| allow_pseudo_reg
)
7569 if (operand_type_all_zero (&r
->reg_type
))
7570 return (const reg_entry
*) NULL
;
7572 if ((r
->reg_type
.bitfield
.reg32
7573 || r
->reg_type
.bitfield
.sreg3
7574 || r
->reg_type
.bitfield
.control
7575 || r
->reg_type
.bitfield
.debug
7576 || r
->reg_type
.bitfield
.test
)
7577 && !cpu_arch_flags
.bitfield
.cpui386
)
7578 return (const reg_entry
*) NULL
;
7580 if (r
->reg_type
.bitfield
.floatreg
7581 && !cpu_arch_flags
.bitfield
.cpu8087
7582 && !cpu_arch_flags
.bitfield
.cpu287
7583 && !cpu_arch_flags
.bitfield
.cpu387
)
7584 return (const reg_entry
*) NULL
;
7586 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7587 return (const reg_entry
*) NULL
;
7589 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7590 return (const reg_entry
*) NULL
;
7592 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7593 return (const reg_entry
*) NULL
;
7595 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7596 if (!allow_index_reg
7597 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7598 return (const reg_entry
*) NULL
;
7600 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7601 || r
->reg_type
.bitfield
.reg64
)
7602 && (!cpu_arch_flags
.bitfield
.cpulm
7603 || !operand_type_equal (&r
->reg_type
, &control
))
7604 && flag_code
!= CODE_64BIT
)
7605 return (const reg_entry
*) NULL
;
7607 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7608 return (const reg_entry
*) NULL
;
7613 /* REG_STRING starts *before* REGISTER_PREFIX. */
7615 static const reg_entry
*
7616 parse_register (char *reg_string
, char **end_op
)
7620 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7621 r
= parse_real_register (reg_string
, end_op
);
7626 char *save
= input_line_pointer
;
7630 input_line_pointer
= reg_string
;
7631 c
= get_symbol_end ();
7632 symbolP
= symbol_find (reg_string
);
7633 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7635 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7637 know (e
->X_op
== O_register
);
7638 know (e
->X_add_number
>= 0
7639 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7640 r
= i386_regtab
+ e
->X_add_number
;
7641 *end_op
= input_line_pointer
;
7643 *input_line_pointer
= c
;
7644 input_line_pointer
= save
;
7650 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7653 char *end
= input_line_pointer
;
7656 r
= parse_register (name
, &input_line_pointer
);
7657 if (r
&& end
<= input_line_pointer
)
7659 *nextcharP
= *input_line_pointer
;
7660 *input_line_pointer
= 0;
7661 e
->X_op
= O_register
;
7662 e
->X_add_number
= r
- i386_regtab
;
7665 input_line_pointer
= end
;
7667 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7671 md_operand (expressionS
*e
)
7676 switch (*input_line_pointer
)
7678 case REGISTER_PREFIX
:
7679 r
= parse_real_register (input_line_pointer
, &end
);
7682 e
->X_op
= O_register
;
7683 e
->X_add_number
= r
- i386_regtab
;
7684 input_line_pointer
= end
;
7689 gas_assert (intel_syntax
);
7690 end
= input_line_pointer
++;
7692 if (*input_line_pointer
== ']')
7694 ++input_line_pointer
;
7695 e
->X_op_symbol
= make_expr_symbol (e
);
7696 e
->X_add_symbol
= NULL
;
7697 e
->X_add_number
= 0;
7703 input_line_pointer
= end
;
7710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7711 const char *md_shortopts
= "kVQ:sqn";
7713 const char *md_shortopts
= "qn";
7716 #define OPTION_32 (OPTION_MD_BASE + 0)
7717 #define OPTION_64 (OPTION_MD_BASE + 1)
7718 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7719 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7720 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7721 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7722 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7723 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7724 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7725 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7726 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7727 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7729 struct option md_longopts
[] =
7731 {"32", no_argument
, NULL
, OPTION_32
},
7732 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7733 || defined (TE_PE) || defined (TE_PEP))
7734 {"64", no_argument
, NULL
, OPTION_64
},
7736 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7737 {"march", required_argument
, NULL
, OPTION_MARCH
},
7738 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7739 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7740 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7741 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7742 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7743 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7744 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7745 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7746 {NULL
, no_argument
, NULL
, 0}
7748 size_t md_longopts_size
= sizeof (md_longopts
);
7751 md_parse_option (int c
, char *arg
)
7759 optimize_align_code
= 0;
7766 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7767 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7768 should be emitted or not. FIXME: Not implemented. */
7772 /* -V: SVR4 argument to print version ID. */
7774 print_version_id ();
7777 /* -k: Ignore for FreeBSD compatibility. */
7782 /* -s: On i386 Solaris, this tells the native assembler to use
7783 .stab instead of .stab.excl. We always use .stab anyhow. */
7786 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7787 || defined (TE_PE) || defined (TE_PEP))
7790 const char **list
, **l
;
7792 list
= bfd_target_list ();
7793 for (l
= list
; *l
!= NULL
; l
++)
7794 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7795 || strcmp (*l
, "coff-x86-64") == 0
7796 || strcmp (*l
, "pe-x86-64") == 0
7797 || strcmp (*l
, "pei-x86-64") == 0)
7799 default_arch
= "x86_64";
7803 as_fatal (_("No compiled in support for x86_64"));
7810 default_arch
= "i386";
7814 #ifdef SVR4_COMMENT_CHARS
7819 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7821 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7825 i386_comment_chars
= n
;
7831 arch
= xstrdup (arg
);
7835 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7836 next
= strchr (arch
, '+');
7839 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7841 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7844 cpu_arch_name
= cpu_arch
[i
].name
;
7845 cpu_sub_arch_name
= NULL
;
7846 cpu_arch_flags
= cpu_arch
[i
].flags
;
7847 cpu_arch_isa
= cpu_arch
[i
].type
;
7848 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7849 if (!cpu_arch_tune_set
)
7851 cpu_arch_tune
= cpu_arch_isa
;
7852 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7856 else if (*cpu_arch
[i
].name
== '.'
7857 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7859 /* ISA entension. */
7860 i386_cpu_flags flags
;
7862 if (strncmp (arch
, "no", 2))
7863 flags
= cpu_flags_or (cpu_arch_flags
,
7866 flags
= cpu_flags_and_not (cpu_arch_flags
,
7868 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7870 if (cpu_sub_arch_name
)
7872 char *name
= cpu_sub_arch_name
;
7873 cpu_sub_arch_name
= concat (name
,
7875 (const char *) NULL
);
7879 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7880 cpu_arch_flags
= flags
;
7886 if (i
>= ARRAY_SIZE (cpu_arch
))
7887 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7891 while (next
!= NULL
);
7896 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7897 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7899 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7901 cpu_arch_tune_set
= 1;
7902 cpu_arch_tune
= cpu_arch
[i
].type
;
7903 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7907 if (i
>= ARRAY_SIZE (cpu_arch
))
7908 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7911 case OPTION_MMNEMONIC
:
7912 if (strcasecmp (arg
, "att") == 0)
7914 else if (strcasecmp (arg
, "intel") == 0)
7917 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7920 case OPTION_MSYNTAX
:
7921 if (strcasecmp (arg
, "att") == 0)
7923 else if (strcasecmp (arg
, "intel") == 0)
7926 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7929 case OPTION_MINDEX_REG
:
7930 allow_index_reg
= 1;
7933 case OPTION_MNAKED_REG
:
7934 allow_naked_reg
= 1;
7937 case OPTION_MOLD_GCC
:
7941 case OPTION_MSSE2AVX
:
7945 case OPTION_MSSE_CHECK
:
7946 if (strcasecmp (arg
, "error") == 0)
7947 sse_check
= sse_check_error
;
7948 else if (strcasecmp (arg
, "warning") == 0)
7949 sse_check
= sse_check_warning
;
7950 else if (strcasecmp (arg
, "none") == 0)
7951 sse_check
= sse_check_none
;
7953 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7963 md_show_usage (stream
)
7966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7967 fprintf (stream
, _("\
7969 -V print assembler version number\n\
7972 fprintf (stream
, _("\
7973 -n Do not optimize code alignment\n\
7974 -q quieten some warnings\n"));
7975 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7976 fprintf (stream
, _("\
7979 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7980 || defined (TE_PE) || defined (TE_PEP))
7981 fprintf (stream
, _("\
7982 --32/--64 generate 32bit/64bit code\n"));
7984 #ifdef SVR4_COMMENT_CHARS
7985 fprintf (stream
, _("\
7986 --divide do not treat `/' as a comment character\n"));
7988 fprintf (stream
, _("\
7989 --divide ignored\n"));
7991 fprintf (stream
, _("\
7992 -march=CPU[,+EXTENSION...]\n\
7993 generate code for CPU and EXTENSION, CPU is one of:\n\
7994 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7995 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7996 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
7997 amdfam10, generic32, generic64\n\
7998 EXTENSION is combination of:\n\
7999 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8000 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8001 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8002 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8003 svme, abm, padlock, fma4\n"));
8004 fprintf (stream
, _("\
8005 -mtune=CPU optimize for CPU, CPU is one of:\n\
8006 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8007 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8008 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8009 amdfam10, generic32, generic64\n"));
8010 fprintf (stream
, _("\
8011 -msse2avx encode SSE instructions with VEX prefix\n"));
8012 fprintf (stream
, _("\
8013 -msse-check=[none|error|warning]\n\
8014 check SSE instructions\n"));
8015 fprintf (stream
, _("\
8016 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8017 fprintf (stream
, _("\
8018 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8019 fprintf (stream
, _("\
8020 -mindex-reg support pseudo index registers\n"));
8021 fprintf (stream
, _("\
8022 -mnaked-reg don't require `%%' prefix for registers\n"));
8023 fprintf (stream
, _("\
8024 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8027 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8028 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8029 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8031 /* Pick the target format to use. */
8034 i386_target_format (void)
8036 if (!strcmp (default_arch
, "x86_64"))
8038 set_code_flag (CODE_64BIT
);
8039 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8041 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8042 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8043 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8044 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8045 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8046 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8047 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8048 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8049 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8050 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8051 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8053 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8055 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8056 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8057 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8058 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8059 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8060 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8061 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8062 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8063 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8064 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8067 else if (!strcmp (default_arch
, "i386"))
8069 set_code_flag (CODE_32BIT
);
8070 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8072 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8073 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8074 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8076 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8078 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8079 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8080 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8084 as_fatal (_("Unknown architecture"));
8085 switch (OUTPUT_FLAVOR
)
8087 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8088 case bfd_target_aout_flavour
:
8089 return AOUT_TARGET_FORMAT
;
8091 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8092 # if defined (TE_PE) || defined (TE_PEP)
8093 case bfd_target_coff_flavour
:
8094 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8095 # elif defined (TE_GO32)
8096 case bfd_target_coff_flavour
:
8099 case bfd_target_coff_flavour
:
8103 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8104 case bfd_target_elf_flavour
:
8106 if (flag_code
== CODE_64BIT
)
8109 use_rela_relocations
= 1;
8111 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8113 if (flag_code
!= CODE_64BIT
)
8114 as_fatal (_("Intel L1OM is 64bit only"));
8115 return ELF_TARGET_L1OM_FORMAT
;
8118 return (flag_code
== CODE_64BIT
8119 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8122 #if defined (OBJ_MACH_O)
8123 case bfd_target_mach_o_flavour
:
8124 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8132 #endif /* OBJ_MAYBE_ more than one */
8134 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8136 i386_elf_emit_arch_note (void)
8138 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8141 asection
*seg
= now_seg
;
8142 subsegT subseg
= now_subseg
;
8143 Elf_Internal_Note i_note
;
8144 Elf_External_Note e_note
;
8145 asection
*note_secp
;
8148 /* Create the .note section. */
8149 note_secp
= subseg_new (".note", 0);
8150 bfd_set_section_flags (stdoutput
,
8152 SEC_HAS_CONTENTS
| SEC_READONLY
);
8154 /* Process the arch string. */
8155 len
= strlen (cpu_arch_name
);
8157 i_note
.namesz
= len
+ 1;
8159 i_note
.type
= NT_ARCH
;
8160 p
= frag_more (sizeof (e_note
.namesz
));
8161 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8162 p
= frag_more (sizeof (e_note
.descsz
));
8163 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8164 p
= frag_more (sizeof (e_note
.type
));
8165 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8166 p
= frag_more (len
+ 1);
8167 strcpy (p
, cpu_arch_name
);
8169 frag_align (2, 0, 0);
8171 subseg_set (seg
, subseg
);
8177 md_undefined_symbol (name
)
8180 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8181 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8182 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8183 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8187 if (symbol_find (name
))
8188 as_bad (_("GOT already in symbol table"));
8189 GOT_symbol
= symbol_new (name
, undefined_section
,
8190 (valueT
) 0, &zero_address_frag
);
8197 /* Round up a section size to the appropriate boundary. */
8200 md_section_align (segment
, size
)
8201 segT segment ATTRIBUTE_UNUSED
;
8204 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8205 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8207 /* For a.out, force the section size to be aligned. If we don't do
8208 this, BFD will align it for us, but it will not write out the
8209 final bytes of the section. This may be a bug in BFD, but it is
8210 easier to fix it here since that is how the other a.out targets
8214 align
= bfd_get_section_alignment (stdoutput
, segment
);
8215 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8222 /* On the i386, PC-relative offsets are relative to the start of the
8223 next instruction. That is, the address of the offset, plus its
8224 size, since the offset is always the last part of the insn. */
8227 md_pcrel_from (fixS
*fixP
)
8229 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8235 s_bss (int ignore ATTRIBUTE_UNUSED
)
8239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8241 obj_elf_section_change_hook ();
8243 temp
= get_absolute_expression ();
8244 subseg_set (bss_section
, (subsegT
) temp
);
8245 demand_empty_rest_of_line ();
8251 i386_validate_fix (fixS
*fixp
)
8253 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8255 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8259 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8264 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8266 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8273 tc_gen_reloc (section
, fixp
)
8274 asection
*section ATTRIBUTE_UNUSED
;
8278 bfd_reloc_code_real_type code
;
8280 switch (fixp
->fx_r_type
)
8282 case BFD_RELOC_X86_64_PLT32
:
8283 case BFD_RELOC_X86_64_GOT32
:
8284 case BFD_RELOC_X86_64_GOTPCREL
:
8285 case BFD_RELOC_386_PLT32
:
8286 case BFD_RELOC_386_GOT32
:
8287 case BFD_RELOC_386_GOTOFF
:
8288 case BFD_RELOC_386_GOTPC
:
8289 case BFD_RELOC_386_TLS_GD
:
8290 case BFD_RELOC_386_TLS_LDM
:
8291 case BFD_RELOC_386_TLS_LDO_32
:
8292 case BFD_RELOC_386_TLS_IE_32
:
8293 case BFD_RELOC_386_TLS_IE
:
8294 case BFD_RELOC_386_TLS_GOTIE
:
8295 case BFD_RELOC_386_TLS_LE_32
:
8296 case BFD_RELOC_386_TLS_LE
:
8297 case BFD_RELOC_386_TLS_GOTDESC
:
8298 case BFD_RELOC_386_TLS_DESC_CALL
:
8299 case BFD_RELOC_X86_64_TLSGD
:
8300 case BFD_RELOC_X86_64_TLSLD
:
8301 case BFD_RELOC_X86_64_DTPOFF32
:
8302 case BFD_RELOC_X86_64_DTPOFF64
:
8303 case BFD_RELOC_X86_64_GOTTPOFF
:
8304 case BFD_RELOC_X86_64_TPOFF32
:
8305 case BFD_RELOC_X86_64_TPOFF64
:
8306 case BFD_RELOC_X86_64_GOTOFF64
:
8307 case BFD_RELOC_X86_64_GOTPC32
:
8308 case BFD_RELOC_X86_64_GOT64
:
8309 case BFD_RELOC_X86_64_GOTPCREL64
:
8310 case BFD_RELOC_X86_64_GOTPC64
:
8311 case BFD_RELOC_X86_64_GOTPLT64
:
8312 case BFD_RELOC_X86_64_PLTOFF64
:
8313 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8314 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8316 case BFD_RELOC_VTABLE_ENTRY
:
8317 case BFD_RELOC_VTABLE_INHERIT
:
8319 case BFD_RELOC_32_SECREL
:
8321 code
= fixp
->fx_r_type
;
8323 case BFD_RELOC_X86_64_32S
:
8324 if (!fixp
->fx_pcrel
)
8326 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8327 code
= fixp
->fx_r_type
;
8333 switch (fixp
->fx_size
)
8336 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8337 _("can not do %d byte pc-relative relocation"),
8339 code
= BFD_RELOC_32_PCREL
;
8341 case 1: code
= BFD_RELOC_8_PCREL
; break;
8342 case 2: code
= BFD_RELOC_16_PCREL
; break;
8343 case 4: code
= BFD_RELOC_32_PCREL
; break;
8345 case 8: code
= BFD_RELOC_64_PCREL
; break;
8351 switch (fixp
->fx_size
)
8354 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8355 _("can not do %d byte relocation"),
8357 code
= BFD_RELOC_32
;
8359 case 1: code
= BFD_RELOC_8
; break;
8360 case 2: code
= BFD_RELOC_16
; break;
8361 case 4: code
= BFD_RELOC_32
; break;
8363 case 8: code
= BFD_RELOC_64
; break;
8370 if ((code
== BFD_RELOC_32
8371 || code
== BFD_RELOC_32_PCREL
8372 || code
== BFD_RELOC_X86_64_32S
)
8374 && fixp
->fx_addsy
== GOT_symbol
)
8377 code
= BFD_RELOC_386_GOTPC
;
8379 code
= BFD_RELOC_X86_64_GOTPC32
;
8381 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8383 && fixp
->fx_addsy
== GOT_symbol
)
8385 code
= BFD_RELOC_X86_64_GOTPC64
;
8388 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8389 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8390 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8392 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8394 if (!use_rela_relocations
)
8396 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8397 vtable entry to be used in the relocation's section offset. */
8398 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8399 rel
->address
= fixp
->fx_offset
;
8400 #if defined (OBJ_COFF) && defined (TE_PE)
8401 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8402 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8407 /* Use the rela in 64bit mode. */
8410 if (!fixp
->fx_pcrel
)
8411 rel
->addend
= fixp
->fx_offset
;
8415 case BFD_RELOC_X86_64_PLT32
:
8416 case BFD_RELOC_X86_64_GOT32
:
8417 case BFD_RELOC_X86_64_GOTPCREL
:
8418 case BFD_RELOC_X86_64_TLSGD
:
8419 case BFD_RELOC_X86_64_TLSLD
:
8420 case BFD_RELOC_X86_64_GOTTPOFF
:
8421 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8422 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8423 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8426 rel
->addend
= (section
->vma
8428 + fixp
->fx_addnumber
8429 + md_pcrel_from (fixp
));
8434 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8435 if (rel
->howto
== NULL
)
8437 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8438 _("cannot represent relocation type %s"),
8439 bfd_get_reloc_code_name (code
));
8440 /* Set howto to a garbage value so that we can keep going. */
8441 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8442 gas_assert (rel
->howto
!= NULL
);
8448 #include "tc-i386-intel.c"
8451 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8453 int saved_naked_reg
;
8454 char saved_register_dot
;
8456 saved_naked_reg
= allow_naked_reg
;
8457 allow_naked_reg
= 1;
8458 saved_register_dot
= register_chars
['.'];
8459 register_chars
['.'] = '.';
8460 allow_pseudo_reg
= 1;
8461 expression_and_evaluate (exp
);
8462 allow_pseudo_reg
= 0;
8463 register_chars
['.'] = saved_register_dot
;
8464 allow_naked_reg
= saved_naked_reg
;
8466 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8468 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8470 exp
->X_op
= O_constant
;
8471 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8472 .dw2_regnum
[flag_code
>> 1];
8475 exp
->X_op
= O_illegal
;
8480 tc_x86_frame_initial_instructions (void)
8482 static unsigned int sp_regno
[2];
8484 if (!sp_regno
[flag_code
>> 1])
8486 char *saved_input
= input_line_pointer
;
8487 char sp
[][4] = {"esp", "rsp"};
8490 input_line_pointer
= sp
[flag_code
>> 1];
8491 tc_x86_parse_to_dw2regnum (&exp
);
8492 gas_assert (exp
.X_op
== O_constant
);
8493 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8494 input_line_pointer
= saved_input
;
8497 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8498 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8502 i386_elf_section_type (const char *str
, size_t len
)
8504 if (flag_code
== CODE_64BIT
8505 && len
== sizeof ("unwind") - 1
8506 && strncmp (str
, "unwind", 6) == 0)
8507 return SHT_X86_64_UNWIND
;
8514 i386_solaris_fix_up_eh_frame (segT sec
)
8516 if (flag_code
== CODE_64BIT
)
8517 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8523 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8527 expr
.X_op
= O_secrel
;
8528 expr
.X_add_symbol
= symbol
;
8529 expr
.X_add_number
= 0;
8530 emit_expr (&expr
, size
);
8534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8535 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8538 x86_64_section_letter (int letter
, char **ptr_msg
)
8540 if (flag_code
== CODE_64BIT
)
8543 return SHF_X86_64_LARGE
;
8545 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8548 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8553 x86_64_section_word (char *str
, size_t len
)
8555 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8556 return SHF_X86_64_LARGE
;
8562 handle_large_common (int small ATTRIBUTE_UNUSED
)
8564 if (flag_code
!= CODE_64BIT
)
8566 s_comm_internal (0, elf_common_parse
);
8567 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8571 static segT lbss_section
;
8572 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8573 asection
*saved_bss_section
= bss_section
;
8575 if (lbss_section
== NULL
)
8577 flagword applicable
;
8579 subsegT subseg
= now_subseg
;
8581 /* The .lbss section is for local .largecomm symbols. */
8582 lbss_section
= subseg_new (".lbss", 0);
8583 applicable
= bfd_applicable_section_flags (stdoutput
);
8584 bfd_set_section_flags (stdoutput
, lbss_section
,
8585 applicable
& SEC_ALLOC
);
8586 seg_info (lbss_section
)->bss
= 1;
8588 subseg_set (seg
, subseg
);
8591 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8592 bss_section
= lbss_section
;
8594 s_comm_internal (0, elf_common_parse
);
8596 elf_com_section_ptr
= saved_com_section_ptr
;
8597 bss_section
= saved_bss_section
;
8600 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */