1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS
*GOT_symbol
;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
432 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
434 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
435 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
436 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
437 {".3dnow", CpuMMX
|Cpu3dnow
},
438 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
439 {".padlock", CpuPadLock
},
440 {".pacifica", CpuSVME
},
445 const pseudo_typeS md_pseudo_table
[] =
447 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
448 {"align", s_align_bytes
, 0},
450 {"align", s_align_ptwo
, 0},
452 {"arch", set_cpu_arch
, 0},
456 {"ffloat", float_cons
, 'f'},
457 {"dfloat", float_cons
, 'd'},
458 {"tfloat", float_cons
, 'x'},
460 {"noopt", s_ignore
, 0},
461 {"optim", s_ignore
, 0},
462 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
463 {"code16", set_code_flag
, CODE_16BIT
},
464 {"code32", set_code_flag
, CODE_32BIT
},
465 {"code64", set_code_flag
, CODE_64BIT
},
466 {"intel_syntax", set_intel_syntax
, 1},
467 {"att_syntax", set_intel_syntax
, 0},
468 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
469 {"loc", dwarf2_directive_loc
, 0},
471 {"secrel32", pe_directive_secrel
, 0},
476 /* For interface with expression (). */
477 extern char *input_line_pointer
;
479 /* Hash table for instruction mnemonic lookup. */
480 static struct hash_control
*op_hash
;
482 /* Hash table for register lookup. */
483 static struct hash_control
*reg_hash
;
486 i386_align_code (fragP
, count
)
490 /* Various efficient no-op patterns for aligning code labels.
491 Note: Don't try to assemble the instructions in the comments.
492 0L and 0w are not legal. */
493 static const char f32_1
[] =
495 static const char f32_2
[] =
496 {0x89,0xf6}; /* movl %esi,%esi */
497 static const char f32_3
[] =
498 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
499 static const char f32_4
[] =
500 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
501 static const char f32_5
[] =
503 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
504 static const char f32_6
[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
506 static const char f32_7
[] =
507 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
508 static const char f32_8
[] =
510 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
511 static const char f32_9
[] =
512 {0x89,0xf6, /* movl %esi,%esi */
513 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
514 static const char f32_10
[] =
515 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
516 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
517 static const char f32_11
[] =
518 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_12
[] =
521 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
522 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
523 static const char f32_13
[] =
524 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_14
[] =
527 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_15
[] =
530 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
531 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
532 static const char f16_3
[] =
533 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
534 static const char f16_4
[] =
535 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
536 static const char f16_5
[] =
538 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
539 static const char f16_6
[] =
540 {0x89,0xf6, /* mov %si,%si */
541 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
542 static const char f16_7
[] =
543 {0x8d,0x74,0x00, /* lea 0(%si),%si */
544 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
545 static const char f16_8
[] =
546 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char *const f32_patt
[] = {
549 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
550 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
552 static const char *const f16_patt
[] = {
553 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
554 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
557 if (count
<= 0 || count
> 15)
560 /* The recommended way to pad 64bit code is to use NOPs preceded by
561 maximally four 0x66 prefixes. Balance the size of nops. */
562 if (flag_code
== CODE_64BIT
)
565 int nnops
= (count
+ 3) / 4;
566 int len
= count
/ nnops
;
567 int remains
= count
- nnops
* len
;
570 for (i
= 0; i
< remains
; i
++)
572 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
573 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
576 for (; i
< nnops
; i
++)
578 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
579 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
584 if (flag_code
== CODE_16BIT
)
586 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
587 f16_patt
[count
- 1], count
);
589 /* Adjust jump offset. */
590 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
593 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
594 f32_patt
[count
- 1], count
);
595 fragP
->fr_var
= count
;
598 static INLINE
unsigned int
599 mode_from_disp_size (t
)
602 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
606 fits_in_signed_byte (num
)
609 return (num
>= -128) && (num
<= 127);
613 fits_in_unsigned_byte (num
)
616 return (num
& 0xff) == num
;
620 fits_in_unsigned_word (num
)
623 return (num
& 0xffff) == num
;
627 fits_in_signed_word (num
)
630 return (-32768 <= num
) && (num
<= 32767);
633 fits_in_signed_long (num
)
634 offsetT num ATTRIBUTE_UNUSED
;
639 return (!(((offsetT
) -1 << 31) & num
)
640 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
642 } /* fits_in_signed_long() */
644 fits_in_unsigned_long (num
)
645 offsetT num ATTRIBUTE_UNUSED
;
650 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
652 } /* fits_in_unsigned_long() */
655 smallest_imm_type (num
)
658 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
660 /* This code is disabled on the 486 because all the Imm1 forms
661 in the opcode table are slower on the i486. They're the
662 versions with the implicitly specified single-position
663 displacement, which has another syntax if you really want to
666 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
668 return (fits_in_signed_byte (num
)
669 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_unsigned_byte (num
)
671 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
672 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
673 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
674 : fits_in_signed_long (num
)
675 ? (Imm32
| Imm32S
| Imm64
)
676 : fits_in_unsigned_long (num
)
682 offset_in_range (val
, size
)
690 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
691 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
692 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
694 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
699 /* If BFD64, sign extend val. */
700 if (!use_rela_relocations
)
701 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
702 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
704 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
706 char buf1
[40], buf2
[40];
708 sprint_value (buf1
, val
);
709 sprint_value (buf2
, val
& mask
);
710 as_warn (_("%s shortened to %s"), buf1
, buf2
);
715 /* Returns 0 if attempting to add a prefix where one from the same
716 class already exists, 1 if non rep/repne added, 2 if rep/repne
725 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
726 && flag_code
== CODE_64BIT
)
734 case CS_PREFIX_OPCODE
:
735 case DS_PREFIX_OPCODE
:
736 case ES_PREFIX_OPCODE
:
737 case FS_PREFIX_OPCODE
:
738 case GS_PREFIX_OPCODE
:
739 case SS_PREFIX_OPCODE
:
743 case REPNE_PREFIX_OPCODE
:
744 case REPE_PREFIX_OPCODE
:
747 case LOCK_PREFIX_OPCODE
:
755 case ADDR_PREFIX_OPCODE
:
759 case DATA_PREFIX_OPCODE
:
764 if (i
.prefix
[q
] != 0)
766 as_bad (_("same type of prefix used twice"));
771 i
.prefix
[q
] = prefix
;
776 set_code_flag (value
)
780 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
781 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
782 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
784 as_bad (_("64bit mode not supported on this CPU."));
786 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
788 as_bad (_("32bit mode not supported on this CPU."));
794 set_16bit_gcc_code_flag (new_code_flag
)
797 flag_code
= new_code_flag
;
798 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
799 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
800 stackop_size
= LONG_MNEM_SUFFIX
;
804 set_intel_syntax (syntax_flag
)
807 /* Find out if register prefixing is specified. */
808 int ask_naked_reg
= 0;
811 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
813 char *string
= input_line_pointer
;
814 int e
= get_symbol_end ();
816 if (strcmp (string
, "prefix") == 0)
818 else if (strcmp (string
, "noprefix") == 0)
821 as_bad (_("bad argument to syntax directive."));
822 *input_line_pointer
= e
;
824 demand_empty_rest_of_line ();
826 intel_syntax
= syntax_flag
;
828 if (ask_naked_reg
== 0)
829 allow_naked_reg
= (intel_syntax
830 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
832 allow_naked_reg
= (ask_naked_reg
< 0);
834 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
835 identifier_chars
['$'] = intel_syntax
? '$' : 0;
840 int dummy ATTRIBUTE_UNUSED
;
844 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
846 char *string
= input_line_pointer
;
847 int e
= get_symbol_end ();
850 for (i
= 0; cpu_arch
[i
].name
; i
++)
852 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
856 cpu_arch_name
= cpu_arch
[i
].name
;
857 cpu_sub_arch_name
= NULL
;
858 cpu_arch_flags
= (cpu_arch
[i
].flags
859 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
862 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
864 cpu_sub_arch_name
= cpu_arch
[i
].name
;
865 cpu_arch_flags
|= cpu_arch
[i
].flags
;
867 *input_line_pointer
= e
;
868 demand_empty_rest_of_line ();
872 if (!cpu_arch
[i
].name
)
873 as_bad (_("no such architecture: `%s'"), string
);
875 *input_line_pointer
= e
;
878 as_bad (_("missing cpu architecture"));
880 no_cond_jump_promotion
= 0;
881 if (*input_line_pointer
== ','
882 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
884 char *string
= ++input_line_pointer
;
885 int e
= get_symbol_end ();
887 if (strcmp (string
, "nojumps") == 0)
888 no_cond_jump_promotion
= 1;
889 else if (strcmp (string
, "jumps") == 0)
892 as_bad (_("no such architecture modifier: `%s'"), string
);
894 *input_line_pointer
= e
;
897 demand_empty_rest_of_line ();
903 if (!strcmp (default_arch
, "x86_64"))
904 return bfd_mach_x86_64
;
905 else if (!strcmp (default_arch
, "i386"))
906 return bfd_mach_i386_i386
;
908 as_fatal (_("Unknown architecture"));
914 const char *hash_err
;
916 /* Initialize op_hash hash table. */
917 op_hash
= hash_new ();
920 const template *optab
;
921 templates
*core_optab
;
923 /* Setup for loop. */
925 core_optab
= (templates
*) xmalloc (sizeof (templates
));
926 core_optab
->start
= optab
;
931 if (optab
->name
== NULL
932 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
934 /* different name --> ship out current template list;
935 add to hash table; & begin anew. */
936 core_optab
->end
= optab
;
937 hash_err
= hash_insert (op_hash
,
942 as_fatal (_("Internal Error: Can't hash %s: %s"),
946 if (optab
->name
== NULL
)
948 core_optab
= (templates
*) xmalloc (sizeof (templates
));
949 core_optab
->start
= optab
;
954 /* Initialize reg_hash hash table. */
955 reg_hash
= hash_new ();
957 const reg_entry
*regtab
;
959 for (regtab
= i386_regtab
;
960 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
963 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
965 as_fatal (_("Internal Error: Can't hash %s: %s"),
971 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
976 for (c
= 0; c
< 256; c
++)
981 mnemonic_chars
[c
] = c
;
982 register_chars
[c
] = c
;
983 operand_chars
[c
] = c
;
985 else if (ISLOWER (c
))
987 mnemonic_chars
[c
] = c
;
988 register_chars
[c
] = c
;
989 operand_chars
[c
] = c
;
991 else if (ISUPPER (c
))
993 mnemonic_chars
[c
] = TOLOWER (c
);
994 register_chars
[c
] = mnemonic_chars
[c
];
995 operand_chars
[c
] = c
;
998 if (ISALPHA (c
) || ISDIGIT (c
))
999 identifier_chars
[c
] = c
;
1002 identifier_chars
[c
] = c
;
1003 operand_chars
[c
] = c
;
1008 identifier_chars
['@'] = '@';
1011 identifier_chars
['?'] = '?';
1012 operand_chars
['?'] = '?';
1014 digit_chars
['-'] = '-';
1015 mnemonic_chars
['-'] = '-';
1016 identifier_chars
['_'] = '_';
1017 identifier_chars
['.'] = '.';
1019 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1020 operand_chars
[(unsigned char) *p
] = *p
;
1023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1024 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1026 record_alignment (text_section
, 2);
1027 record_alignment (data_section
, 2);
1028 record_alignment (bss_section
, 2);
1032 if (flag_code
== CODE_64BIT
)
1034 x86_dwarf2_return_column
= 16;
1035 x86_cie_data_alignment
= -8;
1039 x86_dwarf2_return_column
= 8;
1040 x86_cie_data_alignment
= -4;
1045 i386_print_statistics (file
)
1048 hash_print_statistics (file
, "i386 opcode", op_hash
);
1049 hash_print_statistics (file
, "i386 register", reg_hash
);
1054 /* Debugging routines for md_assemble. */
1055 static void pi
PARAMS ((char *, i386_insn
*));
1056 static void pte
PARAMS ((template *));
1057 static void pt
PARAMS ((unsigned int));
1058 static void pe
PARAMS ((expressionS
*));
1059 static void ps
PARAMS ((symbolS
*));
1068 fprintf (stdout
, "%s: template ", line
);
1070 fprintf (stdout
, " address: base %s index %s scale %x\n",
1071 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1072 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1073 x
->log2_scale_factor
);
1074 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1075 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1076 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1077 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1078 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1079 (x
->rex
& REX_MODE64
) != 0,
1080 (x
->rex
& REX_EXTX
) != 0,
1081 (x
->rex
& REX_EXTY
) != 0,
1082 (x
->rex
& REX_EXTZ
) != 0);
1083 for (i
= 0; i
< x
->operands
; i
++)
1085 fprintf (stdout
, " #%d: ", i
+ 1);
1087 fprintf (stdout
, "\n");
1089 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1090 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1091 if (x
->types
[i
] & Imm
)
1093 if (x
->types
[i
] & Disp
)
1094 pe (x
->op
[i
].disps
);
1103 fprintf (stdout
, " %d operands ", t
->operands
);
1104 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1105 if (t
->extension_opcode
!= None
)
1106 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1107 if (t
->opcode_modifier
& D
)
1108 fprintf (stdout
, "D");
1109 if (t
->opcode_modifier
& W
)
1110 fprintf (stdout
, "W");
1111 fprintf (stdout
, "\n");
1112 for (i
= 0; i
< t
->operands
; i
++)
1114 fprintf (stdout
, " #%d type ", i
+ 1);
1115 pt (t
->operand_types
[i
]);
1116 fprintf (stdout
, "\n");
1124 fprintf (stdout
, " operation %d\n", e
->X_op
);
1125 fprintf (stdout
, " add_number %ld (%lx)\n",
1126 (long) e
->X_add_number
, (long) e
->X_add_number
);
1127 if (e
->X_add_symbol
)
1129 fprintf (stdout
, " add_symbol ");
1130 ps (e
->X_add_symbol
);
1131 fprintf (stdout
, "\n");
1135 fprintf (stdout
, " op_symbol ");
1136 ps (e
->X_op_symbol
);
1137 fprintf (stdout
, "\n");
1145 fprintf (stdout
, "%s type %s%s",
1147 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1148 segment_name (S_GET_SEGMENT (s
)));
1157 static const type_names
[] =
1170 { BaseIndex
, "BaseIndex" },
1174 { Disp32S
, "d32s" },
1176 { InOutPortReg
, "InOutPortReg" },
1177 { ShiftCount
, "ShiftCount" },
1178 { Control
, "control reg" },
1179 { Test
, "test reg" },
1180 { Debug
, "debug reg" },
1181 { FloatReg
, "FReg" },
1182 { FloatAcc
, "FAcc" },
1186 { JumpAbsolute
, "Jump Absolute" },
1197 const struct type_name
*ty
;
1199 for (ty
= type_names
; ty
->mask
; ty
++)
1201 fprintf (stdout
, "%s, ", ty
->tname
);
1205 #endif /* DEBUG386 */
1207 static bfd_reloc_code_real_type reloc
1208 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1210 static bfd_reloc_code_real_type
1211 reloc (size
, pcrel
, sign
, other
)
1215 bfd_reloc_code_real_type other
;
1217 if (other
!= NO_RELOC
)
1223 as_bad (_("There are no unsigned pc-relative relocations"));
1226 case 1: return BFD_RELOC_8_PCREL
;
1227 case 2: return BFD_RELOC_16_PCREL
;
1228 case 4: return BFD_RELOC_32_PCREL
;
1229 case 8: return BFD_RELOC_64_PCREL
;
1231 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1238 case 4: return BFD_RELOC_X86_64_32S
;
1243 case 1: return BFD_RELOC_8
;
1244 case 2: return BFD_RELOC_16
;
1245 case 4: return BFD_RELOC_32
;
1246 case 8: return BFD_RELOC_64
;
1248 as_bad (_("can not do %s %d byte relocation"),
1249 sign
? "signed" : "unsigned", size
);
1253 return BFD_RELOC_NONE
;
1256 /* Here we decide which fixups can be adjusted to make them relative to
1257 the beginning of the section instead of the symbol. Basically we need
1258 to make sure that the dynamic relocations are done correctly, so in
1259 some cases we force the original symbol to be used. */
1262 tc_i386_fix_adjustable (fixP
)
1263 fixS
*fixP ATTRIBUTE_UNUSED
;
1265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1266 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1269 /* Don't adjust pc-relative references to merge sections in 64-bit
1271 if (use_rela_relocations
1272 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1276 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1277 and changed later by validate_fix. */
1278 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1279 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1282 /* adjust_reloc_syms doesn't know about the GOT. */
1283 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1284 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1285 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1291 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1292 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1293 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1305 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1306 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1312 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1315 intel_float_operand (mnemonic
)
1316 const char *mnemonic
;
1318 /* Note that the value returned is meaningful only for opcodes with (memory)
1319 operands, hence the code here is free to improperly handle opcodes that
1320 have no operands (for better performance and smaller code). */
1322 if (mnemonic
[0] != 'f')
1323 return 0; /* non-math */
1325 switch (mnemonic
[1])
1327 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1328 the fs segment override prefix not currently handled because no
1329 call path can make opcodes without operands get here */
1331 return 2 /* integer op */;
1333 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1334 return 3; /* fldcw/fldenv */
1337 if (mnemonic
[2] != 'o' /* fnop */)
1338 return 3; /* non-waiting control op */
1341 if (mnemonic
[2] == 's')
1342 return 3; /* frstor/frstpm */
1345 if (mnemonic
[2] == 'a')
1346 return 3; /* fsave */
1347 if (mnemonic
[2] == 't')
1349 switch (mnemonic
[3])
1351 case 'c': /* fstcw */
1352 case 'd': /* fstdw */
1353 case 'e': /* fstenv */
1354 case 's': /* fsts[gw] */
1360 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1361 return 0; /* fxsave/fxrstor are not really math ops */
1368 /* This is the guts of the machine-dependent assembler. LINE points to a
1369 machine dependent instruction. This function is supposed to emit
1370 the frags/bytes it assembles to. */
1377 char mnemonic
[MAX_MNEM_SIZE
];
1379 /* Initialize globals. */
1380 memset (&i
, '\0', sizeof (i
));
1381 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1382 i
.reloc
[j
] = NO_RELOC
;
1383 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1384 memset (im_expressions
, '\0', sizeof (im_expressions
));
1385 save_stack_p
= save_stack
;
1387 /* First parse an instruction mnemonic & call i386_operand for the operands.
1388 We assume that the scrubber has arranged it so that line[0] is the valid
1389 start of a (possibly prefixed) mnemonic. */
1391 line
= parse_insn (line
, mnemonic
);
1395 line
= parse_operands (line
, mnemonic
);
1399 /* Now we've parsed the mnemonic into a set of templates, and have the
1400 operands at hand. */
1402 /* All intel opcodes have reversed operands except for "bound" and
1403 "enter". We also don't reverse intersegment "jmp" and "call"
1404 instructions with 2 immediate operands so that the immediate segment
1405 precedes the offset, as it does when in AT&T mode. "enter" and the
1406 intersegment "jmp" and "call" instructions are the only ones that
1407 have two immediate operands. */
1408 if (intel_syntax
&& i
.operands
> 1
1409 && (strcmp (mnemonic
, "bound") != 0)
1410 && (strcmp (mnemonic
, "invlpga") != 0)
1411 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1417 /* Don't optimize displacement for movabs since it only takes 64bit
1420 && (flag_code
!= CODE_64BIT
1421 || strcmp (mnemonic
, "movabs") != 0))
1424 /* Next, we find a template that matches the given insn,
1425 making sure the overlap of the given operands types is consistent
1426 with the template operand types. */
1428 if (!match_template ())
1433 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1435 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1436 i
.tm
.base_opcode
^= FloatR
;
1438 /* Zap movzx and movsx suffix. The suffix may have been set from
1439 "word ptr" or "byte ptr" on the source operand, but we'll use
1440 the suffix later to choose the destination register. */
1441 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1443 if (i
.reg_operands
< 2
1445 && (~i
.tm
.opcode_modifier
1452 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1458 if (i
.tm
.opcode_modifier
& FWait
)
1459 if (!add_prefix (FWAIT_OPCODE
))
1462 /* Check string instruction segment overrides. */
1463 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1465 if (!check_string ())
1469 if (!process_suffix ())
1472 /* Make still unresolved immediate matches conform to size of immediate
1473 given in i.suffix. */
1474 if (!finalize_imm ())
1477 if (i
.types
[0] & Imm1
)
1478 i
.imm_operands
= 0; /* kludge for shift insns. */
1479 if (i
.types
[0] & ImplicitRegister
)
1481 if (i
.types
[1] & ImplicitRegister
)
1483 if (i
.types
[2] & ImplicitRegister
)
1486 if (i
.tm
.opcode_modifier
& ImmExt
)
1490 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1492 /* These Intel Prescott New Instructions have the fixed
1493 operands with an opcode suffix which is coded in the same
1494 place as an 8-bit immediate field would be. Here we check
1495 those operands and remove them afterwards. */
1498 for (x
= 0; x
< i
.operands
; x
++)
1499 if (i
.op
[x
].regs
->reg_num
!= x
)
1500 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1501 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1505 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1506 opcode suffix which is coded in the same place as an 8-bit
1507 immediate field would be. Here we fake an 8-bit immediate
1508 operand from the opcode suffix stored in tm.extension_opcode. */
1510 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1512 exp
= &im_expressions
[i
.imm_operands
++];
1513 i
.op
[i
.operands
].imms
= exp
;
1514 i
.types
[i
.operands
++] = Imm8
;
1515 exp
->X_op
= O_constant
;
1516 exp
->X_add_number
= i
.tm
.extension_opcode
;
1517 i
.tm
.extension_opcode
= None
;
1520 /* For insns with operands there are more diddles to do to the opcode. */
1523 if (!process_operands ())
1526 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1528 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1529 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1532 /* Handle conversion of 'int $3' --> special int3 insn. */
1533 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1535 i
.tm
.base_opcode
= INT3_OPCODE
;
1539 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1540 && i
.op
[0].disps
->X_op
== O_constant
)
1542 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1543 the absolute address given by the constant. Since ix86 jumps and
1544 calls are pc relative, we need to generate a reloc. */
1545 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1546 i
.op
[0].disps
->X_op
= O_symbol
;
1549 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1550 i
.rex
|= REX_MODE64
;
1552 /* For 8 bit registers we need an empty rex prefix. Also if the
1553 instruction already has a prefix, we need to convert old
1554 registers to new ones. */
1556 if (((i
.types
[0] & Reg8
) != 0
1557 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1558 || ((i
.types
[1] & Reg8
) != 0
1559 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1560 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1565 i
.rex
|= REX_OPCODE
;
1566 for (x
= 0; x
< 2; x
++)
1568 /* Look for 8 bit operand that uses old registers. */
1569 if ((i
.types
[x
] & Reg8
) != 0
1570 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1572 /* In case it is "hi" register, give up. */
1573 if (i
.op
[x
].regs
->reg_num
> 3)
1574 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1575 i
.op
[x
].regs
->reg_name
);
1577 /* Otherwise it is equivalent to the extended register.
1578 Since the encoding doesn't change this is merely
1579 cosmetic cleanup for debug output. */
1581 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1587 add_prefix (REX_OPCODE
| i
.rex
);
1589 /* We are ready to output the insn. */
1594 parse_insn (line
, mnemonic
)
1599 char *token_start
= l
;
1604 /* Non-zero if we found a prefix only acceptable with string insns. */
1605 const char *expecting_string_instruction
= NULL
;
1610 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1613 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1615 as_bad (_("no such instruction: `%s'"), token_start
);
1620 if (!is_space_char (*l
)
1621 && *l
!= END_OF_INSN
1623 || (*l
!= PREFIX_SEPARATOR
1626 as_bad (_("invalid character %s in mnemonic"),
1627 output_invalid (*l
));
1630 if (token_start
== l
)
1632 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1633 as_bad (_("expecting prefix; got nothing"));
1635 as_bad (_("expecting mnemonic; got nothing"));
1639 /* Look up instruction (or prefix) via hash table. */
1640 current_templates
= hash_find (op_hash
, mnemonic
);
1642 if (*l
!= END_OF_INSN
1643 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1644 && current_templates
1645 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1647 if (current_templates
->start
->cpu_flags
1648 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1650 as_bad ((flag_code
!= CODE_64BIT
1651 ? _("`%s' is only supported in 64-bit mode")
1652 : _("`%s' is not supported in 64-bit mode")),
1653 current_templates
->start
->name
);
1656 /* If we are in 16-bit mode, do not allow addr16 or data16.
1657 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1658 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1659 && flag_code
!= CODE_64BIT
1660 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1661 ^ (flag_code
== CODE_16BIT
)))
1663 as_bad (_("redundant %s prefix"),
1664 current_templates
->start
->name
);
1667 /* Add prefix, checking for repeated prefixes. */
1668 switch (add_prefix (current_templates
->start
->base_opcode
))
1673 expecting_string_instruction
= current_templates
->start
->name
;
1676 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1683 if (!current_templates
)
1685 /* See if we can get a match by trimming off a suffix. */
1688 case WORD_MNEM_SUFFIX
:
1689 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1690 i
.suffix
= SHORT_MNEM_SUFFIX
;
1692 case BYTE_MNEM_SUFFIX
:
1693 case QWORD_MNEM_SUFFIX
:
1694 i
.suffix
= mnem_p
[-1];
1696 current_templates
= hash_find (op_hash
, mnemonic
);
1698 case SHORT_MNEM_SUFFIX
:
1699 case LONG_MNEM_SUFFIX
:
1702 i
.suffix
= mnem_p
[-1];
1704 current_templates
= hash_find (op_hash
, mnemonic
);
1712 if (intel_float_operand (mnemonic
) == 1)
1713 i
.suffix
= SHORT_MNEM_SUFFIX
;
1715 i
.suffix
= LONG_MNEM_SUFFIX
;
1717 current_templates
= hash_find (op_hash
, mnemonic
);
1721 if (!current_templates
)
1723 as_bad (_("no such instruction: `%s'"), token_start
);
1728 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1730 /* Check for a branch hint. We allow ",pt" and ",pn" for
1731 predict taken and predict not taken respectively.
1732 I'm not sure that branch hints actually do anything on loop
1733 and jcxz insns (JumpByte) for current Pentium4 chips. They
1734 may work in the future and it doesn't hurt to accept them
1736 if (l
[0] == ',' && l
[1] == 'p')
1740 if (!add_prefix (DS_PREFIX_OPCODE
))
1744 else if (l
[2] == 'n')
1746 if (!add_prefix (CS_PREFIX_OPCODE
))
1752 /* Any other comma loses. */
1755 as_bad (_("invalid character %s in mnemonic"),
1756 output_invalid (*l
));
1760 /* Check if instruction is supported on specified architecture. */
1762 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1764 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1765 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1767 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1770 if (!(supported
& 2))
1772 as_bad (flag_code
== CODE_64BIT
1773 ? _("`%s' is not supported in 64-bit mode")
1774 : _("`%s' is only supported in 64-bit mode"),
1775 current_templates
->start
->name
);
1778 if (!(supported
& 1))
1780 as_warn (_("`%s' is not supported on `%s%s'"),
1781 current_templates
->start
->name
,
1783 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1785 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1787 as_warn (_("use .code16 to ensure correct addressing mode"));
1790 /* Check for rep/repne without a string instruction. */
1791 if (expecting_string_instruction
)
1793 static templates override
;
1795 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1796 if (t
->opcode_modifier
& IsString
)
1798 if (t
>= current_templates
->end
)
1800 as_bad (_("expecting string instruction after `%s'"),
1801 expecting_string_instruction
);
1804 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1805 if (!(t
->opcode_modifier
& IsString
))
1808 current_templates
= &override
;
1815 parse_operands (l
, mnemonic
)
1817 const char *mnemonic
;
1821 /* 1 if operand is pending after ','. */
1822 unsigned int expecting_operand
= 0;
1824 /* Non-zero if operand parens not balanced. */
1825 unsigned int paren_not_balanced
;
1827 while (*l
!= END_OF_INSN
)
1829 /* Skip optional white space before operand. */
1830 if (is_space_char (*l
))
1832 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1834 as_bad (_("invalid character %s before operand %d"),
1835 output_invalid (*l
),
1839 token_start
= l
; /* after white space */
1840 paren_not_balanced
= 0;
1841 while (paren_not_balanced
|| *l
!= ',')
1843 if (*l
== END_OF_INSN
)
1845 if (paren_not_balanced
)
1848 as_bad (_("unbalanced parenthesis in operand %d."),
1851 as_bad (_("unbalanced brackets in operand %d."),
1856 break; /* we are done */
1858 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1860 as_bad (_("invalid character %s in operand %d"),
1861 output_invalid (*l
),
1868 ++paren_not_balanced
;
1870 --paren_not_balanced
;
1875 ++paren_not_balanced
;
1877 --paren_not_balanced
;
1881 if (l
!= token_start
)
1882 { /* Yes, we've read in another operand. */
1883 unsigned int operand_ok
;
1884 this_operand
= i
.operands
++;
1885 if (i
.operands
> MAX_OPERANDS
)
1887 as_bad (_("spurious operands; (%d operands/instruction max)"),
1891 /* Now parse operand adding info to 'i' as we go along. */
1892 END_STRING_AND_SAVE (l
);
1896 i386_intel_operand (token_start
,
1897 intel_float_operand (mnemonic
));
1899 operand_ok
= i386_operand (token_start
);
1901 RESTORE_END_STRING (l
);
1907 if (expecting_operand
)
1909 expecting_operand_after_comma
:
1910 as_bad (_("expecting operand after ','; got nothing"));
1915 as_bad (_("expecting operand before ','; got nothing"));
1920 /* Now *l must be either ',' or END_OF_INSN. */
1923 if (*++l
== END_OF_INSN
)
1925 /* Just skip it, if it's \n complain. */
1926 goto expecting_operand_after_comma
;
1928 expecting_operand
= 1;
1937 union i386_op temp_op
;
1938 unsigned int temp_type
;
1939 enum bfd_reloc_code_real temp_reloc
;
1943 if (i
.operands
== 2)
1948 else if (i
.operands
== 3)
1953 temp_type
= i
.types
[xchg2
];
1954 i
.types
[xchg2
] = i
.types
[xchg1
];
1955 i
.types
[xchg1
] = temp_type
;
1956 temp_op
= i
.op
[xchg2
];
1957 i
.op
[xchg2
] = i
.op
[xchg1
];
1958 i
.op
[xchg1
] = temp_op
;
1959 temp_reloc
= i
.reloc
[xchg2
];
1960 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1961 i
.reloc
[xchg1
] = temp_reloc
;
1963 if (i
.mem_operands
== 2)
1965 const seg_entry
*temp_seg
;
1966 temp_seg
= i
.seg
[0];
1967 i
.seg
[0] = i
.seg
[1];
1968 i
.seg
[1] = temp_seg
;
1972 /* Try to ensure constant immediates are represented in the smallest
1977 char guess_suffix
= 0;
1981 guess_suffix
= i
.suffix
;
1982 else if (i
.reg_operands
)
1984 /* Figure out a suffix from the last register operand specified.
1985 We can't do this properly yet, ie. excluding InOutPortReg,
1986 but the following works for instructions with immediates.
1987 In any case, we can't set i.suffix yet. */
1988 for (op
= i
.operands
; --op
>= 0;)
1989 if (i
.types
[op
] & Reg
)
1991 if (i
.types
[op
] & Reg8
)
1992 guess_suffix
= BYTE_MNEM_SUFFIX
;
1993 else if (i
.types
[op
] & Reg16
)
1994 guess_suffix
= WORD_MNEM_SUFFIX
;
1995 else if (i
.types
[op
] & Reg32
)
1996 guess_suffix
= LONG_MNEM_SUFFIX
;
1997 else if (i
.types
[op
] & Reg64
)
1998 guess_suffix
= QWORD_MNEM_SUFFIX
;
2002 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2003 guess_suffix
= WORD_MNEM_SUFFIX
;
2005 for (op
= i
.operands
; --op
>= 0;)
2006 if (i
.types
[op
] & Imm
)
2008 switch (i
.op
[op
].imms
->X_op
)
2011 /* If a suffix is given, this operand may be shortened. */
2012 switch (guess_suffix
)
2014 case LONG_MNEM_SUFFIX
:
2015 i
.types
[op
] |= Imm32
| Imm64
;
2017 case WORD_MNEM_SUFFIX
:
2018 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2020 case BYTE_MNEM_SUFFIX
:
2021 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2025 /* If this operand is at most 16 bits, convert it
2026 to a signed 16 bit number before trying to see
2027 whether it will fit in an even smaller size.
2028 This allows a 16-bit operand such as $0xffe0 to
2029 be recognised as within Imm8S range. */
2030 if ((i
.types
[op
] & Imm16
)
2031 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2033 i
.op
[op
].imms
->X_add_number
=
2034 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2036 if ((i
.types
[op
] & Imm32
)
2037 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2040 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2041 ^ ((offsetT
) 1 << 31))
2042 - ((offsetT
) 1 << 31));
2044 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2046 /* We must avoid matching of Imm32 templates when 64bit
2047 only immediate is available. */
2048 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2049 i
.types
[op
] &= ~Imm32
;
2056 /* Symbols and expressions. */
2058 /* Convert symbolic operand to proper sizes for matching. */
2059 switch (guess_suffix
)
2061 case QWORD_MNEM_SUFFIX
:
2062 i
.types
[op
] = Imm64
| Imm32S
;
2064 case LONG_MNEM_SUFFIX
:
2065 i
.types
[op
] = Imm32
;
2067 case WORD_MNEM_SUFFIX
:
2068 i
.types
[op
] = Imm16
;
2070 case BYTE_MNEM_SUFFIX
:
2071 i
.types
[op
] = Imm8
| Imm8S
;
2079 /* Try to use the smallest displacement type too. */
2085 for (op
= i
.operands
; --op
>= 0;)
2086 if (i
.types
[op
] & Disp
)
2088 if (i
.op
[op
].disps
->X_op
== O_constant
)
2090 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2092 if ((i
.types
[op
] & Disp16
)
2093 && (disp
& ~(offsetT
) 0xffff) == 0)
2095 /* If this operand is at most 16 bits, convert
2096 to a signed 16 bit number and don't use 64bit
2098 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2099 i
.types
[op
] &= ~Disp64
;
2101 if ((i
.types
[op
] & Disp32
)
2102 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2104 /* If this operand is at most 32 bits, convert
2105 to a signed 32 bit number and don't use 64bit
2107 disp
&= (((offsetT
) 2 << 31) - 1);
2108 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2109 i
.types
[op
] &= ~Disp64
;
2111 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2113 i
.types
[op
] &= ~Disp
;
2117 else if (flag_code
== CODE_64BIT
)
2119 if (fits_in_signed_long (disp
))
2121 i
.types
[op
] &= ~Disp64
;
2122 i
.types
[op
] |= Disp32S
;
2124 if (fits_in_unsigned_long (disp
))
2125 i
.types
[op
] |= Disp32
;
2127 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2128 && fits_in_signed_byte (disp
))
2129 i
.types
[op
] |= Disp8
;
2132 /* We only support 64bit displacement on constants. */
2133 i
.types
[op
] &= ~Disp64
;
2140 /* Points to template once we've found it. */
2142 unsigned int overlap0
, overlap1
, overlap2
;
2143 unsigned int found_reverse_match
;
2146 #define MATCH(overlap, given, template) \
2147 ((overlap & ~JumpAbsolute) \
2148 && (((given) & (BaseIndex | JumpAbsolute)) \
2149 == ((overlap) & (BaseIndex | JumpAbsolute))))
2151 /* If given types r0 and r1 are registers they must be of the same type
2152 unless the expected operand type register overlap is null.
2153 Note that Acc in a template matches every size of reg. */
2154 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2155 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2156 || ((g0) & Reg) == ((g1) & Reg) \
2157 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2162 found_reverse_match
= 0;
2163 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2165 : (i
.suffix
== WORD_MNEM_SUFFIX
2167 : (i
.suffix
== SHORT_MNEM_SUFFIX
2169 : (i
.suffix
== LONG_MNEM_SUFFIX
2171 : (i
.suffix
== QWORD_MNEM_SUFFIX
2173 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2174 ? No_xSuf
: 0))))));
2176 t
= current_templates
->start
;
2177 if (i
.suffix
== QWORD_MNEM_SUFFIX
2178 && flag_code
!= CODE_64BIT
2180 ? !(t
->opcode_modifier
& IgnoreSize
)
2181 && !intel_float_operand (t
->name
)
2182 : intel_float_operand (t
->name
) != 2)
2183 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2184 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2185 && (t
->base_opcode
!= 0x0fc7
2186 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2187 t
= current_templates
->end
;
2188 for (; t
< current_templates
->end
; t
++)
2190 /* Must have right number of operands. */
2191 if (i
.operands
!= t
->operands
)
2194 /* Check the suffix, except for some instructions in intel mode. */
2195 if ((t
->opcode_modifier
& suffix_check
)
2197 && (t
->opcode_modifier
& IgnoreSize
)))
2200 /* Do not verify operands when there are none. */
2201 else if (!t
->operands
)
2203 if (t
->cpu_flags
& ~cpu_arch_flags
)
2205 /* We've found a match; break out of loop. */
2209 overlap0
= i
.types
[0] & t
->operand_types
[0];
2210 switch (t
->operands
)
2213 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2218 overlap1
= i
.types
[1] & t
->operand_types
[1];
2219 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2220 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2221 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2222 t
->operand_types
[0],
2223 overlap1
, i
.types
[1],
2224 t
->operand_types
[1]))
2226 /* Check if other direction is valid ... */
2227 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2230 /* Try reversing direction of operands. */
2231 overlap0
= i
.types
[0] & t
->operand_types
[1];
2232 overlap1
= i
.types
[1] & t
->operand_types
[0];
2233 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2234 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2235 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2236 t
->operand_types
[1],
2237 overlap1
, i
.types
[1],
2238 t
->operand_types
[0]))
2240 /* Does not match either direction. */
2243 /* found_reverse_match holds which of D or FloatDR
2245 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2247 /* Found a forward 2 operand match here. */
2248 else if (t
->operands
== 3)
2250 /* Here we make use of the fact that there are no
2251 reverse match 3 operand instructions, and all 3
2252 operand instructions only need to be checked for
2253 register consistency between operands 2 and 3. */
2254 overlap2
= i
.types
[2] & t
->operand_types
[2];
2255 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2256 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2257 t
->operand_types
[1],
2258 overlap2
, i
.types
[2],
2259 t
->operand_types
[2]))
2263 /* Found either forward/reverse 2 or 3 operand match here:
2264 slip through to break. */
2266 if (t
->cpu_flags
& ~cpu_arch_flags
)
2268 found_reverse_match
= 0;
2271 /* We've found a match; break out of loop. */
2275 if (t
== current_templates
->end
)
2277 /* We found no match. */
2278 as_bad (_("suffix or operands invalid for `%s'"),
2279 current_templates
->start
->name
);
2283 if (!quiet_warnings
)
2286 && ((i
.types
[0] & JumpAbsolute
)
2287 != (t
->operand_types
[0] & JumpAbsolute
)))
2289 as_warn (_("indirect %s without `*'"), t
->name
);
2292 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2293 == (IsPrefix
| IgnoreSize
))
2295 /* Warn them that a data or address size prefix doesn't
2296 affect assembly of the next line of code. */
2297 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2301 /* Copy the template we found. */
2303 if (found_reverse_match
)
2305 /* If we found a reverse match we must alter the opcode
2306 direction bit. found_reverse_match holds bits to change
2307 (different for int & float insns). */
2309 i
.tm
.base_opcode
^= found_reverse_match
;
2311 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2312 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2321 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2322 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2324 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2326 as_bad (_("`%s' operand %d must use `%%es' segment"),
2331 /* There's only ever one segment override allowed per instruction.
2332 This instruction possibly has a legal segment override on the
2333 second operand, so copy the segment to where non-string
2334 instructions store it, allowing common code. */
2335 i
.seg
[0] = i
.seg
[1];
2337 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2339 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2341 as_bad (_("`%s' operand %d must use `%%es' segment"),
2351 process_suffix (void)
2353 /* If matched instruction specifies an explicit instruction mnemonic
2355 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2357 if (i
.tm
.opcode_modifier
& Size16
)
2358 i
.suffix
= WORD_MNEM_SUFFIX
;
2359 else if (i
.tm
.opcode_modifier
& Size64
)
2360 i
.suffix
= QWORD_MNEM_SUFFIX
;
2362 i
.suffix
= LONG_MNEM_SUFFIX
;
2364 else if (i
.reg_operands
)
2366 /* If there's no instruction mnemonic suffix we try to invent one
2367 based on register operands. */
2370 /* We take i.suffix from the last register operand specified,
2371 Destination register type is more significant than source
2375 for (op
= i
.operands
; --op
>= 0;)
2376 if ((i
.types
[op
] & Reg
)
2377 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2379 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2380 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2381 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2386 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2388 if (!check_byte_reg ())
2391 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2393 if (!check_long_reg ())
2396 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2398 if (!check_qword_reg ())
2401 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2403 if (!check_word_reg ())
2406 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2407 /* Do nothing if the instruction is going to ignore the prefix. */
2412 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2414 /* exclude fldenv/frstor/fsave/fstenv */
2415 && (i
.tm
.opcode_modifier
& No_sSuf
))
2417 i
.suffix
= stackop_size
;
2419 else if (intel_syntax
2421 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2422 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2423 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2424 && i
.tm
.extension_opcode
<= 3)))
2429 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2431 i
.suffix
= QWORD_MNEM_SUFFIX
;
2435 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2436 i
.suffix
= LONG_MNEM_SUFFIX
;
2439 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2440 i
.suffix
= WORD_MNEM_SUFFIX
;
2449 if (i
.tm
.opcode_modifier
& W
)
2451 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2457 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2465 if ((i
.tm
.opcode_modifier
& W
)
2466 || ((suffixes
& (suffixes
- 1))
2467 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2469 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2475 /* Change the opcode based on the operand size given by i.suffix;
2476 We don't need to change things for byte insns. */
2478 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2480 /* It's not a byte, select word/dword operation. */
2481 if (i
.tm
.opcode_modifier
& W
)
2483 if (i
.tm
.opcode_modifier
& ShortForm
)
2484 i
.tm
.base_opcode
|= 8;
2486 i
.tm
.base_opcode
|= 1;
2489 /* Now select between word & dword operations via the operand
2490 size prefix, except for instructions that will ignore this
2492 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2493 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2494 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2495 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2496 || (flag_code
== CODE_64BIT
2497 && (i
.tm
.opcode_modifier
& JumpByte
))))
2499 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2501 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2502 prefix
= ADDR_PREFIX_OPCODE
;
2504 if (!add_prefix (prefix
))
2508 /* Set mode64 for an operand. */
2509 if (i
.suffix
== QWORD_MNEM_SUFFIX
2510 && flag_code
== CODE_64BIT
2511 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2512 i
.rex
|= REX_MODE64
;
2514 /* Size floating point instruction. */
2515 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2516 if (i
.tm
.opcode_modifier
& FloatMF
)
2517 i
.tm
.base_opcode
^= 4;
2524 check_byte_reg (void)
2528 for (op
= i
.operands
; --op
>= 0;)
2530 /* If this is an eight bit register, it's OK. If it's the 16 or
2531 32 bit version of an eight bit register, we will just use the
2532 low portion, and that's OK too. */
2533 if (i
.types
[op
] & Reg8
)
2536 /* movzx and movsx should not generate this warning. */
2538 && (i
.tm
.base_opcode
== 0xfb7
2539 || i
.tm
.base_opcode
== 0xfb6
2540 || i
.tm
.base_opcode
== 0x63
2541 || i
.tm
.base_opcode
== 0xfbe
2542 || i
.tm
.base_opcode
== 0xfbf))
2545 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2547 /* Prohibit these changes in the 64bit mode, since the
2548 lowering is more complicated. */
2549 if (flag_code
== CODE_64BIT
2550 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2552 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2553 i
.op
[op
].regs
->reg_name
,
2557 #if REGISTER_WARNINGS
2559 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2560 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2561 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2562 ? REGNAM_AL
- REGNAM_AX
2563 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2564 i
.op
[op
].regs
->reg_name
,
2569 /* Any other register is bad. */
2570 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2572 | Control
| Debug
| Test
2573 | FloatReg
| FloatAcc
))
2575 as_bad (_("`%%%s' not allowed with `%s%c'"),
2576 i
.op
[op
].regs
->reg_name
,
2590 for (op
= i
.operands
; --op
>= 0;)
2591 /* Reject eight bit registers, except where the template requires
2592 them. (eg. movzb) */
2593 if ((i
.types
[op
] & Reg8
) != 0
2594 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2596 as_bad (_("`%%%s' not allowed with `%s%c'"),
2597 i
.op
[op
].regs
->reg_name
,
2602 /* Warn if the e prefix on a general reg is missing. */
2603 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2604 && (i
.types
[op
] & Reg16
) != 0
2605 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2607 /* Prohibit these changes in the 64bit mode, since the
2608 lowering is more complicated. */
2609 if (flag_code
== CODE_64BIT
)
2611 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2612 i
.op
[op
].regs
->reg_name
,
2616 #if REGISTER_WARNINGS
2618 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2619 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2620 i
.op
[op
].regs
->reg_name
,
2624 /* Warn if the r prefix on a general reg is missing. */
2625 else if ((i
.types
[op
] & Reg64
) != 0
2626 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2628 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2629 i
.op
[op
].regs
->reg_name
,
2641 for (op
= i
.operands
; --op
>= 0; )
2642 /* Reject eight bit registers, except where the template requires
2643 them. (eg. movzb) */
2644 if ((i
.types
[op
] & Reg8
) != 0
2645 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2647 as_bad (_("`%%%s' not allowed with `%s%c'"),
2648 i
.op
[op
].regs
->reg_name
,
2653 /* Warn if the e prefix on a general reg is missing. */
2654 else if (((i
.types
[op
] & Reg16
) != 0
2655 || (i
.types
[op
] & Reg32
) != 0)
2656 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2658 /* Prohibit these changes in the 64bit mode, since the
2659 lowering is more complicated. */
2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2661 i
.op
[op
].regs
->reg_name
,
2672 for (op
= i
.operands
; --op
>= 0;)
2673 /* Reject eight bit registers, except where the template requires
2674 them. (eg. movzb) */
2675 if ((i
.types
[op
] & Reg8
) != 0
2676 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2678 as_bad (_("`%%%s' not allowed with `%s%c'"),
2679 i
.op
[op
].regs
->reg_name
,
2684 /* Warn if the e prefix on a general reg is present. */
2685 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2686 && (i
.types
[op
] & Reg32
) != 0
2687 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2689 /* Prohibit these changes in the 64bit mode, since the
2690 lowering is more complicated. */
2691 if (flag_code
== CODE_64BIT
)
2693 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2694 i
.op
[op
].regs
->reg_name
,
2699 #if REGISTER_WARNINGS
2700 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2701 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2702 i
.op
[op
].regs
->reg_name
,
2712 unsigned int overlap0
, overlap1
, overlap2
;
2714 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2715 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2716 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2717 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2718 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2722 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2724 : (i
.suffix
== WORD_MNEM_SUFFIX
2726 : (i
.suffix
== QWORD_MNEM_SUFFIX
2730 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2731 || overlap0
== (Imm16
| Imm32
)
2732 || overlap0
== (Imm16
| Imm32S
))
2734 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2737 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2738 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2739 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2741 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2745 i
.types
[0] = overlap0
;
2747 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2748 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2749 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2750 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2751 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2755 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2757 : (i
.suffix
== WORD_MNEM_SUFFIX
2759 : (i
.suffix
== QWORD_MNEM_SUFFIX
2763 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2764 || overlap1
== (Imm16
| Imm32
)
2765 || overlap1
== (Imm16
| Imm32S
))
2767 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2770 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2771 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2772 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2774 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2778 i
.types
[1] = overlap1
;
2780 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2781 assert ((overlap2
& Imm
) == 0);
2782 i
.types
[2] = overlap2
;
2790 /* Default segment register this instruction will use for memory
2791 accesses. 0 means unknown. This is only for optimizing out
2792 unnecessary segment overrides. */
2793 const seg_entry
*default_seg
= 0;
2795 /* The imul $imm, %reg instruction is converted into
2796 imul $imm, %reg, %reg, and the clr %reg instruction
2797 is converted into xor %reg, %reg. */
2798 if (i
.tm
.opcode_modifier
& regKludge
)
2800 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2801 /* Pretend we saw the extra register operand. */
2802 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2803 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2804 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2808 if (i
.tm
.opcode_modifier
& ShortForm
)
2810 /* The register or float register operand is in operand 0 or 1. */
2811 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2812 /* Register goes in low 3 bits of opcode. */
2813 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2814 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2816 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2818 /* Warn about some common errors, but press on regardless.
2819 The first case can be generated by gcc (<= 2.8.1). */
2820 if (i
.operands
== 2)
2822 /* Reversed arguments on faddp, fsubp, etc. */
2823 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2824 i
.op
[1].regs
->reg_name
,
2825 i
.op
[0].regs
->reg_name
);
2829 /* Extraneous `l' suffix on fp insn. */
2830 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2831 i
.op
[0].regs
->reg_name
);
2835 else if (i
.tm
.opcode_modifier
& Modrm
)
2837 /* The opcode is completed (modulo i.tm.extension_opcode which
2838 must be put into the modrm byte). Now, we make the modrm and
2839 index base bytes based on all the info we've collected. */
2841 default_seg
= build_modrm_byte ();
2843 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2845 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2846 && i
.op
[0].regs
->reg_num
== 1)
2848 as_bad (_("you can't `pop %%cs'"));
2851 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2852 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2855 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2859 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2861 /* For the string instructions that allow a segment override
2862 on one of their operands, the default segment is ds. */
2866 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2867 || (i
.tm
.cpu_flags
& CpuSVME
))
2868 && i
.seg
[0] && !quiet_warnings
)
2869 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2871 /* If a segment was explicitly specified, and the specified segment
2872 is not the default, use an opcode prefix to select it. If we
2873 never figured out what the default segment is, then default_seg
2874 will be zero at this point, and the specified segment prefix will
2876 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2878 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2884 static const seg_entry
*
2887 const seg_entry
*default_seg
= 0;
2889 /* i.reg_operands MUST be the number of real register operands;
2890 implicit registers do not count. */
2891 if (i
.reg_operands
== 2)
2893 unsigned int source
, dest
;
2894 source
= ((i
.types
[0]
2895 & (Reg
| RegMMX
| RegXMM
2897 | Control
| Debug
| Test
))
2902 /* One of the register operands will be encoded in the i.tm.reg
2903 field, the other in the combined i.tm.mode and i.tm.regmem
2904 fields. If no form of this instruction supports a memory
2905 destination operand, then we assume the source operand may
2906 sometimes be a memory operand and so we need to store the
2907 destination in the i.rm.reg field. */
2908 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2910 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2911 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2912 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2914 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2919 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2920 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2921 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2923 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2926 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2928 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2930 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2931 add_prefix (LOCK_PREFIX_OPCODE
);
2935 { /* If it's not 2 reg operands... */
2938 unsigned int fake_zero_displacement
= 0;
2939 unsigned int op
= ((i
.types
[0] & AnyMem
)
2941 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2945 if (i
.base_reg
== 0)
2948 if (!i
.disp_operands
)
2949 fake_zero_displacement
= 1;
2950 if (i
.index_reg
== 0)
2952 /* Operand is just <disp> */
2953 if (flag_code
== CODE_64BIT
)
2955 /* 64bit mode overwrites the 32bit absolute
2956 addressing by RIP relative addressing and
2957 absolute addressing is encoded by one of the
2958 redundant SIB forms. */
2959 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2960 i
.sib
.base
= NO_BASE_REGISTER
;
2961 i
.sib
.index
= NO_INDEX_REGISTER
;
2962 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2964 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2966 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2967 i
.types
[op
] = Disp16
;
2971 i
.rm
.regmem
= NO_BASE_REGISTER
;
2972 i
.types
[op
] = Disp32
;
2975 else /* !i.base_reg && i.index_reg */
2977 i
.sib
.index
= i
.index_reg
->reg_num
;
2978 i
.sib
.base
= NO_BASE_REGISTER
;
2979 i
.sib
.scale
= i
.log2_scale_factor
;
2980 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2981 i
.types
[op
] &= ~Disp
;
2982 if (flag_code
!= CODE_64BIT
)
2983 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2985 i
.types
[op
] |= Disp32S
;
2986 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2990 /* RIP addressing for 64bit mode. */
2991 else if (i
.base_reg
->reg_type
== BaseIndex
)
2993 i
.rm
.regmem
= NO_BASE_REGISTER
;
2994 i
.types
[op
] &= ~ Disp
;
2995 i
.types
[op
] |= Disp32S
;
2996 i
.flags
[op
] = Operand_PCrel
;
2997 if (! i
.disp_operands
)
2998 fake_zero_displacement
= 1;
3000 else if (i
.base_reg
->reg_type
& Reg16
)
3002 switch (i
.base_reg
->reg_num
)
3005 if (i
.index_reg
== 0)
3007 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3008 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3012 if (i
.index_reg
== 0)
3015 if ((i
.types
[op
] & Disp
) == 0)
3017 /* fake (%bp) into 0(%bp) */
3018 i
.types
[op
] |= Disp8
;
3019 fake_zero_displacement
= 1;
3022 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3023 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3025 default: /* (%si) -> 4 or (%di) -> 5 */
3026 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3028 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3030 else /* i.base_reg and 32/64 bit mode */
3032 if (flag_code
== CODE_64BIT
3033 && (i
.types
[op
] & Disp
))
3034 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3036 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3037 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3039 i
.sib
.base
= i
.base_reg
->reg_num
;
3040 /* x86-64 ignores REX prefix bit here to avoid decoder
3042 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3045 if (i
.disp_operands
== 0)
3047 fake_zero_displacement
= 1;
3048 i
.types
[op
] |= Disp8
;
3051 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3055 i
.sib
.scale
= i
.log2_scale_factor
;
3056 if (i
.index_reg
== 0)
3058 /* <disp>(%esp) becomes two byte modrm with no index
3059 register. We've already stored the code for esp
3060 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3061 Any base register besides %esp will not use the
3062 extra modrm byte. */
3063 i
.sib
.index
= NO_INDEX_REGISTER
;
3064 #if !SCALE1_WHEN_NO_INDEX
3065 /* Another case where we force the second modrm byte. */
3066 if (i
.log2_scale_factor
)
3067 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3072 i
.sib
.index
= i
.index_reg
->reg_num
;
3073 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3074 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3077 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3080 if (fake_zero_displacement
)
3082 /* Fakes a zero displacement assuming that i.types[op]
3083 holds the correct displacement size. */
3086 assert (i
.op
[op
].disps
== 0);
3087 exp
= &disp_expressions
[i
.disp_operands
++];
3088 i
.op
[op
].disps
= exp
;
3089 exp
->X_op
= O_constant
;
3090 exp
->X_add_number
= 0;
3091 exp
->X_add_symbol
= (symbolS
*) 0;
3092 exp
->X_op_symbol
= (symbolS
*) 0;
3096 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3097 (if any) based on i.tm.extension_opcode. Again, we must be
3098 careful to make sure that segment/control/debug/test/MMX
3099 registers are coded into the i.rm.reg field. */
3104 & (Reg
| RegMMX
| RegXMM
3106 | Control
| Debug
| Test
))
3109 & (Reg
| RegMMX
| RegXMM
3111 | Control
| Debug
| Test
))
3114 /* If there is an extension opcode to put here, the register
3115 number must be put into the regmem field. */
3116 if (i
.tm
.extension_opcode
!= None
)
3118 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3119 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3124 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3125 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3129 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3130 must set it to 3 to indicate this is a register operand
3131 in the regmem field. */
3132 if (!i
.mem_operands
)
3136 /* Fill in i.rm.reg field with extension opcode (if any). */
3137 if (i
.tm
.extension_opcode
!= None
)
3138 i
.rm
.reg
= i
.tm
.extension_opcode
;
3149 relax_substateT subtype
;
3154 if (flag_code
== CODE_16BIT
)
3158 if (i
.prefix
[DATA_PREFIX
] != 0)
3164 /* Pentium4 branch hints. */
3165 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3166 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3171 if (i
.prefix
[REX_PREFIX
] != 0)
3177 if (i
.prefixes
!= 0 && !intel_syntax
)
3178 as_warn (_("skipping prefixes on this instruction"));
3180 /* It's always a symbol; End frag & setup for relax.
3181 Make sure there is enough room in this frag for the largest
3182 instruction we may generate in md_convert_frag. This is 2
3183 bytes for the opcode and room for the prefix and largest
3185 frag_grow (prefix
+ 2 + 4);
3186 /* Prefix and 1 opcode byte go in fr_fix. */
3187 p
= frag_more (prefix
+ 1);
3188 if (i
.prefix
[DATA_PREFIX
] != 0)
3189 *p
++ = DATA_PREFIX_OPCODE
;
3190 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3191 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3192 *p
++ = i
.prefix
[SEG_PREFIX
];
3193 if (i
.prefix
[REX_PREFIX
] != 0)
3194 *p
++ = i
.prefix
[REX_PREFIX
];
3195 *p
= i
.tm
.base_opcode
;
3197 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3198 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3199 else if ((cpu_arch_flags
& Cpu386
) != 0)
3200 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3202 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3205 sym
= i
.op
[0].disps
->X_add_symbol
;
3206 off
= i
.op
[0].disps
->X_add_number
;
3208 if (i
.op
[0].disps
->X_op
!= O_constant
3209 && i
.op
[0].disps
->X_op
!= O_symbol
)
3211 /* Handle complex expressions. */
3212 sym
= make_expr_symbol (i
.op
[0].disps
);
3216 /* 1 possible extra opcode + 4 byte displacement go in var part.
3217 Pass reloc in fr_var. */
3218 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3228 if (i
.tm
.opcode_modifier
& JumpByte
)
3230 /* This is a loop or jecxz type instruction. */
3232 if (i
.prefix
[ADDR_PREFIX
] != 0)
3234 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3237 /* Pentium4 branch hints. */
3238 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3239 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3241 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3250 if (flag_code
== CODE_16BIT
)
3253 if (i
.prefix
[DATA_PREFIX
] != 0)
3255 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3265 if (i
.prefix
[REX_PREFIX
] != 0)
3267 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3271 if (i
.prefixes
!= 0 && !intel_syntax
)
3272 as_warn (_("skipping prefixes on this instruction"));
3274 p
= frag_more (1 + size
);
3275 *p
++ = i
.tm
.base_opcode
;
3277 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3278 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3280 /* All jumps handled here are signed, but don't use a signed limit
3281 check for 32 and 16 bit jumps as we want to allow wrap around at
3282 4G and 64k respectively. */
3284 fixP
->fx_signed
= 1;
3288 output_interseg_jump ()
3296 if (flag_code
== CODE_16BIT
)
3300 if (i
.prefix
[DATA_PREFIX
] != 0)
3306 if (i
.prefix
[REX_PREFIX
] != 0)
3316 if (i
.prefixes
!= 0 && !intel_syntax
)
3317 as_warn (_("skipping prefixes on this instruction"));
3319 /* 1 opcode; 2 segment; offset */
3320 p
= frag_more (prefix
+ 1 + 2 + size
);
3322 if (i
.prefix
[DATA_PREFIX
] != 0)
3323 *p
++ = DATA_PREFIX_OPCODE
;
3325 if (i
.prefix
[REX_PREFIX
] != 0)
3326 *p
++ = i
.prefix
[REX_PREFIX
];
3328 *p
++ = i
.tm
.base_opcode
;
3329 if (i
.op
[1].imms
->X_op
== O_constant
)
3331 offsetT n
= i
.op
[1].imms
->X_add_number
;
3334 && !fits_in_unsigned_word (n
)
3335 && !fits_in_signed_word (n
))
3337 as_bad (_("16-bit jump out of range"));
3340 md_number_to_chars (p
, n
, size
);
3343 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3344 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3345 if (i
.op
[0].imms
->X_op
!= O_constant
)
3346 as_bad (_("can't handle non absolute segment in `%s'"),
3348 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3354 fragS
*insn_start_frag
;
3355 offsetT insn_start_off
;
3357 /* Tie dwarf2 debug info to the address at the start of the insn.
3358 We can't do this after the insn has been output as the current
3359 frag may have been closed off. eg. by frag_var. */
3360 dwarf2_emit_insn (0);
3362 insn_start_frag
= frag_now
;
3363 insn_start_off
= frag_now_fix ();
3366 if (i
.tm
.opcode_modifier
& Jump
)
3368 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3370 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3371 output_interseg_jump ();
3374 /* Output normal instructions here. */
3378 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3379 more higher byte to specify a prefix the instruction
3381 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3383 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3385 unsigned int prefix
;
3386 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3388 if (prefix
!= REPE_PREFIX_OPCODE
3389 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3390 add_prefix (prefix
);
3393 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3396 /* The prefix bytes. */
3398 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3404 md_number_to_chars (p
, (valueT
) *q
, 1);
3408 /* Now the opcode; be careful about word order here! */
3409 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3411 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3417 /* Put out high byte first: can't use md_number_to_chars! */
3418 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3419 *p
= i
.tm
.base_opcode
& 0xff;
3422 /* Now the modrm byte and sib byte (if present). */
3423 if (i
.tm
.opcode_modifier
& Modrm
)
3426 md_number_to_chars (p
,
3427 (valueT
) (i
.rm
.regmem
<< 0
3431 /* If i.rm.regmem == ESP (4)
3432 && i.rm.mode != (Register mode)
3434 ==> need second modrm byte. */
3435 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3437 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3440 md_number_to_chars (p
,
3441 (valueT
) (i
.sib
.base
<< 0
3443 | i
.sib
.scale
<< 6),
3448 if (i
.disp_operands
)
3449 output_disp (insn_start_frag
, insn_start_off
);
3452 output_imm (insn_start_frag
, insn_start_off
);
3460 #endif /* DEBUG386 */
3464 output_disp (insn_start_frag
, insn_start_off
)
3465 fragS
*insn_start_frag
;
3466 offsetT insn_start_off
;
3471 for (n
= 0; n
< i
.operands
; n
++)
3473 if (i
.types
[n
] & Disp
)
3475 if (i
.op
[n
].disps
->X_op
== O_constant
)
3481 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3484 if (i
.types
[n
] & Disp8
)
3486 if (i
.types
[n
] & Disp64
)
3489 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3491 p
= frag_more (size
);
3492 md_number_to_chars (p
, val
, size
);
3496 enum bfd_reloc_code_real reloc_type
;
3499 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3501 /* The PC relative address is computed relative
3502 to the instruction boundary, so in case immediate
3503 fields follows, we need to adjust the value. */
3504 if (pcrel
&& i
.imm_operands
)
3509 for (n1
= 0; n1
< i
.operands
; n1
++)
3510 if (i
.types
[n1
] & Imm
)
3512 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3515 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3517 if (i
.types
[n1
] & Imm64
)
3522 /* We should find the immediate. */
3523 if (n1
== i
.operands
)
3525 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3528 if (i
.types
[n
] & Disp32S
)
3531 if (i
.types
[n
] & (Disp16
| Disp64
))
3534 if (i
.types
[n
] & Disp64
)
3538 p
= frag_more (size
);
3539 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3541 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3542 && (((reloc_type
== BFD_RELOC_32
3543 || reloc_type
== BFD_RELOC_X86_64_32S
)
3544 && (i
.op
[n
].disps
->X_op
== O_symbol
3545 || (i
.op
[n
].disps
->X_op
== O_add
3546 && ((symbol_get_value_expression
3547 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3549 || reloc_type
== BFD_RELOC_32_PCREL
))
3553 if (insn_start_frag
== frag_now
)
3554 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3559 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3560 for (fr
= insn_start_frag
->fr_next
;
3561 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3563 add
+= p
- frag_now
->fr_literal
;
3566 if (flag_code
!= CODE_64BIT
)
3567 reloc_type
= BFD_RELOC_386_GOTPC
;
3569 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3570 i
.op
[n
].disps
->X_add_number
+= add
;
3572 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3573 i
.op
[n
].disps
, pcrel
, reloc_type
);
3580 output_imm (insn_start_frag
, insn_start_off
)
3581 fragS
*insn_start_frag
;
3582 offsetT insn_start_off
;
3587 for (n
= 0; n
< i
.operands
; n
++)
3589 if (i
.types
[n
] & Imm
)
3591 if (i
.op
[n
].imms
->X_op
== O_constant
)
3597 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3600 if (i
.types
[n
] & (Imm8
| Imm8S
))
3602 else if (i
.types
[n
] & Imm64
)
3605 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3607 p
= frag_more (size
);
3608 md_number_to_chars (p
, val
, size
);
3612 /* Not absolute_section.
3613 Need a 32-bit fixup (don't support 8bit
3614 non-absolute imms). Try to support other
3616 enum bfd_reloc_code_real reloc_type
;
3620 if ((i
.types
[n
] & (Imm32S
))
3621 && (i
.suffix
== QWORD_MNEM_SUFFIX
3622 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3624 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3627 if (i
.types
[n
] & (Imm8
| Imm8S
))
3629 if (i
.types
[n
] & Imm64
)
3633 p
= frag_more (size
);
3634 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3636 /* This is tough to explain. We end up with this one if we
3637 * have operands that look like
3638 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3639 * obtain the absolute address of the GOT, and it is strongly
3640 * preferable from a performance point of view to avoid using
3641 * a runtime relocation for this. The actual sequence of
3642 * instructions often look something like:
3647 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3649 * The call and pop essentially return the absolute address
3650 * of the label .L66 and store it in %ebx. The linker itself
3651 * will ultimately change the first operand of the addl so
3652 * that %ebx points to the GOT, but to keep things simple, the
3653 * .o file must have this operand set so that it generates not
3654 * the absolute address of .L66, but the absolute address of
3655 * itself. This allows the linker itself simply treat a GOTPC
3656 * relocation as asking for a pcrel offset to the GOT to be
3657 * added in, and the addend of the relocation is stored in the
3658 * operand field for the instruction itself.
3660 * Our job here is to fix the operand so that it would add
3661 * the correct offset so that %ebx would point to itself. The
3662 * thing that is tricky is that .-.L66 will point to the
3663 * beginning of the instruction, so we need to further modify
3664 * the operand so that it will point to itself. There are
3665 * other cases where you have something like:
3667 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3669 * and here no correction would be required. Internally in
3670 * the assembler we treat operands of this form as not being
3671 * pcrel since the '.' is explicitly mentioned, and I wonder
3672 * whether it would simplify matters to do it this way. Who
3673 * knows. In earlier versions of the PIC patches, the
3674 * pcrel_adjust field was used to store the correction, but
3675 * since the expression is not pcrel, I felt it would be
3676 * confusing to do it this way. */
3678 if ((reloc_type
== BFD_RELOC_32
3679 || reloc_type
== BFD_RELOC_X86_64_32S
)
3681 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3682 && (i
.op
[n
].imms
->X_op
== O_symbol
3683 || (i
.op
[n
].imms
->X_op
== O_add
3684 && ((symbol_get_value_expression
3685 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3690 if (insn_start_frag
== frag_now
)
3691 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3696 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3697 for (fr
= insn_start_frag
->fr_next
;
3698 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3700 add
+= p
- frag_now
->fr_literal
;
3703 if (flag_code
!= CODE_64BIT
)
3704 reloc_type
= BFD_RELOC_386_GOTPC
;
3706 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3707 i
.op
[n
].imms
->X_add_number
+= add
;
3709 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3710 i
.op
[n
].imms
, 0, reloc_type
);
3717 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3719 /* Parse operands of the form
3720 <symbol>@GOTOFF+<nnn>
3721 and similar .plt or .got references.
3723 If we find one, set up the correct relocation in RELOC and copy the
3724 input string, minus the `@GOTOFF' into a malloc'd buffer for
3725 parsing by the calling routine. Return this buffer, and if ADJUST
3726 is non-null set it to the length of the string we removed from the
3727 input line. Otherwise return NULL. */
3729 lex_got (reloc
, adjust
)
3730 enum bfd_reloc_code_real
*reloc
;
3733 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3734 static const struct {
3736 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3738 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3739 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
} },
3740 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3741 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3742 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3743 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3744 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3745 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3746 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3747 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3748 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3749 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3750 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3755 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3756 if (is_end_of_line
[(unsigned char) *cp
])
3759 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3763 len
= strlen (gotrel
[j
].str
);
3764 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3766 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3769 char *tmpbuf
, *past_reloc
;
3771 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3775 if (GOT_symbol
== NULL
)
3776 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3778 /* Replace the relocation token with ' ', so that
3779 errors like foo@GOTOFF1 will be detected. */
3781 /* The length of the first part of our input line. */
3782 first
= cp
- input_line_pointer
;
3784 /* The second part goes from after the reloc token until
3785 (and including) an end_of_line char. Don't use strlen
3786 here as the end_of_line char may not be a NUL. */
3787 past_reloc
= cp
+ 1 + len
;
3788 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3790 second
= cp
- past_reloc
;
3792 /* Allocate and copy string. The trailing NUL shouldn't
3793 be necessary, but be safe. */
3794 tmpbuf
= xmalloc (first
+ second
+ 2);
3795 memcpy (tmpbuf
, input_line_pointer
, first
);
3796 tmpbuf
[first
] = ' ';
3797 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3798 tmpbuf
[first
+ second
+ 1] = '\0';
3802 as_bad (_("@%s reloc is not supported in %s bit mode"),
3803 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3808 /* Might be a symbol version string. Don't as_bad here. */
3812 /* x86_cons_fix_new is called via the expression parsing code when a
3813 reloc is needed. We use this hook to get the correct .got reloc. */
3814 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3817 x86_cons_fix_new (frag
, off
, len
, exp
)
3823 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3824 got_reloc
= NO_RELOC
;
3825 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3829 x86_cons (exp
, size
)
3833 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3835 /* Handle @GOTOFF and the like in an expression. */
3837 char *gotfree_input_line
;
3840 save
= input_line_pointer
;
3841 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3842 if (gotfree_input_line
)
3843 input_line_pointer
= gotfree_input_line
;
3847 if (gotfree_input_line
)
3849 /* expression () has merrily parsed up to the end of line,
3850 or a comma - in the wrong buffer. Transfer how far
3851 input_line_pointer has moved to the right buffer. */
3852 input_line_pointer
= (save
3853 + (input_line_pointer
- gotfree_input_line
)
3855 free (gotfree_input_line
);
3866 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3872 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3874 if (exp
->X_op
== O_secrel
)
3876 exp
->X_op
= O_symbol
;
3877 r
= BFD_RELOC_32_SECREL
;
3880 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3884 pe_directive_secrel (dummy
)
3885 int dummy ATTRIBUTE_UNUSED
;
3892 if (exp
.X_op
== O_symbol
)
3893 exp
.X_op
= O_secrel
;
3895 emit_expr (&exp
, 4);
3897 while (*input_line_pointer
++ == ',');
3899 input_line_pointer
--;
3900 demand_empty_rest_of_line ();
3905 static int i386_immediate
PARAMS ((char *));
3908 i386_immediate (imm_start
)
3911 char *save_input_line_pointer
;
3913 char *gotfree_input_line
;
3918 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3920 as_bad (_("only 1 or 2 immediate operands are allowed"));
3924 exp
= &im_expressions
[i
.imm_operands
++];
3925 i
.op
[this_operand
].imms
= exp
;
3927 if (is_space_char (*imm_start
))
3930 save_input_line_pointer
= input_line_pointer
;
3931 input_line_pointer
= imm_start
;
3934 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3935 if (gotfree_input_line
)
3936 input_line_pointer
= gotfree_input_line
;
3939 exp_seg
= expression (exp
);
3942 if (*input_line_pointer
)
3943 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3945 input_line_pointer
= save_input_line_pointer
;
3947 if (gotfree_input_line
)
3948 free (gotfree_input_line
);
3951 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3953 /* Missing or bad expr becomes absolute 0. */
3954 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3956 exp
->X_op
= O_constant
;
3957 exp
->X_add_number
= 0;
3958 exp
->X_add_symbol
= (symbolS
*) 0;
3959 exp
->X_op_symbol
= (symbolS
*) 0;
3961 else if (exp
->X_op
== O_constant
)
3963 /* Size it properly later. */
3964 i
.types
[this_operand
] |= Imm64
;
3965 /* If BFD64, sign extend val. */
3966 if (!use_rela_relocations
)
3967 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3968 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3970 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3971 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3972 && exp_seg
!= absolute_section
3973 && exp_seg
!= text_section
3974 && exp_seg
!= data_section
3975 && exp_seg
!= bss_section
3976 && exp_seg
!= undefined_section
3977 && !bfd_is_com_section (exp_seg
))
3979 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3985 /* This is an address. The size of the address will be
3986 determined later, depending on destination register,
3987 suffix, or the default for the section. */
3988 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3994 static char *i386_scale
PARAMS ((char *));
4001 char *save
= input_line_pointer
;
4003 input_line_pointer
= scale
;
4004 val
= get_absolute_expression ();
4009 i
.log2_scale_factor
= 0;
4012 i
.log2_scale_factor
= 1;
4015 i
.log2_scale_factor
= 2;
4018 i
.log2_scale_factor
= 3;
4022 char sep
= *input_line_pointer
;
4024 *input_line_pointer
= '\0';
4025 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4027 *input_line_pointer
= sep
;
4028 input_line_pointer
= save
;
4032 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4034 as_warn (_("scale factor of %d without an index register"),
4035 1 << i
.log2_scale_factor
);
4036 #if SCALE1_WHEN_NO_INDEX
4037 i
.log2_scale_factor
= 0;
4040 scale
= input_line_pointer
;
4041 input_line_pointer
= save
;
4045 static int i386_displacement
PARAMS ((char *, char *));
4048 i386_displacement (disp_start
, disp_end
)
4054 char *save_input_line_pointer
;
4056 char *gotfree_input_line
;
4058 int bigdisp
= Disp32
;
4060 if (flag_code
== CODE_64BIT
)
4062 if (i
.prefix
[ADDR_PREFIX
] == 0)
4065 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4067 i
.types
[this_operand
] |= bigdisp
;
4069 exp
= &disp_expressions
[i
.disp_operands
];
4070 i
.op
[this_operand
].disps
= exp
;
4072 save_input_line_pointer
= input_line_pointer
;
4073 input_line_pointer
= disp_start
;
4074 END_STRING_AND_SAVE (disp_end
);
4076 #ifndef GCC_ASM_O_HACK
4077 #define GCC_ASM_O_HACK 0
4080 END_STRING_AND_SAVE (disp_end
+ 1);
4081 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4082 && displacement_string_end
[-1] == '+')
4084 /* This hack is to avoid a warning when using the "o"
4085 constraint within gcc asm statements.
4088 #define _set_tssldt_desc(n,addr,limit,type) \
4089 __asm__ __volatile__ ( \
4091 "movw %w1,2+%0\n\t" \
4093 "movb %b1,4+%0\n\t" \
4094 "movb %4,5+%0\n\t" \
4095 "movb $0,6+%0\n\t" \
4096 "movb %h1,7+%0\n\t" \
4098 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4100 This works great except that the output assembler ends
4101 up looking a bit weird if it turns out that there is
4102 no offset. You end up producing code that looks like:
4115 So here we provide the missing zero. */
4117 *displacement_string_end
= '0';
4121 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
4122 if (gotfree_input_line
)
4123 input_line_pointer
= gotfree_input_line
;
4126 exp_seg
= expression (exp
);
4129 if (*input_line_pointer
)
4130 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4132 RESTORE_END_STRING (disp_end
+ 1);
4134 RESTORE_END_STRING (disp_end
);
4135 input_line_pointer
= save_input_line_pointer
;
4137 if (gotfree_input_line
)
4138 free (gotfree_input_line
);
4141 /* We do this to make sure that the section symbol is in
4142 the symbol table. We will ultimately change the relocation
4143 to be relative to the beginning of the section. */
4144 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4145 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4146 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4148 if (exp
->X_op
!= O_symbol
)
4150 as_bad (_("bad expression used with @%s"),
4151 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4157 if (S_IS_LOCAL (exp
->X_add_symbol
)
4158 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4159 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4160 exp
->X_op
= O_subtract
;
4161 exp
->X_op_symbol
= GOT_symbol
;
4162 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4163 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4164 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4165 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4167 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4170 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4172 /* Missing or bad expr becomes absolute 0. */
4173 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4175 exp
->X_op
= O_constant
;
4176 exp
->X_add_number
= 0;
4177 exp
->X_add_symbol
= (symbolS
*) 0;
4178 exp
->X_op_symbol
= (symbolS
*) 0;
4181 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4182 if (exp
->X_op
!= O_constant
4183 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4184 && exp_seg
!= absolute_section
4185 && exp_seg
!= text_section
4186 && exp_seg
!= data_section
4187 && exp_seg
!= bss_section
4188 && exp_seg
!= undefined_section
4189 && !bfd_is_com_section (exp_seg
))
4191 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4195 else if (flag_code
== CODE_64BIT
)
4196 i
.types
[this_operand
] |= Disp32S
| Disp32
;
4200 static int i386_index_check
PARAMS ((const char *));
4202 /* Make sure the memory operand we've been dealt is valid.
4203 Return 1 on success, 0 on a failure. */
4206 i386_index_check (operand_string
)
4207 const char *operand_string
;
4210 #if INFER_ADDR_PREFIX
4216 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4217 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4219 /* Memory operands of SVME insns are special in that they only allow
4220 rAX as their memory address and ignore any segment override. */
4223 /* SKINIT is even more restrictive: it always requires EAX. */
4224 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4226 else if (flag_code
== CODE_64BIT
)
4227 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4229 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4233 || !(i
.base_reg
->reg_type
& Acc
)
4234 || !(i
.base_reg
->reg_type
& RegXX
)
4236 || (i
.types
[0] & Disp
))
4239 else if (flag_code
== CODE_64BIT
)
4241 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4244 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4245 && (i
.base_reg
->reg_type
!= BaseIndex
4248 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4249 != (RegXX
| BaseIndex
))))
4254 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4258 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4259 != (Reg16
| BaseIndex
)))
4261 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4262 != (Reg16
| BaseIndex
))
4264 && i
.base_reg
->reg_num
< 6
4265 && i
.index_reg
->reg_num
>= 6
4266 && i
.log2_scale_factor
== 0))))
4273 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4275 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4276 != (Reg32
| BaseIndex
))))
4282 #if INFER_ADDR_PREFIX
4283 if (i
.prefix
[ADDR_PREFIX
] == 0)
4285 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4287 /* Change the size of any displacement too. At most one of
4288 Disp16 or Disp32 is set.
4289 FIXME. There doesn't seem to be any real need for separate
4290 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4291 Removing them would probably clean up the code quite a lot. */
4292 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4293 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4298 as_bad (_("`%s' is not a valid base/index expression"),
4302 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4304 flag_code_names
[flag_code
]);
4309 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4313 i386_operand (operand_string
)
4314 char *operand_string
;
4318 char *op_string
= operand_string
;
4320 if (is_space_char (*op_string
))
4323 /* We check for an absolute prefix (differentiating,
4324 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4325 if (*op_string
== ABSOLUTE_PREFIX
)
4328 if (is_space_char (*op_string
))
4330 i
.types
[this_operand
] |= JumpAbsolute
;
4333 /* Check if operand is a register. */
4334 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4335 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4337 /* Check for a segment override by searching for ':' after a
4338 segment register. */
4340 if (is_space_char (*op_string
))
4342 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4347 i
.seg
[i
.mem_operands
] = &es
;
4350 i
.seg
[i
.mem_operands
] = &cs
;
4353 i
.seg
[i
.mem_operands
] = &ss
;
4356 i
.seg
[i
.mem_operands
] = &ds
;
4359 i
.seg
[i
.mem_operands
] = &fs
;
4362 i
.seg
[i
.mem_operands
] = &gs
;
4366 /* Skip the ':' and whitespace. */
4368 if (is_space_char (*op_string
))
4371 if (!is_digit_char (*op_string
)
4372 && !is_identifier_char (*op_string
)
4373 && *op_string
!= '('
4374 && *op_string
!= ABSOLUTE_PREFIX
)
4376 as_bad (_("bad memory operand `%s'"), op_string
);
4379 /* Handle case of %es:*foo. */
4380 if (*op_string
== ABSOLUTE_PREFIX
)
4383 if (is_space_char (*op_string
))
4385 i
.types
[this_operand
] |= JumpAbsolute
;
4387 goto do_memory_reference
;
4391 as_bad (_("junk `%s' after register"), op_string
);
4394 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4395 i
.op
[this_operand
].regs
= r
;
4398 else if (*op_string
== REGISTER_PREFIX
)
4400 as_bad (_("bad register name `%s'"), op_string
);
4403 else if (*op_string
== IMMEDIATE_PREFIX
)
4406 if (i
.types
[this_operand
] & JumpAbsolute
)
4408 as_bad (_("immediate operand illegal with absolute jump"));
4411 if (!i386_immediate (op_string
))
4414 else if (is_digit_char (*op_string
)
4415 || is_identifier_char (*op_string
)
4416 || *op_string
== '(')
4418 /* This is a memory reference of some sort. */
4421 /* Start and end of displacement string expression (if found). */
4422 char *displacement_string_start
;
4423 char *displacement_string_end
;
4425 do_memory_reference
:
4426 if ((i
.mem_operands
== 1
4427 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4428 || i
.mem_operands
== 2)
4430 as_bad (_("too many memory references for `%s'"),
4431 current_templates
->start
->name
);
4435 /* Check for base index form. We detect the base index form by
4436 looking for an ')' at the end of the operand, searching
4437 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4439 base_string
= op_string
+ strlen (op_string
);
4442 if (is_space_char (*base_string
))
4445 /* If we only have a displacement, set-up for it to be parsed later. */
4446 displacement_string_start
= op_string
;
4447 displacement_string_end
= base_string
+ 1;
4449 if (*base_string
== ')')
4452 unsigned int parens_balanced
= 1;
4453 /* We've already checked that the number of left & right ()'s are
4454 equal, so this loop will not be infinite. */
4458 if (*base_string
== ')')
4460 if (*base_string
== '(')
4463 while (parens_balanced
);
4465 temp_string
= base_string
;
4467 /* Skip past '(' and whitespace. */
4469 if (is_space_char (*base_string
))
4472 if (*base_string
== ','
4473 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4474 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4476 displacement_string_end
= temp_string
;
4478 i
.types
[this_operand
] |= BaseIndex
;
4482 base_string
= end_op
;
4483 if (is_space_char (*base_string
))
4487 /* There may be an index reg or scale factor here. */
4488 if (*base_string
== ',')
4491 if (is_space_char (*base_string
))
4494 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4495 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4497 base_string
= end_op
;
4498 if (is_space_char (*base_string
))
4500 if (*base_string
== ',')
4503 if (is_space_char (*base_string
))
4506 else if (*base_string
!= ')')
4508 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4513 else if (*base_string
== REGISTER_PREFIX
)
4515 as_bad (_("bad register name `%s'"), base_string
);
4519 /* Check for scale factor. */
4520 if (*base_string
!= ')')
4522 char *end_scale
= i386_scale (base_string
);
4527 base_string
= end_scale
;
4528 if (is_space_char (*base_string
))
4530 if (*base_string
!= ')')
4532 as_bad (_("expecting `)' after scale factor in `%s'"),
4537 else if (!i
.index_reg
)
4539 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4544 else if (*base_string
!= ')')
4546 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4551 else if (*base_string
== REGISTER_PREFIX
)
4553 as_bad (_("bad register name `%s'"), base_string
);
4558 /* If there's an expression beginning the operand, parse it,
4559 assuming displacement_string_start and
4560 displacement_string_end are meaningful. */
4561 if (displacement_string_start
!= displacement_string_end
)
4563 if (!i386_displacement (displacement_string_start
,
4564 displacement_string_end
))
4568 /* Special case for (%dx) while doing input/output op. */
4570 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4572 && i
.log2_scale_factor
== 0
4573 && i
.seg
[i
.mem_operands
] == 0
4574 && (i
.types
[this_operand
] & Disp
) == 0)
4576 i
.types
[this_operand
] = InOutPortReg
;
4580 if (i386_index_check (operand_string
) == 0)
4586 /* It's not a memory operand; argh! */
4587 as_bad (_("invalid char %s beginning operand %d `%s'"),
4588 output_invalid (*op_string
),
4593 return 1; /* Normal return. */
4596 /* md_estimate_size_before_relax()
4598 Called just before relax() for rs_machine_dependent frags. The x86
4599 assembler uses these frags to handle variable size jump
4602 Any symbol that is now undefined will not become defined.
4603 Return the correct fr_subtype in the frag.
4604 Return the initial "guess for variable size of frag" to caller.
4605 The guess is actually the growth beyond the fixed part. Whatever
4606 we do to grow the fixed or variable part contributes to our
4610 md_estimate_size_before_relax (fragP
, segment
)
4614 /* We've already got fragP->fr_subtype right; all we have to do is
4615 check for un-relaxable symbols. On an ELF system, we can't relax
4616 an externally visible symbol, because it may be overridden by a
4618 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4620 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4621 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4622 || S_IS_WEAK (fragP
->fr_symbol
)))
4626 /* Symbol is undefined in this segment, or we need to keep a
4627 reloc so that weak symbols can be overridden. */
4628 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4629 enum bfd_reloc_code_real reloc_type
;
4630 unsigned char *opcode
;
4633 if (fragP
->fr_var
!= NO_RELOC
)
4634 reloc_type
= fragP
->fr_var
;
4636 reloc_type
= BFD_RELOC_16_PCREL
;
4638 reloc_type
= BFD_RELOC_32_PCREL
;
4640 old_fr_fix
= fragP
->fr_fix
;
4641 opcode
= (unsigned char *) fragP
->fr_opcode
;
4643 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4646 /* Make jmp (0xeb) a (d)word displacement jump. */
4648 fragP
->fr_fix
+= size
;
4649 fix_new (fragP
, old_fr_fix
, size
,
4651 fragP
->fr_offset
, 1,
4657 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4659 /* Negate the condition, and branch past an
4660 unconditional jump. */
4663 /* Insert an unconditional jump. */
4665 /* We added two extra opcode bytes, and have a two byte
4667 fragP
->fr_fix
+= 2 + 2;
4668 fix_new (fragP
, old_fr_fix
+ 2, 2,
4670 fragP
->fr_offset
, 1,
4677 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4682 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4684 fragP
->fr_offset
, 1,
4686 fixP
->fx_signed
= 1;
4690 /* This changes the byte-displacement jump 0x7N
4691 to the (d)word-displacement jump 0x0f,0x8N. */
4692 opcode
[1] = opcode
[0] + 0x10;
4693 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4694 /* We've added an opcode byte. */
4695 fragP
->fr_fix
+= 1 + size
;
4696 fix_new (fragP
, old_fr_fix
+ 1, size
,
4698 fragP
->fr_offset
, 1,
4703 BAD_CASE (fragP
->fr_subtype
);
4707 return fragP
->fr_fix
- old_fr_fix
;
4710 /* Guess size depending on current relax state. Initially the relax
4711 state will correspond to a short jump and we return 1, because
4712 the variable part of the frag (the branch offset) is one byte
4713 long. However, we can relax a section more than once and in that
4714 case we must either set fr_subtype back to the unrelaxed state,
4715 or return the value for the appropriate branch. */
4716 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4719 /* Called after relax() is finished.
4721 In: Address of frag.
4722 fr_type == rs_machine_dependent.
4723 fr_subtype is what the address relaxed to.
4725 Out: Any fixSs and constants are set up.
4726 Caller will turn frag into a ".space 0". */
4729 md_convert_frag (abfd
, sec
, fragP
)
4730 bfd
*abfd ATTRIBUTE_UNUSED
;
4731 segT sec ATTRIBUTE_UNUSED
;
4734 unsigned char *opcode
;
4735 unsigned char *where_to_put_displacement
= NULL
;
4736 offsetT target_address
;
4737 offsetT opcode_address
;
4738 unsigned int extension
= 0;
4739 offsetT displacement_from_opcode_start
;
4741 opcode
= (unsigned char *) fragP
->fr_opcode
;
4743 /* Address we want to reach in file space. */
4744 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4746 /* Address opcode resides at in file space. */
4747 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4749 /* Displacement from opcode start to fill into instruction. */
4750 displacement_from_opcode_start
= target_address
- opcode_address
;
4752 if ((fragP
->fr_subtype
& BIG
) == 0)
4754 /* Don't have to change opcode. */
4755 extension
= 1; /* 1 opcode + 1 displacement */
4756 where_to_put_displacement
= &opcode
[1];
4760 if (no_cond_jump_promotion
4761 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4762 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4764 switch (fragP
->fr_subtype
)
4766 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4767 extension
= 4; /* 1 opcode + 4 displacement */
4769 where_to_put_displacement
= &opcode
[1];
4772 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4773 extension
= 2; /* 1 opcode + 2 displacement */
4775 where_to_put_displacement
= &opcode
[1];
4778 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4779 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4780 extension
= 5; /* 2 opcode + 4 displacement */
4781 opcode
[1] = opcode
[0] + 0x10;
4782 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4783 where_to_put_displacement
= &opcode
[2];
4786 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4787 extension
= 3; /* 2 opcode + 2 displacement */
4788 opcode
[1] = opcode
[0] + 0x10;
4789 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4790 where_to_put_displacement
= &opcode
[2];
4793 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4798 where_to_put_displacement
= &opcode
[3];
4802 BAD_CASE (fragP
->fr_subtype
);
4807 /* Now put displacement after opcode. */
4808 md_number_to_chars ((char *) where_to_put_displacement
,
4809 (valueT
) (displacement_from_opcode_start
- extension
),
4810 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4811 fragP
->fr_fix
+= extension
;
4814 /* Size of byte displacement jmp. */
4815 int md_short_jump_size
= 2;
4817 /* Size of dword displacement jmp. */
4818 int md_long_jump_size
= 5;
4820 /* Size of relocation record. */
4821 const int md_reloc_size
= 8;
4824 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4826 addressT from_addr
, to_addr
;
4827 fragS
*frag ATTRIBUTE_UNUSED
;
4828 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4832 offset
= to_addr
- (from_addr
+ 2);
4833 /* Opcode for byte-disp jump. */
4834 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4835 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4839 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4841 addressT from_addr
, to_addr
;
4842 fragS
*frag ATTRIBUTE_UNUSED
;
4843 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4847 offset
= to_addr
- (from_addr
+ 5);
4848 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4849 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4852 /* Apply a fixup (fixS) to segment data, once it has been determined
4853 by our caller that we have all the info we need to fix it up.
4855 On the 386, immediates, displacements, and data pointers are all in
4856 the same (little-endian) format, so we don't need to care about which
4860 md_apply_fix (fixP
, valP
, seg
)
4861 /* The fix we're to put in. */
4863 /* Pointer to the value of the bits. */
4865 /* Segment fix is from. */
4866 segT seg ATTRIBUTE_UNUSED
;
4868 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4869 valueT value
= *valP
;
4871 #if !defined (TE_Mach)
4874 switch (fixP
->fx_r_type
)
4880 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4883 case BFD_RELOC_X86_64_32S
:
4884 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4887 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4890 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4895 if (fixP
->fx_addsy
!= NULL
4896 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4897 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4898 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4899 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4900 && !use_rela_relocations
)
4902 /* This is a hack. There should be a better way to handle this.
4903 This covers for the fact that bfd_install_relocation will
4904 subtract the current location (for partial_inplace, PC relative
4905 relocations); see more below. */
4907 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4909 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4912 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4915 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4917 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4920 || (symbol_section_p (fixP
->fx_addsy
)
4921 && sym_seg
!= absolute_section
))
4922 && !generic_force_reloc (fixP
))
4924 /* Yes, we add the values in twice. This is because
4925 bfd_install_relocation subtracts them out again. I think
4926 bfd_install_relocation is broken, but I don't dare change
4928 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4932 #if defined (OBJ_COFF) && defined (TE_PE)
4933 /* For some reason, the PE format does not store a
4934 section address offset for a PC relative symbol. */
4935 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4936 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4937 || S_IS_WEAK (fixP
->fx_addsy
)
4940 value
+= md_pcrel_from (fixP
);
4944 /* Fix a few things - the dynamic linker expects certain values here,
4945 and we must not disappoint it. */
4946 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4947 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4949 switch (fixP
->fx_r_type
)
4951 case BFD_RELOC_386_PLT32
:
4952 case BFD_RELOC_X86_64_PLT32
:
4953 /* Make the jump instruction point to the address of the operand. At
4954 runtime we merely add the offset to the actual PLT entry. */
4958 case BFD_RELOC_386_TLS_GD
:
4959 case BFD_RELOC_386_TLS_LDM
:
4960 case BFD_RELOC_386_TLS_IE_32
:
4961 case BFD_RELOC_386_TLS_IE
:
4962 case BFD_RELOC_386_TLS_GOTIE
:
4963 case BFD_RELOC_X86_64_TLSGD
:
4964 case BFD_RELOC_X86_64_TLSLD
:
4965 case BFD_RELOC_X86_64_GOTTPOFF
:
4966 value
= 0; /* Fully resolved at runtime. No addend. */
4968 case BFD_RELOC_386_TLS_LE
:
4969 case BFD_RELOC_386_TLS_LDO_32
:
4970 case BFD_RELOC_386_TLS_LE_32
:
4971 case BFD_RELOC_X86_64_DTPOFF32
:
4972 case BFD_RELOC_X86_64_DTPOFF64
:
4973 case BFD_RELOC_X86_64_TPOFF32
:
4974 case BFD_RELOC_X86_64_TPOFF64
:
4975 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4978 case BFD_RELOC_386_GOT32
:
4979 case BFD_RELOC_X86_64_GOT32
:
4980 value
= 0; /* Fully resolved at runtime. No addend. */
4983 case BFD_RELOC_VTABLE_INHERIT
:
4984 case BFD_RELOC_VTABLE_ENTRY
:
4991 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4993 #endif /* !defined (TE_Mach) */
4995 /* Are we finished with this relocation now? */
4996 if (fixP
->fx_addsy
== NULL
)
4998 else if (use_rela_relocations
)
5000 fixP
->fx_no_overflow
= 1;
5001 /* Remember value for tc_gen_reloc. */
5002 fixP
->fx_addnumber
= value
;
5006 md_number_to_chars (p
, value
, fixP
->fx_size
);
5009 #define MAX_LITTLENUMS 6
5011 /* Turn the string pointed to by litP into a floating point constant
5012 of type TYPE, and emit the appropriate bytes. The number of
5013 LITTLENUMS emitted is stored in *SIZEP. An error message is
5014 returned, or NULL on OK. */
5017 md_atof (type
, litP
, sizeP
)
5023 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5024 LITTLENUM_TYPE
*wordP
;
5046 return _("Bad call to md_atof ()");
5048 t
= atof_ieee (input_line_pointer
, type
, words
);
5050 input_line_pointer
= t
;
5052 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5053 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5054 the bigendian 386. */
5055 for (wordP
= words
+ prec
- 1; prec
--;)
5057 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5058 litP
+= sizeof (LITTLENUM_TYPE
);
5063 static char output_invalid_buf
[8];
5070 sprintf (output_invalid_buf
, "'%c'", c
);
5072 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5073 return output_invalid_buf
;
5076 /* REG_STRING starts *before* REGISTER_PREFIX. */
5078 static const reg_entry
*
5079 parse_register (reg_string
, end_op
)
5083 char *s
= reg_string
;
5085 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5088 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5089 if (*s
== REGISTER_PREFIX
)
5092 if (is_space_char (*s
))
5096 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5098 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5099 return (const reg_entry
*) NULL
;
5103 /* For naked regs, make sure that we are not dealing with an identifier.
5104 This prevents confusing an identifier like `eax_var' with register
5106 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5107 return (const reg_entry
*) NULL
;
5111 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5113 /* Handle floating point regs, allowing spaces in the (i) part. */
5114 if (r
== i386_regtab
/* %st is first entry of table */)
5116 if (is_space_char (*s
))
5121 if (is_space_char (*s
))
5123 if (*s
>= '0' && *s
<= '7')
5125 r
= &i386_float_regtab
[*s
- '0'];
5127 if (is_space_char (*s
))
5135 /* We have "%st(" then garbage. */
5136 return (const reg_entry
*) NULL
;
5141 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5142 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5143 && flag_code
!= CODE_64BIT
)
5144 return (const reg_entry
*) NULL
;
5149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5150 const char *md_shortopts
= "kVQ:sqn";
5152 const char *md_shortopts
= "qn";
5155 struct option md_longopts
[] = {
5156 #define OPTION_32 (OPTION_MD_BASE + 0)
5157 {"32", no_argument
, NULL
, OPTION_32
},
5158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5159 #define OPTION_64 (OPTION_MD_BASE + 1)
5160 {"64", no_argument
, NULL
, OPTION_64
},
5162 {NULL
, no_argument
, NULL
, 0}
5164 size_t md_longopts_size
= sizeof (md_longopts
);
5167 md_parse_option (c
, arg
)
5169 char *arg ATTRIBUTE_UNUSED
;
5174 optimize_align_code
= 0;
5181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5182 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5183 should be emitted or not. FIXME: Not implemented. */
5187 /* -V: SVR4 argument to print version ID. */
5189 print_version_id ();
5192 /* -k: Ignore for FreeBSD compatibility. */
5197 /* -s: On i386 Solaris, this tells the native assembler to use
5198 .stab instead of .stab.excl. We always use .stab anyhow. */
5203 const char **list
, **l
;
5205 list
= bfd_target_list ();
5206 for (l
= list
; *l
!= NULL
; l
++)
5207 if (strcmp (*l
, "elf64-x86-64") == 0)
5209 default_arch
= "x86_64";
5213 as_fatal (_("No compiled in support for x86_64"));
5220 default_arch
= "i386";
5230 md_show_usage (stream
)
5233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5234 fprintf (stream
, _("\
5236 -V print assembler version number\n\
5238 -n Do not optimize code alignment\n\
5239 -q quieten some warnings\n\
5242 fprintf (stream
, _("\
5243 -n Do not optimize code alignment\n\
5244 -q quieten some warnings\n"));
5248 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5249 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5251 /* Pick the target format to use. */
5254 i386_target_format ()
5256 if (!strcmp (default_arch
, "x86_64"))
5257 set_code_flag (CODE_64BIT
);
5258 else if (!strcmp (default_arch
, "i386"))
5259 set_code_flag (CODE_32BIT
);
5261 as_fatal (_("Unknown architecture"));
5262 switch (OUTPUT_FLAVOR
)
5264 #ifdef OBJ_MAYBE_AOUT
5265 case bfd_target_aout_flavour
:
5266 return AOUT_TARGET_FORMAT
;
5268 #ifdef OBJ_MAYBE_COFF
5269 case bfd_target_coff_flavour
:
5272 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5273 case bfd_target_elf_flavour
:
5275 if (flag_code
== CODE_64BIT
)
5276 use_rela_relocations
= 1;
5277 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5286 #endif /* OBJ_MAYBE_ more than one */
5288 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5289 void i386_elf_emit_arch_note ()
5291 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5292 && cpu_arch_name
!= NULL
)
5295 asection
*seg
= now_seg
;
5296 subsegT subseg
= now_subseg
;
5297 Elf_Internal_Note i_note
;
5298 Elf_External_Note e_note
;
5299 asection
*note_secp
;
5302 /* Create the .note section. */
5303 note_secp
= subseg_new (".note", 0);
5304 bfd_set_section_flags (stdoutput
,
5306 SEC_HAS_CONTENTS
| SEC_READONLY
);
5308 /* Process the arch string. */
5309 len
= strlen (cpu_arch_name
);
5311 i_note
.namesz
= len
+ 1;
5313 i_note
.type
= NT_ARCH
;
5314 p
= frag_more (sizeof (e_note
.namesz
));
5315 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5316 p
= frag_more (sizeof (e_note
.descsz
));
5317 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5318 p
= frag_more (sizeof (e_note
.type
));
5319 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5320 p
= frag_more (len
+ 1);
5321 strcpy (p
, cpu_arch_name
);
5323 frag_align (2, 0, 0);
5325 subseg_set (seg
, subseg
);
5331 md_undefined_symbol (name
)
5334 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5335 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5336 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5337 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5341 if (symbol_find (name
))
5342 as_bad (_("GOT already in symbol table"));
5343 GOT_symbol
= symbol_new (name
, undefined_section
,
5344 (valueT
) 0, &zero_address_frag
);
5351 /* Round up a section size to the appropriate boundary. */
5354 md_section_align (segment
, size
)
5355 segT segment ATTRIBUTE_UNUSED
;
5358 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5359 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5361 /* For a.out, force the section size to be aligned. If we don't do
5362 this, BFD will align it for us, but it will not write out the
5363 final bytes of the section. This may be a bug in BFD, but it is
5364 easier to fix it here since that is how the other a.out targets
5368 align
= bfd_get_section_alignment (stdoutput
, segment
);
5369 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5376 /* On the i386, PC-relative offsets are relative to the start of the
5377 next instruction. That is, the address of the offset, plus its
5378 size, since the offset is always the last part of the insn. */
5381 md_pcrel_from (fixP
)
5384 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5391 int ignore ATTRIBUTE_UNUSED
;
5395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5397 obj_elf_section_change_hook ();
5399 temp
= get_absolute_expression ();
5400 subseg_set (bss_section
, (subsegT
) temp
);
5401 demand_empty_rest_of_line ();
5407 i386_validate_fix (fixp
)
5410 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5412 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5414 if (flag_code
!= CODE_64BIT
)
5416 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5420 if (flag_code
!= CODE_64BIT
)
5421 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5423 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5430 tc_gen_reloc (section
, fixp
)
5431 asection
*section ATTRIBUTE_UNUSED
;
5435 bfd_reloc_code_real_type code
;
5437 switch (fixp
->fx_r_type
)
5439 case BFD_RELOC_X86_64_PLT32
:
5440 case BFD_RELOC_X86_64_GOT32
:
5441 case BFD_RELOC_X86_64_GOTPCREL
:
5442 case BFD_RELOC_386_PLT32
:
5443 case BFD_RELOC_386_GOT32
:
5444 case BFD_RELOC_386_GOTOFF
:
5445 case BFD_RELOC_386_GOTPC
:
5446 case BFD_RELOC_386_TLS_GD
:
5447 case BFD_RELOC_386_TLS_LDM
:
5448 case BFD_RELOC_386_TLS_LDO_32
:
5449 case BFD_RELOC_386_TLS_IE_32
:
5450 case BFD_RELOC_386_TLS_IE
:
5451 case BFD_RELOC_386_TLS_GOTIE
:
5452 case BFD_RELOC_386_TLS_LE_32
:
5453 case BFD_RELOC_386_TLS_LE
:
5454 case BFD_RELOC_X86_64_TLSGD
:
5455 case BFD_RELOC_X86_64_TLSLD
:
5456 case BFD_RELOC_X86_64_DTPOFF32
:
5457 case BFD_RELOC_X86_64_DTPOFF64
:
5458 case BFD_RELOC_X86_64_GOTTPOFF
:
5459 case BFD_RELOC_X86_64_TPOFF32
:
5460 case BFD_RELOC_X86_64_TPOFF64
:
5461 case BFD_RELOC_X86_64_GOTOFF64
:
5462 case BFD_RELOC_X86_64_GOTPC32
:
5464 case BFD_RELOC_VTABLE_ENTRY
:
5465 case BFD_RELOC_VTABLE_INHERIT
:
5467 case BFD_RELOC_32_SECREL
:
5469 code
= fixp
->fx_r_type
;
5471 case BFD_RELOC_X86_64_32S
:
5472 if (!fixp
->fx_pcrel
)
5474 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5475 code
= fixp
->fx_r_type
;
5481 switch (fixp
->fx_size
)
5484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5485 _("can not do %d byte pc-relative relocation"),
5487 code
= BFD_RELOC_32_PCREL
;
5489 case 1: code
= BFD_RELOC_8_PCREL
; break;
5490 case 2: code
= BFD_RELOC_16_PCREL
; break;
5491 case 4: code
= BFD_RELOC_32_PCREL
; break;
5493 case 8: code
= BFD_RELOC_64_PCREL
; break;
5499 switch (fixp
->fx_size
)
5502 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5503 _("can not do %d byte relocation"),
5505 code
= BFD_RELOC_32
;
5507 case 1: code
= BFD_RELOC_8
; break;
5508 case 2: code
= BFD_RELOC_16
; break;
5509 case 4: code
= BFD_RELOC_32
; break;
5511 case 8: code
= BFD_RELOC_64
; break;
5518 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5520 && fixp
->fx_addsy
== GOT_symbol
)
5522 if (flag_code
!= CODE_64BIT
)
5523 code
= BFD_RELOC_386_GOTPC
;
5525 code
= BFD_RELOC_X86_64_GOTPC32
;
5528 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5529 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5530 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5532 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5534 if (!use_rela_relocations
)
5536 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5537 vtable entry to be used in the relocation's section offset. */
5538 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5539 rel
->address
= fixp
->fx_offset
;
5543 /* Use the rela in 64bit mode. */
5546 if (!fixp
->fx_pcrel
)
5547 rel
->addend
= fixp
->fx_offset
;
5551 case BFD_RELOC_X86_64_PLT32
:
5552 case BFD_RELOC_X86_64_GOT32
:
5553 case BFD_RELOC_X86_64_GOTPCREL
:
5554 case BFD_RELOC_X86_64_TLSGD
:
5555 case BFD_RELOC_X86_64_TLSLD
:
5556 case BFD_RELOC_X86_64_GOTTPOFF
:
5557 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5560 rel
->addend
= (section
->vma
5562 + fixp
->fx_addnumber
5563 + md_pcrel_from (fixp
));
5568 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5569 if (rel
->howto
== NULL
)
5571 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5572 _("cannot represent relocation type %s"),
5573 bfd_get_reloc_code_name (code
));
5574 /* Set howto to a garbage value so that we can keep going. */
5575 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5576 assert (rel
->howto
!= NULL
);
5583 /* Parse operands using Intel syntax. This implements a recursive descent
5584 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5587 FIXME: We do not recognize the full operand grammar defined in the MASM
5588 documentation. In particular, all the structure/union and
5589 high-level macro operands are missing.
5591 Uppercase words are terminals, lower case words are non-terminals.
5592 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5593 bars '|' denote choices. Most grammar productions are implemented in
5594 functions called 'intel_<production>'.
5596 Initial production is 'expr'.
5602 binOp & | AND | \| | OR | ^ | XOR
5604 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5606 constant digits [[ radixOverride ]]
5608 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5646 => expr expr cmpOp e04
5649 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5650 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5652 hexdigit a | b | c | d | e | f
5653 | A | B | C | D | E | F
5659 mulOp * | / | % | MOD | << | SHL | >> | SHR
5663 register specialRegister
5667 segmentRegister CS | DS | ES | FS | GS | SS
5669 specialRegister CR0 | CR2 | CR3 | CR4
5670 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5671 | TR3 | TR4 | TR5 | TR6 | TR7
5673 We simplify the grammar in obvious places (e.g., register parsing is
5674 done by calling parse_register) and eliminate immediate left recursion
5675 to implement a recursive-descent parser.
5679 expr' cmpOp e04 expr'
5730 /* Parsing structure for the intel syntax parser. Used to implement the
5731 semantic actions for the operand grammar. */
5732 struct intel_parser_s
5734 char *op_string
; /* The string being parsed. */
5735 int got_a_float
; /* Whether the operand is a float. */
5736 int op_modifier
; /* Operand modifier. */
5737 int is_mem
; /* 1 if operand is memory reference. */
5738 int in_offset
; /* >=1 if parsing operand of offset. */
5739 int in_bracket
; /* >=1 if parsing operand in brackets. */
5740 const reg_entry
*reg
; /* Last register reference found. */
5741 char *disp
; /* Displacement string being built. */
5742 char *next_operand
; /* Resume point when splitting operands. */
5745 static struct intel_parser_s intel_parser
;
5747 /* Token structure for parsing intel syntax. */
5750 int code
; /* Token code. */
5751 const reg_entry
*reg
; /* Register entry for register tokens. */
5752 char *str
; /* String representation. */
5755 static struct intel_token cur_token
, prev_token
;
5757 /* Token codes for the intel parser. Since T_SHORT is already used
5758 by COFF, undefine it first to prevent a warning. */
5777 /* Prototypes for intel parser functions. */
5778 static int intel_match_token
PARAMS ((int code
));
5779 static void intel_get_token
PARAMS ((void));
5780 static void intel_putback_token
PARAMS ((void));
5781 static int intel_expr
PARAMS ((void));
5782 static int intel_e04
PARAMS ((void));
5783 static int intel_e05
PARAMS ((void));
5784 static int intel_e06
PARAMS ((void));
5785 static int intel_e09
PARAMS ((void));
5786 static int intel_bracket_expr
PARAMS ((void));
5787 static int intel_e10
PARAMS ((void));
5788 static int intel_e11
PARAMS ((void));
5791 i386_intel_operand (operand_string
, got_a_float
)
5792 char *operand_string
;
5798 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5799 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5803 /* Initialize token holders. */
5804 cur_token
.code
= prev_token
.code
= T_NIL
;
5805 cur_token
.reg
= prev_token
.reg
= NULL
;
5806 cur_token
.str
= prev_token
.str
= NULL
;
5808 /* Initialize parser structure. */
5809 intel_parser
.got_a_float
= got_a_float
;
5810 intel_parser
.op_modifier
= 0;
5811 intel_parser
.is_mem
= 0;
5812 intel_parser
.in_offset
= 0;
5813 intel_parser
.in_bracket
= 0;
5814 intel_parser
.reg
= NULL
;
5815 intel_parser
.disp
[0] = '\0';
5816 intel_parser
.next_operand
= NULL
;
5818 /* Read the first token and start the parser. */
5820 ret
= intel_expr ();
5825 if (cur_token
.code
!= T_NIL
)
5827 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5828 current_templates
->start
->name
, cur_token
.str
);
5831 /* If we found a memory reference, hand it over to i386_displacement
5832 to fill in the rest of the operand fields. */
5833 else if (intel_parser
.is_mem
)
5835 if ((i
.mem_operands
== 1
5836 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5837 || i
.mem_operands
== 2)
5839 as_bad (_("too many memory references for '%s'"),
5840 current_templates
->start
->name
);
5845 char *s
= intel_parser
.disp
;
5848 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5849 /* See the comments in intel_bracket_expr. */
5850 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5852 /* Add the displacement expression. */
5854 ret
= i386_displacement (s
, s
+ strlen (s
));
5857 /* Swap base and index in 16-bit memory operands like
5858 [si+bx]. Since i386_index_check is also used in AT&T
5859 mode we have to do that here. */
5862 && (i
.base_reg
->reg_type
& Reg16
)
5863 && (i
.index_reg
->reg_type
& Reg16
)
5864 && i
.base_reg
->reg_num
>= 6
5865 && i
.index_reg
->reg_num
< 6)
5867 const reg_entry
*base
= i
.index_reg
;
5869 i
.index_reg
= i
.base_reg
;
5872 ret
= i386_index_check (operand_string
);
5877 /* Constant and OFFSET expressions are handled by i386_immediate. */
5878 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5879 || intel_parser
.reg
== NULL
)
5880 ret
= i386_immediate (intel_parser
.disp
);
5882 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5884 if (!ret
|| !intel_parser
.next_operand
)
5886 intel_parser
.op_string
= intel_parser
.next_operand
;
5887 this_operand
= i
.operands
++;
5891 free (intel_parser
.disp
);
5896 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5900 expr' cmpOp e04 expr'
5905 /* XXX Implement the comparison operators. */
5906 return intel_e04 ();
5923 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5924 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5926 if (cur_token
.code
== '+')
5928 else if (cur_token
.code
== '-')
5929 nregs
= NUM_ADDRESS_REGS
;
5933 strcat (intel_parser
.disp
, cur_token
.str
);
5934 intel_match_token (cur_token
.code
);
5945 int nregs
= ~NUM_ADDRESS_REGS
;
5952 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5956 str
[0] = cur_token
.code
;
5958 strcat (intel_parser
.disp
, str
);
5963 intel_match_token (cur_token
.code
);
5968 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5969 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
5980 int nregs
= ~NUM_ADDRESS_REGS
;
5987 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
5991 str
[0] = cur_token
.code
;
5993 strcat (intel_parser
.disp
, str
);
5995 else if (cur_token
.code
== T_SHL
)
5996 strcat (intel_parser
.disp
, "<<");
5997 else if (cur_token
.code
== T_SHR
)
5998 strcat (intel_parser
.disp
, ">>");
6002 intel_match_token (cur_token
.code
);
6007 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6008 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6026 int nregs
= ~NUM_ADDRESS_REGS
;
6031 /* Don't consume constants here. */
6032 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6034 /* Need to look one token ahead - if the next token
6035 is a constant, the current token is its sign. */
6038 intel_match_token (cur_token
.code
);
6039 next_code
= cur_token
.code
;
6040 intel_putback_token ();
6041 if (next_code
== T_CONST
)
6045 /* e09 OFFSET e09 */
6046 if (cur_token
.code
== T_OFFSET
)
6049 ++intel_parser
.in_offset
;
6053 else if (cur_token
.code
== T_SHORT
)
6054 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6057 else if (cur_token
.code
== '+')
6058 strcat (intel_parser
.disp
, "+");
6063 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6069 str
[0] = cur_token
.code
;
6071 strcat (intel_parser
.disp
, str
);
6078 intel_match_token (cur_token
.code
);
6086 /* e09' PTR e10 e09' */
6087 if (cur_token
.code
== T_PTR
)
6091 if (prev_token
.code
== T_BYTE
)
6092 suffix
= BYTE_MNEM_SUFFIX
;
6094 else if (prev_token
.code
== T_WORD
)
6096 if (current_templates
->start
->name
[0] == 'l'
6097 && current_templates
->start
->name
[2] == 's'
6098 && current_templates
->start
->name
[3] == 0)
6099 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6100 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6101 suffix
= SHORT_MNEM_SUFFIX
;
6103 suffix
= WORD_MNEM_SUFFIX
;
6106 else if (prev_token
.code
== T_DWORD
)
6108 if (current_templates
->start
->name
[0] == 'l'
6109 && current_templates
->start
->name
[2] == 's'
6110 && current_templates
->start
->name
[3] == 0)
6111 suffix
= WORD_MNEM_SUFFIX
;
6112 else if (flag_code
== CODE_16BIT
6113 && (current_templates
->start
->opcode_modifier
6114 & (Jump
|JumpDword
|JumpInterSegment
)))
6115 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6116 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6117 suffix
= SHORT_MNEM_SUFFIX
;
6119 suffix
= LONG_MNEM_SUFFIX
;
6122 else if (prev_token
.code
== T_FWORD
)
6124 if (current_templates
->start
->name
[0] == 'l'
6125 && current_templates
->start
->name
[2] == 's'
6126 && current_templates
->start
->name
[3] == 0)
6127 suffix
= LONG_MNEM_SUFFIX
;
6128 else if (!intel_parser
.got_a_float
)
6130 if (flag_code
== CODE_16BIT
)
6131 add_prefix (DATA_PREFIX_OPCODE
);
6132 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6135 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6138 else if (prev_token
.code
== T_QWORD
)
6140 if (intel_parser
.got_a_float
== 1) /* "f..." */
6141 suffix
= LONG_MNEM_SUFFIX
;
6143 suffix
= QWORD_MNEM_SUFFIX
;
6146 else if (prev_token
.code
== T_TBYTE
)
6148 if (intel_parser
.got_a_float
== 1)
6149 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6151 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6154 else if (prev_token
.code
== T_XMMWORD
)
6156 /* XXX ignored for now, but accepted since gcc uses it */
6162 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6166 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6170 else if (i
.suffix
!= suffix
)
6172 as_bad (_("Conflicting operand modifiers"));
6178 /* e09' : e10 e09' */
6179 else if (cur_token
.code
== ':')
6181 if (prev_token
.code
!= T_REG
)
6183 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6184 segment/group identifier (which we don't have), using comma
6185 as the operand separator there is even less consistent, since
6186 there all branches only have a single operand. */
6187 if (this_operand
!= 0
6188 || intel_parser
.in_offset
6189 || intel_parser
.in_bracket
6190 || (!(current_templates
->start
->opcode_modifier
6191 & (Jump
|JumpDword
|JumpInterSegment
))
6192 && !(current_templates
->start
->operand_types
[0]
6194 return intel_match_token (T_NIL
);
6195 /* Remember the start of the 2nd operand and terminate 1st
6197 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6198 another expression), but it gets at least the simplest case
6199 (a plain number or symbol on the left side) right. */
6200 intel_parser
.next_operand
= intel_parser
.op_string
;
6201 *--intel_parser
.op_string
= '\0';
6202 return intel_match_token (':');
6210 intel_match_token (cur_token
.code
);
6216 --intel_parser
.in_offset
;
6219 if (NUM_ADDRESS_REGS
> nregs
)
6221 as_bad (_("Invalid operand to `OFFSET'"));
6224 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6227 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6228 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6233 intel_bracket_expr ()
6235 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6236 const char *start
= intel_parser
.op_string
;
6239 if (i
.op
[this_operand
].regs
)
6240 return intel_match_token (T_NIL
);
6242 intel_match_token ('[');
6244 /* Mark as a memory operand only if it's not already known to be an
6245 offset expression. If it's an offset expression, we need to keep
6247 if (!intel_parser
.in_offset
)
6249 ++intel_parser
.in_bracket
;
6250 /* Unfortunately gas always diverged from MASM in a respect that can't
6251 be easily fixed without risking to break code sequences likely to be
6252 encountered (the testsuite even check for this): MASM doesn't consider
6253 an expression inside brackets unconditionally as a memory reference.
6254 When that is e.g. a constant, an offset expression, or the sum of the
6255 two, this is still taken as a constant load. gas, however, always
6256 treated these as memory references. As a compromise, we'll try to make
6257 offset expressions inside brackets work the MASM way (since that's
6258 less likely to be found in real world code), but make constants alone
6259 continue to work the traditional gas way. In either case, issue a
6261 intel_parser
.op_modifier
&= ~was_offset
;
6264 strcat (intel_parser
.disp
, "[");
6266 /* Add a '+' to the displacement string if necessary. */
6267 if (*intel_parser
.disp
!= '\0'
6268 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6269 strcat (intel_parser
.disp
, "+");
6272 && (len
= intel_parser
.op_string
- start
- 1,
6273 intel_match_token (']')))
6275 /* Preserve brackets when the operand is an offset expression. */
6276 if (intel_parser
.in_offset
)
6277 strcat (intel_parser
.disp
, "]");
6280 --intel_parser
.in_bracket
;
6281 if (i
.base_reg
|| i
.index_reg
)
6282 intel_parser
.is_mem
= 1;
6283 if (!intel_parser
.is_mem
)
6285 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6286 /* Defer the warning until all of the operand was parsed. */
6287 intel_parser
.is_mem
= -1;
6288 else if (!quiet_warnings
)
6289 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6292 intel_parser
.op_modifier
|= was_offset
;
6309 while (cur_token
.code
== '[')
6311 if (!intel_bracket_expr ())
6336 switch (cur_token
.code
)
6340 intel_match_token ('(');
6341 strcat (intel_parser
.disp
, "(");
6343 if (intel_expr () && intel_match_token (')'))
6345 strcat (intel_parser
.disp
, ")");
6352 /* Operands for jump/call inside brackets denote absolute addresses.
6353 XXX This shouldn't be needed anymore (or if it should rather live
6354 in intel_bracket_expr). */
6355 if (current_templates
->start
->opcode_modifier
6356 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6357 i
.types
[this_operand
] |= JumpAbsolute
;
6359 return intel_bracket_expr ();
6364 strcat (intel_parser
.disp
, cur_token
.str
);
6365 intel_match_token (cur_token
.code
);
6367 /* Mark as a memory operand only if it's not already known to be an
6368 offset expression. */
6369 if (!intel_parser
.in_offset
)
6370 intel_parser
.is_mem
= 1;
6377 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6379 intel_match_token (T_REG
);
6381 /* Check for segment change. */
6382 if (cur_token
.code
== ':')
6384 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6386 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6389 else if (i
.seg
[i
.mem_operands
])
6390 as_warn (_("Extra segment override ignored"));
6393 if (!intel_parser
.in_offset
)
6394 intel_parser
.is_mem
= 1;
6395 switch (reg
->reg_num
)
6398 i
.seg
[i
.mem_operands
] = &es
;
6401 i
.seg
[i
.mem_operands
] = &cs
;
6404 i
.seg
[i
.mem_operands
] = &ss
;
6407 i
.seg
[i
.mem_operands
] = &ds
;
6410 i
.seg
[i
.mem_operands
] = &fs
;
6413 i
.seg
[i
.mem_operands
] = &gs
;
6419 /* Not a segment register. Check for register scaling. */
6420 else if (cur_token
.code
== '*')
6422 if (!intel_parser
.in_bracket
)
6424 as_bad (_("Register scaling only allowed in memory operands"));
6428 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6429 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6430 else if (i
.index_reg
)
6431 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6433 /* What follows must be a valid scale. */
6434 intel_match_token ('*');
6436 i
.types
[this_operand
] |= BaseIndex
;
6438 /* Set the scale after setting the register (otherwise,
6439 i386_scale will complain) */
6440 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6442 char *str
, sign
= cur_token
.code
;
6443 intel_match_token (cur_token
.code
);
6444 if (cur_token
.code
!= T_CONST
)
6446 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6450 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6451 strcpy (str
+ 1, cur_token
.str
);
6453 if (!i386_scale (str
))
6457 else if (!i386_scale (cur_token
.str
))
6459 intel_match_token (cur_token
.code
);
6462 /* No scaling. If this is a memory operand, the register is either a
6463 base register (first occurrence) or an index register (second
6465 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6470 else if (!i
.index_reg
)
6474 as_bad (_("Too many register references in memory operand"));
6478 i
.types
[this_operand
] |= BaseIndex
;
6481 /* Offset modifier. Add the register to the displacement string to be
6482 parsed as an immediate expression after we're done. */
6483 else if (intel_parser
.in_offset
)
6485 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6486 strcat (intel_parser
.disp
, reg
->reg_name
);
6489 /* It's neither base nor index nor offset. */
6490 else if (!intel_parser
.is_mem
)
6492 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6493 i
.op
[this_operand
].regs
= reg
;
6498 as_bad (_("Invalid use of register"));
6502 /* Since registers are not part of the displacement string (except
6503 when we're parsing offset operands), we may need to remove any
6504 preceding '+' from the displacement string. */
6505 if (*intel_parser
.disp
!= '\0'
6506 && !intel_parser
.in_offset
)
6508 char *s
= intel_parser
.disp
;
6509 s
+= strlen (s
) - 1;
6532 intel_match_token (cur_token
.code
);
6534 if (cur_token
.code
== T_PTR
)
6537 /* It must have been an identifier. */
6538 intel_putback_token ();
6539 cur_token
.code
= T_ID
;
6545 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6549 /* The identifier represents a memory reference only if it's not
6550 preceded by an offset modifier and if it's not an equate. */
6551 symbolP
= symbol_find(cur_token
.str
);
6552 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6553 intel_parser
.is_mem
= 1;
6561 char *save_str
, sign
= 0;
6563 /* Allow constants that start with `+' or `-'. */
6564 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6566 sign
= cur_token
.code
;
6567 intel_match_token (cur_token
.code
);
6568 if (cur_token
.code
!= T_CONST
)
6570 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6576 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6577 strcpy (save_str
+ !!sign
, cur_token
.str
);
6581 /* Get the next token to check for register scaling. */
6582 intel_match_token (cur_token
.code
);
6584 /* Check if this constant is a scaling factor for an index register. */
6585 if (cur_token
.code
== '*')
6587 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6589 const reg_entry
*reg
= cur_token
.reg
;
6591 if (!intel_parser
.in_bracket
)
6593 as_bad (_("Register scaling only allowed in memory operands"));
6597 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6598 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6599 else if (i
.index_reg
)
6600 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6602 /* The constant is followed by `* reg', so it must be
6605 i
.types
[this_operand
] |= BaseIndex
;
6607 /* Set the scale after setting the register (otherwise,
6608 i386_scale will complain) */
6609 if (!i386_scale (save_str
))
6611 intel_match_token (T_REG
);
6613 /* Since registers are not part of the displacement
6614 string, we may need to remove any preceding '+' from
6615 the displacement string. */
6616 if (*intel_parser
.disp
!= '\0')
6618 char *s
= intel_parser
.disp
;
6619 s
+= strlen (s
) - 1;
6629 /* The constant was not used for register scaling. Since we have
6630 already consumed the token following `*' we now need to put it
6631 back in the stream. */
6632 intel_putback_token ();
6635 /* Add the constant to the displacement string. */
6636 strcat (intel_parser
.disp
, save_str
);
6643 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6647 /* Match the given token against cur_token. If they match, read the next
6648 token from the operand string. */
6650 intel_match_token (code
)
6653 if (cur_token
.code
== code
)
6660 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6665 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6670 const reg_entry
*reg
;
6671 struct intel_token new_token
;
6673 new_token
.code
= T_NIL
;
6674 new_token
.reg
= NULL
;
6675 new_token
.str
= NULL
;
6677 /* Free the memory allocated to the previous token and move
6678 cur_token to prev_token. */
6680 free (prev_token
.str
);
6682 prev_token
= cur_token
;
6684 /* Skip whitespace. */
6685 while (is_space_char (*intel_parser
.op_string
))
6686 intel_parser
.op_string
++;
6688 /* Return an empty token if we find nothing else on the line. */
6689 if (*intel_parser
.op_string
== '\0')
6691 cur_token
= new_token
;
6695 /* The new token cannot be larger than the remainder of the operand
6697 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6698 new_token
.str
[0] = '\0';
6700 if (strchr ("0123456789", *intel_parser
.op_string
))
6702 char *p
= new_token
.str
;
6703 char *q
= intel_parser
.op_string
;
6704 new_token
.code
= T_CONST
;
6706 /* Allow any kind of identifier char to encompass floating point and
6707 hexadecimal numbers. */
6708 while (is_identifier_char (*q
))
6712 /* Recognize special symbol names [0-9][bf]. */
6713 if (strlen (intel_parser
.op_string
) == 2
6714 && (intel_parser
.op_string
[1] == 'b'
6715 || intel_parser
.op_string
[1] == 'f'))
6716 new_token
.code
= T_ID
;
6719 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6720 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6722 new_token
.code
= T_REG
;
6723 new_token
.reg
= reg
;
6725 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6727 new_token
.str
[0] = REGISTER_PREFIX
;
6728 new_token
.str
[1] = '\0';
6731 strcat (new_token
.str
, reg
->reg_name
);
6734 else if (is_identifier_char (*intel_parser
.op_string
))
6736 char *p
= new_token
.str
;
6737 char *q
= intel_parser
.op_string
;
6739 /* A '.' or '$' followed by an identifier char is an identifier.
6740 Otherwise, it's operator '.' followed by an expression. */
6741 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6743 new_token
.code
= '.';
6744 new_token
.str
[0] = '.';
6745 new_token
.str
[1] = '\0';
6749 while (is_identifier_char (*q
) || *q
== '@')
6753 if (strcasecmp (new_token
.str
, "NOT") == 0)
6754 new_token
.code
= '~';
6756 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6757 new_token
.code
= '%';
6759 else if (strcasecmp (new_token
.str
, "AND") == 0)
6760 new_token
.code
= '&';
6762 else if (strcasecmp (new_token
.str
, "OR") == 0)
6763 new_token
.code
= '|';
6765 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6766 new_token
.code
= '^';
6768 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6769 new_token
.code
= T_SHL
;
6771 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6772 new_token
.code
= T_SHR
;
6774 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6775 new_token
.code
= T_BYTE
;
6777 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6778 new_token
.code
= T_WORD
;
6780 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6781 new_token
.code
= T_DWORD
;
6783 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6784 new_token
.code
= T_FWORD
;
6786 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6787 new_token
.code
= T_QWORD
;
6789 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6790 /* XXX remove (gcc still uses it) */
6791 || strcasecmp (new_token
.str
, "XWORD") == 0)
6792 new_token
.code
= T_TBYTE
;
6794 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6795 || strcasecmp (new_token
.str
, "OWORD") == 0)
6796 new_token
.code
= T_XMMWORD
;
6798 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6799 new_token
.code
= T_PTR
;
6801 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6802 new_token
.code
= T_SHORT
;
6804 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6806 new_token
.code
= T_OFFSET
;
6808 /* ??? This is not mentioned in the MASM grammar but gcc
6809 makes use of it with -mintel-syntax. OFFSET may be
6810 followed by FLAT: */
6811 if (strncasecmp (q
, " FLAT:", 6) == 0)
6812 strcat (new_token
.str
, " FLAT:");
6815 /* ??? This is not mentioned in the MASM grammar. */
6816 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6818 new_token
.code
= T_OFFSET
;
6820 strcat (new_token
.str
, ":");
6822 as_bad (_("`:' expected"));
6826 new_token
.code
= T_ID
;
6830 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6832 new_token
.code
= *intel_parser
.op_string
;
6833 new_token
.str
[0] = *intel_parser
.op_string
;
6834 new_token
.str
[1] = '\0';
6837 else if (strchr ("<>", *intel_parser
.op_string
)
6838 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6840 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6841 new_token
.str
[0] = *intel_parser
.op_string
;
6842 new_token
.str
[1] = *intel_parser
.op_string
;
6843 new_token
.str
[2] = '\0';
6847 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6849 intel_parser
.op_string
+= strlen (new_token
.str
);
6850 cur_token
= new_token
;
6853 /* Put cur_token back into the token stream and make cur_token point to
6856 intel_putback_token ()
6858 if (cur_token
.code
!= T_NIL
)
6860 intel_parser
.op_string
-= strlen (cur_token
.str
);
6861 free (cur_token
.str
);
6863 cur_token
= prev_token
;
6865 /* Forget prev_token. */
6866 prev_token
.code
= T_NIL
;
6867 prev_token
.reg
= NULL
;
6868 prev_token
.str
= NULL
;
6872 tc_x86_regname_to_dw2regnum (const char *regname
)
6874 unsigned int regnum
;
6875 unsigned int regnames_count
;
6876 static const char *const regnames_32
[] =
6878 "eax", "ecx", "edx", "ebx",
6879 "esp", "ebp", "esi", "edi",
6880 "eip", "eflags", NULL
,
6881 "st0", "st1", "st2", "st3",
6882 "st4", "st5", "st6", "st7",
6884 "xmm0", "xmm1", "xmm2", "xmm3",
6885 "xmm4", "xmm5", "xmm6", "xmm7",
6886 "mm0", "mm1", "mm2", "mm3",
6887 "mm4", "mm5", "mm6", "mm7"
6889 static const char *const regnames_64
[] =
6891 "rax", "rdx", "rcx", "rbx",
6892 "rsi", "rdi", "rbp", "rsp",
6893 "r8", "r9", "r10", "r11",
6894 "r12", "r13", "r14", "r15",
6896 "xmm0", "xmm1", "xmm2", "xmm3",
6897 "xmm4", "xmm5", "xmm6", "xmm7",
6898 "xmm8", "xmm9", "xmm10", "xmm11",
6899 "xmm12", "xmm13", "xmm14", "xmm15",
6900 "st0", "st1", "st2", "st3",
6901 "st4", "st5", "st6", "st7",
6902 "mm0", "mm1", "mm2", "mm3",
6903 "mm4", "mm5", "mm6", "mm7"
6905 const char *const *regnames
;
6907 if (flag_code
== CODE_64BIT
)
6909 regnames
= regnames_64
;
6910 regnames_count
= ARRAY_SIZE (regnames_64
);
6914 regnames
= regnames_32
;
6915 regnames_count
= ARRAY_SIZE (regnames_32
);
6918 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6919 if (regnames
[regnum
] != NULL
6920 && strcmp (regname
, regnames
[regnum
]) == 0)
6927 tc_x86_frame_initial_instructions (void)
6929 static unsigned int sp_regno
;
6932 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6935 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6936 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6940 i386_elf_section_type (const char *str
, size_t len
)
6942 if (flag_code
== CODE_64BIT
6943 && len
== sizeof ("unwind") - 1
6944 && strncmp (str
, "unwind", 6) == 0)
6945 return SHT_X86_64_UNWIND
;
6952 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6956 expr
.X_op
= O_secrel
;
6957 expr
.X_add_symbol
= symbol
;
6958 expr
.X_add_number
= 0;
6959 emit_expr (&expr
, size
);