1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1018 CPU_BTVER1_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1020 CPU_BTVER2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1022 CPU_8087_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1030 CPU_CMOV_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1032 CPU_FXSR_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE3_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4A_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1044 CPU_SSSE3_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_1_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1053 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX2_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512F_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512CD_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512ER_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512PF_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512DQ_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512BW_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512VL_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1072 CPU_VMFUNC_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1075 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVE_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEOPT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEC_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVES_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 1 },
1089 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1090 CPU_FSGSBASE_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1092 CPU_RDRND_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1094 CPU_F16C_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1096 CPU_BMI2_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1100 CPU_FMA4_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1106 CPU_MOVBE_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1108 CPU_CX16_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_LZCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_POPCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1120 CPU_INVPCID_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1122 CPU_CLFLUSH_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1126 CPU_SYSCALL_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1128 CPU_RDTSCP_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOW_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOWA_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1134 CPU_PADLOCK_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 1 },
1137 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1140 CPU_SSE4A_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1150 CPU_RDSEED_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1152 CPU_PRFCHW_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1154 CPU_SMAP_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1160 CPU_CLFLUSHOPT_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1162 CPU_PREFETCHWT1_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1165 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1166 CPU_CLWB_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512IFMA_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512VBMI_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VBMI2_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VNNI_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BITALG_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1184 CPU_CLZERO_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1186 CPU_MWAITX_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1188 CPU_OSPKE_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1190 CPU_RDPID_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1192 CPU_PTWRITE_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1195 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1196 CPU_SHSTK_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1198 CPU_GFNI_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1200 CPU_VAES_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1202 CPU_VPCLMULQDQ_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1204 CPU_WBNOINVD_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1206 CPU_PCONFIG_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1208 CPU_WAITPKG_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1210 CPU_CLDEMOTE_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1212 CPU_AMX_INT8_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_BF16_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_TILE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1218 CPU_MOVDIRI_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1220 CPU_MOVDIR64B_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1222 CPU_AVX512_BF16_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1224 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1227 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1228 CPU_ENQCMD_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1230 CPU_SERIALIZE_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1232 CPU_RDPRU_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1234 CPU_MCOMMIT_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1236 CPU_SEV_ES_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1238 CPU_TSXLDTRK_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1241 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1242 CPU_WIDEKL_FLAGS
, 0 },
1245 static const noarch_entry cpu_noarch
[] =
1247 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1248 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1249 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1250 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1251 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1252 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1253 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1255 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1256 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1257 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1258 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1259 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1260 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1261 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1279 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1280 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1282 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1283 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1284 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1285 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1288 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1289 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1290 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1291 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1292 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1293 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1294 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1298 /* Like s_lcomm_internal in gas/read.c but the alignment string
1299 is allowed to be optional. */
1302 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1309 && *input_line_pointer
== ',')
1311 align
= parse_align (needs_align
- 1);
1313 if (align
== (addressT
) -1)
1328 bss_alloc (symbolP
, size
, align
);
1333 pe_lcomm (int needs_align
)
1335 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1339 const pseudo_typeS md_pseudo_table
[] =
1341 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1342 {"align", s_align_bytes
, 0},
1344 {"align", s_align_ptwo
, 0},
1346 {"arch", set_cpu_arch
, 0},
1350 {"lcomm", pe_lcomm
, 1},
1352 {"ffloat", float_cons
, 'f'},
1353 {"dfloat", float_cons
, 'd'},
1354 {"tfloat", float_cons
, 'x'},
1356 {"slong", signed_cons
, 4},
1357 {"noopt", s_ignore
, 0},
1358 {"optim", s_ignore
, 0},
1359 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1360 {"code16", set_code_flag
, CODE_16BIT
},
1361 {"code32", set_code_flag
, CODE_32BIT
},
1363 {"code64", set_code_flag
, CODE_64BIT
},
1365 {"intel_syntax", set_intel_syntax
, 1},
1366 {"att_syntax", set_intel_syntax
, 0},
1367 {"intel_mnemonic", set_intel_mnemonic
, 1},
1368 {"att_mnemonic", set_intel_mnemonic
, 0},
1369 {"allow_index_reg", set_allow_index_reg
, 1},
1370 {"disallow_index_reg", set_allow_index_reg
, 0},
1371 {"sse_check", set_check
, 0},
1372 {"operand_check", set_check
, 1},
1373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1374 {"largecomm", handle_large_common
, 0},
1376 {"file", dwarf2_directive_file
, 0},
1377 {"loc", dwarf2_directive_loc
, 0},
1378 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1381 {"secrel32", pe_directive_secrel
, 0},
1386 /* For interface with expression (). */
1387 extern char *input_line_pointer
;
1389 /* Hash table for instruction mnemonic lookup. */
1390 static htab_t op_hash
;
1392 /* Hash table for register lookup. */
1393 static htab_t reg_hash
;
1395 /* Various efficient no-op patterns for aligning code labels.
1396 Note: Don't try to assemble the instructions in the comments.
1397 0L and 0w are not legal. */
1398 static const unsigned char f32_1
[] =
1400 static const unsigned char f32_2
[] =
1401 {0x66,0x90}; /* xchg %ax,%ax */
1402 static const unsigned char f32_3
[] =
1403 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1404 static const unsigned char f32_4
[] =
1405 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1406 static const unsigned char f32_6
[] =
1407 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1408 static const unsigned char f32_7
[] =
1409 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1410 static const unsigned char f16_3
[] =
1411 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1412 static const unsigned char f16_4
[] =
1413 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1414 static const unsigned char jump_disp8
[] =
1415 {0xeb}; /* jmp disp8 */
1416 static const unsigned char jump32_disp32
[] =
1417 {0xe9}; /* jmp disp32 */
1418 static const unsigned char jump16_disp32
[] =
1419 {0x66,0xe9}; /* jmp disp32 */
1420 /* 32-bit NOPs patterns. */
1421 static const unsigned char *const f32_patt
[] = {
1422 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1424 /* 16-bit NOPs patterns. */
1425 static const unsigned char *const f16_patt
[] = {
1426 f32_1
, f32_2
, f16_3
, f16_4
1428 /* nopl (%[re]ax) */
1429 static const unsigned char alt_3
[] =
1431 /* nopl 0(%[re]ax) */
1432 static const unsigned char alt_4
[] =
1433 {0x0f,0x1f,0x40,0x00};
1434 /* nopl 0(%[re]ax,%[re]ax,1) */
1435 static const unsigned char alt_5
[] =
1436 {0x0f,0x1f,0x44,0x00,0x00};
1437 /* nopw 0(%[re]ax,%[re]ax,1) */
1438 static const unsigned char alt_6
[] =
1439 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1440 /* nopl 0L(%[re]ax) */
1441 static const unsigned char alt_7
[] =
1442 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1443 /* nopl 0L(%[re]ax,%[re]ax,1) */
1444 static const unsigned char alt_8
[] =
1445 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1446 /* nopw 0L(%[re]ax,%[re]ax,1) */
1447 static const unsigned char alt_9
[] =
1448 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1449 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1450 static const unsigned char alt_10
[] =
1451 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1452 /* data16 nopw %cs:0L(%eax,%eax,1) */
1453 static const unsigned char alt_11
[] =
1454 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1455 /* 32-bit and 64-bit NOPs patterns. */
1456 static const unsigned char *const alt_patt
[] = {
1457 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1458 alt_9
, alt_10
, alt_11
1461 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1462 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1465 i386_output_nops (char *where
, const unsigned char *const *patt
,
1466 int count
, int max_single_nop_size
)
1469 /* Place the longer NOP first. */
1472 const unsigned char *nops
;
1474 if (max_single_nop_size
< 1)
1476 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1477 max_single_nop_size
);
1481 nops
= patt
[max_single_nop_size
- 1];
1483 /* Use the smaller one if the requsted one isn't available. */
1486 max_single_nop_size
--;
1487 nops
= patt
[max_single_nop_size
- 1];
1490 last
= count
% max_single_nop_size
;
1493 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1494 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1498 nops
= patt
[last
- 1];
1501 /* Use the smaller one plus one-byte NOP if the needed one
1504 nops
= patt
[last
- 1];
1505 memcpy (where
+ offset
, nops
, last
);
1506 where
[offset
+ last
] = *patt
[0];
1509 memcpy (where
+ offset
, nops
, last
);
1514 fits_in_imm7 (offsetT num
)
1516 return (num
& 0x7f) == num
;
1520 fits_in_imm31 (offsetT num
)
1522 return (num
& 0x7fffffff) == num
;
1525 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1526 single NOP instruction LIMIT. */
1529 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1531 const unsigned char *const *patt
= NULL
;
1532 int max_single_nop_size
;
1533 /* Maximum number of NOPs before switching to jump over NOPs. */
1534 int max_number_of_nops
;
1536 switch (fragP
->fr_type
)
1541 case rs_machine_dependent
:
1542 /* Allow NOP padding for jumps and calls. */
1543 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1544 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1551 /* We need to decide which NOP sequence to use for 32bit and
1552 64bit. When -mtune= is used:
1554 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1555 PROCESSOR_GENERIC32, f32_patt will be used.
1556 2. For the rest, alt_patt will be used.
1558 When -mtune= isn't used, alt_patt will be used if
1559 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1562 When -march= or .arch is used, we can't use anything beyond
1563 cpu_arch_isa_flags. */
1565 if (flag_code
== CODE_16BIT
)
1568 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1569 /* Limit number of NOPs to 2 in 16-bit mode. */
1570 max_number_of_nops
= 2;
1574 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1576 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1577 switch (cpu_arch_tune
)
1579 case PROCESSOR_UNKNOWN
:
1580 /* We use cpu_arch_isa_flags to check if we SHOULD
1581 optimize with nops. */
1582 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1587 case PROCESSOR_PENTIUM4
:
1588 case PROCESSOR_NOCONA
:
1589 case PROCESSOR_CORE
:
1590 case PROCESSOR_CORE2
:
1591 case PROCESSOR_COREI7
:
1592 case PROCESSOR_L1OM
:
1593 case PROCESSOR_K1OM
:
1594 case PROCESSOR_GENERIC64
:
1596 case PROCESSOR_ATHLON
:
1598 case PROCESSOR_AMDFAM10
:
1600 case PROCESSOR_ZNVER
:
1604 case PROCESSOR_I386
:
1605 case PROCESSOR_I486
:
1606 case PROCESSOR_PENTIUM
:
1607 case PROCESSOR_PENTIUMPRO
:
1608 case PROCESSOR_IAMCU
:
1609 case PROCESSOR_GENERIC32
:
1616 switch (fragP
->tc_frag_data
.tune
)
1618 case PROCESSOR_UNKNOWN
:
1619 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1620 PROCESSOR_UNKNOWN. */
1624 case PROCESSOR_I386
:
1625 case PROCESSOR_I486
:
1626 case PROCESSOR_PENTIUM
:
1627 case PROCESSOR_IAMCU
:
1629 case PROCESSOR_ATHLON
:
1631 case PROCESSOR_AMDFAM10
:
1633 case PROCESSOR_ZNVER
:
1635 case PROCESSOR_GENERIC32
:
1636 /* We use cpu_arch_isa_flags to check if we CAN optimize
1638 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1643 case PROCESSOR_PENTIUMPRO
:
1644 case PROCESSOR_PENTIUM4
:
1645 case PROCESSOR_NOCONA
:
1646 case PROCESSOR_CORE
:
1647 case PROCESSOR_CORE2
:
1648 case PROCESSOR_COREI7
:
1649 case PROCESSOR_L1OM
:
1650 case PROCESSOR_K1OM
:
1651 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1656 case PROCESSOR_GENERIC64
:
1662 if (patt
== f32_patt
)
1664 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1665 /* Limit number of NOPs to 2 for older processors. */
1666 max_number_of_nops
= 2;
1670 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1671 /* Limit number of NOPs to 7 for newer processors. */
1672 max_number_of_nops
= 7;
1677 limit
= max_single_nop_size
;
1679 if (fragP
->fr_type
== rs_fill_nop
)
1681 /* Output NOPs for .nop directive. */
1682 if (limit
> max_single_nop_size
)
1684 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1685 _("invalid single nop size: %d "
1686 "(expect within [0, %d])"),
1687 limit
, max_single_nop_size
);
1691 else if (fragP
->fr_type
!= rs_machine_dependent
)
1692 fragP
->fr_var
= count
;
1694 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1696 /* Generate jump over NOPs. */
1697 offsetT disp
= count
- 2;
1698 if (fits_in_imm7 (disp
))
1700 /* Use "jmp disp8" if possible. */
1702 where
[0] = jump_disp8
[0];
1708 unsigned int size_of_jump
;
1710 if (flag_code
== CODE_16BIT
)
1712 where
[0] = jump16_disp32
[0];
1713 where
[1] = jump16_disp32
[1];
1718 where
[0] = jump32_disp32
[0];
1722 count
-= size_of_jump
+ 4;
1723 if (!fits_in_imm31 (count
))
1725 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1726 _("jump over nop padding out of range"));
1730 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1731 where
+= size_of_jump
+ 4;
1735 /* Generate multiple NOPs. */
1736 i386_output_nops (where
, patt
, count
, limit
);
1740 operand_type_all_zero (const union i386_operand_type
*x
)
1742 switch (ARRAY_SIZE(x
->array
))
1753 return !x
->array
[0];
1760 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1762 switch (ARRAY_SIZE(x
->array
))
1778 x
->bitfield
.class = ClassNone
;
1779 x
->bitfield
.instance
= InstanceNone
;
1783 operand_type_equal (const union i386_operand_type
*x
,
1784 const union i386_operand_type
*y
)
1786 switch (ARRAY_SIZE(x
->array
))
1789 if (x
->array
[2] != y
->array
[2])
1793 if (x
->array
[1] != y
->array
[1])
1797 return x
->array
[0] == y
->array
[0];
1805 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1807 switch (ARRAY_SIZE(x
->array
))
1822 return !x
->array
[0];
1829 cpu_flags_equal (const union i386_cpu_flags
*x
,
1830 const union i386_cpu_flags
*y
)
1832 switch (ARRAY_SIZE(x
->array
))
1835 if (x
->array
[3] != y
->array
[3])
1839 if (x
->array
[2] != y
->array
[2])
1843 if (x
->array
[1] != y
->array
[1])
1847 return x
->array
[0] == y
->array
[0];
1855 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1857 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1858 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1861 static INLINE i386_cpu_flags
1862 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[3] &= y
.array
[3];
1870 x
.array
[2] &= y
.array
[2];
1873 x
.array
[1] &= y
.array
[1];
1876 x
.array
[0] &= y
.array
[0];
1884 static INLINE i386_cpu_flags
1885 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1887 switch (ARRAY_SIZE (x
.array
))
1890 x
.array
[3] |= y
.array
[3];
1893 x
.array
[2] |= y
.array
[2];
1896 x
.array
[1] |= y
.array
[1];
1899 x
.array
[0] |= y
.array
[0];
1907 static INLINE i386_cpu_flags
1908 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1910 switch (ARRAY_SIZE (x
.array
))
1913 x
.array
[3] &= ~y
.array
[3];
1916 x
.array
[2] &= ~y
.array
[2];
1919 x
.array
[1] &= ~y
.array
[1];
1922 x
.array
[0] &= ~y
.array
[0];
1930 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1932 #define CPU_FLAGS_ARCH_MATCH 0x1
1933 #define CPU_FLAGS_64BIT_MATCH 0x2
1935 #define CPU_FLAGS_PERFECT_MATCH \
1936 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1938 /* Return CPU flags match bits. */
1941 cpu_flags_match (const insn_template
*t
)
1943 i386_cpu_flags x
= t
->cpu_flags
;
1944 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1946 x
.bitfield
.cpu64
= 0;
1947 x
.bitfield
.cpuno64
= 0;
1949 if (cpu_flags_all_zero (&x
))
1951 /* This instruction is available on all archs. */
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1956 /* This instruction is available only on some archs. */
1957 i386_cpu_flags cpu
= cpu_arch_flags
;
1959 /* AVX512VL is no standalone feature - match it and then strip it. */
1960 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1962 x
.bitfield
.cpuavx512vl
= 0;
1964 cpu
= cpu_flags_and (x
, cpu
);
1965 if (!cpu_flags_all_zero (&cpu
))
1967 if (x
.bitfield
.cpuavx
)
1969 /* We need to check a few extra flags with AVX. */
1970 if (cpu
.bitfield
.cpuavx
1971 && (!t
->opcode_modifier
.sse2avx
1972 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1973 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1974 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1975 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1976 match
|= CPU_FLAGS_ARCH_MATCH
;
1978 else if (x
.bitfield
.cpuavx512f
)
1980 /* We need to check a few extra flags with AVX512F. */
1981 if (cpu
.bitfield
.cpuavx512f
1982 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1983 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1984 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1985 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 match
|= CPU_FLAGS_ARCH_MATCH
;
1994 static INLINE i386_operand_type
1995 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1997 if (x
.bitfield
.class != y
.bitfield
.class)
1998 x
.bitfield
.class = ClassNone
;
1999 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2000 x
.bitfield
.instance
= InstanceNone
;
2002 switch (ARRAY_SIZE (x
.array
))
2005 x
.array
[2] &= y
.array
[2];
2008 x
.array
[1] &= y
.array
[1];
2011 x
.array
[0] &= y
.array
[0];
2019 static INLINE i386_operand_type
2020 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2022 gas_assert (y
.bitfield
.class == ClassNone
);
2023 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2025 switch (ARRAY_SIZE (x
.array
))
2028 x
.array
[2] &= ~y
.array
[2];
2031 x
.array
[1] &= ~y
.array
[1];
2034 x
.array
[0] &= ~y
.array
[0];
2042 static INLINE i386_operand_type
2043 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2045 gas_assert (x
.bitfield
.class == ClassNone
||
2046 y
.bitfield
.class == ClassNone
||
2047 x
.bitfield
.class == y
.bitfield
.class);
2048 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2049 y
.bitfield
.instance
== InstanceNone
||
2050 x
.bitfield
.instance
== y
.bitfield
.instance
);
2052 switch (ARRAY_SIZE (x
.array
))
2055 x
.array
[2] |= y
.array
[2];
2058 x
.array
[1] |= y
.array
[1];
2061 x
.array
[0] |= y
.array
[0];
2069 static INLINE i386_operand_type
2070 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2072 gas_assert (y
.bitfield
.class == ClassNone
);
2073 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2075 switch (ARRAY_SIZE (x
.array
))
2078 x
.array
[2] ^= y
.array
[2];
2081 x
.array
[1] ^= y
.array
[1];
2084 x
.array
[0] ^= y
.array
[0];
2092 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2093 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2094 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2095 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2096 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2097 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2098 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2099 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2100 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2101 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2102 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2103 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2104 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2105 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2106 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2107 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2108 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2119 operand_type_check (i386_operand_type t
, enum operand_type c
)
2124 return t
.bitfield
.class == Reg
;
2127 return (t
.bitfield
.imm8
2131 || t
.bitfield
.imm32s
2132 || t
.bitfield
.imm64
);
2135 return (t
.bitfield
.disp8
2136 || t
.bitfield
.disp16
2137 || t
.bitfield
.disp32
2138 || t
.bitfield
.disp32s
2139 || t
.bitfield
.disp64
);
2142 return (t
.bitfield
.disp8
2143 || t
.bitfield
.disp16
2144 || t
.bitfield
.disp32
2145 || t
.bitfield
.disp32s
2146 || t
.bitfield
.disp64
2147 || t
.bitfield
.baseindex
);
2156 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2157 between operand GIVEN and opeand WANTED for instruction template T. */
2160 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2163 return !((i
.types
[given
].bitfield
.byte
2164 && !t
->operand_types
[wanted
].bitfield
.byte
)
2165 || (i
.types
[given
].bitfield
.word
2166 && !t
->operand_types
[wanted
].bitfield
.word
)
2167 || (i
.types
[given
].bitfield
.dword
2168 && !t
->operand_types
[wanted
].bitfield
.dword
)
2169 || (i
.types
[given
].bitfield
.qword
2170 && !t
->operand_types
[wanted
].bitfield
.qword
)
2171 || (i
.types
[given
].bitfield
.tbyte
2172 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2175 /* Return 1 if there is no conflict in SIMD register between operand
2176 GIVEN and opeand WANTED for instruction template T. */
2179 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2182 return !((i
.types
[given
].bitfield
.xmmword
2183 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2184 || (i
.types
[given
].bitfield
.ymmword
2185 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2186 || (i
.types
[given
].bitfield
.zmmword
2187 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2188 || (i
.types
[given
].bitfield
.tmmword
2189 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2192 /* Return 1 if there is no conflict in any size between operand GIVEN
2193 and opeand WANTED for instruction template T. */
2196 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2199 return (match_operand_size (t
, wanted
, given
)
2200 && !((i
.types
[given
].bitfield
.unspecified
2202 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2203 || (i
.types
[given
].bitfield
.fword
2204 && !t
->operand_types
[wanted
].bitfield
.fword
)
2205 /* For scalar opcode templates to allow register and memory
2206 operands at the same time, some special casing is needed
2207 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2208 down-conversion vpmov*. */
2209 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2210 && t
->operand_types
[wanted
].bitfield
.byte
2211 + t
->operand_types
[wanted
].bitfield
.word
2212 + t
->operand_types
[wanted
].bitfield
.dword
2213 + t
->operand_types
[wanted
].bitfield
.qword
2214 > !!t
->opcode_modifier
.broadcast
)
2215 ? (i
.types
[given
].bitfield
.xmmword
2216 || i
.types
[given
].bitfield
.ymmword
2217 || i
.types
[given
].bitfield
.zmmword
)
2218 : !match_simd_size(t
, wanted
, given
))));
2221 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2222 operands for instruction template T, and it has MATCH_REVERSE set if there
2223 is no size conflict on any operands for the template with operands reversed
2224 (and the template allows for reversing in the first place). */
2226 #define MATCH_STRAIGHT 1
2227 #define MATCH_REVERSE 2
2229 static INLINE
unsigned int
2230 operand_size_match (const insn_template
*t
)
2232 unsigned int j
, match
= MATCH_STRAIGHT
;
2234 /* Don't check non-absolute jump instructions. */
2235 if (t
->opcode_modifier
.jump
2236 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2239 /* Check memory and accumulator operand size. */
2240 for (j
= 0; j
< i
.operands
; j
++)
2242 if (i
.types
[j
].bitfield
.class != Reg
2243 && i
.types
[j
].bitfield
.class != RegSIMD
2244 && t
->opcode_modifier
.anysize
)
2247 if (t
->operand_types
[j
].bitfield
.class == Reg
2248 && !match_operand_size (t
, j
, j
))
2254 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2255 && !match_simd_size (t
, j
, j
))
2261 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2262 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2268 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2275 if (!t
->opcode_modifier
.d
)
2279 i
.error
= operand_size_mismatch
;
2283 /* Check reverse. */
2284 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2286 for (j
= 0; j
< i
.operands
; j
++)
2288 unsigned int given
= i
.operands
- j
- 1;
2290 if (t
->operand_types
[j
].bitfield
.class == Reg
2291 && !match_operand_size (t
, j
, given
))
2294 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2295 && !match_simd_size (t
, j
, given
))
2298 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2299 && (!match_operand_size (t
, j
, given
)
2300 || !match_simd_size (t
, j
, given
)))
2303 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2307 return match
| MATCH_REVERSE
;
2311 operand_type_match (i386_operand_type overlap
,
2312 i386_operand_type given
)
2314 i386_operand_type temp
= overlap
;
2316 temp
.bitfield
.unspecified
= 0;
2317 temp
.bitfield
.byte
= 0;
2318 temp
.bitfield
.word
= 0;
2319 temp
.bitfield
.dword
= 0;
2320 temp
.bitfield
.fword
= 0;
2321 temp
.bitfield
.qword
= 0;
2322 temp
.bitfield
.tbyte
= 0;
2323 temp
.bitfield
.xmmword
= 0;
2324 temp
.bitfield
.ymmword
= 0;
2325 temp
.bitfield
.zmmword
= 0;
2326 temp
.bitfield
.tmmword
= 0;
2327 if (operand_type_all_zero (&temp
))
2330 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2334 i
.error
= operand_type_mismatch
;
2338 /* If given types g0 and g1 are registers they must be of the same type
2339 unless the expected operand type register overlap is null.
2340 Some Intel syntax memory operand size checking also happens here. */
2343 operand_type_register_match (i386_operand_type g0
,
2344 i386_operand_type t0
,
2345 i386_operand_type g1
,
2346 i386_operand_type t1
)
2348 if (g0
.bitfield
.class != Reg
2349 && g0
.bitfield
.class != RegSIMD
2350 && (!operand_type_check (g0
, anymem
)
2351 || g0
.bitfield
.unspecified
2352 || (t0
.bitfield
.class != Reg
2353 && t0
.bitfield
.class != RegSIMD
)))
2356 if (g1
.bitfield
.class != Reg
2357 && g1
.bitfield
.class != RegSIMD
2358 && (!operand_type_check (g1
, anymem
)
2359 || g1
.bitfield
.unspecified
2360 || (t1
.bitfield
.class != Reg
2361 && t1
.bitfield
.class != RegSIMD
)))
2364 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2365 && g0
.bitfield
.word
== g1
.bitfield
.word
2366 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2367 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2368 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2369 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2370 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2373 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2374 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2375 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2376 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2377 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2378 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2379 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2382 i
.error
= register_type_mismatch
;
2387 static INLINE
unsigned int
2388 register_number (const reg_entry
*r
)
2390 unsigned int nr
= r
->reg_num
;
2392 if (r
->reg_flags
& RegRex
)
2395 if (r
->reg_flags
& RegVRex
)
2401 static INLINE
unsigned int
2402 mode_from_disp_size (i386_operand_type t
)
2404 if (t
.bitfield
.disp8
)
2406 else if (t
.bitfield
.disp16
2407 || t
.bitfield
.disp32
2408 || t
.bitfield
.disp32s
)
2415 fits_in_signed_byte (addressT num
)
2417 return num
+ 0x80 <= 0xff;
2421 fits_in_unsigned_byte (addressT num
)
2427 fits_in_unsigned_word (addressT num
)
2429 return num
<= 0xffff;
2433 fits_in_signed_word (addressT num
)
2435 return num
+ 0x8000 <= 0xffff;
2439 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2444 return num
+ 0x80000000 <= 0xffffffff;
2446 } /* fits_in_signed_long() */
2449 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2454 return num
<= 0xffffffff;
2456 } /* fits_in_unsigned_long() */
2459 fits_in_disp8 (offsetT num
)
2461 int shift
= i
.memshift
;
2467 mask
= (1 << shift
) - 1;
2469 /* Return 0 if NUM isn't properly aligned. */
2473 /* Check if NUM will fit in 8bit after shift. */
2474 return fits_in_signed_byte (num
>> shift
);
2478 fits_in_imm4 (offsetT num
)
2480 return (num
& 0xf) == num
;
2483 static i386_operand_type
2484 smallest_imm_type (offsetT num
)
2486 i386_operand_type t
;
2488 operand_type_set (&t
, 0);
2489 t
.bitfield
.imm64
= 1;
2491 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2493 /* This code is disabled on the 486 because all the Imm1 forms
2494 in the opcode table are slower on the i486. They're the
2495 versions with the implicitly specified single-position
2496 displacement, which has another syntax if you really want to
2498 t
.bitfield
.imm1
= 1;
2499 t
.bitfield
.imm8
= 1;
2500 t
.bitfield
.imm8s
= 1;
2501 t
.bitfield
.imm16
= 1;
2502 t
.bitfield
.imm32
= 1;
2503 t
.bitfield
.imm32s
= 1;
2505 else if (fits_in_signed_byte (num
))
2507 t
.bitfield
.imm8
= 1;
2508 t
.bitfield
.imm8s
= 1;
2509 t
.bitfield
.imm16
= 1;
2510 t
.bitfield
.imm32
= 1;
2511 t
.bitfield
.imm32s
= 1;
2513 else if (fits_in_unsigned_byte (num
))
2515 t
.bitfield
.imm8
= 1;
2516 t
.bitfield
.imm16
= 1;
2517 t
.bitfield
.imm32
= 1;
2518 t
.bitfield
.imm32s
= 1;
2520 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2522 t
.bitfield
.imm16
= 1;
2523 t
.bitfield
.imm32
= 1;
2524 t
.bitfield
.imm32s
= 1;
2526 else if (fits_in_signed_long (num
))
2528 t
.bitfield
.imm32
= 1;
2529 t
.bitfield
.imm32s
= 1;
2531 else if (fits_in_unsigned_long (num
))
2532 t
.bitfield
.imm32
= 1;
2538 offset_in_range (offsetT val
, int size
)
2544 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2545 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2546 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2548 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2553 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2555 char buf1
[40], buf2
[40];
2557 sprint_value (buf1
, val
);
2558 sprint_value (buf2
, val
& mask
);
2559 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2574 a. PREFIX_EXIST if attempting to add a prefix where one from the
2575 same class already exists.
2576 b. PREFIX_LOCK if lock prefix is added.
2577 c. PREFIX_REP if rep/repne prefix is added.
2578 d. PREFIX_DS if ds prefix is added.
2579 e. PREFIX_OTHER if other prefix is added.
2582 static enum PREFIX_GROUP
2583 add_prefix (unsigned int prefix
)
2585 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2588 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2589 && flag_code
== CODE_64BIT
)
2591 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2592 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2593 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2594 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2605 case DS_PREFIX_OPCODE
:
2608 case CS_PREFIX_OPCODE
:
2609 case ES_PREFIX_OPCODE
:
2610 case FS_PREFIX_OPCODE
:
2611 case GS_PREFIX_OPCODE
:
2612 case SS_PREFIX_OPCODE
:
2616 case REPNE_PREFIX_OPCODE
:
2617 case REPE_PREFIX_OPCODE
:
2622 case LOCK_PREFIX_OPCODE
:
2631 case ADDR_PREFIX_OPCODE
:
2635 case DATA_PREFIX_OPCODE
:
2639 if (i
.prefix
[q
] != 0)
2647 i
.prefix
[q
] |= prefix
;
2650 as_bad (_("same type of prefix used twice"));
2656 update_code_flag (int value
, int check
)
2658 PRINTF_LIKE ((*as_error
));
2660 flag_code
= (enum flag_code
) value
;
2661 if (flag_code
== CODE_64BIT
)
2663 cpu_arch_flags
.bitfield
.cpu64
= 1;
2664 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2668 cpu_arch_flags
.bitfield
.cpu64
= 0;
2669 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2671 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2674 as_error
= as_fatal
;
2677 (*as_error
) (_("64bit mode not supported on `%s'."),
2678 cpu_arch_name
? cpu_arch_name
: default_arch
);
2680 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2683 as_error
= as_fatal
;
2686 (*as_error
) (_("32bit mode not supported on `%s'."),
2687 cpu_arch_name
? cpu_arch_name
: default_arch
);
2689 stackop_size
= '\0';
2693 set_code_flag (int value
)
2695 update_code_flag (value
, 0);
2699 set_16bit_gcc_code_flag (int new_code_flag
)
2701 flag_code
= (enum flag_code
) new_code_flag
;
2702 if (flag_code
!= CODE_16BIT
)
2704 cpu_arch_flags
.bitfield
.cpu64
= 0;
2705 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2706 stackop_size
= LONG_MNEM_SUFFIX
;
2710 set_intel_syntax (int syntax_flag
)
2712 /* Find out if register prefixing is specified. */
2713 int ask_naked_reg
= 0;
2716 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2719 int e
= get_symbol_name (&string
);
2721 if (strcmp (string
, "prefix") == 0)
2723 else if (strcmp (string
, "noprefix") == 0)
2726 as_bad (_("bad argument to syntax directive."));
2727 (void) restore_line_pointer (e
);
2729 demand_empty_rest_of_line ();
2731 intel_syntax
= syntax_flag
;
2733 if (ask_naked_reg
== 0)
2734 allow_naked_reg
= (intel_syntax
2735 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2737 allow_naked_reg
= (ask_naked_reg
< 0);
2739 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2741 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2742 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2743 register_prefix
= allow_naked_reg
? "" : "%";
2747 set_intel_mnemonic (int mnemonic_flag
)
2749 intel_mnemonic
= mnemonic_flag
;
2753 set_allow_index_reg (int flag
)
2755 allow_index_reg
= flag
;
2759 set_check (int what
)
2761 enum check_kind
*kind
;
2766 kind
= &operand_check
;
2777 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2780 int e
= get_symbol_name (&string
);
2782 if (strcmp (string
, "none") == 0)
2784 else if (strcmp (string
, "warning") == 0)
2785 *kind
= check_warning
;
2786 else if (strcmp (string
, "error") == 0)
2787 *kind
= check_error
;
2789 as_bad (_("bad argument to %s_check directive."), str
);
2790 (void) restore_line_pointer (e
);
2793 as_bad (_("missing argument for %s_check directive"), str
);
2795 demand_empty_rest_of_line ();
2799 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2800 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2803 static const char *arch
;
2805 /* Intel LIOM is only supported on ELF. */
2811 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2812 use default_arch. */
2813 arch
= cpu_arch_name
;
2815 arch
= default_arch
;
2818 /* If we are targeting Intel MCU, we must enable it. */
2819 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2820 || new_flag
.bitfield
.cpuiamcu
)
2823 /* If we are targeting Intel L1OM, we must enable it. */
2824 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2825 || new_flag
.bitfield
.cpul1om
)
2828 /* If we are targeting Intel K1OM, we must enable it. */
2829 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2830 || new_flag
.bitfield
.cpuk1om
)
2833 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2838 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2842 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2845 int e
= get_symbol_name (&string
);
2847 i386_cpu_flags flags
;
2849 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2851 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2853 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2857 cpu_arch_name
= cpu_arch
[j
].name
;
2858 cpu_sub_arch_name
= NULL
;
2859 cpu_arch_flags
= cpu_arch
[j
].flags
;
2860 if (flag_code
== CODE_64BIT
)
2862 cpu_arch_flags
.bitfield
.cpu64
= 1;
2863 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2867 cpu_arch_flags
.bitfield
.cpu64
= 0;
2868 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2870 cpu_arch_isa
= cpu_arch
[j
].type
;
2871 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2872 if (!cpu_arch_tune_set
)
2874 cpu_arch_tune
= cpu_arch_isa
;
2875 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2880 flags
= cpu_flags_or (cpu_arch_flags
,
2883 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2885 if (cpu_sub_arch_name
)
2887 char *name
= cpu_sub_arch_name
;
2888 cpu_sub_arch_name
= concat (name
,
2890 (const char *) NULL
);
2894 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2895 cpu_arch_flags
= flags
;
2896 cpu_arch_isa_flags
= flags
;
2900 = cpu_flags_or (cpu_arch_isa_flags
,
2902 (void) restore_line_pointer (e
);
2903 demand_empty_rest_of_line ();
2908 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2910 /* Disable an ISA extension. */
2911 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2912 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2914 flags
= cpu_flags_and_not (cpu_arch_flags
,
2915 cpu_noarch
[j
].flags
);
2916 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2918 if (cpu_sub_arch_name
)
2920 char *name
= cpu_sub_arch_name
;
2921 cpu_sub_arch_name
= concat (name
, string
,
2922 (const char *) NULL
);
2926 cpu_sub_arch_name
= xstrdup (string
);
2927 cpu_arch_flags
= flags
;
2928 cpu_arch_isa_flags
= flags
;
2930 (void) restore_line_pointer (e
);
2931 demand_empty_rest_of_line ();
2935 j
= ARRAY_SIZE (cpu_arch
);
2938 if (j
>= ARRAY_SIZE (cpu_arch
))
2939 as_bad (_("no such architecture: `%s'"), string
);
2941 *input_line_pointer
= e
;
2944 as_bad (_("missing cpu architecture"));
2946 no_cond_jump_promotion
= 0;
2947 if (*input_line_pointer
== ','
2948 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2953 ++input_line_pointer
;
2954 e
= get_symbol_name (&string
);
2956 if (strcmp (string
, "nojumps") == 0)
2957 no_cond_jump_promotion
= 1;
2958 else if (strcmp (string
, "jumps") == 0)
2961 as_bad (_("no such architecture modifier: `%s'"), string
);
2963 (void) restore_line_pointer (e
);
2966 demand_empty_rest_of_line ();
2969 enum bfd_architecture
2972 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2974 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2975 || flag_code
!= CODE_64BIT
)
2976 as_fatal (_("Intel L1OM is 64bit ELF only"));
2977 return bfd_arch_l1om
;
2979 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2981 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2982 || flag_code
!= CODE_64BIT
)
2983 as_fatal (_("Intel K1OM is 64bit ELF only"));
2984 return bfd_arch_k1om
;
2986 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2988 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2989 || flag_code
== CODE_64BIT
)
2990 as_fatal (_("Intel MCU is 32bit ELF only"));
2991 return bfd_arch_iamcu
;
2994 return bfd_arch_i386
;
3000 if (!strncmp (default_arch
, "x86_64", 6))
3002 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3004 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3005 || default_arch
[6] != '\0')
3006 as_fatal (_("Intel L1OM is 64bit ELF only"));
3007 return bfd_mach_l1om
;
3009 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3011 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3012 || default_arch
[6] != '\0')
3013 as_fatal (_("Intel K1OM is 64bit ELF only"));
3014 return bfd_mach_k1om
;
3016 else if (default_arch
[6] == '\0')
3017 return bfd_mach_x86_64
;
3019 return bfd_mach_x64_32
;
3021 else if (!strcmp (default_arch
, "i386")
3022 || !strcmp (default_arch
, "iamcu"))
3024 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3026 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3027 as_fatal (_("Intel MCU is 32bit ELF only"));
3028 return bfd_mach_i386_iamcu
;
3031 return bfd_mach_i386_i386
;
3034 as_fatal (_("unknown architecture"));
3040 /* Support pseudo prefixes like {disp32}. */
3041 lex_type
['{'] = LEX_BEGIN_NAME
;
3043 /* Initialize op_hash hash table. */
3044 op_hash
= str_htab_create ();
3047 const insn_template
*optab
;
3048 templates
*core_optab
;
3050 /* Setup for loop. */
3052 core_optab
= XNEW (templates
);
3053 core_optab
->start
= optab
;
3058 if (optab
->name
== NULL
3059 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3061 /* different name --> ship out current template list;
3062 add to hash table; & begin anew. */
3063 core_optab
->end
= optab
;
3064 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3065 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3067 if (optab
->name
== NULL
)
3069 core_optab
= XNEW (templates
);
3070 core_optab
->start
= optab
;
3075 /* Initialize reg_hash hash table. */
3076 reg_hash
= str_htab_create ();
3078 const reg_entry
*regtab
;
3079 unsigned int regtab_size
= i386_regtab_size
;
3081 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3082 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3083 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3086 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3091 for (c
= 0; c
< 256; c
++)
3096 mnemonic_chars
[c
] = c
;
3097 register_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3100 else if (ISLOWER (c
))
3102 mnemonic_chars
[c
] = c
;
3103 register_chars
[c
] = c
;
3104 operand_chars
[c
] = c
;
3106 else if (ISUPPER (c
))
3108 mnemonic_chars
[c
] = TOLOWER (c
);
3109 register_chars
[c
] = mnemonic_chars
[c
];
3110 operand_chars
[c
] = c
;
3112 else if (c
== '{' || c
== '}')
3114 mnemonic_chars
[c
] = c
;
3115 operand_chars
[c
] = c
;
3117 #ifdef SVR4_COMMENT_CHARS
3118 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3119 operand_chars
[c
] = c
;
3122 if (ISALPHA (c
) || ISDIGIT (c
))
3123 identifier_chars
[c
] = c
;
3126 identifier_chars
[c
] = c
;
3127 operand_chars
[c
] = c
;
3132 identifier_chars
['@'] = '@';
3135 identifier_chars
['?'] = '?';
3136 operand_chars
['?'] = '?';
3138 digit_chars
['-'] = '-';
3139 mnemonic_chars
['_'] = '_';
3140 mnemonic_chars
['-'] = '-';
3141 mnemonic_chars
['.'] = '.';
3142 identifier_chars
['_'] = '_';
3143 identifier_chars
['.'] = '.';
3145 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3146 operand_chars
[(unsigned char) *p
] = *p
;
3149 if (flag_code
== CODE_64BIT
)
3151 #if defined (OBJ_COFF) && defined (TE_PE)
3152 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3155 x86_dwarf2_return_column
= 16;
3157 x86_cie_data_alignment
= -8;
3161 x86_dwarf2_return_column
= 8;
3162 x86_cie_data_alignment
= -4;
3165 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3166 can be turned into BRANCH_PREFIX frag. */
3167 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3172 i386_print_statistics (FILE *file
)
3174 htab_print_statistics (file
, "i386 opcode", op_hash
);
3175 htab_print_statistics (file
, "i386 register", reg_hash
);
3180 /* Debugging routines for md_assemble. */
3181 static void pte (insn_template
*);
3182 static void pt (i386_operand_type
);
3183 static void pe (expressionS
*);
3184 static void ps (symbolS
*);
3187 pi (const char *line
, i386_insn
*x
)
3191 fprintf (stdout
, "%s: template ", line
);
3193 fprintf (stdout
, " address: base %s index %s scale %x\n",
3194 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3195 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3196 x
->log2_scale_factor
);
3197 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3198 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3199 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3200 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3201 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3202 (x
->rex
& REX_W
) != 0,
3203 (x
->rex
& REX_R
) != 0,
3204 (x
->rex
& REX_X
) != 0,
3205 (x
->rex
& REX_B
) != 0);
3206 for (j
= 0; j
< x
->operands
; j
++)
3208 fprintf (stdout
, " #%d: ", j
+ 1);
3210 fprintf (stdout
, "\n");
3211 if (x
->types
[j
].bitfield
.class == Reg
3212 || x
->types
[j
].bitfield
.class == RegMMX
3213 || x
->types
[j
].bitfield
.class == RegSIMD
3214 || x
->types
[j
].bitfield
.class == RegMask
3215 || x
->types
[j
].bitfield
.class == SReg
3216 || x
->types
[j
].bitfield
.class == RegCR
3217 || x
->types
[j
].bitfield
.class == RegDR
3218 || x
->types
[j
].bitfield
.class == RegTR
3219 || x
->types
[j
].bitfield
.class == RegBND
)
3220 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3221 if (operand_type_check (x
->types
[j
], imm
))
3223 if (operand_type_check (x
->types
[j
], disp
))
3224 pe (x
->op
[j
].disps
);
3229 pte (insn_template
*t
)
3232 fprintf (stdout
, " %d operands ", t
->operands
);
3233 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3234 if (t
->extension_opcode
!= None
)
3235 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3236 if (t
->opcode_modifier
.d
)
3237 fprintf (stdout
, "D");
3238 if (t
->opcode_modifier
.w
)
3239 fprintf (stdout
, "W");
3240 fprintf (stdout
, "\n");
3241 for (j
= 0; j
< t
->operands
; j
++)
3243 fprintf (stdout
, " #%d type ", j
+ 1);
3244 pt (t
->operand_types
[j
]);
3245 fprintf (stdout
, "\n");
3252 fprintf (stdout
, " operation %d\n", e
->X_op
);
3253 fprintf (stdout
, " add_number %ld (%lx)\n",
3254 (long) e
->X_add_number
, (long) e
->X_add_number
);
3255 if (e
->X_add_symbol
)
3257 fprintf (stdout
, " add_symbol ");
3258 ps (e
->X_add_symbol
);
3259 fprintf (stdout
, "\n");
3263 fprintf (stdout
, " op_symbol ");
3264 ps (e
->X_op_symbol
);
3265 fprintf (stdout
, "\n");
3272 fprintf (stdout
, "%s type %s%s",
3274 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3275 segment_name (S_GET_SEGMENT (s
)));
3278 static struct type_name
3280 i386_operand_type mask
;
3283 const type_names
[] =
3285 { OPERAND_TYPE_REG8
, "r8" },
3286 { OPERAND_TYPE_REG16
, "r16" },
3287 { OPERAND_TYPE_REG32
, "r32" },
3288 { OPERAND_TYPE_REG64
, "r64" },
3289 { OPERAND_TYPE_ACC8
, "acc8" },
3290 { OPERAND_TYPE_ACC16
, "acc16" },
3291 { OPERAND_TYPE_ACC32
, "acc32" },
3292 { OPERAND_TYPE_ACC64
, "acc64" },
3293 { OPERAND_TYPE_IMM8
, "i8" },
3294 { OPERAND_TYPE_IMM8
, "i8s" },
3295 { OPERAND_TYPE_IMM16
, "i16" },
3296 { OPERAND_TYPE_IMM32
, "i32" },
3297 { OPERAND_TYPE_IMM32S
, "i32s" },
3298 { OPERAND_TYPE_IMM64
, "i64" },
3299 { OPERAND_TYPE_IMM1
, "i1" },
3300 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3301 { OPERAND_TYPE_DISP8
, "d8" },
3302 { OPERAND_TYPE_DISP16
, "d16" },
3303 { OPERAND_TYPE_DISP32
, "d32" },
3304 { OPERAND_TYPE_DISP32S
, "d32s" },
3305 { OPERAND_TYPE_DISP64
, "d64" },
3306 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3307 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3308 { OPERAND_TYPE_CONTROL
, "control reg" },
3309 { OPERAND_TYPE_TEST
, "test reg" },
3310 { OPERAND_TYPE_DEBUG
, "debug reg" },
3311 { OPERAND_TYPE_FLOATREG
, "FReg" },
3312 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3313 { OPERAND_TYPE_SREG
, "SReg" },
3314 { OPERAND_TYPE_REGMMX
, "rMMX" },
3315 { OPERAND_TYPE_REGXMM
, "rXMM" },
3316 { OPERAND_TYPE_REGYMM
, "rYMM" },
3317 { OPERAND_TYPE_REGZMM
, "rZMM" },
3318 { OPERAND_TYPE_REGTMM
, "rTMM" },
3319 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3323 pt (i386_operand_type t
)
3326 i386_operand_type a
;
3328 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3330 a
= operand_type_and (t
, type_names
[j
].mask
);
3331 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3332 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3337 #endif /* DEBUG386 */
3339 static bfd_reloc_code_real_type
3340 reloc (unsigned int size
,
3343 bfd_reloc_code_real_type other
)
3345 if (other
!= NO_RELOC
)
3347 reloc_howto_type
*rel
;
3352 case BFD_RELOC_X86_64_GOT32
:
3353 return BFD_RELOC_X86_64_GOT64
;
3355 case BFD_RELOC_X86_64_GOTPLT64
:
3356 return BFD_RELOC_X86_64_GOTPLT64
;
3358 case BFD_RELOC_X86_64_PLTOFF64
:
3359 return BFD_RELOC_X86_64_PLTOFF64
;
3361 case BFD_RELOC_X86_64_GOTPC32
:
3362 other
= BFD_RELOC_X86_64_GOTPC64
;
3364 case BFD_RELOC_X86_64_GOTPCREL
:
3365 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3367 case BFD_RELOC_X86_64_TPOFF32
:
3368 other
= BFD_RELOC_X86_64_TPOFF64
;
3370 case BFD_RELOC_X86_64_DTPOFF32
:
3371 other
= BFD_RELOC_X86_64_DTPOFF64
;
3377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3378 if (other
== BFD_RELOC_SIZE32
)
3381 other
= BFD_RELOC_SIZE64
;
3384 as_bad (_("there are no pc-relative size relocations"));
3390 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3391 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3394 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3396 as_bad (_("unknown relocation (%u)"), other
);
3397 else if (size
!= bfd_get_reloc_size (rel
))
3398 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3399 bfd_get_reloc_size (rel
),
3401 else if (pcrel
&& !rel
->pc_relative
)
3402 as_bad (_("non-pc-relative relocation for pc-relative field"));
3403 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3405 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3407 as_bad (_("relocated field and relocation type differ in signedness"));
3416 as_bad (_("there are no unsigned pc-relative relocations"));
3419 case 1: return BFD_RELOC_8_PCREL
;
3420 case 2: return BFD_RELOC_16_PCREL
;
3421 case 4: return BFD_RELOC_32_PCREL
;
3422 case 8: return BFD_RELOC_64_PCREL
;
3424 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3431 case 4: return BFD_RELOC_X86_64_32S
;
3436 case 1: return BFD_RELOC_8
;
3437 case 2: return BFD_RELOC_16
;
3438 case 4: return BFD_RELOC_32
;
3439 case 8: return BFD_RELOC_64
;
3441 as_bad (_("cannot do %s %u byte relocation"),
3442 sign
> 0 ? "signed" : "unsigned", size
);
3448 /* Here we decide which fixups can be adjusted to make them relative to
3449 the beginning of the section instead of the symbol. Basically we need
3450 to make sure that the dynamic relocations are done correctly, so in
3451 some cases we force the original symbol to be used. */
3454 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3456 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3460 /* Don't adjust pc-relative references to merge sections in 64-bit
3462 if (use_rela_relocations
3463 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3467 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3468 and changed later by validate_fix. */
3469 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3470 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3473 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3474 for size relocations. */
3475 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3476 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3477 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3478 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3479 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3480 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3481 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3485 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3486 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3487 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3488 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3489 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3499 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3500 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3504 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3505 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3512 intel_float_operand (const char *mnemonic
)
3514 /* Note that the value returned is meaningful only for opcodes with (memory)
3515 operands, hence the code here is free to improperly handle opcodes that
3516 have no operands (for better performance and smaller code). */
3518 if (mnemonic
[0] != 'f')
3519 return 0; /* non-math */
3521 switch (mnemonic
[1])
3523 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3524 the fs segment override prefix not currently handled because no
3525 call path can make opcodes without operands get here */
3527 return 2 /* integer op */;
3529 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3530 return 3; /* fldcw/fldenv */
3533 if (mnemonic
[2] != 'o' /* fnop */)
3534 return 3; /* non-waiting control op */
3537 if (mnemonic
[2] == 's')
3538 return 3; /* frstor/frstpm */
3541 if (mnemonic
[2] == 'a')
3542 return 3; /* fsave */
3543 if (mnemonic
[2] == 't')
3545 switch (mnemonic
[3])
3547 case 'c': /* fstcw */
3548 case 'd': /* fstdw */
3549 case 'e': /* fstenv */
3550 case 's': /* fsts[gw] */
3556 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3557 return 0; /* fxsave/fxrstor are not really math ops */
3564 /* Build the VEX prefix. */
3567 build_vex_prefix (const insn_template
*t
)
3569 unsigned int register_specifier
;
3570 unsigned int implied_prefix
;
3571 unsigned int vector_length
;
3574 /* Check register specifier. */
3575 if (i
.vex
.register_specifier
)
3577 register_specifier
=
3578 ~register_number (i
.vex
.register_specifier
) & 0xf;
3579 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3582 register_specifier
= 0xf;
3584 /* Use 2-byte VEX prefix by swapping destination and source operand
3585 if there are more than 1 register operand. */
3586 if (i
.reg_operands
> 1
3587 && i
.vec_encoding
!= vex_encoding_vex3
3588 && i
.dir_encoding
== dir_encoding_default
3589 && i
.operands
== i
.reg_operands
3590 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3591 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3592 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3595 unsigned int xchg
= i
.operands
- 1;
3596 union i386_op temp_op
;
3597 i386_operand_type temp_type
;
3599 temp_type
= i
.types
[xchg
];
3600 i
.types
[xchg
] = i
.types
[0];
3601 i
.types
[0] = temp_type
;
3602 temp_op
= i
.op
[xchg
];
3603 i
.op
[xchg
] = i
.op
[0];
3606 gas_assert (i
.rm
.mode
== 3);
3610 i
.rm
.regmem
= i
.rm
.reg
;
3613 if (i
.tm
.opcode_modifier
.d
)
3614 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3615 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3616 else /* Use the next insn. */
3620 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3621 are no memory operands and at least 3 register ones. */
3622 if (i
.reg_operands
>= 3
3623 && i
.vec_encoding
!= vex_encoding_vex3
3624 && i
.reg_operands
== i
.operands
- i
.imm_operands
3625 && i
.tm
.opcode_modifier
.vex
3626 && i
.tm
.opcode_modifier
.commutative
3627 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3629 && i
.vex
.register_specifier
3630 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3632 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3633 union i386_op temp_op
;
3634 i386_operand_type temp_type
;
3636 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3637 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3638 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3639 &i
.types
[i
.operands
- 3]));
3640 gas_assert (i
.rm
.mode
== 3);
3642 temp_type
= i
.types
[xchg
];
3643 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3644 i
.types
[xchg
+ 1] = temp_type
;
3645 temp_op
= i
.op
[xchg
];
3646 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3647 i
.op
[xchg
+ 1] = temp_op
;
3650 xchg
= i
.rm
.regmem
| 8;
3651 i
.rm
.regmem
= ~register_specifier
& 0xf;
3652 gas_assert (!(i
.rm
.regmem
& 8));
3653 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3654 register_specifier
= ~xchg
& 0xf;
3657 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3658 vector_length
= avxscalar
;
3659 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3665 /* Determine vector length from the last multi-length vector
3668 for (op
= t
->operands
; op
--;)
3669 if (t
->operand_types
[op
].bitfield
.xmmword
3670 && t
->operand_types
[op
].bitfield
.ymmword
3671 && i
.types
[op
].bitfield
.ymmword
)
3678 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3683 case DATA_PREFIX_OPCODE
:
3686 case REPE_PREFIX_OPCODE
:
3689 case REPNE_PREFIX_OPCODE
:
3696 /* Check the REX.W bit and VEXW. */
3697 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3698 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3699 else if (i
.tm
.opcode_modifier
.vexw
)
3700 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3702 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3704 /* Use 2-byte VEX prefix if possible. */
3706 && i
.vec_encoding
!= vex_encoding_vex3
3707 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3708 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3710 /* 2-byte VEX prefix. */
3714 i
.vex
.bytes
[0] = 0xc5;
3716 /* Check the REX.R bit. */
3717 r
= (i
.rex
& REX_R
) ? 0 : 1;
3718 i
.vex
.bytes
[1] = (r
<< 7
3719 | register_specifier
<< 3
3720 | vector_length
<< 2
3725 /* 3-byte VEX prefix. */
3730 switch (i
.tm
.opcode_modifier
.vexopcode
)
3734 i
.vex
.bytes
[0] = 0xc4;
3738 i
.vex
.bytes
[0] = 0xc4;
3742 i
.vex
.bytes
[0] = 0xc4;
3746 i
.vex
.bytes
[0] = 0x8f;
3750 i
.vex
.bytes
[0] = 0x8f;
3754 i
.vex
.bytes
[0] = 0x8f;
3760 /* The high 3 bits of the second VEX byte are 1's compliment
3761 of RXB bits from REX. */
3762 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3764 i
.vex
.bytes
[2] = (w
<< 7
3765 | register_specifier
<< 3
3766 | vector_length
<< 2
3771 static INLINE bfd_boolean
3772 is_evex_encoding (const insn_template
*t
)
3774 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3775 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3776 || t
->opcode_modifier
.sae
;
3779 static INLINE bfd_boolean
3780 is_any_vex_encoding (const insn_template
*t
)
3782 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3783 || is_evex_encoding (t
);
3786 /* Build the EVEX prefix. */
3789 build_evex_prefix (void)
3791 unsigned int register_specifier
;
3792 unsigned int implied_prefix
;
3794 rex_byte vrex_used
= 0;
3796 /* Check register specifier. */
3797 if (i
.vex
.register_specifier
)
3799 gas_assert ((i
.vrex
& REX_X
) == 0);
3801 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3802 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3803 register_specifier
+= 8;
3804 /* The upper 16 registers are encoded in the fourth byte of the
3806 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3807 i
.vex
.bytes
[3] = 0x8;
3808 register_specifier
= ~register_specifier
& 0xf;
3812 register_specifier
= 0xf;
3814 /* Encode upper 16 vector index register in the fourth byte of
3816 if (!(i
.vrex
& REX_X
))
3817 i
.vex
.bytes
[3] = 0x8;
3822 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3827 case DATA_PREFIX_OPCODE
:
3830 case REPE_PREFIX_OPCODE
:
3833 case REPNE_PREFIX_OPCODE
:
3840 /* 4 byte EVEX prefix. */
3842 i
.vex
.bytes
[0] = 0x62;
3845 switch (i
.tm
.opcode_modifier
.vexopcode
)
3861 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3863 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3865 /* The fifth bit of the second EVEX byte is 1's compliment of the
3866 REX_R bit in VREX. */
3867 if (!(i
.vrex
& REX_R
))
3868 i
.vex
.bytes
[1] |= 0x10;
3872 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3874 /* When all operands are registers, the REX_X bit in REX is not
3875 used. We reuse it to encode the upper 16 registers, which is
3876 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3877 as 1's compliment. */
3878 if ((i
.vrex
& REX_B
))
3881 i
.vex
.bytes
[1] &= ~0x40;
3885 /* EVEX instructions shouldn't need the REX prefix. */
3886 i
.vrex
&= ~vrex_used
;
3887 gas_assert (i
.vrex
== 0);
3889 /* Check the REX.W bit and VEXW. */
3890 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3891 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3892 else if (i
.tm
.opcode_modifier
.vexw
)
3893 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3895 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3897 /* Encode the U bit. */
3898 implied_prefix
|= 0x4;
3900 /* The third byte of the EVEX prefix. */
3901 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3903 /* The fourth byte of the EVEX prefix. */
3904 /* The zeroing-masking bit. */
3905 if (i
.mask
&& i
.mask
->zeroing
)
3906 i
.vex
.bytes
[3] |= 0x80;
3908 /* Don't always set the broadcast bit if there is no RC. */
3911 /* Encode the vector length. */
3912 unsigned int vec_length
;
3914 if (!i
.tm
.opcode_modifier
.evex
3915 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3919 /* Determine vector length from the last multi-length vector
3921 for (op
= i
.operands
; op
--;)
3922 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3923 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3924 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3926 if (i
.types
[op
].bitfield
.zmmword
)
3928 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3931 else if (i
.types
[op
].bitfield
.ymmword
)
3933 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3936 else if (i
.types
[op
].bitfield
.xmmword
)
3938 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3941 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3943 switch (i
.broadcast
->bytes
)
3946 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3949 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3952 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3961 if (op
>= MAX_OPERANDS
)
3965 switch (i
.tm
.opcode_modifier
.evex
)
3967 case EVEXLIG
: /* LL' is ignored */
3968 vec_length
= evexlig
<< 5;
3971 vec_length
= 0 << 5;
3974 vec_length
= 1 << 5;
3977 vec_length
= 2 << 5;
3983 i
.vex
.bytes
[3] |= vec_length
;
3984 /* Encode the broadcast bit. */
3986 i
.vex
.bytes
[3] |= 0x10;
3990 if (i
.rounding
->type
!= saeonly
)
3991 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3993 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3996 if (i
.mask
&& i
.mask
->mask
)
3997 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4001 process_immext (void)
4005 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4006 which is coded in the same place as an 8-bit immediate field
4007 would be. Here we fake an 8-bit immediate operand from the
4008 opcode suffix stored in tm.extension_opcode.
4010 AVX instructions also use this encoding, for some of
4011 3 argument instructions. */
4013 gas_assert (i
.imm_operands
<= 1
4015 || (is_any_vex_encoding (&i
.tm
)
4016 && i
.operands
<= 4)));
4018 exp
= &im_expressions
[i
.imm_operands
++];
4019 i
.op
[i
.operands
].imms
= exp
;
4020 i
.types
[i
.operands
] = imm8
;
4022 exp
->X_op
= O_constant
;
4023 exp
->X_add_number
= i
.tm
.extension_opcode
;
4024 i
.tm
.extension_opcode
= None
;
4031 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4036 as_bad (_("invalid instruction `%s' after `%s'"),
4037 i
.tm
.name
, i
.hle_prefix
);
4040 if (i
.prefix
[LOCK_PREFIX
])
4042 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4046 case HLEPrefixRelease
:
4047 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4049 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4053 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4055 as_bad (_("memory destination needed for instruction `%s'"
4056 " after `xrelease'"), i
.tm
.name
);
4063 /* Try the shortest encoding by shortening operand size. */
4066 optimize_encoding (void)
4070 if (optimize_for_space
4071 && !is_any_vex_encoding (&i
.tm
)
4072 && i
.reg_operands
== 1
4073 && i
.imm_operands
== 1
4074 && !i
.types
[1].bitfield
.byte
4075 && i
.op
[0].imms
->X_op
== O_constant
4076 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4077 && (i
.tm
.base_opcode
== 0xa8
4078 || (i
.tm
.base_opcode
== 0xf6
4079 && i
.tm
.extension_opcode
== 0x0)))
4082 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4084 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4085 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4087 i
.types
[1].bitfield
.byte
= 1;
4088 /* Ignore the suffix. */
4090 /* Convert to byte registers. */
4091 if (i
.types
[1].bitfield
.word
)
4093 else if (i
.types
[1].bitfield
.dword
)
4097 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4102 else if (flag_code
== CODE_64BIT
4103 && !is_any_vex_encoding (&i
.tm
)
4104 && ((i
.types
[1].bitfield
.qword
4105 && i
.reg_operands
== 1
4106 && i
.imm_operands
== 1
4107 && i
.op
[0].imms
->X_op
== O_constant
4108 && ((i
.tm
.base_opcode
== 0xb8
4109 && i
.tm
.extension_opcode
== None
4110 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4111 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4112 && ((i
.tm
.base_opcode
== 0x24
4113 || i
.tm
.base_opcode
== 0xa8)
4114 || (i
.tm
.base_opcode
== 0x80
4115 && i
.tm
.extension_opcode
== 0x4)
4116 || ((i
.tm
.base_opcode
== 0xf6
4117 || (i
.tm
.base_opcode
| 1) == 0xc7)
4118 && i
.tm
.extension_opcode
== 0x0)))
4119 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4120 && i
.tm
.base_opcode
== 0x83
4121 && i
.tm
.extension_opcode
== 0x4)))
4122 || (i
.types
[0].bitfield
.qword
4123 && ((i
.reg_operands
== 2
4124 && i
.op
[0].regs
== i
.op
[1].regs
4125 && (i
.tm
.base_opcode
== 0x30
4126 || i
.tm
.base_opcode
== 0x28))
4127 || (i
.reg_operands
== 1
4129 && i
.tm
.base_opcode
== 0x30)))))
4132 andq $imm31, %r64 -> andl $imm31, %r32
4133 andq $imm7, %r64 -> andl $imm7, %r32
4134 testq $imm31, %r64 -> testl $imm31, %r32
4135 xorq %r64, %r64 -> xorl %r32, %r32
4136 subq %r64, %r64 -> subl %r32, %r32
4137 movq $imm31, %r64 -> movl $imm31, %r32
4138 movq $imm32, %r64 -> movl $imm32, %r32
4140 i
.tm
.opcode_modifier
.norex64
= 1;
4141 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4144 movq $imm31, %r64 -> movl $imm31, %r32
4145 movq $imm32, %r64 -> movl $imm32, %r32
4147 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4148 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4149 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4150 i
.types
[0].bitfield
.imm32
= 1;
4151 i
.types
[0].bitfield
.imm32s
= 0;
4152 i
.types
[0].bitfield
.imm64
= 0;
4153 i
.types
[1].bitfield
.dword
= 1;
4154 i
.types
[1].bitfield
.qword
= 0;
4155 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4158 movq $imm31, %r64 -> movl $imm31, %r32
4160 i
.tm
.base_opcode
= 0xb8;
4161 i
.tm
.extension_opcode
= None
;
4162 i
.tm
.opcode_modifier
.w
= 0;
4163 i
.tm
.opcode_modifier
.modrm
= 0;
4167 else if (optimize
> 1
4168 && !optimize_for_space
4169 && !is_any_vex_encoding (&i
.tm
)
4170 && i
.reg_operands
== 2
4171 && i
.op
[0].regs
== i
.op
[1].regs
4172 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4173 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4174 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4177 andb %rN, %rN -> testb %rN, %rN
4178 andw %rN, %rN -> testw %rN, %rN
4179 andq %rN, %rN -> testq %rN, %rN
4180 orb %rN, %rN -> testb %rN, %rN
4181 orw %rN, %rN -> testw %rN, %rN
4182 orq %rN, %rN -> testq %rN, %rN
4184 and outside of 64-bit mode
4186 andl %rN, %rN -> testl %rN, %rN
4187 orl %rN, %rN -> testl %rN, %rN
4189 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4191 else if (i
.reg_operands
== 3
4192 && i
.op
[0].regs
== i
.op
[1].regs
4193 && !i
.types
[2].bitfield
.xmmword
4194 && (i
.tm
.opcode_modifier
.vex
4195 || ((!i
.mask
|| i
.mask
->zeroing
)
4197 && is_evex_encoding (&i
.tm
)
4198 && (i
.vec_encoding
!= vex_encoding_evex
4199 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4200 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4201 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4202 && i
.types
[2].bitfield
.ymmword
))))
4203 && ((i
.tm
.base_opcode
== 0x55
4204 || i
.tm
.base_opcode
== 0x6655
4205 || i
.tm
.base_opcode
== 0x66df
4206 || i
.tm
.base_opcode
== 0x57
4207 || i
.tm
.base_opcode
== 0x6657
4208 || i
.tm
.base_opcode
== 0x66ef
4209 || i
.tm
.base_opcode
== 0x66f8
4210 || i
.tm
.base_opcode
== 0x66f9
4211 || i
.tm
.base_opcode
== 0x66fa
4212 || i
.tm
.base_opcode
== 0x66fb
4213 || i
.tm
.base_opcode
== 0x42
4214 || i
.tm
.base_opcode
== 0x6642
4215 || i
.tm
.base_opcode
== 0x47
4216 || i
.tm
.base_opcode
== 0x6647)
4217 && i
.tm
.extension_opcode
== None
))
4220 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4222 EVEX VOP %zmmM, %zmmM, %zmmN
4223 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4224 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4225 EVEX VOP %ymmM, %ymmM, %ymmN
4226 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4227 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4228 VEX VOP %ymmM, %ymmM, %ymmN
4229 -> VEX VOP %xmmM, %xmmM, %xmmN
4230 VOP, one of vpandn and vpxor:
4231 VEX VOP %ymmM, %ymmM, %ymmN
4232 -> VEX VOP %xmmM, %xmmM, %xmmN
4233 VOP, one of vpandnd and vpandnq:
4234 EVEX VOP %zmmM, %zmmM, %zmmN
4235 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4236 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4237 EVEX VOP %ymmM, %ymmM, %ymmN
4238 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4239 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4240 VOP, one of vpxord and vpxorq:
4241 EVEX VOP %zmmM, %zmmM, %zmmN
4242 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4243 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4244 EVEX VOP %ymmM, %ymmM, %ymmN
4245 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4246 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4247 VOP, one of kxord and kxorq:
4248 VEX VOP %kM, %kM, %kN
4249 -> VEX kxorw %kM, %kM, %kN
4250 VOP, one of kandnd and kandnq:
4251 VEX VOP %kM, %kM, %kN
4252 -> VEX kandnw %kM, %kM, %kN
4254 if (is_evex_encoding (&i
.tm
))
4256 if (i
.vec_encoding
!= vex_encoding_evex
)
4258 i
.tm
.opcode_modifier
.vex
= VEX128
;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4260 i
.tm
.opcode_modifier
.evex
= 0;
4262 else if (optimize
> 1)
4263 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4267 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4269 i
.tm
.base_opcode
&= 0xff;
4270 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4273 i
.tm
.opcode_modifier
.vex
= VEX128
;
4275 if (i
.tm
.opcode_modifier
.vex
)
4276 for (j
= 0; j
< 3; j
++)
4278 i
.types
[j
].bitfield
.xmmword
= 1;
4279 i
.types
[j
].bitfield
.ymmword
= 0;
4282 else if (i
.vec_encoding
!= vex_encoding_evex
4283 && !i
.types
[0].bitfield
.zmmword
4284 && !i
.types
[1].bitfield
.zmmword
4287 && is_evex_encoding (&i
.tm
)
4288 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4289 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4290 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4291 || (i
.tm
.base_opcode
& ~4) == 0x66db
4292 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4293 && i
.tm
.extension_opcode
== None
)
4296 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4297 vmovdqu32 and vmovdqu64:
4298 EVEX VOP %xmmM, %xmmN
4299 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4300 EVEX VOP %ymmM, %ymmN
4301 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4303 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4305 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4307 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4309 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4310 VOP, one of vpand, vpandn, vpor, vpxor:
4311 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4312 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4313 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4314 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4315 EVEX VOP{d,q} mem, %xmmM, %xmmN
4316 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4317 EVEX VOP{d,q} mem, %ymmM, %ymmN
4318 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4320 for (j
= 0; j
< i
.operands
; j
++)
4321 if (operand_type_check (i
.types
[j
], disp
)
4322 && i
.op
[j
].disps
->X_op
== O_constant
)
4324 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4325 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4326 bytes, we choose EVEX Disp8 over VEX Disp32. */
4327 int evex_disp8
, vex_disp8
;
4328 unsigned int memshift
= i
.memshift
;
4329 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4331 evex_disp8
= fits_in_disp8 (n
);
4333 vex_disp8
= fits_in_disp8 (n
);
4334 if (evex_disp8
!= vex_disp8
)
4336 i
.memshift
= memshift
;
4340 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4343 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4344 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4345 i
.tm
.opcode_modifier
.vex
4346 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4347 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4348 /* VPAND, VPOR, and VPXOR are commutative. */
4349 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4350 i
.tm
.opcode_modifier
.commutative
= 1;
4351 i
.tm
.opcode_modifier
.evex
= 0;
4352 i
.tm
.opcode_modifier
.masking
= 0;
4353 i
.tm
.opcode_modifier
.broadcast
= 0;
4354 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4357 i
.types
[j
].bitfield
.disp8
4358 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4362 /* Return non-zero for load instruction. */
4368 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4369 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4373 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4374 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4375 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4376 if (i
.tm
.opcode_modifier
.anysize
)
4379 /* pop, popf, popa. */
4380 if (strcmp (i
.tm
.name
, "pop") == 0
4381 || i
.tm
.base_opcode
== 0x9d
4382 || i
.tm
.base_opcode
== 0x61)
4385 /* movs, cmps, lods, scas. */
4386 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4390 if (base_opcode
== 0x6f
4391 || i
.tm
.base_opcode
== 0xd7)
4393 /* NB: For AMD-specific insns with implicit memory operands,
4394 they're intentionally not covered. */
4397 /* No memory operand. */
4398 if (!i
.mem_operands
)
4404 if (i
.tm
.base_opcode
== 0xae
4405 && i
.tm
.opcode_modifier
.vex
4406 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4407 && i
.tm
.extension_opcode
== 2)
4412 /* test, not, neg, mul, imul, div, idiv. */
4413 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4414 && i
.tm
.extension_opcode
!= 1)
4418 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4421 /* add, or, adc, sbb, and, sub, xor, cmp. */
4422 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4425 /* bt, bts, btr, btc. */
4426 if (i
.tm
.base_opcode
== 0xfba
4427 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4430 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4431 if ((base_opcode
== 0xc1
4432 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4433 && i
.tm
.extension_opcode
!= 6)
4436 /* cmpxchg8b, cmpxchg16b, xrstors. */
4437 if (i
.tm
.base_opcode
== 0xfc7
4438 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4441 /* fxrstor, ldmxcsr, xrstor. */
4442 if (i
.tm
.base_opcode
== 0xfae
4443 && (i
.tm
.extension_opcode
== 1
4444 || i
.tm
.extension_opcode
== 2
4445 || i
.tm
.extension_opcode
== 5))
4448 /* lgdt, lidt, lmsw. */
4449 if (i
.tm
.base_opcode
== 0xf01
4450 && (i
.tm
.extension_opcode
== 2
4451 || i
.tm
.extension_opcode
== 3
4452 || i
.tm
.extension_opcode
== 6))
4456 if (i
.tm
.base_opcode
== 0xfc7
4457 && i
.tm
.extension_opcode
== 6)
4460 /* Check for x87 instructions. */
4461 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4463 /* Skip fst, fstp, fstenv, fstcw. */
4464 if (i
.tm
.base_opcode
== 0xd9
4465 && (i
.tm
.extension_opcode
== 2
4466 || i
.tm
.extension_opcode
== 3
4467 || i
.tm
.extension_opcode
== 6
4468 || i
.tm
.extension_opcode
== 7))
4471 /* Skip fisttp, fist, fistp, fstp. */
4472 if (i
.tm
.base_opcode
== 0xdb
4473 && (i
.tm
.extension_opcode
== 1
4474 || i
.tm
.extension_opcode
== 2
4475 || i
.tm
.extension_opcode
== 3
4476 || i
.tm
.extension_opcode
== 7))
4479 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4480 if (i
.tm
.base_opcode
== 0xdd
4481 && (i
.tm
.extension_opcode
== 1
4482 || i
.tm
.extension_opcode
== 2
4483 || i
.tm
.extension_opcode
== 3
4484 || i
.tm
.extension_opcode
== 6
4485 || i
.tm
.extension_opcode
== 7))
4488 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4489 if (i
.tm
.base_opcode
== 0xdf
4490 && (i
.tm
.extension_opcode
== 1
4491 || i
.tm
.extension_opcode
== 2
4492 || i
.tm
.extension_opcode
== 3
4493 || i
.tm
.extension_opcode
== 6
4494 || i
.tm
.extension_opcode
== 7))
4501 dest
= i
.operands
- 1;
4503 /* Check fake imm8 operand and 3 source operands. */
4504 if ((i
.tm
.opcode_modifier
.immext
4505 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4506 && i
.types
[dest
].bitfield
.imm8
)
4509 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4511 && (base_opcode
== 0x1
4512 || base_opcode
== 0x9
4513 || base_opcode
== 0x11
4514 || base_opcode
== 0x19
4515 || base_opcode
== 0x21
4516 || base_opcode
== 0x29
4517 || base_opcode
== 0x31
4518 || base_opcode
== 0x39
4519 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4520 || base_opcode
== 0xfc1))
4523 /* Check for load instruction. */
4524 return (i
.types
[dest
].bitfield
.class != ClassNone
4525 || i
.types
[dest
].bitfield
.instance
== Accum
);
4528 /* Output lfence, 0xfaee8, after instruction. */
4531 insert_lfence_after (void)
4533 if (lfence_after_load
&& load_insn_p ())
4535 /* There are also two REP string instructions that require
4536 special treatment. Specifically, the compare string (CMPS)
4537 and scan string (SCAS) instructions set EFLAGS in a manner
4538 that depends on the data being compared/scanned. When used
4539 with a REP prefix, the number of iterations may therefore
4540 vary depending on this data. If the data is a program secret
4541 chosen by the adversary using an LVI method,
4542 then this data-dependent behavior may leak some aspect
4544 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4545 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4546 && i
.prefix
[REP_PREFIX
])
4548 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4551 char *p
= frag_more (3);
4558 /* Output lfence, 0xfaee8, before instruction. */
4561 insert_lfence_before (void)
4565 if (is_any_vex_encoding (&i
.tm
))
4568 if (i
.tm
.base_opcode
== 0xff
4569 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4571 /* Insert lfence before indirect branch if needed. */
4573 if (lfence_before_indirect_branch
== lfence_branch_none
)
4576 if (i
.operands
!= 1)
4579 if (i
.reg_operands
== 1)
4581 /* Indirect branch via register. Don't insert lfence with
4582 -mlfence-after-load=yes. */
4583 if (lfence_after_load
4584 || lfence_before_indirect_branch
== lfence_branch_memory
)
4587 else if (i
.mem_operands
== 1
4588 && lfence_before_indirect_branch
!= lfence_branch_register
)
4590 as_warn (_("indirect `%s` with memory operand should be avoided"),
4597 if (last_insn
.kind
!= last_insn_other
4598 && last_insn
.seg
== now_seg
)
4600 as_warn_where (last_insn
.file
, last_insn
.line
,
4601 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4602 last_insn
.name
, i
.tm
.name
);
4613 /* Output or/not/shl and lfence before near ret. */
4614 if (lfence_before_ret
!= lfence_before_ret_none
4615 && (i
.tm
.base_opcode
== 0xc2
4616 || i
.tm
.base_opcode
== 0xc3))
4618 if (last_insn
.kind
!= last_insn_other
4619 && last_insn
.seg
== now_seg
)
4621 as_warn_where (last_insn
.file
, last_insn
.line
,
4622 _("`%s` skips -mlfence-before-ret on `%s`"),
4623 last_insn
.name
, i
.tm
.name
);
4627 /* Near ret ingore operand size override under CPU64. */
4628 char prefix
= flag_code
== CODE_64BIT
4630 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4632 if (lfence_before_ret
== lfence_before_ret_not
)
4634 /* not: 0xf71424, may add prefix
4635 for operand size override or 64-bit code. */
4636 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4650 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4653 if (lfence_before_ret
== lfence_before_ret_or
)
4655 /* or: 0x830c2400, may add prefix
4656 for operand size override or 64-bit code. */
4662 /* shl: 0xc1242400, may add prefix
4663 for operand size override or 64-bit code. */
4678 /* This is the guts of the machine-dependent assembler. LINE points to a
4679 machine dependent instruction. This function is supposed to emit
4680 the frags/bytes it assembles to. */
4683 md_assemble (char *line
)
4686 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4687 const insn_template
*t
;
4689 /* Initialize globals. */
4690 memset (&i
, '\0', sizeof (i
));
4691 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4692 i
.reloc
[j
] = NO_RELOC
;
4693 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4694 memset (im_expressions
, '\0', sizeof (im_expressions
));
4695 save_stack_p
= save_stack
;
4697 /* First parse an instruction mnemonic & call i386_operand for the operands.
4698 We assume that the scrubber has arranged it so that line[0] is the valid
4699 start of a (possibly prefixed) mnemonic. */
4701 line
= parse_insn (line
, mnemonic
);
4704 mnem_suffix
= i
.suffix
;
4706 line
= parse_operands (line
, mnemonic
);
4708 xfree (i
.memop1_string
);
4709 i
.memop1_string
= NULL
;
4713 /* Now we've parsed the mnemonic into a set of templates, and have the
4714 operands at hand. */
4716 /* All Intel opcodes have reversed operands except for "bound", "enter",
4717 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4718 intersegment "jmp" and "call" instructions with 2 immediate operands so
4719 that the immediate segment precedes the offset, as it does when in AT&T
4723 && (strcmp (mnemonic
, "bound") != 0)
4724 && (strcmp (mnemonic
, "invlpga") != 0)
4725 && (strncmp (mnemonic
, "monitor", 7) != 0)
4726 && (strncmp (mnemonic
, "mwait", 5) != 0)
4727 && (strcmp (mnemonic
, "tpause") != 0)
4728 && (strcmp (mnemonic
, "umwait") != 0)
4729 && !(operand_type_check (i
.types
[0], imm
)
4730 && operand_type_check (i
.types
[1], imm
)))
4733 /* The order of the immediates should be reversed
4734 for 2 immediates extrq and insertq instructions */
4735 if (i
.imm_operands
== 2
4736 && (strcmp (mnemonic
, "extrq") == 0
4737 || strcmp (mnemonic
, "insertq") == 0))
4738 swap_2_operands (0, 1);
4743 /* Don't optimize displacement for movabs since it only takes 64bit
4746 && i
.disp_encoding
!= disp_encoding_32bit
4747 && (flag_code
!= CODE_64BIT
4748 || strcmp (mnemonic
, "movabs") != 0))
4751 /* Next, we find a template that matches the given insn,
4752 making sure the overlap of the given operands types is consistent
4753 with the template operand types. */
4755 if (!(t
= match_template (mnem_suffix
)))
4758 if (sse_check
!= check_none
4759 && !i
.tm
.opcode_modifier
.noavx
4760 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4761 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4762 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4763 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4764 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4765 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4766 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4767 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4768 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4769 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4770 || i
.tm
.cpu_flags
.bitfield
.cpusha
4771 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4773 (sse_check
== check_warning
4775 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4778 if (i
.tm
.opcode_modifier
.fwait
)
4779 if (!add_prefix (FWAIT_OPCODE
))
4782 /* Check if REP prefix is OK. */
4783 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4785 as_bad (_("invalid instruction `%s' after `%s'"),
4786 i
.tm
.name
, i
.rep_prefix
);
4790 /* Check for lock without a lockable instruction. Destination operand
4791 must be memory unless it is xchg (0x86). */
4792 if (i
.prefix
[LOCK_PREFIX
]
4793 && (!i
.tm
.opcode_modifier
.islockable
4794 || i
.mem_operands
== 0
4795 || (i
.tm
.base_opcode
!= 0x86
4796 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4798 as_bad (_("expecting lockable instruction after `lock'"));
4802 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4803 if (i
.prefix
[DATA_PREFIX
]
4804 && (is_any_vex_encoding (&i
.tm
)
4805 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4806 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4808 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4812 /* Check if HLE prefix is OK. */
4813 if (i
.hle_prefix
&& !check_hle ())
4816 /* Check BND prefix. */
4817 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4818 as_bad (_("expecting valid branch instruction after `bnd'"));
4820 /* Check NOTRACK prefix. */
4821 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4822 as_bad (_("expecting indirect branch instruction after `notrack'"));
4824 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4826 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4827 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4828 else if (flag_code
!= CODE_16BIT
4829 ? i
.prefix
[ADDR_PREFIX
]
4830 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4831 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4834 /* Insert BND prefix. */
4835 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4837 if (!i
.prefix
[BND_PREFIX
])
4838 add_prefix (BND_PREFIX_OPCODE
);
4839 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4841 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4842 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4846 /* Check string instruction segment overrides. */
4847 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4849 gas_assert (i
.mem_operands
);
4850 if (!check_string ())
4852 i
.disp_operands
= 0;
4855 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4856 optimize_encoding ();
4858 if (!process_suffix ())
4861 /* Update operand types and check extended states. */
4862 for (j
= 0; j
< i
.operands
; j
++)
4864 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4865 switch (i
.types
[j
].bitfield
.class)
4870 i
.xstate
|= xstate_mmx
;
4873 i
.xstate
|= xstate_mask
;
4876 if (i
.types
[j
].bitfield
.tmmword
)
4877 i
.xstate
|= xstate_tmm
;
4878 else if (i
.types
[j
].bitfield
.zmmword
)
4879 i
.xstate
|= xstate_zmm
;
4880 else if (i
.types
[j
].bitfield
.ymmword
)
4881 i
.xstate
|= xstate_ymm
;
4882 else if (i
.types
[j
].bitfield
.xmmword
)
4883 i
.xstate
|= xstate_xmm
;
4888 /* Make still unresolved immediate matches conform to size of immediate
4889 given in i.suffix. */
4890 if (!finalize_imm ())
4893 if (i
.types
[0].bitfield
.imm1
)
4894 i
.imm_operands
= 0; /* kludge for shift insns. */
4896 /* We only need to check those implicit registers for instructions
4897 with 3 operands or less. */
4898 if (i
.operands
<= 3)
4899 for (j
= 0; j
< i
.operands
; j
++)
4900 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4901 && !i
.types
[j
].bitfield
.xmmword
)
4904 /* For insns with operands there are more diddles to do to the opcode. */
4907 if (!process_operands ())
4910 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4912 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4913 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4916 if (is_any_vex_encoding (&i
.tm
))
4918 if (!cpu_arch_flags
.bitfield
.cpui286
)
4920 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4925 /* Check for explicit REX prefix. */
4926 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4928 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4932 if (i
.tm
.opcode_modifier
.vex
)
4933 build_vex_prefix (t
);
4935 build_evex_prefix ();
4937 /* The individual REX.RXBW bits got consumed. */
4938 i
.rex
&= REX_OPCODE
;
4941 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4942 instructions may define INT_OPCODE as well, so avoid this corner
4943 case for those instructions that use MODRM. */
4944 if (i
.tm
.base_opcode
== INT_OPCODE
4945 && !i
.tm
.opcode_modifier
.modrm
4946 && i
.op
[0].imms
->X_add_number
== 3)
4948 i
.tm
.base_opcode
= INT3_OPCODE
;
4952 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4953 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4954 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4955 && i
.op
[0].disps
->X_op
== O_constant
)
4957 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4958 the absolute address given by the constant. Since ix86 jumps and
4959 calls are pc relative, we need to generate a reloc. */
4960 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4961 i
.op
[0].disps
->X_op
= O_symbol
;
4964 /* For 8 bit registers we need an empty rex prefix. Also if the
4965 instruction already has a prefix, we need to convert old
4966 registers to new ones. */
4968 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4969 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4970 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4971 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4972 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4973 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4978 i
.rex
|= REX_OPCODE
;
4979 for (x
= 0; x
< 2; x
++)
4981 /* Look for 8 bit operand that uses old registers. */
4982 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4983 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4985 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4986 /* In case it is "hi" register, give up. */
4987 if (i
.op
[x
].regs
->reg_num
> 3)
4988 as_bad (_("can't encode register '%s%s' in an "
4989 "instruction requiring REX prefix."),
4990 register_prefix
, i
.op
[x
].regs
->reg_name
);
4992 /* Otherwise it is equivalent to the extended register.
4993 Since the encoding doesn't change this is merely
4994 cosmetic cleanup for debug output. */
4996 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5001 if (i
.rex
== 0 && i
.rex_encoding
)
5003 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5004 that uses legacy register. If it is "hi" register, don't add
5005 the REX_OPCODE byte. */
5007 for (x
= 0; x
< 2; x
++)
5008 if (i
.types
[x
].bitfield
.class == Reg
5009 && i
.types
[x
].bitfield
.byte
5010 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5011 && i
.op
[x
].regs
->reg_num
> 3)
5013 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5014 i
.rex_encoding
= FALSE
;
5023 add_prefix (REX_OPCODE
| i
.rex
);
5025 insert_lfence_before ();
5027 /* We are ready to output the insn. */
5030 insert_lfence_after ();
5032 last_insn
.seg
= now_seg
;
5034 if (i
.tm
.opcode_modifier
.isprefix
)
5036 last_insn
.kind
= last_insn_prefix
;
5037 last_insn
.name
= i
.tm
.name
;
5038 last_insn
.file
= as_where (&last_insn
.line
);
5041 last_insn
.kind
= last_insn_other
;
5045 parse_insn (char *line
, char *mnemonic
)
5048 char *token_start
= l
;
5051 const insn_template
*t
;
5057 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5062 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5064 as_bad (_("no such instruction: `%s'"), token_start
);
5069 if (!is_space_char (*l
)
5070 && *l
!= END_OF_INSN
5072 || (*l
!= PREFIX_SEPARATOR
5075 as_bad (_("invalid character %s in mnemonic"),
5076 output_invalid (*l
));
5079 if (token_start
== l
)
5081 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5082 as_bad (_("expecting prefix; got nothing"));
5084 as_bad (_("expecting mnemonic; got nothing"));
5088 /* Look up instruction (or prefix) via hash table. */
5089 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5091 if (*l
!= END_OF_INSN
5092 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5093 && current_templates
5094 && current_templates
->start
->opcode_modifier
.isprefix
)
5096 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5098 as_bad ((flag_code
!= CODE_64BIT
5099 ? _("`%s' is only supported in 64-bit mode")
5100 : _("`%s' is not supported in 64-bit mode")),
5101 current_templates
->start
->name
);
5104 /* If we are in 16-bit mode, do not allow addr16 or data16.
5105 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5106 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5107 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5108 && flag_code
!= CODE_64BIT
5109 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5110 ^ (flag_code
== CODE_16BIT
)))
5112 as_bad (_("redundant %s prefix"),
5113 current_templates
->start
->name
);
5116 if (current_templates
->start
->opcode_length
== 0)
5118 /* Handle pseudo prefixes. */
5119 switch (current_templates
->start
->base_opcode
)
5123 i
.disp_encoding
= disp_encoding_8bit
;
5127 i
.disp_encoding
= disp_encoding_16bit
;
5131 i
.disp_encoding
= disp_encoding_32bit
;
5135 i
.dir_encoding
= dir_encoding_load
;
5139 i
.dir_encoding
= dir_encoding_store
;
5143 i
.vec_encoding
= vex_encoding_vex
;
5147 i
.vec_encoding
= vex_encoding_vex3
;
5151 i
.vec_encoding
= vex_encoding_evex
;
5155 i
.rex_encoding
= TRUE
;
5157 case Prefix_NoOptimize
:
5159 i
.no_optimize
= TRUE
;
5167 /* Add prefix, checking for repeated prefixes. */
5168 switch (add_prefix (current_templates
->start
->base_opcode
))
5173 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5174 i
.notrack_prefix
= current_templates
->start
->name
;
5177 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5178 i
.hle_prefix
= current_templates
->start
->name
;
5179 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5180 i
.bnd_prefix
= current_templates
->start
->name
;
5182 i
.rep_prefix
= current_templates
->start
->name
;
5188 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5195 if (!current_templates
)
5197 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5198 Check if we should swap operand or force 32bit displacement in
5200 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5201 i
.dir_encoding
= dir_encoding_swap
;
5202 else if (mnem_p
- 3 == dot_p
5205 i
.disp_encoding
= disp_encoding_8bit
;
5206 else if (mnem_p
- 4 == dot_p
5210 i
.disp_encoding
= disp_encoding_32bit
;
5215 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5218 if (!current_templates
)
5221 if (mnem_p
> mnemonic
)
5223 /* See if we can get a match by trimming off a suffix. */
5226 case WORD_MNEM_SUFFIX
:
5227 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5228 i
.suffix
= SHORT_MNEM_SUFFIX
;
5231 case BYTE_MNEM_SUFFIX
:
5232 case QWORD_MNEM_SUFFIX
:
5233 i
.suffix
= mnem_p
[-1];
5236 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5238 case SHORT_MNEM_SUFFIX
:
5239 case LONG_MNEM_SUFFIX
:
5242 i
.suffix
= mnem_p
[-1];
5245 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5253 if (intel_float_operand (mnemonic
) == 1)
5254 i
.suffix
= SHORT_MNEM_SUFFIX
;
5256 i
.suffix
= LONG_MNEM_SUFFIX
;
5259 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5265 if (!current_templates
)
5267 as_bad (_("no such instruction: `%s'"), token_start
);
5272 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5273 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5275 /* Check for a branch hint. We allow ",pt" and ",pn" for
5276 predict taken and predict not taken respectively.
5277 I'm not sure that branch hints actually do anything on loop
5278 and jcxz insns (JumpByte) for current Pentium4 chips. They
5279 may work in the future and it doesn't hurt to accept them
5281 if (l
[0] == ',' && l
[1] == 'p')
5285 if (!add_prefix (DS_PREFIX_OPCODE
))
5289 else if (l
[2] == 'n')
5291 if (!add_prefix (CS_PREFIX_OPCODE
))
5297 /* Any other comma loses. */
5300 as_bad (_("invalid character %s in mnemonic"),
5301 output_invalid (*l
));
5305 /* Check if instruction is supported on specified architecture. */
5307 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5309 supported
|= cpu_flags_match (t
);
5310 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5312 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5313 as_warn (_("use .code16 to ensure correct addressing mode"));
5319 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5320 as_bad (flag_code
== CODE_64BIT
5321 ? _("`%s' is not supported in 64-bit mode")
5322 : _("`%s' is only supported in 64-bit mode"),
5323 current_templates
->start
->name
);
5325 as_bad (_("`%s' is not supported on `%s%s'"),
5326 current_templates
->start
->name
,
5327 cpu_arch_name
? cpu_arch_name
: default_arch
,
5328 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5334 parse_operands (char *l
, const char *mnemonic
)
5338 /* 1 if operand is pending after ','. */
5339 unsigned int expecting_operand
= 0;
5341 /* Non-zero if operand parens not balanced. */
5342 unsigned int paren_not_balanced
;
5344 while (*l
!= END_OF_INSN
)
5346 /* Skip optional white space before operand. */
5347 if (is_space_char (*l
))
5349 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5351 as_bad (_("invalid character %s before operand %d"),
5352 output_invalid (*l
),
5356 token_start
= l
; /* After white space. */
5357 paren_not_balanced
= 0;
5358 while (paren_not_balanced
|| *l
!= ',')
5360 if (*l
== END_OF_INSN
)
5362 if (paren_not_balanced
)
5365 as_bad (_("unbalanced parenthesis in operand %d."),
5368 as_bad (_("unbalanced brackets in operand %d."),
5373 break; /* we are done */
5375 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5377 as_bad (_("invalid character %s in operand %d"),
5378 output_invalid (*l
),
5385 ++paren_not_balanced
;
5387 --paren_not_balanced
;
5392 ++paren_not_balanced
;
5394 --paren_not_balanced
;
5398 if (l
!= token_start
)
5399 { /* Yes, we've read in another operand. */
5400 unsigned int operand_ok
;
5401 this_operand
= i
.operands
++;
5402 if (i
.operands
> MAX_OPERANDS
)
5404 as_bad (_("spurious operands; (%d operands/instruction max)"),
5408 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5409 /* Now parse operand adding info to 'i' as we go along. */
5410 END_STRING_AND_SAVE (l
);
5412 if (i
.mem_operands
> 1)
5414 as_bad (_("too many memory references for `%s'"),
5421 i386_intel_operand (token_start
,
5422 intel_float_operand (mnemonic
));
5424 operand_ok
= i386_att_operand (token_start
);
5426 RESTORE_END_STRING (l
);
5432 if (expecting_operand
)
5434 expecting_operand_after_comma
:
5435 as_bad (_("expecting operand after ','; got nothing"));
5440 as_bad (_("expecting operand before ','; got nothing"));
5445 /* Now *l must be either ',' or END_OF_INSN. */
5448 if (*++l
== END_OF_INSN
)
5450 /* Just skip it, if it's \n complain. */
5451 goto expecting_operand_after_comma
;
5453 expecting_operand
= 1;
5460 swap_2_operands (int xchg1
, int xchg2
)
5462 union i386_op temp_op
;
5463 i386_operand_type temp_type
;
5464 unsigned int temp_flags
;
5465 enum bfd_reloc_code_real temp_reloc
;
5467 temp_type
= i
.types
[xchg2
];
5468 i
.types
[xchg2
] = i
.types
[xchg1
];
5469 i
.types
[xchg1
] = temp_type
;
5471 temp_flags
= i
.flags
[xchg2
];
5472 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5473 i
.flags
[xchg1
] = temp_flags
;
5475 temp_op
= i
.op
[xchg2
];
5476 i
.op
[xchg2
] = i
.op
[xchg1
];
5477 i
.op
[xchg1
] = temp_op
;
5479 temp_reloc
= i
.reloc
[xchg2
];
5480 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5481 i
.reloc
[xchg1
] = temp_reloc
;
5485 if (i
.mask
->operand
== xchg1
)
5486 i
.mask
->operand
= xchg2
;
5487 else if (i
.mask
->operand
== xchg2
)
5488 i
.mask
->operand
= xchg1
;
5492 if (i
.broadcast
->operand
== xchg1
)
5493 i
.broadcast
->operand
= xchg2
;
5494 else if (i
.broadcast
->operand
== xchg2
)
5495 i
.broadcast
->operand
= xchg1
;
5499 if (i
.rounding
->operand
== xchg1
)
5500 i
.rounding
->operand
= xchg2
;
5501 else if (i
.rounding
->operand
== xchg2
)
5502 i
.rounding
->operand
= xchg1
;
5507 swap_operands (void)
5513 swap_2_operands (1, i
.operands
- 2);
5517 swap_2_operands (0, i
.operands
- 1);
5523 if (i
.mem_operands
== 2)
5525 const seg_entry
*temp_seg
;
5526 temp_seg
= i
.seg
[0];
5527 i
.seg
[0] = i
.seg
[1];
5528 i
.seg
[1] = temp_seg
;
5532 /* Try to ensure constant immediates are represented in the smallest
5537 char guess_suffix
= 0;
5541 guess_suffix
= i
.suffix
;
5542 else if (i
.reg_operands
)
5544 /* Figure out a suffix from the last register operand specified.
5545 We can't do this properly yet, i.e. excluding special register
5546 instances, but the following works for instructions with
5547 immediates. In any case, we can't set i.suffix yet. */
5548 for (op
= i
.operands
; --op
>= 0;)
5549 if (i
.types
[op
].bitfield
.class != Reg
)
5551 else if (i
.types
[op
].bitfield
.byte
)
5553 guess_suffix
= BYTE_MNEM_SUFFIX
;
5556 else if (i
.types
[op
].bitfield
.word
)
5558 guess_suffix
= WORD_MNEM_SUFFIX
;
5561 else if (i
.types
[op
].bitfield
.dword
)
5563 guess_suffix
= LONG_MNEM_SUFFIX
;
5566 else if (i
.types
[op
].bitfield
.qword
)
5568 guess_suffix
= QWORD_MNEM_SUFFIX
;
5572 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5573 guess_suffix
= WORD_MNEM_SUFFIX
;
5575 for (op
= i
.operands
; --op
>= 0;)
5576 if (operand_type_check (i
.types
[op
], imm
))
5578 switch (i
.op
[op
].imms
->X_op
)
5581 /* If a suffix is given, this operand may be shortened. */
5582 switch (guess_suffix
)
5584 case LONG_MNEM_SUFFIX
:
5585 i
.types
[op
].bitfield
.imm32
= 1;
5586 i
.types
[op
].bitfield
.imm64
= 1;
5588 case WORD_MNEM_SUFFIX
:
5589 i
.types
[op
].bitfield
.imm16
= 1;
5590 i
.types
[op
].bitfield
.imm32
= 1;
5591 i
.types
[op
].bitfield
.imm32s
= 1;
5592 i
.types
[op
].bitfield
.imm64
= 1;
5594 case BYTE_MNEM_SUFFIX
:
5595 i
.types
[op
].bitfield
.imm8
= 1;
5596 i
.types
[op
].bitfield
.imm8s
= 1;
5597 i
.types
[op
].bitfield
.imm16
= 1;
5598 i
.types
[op
].bitfield
.imm32
= 1;
5599 i
.types
[op
].bitfield
.imm32s
= 1;
5600 i
.types
[op
].bitfield
.imm64
= 1;
5604 /* If this operand is at most 16 bits, convert it
5605 to a signed 16 bit number before trying to see
5606 whether it will fit in an even smaller size.
5607 This allows a 16-bit operand such as $0xffe0 to
5608 be recognised as within Imm8S range. */
5609 if ((i
.types
[op
].bitfield
.imm16
)
5610 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5612 i
.op
[op
].imms
->X_add_number
=
5613 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5616 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5617 if ((i
.types
[op
].bitfield
.imm32
)
5618 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5621 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5622 ^ ((offsetT
) 1 << 31))
5623 - ((offsetT
) 1 << 31));
5627 = operand_type_or (i
.types
[op
],
5628 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5630 /* We must avoid matching of Imm32 templates when 64bit
5631 only immediate is available. */
5632 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5633 i
.types
[op
].bitfield
.imm32
= 0;
5640 /* Symbols and expressions. */
5642 /* Convert symbolic operand to proper sizes for matching, but don't
5643 prevent matching a set of insns that only supports sizes other
5644 than those matching the insn suffix. */
5646 i386_operand_type mask
, allowed
;
5647 const insn_template
*t
;
5649 operand_type_set (&mask
, 0);
5650 operand_type_set (&allowed
, 0);
5652 for (t
= current_templates
->start
;
5653 t
< current_templates
->end
;
5656 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5657 allowed
= operand_type_and (allowed
, anyimm
);
5659 switch (guess_suffix
)
5661 case QWORD_MNEM_SUFFIX
:
5662 mask
.bitfield
.imm64
= 1;
5663 mask
.bitfield
.imm32s
= 1;
5665 case LONG_MNEM_SUFFIX
:
5666 mask
.bitfield
.imm32
= 1;
5668 case WORD_MNEM_SUFFIX
:
5669 mask
.bitfield
.imm16
= 1;
5671 case BYTE_MNEM_SUFFIX
:
5672 mask
.bitfield
.imm8
= 1;
5677 allowed
= operand_type_and (mask
, allowed
);
5678 if (!operand_type_all_zero (&allowed
))
5679 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5686 /* Try to use the smallest displacement type too. */
5688 optimize_disp (void)
5692 for (op
= i
.operands
; --op
>= 0;)
5693 if (operand_type_check (i
.types
[op
], disp
))
5695 if (i
.op
[op
].disps
->X_op
== O_constant
)
5697 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5699 if (i
.types
[op
].bitfield
.disp16
5700 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5702 /* If this operand is at most 16 bits, convert
5703 to a signed 16 bit number and don't use 64bit
5705 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5706 i
.types
[op
].bitfield
.disp64
= 0;
5709 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5710 if (i
.types
[op
].bitfield
.disp32
5711 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5713 /* If this operand is at most 32 bits, convert
5714 to a signed 32 bit number and don't use 64bit
5716 op_disp
&= (((offsetT
) 2 << 31) - 1);
5717 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5718 i
.types
[op
].bitfield
.disp64
= 0;
5721 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5723 i
.types
[op
].bitfield
.disp8
= 0;
5724 i
.types
[op
].bitfield
.disp16
= 0;
5725 i
.types
[op
].bitfield
.disp32
= 0;
5726 i
.types
[op
].bitfield
.disp32s
= 0;
5727 i
.types
[op
].bitfield
.disp64
= 0;
5731 else if (flag_code
== CODE_64BIT
)
5733 if (fits_in_signed_long (op_disp
))
5735 i
.types
[op
].bitfield
.disp64
= 0;
5736 i
.types
[op
].bitfield
.disp32s
= 1;
5738 if (i
.prefix
[ADDR_PREFIX
]
5739 && fits_in_unsigned_long (op_disp
))
5740 i
.types
[op
].bitfield
.disp32
= 1;
5742 if ((i
.types
[op
].bitfield
.disp32
5743 || i
.types
[op
].bitfield
.disp32s
5744 || i
.types
[op
].bitfield
.disp16
)
5745 && fits_in_disp8 (op_disp
))
5746 i
.types
[op
].bitfield
.disp8
= 1;
5748 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5749 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5751 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5752 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5753 i
.types
[op
].bitfield
.disp8
= 0;
5754 i
.types
[op
].bitfield
.disp16
= 0;
5755 i
.types
[op
].bitfield
.disp32
= 0;
5756 i
.types
[op
].bitfield
.disp32s
= 0;
5757 i
.types
[op
].bitfield
.disp64
= 0;
5760 /* We only support 64bit displacement on constants. */
5761 i
.types
[op
].bitfield
.disp64
= 0;
5765 /* Return 1 if there is a match in broadcast bytes between operand
5766 GIVEN and instruction template T. */
5769 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5771 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5772 && i
.types
[given
].bitfield
.byte
)
5773 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5774 && i
.types
[given
].bitfield
.word
)
5775 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5776 && i
.types
[given
].bitfield
.dword
)
5777 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5778 && i
.types
[given
].bitfield
.qword
));
5781 /* Check if operands are valid for the instruction. */
5784 check_VecOperands (const insn_template
*t
)
5789 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5790 any one operand are implicity requiring AVX512VL support if the actual
5791 operand size is YMMword or XMMword. Since this function runs after
5792 template matching, there's no need to check for YMMword/XMMword in
5794 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5795 if (!cpu_flags_all_zero (&cpu
)
5796 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5797 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5799 for (op
= 0; op
< t
->operands
; ++op
)
5801 if (t
->operand_types
[op
].bitfield
.zmmword
5802 && (i
.types
[op
].bitfield
.ymmword
5803 || i
.types
[op
].bitfield
.xmmword
))
5805 i
.error
= unsupported
;
5811 /* Without VSIB byte, we can't have a vector register for index. */
5812 if (!t
->opcode_modifier
.sib
5814 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5815 || i
.index_reg
->reg_type
.bitfield
.ymmword
5816 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5818 i
.error
= unsupported_vector_index_register
;
5822 /* Check if default mask is allowed. */
5823 if (t
->opcode_modifier
.nodefmask
5824 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5826 i
.error
= no_default_mask
;
5830 /* For VSIB byte, we need a vector register for index, and all vector
5831 registers must be distinct. */
5832 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5835 || !((t
->opcode_modifier
.sib
== VECSIB128
5836 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5837 || (t
->opcode_modifier
.sib
== VECSIB256
5838 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5839 || (t
->opcode_modifier
.sib
== VECSIB512
5840 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5842 i
.error
= invalid_vsib_address
;
5846 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5847 if (i
.reg_operands
== 2 && !i
.mask
)
5849 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5850 gas_assert (i
.types
[0].bitfield
.xmmword
5851 || i
.types
[0].bitfield
.ymmword
);
5852 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5853 gas_assert (i
.types
[2].bitfield
.xmmword
5854 || i
.types
[2].bitfield
.ymmword
);
5855 if (operand_check
== check_none
)
5857 if (register_number (i
.op
[0].regs
)
5858 != register_number (i
.index_reg
)
5859 && register_number (i
.op
[2].regs
)
5860 != register_number (i
.index_reg
)
5861 && register_number (i
.op
[0].regs
)
5862 != register_number (i
.op
[2].regs
))
5864 if (operand_check
== check_error
)
5866 i
.error
= invalid_vector_register_set
;
5869 as_warn (_("mask, index, and destination registers should be distinct"));
5871 else if (i
.reg_operands
== 1 && i
.mask
)
5873 if (i
.types
[1].bitfield
.class == RegSIMD
5874 && (i
.types
[1].bitfield
.xmmword
5875 || i
.types
[1].bitfield
.ymmword
5876 || i
.types
[1].bitfield
.zmmword
)
5877 && (register_number (i
.op
[1].regs
)
5878 == register_number (i
.index_reg
)))
5880 if (operand_check
== check_error
)
5882 i
.error
= invalid_vector_register_set
;
5885 if (operand_check
!= check_none
)
5886 as_warn (_("index and destination registers should be distinct"));
5891 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5893 if (t
->operand_types
[0].bitfield
.tmmword
5894 && i
.reg_operands
== 3)
5896 if (register_number (i
.op
[0].regs
)
5897 == register_number (i
.op
[1].regs
)
5898 || register_number (i
.op
[0].regs
)
5899 == register_number (i
.op
[2].regs
)
5900 || register_number (i
.op
[1].regs
)
5901 == register_number (i
.op
[2].regs
))
5903 i
.error
= invalid_tmm_register_set
;
5908 /* Check if broadcast is supported by the instruction and is applied
5909 to the memory operand. */
5912 i386_operand_type type
, overlap
;
5914 /* Check if specified broadcast is supported in this instruction,
5915 and its broadcast bytes match the memory operand. */
5916 op
= i
.broadcast
->operand
;
5917 if (!t
->opcode_modifier
.broadcast
5918 || !(i
.flags
[op
] & Operand_Mem
)
5919 || (!i
.types
[op
].bitfield
.unspecified
5920 && !match_broadcast_size (t
, op
)))
5923 i
.error
= unsupported_broadcast
;
5927 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5928 * i
.broadcast
->type
);
5929 operand_type_set (&type
, 0);
5930 switch (i
.broadcast
->bytes
)
5933 type
.bitfield
.word
= 1;
5936 type
.bitfield
.dword
= 1;
5939 type
.bitfield
.qword
= 1;
5942 type
.bitfield
.xmmword
= 1;
5945 type
.bitfield
.ymmword
= 1;
5948 type
.bitfield
.zmmword
= 1;
5954 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5955 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5956 && t
->operand_types
[op
].bitfield
.byte
5957 + t
->operand_types
[op
].bitfield
.word
5958 + t
->operand_types
[op
].bitfield
.dword
5959 + t
->operand_types
[op
].bitfield
.qword
> 1)
5961 overlap
.bitfield
.xmmword
= 0;
5962 overlap
.bitfield
.ymmword
= 0;
5963 overlap
.bitfield
.zmmword
= 0;
5965 if (operand_type_all_zero (&overlap
))
5968 if (t
->opcode_modifier
.checkregsize
)
5972 type
.bitfield
.baseindex
= 1;
5973 for (j
= 0; j
< i
.operands
; ++j
)
5976 && !operand_type_register_match(i
.types
[j
],
5977 t
->operand_types
[j
],
5979 t
->operand_types
[op
]))
5984 /* If broadcast is supported in this instruction, we need to check if
5985 operand of one-element size isn't specified without broadcast. */
5986 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5988 /* Find memory operand. */
5989 for (op
= 0; op
< i
.operands
; op
++)
5990 if (i
.flags
[op
] & Operand_Mem
)
5992 gas_assert (op
< i
.operands
);
5993 /* Check size of the memory operand. */
5994 if (match_broadcast_size (t
, op
))
5996 i
.error
= broadcast_needed
;
6001 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6003 /* Check if requested masking is supported. */
6006 switch (t
->opcode_modifier
.masking
)
6010 case MERGING_MASKING
:
6011 if (i
.mask
->zeroing
)
6014 i
.error
= unsupported_masking
;
6018 case DYNAMIC_MASKING
:
6019 /* Memory destinations allow only merging masking. */
6020 if (i
.mask
->zeroing
&& i
.mem_operands
)
6022 /* Find memory operand. */
6023 for (op
= 0; op
< i
.operands
; op
++)
6024 if (i
.flags
[op
] & Operand_Mem
)
6026 gas_assert (op
< i
.operands
);
6027 if (op
== i
.operands
- 1)
6029 i
.error
= unsupported_masking
;
6039 /* Check if masking is applied to dest operand. */
6040 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6042 i
.error
= mask_not_on_destination
;
6049 if (!t
->opcode_modifier
.sae
6050 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6052 i
.error
= unsupported_rc_sae
;
6055 /* If the instruction has several immediate operands and one of
6056 them is rounding, the rounding operand should be the last
6057 immediate operand. */
6058 if (i
.imm_operands
> 1
6059 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6061 i
.error
= rc_sae_operand_not_last_imm
;
6066 /* Check the special Imm4 cases; must be the first operand. */
6067 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6069 if (i
.op
[0].imms
->X_op
!= O_constant
6070 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6076 /* Turn off Imm<N> so that update_imm won't complain. */
6077 operand_type_set (&i
.types
[0], 0);
6080 /* Check vector Disp8 operand. */
6081 if (t
->opcode_modifier
.disp8memshift
6082 && i
.disp_encoding
!= disp_encoding_32bit
)
6085 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6086 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6087 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6090 const i386_operand_type
*type
= NULL
;
6093 for (op
= 0; op
< i
.operands
; op
++)
6094 if (i
.flags
[op
] & Operand_Mem
)
6096 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6097 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6098 else if (t
->operand_types
[op
].bitfield
.xmmword
6099 + t
->operand_types
[op
].bitfield
.ymmword
6100 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6101 type
= &t
->operand_types
[op
];
6102 else if (!i
.types
[op
].bitfield
.unspecified
)
6103 type
= &i
.types
[op
];
6105 else if (i
.types
[op
].bitfield
.class == RegSIMD
6106 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6108 if (i
.types
[op
].bitfield
.zmmword
)
6110 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6112 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6118 if (type
->bitfield
.zmmword
)
6120 else if (type
->bitfield
.ymmword
)
6122 else if (type
->bitfield
.xmmword
)
6126 /* For the check in fits_in_disp8(). */
6127 if (i
.memshift
== 0)
6131 for (op
= 0; op
< i
.operands
; op
++)
6132 if (operand_type_check (i
.types
[op
], disp
)
6133 && i
.op
[op
].disps
->X_op
== O_constant
)
6135 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6137 i
.types
[op
].bitfield
.disp8
= 1;
6140 i
.types
[op
].bitfield
.disp8
= 0;
6149 /* Check if encoding requirements are met by the instruction. */
6152 VEX_check_encoding (const insn_template
*t
)
6154 if (i
.vec_encoding
== vex_encoding_error
)
6156 i
.error
= unsupported
;
6160 if (i
.vec_encoding
== vex_encoding_evex
)
6162 /* This instruction must be encoded with EVEX prefix. */
6163 if (!is_evex_encoding (t
))
6165 i
.error
= unsupported
;
6171 if (!t
->opcode_modifier
.vex
)
6173 /* This instruction template doesn't have VEX prefix. */
6174 if (i
.vec_encoding
!= vex_encoding_default
)
6176 i
.error
= unsupported
;
6185 static const insn_template
*
6186 match_template (char mnem_suffix
)
6188 /* Points to template once we've found it. */
6189 const insn_template
*t
;
6190 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6191 i386_operand_type overlap4
;
6192 unsigned int found_reverse_match
;
6193 i386_opcode_modifier suffix_check
;
6194 i386_operand_type operand_types
[MAX_OPERANDS
];
6195 int addr_prefix_disp
;
6196 unsigned int j
, size_match
, check_register
;
6197 enum i386_error specific_error
= 0;
6199 #if MAX_OPERANDS != 5
6200 # error "MAX_OPERANDS must be 5."
6203 found_reverse_match
= 0;
6204 addr_prefix_disp
= -1;
6206 /* Prepare for mnemonic suffix check. */
6207 memset (&suffix_check
, 0, sizeof (suffix_check
));
6208 switch (mnem_suffix
)
6210 case BYTE_MNEM_SUFFIX
:
6211 suffix_check
.no_bsuf
= 1;
6213 case WORD_MNEM_SUFFIX
:
6214 suffix_check
.no_wsuf
= 1;
6216 case SHORT_MNEM_SUFFIX
:
6217 suffix_check
.no_ssuf
= 1;
6219 case LONG_MNEM_SUFFIX
:
6220 suffix_check
.no_lsuf
= 1;
6222 case QWORD_MNEM_SUFFIX
:
6223 suffix_check
.no_qsuf
= 1;
6226 /* NB: In Intel syntax, normally we can check for memory operand
6227 size when there is no mnemonic suffix. But jmp and call have
6228 2 different encodings with Dword memory operand size, one with
6229 No_ldSuf and the other without. i.suffix is set to
6230 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6231 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6232 suffix_check
.no_ldsuf
= 1;
6235 /* Must have right number of operands. */
6236 i
.error
= number_of_operands_mismatch
;
6238 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6240 addr_prefix_disp
= -1;
6241 found_reverse_match
= 0;
6243 if (i
.operands
!= t
->operands
)
6246 /* Check processor support. */
6247 i
.error
= unsupported
;
6248 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6251 /* Check AT&T mnemonic. */
6252 i
.error
= unsupported_with_intel_mnemonic
;
6253 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6256 /* Check AT&T/Intel syntax. */
6257 i
.error
= unsupported_syntax
;
6258 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6259 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6262 /* Check Intel64/AMD64 ISA. */
6266 /* Default: Don't accept Intel64. */
6267 if (t
->opcode_modifier
.isa64
== INTEL64
)
6271 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6272 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6276 /* -mintel64: Don't accept AMD64. */
6277 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6282 /* Check the suffix. */
6283 i
.error
= invalid_instruction_suffix
;
6284 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6285 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6286 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6287 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6288 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6289 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6292 size_match
= operand_size_match (t
);
6296 /* This is intentionally not
6298 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6300 as the case of a missing * on the operand is accepted (perhaps with
6301 a warning, issued further down). */
6302 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6304 i
.error
= operand_type_mismatch
;
6308 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6309 operand_types
[j
] = t
->operand_types
[j
];
6311 /* In general, don't allow
6312 - 64-bit operands outside of 64-bit mode,
6313 - 32-bit operands on pre-386. */
6314 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6315 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6316 && flag_code
!= CODE_64BIT
6317 && (t
->base_opcode
!= 0x0fc7
6318 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6319 || (i
.suffix
== LONG_MNEM_SUFFIX
6320 && !cpu_arch_flags
.bitfield
.cpui386
))
6322 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6323 && !intel_float_operand (t
->name
))
6324 : intel_float_operand (t
->name
) != 2)
6325 && (t
->operands
== i
.imm_operands
6326 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6327 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6328 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6329 || (operand_types
[j
].bitfield
.class != RegMMX
6330 && operand_types
[j
].bitfield
.class != RegSIMD
6331 && operand_types
[j
].bitfield
.class != RegMask
))
6332 && !t
->opcode_modifier
.sib
)
6335 /* Do not verify operands when there are none. */
6338 if (VEX_check_encoding (t
))
6340 specific_error
= i
.error
;
6344 /* We've found a match; break out of loop. */
6348 if (!t
->opcode_modifier
.jump
6349 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6351 /* There should be only one Disp operand. */
6352 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6353 if (operand_type_check (operand_types
[j
], disp
))
6355 if (j
< MAX_OPERANDS
)
6357 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6359 addr_prefix_disp
= j
;
6361 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6362 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6366 override
= !override
;
6369 if (operand_types
[j
].bitfield
.disp32
6370 && operand_types
[j
].bitfield
.disp16
)
6372 operand_types
[j
].bitfield
.disp16
= override
;
6373 operand_types
[j
].bitfield
.disp32
= !override
;
6375 operand_types
[j
].bitfield
.disp32s
= 0;
6376 operand_types
[j
].bitfield
.disp64
= 0;
6380 if (operand_types
[j
].bitfield
.disp32s
6381 || operand_types
[j
].bitfield
.disp64
)
6383 operand_types
[j
].bitfield
.disp64
&= !override
;
6384 operand_types
[j
].bitfield
.disp32s
&= !override
;
6385 operand_types
[j
].bitfield
.disp32
= override
;
6387 operand_types
[j
].bitfield
.disp16
= 0;
6393 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6394 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6397 /* We check register size if needed. */
6398 if (t
->opcode_modifier
.checkregsize
)
6400 check_register
= (1 << t
->operands
) - 1;
6402 check_register
&= ~(1 << i
.broadcast
->operand
);
6407 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6408 switch (t
->operands
)
6411 if (!operand_type_match (overlap0
, i
.types
[0]))
6415 /* xchg %eax, %eax is a special case. It is an alias for nop
6416 only in 32bit mode and we can use opcode 0x90. In 64bit
6417 mode, we can't use 0x90 for xchg %eax, %eax since it should
6418 zero-extend %eax to %rax. */
6419 if (flag_code
== CODE_64BIT
6420 && t
->base_opcode
== 0x90
6421 && i
.types
[0].bitfield
.instance
== Accum
6422 && i
.types
[0].bitfield
.dword
6423 && i
.types
[1].bitfield
.instance
== Accum
6424 && i
.types
[1].bitfield
.dword
)
6426 /* xrelease mov %eax, <disp> is another special case. It must not
6427 match the accumulator-only encoding of mov. */
6428 if (flag_code
!= CODE_64BIT
6430 && t
->base_opcode
== 0xa0
6431 && i
.types
[0].bitfield
.instance
== Accum
6432 && (i
.flags
[1] & Operand_Mem
))
6437 if (!(size_match
& MATCH_STRAIGHT
))
6439 /* Reverse direction of operands if swapping is possible in the first
6440 place (operands need to be symmetric) and
6441 - the load form is requested, and the template is a store form,
6442 - the store form is requested, and the template is a load form,
6443 - the non-default (swapped) form is requested. */
6444 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6445 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6446 && !operand_type_all_zero (&overlap1
))
6447 switch (i
.dir_encoding
)
6449 case dir_encoding_load
:
6450 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6451 || t
->opcode_modifier
.regmem
)
6455 case dir_encoding_store
:
6456 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6457 && !t
->opcode_modifier
.regmem
)
6461 case dir_encoding_swap
:
6464 case dir_encoding_default
:
6467 /* If we want store form, we skip the current load. */
6468 if ((i
.dir_encoding
== dir_encoding_store
6469 || i
.dir_encoding
== dir_encoding_swap
)
6470 && i
.mem_operands
== 0
6471 && t
->opcode_modifier
.load
)
6476 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6477 if (!operand_type_match (overlap0
, i
.types
[0])
6478 || !operand_type_match (overlap1
, i
.types
[1])
6479 || ((check_register
& 3) == 3
6480 && !operand_type_register_match (i
.types
[0],
6485 /* Check if other direction is valid ... */
6486 if (!t
->opcode_modifier
.d
)
6490 if (!(size_match
& MATCH_REVERSE
))
6492 /* Try reversing direction of operands. */
6493 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6494 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6495 if (!operand_type_match (overlap0
, i
.types
[0])
6496 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6498 && !operand_type_register_match (i
.types
[0],
6499 operand_types
[i
.operands
- 1],
6500 i
.types
[i
.operands
- 1],
6503 /* Does not match either direction. */
6506 /* found_reverse_match holds which of D or FloatR
6508 if (!t
->opcode_modifier
.d
)
6509 found_reverse_match
= 0;
6510 else if (operand_types
[0].bitfield
.tbyte
)
6511 found_reverse_match
= Opcode_FloatD
;
6512 else if (operand_types
[0].bitfield
.xmmword
6513 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6514 || operand_types
[0].bitfield
.class == RegMMX
6515 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6516 || is_any_vex_encoding(t
))
6517 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6518 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6520 found_reverse_match
= Opcode_D
;
6521 if (t
->opcode_modifier
.floatr
)
6522 found_reverse_match
|= Opcode_FloatR
;
6526 /* Found a forward 2 operand match here. */
6527 switch (t
->operands
)
6530 overlap4
= operand_type_and (i
.types
[4],
6534 overlap3
= operand_type_and (i
.types
[3],
6538 overlap2
= operand_type_and (i
.types
[2],
6543 switch (t
->operands
)
6546 if (!operand_type_match (overlap4
, i
.types
[4])
6547 || !operand_type_register_match (i
.types
[3],
6554 if (!operand_type_match (overlap3
, i
.types
[3])
6555 || ((check_register
& 0xa) == 0xa
6556 && !operand_type_register_match (i
.types
[1],
6560 || ((check_register
& 0xc) == 0xc
6561 && !operand_type_register_match (i
.types
[2],
6568 /* Here we make use of the fact that there are no
6569 reverse match 3 operand instructions. */
6570 if (!operand_type_match (overlap2
, i
.types
[2])
6571 || ((check_register
& 5) == 5
6572 && !operand_type_register_match (i
.types
[0],
6576 || ((check_register
& 6) == 6
6577 && !operand_type_register_match (i
.types
[1],
6585 /* Found either forward/reverse 2, 3 or 4 operand match here:
6586 slip through to break. */
6589 /* Check if vector operands are valid. */
6590 if (check_VecOperands (t
))
6592 specific_error
= i
.error
;
6596 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6597 if (VEX_check_encoding (t
))
6599 specific_error
= i
.error
;
6603 /* We've found a match; break out of loop. */
6607 if (t
== current_templates
->end
)
6609 /* We found no match. */
6610 const char *err_msg
;
6611 switch (specific_error
? specific_error
: i
.error
)
6615 case operand_size_mismatch
:
6616 err_msg
= _("operand size mismatch");
6618 case operand_type_mismatch
:
6619 err_msg
= _("operand type mismatch");
6621 case register_type_mismatch
:
6622 err_msg
= _("register type mismatch");
6624 case number_of_operands_mismatch
:
6625 err_msg
= _("number of operands mismatch");
6627 case invalid_instruction_suffix
:
6628 err_msg
= _("invalid instruction suffix");
6631 err_msg
= _("constant doesn't fit in 4 bits");
6633 case unsupported_with_intel_mnemonic
:
6634 err_msg
= _("unsupported with Intel mnemonic");
6636 case unsupported_syntax
:
6637 err_msg
= _("unsupported syntax");
6640 as_bad (_("unsupported instruction `%s'"),
6641 current_templates
->start
->name
);
6643 case invalid_sib_address
:
6644 err_msg
= _("invalid SIB address");
6646 case invalid_vsib_address
:
6647 err_msg
= _("invalid VSIB address");
6649 case invalid_vector_register_set
:
6650 err_msg
= _("mask, index, and destination registers must be distinct");
6652 case invalid_tmm_register_set
:
6653 err_msg
= _("all tmm registers must be distinct");
6655 case unsupported_vector_index_register
:
6656 err_msg
= _("unsupported vector index register");
6658 case unsupported_broadcast
:
6659 err_msg
= _("unsupported broadcast");
6661 case broadcast_needed
:
6662 err_msg
= _("broadcast is needed for operand of such type");
6664 case unsupported_masking
:
6665 err_msg
= _("unsupported masking");
6667 case mask_not_on_destination
:
6668 err_msg
= _("mask not on destination operand");
6670 case no_default_mask
:
6671 err_msg
= _("default mask isn't allowed");
6673 case unsupported_rc_sae
:
6674 err_msg
= _("unsupported static rounding/sae");
6676 case rc_sae_operand_not_last_imm
:
6678 err_msg
= _("RC/SAE operand must precede immediate operands");
6680 err_msg
= _("RC/SAE operand must follow immediate operands");
6682 case invalid_register_operand
:
6683 err_msg
= _("invalid register operand");
6686 as_bad (_("%s for `%s'"), err_msg
,
6687 current_templates
->start
->name
);
6691 if (!quiet_warnings
)
6694 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6695 as_warn (_("indirect %s without `*'"), t
->name
);
6697 if (t
->opcode_modifier
.isprefix
6698 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6700 /* Warn them that a data or address size prefix doesn't
6701 affect assembly of the next line of code. */
6702 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6706 /* Copy the template we found. */
6709 if (addr_prefix_disp
!= -1)
6710 i
.tm
.operand_types
[addr_prefix_disp
]
6711 = operand_types
[addr_prefix_disp
];
6713 if (found_reverse_match
)
6715 /* If we found a reverse match we must alter the opcode direction
6716 bit and clear/flip the regmem modifier one. found_reverse_match
6717 holds bits to change (different for int & float insns). */
6719 i
.tm
.base_opcode
^= found_reverse_match
;
6721 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6722 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6724 /* Certain SIMD insns have their load forms specified in the opcode
6725 table, and hence we need to _set_ RegMem instead of clearing it.
6726 We need to avoid setting the bit though on insns like KMOVW. */
6727 i
.tm
.opcode_modifier
.regmem
6728 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6729 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6730 && !i
.tm
.opcode_modifier
.regmem
;
6739 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6740 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6742 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6744 as_bad (_("`%s' operand %u must use `%ses' segment"),
6746 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6751 /* There's only ever one segment override allowed per instruction.
6752 This instruction possibly has a legal segment override on the
6753 second operand, so copy the segment to where non-string
6754 instructions store it, allowing common code. */
6755 i
.seg
[op
] = i
.seg
[1];
6761 process_suffix (void)
6763 /* If matched instruction specifies an explicit instruction mnemonic
6765 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6766 i
.suffix
= WORD_MNEM_SUFFIX
;
6767 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6768 i
.suffix
= LONG_MNEM_SUFFIX
;
6769 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6770 i
.suffix
= QWORD_MNEM_SUFFIX
;
6771 else if (i
.reg_operands
6772 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6773 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6775 unsigned int numop
= i
.operands
;
6777 /* movsx/movzx want only their source operand considered here, for the
6778 ambiguity checking below. The suffix will be replaced afterwards
6779 to represent the destination (register). */
6780 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6781 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6784 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6785 if (i
.tm
.base_opcode
== 0xf20f38f0
6786 && i
.tm
.operand_types
[1].bitfield
.qword
)
6789 /* If there's no instruction mnemonic suffix we try to invent one
6790 based on GPR operands. */
6793 /* We take i.suffix from the last register operand specified,
6794 Destination register type is more significant than source
6795 register type. crc32 in SSE4.2 prefers source register
6797 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6800 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6801 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6803 if (i
.types
[op
].bitfield
.class != Reg
)
6805 if (i
.types
[op
].bitfield
.byte
)
6806 i
.suffix
= BYTE_MNEM_SUFFIX
;
6807 else if (i
.types
[op
].bitfield
.word
)
6808 i
.suffix
= WORD_MNEM_SUFFIX
;
6809 else if (i
.types
[op
].bitfield
.dword
)
6810 i
.suffix
= LONG_MNEM_SUFFIX
;
6811 else if (i
.types
[op
].bitfield
.qword
)
6812 i
.suffix
= QWORD_MNEM_SUFFIX
;
6818 /* As an exception, movsx/movzx silently default to a byte source
6820 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6821 && !i
.suffix
&& !intel_syntax
)
6822 i
.suffix
= BYTE_MNEM_SUFFIX
;
6824 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6827 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6828 && i
.tm
.opcode_modifier
.no_bsuf
)
6830 else if (!check_byte_reg ())
6833 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6836 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6837 && i
.tm
.opcode_modifier
.no_lsuf
6838 && !i
.tm
.opcode_modifier
.todword
6839 && !i
.tm
.opcode_modifier
.toqword
)
6841 else if (!check_long_reg ())
6844 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6847 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6848 && i
.tm
.opcode_modifier
.no_qsuf
6849 && !i
.tm
.opcode_modifier
.todword
6850 && !i
.tm
.opcode_modifier
.toqword
)
6852 else if (!check_qword_reg ())
6855 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6858 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6859 && i
.tm
.opcode_modifier
.no_wsuf
)
6861 else if (!check_word_reg ())
6864 else if (intel_syntax
6865 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6866 /* Do nothing if the instruction is going to ignore the prefix. */
6871 /* Undo the movsx/movzx change done above. */
6874 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6877 i
.suffix
= stackop_size
;
6878 if (stackop_size
== LONG_MNEM_SUFFIX
)
6880 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6881 .code16gcc directive to support 16-bit mode with
6882 32-bit address. For IRET without a suffix, generate
6883 16-bit IRET (opcode 0xcf) to return from an interrupt
6885 if (i
.tm
.base_opcode
== 0xcf)
6887 i
.suffix
= WORD_MNEM_SUFFIX
;
6888 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6890 /* Warn about changed behavior for segment register push/pop. */
6891 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6892 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6897 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6898 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6899 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6900 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6901 && i
.tm
.extension_opcode
<= 3)))
6906 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6908 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6909 || i
.tm
.opcode_modifier
.no_lsuf
)
6910 i
.suffix
= QWORD_MNEM_SUFFIX
;
6915 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6916 i
.suffix
= LONG_MNEM_SUFFIX
;
6919 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6920 i
.suffix
= WORD_MNEM_SUFFIX
;
6926 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6927 /* Also cover lret/retf/iret in 64-bit mode. */
6928 || (flag_code
== CODE_64BIT
6929 && !i
.tm
.opcode_modifier
.no_lsuf
6930 && !i
.tm
.opcode_modifier
.no_qsuf
))
6931 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6932 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6933 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6934 /* Accept FLDENV et al without suffix. */
6935 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6937 unsigned int suffixes
, evex
= 0;
6939 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6940 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6942 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6944 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6946 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6948 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6951 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6952 also suitable for AT&T syntax mode, it was requested that this be
6953 restricted to just Intel syntax. */
6954 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6958 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6960 if (is_evex_encoding (&i
.tm
)
6961 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6963 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6964 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6965 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6966 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6967 if (!i
.tm
.opcode_modifier
.evex
6968 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6969 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6972 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6973 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6974 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6977 /* Any properly sized operand disambiguates the insn. */
6978 if (i
.types
[op
].bitfield
.xmmword
6979 || i
.types
[op
].bitfield
.ymmword
6980 || i
.types
[op
].bitfield
.zmmword
)
6982 suffixes
&= ~(7 << 6);
6987 if ((i
.flags
[op
] & Operand_Mem
)
6988 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6990 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6992 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6994 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6996 if (is_evex_encoding (&i
.tm
))
7002 /* Are multiple suffixes / operand sizes allowed? */
7003 if (suffixes
& (suffixes
- 1))
7006 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7007 || operand_check
== check_error
))
7009 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7012 if (operand_check
== check_error
)
7014 as_bad (_("no instruction mnemonic suffix given and "
7015 "no register operands; can't size `%s'"), i
.tm
.name
);
7018 if (operand_check
== check_warning
)
7019 as_warn (_("%s; using default for `%s'"),
7021 ? _("ambiguous operand size")
7022 : _("no instruction mnemonic suffix given and "
7023 "no register operands"),
7026 if (i
.tm
.opcode_modifier
.floatmf
)
7027 i
.suffix
= SHORT_MNEM_SUFFIX
;
7028 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7029 || (i
.tm
.base_opcode
== 0x63
7030 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7031 /* handled below */;
7033 i
.tm
.opcode_modifier
.evex
= evex
;
7034 else if (flag_code
== CODE_16BIT
)
7035 i
.suffix
= WORD_MNEM_SUFFIX
;
7036 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7037 i
.suffix
= LONG_MNEM_SUFFIX
;
7039 i
.suffix
= QWORD_MNEM_SUFFIX
;
7043 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7044 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7046 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7047 In AT&T syntax, if there is no suffix (warned about above), the default
7048 will be byte extension. */
7049 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7050 i
.tm
.base_opcode
|= 1;
7052 /* For further processing, the suffix should represent the destination
7053 (register). This is already the case when one was used with
7054 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7055 no suffix to begin with. */
7056 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7058 if (i
.types
[1].bitfield
.word
)
7059 i
.suffix
= WORD_MNEM_SUFFIX
;
7060 else if (i
.types
[1].bitfield
.qword
)
7061 i
.suffix
= QWORD_MNEM_SUFFIX
;
7063 i
.suffix
= LONG_MNEM_SUFFIX
;
7065 i
.tm
.opcode_modifier
.w
= 0;
7069 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7070 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7071 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7073 /* Change the opcode based on the operand size given by i.suffix. */
7076 /* Size floating point instruction. */
7077 case LONG_MNEM_SUFFIX
:
7078 if (i
.tm
.opcode_modifier
.floatmf
)
7080 i
.tm
.base_opcode
^= 4;
7084 case WORD_MNEM_SUFFIX
:
7085 case QWORD_MNEM_SUFFIX
:
7086 /* It's not a byte, select word/dword operation. */
7087 if (i
.tm
.opcode_modifier
.w
)
7090 i
.tm
.base_opcode
|= 8;
7092 i
.tm
.base_opcode
|= 1;
7095 case SHORT_MNEM_SUFFIX
:
7096 /* Now select between word & dword operations via the operand
7097 size prefix, except for instructions that will ignore this
7099 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7100 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7101 && !i
.tm
.opcode_modifier
.floatmf
7102 && !is_any_vex_encoding (&i
.tm
)
7103 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7104 || (flag_code
== CODE_64BIT
7105 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7107 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7109 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7110 prefix
= ADDR_PREFIX_OPCODE
;
7112 if (!add_prefix (prefix
))
7116 /* Set mode64 for an operand. */
7117 if (i
.suffix
== QWORD_MNEM_SUFFIX
7118 && flag_code
== CODE_64BIT
7119 && !i
.tm
.opcode_modifier
.norex64
7120 && !i
.tm
.opcode_modifier
.vexw
7121 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7123 && ! (i
.operands
== 2
7124 && i
.tm
.base_opcode
== 0x90
7125 && i
.tm
.extension_opcode
== None
7126 && i
.types
[0].bitfield
.instance
== Accum
7127 && i
.types
[0].bitfield
.qword
7128 && i
.types
[1].bitfield
.instance
== Accum
7129 && i
.types
[1].bitfield
.qword
))
7135 /* Select word/dword/qword operation with explict data sizing prefix
7136 when there are no suitable register operands. */
7137 if (i
.tm
.opcode_modifier
.w
7138 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7140 || (i
.reg_operands
== 1
7142 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7144 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7145 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7147 || i
.tm
.base_opcode
== 0xf20f38f0))))
7148 i
.tm
.base_opcode
|= 1;
7152 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7154 gas_assert (!i
.suffix
);
7155 gas_assert (i
.reg_operands
);
7157 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7160 /* The address size override prefix changes the size of the
7162 if (flag_code
== CODE_64BIT
7163 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7165 as_bad (_("16-bit addressing unavailable for `%s'"),
7170 if ((flag_code
== CODE_32BIT
7171 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7172 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7173 && !add_prefix (ADDR_PREFIX_OPCODE
))
7178 /* Check invalid register operand when the address size override
7179 prefix changes the size of register operands. */
7181 enum { need_word
, need_dword
, need_qword
} need
;
7183 /* Check the register operand for the address size prefix if
7184 the memory operand has no real registers, like symbol, DISP
7186 if (i
.mem_operands
== 1
7187 && i
.reg_operands
== 1
7189 && i
.types
[1].bitfield
.class == Reg
7190 && (flag_code
== CODE_32BIT
7191 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7192 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7193 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7195 && i
.base_reg
->reg_num
== RegIP
7196 && i
.base_reg
->reg_type
.bitfield
.qword
))
7197 && !add_prefix (ADDR_PREFIX_OPCODE
))
7200 if (flag_code
== CODE_32BIT
)
7201 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7202 else if (i
.prefix
[ADDR_PREFIX
])
7205 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7207 for (op
= 0; op
< i
.operands
; op
++)
7209 if (i
.types
[op
].bitfield
.class != Reg
)
7215 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7219 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7223 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7228 as_bad (_("invalid register operand size for `%s'"),
7239 check_byte_reg (void)
7243 for (op
= i
.operands
; --op
>= 0;)
7245 /* Skip non-register operands. */
7246 if (i
.types
[op
].bitfield
.class != Reg
)
7249 /* If this is an eight bit register, it's OK. If it's the 16 or
7250 32 bit version of an eight bit register, we will just use the
7251 low portion, and that's OK too. */
7252 if (i
.types
[op
].bitfield
.byte
)
7255 /* I/O port address operands are OK too. */
7256 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7257 && i
.tm
.operand_types
[op
].bitfield
.word
)
7260 /* crc32 only wants its source operand checked here. */
7261 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7264 /* Any other register is bad. */
7265 as_bad (_("`%s%s' not allowed with `%s%c'"),
7266 register_prefix
, i
.op
[op
].regs
->reg_name
,
7267 i
.tm
.name
, i
.suffix
);
7274 check_long_reg (void)
7278 for (op
= i
.operands
; --op
>= 0;)
7279 /* Skip non-register operands. */
7280 if (i
.types
[op
].bitfield
.class != Reg
)
7282 /* Reject eight bit registers, except where the template requires
7283 them. (eg. movzb) */
7284 else if (i
.types
[op
].bitfield
.byte
7285 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7286 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7287 && (i
.tm
.operand_types
[op
].bitfield
.word
7288 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7290 as_bad (_("`%s%s' not allowed with `%s%c'"),
7292 i
.op
[op
].regs
->reg_name
,
7297 /* Error if the e prefix on a general reg is missing. */
7298 else if (i
.types
[op
].bitfield
.word
7299 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7300 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7301 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7303 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7304 register_prefix
, i
.op
[op
].regs
->reg_name
,
7308 /* Warn if the r prefix on a general reg is present. */
7309 else if (i
.types
[op
].bitfield
.qword
7310 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7311 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7312 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7315 && i
.tm
.opcode_modifier
.toqword
7316 && i
.types
[0].bitfield
.class != RegSIMD
)
7318 /* Convert to QWORD. We want REX byte. */
7319 i
.suffix
= QWORD_MNEM_SUFFIX
;
7323 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7324 register_prefix
, i
.op
[op
].regs
->reg_name
,
7333 check_qword_reg (void)
7337 for (op
= i
.operands
; --op
>= 0; )
7338 /* Skip non-register operands. */
7339 if (i
.types
[op
].bitfield
.class != Reg
)
7341 /* Reject eight bit registers, except where the template requires
7342 them. (eg. movzb) */
7343 else if (i
.types
[op
].bitfield
.byte
7344 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7345 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7346 && (i
.tm
.operand_types
[op
].bitfield
.word
7347 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7349 as_bad (_("`%s%s' not allowed with `%s%c'"),
7351 i
.op
[op
].regs
->reg_name
,
7356 /* Warn if the r prefix on a general reg is missing. */
7357 else if ((i
.types
[op
].bitfield
.word
7358 || i
.types
[op
].bitfield
.dword
)
7359 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7360 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7361 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7363 /* Prohibit these changes in the 64bit mode, since the
7364 lowering is more complicated. */
7366 && i
.tm
.opcode_modifier
.todword
7367 && i
.types
[0].bitfield
.class != RegSIMD
)
7369 /* Convert to DWORD. We don't want REX byte. */
7370 i
.suffix
= LONG_MNEM_SUFFIX
;
7374 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7375 register_prefix
, i
.op
[op
].regs
->reg_name
,
7384 check_word_reg (void)
7387 for (op
= i
.operands
; --op
>= 0;)
7388 /* Skip non-register operands. */
7389 if (i
.types
[op
].bitfield
.class != Reg
)
7391 /* Reject eight bit registers, except where the template requires
7392 them. (eg. movzb) */
7393 else if (i
.types
[op
].bitfield
.byte
7394 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7395 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7396 && (i
.tm
.operand_types
[op
].bitfield
.word
7397 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7399 as_bad (_("`%s%s' not allowed with `%s%c'"),
7401 i
.op
[op
].regs
->reg_name
,
7406 /* Error if the e or r prefix on a general reg is present. */
7407 else if ((i
.types
[op
].bitfield
.dword
7408 || i
.types
[op
].bitfield
.qword
)
7409 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7410 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7411 && i
.tm
.operand_types
[op
].bitfield
.word
)
7413 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7414 register_prefix
, i
.op
[op
].regs
->reg_name
,
7422 update_imm (unsigned int j
)
7424 i386_operand_type overlap
= i
.types
[j
];
7425 if ((overlap
.bitfield
.imm8
7426 || overlap
.bitfield
.imm8s
7427 || overlap
.bitfield
.imm16
7428 || overlap
.bitfield
.imm32
7429 || overlap
.bitfield
.imm32s
7430 || overlap
.bitfield
.imm64
)
7431 && !operand_type_equal (&overlap
, &imm8
)
7432 && !operand_type_equal (&overlap
, &imm8s
)
7433 && !operand_type_equal (&overlap
, &imm16
)
7434 && !operand_type_equal (&overlap
, &imm32
)
7435 && !operand_type_equal (&overlap
, &imm32s
)
7436 && !operand_type_equal (&overlap
, &imm64
))
7440 i386_operand_type temp
;
7442 operand_type_set (&temp
, 0);
7443 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7445 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7446 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7448 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7449 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7450 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7452 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7453 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7456 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7459 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7460 || operand_type_equal (&overlap
, &imm16_32
)
7461 || operand_type_equal (&overlap
, &imm16_32s
))
7463 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7468 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7469 overlap
= operand_type_and (overlap
, imm32s
);
7470 else if (i
.prefix
[DATA_PREFIX
])
7471 overlap
= operand_type_and (overlap
,
7472 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7473 if (!operand_type_equal (&overlap
, &imm8
)
7474 && !operand_type_equal (&overlap
, &imm8s
)
7475 && !operand_type_equal (&overlap
, &imm16
)
7476 && !operand_type_equal (&overlap
, &imm32
)
7477 && !operand_type_equal (&overlap
, &imm32s
)
7478 && !operand_type_equal (&overlap
, &imm64
))
7480 as_bad (_("no instruction mnemonic suffix given; "
7481 "can't determine immediate size"));
7485 i
.types
[j
] = overlap
;
7495 /* Update the first 2 immediate operands. */
7496 n
= i
.operands
> 2 ? 2 : i
.operands
;
7499 for (j
= 0; j
< n
; j
++)
7500 if (update_imm (j
) == 0)
7503 /* The 3rd operand can't be immediate operand. */
7504 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7511 process_operands (void)
7513 /* Default segment register this instruction will use for memory
7514 accesses. 0 means unknown. This is only for optimizing out
7515 unnecessary segment overrides. */
7516 const seg_entry
*default_seg
= 0;
7518 if (i
.tm
.opcode_modifier
.sse2avx
)
7520 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7522 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7523 i
.prefix
[REX_PREFIX
] = 0;
7526 /* ImmExt should be processed after SSE2AVX. */
7527 else if (i
.tm
.opcode_modifier
.immext
)
7530 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7532 unsigned int dupl
= i
.operands
;
7533 unsigned int dest
= dupl
- 1;
7536 /* The destination must be an xmm register. */
7537 gas_assert (i
.reg_operands
7538 && MAX_OPERANDS
> dupl
7539 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7541 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7542 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7544 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7546 /* Keep xmm0 for instructions with VEX prefix and 3
7548 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7549 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7554 /* We remove the first xmm0 and keep the number of
7555 operands unchanged, which in fact duplicates the
7557 for (j
= 1; j
< i
.operands
; j
++)
7559 i
.op
[j
- 1] = i
.op
[j
];
7560 i
.types
[j
- 1] = i
.types
[j
];
7561 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7562 i
.flags
[j
- 1] = i
.flags
[j
];
7566 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7568 gas_assert ((MAX_OPERANDS
- 1) > dupl
7569 && (i
.tm
.opcode_modifier
.vexsources
7572 /* Add the implicit xmm0 for instructions with VEX prefix
7574 for (j
= i
.operands
; j
> 0; j
--)
7576 i
.op
[j
] = i
.op
[j
- 1];
7577 i
.types
[j
] = i
.types
[j
- 1];
7578 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7579 i
.flags
[j
] = i
.flags
[j
- 1];
7582 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7583 i
.types
[0] = regxmm
;
7584 i
.tm
.operand_types
[0] = regxmm
;
7587 i
.reg_operands
+= 2;
7592 i
.op
[dupl
] = i
.op
[dest
];
7593 i
.types
[dupl
] = i
.types
[dest
];
7594 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7595 i
.flags
[dupl
] = i
.flags
[dest
];
7604 i
.op
[dupl
] = i
.op
[dest
];
7605 i
.types
[dupl
] = i
.types
[dest
];
7606 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7607 i
.flags
[dupl
] = i
.flags
[dest
];
7610 if (i
.tm
.opcode_modifier
.immext
)
7613 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7614 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7618 for (j
= 1; j
< i
.operands
; j
++)
7620 i
.op
[j
- 1] = i
.op
[j
];
7621 i
.types
[j
- 1] = i
.types
[j
];
7623 /* We need to adjust fields in i.tm since they are used by
7624 build_modrm_byte. */
7625 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7627 i
.flags
[j
- 1] = i
.flags
[j
];
7634 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7636 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7638 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7639 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7640 regnum
= register_number (i
.op
[1].regs
);
7641 first_reg_in_group
= regnum
& ~3;
7642 last_reg_in_group
= first_reg_in_group
+ 3;
7643 if (regnum
!= first_reg_in_group
)
7644 as_warn (_("source register `%s%s' implicitly denotes"
7645 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7646 register_prefix
, i
.op
[1].regs
->reg_name
,
7647 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7648 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7651 else if (i
.tm
.opcode_modifier
.regkludge
)
7653 /* The imul $imm, %reg instruction is converted into
7654 imul $imm, %reg, %reg, and the clr %reg instruction
7655 is converted into xor %reg, %reg. */
7657 unsigned int first_reg_op
;
7659 if (operand_type_check (i
.types
[0], reg
))
7663 /* Pretend we saw the extra register operand. */
7664 gas_assert (i
.reg_operands
== 1
7665 && i
.op
[first_reg_op
+ 1].regs
== 0);
7666 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7667 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7672 if (i
.tm
.opcode_modifier
.modrm
)
7674 /* The opcode is completed (modulo i.tm.extension_opcode which
7675 must be put into the modrm byte). Now, we make the modrm and
7676 index base bytes based on all the info we've collected. */
7678 default_seg
= build_modrm_byte ();
7680 else if (i
.types
[0].bitfield
.class == SReg
)
7682 if (flag_code
!= CODE_64BIT
7683 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7684 && i
.op
[0].regs
->reg_num
== 1
7685 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7686 && i
.op
[0].regs
->reg_num
< 4)
7688 as_bad (_("you can't `%s %s%s'"),
7689 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7692 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7694 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7695 i
.tm
.opcode_length
= 2;
7697 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7699 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7703 else if (i
.tm
.opcode_modifier
.isstring
)
7705 /* For the string instructions that allow a segment override
7706 on one of their operands, the default segment is ds. */
7709 else if (i
.short_form
)
7711 /* The register or float register operand is in operand
7713 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7715 /* Register goes in low 3 bits of opcode. */
7716 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7717 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7719 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7721 /* Warn about some common errors, but press on regardless.
7722 The first case can be generated by gcc (<= 2.8.1). */
7723 if (i
.operands
== 2)
7725 /* Reversed arguments on faddp, fsubp, etc. */
7726 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7727 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7728 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7732 /* Extraneous `l' suffix on fp insn. */
7733 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7734 register_prefix
, i
.op
[0].regs
->reg_name
);
7739 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7740 && i
.tm
.base_opcode
== 0x8d /* lea */
7741 && !is_any_vex_encoding(&i
.tm
))
7743 if (!quiet_warnings
)
7744 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7748 i
.prefix
[SEG_PREFIX
] = 0;
7752 /* If a segment was explicitly specified, and the specified segment
7753 is neither the default nor the one already recorded from a prefix,
7754 use an opcode prefix to select it. If we never figured out what
7755 the default segment is, then default_seg will be zero at this
7756 point, and the specified segment prefix will always be used. */
7758 && i
.seg
[0] != default_seg
7759 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7761 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7767 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7768 bfd_boolean do_sse2avx
)
7770 if (r
->reg_flags
& RegRex
)
7772 if (i
.rex
& rex_bit
)
7773 as_bad (_("same type of prefix used twice"));
7776 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7778 gas_assert (i
.vex
.register_specifier
== r
);
7779 i
.vex
.register_specifier
+= 8;
7782 if (r
->reg_flags
& RegVRex
)
7786 static const seg_entry
*
7787 build_modrm_byte (void)
7789 const seg_entry
*default_seg
= 0;
7790 unsigned int source
, dest
;
7793 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7796 unsigned int nds
, reg_slot
;
7799 dest
= i
.operands
- 1;
7802 /* There are 2 kinds of instructions:
7803 1. 5 operands: 4 register operands or 3 register operands
7804 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7805 VexW0 or VexW1. The destination must be either XMM, YMM or
7807 2. 4 operands: 4 register operands or 3 register operands
7808 plus 1 memory operand, with VexXDS. */
7809 gas_assert ((i
.reg_operands
== 4
7810 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7811 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7812 && i
.tm
.opcode_modifier
.vexw
7813 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7815 /* If VexW1 is set, the first non-immediate operand is the source and
7816 the second non-immediate one is encoded in the immediate operand. */
7817 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7819 source
= i
.imm_operands
;
7820 reg_slot
= i
.imm_operands
+ 1;
7824 source
= i
.imm_operands
+ 1;
7825 reg_slot
= i
.imm_operands
;
7828 if (i
.imm_operands
== 0)
7830 /* When there is no immediate operand, generate an 8bit
7831 immediate operand to encode the first operand. */
7832 exp
= &im_expressions
[i
.imm_operands
++];
7833 i
.op
[i
.operands
].imms
= exp
;
7834 i
.types
[i
.operands
] = imm8
;
7837 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7838 exp
->X_op
= O_constant
;
7839 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7840 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7844 gas_assert (i
.imm_operands
== 1);
7845 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7846 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7848 /* Turn on Imm8 again so that output_imm will generate it. */
7849 i
.types
[0].bitfield
.imm8
= 1;
7851 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7852 i
.op
[0].imms
->X_add_number
7853 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7854 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7857 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7858 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7863 /* i.reg_operands MUST be the number of real register operands;
7864 implicit registers do not count. If there are 3 register
7865 operands, it must be a instruction with VexNDS. For a
7866 instruction with VexNDD, the destination register is encoded
7867 in VEX prefix. If there are 4 register operands, it must be
7868 a instruction with VEX prefix and 3 sources. */
7869 if (i
.mem_operands
== 0
7870 && ((i
.reg_operands
== 2
7871 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7872 || (i
.reg_operands
== 3
7873 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7874 || (i
.reg_operands
== 4 && vex_3_sources
)))
7882 /* When there are 3 operands, one of them may be immediate,
7883 which may be the first or the last operand. Otherwise,
7884 the first operand must be shift count register (cl) or it
7885 is an instruction with VexNDS. */
7886 gas_assert (i
.imm_operands
== 1
7887 || (i
.imm_operands
== 0
7888 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7889 || (i
.types
[0].bitfield
.instance
== RegC
7890 && i
.types
[0].bitfield
.byte
))));
7891 if (operand_type_check (i
.types
[0], imm
)
7892 || (i
.types
[0].bitfield
.instance
== RegC
7893 && i
.types
[0].bitfield
.byte
))
7899 /* When there are 4 operands, the first two must be 8bit
7900 immediate operands. The source operand will be the 3rd
7903 For instructions with VexNDS, if the first operand
7904 an imm8, the source operand is the 2nd one. If the last
7905 operand is imm8, the source operand is the first one. */
7906 gas_assert ((i
.imm_operands
== 2
7907 && i
.types
[0].bitfield
.imm8
7908 && i
.types
[1].bitfield
.imm8
)
7909 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7910 && i
.imm_operands
== 1
7911 && (i
.types
[0].bitfield
.imm8
7912 || i
.types
[i
.operands
- 1].bitfield
.imm8
7914 if (i
.imm_operands
== 2)
7918 if (i
.types
[0].bitfield
.imm8
)
7925 if (is_evex_encoding (&i
.tm
))
7927 /* For EVEX instructions, when there are 5 operands, the
7928 first one must be immediate operand. If the second one
7929 is immediate operand, the source operand is the 3th
7930 one. If the last one is immediate operand, the source
7931 operand is the 2nd one. */
7932 gas_assert (i
.imm_operands
== 2
7933 && i
.tm
.opcode_modifier
.sae
7934 && operand_type_check (i
.types
[0], imm
));
7935 if (operand_type_check (i
.types
[1], imm
))
7937 else if (operand_type_check (i
.types
[4], imm
))
7951 /* RC/SAE operand could be between DEST and SRC. That happens
7952 when one operand is GPR and the other one is XMM/YMM/ZMM
7954 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7957 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7959 /* For instructions with VexNDS, the register-only source
7960 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7961 register. It is encoded in VEX prefix. */
7963 i386_operand_type op
;
7966 /* Swap two source operands if needed. */
7967 if (i
.tm
.opcode_modifier
.swapsources
)
7975 op
= i
.tm
.operand_types
[vvvv
];
7976 if ((dest
+ 1) >= i
.operands
7977 || ((op
.bitfield
.class != Reg
7978 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7979 && op
.bitfield
.class != RegSIMD
7980 && !operand_type_equal (&op
, ®mask
)))
7982 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7988 /* One of the register operands will be encoded in the i.rm.reg
7989 field, the other in the combined i.rm.mode and i.rm.regmem
7990 fields. If no form of this instruction supports a memory
7991 destination operand, then we assume the source operand may
7992 sometimes be a memory operand and so we need to store the
7993 destination in the i.rm.reg field. */
7994 if (!i
.tm
.opcode_modifier
.regmem
7995 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7997 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7998 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7999 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8000 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8004 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8005 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8006 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8007 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8009 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8011 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8014 add_prefix (LOCK_PREFIX_OPCODE
);
8018 { /* If it's not 2 reg operands... */
8023 unsigned int fake_zero_displacement
= 0;
8026 for (op
= 0; op
< i
.operands
; op
++)
8027 if (i
.flags
[op
] & Operand_Mem
)
8029 gas_assert (op
< i
.operands
);
8031 if (i
.tm
.opcode_modifier
.sib
)
8033 /* The index register of VSIB shouldn't be RegIZ. */
8034 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8035 && i
.index_reg
->reg_num
== RegIZ
)
8038 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8041 i
.sib
.base
= NO_BASE_REGISTER
;
8042 i
.sib
.scale
= i
.log2_scale_factor
;
8043 i
.types
[op
].bitfield
.disp8
= 0;
8044 i
.types
[op
].bitfield
.disp16
= 0;
8045 i
.types
[op
].bitfield
.disp64
= 0;
8046 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8048 /* Must be 32 bit */
8049 i
.types
[op
].bitfield
.disp32
= 1;
8050 i
.types
[op
].bitfield
.disp32s
= 0;
8054 i
.types
[op
].bitfield
.disp32
= 0;
8055 i
.types
[op
].bitfield
.disp32s
= 1;
8059 /* Since the mandatory SIB always has index register, so
8060 the code logic remains unchanged. The non-mandatory SIB
8061 without index register is allowed and will be handled
8065 if (i
.index_reg
->reg_num
== RegIZ
)
8066 i
.sib
.index
= NO_INDEX_REGISTER
;
8068 i
.sib
.index
= i
.index_reg
->reg_num
;
8069 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8075 if (i
.base_reg
== 0)
8078 if (!i
.disp_operands
)
8079 fake_zero_displacement
= 1;
8080 if (i
.index_reg
== 0)
8082 i386_operand_type newdisp
;
8084 /* Both check for VSIB and mandatory non-vector SIB. */
8085 gas_assert (!i
.tm
.opcode_modifier
.sib
8086 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8087 /* Operand is just <disp> */
8088 if (flag_code
== CODE_64BIT
)
8090 /* 64bit mode overwrites the 32bit absolute
8091 addressing by RIP relative addressing and
8092 absolute addressing is encoded by one of the
8093 redundant SIB forms. */
8094 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8095 i
.sib
.base
= NO_BASE_REGISTER
;
8096 i
.sib
.index
= NO_INDEX_REGISTER
;
8097 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8099 else if ((flag_code
== CODE_16BIT
)
8100 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8102 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8107 i
.rm
.regmem
= NO_BASE_REGISTER
;
8110 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8111 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8113 else if (!i
.tm
.opcode_modifier
.sib
)
8115 /* !i.base_reg && i.index_reg */
8116 if (i
.index_reg
->reg_num
== RegIZ
)
8117 i
.sib
.index
= NO_INDEX_REGISTER
;
8119 i
.sib
.index
= i
.index_reg
->reg_num
;
8120 i
.sib
.base
= NO_BASE_REGISTER
;
8121 i
.sib
.scale
= i
.log2_scale_factor
;
8122 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8123 i
.types
[op
].bitfield
.disp8
= 0;
8124 i
.types
[op
].bitfield
.disp16
= 0;
8125 i
.types
[op
].bitfield
.disp64
= 0;
8126 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8128 /* Must be 32 bit */
8129 i
.types
[op
].bitfield
.disp32
= 1;
8130 i
.types
[op
].bitfield
.disp32s
= 0;
8134 i
.types
[op
].bitfield
.disp32
= 0;
8135 i
.types
[op
].bitfield
.disp32s
= 1;
8137 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8141 /* RIP addressing for 64bit mode. */
8142 else if (i
.base_reg
->reg_num
== RegIP
)
8144 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8145 i
.rm
.regmem
= NO_BASE_REGISTER
;
8146 i
.types
[op
].bitfield
.disp8
= 0;
8147 i
.types
[op
].bitfield
.disp16
= 0;
8148 i
.types
[op
].bitfield
.disp32
= 0;
8149 i
.types
[op
].bitfield
.disp32s
= 1;
8150 i
.types
[op
].bitfield
.disp64
= 0;
8151 i
.flags
[op
] |= Operand_PCrel
;
8152 if (! i
.disp_operands
)
8153 fake_zero_displacement
= 1;
8155 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8157 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8158 switch (i
.base_reg
->reg_num
)
8161 if (i
.index_reg
== 0)
8163 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8164 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8168 if (i
.index_reg
== 0)
8171 if (operand_type_check (i
.types
[op
], disp
) == 0)
8173 /* fake (%bp) into 0(%bp) */
8174 if (i
.disp_encoding
== disp_encoding_16bit
)
8175 i
.types
[op
].bitfield
.disp16
= 1;
8177 i
.types
[op
].bitfield
.disp8
= 1;
8178 fake_zero_displacement
= 1;
8181 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8182 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8184 default: /* (%si) -> 4 or (%di) -> 5 */
8185 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8187 if (!fake_zero_displacement
8191 fake_zero_displacement
= 1;
8192 if (i
.disp_encoding
== disp_encoding_8bit
)
8193 i
.types
[op
].bitfield
.disp8
= 1;
8195 i
.types
[op
].bitfield
.disp16
= 1;
8197 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8199 else /* i.base_reg and 32/64 bit mode */
8201 if (flag_code
== CODE_64BIT
8202 && operand_type_check (i
.types
[op
], disp
))
8204 i
.types
[op
].bitfield
.disp16
= 0;
8205 i
.types
[op
].bitfield
.disp64
= 0;
8206 if (i
.prefix
[ADDR_PREFIX
] == 0)
8208 i
.types
[op
].bitfield
.disp32
= 0;
8209 i
.types
[op
].bitfield
.disp32s
= 1;
8213 i
.types
[op
].bitfield
.disp32
= 1;
8214 i
.types
[op
].bitfield
.disp32s
= 0;
8218 if (!i
.tm
.opcode_modifier
.sib
)
8219 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8220 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8222 i
.sib
.base
= i
.base_reg
->reg_num
;
8223 /* x86-64 ignores REX prefix bit here to avoid decoder
8225 if (!(i
.base_reg
->reg_flags
& RegRex
)
8226 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8227 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8229 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8231 fake_zero_displacement
= 1;
8232 if (i
.disp_encoding
== disp_encoding_32bit
)
8233 i
.types
[op
].bitfield
.disp32
= 1;
8235 i
.types
[op
].bitfield
.disp8
= 1;
8237 i
.sib
.scale
= i
.log2_scale_factor
;
8238 if (i
.index_reg
== 0)
8240 /* Only check for VSIB. */
8241 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8242 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8243 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8245 /* <disp>(%esp) becomes two byte modrm with no index
8246 register. We've already stored the code for esp
8247 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8248 Any base register besides %esp will not use the
8249 extra modrm byte. */
8250 i
.sib
.index
= NO_INDEX_REGISTER
;
8252 else if (!i
.tm
.opcode_modifier
.sib
)
8254 if (i
.index_reg
->reg_num
== RegIZ
)
8255 i
.sib
.index
= NO_INDEX_REGISTER
;
8257 i
.sib
.index
= i
.index_reg
->reg_num
;
8258 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8259 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8264 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8265 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8269 if (!fake_zero_displacement
8273 fake_zero_displacement
= 1;
8274 if (i
.disp_encoding
== disp_encoding_8bit
)
8275 i
.types
[op
].bitfield
.disp8
= 1;
8277 i
.types
[op
].bitfield
.disp32
= 1;
8279 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8283 if (fake_zero_displacement
)
8285 /* Fakes a zero displacement assuming that i.types[op]
8286 holds the correct displacement size. */
8289 gas_assert (i
.op
[op
].disps
== 0);
8290 exp
= &disp_expressions
[i
.disp_operands
++];
8291 i
.op
[op
].disps
= exp
;
8292 exp
->X_op
= O_constant
;
8293 exp
->X_add_number
= 0;
8294 exp
->X_add_symbol
= (symbolS
*) 0;
8295 exp
->X_op_symbol
= (symbolS
*) 0;
8303 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8305 if (operand_type_check (i
.types
[0], imm
))
8306 i
.vex
.register_specifier
= NULL
;
8309 /* VEX.vvvv encodes one of the sources when the first
8310 operand is not an immediate. */
8311 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8312 i
.vex
.register_specifier
= i
.op
[0].regs
;
8314 i
.vex
.register_specifier
= i
.op
[1].regs
;
8317 /* Destination is a XMM register encoded in the ModRM.reg
8319 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8320 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8323 /* ModRM.rm and VEX.B encodes the other source. */
8324 if (!i
.mem_operands
)
8328 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8329 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8331 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8333 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8337 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8339 i
.vex
.register_specifier
= i
.op
[2].regs
;
8340 if (!i
.mem_operands
)
8343 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8344 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8348 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8349 (if any) based on i.tm.extension_opcode. Again, we must be
8350 careful to make sure that segment/control/debug/test/MMX
8351 registers are coded into the i.rm.reg field. */
8352 else if (i
.reg_operands
)
8355 unsigned int vex_reg
= ~0;
8357 for (op
= 0; op
< i
.operands
; op
++)
8358 if (i
.types
[op
].bitfield
.class == Reg
8359 || i
.types
[op
].bitfield
.class == RegBND
8360 || i
.types
[op
].bitfield
.class == RegMask
8361 || i
.types
[op
].bitfield
.class == SReg
8362 || i
.types
[op
].bitfield
.class == RegCR
8363 || i
.types
[op
].bitfield
.class == RegDR
8364 || i
.types
[op
].bitfield
.class == RegTR
8365 || i
.types
[op
].bitfield
.class == RegSIMD
8366 || i
.types
[op
].bitfield
.class == RegMMX
)
8371 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8373 /* For instructions with VexNDS, the register-only
8374 source operand is encoded in VEX prefix. */
8375 gas_assert (mem
!= (unsigned int) ~0);
8380 gas_assert (op
< i
.operands
);
8384 /* Check register-only source operand when two source
8385 operands are swapped. */
8386 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8387 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8391 gas_assert (mem
== (vex_reg
+ 1)
8392 && op
< i
.operands
);
8397 gas_assert (vex_reg
< i
.operands
);
8401 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8403 /* For instructions with VexNDD, the register destination
8404 is encoded in VEX prefix. */
8405 if (i
.mem_operands
== 0)
8407 /* There is no memory operand. */
8408 gas_assert ((op
+ 2) == i
.operands
);
8413 /* There are only 2 non-immediate operands. */
8414 gas_assert (op
< i
.imm_operands
+ 2
8415 && i
.operands
== i
.imm_operands
+ 2);
8416 vex_reg
= i
.imm_operands
+ 1;
8420 gas_assert (op
< i
.operands
);
8422 if (vex_reg
!= (unsigned int) ~0)
8424 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8426 if ((type
->bitfield
.class != Reg
8427 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8428 && type
->bitfield
.class != RegSIMD
8429 && !operand_type_equal (type
, ®mask
))
8432 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8435 /* Don't set OP operand twice. */
8438 /* If there is an extension opcode to put here, the
8439 register number must be put into the regmem field. */
8440 if (i
.tm
.extension_opcode
!= None
)
8442 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8443 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8444 i
.tm
.opcode_modifier
.sse2avx
);
8448 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8449 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8450 i
.tm
.opcode_modifier
.sse2avx
);
8454 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8455 must set it to 3 to indicate this is a register operand
8456 in the regmem field. */
8457 if (!i
.mem_operands
)
8461 /* Fill in i.rm.reg field with extension opcode (if any). */
8462 if (i
.tm
.extension_opcode
!= None
)
8463 i
.rm
.reg
= i
.tm
.extension_opcode
;
8469 frag_opcode_byte (unsigned char byte
)
8471 if (now_seg
!= absolute_section
)
8472 FRAG_APPEND_1_CHAR (byte
);
8474 ++abs_section_offset
;
8478 flip_code16 (unsigned int code16
)
8480 gas_assert (i
.tm
.operands
== 1);
8482 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8483 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8484 || i
.tm
.operand_types
[0].bitfield
.disp32s
8485 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8490 output_branch (void)
8496 relax_substateT subtype
;
8500 if (now_seg
== absolute_section
)
8502 as_bad (_("relaxable branches not supported in absolute section"));
8506 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8507 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8510 if (i
.prefix
[DATA_PREFIX
] != 0)
8514 code16
^= flip_code16(code16
);
8516 /* Pentium4 branch hints. */
8517 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8518 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8523 if (i
.prefix
[REX_PREFIX
] != 0)
8529 /* BND prefixed jump. */
8530 if (i
.prefix
[BND_PREFIX
] != 0)
8536 if (i
.prefixes
!= 0)
8537 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8539 /* It's always a symbol; End frag & setup for relax.
8540 Make sure there is enough room in this frag for the largest
8541 instruction we may generate in md_convert_frag. This is 2
8542 bytes for the opcode and room for the prefix and largest
8544 frag_grow (prefix
+ 2 + 4);
8545 /* Prefix and 1 opcode byte go in fr_fix. */
8546 p
= frag_more (prefix
+ 1);
8547 if (i
.prefix
[DATA_PREFIX
] != 0)
8548 *p
++ = DATA_PREFIX_OPCODE
;
8549 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8550 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8551 *p
++ = i
.prefix
[SEG_PREFIX
];
8552 if (i
.prefix
[BND_PREFIX
] != 0)
8553 *p
++ = BND_PREFIX_OPCODE
;
8554 if (i
.prefix
[REX_PREFIX
] != 0)
8555 *p
++ = i
.prefix
[REX_PREFIX
];
8556 *p
= i
.tm
.base_opcode
;
8558 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8559 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8560 else if (cpu_arch_flags
.bitfield
.cpui386
)
8561 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8563 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8566 sym
= i
.op
[0].disps
->X_add_symbol
;
8567 off
= i
.op
[0].disps
->X_add_number
;
8569 if (i
.op
[0].disps
->X_op
!= O_constant
8570 && i
.op
[0].disps
->X_op
!= O_symbol
)
8572 /* Handle complex expressions. */
8573 sym
= make_expr_symbol (i
.op
[0].disps
);
8577 /* 1 possible extra opcode + 4 byte displacement go in var part.
8578 Pass reloc in fr_var. */
8579 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8583 /* Return TRUE iff PLT32 relocation should be used for branching to
8587 need_plt32_p (symbolS
*s
)
8589 /* PLT32 relocation is ELF only. */
8594 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8595 krtld support it. */
8599 /* Since there is no need to prepare for PLT branch on x86-64, we
8600 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8601 be used as a marker for 32-bit PC-relative branches. */
8605 /* Weak or undefined symbol need PLT32 relocation. */
8606 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8609 /* Non-global symbol doesn't need PLT32 relocation. */
8610 if (! S_IS_EXTERNAL (s
))
8613 /* Other global symbols need PLT32 relocation. NB: Symbol with
8614 non-default visibilities are treated as normal global symbol
8615 so that PLT32 relocation can be used as a marker for 32-bit
8616 PC-relative branches. It is useful for linker relaxation. */
8627 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8629 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8631 /* This is a loop or jecxz type instruction. */
8633 if (i
.prefix
[ADDR_PREFIX
] != 0)
8635 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8638 /* Pentium4 branch hints. */
8639 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8640 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8642 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8651 if (flag_code
== CODE_16BIT
)
8654 if (i
.prefix
[DATA_PREFIX
] != 0)
8656 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8658 code16
^= flip_code16(code16
);
8666 /* BND prefixed jump. */
8667 if (i
.prefix
[BND_PREFIX
] != 0)
8669 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8673 if (i
.prefix
[REX_PREFIX
] != 0)
8675 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8679 if (i
.prefixes
!= 0)
8680 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8682 if (now_seg
== absolute_section
)
8684 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8688 p
= frag_more (i
.tm
.opcode_length
+ size
);
8689 switch (i
.tm
.opcode_length
)
8692 *p
++ = i
.tm
.base_opcode
>> 8;
8695 *p
++ = i
.tm
.base_opcode
;
8701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8703 && jump_reloc
== NO_RELOC
8704 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8705 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8708 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8710 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8711 i
.op
[0].disps
, 1, jump_reloc
);
8713 /* All jumps handled here are signed, but don't use a signed limit
8714 check for 32 and 16 bit jumps as we want to allow wrap around at
8715 4G and 64k respectively. */
8717 fixP
->fx_signed
= 1;
8721 output_interseg_jump (void)
8729 if (flag_code
== CODE_16BIT
)
8733 if (i
.prefix
[DATA_PREFIX
] != 0)
8740 gas_assert (!i
.prefix
[REX_PREFIX
]);
8746 if (i
.prefixes
!= 0)
8747 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8749 if (now_seg
== absolute_section
)
8751 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8755 /* 1 opcode; 2 segment; offset */
8756 p
= frag_more (prefix
+ 1 + 2 + size
);
8758 if (i
.prefix
[DATA_PREFIX
] != 0)
8759 *p
++ = DATA_PREFIX_OPCODE
;
8761 if (i
.prefix
[REX_PREFIX
] != 0)
8762 *p
++ = i
.prefix
[REX_PREFIX
];
8764 *p
++ = i
.tm
.base_opcode
;
8765 if (i
.op
[1].imms
->X_op
== O_constant
)
8767 offsetT n
= i
.op
[1].imms
->X_add_number
;
8770 && !fits_in_unsigned_word (n
)
8771 && !fits_in_signed_word (n
))
8773 as_bad (_("16-bit jump out of range"));
8776 md_number_to_chars (p
, n
, size
);
8779 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8780 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8783 if (i
.op
[0].imms
->X_op
== O_constant
)
8784 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8786 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8787 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8795 asection
*seg
= now_seg
;
8796 subsegT subseg
= now_subseg
;
8798 unsigned int alignment
, align_size_1
;
8799 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8800 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8801 unsigned int padding
;
8803 if (!IS_ELF
|| !x86_used_note
)
8806 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8808 /* The .note.gnu.property section layout:
8810 Field Length Contents
8813 n_descsz 4 The note descriptor size
8814 n_type 4 NT_GNU_PROPERTY_TYPE_0
8816 n_desc n_descsz The program property array
8820 /* Create the .note.gnu.property section. */
8821 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8822 bfd_set_section_flags (sec
,
8829 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8840 bfd_set_section_alignment (sec
, alignment
);
8841 elf_section_type (sec
) = SHT_NOTE
;
8843 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8845 isa_1_descsz_raw
= 4 + 4 + 4;
8846 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8847 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8849 feature_2_descsz_raw
= isa_1_descsz
;
8850 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8852 feature_2_descsz_raw
+= 4 + 4 + 4;
8853 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8854 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8857 descsz
= feature_2_descsz
;
8858 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8859 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8861 /* Write n_namsz. */
8862 md_number_to_chars (p
, (valueT
) 4, 4);
8864 /* Write n_descsz. */
8865 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8868 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8871 memcpy (p
+ 4 * 3, "GNU", 4);
8873 /* Write 4-byte type. */
8874 md_number_to_chars (p
+ 4 * 4,
8875 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8877 /* Write 4-byte data size. */
8878 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8880 /* Write 4-byte data. */
8881 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8883 /* Zero out paddings. */
8884 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8886 memset (p
+ 4 * 7, 0, padding
);
8888 /* Write 4-byte type. */
8889 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8890 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8892 /* Write 4-byte data size. */
8893 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8895 /* Write 4-byte data. */
8896 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8897 (valueT
) x86_feature_2_used
, 4);
8899 /* Zero out paddings. */
8900 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8902 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8904 /* We probably can't restore the current segment, for there likely
8907 subseg_set (seg
, subseg
);
8912 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8913 const char *frag_now_ptr
)
8915 unsigned int len
= 0;
8917 if (start_frag
!= frag_now
)
8919 const fragS
*fr
= start_frag
;
8924 } while (fr
&& fr
!= frag_now
);
8927 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8930 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8931 be macro-fused with conditional jumps.
8932 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8933 or is one of the following format:
8946 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8948 /* No RIP address. */
8949 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8952 /* No VEX/EVEX encoding. */
8953 if (is_any_vex_encoding (&i
.tm
))
8956 /* add, sub without add/sub m, imm. */
8957 if (i
.tm
.base_opcode
<= 5
8958 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8959 || ((i
.tm
.base_opcode
| 3) == 0x83
8960 && (i
.tm
.extension_opcode
== 0x5
8961 || i
.tm
.extension_opcode
== 0x0)))
8963 *mf_cmp_p
= mf_cmp_alu_cmp
;
8964 return !(i
.mem_operands
&& i
.imm_operands
);
8967 /* and without and m, imm. */
8968 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8969 || ((i
.tm
.base_opcode
| 3) == 0x83
8970 && i
.tm
.extension_opcode
== 0x4))
8972 *mf_cmp_p
= mf_cmp_test_and
;
8973 return !(i
.mem_operands
&& i
.imm_operands
);
8976 /* test without test m imm. */
8977 if ((i
.tm
.base_opcode
| 1) == 0x85
8978 || (i
.tm
.base_opcode
| 1) == 0xa9
8979 || ((i
.tm
.base_opcode
| 1) == 0xf7
8980 && i
.tm
.extension_opcode
== 0))
8982 *mf_cmp_p
= mf_cmp_test_and
;
8983 return !(i
.mem_operands
&& i
.imm_operands
);
8986 /* cmp without cmp m, imm. */
8987 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8988 || ((i
.tm
.base_opcode
| 3) == 0x83
8989 && (i
.tm
.extension_opcode
== 0x7)))
8991 *mf_cmp_p
= mf_cmp_alu_cmp
;
8992 return !(i
.mem_operands
&& i
.imm_operands
);
8995 /* inc, dec without inc/dec m. */
8996 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8997 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8998 || ((i
.tm
.base_opcode
| 1) == 0xff
8999 && i
.tm
.extension_opcode
<= 0x1))
9001 *mf_cmp_p
= mf_cmp_incdec
;
9002 return !i
.mem_operands
;
9008 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9011 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9013 /* NB: Don't work with COND_JUMP86 without i386. */
9014 if (!align_branch_power
9015 || now_seg
== absolute_section
9016 || !cpu_arch_flags
.bitfield
.cpui386
9017 || !(align_branch
& align_branch_fused_bit
))
9020 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9022 if (last_insn
.kind
== last_insn_other
9023 || last_insn
.seg
!= now_seg
)
9026 as_warn_where (last_insn
.file
, last_insn
.line
,
9027 _("`%s` skips -malign-branch-boundary on `%s`"),
9028 last_insn
.name
, i
.tm
.name
);
9034 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9037 add_branch_prefix_frag_p (void)
9039 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9040 to PadLock instructions since they include prefixes in opcode. */
9041 if (!align_branch_power
9042 || !align_branch_prefix_size
9043 || now_seg
== absolute_section
9044 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9045 || !cpu_arch_flags
.bitfield
.cpui386
)
9048 /* Don't add prefix if it is a prefix or there is no operand in case
9049 that segment prefix is special. */
9050 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9053 if (last_insn
.kind
== last_insn_other
9054 || last_insn
.seg
!= now_seg
)
9058 as_warn_where (last_insn
.file
, last_insn
.line
,
9059 _("`%s` skips -malign-branch-boundary on `%s`"),
9060 last_insn
.name
, i
.tm
.name
);
9065 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9068 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9069 enum mf_jcc_kind
*mf_jcc_p
)
9073 /* NB: Don't work with COND_JUMP86 without i386. */
9074 if (!align_branch_power
9075 || now_seg
== absolute_section
9076 || !cpu_arch_flags
.bitfield
.cpui386
)
9081 /* Check for jcc and direct jmp. */
9082 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9084 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9086 *branch_p
= align_branch_jmp
;
9087 add_padding
= align_branch
& align_branch_jmp_bit
;
9091 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9092 igore the lowest bit. */
9093 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9094 *branch_p
= align_branch_jcc
;
9095 if ((align_branch
& align_branch_jcc_bit
))
9099 else if (is_any_vex_encoding (&i
.tm
))
9101 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9104 *branch_p
= align_branch_ret
;
9105 if ((align_branch
& align_branch_ret_bit
))
9110 /* Check for indirect jmp, direct and indirect calls. */
9111 if (i
.tm
.base_opcode
== 0xe8)
9114 *branch_p
= align_branch_call
;
9115 if ((align_branch
& align_branch_call_bit
))
9118 else if (i
.tm
.base_opcode
== 0xff
9119 && (i
.tm
.extension_opcode
== 2
9120 || i
.tm
.extension_opcode
== 4))
9122 /* Indirect call and jmp. */
9123 *branch_p
= align_branch_indirect
;
9124 if ((align_branch
& align_branch_indirect_bit
))
9131 && (i
.op
[0].disps
->X_op
== O_symbol
9132 || (i
.op
[0].disps
->X_op
== O_subtract
9133 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9135 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9136 /* No padding to call to global or undefined tls_get_addr. */
9137 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9138 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9144 && last_insn
.kind
!= last_insn_other
9145 && last_insn
.seg
== now_seg
)
9148 as_warn_where (last_insn
.file
, last_insn
.line
,
9149 _("`%s` skips -malign-branch-boundary on `%s`"),
9150 last_insn
.name
, i
.tm
.name
);
9160 fragS
*insn_start_frag
;
9161 offsetT insn_start_off
;
9162 fragS
*fragP
= NULL
;
9163 enum align_branch_kind branch
= align_branch_none
;
9164 /* The initializer is arbitrary just to avoid uninitialized error.
9165 it's actually either assigned in add_branch_padding_frag_p
9166 or never be used. */
9167 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9170 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9172 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9173 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9174 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9176 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9177 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9178 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9179 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9180 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9181 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9182 /* LAHF-SAHF insns in 64-bit mode. */
9183 || (flag_code
== CODE_64BIT
9184 && (i
.tm
.base_opcode
| 1) == 0x9f))
9185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9186 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9187 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9188 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9189 CpuAVX512DQ, LPW, TBM and AMX. */
9190 || (i
.tm
.opcode_modifier
.vex
9191 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9192 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9193 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9194 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9195 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9196 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9197 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9198 || i
.tm
.cpu_flags
.bitfield
.cpufma
9199 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9200 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9201 || i
.tm
.cpu_flags
.bitfield
.cpuxsave
9202 || i
.tm
.cpu_flags
.bitfield
.cpuxsavec
9203 || i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
9204 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
)
9205 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9206 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9207 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9208 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9209 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9210 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9212 || (i
.tm
.opcode_modifier
.evex
9213 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9214 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9215 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9216 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9218 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9219 || i
.tm
.cpu_flags
.bitfield
.cpu287
9220 || i
.tm
.cpu_flags
.bitfield
.cpu387
9221 || i
.tm
.cpu_flags
.bitfield
.cpu687
9222 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9223 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9224 if ((i
.xstate
& xstate_mmx
)
9225 || i
.tm
.base_opcode
== 0xf77 /* emms */
9226 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9227 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9230 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9231 i
.xstate
|= xstate_zmm
;
9232 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9233 i
.xstate
|= xstate_ymm
;
9234 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9235 i
.xstate
|= xstate_xmm
;
9237 if ((i
.xstate
& xstate_xmm
)
9238 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9239 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9240 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9241 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9242 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9243 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9244 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9245 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9246 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9247 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9248 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9249 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9250 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9251 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9252 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9253 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9254 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9258 /* Tie dwarf2 debug info to the address at the start of the insn.
9259 We can't do this after the insn has been output as the current
9260 frag may have been closed off. eg. by frag_var. */
9261 dwarf2_emit_insn (0);
9263 insn_start_frag
= frag_now
;
9264 insn_start_off
= frag_now_fix ();
9266 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9269 /* Branch can be 8 bytes. Leave some room for prefixes. */
9270 unsigned int max_branch_padding_size
= 14;
9272 /* Align section to boundary. */
9273 record_alignment (now_seg
, align_branch_power
);
9275 /* Make room for padding. */
9276 frag_grow (max_branch_padding_size
);
9278 /* Start of the padding. */
9283 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9284 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9287 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9288 fragP
->tc_frag_data
.branch_type
= branch
;
9289 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9293 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9295 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9296 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9298 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9299 output_interseg_jump ();
9302 /* Output normal instructions here. */
9306 unsigned int prefix
;
9307 enum mf_cmp_kind mf_cmp
;
9310 && (i
.tm
.base_opcode
== 0xfaee8
9311 || i
.tm
.base_opcode
== 0xfaef0
9312 || i
.tm
.base_opcode
== 0xfaef8))
9314 /* Encode lfence, mfence, and sfence as
9315 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9316 if (now_seg
!= absolute_section
)
9318 offsetT val
= 0x240483f0ULL
;
9321 md_number_to_chars (p
, val
, 5);
9324 abs_section_offset
+= 5;
9328 /* Some processors fail on LOCK prefix. This options makes
9329 assembler ignore LOCK prefix and serves as a workaround. */
9330 if (omit_lock_prefix
)
9332 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9334 i
.prefix
[LOCK_PREFIX
] = 0;
9338 /* Skip if this is a branch. */
9340 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9342 /* Make room for padding. */
9343 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9348 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9349 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9352 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9353 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9354 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9356 else if (add_branch_prefix_frag_p ())
9358 unsigned int max_prefix_size
= align_branch_prefix_size
;
9360 /* Make room for padding. */
9361 frag_grow (max_prefix_size
);
9366 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9367 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9370 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9373 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9374 don't need the explicit prefix. */
9375 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9377 switch (i
.tm
.opcode_length
)
9380 if (i
.tm
.base_opcode
& 0xff000000)
9382 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9383 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9384 || prefix
!= REPE_PREFIX_OPCODE
9385 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9386 add_prefix (prefix
);
9390 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9392 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9393 add_prefix (prefix
);
9399 /* Check for pseudo prefixes. */
9400 as_bad_where (insn_start_frag
->fr_file
,
9401 insn_start_frag
->fr_line
,
9402 _("pseudo prefix without instruction"));
9408 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9409 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9410 R_X86_64_GOTTPOFF relocation so that linker can safely
9411 perform IE->LE optimization. A dummy REX_OPCODE prefix
9412 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9413 relocation for GDesc -> IE/LE optimization. */
9414 if (x86_elf_abi
== X86_64_X32_ABI
9416 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9417 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9418 && i
.prefix
[REX_PREFIX
] == 0)
9419 add_prefix (REX_OPCODE
);
9422 /* The prefix bytes. */
9423 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9425 frag_opcode_byte (*q
);
9429 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9435 frag_opcode_byte (*q
);
9438 /* There should be no other prefixes for instructions
9443 /* For EVEX instructions i.vrex should become 0 after
9444 build_evex_prefix. For VEX instructions upper 16 registers
9445 aren't available, so VREX should be 0. */
9448 /* Now the VEX prefix. */
9449 if (now_seg
!= absolute_section
)
9451 p
= frag_more (i
.vex
.length
);
9452 for (j
= 0; j
< i
.vex
.length
; j
++)
9453 p
[j
] = i
.vex
.bytes
[j
];
9456 abs_section_offset
+= i
.vex
.length
;
9459 /* Now the opcode; be careful about word order here! */
9460 if (now_seg
== absolute_section
)
9461 abs_section_offset
+= i
.tm
.opcode_length
;
9462 else if (i
.tm
.opcode_length
== 1)
9464 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9468 switch (i
.tm
.opcode_length
)
9472 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9473 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9477 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9487 /* Put out high byte first: can't use md_number_to_chars! */
9488 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9489 *p
= i
.tm
.base_opcode
& 0xff;
9492 /* Now the modrm byte and sib byte (if present). */
9493 if (i
.tm
.opcode_modifier
.modrm
)
9495 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9497 | (i
.rm
.mode
<< 6));
9498 /* If i.rm.regmem == ESP (4)
9499 && i.rm.mode != (Register mode)
9501 ==> need second modrm byte. */
9502 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9504 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9505 frag_opcode_byte ((i
.sib
.base
<< 0)
9506 | (i
.sib
.index
<< 3)
9507 | (i
.sib
.scale
<< 6));
9510 if (i
.disp_operands
)
9511 output_disp (insn_start_frag
, insn_start_off
);
9514 output_imm (insn_start_frag
, insn_start_off
);
9517 * frag_now_fix () returning plain abs_section_offset when we're in the
9518 * absolute section, and abs_section_offset not getting updated as data
9519 * gets added to the frag breaks the logic below.
9521 if (now_seg
!= absolute_section
)
9523 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9525 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9529 /* NB: Don't add prefix with GOTPC relocation since
9530 output_disp() above depends on the fixed encoding
9531 length. Can't add prefix with TLS relocation since
9532 it breaks TLS linker optimization. */
9533 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9534 /* Prefix count on the current instruction. */
9535 unsigned int count
= i
.vex
.length
;
9537 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9538 /* REX byte is encoded in VEX/EVEX prefix. */
9539 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9542 /* Count prefixes for extended opcode maps. */
9544 switch (i
.tm
.opcode_length
)
9547 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9550 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9562 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9571 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9574 /* Set the maximum prefix size in BRANCH_PREFIX
9576 if (fragP
->tc_frag_data
.max_bytes
> max
)
9577 fragP
->tc_frag_data
.max_bytes
= max
;
9578 if (fragP
->tc_frag_data
.max_bytes
> count
)
9579 fragP
->tc_frag_data
.max_bytes
-= count
;
9581 fragP
->tc_frag_data
.max_bytes
= 0;
9585 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9587 unsigned int max_prefix_size
;
9588 if (align_branch_prefix_size
> max
)
9589 max_prefix_size
= max
;
9591 max_prefix_size
= align_branch_prefix_size
;
9592 if (max_prefix_size
> count
)
9593 fragP
->tc_frag_data
.max_prefix_length
9594 = max_prefix_size
- count
;
9597 /* Use existing segment prefix if possible. Use CS
9598 segment prefix in 64-bit mode. In 32-bit mode, use SS
9599 segment prefix with ESP/EBP base register and use DS
9600 segment prefix without ESP/EBP base register. */
9601 if (i
.prefix
[SEG_PREFIX
])
9602 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9603 else if (flag_code
== CODE_64BIT
)
9604 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9606 && (i
.base_reg
->reg_num
== 4
9607 || i
.base_reg
->reg_num
== 5))
9608 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9610 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9615 /* NB: Don't work with COND_JUMP86 without i386. */
9616 if (align_branch_power
9617 && now_seg
!= absolute_section
9618 && cpu_arch_flags
.bitfield
.cpui386
)
9620 /* Terminate each frag so that we can add prefix and check for
9622 frag_wane (frag_now
);
9629 pi ("" /*line*/, &i
);
9631 #endif /* DEBUG386 */
9634 /* Return the size of the displacement operand N. */
9637 disp_size (unsigned int n
)
9641 if (i
.types
[n
].bitfield
.disp64
)
9643 else if (i
.types
[n
].bitfield
.disp8
)
9645 else if (i
.types
[n
].bitfield
.disp16
)
9650 /* Return the size of the immediate operand N. */
9653 imm_size (unsigned int n
)
9656 if (i
.types
[n
].bitfield
.imm64
)
9658 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9660 else if (i
.types
[n
].bitfield
.imm16
)
9666 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9671 for (n
= 0; n
< i
.operands
; n
++)
9673 if (operand_type_check (i
.types
[n
], disp
))
9675 int size
= disp_size (n
);
9677 if (now_seg
== absolute_section
)
9678 abs_section_offset
+= size
;
9679 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9681 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9683 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9685 p
= frag_more (size
);
9686 md_number_to_chars (p
, val
, size
);
9690 enum bfd_reloc_code_real reloc_type
;
9691 int sign
= i
.types
[n
].bitfield
.disp32s
;
9692 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9695 /* We can't have 8 bit displacement here. */
9696 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9698 /* The PC relative address is computed relative
9699 to the instruction boundary, so in case immediate
9700 fields follows, we need to adjust the value. */
9701 if (pcrel
&& i
.imm_operands
)
9706 for (n1
= 0; n1
< i
.operands
; n1
++)
9707 if (operand_type_check (i
.types
[n1
], imm
))
9709 /* Only one immediate is allowed for PC
9710 relative address. */
9711 gas_assert (sz
== 0);
9713 i
.op
[n
].disps
->X_add_number
-= sz
;
9715 /* We should find the immediate. */
9716 gas_assert (sz
!= 0);
9719 p
= frag_more (size
);
9720 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9722 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9723 && (((reloc_type
== BFD_RELOC_32
9724 || reloc_type
== BFD_RELOC_X86_64_32S
9725 || (reloc_type
== BFD_RELOC_64
9727 && (i
.op
[n
].disps
->X_op
== O_symbol
9728 || (i
.op
[n
].disps
->X_op
== O_add
9729 && ((symbol_get_value_expression
9730 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9732 || reloc_type
== BFD_RELOC_32_PCREL
))
9736 reloc_type
= BFD_RELOC_386_GOTPC
;
9737 i
.has_gotpc_tls_reloc
= TRUE
;
9738 i
.op
[n
].imms
->X_add_number
+=
9739 encoding_length (insn_start_frag
, insn_start_off
, p
);
9741 else if (reloc_type
== BFD_RELOC_64
)
9742 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9744 /* Don't do the adjustment for x86-64, as there
9745 the pcrel addressing is relative to the _next_
9746 insn, and that is taken care of in other code. */
9747 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9749 else if (align_branch_power
)
9753 case BFD_RELOC_386_TLS_GD
:
9754 case BFD_RELOC_386_TLS_LDM
:
9755 case BFD_RELOC_386_TLS_IE
:
9756 case BFD_RELOC_386_TLS_IE_32
:
9757 case BFD_RELOC_386_TLS_GOTIE
:
9758 case BFD_RELOC_386_TLS_GOTDESC
:
9759 case BFD_RELOC_386_TLS_DESC_CALL
:
9760 case BFD_RELOC_X86_64_TLSGD
:
9761 case BFD_RELOC_X86_64_TLSLD
:
9762 case BFD_RELOC_X86_64_GOTTPOFF
:
9763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9764 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9765 i
.has_gotpc_tls_reloc
= TRUE
;
9770 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9771 size
, i
.op
[n
].disps
, pcrel
,
9773 /* Check for "call/jmp *mem", "mov mem, %reg",
9774 "test %reg, mem" and "binop mem, %reg" where binop
9775 is one of adc, add, and, cmp, or, sbb, sub, xor
9776 instructions without data prefix. Always generate
9777 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9778 if (i
.prefix
[DATA_PREFIX
] == 0
9779 && (generate_relax_relocations
9782 && i
.rm
.regmem
== 5))
9784 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9785 && !is_any_vex_encoding(&i
.tm
)
9786 && ((i
.operands
== 1
9787 && i
.tm
.base_opcode
== 0xff
9788 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9790 && (i
.tm
.base_opcode
== 0x8b
9791 || i
.tm
.base_opcode
== 0x85
9792 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9796 fixP
->fx_tcbit
= i
.rex
!= 0;
9798 && (i
.base_reg
->reg_num
== RegIP
))
9799 fixP
->fx_tcbit2
= 1;
9802 fixP
->fx_tcbit2
= 1;
9810 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9815 for (n
= 0; n
< i
.operands
; n
++)
9817 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9818 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9821 if (operand_type_check (i
.types
[n
], imm
))
9823 int size
= imm_size (n
);
9825 if (now_seg
== absolute_section
)
9826 abs_section_offset
+= size
;
9827 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9831 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9833 p
= frag_more (size
);
9834 md_number_to_chars (p
, val
, size
);
9838 /* Not absolute_section.
9839 Need a 32-bit fixup (don't support 8bit
9840 non-absolute imms). Try to support other
9842 enum bfd_reloc_code_real reloc_type
;
9845 if (i
.types
[n
].bitfield
.imm32s
9846 && (i
.suffix
== QWORD_MNEM_SUFFIX
9847 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9852 p
= frag_more (size
);
9853 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9855 /* This is tough to explain. We end up with this one if we
9856 * have operands that look like
9857 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9858 * obtain the absolute address of the GOT, and it is strongly
9859 * preferable from a performance point of view to avoid using
9860 * a runtime relocation for this. The actual sequence of
9861 * instructions often look something like:
9866 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9868 * The call and pop essentially return the absolute address
9869 * of the label .L66 and store it in %ebx. The linker itself
9870 * will ultimately change the first operand of the addl so
9871 * that %ebx points to the GOT, but to keep things simple, the
9872 * .o file must have this operand set so that it generates not
9873 * the absolute address of .L66, but the absolute address of
9874 * itself. This allows the linker itself simply treat a GOTPC
9875 * relocation as asking for a pcrel offset to the GOT to be
9876 * added in, and the addend of the relocation is stored in the
9877 * operand field for the instruction itself.
9879 * Our job here is to fix the operand so that it would add
9880 * the correct offset so that %ebx would point to itself. The
9881 * thing that is tricky is that .-.L66 will point to the
9882 * beginning of the instruction, so we need to further modify
9883 * the operand so that it will point to itself. There are
9884 * other cases where you have something like:
9886 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9888 * and here no correction would be required. Internally in
9889 * the assembler we treat operands of this form as not being
9890 * pcrel since the '.' is explicitly mentioned, and I wonder
9891 * whether it would simplify matters to do it this way. Who
9892 * knows. In earlier versions of the PIC patches, the
9893 * pcrel_adjust field was used to store the correction, but
9894 * since the expression is not pcrel, I felt it would be
9895 * confusing to do it this way. */
9897 if ((reloc_type
== BFD_RELOC_32
9898 || reloc_type
== BFD_RELOC_X86_64_32S
9899 || reloc_type
== BFD_RELOC_64
)
9901 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9902 && (i
.op
[n
].imms
->X_op
== O_symbol
9903 || (i
.op
[n
].imms
->X_op
== O_add
9904 && ((symbol_get_value_expression
9905 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9909 reloc_type
= BFD_RELOC_386_GOTPC
;
9911 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9913 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9914 i
.has_gotpc_tls_reloc
= TRUE
;
9915 i
.op
[n
].imms
->X_add_number
+=
9916 encoding_length (insn_start_frag
, insn_start_off
, p
);
9918 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9919 i
.op
[n
].imms
, 0, reloc_type
);
9925 /* x86_cons_fix_new is called via the expression parsing code when a
9926 reloc is needed. We use this hook to get the correct .got reloc. */
9927 static int cons_sign
= -1;
9930 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9931 expressionS
*exp
, bfd_reloc_code_real_type r
)
9933 r
= reloc (len
, 0, cons_sign
, r
);
9936 if (exp
->X_op
== O_secrel
)
9938 exp
->X_op
= O_symbol
;
9939 r
= BFD_RELOC_32_SECREL
;
9943 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9946 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9947 purpose of the `.dc.a' internal pseudo-op. */
9950 x86_address_bytes (void)
9952 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9954 return stdoutput
->arch_info
->bits_per_address
/ 8;
9957 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9959 # define lex_got(reloc, adjust, types) NULL
9961 /* Parse operands of the form
9962 <symbol>@GOTOFF+<nnn>
9963 and similar .plt or .got references.
9965 If we find one, set up the correct relocation in RELOC and copy the
9966 input string, minus the `@GOTOFF' into a malloc'd buffer for
9967 parsing by the calling routine. Return this buffer, and if ADJUST
9968 is non-null set it to the length of the string we removed from the
9969 input line. Otherwise return NULL. */
9971 lex_got (enum bfd_reloc_code_real
*rel
,
9973 i386_operand_type
*types
)
9975 /* Some of the relocations depend on the size of what field is to
9976 be relocated. But in our callers i386_immediate and i386_displacement
9977 we don't yet know the operand size (this will be set by insn
9978 matching). Hence we record the word32 relocation here,
9979 and adjust the reloc according to the real size in reloc(). */
9980 static const struct {
9983 const enum bfd_reloc_code_real rel
[2];
9984 const i386_operand_type types64
;
9986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9989 OPERAND_TYPE_IMM32_64
},
9991 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9992 BFD_RELOC_X86_64_PLTOFF64
},
9993 OPERAND_TYPE_IMM64
},
9994 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9995 BFD_RELOC_X86_64_PLT32
},
9996 OPERAND_TYPE_IMM32_32S_DISP32
},
9997 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9998 BFD_RELOC_X86_64_GOTPLT64
},
9999 OPERAND_TYPE_IMM64_DISP64
},
10000 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10001 BFD_RELOC_X86_64_GOTOFF64
},
10002 OPERAND_TYPE_IMM64_DISP64
},
10003 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10004 BFD_RELOC_X86_64_GOTPCREL
},
10005 OPERAND_TYPE_IMM32_32S_DISP32
},
10006 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10007 BFD_RELOC_X86_64_TLSGD
},
10008 OPERAND_TYPE_IMM32_32S_DISP32
},
10009 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10010 _dummy_first_bfd_reloc_code_real
},
10011 OPERAND_TYPE_NONE
},
10012 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10013 BFD_RELOC_X86_64_TLSLD
},
10014 OPERAND_TYPE_IMM32_32S_DISP32
},
10015 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10016 BFD_RELOC_X86_64_GOTTPOFF
},
10017 OPERAND_TYPE_IMM32_32S_DISP32
},
10018 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10019 BFD_RELOC_X86_64_TPOFF32
},
10020 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10021 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10022 _dummy_first_bfd_reloc_code_real
},
10023 OPERAND_TYPE_NONE
},
10024 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10025 BFD_RELOC_X86_64_DTPOFF32
},
10026 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10027 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10028 _dummy_first_bfd_reloc_code_real
},
10029 OPERAND_TYPE_NONE
},
10030 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10031 _dummy_first_bfd_reloc_code_real
},
10032 OPERAND_TYPE_NONE
},
10033 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10034 BFD_RELOC_X86_64_GOT32
},
10035 OPERAND_TYPE_IMM32_32S_64_DISP32
},
10036 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10037 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10038 OPERAND_TYPE_IMM32_32S_DISP32
},
10039 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10040 BFD_RELOC_X86_64_TLSDESC_CALL
},
10041 OPERAND_TYPE_IMM32_32S_DISP32
},
10046 #if defined (OBJ_MAYBE_ELF)
10051 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10052 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10055 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10057 int len
= gotrel
[j
].len
;
10058 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10060 if (gotrel
[j
].rel
[object_64bit
] != 0)
10063 char *tmpbuf
, *past_reloc
;
10065 *rel
= gotrel
[j
].rel
[object_64bit
];
10069 if (flag_code
!= CODE_64BIT
)
10071 types
->bitfield
.imm32
= 1;
10072 types
->bitfield
.disp32
= 1;
10075 *types
= gotrel
[j
].types64
;
10078 if (j
!= 0 && GOT_symbol
== NULL
)
10079 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10081 /* The length of the first part of our input line. */
10082 first
= cp
- input_line_pointer
;
10084 /* The second part goes from after the reloc token until
10085 (and including) an end_of_line char or comma. */
10086 past_reloc
= cp
+ 1 + len
;
10088 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10090 second
= cp
+ 1 - past_reloc
;
10092 /* Allocate and copy string. The trailing NUL shouldn't
10093 be necessary, but be safe. */
10094 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10095 memcpy (tmpbuf
, input_line_pointer
, first
);
10096 if (second
!= 0 && *past_reloc
!= ' ')
10097 /* Replace the relocation token with ' ', so that
10098 errors like foo@GOTOFF1 will be detected. */
10099 tmpbuf
[first
++] = ' ';
10101 /* Increment length by 1 if the relocation token is
10106 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10107 tmpbuf
[first
+ second
] = '\0';
10111 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10112 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10117 /* Might be a symbol version string. Don't as_bad here. */
10126 /* Parse operands of the form
10127 <symbol>@SECREL32+<nnn>
10129 If we find one, set up the correct relocation in RELOC and copy the
10130 input string, minus the `@SECREL32' into a malloc'd buffer for
10131 parsing by the calling routine. Return this buffer, and if ADJUST
10132 is non-null set it to the length of the string we removed from the
10133 input line. Otherwise return NULL.
10135 This function is copied from the ELF version above adjusted for PE targets. */
10138 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10139 int *adjust ATTRIBUTE_UNUSED
,
10140 i386_operand_type
*types
)
10142 static const struct
10146 const enum bfd_reloc_code_real rel
[2];
10147 const i386_operand_type types64
;
10151 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10152 BFD_RELOC_32_SECREL
},
10153 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10159 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10160 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10163 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10165 int len
= gotrel
[j
].len
;
10167 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10169 if (gotrel
[j
].rel
[object_64bit
] != 0)
10172 char *tmpbuf
, *past_reloc
;
10174 *rel
= gotrel
[j
].rel
[object_64bit
];
10180 if (flag_code
!= CODE_64BIT
)
10182 types
->bitfield
.imm32
= 1;
10183 types
->bitfield
.disp32
= 1;
10186 *types
= gotrel
[j
].types64
;
10189 /* The length of the first part of our input line. */
10190 first
= cp
- input_line_pointer
;
10192 /* The second part goes from after the reloc token until
10193 (and including) an end_of_line char or comma. */
10194 past_reloc
= cp
+ 1 + len
;
10196 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10198 second
= cp
+ 1 - past_reloc
;
10200 /* Allocate and copy string. The trailing NUL shouldn't
10201 be necessary, but be safe. */
10202 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10203 memcpy (tmpbuf
, input_line_pointer
, first
);
10204 if (second
!= 0 && *past_reloc
!= ' ')
10205 /* Replace the relocation token with ' ', so that
10206 errors like foo@SECLREL321 will be detected. */
10207 tmpbuf
[first
++] = ' ';
10208 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10209 tmpbuf
[first
+ second
] = '\0';
10213 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10214 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10219 /* Might be a symbol version string. Don't as_bad here. */
10225 bfd_reloc_code_real_type
10226 x86_cons (expressionS
*exp
, int size
)
10228 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10230 intel_syntax
= -intel_syntax
;
10233 if (size
== 4 || (object_64bit
&& size
== 8))
10235 /* Handle @GOTOFF and the like in an expression. */
10237 char *gotfree_input_line
;
10240 save
= input_line_pointer
;
10241 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10242 if (gotfree_input_line
)
10243 input_line_pointer
= gotfree_input_line
;
10247 if (gotfree_input_line
)
10249 /* expression () has merrily parsed up to the end of line,
10250 or a comma - in the wrong buffer. Transfer how far
10251 input_line_pointer has moved to the right buffer. */
10252 input_line_pointer
= (save
10253 + (input_line_pointer
- gotfree_input_line
)
10255 free (gotfree_input_line
);
10256 if (exp
->X_op
== O_constant
10257 || exp
->X_op
== O_absent
10258 || exp
->X_op
== O_illegal
10259 || exp
->X_op
== O_register
10260 || exp
->X_op
== O_big
)
10262 char c
= *input_line_pointer
;
10263 *input_line_pointer
= 0;
10264 as_bad (_("missing or invalid expression `%s'"), save
);
10265 *input_line_pointer
= c
;
10267 else if ((got_reloc
== BFD_RELOC_386_PLT32
10268 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10269 && exp
->X_op
!= O_symbol
)
10271 char c
= *input_line_pointer
;
10272 *input_line_pointer
= 0;
10273 as_bad (_("invalid PLT expression `%s'"), save
);
10274 *input_line_pointer
= c
;
10281 intel_syntax
= -intel_syntax
;
10284 i386_intel_simplify (exp
);
10290 signed_cons (int size
)
10292 if (flag_code
== CODE_64BIT
)
10300 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10307 if (exp
.X_op
== O_symbol
)
10308 exp
.X_op
= O_secrel
;
10310 emit_expr (&exp
, 4);
10312 while (*input_line_pointer
++ == ',');
10314 input_line_pointer
--;
10315 demand_empty_rest_of_line ();
10319 /* Handle Vector operations. */
10322 check_VecOperations (char *op_string
, char *op_end
)
10324 const reg_entry
*mask
;
10329 && (op_end
== NULL
|| op_string
< op_end
))
10332 if (*op_string
== '{')
10336 /* Check broadcasts. */
10337 if (strncmp (op_string
, "1to", 3) == 0)
10342 goto duplicated_vec_op
;
10345 if (*op_string
== '8')
10347 else if (*op_string
== '4')
10349 else if (*op_string
== '2')
10351 else if (*op_string
== '1'
10352 && *(op_string
+1) == '6')
10359 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10364 broadcast_op
.type
= bcst_type
;
10365 broadcast_op
.operand
= this_operand
;
10366 broadcast_op
.bytes
= 0;
10367 i
.broadcast
= &broadcast_op
;
10369 /* Check masking operation. */
10370 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10372 if (mask
== &bad_reg
)
10375 /* k0 can't be used for write mask. */
10376 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10378 as_bad (_("`%s%s' can't be used for write mask"),
10379 register_prefix
, mask
->reg_name
);
10385 mask_op
.mask
= mask
;
10386 mask_op
.zeroing
= 0;
10387 mask_op
.operand
= this_operand
;
10393 goto duplicated_vec_op
;
10395 i
.mask
->mask
= mask
;
10397 /* Only "{z}" is allowed here. No need to check
10398 zeroing mask explicitly. */
10399 if (i
.mask
->operand
!= this_operand
)
10401 as_bad (_("invalid write mask `%s'"), saved
);
10406 op_string
= end_op
;
10408 /* Check zeroing-flag for masking operation. */
10409 else if (*op_string
== 'z')
10413 mask_op
.mask
= NULL
;
10414 mask_op
.zeroing
= 1;
10415 mask_op
.operand
= this_operand
;
10420 if (i
.mask
->zeroing
)
10423 as_bad (_("duplicated `%s'"), saved
);
10427 i
.mask
->zeroing
= 1;
10429 /* Only "{%k}" is allowed here. No need to check mask
10430 register explicitly. */
10431 if (i
.mask
->operand
!= this_operand
)
10433 as_bad (_("invalid zeroing-masking `%s'"),
10442 goto unknown_vec_op
;
10444 if (*op_string
!= '}')
10446 as_bad (_("missing `}' in `%s'"), saved
);
10451 /* Strip whitespace since the addition of pseudo prefixes
10452 changed how the scrubber treats '{'. */
10453 if (is_space_char (*op_string
))
10459 /* We don't know this one. */
10460 as_bad (_("unknown vector operation: `%s'"), saved
);
10464 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10466 as_bad (_("zeroing-masking only allowed with write mask"));
10474 i386_immediate (char *imm_start
)
10476 char *save_input_line_pointer
;
10477 char *gotfree_input_line
;
10480 i386_operand_type types
;
10482 operand_type_set (&types
, ~0);
10484 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10486 as_bad (_("at most %d immediate operands are allowed"),
10487 MAX_IMMEDIATE_OPERANDS
);
10491 exp
= &im_expressions
[i
.imm_operands
++];
10492 i
.op
[this_operand
].imms
= exp
;
10494 if (is_space_char (*imm_start
))
10497 save_input_line_pointer
= input_line_pointer
;
10498 input_line_pointer
= imm_start
;
10500 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10501 if (gotfree_input_line
)
10502 input_line_pointer
= gotfree_input_line
;
10504 exp_seg
= expression (exp
);
10506 SKIP_WHITESPACE ();
10508 /* Handle vector operations. */
10509 if (*input_line_pointer
== '{')
10511 input_line_pointer
= check_VecOperations (input_line_pointer
,
10513 if (input_line_pointer
== NULL
)
10517 if (*input_line_pointer
)
10518 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10520 input_line_pointer
= save_input_line_pointer
;
10521 if (gotfree_input_line
)
10523 free (gotfree_input_line
);
10525 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10526 exp
->X_op
= O_illegal
;
10529 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10533 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10534 i386_operand_type types
, const char *imm_start
)
10536 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10539 as_bad (_("missing or invalid immediate expression `%s'"),
10543 else if (exp
->X_op
== O_constant
)
10545 /* Size it properly later. */
10546 i
.types
[this_operand
].bitfield
.imm64
= 1;
10547 /* If not 64bit, sign extend val. */
10548 if (flag_code
!= CODE_64BIT
10549 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10551 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10553 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10554 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10555 && exp_seg
!= absolute_section
10556 && exp_seg
!= text_section
10557 && exp_seg
!= data_section
10558 && exp_seg
!= bss_section
10559 && exp_seg
!= undefined_section
10560 && !bfd_is_com_section (exp_seg
))
10562 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10566 else if (!intel_syntax
&& exp_seg
== reg_section
)
10569 as_bad (_("illegal immediate register operand %s"), imm_start
);
10574 /* This is an address. The size of the address will be
10575 determined later, depending on destination register,
10576 suffix, or the default for the section. */
10577 i
.types
[this_operand
].bitfield
.imm8
= 1;
10578 i
.types
[this_operand
].bitfield
.imm16
= 1;
10579 i
.types
[this_operand
].bitfield
.imm32
= 1;
10580 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10581 i
.types
[this_operand
].bitfield
.imm64
= 1;
10582 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10590 i386_scale (char *scale
)
10593 char *save
= input_line_pointer
;
10595 input_line_pointer
= scale
;
10596 val
= get_absolute_expression ();
10601 i
.log2_scale_factor
= 0;
10604 i
.log2_scale_factor
= 1;
10607 i
.log2_scale_factor
= 2;
10610 i
.log2_scale_factor
= 3;
10614 char sep
= *input_line_pointer
;
10616 *input_line_pointer
= '\0';
10617 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10619 *input_line_pointer
= sep
;
10620 input_line_pointer
= save
;
10624 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10626 as_warn (_("scale factor of %d without an index register"),
10627 1 << i
.log2_scale_factor
);
10628 i
.log2_scale_factor
= 0;
10630 scale
= input_line_pointer
;
10631 input_line_pointer
= save
;
10636 i386_displacement (char *disp_start
, char *disp_end
)
10640 char *save_input_line_pointer
;
10641 char *gotfree_input_line
;
10643 i386_operand_type bigdisp
, types
= anydisp
;
10646 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10648 as_bad (_("at most %d displacement operands are allowed"),
10649 MAX_MEMORY_OPERANDS
);
10653 operand_type_set (&bigdisp
, 0);
10655 || i
.types
[this_operand
].bitfield
.baseindex
10656 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10657 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10659 i386_addressing_mode ();
10660 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10661 if (flag_code
== CODE_64BIT
)
10665 bigdisp
.bitfield
.disp32s
= 1;
10666 bigdisp
.bitfield
.disp64
= 1;
10669 bigdisp
.bitfield
.disp32
= 1;
10671 else if ((flag_code
== CODE_16BIT
) ^ override
)
10672 bigdisp
.bitfield
.disp16
= 1;
10674 bigdisp
.bitfield
.disp32
= 1;
10678 /* For PC-relative branches, the width of the displacement may be
10679 dependent upon data size, but is never dependent upon address size.
10680 Also make sure to not unintentionally match against a non-PC-relative
10681 branch template. */
10682 static templates aux_templates
;
10683 const insn_template
*t
= current_templates
->start
;
10684 bfd_boolean has_intel64
= FALSE
;
10686 aux_templates
.start
= t
;
10687 while (++t
< current_templates
->end
)
10689 if (t
->opcode_modifier
.jump
10690 != current_templates
->start
->opcode_modifier
.jump
)
10692 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10693 has_intel64
= TRUE
;
10695 if (t
< current_templates
->end
)
10697 aux_templates
.end
= t
;
10698 current_templates
= &aux_templates
;
10701 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10702 if (flag_code
== CODE_64BIT
)
10704 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10705 && (!intel64
|| !has_intel64
))
10706 bigdisp
.bitfield
.disp16
= 1;
10708 bigdisp
.bitfield
.disp32s
= 1;
10713 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10715 : LONG_MNEM_SUFFIX
));
10716 bigdisp
.bitfield
.disp32
= 1;
10717 if ((flag_code
== CODE_16BIT
) ^ override
)
10719 bigdisp
.bitfield
.disp32
= 0;
10720 bigdisp
.bitfield
.disp16
= 1;
10724 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10727 exp
= &disp_expressions
[i
.disp_operands
];
10728 i
.op
[this_operand
].disps
= exp
;
10730 save_input_line_pointer
= input_line_pointer
;
10731 input_line_pointer
= disp_start
;
10732 END_STRING_AND_SAVE (disp_end
);
10734 #ifndef GCC_ASM_O_HACK
10735 #define GCC_ASM_O_HACK 0
10738 END_STRING_AND_SAVE (disp_end
+ 1);
10739 if (i
.types
[this_operand
].bitfield
.baseIndex
10740 && displacement_string_end
[-1] == '+')
10742 /* This hack is to avoid a warning when using the "o"
10743 constraint within gcc asm statements.
10746 #define _set_tssldt_desc(n,addr,limit,type) \
10747 __asm__ __volatile__ ( \
10748 "movw %w2,%0\n\t" \
10749 "movw %w1,2+%0\n\t" \
10750 "rorl $16,%1\n\t" \
10751 "movb %b1,4+%0\n\t" \
10752 "movb %4,5+%0\n\t" \
10753 "movb $0,6+%0\n\t" \
10754 "movb %h1,7+%0\n\t" \
10756 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10758 This works great except that the output assembler ends
10759 up looking a bit weird if it turns out that there is
10760 no offset. You end up producing code that looks like:
10773 So here we provide the missing zero. */
10775 *displacement_string_end
= '0';
10778 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10779 if (gotfree_input_line
)
10780 input_line_pointer
= gotfree_input_line
;
10782 exp_seg
= expression (exp
);
10784 SKIP_WHITESPACE ();
10785 if (*input_line_pointer
)
10786 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10788 RESTORE_END_STRING (disp_end
+ 1);
10790 input_line_pointer
= save_input_line_pointer
;
10791 if (gotfree_input_line
)
10793 free (gotfree_input_line
);
10795 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10796 exp
->X_op
= O_illegal
;
10799 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10801 RESTORE_END_STRING (disp_end
);
10807 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10808 i386_operand_type types
, const char *disp_start
)
10810 i386_operand_type bigdisp
;
10813 /* We do this to make sure that the section symbol is in
10814 the symbol table. We will ultimately change the relocation
10815 to be relative to the beginning of the section. */
10816 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10817 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10818 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10820 if (exp
->X_op
!= O_symbol
)
10823 if (S_IS_LOCAL (exp
->X_add_symbol
)
10824 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10825 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10826 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10827 exp
->X_op
= O_subtract
;
10828 exp
->X_op_symbol
= GOT_symbol
;
10829 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10830 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10831 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10832 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10834 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10837 else if (exp
->X_op
== O_absent
10838 || exp
->X_op
== O_illegal
10839 || exp
->X_op
== O_big
)
10842 as_bad (_("missing or invalid displacement expression `%s'"),
10847 else if (flag_code
== CODE_64BIT
10848 && !i
.prefix
[ADDR_PREFIX
]
10849 && exp
->X_op
== O_constant
)
10851 /* Since displacement is signed extended to 64bit, don't allow
10852 disp32 and turn off disp32s if they are out of range. */
10853 i
.types
[this_operand
].bitfield
.disp32
= 0;
10854 if (!fits_in_signed_long (exp
->X_add_number
))
10856 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10857 if (i
.types
[this_operand
].bitfield
.baseindex
)
10859 as_bad (_("0x%lx out range of signed 32bit displacement"),
10860 (long) exp
->X_add_number
);
10866 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10867 else if (exp
->X_op
!= O_constant
10868 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10869 && exp_seg
!= absolute_section
10870 && exp_seg
!= text_section
10871 && exp_seg
!= data_section
10872 && exp_seg
!= bss_section
10873 && exp_seg
!= undefined_section
10874 && !bfd_is_com_section (exp_seg
))
10876 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10881 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10882 /* Constants get taken care of by optimize_disp(). */
10883 && exp
->X_op
!= O_constant
)
10884 i
.types
[this_operand
].bitfield
.disp8
= 1;
10886 /* Check if this is a displacement only operand. */
10887 bigdisp
= i
.types
[this_operand
];
10888 bigdisp
.bitfield
.disp8
= 0;
10889 bigdisp
.bitfield
.disp16
= 0;
10890 bigdisp
.bitfield
.disp32
= 0;
10891 bigdisp
.bitfield
.disp32s
= 0;
10892 bigdisp
.bitfield
.disp64
= 0;
10893 if (operand_type_all_zero (&bigdisp
))
10894 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10900 /* Return the active addressing mode, taking address override and
10901 registers forming the address into consideration. Update the
10902 address override prefix if necessary. */
10904 static enum flag_code
10905 i386_addressing_mode (void)
10907 enum flag_code addr_mode
;
10909 if (i
.prefix
[ADDR_PREFIX
])
10910 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10911 else if (flag_code
== CODE_16BIT
10912 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10913 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10914 from md_assemble() by "is not a valid base/index expression"
10915 when there is a base and/or index. */
10916 && !i
.types
[this_operand
].bitfield
.baseindex
)
10918 /* MPX insn memory operands with neither base nor index must be forced
10919 to use 32-bit addressing in 16-bit mode. */
10920 addr_mode
= CODE_32BIT
;
10921 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10923 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10924 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10928 addr_mode
= flag_code
;
10930 #if INFER_ADDR_PREFIX
10931 if (i
.mem_operands
== 0)
10933 /* Infer address prefix from the first memory operand. */
10934 const reg_entry
*addr_reg
= i
.base_reg
;
10936 if (addr_reg
== NULL
)
10937 addr_reg
= i
.index_reg
;
10941 if (addr_reg
->reg_type
.bitfield
.dword
)
10942 addr_mode
= CODE_32BIT
;
10943 else if (flag_code
!= CODE_64BIT
10944 && addr_reg
->reg_type
.bitfield
.word
)
10945 addr_mode
= CODE_16BIT
;
10947 if (addr_mode
!= flag_code
)
10949 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10951 /* Change the size of any displacement too. At most one
10952 of Disp16 or Disp32 is set.
10953 FIXME. There doesn't seem to be any real need for
10954 separate Disp16 and Disp32 flags. The same goes for
10955 Imm16 and Imm32. Removing them would probably clean
10956 up the code quite a lot. */
10957 if (flag_code
!= CODE_64BIT
10958 && (i
.types
[this_operand
].bitfield
.disp16
10959 || i
.types
[this_operand
].bitfield
.disp32
))
10960 i
.types
[this_operand
]
10961 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10971 /* Make sure the memory operand we've been dealt is valid.
10972 Return 1 on success, 0 on a failure. */
10975 i386_index_check (const char *operand_string
)
10977 const char *kind
= "base/index";
10978 enum flag_code addr_mode
= i386_addressing_mode ();
10980 if (current_templates
->start
->opcode_modifier
.isstring
10981 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10982 && (current_templates
->end
[-1].opcode_modifier
.isstring
10983 || i
.mem_operands
))
10985 /* Memory operands of string insns are special in that they only allow
10986 a single register (rDI, rSI, or rBX) as their memory address. */
10987 const reg_entry
*expected_reg
;
10988 static const char *di_si
[][2] =
10994 static const char *bx
[] = { "ebx", "bx", "rbx" };
10996 kind
= "string address";
10998 if (current_templates
->start
->opcode_modifier
.repprefixok
)
11000 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11001 - IS_STRING_ES_OP0
;
11004 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11005 || ((!i
.mem_operands
!= !intel_syntax
)
11006 && current_templates
->end
[-1].operand_types
[1]
11007 .bitfield
.baseindex
))
11010 = (const reg_entry
*) str_hash_find (reg_hash
,
11011 di_si
[addr_mode
][op
== es_op
]);
11015 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11017 if (i
.base_reg
!= expected_reg
11019 || operand_type_check (i
.types
[this_operand
], disp
))
11021 /* The second memory operand must have the same size as
11025 && !((addr_mode
== CODE_64BIT
11026 && i
.base_reg
->reg_type
.bitfield
.qword
)
11027 || (addr_mode
== CODE_32BIT
11028 ? i
.base_reg
->reg_type
.bitfield
.dword
11029 : i
.base_reg
->reg_type
.bitfield
.word
)))
11032 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11034 intel_syntax
? '[' : '(',
11036 expected_reg
->reg_name
,
11037 intel_syntax
? ']' : ')');
11044 as_bad (_("`%s' is not a valid %s expression"),
11045 operand_string
, kind
);
11050 if (addr_mode
!= CODE_16BIT
)
11052 /* 32-bit/64-bit checks. */
11053 if (i
.disp_encoding
== disp_encoding_16bit
)
11056 as_bad (_("invalid `%s' prefix"),
11057 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11062 && ((addr_mode
== CODE_64BIT
11063 ? !i
.base_reg
->reg_type
.bitfield
.qword
11064 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11065 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11066 || i
.base_reg
->reg_num
== RegIZ
))
11068 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11069 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11070 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11071 && ((addr_mode
== CODE_64BIT
11072 ? !i
.index_reg
->reg_type
.bitfield
.qword
11073 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11074 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11077 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11078 if (current_templates
->start
->base_opcode
== 0xf30f1b
11079 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11080 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11082 /* They cannot use RIP-relative addressing. */
11083 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11085 as_bad (_("`%s' cannot be used here"), operand_string
);
11089 /* bndldx and bndstx ignore their scale factor. */
11090 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11091 && i
.log2_scale_factor
)
11092 as_warn (_("register scaling is being ignored here"));
11097 /* 16-bit checks. */
11098 if (i
.disp_encoding
== disp_encoding_32bit
)
11102 && (!i
.base_reg
->reg_type
.bitfield
.word
11103 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11105 && (!i
.index_reg
->reg_type
.bitfield
.word
11106 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11108 && i
.base_reg
->reg_num
< 6
11109 && i
.index_reg
->reg_num
>= 6
11110 && i
.log2_scale_factor
== 0))))
11117 /* Handle vector immediates. */
11120 RC_SAE_immediate (const char *imm_start
)
11122 unsigned int match_found
, j
;
11123 const char *pstr
= imm_start
;
11131 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11133 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11137 rc_op
.type
= RC_NamesTable
[j
].type
;
11138 rc_op
.operand
= this_operand
;
11139 i
.rounding
= &rc_op
;
11143 as_bad (_("duplicated `%s'"), imm_start
);
11146 pstr
+= RC_NamesTable
[j
].len
;
11154 if (*pstr
++ != '}')
11156 as_bad (_("Missing '}': '%s'"), imm_start
);
11159 /* RC/SAE immediate string should contain nothing more. */;
11162 as_bad (_("Junk after '}': '%s'"), imm_start
);
11166 exp
= &im_expressions
[i
.imm_operands
++];
11167 i
.op
[this_operand
].imms
= exp
;
11169 exp
->X_op
= O_constant
;
11170 exp
->X_add_number
= 0;
11171 exp
->X_add_symbol
= (symbolS
*) 0;
11172 exp
->X_op_symbol
= (symbolS
*) 0;
11174 i
.types
[this_operand
].bitfield
.imm8
= 1;
11178 /* Only string instructions can have a second memory operand, so
11179 reduce current_templates to just those if it contains any. */
11181 maybe_adjust_templates (void)
11183 const insn_template
*t
;
11185 gas_assert (i
.mem_operands
== 1);
11187 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11188 if (t
->opcode_modifier
.isstring
)
11191 if (t
< current_templates
->end
)
11193 static templates aux_templates
;
11194 bfd_boolean recheck
;
11196 aux_templates
.start
= t
;
11197 for (; t
< current_templates
->end
; ++t
)
11198 if (!t
->opcode_modifier
.isstring
)
11200 aux_templates
.end
= t
;
11202 /* Determine whether to re-check the first memory operand. */
11203 recheck
= (aux_templates
.start
!= current_templates
->start
11204 || t
!= current_templates
->end
);
11206 current_templates
= &aux_templates
;
11210 i
.mem_operands
= 0;
11211 if (i
.memop1_string
!= NULL
11212 && i386_index_check (i
.memop1_string
) == 0)
11214 i
.mem_operands
= 1;
11221 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11225 i386_att_operand (char *operand_string
)
11227 const reg_entry
*r
;
11229 char *op_string
= operand_string
;
11231 if (is_space_char (*op_string
))
11234 /* We check for an absolute prefix (differentiating,
11235 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11236 if (*op_string
== ABSOLUTE_PREFIX
)
11239 if (is_space_char (*op_string
))
11241 i
.jumpabsolute
= TRUE
;
11244 /* Check if operand is a register. */
11245 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11247 i386_operand_type temp
;
11252 /* Check for a segment override by searching for ':' after a
11253 segment register. */
11254 op_string
= end_op
;
11255 if (is_space_char (*op_string
))
11257 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11259 switch (r
->reg_num
)
11262 i
.seg
[i
.mem_operands
] = &es
;
11265 i
.seg
[i
.mem_operands
] = &cs
;
11268 i
.seg
[i
.mem_operands
] = &ss
;
11271 i
.seg
[i
.mem_operands
] = &ds
;
11274 i
.seg
[i
.mem_operands
] = &fs
;
11277 i
.seg
[i
.mem_operands
] = &gs
;
11281 /* Skip the ':' and whitespace. */
11283 if (is_space_char (*op_string
))
11286 if (!is_digit_char (*op_string
)
11287 && !is_identifier_char (*op_string
)
11288 && *op_string
!= '('
11289 && *op_string
!= ABSOLUTE_PREFIX
)
11291 as_bad (_("bad memory operand `%s'"), op_string
);
11294 /* Handle case of %es:*foo. */
11295 if (*op_string
== ABSOLUTE_PREFIX
)
11298 if (is_space_char (*op_string
))
11300 i
.jumpabsolute
= TRUE
;
11302 goto do_memory_reference
;
11305 /* Handle vector operations. */
11306 if (*op_string
== '{')
11308 op_string
= check_VecOperations (op_string
, NULL
);
11309 if (op_string
== NULL
)
11315 as_bad (_("junk `%s' after register"), op_string
);
11318 temp
= r
->reg_type
;
11319 temp
.bitfield
.baseindex
= 0;
11320 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11322 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11323 i
.op
[this_operand
].regs
= r
;
11326 else if (*op_string
== REGISTER_PREFIX
)
11328 as_bad (_("bad register name `%s'"), op_string
);
11331 else if (*op_string
== IMMEDIATE_PREFIX
)
11334 if (i
.jumpabsolute
)
11336 as_bad (_("immediate operand illegal with absolute jump"));
11339 if (!i386_immediate (op_string
))
11342 else if (RC_SAE_immediate (operand_string
))
11344 /* If it is a RC or SAE immediate, do nothing. */
11347 else if (is_digit_char (*op_string
)
11348 || is_identifier_char (*op_string
)
11349 || *op_string
== '"'
11350 || *op_string
== '(')
11352 /* This is a memory reference of some sort. */
11355 /* Start and end of displacement string expression (if found). */
11356 char *displacement_string_start
;
11357 char *displacement_string_end
;
11360 do_memory_reference
:
11361 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11363 if ((i
.mem_operands
== 1
11364 && !current_templates
->start
->opcode_modifier
.isstring
)
11365 || i
.mem_operands
== 2)
11367 as_bad (_("too many memory references for `%s'"),
11368 current_templates
->start
->name
);
11372 /* Check for base index form. We detect the base index form by
11373 looking for an ')' at the end of the operand, searching
11374 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11376 base_string
= op_string
+ strlen (op_string
);
11378 /* Handle vector operations. */
11379 vop_start
= strchr (op_string
, '{');
11380 if (vop_start
&& vop_start
< base_string
)
11382 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11384 base_string
= vop_start
;
11388 if (is_space_char (*base_string
))
11391 /* If we only have a displacement, set-up for it to be parsed later. */
11392 displacement_string_start
= op_string
;
11393 displacement_string_end
= base_string
+ 1;
11395 if (*base_string
== ')')
11398 unsigned int parens_balanced
= 1;
11399 /* We've already checked that the number of left & right ()'s are
11400 equal, so this loop will not be infinite. */
11404 if (*base_string
== ')')
11406 if (*base_string
== '(')
11409 while (parens_balanced
);
11411 temp_string
= base_string
;
11413 /* Skip past '(' and whitespace. */
11415 if (is_space_char (*base_string
))
11418 if (*base_string
== ','
11419 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11422 displacement_string_end
= temp_string
;
11424 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11428 if (i
.base_reg
== &bad_reg
)
11430 base_string
= end_op
;
11431 if (is_space_char (*base_string
))
11435 /* There may be an index reg or scale factor here. */
11436 if (*base_string
== ',')
11439 if (is_space_char (*base_string
))
11442 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11445 if (i
.index_reg
== &bad_reg
)
11447 base_string
= end_op
;
11448 if (is_space_char (*base_string
))
11450 if (*base_string
== ',')
11453 if (is_space_char (*base_string
))
11456 else if (*base_string
!= ')')
11458 as_bad (_("expecting `,' or `)' "
11459 "after index register in `%s'"),
11464 else if (*base_string
== REGISTER_PREFIX
)
11466 end_op
= strchr (base_string
, ',');
11469 as_bad (_("bad register name `%s'"), base_string
);
11473 /* Check for scale factor. */
11474 if (*base_string
!= ')')
11476 char *end_scale
= i386_scale (base_string
);
11481 base_string
= end_scale
;
11482 if (is_space_char (*base_string
))
11484 if (*base_string
!= ')')
11486 as_bad (_("expecting `)' "
11487 "after scale factor in `%s'"),
11492 else if (!i
.index_reg
)
11494 as_bad (_("expecting index register or scale factor "
11495 "after `,'; got '%c'"),
11500 else if (*base_string
!= ')')
11502 as_bad (_("expecting `,' or `)' "
11503 "after base register in `%s'"),
11508 else if (*base_string
== REGISTER_PREFIX
)
11510 end_op
= strchr (base_string
, ',');
11513 as_bad (_("bad register name `%s'"), base_string
);
11518 /* If there's an expression beginning the operand, parse it,
11519 assuming displacement_string_start and
11520 displacement_string_end are meaningful. */
11521 if (displacement_string_start
!= displacement_string_end
)
11523 if (!i386_displacement (displacement_string_start
,
11524 displacement_string_end
))
11528 /* Special case for (%dx) while doing input/output op. */
11530 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11531 && i
.base_reg
->reg_type
.bitfield
.word
11532 && i
.index_reg
== 0
11533 && i
.log2_scale_factor
== 0
11534 && i
.seg
[i
.mem_operands
] == 0
11535 && !operand_type_check (i
.types
[this_operand
], disp
))
11537 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11541 if (i386_index_check (operand_string
) == 0)
11543 i
.flags
[this_operand
] |= Operand_Mem
;
11544 if (i
.mem_operands
== 0)
11545 i
.memop1_string
= xstrdup (operand_string
);
11550 /* It's not a memory operand; argh! */
11551 as_bad (_("invalid char %s beginning operand %d `%s'"),
11552 output_invalid (*op_string
),
11557 return 1; /* Normal return. */
11560 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11561 that an rs_machine_dependent frag may reach. */
11564 i386_frag_max_var (fragS
*frag
)
11566 /* The only relaxable frags are for jumps.
11567 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11568 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11569 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11574 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11576 /* STT_GNU_IFUNC symbol must go through PLT. */
11577 if ((symbol_get_bfdsym (fr_symbol
)->flags
11578 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11581 if (!S_IS_EXTERNAL (fr_symbol
))
11582 /* Symbol may be weak or local. */
11583 return !S_IS_WEAK (fr_symbol
);
11585 /* Global symbols with non-default visibility can't be preempted. */
11586 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11589 if (fr_var
!= NO_RELOC
)
11590 switch ((enum bfd_reloc_code_real
) fr_var
)
11592 case BFD_RELOC_386_PLT32
:
11593 case BFD_RELOC_X86_64_PLT32
:
11594 /* Symbol with PLT relocation may be preempted. */
11600 /* Global symbols with default visibility in a shared library may be
11601 preempted by another definition. */
11606 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11607 Note also work for Skylake and Cascadelake.
11608 ---------------------------------------------------------------------
11609 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11610 | ------ | ----------- | ------- | -------- |
11612 | Jno | N | N | Y |
11613 | Jc/Jb | Y | N | Y |
11614 | Jae/Jnb | Y | N | Y |
11615 | Je/Jz | Y | Y | Y |
11616 | Jne/Jnz | Y | Y | Y |
11617 | Jna/Jbe | Y | N | Y |
11618 | Ja/Jnbe | Y | N | Y |
11620 | Jns | N | N | Y |
11621 | Jp/Jpe | N | N | Y |
11622 | Jnp/Jpo | N | N | Y |
11623 | Jl/Jnge | Y | Y | Y |
11624 | Jge/Jnl | Y | Y | Y |
11625 | Jle/Jng | Y | Y | Y |
11626 | Jg/Jnle | Y | Y | Y |
11627 --------------------------------------------------------------------- */
11629 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11631 if (mf_cmp
== mf_cmp_alu_cmp
)
11632 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11633 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11634 if (mf_cmp
== mf_cmp_incdec
)
11635 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11636 || mf_jcc
== mf_jcc_jle
);
11637 if (mf_cmp
== mf_cmp_test_and
)
11642 /* Return the next non-empty frag. */
11645 i386_next_non_empty_frag (fragS
*fragP
)
11647 /* There may be a frag with a ".fill 0" when there is no room in
11648 the current frag for frag_grow in output_insn. */
11649 for (fragP
= fragP
->fr_next
;
11651 && fragP
->fr_type
== rs_fill
11652 && fragP
->fr_fix
== 0);
11653 fragP
= fragP
->fr_next
)
11658 /* Return the next jcc frag after BRANCH_PADDING. */
11661 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11663 fragS
*branch_fragP
;
11667 if (pad_fragP
->fr_type
== rs_machine_dependent
11668 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11669 == BRANCH_PADDING
))
11671 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11672 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11674 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11675 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11676 pad_fragP
->tc_frag_data
.mf_type
))
11677 return branch_fragP
;
11683 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11686 i386_classify_machine_dependent_frag (fragS
*fragP
)
11690 fragS
*branch_fragP
;
11692 unsigned int max_prefix_length
;
11694 if (fragP
->tc_frag_data
.classified
)
11697 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11698 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11699 for (next_fragP
= fragP
;
11700 next_fragP
!= NULL
;
11701 next_fragP
= next_fragP
->fr_next
)
11703 next_fragP
->tc_frag_data
.classified
= 1;
11704 if (next_fragP
->fr_type
== rs_machine_dependent
)
11705 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11707 case BRANCH_PADDING
:
11708 /* The BRANCH_PADDING frag must be followed by a branch
11710 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11711 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11713 case FUSED_JCC_PADDING
:
11714 /* Check if this is a fused jcc:
11716 CMP like instruction
11720 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11721 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11722 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11725 /* The BRANCH_PADDING frag is merged with the
11726 FUSED_JCC_PADDING frag. */
11727 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11728 /* CMP like instruction size. */
11729 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11730 frag_wane (pad_fragP
);
11731 /* Skip to branch_fragP. */
11732 next_fragP
= branch_fragP
;
11734 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11736 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11738 next_fragP
->fr_subtype
11739 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11740 next_fragP
->tc_frag_data
.max_bytes
11741 = next_fragP
->tc_frag_data
.max_prefix_length
;
11742 /* This will be updated in the BRANCH_PREFIX scan. */
11743 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11746 frag_wane (next_fragP
);
11751 /* Stop if there is no BRANCH_PREFIX. */
11752 if (!align_branch_prefix_size
)
11755 /* Scan for BRANCH_PREFIX. */
11756 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11758 if (fragP
->fr_type
!= rs_machine_dependent
11759 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11763 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11764 COND_JUMP_PREFIX. */
11765 max_prefix_length
= 0;
11766 for (next_fragP
= fragP
;
11767 next_fragP
!= NULL
;
11768 next_fragP
= next_fragP
->fr_next
)
11770 if (next_fragP
->fr_type
== rs_fill
)
11771 /* Skip rs_fill frags. */
11773 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11774 /* Stop for all other frags. */
11777 /* rs_machine_dependent frags. */
11778 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11781 /* Count BRANCH_PREFIX frags. */
11782 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11784 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11785 frag_wane (next_fragP
);
11789 += next_fragP
->tc_frag_data
.max_bytes
;
11791 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11793 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11794 == FUSED_JCC_PADDING
))
11796 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11797 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11801 /* Stop for other rs_machine_dependent frags. */
11805 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11807 /* Skip to the next frag. */
11808 fragP
= next_fragP
;
11812 /* Compute padding size for
11815 CMP like instruction
11817 COND_JUMP/UNCOND_JUMP
11822 COND_JUMP/UNCOND_JUMP
11826 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11828 unsigned int offset
, size
, padding_size
;
11829 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11831 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11833 address
= fragP
->fr_address
;
11834 address
+= fragP
->fr_fix
;
11836 /* CMP like instrunction size. */
11837 size
= fragP
->tc_frag_data
.cmp_size
;
11839 /* The base size of the branch frag. */
11840 size
+= branch_fragP
->fr_fix
;
11842 /* Add opcode and displacement bytes for the rs_machine_dependent
11844 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11845 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11847 /* Check if branch is within boundary and doesn't end at the last
11849 offset
= address
& ((1U << align_branch_power
) - 1);
11850 if ((offset
+ size
) >= (1U << align_branch_power
))
11851 /* Padding needed to avoid crossing boundary. */
11852 padding_size
= (1U << align_branch_power
) - offset
;
11854 /* No padding needed. */
11857 /* The return value may be saved in tc_frag_data.length which is
11859 if (!fits_in_unsigned_byte (padding_size
))
11862 return padding_size
;
11865 /* i386_generic_table_relax_frag()
11867 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11868 grow/shrink padding to align branch frags. Hand others to
11872 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11874 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11875 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11877 long padding_size
= i386_branch_padding_size (fragP
, 0);
11878 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11880 /* When the BRANCH_PREFIX frag is used, the computed address
11881 must match the actual address and there should be no padding. */
11882 if (fragP
->tc_frag_data
.padding_address
11883 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11887 /* Update the padding size. */
11889 fragP
->tc_frag_data
.length
= padding_size
;
11893 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11895 fragS
*padding_fragP
, *next_fragP
;
11896 long padding_size
, left_size
, last_size
;
11898 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11899 if (!padding_fragP
)
11900 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11901 return (fragP
->tc_frag_data
.length
11902 - fragP
->tc_frag_data
.last_length
);
11904 /* Compute the relative address of the padding frag in the very
11905 first time where the BRANCH_PREFIX frag sizes are zero. */
11906 if (!fragP
->tc_frag_data
.padding_address
)
11907 fragP
->tc_frag_data
.padding_address
11908 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11910 /* First update the last length from the previous interation. */
11911 left_size
= fragP
->tc_frag_data
.prefix_length
;
11912 for (next_fragP
= fragP
;
11913 next_fragP
!= padding_fragP
;
11914 next_fragP
= next_fragP
->fr_next
)
11915 if (next_fragP
->fr_type
== rs_machine_dependent
11916 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11921 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11925 if (max
> left_size
)
11930 next_fragP
->tc_frag_data
.last_length
= size
;
11934 next_fragP
->tc_frag_data
.last_length
= 0;
11937 /* Check the padding size for the padding frag. */
11938 padding_size
= i386_branch_padding_size
11939 (padding_fragP
, (fragP
->fr_address
11940 + fragP
->tc_frag_data
.padding_address
));
11942 last_size
= fragP
->tc_frag_data
.prefix_length
;
11943 /* Check if there is change from the last interation. */
11944 if (padding_size
== last_size
)
11946 /* Update the expected address of the padding frag. */
11947 padding_fragP
->tc_frag_data
.padding_address
11948 = (fragP
->fr_address
+ padding_size
11949 + fragP
->tc_frag_data
.padding_address
);
11953 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11955 /* No padding if there is no sufficient room. Clear the
11956 expected address of the padding frag. */
11957 padding_fragP
->tc_frag_data
.padding_address
= 0;
11961 /* Store the expected address of the padding frag. */
11962 padding_fragP
->tc_frag_data
.padding_address
11963 = (fragP
->fr_address
+ padding_size
11964 + fragP
->tc_frag_data
.padding_address
);
11966 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11968 /* Update the length for the current interation. */
11969 left_size
= padding_size
;
11970 for (next_fragP
= fragP
;
11971 next_fragP
!= padding_fragP
;
11972 next_fragP
= next_fragP
->fr_next
)
11973 if (next_fragP
->fr_type
== rs_machine_dependent
11974 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11979 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11983 if (max
> left_size
)
11988 next_fragP
->tc_frag_data
.length
= size
;
11992 next_fragP
->tc_frag_data
.length
= 0;
11995 return (fragP
->tc_frag_data
.length
11996 - fragP
->tc_frag_data
.last_length
);
11998 return relax_frag (segment
, fragP
, stretch
);
12001 /* md_estimate_size_before_relax()
12003 Called just before relax() for rs_machine_dependent frags. The x86
12004 assembler uses these frags to handle variable size jump
12007 Any symbol that is now undefined will not become defined.
12008 Return the correct fr_subtype in the frag.
12009 Return the initial "guess for variable size of frag" to caller.
12010 The guess is actually the growth beyond the fixed part. Whatever
12011 we do to grow the fixed or variable part contributes to our
12015 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12017 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12018 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12019 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12021 i386_classify_machine_dependent_frag (fragP
);
12022 return fragP
->tc_frag_data
.length
;
12025 /* We've already got fragP->fr_subtype right; all we have to do is
12026 check for un-relaxable symbols. On an ELF system, we can't relax
12027 an externally visible symbol, because it may be overridden by a
12029 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12032 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12035 #if defined (OBJ_COFF) && defined (TE_PE)
12036 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12037 && S_IS_WEAK (fragP
->fr_symbol
))
12041 /* Symbol is undefined in this segment, or we need to keep a
12042 reloc so that weak symbols can be overridden. */
12043 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12044 enum bfd_reloc_code_real reloc_type
;
12045 unsigned char *opcode
;
12048 if (fragP
->fr_var
!= NO_RELOC
)
12049 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12050 else if (size
== 2)
12051 reloc_type
= BFD_RELOC_16_PCREL
;
12052 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12053 else if (need_plt32_p (fragP
->fr_symbol
))
12054 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12057 reloc_type
= BFD_RELOC_32_PCREL
;
12059 old_fr_fix
= fragP
->fr_fix
;
12060 opcode
= (unsigned char *) fragP
->fr_opcode
;
12062 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12065 /* Make jmp (0xeb) a (d)word displacement jump. */
12067 fragP
->fr_fix
+= size
;
12068 fix_new (fragP
, old_fr_fix
, size
,
12070 fragP
->fr_offset
, 1,
12076 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12078 /* Negate the condition, and branch past an
12079 unconditional jump. */
12082 /* Insert an unconditional jump. */
12084 /* We added two extra opcode bytes, and have a two byte
12086 fragP
->fr_fix
+= 2 + 2;
12087 fix_new (fragP
, old_fr_fix
+ 2, 2,
12089 fragP
->fr_offset
, 1,
12093 /* Fall through. */
12096 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12100 fragP
->fr_fix
+= 1;
12101 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12103 fragP
->fr_offset
, 1,
12104 BFD_RELOC_8_PCREL
);
12105 fixP
->fx_signed
= 1;
12109 /* This changes the byte-displacement jump 0x7N
12110 to the (d)word-displacement jump 0x0f,0x8N. */
12111 opcode
[1] = opcode
[0] + 0x10;
12112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12113 /* We've added an opcode byte. */
12114 fragP
->fr_fix
+= 1 + size
;
12115 fix_new (fragP
, old_fr_fix
+ 1, size
,
12117 fragP
->fr_offset
, 1,
12122 BAD_CASE (fragP
->fr_subtype
);
12126 return fragP
->fr_fix
- old_fr_fix
;
12129 /* Guess size depending on current relax state. Initially the relax
12130 state will correspond to a short jump and we return 1, because
12131 the variable part of the frag (the branch offset) is one byte
12132 long. However, we can relax a section more than once and in that
12133 case we must either set fr_subtype back to the unrelaxed state,
12134 or return the value for the appropriate branch. */
12135 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12138 /* Called after relax() is finished.
12140 In: Address of frag.
12141 fr_type == rs_machine_dependent.
12142 fr_subtype is what the address relaxed to.
12144 Out: Any fixSs and constants are set up.
12145 Caller will turn frag into a ".space 0". */
12148 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12151 unsigned char *opcode
;
12152 unsigned char *where_to_put_displacement
= NULL
;
12153 offsetT target_address
;
12154 offsetT opcode_address
;
12155 unsigned int extension
= 0;
12156 offsetT displacement_from_opcode_start
;
12158 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12159 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12160 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12162 /* Generate nop padding. */
12163 unsigned int size
= fragP
->tc_frag_data
.length
;
12166 if (size
> fragP
->tc_frag_data
.max_bytes
)
12172 const char *branch
= "branch";
12173 const char *prefix
= "";
12174 fragS
*padding_fragP
;
12175 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12178 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12179 switch (fragP
->tc_frag_data
.default_prefix
)
12184 case CS_PREFIX_OPCODE
:
12187 case DS_PREFIX_OPCODE
:
12190 case ES_PREFIX_OPCODE
:
12193 case FS_PREFIX_OPCODE
:
12196 case GS_PREFIX_OPCODE
:
12199 case SS_PREFIX_OPCODE
:
12204 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12205 "%s within %d-byte boundary\n");
12207 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12208 "align %s within %d-byte boundary\n");
12212 padding_fragP
= fragP
;
12213 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12214 "%s within %d-byte boundary\n");
12218 switch (padding_fragP
->tc_frag_data
.branch_type
)
12220 case align_branch_jcc
:
12223 case align_branch_fused
:
12224 branch
= "fused jcc";
12226 case align_branch_jmp
:
12229 case align_branch_call
:
12232 case align_branch_indirect
:
12233 branch
= "indiret branch";
12235 case align_branch_ret
:
12242 fprintf (stdout
, msg
,
12243 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12244 (long long) fragP
->fr_address
, branch
,
12245 1 << align_branch_power
);
12247 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12248 memset (fragP
->fr_opcode
,
12249 fragP
->tc_frag_data
.default_prefix
, size
);
12251 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12253 fragP
->fr_fix
+= size
;
12258 opcode
= (unsigned char *) fragP
->fr_opcode
;
12260 /* Address we want to reach in file space. */
12261 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12263 /* Address opcode resides at in file space. */
12264 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12266 /* Displacement from opcode start to fill into instruction. */
12267 displacement_from_opcode_start
= target_address
- opcode_address
;
12269 if ((fragP
->fr_subtype
& BIG
) == 0)
12271 /* Don't have to change opcode. */
12272 extension
= 1; /* 1 opcode + 1 displacement */
12273 where_to_put_displacement
= &opcode
[1];
12277 if (no_cond_jump_promotion
12278 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12279 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12280 _("long jump required"));
12282 switch (fragP
->fr_subtype
)
12284 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12285 extension
= 4; /* 1 opcode + 4 displacement */
12287 where_to_put_displacement
= &opcode
[1];
12290 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12291 extension
= 2; /* 1 opcode + 2 displacement */
12293 where_to_put_displacement
= &opcode
[1];
12296 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12297 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12298 extension
= 5; /* 2 opcode + 4 displacement */
12299 opcode
[1] = opcode
[0] + 0x10;
12300 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12301 where_to_put_displacement
= &opcode
[2];
12304 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12305 extension
= 3; /* 2 opcode + 2 displacement */
12306 opcode
[1] = opcode
[0] + 0x10;
12307 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12308 where_to_put_displacement
= &opcode
[2];
12311 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12316 where_to_put_displacement
= &opcode
[3];
12320 BAD_CASE (fragP
->fr_subtype
);
12325 /* If size if less then four we are sure that the operand fits,
12326 but if it's 4, then it could be that the displacement is larger
12328 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12330 && ((addressT
) (displacement_from_opcode_start
- extension
12331 + ((addressT
) 1 << 31))
12332 > (((addressT
) 2 << 31) - 1)))
12334 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12335 _("jump target out of range"));
12336 /* Make us emit 0. */
12337 displacement_from_opcode_start
= extension
;
12339 /* Now put displacement after opcode. */
12340 md_number_to_chars ((char *) where_to_put_displacement
,
12341 (valueT
) (displacement_from_opcode_start
- extension
),
12342 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12343 fragP
->fr_fix
+= extension
;
12346 /* Apply a fixup (fixP) to segment data, once it has been determined
12347 by our caller that we have all the info we need to fix it up.
12349 Parameter valP is the pointer to the value of the bits.
12351 On the 386, immediates, displacements, and data pointers are all in
12352 the same (little-endian) format, so we don't need to care about which
12353 we are handling. */
12356 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12358 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12359 valueT value
= *valP
;
12361 #if !defined (TE_Mach)
12362 if (fixP
->fx_pcrel
)
12364 switch (fixP
->fx_r_type
)
12370 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12373 case BFD_RELOC_X86_64_32S
:
12374 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12377 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12380 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12385 if (fixP
->fx_addsy
!= NULL
12386 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12387 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12388 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12389 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12390 && !use_rela_relocations
)
12392 /* This is a hack. There should be a better way to handle this.
12393 This covers for the fact that bfd_install_relocation will
12394 subtract the current location (for partial_inplace, PC relative
12395 relocations); see more below. */
12399 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12402 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12407 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12409 if ((sym_seg
== seg
12410 || (symbol_section_p (fixP
->fx_addsy
)
12411 && sym_seg
!= absolute_section
))
12412 && !generic_force_reloc (fixP
))
12414 /* Yes, we add the values in twice. This is because
12415 bfd_install_relocation subtracts them out again. I think
12416 bfd_install_relocation is broken, but I don't dare change
12418 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12422 #if defined (OBJ_COFF) && defined (TE_PE)
12423 /* For some reason, the PE format does not store a
12424 section address offset for a PC relative symbol. */
12425 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12426 || S_IS_WEAK (fixP
->fx_addsy
))
12427 value
+= md_pcrel_from (fixP
);
12430 #if defined (OBJ_COFF) && defined (TE_PE)
12431 if (fixP
->fx_addsy
!= NULL
12432 && S_IS_WEAK (fixP
->fx_addsy
)
12433 /* PR 16858: Do not modify weak function references. */
12434 && ! fixP
->fx_pcrel
)
12436 #if !defined (TE_PEP)
12437 /* For x86 PE weak function symbols are neither PC-relative
12438 nor do they set S_IS_FUNCTION. So the only reliable way
12439 to detect them is to check the flags of their containing
12441 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12442 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12446 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12450 /* Fix a few things - the dynamic linker expects certain values here,
12451 and we must not disappoint it. */
12452 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12453 if (IS_ELF
&& fixP
->fx_addsy
)
12454 switch (fixP
->fx_r_type
)
12456 case BFD_RELOC_386_PLT32
:
12457 case BFD_RELOC_X86_64_PLT32
:
12458 /* Make the jump instruction point to the address of the operand.
12459 At runtime we merely add the offset to the actual PLT entry.
12460 NB: Subtract the offset size only for jump instructions. */
12461 if (fixP
->fx_pcrel
)
12465 case BFD_RELOC_386_TLS_GD
:
12466 case BFD_RELOC_386_TLS_LDM
:
12467 case BFD_RELOC_386_TLS_IE_32
:
12468 case BFD_RELOC_386_TLS_IE
:
12469 case BFD_RELOC_386_TLS_GOTIE
:
12470 case BFD_RELOC_386_TLS_GOTDESC
:
12471 case BFD_RELOC_X86_64_TLSGD
:
12472 case BFD_RELOC_X86_64_TLSLD
:
12473 case BFD_RELOC_X86_64_GOTTPOFF
:
12474 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12475 value
= 0; /* Fully resolved at runtime. No addend. */
12477 case BFD_RELOC_386_TLS_LE
:
12478 case BFD_RELOC_386_TLS_LDO_32
:
12479 case BFD_RELOC_386_TLS_LE_32
:
12480 case BFD_RELOC_X86_64_DTPOFF32
:
12481 case BFD_RELOC_X86_64_DTPOFF64
:
12482 case BFD_RELOC_X86_64_TPOFF32
:
12483 case BFD_RELOC_X86_64_TPOFF64
:
12484 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12487 case BFD_RELOC_386_TLS_DESC_CALL
:
12488 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12489 value
= 0; /* Fully resolved at runtime. No addend. */
12490 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12494 case BFD_RELOC_VTABLE_INHERIT
:
12495 case BFD_RELOC_VTABLE_ENTRY
:
12502 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12504 #endif /* !defined (TE_Mach) */
12506 /* Are we finished with this relocation now? */
12507 if (fixP
->fx_addsy
== NULL
)
12509 #if defined (OBJ_COFF) && defined (TE_PE)
12510 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12513 /* Remember value for tc_gen_reloc. */
12514 fixP
->fx_addnumber
= value
;
12515 /* Clear out the frag for now. */
12519 else if (use_rela_relocations
)
12521 fixP
->fx_no_overflow
= 1;
12522 /* Remember value for tc_gen_reloc. */
12523 fixP
->fx_addnumber
= value
;
12527 md_number_to_chars (p
, value
, fixP
->fx_size
);
12531 md_atof (int type
, char *litP
, int *sizeP
)
12533 /* This outputs the LITTLENUMs in REVERSE order;
12534 in accord with the bigendian 386. */
12535 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12538 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12541 output_invalid (int c
)
12544 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12547 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12548 "(0x%x)", (unsigned char) c
);
12549 return output_invalid_buf
;
12552 /* Verify that @r can be used in the current context. */
12554 static bfd_boolean
check_register (const reg_entry
*r
)
12556 if (allow_pseudo_reg
)
12559 if (operand_type_all_zero (&r
->reg_type
))
12562 if ((r
->reg_type
.bitfield
.dword
12563 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12564 || r
->reg_type
.bitfield
.class == RegCR
12565 || r
->reg_type
.bitfield
.class == RegDR
)
12566 && !cpu_arch_flags
.bitfield
.cpui386
)
12569 if (r
->reg_type
.bitfield
.class == RegTR
12570 && (flag_code
== CODE_64BIT
12571 || !cpu_arch_flags
.bitfield
.cpui386
12572 || cpu_arch_isa_flags
.bitfield
.cpui586
12573 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12576 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12579 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12581 if (r
->reg_type
.bitfield
.zmmword
12582 || r
->reg_type
.bitfield
.class == RegMask
)
12585 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12587 if (r
->reg_type
.bitfield
.ymmword
)
12590 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12595 if (r
->reg_type
.bitfield
.tmmword
12596 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12597 || flag_code
!= CODE_64BIT
))
12600 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12603 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12604 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12607 /* Upper 16 vector registers are only available with VREX in 64bit
12608 mode, and require EVEX encoding. */
12609 if (r
->reg_flags
& RegVRex
)
12611 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12612 || flag_code
!= CODE_64BIT
)
12615 if (i
.vec_encoding
== vex_encoding_default
)
12616 i
.vec_encoding
= vex_encoding_evex
;
12617 else if (i
.vec_encoding
!= vex_encoding_evex
)
12618 i
.vec_encoding
= vex_encoding_error
;
12621 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12622 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12623 && flag_code
!= CODE_64BIT
)
12626 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12633 /* REG_STRING starts *before* REGISTER_PREFIX. */
12635 static const reg_entry
*
12636 parse_real_register (char *reg_string
, char **end_op
)
12638 char *s
= reg_string
;
12640 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12641 const reg_entry
*r
;
12643 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12644 if (*s
== REGISTER_PREFIX
)
12647 if (is_space_char (*s
))
12650 p
= reg_name_given
;
12651 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12653 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12654 return (const reg_entry
*) NULL
;
12658 /* For naked regs, make sure that we are not dealing with an identifier.
12659 This prevents confusing an identifier like `eax_var' with register
12661 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12662 return (const reg_entry
*) NULL
;
12666 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12668 /* Handle floating point regs, allowing spaces in the (i) part. */
12669 if (r
== i386_regtab
/* %st is first entry of table */)
12671 if (!cpu_arch_flags
.bitfield
.cpu8087
12672 && !cpu_arch_flags
.bitfield
.cpu287
12673 && !cpu_arch_flags
.bitfield
.cpu387
12674 && !allow_pseudo_reg
)
12675 return (const reg_entry
*) NULL
;
12677 if (is_space_char (*s
))
12682 if (is_space_char (*s
))
12684 if (*s
>= '0' && *s
<= '7')
12686 int fpr
= *s
- '0';
12688 if (is_space_char (*s
))
12693 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12698 /* We have "%st(" then garbage. */
12699 return (const reg_entry
*) NULL
;
12703 return r
&& check_register (r
) ? r
: NULL
;
12706 /* REG_STRING starts *before* REGISTER_PREFIX. */
12708 static const reg_entry
*
12709 parse_register (char *reg_string
, char **end_op
)
12711 const reg_entry
*r
;
12713 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12714 r
= parse_real_register (reg_string
, end_op
);
12719 char *save
= input_line_pointer
;
12723 input_line_pointer
= reg_string
;
12724 c
= get_symbol_name (®_string
);
12725 symbolP
= symbol_find (reg_string
);
12726 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12728 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12730 know (e
->X_op
== O_register
);
12731 know (e
->X_add_number
>= 0
12732 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12733 r
= i386_regtab
+ e
->X_add_number
;
12734 if (!check_register (r
))
12736 as_bad (_("register '%s%s' cannot be used here"),
12737 register_prefix
, r
->reg_name
);
12740 *end_op
= input_line_pointer
;
12742 *input_line_pointer
= c
;
12743 input_line_pointer
= save
;
12749 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12751 const reg_entry
*r
;
12752 char *end
= input_line_pointer
;
12755 r
= parse_register (name
, &input_line_pointer
);
12756 if (r
&& end
<= input_line_pointer
)
12758 *nextcharP
= *input_line_pointer
;
12759 *input_line_pointer
= 0;
12762 e
->X_op
= O_register
;
12763 e
->X_add_number
= r
- i386_regtab
;
12766 e
->X_op
= O_illegal
;
12769 input_line_pointer
= end
;
12771 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12775 md_operand (expressionS
*e
)
12778 const reg_entry
*r
;
12780 switch (*input_line_pointer
)
12782 case REGISTER_PREFIX
:
12783 r
= parse_real_register (input_line_pointer
, &end
);
12786 e
->X_op
= O_register
;
12787 e
->X_add_number
= r
- i386_regtab
;
12788 input_line_pointer
= end
;
12793 gas_assert (intel_syntax
);
12794 end
= input_line_pointer
++;
12796 if (*input_line_pointer
== ']')
12798 ++input_line_pointer
;
12799 e
->X_op_symbol
= make_expr_symbol (e
);
12800 e
->X_add_symbol
= NULL
;
12801 e
->X_add_number
= 0;
12806 e
->X_op
= O_absent
;
12807 input_line_pointer
= end
;
12814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12815 const char *md_shortopts
= "kVQ:sqnO::";
12817 const char *md_shortopts
= "qnO::";
12820 #define OPTION_32 (OPTION_MD_BASE + 0)
12821 #define OPTION_64 (OPTION_MD_BASE + 1)
12822 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12823 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12824 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12825 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12826 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12827 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12828 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12829 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12830 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12831 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12832 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12833 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12834 #define OPTION_X32 (OPTION_MD_BASE + 14)
12835 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12836 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12837 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12838 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12839 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12840 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12841 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12842 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12843 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12844 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12845 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12846 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12847 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12848 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12849 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12850 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12851 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12852 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12853 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12855 struct option md_longopts
[] =
12857 {"32", no_argument
, NULL
, OPTION_32
},
12858 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12859 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12860 {"64", no_argument
, NULL
, OPTION_64
},
12862 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12863 {"x32", no_argument
, NULL
, OPTION_X32
},
12864 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12865 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12867 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12868 {"march", required_argument
, NULL
, OPTION_MARCH
},
12869 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12870 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12871 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12872 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12873 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12874 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12875 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12876 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12877 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12878 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12879 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12880 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12881 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12882 # if defined (TE_PE) || defined (TE_PEP)
12883 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12885 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12886 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12887 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12888 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12889 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12890 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12891 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12892 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12893 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12894 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12895 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12896 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12897 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12898 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12899 {NULL
, no_argument
, NULL
, 0}
12901 size_t md_longopts_size
= sizeof (md_longopts
);
12904 md_parse_option (int c
, const char *arg
)
12907 char *arch
, *next
, *saved
, *type
;
12912 optimize_align_code
= 0;
12916 quiet_warnings
= 1;
12919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12920 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12921 should be emitted or not. FIXME: Not implemented. */
12923 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12927 /* -V: SVR4 argument to print version ID. */
12929 print_version_id ();
12932 /* -k: Ignore for FreeBSD compatibility. */
12937 /* -s: On i386 Solaris, this tells the native assembler to use
12938 .stab instead of .stab.excl. We always use .stab anyhow. */
12941 case OPTION_MSHARED
:
12945 case OPTION_X86_USED_NOTE
:
12946 if (strcasecmp (arg
, "yes") == 0)
12948 else if (strcasecmp (arg
, "no") == 0)
12951 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12956 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12957 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12960 const char **list
, **l
;
12962 list
= bfd_target_list ();
12963 for (l
= list
; *l
!= NULL
; l
++)
12964 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12965 || strcmp (*l
, "coff-x86-64") == 0
12966 || strcmp (*l
, "pe-x86-64") == 0
12967 || strcmp (*l
, "pei-x86-64") == 0
12968 || strcmp (*l
, "mach-o-x86-64") == 0)
12970 default_arch
= "x86_64";
12974 as_fatal (_("no compiled in support for x86_64"));
12980 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12984 const char **list
, **l
;
12986 list
= bfd_target_list ();
12987 for (l
= list
; *l
!= NULL
; l
++)
12988 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12990 default_arch
= "x86_64:32";
12994 as_fatal (_("no compiled in support for 32bit x86_64"));
12998 as_fatal (_("32bit x86_64 is only supported for ELF"));
13003 default_arch
= "i386";
13006 case OPTION_DIVIDE
:
13007 #ifdef SVR4_COMMENT_CHARS
13012 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13014 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13018 i386_comment_chars
= n
;
13024 saved
= xstrdup (arg
);
13026 /* Allow -march=+nosse. */
13032 as_fatal (_("invalid -march= option: `%s'"), arg
);
13033 next
= strchr (arch
, '+');
13036 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13038 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13041 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13044 cpu_arch_name
= cpu_arch
[j
].name
;
13045 cpu_sub_arch_name
= NULL
;
13046 cpu_arch_flags
= cpu_arch
[j
].flags
;
13047 cpu_arch_isa
= cpu_arch
[j
].type
;
13048 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13049 if (!cpu_arch_tune_set
)
13051 cpu_arch_tune
= cpu_arch_isa
;
13052 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13056 else if (*cpu_arch
[j
].name
== '.'
13057 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13059 /* ISA extension. */
13060 i386_cpu_flags flags
;
13062 flags
= cpu_flags_or (cpu_arch_flags
,
13063 cpu_arch
[j
].flags
);
13065 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13067 if (cpu_sub_arch_name
)
13069 char *name
= cpu_sub_arch_name
;
13070 cpu_sub_arch_name
= concat (name
,
13072 (const char *) NULL
);
13076 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13077 cpu_arch_flags
= flags
;
13078 cpu_arch_isa_flags
= flags
;
13082 = cpu_flags_or (cpu_arch_isa_flags
,
13083 cpu_arch
[j
].flags
);
13088 if (j
>= ARRAY_SIZE (cpu_arch
))
13090 /* Disable an ISA extension. */
13091 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13092 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13094 i386_cpu_flags flags
;
13096 flags
= cpu_flags_and_not (cpu_arch_flags
,
13097 cpu_noarch
[j
].flags
);
13098 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13100 if (cpu_sub_arch_name
)
13102 char *name
= cpu_sub_arch_name
;
13103 cpu_sub_arch_name
= concat (arch
,
13104 (const char *) NULL
);
13108 cpu_sub_arch_name
= xstrdup (arch
);
13109 cpu_arch_flags
= flags
;
13110 cpu_arch_isa_flags
= flags
;
13115 if (j
>= ARRAY_SIZE (cpu_noarch
))
13116 j
= ARRAY_SIZE (cpu_arch
);
13119 if (j
>= ARRAY_SIZE (cpu_arch
))
13120 as_fatal (_("invalid -march= option: `%s'"), arg
);
13124 while (next
!= NULL
);
13130 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13131 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13133 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13135 cpu_arch_tune_set
= 1;
13136 cpu_arch_tune
= cpu_arch
[j
].type
;
13137 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13141 if (j
>= ARRAY_SIZE (cpu_arch
))
13142 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13145 case OPTION_MMNEMONIC
:
13146 if (strcasecmp (arg
, "att") == 0)
13147 intel_mnemonic
= 0;
13148 else if (strcasecmp (arg
, "intel") == 0)
13149 intel_mnemonic
= 1;
13151 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13154 case OPTION_MSYNTAX
:
13155 if (strcasecmp (arg
, "att") == 0)
13157 else if (strcasecmp (arg
, "intel") == 0)
13160 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13163 case OPTION_MINDEX_REG
:
13164 allow_index_reg
= 1;
13167 case OPTION_MNAKED_REG
:
13168 allow_naked_reg
= 1;
13171 case OPTION_MSSE2AVX
:
13175 case OPTION_MSSE_CHECK
:
13176 if (strcasecmp (arg
, "error") == 0)
13177 sse_check
= check_error
;
13178 else if (strcasecmp (arg
, "warning") == 0)
13179 sse_check
= check_warning
;
13180 else if (strcasecmp (arg
, "none") == 0)
13181 sse_check
= check_none
;
13183 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13186 case OPTION_MOPERAND_CHECK
:
13187 if (strcasecmp (arg
, "error") == 0)
13188 operand_check
= check_error
;
13189 else if (strcasecmp (arg
, "warning") == 0)
13190 operand_check
= check_warning
;
13191 else if (strcasecmp (arg
, "none") == 0)
13192 operand_check
= check_none
;
13194 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13197 case OPTION_MAVXSCALAR
:
13198 if (strcasecmp (arg
, "128") == 0)
13199 avxscalar
= vex128
;
13200 else if (strcasecmp (arg
, "256") == 0)
13201 avxscalar
= vex256
;
13203 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13206 case OPTION_MVEXWIG
:
13207 if (strcmp (arg
, "0") == 0)
13209 else if (strcmp (arg
, "1") == 0)
13212 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13215 case OPTION_MADD_BND_PREFIX
:
13216 add_bnd_prefix
= 1;
13219 case OPTION_MEVEXLIG
:
13220 if (strcmp (arg
, "128") == 0)
13221 evexlig
= evexl128
;
13222 else if (strcmp (arg
, "256") == 0)
13223 evexlig
= evexl256
;
13224 else if (strcmp (arg
, "512") == 0)
13225 evexlig
= evexl512
;
13227 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13230 case OPTION_MEVEXRCIG
:
13231 if (strcmp (arg
, "rne") == 0)
13233 else if (strcmp (arg
, "rd") == 0)
13235 else if (strcmp (arg
, "ru") == 0)
13237 else if (strcmp (arg
, "rz") == 0)
13240 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13243 case OPTION_MEVEXWIG
:
13244 if (strcmp (arg
, "0") == 0)
13246 else if (strcmp (arg
, "1") == 0)
13249 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13252 # if defined (TE_PE) || defined (TE_PEP)
13253 case OPTION_MBIG_OBJ
:
13258 case OPTION_MOMIT_LOCK_PREFIX
:
13259 if (strcasecmp (arg
, "yes") == 0)
13260 omit_lock_prefix
= 1;
13261 else if (strcasecmp (arg
, "no") == 0)
13262 omit_lock_prefix
= 0;
13264 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13267 case OPTION_MFENCE_AS_LOCK_ADD
:
13268 if (strcasecmp (arg
, "yes") == 0)
13270 else if (strcasecmp (arg
, "no") == 0)
13273 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13276 case OPTION_MLFENCE_AFTER_LOAD
:
13277 if (strcasecmp (arg
, "yes") == 0)
13278 lfence_after_load
= 1;
13279 else if (strcasecmp (arg
, "no") == 0)
13280 lfence_after_load
= 0;
13282 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13285 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13286 if (strcasecmp (arg
, "all") == 0)
13288 lfence_before_indirect_branch
= lfence_branch_all
;
13289 if (lfence_before_ret
== lfence_before_ret_none
)
13290 lfence_before_ret
= lfence_before_ret_shl
;
13292 else if (strcasecmp (arg
, "memory") == 0)
13293 lfence_before_indirect_branch
= lfence_branch_memory
;
13294 else if (strcasecmp (arg
, "register") == 0)
13295 lfence_before_indirect_branch
= lfence_branch_register
;
13296 else if (strcasecmp (arg
, "none") == 0)
13297 lfence_before_indirect_branch
= lfence_branch_none
;
13299 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13303 case OPTION_MLFENCE_BEFORE_RET
:
13304 if (strcasecmp (arg
, "or") == 0)
13305 lfence_before_ret
= lfence_before_ret_or
;
13306 else if (strcasecmp (arg
, "not") == 0)
13307 lfence_before_ret
= lfence_before_ret_not
;
13308 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13309 lfence_before_ret
= lfence_before_ret_shl
;
13310 else if (strcasecmp (arg
, "none") == 0)
13311 lfence_before_ret
= lfence_before_ret_none
;
13313 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13317 case OPTION_MRELAX_RELOCATIONS
:
13318 if (strcasecmp (arg
, "yes") == 0)
13319 generate_relax_relocations
= 1;
13320 else if (strcasecmp (arg
, "no") == 0)
13321 generate_relax_relocations
= 0;
13323 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13326 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13329 long int align
= strtoul (arg
, &end
, 0);
13334 align_branch_power
= 0;
13337 else if (align
>= 16)
13340 for (align_power
= 0;
13342 align
>>= 1, align_power
++)
13344 /* Limit alignment power to 31. */
13345 if (align
== 1 && align_power
< 32)
13347 align_branch_power
= align_power
;
13352 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13356 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13359 int align
= strtoul (arg
, &end
, 0);
13360 /* Some processors only support 5 prefixes. */
13361 if (*end
== '\0' && align
>= 0 && align
< 6)
13363 align_branch_prefix_size
= align
;
13366 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13371 case OPTION_MALIGN_BRANCH
:
13373 saved
= xstrdup (arg
);
13377 next
= strchr (type
, '+');
13380 if (strcasecmp (type
, "jcc") == 0)
13381 align_branch
|= align_branch_jcc_bit
;
13382 else if (strcasecmp (type
, "fused") == 0)
13383 align_branch
|= align_branch_fused_bit
;
13384 else if (strcasecmp (type
, "jmp") == 0)
13385 align_branch
|= align_branch_jmp_bit
;
13386 else if (strcasecmp (type
, "call") == 0)
13387 align_branch
|= align_branch_call_bit
;
13388 else if (strcasecmp (type
, "ret") == 0)
13389 align_branch
|= align_branch_ret_bit
;
13390 else if (strcasecmp (type
, "indirect") == 0)
13391 align_branch
|= align_branch_indirect_bit
;
13393 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13396 while (next
!= NULL
);
13400 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13401 align_branch_power
= 5;
13402 align_branch_prefix_size
= 5;
13403 align_branch
= (align_branch_jcc_bit
13404 | align_branch_fused_bit
13405 | align_branch_jmp_bit
);
13408 case OPTION_MAMD64
:
13412 case OPTION_MINTEL64
:
13420 /* Turn off -Os. */
13421 optimize_for_space
= 0;
13423 else if (*arg
== 's')
13425 optimize_for_space
= 1;
13426 /* Turn on all encoding optimizations. */
13427 optimize
= INT_MAX
;
13431 optimize
= atoi (arg
);
13432 /* Turn off -Os. */
13433 optimize_for_space
= 0;
13443 #define MESSAGE_TEMPLATE \
13447 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13448 int *left_p
, const char *name
, int len
)
13450 int size
= sizeof (MESSAGE_TEMPLATE
);
13451 int left
= *left_p
;
13453 /* Reserve 2 spaces for ", " or ",\0" */
13456 /* Check if there is any room. */
13464 p
= mempcpy (p
, name
, len
);
13468 /* Output the current message now and start a new one. */
13471 fprintf (stream
, "%s\n", message
);
13473 left
= size
- (start
- message
) - len
- 2;
13475 gas_assert (left
>= 0);
13477 p
= mempcpy (p
, name
, len
);
13485 show_arch (FILE *stream
, int ext
, int check
)
13487 static char message
[] = MESSAGE_TEMPLATE
;
13488 char *start
= message
+ 27;
13490 int size
= sizeof (MESSAGE_TEMPLATE
);
13497 left
= size
- (start
- message
);
13498 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13500 /* Should it be skipped? */
13501 if (cpu_arch
[j
].skip
)
13504 name
= cpu_arch
[j
].name
;
13505 len
= cpu_arch
[j
].len
;
13508 /* It is an extension. Skip if we aren't asked to show it. */
13519 /* It is an processor. Skip if we show only extension. */
13522 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13524 /* It is an impossible processor - skip. */
13528 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13531 /* Display disabled extensions. */
13533 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13535 name
= cpu_noarch
[j
].name
;
13536 len
= cpu_noarch
[j
].len
;
13537 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13542 fprintf (stream
, "%s\n", message
);
13546 md_show_usage (FILE *stream
)
13548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13549 fprintf (stream
, _("\
13550 -Qy, -Qn ignored\n\
13551 -V print assembler version number\n\
13554 fprintf (stream
, _("\
13555 -n Do not optimize code alignment\n\
13556 -q quieten some warnings\n"));
13557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13558 fprintf (stream
, _("\
13561 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13562 || defined (TE_PE) || defined (TE_PEP))
13563 fprintf (stream
, _("\
13564 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13566 #ifdef SVR4_COMMENT_CHARS
13567 fprintf (stream
, _("\
13568 --divide do not treat `/' as a comment character\n"));
13570 fprintf (stream
, _("\
13571 --divide ignored\n"));
13573 fprintf (stream
, _("\
13574 -march=CPU[,+EXTENSION...]\n\
13575 generate code for CPU and EXTENSION, CPU is one of:\n"));
13576 show_arch (stream
, 0, 1);
13577 fprintf (stream
, _("\
13578 EXTENSION is combination of:\n"));
13579 show_arch (stream
, 1, 0);
13580 fprintf (stream
, _("\
13581 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13582 show_arch (stream
, 0, 0);
13583 fprintf (stream
, _("\
13584 -msse2avx encode SSE instructions with VEX prefix\n"));
13585 fprintf (stream
, _("\
13586 -msse-check=[none|error|warning] (default: warning)\n\
13587 check SSE instructions\n"));
13588 fprintf (stream
, _("\
13589 -moperand-check=[none|error|warning] (default: warning)\n\
13590 check operand combinations for validity\n"));
13591 fprintf (stream
, _("\
13592 -mavxscalar=[128|256] (default: 128)\n\
13593 encode scalar AVX instructions with specific vector\n\
13595 fprintf (stream
, _("\
13596 -mvexwig=[0|1] (default: 0)\n\
13597 encode VEX instructions with specific VEX.W value\n\
13598 for VEX.W bit ignored instructions\n"));
13599 fprintf (stream
, _("\
13600 -mevexlig=[128|256|512] (default: 128)\n\
13601 encode scalar EVEX instructions with specific vector\n\
13603 fprintf (stream
, _("\
13604 -mevexwig=[0|1] (default: 0)\n\
13605 encode EVEX instructions with specific EVEX.W value\n\
13606 for EVEX.W bit ignored instructions\n"));
13607 fprintf (stream
, _("\
13608 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13609 encode EVEX instructions with specific EVEX.RC value\n\
13610 for SAE-only ignored instructions\n"));
13611 fprintf (stream
, _("\
13612 -mmnemonic=[att|intel] "));
13613 if (SYSV386_COMPAT
)
13614 fprintf (stream
, _("(default: att)\n"));
13616 fprintf (stream
, _("(default: intel)\n"));
13617 fprintf (stream
, _("\
13618 use AT&T/Intel mnemonic\n"));
13619 fprintf (stream
, _("\
13620 -msyntax=[att|intel] (default: att)\n\
13621 use AT&T/Intel syntax\n"));
13622 fprintf (stream
, _("\
13623 -mindex-reg support pseudo index registers\n"));
13624 fprintf (stream
, _("\
13625 -mnaked-reg don't require `%%' prefix for registers\n"));
13626 fprintf (stream
, _("\
13627 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13628 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13629 fprintf (stream
, _("\
13630 -mshared disable branch optimization for shared code\n"));
13631 fprintf (stream
, _("\
13632 -mx86-used-note=[no|yes] "));
13633 if (DEFAULT_X86_USED_NOTE
)
13634 fprintf (stream
, _("(default: yes)\n"));
13636 fprintf (stream
, _("(default: no)\n"));
13637 fprintf (stream
, _("\
13638 generate x86 used ISA and feature properties\n"));
13640 #if defined (TE_PE) || defined (TE_PEP)
13641 fprintf (stream
, _("\
13642 -mbig-obj generate big object files\n"));
13644 fprintf (stream
, _("\
13645 -momit-lock-prefix=[no|yes] (default: no)\n\
13646 strip all lock prefixes\n"));
13647 fprintf (stream
, _("\
13648 -mfence-as-lock-add=[no|yes] (default: no)\n\
13649 encode lfence, mfence and sfence as\n\
13650 lock addl $0x0, (%%{re}sp)\n"));
13651 fprintf (stream
, _("\
13652 -mrelax-relocations=[no|yes] "));
13653 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13654 fprintf (stream
, _("(default: yes)\n"));
13656 fprintf (stream
, _("(default: no)\n"));
13657 fprintf (stream
, _("\
13658 generate relax relocations\n"));
13659 fprintf (stream
, _("\
13660 -malign-branch-boundary=NUM (default: 0)\n\
13661 align branches within NUM byte boundary\n"));
13662 fprintf (stream
, _("\
13663 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13664 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13666 specify types of branches to align\n"));
13667 fprintf (stream
, _("\
13668 -malign-branch-prefix-size=NUM (default: 5)\n\
13669 align branches with NUM prefixes per instruction\n"));
13670 fprintf (stream
, _("\
13671 -mbranches-within-32B-boundaries\n\
13672 align branches within 32 byte boundary\n"));
13673 fprintf (stream
, _("\
13674 -mlfence-after-load=[no|yes] (default: no)\n\
13675 generate lfence after load\n"));
13676 fprintf (stream
, _("\
13677 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13678 generate lfence before indirect near branch\n"));
13679 fprintf (stream
, _("\
13680 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13681 generate lfence before ret\n"));
13682 fprintf (stream
, _("\
13683 -mamd64 accept only AMD64 ISA [default]\n"));
13684 fprintf (stream
, _("\
13685 -mintel64 accept only Intel64 ISA\n"));
13688 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13689 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13690 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13692 /* Pick the target format to use. */
13695 i386_target_format (void)
13697 if (!strncmp (default_arch
, "x86_64", 6))
13699 update_code_flag (CODE_64BIT
, 1);
13700 if (default_arch
[6] == '\0')
13701 x86_elf_abi
= X86_64_ABI
;
13703 x86_elf_abi
= X86_64_X32_ABI
;
13705 else if (!strcmp (default_arch
, "i386"))
13706 update_code_flag (CODE_32BIT
, 1);
13707 else if (!strcmp (default_arch
, "iamcu"))
13709 update_code_flag (CODE_32BIT
, 1);
13710 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13712 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13713 cpu_arch_name
= "iamcu";
13714 cpu_sub_arch_name
= NULL
;
13715 cpu_arch_flags
= iamcu_flags
;
13716 cpu_arch_isa
= PROCESSOR_IAMCU
;
13717 cpu_arch_isa_flags
= iamcu_flags
;
13718 if (!cpu_arch_tune_set
)
13720 cpu_arch_tune
= cpu_arch_isa
;
13721 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13724 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13725 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13729 as_fatal (_("unknown architecture"));
13731 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13732 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13733 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13734 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13736 switch (OUTPUT_FLAVOR
)
13738 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13739 case bfd_target_aout_flavour
:
13740 return AOUT_TARGET_FORMAT
;
13742 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13743 # if defined (TE_PE) || defined (TE_PEP)
13744 case bfd_target_coff_flavour
:
13745 if (flag_code
== CODE_64BIT
)
13746 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13748 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13749 # elif defined (TE_GO32)
13750 case bfd_target_coff_flavour
:
13751 return "coff-go32";
13753 case bfd_target_coff_flavour
:
13754 return "coff-i386";
13757 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13758 case bfd_target_elf_flavour
:
13760 const char *format
;
13762 switch (x86_elf_abi
)
13765 format
= ELF_TARGET_FORMAT
;
13767 tls_get_addr
= "___tls_get_addr";
13771 use_rela_relocations
= 1;
13774 tls_get_addr
= "__tls_get_addr";
13776 format
= ELF_TARGET_FORMAT64
;
13778 case X86_64_X32_ABI
:
13779 use_rela_relocations
= 1;
13782 tls_get_addr
= "__tls_get_addr";
13784 disallow_64bit_reloc
= 1;
13785 format
= ELF_TARGET_FORMAT32
;
13788 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13790 if (x86_elf_abi
!= X86_64_ABI
)
13791 as_fatal (_("Intel L1OM is 64bit only"));
13792 return ELF_TARGET_L1OM_FORMAT
;
13794 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13796 if (x86_elf_abi
!= X86_64_ABI
)
13797 as_fatal (_("Intel K1OM is 64bit only"));
13798 return ELF_TARGET_K1OM_FORMAT
;
13800 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13802 if (x86_elf_abi
!= I386_ABI
)
13803 as_fatal (_("Intel MCU is 32bit only"));
13804 return ELF_TARGET_IAMCU_FORMAT
;
13810 #if defined (OBJ_MACH_O)
13811 case bfd_target_mach_o_flavour
:
13812 if (flag_code
== CODE_64BIT
)
13814 use_rela_relocations
= 1;
13816 return "mach-o-x86-64";
13819 return "mach-o-i386";
13827 #endif /* OBJ_MAYBE_ more than one */
13830 md_undefined_symbol (char *name
)
13832 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13833 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13834 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13835 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13839 if (symbol_find (name
))
13840 as_bad (_("GOT already in symbol table"));
13841 GOT_symbol
= symbol_new (name
, undefined_section
,
13842 &zero_address_frag
, 0);
13849 /* Round up a section size to the appropriate boundary. */
13852 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13854 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13855 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13857 /* For a.out, force the section size to be aligned. If we don't do
13858 this, BFD will align it for us, but it will not write out the
13859 final bytes of the section. This may be a bug in BFD, but it is
13860 easier to fix it here since that is how the other a.out targets
13864 align
= bfd_section_alignment (segment
);
13865 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13872 /* On the i386, PC-relative offsets are relative to the start of the
13873 next instruction. That is, the address of the offset, plus its
13874 size, since the offset is always the last part of the insn. */
13877 md_pcrel_from (fixS
*fixP
)
13879 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13885 s_bss (int ignore ATTRIBUTE_UNUSED
)
13889 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13891 obj_elf_section_change_hook ();
13893 temp
= get_absolute_expression ();
13894 subseg_set (bss_section
, (subsegT
) temp
);
13895 demand_empty_rest_of_line ();
13900 /* Remember constant directive. */
13903 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13905 if (last_insn
.kind
!= last_insn_directive
13906 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13908 last_insn
.seg
= now_seg
;
13909 last_insn
.kind
= last_insn_directive
;
13910 last_insn
.name
= "constant directive";
13911 last_insn
.file
= as_where (&last_insn
.line
);
13912 if (lfence_before_ret
!= lfence_before_ret_none
)
13914 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13915 as_warn (_("constant directive skips -mlfence-before-ret "
13916 "and -mlfence-before-indirect-branch"));
13918 as_warn (_("constant directive skips -mlfence-before-ret"));
13920 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13921 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13926 i386_validate_fix (fixS
*fixp
)
13928 if (fixp
->fx_subsy
)
13930 if (fixp
->fx_subsy
== GOT_symbol
)
13932 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13937 if (fixp
->fx_tcbit2
)
13938 fixp
->fx_r_type
= (fixp
->fx_tcbit
13939 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13940 : BFD_RELOC_X86_64_GOTPCRELX
);
13943 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13948 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13950 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13952 fixp
->fx_subsy
= 0;
13955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13958 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13959 to section. Since PLT32 relocation must be against symbols,
13960 turn such PLT32 relocation into PC32 relocation. */
13962 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13963 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13964 && symbol_section_p (fixp
->fx_addsy
))
13965 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13968 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13969 && fixp
->fx_tcbit2
)
13970 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13977 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13980 bfd_reloc_code_real_type code
;
13982 switch (fixp
->fx_r_type
)
13984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13985 case BFD_RELOC_SIZE32
:
13986 case BFD_RELOC_SIZE64
:
13987 if (S_IS_DEFINED (fixp
->fx_addsy
)
13988 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13990 /* Resolve size relocation against local symbol to size of
13991 the symbol plus addend. */
13992 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13993 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13994 && !fits_in_unsigned_long (value
))
13995 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13996 _("symbol size computation overflow"));
13997 fixp
->fx_addsy
= NULL
;
13998 fixp
->fx_subsy
= NULL
;
13999 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14003 /* Fall through. */
14005 case BFD_RELOC_X86_64_PLT32
:
14006 case BFD_RELOC_X86_64_GOT32
:
14007 case BFD_RELOC_X86_64_GOTPCREL
:
14008 case BFD_RELOC_X86_64_GOTPCRELX
:
14009 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14010 case BFD_RELOC_386_PLT32
:
14011 case BFD_RELOC_386_GOT32
:
14012 case BFD_RELOC_386_GOT32X
:
14013 case BFD_RELOC_386_GOTOFF
:
14014 case BFD_RELOC_386_GOTPC
:
14015 case BFD_RELOC_386_TLS_GD
:
14016 case BFD_RELOC_386_TLS_LDM
:
14017 case BFD_RELOC_386_TLS_LDO_32
:
14018 case BFD_RELOC_386_TLS_IE_32
:
14019 case BFD_RELOC_386_TLS_IE
:
14020 case BFD_RELOC_386_TLS_GOTIE
:
14021 case BFD_RELOC_386_TLS_LE_32
:
14022 case BFD_RELOC_386_TLS_LE
:
14023 case BFD_RELOC_386_TLS_GOTDESC
:
14024 case BFD_RELOC_386_TLS_DESC_CALL
:
14025 case BFD_RELOC_X86_64_TLSGD
:
14026 case BFD_RELOC_X86_64_TLSLD
:
14027 case BFD_RELOC_X86_64_DTPOFF32
:
14028 case BFD_RELOC_X86_64_DTPOFF64
:
14029 case BFD_RELOC_X86_64_GOTTPOFF
:
14030 case BFD_RELOC_X86_64_TPOFF32
:
14031 case BFD_RELOC_X86_64_TPOFF64
:
14032 case BFD_RELOC_X86_64_GOTOFF64
:
14033 case BFD_RELOC_X86_64_GOTPC32
:
14034 case BFD_RELOC_X86_64_GOT64
:
14035 case BFD_RELOC_X86_64_GOTPCREL64
:
14036 case BFD_RELOC_X86_64_GOTPC64
:
14037 case BFD_RELOC_X86_64_GOTPLT64
:
14038 case BFD_RELOC_X86_64_PLTOFF64
:
14039 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14040 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14041 case BFD_RELOC_RVA
:
14042 case BFD_RELOC_VTABLE_ENTRY
:
14043 case BFD_RELOC_VTABLE_INHERIT
:
14045 case BFD_RELOC_32_SECREL
:
14047 code
= fixp
->fx_r_type
;
14049 case BFD_RELOC_X86_64_32S
:
14050 if (!fixp
->fx_pcrel
)
14052 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14053 code
= fixp
->fx_r_type
;
14056 /* Fall through. */
14058 if (fixp
->fx_pcrel
)
14060 switch (fixp
->fx_size
)
14063 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14064 _("can not do %d byte pc-relative relocation"),
14066 code
= BFD_RELOC_32_PCREL
;
14068 case 1: code
= BFD_RELOC_8_PCREL
; break;
14069 case 2: code
= BFD_RELOC_16_PCREL
; break;
14070 case 4: code
= BFD_RELOC_32_PCREL
; break;
14072 case 8: code
= BFD_RELOC_64_PCREL
; break;
14078 switch (fixp
->fx_size
)
14081 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14082 _("can not do %d byte relocation"),
14084 code
= BFD_RELOC_32
;
14086 case 1: code
= BFD_RELOC_8
; break;
14087 case 2: code
= BFD_RELOC_16
; break;
14088 case 4: code
= BFD_RELOC_32
; break;
14090 case 8: code
= BFD_RELOC_64
; break;
14097 if ((code
== BFD_RELOC_32
14098 || code
== BFD_RELOC_32_PCREL
14099 || code
== BFD_RELOC_X86_64_32S
)
14101 && fixp
->fx_addsy
== GOT_symbol
)
14104 code
= BFD_RELOC_386_GOTPC
;
14106 code
= BFD_RELOC_X86_64_GOTPC32
;
14108 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14110 && fixp
->fx_addsy
== GOT_symbol
)
14112 code
= BFD_RELOC_X86_64_GOTPC64
;
14115 rel
= XNEW (arelent
);
14116 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14117 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14119 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14121 if (!use_rela_relocations
)
14123 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14124 vtable entry to be used in the relocation's section offset. */
14125 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14126 rel
->address
= fixp
->fx_offset
;
14127 #if defined (OBJ_COFF) && defined (TE_PE)
14128 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14129 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14134 /* Use the rela in 64bit mode. */
14137 if (disallow_64bit_reloc
)
14140 case BFD_RELOC_X86_64_DTPOFF64
:
14141 case BFD_RELOC_X86_64_TPOFF64
:
14142 case BFD_RELOC_64_PCREL
:
14143 case BFD_RELOC_X86_64_GOTOFF64
:
14144 case BFD_RELOC_X86_64_GOT64
:
14145 case BFD_RELOC_X86_64_GOTPCREL64
:
14146 case BFD_RELOC_X86_64_GOTPC64
:
14147 case BFD_RELOC_X86_64_GOTPLT64
:
14148 case BFD_RELOC_X86_64_PLTOFF64
:
14149 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14150 _("cannot represent relocation type %s in x32 mode"),
14151 bfd_get_reloc_code_name (code
));
14157 if (!fixp
->fx_pcrel
)
14158 rel
->addend
= fixp
->fx_offset
;
14162 case BFD_RELOC_X86_64_PLT32
:
14163 case BFD_RELOC_X86_64_GOT32
:
14164 case BFD_RELOC_X86_64_GOTPCREL
:
14165 case BFD_RELOC_X86_64_GOTPCRELX
:
14166 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14167 case BFD_RELOC_X86_64_TLSGD
:
14168 case BFD_RELOC_X86_64_TLSLD
:
14169 case BFD_RELOC_X86_64_GOTTPOFF
:
14170 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14171 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14172 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14175 rel
->addend
= (section
->vma
14177 + fixp
->fx_addnumber
14178 + md_pcrel_from (fixp
));
14183 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14184 if (rel
->howto
== NULL
)
14186 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14187 _("cannot represent relocation type %s"),
14188 bfd_get_reloc_code_name (code
));
14189 /* Set howto to a garbage value so that we can keep going. */
14190 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14191 gas_assert (rel
->howto
!= NULL
);
14197 #include "tc-i386-intel.c"
14200 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14202 int saved_naked_reg
;
14203 char saved_register_dot
;
14205 saved_naked_reg
= allow_naked_reg
;
14206 allow_naked_reg
= 1;
14207 saved_register_dot
= register_chars
['.'];
14208 register_chars
['.'] = '.';
14209 allow_pseudo_reg
= 1;
14210 expression_and_evaluate (exp
);
14211 allow_pseudo_reg
= 0;
14212 register_chars
['.'] = saved_register_dot
;
14213 allow_naked_reg
= saved_naked_reg
;
14215 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14217 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14219 exp
->X_op
= O_constant
;
14220 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14221 .dw2_regnum
[flag_code
>> 1];
14224 exp
->X_op
= O_illegal
;
14229 tc_x86_frame_initial_instructions (void)
14231 static unsigned int sp_regno
[2];
14233 if (!sp_regno
[flag_code
>> 1])
14235 char *saved_input
= input_line_pointer
;
14236 char sp
[][4] = {"esp", "rsp"};
14239 input_line_pointer
= sp
[flag_code
>> 1];
14240 tc_x86_parse_to_dw2regnum (&exp
);
14241 gas_assert (exp
.X_op
== O_constant
);
14242 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14243 input_line_pointer
= saved_input
;
14246 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14247 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14251 x86_dwarf2_addr_size (void)
14253 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14254 if (x86_elf_abi
== X86_64_X32_ABI
)
14257 return bfd_arch_bits_per_address (stdoutput
) / 8;
14261 i386_elf_section_type (const char *str
, size_t len
)
14263 if (flag_code
== CODE_64BIT
14264 && len
== sizeof ("unwind") - 1
14265 && strncmp (str
, "unwind", 6) == 0)
14266 return SHT_X86_64_UNWIND
;
14273 i386_solaris_fix_up_eh_frame (segT sec
)
14275 if (flag_code
== CODE_64BIT
)
14276 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14282 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14286 exp
.X_op
= O_secrel
;
14287 exp
.X_add_symbol
= symbol
;
14288 exp
.X_add_number
= 0;
14289 emit_expr (&exp
, size
);
14293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14294 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14297 x86_64_section_letter (int letter
, const char **ptr_msg
)
14299 if (flag_code
== CODE_64BIT
)
14302 return SHF_X86_64_LARGE
;
14304 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14307 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14312 x86_64_section_word (char *str
, size_t len
)
14314 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14315 return SHF_X86_64_LARGE
;
14321 handle_large_common (int small ATTRIBUTE_UNUSED
)
14323 if (flag_code
!= CODE_64BIT
)
14325 s_comm_internal (0, elf_common_parse
);
14326 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14330 static segT lbss_section
;
14331 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14332 asection
*saved_bss_section
= bss_section
;
14334 if (lbss_section
== NULL
)
14336 flagword applicable
;
14337 segT seg
= now_seg
;
14338 subsegT subseg
= now_subseg
;
14340 /* The .lbss section is for local .largecomm symbols. */
14341 lbss_section
= subseg_new (".lbss", 0);
14342 applicable
= bfd_applicable_section_flags (stdoutput
);
14343 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14344 seg_info (lbss_section
)->bss
= 1;
14346 subseg_set (seg
, subseg
);
14349 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14350 bss_section
= lbss_section
;
14352 s_comm_internal (0, elf_common_parse
);
14354 elf_com_section_ptr
= saved_com_section_ptr
;
14355 bss_section
= saved_bss_section
;
14358 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */