1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c
);
69 static int i386_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry
*parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry
*build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS
*, offsetT
);
91 static void output_disp (fragS
*, offsetT
);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
99 static const char *default_arch
= DEFAULT_ARCH
;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry
*regs
;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands
;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types
[MAX_OPERANDS
];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op
[MAX_OPERANDS
];
136 /* Flags for operands. */
137 unsigned int flags
[MAX_OPERANDS
];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry
*base_reg
;
146 const reg_entry
*index_reg
;
147 unsigned int log2_scale_factor
;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry
*seg
[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes
;
156 unsigned char prefix
[MAX_PREFIXES
];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn
;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars
[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars
= "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars
= "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "#/";
210 const char line_separator_chars
[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS
[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS
[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars
[256];
223 static char register_chars
[256];
224 static char operand_chars
[256];
225 static char identifier_chars
[256];
226 static char digit_chars
[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack
[32];
244 static char *save_stack_p
;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates
*current_templates
;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
258 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
260 /* Current operand we are working on. */
261 static int this_operand
;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code
;
272 static unsigned int object_64bit
;
273 static int use_rela_relocations
= 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names
[] =
283 /* 1 for intel syntax,
285 static int intel_syntax
= 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic
= !SYSV386_COMPAT
;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc
= OLDGCC_COMPAT
;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg
= 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg
= 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix
= "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size
= '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code
= 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings
= 0;
315 static const char *cpu_arch_name
= NULL
;
316 static const char *cpu_sub_arch_name
= NULL
;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set
= 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags
;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags
;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion
= 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS
*GOT_symbol
;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column
;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment
;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table
[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch
[] =
430 {"generic32", PROCESSOR_GENERIC32
,
431 CPU_GENERIC32_FLAGS
},
432 {"generic64", PROCESSOR_GENERIC64
,
433 CPU_GENERIC64_FLAGS
},
434 {"i8086", PROCESSOR_UNKNOWN
,
436 {"i186", PROCESSOR_UNKNOWN
,
438 {"i286", PROCESSOR_UNKNOWN
,
440 {"i386", PROCESSOR_I386
,
442 {"i486", PROCESSOR_I486
,
444 {"i586", PROCESSOR_PENTIUM
,
446 {"i686", PROCESSOR_PENTIUMPRO
,
448 {"pentium", PROCESSOR_PENTIUM
,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
452 {"pentiumii", PROCESSOR_PENTIUMPRO
,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
456 {"pentium4", PROCESSOR_PENTIUM4
,
458 {"prescott", PROCESSOR_NOCONA
,
460 {"nocona", PROCESSOR_NOCONA
,
462 {"yonah", PROCESSOR_CORE
,
464 {"core", PROCESSOR_CORE
,
466 {"merom", PROCESSOR_CORE2
,
468 {"core2", PROCESSOR_CORE2
,
472 {"k6_2", PROCESSOR_K6
,
474 {"athlon", PROCESSOR_ATHLON
,
476 {"sledgehammer", PROCESSOR_K8
,
478 {"opteron", PROCESSOR_K8
,
482 {"amdfam10", PROCESSOR_AMDFAM10
,
483 CPU_AMDFAM10_FLAGS
},
484 {".mmx", PROCESSOR_UNKNOWN
,
486 {".sse", PROCESSOR_UNKNOWN
,
488 {".sse2", PROCESSOR_UNKNOWN
,
490 {".sse3", PROCESSOR_UNKNOWN
,
492 {".ssse3", PROCESSOR_UNKNOWN
,
494 {".sse4.1", PROCESSOR_UNKNOWN
,
496 {".sse4.2", PROCESSOR_UNKNOWN
,
498 {".sse4", PROCESSOR_UNKNOWN
,
500 {".3dnow", PROCESSOR_UNKNOWN
,
502 {".3dnowa", PROCESSOR_UNKNOWN
,
504 {".padlock", PROCESSOR_UNKNOWN
,
506 {".pacifica", PROCESSOR_UNKNOWN
,
508 {".svme", PROCESSOR_UNKNOWN
,
510 {".sse4a", PROCESSOR_UNKNOWN
,
512 {".abm", PROCESSOR_UNKNOWN
,
514 {".sse5", PROCESSOR_UNKNOWN
,
518 const pseudo_typeS md_pseudo_table
[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes
, 0},
523 {"align", s_align_ptwo
, 0},
525 {"arch", set_cpu_arch
, 0},
529 {"ffloat", float_cons
, 'f'},
530 {"dfloat", float_cons
, 'd'},
531 {"tfloat", float_cons
, 'x'},
533 {"slong", signed_cons
, 4},
534 {"noopt", s_ignore
, 0},
535 {"optim", s_ignore
, 0},
536 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
537 {"code16", set_code_flag
, CODE_16BIT
},
538 {"code32", set_code_flag
, CODE_32BIT
},
539 {"code64", set_code_flag
, CODE_64BIT
},
540 {"intel_syntax", set_intel_syntax
, 1},
541 {"att_syntax", set_intel_syntax
, 0},
542 {"intel_mnemonic", set_intel_mnemonic
, 1},
543 {"att_mnemonic", set_intel_mnemonic
, 0},
544 {"allow_index_reg", set_allow_index_reg
, 1},
545 {"disallow_index_reg", set_allow_index_reg
, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common
, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
550 {"loc", dwarf2_directive_loc
, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
554 {"secrel32", pe_directive_secrel
, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer
;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control
*op_hash
;
565 /* Hash table for register lookup. */
566 static struct hash_control
*reg_hash
;
569 i386_align_code (fragS
*fragP
, int count
)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1
[] =
576 static const char f32_2
[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3
[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4
[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5
[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6
[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7
[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8
[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9
[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10
[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11
[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12
[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13
[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14
[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3
[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4
[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5
[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6
[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7
[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8
[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31
[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt
[] = {
632 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
633 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
635 static const char *const f16_patt
[] = {
636 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
639 static const char alt_3
[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4
[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5
[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6
[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7
[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8
[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9
[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10
[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14
[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15
[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11
[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13
[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15
[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
735 alt_short_14
, alt_short_15
737 static const char *const alt_long_patt
[] = {
738 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
739 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
740 alt_long_14
, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code
== CODE_16BIT
)
769 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
771 /* Adjust jump offset. */
772 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
775 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
776 f16_patt
[count
- 1], count
);
780 const char *const *patt
= NULL
;
782 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune
)
787 case PROCESSOR_UNKNOWN
:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
791 patt
= alt_long_patt
;
795 case PROCESSOR_PENTIUMPRO
:
796 case PROCESSOR_PENTIUM4
:
797 case PROCESSOR_NOCONA
:
799 case PROCESSOR_CORE2
:
800 case PROCESSOR_GENERIC64
:
801 patt
= alt_long_patt
;
804 case PROCESSOR_ATHLON
:
806 case PROCESSOR_AMDFAM10
:
807 patt
= alt_short_patt
;
811 case PROCESSOR_PENTIUM
:
812 case PROCESSOR_GENERIC32
:
819 switch (cpu_arch_tune
)
821 case PROCESSOR_UNKNOWN
:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM
:
831 case PROCESSOR_ATHLON
:
833 case PROCESSOR_AMDFAM10
:
834 case PROCESSOR_GENERIC32
:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
838 patt
= alt_short_patt
;
842 case PROCESSOR_PENTIUMPRO
:
843 case PROCESSOR_PENTIUM4
:
844 case PROCESSOR_NOCONA
:
846 case PROCESSOR_CORE2
:
847 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
848 patt
= alt_long_patt
;
852 case PROCESSOR_GENERIC64
:
853 patt
= alt_long_patt
;
858 if (patt
== f32_patt
)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
865 patt
[count
- 1], count
);
868 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
870 /* Adjust jump offset. */
871 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
888 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
889 patt
[padding
- 1], padding
);
892 fragP
->fr_var
= count
;
896 uints_all_zero (const unsigned int *x
, unsigned int size
)
914 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
931 uints_equal (const unsigned int *x
, const unsigned int *y
,
943 return x
[0] == y
[0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f
)
962 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
963 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
969 switch (ARRAY_SIZE (x
.array
))
972 x
.array
[2] &= y
.array
[2];
974 x
.array
[1] &= y
.array
[1];
976 x
.array
[0] &= y
.array
[0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
987 switch (ARRAY_SIZE (x
.array
))
990 x
.array
[2] |= y
.array
[2];
992 x
.array
[1] |= y
.array
[1];
994 x
.array
[0] |= y
.array
[0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x
)
1008 int overlap
= cpu_flags_check_cpu64 (x
) ? 2 : 0;
1010 x
.bitfield
.cpu64
= 0;
1011 x
.bitfield
.cpuno64
= 0;
1013 if (UINTS_ALL_ZERO (x
))
1017 i386_cpu_flags cpu
= cpu_arch_flags
;
1019 cpu
.bitfield
.cpu64
= 0;
1020 cpu
.bitfield
.cpuno64
= 0;
1021 cpu
= cpu_flags_and (x
, cpu
);
1022 overlap
|= UINTS_ALL_ZERO (cpu
) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1030 switch (ARRAY_SIZE (x
.array
))
1033 x
.array
[2] &= y
.array
[2];
1035 x
.array
[1] &= y
.array
[1];
1037 x
.array
[0] &= y
.array
[0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1048 switch (ARRAY_SIZE (x
.array
))
1051 x
.array
[2] |= y
.array
[2];
1053 x
.array
[1] |= y
.array
[1];
1055 x
.array
[0] |= y
.array
[0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1066 switch (ARRAY_SIZE (x
.array
))
1069 x
.array
[2] ^= y
.array
[2];
1071 x
.array
[1] ^= y
.array
[1];
1073 x
.array
[0] ^= y
.array
[0];
1081 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1082 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1083 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1086 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1087 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1088 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1089 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP
;
1092 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1093 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1094 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1095 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1096 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1097 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1098 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1099 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1100 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1101 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1112 operand_type_check (i386_operand_type t
, enum operand_type c
)
1117 return (t
.bitfield
.reg8
1120 || t
.bitfield
.reg64
);
1123 return (t
.bitfield
.imm8
1127 || t
.bitfield
.imm32s
1128 || t
.bitfield
.imm64
);
1131 return (t
.bitfield
.disp8
1132 || t
.bitfield
.disp16
1133 || t
.bitfield
.disp32
1134 || t
.bitfield
.disp32s
1135 || t
.bitfield
.disp64
);
1138 return (t
.bitfield
.disp8
1139 || t
.bitfield
.disp16
1140 || t
.bitfield
.disp32
1141 || t
.bitfield
.disp32s
1142 || t
.bitfield
.disp64
1143 || t
.bitfield
.baseindex
);
1151 operand_type_match (i386_operand_type overlap
,
1152 i386_operand_type given
)
1154 i386_operand_type temp
= overlap
;
1156 temp
.bitfield
.jumpabsolute
= 0;
1157 if (UINTS_ALL_ZERO (temp
))
1160 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1161 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1164 /* If given types r0 and r1 are registers they must be of the same type
1165 unless the expected operand type register overlap is null.
1166 Note that Acc in a template matches every size of reg. */
1169 operand_type_register_match (i386_operand_type m0
,
1170 i386_operand_type g0
,
1171 i386_operand_type t0
,
1172 i386_operand_type m1
,
1173 i386_operand_type g1
,
1174 i386_operand_type t1
)
1176 if (!operand_type_check (g0
, reg
))
1179 if (!operand_type_check (g1
, reg
))
1182 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1183 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1184 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1185 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1188 if (m0
.bitfield
.acc
)
1190 t0
.bitfield
.reg8
= 1;
1191 t0
.bitfield
.reg16
= 1;
1192 t0
.bitfield
.reg32
= 1;
1193 t0
.bitfield
.reg64
= 1;
1196 if (m1
.bitfield
.acc
)
1198 t1
.bitfield
.reg8
= 1;
1199 t1
.bitfield
.reg16
= 1;
1200 t1
.bitfield
.reg32
= 1;
1201 t1
.bitfield
.reg64
= 1;
1204 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1205 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1206 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1207 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1210 static INLINE
unsigned int
1211 mode_from_disp_size (i386_operand_type t
)
1213 if (t
.bitfield
.disp8
)
1215 else if (t
.bitfield
.disp16
1216 || t
.bitfield
.disp32
1217 || t
.bitfield
.disp32s
)
1224 fits_in_signed_byte (offsetT num
)
1226 return (num
>= -128) && (num
<= 127);
1230 fits_in_unsigned_byte (offsetT num
)
1232 return (num
& 0xff) == num
;
1236 fits_in_unsigned_word (offsetT num
)
1238 return (num
& 0xffff) == num
;
1242 fits_in_signed_word (offsetT num
)
1244 return (-32768 <= num
) && (num
<= 32767);
1248 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1253 return (!(((offsetT
) -1 << 31) & num
)
1254 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1256 } /* fits_in_signed_long() */
1259 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1264 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1266 } /* fits_in_unsigned_long() */
1268 static i386_operand_type
1269 smallest_imm_type (offsetT num
)
1271 i386_operand_type t
;
1274 t
.bitfield
.imm64
= 1;
1276 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1278 /* This code is disabled on the 486 because all the Imm1 forms
1279 in the opcode table are slower on the i486. They're the
1280 versions with the implicitly specified single-position
1281 displacement, which has another syntax if you really want to
1283 t
.bitfield
.imm1
= 1;
1284 t
.bitfield
.imm8
= 1;
1285 t
.bitfield
.imm8s
= 1;
1286 t
.bitfield
.imm16
= 1;
1287 t
.bitfield
.imm32
= 1;
1288 t
.bitfield
.imm32s
= 1;
1290 else if (fits_in_signed_byte (num
))
1292 t
.bitfield
.imm8
= 1;
1293 t
.bitfield
.imm8s
= 1;
1294 t
.bitfield
.imm16
= 1;
1295 t
.bitfield
.imm32
= 1;
1296 t
.bitfield
.imm32s
= 1;
1298 else if (fits_in_unsigned_byte (num
))
1300 t
.bitfield
.imm8
= 1;
1301 t
.bitfield
.imm16
= 1;
1302 t
.bitfield
.imm32
= 1;
1303 t
.bitfield
.imm32s
= 1;
1305 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1307 t
.bitfield
.imm16
= 1;
1308 t
.bitfield
.imm32
= 1;
1309 t
.bitfield
.imm32s
= 1;
1311 else if (fits_in_signed_long (num
))
1313 t
.bitfield
.imm32
= 1;
1314 t
.bitfield
.imm32s
= 1;
1316 else if (fits_in_unsigned_long (num
))
1317 t
.bitfield
.imm32
= 1;
1323 offset_in_range (offsetT val
, int size
)
1329 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1330 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1331 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1333 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1338 /* If BFD64, sign extend val. */
1339 if (!use_rela_relocations
)
1340 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1341 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1343 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1345 char buf1
[40], buf2
[40];
1347 sprint_value (buf1
, val
);
1348 sprint_value (buf2
, val
& mask
);
1349 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1354 /* Returns 0 if attempting to add a prefix where one from the same
1355 class already exists, 1 if non rep/repne added, 2 if rep/repne
1358 add_prefix (unsigned int prefix
)
1363 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1364 && flag_code
== CODE_64BIT
)
1366 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1367 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1368 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1379 case CS_PREFIX_OPCODE
:
1380 case DS_PREFIX_OPCODE
:
1381 case ES_PREFIX_OPCODE
:
1382 case FS_PREFIX_OPCODE
:
1383 case GS_PREFIX_OPCODE
:
1384 case SS_PREFIX_OPCODE
:
1388 case REPNE_PREFIX_OPCODE
:
1389 case REPE_PREFIX_OPCODE
:
1392 case LOCK_PREFIX_OPCODE
:
1400 case ADDR_PREFIX_OPCODE
:
1404 case DATA_PREFIX_OPCODE
:
1408 if (i
.prefix
[q
] != 0)
1416 i
.prefix
[q
] |= prefix
;
1419 as_bad (_("same type of prefix used twice"));
1425 set_code_flag (int value
)
1428 if (flag_code
== CODE_64BIT
)
1430 cpu_arch_flags
.bitfield
.cpu64
= 1;
1431 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1435 cpu_arch_flags
.bitfield
.cpu64
= 0;
1436 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1438 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1440 as_bad (_("64bit mode not supported on this CPU."));
1442 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1444 as_bad (_("32bit mode not supported on this CPU."));
1446 stackop_size
= '\0';
1450 set_16bit_gcc_code_flag (int new_code_flag
)
1452 flag_code
= new_code_flag
;
1453 if (flag_code
!= CODE_16BIT
)
1455 cpu_arch_flags
.bitfield
.cpu64
= 0;
1456 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1457 stackop_size
= LONG_MNEM_SUFFIX
;
1461 set_intel_syntax (int syntax_flag
)
1463 /* Find out if register prefixing is specified. */
1464 int ask_naked_reg
= 0;
1467 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1469 char *string
= input_line_pointer
;
1470 int e
= get_symbol_end ();
1472 if (strcmp (string
, "prefix") == 0)
1474 else if (strcmp (string
, "noprefix") == 0)
1477 as_bad (_("bad argument to syntax directive."));
1478 *input_line_pointer
= e
;
1480 demand_empty_rest_of_line ();
1482 intel_syntax
= syntax_flag
;
1484 if (ask_naked_reg
== 0)
1485 allow_naked_reg
= (intel_syntax
1486 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1488 allow_naked_reg
= (ask_naked_reg
< 0);
1490 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1491 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1492 register_prefix
= allow_naked_reg
? "" : "%";
1496 set_intel_mnemonic (int mnemonic_flag
)
1498 /* Find out if register prefixing is specified. */
1499 int ask_naked_reg
= 0;
1502 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1504 char *string
= input_line_pointer
;
1505 int e
= get_symbol_end ();
1507 if (strcmp (string
, "prefix") == 0)
1509 else if (strcmp (string
, "noprefix") == 0)
1512 as_bad (_("bad argument to syntax directive."));
1513 *input_line_pointer
= e
;
1515 demand_empty_rest_of_line ();
1517 /* intel_mnemonic implies intel_syntax. */
1518 intel_mnemonic
= intel_syntax
= mnemonic_flag
;
1520 if (ask_naked_reg
== 0)
1521 allow_naked_reg
= (intel_mnemonic
1522 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1524 allow_naked_reg
= (ask_naked_reg
< 0);
1526 identifier_chars
['%'] = intel_mnemonic
&& allow_naked_reg
? '%' : 0;
1527 identifier_chars
['$'] = intel_mnemonic
? '$' : 0;
1528 register_prefix
= allow_naked_reg
? "" : "%";
1532 set_allow_index_reg (int flag
)
1534 allow_index_reg
= flag
;
1538 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1542 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1544 char *string
= input_line_pointer
;
1545 int e
= get_symbol_end ();
1547 i386_cpu_flags flags
;
1549 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1551 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1555 cpu_arch_name
= cpu_arch
[i
].name
;
1556 cpu_sub_arch_name
= NULL
;
1557 cpu_arch_flags
= cpu_arch
[i
].flags
;
1558 if (flag_code
== CODE_64BIT
)
1560 cpu_arch_flags
.bitfield
.cpu64
= 1;
1561 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1565 cpu_arch_flags
.bitfield
.cpu64
= 0;
1566 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1568 cpu_arch_isa
= cpu_arch
[i
].type
;
1569 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1570 if (!cpu_arch_tune_set
)
1572 cpu_arch_tune
= cpu_arch_isa
;
1573 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1578 flags
= cpu_flags_or (cpu_arch_flags
,
1580 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1582 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1583 cpu_arch_flags
= flags
;
1585 *input_line_pointer
= e
;
1586 demand_empty_rest_of_line ();
1590 if (i
>= ARRAY_SIZE (cpu_arch
))
1591 as_bad (_("no such architecture: `%s'"), string
);
1593 *input_line_pointer
= e
;
1596 as_bad (_("missing cpu architecture"));
1598 no_cond_jump_promotion
= 0;
1599 if (*input_line_pointer
== ','
1600 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1602 char *string
= ++input_line_pointer
;
1603 int e
= get_symbol_end ();
1605 if (strcmp (string
, "nojumps") == 0)
1606 no_cond_jump_promotion
= 1;
1607 else if (strcmp (string
, "jumps") == 0)
1610 as_bad (_("no such architecture modifier: `%s'"), string
);
1612 *input_line_pointer
= e
;
1615 demand_empty_rest_of_line ();
1621 if (!strcmp (default_arch
, "x86_64"))
1622 return bfd_mach_x86_64
;
1623 else if (!strcmp (default_arch
, "i386"))
1624 return bfd_mach_i386_i386
;
1626 as_fatal (_("Unknown architecture"));
1632 const char *hash_err
;
1634 /* Initialize op_hash hash table. */
1635 op_hash
= hash_new ();
1638 const template *optab
;
1639 templates
*core_optab
;
1641 /* Setup for loop. */
1643 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1644 core_optab
->start
= optab
;
1649 if (optab
->name
== NULL
1650 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1652 /* different name --> ship out current template list;
1653 add to hash table; & begin anew. */
1654 core_optab
->end
= optab
;
1655 hash_err
= hash_insert (op_hash
,
1660 as_fatal (_("Internal Error: Can't hash %s: %s"),
1664 if (optab
->name
== NULL
)
1666 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1667 core_optab
->start
= optab
;
1672 /* Initialize reg_hash hash table. */
1673 reg_hash
= hash_new ();
1675 const reg_entry
*regtab
;
1676 unsigned int regtab_size
= i386_regtab_size
;
1678 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1680 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1682 as_fatal (_("Internal Error: Can't hash %s: %s"),
1688 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1693 for (c
= 0; c
< 256; c
++)
1698 mnemonic_chars
[c
] = c
;
1699 register_chars
[c
] = c
;
1700 operand_chars
[c
] = c
;
1702 else if (ISLOWER (c
))
1704 mnemonic_chars
[c
] = c
;
1705 register_chars
[c
] = c
;
1706 operand_chars
[c
] = c
;
1708 else if (ISUPPER (c
))
1710 mnemonic_chars
[c
] = TOLOWER (c
);
1711 register_chars
[c
] = mnemonic_chars
[c
];
1712 operand_chars
[c
] = c
;
1715 if (ISALPHA (c
) || ISDIGIT (c
))
1716 identifier_chars
[c
] = c
;
1719 identifier_chars
[c
] = c
;
1720 operand_chars
[c
] = c
;
1725 identifier_chars
['@'] = '@';
1728 identifier_chars
['?'] = '?';
1729 operand_chars
['?'] = '?';
1731 digit_chars
['-'] = '-';
1732 mnemonic_chars
['-'] = '-';
1733 mnemonic_chars
['.'] = '.';
1734 identifier_chars
['_'] = '_';
1735 identifier_chars
['.'] = '.';
1737 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1738 operand_chars
[(unsigned char) *p
] = *p
;
1741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1744 record_alignment (text_section
, 2);
1745 record_alignment (data_section
, 2);
1746 record_alignment (bss_section
, 2);
1750 if (flag_code
== CODE_64BIT
)
1752 x86_dwarf2_return_column
= 16;
1753 x86_cie_data_alignment
= -8;
1757 x86_dwarf2_return_column
= 8;
1758 x86_cie_data_alignment
= -4;
1763 i386_print_statistics (FILE *file
)
1765 hash_print_statistics (file
, "i386 opcode", op_hash
);
1766 hash_print_statistics (file
, "i386 register", reg_hash
);
1771 /* Debugging routines for md_assemble. */
1772 static void pte (template *);
1773 static void pt (i386_operand_type
);
1774 static void pe (expressionS
*);
1775 static void ps (symbolS
*);
1778 pi (char *line
, i386_insn
*x
)
1782 fprintf (stdout
, "%s: template ", line
);
1784 fprintf (stdout
, " address: base %s index %s scale %x\n",
1785 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1786 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1787 x
->log2_scale_factor
);
1788 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1789 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1790 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1791 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1792 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1793 (x
->rex
& REX_W
) != 0,
1794 (x
->rex
& REX_R
) != 0,
1795 (x
->rex
& REX_X
) != 0,
1796 (x
->rex
& REX_B
) != 0);
1797 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
1798 x
->drex
.reg
, x
->drex
.rex
);
1799 for (i
= 0; i
< x
->operands
; i
++)
1801 fprintf (stdout
, " #%d: ", i
+ 1);
1803 fprintf (stdout
, "\n");
1804 if (x
->types
[i
].bitfield
.reg8
1805 || x
->types
[i
].bitfield
.reg16
1806 || x
->types
[i
].bitfield
.reg32
1807 || x
->types
[i
].bitfield
.reg64
1808 || x
->types
[i
].bitfield
.regmmx
1809 || x
->types
[i
].bitfield
.regxmm
1810 || x
->types
[i
].bitfield
.sreg2
1811 || x
->types
[i
].bitfield
.sreg3
1812 || x
->types
[i
].bitfield
.control
1813 || x
->types
[i
].bitfield
.debug
1814 || x
->types
[i
].bitfield
.test
)
1815 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1816 if (operand_type_check (x
->types
[i
], imm
))
1818 if (operand_type_check (x
->types
[i
], disp
))
1819 pe (x
->op
[i
].disps
);
1827 fprintf (stdout
, " %d operands ", t
->operands
);
1828 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1829 if (t
->extension_opcode
!= None
)
1830 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1831 if (t
->opcode_modifier
.d
)
1832 fprintf (stdout
, "D");
1833 if (t
->opcode_modifier
.w
)
1834 fprintf (stdout
, "W");
1835 fprintf (stdout
, "\n");
1836 for (i
= 0; i
< t
->operands
; i
++)
1838 fprintf (stdout
, " #%d type ", i
+ 1);
1839 pt (t
->operand_types
[i
]);
1840 fprintf (stdout
, "\n");
1847 fprintf (stdout
, " operation %d\n", e
->X_op
);
1848 fprintf (stdout
, " add_number %ld (%lx)\n",
1849 (long) e
->X_add_number
, (long) e
->X_add_number
);
1850 if (e
->X_add_symbol
)
1852 fprintf (stdout
, " add_symbol ");
1853 ps (e
->X_add_symbol
);
1854 fprintf (stdout
, "\n");
1858 fprintf (stdout
, " op_symbol ");
1859 ps (e
->X_op_symbol
);
1860 fprintf (stdout
, "\n");
1867 fprintf (stdout
, "%s type %s%s",
1869 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1870 segment_name (S_GET_SEGMENT (s
)));
1873 static struct type_name
1875 i386_operand_type mask
;
1878 const type_names
[] =
1880 { OPERAND_TYPE_REG8
, "r8" },
1881 { OPERAND_TYPE_REG16
, "r16" },
1882 { OPERAND_TYPE_REG32
, "r32" },
1883 { OPERAND_TYPE_REG64
, "r64" },
1884 { OPERAND_TYPE_IMM8
, "i8" },
1885 { OPERAND_TYPE_IMM8
, "i8s" },
1886 { OPERAND_TYPE_IMM16
, "i16" },
1887 { OPERAND_TYPE_IMM32
, "i32" },
1888 { OPERAND_TYPE_IMM32S
, "i32s" },
1889 { OPERAND_TYPE_IMM64
, "i64" },
1890 { OPERAND_TYPE_IMM1
, "i1" },
1891 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1892 { OPERAND_TYPE_DISP8
, "d8" },
1893 { OPERAND_TYPE_DISP16
, "d16" },
1894 { OPERAND_TYPE_DISP32
, "d32" },
1895 { OPERAND_TYPE_DISP32S
, "d32s" },
1896 { OPERAND_TYPE_DISP64
, "d64" },
1897 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1898 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1899 { OPERAND_TYPE_CONTROL
, "control reg" },
1900 { OPERAND_TYPE_TEST
, "test reg" },
1901 { OPERAND_TYPE_DEBUG
, "debug reg" },
1902 { OPERAND_TYPE_FLOATREG
, "FReg" },
1903 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1904 { OPERAND_TYPE_SREG2
, "SReg2" },
1905 { OPERAND_TYPE_SREG3
, "SReg3" },
1906 { OPERAND_TYPE_ACC
, "Acc" },
1907 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1908 { OPERAND_TYPE_REGMMX
, "rMMX" },
1909 { OPERAND_TYPE_REGXMM
, "rXMM" },
1910 { OPERAND_TYPE_ESSEG
, "es" },
1914 pt (i386_operand_type t
)
1917 i386_operand_type a
;
1919 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1921 a
= operand_type_and (t
, type_names
[j
].mask
);
1922 if (!UINTS_ALL_ZERO (a
))
1923 fprintf (stdout
, "%s, ", type_names
[j
].name
);
1928 #endif /* DEBUG386 */
1930 static bfd_reloc_code_real_type
1931 reloc (unsigned int size
,
1934 bfd_reloc_code_real_type other
)
1936 if (other
!= NO_RELOC
)
1938 reloc_howto_type
*reloc
;
1943 case BFD_RELOC_X86_64_GOT32
:
1944 return BFD_RELOC_X86_64_GOT64
;
1946 case BFD_RELOC_X86_64_PLTOFF64
:
1947 return BFD_RELOC_X86_64_PLTOFF64
;
1949 case BFD_RELOC_X86_64_GOTPC32
:
1950 other
= BFD_RELOC_X86_64_GOTPC64
;
1952 case BFD_RELOC_X86_64_GOTPCREL
:
1953 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1955 case BFD_RELOC_X86_64_TPOFF32
:
1956 other
= BFD_RELOC_X86_64_TPOFF64
;
1958 case BFD_RELOC_X86_64_DTPOFF32
:
1959 other
= BFD_RELOC_X86_64_DTPOFF64
;
1965 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1966 if (size
== 4 && flag_code
!= CODE_64BIT
)
1969 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1971 as_bad (_("unknown relocation (%u)"), other
);
1972 else if (size
!= bfd_get_reloc_size (reloc
))
1973 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1974 bfd_get_reloc_size (reloc
),
1976 else if (pcrel
&& !reloc
->pc_relative
)
1977 as_bad (_("non-pc-relative relocation for pc-relative field"));
1978 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1980 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1982 as_bad (_("relocated field and relocation type differ in signedness"));
1991 as_bad (_("there are no unsigned pc-relative relocations"));
1994 case 1: return BFD_RELOC_8_PCREL
;
1995 case 2: return BFD_RELOC_16_PCREL
;
1996 case 4: return BFD_RELOC_32_PCREL
;
1997 case 8: return BFD_RELOC_64_PCREL
;
1999 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2006 case 4: return BFD_RELOC_X86_64_32S
;
2011 case 1: return BFD_RELOC_8
;
2012 case 2: return BFD_RELOC_16
;
2013 case 4: return BFD_RELOC_32
;
2014 case 8: return BFD_RELOC_64
;
2016 as_bad (_("cannot do %s %u byte relocation"),
2017 sign
> 0 ? "signed" : "unsigned", size
);
2021 return BFD_RELOC_NONE
;
2024 /* Here we decide which fixups can be adjusted to make them relative to
2025 the beginning of the section instead of the symbol. Basically we need
2026 to make sure that the dynamic relocations are done correctly, so in
2027 some cases we force the original symbol to be used. */
2030 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2036 /* Don't adjust pc-relative references to merge sections in 64-bit
2038 if (use_rela_relocations
2039 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2043 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2044 and changed later by validate_fix. */
2045 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2046 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2049 /* adjust_reloc_syms doesn't know about the GOT. */
2050 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2051 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2052 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2053 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2054 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2055 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2056 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2057 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2058 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2059 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2060 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2061 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2062 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2063 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2064 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2065 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2066 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2067 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2068 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2069 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2070 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2071 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2072 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2073 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2074 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2075 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2076 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2077 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2084 intel_float_operand (const char *mnemonic
)
2086 /* Note that the value returned is meaningful only for opcodes with (memory)
2087 operands, hence the code here is free to improperly handle opcodes that
2088 have no operands (for better performance and smaller code). */
2090 if (mnemonic
[0] != 'f')
2091 return 0; /* non-math */
2093 switch (mnemonic
[1])
2095 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2096 the fs segment override prefix not currently handled because no
2097 call path can make opcodes without operands get here */
2099 return 2 /* integer op */;
2101 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2102 return 3; /* fldcw/fldenv */
2105 if (mnemonic
[2] != 'o' /* fnop */)
2106 return 3; /* non-waiting control op */
2109 if (mnemonic
[2] == 's')
2110 return 3; /* frstor/frstpm */
2113 if (mnemonic
[2] == 'a')
2114 return 3; /* fsave */
2115 if (mnemonic
[2] == 't')
2117 switch (mnemonic
[3])
2119 case 'c': /* fstcw */
2120 case 'd': /* fstdw */
2121 case 'e': /* fstenv */
2122 case 's': /* fsts[gw] */
2128 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2129 return 0; /* fxsave/fxrstor are not really math ops */
2136 /* This is the guts of the machine-dependent assembler. LINE points to a
2137 machine dependent instruction. This function is supposed to emit
2138 the frags/bytes it assembles to. */
2145 char mnemonic
[MAX_MNEM_SIZE
];
2147 /* Initialize globals. */
2148 memset (&i
, '\0', sizeof (i
));
2149 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2150 i
.reloc
[j
] = NO_RELOC
;
2151 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2152 memset (im_expressions
, '\0', sizeof (im_expressions
));
2153 save_stack_p
= save_stack
;
2155 /* First parse an instruction mnemonic & call i386_operand for the operands.
2156 We assume that the scrubber has arranged it so that line[0] is the valid
2157 start of a (possibly prefixed) mnemonic. */
2159 line
= parse_insn (line
, mnemonic
);
2163 line
= parse_operands (line
, mnemonic
);
2167 /* Now we've parsed the mnemonic into a set of templates, and have the
2168 operands at hand. */
2170 /* All intel opcodes have reversed operands except for "bound" and
2171 "enter". We also don't reverse intersegment "jmp" and "call"
2172 instructions with 2 immediate operands so that the immediate segment
2173 precedes the offset, as it does when in AT&T mode. */
2176 && (strcmp (mnemonic
, "bound") != 0)
2177 && (strcmp (mnemonic
, "invlpga") != 0)
2178 && !(operand_type_check (i
.types
[0], imm
)
2179 && operand_type_check (i
.types
[1], imm
)))
2182 /* The order of the immediates should be reversed
2183 for 2 immediates extrq and insertq instructions */
2184 if (i
.imm_operands
== 2
2185 && (strcmp (mnemonic
, "extrq") == 0
2186 || strcmp (mnemonic
, "insertq") == 0))
2187 swap_2_operands (0, 1);
2192 /* Don't optimize displacement for movabs since it only takes 64bit
2195 && (flag_code
!= CODE_64BIT
2196 || strcmp (mnemonic
, "movabs") != 0))
2199 /* Next, we find a template that matches the given insn,
2200 making sure the overlap of the given operands types is consistent
2201 with the template operand types. */
2203 if (!match_template ())
2208 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2210 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
2211 i
.tm
.base_opcode
^= Opcode_FloatR
;
2213 /* Zap movzx and movsx suffix. The suffix may have been set from
2214 "word ptr" or "byte ptr" on the source operand, but we'll use
2215 the suffix later to choose the destination register. */
2216 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2218 if (i
.reg_operands
< 2
2220 && (!i
.tm
.opcode_modifier
.no_bsuf
2221 || !i
.tm
.opcode_modifier
.no_wsuf
2222 || !i
.tm
.opcode_modifier
.no_lsuf
2223 || !i
.tm
.opcode_modifier
.no_ssuf
2224 || !i
.tm
.opcode_modifier
.no_ldsuf
2225 || !i
.tm
.opcode_modifier
.no_qsuf
))
2226 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2232 if (i
.tm
.opcode_modifier
.fwait
)
2233 if (!add_prefix (FWAIT_OPCODE
))
2236 /* Check string instruction segment overrides. */
2237 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2239 if (!check_string ())
2243 if (!process_suffix ())
2246 /* Make still unresolved immediate matches conform to size of immediate
2247 given in i.suffix. */
2248 if (!finalize_imm ())
2251 if (i
.types
[0].bitfield
.imm1
)
2252 i
.imm_operands
= 0; /* kludge for shift insns. */
2254 for (j
= 0; j
< 3; j
++)
2255 if (i
.types
[j
].bitfield
.inoutportreg
2256 || i
.types
[j
].bitfield
.shiftcount
2257 || i
.types
[j
].bitfield
.acc
2258 || i
.types
[j
].bitfield
.floatacc
)
2261 if (i
.tm
.opcode_modifier
.immext
)
2265 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2267 /* Streaming SIMD extensions 3 Instructions have the fixed
2268 operands with an opcode suffix which is coded in the same
2269 place as an 8-bit immediate field would be. Here we check
2270 those operands and remove them afterwards. */
2273 for (x
= 0; x
< i
.operands
; x
++)
2274 if (i
.op
[x
].regs
->reg_num
!= x
)
2275 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2277 i
.op
[x
].regs
->reg_name
,
2283 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2284 opcode suffix which is coded in the same place as an 8-bit
2285 immediate field would be. Here we fake an 8-bit immediate
2286 operand from the opcode suffix stored in tm.extension_opcode.
2287 SSE5 also uses this encoding, for some of its 3 argument
2290 assert (i
.imm_operands
== 0
2292 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2293 && i
.operands
<= 3)));
2295 exp
= &im_expressions
[i
.imm_operands
++];
2296 i
.op
[i
.operands
].imms
= exp
;
2297 UINTS_CLEAR (i
.types
[i
.operands
]);
2298 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2300 exp
->X_op
= O_constant
;
2301 exp
->X_add_number
= i
.tm
.extension_opcode
;
2302 i
.tm
.extension_opcode
= None
;
2305 /* For insns with operands there are more diddles to do to the opcode. */
2308 if (!process_operands ())
2311 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2313 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2314 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2317 /* Handle conversion of 'int $3' --> special int3 insn. */
2318 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2320 i
.tm
.base_opcode
= INT3_OPCODE
;
2324 if ((i
.tm
.opcode_modifier
.jump
2325 || i
.tm
.opcode_modifier
.jumpbyte
2326 || i
.tm
.opcode_modifier
.jumpdword
)
2327 && i
.op
[0].disps
->X_op
== O_constant
)
2329 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2330 the absolute address given by the constant. Since ix86 jumps and
2331 calls are pc relative, we need to generate a reloc. */
2332 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2333 i
.op
[0].disps
->X_op
= O_symbol
;
2336 if (i
.tm
.opcode_modifier
.rex64
)
2339 /* For 8 bit registers we need an empty rex prefix. Also if the
2340 instruction already has a prefix, we need to convert old
2341 registers to new ones. */
2343 if ((i
.types
[0].bitfield
.reg8
2344 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2345 || (i
.types
[1].bitfield
.reg8
2346 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2347 || ((i
.types
[0].bitfield
.reg8
2348 || i
.types
[1].bitfield
.reg8
)
2353 i
.rex
|= REX_OPCODE
;
2354 for (x
= 0; x
< 2; x
++)
2356 /* Look for 8 bit operand that uses old registers. */
2357 if (i
.types
[x
].bitfield
.reg8
2358 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2360 /* In case it is "hi" register, give up. */
2361 if (i
.op
[x
].regs
->reg_num
> 3)
2362 as_bad (_("can't encode register '%s%s' in an "
2363 "instruction requiring REX prefix."),
2364 register_prefix
, i
.op
[x
].regs
->reg_name
);
2366 /* Otherwise it is equivalent to the extended register.
2367 Since the encoding doesn't change this is merely
2368 cosmetic cleanup for debug output. */
2370 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2375 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2377 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2382 else if (i
.rex
!= 0)
2383 add_prefix (REX_OPCODE
| i
.rex
);
2385 /* We are ready to output the insn. */
2390 parse_insn (char *line
, char *mnemonic
)
2393 char *token_start
= l
;
2398 /* Non-zero if we found a prefix only acceptable with string insns. */
2399 const char *expecting_string_instruction
= NULL
;
2404 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2407 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2409 as_bad (_("no such instruction: `%s'"), token_start
);
2414 if (!is_space_char (*l
)
2415 && *l
!= END_OF_INSN
2417 || (*l
!= PREFIX_SEPARATOR
2420 as_bad (_("invalid character %s in mnemonic"),
2421 output_invalid (*l
));
2424 if (token_start
== l
)
2426 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2427 as_bad (_("expecting prefix; got nothing"));
2429 as_bad (_("expecting mnemonic; got nothing"));
2433 /* Look up instruction (or prefix) via hash table. */
2434 current_templates
= hash_find (op_hash
, mnemonic
);
2436 if (*l
!= END_OF_INSN
2437 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2438 && current_templates
2439 && current_templates
->start
->opcode_modifier
.isprefix
)
2441 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2443 as_bad ((flag_code
!= CODE_64BIT
2444 ? _("`%s' is only supported in 64-bit mode")
2445 : _("`%s' is not supported in 64-bit mode")),
2446 current_templates
->start
->name
);
2449 /* If we are in 16-bit mode, do not allow addr16 or data16.
2450 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2451 if ((current_templates
->start
->opcode_modifier
.size16
2452 || current_templates
->start
->opcode_modifier
.size32
)
2453 && flag_code
!= CODE_64BIT
2454 && (current_templates
->start
->opcode_modifier
.size32
2455 ^ (flag_code
== CODE_16BIT
)))
2457 as_bad (_("redundant %s prefix"),
2458 current_templates
->start
->name
);
2461 /* Add prefix, checking for repeated prefixes. */
2462 switch (add_prefix (current_templates
->start
->base_opcode
))
2467 expecting_string_instruction
= current_templates
->start
->name
;
2470 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2477 if (!current_templates
)
2479 /* See if we can get a match by trimming off a suffix. */
2482 case WORD_MNEM_SUFFIX
:
2483 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2484 i
.suffix
= SHORT_MNEM_SUFFIX
;
2486 case BYTE_MNEM_SUFFIX
:
2487 case QWORD_MNEM_SUFFIX
:
2488 i
.suffix
= mnem_p
[-1];
2490 current_templates
= hash_find (op_hash
, mnemonic
);
2492 case SHORT_MNEM_SUFFIX
:
2493 case LONG_MNEM_SUFFIX
:
2496 i
.suffix
= mnem_p
[-1];
2498 current_templates
= hash_find (op_hash
, mnemonic
);
2506 if (intel_float_operand (mnemonic
) == 1)
2507 i
.suffix
= SHORT_MNEM_SUFFIX
;
2509 i
.suffix
= LONG_MNEM_SUFFIX
;
2511 current_templates
= hash_find (op_hash
, mnemonic
);
2515 if (!current_templates
)
2517 as_bad (_("no such instruction: `%s'"), token_start
);
2522 if (current_templates
->start
->opcode_modifier
.jump
2523 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2525 /* Check for a branch hint. We allow ",pt" and ",pn" for
2526 predict taken and predict not taken respectively.
2527 I'm not sure that branch hints actually do anything on loop
2528 and jcxz insns (JumpByte) for current Pentium4 chips. They
2529 may work in the future and it doesn't hurt to accept them
2531 if (l
[0] == ',' && l
[1] == 'p')
2535 if (!add_prefix (DS_PREFIX_OPCODE
))
2539 else if (l
[2] == 'n')
2541 if (!add_prefix (CS_PREFIX_OPCODE
))
2547 /* Any other comma loses. */
2550 as_bad (_("invalid character %s in mnemonic"),
2551 output_invalid (*l
));
2555 /* Check if instruction is supported on specified architecture. */
2557 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2559 supported
|= cpu_flags_match (t
->cpu_flags
);
2564 if (!(supported
& 2))
2566 as_bad (flag_code
== CODE_64BIT
2567 ? _("`%s' is not supported in 64-bit mode")
2568 : _("`%s' is only supported in 64-bit mode"),
2569 current_templates
->start
->name
);
2572 if (!(supported
& 1))
2574 as_bad (_("`%s' is not supported on `%s%s'"),
2575 current_templates
->start
->name
, cpu_arch_name
,
2576 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2581 if (!cpu_arch_flags
.bitfield
.cpui386
2582 && (flag_code
!= CODE_16BIT
))
2584 as_warn (_("use .code16 to ensure correct addressing mode"));
2587 /* Check for rep/repne without a string instruction. */
2588 if (expecting_string_instruction
)
2590 static templates override
;
2592 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2593 if (t
->opcode_modifier
.isstring
)
2595 if (t
>= current_templates
->end
)
2597 as_bad (_("expecting string instruction after `%s'"),
2598 expecting_string_instruction
);
2601 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2602 if (!t
->opcode_modifier
.isstring
)
2605 current_templates
= &override
;
2612 parse_operands (char *l
, const char *mnemonic
)
2616 /* 1 if operand is pending after ','. */
2617 unsigned int expecting_operand
= 0;
2619 /* Non-zero if operand parens not balanced. */
2620 unsigned int paren_not_balanced
;
2622 while (*l
!= END_OF_INSN
)
2624 /* Skip optional white space before operand. */
2625 if (is_space_char (*l
))
2627 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2629 as_bad (_("invalid character %s before operand %d"),
2630 output_invalid (*l
),
2634 token_start
= l
; /* after white space */
2635 paren_not_balanced
= 0;
2636 while (paren_not_balanced
|| *l
!= ',')
2638 if (*l
== END_OF_INSN
)
2640 if (paren_not_balanced
)
2643 as_bad (_("unbalanced parenthesis in operand %d."),
2646 as_bad (_("unbalanced brackets in operand %d."),
2651 break; /* we are done */
2653 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2655 as_bad (_("invalid character %s in operand %d"),
2656 output_invalid (*l
),
2663 ++paren_not_balanced
;
2665 --paren_not_balanced
;
2670 ++paren_not_balanced
;
2672 --paren_not_balanced
;
2676 if (l
!= token_start
)
2677 { /* Yes, we've read in another operand. */
2678 unsigned int operand_ok
;
2679 this_operand
= i
.operands
++;
2680 if (i
.operands
> MAX_OPERANDS
)
2682 as_bad (_("spurious operands; (%d operands/instruction max)"),
2686 /* Now parse operand adding info to 'i' as we go along. */
2687 END_STRING_AND_SAVE (l
);
2691 i386_intel_operand (token_start
,
2692 intel_float_operand (mnemonic
));
2694 operand_ok
= i386_operand (token_start
);
2696 RESTORE_END_STRING (l
);
2702 if (expecting_operand
)
2704 expecting_operand_after_comma
:
2705 as_bad (_("expecting operand after ','; got nothing"));
2710 as_bad (_("expecting operand before ','; got nothing"));
2715 /* Now *l must be either ',' or END_OF_INSN. */
2718 if (*++l
== END_OF_INSN
)
2720 /* Just skip it, if it's \n complain. */
2721 goto expecting_operand_after_comma
;
2723 expecting_operand
= 1;
2730 swap_2_operands (int xchg1
, int xchg2
)
2732 union i386_op temp_op
;
2733 i386_operand_type temp_type
;
2734 enum bfd_reloc_code_real temp_reloc
;
2736 temp_type
= i
.types
[xchg2
];
2737 i
.types
[xchg2
] = i
.types
[xchg1
];
2738 i
.types
[xchg1
] = temp_type
;
2739 temp_op
= i
.op
[xchg2
];
2740 i
.op
[xchg2
] = i
.op
[xchg1
];
2741 i
.op
[xchg1
] = temp_op
;
2742 temp_reloc
= i
.reloc
[xchg2
];
2743 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2744 i
.reloc
[xchg1
] = temp_reloc
;
2748 swap_operands (void)
2753 swap_2_operands (1, i
.operands
- 2);
2756 swap_2_operands (0, i
.operands
- 1);
2762 if (i
.mem_operands
== 2)
2764 const seg_entry
*temp_seg
;
2765 temp_seg
= i
.seg
[0];
2766 i
.seg
[0] = i
.seg
[1];
2767 i
.seg
[1] = temp_seg
;
2771 /* Try to ensure constant immediates are represented in the smallest
2776 char guess_suffix
= 0;
2780 guess_suffix
= i
.suffix
;
2781 else if (i
.reg_operands
)
2783 /* Figure out a suffix from the last register operand specified.
2784 We can't do this properly yet, ie. excluding InOutPortReg,
2785 but the following works for instructions with immediates.
2786 In any case, we can't set i.suffix yet. */
2787 for (op
= i
.operands
; --op
>= 0;)
2788 if (i
.types
[op
].bitfield
.reg8
)
2790 guess_suffix
= BYTE_MNEM_SUFFIX
;
2793 else if (i
.types
[op
].bitfield
.reg16
)
2795 guess_suffix
= WORD_MNEM_SUFFIX
;
2798 else if (i
.types
[op
].bitfield
.reg32
)
2800 guess_suffix
= LONG_MNEM_SUFFIX
;
2803 else if (i
.types
[op
].bitfield
.reg64
)
2805 guess_suffix
= QWORD_MNEM_SUFFIX
;
2809 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2810 guess_suffix
= WORD_MNEM_SUFFIX
;
2812 for (op
= i
.operands
; --op
>= 0;)
2813 if (operand_type_check (i
.types
[op
], imm
))
2815 switch (i
.op
[op
].imms
->X_op
)
2818 /* If a suffix is given, this operand may be shortened. */
2819 switch (guess_suffix
)
2821 case LONG_MNEM_SUFFIX
:
2822 i
.types
[op
].bitfield
.imm32
= 1;
2823 i
.types
[op
].bitfield
.imm64
= 1;
2825 case WORD_MNEM_SUFFIX
:
2826 i
.types
[op
].bitfield
.imm16
= 1;
2827 i
.types
[op
].bitfield
.imm32
= 1;
2828 i
.types
[op
].bitfield
.imm32s
= 1;
2829 i
.types
[op
].bitfield
.imm64
= 1;
2831 case BYTE_MNEM_SUFFIX
:
2832 i
.types
[op
].bitfield
.imm8
= 1;
2833 i
.types
[op
].bitfield
.imm8s
= 1;
2834 i
.types
[op
].bitfield
.imm16
= 1;
2835 i
.types
[op
].bitfield
.imm32
= 1;
2836 i
.types
[op
].bitfield
.imm32s
= 1;
2837 i
.types
[op
].bitfield
.imm64
= 1;
2841 /* If this operand is at most 16 bits, convert it
2842 to a signed 16 bit number before trying to see
2843 whether it will fit in an even smaller size.
2844 This allows a 16-bit operand such as $0xffe0 to
2845 be recognised as within Imm8S range. */
2846 if ((i
.types
[op
].bitfield
.imm16
)
2847 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2849 i
.op
[op
].imms
->X_add_number
=
2850 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2852 if ((i
.types
[op
].bitfield
.imm32
)
2853 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2856 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2857 ^ ((offsetT
) 1 << 31))
2858 - ((offsetT
) 1 << 31));
2861 = operand_type_or (i
.types
[op
],
2862 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2864 /* We must avoid matching of Imm32 templates when 64bit
2865 only immediate is available. */
2866 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2867 i
.types
[op
].bitfield
.imm32
= 0;
2874 /* Symbols and expressions. */
2876 /* Convert symbolic operand to proper sizes for matching, but don't
2877 prevent matching a set of insns that only supports sizes other
2878 than those matching the insn suffix. */
2880 i386_operand_type mask
, allowed
;
2884 UINTS_CLEAR (allowed
);
2886 for (t
= current_templates
->start
;
2887 t
< current_templates
->end
;
2889 allowed
= operand_type_or (allowed
,
2890 t
->operand_types
[op
]);
2891 switch (guess_suffix
)
2893 case QWORD_MNEM_SUFFIX
:
2894 mask
.bitfield
.imm64
= 1;
2895 mask
.bitfield
.imm32s
= 1;
2897 case LONG_MNEM_SUFFIX
:
2898 mask
.bitfield
.imm32
= 1;
2900 case WORD_MNEM_SUFFIX
:
2901 mask
.bitfield
.imm16
= 1;
2903 case BYTE_MNEM_SUFFIX
:
2904 mask
.bitfield
.imm8
= 1;
2909 allowed
= operand_type_and (mask
, allowed
);
2910 if (!UINTS_ALL_ZERO (allowed
))
2911 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2918 /* Try to use the smallest displacement type too. */
2920 optimize_disp (void)
2924 for (op
= i
.operands
; --op
>= 0;)
2925 if (operand_type_check (i
.types
[op
], disp
))
2927 if (i
.op
[op
].disps
->X_op
== O_constant
)
2929 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2931 if (i
.types
[op
].bitfield
.disp16
2932 && (disp
& ~(offsetT
) 0xffff) == 0)
2934 /* If this operand is at most 16 bits, convert
2935 to a signed 16 bit number and don't use 64bit
2937 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2938 i
.types
[op
].bitfield
.disp64
= 0;
2940 if (i
.types
[op
].bitfield
.disp32
2941 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2943 /* If this operand is at most 32 bits, convert
2944 to a signed 32 bit number and don't use 64bit
2946 disp
&= (((offsetT
) 2 << 31) - 1);
2947 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2948 i
.types
[op
].bitfield
.disp64
= 0;
2950 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
2952 i
.types
[op
].bitfield
.disp8
= 0;
2953 i
.types
[op
].bitfield
.disp16
= 0;
2954 i
.types
[op
].bitfield
.disp32
= 0;
2955 i
.types
[op
].bitfield
.disp32s
= 0;
2956 i
.types
[op
].bitfield
.disp64
= 0;
2960 else if (flag_code
== CODE_64BIT
)
2962 if (fits_in_signed_long (disp
))
2964 i
.types
[op
].bitfield
.disp64
= 0;
2965 i
.types
[op
].bitfield
.disp32s
= 1;
2967 if (fits_in_unsigned_long (disp
))
2968 i
.types
[op
].bitfield
.disp32
= 1;
2970 if ((i
.types
[op
].bitfield
.disp32
2971 || i
.types
[op
].bitfield
.disp32s
2972 || i
.types
[op
].bitfield
.disp16
)
2973 && fits_in_signed_byte (disp
))
2974 i
.types
[op
].bitfield
.disp8
= 1;
2976 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2977 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2979 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2980 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2981 i
.types
[op
].bitfield
.disp8
= 0;
2982 i
.types
[op
].bitfield
.disp16
= 0;
2983 i
.types
[op
].bitfield
.disp32
= 0;
2984 i
.types
[op
].bitfield
.disp32s
= 0;
2985 i
.types
[op
].bitfield
.disp64
= 0;
2988 /* We only support 64bit displacement on constants. */
2989 i
.types
[op
].bitfield
.disp64
= 0;
2994 match_template (void)
2996 /* Points to template once we've found it. */
2998 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
2999 unsigned int found_reverse_match
;
3000 i386_opcode_modifier suffix_check
;
3001 i386_operand_type operand_types
[MAX_OPERANDS
];
3002 int addr_prefix_disp
;
3004 unsigned int found_cpu_match
;
3006 #if MAX_OPERANDS != 4
3007 # error "MAX_OPERANDS must be 4."
3010 found_reverse_match
= 0;
3011 addr_prefix_disp
= -1;
3013 memset (&suffix_check
, 0, sizeof (suffix_check
));
3014 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3015 suffix_check
.no_bsuf
= 1;
3016 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3017 suffix_check
.no_wsuf
= 1;
3018 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3019 suffix_check
.no_ssuf
= 1;
3020 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3021 suffix_check
.no_lsuf
= 1;
3022 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3023 suffix_check
.no_qsuf
= 1;
3024 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3025 suffix_check
.no_ldsuf
= 1;
3026 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
)
3027 suffix_check
.xmmword
= 1;
3029 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3031 addr_prefix_disp
= -1;
3033 /* Must have right number of operands. */
3034 if (i
.operands
!= t
->operands
)
3037 /* Check AT&T mnemonic and old gcc support. */
3038 if (t
->opcode_modifier
.attmnemonic
3041 && t
->opcode_modifier
.oldgcc
)))
3044 /* Check Intel mnemonic. */
3045 if (!intel_mnemonic
&& t
->opcode_modifier
.intelmnemonic
)
3048 /* Check the suffix, except for some instructions in intel mode. */
3049 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3050 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3051 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3052 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3053 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3054 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3055 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3058 /* Check the memory size in Intel mode when it is provided if
3062 && t
->opcode_modifier
.checksize
3063 && (!t
->opcode_modifier
.byte
|| !suffix_check
.no_bsuf
)
3064 && (!t
->opcode_modifier
.word
|| !suffix_check
.no_wsuf
)
3065 && (!t
->opcode_modifier
.dword
|| !suffix_check
.no_lsuf
)
3066 && (!t
->opcode_modifier
.qword
|| !suffix_check
.no_qsuf
)
3067 && (!t
->opcode_modifier
.xmmword
|| !suffix_check
.xmmword
))
3070 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3071 operand_types
[j
] = t
->operand_types
[j
];
3073 /* In general, don't allow 64-bit operands in 32-bit mode. */
3074 if (i
.suffix
== QWORD_MNEM_SUFFIX
3075 && flag_code
!= CODE_64BIT
3077 ? (!t
->opcode_modifier
.ignoresize
3078 && !intel_float_operand (t
->name
))
3079 : intel_float_operand (t
->name
) != 2)
3080 && ((!operand_types
[0].bitfield
.regmmx
3081 && !operand_types
[0].bitfield
.regxmm
)
3082 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3083 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3084 && (t
->base_opcode
!= 0x0fc7
3085 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3088 /* Do not verify operands when there are none. */
3091 found_cpu_match
= cpu_flags_match (t
->cpu_flags
) == 3;
3094 if (!found_cpu_match
)
3096 /* We've found a match; break out of loop. */
3101 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3102 into Disp32/Disp16/Disp32 operand. */
3103 if (i
.prefix
[ADDR_PREFIX
] != 0)
3105 /* There should be only one Disp operand. */
3109 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3111 if (operand_types
[j
].bitfield
.disp16
)
3113 addr_prefix_disp
= j
;
3114 operand_types
[j
].bitfield
.disp32
= 1;
3115 operand_types
[j
].bitfield
.disp16
= 0;
3121 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3123 if (operand_types
[j
].bitfield
.disp32
)
3125 addr_prefix_disp
= j
;
3126 operand_types
[j
].bitfield
.disp32
= 0;
3127 operand_types
[j
].bitfield
.disp16
= 1;
3133 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3135 if (operand_types
[j
].bitfield
.disp64
)
3137 addr_prefix_disp
= j
;
3138 operand_types
[j
].bitfield
.disp64
= 0;
3139 operand_types
[j
].bitfield
.disp32
= 1;
3147 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3148 switch (t
->operands
)
3151 if (!operand_type_match (overlap0
, i
.types
[0]))
3155 /* xchg %eax, %eax is a special case. It is an aliase for nop
3156 only in 32bit mode and we can use opcode 0x90. In 64bit
3157 mode, we can't use 0x90 for xchg %eax, %eax since it should
3158 zero-extend %eax to %rax. */
3159 if (flag_code
== CODE_64BIT
3160 && t
->base_opcode
== 0x90
3161 && UINTS_EQUAL (i
.types
[0], acc32
)
3162 && UINTS_EQUAL (i
.types
[1], acc32
))
3166 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3167 if (!operand_type_match (overlap0
, i
.types
[0])
3168 || !operand_type_match (overlap1
, i
.types
[1])
3169 /* monitor in SSE3 is a very special case. The first
3170 register and the second register may have different
3171 sizes. The same applies to crc32 in SSE4.2. It is
3172 also true for invlpga, vmload, vmrun and vmsave in
3174 || !((t
->base_opcode
== 0x0f01
3175 && (t
->extension_opcode
== 0xc8
3176 || t
->extension_opcode
== 0xd8
3177 || t
->extension_opcode
== 0xda
3178 || t
->extension_opcode
== 0xdb
3179 || t
->extension_opcode
== 0xdf))
3180 || t
->base_opcode
== 0xf20f38f1
3181 || operand_type_register_match (overlap0
, i
.types
[0],
3183 overlap1
, i
.types
[1],
3186 /* Check if other direction is valid ... */
3187 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3190 /* Try reversing direction of operands. */
3191 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3192 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3193 if (!operand_type_match (overlap0
, i
.types
[0])
3194 || !operand_type_match (overlap1
, i
.types
[1])
3195 || !operand_type_register_match (overlap0
, i
.types
[0],
3197 overlap1
, i
.types
[1],
3200 /* Does not match either direction. */
3203 /* found_reverse_match holds which of D or FloatDR
3205 if (t
->opcode_modifier
.d
)
3206 found_reverse_match
= Opcode_D
;
3207 else if (t
->opcode_modifier
.floatd
)
3208 found_reverse_match
= Opcode_FloatD
;
3210 found_reverse_match
= 0;
3211 if (t
->opcode_modifier
.floatr
)
3212 found_reverse_match
|= Opcode_FloatR
;
3216 /* Found a forward 2 operand match here. */
3217 switch (t
->operands
)
3220 overlap3
= operand_type_and (i
.types
[3],
3223 overlap2
= operand_type_and (i
.types
[2],
3228 switch (t
->operands
)
3231 if (!operand_type_match (overlap3
, i
.types
[3])
3232 || !operand_type_register_match (overlap2
,
3240 /* Here we make use of the fact that there are no
3241 reverse match 3 operand instructions, and all 3
3242 operand instructions only need to be checked for
3243 register consistency between operands 2 and 3. */
3244 if (!operand_type_match (overlap2
, i
.types
[2])
3245 || !operand_type_register_match (overlap1
,
3255 /* Found either forward/reverse 2, 3 or 4 operand match here:
3256 slip through to break. */
3258 if (!found_cpu_match
)
3260 found_reverse_match
= 0;
3263 /* We've found a match; break out of loop. */
3267 if (t
== current_templates
->end
)
3269 /* We found no match. */
3270 as_bad (_("suffix or operands invalid for `%s'"),
3271 current_templates
->start
->name
);
3275 if (!quiet_warnings
)
3278 && (i
.types
[0].bitfield
.jumpabsolute
3279 != operand_types
[0].bitfield
.jumpabsolute
))
3281 as_warn (_("indirect %s without `*'"), t
->name
);
3284 if (t
->opcode_modifier
.isprefix
3285 && t
->opcode_modifier
.ignoresize
)
3287 /* Warn them that a data or address size prefix doesn't
3288 affect assembly of the next line of code. */
3289 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3293 /* Copy the template we found. */
3296 if (addr_prefix_disp
!= -1)
3297 i
.tm
.operand_types
[addr_prefix_disp
]
3298 = operand_types
[addr_prefix_disp
];
3300 if (found_reverse_match
)
3302 /* If we found a reverse match we must alter the opcode
3303 direction bit. found_reverse_match holds bits to change
3304 (different for int & float insns). */
3306 i
.tm
.base_opcode
^= found_reverse_match
;
3308 i
.tm
.operand_types
[0] = operand_types
[1];
3309 i
.tm
.operand_types
[1] = operand_types
[0];
3318 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3319 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3321 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3323 as_bad (_("`%s' operand %d must use `%%es' segment"),
3328 /* There's only ever one segment override allowed per instruction.
3329 This instruction possibly has a legal segment override on the
3330 second operand, so copy the segment to where non-string
3331 instructions store it, allowing common code. */
3332 i
.seg
[0] = i
.seg
[1];
3334 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3336 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3338 as_bad (_("`%s' operand %d must use `%%es' segment"),
3348 process_suffix (void)
3350 /* If matched instruction specifies an explicit instruction mnemonic
3352 if (i
.tm
.opcode_modifier
.size16
)
3353 i
.suffix
= WORD_MNEM_SUFFIX
;
3354 else if (i
.tm
.opcode_modifier
.size32
)
3355 i
.suffix
= LONG_MNEM_SUFFIX
;
3356 else if (i
.tm
.opcode_modifier
.size64
)
3357 i
.suffix
= QWORD_MNEM_SUFFIX
;
3358 else if (i
.reg_operands
)
3360 /* If there's no instruction mnemonic suffix we try to invent one
3361 based on register operands. */
3364 /* We take i.suffix from the last register operand specified,
3365 Destination register type is more significant than source
3366 register type. crc32 in SSE4.2 prefers source register
3368 if (i
.tm
.base_opcode
== 0xf20f38f1)
3370 if (i
.types
[0].bitfield
.reg16
)
3371 i
.suffix
= WORD_MNEM_SUFFIX
;
3372 else if (i
.types
[0].bitfield
.reg32
)
3373 i
.suffix
= LONG_MNEM_SUFFIX
;
3374 else if (i
.types
[0].bitfield
.reg64
)
3375 i
.suffix
= QWORD_MNEM_SUFFIX
;
3377 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3379 if (i
.types
[0].bitfield
.reg8
)
3380 i
.suffix
= BYTE_MNEM_SUFFIX
;
3387 if (i
.tm
.base_opcode
== 0xf20f38f1
3388 || i
.tm
.base_opcode
== 0xf20f38f0)
3390 /* We have to know the operand size for crc32. */
3391 as_bad (_("ambiguous memory operand size for `%s`"),
3396 for (op
= i
.operands
; --op
>= 0;)
3397 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3399 if (i
.types
[op
].bitfield
.reg8
)
3401 i
.suffix
= BYTE_MNEM_SUFFIX
;
3404 else if (i
.types
[op
].bitfield
.reg16
)
3406 i
.suffix
= WORD_MNEM_SUFFIX
;
3409 else if (i
.types
[op
].bitfield
.reg32
)
3411 i
.suffix
= LONG_MNEM_SUFFIX
;
3414 else if (i
.types
[op
].bitfield
.reg64
)
3416 i
.suffix
= QWORD_MNEM_SUFFIX
;
3422 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3424 if (!check_byte_reg ())
3427 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3429 if (!check_long_reg ())
3432 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3435 && i
.tm
.opcode_modifier
.ignoresize
3436 && i
.tm
.opcode_modifier
.no_qsuf
)
3438 else if (!check_qword_reg ())
3441 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3443 if (!check_word_reg ())
3446 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
)
3448 /* Skip if the instruction has x suffix. match_template
3449 should check if it is a valid suffix. */
3451 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3452 /* Do nothing if the instruction is going to ignore the prefix. */
3457 else if (i
.tm
.opcode_modifier
.defaultsize
3459 /* exclude fldenv/frstor/fsave/fstenv */
3460 && i
.tm
.opcode_modifier
.no_ssuf
)
3462 i
.suffix
= stackop_size
;
3464 else if (intel_syntax
3466 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3467 || i
.tm
.opcode_modifier
.jumpbyte
3468 || i
.tm
.opcode_modifier
.jumpintersegment
3469 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3470 && i
.tm
.extension_opcode
<= 3)))
3475 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3477 i
.suffix
= QWORD_MNEM_SUFFIX
;
3481 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3482 i
.suffix
= LONG_MNEM_SUFFIX
;
3485 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3486 i
.suffix
= WORD_MNEM_SUFFIX
;
3495 if (i
.tm
.opcode_modifier
.w
)
3497 as_bad (_("no instruction mnemonic suffix given and "
3498 "no register operands; can't size instruction"));
3504 unsigned int suffixes
;
3506 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3507 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3509 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3511 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
3513 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3515 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3518 /* There are more than suffix matches. */
3519 if (i
.tm
.opcode_modifier
.w
3520 || ((suffixes
& (suffixes
- 1))
3521 && !i
.tm
.opcode_modifier
.defaultsize
3522 && !i
.tm
.opcode_modifier
.ignoresize
))
3524 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3530 /* Change the opcode based on the operand size given by i.suffix;
3531 We don't need to change things for byte insns. */
3534 && i
.suffix
!= BYTE_MNEM_SUFFIX
3535 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
)
3537 /* It's not a byte, select word/dword operation. */
3538 if (i
.tm
.opcode_modifier
.w
)
3540 if (i
.tm
.opcode_modifier
.shortform
)
3541 i
.tm
.base_opcode
|= 8;
3543 i
.tm
.base_opcode
|= 1;
3546 /* Now select between word & dword operations via the operand
3547 size prefix, except for instructions that will ignore this
3549 if (i
.tm
.opcode_modifier
.addrprefixop0
)
3551 /* The address size override prefix changes the size of the
3553 if ((flag_code
== CODE_32BIT
3554 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3555 || (flag_code
!= CODE_32BIT
3556 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3557 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3560 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3561 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3562 && !i
.tm
.opcode_modifier
.ignoresize
3563 && !i
.tm
.opcode_modifier
.floatmf
3564 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3565 || (flag_code
== CODE_64BIT
3566 && i
.tm
.opcode_modifier
.jumpbyte
)))
3568 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3570 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3571 prefix
= ADDR_PREFIX_OPCODE
;
3573 if (!add_prefix (prefix
))
3577 /* Set mode64 for an operand. */
3578 if (i
.suffix
== QWORD_MNEM_SUFFIX
3579 && flag_code
== CODE_64BIT
3580 && !i
.tm
.opcode_modifier
.norex64
)
3582 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3583 need rex64. cmpxchg8b is also a special case. */
3584 if (! (i
.operands
== 2
3585 && i
.tm
.base_opcode
== 0x90
3586 && i
.tm
.extension_opcode
== None
3587 && UINTS_EQUAL (i
.types
[0], acc64
)
3588 && UINTS_EQUAL (i
.types
[1], acc64
))
3589 && ! (i
.operands
== 1
3590 && i
.tm
.base_opcode
== 0xfc7
3591 && i
.tm
.extension_opcode
== 1
3592 && !operand_type_check (i
.types
[0], reg
)
3593 && operand_type_check (i
.types
[0], anymem
)))
3597 /* Size floating point instruction. */
3598 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3599 if (i
.tm
.opcode_modifier
.floatmf
)
3600 i
.tm
.base_opcode
^= 4;
3607 check_byte_reg (void)
3611 for (op
= i
.operands
; --op
>= 0;)
3613 /* If this is an eight bit register, it's OK. If it's the 16 or
3614 32 bit version of an eight bit register, we will just use the
3615 low portion, and that's OK too. */
3616 if (i
.types
[op
].bitfield
.reg8
)
3619 /* Don't generate this warning if not needed. */
3620 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
3623 /* crc32 doesn't generate this warning. */
3624 if (i
.tm
.base_opcode
== 0xf20f38f0)
3627 if ((i
.types
[op
].bitfield
.reg16
3628 || i
.types
[op
].bitfield
.reg32
3629 || i
.types
[op
].bitfield
.reg64
)
3630 && i
.op
[op
].regs
->reg_num
< 4)
3632 /* Prohibit these changes in the 64bit mode, since the
3633 lowering is more complicated. */
3634 if (flag_code
== CODE_64BIT
3635 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3637 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3638 register_prefix
, i
.op
[op
].regs
->reg_name
,
3642 #if REGISTER_WARNINGS
3644 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3645 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3647 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3648 ? REGNAM_AL
- REGNAM_AX
3649 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3651 i
.op
[op
].regs
->reg_name
,
3656 /* Any other register is bad. */
3657 if (i
.types
[op
].bitfield
.reg16
3658 || i
.types
[op
].bitfield
.reg32
3659 || i
.types
[op
].bitfield
.reg64
3660 || i
.types
[op
].bitfield
.regmmx
3661 || i
.types
[op
].bitfield
.regxmm
3662 || i
.types
[op
].bitfield
.sreg2
3663 || i
.types
[op
].bitfield
.sreg3
3664 || i
.types
[op
].bitfield
.control
3665 || i
.types
[op
].bitfield
.debug
3666 || i
.types
[op
].bitfield
.test
3667 || i
.types
[op
].bitfield
.floatreg
3668 || i
.types
[op
].bitfield
.floatacc
)
3670 as_bad (_("`%s%s' not allowed with `%s%c'"),
3672 i
.op
[op
].regs
->reg_name
,
3682 check_long_reg (void)
3686 for (op
= i
.operands
; --op
>= 0;)
3687 /* Reject eight bit registers, except where the template requires
3688 them. (eg. movzb) */
3689 if (i
.types
[op
].bitfield
.reg8
3690 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3691 || i
.tm
.operand_types
[op
].bitfield
.reg32
3692 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3694 as_bad (_("`%s%s' not allowed with `%s%c'"),
3696 i
.op
[op
].regs
->reg_name
,
3701 /* Warn if the e prefix on a general reg is missing. */
3702 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3703 && i
.types
[op
].bitfield
.reg16
3704 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3705 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3707 /* Prohibit these changes in the 64bit mode, since the
3708 lowering is more complicated. */
3709 if (flag_code
== CODE_64BIT
)
3711 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3712 register_prefix
, i
.op
[op
].regs
->reg_name
,
3716 #if REGISTER_WARNINGS
3718 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3720 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3722 i
.op
[op
].regs
->reg_name
,
3726 /* Warn if the r prefix on a general reg is missing. */
3727 else if (i
.types
[op
].bitfield
.reg64
3728 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3729 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3732 && i
.tm
.opcode_modifier
.toqword
3733 && !i
.types
[0].bitfield
.regxmm
)
3735 /* Convert to QWORD. We want REX byte. */
3736 i
.suffix
= QWORD_MNEM_SUFFIX
;
3740 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3741 register_prefix
, i
.op
[op
].regs
->reg_name
,
3750 check_qword_reg (void)
3754 for (op
= i
.operands
; --op
>= 0; )
3755 /* Reject eight bit registers, except where the template requires
3756 them. (eg. movzb) */
3757 if (i
.types
[op
].bitfield
.reg8
3758 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3759 || i
.tm
.operand_types
[op
].bitfield
.reg32
3760 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3762 as_bad (_("`%s%s' not allowed with `%s%c'"),
3764 i
.op
[op
].regs
->reg_name
,
3769 /* Warn if the e prefix on a general reg is missing. */
3770 else if ((i
.types
[op
].bitfield
.reg16
3771 || i
.types
[op
].bitfield
.reg32
)
3772 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3773 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3775 /* Prohibit these changes in the 64bit mode, since the
3776 lowering is more complicated. */
3778 && i
.tm
.opcode_modifier
.todword
3779 && !i
.types
[0].bitfield
.regxmm
)
3781 /* Convert to DWORD. We don't want REX byte. */
3782 i
.suffix
= LONG_MNEM_SUFFIX
;
3786 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3787 register_prefix
, i
.op
[op
].regs
->reg_name
,
3796 check_word_reg (void)
3799 for (op
= i
.operands
; --op
>= 0;)
3800 /* Reject eight bit registers, except where the template requires
3801 them. (eg. movzb) */
3802 if (i
.types
[op
].bitfield
.reg8
3803 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3804 || i
.tm
.operand_types
[op
].bitfield
.reg32
3805 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3807 as_bad (_("`%s%s' not allowed with `%s%c'"),
3809 i
.op
[op
].regs
->reg_name
,
3814 /* Warn if the e prefix on a general reg is present. */
3815 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3816 && i
.types
[op
].bitfield
.reg32
3817 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3818 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3820 /* Prohibit these changes in the 64bit mode, since the
3821 lowering is more complicated. */
3822 if (flag_code
== CODE_64BIT
)
3824 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3825 register_prefix
, i
.op
[op
].regs
->reg_name
,
3830 #if REGISTER_WARNINGS
3831 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3833 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3835 i
.op
[op
].regs
->reg_name
,
3843 update_imm (unsigned int j
)
3845 i386_operand_type overlap
;
3847 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3848 if ((overlap
.bitfield
.imm8
3849 || overlap
.bitfield
.imm8s
3850 || overlap
.bitfield
.imm16
3851 || overlap
.bitfield
.imm32
3852 || overlap
.bitfield
.imm32s
3853 || overlap
.bitfield
.imm64
)
3854 && !UINTS_EQUAL (overlap
, imm8
)
3855 && !UINTS_EQUAL (overlap
, imm8s
)
3856 && !UINTS_EQUAL (overlap
, imm16
)
3857 && !UINTS_EQUAL (overlap
, imm32
)
3858 && !UINTS_EQUAL (overlap
, imm32s
)
3859 && !UINTS_EQUAL (overlap
, imm64
))
3863 i386_operand_type temp
;
3866 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3868 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3869 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3871 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3872 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3873 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3875 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3876 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3879 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3882 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3883 || UINTS_EQUAL (overlap
, imm16_32
)
3884 || UINTS_EQUAL (overlap
, imm16_32s
))
3886 UINTS_CLEAR (overlap
);
3887 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3888 overlap
.bitfield
.imm16
= 1;
3890 overlap
.bitfield
.imm32s
= 1;
3892 if (!UINTS_EQUAL (overlap
, imm8
)
3893 && !UINTS_EQUAL (overlap
, imm8s
)
3894 && !UINTS_EQUAL (overlap
, imm16
)
3895 && !UINTS_EQUAL (overlap
, imm32
)
3896 && !UINTS_EQUAL (overlap
, imm32s
)
3897 && !UINTS_EQUAL (overlap
, imm64
))
3899 as_bad (_("no instruction mnemonic suffix given; "
3900 "can't determine immediate size"));
3904 i
.types
[j
] = overlap
;
3914 for (j
= 0; j
< 2; j
++)
3915 if (update_imm (j
) == 0)
3918 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3919 assert (operand_type_check (i
.types
[2], imm
) == 0);
3927 i
.drex
.modrm_reg
= 0;
3928 i
.drex
.modrm_regmem
= 0;
3930 /* SSE5 4 operand instructions must have the destination the same as
3931 one of the inputs. Figure out the destination register and cache
3932 it away in the drex field, and remember which fields to use for
3934 if (i
.tm
.opcode_modifier
.drex
3935 && i
.tm
.opcode_modifier
.drexv
3938 i
.tm
.extension_opcode
= None
;
3940 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3941 if (i
.types
[0].bitfield
.regxmm
!= 0
3942 && i
.types
[1].bitfield
.regxmm
!= 0
3943 && i
.types
[2].bitfield
.regxmm
!= 0
3944 && i
.types
[3].bitfield
.regxmm
!= 0
3945 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3946 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3948 /* Clear the arguments that are stored in drex. */
3949 UINTS_CLEAR (i
.types
[0]);
3950 UINTS_CLEAR (i
.types
[3]);
3951 i
.reg_operands
-= 2;
3953 /* There are two different ways to encode a 4 operand
3954 instruction with all registers that uses OC1 set to
3955 0 or 1. Favor setting OC1 to 0 since this mimics the
3956 actions of other SSE5 assemblers. Use modrm encoding 2
3957 for register/register. Include the high order bit that
3958 is normally stored in the REX byte in the register
3960 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3961 i
.drex
.modrm_reg
= 2;
3962 i
.drex
.modrm_regmem
= 1;
3963 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3964 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3967 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3968 else if (i
.types
[0].bitfield
.regxmm
!= 0
3969 && i
.types
[1].bitfield
.regxmm
!= 0
3970 && (i
.types
[2].bitfield
.regxmm
3971 || operand_type_check (i
.types
[2], anymem
))
3972 && i
.types
[3].bitfield
.regxmm
!= 0
3973 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3974 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3976 /* clear the arguments that are stored in drex */
3977 UINTS_CLEAR (i
.types
[0]);
3978 UINTS_CLEAR (i
.types
[3]);
3979 i
.reg_operands
-= 2;
3981 /* Specify the modrm encoding for memory addressing. Include
3982 the high order bit that is normally stored in the REX byte
3983 in the register field. */
3984 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
3985 i
.drex
.modrm_reg
= 1;
3986 i
.drex
.modrm_regmem
= 2;
3987 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3988 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3991 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3992 else if (i
.types
[0].bitfield
.regxmm
!= 0
3993 && operand_type_check (i
.types
[1], anymem
) != 0
3994 && i
.types
[2].bitfield
.regxmm
!= 0
3995 && i
.types
[3].bitfield
.regxmm
!= 0
3996 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3997 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3999 /* Clear the arguments that are stored in drex. */
4000 UINTS_CLEAR (i
.types
[0]);
4001 UINTS_CLEAR (i
.types
[3]);
4002 i
.reg_operands
-= 2;
4004 /* Specify the modrm encoding for memory addressing. Include
4005 the high order bit that is normally stored in the REX byte
4006 in the register field. */
4007 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4008 i
.drex
.modrm_reg
= 2;
4009 i
.drex
.modrm_regmem
= 1;
4010 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4011 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4014 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4015 else if (i
.types
[0].bitfield
.regxmm
!= 0
4016 && i
.types
[1].bitfield
.regxmm
!= 0
4017 && i
.types
[2].bitfield
.regxmm
!= 0
4018 && i
.types
[3].bitfield
.regxmm
!= 0
4019 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4020 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4022 /* clear the arguments that are stored in drex */
4023 UINTS_CLEAR (i
.types
[2]);
4024 UINTS_CLEAR (i
.types
[3]);
4025 i
.reg_operands
-= 2;
4027 /* There are two different ways to encode a 4 operand
4028 instruction with all registers that uses OC1 set to
4029 0 or 1. Favor setting OC1 to 0 since this mimics the
4030 actions of other SSE5 assemblers. Use modrm encoding
4031 2 for register/register. Include the high order bit that
4032 is normally stored in the REX byte in the register
4034 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4035 i
.drex
.modrm_reg
= 1;
4036 i
.drex
.modrm_regmem
= 0;
4038 /* Remember the register, including the upper bits */
4039 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4040 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4043 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4044 else if (i
.types
[0].bitfield
.regxmm
!= 0
4045 && (i
.types
[1].bitfield
.regxmm
4046 || operand_type_check (i
.types
[1], anymem
))
4047 && i
.types
[2].bitfield
.regxmm
!= 0
4048 && i
.types
[3].bitfield
.regxmm
!= 0
4049 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4050 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4052 /* Clear the arguments that are stored in drex. */
4053 UINTS_CLEAR (i
.types
[2]);
4054 UINTS_CLEAR (i
.types
[3]);
4055 i
.reg_operands
-= 2;
4057 /* Specify the modrm encoding and remember the register
4058 including the bits normally stored in the REX byte. */
4059 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4060 i
.drex
.modrm_reg
= 0;
4061 i
.drex
.modrm_regmem
= 1;
4062 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4063 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4066 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4067 else if (operand_type_check (i
.types
[0], anymem
) != 0
4068 && i
.types
[1].bitfield
.regxmm
!= 0
4069 && i
.types
[2].bitfield
.regxmm
!= 0
4070 && i
.types
[3].bitfield
.regxmm
!= 0
4071 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4072 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4074 /* clear the arguments that are stored in drex */
4075 UINTS_CLEAR (i
.types
[2]);
4076 UINTS_CLEAR (i
.types
[3]);
4077 i
.reg_operands
-= 2;
4079 /* Specify the modrm encoding and remember the register
4080 including the bits normally stored in the REX byte. */
4081 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4082 i
.drex
.modrm_reg
= 1;
4083 i
.drex
.modrm_regmem
= 0;
4084 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4085 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4089 as_bad (_("Incorrect operands for the '%s' instruction"),
4093 /* SSE5 instructions with the DREX byte where the only memory operand
4094 is in the 2nd argument, and the first and last xmm register must
4095 match, and is encoded in the DREX byte. */
4096 else if (i
.tm
.opcode_modifier
.drex
4097 && !i
.tm
.opcode_modifier
.drexv
4100 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4101 if (i
.types
[0].bitfield
.regxmm
!= 0
4102 && (i
.types
[1].bitfield
.regxmm
4103 || operand_type_check(i
.types
[1], anymem
))
4104 && i
.types
[2].bitfield
.regxmm
!= 0
4105 && i
.types
[3].bitfield
.regxmm
!= 0
4106 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4107 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4109 /* clear the arguments that are stored in drex */
4110 UINTS_CLEAR (i
.types
[0]);
4111 UINTS_CLEAR (i
.types
[3]);
4112 i
.reg_operands
-= 2;
4114 /* Specify the modrm encoding and remember the register
4115 including the high bit normally stored in the REX
4117 i
.drex
.modrm_reg
= 2;
4118 i
.drex
.modrm_regmem
= 1;
4119 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4120 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4124 as_bad (_("Incorrect operands for the '%s' instruction"),
4128 /* SSE5 3 operand instructions that the result is a register, being
4129 either operand can be a memory operand, using OC0 to note which
4130 one is the memory. */
4131 else if (i
.tm
.opcode_modifier
.drex
4132 && i
.tm
.opcode_modifier
.drexv
4135 i
.tm
.extension_opcode
= None
;
4137 /* Case 1: 3 operand insn, src1 = register. */
4138 if (i
.types
[0].bitfield
.regxmm
!= 0
4139 && i
.types
[1].bitfield
.regxmm
!= 0
4140 && i
.types
[2].bitfield
.regxmm
!= 0)
4142 /* Clear the arguments that are stored in drex. */
4143 UINTS_CLEAR (i
.types
[2]);
4146 /* Specify the modrm encoding and remember the register
4147 including the high bit normally stored in the REX byte. */
4148 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4149 i
.drex
.modrm_reg
= 1;
4150 i
.drex
.modrm_regmem
= 0;
4151 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4152 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4155 /* Case 2: 3 operand insn, src1 = memory. */
4156 else if (operand_type_check (i
.types
[0], anymem
) != 0
4157 && i
.types
[1].bitfield
.regxmm
!= 0
4158 && i
.types
[2].bitfield
.regxmm
!= 0)
4160 /* Clear the arguments that are stored in drex. */
4161 UINTS_CLEAR (i
.types
[2]);
4164 /* Specify the modrm encoding and remember the register
4165 including the high bit normally stored in the REX
4167 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4168 i
.drex
.modrm_reg
= 1;
4169 i
.drex
.modrm_regmem
= 0;
4170 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4171 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4174 /* Case 3: 3 operand insn, src2 = memory. */
4175 else if (i
.types
[0].bitfield
.regxmm
!= 0
4176 && operand_type_check (i
.types
[1], anymem
) != 0
4177 && i
.types
[2].bitfield
.regxmm
!= 0)
4179 /* Clear the arguments that are stored in drex. */
4180 UINTS_CLEAR (i
.types
[2]);
4183 /* Specify the modrm encoding and remember the register
4184 including the high bit normally stored in the REX byte. */
4185 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4186 i
.drex
.modrm_reg
= 0;
4187 i
.drex
.modrm_regmem
= 1;
4188 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4189 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4193 as_bad (_("Incorrect operands for the '%s' instruction"),
4197 /* SSE5 4 operand instructions that are the comparison instructions
4198 where the first operand is the immediate value of the comparison
4200 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4202 /* Case 1: 4 operand insn, src1 = reg/memory. */
4203 if (operand_type_check (i
.types
[0], imm
) != 0
4204 && (i
.types
[1].bitfield
.regxmm
4205 || operand_type_check (i
.types
[1], anymem
))
4206 && i
.types
[2].bitfield
.regxmm
!= 0
4207 && i
.types
[3].bitfield
.regxmm
!= 0)
4209 /* clear the arguments that are stored in drex */
4210 UINTS_CLEAR (i
.types
[3]);
4213 /* Specify the modrm encoding and remember the register
4214 including the high bit normally stored in the REX byte. */
4215 i
.drex
.modrm_reg
= 2;
4216 i
.drex
.modrm_regmem
= 1;
4217 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4218 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4221 /* Case 2: 3 operand insn with ImmExt that places the
4222 opcode_extension as an immediate argument. This is used for
4223 all of the varients of comparison that supplies the appropriate
4224 value as part of the instruction. */
4225 else if ((i
.types
[0].bitfield
.regxmm
4226 || operand_type_check (i
.types
[0], anymem
))
4227 && i
.types
[1].bitfield
.regxmm
!= 0
4228 && i
.types
[2].bitfield
.regxmm
!= 0
4229 && operand_type_check (i
.types
[3], imm
) != 0)
4231 /* clear the arguments that are stored in drex */
4232 UINTS_CLEAR (i
.types
[2]);
4235 /* Specify the modrm encoding and remember the register
4236 including the high bit normally stored in the REX byte. */
4237 i
.drex
.modrm_reg
= 1;
4238 i
.drex
.modrm_regmem
= 0;
4239 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4240 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4244 as_bad (_("Incorrect operands for the '%s' instruction"),
4248 else if (i
.tm
.opcode_modifier
.drex
4249 || i
.tm
.opcode_modifier
.drexv
4250 || i
.tm
.opcode_modifier
.drexc
)
4251 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4255 process_operands (void)
4257 /* Default segment register this instruction will use for memory
4258 accesses. 0 means unknown. This is only for optimizing out
4259 unnecessary segment overrides. */
4260 const seg_entry
*default_seg
= 0;
4262 /* Handle all of the DREX munging that SSE5 needs. */
4263 if (i
.tm
.opcode_modifier
.drex
4264 || i
.tm
.opcode_modifier
.drexv
4265 || i
.tm
.opcode_modifier
.drexc
)
4268 if (i
.tm
.opcode_modifier
.firstxmm0
)
4272 /* The first operand is implicit and must be xmm0. */
4273 assert (i
.reg_operands
&& UINTS_EQUAL (i
.types
[0], regxmm
));
4274 if (i
.op
[0].regs
->reg_num
!= 0)
4277 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4278 i
.tm
.name
, register_prefix
);
4280 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4281 i
.tm
.name
, register_prefix
);
4285 for (j
= 1; j
< i
.operands
; j
++)
4287 i
.op
[j
- 1] = i
.op
[j
];
4288 i
.types
[j
- 1] = i
.types
[j
];
4290 /* We need to adjust fields in i.tm since they are used by
4291 build_modrm_byte. */
4292 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4299 else if (i
.tm
.opcode_modifier
.regkludge
)
4301 /* The imul $imm, %reg instruction is converted into
4302 imul $imm, %reg, %reg, and the clr %reg instruction
4303 is converted into xor %reg, %reg. */
4305 unsigned int first_reg_op
;
4307 if (operand_type_check (i
.types
[0], reg
))
4311 /* Pretend we saw the extra register operand. */
4312 assert (i
.reg_operands
== 1
4313 && i
.op
[first_reg_op
+ 1].regs
== 0);
4314 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4315 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4320 if (i
.tm
.opcode_modifier
.shortform
)
4322 if (i
.types
[0].bitfield
.sreg2
4323 || i
.types
[0].bitfield
.sreg3
)
4325 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4326 && i
.op
[0].regs
->reg_num
== 1)
4328 as_bad (_("you can't `pop %%cs'"));
4331 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4332 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4337 /* The register or float register operand is in operand
4341 if (i
.types
[0].bitfield
.floatreg
4342 || operand_type_check (i
.types
[0], reg
))
4346 /* Register goes in low 3 bits of opcode. */
4347 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4348 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4350 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4352 /* Warn about some common errors, but press on regardless.
4353 The first case can be generated by gcc (<= 2.8.1). */
4354 if (i
.operands
== 2)
4356 /* Reversed arguments on faddp, fsubp, etc. */
4357 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4358 register_prefix
, i
.op
[1].regs
->reg_name
,
4359 register_prefix
, i
.op
[0].regs
->reg_name
);
4363 /* Extraneous `l' suffix on fp insn. */
4364 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4365 register_prefix
, i
.op
[0].regs
->reg_name
);
4370 else if (i
.tm
.opcode_modifier
.modrm
)
4372 /* The opcode is completed (modulo i.tm.extension_opcode which
4373 must be put into the modrm byte). Now, we make the modrm and
4374 index base bytes based on all the info we've collected. */
4376 default_seg
= build_modrm_byte ();
4378 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4382 else if (i
.tm
.opcode_modifier
.isstring
)
4384 /* For the string instructions that allow a segment override
4385 on one of their operands, the default segment is ds. */
4389 if (i
.tm
.base_opcode
== 0x8d /* lea */
4392 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4394 /* If a segment was explicitly specified, and the specified segment
4395 is not the default, use an opcode prefix to select it. If we
4396 never figured out what the default segment is, then default_seg
4397 will be zero at this point, and the specified segment prefix will
4399 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4401 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4407 static const seg_entry
*
4408 build_modrm_byte (void)
4410 const seg_entry
*default_seg
= 0;
4412 /* SSE5 4 operand instructions are encoded in such a way that one of
4413 the inputs must match the destination register. Process_drex hides
4414 the 3rd argument in the drex field, so that by the time we get
4415 here, it looks to GAS as if this is a 2 operand instruction. */
4416 if ((i
.tm
.opcode_modifier
.drex
4417 || i
.tm
.opcode_modifier
.drexv
4418 || i
.tm
.opcode_modifier
.drexc
)
4419 && i
.reg_operands
== 2)
4421 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
4422 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
4424 i
.rm
.reg
= reg
->reg_num
;
4425 i
.rm
.regmem
= regmem
->reg_num
;
4427 if ((reg
->reg_flags
& RegRex
) != 0)
4429 if ((regmem
->reg_flags
& RegRex
) != 0)
4433 /* i.reg_operands MUST be the number of real register operands;
4434 implicit registers do not count. */
4435 else if (i
.reg_operands
== 2)
4437 unsigned int source
, dest
;
4445 /* When there are 3 operands, one of them may be immediate,
4446 which may be the first or the last operand. Otherwise,
4447 the first operand must be shift count register (cl). */
4448 assert (i
.imm_operands
== 1
4449 || (i
.imm_operands
== 0
4450 && i
.types
[0].bitfield
.shiftcount
));
4451 if (operand_type_check (i
.types
[0], imm
)
4452 || i
.types
[0].bitfield
.shiftcount
)
4458 /* When there are 4 operands, the first two must be 8bit
4459 immediate operands. The source operand will be the 3rd
4461 assert (i
.imm_operands
== 2
4462 && i
.types
[0].bitfield
.imm8
4463 && i
.types
[1].bitfield
.imm8
);
4473 /* One of the register operands will be encoded in the i.tm.reg
4474 field, the other in the combined i.tm.mode and i.tm.regmem
4475 fields. If no form of this instruction supports a memory
4476 destination operand, then we assume the source operand may
4477 sometimes be a memory operand and so we need to store the
4478 destination in the i.rm.reg field. */
4479 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4480 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4482 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4483 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4484 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4486 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4491 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4492 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4493 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4495 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4498 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4500 if (!i
.types
[0].bitfield
.control
4501 && !i
.types
[1].bitfield
.control
)
4503 i
.rex
&= ~(REX_R
| REX_B
);
4504 add_prefix (LOCK_PREFIX_OPCODE
);
4508 { /* If it's not 2 reg operands... */
4511 unsigned int fake_zero_displacement
= 0;
4514 /* This has been precalculated for SSE5 instructions
4515 that have a DREX field earlier in process_drex. */
4516 if (i
.tm
.opcode_modifier
.drex
4517 || i
.tm
.opcode_modifier
.drexv
4518 || i
.tm
.opcode_modifier
.drexc
)
4519 op
= i
.drex
.modrm_regmem
;
4522 for (op
= 0; op
< i
.operands
; op
++)
4523 if (operand_type_check (i
.types
[op
], anymem
))
4525 assert (op
< i
.operands
);
4530 if (i
.base_reg
== 0)
4533 if (!i
.disp_operands
)
4534 fake_zero_displacement
= 1;
4535 if (i
.index_reg
== 0)
4537 /* Operand is just <disp> */
4538 if (flag_code
== CODE_64BIT
)
4540 /* 64bit mode overwrites the 32bit absolute
4541 addressing by RIP relative addressing and
4542 absolute addressing is encoded by one of the
4543 redundant SIB forms. */
4544 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4545 i
.sib
.base
= NO_BASE_REGISTER
;
4546 i
.sib
.index
= NO_INDEX_REGISTER
;
4547 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4548 ? disp32s
: disp32
);
4550 else if ((flag_code
== CODE_16BIT
)
4551 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4553 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4554 i
.types
[op
] = disp16
;
4558 i
.rm
.regmem
= NO_BASE_REGISTER
;
4559 i
.types
[op
] = disp32
;
4562 else /* !i.base_reg && i.index_reg */
4564 if (i
.index_reg
->reg_num
== RegEiz
4565 || i
.index_reg
->reg_num
== RegRiz
)
4566 i
.sib
.index
= NO_INDEX_REGISTER
;
4568 i
.sib
.index
= i
.index_reg
->reg_num
;
4569 i
.sib
.base
= NO_BASE_REGISTER
;
4570 i
.sib
.scale
= i
.log2_scale_factor
;
4571 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4572 i
.types
[op
].bitfield
.disp8
= 0;
4573 i
.types
[op
].bitfield
.disp16
= 0;
4574 i
.types
[op
].bitfield
.disp64
= 0;
4575 if (flag_code
!= CODE_64BIT
)
4577 /* Must be 32 bit */
4578 i
.types
[op
].bitfield
.disp32
= 1;
4579 i
.types
[op
].bitfield
.disp32s
= 0;
4583 i
.types
[op
].bitfield
.disp32
= 0;
4584 i
.types
[op
].bitfield
.disp32s
= 1;
4586 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4590 /* RIP addressing for 64bit mode. */
4591 else if (i
.base_reg
->reg_num
== RegRip
||
4592 i
.base_reg
->reg_num
== RegEip
)
4594 i
.rm
.regmem
= NO_BASE_REGISTER
;
4595 i
.types
[op
].bitfield
.disp8
= 0;
4596 i
.types
[op
].bitfield
.disp16
= 0;
4597 i
.types
[op
].bitfield
.disp32
= 0;
4598 i
.types
[op
].bitfield
.disp32s
= 1;
4599 i
.types
[op
].bitfield
.disp64
= 0;
4600 i
.flags
[op
] |= Operand_PCrel
;
4601 if (! i
.disp_operands
)
4602 fake_zero_displacement
= 1;
4604 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4606 switch (i
.base_reg
->reg_num
)
4609 if (i
.index_reg
== 0)
4611 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4612 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4616 if (i
.index_reg
== 0)
4619 if (operand_type_check (i
.types
[op
], disp
) == 0)
4621 /* fake (%bp) into 0(%bp) */
4622 i
.types
[op
].bitfield
.disp8
= 1;
4623 fake_zero_displacement
= 1;
4626 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4627 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4629 default: /* (%si) -> 4 or (%di) -> 5 */
4630 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4632 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4634 else /* i.base_reg and 32/64 bit mode */
4636 if (flag_code
== CODE_64BIT
4637 && operand_type_check (i
.types
[op
], disp
))
4639 i386_operand_type temp
;
4641 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4643 if (i
.prefix
[ADDR_PREFIX
] == 0)
4644 i
.types
[op
].bitfield
.disp32s
= 1;
4646 i
.types
[op
].bitfield
.disp32
= 1;
4649 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4650 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4652 i
.sib
.base
= i
.base_reg
->reg_num
;
4653 /* x86-64 ignores REX prefix bit here to avoid decoder
4655 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4658 if (i
.disp_operands
== 0)
4660 fake_zero_displacement
= 1;
4661 i
.types
[op
].bitfield
.disp8
= 1;
4664 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4668 i
.sib
.scale
= i
.log2_scale_factor
;
4669 if (i
.index_reg
== 0)
4671 /* <disp>(%esp) becomes two byte modrm with no index
4672 register. We've already stored the code for esp
4673 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4674 Any base register besides %esp will not use the
4675 extra modrm byte. */
4676 i
.sib
.index
= NO_INDEX_REGISTER
;
4680 if (i
.index_reg
->reg_num
== RegEiz
4681 || i
.index_reg
->reg_num
== RegRiz
)
4682 i
.sib
.index
= NO_INDEX_REGISTER
;
4684 i
.sib
.index
= i
.index_reg
->reg_num
;
4685 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4686 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4691 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4692 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4695 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4698 if (fake_zero_displacement
)
4700 /* Fakes a zero displacement assuming that i.types[op]
4701 holds the correct displacement size. */
4704 assert (i
.op
[op
].disps
== 0);
4705 exp
= &disp_expressions
[i
.disp_operands
++];
4706 i
.op
[op
].disps
= exp
;
4707 exp
->X_op
= O_constant
;
4708 exp
->X_add_number
= 0;
4709 exp
->X_add_symbol
= (symbolS
*) 0;
4710 exp
->X_op_symbol
= (symbolS
*) 0;
4714 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4715 (if any) based on i.tm.extension_opcode. Again, we must be
4716 careful to make sure that segment/control/debug/test/MMX
4717 registers are coded into the i.rm.reg field. */
4722 /* This has been precalculated for SSE5 instructions
4723 that have a DREX field earlier in process_drex. */
4724 if (i
.tm
.opcode_modifier
.drex
4725 || i
.tm
.opcode_modifier
.drexv
4726 || i
.tm
.opcode_modifier
.drexc
)
4728 op
= i
.drex
.modrm_reg
;
4729 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4730 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4735 for (op
= 0; op
< i
.operands
; op
++)
4736 if (i
.types
[op
].bitfield
.reg8
4737 || i
.types
[op
].bitfield
.reg16
4738 || i
.types
[op
].bitfield
.reg32
4739 || i
.types
[op
].bitfield
.reg64
4740 || i
.types
[op
].bitfield
.regmmx
4741 || i
.types
[op
].bitfield
.regxmm
4742 || i
.types
[op
].bitfield
.sreg2
4743 || i
.types
[op
].bitfield
.sreg3
4744 || i
.types
[op
].bitfield
.control
4745 || i
.types
[op
].bitfield
.debug
4746 || i
.types
[op
].bitfield
.test
)
4749 assert (op
< i
.operands
);
4751 /* If there is an extension opcode to put here, the
4752 register number must be put into the regmem field. */
4753 if (i
.tm
.extension_opcode
!= None
)
4755 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4756 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4761 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4762 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4767 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4768 must set it to 3 to indicate this is a register operand
4769 in the regmem field. */
4770 if (!i
.mem_operands
)
4774 /* Fill in i.rm.reg field with extension opcode (if any). */
4775 if (i
.tm
.extension_opcode
!= None
4776 && !(i
.tm
.opcode_modifier
.drex
4777 || i
.tm
.opcode_modifier
.drexv
4778 || i
.tm
.opcode_modifier
.drexc
))
4779 i
.rm
.reg
= i
.tm
.extension_opcode
;
4785 output_branch (void)
4790 relax_substateT subtype
;
4795 if (flag_code
== CODE_16BIT
)
4799 if (i
.prefix
[DATA_PREFIX
] != 0)
4805 /* Pentium4 branch hints. */
4806 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4807 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4812 if (i
.prefix
[REX_PREFIX
] != 0)
4818 if (i
.prefixes
!= 0 && !intel_syntax
)
4819 as_warn (_("skipping prefixes on this instruction"));
4821 /* It's always a symbol; End frag & setup for relax.
4822 Make sure there is enough room in this frag for the largest
4823 instruction we may generate in md_convert_frag. This is 2
4824 bytes for the opcode and room for the prefix and largest
4826 frag_grow (prefix
+ 2 + 4);
4827 /* Prefix and 1 opcode byte go in fr_fix. */
4828 p
= frag_more (prefix
+ 1);
4829 if (i
.prefix
[DATA_PREFIX
] != 0)
4830 *p
++ = DATA_PREFIX_OPCODE
;
4831 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4832 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4833 *p
++ = i
.prefix
[SEG_PREFIX
];
4834 if (i
.prefix
[REX_PREFIX
] != 0)
4835 *p
++ = i
.prefix
[REX_PREFIX
];
4836 *p
= i
.tm
.base_opcode
;
4838 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4839 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4840 else if (cpu_arch_flags
.bitfield
.cpui386
)
4841 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4843 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4846 sym
= i
.op
[0].disps
->X_add_symbol
;
4847 off
= i
.op
[0].disps
->X_add_number
;
4849 if (i
.op
[0].disps
->X_op
!= O_constant
4850 && i
.op
[0].disps
->X_op
!= O_symbol
)
4852 /* Handle complex expressions. */
4853 sym
= make_expr_symbol (i
.op
[0].disps
);
4857 /* 1 possible extra opcode + 4 byte displacement go in var part.
4858 Pass reloc in fr_var. */
4859 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4869 if (i
.tm
.opcode_modifier
.jumpbyte
)
4871 /* This is a loop or jecxz type instruction. */
4873 if (i
.prefix
[ADDR_PREFIX
] != 0)
4875 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4878 /* Pentium4 branch hints. */
4879 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4880 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4882 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4891 if (flag_code
== CODE_16BIT
)
4894 if (i
.prefix
[DATA_PREFIX
] != 0)
4896 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4906 if (i
.prefix
[REX_PREFIX
] != 0)
4908 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4912 if (i
.prefixes
!= 0 && !intel_syntax
)
4913 as_warn (_("skipping prefixes on this instruction"));
4915 p
= frag_more (1 + size
);
4916 *p
++ = i
.tm
.base_opcode
;
4918 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4919 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4921 /* All jumps handled here are signed, but don't use a signed limit
4922 check for 32 and 16 bit jumps as we want to allow wrap around at
4923 4G and 64k respectively. */
4925 fixP
->fx_signed
= 1;
4929 output_interseg_jump (void)
4937 if (flag_code
== CODE_16BIT
)
4941 if (i
.prefix
[DATA_PREFIX
] != 0)
4947 if (i
.prefix
[REX_PREFIX
] != 0)
4957 if (i
.prefixes
!= 0 && !intel_syntax
)
4958 as_warn (_("skipping prefixes on this instruction"));
4960 /* 1 opcode; 2 segment; offset */
4961 p
= frag_more (prefix
+ 1 + 2 + size
);
4963 if (i
.prefix
[DATA_PREFIX
] != 0)
4964 *p
++ = DATA_PREFIX_OPCODE
;
4966 if (i
.prefix
[REX_PREFIX
] != 0)
4967 *p
++ = i
.prefix
[REX_PREFIX
];
4969 *p
++ = i
.tm
.base_opcode
;
4970 if (i
.op
[1].imms
->X_op
== O_constant
)
4972 offsetT n
= i
.op
[1].imms
->X_add_number
;
4975 && !fits_in_unsigned_word (n
)
4976 && !fits_in_signed_word (n
))
4978 as_bad (_("16-bit jump out of range"));
4981 md_number_to_chars (p
, n
, size
);
4984 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4985 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4986 if (i
.op
[0].imms
->X_op
!= O_constant
)
4987 as_bad (_("can't handle non absolute segment in `%s'"),
4989 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4995 fragS
*insn_start_frag
;
4996 offsetT insn_start_off
;
4998 /* Tie dwarf2 debug info to the address at the start of the insn.
4999 We can't do this after the insn has been output as the current
5000 frag may have been closed off. eg. by frag_var. */
5001 dwarf2_emit_insn (0);
5003 insn_start_frag
= frag_now
;
5004 insn_start_off
= frag_now_fix ();
5007 if (i
.tm
.opcode_modifier
.jump
)
5009 else if (i
.tm
.opcode_modifier
.jumpbyte
5010 || i
.tm
.opcode_modifier
.jumpdword
)
5012 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5013 output_interseg_jump ();
5016 /* Output normal instructions here. */
5020 unsigned int prefix
;
5022 switch (i
.tm
.opcode_length
)
5025 if (i
.tm
.base_opcode
& 0xff000000)
5027 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5032 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5034 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5035 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5038 if (prefix
!= REPE_PREFIX_OPCODE
5039 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
5040 add_prefix (prefix
);
5043 add_prefix (prefix
);
5052 /* The prefix bytes. */
5053 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5055 FRAG_APPEND_1_CHAR (*q
);
5057 /* Now the opcode; be careful about word order here! */
5058 if (i
.tm
.opcode_length
== 1)
5060 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5064 switch (i
.tm
.opcode_length
)
5068 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5078 /* Put out high byte first: can't use md_number_to_chars! */
5079 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5080 *p
= i
.tm
.base_opcode
& 0xff;
5082 /* On SSE5, encode the OC1 bit in the DREX field if this
5083 encoding has multiple formats. */
5084 if (i
.tm
.opcode_modifier
.drex
5085 && i
.tm
.opcode_modifier
.drexv
5086 && DREX_OC1 (i
.tm
.extension_opcode
))
5087 *p
|= DREX_OC1_MASK
;
5090 /* Now the modrm byte and sib byte (if present). */
5091 if (i
.tm
.opcode_modifier
.modrm
)
5093 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5096 /* If i.rm.regmem == ESP (4)
5097 && i.rm.mode != (Register mode)
5099 ==> need second modrm byte. */
5100 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5102 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5103 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5105 | i
.sib
.scale
<< 6));
5108 /* Write the DREX byte if needed. */
5109 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5112 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5114 /* Encode the OC0 bit if this encoding has multiple
5116 if ((i
.tm
.opcode_modifier
.drex
5117 || i
.tm
.opcode_modifier
.drexv
)
5118 && DREX_OC0 (i
.tm
.extension_opcode
))
5119 *p
|= DREX_OC0_MASK
;
5122 if (i
.disp_operands
)
5123 output_disp (insn_start_frag
, insn_start_off
);
5126 output_imm (insn_start_frag
, insn_start_off
);
5132 pi ("" /*line*/, &i
);
5134 #endif /* DEBUG386 */
5137 /* Return the size of the displacement operand N. */
5140 disp_size (unsigned int n
)
5143 if (i
.types
[n
].bitfield
.disp64
)
5145 else if (i
.types
[n
].bitfield
.disp8
)
5147 else if (i
.types
[n
].bitfield
.disp16
)
5152 /* Return the size of the immediate operand N. */
5155 imm_size (unsigned int n
)
5158 if (i
.types
[n
].bitfield
.imm64
)
5160 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5162 else if (i
.types
[n
].bitfield
.imm16
)
5168 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5173 for (n
= 0; n
< i
.operands
; n
++)
5175 if (operand_type_check (i
.types
[n
], disp
))
5177 if (i
.op
[n
].disps
->X_op
== O_constant
)
5179 int size
= disp_size (n
);
5182 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5184 p
= frag_more (size
);
5185 md_number_to_chars (p
, val
, size
);
5189 enum bfd_reloc_code_real reloc_type
;
5190 int size
= disp_size (n
);
5191 int sign
= i
.types
[n
].bitfield
.disp32s
;
5192 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5194 /* We can't have 8 bit displacement here. */
5195 assert (!i
.types
[n
].bitfield
.disp8
);
5197 /* The PC relative address is computed relative
5198 to the instruction boundary, so in case immediate
5199 fields follows, we need to adjust the value. */
5200 if (pcrel
&& i
.imm_operands
)
5205 for (n1
= 0; n1
< i
.operands
; n1
++)
5206 if (operand_type_check (i
.types
[n1
], imm
))
5208 /* Only one immediate is allowed for PC
5209 relative address. */
5212 i
.op
[n
].disps
->X_add_number
-= sz
;
5214 /* We should find the immediate. */
5218 p
= frag_more (size
);
5219 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5221 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5222 && (((reloc_type
== BFD_RELOC_32
5223 || reloc_type
== BFD_RELOC_X86_64_32S
5224 || (reloc_type
== BFD_RELOC_64
5226 && (i
.op
[n
].disps
->X_op
== O_symbol
5227 || (i
.op
[n
].disps
->X_op
== O_add
5228 && ((symbol_get_value_expression
5229 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5231 || reloc_type
== BFD_RELOC_32_PCREL
))
5235 if (insn_start_frag
== frag_now
)
5236 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5241 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5242 for (fr
= insn_start_frag
->fr_next
;
5243 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5245 add
+= p
- frag_now
->fr_literal
;
5250 reloc_type
= BFD_RELOC_386_GOTPC
;
5251 i
.op
[n
].imms
->X_add_number
+= add
;
5253 else if (reloc_type
== BFD_RELOC_64
)
5254 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5256 /* Don't do the adjustment for x86-64, as there
5257 the pcrel addressing is relative to the _next_
5258 insn, and that is taken care of in other code. */
5259 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5261 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5262 i
.op
[n
].disps
, pcrel
, reloc_type
);
5269 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5274 for (n
= 0; n
< i
.operands
; n
++)
5276 if (operand_type_check (i
.types
[n
], imm
))
5278 if (i
.op
[n
].imms
->X_op
== O_constant
)
5280 int size
= imm_size (n
);
5283 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5285 p
= frag_more (size
);
5286 md_number_to_chars (p
, val
, size
);
5290 /* Not absolute_section.
5291 Need a 32-bit fixup (don't support 8bit
5292 non-absolute imms). Try to support other
5294 enum bfd_reloc_code_real reloc_type
;
5295 int size
= imm_size (n
);
5298 if (i
.types
[n
].bitfield
.imm32s
5299 && (i
.suffix
== QWORD_MNEM_SUFFIX
5300 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5305 p
= frag_more (size
);
5306 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5308 /* This is tough to explain. We end up with this one if we
5309 * have operands that look like
5310 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5311 * obtain the absolute address of the GOT, and it is strongly
5312 * preferable from a performance point of view to avoid using
5313 * a runtime relocation for this. The actual sequence of
5314 * instructions often look something like:
5319 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5321 * The call and pop essentially return the absolute address
5322 * of the label .L66 and store it in %ebx. The linker itself
5323 * will ultimately change the first operand of the addl so
5324 * that %ebx points to the GOT, but to keep things simple, the
5325 * .o file must have this operand set so that it generates not
5326 * the absolute address of .L66, but the absolute address of
5327 * itself. This allows the linker itself simply treat a GOTPC
5328 * relocation as asking for a pcrel offset to the GOT to be
5329 * added in, and the addend of the relocation is stored in the
5330 * operand field for the instruction itself.
5332 * Our job here is to fix the operand so that it would add
5333 * the correct offset so that %ebx would point to itself. The
5334 * thing that is tricky is that .-.L66 will point to the
5335 * beginning of the instruction, so we need to further modify
5336 * the operand so that it will point to itself. There are
5337 * other cases where you have something like:
5339 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5341 * and here no correction would be required. Internally in
5342 * the assembler we treat operands of this form as not being
5343 * pcrel since the '.' is explicitly mentioned, and I wonder
5344 * whether it would simplify matters to do it this way. Who
5345 * knows. In earlier versions of the PIC patches, the
5346 * pcrel_adjust field was used to store the correction, but
5347 * since the expression is not pcrel, I felt it would be
5348 * confusing to do it this way. */
5350 if ((reloc_type
== BFD_RELOC_32
5351 || reloc_type
== BFD_RELOC_X86_64_32S
5352 || reloc_type
== BFD_RELOC_64
)
5354 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5355 && (i
.op
[n
].imms
->X_op
== O_symbol
5356 || (i
.op
[n
].imms
->X_op
== O_add
5357 && ((symbol_get_value_expression
5358 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5363 if (insn_start_frag
== frag_now
)
5364 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5369 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5370 for (fr
= insn_start_frag
->fr_next
;
5371 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5373 add
+= p
- frag_now
->fr_literal
;
5377 reloc_type
= BFD_RELOC_386_GOTPC
;
5379 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5381 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5382 i
.op
[n
].imms
->X_add_number
+= add
;
5384 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5385 i
.op
[n
].imms
, 0, reloc_type
);
5391 /* x86_cons_fix_new is called via the expression parsing code when a
5392 reloc is needed. We use this hook to get the correct .got reloc. */
5393 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5394 static int cons_sign
= -1;
5397 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5400 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5402 got_reloc
= NO_RELOC
;
5405 if (exp
->X_op
== O_secrel
)
5407 exp
->X_op
= O_symbol
;
5408 r
= BFD_RELOC_32_SECREL
;
5412 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5415 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5416 # define lex_got(reloc, adjust, types) NULL
5418 /* Parse operands of the form
5419 <symbol>@GOTOFF+<nnn>
5420 and similar .plt or .got references.
5422 If we find one, set up the correct relocation in RELOC and copy the
5423 input string, minus the `@GOTOFF' into a malloc'd buffer for
5424 parsing by the calling routine. Return this buffer, and if ADJUST
5425 is non-null set it to the length of the string we removed from the
5426 input line. Otherwise return NULL. */
5428 lex_got (enum bfd_reloc_code_real
*reloc
,
5430 i386_operand_type
*types
)
5432 /* Some of the relocations depend on the size of what field is to
5433 be relocated. But in our callers i386_immediate and i386_displacement
5434 we don't yet know the operand size (this will be set by insn
5435 matching). Hence we record the word32 relocation here,
5436 and adjust the reloc according to the real size in reloc(). */
5437 static const struct {
5439 const enum bfd_reloc_code_real rel
[2];
5440 const i386_operand_type types64
;
5443 BFD_RELOC_X86_64_PLTOFF64
},
5444 OPERAND_TYPE_IMM64
},
5445 { "PLT", { BFD_RELOC_386_PLT32
,
5446 BFD_RELOC_X86_64_PLT32
},
5447 OPERAND_TYPE_IMM32_32S_DISP32
},
5449 BFD_RELOC_X86_64_GOTPLT64
},
5450 OPERAND_TYPE_IMM64_DISP64
},
5451 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5452 BFD_RELOC_X86_64_GOTOFF64
},
5453 OPERAND_TYPE_IMM64_DISP64
},
5455 BFD_RELOC_X86_64_GOTPCREL
},
5456 OPERAND_TYPE_IMM32_32S_DISP32
},
5457 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5458 BFD_RELOC_X86_64_TLSGD
},
5459 OPERAND_TYPE_IMM32_32S_DISP32
},
5460 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5462 OPERAND_TYPE_NONE
},
5464 BFD_RELOC_X86_64_TLSLD
},
5465 OPERAND_TYPE_IMM32_32S_DISP32
},
5466 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5467 BFD_RELOC_X86_64_GOTTPOFF
},
5468 OPERAND_TYPE_IMM32_32S_DISP32
},
5469 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5470 BFD_RELOC_X86_64_TPOFF32
},
5471 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5472 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5474 OPERAND_TYPE_NONE
},
5475 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5476 BFD_RELOC_X86_64_DTPOFF32
},
5478 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5479 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5481 OPERAND_TYPE_NONE
},
5482 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5484 OPERAND_TYPE_NONE
},
5485 { "GOT", { BFD_RELOC_386_GOT32
,
5486 BFD_RELOC_X86_64_GOT32
},
5487 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5488 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5489 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5490 OPERAND_TYPE_IMM32_32S_DISP32
},
5491 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5492 BFD_RELOC_X86_64_TLSDESC_CALL
},
5493 OPERAND_TYPE_IMM32_32S_DISP32
},
5501 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5502 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5505 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5509 len
= strlen (gotrel
[j
].str
);
5510 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5512 if (gotrel
[j
].rel
[object_64bit
] != 0)
5515 char *tmpbuf
, *past_reloc
;
5517 *reloc
= gotrel
[j
].rel
[object_64bit
];
5523 if (flag_code
!= CODE_64BIT
)
5525 types
->bitfield
.imm32
= 1;
5526 types
->bitfield
.disp32
= 1;
5529 *types
= gotrel
[j
].types64
;
5532 if (GOT_symbol
== NULL
)
5533 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5535 /* The length of the first part of our input line. */
5536 first
= cp
- input_line_pointer
;
5538 /* The second part goes from after the reloc token until
5539 (and including) an end_of_line char or comma. */
5540 past_reloc
= cp
+ 1 + len
;
5542 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5544 second
= cp
+ 1 - past_reloc
;
5546 /* Allocate and copy string. The trailing NUL shouldn't
5547 be necessary, but be safe. */
5548 tmpbuf
= xmalloc (first
+ second
+ 2);
5549 memcpy (tmpbuf
, input_line_pointer
, first
);
5550 if (second
!= 0 && *past_reloc
!= ' ')
5551 /* Replace the relocation token with ' ', so that
5552 errors like foo@GOTOFF1 will be detected. */
5553 tmpbuf
[first
++] = ' ';
5554 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5555 tmpbuf
[first
+ second
] = '\0';
5559 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5560 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5565 /* Might be a symbol version string. Don't as_bad here. */
5570 x86_cons (expressionS
*exp
, int size
)
5572 if (size
== 4 || (object_64bit
&& size
== 8))
5574 /* Handle @GOTOFF and the like in an expression. */
5576 char *gotfree_input_line
;
5579 save
= input_line_pointer
;
5580 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5581 if (gotfree_input_line
)
5582 input_line_pointer
= gotfree_input_line
;
5586 if (gotfree_input_line
)
5588 /* expression () has merrily parsed up to the end of line,
5589 or a comma - in the wrong buffer. Transfer how far
5590 input_line_pointer has moved to the right buffer. */
5591 input_line_pointer
= (save
5592 + (input_line_pointer
- gotfree_input_line
)
5594 free (gotfree_input_line
);
5595 if (exp
->X_op
== O_constant
5596 || exp
->X_op
== O_absent
5597 || exp
->X_op
== O_illegal
5598 || exp
->X_op
== O_register
5599 || exp
->X_op
== O_big
)
5601 char c
= *input_line_pointer
;
5602 *input_line_pointer
= 0;
5603 as_bad (_("missing or invalid expression `%s'"), save
);
5604 *input_line_pointer
= c
;
5613 static void signed_cons (int size
)
5615 if (flag_code
== CODE_64BIT
)
5623 pe_directive_secrel (dummy
)
5624 int dummy ATTRIBUTE_UNUSED
;
5631 if (exp
.X_op
== O_symbol
)
5632 exp
.X_op
= O_secrel
;
5634 emit_expr (&exp
, 4);
5636 while (*input_line_pointer
++ == ',');
5638 input_line_pointer
--;
5639 demand_empty_rest_of_line ();
5644 i386_immediate (char *imm_start
)
5646 char *save_input_line_pointer
;
5647 char *gotfree_input_line
;
5650 i386_operand_type types
;
5652 UINTS_SET (types
, ~0);
5654 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5656 as_bad (_("at most %d immediate operands are allowed"),
5657 MAX_IMMEDIATE_OPERANDS
);
5661 exp
= &im_expressions
[i
.imm_operands
++];
5662 i
.op
[this_operand
].imms
= exp
;
5664 if (is_space_char (*imm_start
))
5667 save_input_line_pointer
= input_line_pointer
;
5668 input_line_pointer
= imm_start
;
5670 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5671 if (gotfree_input_line
)
5672 input_line_pointer
= gotfree_input_line
;
5674 exp_seg
= expression (exp
);
5677 if (*input_line_pointer
)
5678 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5680 input_line_pointer
= save_input_line_pointer
;
5681 if (gotfree_input_line
)
5682 free (gotfree_input_line
);
5684 if (exp
->X_op
== O_absent
5685 || exp
->X_op
== O_illegal
5686 || exp
->X_op
== O_big
5687 || (gotfree_input_line
5688 && (exp
->X_op
== O_constant
5689 || exp
->X_op
== O_register
)))
5691 as_bad (_("missing or invalid immediate expression `%s'"),
5695 else if (exp
->X_op
== O_constant
)
5697 /* Size it properly later. */
5698 i
.types
[this_operand
].bitfield
.imm64
= 1;
5699 /* If BFD64, sign extend val. */
5700 if (!use_rela_relocations
5701 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5703 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5705 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5706 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5707 && exp_seg
!= absolute_section
5708 && exp_seg
!= text_section
5709 && exp_seg
!= data_section
5710 && exp_seg
!= bss_section
5711 && exp_seg
!= undefined_section
5712 && !bfd_is_com_section (exp_seg
))
5714 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5718 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5720 as_bad (_("illegal immediate register operand %s"), imm_start
);
5725 /* This is an address. The size of the address will be
5726 determined later, depending on destination register,
5727 suffix, or the default for the section. */
5728 i
.types
[this_operand
].bitfield
.imm8
= 1;
5729 i
.types
[this_operand
].bitfield
.imm16
= 1;
5730 i
.types
[this_operand
].bitfield
.imm32
= 1;
5731 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5732 i
.types
[this_operand
].bitfield
.imm64
= 1;
5733 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5741 i386_scale (char *scale
)
5744 char *save
= input_line_pointer
;
5746 input_line_pointer
= scale
;
5747 val
= get_absolute_expression ();
5752 i
.log2_scale_factor
= 0;
5755 i
.log2_scale_factor
= 1;
5758 i
.log2_scale_factor
= 2;
5761 i
.log2_scale_factor
= 3;
5765 char sep
= *input_line_pointer
;
5767 *input_line_pointer
= '\0';
5768 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5770 *input_line_pointer
= sep
;
5771 input_line_pointer
= save
;
5775 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5777 as_warn (_("scale factor of %d without an index register"),
5778 1 << i
.log2_scale_factor
);
5779 i
.log2_scale_factor
= 0;
5781 scale
= input_line_pointer
;
5782 input_line_pointer
= save
;
5787 i386_displacement (char *disp_start
, char *disp_end
)
5791 char *save_input_line_pointer
;
5792 char *gotfree_input_line
;
5794 i386_operand_type bigdisp
, types
= anydisp
;
5797 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5799 as_bad (_("at most %d displacement operands are allowed"),
5800 MAX_MEMORY_OPERANDS
);
5804 UINTS_CLEAR (bigdisp
);
5805 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5806 || (!current_templates
->start
->opcode_modifier
.jump
5807 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5809 bigdisp
.bitfield
.disp32
= 1;
5810 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5811 if (flag_code
== CODE_64BIT
)
5815 bigdisp
.bitfield
.disp32s
= 1;
5816 bigdisp
.bitfield
.disp64
= 1;
5819 else if ((flag_code
== CODE_16BIT
) ^ override
)
5821 bigdisp
.bitfield
.disp32
= 0;
5822 bigdisp
.bitfield
.disp16
= 1;
5827 /* For PC-relative branches, the width of the displacement
5828 is dependent upon data size, not address size. */
5829 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5830 if (flag_code
== CODE_64BIT
)
5832 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5833 bigdisp
.bitfield
.disp16
= 1;
5836 bigdisp
.bitfield
.disp32
= 1;
5837 bigdisp
.bitfield
.disp32s
= 1;
5843 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5845 : LONG_MNEM_SUFFIX
));
5846 bigdisp
.bitfield
.disp32
= 1;
5847 if ((flag_code
== CODE_16BIT
) ^ override
)
5849 bigdisp
.bitfield
.disp32
= 0;
5850 bigdisp
.bitfield
.disp16
= 1;
5854 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5857 exp
= &disp_expressions
[i
.disp_operands
];
5858 i
.op
[this_operand
].disps
= exp
;
5860 save_input_line_pointer
= input_line_pointer
;
5861 input_line_pointer
= disp_start
;
5862 END_STRING_AND_SAVE (disp_end
);
5864 #ifndef GCC_ASM_O_HACK
5865 #define GCC_ASM_O_HACK 0
5868 END_STRING_AND_SAVE (disp_end
+ 1);
5869 if (i
.types
[this_operand
].bitfield
.baseIndex
5870 && displacement_string_end
[-1] == '+')
5872 /* This hack is to avoid a warning when using the "o"
5873 constraint within gcc asm statements.
5876 #define _set_tssldt_desc(n,addr,limit,type) \
5877 __asm__ __volatile__ ( \
5879 "movw %w1,2+%0\n\t" \
5881 "movb %b1,4+%0\n\t" \
5882 "movb %4,5+%0\n\t" \
5883 "movb $0,6+%0\n\t" \
5884 "movb %h1,7+%0\n\t" \
5886 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5888 This works great except that the output assembler ends
5889 up looking a bit weird if it turns out that there is
5890 no offset. You end up producing code that looks like:
5903 So here we provide the missing zero. */
5905 *displacement_string_end
= '0';
5908 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5909 if (gotfree_input_line
)
5910 input_line_pointer
= gotfree_input_line
;
5912 exp_seg
= expression (exp
);
5915 if (*input_line_pointer
)
5916 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5918 RESTORE_END_STRING (disp_end
+ 1);
5920 input_line_pointer
= save_input_line_pointer
;
5921 if (gotfree_input_line
)
5922 free (gotfree_input_line
);
5925 /* We do this to make sure that the section symbol is in
5926 the symbol table. We will ultimately change the relocation
5927 to be relative to the beginning of the section. */
5928 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5929 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5930 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5932 if (exp
->X_op
!= O_symbol
)
5935 if (S_IS_LOCAL (exp
->X_add_symbol
)
5936 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5937 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5938 exp
->X_op
= O_subtract
;
5939 exp
->X_op_symbol
= GOT_symbol
;
5940 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
5941 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
5942 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5943 i
.reloc
[this_operand
] = BFD_RELOC_64
;
5945 i
.reloc
[this_operand
] = BFD_RELOC_32
;
5948 else if (exp
->X_op
== O_absent
5949 || exp
->X_op
== O_illegal
5950 || exp
->X_op
== O_big
5951 || (gotfree_input_line
5952 && (exp
->X_op
== O_constant
5953 || exp
->X_op
== O_register
)))
5956 as_bad (_("missing or invalid displacement expression `%s'"),
5961 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5962 else if (exp
->X_op
!= O_constant
5963 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
5964 && exp_seg
!= absolute_section
5965 && exp_seg
!= text_section
5966 && exp_seg
!= data_section
5967 && exp_seg
!= bss_section
5968 && exp_seg
!= undefined_section
5969 && !bfd_is_com_section (exp_seg
))
5971 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5976 RESTORE_END_STRING (disp_end
);
5978 /* Check if this is a displacement only operand. */
5979 bigdisp
= i
.types
[this_operand
];
5980 bigdisp
.bitfield
.disp8
= 0;
5981 bigdisp
.bitfield
.disp16
= 0;
5982 bigdisp
.bitfield
.disp32
= 0;
5983 bigdisp
.bitfield
.disp32s
= 0;
5984 bigdisp
.bitfield
.disp64
= 0;
5985 if (UINTS_ALL_ZERO (bigdisp
))
5986 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5992 /* Make sure the memory operand we've been dealt is valid.
5993 Return 1 on success, 0 on a failure. */
5996 i386_index_check (const char *operand_string
)
5999 #if INFER_ADDR_PREFIX
6005 if (flag_code
== CODE_64BIT
)
6008 && ((i
.prefix
[ADDR_PREFIX
] == 0
6009 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6010 || (i
.prefix
[ADDR_PREFIX
]
6011 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6013 || i
.base_reg
->reg_num
!=
6014 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6016 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6017 || (i
.prefix
[ADDR_PREFIX
] == 0
6018 && i
.index_reg
->reg_num
!= RegRiz
6019 && !i
.index_reg
->reg_type
.bitfield
.reg64
6021 || (i
.prefix
[ADDR_PREFIX
]
6022 && i
.index_reg
->reg_num
!= RegEiz
6023 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6028 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6032 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6033 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6035 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6036 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6038 && i
.base_reg
->reg_num
< 6
6039 && i
.index_reg
->reg_num
>= 6
6040 && i
.log2_scale_factor
== 0))))
6047 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6049 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6050 && i
.index_reg
->reg_num
!= RegEiz
)
6051 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6057 #if INFER_ADDR_PREFIX
6058 if (i
.prefix
[ADDR_PREFIX
] == 0)
6060 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6062 /* Change the size of any displacement too. At most one of
6063 Disp16 or Disp32 is set.
6064 FIXME. There doesn't seem to be any real need for separate
6065 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6066 Removing them would probably clean up the code quite a lot. */
6067 if (flag_code
!= CODE_64BIT
6068 && (i
.types
[this_operand
].bitfield
.disp16
6069 || i
.types
[this_operand
].bitfield
.disp32
))
6070 i
.types
[this_operand
]
6071 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6076 as_bad (_("`%s' is not a valid base/index expression"),
6080 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6082 flag_code_names
[flag_code
]);
6087 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6091 i386_operand (char *operand_string
)
6095 char *op_string
= operand_string
;
6097 if (is_space_char (*op_string
))
6100 /* We check for an absolute prefix (differentiating,
6101 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6102 if (*op_string
== ABSOLUTE_PREFIX
)
6105 if (is_space_char (*op_string
))
6107 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6110 /* Check if operand is a register. */
6111 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6113 i386_operand_type temp
;
6115 /* Check for a segment override by searching for ':' after a
6116 segment register. */
6118 if (is_space_char (*op_string
))
6120 if (*op_string
== ':'
6121 && (r
->reg_type
.bitfield
.sreg2
6122 || r
->reg_type
.bitfield
.sreg3
))
6127 i
.seg
[i
.mem_operands
] = &es
;
6130 i
.seg
[i
.mem_operands
] = &cs
;
6133 i
.seg
[i
.mem_operands
] = &ss
;
6136 i
.seg
[i
.mem_operands
] = &ds
;
6139 i
.seg
[i
.mem_operands
] = &fs
;
6142 i
.seg
[i
.mem_operands
] = &gs
;
6146 /* Skip the ':' and whitespace. */
6148 if (is_space_char (*op_string
))
6151 if (!is_digit_char (*op_string
)
6152 && !is_identifier_char (*op_string
)
6153 && *op_string
!= '('
6154 && *op_string
!= ABSOLUTE_PREFIX
)
6156 as_bad (_("bad memory operand `%s'"), op_string
);
6159 /* Handle case of %es:*foo. */
6160 if (*op_string
== ABSOLUTE_PREFIX
)
6163 if (is_space_char (*op_string
))
6165 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6167 goto do_memory_reference
;
6171 as_bad (_("junk `%s' after register"), op_string
);
6175 temp
.bitfield
.baseindex
= 0;
6176 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6178 i
.op
[this_operand
].regs
= r
;
6181 else if (*op_string
== REGISTER_PREFIX
)
6183 as_bad (_("bad register name `%s'"), op_string
);
6186 else if (*op_string
== IMMEDIATE_PREFIX
)
6189 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6191 as_bad (_("immediate operand illegal with absolute jump"));
6194 if (!i386_immediate (op_string
))
6197 else if (is_digit_char (*op_string
)
6198 || is_identifier_char (*op_string
)
6199 || *op_string
== '(')
6201 /* This is a memory reference of some sort. */
6204 /* Start and end of displacement string expression (if found). */
6205 char *displacement_string_start
;
6206 char *displacement_string_end
;
6208 do_memory_reference
:
6209 if ((i
.mem_operands
== 1
6210 && !current_templates
->start
->opcode_modifier
.isstring
)
6211 || i
.mem_operands
== 2)
6213 as_bad (_("too many memory references for `%s'"),
6214 current_templates
->start
->name
);
6218 /* Check for base index form. We detect the base index form by
6219 looking for an ')' at the end of the operand, searching
6220 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6222 base_string
= op_string
+ strlen (op_string
);
6225 if (is_space_char (*base_string
))
6228 /* If we only have a displacement, set-up for it to be parsed later. */
6229 displacement_string_start
= op_string
;
6230 displacement_string_end
= base_string
+ 1;
6232 if (*base_string
== ')')
6235 unsigned int parens_balanced
= 1;
6236 /* We've already checked that the number of left & right ()'s are
6237 equal, so this loop will not be infinite. */
6241 if (*base_string
== ')')
6243 if (*base_string
== '(')
6246 while (parens_balanced
);
6248 temp_string
= base_string
;
6250 /* Skip past '(' and whitespace. */
6252 if (is_space_char (*base_string
))
6255 if (*base_string
== ','
6256 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6259 displacement_string_end
= temp_string
;
6261 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6265 base_string
= end_op
;
6266 if (is_space_char (*base_string
))
6270 /* There may be an index reg or scale factor here. */
6271 if (*base_string
== ',')
6274 if (is_space_char (*base_string
))
6277 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6280 base_string
= end_op
;
6281 if (is_space_char (*base_string
))
6283 if (*base_string
== ',')
6286 if (is_space_char (*base_string
))
6289 else if (*base_string
!= ')')
6291 as_bad (_("expecting `,' or `)' "
6292 "after index register in `%s'"),
6297 else if (*base_string
== REGISTER_PREFIX
)
6299 as_bad (_("bad register name `%s'"), base_string
);
6303 /* Check for scale factor. */
6304 if (*base_string
!= ')')
6306 char *end_scale
= i386_scale (base_string
);
6311 base_string
= end_scale
;
6312 if (is_space_char (*base_string
))
6314 if (*base_string
!= ')')
6316 as_bad (_("expecting `)' "
6317 "after scale factor in `%s'"),
6322 else if (!i
.index_reg
)
6324 as_bad (_("expecting index register or scale factor "
6325 "after `,'; got '%c'"),
6330 else if (*base_string
!= ')')
6332 as_bad (_("expecting `,' or `)' "
6333 "after base register in `%s'"),
6338 else if (*base_string
== REGISTER_PREFIX
)
6340 as_bad (_("bad register name `%s'"), base_string
);
6345 /* If there's an expression beginning the operand, parse it,
6346 assuming displacement_string_start and
6347 displacement_string_end are meaningful. */
6348 if (displacement_string_start
!= displacement_string_end
)
6350 if (!i386_displacement (displacement_string_start
,
6351 displacement_string_end
))
6355 /* Special case for (%dx) while doing input/output op. */
6357 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
6359 && i
.log2_scale_factor
== 0
6360 && i
.seg
[i
.mem_operands
] == 0
6361 && !operand_type_check (i
.types
[this_operand
], disp
))
6363 UINTS_CLEAR (i
.types
[this_operand
]);
6364 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
6368 if (i386_index_check (operand_string
) == 0)
6374 /* It's not a memory operand; argh! */
6375 as_bad (_("invalid char %s beginning operand %d `%s'"),
6376 output_invalid (*op_string
),
6381 return 1; /* Normal return. */
6384 /* md_estimate_size_before_relax()
6386 Called just before relax() for rs_machine_dependent frags. The x86
6387 assembler uses these frags to handle variable size jump
6390 Any symbol that is now undefined will not become defined.
6391 Return the correct fr_subtype in the frag.
6392 Return the initial "guess for variable size of frag" to caller.
6393 The guess is actually the growth beyond the fixed part. Whatever
6394 we do to grow the fixed or variable part contributes to our
6398 md_estimate_size_before_relax (fragP
, segment
)
6402 /* We've already got fragP->fr_subtype right; all we have to do is
6403 check for un-relaxable symbols. On an ELF system, we can't relax
6404 an externally visible symbol, because it may be overridden by a
6406 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6409 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6410 || S_IS_WEAK (fragP
->fr_symbol
)))
6414 /* Symbol is undefined in this segment, or we need to keep a
6415 reloc so that weak symbols can be overridden. */
6416 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6417 enum bfd_reloc_code_real reloc_type
;
6418 unsigned char *opcode
;
6421 if (fragP
->fr_var
!= NO_RELOC
)
6422 reloc_type
= fragP
->fr_var
;
6424 reloc_type
= BFD_RELOC_16_PCREL
;
6426 reloc_type
= BFD_RELOC_32_PCREL
;
6428 old_fr_fix
= fragP
->fr_fix
;
6429 opcode
= (unsigned char *) fragP
->fr_opcode
;
6431 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6434 /* Make jmp (0xeb) a (d)word displacement jump. */
6436 fragP
->fr_fix
+= size
;
6437 fix_new (fragP
, old_fr_fix
, size
,
6439 fragP
->fr_offset
, 1,
6445 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6447 /* Negate the condition, and branch past an
6448 unconditional jump. */
6451 /* Insert an unconditional jump. */
6453 /* We added two extra opcode bytes, and have a two byte
6455 fragP
->fr_fix
+= 2 + 2;
6456 fix_new (fragP
, old_fr_fix
+ 2, 2,
6458 fragP
->fr_offset
, 1,
6465 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6470 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6472 fragP
->fr_offset
, 1,
6474 fixP
->fx_signed
= 1;
6478 /* This changes the byte-displacement jump 0x7N
6479 to the (d)word-displacement jump 0x0f,0x8N. */
6480 opcode
[1] = opcode
[0] + 0x10;
6481 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6482 /* We've added an opcode byte. */
6483 fragP
->fr_fix
+= 1 + size
;
6484 fix_new (fragP
, old_fr_fix
+ 1, size
,
6486 fragP
->fr_offset
, 1,
6491 BAD_CASE (fragP
->fr_subtype
);
6495 return fragP
->fr_fix
- old_fr_fix
;
6498 /* Guess size depending on current relax state. Initially the relax
6499 state will correspond to a short jump and we return 1, because
6500 the variable part of the frag (the branch offset) is one byte
6501 long. However, we can relax a section more than once and in that
6502 case we must either set fr_subtype back to the unrelaxed state,
6503 or return the value for the appropriate branch. */
6504 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6507 /* Called after relax() is finished.
6509 In: Address of frag.
6510 fr_type == rs_machine_dependent.
6511 fr_subtype is what the address relaxed to.
6513 Out: Any fixSs and constants are set up.
6514 Caller will turn frag into a ".space 0". */
6517 md_convert_frag (abfd
, sec
, fragP
)
6518 bfd
*abfd ATTRIBUTE_UNUSED
;
6519 segT sec ATTRIBUTE_UNUSED
;
6522 unsigned char *opcode
;
6523 unsigned char *where_to_put_displacement
= NULL
;
6524 offsetT target_address
;
6525 offsetT opcode_address
;
6526 unsigned int extension
= 0;
6527 offsetT displacement_from_opcode_start
;
6529 opcode
= (unsigned char *) fragP
->fr_opcode
;
6531 /* Address we want to reach in file space. */
6532 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6534 /* Address opcode resides at in file space. */
6535 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6537 /* Displacement from opcode start to fill into instruction. */
6538 displacement_from_opcode_start
= target_address
- opcode_address
;
6540 if ((fragP
->fr_subtype
& BIG
) == 0)
6542 /* Don't have to change opcode. */
6543 extension
= 1; /* 1 opcode + 1 displacement */
6544 where_to_put_displacement
= &opcode
[1];
6548 if (no_cond_jump_promotion
6549 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6550 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6551 _("long jump required"));
6553 switch (fragP
->fr_subtype
)
6555 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6556 extension
= 4; /* 1 opcode + 4 displacement */
6558 where_to_put_displacement
= &opcode
[1];
6561 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6562 extension
= 2; /* 1 opcode + 2 displacement */
6564 where_to_put_displacement
= &opcode
[1];
6567 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6568 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6569 extension
= 5; /* 2 opcode + 4 displacement */
6570 opcode
[1] = opcode
[0] + 0x10;
6571 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6572 where_to_put_displacement
= &opcode
[2];
6575 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6576 extension
= 3; /* 2 opcode + 2 displacement */
6577 opcode
[1] = opcode
[0] + 0x10;
6578 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6579 where_to_put_displacement
= &opcode
[2];
6582 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6587 where_to_put_displacement
= &opcode
[3];
6591 BAD_CASE (fragP
->fr_subtype
);
6596 /* If size if less then four we are sure that the operand fits,
6597 but if it's 4, then it could be that the displacement is larger
6599 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6601 && ((addressT
) (displacement_from_opcode_start
- extension
6602 + ((addressT
) 1 << 31))
6603 > (((addressT
) 2 << 31) - 1)))
6605 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6606 _("jump target out of range"));
6607 /* Make us emit 0. */
6608 displacement_from_opcode_start
= extension
;
6610 /* Now put displacement after opcode. */
6611 md_number_to_chars ((char *) where_to_put_displacement
,
6612 (valueT
) (displacement_from_opcode_start
- extension
),
6613 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6614 fragP
->fr_fix
+= extension
;
6617 /* Apply a fixup (fixS) to segment data, once it has been determined
6618 by our caller that we have all the info we need to fix it up.
6620 On the 386, immediates, displacements, and data pointers are all in
6621 the same (little-endian) format, so we don't need to care about which
6625 md_apply_fix (fixP
, valP
, seg
)
6626 /* The fix we're to put in. */
6628 /* Pointer to the value of the bits. */
6630 /* Segment fix is from. */
6631 segT seg ATTRIBUTE_UNUSED
;
6633 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6634 valueT value
= *valP
;
6636 #if !defined (TE_Mach)
6639 switch (fixP
->fx_r_type
)
6645 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6648 case BFD_RELOC_X86_64_32S
:
6649 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6652 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6655 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6660 if (fixP
->fx_addsy
!= NULL
6661 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6662 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6663 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6664 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6665 && !use_rela_relocations
)
6667 /* This is a hack. There should be a better way to handle this.
6668 This covers for the fact that bfd_install_relocation will
6669 subtract the current location (for partial_inplace, PC relative
6670 relocations); see more below. */
6674 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6677 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6682 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6685 || (symbol_section_p (fixP
->fx_addsy
)
6686 && sym_seg
!= absolute_section
))
6687 && !generic_force_reloc (fixP
))
6689 /* Yes, we add the values in twice. This is because
6690 bfd_install_relocation subtracts them out again. I think
6691 bfd_install_relocation is broken, but I don't dare change
6693 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6697 #if defined (OBJ_COFF) && defined (TE_PE)
6698 /* For some reason, the PE format does not store a
6699 section address offset for a PC relative symbol. */
6700 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6701 || S_IS_WEAK (fixP
->fx_addsy
))
6702 value
+= md_pcrel_from (fixP
);
6706 /* Fix a few things - the dynamic linker expects certain values here,
6707 and we must not disappoint it. */
6708 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6709 if (IS_ELF
&& fixP
->fx_addsy
)
6710 switch (fixP
->fx_r_type
)
6712 case BFD_RELOC_386_PLT32
:
6713 case BFD_RELOC_X86_64_PLT32
:
6714 /* Make the jump instruction point to the address of the operand. At
6715 runtime we merely add the offset to the actual PLT entry. */
6719 case BFD_RELOC_386_TLS_GD
:
6720 case BFD_RELOC_386_TLS_LDM
:
6721 case BFD_RELOC_386_TLS_IE_32
:
6722 case BFD_RELOC_386_TLS_IE
:
6723 case BFD_RELOC_386_TLS_GOTIE
:
6724 case BFD_RELOC_386_TLS_GOTDESC
:
6725 case BFD_RELOC_X86_64_TLSGD
:
6726 case BFD_RELOC_X86_64_TLSLD
:
6727 case BFD_RELOC_X86_64_GOTTPOFF
:
6728 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6729 value
= 0; /* Fully resolved at runtime. No addend. */
6731 case BFD_RELOC_386_TLS_LE
:
6732 case BFD_RELOC_386_TLS_LDO_32
:
6733 case BFD_RELOC_386_TLS_LE_32
:
6734 case BFD_RELOC_X86_64_DTPOFF32
:
6735 case BFD_RELOC_X86_64_DTPOFF64
:
6736 case BFD_RELOC_X86_64_TPOFF32
:
6737 case BFD_RELOC_X86_64_TPOFF64
:
6738 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6741 case BFD_RELOC_386_TLS_DESC_CALL
:
6742 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6743 value
= 0; /* Fully resolved at runtime. No addend. */
6744 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6748 case BFD_RELOC_386_GOT32
:
6749 case BFD_RELOC_X86_64_GOT32
:
6750 value
= 0; /* Fully resolved at runtime. No addend. */
6753 case BFD_RELOC_VTABLE_INHERIT
:
6754 case BFD_RELOC_VTABLE_ENTRY
:
6761 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6763 #endif /* !defined (TE_Mach) */
6765 /* Are we finished with this relocation now? */
6766 if (fixP
->fx_addsy
== NULL
)
6768 else if (use_rela_relocations
)
6770 fixP
->fx_no_overflow
= 1;
6771 /* Remember value for tc_gen_reloc. */
6772 fixP
->fx_addnumber
= value
;
6776 md_number_to_chars (p
, value
, fixP
->fx_size
);
6780 md_atof (int type
, char *litP
, int *sizeP
)
6782 /* This outputs the LITTLENUMs in REVERSE order;
6783 in accord with the bigendian 386. */
6784 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
6787 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6790 output_invalid (int c
)
6793 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6796 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6797 "(0x%x)", (unsigned char) c
);
6798 return output_invalid_buf
;
6801 /* REG_STRING starts *before* REGISTER_PREFIX. */
6803 static const reg_entry
*
6804 parse_real_register (char *reg_string
, char **end_op
)
6806 char *s
= reg_string
;
6808 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6811 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6812 if (*s
== REGISTER_PREFIX
)
6815 if (is_space_char (*s
))
6819 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6821 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6822 return (const reg_entry
*) NULL
;
6826 /* For naked regs, make sure that we are not dealing with an identifier.
6827 This prevents confusing an identifier like `eax_var' with register
6829 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6830 return (const reg_entry
*) NULL
;
6834 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6836 /* Handle floating point regs, allowing spaces in the (i) part. */
6837 if (r
== i386_regtab
/* %st is first entry of table */)
6839 if (is_space_char (*s
))
6844 if (is_space_char (*s
))
6846 if (*s
>= '0' && *s
<= '7')
6850 if (is_space_char (*s
))
6855 r
= hash_find (reg_hash
, "st(0)");
6860 /* We have "%st(" then garbage. */
6861 return (const reg_entry
*) NULL
;
6865 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6868 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
6869 return (const reg_entry
*) NULL
;
6872 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6873 || r
->reg_type
.bitfield
.reg64
)
6874 && (!cpu_arch_flags
.bitfield
.cpulm
6875 || !UINTS_EQUAL (r
->reg_type
, control
))
6876 && flag_code
!= CODE_64BIT
)
6877 return (const reg_entry
*) NULL
;
6882 /* REG_STRING starts *before* REGISTER_PREFIX. */
6884 static const reg_entry
*
6885 parse_register (char *reg_string
, char **end_op
)
6889 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6890 r
= parse_real_register (reg_string
, end_op
);
6895 char *save
= input_line_pointer
;
6899 input_line_pointer
= reg_string
;
6900 c
= get_symbol_end ();
6901 symbolP
= symbol_find (reg_string
);
6902 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6904 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6906 know (e
->X_op
== O_register
);
6907 know (e
->X_add_number
>= 0
6908 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6909 r
= i386_regtab
+ e
->X_add_number
;
6910 *end_op
= input_line_pointer
;
6912 *input_line_pointer
= c
;
6913 input_line_pointer
= save
;
6919 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6922 char *end
= input_line_pointer
;
6925 r
= parse_register (name
, &input_line_pointer
);
6926 if (r
&& end
<= input_line_pointer
)
6928 *nextcharP
= *input_line_pointer
;
6929 *input_line_pointer
= 0;
6930 e
->X_op
= O_register
;
6931 e
->X_add_number
= r
- i386_regtab
;
6934 input_line_pointer
= end
;
6940 md_operand (expressionS
*e
)
6942 if (*input_line_pointer
== REGISTER_PREFIX
)
6945 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
6949 e
->X_op
= O_register
;
6950 e
->X_add_number
= r
- i386_regtab
;
6951 input_line_pointer
= end
;
6957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6958 const char *md_shortopts
= "kVQ:sqn";
6960 const char *md_shortopts
= "qn";
6963 #define OPTION_32 (OPTION_MD_BASE + 0)
6964 #define OPTION_64 (OPTION_MD_BASE + 1)
6965 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6966 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6967 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6968 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6969 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6970 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6971 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6972 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6974 struct option md_longopts
[] =
6976 {"32", no_argument
, NULL
, OPTION_32
},
6977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6978 {"64", no_argument
, NULL
, OPTION_64
},
6980 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
6981 {"march", required_argument
, NULL
, OPTION_MARCH
},
6982 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
6983 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
6984 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
6985 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
6986 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
6987 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
6988 {NULL
, no_argument
, NULL
, 0}
6990 size_t md_longopts_size
= sizeof (md_longopts
);
6993 md_parse_option (int c
, char *arg
)
7000 optimize_align_code
= 0;
7007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7008 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7009 should be emitted or not. FIXME: Not implemented. */
7013 /* -V: SVR4 argument to print version ID. */
7015 print_version_id ();
7018 /* -k: Ignore for FreeBSD compatibility. */
7023 /* -s: On i386 Solaris, this tells the native assembler to use
7024 .stab instead of .stab.excl. We always use .stab anyhow. */
7027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7030 const char **list
, **l
;
7032 list
= bfd_target_list ();
7033 for (l
= list
; *l
!= NULL
; l
++)
7034 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7035 || strcmp (*l
, "coff-x86-64") == 0
7036 || strcmp (*l
, "pe-x86-64") == 0
7037 || strcmp (*l
, "pei-x86-64") == 0)
7039 default_arch
= "x86_64";
7043 as_fatal (_("No compiled in support for x86_64"));
7050 default_arch
= "i386";
7054 #ifdef SVR4_COMMENT_CHARS
7059 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7061 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7065 i386_comment_chars
= n
;
7072 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7073 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7075 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7077 cpu_arch_isa
= cpu_arch
[i
].type
;
7078 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7079 if (!cpu_arch_tune_set
)
7081 cpu_arch_tune
= cpu_arch_isa
;
7082 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7087 if (i
>= ARRAY_SIZE (cpu_arch
))
7088 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7093 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7094 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7096 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7098 cpu_arch_tune_set
= 1;
7099 cpu_arch_tune
= cpu_arch
[i
].type
;
7100 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7104 if (i
>= ARRAY_SIZE (cpu_arch
))
7105 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7108 case OPTION_MMNEMONIC
:
7109 if (strcasecmp (arg
, "att") == 0)
7111 else if (strcasecmp (arg
, "intel") == 0)
7114 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7117 case OPTION_MSYNTAX
:
7118 if (strcasecmp (arg
, "att") == 0)
7120 else if (strcasecmp (arg
, "intel") == 0)
7123 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7126 case OPTION_MINDEX_REG
:
7127 allow_index_reg
= 1;
7130 case OPTION_MNAKED_REG
:
7131 allow_naked_reg
= 1;
7134 case OPTION_MOLD_GCC
:
7146 md_show_usage (stream
)
7149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7150 fprintf (stream
, _("\
7152 -V print assembler version number\n\
7155 fprintf (stream
, _("\
7156 -n Do not optimize code alignment\n\
7157 -q quieten some warnings\n"));
7158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7159 fprintf (stream
, _("\
7162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7163 fprintf (stream
, _("\
7164 --32/--64 generate 32bit/64bit code\n"));
7166 #ifdef SVR4_COMMENT_CHARS
7167 fprintf (stream
, _("\
7168 --divide do not treat `/' as a comment character\n"));
7170 fprintf (stream
, _("\
7171 --divide ignored\n"));
7173 fprintf (stream
, _("\
7174 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7175 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7176 core, core2, k6, athlon, k8, generic32, generic64\n"));
7177 fprintf (stream
, _("\
7178 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7179 fprintf (stream
, _("\
7180 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7181 fprintf (stream
, _("\
7182 -mindex-reg support pseudo index registers\n"));
7183 fprintf (stream
, _("\
7184 -mnaked-reg don't require `%%' prefix for registers\n"));
7185 fprintf (stream
, _("\
7186 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7189 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7190 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7192 /* Pick the target format to use. */
7195 i386_target_format (void)
7197 if (!strcmp (default_arch
, "x86_64"))
7199 set_code_flag (CODE_64BIT
);
7200 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7202 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7203 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7204 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7205 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7206 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7207 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7208 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
7209 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7210 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
7211 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7212 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7214 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7216 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7217 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7218 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7219 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7220 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7221 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7222 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
7223 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7224 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
7225 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7226 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7229 else if (!strcmp (default_arch
, "i386"))
7231 set_code_flag (CODE_32BIT
);
7232 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7234 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7235 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7236 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7238 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7240 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7241 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7242 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7246 as_fatal (_("Unknown architecture"));
7247 switch (OUTPUT_FLAVOR
)
7250 case bfd_target_coff_flavour
:
7251 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
7254 #ifdef OBJ_MAYBE_AOUT
7255 case bfd_target_aout_flavour
:
7256 return AOUT_TARGET_FORMAT
;
7258 #ifdef OBJ_MAYBE_COFF
7259 case bfd_target_coff_flavour
:
7262 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7263 case bfd_target_elf_flavour
:
7265 if (flag_code
== CODE_64BIT
)
7268 use_rela_relocations
= 1;
7270 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7279 #endif /* OBJ_MAYBE_ more than one */
7281 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7283 i386_elf_emit_arch_note (void)
7285 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7288 asection
*seg
= now_seg
;
7289 subsegT subseg
= now_subseg
;
7290 Elf_Internal_Note i_note
;
7291 Elf_External_Note e_note
;
7292 asection
*note_secp
;
7295 /* Create the .note section. */
7296 note_secp
= subseg_new (".note", 0);
7297 bfd_set_section_flags (stdoutput
,
7299 SEC_HAS_CONTENTS
| SEC_READONLY
);
7301 /* Process the arch string. */
7302 len
= strlen (cpu_arch_name
);
7304 i_note
.namesz
= len
+ 1;
7306 i_note
.type
= NT_ARCH
;
7307 p
= frag_more (sizeof (e_note
.namesz
));
7308 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
7309 p
= frag_more (sizeof (e_note
.descsz
));
7310 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
7311 p
= frag_more (sizeof (e_note
.type
));
7312 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
7313 p
= frag_more (len
+ 1);
7314 strcpy (p
, cpu_arch_name
);
7316 frag_align (2, 0, 0);
7318 subseg_set (seg
, subseg
);
7324 md_undefined_symbol (name
)
7327 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
7328 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
7329 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
7330 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
7334 if (symbol_find (name
))
7335 as_bad (_("GOT already in symbol table"));
7336 GOT_symbol
= symbol_new (name
, undefined_section
,
7337 (valueT
) 0, &zero_address_frag
);
7344 /* Round up a section size to the appropriate boundary. */
7347 md_section_align (segment
, size
)
7348 segT segment ATTRIBUTE_UNUSED
;
7351 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7352 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
7354 /* For a.out, force the section size to be aligned. If we don't do
7355 this, BFD will align it for us, but it will not write out the
7356 final bytes of the section. This may be a bug in BFD, but it is
7357 easier to fix it here since that is how the other a.out targets
7361 align
= bfd_get_section_alignment (stdoutput
, segment
);
7362 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7369 /* On the i386, PC-relative offsets are relative to the start of the
7370 next instruction. That is, the address of the offset, plus its
7371 size, since the offset is always the last part of the insn. */
7374 md_pcrel_from (fixS
*fixP
)
7376 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7382 s_bss (int ignore ATTRIBUTE_UNUSED
)
7386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7388 obj_elf_section_change_hook ();
7390 temp
= get_absolute_expression ();
7391 subseg_set (bss_section
, (subsegT
) temp
);
7392 demand_empty_rest_of_line ();
7398 i386_validate_fix (fixS
*fixp
)
7400 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
7402 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
7406 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
7411 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
7413 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
7420 tc_gen_reloc (section
, fixp
)
7421 asection
*section ATTRIBUTE_UNUSED
;
7425 bfd_reloc_code_real_type code
;
7427 switch (fixp
->fx_r_type
)
7429 case BFD_RELOC_X86_64_PLT32
:
7430 case BFD_RELOC_X86_64_GOT32
:
7431 case BFD_RELOC_X86_64_GOTPCREL
:
7432 case BFD_RELOC_386_PLT32
:
7433 case BFD_RELOC_386_GOT32
:
7434 case BFD_RELOC_386_GOTOFF
:
7435 case BFD_RELOC_386_GOTPC
:
7436 case BFD_RELOC_386_TLS_GD
:
7437 case BFD_RELOC_386_TLS_LDM
:
7438 case BFD_RELOC_386_TLS_LDO_32
:
7439 case BFD_RELOC_386_TLS_IE_32
:
7440 case BFD_RELOC_386_TLS_IE
:
7441 case BFD_RELOC_386_TLS_GOTIE
:
7442 case BFD_RELOC_386_TLS_LE_32
:
7443 case BFD_RELOC_386_TLS_LE
:
7444 case BFD_RELOC_386_TLS_GOTDESC
:
7445 case BFD_RELOC_386_TLS_DESC_CALL
:
7446 case BFD_RELOC_X86_64_TLSGD
:
7447 case BFD_RELOC_X86_64_TLSLD
:
7448 case BFD_RELOC_X86_64_DTPOFF32
:
7449 case BFD_RELOC_X86_64_DTPOFF64
:
7450 case BFD_RELOC_X86_64_GOTTPOFF
:
7451 case BFD_RELOC_X86_64_TPOFF32
:
7452 case BFD_RELOC_X86_64_TPOFF64
:
7453 case BFD_RELOC_X86_64_GOTOFF64
:
7454 case BFD_RELOC_X86_64_GOTPC32
:
7455 case BFD_RELOC_X86_64_GOT64
:
7456 case BFD_RELOC_X86_64_GOTPCREL64
:
7457 case BFD_RELOC_X86_64_GOTPC64
:
7458 case BFD_RELOC_X86_64_GOTPLT64
:
7459 case BFD_RELOC_X86_64_PLTOFF64
:
7460 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7461 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7463 case BFD_RELOC_VTABLE_ENTRY
:
7464 case BFD_RELOC_VTABLE_INHERIT
:
7466 case BFD_RELOC_32_SECREL
:
7468 code
= fixp
->fx_r_type
;
7470 case BFD_RELOC_X86_64_32S
:
7471 if (!fixp
->fx_pcrel
)
7473 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7474 code
= fixp
->fx_r_type
;
7480 switch (fixp
->fx_size
)
7483 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7484 _("can not do %d byte pc-relative relocation"),
7486 code
= BFD_RELOC_32_PCREL
;
7488 case 1: code
= BFD_RELOC_8_PCREL
; break;
7489 case 2: code
= BFD_RELOC_16_PCREL
; break;
7490 case 4: code
= BFD_RELOC_32_PCREL
; break;
7492 case 8: code
= BFD_RELOC_64_PCREL
; break;
7498 switch (fixp
->fx_size
)
7501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7502 _("can not do %d byte relocation"),
7504 code
= BFD_RELOC_32
;
7506 case 1: code
= BFD_RELOC_8
; break;
7507 case 2: code
= BFD_RELOC_16
; break;
7508 case 4: code
= BFD_RELOC_32
; break;
7510 case 8: code
= BFD_RELOC_64
; break;
7517 if ((code
== BFD_RELOC_32
7518 || code
== BFD_RELOC_32_PCREL
7519 || code
== BFD_RELOC_X86_64_32S
)
7521 && fixp
->fx_addsy
== GOT_symbol
)
7524 code
= BFD_RELOC_386_GOTPC
;
7526 code
= BFD_RELOC_X86_64_GOTPC32
;
7528 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7530 && fixp
->fx_addsy
== GOT_symbol
)
7532 code
= BFD_RELOC_X86_64_GOTPC64
;
7535 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7536 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7537 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7539 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7541 if (!use_rela_relocations
)
7543 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7544 vtable entry to be used in the relocation's section offset. */
7545 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7546 rel
->address
= fixp
->fx_offset
;
7550 /* Use the rela in 64bit mode. */
7553 if (!fixp
->fx_pcrel
)
7554 rel
->addend
= fixp
->fx_offset
;
7558 case BFD_RELOC_X86_64_PLT32
:
7559 case BFD_RELOC_X86_64_GOT32
:
7560 case BFD_RELOC_X86_64_GOTPCREL
:
7561 case BFD_RELOC_X86_64_TLSGD
:
7562 case BFD_RELOC_X86_64_TLSLD
:
7563 case BFD_RELOC_X86_64_GOTTPOFF
:
7564 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7565 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7566 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7569 rel
->addend
= (section
->vma
7571 + fixp
->fx_addnumber
7572 + md_pcrel_from (fixp
));
7577 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7578 if (rel
->howto
== NULL
)
7580 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7581 _("cannot represent relocation type %s"),
7582 bfd_get_reloc_code_name (code
));
7583 /* Set howto to a garbage value so that we can keep going. */
7584 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7585 assert (rel
->howto
!= NULL
);
7592 /* Parse operands using Intel syntax. This implements a recursive descent
7593 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7596 FIXME: We do not recognize the full operand grammar defined in the MASM
7597 documentation. In particular, all the structure/union and
7598 high-level macro operands are missing.
7600 Uppercase words are terminals, lower case words are non-terminals.
7601 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7602 bars '|' denote choices. Most grammar productions are implemented in
7603 functions called 'intel_<production>'.
7605 Initial production is 'expr'.
7611 binOp & | AND | \| | OR | ^ | XOR
7613 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7615 constant digits [[ radixOverride ]]
7617 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7655 => expr expr cmpOp e04
7658 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7659 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7661 hexdigit a | b | c | d | e | f
7662 | A | B | C | D | E | F
7668 mulOp * | / | % | MOD | << | SHL | >> | SHR
7672 register specialRegister
7676 segmentRegister CS | DS | ES | FS | GS | SS
7678 specialRegister CR0 | CR2 | CR3 | CR4
7679 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7680 | TR3 | TR4 | TR5 | TR6 | TR7
7682 We simplify the grammar in obvious places (e.g., register parsing is
7683 done by calling parse_register) and eliminate immediate left recursion
7684 to implement a recursive-descent parser.
7688 expr' cmpOp e04 expr'
7739 /* Parsing structure for the intel syntax parser. Used to implement the
7740 semantic actions for the operand grammar. */
7741 struct intel_parser_s
7743 char *op_string
; /* The string being parsed. */
7744 int got_a_float
; /* Whether the operand is a float. */
7745 int op_modifier
; /* Operand modifier. */
7746 int is_mem
; /* 1 if operand is memory reference. */
7747 int in_offset
; /* >=1 if parsing operand of offset. */
7748 int in_bracket
; /* >=1 if parsing operand in brackets. */
7749 const reg_entry
*reg
; /* Last register reference found. */
7750 char *disp
; /* Displacement string being built. */
7751 char *next_operand
; /* Resume point when splitting operands. */
7754 static struct intel_parser_s intel_parser
;
7756 /* Token structure for parsing intel syntax. */
7759 int code
; /* Token code. */
7760 const reg_entry
*reg
; /* Register entry for register tokens. */
7761 char *str
; /* String representation. */
7764 static struct intel_token cur_token
, prev_token
;
7766 /* Token codes for the intel parser. Since T_SHORT is already used
7767 by COFF, undefine it first to prevent a warning. */
7786 /* Prototypes for intel parser functions. */
7787 static int intel_match_token (int);
7788 static void intel_putback_token (void);
7789 static void intel_get_token (void);
7790 static int intel_expr (void);
7791 static int intel_e04 (void);
7792 static int intel_e05 (void);
7793 static int intel_e06 (void);
7794 static int intel_e09 (void);
7795 static int intel_e10 (void);
7796 static int intel_e11 (void);
7799 i386_intel_operand (char *operand_string
, int got_a_float
)
7804 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7805 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7809 /* Initialize token holders. */
7810 cur_token
.code
= prev_token
.code
= T_NIL
;
7811 cur_token
.reg
= prev_token
.reg
= NULL
;
7812 cur_token
.str
= prev_token
.str
= NULL
;
7814 /* Initialize parser structure. */
7815 intel_parser
.got_a_float
= got_a_float
;
7816 intel_parser
.op_modifier
= 0;
7817 intel_parser
.is_mem
= 0;
7818 intel_parser
.in_offset
= 0;
7819 intel_parser
.in_bracket
= 0;
7820 intel_parser
.reg
= NULL
;
7821 intel_parser
.disp
[0] = '\0';
7822 intel_parser
.next_operand
= NULL
;
7824 /* Read the first token and start the parser. */
7826 ret
= intel_expr ();
7831 if (cur_token
.code
!= T_NIL
)
7833 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7834 current_templates
->start
->name
, cur_token
.str
);
7837 /* If we found a memory reference, hand it over to i386_displacement
7838 to fill in the rest of the operand fields. */
7839 else if (intel_parser
.is_mem
)
7841 if ((i
.mem_operands
== 1
7842 && !current_templates
->start
->opcode_modifier
.isstring
)
7843 || i
.mem_operands
== 2)
7845 as_bad (_("too many memory references for '%s'"),
7846 current_templates
->start
->name
);
7851 char *s
= intel_parser
.disp
;
7854 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7855 /* See the comments in intel_bracket_expr. */
7856 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7858 /* Add the displacement expression. */
7860 ret
= i386_displacement (s
, s
+ strlen (s
));
7863 /* Swap base and index in 16-bit memory operands like
7864 [si+bx]. Since i386_index_check is also used in AT&T
7865 mode we have to do that here. */
7868 && i
.base_reg
->reg_type
.bitfield
.reg16
7869 && i
.index_reg
->reg_type
.bitfield
.reg16
7870 && i
.base_reg
->reg_num
>= 6
7871 && i
.index_reg
->reg_num
< 6)
7873 const reg_entry
*base
= i
.index_reg
;
7875 i
.index_reg
= i
.base_reg
;
7878 ret
= i386_index_check (operand_string
);
7883 /* Constant and OFFSET expressions are handled by i386_immediate. */
7884 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7885 || intel_parser
.reg
== NULL
)
7886 ret
= i386_immediate (intel_parser
.disp
);
7888 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7890 if (!ret
|| !intel_parser
.next_operand
)
7892 intel_parser
.op_string
= intel_parser
.next_operand
;
7893 this_operand
= i
.operands
++;
7897 free (intel_parser
.disp
);
7902 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7906 expr' cmpOp e04 expr'
7911 /* XXX Implement the comparison operators. */
7912 return intel_e04 ();
7929 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7930 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7932 if (cur_token
.code
== '+')
7934 else if (cur_token
.code
== '-')
7935 nregs
= NUM_ADDRESS_REGS
;
7939 strcat (intel_parser
.disp
, cur_token
.str
);
7940 intel_match_token (cur_token
.code
);
7951 int nregs
= ~NUM_ADDRESS_REGS
;
7958 if (cur_token
.code
== '&'
7959 || cur_token
.code
== '|'
7960 || cur_token
.code
== '^')
7964 str
[0] = cur_token
.code
;
7966 strcat (intel_parser
.disp
, str
);
7971 intel_match_token (cur_token
.code
);
7976 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7977 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
7988 int nregs
= ~NUM_ADDRESS_REGS
;
7995 if (cur_token
.code
== '*'
7996 || cur_token
.code
== '/'
7997 || cur_token
.code
== '%')
8001 str
[0] = cur_token
.code
;
8003 strcat (intel_parser
.disp
, str
);
8005 else if (cur_token
.code
== T_SHL
)
8006 strcat (intel_parser
.disp
, "<<");
8007 else if (cur_token
.code
== T_SHR
)
8008 strcat (intel_parser
.disp
, ">>");
8012 intel_match_token (cur_token
.code
);
8017 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8018 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8036 int nregs
= ~NUM_ADDRESS_REGS
;
8041 /* Don't consume constants here. */
8042 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8044 /* Need to look one token ahead - if the next token
8045 is a constant, the current token is its sign. */
8048 intel_match_token (cur_token
.code
);
8049 next_code
= cur_token
.code
;
8050 intel_putback_token ();
8051 if (next_code
== T_CONST
)
8055 /* e09 OFFSET e09 */
8056 if (cur_token
.code
== T_OFFSET
)
8059 ++intel_parser
.in_offset
;
8063 else if (cur_token
.code
== T_SHORT
)
8064 intel_parser
.op_modifier
|= 1 << T_SHORT
;
8067 else if (cur_token
.code
== '+')
8068 strcat (intel_parser
.disp
, "+");
8073 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
8079 str
[0] = cur_token
.code
;
8081 strcat (intel_parser
.disp
, str
);
8088 intel_match_token (cur_token
.code
);
8096 /* e09' PTR e10 e09' */
8097 if (cur_token
.code
== T_PTR
)
8101 if (prev_token
.code
== T_BYTE
)
8102 suffix
= BYTE_MNEM_SUFFIX
;
8104 else if (prev_token
.code
== T_WORD
)
8106 if (current_templates
->start
->name
[0] == 'l'
8107 && current_templates
->start
->name
[2] == 's'
8108 && current_templates
->start
->name
[3] == 0)
8109 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8110 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
8111 suffix
= SHORT_MNEM_SUFFIX
;
8113 suffix
= WORD_MNEM_SUFFIX
;
8116 else if (prev_token
.code
== T_DWORD
)
8118 if (current_templates
->start
->name
[0] == 'l'
8119 && current_templates
->start
->name
[2] == 's'
8120 && current_templates
->start
->name
[3] == 0)
8121 suffix
= WORD_MNEM_SUFFIX
;
8122 else if (flag_code
== CODE_16BIT
8123 && (current_templates
->start
->opcode_modifier
.jump
8124 || current_templates
->start
->opcode_modifier
.jumpdword
))
8125 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8126 else if (intel_parser
.got_a_float
== 1) /* "f..." */
8127 suffix
= SHORT_MNEM_SUFFIX
;
8129 suffix
= LONG_MNEM_SUFFIX
;
8132 else if (prev_token
.code
== T_FWORD
)
8134 if (current_templates
->start
->name
[0] == 'l'
8135 && current_templates
->start
->name
[2] == 's'
8136 && current_templates
->start
->name
[3] == 0)
8137 suffix
= LONG_MNEM_SUFFIX
;
8138 else if (!intel_parser
.got_a_float
)
8140 if (flag_code
== CODE_16BIT
)
8141 add_prefix (DATA_PREFIX_OPCODE
);
8142 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8145 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8148 else if (prev_token
.code
== T_QWORD
)
8150 if (intel_parser
.got_a_float
== 1) /* "f..." */
8151 suffix
= LONG_MNEM_SUFFIX
;
8153 suffix
= QWORD_MNEM_SUFFIX
;
8156 else if (prev_token
.code
== T_TBYTE
)
8158 if (intel_parser
.got_a_float
== 1)
8159 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8161 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8164 else if (prev_token
.code
== T_XMMWORD
)
8166 suffix
= XMMWORD_MNEM_SUFFIX
;
8171 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
8175 /* Operands for jump/call using 'ptr' notation denote absolute
8177 if (current_templates
->start
->opcode_modifier
.jump
8178 || current_templates
->start
->opcode_modifier
.jumpdword
)
8179 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8181 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
8185 else if (i
.suffix
!= suffix
)
8187 as_bad (_("Conflicting operand modifiers"));
8193 /* e09' : e10 e09' */
8194 else if (cur_token
.code
== ':')
8196 if (prev_token
.code
!= T_REG
)
8198 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8199 segment/group identifier (which we don't have), using comma
8200 as the operand separator there is even less consistent, since
8201 there all branches only have a single operand. */
8202 if (this_operand
!= 0
8203 || intel_parser
.in_offset
8204 || intel_parser
.in_bracket
8205 || (!current_templates
->start
->opcode_modifier
.jump
8206 && !current_templates
->start
->opcode_modifier
.jumpdword
8207 && !current_templates
->start
->opcode_modifier
.jumpintersegment
8208 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
8209 return intel_match_token (T_NIL
);
8210 /* Remember the start of the 2nd operand and terminate 1st
8212 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8213 another expression), but it gets at least the simplest case
8214 (a plain number or symbol on the left side) right. */
8215 intel_parser
.next_operand
= intel_parser
.op_string
;
8216 *--intel_parser
.op_string
= '\0';
8217 return intel_match_token (':');
8225 intel_match_token (cur_token
.code
);
8231 --intel_parser
.in_offset
;
8234 if (NUM_ADDRESS_REGS
> nregs
)
8236 as_bad (_("Invalid operand to `OFFSET'"));
8239 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
8242 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8243 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
8248 intel_bracket_expr (void)
8250 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
8251 const char *start
= intel_parser
.op_string
;
8254 if (i
.op
[this_operand
].regs
)
8255 return intel_match_token (T_NIL
);
8257 intel_match_token ('[');
8259 /* Mark as a memory operand only if it's not already known to be an
8260 offset expression. If it's an offset expression, we need to keep
8262 if (!intel_parser
.in_offset
)
8264 ++intel_parser
.in_bracket
;
8266 /* Operands for jump/call inside brackets denote absolute addresses. */
8267 if (current_templates
->start
->opcode_modifier
.jump
8268 || current_templates
->start
->opcode_modifier
.jumpdword
)
8269 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8271 /* Unfortunately gas always diverged from MASM in a respect that can't
8272 be easily fixed without risking to break code sequences likely to be
8273 encountered (the testsuite even check for this): MASM doesn't consider
8274 an expression inside brackets unconditionally as a memory reference.
8275 When that is e.g. a constant, an offset expression, or the sum of the
8276 two, this is still taken as a constant load. gas, however, always
8277 treated these as memory references. As a compromise, we'll try to make
8278 offset expressions inside brackets work the MASM way (since that's
8279 less likely to be found in real world code), but make constants alone
8280 continue to work the traditional gas way. In either case, issue a
8282 intel_parser
.op_modifier
&= ~was_offset
;
8285 strcat (intel_parser
.disp
, "[");
8287 /* Add a '+' to the displacement string if necessary. */
8288 if (*intel_parser
.disp
!= '\0'
8289 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
8290 strcat (intel_parser
.disp
, "+");
8293 && (len
= intel_parser
.op_string
- start
- 1,
8294 intel_match_token (']')))
8296 /* Preserve brackets when the operand is an offset expression. */
8297 if (intel_parser
.in_offset
)
8298 strcat (intel_parser
.disp
, "]");
8301 --intel_parser
.in_bracket
;
8302 if (i
.base_reg
|| i
.index_reg
)
8303 intel_parser
.is_mem
= 1;
8304 if (!intel_parser
.is_mem
)
8306 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8307 /* Defer the warning until all of the operand was parsed. */
8308 intel_parser
.is_mem
= -1;
8309 else if (!quiet_warnings
)
8310 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8311 len
, start
, len
, start
);
8314 intel_parser
.op_modifier
|= was_offset
;
8331 while (cur_token
.code
== '[')
8333 if (!intel_bracket_expr ())
8358 switch (cur_token
.code
)
8362 intel_match_token ('(');
8363 strcat (intel_parser
.disp
, "(");
8365 if (intel_expr () && intel_match_token (')'))
8367 strcat (intel_parser
.disp
, ")");
8374 return intel_bracket_expr ();
8379 strcat (intel_parser
.disp
, cur_token
.str
);
8380 intel_match_token (cur_token
.code
);
8382 /* Mark as a memory operand only if it's not already known to be an
8383 offset expression. */
8384 if (!intel_parser
.in_offset
)
8385 intel_parser
.is_mem
= 1;
8392 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
8394 intel_match_token (T_REG
);
8396 /* Check for segment change. */
8397 if (cur_token
.code
== ':')
8399 if (!reg
->reg_type
.bitfield
.sreg2
8400 && !reg
->reg_type
.bitfield
.sreg3
)
8402 as_bad (_("`%s' is not a valid segment register"),
8406 else if (i
.seg
[i
.mem_operands
])
8407 as_warn (_("Extra segment override ignored"));
8410 if (!intel_parser
.in_offset
)
8411 intel_parser
.is_mem
= 1;
8412 switch (reg
->reg_num
)
8415 i
.seg
[i
.mem_operands
] = &es
;
8418 i
.seg
[i
.mem_operands
] = &cs
;
8421 i
.seg
[i
.mem_operands
] = &ss
;
8424 i
.seg
[i
.mem_operands
] = &ds
;
8427 i
.seg
[i
.mem_operands
] = &fs
;
8430 i
.seg
[i
.mem_operands
] = &gs
;
8436 /* Not a segment register. Check for register scaling. */
8437 else if (cur_token
.code
== '*')
8439 if (!intel_parser
.in_bracket
)
8441 as_bad (_("Register scaling only allowed in memory operands"));
8445 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8446 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8447 else if (i
.index_reg
)
8448 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8450 /* What follows must be a valid scale. */
8451 intel_match_token ('*');
8453 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8455 /* Set the scale after setting the register (otherwise,
8456 i386_scale will complain) */
8457 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8459 char *str
, sign
= cur_token
.code
;
8460 intel_match_token (cur_token
.code
);
8461 if (cur_token
.code
!= T_CONST
)
8463 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8467 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8468 strcpy (str
+ 1, cur_token
.str
);
8470 if (!i386_scale (str
))
8474 else if (!i386_scale (cur_token
.str
))
8476 intel_match_token (cur_token
.code
);
8479 /* No scaling. If this is a memory operand, the register is either a
8480 base register (first occurrence) or an index register (second
8482 else if (intel_parser
.in_bracket
)
8487 else if (!i
.index_reg
)
8491 as_bad (_("Too many register references in memory operand"));
8495 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8498 /* It's neither base nor index. */
8499 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8501 i386_operand_type temp
= reg
->reg_type
;
8502 temp
.bitfield
.baseindex
= 0;
8503 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8505 i
.op
[this_operand
].regs
= reg
;
8510 as_bad (_("Invalid use of register"));
8514 /* Since registers are not part of the displacement string (except
8515 when we're parsing offset operands), we may need to remove any
8516 preceding '+' from the displacement string. */
8517 if (*intel_parser
.disp
!= '\0'
8518 && !intel_parser
.in_offset
)
8520 char *s
= intel_parser
.disp
;
8521 s
+= strlen (s
) - 1;
8544 intel_match_token (cur_token
.code
);
8546 if (cur_token
.code
== T_PTR
)
8549 /* It must have been an identifier. */
8550 intel_putback_token ();
8551 cur_token
.code
= T_ID
;
8557 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8561 /* The identifier represents a memory reference only if it's not
8562 preceded by an offset modifier and if it's not an equate. */
8563 symbolP
= symbol_find(cur_token
.str
);
8564 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8565 intel_parser
.is_mem
= 1;
8573 char *save_str
, sign
= 0;
8575 /* Allow constants that start with `+' or `-'. */
8576 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8578 sign
= cur_token
.code
;
8579 intel_match_token (cur_token
.code
);
8580 if (cur_token
.code
!= T_CONST
)
8582 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8588 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8589 strcpy (save_str
+ !!sign
, cur_token
.str
);
8593 /* Get the next token to check for register scaling. */
8594 intel_match_token (cur_token
.code
);
8596 /* Check if this constant is a scaling factor for an
8598 if (cur_token
.code
== '*')
8600 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8602 const reg_entry
*reg
= cur_token
.reg
;
8604 if (!intel_parser
.in_bracket
)
8606 as_bad (_("Register scaling only allowed "
8607 "in memory operands"));
8611 /* Disallow things like [1*si].
8612 sp and esp are invalid as index. */
8613 if (reg
->reg_type
.bitfield
.reg16
)
8614 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8615 else if (i
.index_reg
)
8616 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8618 /* The constant is followed by `* reg', so it must be
8621 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8623 /* Set the scale after setting the register (otherwise,
8624 i386_scale will complain) */
8625 if (!i386_scale (save_str
))
8627 intel_match_token (T_REG
);
8629 /* Since registers are not part of the displacement
8630 string, we may need to remove any preceding '+' from
8631 the displacement string. */
8632 if (*intel_parser
.disp
!= '\0')
8634 char *s
= intel_parser
.disp
;
8635 s
+= strlen (s
) - 1;
8645 /* The constant was not used for register scaling. Since we have
8646 already consumed the token following `*' we now need to put it
8647 back in the stream. */
8648 intel_putback_token ();
8651 /* Add the constant to the displacement string. */
8652 strcat (intel_parser
.disp
, save_str
);
8659 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8663 /* Match the given token against cur_token. If they match, read the next
8664 token from the operand string. */
8666 intel_match_token (int code
)
8668 if (cur_token
.code
== code
)
8675 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8680 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8682 intel_get_token (void)
8685 const reg_entry
*reg
;
8686 struct intel_token new_token
;
8688 new_token
.code
= T_NIL
;
8689 new_token
.reg
= NULL
;
8690 new_token
.str
= NULL
;
8692 /* Free the memory allocated to the previous token and move
8693 cur_token to prev_token. */
8695 free (prev_token
.str
);
8697 prev_token
= cur_token
;
8699 /* Skip whitespace. */
8700 while (is_space_char (*intel_parser
.op_string
))
8701 intel_parser
.op_string
++;
8703 /* Return an empty token if we find nothing else on the line. */
8704 if (*intel_parser
.op_string
== '\0')
8706 cur_token
= new_token
;
8710 /* The new token cannot be larger than the remainder of the operand
8712 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8713 new_token
.str
[0] = '\0';
8715 if (strchr ("0123456789", *intel_parser
.op_string
))
8717 char *p
= new_token
.str
;
8718 char *q
= intel_parser
.op_string
;
8719 new_token
.code
= T_CONST
;
8721 /* Allow any kind of identifier char to encompass floating point and
8722 hexadecimal numbers. */
8723 while (is_identifier_char (*q
))
8727 /* Recognize special symbol names [0-9][bf]. */
8728 if (strlen (intel_parser
.op_string
) == 2
8729 && (intel_parser
.op_string
[1] == 'b'
8730 || intel_parser
.op_string
[1] == 'f'))
8731 new_token
.code
= T_ID
;
8734 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8736 size_t len
= end_op
- intel_parser
.op_string
;
8738 new_token
.code
= T_REG
;
8739 new_token
.reg
= reg
;
8741 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8742 new_token
.str
[len
] = '\0';
8745 else if (is_identifier_char (*intel_parser
.op_string
))
8747 char *p
= new_token
.str
;
8748 char *q
= intel_parser
.op_string
;
8750 /* A '.' or '$' followed by an identifier char is an identifier.
8751 Otherwise, it's operator '.' followed by an expression. */
8752 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8754 new_token
.code
= '.';
8755 new_token
.str
[0] = '.';
8756 new_token
.str
[1] = '\0';
8760 while (is_identifier_char (*q
) || *q
== '@')
8764 if (strcasecmp (new_token
.str
, "NOT") == 0)
8765 new_token
.code
= '~';
8767 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8768 new_token
.code
= '%';
8770 else if (strcasecmp (new_token
.str
, "AND") == 0)
8771 new_token
.code
= '&';
8773 else if (strcasecmp (new_token
.str
, "OR") == 0)
8774 new_token
.code
= '|';
8776 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8777 new_token
.code
= '^';
8779 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8780 new_token
.code
= T_SHL
;
8782 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8783 new_token
.code
= T_SHR
;
8785 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8786 new_token
.code
= T_BYTE
;
8788 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8789 new_token
.code
= T_WORD
;
8791 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8792 new_token
.code
= T_DWORD
;
8794 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8795 new_token
.code
= T_FWORD
;
8797 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8798 new_token
.code
= T_QWORD
;
8800 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8801 /* XXX remove (gcc still uses it) */
8802 || strcasecmp (new_token
.str
, "XWORD") == 0)
8803 new_token
.code
= T_TBYTE
;
8805 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8806 || strcasecmp (new_token
.str
, "OWORD") == 0)
8807 new_token
.code
= T_XMMWORD
;
8809 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8810 new_token
.code
= T_PTR
;
8812 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8813 new_token
.code
= T_SHORT
;
8815 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8817 new_token
.code
= T_OFFSET
;
8819 /* ??? This is not mentioned in the MASM grammar but gcc
8820 makes use of it with -mintel-syntax. OFFSET may be
8821 followed by FLAT: */
8822 if (strncasecmp (q
, " FLAT:", 6) == 0)
8823 strcat (new_token
.str
, " FLAT:");
8826 /* ??? This is not mentioned in the MASM grammar. */
8827 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8829 new_token
.code
= T_OFFSET
;
8831 strcat (new_token
.str
, ":");
8833 as_bad (_("`:' expected"));
8837 new_token
.code
= T_ID
;
8841 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8843 new_token
.code
= *intel_parser
.op_string
;
8844 new_token
.str
[0] = *intel_parser
.op_string
;
8845 new_token
.str
[1] = '\0';
8848 else if (strchr ("<>", *intel_parser
.op_string
)
8849 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8851 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8852 new_token
.str
[0] = *intel_parser
.op_string
;
8853 new_token
.str
[1] = *intel_parser
.op_string
;
8854 new_token
.str
[2] = '\0';
8858 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8860 intel_parser
.op_string
+= strlen (new_token
.str
);
8861 cur_token
= new_token
;
8864 /* Put cur_token back into the token stream and make cur_token point to
8867 intel_putback_token (void)
8869 if (cur_token
.code
!= T_NIL
)
8871 intel_parser
.op_string
-= strlen (cur_token
.str
);
8872 free (cur_token
.str
);
8874 cur_token
= prev_token
;
8876 /* Forget prev_token. */
8877 prev_token
.code
= T_NIL
;
8878 prev_token
.reg
= NULL
;
8879 prev_token
.str
= NULL
;
8883 tc_x86_regname_to_dw2regnum (char *regname
)
8885 unsigned int regnum
;
8886 unsigned int regnames_count
;
8887 static const char *const regnames_32
[] =
8889 "eax", "ecx", "edx", "ebx",
8890 "esp", "ebp", "esi", "edi",
8891 "eip", "eflags", NULL
,
8892 "st0", "st1", "st2", "st3",
8893 "st4", "st5", "st6", "st7",
8895 "xmm0", "xmm1", "xmm2", "xmm3",
8896 "xmm4", "xmm5", "xmm6", "xmm7",
8897 "mm0", "mm1", "mm2", "mm3",
8898 "mm4", "mm5", "mm6", "mm7",
8899 "fcw", "fsw", "mxcsr",
8900 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8903 static const char *const regnames_64
[] =
8905 "rax", "rdx", "rcx", "rbx",
8906 "rsi", "rdi", "rbp", "rsp",
8907 "r8", "r9", "r10", "r11",
8908 "r12", "r13", "r14", "r15",
8910 "xmm0", "xmm1", "xmm2", "xmm3",
8911 "xmm4", "xmm5", "xmm6", "xmm7",
8912 "xmm8", "xmm9", "xmm10", "xmm11",
8913 "xmm12", "xmm13", "xmm14", "xmm15",
8914 "st0", "st1", "st2", "st3",
8915 "st4", "st5", "st6", "st7",
8916 "mm0", "mm1", "mm2", "mm3",
8917 "mm4", "mm5", "mm6", "mm7",
8919 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8920 "fs.base", "gs.base", NULL
, NULL
,
8922 "mxcsr", "fcw", "fsw"
8924 const char *const *regnames
;
8926 if (flag_code
== CODE_64BIT
)
8928 regnames
= regnames_64
;
8929 regnames_count
= ARRAY_SIZE (regnames_64
);
8933 regnames
= regnames_32
;
8934 regnames_count
= ARRAY_SIZE (regnames_32
);
8937 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
8938 if (regnames
[regnum
] != NULL
8939 && strcmp (regname
, regnames
[regnum
]) == 0)
8946 tc_x86_frame_initial_instructions (void)
8948 static unsigned int sp_regno
;
8951 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
8954 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
8955 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8959 i386_elf_section_type (const char *str
, size_t len
)
8961 if (flag_code
== CODE_64BIT
8962 && len
== sizeof ("unwind") - 1
8963 && strncmp (str
, "unwind", 6) == 0)
8964 return SHT_X86_64_UNWIND
;
8971 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8975 expr
.X_op
= O_secrel
;
8976 expr
.X_add_symbol
= symbol
;
8977 expr
.X_add_number
= 0;
8978 emit_expr (&expr
, size
);
8982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8983 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8986 x86_64_section_letter (int letter
, char **ptr_msg
)
8988 if (flag_code
== CODE_64BIT
)
8991 return SHF_X86_64_LARGE
;
8993 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8996 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9001 x86_64_section_word (char *str
, size_t len
)
9003 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9004 return SHF_X86_64_LARGE
;
9010 handle_large_common (int small ATTRIBUTE_UNUSED
)
9012 if (flag_code
!= CODE_64BIT
)
9014 s_comm_internal (0, elf_common_parse
);
9015 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9019 static segT lbss_section
;
9020 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9021 asection
*saved_bss_section
= bss_section
;
9023 if (lbss_section
== NULL
)
9025 flagword applicable
;
9027 subsegT subseg
= now_subseg
;
9029 /* The .lbss section is for local .largecomm symbols. */
9030 lbss_section
= subseg_new (".lbss", 0);
9031 applicable
= bfd_applicable_section_flags (stdoutput
);
9032 bfd_set_section_flags (stdoutput
, lbss_section
,
9033 applicable
& SEC_ALLOC
);
9034 seg_info (lbss_section
)->bss
= 1;
9036 subseg_set (seg
, subseg
);
9039 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9040 bss_section
= lbss_section
;
9042 s_comm_internal (0, elf_common_parse
);
9044 elf_com_section_ptr
= saved_com_section_ptr
;
9045 bss_section
= saved_bss_section
;
9048 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */