1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_allow_index_reg (int);
62 static void set_cpu_arch (int);
64 static void pe_directive_secrel (int);
66 static void signed_cons (int);
67 static char *output_invalid (int c
);
68 static int i386_operand (char *);
69 static int i386_intel_operand (char *, int);
70 static const reg_entry
*parse_register (char *, char **);
71 static char *parse_insn (char *, char *);
72 static char *parse_operands (char *, const char *);
73 static void swap_operands (void);
74 static void swap_2_operands (int, int);
75 static void optimize_imm (void);
76 static void optimize_disp (void);
77 static int match_template (void);
78 static int check_string (void);
79 static int process_suffix (void);
80 static int check_byte_reg (void);
81 static int check_long_reg (void);
82 static int check_qword_reg (void);
83 static int check_word_reg (void);
84 static int finalize_imm (void);
85 static void process_drex (void);
86 static int process_operands (void);
87 static const seg_entry
*build_modrm_byte (void);
88 static void output_insn (void);
89 static void output_imm (fragS
*, offsetT
);
90 static void output_disp (fragS
*, offsetT
);
92 static void s_bss (int);
94 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
98 static const char *default_arch
= DEFAULT_ARCH
;
100 /* 'md_assemble ()' gathers together information and puts it into a
107 const reg_entry
*regs
;
112 /* TM holds the template for the insn were currently assembling. */
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
119 /* OPERANDS gives the number of given operands. */
120 unsigned int operands
;
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
125 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
127 /* TYPES [i] is the type (see above #defines) which tells us how to
128 use OP[i] for the corresponding operand. */
129 i386_operand_type types
[MAX_OPERANDS
];
131 /* Displacement expression, immediate expression, or register for each
133 union i386_op op
[MAX_OPERANDS
];
135 /* Flags for operands. */
136 unsigned int flags
[MAX_OPERANDS
];
137 #define Operand_PCrel 1
139 /* Relocation type for operand */
140 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry
*base_reg
;
145 const reg_entry
*index_reg
;
146 unsigned int log2_scale_factor
;
148 /* SEG gives the seg_entries of this insn. They are zero unless
149 explicit segment overrides are given. */
150 const seg_entry
*seg
[2];
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes
;
155 unsigned char prefix
[MAX_PREFIXES
];
157 /* RM and SIB are the modrm byte and the sib byte where the
158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
167 typedef struct _i386_insn i386_insn
;
169 /* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
171 const char extra_symbol_chars
[] = "*%-(["
180 #if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
182 && !defined (TE_GNU) \
183 && !defined (TE_LINUX) \
184 && !defined (TE_NETWARE) \
185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190 const char *i386_comment_chars
= "#/";
191 #define SVR4_COMMENT_CHARS 1
192 #define PREFIX_SEPARATOR '\\'
195 const char *i386_comment_chars
= "#";
196 #define PREFIX_SEPARATOR '/'
199 /* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
203 first line of the input file. This is because the compiler outputs
204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
206 '/' isn't otherwise defined. */
207 const char line_comment_chars
[] = "#/";
209 const char line_separator_chars
[] = ";";
211 /* Chars that can be used to separate mant from exp in floating point
213 const char EXP_CHARS
[] = "eE";
215 /* Chars that mean this number is a floating point constant
218 const char FLT_CHARS
[] = "fFdDxX";
220 /* Tables for lexical analysis. */
221 static char mnemonic_chars
[256];
222 static char register_chars
[256];
223 static char operand_chars
[256];
224 static char identifier_chars
[256];
225 static char digit_chars
[256];
227 /* Lexical macros. */
228 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229 #define is_operand_char(x) (operand_chars[(unsigned char) x])
230 #define is_register_char(x) (register_chars[(unsigned char) x])
231 #define is_space_char(x) ((x) == ' ')
232 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233 #define is_digit_char(x) (digit_chars[(unsigned char) x])
235 /* All non-digit non-letter characters that may occur in an operand. */
236 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
238 /* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
241 assembler instruction). */
242 static char save_stack
[32];
243 static char *save_stack_p
;
244 #define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246 #define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
249 /* The instruction we're assembling. */
252 /* Possible templates for current insn. */
253 static const templates
*current_templates
;
255 /* Per instruction expressionS buffers: max displacements & immediates. */
256 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
257 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
259 /* Current operand we are working on. */
260 static int this_operand
;
262 /* We support four different modes. FLAG_CODE variable is used to distinguish
270 static enum flag_code flag_code
;
271 static unsigned int object_64bit
;
272 static int use_rela_relocations
= 0;
274 /* The names used to print error messages. */
275 static const char *flag_code_names
[] =
282 /* 1 for intel syntax,
284 static int intel_syntax
= 0;
286 /* 1 if register prefix % not required. */
287 static int allow_naked_reg
= 0;
289 /* 1 if fake index register, eiz/riz, is allowed . */
290 static int allow_index_reg
= 0;
292 /* Register prefix used for error message. */
293 static const char *register_prefix
= "%";
295 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298 static char stackop_size
= '\0';
300 /* Non-zero to optimize code alignment. */
301 int optimize_align_code
= 1;
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings
= 0;
307 static const char *cpu_arch_name
= NULL
;
308 static const char *cpu_sub_arch_name
= NULL
;
310 /* CPU feature flags. */
311 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
313 /* Bitwise NOT of cpu_arch_flags. */
314 static i386_cpu_flags cpu_arch_flags_not
;
316 /* If we have selected a cpu we are generating instructions for. */
317 static int cpu_arch_tune_set
= 0;
319 /* Cpu we are generating instructions for. */
320 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
322 /* CPU feature flags of cpu we are generating instructions for. */
323 static i386_cpu_flags cpu_arch_tune_flags
;
325 /* CPU instruction set architecture used. */
326 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
328 /* CPU feature flags of instruction set architecture used. */
329 static i386_cpu_flags cpu_arch_isa_flags
;
331 /* If set, conditional jumps are not automatically promoted to handle
332 larger than a byte offset. */
333 static unsigned int no_cond_jump_promotion
= 0;
335 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
336 static symbolS
*GOT_symbol
;
338 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
339 unsigned int x86_dwarf2_return_column
;
341 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
342 int x86_cie_data_alignment
;
344 /* Interface to relax_segment.
345 There are 3 major relax states for 386 jump insns because the
346 different types of jumps add different sizes to frags when we're
347 figuring out what sort of jump to choose to reach a given label. */
350 #define UNCOND_JUMP 0
352 #define COND_JUMP86 2
357 #define SMALL16 (SMALL | CODE16)
359 #define BIG16 (BIG | CODE16)
363 #define INLINE __inline__
369 #define ENCODE_RELAX_STATE(type, size) \
370 ((relax_substateT) (((type) << 2) | (size)))
371 #define TYPE_FROM_RELAX_STATE(s) \
373 #define DISP_SIZE_FROM_RELAX_STATE(s) \
374 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
376 /* This table is used by relax_frag to promote short jumps to long
377 ones where necessary. SMALL (short) jumps may be promoted to BIG
378 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
379 don't allow a short jump in a 32 bit code segment to be promoted to
380 a 16 bit offset jump because it's slower (requires data size
381 prefix), and doesn't work, unless the destination is in the bottom
382 64k of the code segment (The top 16 bits of eip are zeroed). */
384 const relax_typeS md_relax_table
[] =
387 1) most positive reach of this state,
388 2) most negative reach of this state,
389 3) how many bytes this mode will have in the variable part of the frag
390 4) which index into the table to try if we can't fit into this one. */
392 /* UNCOND_JUMP states. */
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
395 /* dword jmp adds 4 bytes to frag:
396 0 extra opcode bytes, 4 displacement bytes. */
398 /* word jmp adds 2 byte2 to frag:
399 0 extra opcode bytes, 2 displacement bytes. */
402 /* COND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
408 /* word conditionals add 3 bytes to frag:
409 1 extra opcode byte, 2 displacement bytes. */
412 /* COND_JUMP86 states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
418 /* word conditionals add 4 bytes to frag:
419 1 displacement byte and a 3 byte long branch insn. */
423 static const arch_entry cpu_arch
[] =
425 {"generic32", PROCESSOR_GENERIC32
,
426 CPU_GENERIC32_FLAGS
},
427 {"generic64", PROCESSOR_GENERIC64
,
428 CPU_GENERIC64_FLAGS
},
429 {"i8086", PROCESSOR_UNKNOWN
,
431 {"i186", PROCESSOR_UNKNOWN
,
433 {"i286", PROCESSOR_UNKNOWN
,
435 {"i386", PROCESSOR_I386
,
437 {"i486", PROCESSOR_I486
,
439 {"i586", PROCESSOR_PENTIUM
,
441 {"i686", PROCESSOR_PENTIUMPRO
,
443 {"pentium", PROCESSOR_PENTIUM
,
445 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
447 {"pentiumii", PROCESSOR_PENTIUMPRO
,
449 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
451 {"pentium4", PROCESSOR_PENTIUM4
,
453 {"prescott", PROCESSOR_NOCONA
,
455 {"nocona", PROCESSOR_NOCONA
,
457 {"yonah", PROCESSOR_CORE
,
459 {"core", PROCESSOR_CORE
,
461 {"merom", PROCESSOR_CORE2
,
463 {"core2", PROCESSOR_CORE2
,
467 {"k6_2", PROCESSOR_K6
,
469 {"athlon", PROCESSOR_ATHLON
,
471 {"sledgehammer", PROCESSOR_K8
,
473 {"opteron", PROCESSOR_K8
,
477 {"amdfam10", PROCESSOR_AMDFAM10
,
478 CPU_AMDFAM10_FLAGS
},
479 {".mmx", PROCESSOR_UNKNOWN
,
481 {".sse", PROCESSOR_UNKNOWN
,
483 {".sse2", PROCESSOR_UNKNOWN
,
485 {".sse3", PROCESSOR_UNKNOWN
,
487 {".ssse3", PROCESSOR_UNKNOWN
,
489 {".sse4.1", PROCESSOR_UNKNOWN
,
491 {".sse4.2", PROCESSOR_UNKNOWN
,
493 {".sse4", PROCESSOR_UNKNOWN
,
495 {".3dnow", PROCESSOR_UNKNOWN
,
497 {".3dnowa", PROCESSOR_UNKNOWN
,
499 {".padlock", PROCESSOR_UNKNOWN
,
501 {".pacifica", PROCESSOR_UNKNOWN
,
503 {".svme", PROCESSOR_UNKNOWN
,
505 {".sse4a", PROCESSOR_UNKNOWN
,
507 {".abm", PROCESSOR_UNKNOWN
,
509 {".sse5", PROCESSOR_UNKNOWN
,
513 const pseudo_typeS md_pseudo_table
[] =
515 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes
, 0},
518 {"align", s_align_ptwo
, 0},
520 {"arch", set_cpu_arch
, 0},
524 {"ffloat", float_cons
, 'f'},
525 {"dfloat", float_cons
, 'd'},
526 {"tfloat", float_cons
, 'x'},
528 {"slong", signed_cons
, 4},
529 {"noopt", s_ignore
, 0},
530 {"optim", s_ignore
, 0},
531 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
532 {"code16", set_code_flag
, CODE_16BIT
},
533 {"code32", set_code_flag
, CODE_32BIT
},
534 {"code64", set_code_flag
, CODE_64BIT
},
535 {"intel_syntax", set_intel_syntax
, 1},
536 {"att_syntax", set_intel_syntax
, 0},
537 {"allow_index_reg", set_allow_index_reg
, 1},
538 {"disallow_index_reg", set_allow_index_reg
, 0},
539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common
, 0},
542 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
543 {"loc", dwarf2_directive_loc
, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
547 {"secrel32", pe_directive_secrel
, 0},
552 /* For interface with expression (). */
553 extern char *input_line_pointer
;
555 /* Hash table for instruction mnemonic lookup. */
556 static struct hash_control
*op_hash
;
558 /* Hash table for register lookup. */
559 static struct hash_control
*reg_hash
;
562 i386_align_code (fragS
*fragP
, int count
)
564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
567 static const char f32_1
[] =
569 static const char f32_2
[] =
570 {0x66,0x90}; /* xchg %ax,%ax */
571 static const char f32_3
[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4
[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5
[] =
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6
[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7
[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8
[] =
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9
[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10
[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11
[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12
[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13
[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14
[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f16_3
[] =
604 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
605 static const char f16_4
[] =
606 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
607 static const char f16_5
[] =
609 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_6
[] =
611 {0x89,0xf6, /* mov %si,%si */
612 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
613 static const char f16_7
[] =
614 {0x8d,0x74,0x00, /* lea 0(%si),%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_8
[] =
617 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char jump_31
[] =
620 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
624 static const char *const f32_patt
[] = {
625 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
626 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
628 static const char *const f16_patt
[] = {
629 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
632 static const char alt_3
[] =
634 /* nopl 0(%[re]ax) */
635 static const char alt_4
[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5
[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6
[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7
[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8
[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9
[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10
[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11
[] =
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13
[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14
[] =
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15
[] =
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11
[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12
[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
712 static const char alt_short_13
[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 static const char alt_short_14
[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15
[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt
[] = {
726 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
727 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
728 alt_short_14
, alt_short_15
730 static const char *const alt_long_patt
[] = {
731 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
732 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
733 alt_long_14
, alt_long_15
736 /* Only align for at least a positive non-zero boundary. */
737 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
743 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
744 PROCESSOR_GENERIC32, f32_patt will be used.
745 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
747 alt_long_patt will be used.
748 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
749 PROCESSOR_AMDFAM10, alt_short_patt will be used.
751 When -mtune= isn't used, alt_long_patt will be used if
752 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code
== CODE_16BIT
)
762 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
764 /* Adjust jump offset. */
765 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
768 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
769 f16_patt
[count
- 1], count
);
773 const char *const *patt
= NULL
;
775 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
777 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
778 switch (cpu_arch_tune
)
780 case PROCESSOR_UNKNOWN
:
781 /* We use cpu_arch_isa_flags to check if we SHOULD
782 optimize for Cpu686. */
783 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
784 patt
= alt_long_patt
;
788 case PROCESSOR_PENTIUMPRO
:
789 case PROCESSOR_PENTIUM4
:
790 case PROCESSOR_NOCONA
:
792 case PROCESSOR_CORE2
:
793 case PROCESSOR_GENERIC64
:
794 patt
= alt_long_patt
;
797 case PROCESSOR_ATHLON
:
799 case PROCESSOR_AMDFAM10
:
800 patt
= alt_short_patt
;
804 case PROCESSOR_PENTIUM
:
805 case PROCESSOR_GENERIC32
:
812 switch (cpu_arch_tune
)
814 case PROCESSOR_UNKNOWN
:
815 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
816 PROCESSOR_UNKNOWN. */
822 case PROCESSOR_PENTIUM
:
824 case PROCESSOR_ATHLON
:
826 case PROCESSOR_AMDFAM10
:
827 case PROCESSOR_GENERIC32
:
828 /* We use cpu_arch_isa_flags to check if we CAN optimize
830 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
831 patt
= alt_short_patt
;
835 case PROCESSOR_PENTIUMPRO
:
836 case PROCESSOR_PENTIUM4
:
837 case PROCESSOR_NOCONA
:
839 case PROCESSOR_CORE2
:
840 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
841 patt
= alt_long_patt
;
845 case PROCESSOR_GENERIC64
:
846 patt
= alt_long_patt
;
851 if (patt
== f32_patt
)
853 /* If the padding is less than 15 bytes, we use the normal
854 ones. Otherwise, we use a jump instruction and adjust
857 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
858 patt
[count
- 1], count
);
861 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
863 /* Adjust jump offset. */
864 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
869 /* Maximum length of an instruction is 15 byte. If the
870 padding is greater than 15 bytes and we don't use jump,
871 we have to break it into smaller pieces. */
876 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
881 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
882 patt
[padding
- 1], padding
);
885 fragP
->fr_var
= count
;
889 uints_all_zero (const unsigned int *x
, unsigned int size
)
907 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
924 uints_equal (const unsigned int *x
, const unsigned int *y
,
936 return x
[0] == y
[0];
943 #define UINTS_ALL_ZERO(x) \
944 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
945 #define UINTS_SET(x, v) \
946 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
947 #define UINTS_CLEAR(x) \
948 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
949 #define UINTS_EQUAL(x, y) \
950 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
953 cpu_flags_check_cpu64 (i386_cpu_flags f
)
955 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
956 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
959 static INLINE i386_cpu_flags
960 cpu_flags_not (i386_cpu_flags x
)
962 switch (ARRAY_SIZE (x
.array
))
965 x
.array
[2] = ~x
.array
[2];
967 x
.array
[1] = ~x
.array
[1];
969 x
.array
[0] = ~x
.array
[0];
976 x
.bitfield
.unused
= 0;
982 static INLINE i386_cpu_flags
983 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
985 switch (ARRAY_SIZE (x
.array
))
988 x
.array
[2] &= y
.array
[2];
990 x
.array
[1] &= y
.array
[1];
992 x
.array
[0] &= y
.array
[0];
1000 static INLINE i386_cpu_flags
1001 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1003 switch (ARRAY_SIZE (x
.array
))
1006 x
.array
[2] |= y
.array
[2];
1008 x
.array
[1] |= y
.array
[1];
1010 x
.array
[0] |= y
.array
[0];
1019 cpu_flags_match (i386_cpu_flags x
)
1021 i386_cpu_flags
not = cpu_arch_flags_not
;
1023 not.bitfield
.cpu64
= 1;
1024 not.bitfield
.cpuno64
= 1;
1026 x
.bitfield
.cpu64
= 0;
1027 x
.bitfield
.cpuno64
= 0;
1029 not = cpu_flags_and (x
, not);
1030 return UINTS_ALL_ZERO (not);
1033 static INLINE i386_operand_type
1034 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1036 switch (ARRAY_SIZE (x
.array
))
1039 x
.array
[2] &= y
.array
[2];
1041 x
.array
[1] &= y
.array
[1];
1043 x
.array
[0] &= y
.array
[0];
1051 static INLINE i386_operand_type
1052 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1054 switch (ARRAY_SIZE (x
.array
))
1057 x
.array
[2] |= y
.array
[2];
1059 x
.array
[1] |= y
.array
[1];
1061 x
.array
[0] |= y
.array
[0];
1069 static INLINE i386_operand_type
1070 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1072 switch (ARRAY_SIZE (x
.array
))
1075 x
.array
[2] ^= y
.array
[2];
1077 x
.array
[1] ^= y
.array
[1];
1079 x
.array
[0] ^= y
.array
[0];
1087 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1088 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1089 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1090 static const i386_operand_type reg16_inoutportreg
1091 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1092 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1093 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1094 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1095 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1096 static const i386_operand_type anydisp
1097 = OPERAND_TYPE_ANYDISP
;
1098 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1099 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1100 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1101 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1102 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1103 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1104 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1105 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1106 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1107 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1118 operand_type_check (i386_operand_type t
, enum operand_type c
)
1123 return (t
.bitfield
.reg8
1126 || t
.bitfield
.reg64
);
1129 return (t
.bitfield
.imm8
1133 || t
.bitfield
.imm32s
1134 || t
.bitfield
.imm64
);
1137 return (t
.bitfield
.disp8
1138 || t
.bitfield
.disp16
1139 || t
.bitfield
.disp32
1140 || t
.bitfield
.disp32s
1141 || t
.bitfield
.disp64
);
1144 return (t
.bitfield
.disp8
1145 || t
.bitfield
.disp16
1146 || t
.bitfield
.disp32
1147 || t
.bitfield
.disp32s
1148 || t
.bitfield
.disp64
1149 || t
.bitfield
.baseindex
);
1157 operand_type_match (i386_operand_type overlap
,
1158 i386_operand_type given
)
1160 i386_operand_type temp
= overlap
;
1162 temp
.bitfield
.jumpabsolute
= 0;
1163 if (UINTS_ALL_ZERO (temp
))
1166 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1167 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1170 /* If given types r0 and r1 are registers they must be of the same type
1171 unless the expected operand type register overlap is null.
1172 Note that Acc in a template matches every size of reg. */
1175 operand_type_register_match (i386_operand_type m0
,
1176 i386_operand_type g0
,
1177 i386_operand_type t0
,
1178 i386_operand_type m1
,
1179 i386_operand_type g1
,
1180 i386_operand_type t1
)
1182 if (!operand_type_check (g0
, reg
))
1185 if (!operand_type_check (g1
, reg
))
1188 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1189 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1190 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1191 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1194 if (m0
.bitfield
.acc
)
1196 t0
.bitfield
.reg8
= 1;
1197 t0
.bitfield
.reg16
= 1;
1198 t0
.bitfield
.reg32
= 1;
1199 t0
.bitfield
.reg64
= 1;
1202 if (m1
.bitfield
.acc
)
1204 t1
.bitfield
.reg8
= 1;
1205 t1
.bitfield
.reg16
= 1;
1206 t1
.bitfield
.reg32
= 1;
1207 t1
.bitfield
.reg64
= 1;
1210 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1211 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1212 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1213 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1216 static INLINE
unsigned int
1217 mode_from_disp_size (i386_operand_type t
)
1219 if (t
.bitfield
.disp8
)
1221 else if (t
.bitfield
.disp16
1222 || t
.bitfield
.disp32
1223 || t
.bitfield
.disp32s
)
1230 fits_in_signed_byte (offsetT num
)
1232 return (num
>= -128) && (num
<= 127);
1236 fits_in_unsigned_byte (offsetT num
)
1238 return (num
& 0xff) == num
;
1242 fits_in_unsigned_word (offsetT num
)
1244 return (num
& 0xffff) == num
;
1248 fits_in_signed_word (offsetT num
)
1250 return (-32768 <= num
) && (num
<= 32767);
1254 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1259 return (!(((offsetT
) -1 << 31) & num
)
1260 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1262 } /* fits_in_signed_long() */
1265 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1270 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1272 } /* fits_in_unsigned_long() */
1274 static i386_operand_type
1275 smallest_imm_type (offsetT num
)
1277 i386_operand_type t
;
1280 t
.bitfield
.imm64
= 1;
1282 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1284 /* This code is disabled on the 486 because all the Imm1 forms
1285 in the opcode table are slower on the i486. They're the
1286 versions with the implicitly specified single-position
1287 displacement, which has another syntax if you really want to
1289 t
.bitfield
.imm1
= 1;
1290 t
.bitfield
.imm8
= 1;
1291 t
.bitfield
.imm8s
= 1;
1292 t
.bitfield
.imm16
= 1;
1293 t
.bitfield
.imm32
= 1;
1294 t
.bitfield
.imm32s
= 1;
1296 else if (fits_in_signed_byte (num
))
1298 t
.bitfield
.imm8
= 1;
1299 t
.bitfield
.imm8s
= 1;
1300 t
.bitfield
.imm16
= 1;
1301 t
.bitfield
.imm32
= 1;
1302 t
.bitfield
.imm32s
= 1;
1304 else if (fits_in_unsigned_byte (num
))
1306 t
.bitfield
.imm8
= 1;
1307 t
.bitfield
.imm16
= 1;
1308 t
.bitfield
.imm32
= 1;
1309 t
.bitfield
.imm32s
= 1;
1311 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1313 t
.bitfield
.imm16
= 1;
1314 t
.bitfield
.imm32
= 1;
1315 t
.bitfield
.imm32s
= 1;
1317 else if (fits_in_signed_long (num
))
1319 t
.bitfield
.imm32
= 1;
1320 t
.bitfield
.imm32s
= 1;
1322 else if (fits_in_unsigned_long (num
))
1323 t
.bitfield
.imm32
= 1;
1329 offset_in_range (offsetT val
, int size
)
1335 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1336 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1337 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1339 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1344 /* If BFD64, sign extend val. */
1345 if (!use_rela_relocations
)
1346 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1347 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1349 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1351 char buf1
[40], buf2
[40];
1353 sprint_value (buf1
, val
);
1354 sprint_value (buf2
, val
& mask
);
1355 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1360 /* Returns 0 if attempting to add a prefix where one from the same
1361 class already exists, 1 if non rep/repne added, 2 if rep/repne
1364 add_prefix (unsigned int prefix
)
1369 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1370 && flag_code
== CODE_64BIT
)
1372 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1373 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1374 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1385 case CS_PREFIX_OPCODE
:
1386 case DS_PREFIX_OPCODE
:
1387 case ES_PREFIX_OPCODE
:
1388 case FS_PREFIX_OPCODE
:
1389 case GS_PREFIX_OPCODE
:
1390 case SS_PREFIX_OPCODE
:
1394 case REPNE_PREFIX_OPCODE
:
1395 case REPE_PREFIX_OPCODE
:
1398 case LOCK_PREFIX_OPCODE
:
1406 case ADDR_PREFIX_OPCODE
:
1410 case DATA_PREFIX_OPCODE
:
1414 if (i
.prefix
[q
] != 0)
1422 i
.prefix
[q
] |= prefix
;
1425 as_bad (_("same type of prefix used twice"));
1431 set_code_flag (int value
)
1434 if (flag_code
== CODE_64BIT
)
1436 cpu_arch_flags
.bitfield
.cpu64
= 1;
1437 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1438 cpu_arch_flags_not
.bitfield
.cpu64
= 0;
1439 cpu_arch_flags_not
.bitfield
.cpuno64
= 1;
1443 cpu_arch_flags
.bitfield
.cpu64
= 0;
1444 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1445 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1446 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1448 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1450 as_bad (_("64bit mode not supported on this CPU."));
1452 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1454 as_bad (_("32bit mode not supported on this CPU."));
1456 stackop_size
= '\0';
1460 set_16bit_gcc_code_flag (int new_code_flag
)
1462 flag_code
= new_code_flag
;
1463 if (flag_code
!= CODE_16BIT
)
1465 cpu_arch_flags
.bitfield
.cpu64
= 0;
1466 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1467 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1468 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1469 stackop_size
= LONG_MNEM_SUFFIX
;
1473 set_intel_syntax (int syntax_flag
)
1475 /* Find out if register prefixing is specified. */
1476 int ask_naked_reg
= 0;
1479 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1481 char *string
= input_line_pointer
;
1482 int e
= get_symbol_end ();
1484 if (strcmp (string
, "prefix") == 0)
1486 else if (strcmp (string
, "noprefix") == 0)
1489 as_bad (_("bad argument to syntax directive."));
1490 *input_line_pointer
= e
;
1492 demand_empty_rest_of_line ();
1494 intel_syntax
= syntax_flag
;
1496 if (ask_naked_reg
== 0)
1497 allow_naked_reg
= (intel_syntax
1498 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1500 allow_naked_reg
= (ask_naked_reg
< 0);
1502 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1503 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1504 register_prefix
= allow_naked_reg
? "" : "%";
1508 set_allow_index_reg (int flag
)
1510 allow_index_reg
= flag
;
1514 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1518 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1520 char *string
= input_line_pointer
;
1521 int e
= get_symbol_end ();
1523 i386_cpu_flags flags
;
1525 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1527 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1531 cpu_arch_name
= cpu_arch
[i
].name
;
1532 cpu_sub_arch_name
= NULL
;
1533 cpu_arch_flags
= cpu_arch
[i
].flags
;
1534 if (flag_code
== CODE_64BIT
)
1536 cpu_arch_flags
.bitfield
.cpu64
= 1;
1537 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1541 cpu_arch_flags
.bitfield
.cpu64
= 0;
1542 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1544 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1545 cpu_arch_isa
= cpu_arch
[i
].type
;
1546 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1547 if (!cpu_arch_tune_set
)
1549 cpu_arch_tune
= cpu_arch_isa
;
1550 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1555 flags
= cpu_flags_or (cpu_arch_flags
,
1557 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1559 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1560 cpu_arch_flags
= flags
;
1561 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1563 *input_line_pointer
= e
;
1564 demand_empty_rest_of_line ();
1568 if (i
>= ARRAY_SIZE (cpu_arch
))
1569 as_bad (_("no such architecture: `%s'"), string
);
1571 *input_line_pointer
= e
;
1574 as_bad (_("missing cpu architecture"));
1576 no_cond_jump_promotion
= 0;
1577 if (*input_line_pointer
== ','
1578 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1580 char *string
= ++input_line_pointer
;
1581 int e
= get_symbol_end ();
1583 if (strcmp (string
, "nojumps") == 0)
1584 no_cond_jump_promotion
= 1;
1585 else if (strcmp (string
, "jumps") == 0)
1588 as_bad (_("no such architecture modifier: `%s'"), string
);
1590 *input_line_pointer
= e
;
1593 demand_empty_rest_of_line ();
1599 if (!strcmp (default_arch
, "x86_64"))
1600 return bfd_mach_x86_64
;
1601 else if (!strcmp (default_arch
, "i386"))
1602 return bfd_mach_i386_i386
;
1604 as_fatal (_("Unknown architecture"));
1610 const char *hash_err
;
1612 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1614 /* Initialize op_hash hash table. */
1615 op_hash
= hash_new ();
1618 const template *optab
;
1619 templates
*core_optab
;
1621 /* Setup for loop. */
1623 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1624 core_optab
->start
= optab
;
1629 if (optab
->name
== NULL
1630 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1632 /* different name --> ship out current template list;
1633 add to hash table; & begin anew. */
1634 core_optab
->end
= optab
;
1635 hash_err
= hash_insert (op_hash
,
1640 as_fatal (_("Internal Error: Can't hash %s: %s"),
1644 if (optab
->name
== NULL
)
1646 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1647 core_optab
->start
= optab
;
1652 /* Initialize reg_hash hash table. */
1653 reg_hash
= hash_new ();
1655 const reg_entry
*regtab
;
1656 unsigned int regtab_size
= i386_regtab_size
;
1658 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1660 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1662 as_fatal (_("Internal Error: Can't hash %s: %s"),
1668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1673 for (c
= 0; c
< 256; c
++)
1678 mnemonic_chars
[c
] = c
;
1679 register_chars
[c
] = c
;
1680 operand_chars
[c
] = c
;
1682 else if (ISLOWER (c
))
1684 mnemonic_chars
[c
] = c
;
1685 register_chars
[c
] = c
;
1686 operand_chars
[c
] = c
;
1688 else if (ISUPPER (c
))
1690 mnemonic_chars
[c
] = TOLOWER (c
);
1691 register_chars
[c
] = mnemonic_chars
[c
];
1692 operand_chars
[c
] = c
;
1695 if (ISALPHA (c
) || ISDIGIT (c
))
1696 identifier_chars
[c
] = c
;
1699 identifier_chars
[c
] = c
;
1700 operand_chars
[c
] = c
;
1705 identifier_chars
['@'] = '@';
1708 identifier_chars
['?'] = '?';
1709 operand_chars
['?'] = '?';
1711 digit_chars
['-'] = '-';
1712 mnemonic_chars
['-'] = '-';
1713 mnemonic_chars
['.'] = '.';
1714 identifier_chars
['_'] = '_';
1715 identifier_chars
['.'] = '.';
1717 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1718 operand_chars
[(unsigned char) *p
] = *p
;
1721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1724 record_alignment (text_section
, 2);
1725 record_alignment (data_section
, 2);
1726 record_alignment (bss_section
, 2);
1730 if (flag_code
== CODE_64BIT
)
1732 x86_dwarf2_return_column
= 16;
1733 x86_cie_data_alignment
= -8;
1737 x86_dwarf2_return_column
= 8;
1738 x86_cie_data_alignment
= -4;
1743 i386_print_statistics (FILE *file
)
1745 hash_print_statistics (file
, "i386 opcode", op_hash
);
1746 hash_print_statistics (file
, "i386 register", reg_hash
);
1751 /* Debugging routines for md_assemble. */
1752 static void pte (template *);
1753 static void pt (i386_operand_type
);
1754 static void pe (expressionS
*);
1755 static void ps (symbolS
*);
1758 pi (char *line
, i386_insn
*x
)
1762 fprintf (stdout
, "%s: template ", line
);
1764 fprintf (stdout
, " address: base %s index %s scale %x\n",
1765 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1766 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1767 x
->log2_scale_factor
);
1768 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1769 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1770 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1771 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1772 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1773 (x
->rex
& REX_W
) != 0,
1774 (x
->rex
& REX_R
) != 0,
1775 (x
->rex
& REX_X
) != 0,
1776 (x
->rex
& REX_B
) != 0);
1777 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
1778 x
->drex
.reg
, x
->drex
.rex
);
1779 for (i
= 0; i
< x
->operands
; i
++)
1781 fprintf (stdout
, " #%d: ", i
+ 1);
1783 fprintf (stdout
, "\n");
1784 if (x
->types
[i
].bitfield
.reg8
1785 || x
->types
[i
].bitfield
.reg16
1786 || x
->types
[i
].bitfield
.reg32
1787 || x
->types
[i
].bitfield
.reg64
1788 || x
->types
[i
].bitfield
.regmmx
1789 || x
->types
[i
].bitfield
.regxmm
1790 || x
->types
[i
].bitfield
.sreg2
1791 || x
->types
[i
].bitfield
.sreg3
1792 || x
->types
[i
].bitfield
.control
1793 || x
->types
[i
].bitfield
.debug
1794 || x
->types
[i
].bitfield
.test
)
1795 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1796 if (operand_type_check (x
->types
[i
], imm
))
1798 if (operand_type_check (x
->types
[i
], disp
))
1799 pe (x
->op
[i
].disps
);
1807 fprintf (stdout
, " %d operands ", t
->operands
);
1808 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1809 if (t
->extension_opcode
!= None
)
1810 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1811 if (t
->opcode_modifier
.d
)
1812 fprintf (stdout
, "D");
1813 if (t
->opcode_modifier
.w
)
1814 fprintf (stdout
, "W");
1815 fprintf (stdout
, "\n");
1816 for (i
= 0; i
< t
->operands
; i
++)
1818 fprintf (stdout
, " #%d type ", i
+ 1);
1819 pt (t
->operand_types
[i
]);
1820 fprintf (stdout
, "\n");
1827 fprintf (stdout
, " operation %d\n", e
->X_op
);
1828 fprintf (stdout
, " add_number %ld (%lx)\n",
1829 (long) e
->X_add_number
, (long) e
->X_add_number
);
1830 if (e
->X_add_symbol
)
1832 fprintf (stdout
, " add_symbol ");
1833 ps (e
->X_add_symbol
);
1834 fprintf (stdout
, "\n");
1838 fprintf (stdout
, " op_symbol ");
1839 ps (e
->X_op_symbol
);
1840 fprintf (stdout
, "\n");
1847 fprintf (stdout
, "%s type %s%s",
1849 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1850 segment_name (S_GET_SEGMENT (s
)));
1853 static struct type_name
1855 i386_operand_type mask
;
1858 const type_names
[] =
1860 { OPERAND_TYPE_REG8
, "r8" },
1861 { OPERAND_TYPE_REG16
, "r16" },
1862 { OPERAND_TYPE_REG32
, "r32" },
1863 { OPERAND_TYPE_REG64
, "r64" },
1864 { OPERAND_TYPE_IMM8
, "i8" },
1865 { OPERAND_TYPE_IMM8
, "i8s" },
1866 { OPERAND_TYPE_IMM16
, "i16" },
1867 { OPERAND_TYPE_IMM32
, "i32" },
1868 { OPERAND_TYPE_IMM32S
, "i32s" },
1869 { OPERAND_TYPE_IMM64
, "i64" },
1870 { OPERAND_TYPE_IMM1
, "i1" },
1871 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1872 { OPERAND_TYPE_DISP8
, "d8" },
1873 { OPERAND_TYPE_DISP16
, "d16" },
1874 { OPERAND_TYPE_DISP32
, "d32" },
1875 { OPERAND_TYPE_DISP32S
, "d32s" },
1876 { OPERAND_TYPE_DISP64
, "d64" },
1877 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1878 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1879 { OPERAND_TYPE_CONTROL
, "control reg" },
1880 { OPERAND_TYPE_TEST
, "test reg" },
1881 { OPERAND_TYPE_DEBUG
, "debug reg" },
1882 { OPERAND_TYPE_FLOATREG
, "FReg" },
1883 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1884 { OPERAND_TYPE_SREG2
, "SReg2" },
1885 { OPERAND_TYPE_SREG3
, "SReg3" },
1886 { OPERAND_TYPE_ACC
, "Acc" },
1887 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1888 { OPERAND_TYPE_REGMMX
, "rMMX" },
1889 { OPERAND_TYPE_REGXMM
, "rXMM" },
1890 { OPERAND_TYPE_ESSEG
, "es" },
1894 pt (i386_operand_type t
)
1897 i386_operand_type a
;
1899 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1901 a
= operand_type_and (t
, type_names
[j
].mask
);
1902 if (!UINTS_ALL_ZERO (a
))
1903 fprintf (stdout
, "%s, ", type_names
[j
].name
);
1908 #endif /* DEBUG386 */
1910 static bfd_reloc_code_real_type
1911 reloc (unsigned int size
,
1914 bfd_reloc_code_real_type other
)
1916 if (other
!= NO_RELOC
)
1918 reloc_howto_type
*reloc
;
1923 case BFD_RELOC_X86_64_GOT32
:
1924 return BFD_RELOC_X86_64_GOT64
;
1926 case BFD_RELOC_X86_64_PLTOFF64
:
1927 return BFD_RELOC_X86_64_PLTOFF64
;
1929 case BFD_RELOC_X86_64_GOTPC32
:
1930 other
= BFD_RELOC_X86_64_GOTPC64
;
1932 case BFD_RELOC_X86_64_GOTPCREL
:
1933 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1935 case BFD_RELOC_X86_64_TPOFF32
:
1936 other
= BFD_RELOC_X86_64_TPOFF64
;
1938 case BFD_RELOC_X86_64_DTPOFF32
:
1939 other
= BFD_RELOC_X86_64_DTPOFF64
;
1945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1946 if (size
== 4 && flag_code
!= CODE_64BIT
)
1949 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1951 as_bad (_("unknown relocation (%u)"), other
);
1952 else if (size
!= bfd_get_reloc_size (reloc
))
1953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1954 bfd_get_reloc_size (reloc
),
1956 else if (pcrel
&& !reloc
->pc_relative
)
1957 as_bad (_("non-pc-relative relocation for pc-relative field"));
1958 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1960 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1962 as_bad (_("relocated field and relocation type differ in signedness"));
1971 as_bad (_("there are no unsigned pc-relative relocations"));
1974 case 1: return BFD_RELOC_8_PCREL
;
1975 case 2: return BFD_RELOC_16_PCREL
;
1976 case 4: return BFD_RELOC_32_PCREL
;
1977 case 8: return BFD_RELOC_64_PCREL
;
1979 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1986 case 4: return BFD_RELOC_X86_64_32S
;
1991 case 1: return BFD_RELOC_8
;
1992 case 2: return BFD_RELOC_16
;
1993 case 4: return BFD_RELOC_32
;
1994 case 8: return BFD_RELOC_64
;
1996 as_bad (_("cannot do %s %u byte relocation"),
1997 sign
> 0 ? "signed" : "unsigned", size
);
2001 return BFD_RELOC_NONE
;
2004 /* Here we decide which fixups can be adjusted to make them relative to
2005 the beginning of the section instead of the symbol. Basically we need
2006 to make sure that the dynamic relocations are done correctly, so in
2007 some cases we force the original symbol to be used. */
2010 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2016 /* Don't adjust pc-relative references to merge sections in 64-bit
2018 if (use_rela_relocations
2019 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2023 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2024 and changed later by validate_fix. */
2025 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2026 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2029 /* adjust_reloc_syms doesn't know about the GOT. */
2030 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2031 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2032 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2034 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2035 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2036 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2037 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2038 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2040 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2042 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2056 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2057 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2064 intel_float_operand (const char *mnemonic
)
2066 /* Note that the value returned is meaningful only for opcodes with (memory)
2067 operands, hence the code here is free to improperly handle opcodes that
2068 have no operands (for better performance and smaller code). */
2070 if (mnemonic
[0] != 'f')
2071 return 0; /* non-math */
2073 switch (mnemonic
[1])
2075 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2076 the fs segment override prefix not currently handled because no
2077 call path can make opcodes without operands get here */
2079 return 2 /* integer op */;
2081 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2082 return 3; /* fldcw/fldenv */
2085 if (mnemonic
[2] != 'o' /* fnop */)
2086 return 3; /* non-waiting control op */
2089 if (mnemonic
[2] == 's')
2090 return 3; /* frstor/frstpm */
2093 if (mnemonic
[2] == 'a')
2094 return 3; /* fsave */
2095 if (mnemonic
[2] == 't')
2097 switch (mnemonic
[3])
2099 case 'c': /* fstcw */
2100 case 'd': /* fstdw */
2101 case 'e': /* fstenv */
2102 case 's': /* fsts[gw] */
2108 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2109 return 0; /* fxsave/fxrstor are not really math ops */
2116 /* This is the guts of the machine-dependent assembler. LINE points to a
2117 machine dependent instruction. This function is supposed to emit
2118 the frags/bytes it assembles to. */
2125 char mnemonic
[MAX_MNEM_SIZE
];
2127 /* Initialize globals. */
2128 memset (&i
, '\0', sizeof (i
));
2129 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2130 i
.reloc
[j
] = NO_RELOC
;
2131 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2132 memset (im_expressions
, '\0', sizeof (im_expressions
));
2133 save_stack_p
= save_stack
;
2135 /* First parse an instruction mnemonic & call i386_operand for the operands.
2136 We assume that the scrubber has arranged it so that line[0] is the valid
2137 start of a (possibly prefixed) mnemonic. */
2139 line
= parse_insn (line
, mnemonic
);
2143 line
= parse_operands (line
, mnemonic
);
2147 /* Now we've parsed the mnemonic into a set of templates, and have the
2148 operands at hand. */
2150 /* All intel opcodes have reversed operands except for "bound" and
2151 "enter". We also don't reverse intersegment "jmp" and "call"
2152 instructions with 2 immediate operands so that the immediate segment
2153 precedes the offset, as it does when in AT&T mode. */
2156 && (strcmp (mnemonic
, "bound") != 0)
2157 && (strcmp (mnemonic
, "invlpga") != 0)
2158 && !(operand_type_check (i
.types
[0], imm
)
2159 && operand_type_check (i
.types
[1], imm
)))
2162 /* The order of the immediates should be reversed
2163 for 2 immediates extrq and insertq instructions */
2164 if (i
.imm_operands
== 2
2165 && (strcmp (mnemonic
, "extrq") == 0
2166 || strcmp (mnemonic
, "insertq") == 0))
2167 swap_2_operands (0, 1);
2172 /* Don't optimize displacement for movabs since it only takes 64bit
2175 && (flag_code
!= CODE_64BIT
2176 || strcmp (mnemonic
, "movabs") != 0))
2179 /* Next, we find a template that matches the given insn,
2180 making sure the overlap of the given operands types is consistent
2181 with the template operand types. */
2183 if (!match_template ())
2188 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2190 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
2191 i
.tm
.base_opcode
^= Opcode_FloatR
;
2193 /* Zap movzx and movsx suffix. The suffix may have been set from
2194 "word ptr" or "byte ptr" on the source operand, but we'll use
2195 the suffix later to choose the destination register. */
2196 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2198 if (i
.reg_operands
< 2
2200 && (!i
.tm
.opcode_modifier
.no_bsuf
2201 || !i
.tm
.opcode_modifier
.no_wsuf
2202 || !i
.tm
.opcode_modifier
.no_lsuf
2203 || !i
.tm
.opcode_modifier
.no_ssuf
2204 || !i
.tm
.opcode_modifier
.no_ldsuf
2205 || !i
.tm
.opcode_modifier
.no_qsuf
))
2206 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2212 if (i
.tm
.opcode_modifier
.fwait
)
2213 if (!add_prefix (FWAIT_OPCODE
))
2216 /* Check string instruction segment overrides. */
2217 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2219 if (!check_string ())
2223 if (!process_suffix ())
2226 /* Make still unresolved immediate matches conform to size of immediate
2227 given in i.suffix. */
2228 if (!finalize_imm ())
2231 if (i
.types
[0].bitfield
.imm1
)
2232 i
.imm_operands
= 0; /* kludge for shift insns. */
2234 for (j
= 0; j
< 3; j
++)
2235 if (i
.types
[j
].bitfield
.inoutportreg
2236 || i
.types
[j
].bitfield
.shiftcount
2237 || i
.types
[j
].bitfield
.acc
2238 || i
.types
[j
].bitfield
.floatacc
)
2241 if (i
.tm
.opcode_modifier
.immext
)
2245 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2247 /* Streaming SIMD extensions 3 Instructions have the fixed
2248 operands with an opcode suffix which is coded in the same
2249 place as an 8-bit immediate field would be. Here we check
2250 those operands and remove them afterwards. */
2253 for (x
= 0; x
< i
.operands
; x
++)
2254 if (i
.op
[x
].regs
->reg_num
!= x
)
2255 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2257 i
.op
[x
].regs
->reg_name
,
2263 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2264 opcode suffix which is coded in the same place as an 8-bit
2265 immediate field would be. Here we fake an 8-bit immediate
2266 operand from the opcode suffix stored in tm.extension_opcode.
2267 SSE5 also uses this encoding, for some of its 3 argument
2270 assert (i
.imm_operands
== 0
2272 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2273 && i
.operands
<= 3)));
2275 exp
= &im_expressions
[i
.imm_operands
++];
2276 i
.op
[i
.operands
].imms
= exp
;
2277 UINTS_CLEAR (i
.types
[i
.operands
]);
2278 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2280 exp
->X_op
= O_constant
;
2281 exp
->X_add_number
= i
.tm
.extension_opcode
;
2282 i
.tm
.extension_opcode
= None
;
2285 /* For insns with operands there are more diddles to do to the opcode. */
2288 if (!process_operands ())
2291 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2293 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2294 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2297 /* Handle conversion of 'int $3' --> special int3 insn. */
2298 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2300 i
.tm
.base_opcode
= INT3_OPCODE
;
2304 if ((i
.tm
.opcode_modifier
.jump
2305 || i
.tm
.opcode_modifier
.jumpbyte
2306 || i
.tm
.opcode_modifier
.jumpdword
)
2307 && i
.op
[0].disps
->X_op
== O_constant
)
2309 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2310 the absolute address given by the constant. Since ix86 jumps and
2311 calls are pc relative, we need to generate a reloc. */
2312 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2313 i
.op
[0].disps
->X_op
= O_symbol
;
2316 if (i
.tm
.opcode_modifier
.rex64
)
2319 /* For 8 bit registers we need an empty rex prefix. Also if the
2320 instruction already has a prefix, we need to convert old
2321 registers to new ones. */
2323 if ((i
.types
[0].bitfield
.reg8
2324 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2325 || (i
.types
[1].bitfield
.reg8
2326 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2327 || ((i
.types
[0].bitfield
.reg8
2328 || i
.types
[1].bitfield
.reg8
)
2333 i
.rex
|= REX_OPCODE
;
2334 for (x
= 0; x
< 2; x
++)
2336 /* Look for 8 bit operand that uses old registers. */
2337 if (i
.types
[x
].bitfield
.reg8
2338 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2340 /* In case it is "hi" register, give up. */
2341 if (i
.op
[x
].regs
->reg_num
> 3)
2342 as_bad (_("can't encode register '%s%s' in an "
2343 "instruction requiring REX prefix."),
2344 register_prefix
, i
.op
[x
].regs
->reg_name
);
2346 /* Otherwise it is equivalent to the extended register.
2347 Since the encoding doesn't change this is merely
2348 cosmetic cleanup for debug output. */
2350 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2355 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2357 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2362 else if (i
.rex
!= 0)
2363 add_prefix (REX_OPCODE
| i
.rex
);
2365 /* We are ready to output the insn. */
2370 parse_insn (char *line
, char *mnemonic
)
2373 char *token_start
= l
;
2378 /* Non-zero if we found a prefix only acceptable with string insns. */
2379 const char *expecting_string_instruction
= NULL
;
2384 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2387 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2389 as_bad (_("no such instruction: `%s'"), token_start
);
2394 if (!is_space_char (*l
)
2395 && *l
!= END_OF_INSN
2397 || (*l
!= PREFIX_SEPARATOR
2400 as_bad (_("invalid character %s in mnemonic"),
2401 output_invalid (*l
));
2404 if (token_start
== l
)
2406 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2407 as_bad (_("expecting prefix; got nothing"));
2409 as_bad (_("expecting mnemonic; got nothing"));
2413 /* Look up instruction (or prefix) via hash table. */
2414 current_templates
= hash_find (op_hash
, mnemonic
);
2416 if (*l
!= END_OF_INSN
2417 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2418 && current_templates
2419 && current_templates
->start
->opcode_modifier
.isprefix
)
2421 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2423 as_bad ((flag_code
!= CODE_64BIT
2424 ? _("`%s' is only supported in 64-bit mode")
2425 : _("`%s' is not supported in 64-bit mode")),
2426 current_templates
->start
->name
);
2429 /* If we are in 16-bit mode, do not allow addr16 or data16.
2430 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2431 if ((current_templates
->start
->opcode_modifier
.size16
2432 || current_templates
->start
->opcode_modifier
.size32
)
2433 && flag_code
!= CODE_64BIT
2434 && (current_templates
->start
->opcode_modifier
.size32
2435 ^ (flag_code
== CODE_16BIT
)))
2437 as_bad (_("redundant %s prefix"),
2438 current_templates
->start
->name
);
2441 /* Add prefix, checking for repeated prefixes. */
2442 switch (add_prefix (current_templates
->start
->base_opcode
))
2447 expecting_string_instruction
= current_templates
->start
->name
;
2450 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2457 if (!current_templates
)
2459 /* See if we can get a match by trimming off a suffix. */
2462 case WORD_MNEM_SUFFIX
:
2463 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2464 i
.suffix
= SHORT_MNEM_SUFFIX
;
2466 case BYTE_MNEM_SUFFIX
:
2467 case QWORD_MNEM_SUFFIX
:
2468 i
.suffix
= mnem_p
[-1];
2470 current_templates
= hash_find (op_hash
, mnemonic
);
2472 case SHORT_MNEM_SUFFIX
:
2473 case LONG_MNEM_SUFFIX
:
2476 i
.suffix
= mnem_p
[-1];
2478 current_templates
= hash_find (op_hash
, mnemonic
);
2486 if (intel_float_operand (mnemonic
) == 1)
2487 i
.suffix
= SHORT_MNEM_SUFFIX
;
2489 i
.suffix
= LONG_MNEM_SUFFIX
;
2491 current_templates
= hash_find (op_hash
, mnemonic
);
2495 if (!current_templates
)
2497 as_bad (_("no such instruction: `%s'"), token_start
);
2502 if (current_templates
->start
->opcode_modifier
.jump
2503 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2505 /* Check for a branch hint. We allow ",pt" and ",pn" for
2506 predict taken and predict not taken respectively.
2507 I'm not sure that branch hints actually do anything on loop
2508 and jcxz insns (JumpByte) for current Pentium4 chips. They
2509 may work in the future and it doesn't hurt to accept them
2511 if (l
[0] == ',' && l
[1] == 'p')
2515 if (!add_prefix (DS_PREFIX_OPCODE
))
2519 else if (l
[2] == 'n')
2521 if (!add_prefix (CS_PREFIX_OPCODE
))
2527 /* Any other comma loses. */
2530 as_bad (_("invalid character %s in mnemonic"),
2531 output_invalid (*l
));
2535 /* Check if instruction is supported on specified architecture. */
2537 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2539 if (cpu_flags_match (t
->cpu_flags
))
2541 if (cpu_flags_check_cpu64 (t
->cpu_flags
))
2544 if (!(supported
& 2))
2546 as_bad (flag_code
== CODE_64BIT
2547 ? _("`%s' is not supported in 64-bit mode")
2548 : _("`%s' is only supported in 64-bit mode"),
2549 current_templates
->start
->name
);
2552 if (!(supported
& 1))
2554 as_warn (_("`%s' is not supported on `%s%s'"),
2555 current_templates
->start
->name
,
2557 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2559 else if (!cpu_arch_flags
.bitfield
.cpui386
2560 && (flag_code
!= CODE_16BIT
))
2562 as_warn (_("use .code16 to ensure correct addressing mode"));
2565 /* Check for rep/repne without a string instruction. */
2566 if (expecting_string_instruction
)
2568 static templates override
;
2570 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2571 if (t
->opcode_modifier
.isstring
)
2573 if (t
>= current_templates
->end
)
2575 as_bad (_("expecting string instruction after `%s'"),
2576 expecting_string_instruction
);
2579 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2580 if (!t
->opcode_modifier
.isstring
)
2583 current_templates
= &override
;
2590 parse_operands (char *l
, const char *mnemonic
)
2594 /* 1 if operand is pending after ','. */
2595 unsigned int expecting_operand
= 0;
2597 /* Non-zero if operand parens not balanced. */
2598 unsigned int paren_not_balanced
;
2600 while (*l
!= END_OF_INSN
)
2602 /* Skip optional white space before operand. */
2603 if (is_space_char (*l
))
2605 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2607 as_bad (_("invalid character %s before operand %d"),
2608 output_invalid (*l
),
2612 token_start
= l
; /* after white space */
2613 paren_not_balanced
= 0;
2614 while (paren_not_balanced
|| *l
!= ',')
2616 if (*l
== END_OF_INSN
)
2618 if (paren_not_balanced
)
2621 as_bad (_("unbalanced parenthesis in operand %d."),
2624 as_bad (_("unbalanced brackets in operand %d."),
2629 break; /* we are done */
2631 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2633 as_bad (_("invalid character %s in operand %d"),
2634 output_invalid (*l
),
2641 ++paren_not_balanced
;
2643 --paren_not_balanced
;
2648 ++paren_not_balanced
;
2650 --paren_not_balanced
;
2654 if (l
!= token_start
)
2655 { /* Yes, we've read in another operand. */
2656 unsigned int operand_ok
;
2657 this_operand
= i
.operands
++;
2658 if (i
.operands
> MAX_OPERANDS
)
2660 as_bad (_("spurious operands; (%d operands/instruction max)"),
2664 /* Now parse operand adding info to 'i' as we go along. */
2665 END_STRING_AND_SAVE (l
);
2669 i386_intel_operand (token_start
,
2670 intel_float_operand (mnemonic
));
2672 operand_ok
= i386_operand (token_start
);
2674 RESTORE_END_STRING (l
);
2680 if (expecting_operand
)
2682 expecting_operand_after_comma
:
2683 as_bad (_("expecting operand after ','; got nothing"));
2688 as_bad (_("expecting operand before ','; got nothing"));
2693 /* Now *l must be either ',' or END_OF_INSN. */
2696 if (*++l
== END_OF_INSN
)
2698 /* Just skip it, if it's \n complain. */
2699 goto expecting_operand_after_comma
;
2701 expecting_operand
= 1;
2708 swap_2_operands (int xchg1
, int xchg2
)
2710 union i386_op temp_op
;
2711 i386_operand_type temp_type
;
2712 enum bfd_reloc_code_real temp_reloc
;
2714 temp_type
= i
.types
[xchg2
];
2715 i
.types
[xchg2
] = i
.types
[xchg1
];
2716 i
.types
[xchg1
] = temp_type
;
2717 temp_op
= i
.op
[xchg2
];
2718 i
.op
[xchg2
] = i
.op
[xchg1
];
2719 i
.op
[xchg1
] = temp_op
;
2720 temp_reloc
= i
.reloc
[xchg2
];
2721 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2722 i
.reloc
[xchg1
] = temp_reloc
;
2726 swap_operands (void)
2731 swap_2_operands (1, i
.operands
- 2);
2734 swap_2_operands (0, i
.operands
- 1);
2740 if (i
.mem_operands
== 2)
2742 const seg_entry
*temp_seg
;
2743 temp_seg
= i
.seg
[0];
2744 i
.seg
[0] = i
.seg
[1];
2745 i
.seg
[1] = temp_seg
;
2749 /* Try to ensure constant immediates are represented in the smallest
2754 char guess_suffix
= 0;
2758 guess_suffix
= i
.suffix
;
2759 else if (i
.reg_operands
)
2761 /* Figure out a suffix from the last register operand specified.
2762 We can't do this properly yet, ie. excluding InOutPortReg,
2763 but the following works for instructions with immediates.
2764 In any case, we can't set i.suffix yet. */
2765 for (op
= i
.operands
; --op
>= 0;)
2766 if (i
.types
[op
].bitfield
.reg8
)
2768 guess_suffix
= BYTE_MNEM_SUFFIX
;
2771 else if (i
.types
[op
].bitfield
.reg16
)
2773 guess_suffix
= WORD_MNEM_SUFFIX
;
2776 else if (i
.types
[op
].bitfield
.reg32
)
2778 guess_suffix
= LONG_MNEM_SUFFIX
;
2781 else if (i
.types
[op
].bitfield
.reg64
)
2783 guess_suffix
= QWORD_MNEM_SUFFIX
;
2787 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2788 guess_suffix
= WORD_MNEM_SUFFIX
;
2790 for (op
= i
.operands
; --op
>= 0;)
2791 if (operand_type_check (i
.types
[op
], imm
))
2793 switch (i
.op
[op
].imms
->X_op
)
2796 /* If a suffix is given, this operand may be shortened. */
2797 switch (guess_suffix
)
2799 case LONG_MNEM_SUFFIX
:
2800 i
.types
[op
].bitfield
.imm32
= 1;
2801 i
.types
[op
].bitfield
.imm64
= 1;
2803 case WORD_MNEM_SUFFIX
:
2804 i
.types
[op
].bitfield
.imm16
= 1;
2805 i
.types
[op
].bitfield
.imm32
= 1;
2806 i
.types
[op
].bitfield
.imm32s
= 1;
2807 i
.types
[op
].bitfield
.imm64
= 1;
2809 case BYTE_MNEM_SUFFIX
:
2810 i
.types
[op
].bitfield
.imm8
= 1;
2811 i
.types
[op
].bitfield
.imm8s
= 1;
2812 i
.types
[op
].bitfield
.imm16
= 1;
2813 i
.types
[op
].bitfield
.imm32
= 1;
2814 i
.types
[op
].bitfield
.imm32s
= 1;
2815 i
.types
[op
].bitfield
.imm64
= 1;
2819 /* If this operand is at most 16 bits, convert it
2820 to a signed 16 bit number before trying to see
2821 whether it will fit in an even smaller size.
2822 This allows a 16-bit operand such as $0xffe0 to
2823 be recognised as within Imm8S range. */
2824 if ((i
.types
[op
].bitfield
.imm16
)
2825 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2827 i
.op
[op
].imms
->X_add_number
=
2828 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2830 if ((i
.types
[op
].bitfield
.imm32
)
2831 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2834 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2835 ^ ((offsetT
) 1 << 31))
2836 - ((offsetT
) 1 << 31));
2839 = operand_type_or (i
.types
[op
],
2840 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2842 /* We must avoid matching of Imm32 templates when 64bit
2843 only immediate is available. */
2844 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2845 i
.types
[op
].bitfield
.imm32
= 0;
2852 /* Symbols and expressions. */
2854 /* Convert symbolic operand to proper sizes for matching, but don't
2855 prevent matching a set of insns that only supports sizes other
2856 than those matching the insn suffix. */
2858 i386_operand_type mask
, allowed
;
2862 UINTS_CLEAR (allowed
);
2864 for (t
= current_templates
->start
;
2865 t
< current_templates
->end
;
2867 allowed
= operand_type_or (allowed
,
2868 t
->operand_types
[op
]);
2869 switch (guess_suffix
)
2871 case QWORD_MNEM_SUFFIX
:
2872 mask
.bitfield
.imm64
= 1;
2873 mask
.bitfield
.imm32s
= 1;
2875 case LONG_MNEM_SUFFIX
:
2876 mask
.bitfield
.imm32
= 1;
2878 case WORD_MNEM_SUFFIX
:
2879 mask
.bitfield
.imm16
= 1;
2881 case BYTE_MNEM_SUFFIX
:
2882 mask
.bitfield
.imm8
= 1;
2887 allowed
= operand_type_and (mask
, allowed
);
2888 if (!UINTS_ALL_ZERO (allowed
))
2889 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2896 /* Try to use the smallest displacement type too. */
2898 optimize_disp (void)
2902 for (op
= i
.operands
; --op
>= 0;)
2903 if (operand_type_check (i
.types
[op
], disp
))
2905 if (i
.op
[op
].disps
->X_op
== O_constant
)
2907 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2909 if (i
.types
[op
].bitfield
.disp16
2910 && (disp
& ~(offsetT
) 0xffff) == 0)
2912 /* If this operand is at most 16 bits, convert
2913 to a signed 16 bit number and don't use 64bit
2915 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2916 i
.types
[op
].bitfield
.disp64
= 0;
2918 if (i
.types
[op
].bitfield
.disp32
2919 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2921 /* If this operand is at most 32 bits, convert
2922 to a signed 32 bit number and don't use 64bit
2924 disp
&= (((offsetT
) 2 << 31) - 1);
2925 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2926 i
.types
[op
].bitfield
.disp64
= 0;
2928 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
2930 i
.types
[op
].bitfield
.disp8
= 0;
2931 i
.types
[op
].bitfield
.disp16
= 0;
2932 i
.types
[op
].bitfield
.disp32
= 0;
2933 i
.types
[op
].bitfield
.disp32s
= 0;
2934 i
.types
[op
].bitfield
.disp64
= 0;
2938 else if (flag_code
== CODE_64BIT
)
2940 if (fits_in_signed_long (disp
))
2942 i
.types
[op
].bitfield
.disp64
= 0;
2943 i
.types
[op
].bitfield
.disp32s
= 1;
2945 if (fits_in_unsigned_long (disp
))
2946 i
.types
[op
].bitfield
.disp32
= 1;
2948 if ((i
.types
[op
].bitfield
.disp32
2949 || i
.types
[op
].bitfield
.disp32s
2950 || i
.types
[op
].bitfield
.disp16
)
2951 && fits_in_signed_byte (disp
))
2952 i
.types
[op
].bitfield
.disp8
= 1;
2954 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2955 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2957 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2958 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2959 i
.types
[op
].bitfield
.disp8
= 0;
2960 i
.types
[op
].bitfield
.disp16
= 0;
2961 i
.types
[op
].bitfield
.disp32
= 0;
2962 i
.types
[op
].bitfield
.disp32s
= 0;
2963 i
.types
[op
].bitfield
.disp64
= 0;
2966 /* We only support 64bit displacement on constants. */
2967 i
.types
[op
].bitfield
.disp64
= 0;
2972 match_template (void)
2974 /* Points to template once we've found it. */
2976 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
2977 unsigned int found_reverse_match
;
2978 i386_opcode_modifier suffix_check
;
2979 i386_operand_type operand_types
[MAX_OPERANDS
];
2980 int addr_prefix_disp
;
2982 i386_cpu_flags overlap
;
2984 #if MAX_OPERANDS != 4
2985 # error "MAX_OPERANDS must be 4."
2988 found_reverse_match
= 0;
2989 addr_prefix_disp
= -1;
2991 memset (&suffix_check
, 0, sizeof (suffix_check
));
2992 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2993 suffix_check
.no_bsuf
= 1;
2994 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2995 suffix_check
.no_wsuf
= 1;
2996 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
2997 suffix_check
.no_ssuf
= 1;
2998 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2999 suffix_check
.no_lsuf
= 1;
3000 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3001 suffix_check
.no_qsuf
= 1;
3002 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3003 suffix_check
.no_ldsuf
= 1;
3005 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3007 addr_prefix_disp
= -1;
3009 /* Must have right number of operands. */
3010 if (i
.operands
!= t
->operands
)
3013 /* Check the suffix, except for some instructions in intel mode. */
3014 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3015 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3016 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3017 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3018 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3019 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3020 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3023 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3024 operand_types
[j
] = t
->operand_types
[j
];
3026 /* In general, don't allow 64-bit operands in 32-bit mode. */
3027 if (i
.suffix
== QWORD_MNEM_SUFFIX
3028 && flag_code
!= CODE_64BIT
3030 ? (!t
->opcode_modifier
.ignoresize
3031 && !intel_float_operand (t
->name
))
3032 : intel_float_operand (t
->name
) != 2)
3033 && ((!operand_types
[0].bitfield
.regmmx
3034 && !operand_types
[0].bitfield
.regxmm
)
3035 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3036 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3037 && (t
->base_opcode
!= 0x0fc7
3038 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3041 /* Do not verify operands when there are none. */
3044 overlap
= cpu_flags_and (t
->cpu_flags
, cpu_arch_flags_not
);
3047 if (!UINTS_ALL_ZERO (overlap
))
3049 /* We've found a match; break out of loop. */
3054 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3055 into Disp32/Disp16/Disp32 operand. */
3056 if (i
.prefix
[ADDR_PREFIX
] != 0)
3058 /* There should be only one Disp operand. */
3062 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3064 if (operand_types
[j
].bitfield
.disp16
)
3066 addr_prefix_disp
= j
;
3067 operand_types
[j
].bitfield
.disp32
= 1;
3068 operand_types
[j
].bitfield
.disp16
= 0;
3074 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3076 if (operand_types
[j
].bitfield
.disp32
)
3078 addr_prefix_disp
= j
;
3079 operand_types
[j
].bitfield
.disp32
= 0;
3080 operand_types
[j
].bitfield
.disp16
= 1;
3086 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3088 if (operand_types
[j
].bitfield
.disp64
)
3090 addr_prefix_disp
= j
;
3091 operand_types
[j
].bitfield
.disp64
= 0;
3092 operand_types
[j
].bitfield
.disp32
= 1;
3100 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3101 switch (t
->operands
)
3104 if (!operand_type_match (overlap0
, i
.types
[0]))
3108 /* xchg %eax, %eax is a special case. It is an aliase for nop
3109 only in 32bit mode and we can use opcode 0x90. In 64bit
3110 mode, we can't use 0x90 for xchg %eax, %eax since it should
3111 zero-extend %eax to %rax. */
3112 if (flag_code
== CODE_64BIT
3113 && t
->base_opcode
== 0x90
3114 && UINTS_EQUAL (i
.types
[0], acc32
)
3115 && UINTS_EQUAL (i
.types
[1], acc32
))
3119 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3120 if (!operand_type_match (overlap0
, i
.types
[0])
3121 || !operand_type_match (overlap1
, i
.types
[1])
3122 /* monitor in SSE3 is a very special case. The first
3123 register and the second register may have different
3124 sizes. The same applies to crc32 in SSE4.2. It is
3125 also true for invlpga, vmload, vmrun and vmsave in
3127 || !((t
->base_opcode
== 0x0f01
3128 && (t
->extension_opcode
== 0xc8
3129 || t
->extension_opcode
== 0xd8
3130 || t
->extension_opcode
== 0xda
3131 || t
->extension_opcode
== 0xdb
3132 || t
->extension_opcode
== 0xdf))
3133 || t
->base_opcode
== 0xf20f38f1
3134 || operand_type_register_match (overlap0
, i
.types
[0],
3136 overlap1
, i
.types
[1],
3139 /* Check if other direction is valid ... */
3140 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3143 /* Try reversing direction of operands. */
3144 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3145 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3146 if (!operand_type_match (overlap0
, i
.types
[0])
3147 || !operand_type_match (overlap1
, i
.types
[1])
3148 || !operand_type_register_match (overlap0
, i
.types
[0],
3150 overlap1
, i
.types
[1],
3153 /* Does not match either direction. */
3156 /* found_reverse_match holds which of D or FloatDR
3158 if (t
->opcode_modifier
.d
)
3159 found_reverse_match
= Opcode_D
;
3160 else if (t
->opcode_modifier
.floatd
)
3161 found_reverse_match
= Opcode_FloatD
;
3163 found_reverse_match
= 0;
3164 if (t
->opcode_modifier
.floatr
)
3165 found_reverse_match
|= Opcode_FloatR
;
3169 /* Found a forward 2 operand match here. */
3170 switch (t
->operands
)
3173 overlap3
= operand_type_and (i
.types
[3],
3176 overlap2
= operand_type_and (i
.types
[2],
3181 switch (t
->operands
)
3184 if (!operand_type_match (overlap3
, i
.types
[3])
3185 || !operand_type_register_match (overlap2
,
3193 /* Here we make use of the fact that there are no
3194 reverse match 3 operand instructions, and all 3
3195 operand instructions only need to be checked for
3196 register consistency between operands 2 and 3. */
3197 if (!operand_type_match (overlap2
, i
.types
[2])
3198 || !operand_type_register_match (overlap1
,
3208 /* Found either forward/reverse 2, 3 or 4 operand match here:
3209 slip through to break. */
3211 if (!UINTS_ALL_ZERO (overlap
))
3213 found_reverse_match
= 0;
3216 /* We've found a match; break out of loop. */
3220 if (t
== current_templates
->end
)
3222 /* We found no match. */
3223 as_bad (_("suffix or operands invalid for `%s'"),
3224 current_templates
->start
->name
);
3228 if (!quiet_warnings
)
3231 && (i
.types
[0].bitfield
.jumpabsolute
3232 != operand_types
[0].bitfield
.jumpabsolute
))
3234 as_warn (_("indirect %s without `*'"), t
->name
);
3237 if (t
->opcode_modifier
.isprefix
3238 && t
->opcode_modifier
.ignoresize
)
3240 /* Warn them that a data or address size prefix doesn't
3241 affect assembly of the next line of code. */
3242 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3246 /* Copy the template we found. */
3249 if (addr_prefix_disp
!= -1)
3250 i
.tm
.operand_types
[addr_prefix_disp
]
3251 = operand_types
[addr_prefix_disp
];
3253 if (found_reverse_match
)
3255 /* If we found a reverse match we must alter the opcode
3256 direction bit. found_reverse_match holds bits to change
3257 (different for int & float insns). */
3259 i
.tm
.base_opcode
^= found_reverse_match
;
3261 i
.tm
.operand_types
[0] = operand_types
[1];
3262 i
.tm
.operand_types
[1] = operand_types
[0];
3271 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3272 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3274 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3276 as_bad (_("`%s' operand %d must use `%%es' segment"),
3281 /* There's only ever one segment override allowed per instruction.
3282 This instruction possibly has a legal segment override on the
3283 second operand, so copy the segment to where non-string
3284 instructions store it, allowing common code. */
3285 i
.seg
[0] = i
.seg
[1];
3287 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3289 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3291 as_bad (_("`%s' operand %d must use `%%es' segment"),
3301 process_suffix (void)
3303 /* If matched instruction specifies an explicit instruction mnemonic
3305 if (i
.tm
.opcode_modifier
.size16
)
3306 i
.suffix
= WORD_MNEM_SUFFIX
;
3307 else if (i
.tm
.opcode_modifier
.size32
)
3308 i
.suffix
= LONG_MNEM_SUFFIX
;
3309 else if (i
.tm
.opcode_modifier
.size64
)
3310 i
.suffix
= QWORD_MNEM_SUFFIX
;
3311 else if (i
.reg_operands
)
3313 /* If there's no instruction mnemonic suffix we try to invent one
3314 based on register operands. */
3317 /* We take i.suffix from the last register operand specified,
3318 Destination register type is more significant than source
3319 register type. crc32 in SSE4.2 prefers source register
3321 if (i
.tm
.base_opcode
== 0xf20f38f1)
3323 if (i
.types
[0].bitfield
.reg16
)
3324 i
.suffix
= WORD_MNEM_SUFFIX
;
3325 else if (i
.types
[0].bitfield
.reg32
)
3326 i
.suffix
= LONG_MNEM_SUFFIX
;
3327 else if (i
.types
[0].bitfield
.reg64
)
3328 i
.suffix
= QWORD_MNEM_SUFFIX
;
3330 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3332 if (i
.types
[0].bitfield
.reg8
)
3333 i
.suffix
= BYTE_MNEM_SUFFIX
;
3340 if (i
.tm
.base_opcode
== 0xf20f38f1
3341 || i
.tm
.base_opcode
== 0xf20f38f0)
3343 /* We have to know the operand size for crc32. */
3344 as_bad (_("ambiguous memory operand size for `%s`"),
3349 for (op
= i
.operands
; --op
>= 0;)
3350 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3352 if (i
.types
[op
].bitfield
.reg8
)
3354 i
.suffix
= BYTE_MNEM_SUFFIX
;
3357 else if (i
.types
[op
].bitfield
.reg16
)
3359 i
.suffix
= WORD_MNEM_SUFFIX
;
3362 else if (i
.types
[op
].bitfield
.reg32
)
3364 i
.suffix
= LONG_MNEM_SUFFIX
;
3367 else if (i
.types
[op
].bitfield
.reg64
)
3369 i
.suffix
= QWORD_MNEM_SUFFIX
;
3375 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3377 if (!check_byte_reg ())
3380 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3382 if (!check_long_reg ())
3385 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3388 && i
.tm
.opcode_modifier
.ignoresize
3389 && i
.tm
.opcode_modifier
.no_qsuf
)
3391 else if (!check_qword_reg ())
3394 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3396 if (!check_word_reg ())
3399 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3400 /* Do nothing if the instruction is going to ignore the prefix. */
3405 else if (i
.tm
.opcode_modifier
.defaultsize
3407 /* exclude fldenv/frstor/fsave/fstenv */
3408 && i
.tm
.opcode_modifier
.no_ssuf
)
3410 i
.suffix
= stackop_size
;
3412 else if (intel_syntax
3414 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3415 || i
.tm
.opcode_modifier
.jumpbyte
3416 || i
.tm
.opcode_modifier
.jumpintersegment
3417 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3418 && i
.tm
.extension_opcode
<= 3)))
3423 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3425 i
.suffix
= QWORD_MNEM_SUFFIX
;
3429 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3430 i
.suffix
= LONG_MNEM_SUFFIX
;
3433 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3434 i
.suffix
= WORD_MNEM_SUFFIX
;
3443 if (i
.tm
.opcode_modifier
.w
)
3445 as_bad (_("no instruction mnemonic suffix given and "
3446 "no register operands; can't size instruction"));
3452 unsigned int suffixes
;
3454 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3455 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3457 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3459 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3461 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3463 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3466 /* There are more than suffix matches. */
3467 if (i
.tm
.opcode_modifier
.w
3468 || ((suffixes
& (suffixes
- 1))
3469 && !i
.tm
.opcode_modifier
.defaultsize
3470 && !i
.tm
.opcode_modifier
.ignoresize
))
3472 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3478 /* Change the opcode based on the operand size given by i.suffix;
3479 We don't need to change things for byte insns. */
3481 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
3483 /* It's not a byte, select word/dword operation. */
3484 if (i
.tm
.opcode_modifier
.w
)
3486 if (i
.tm
.opcode_modifier
.shortform
)
3487 i
.tm
.base_opcode
|= 8;
3489 i
.tm
.base_opcode
|= 1;
3492 /* Now select between word & dword operations via the operand
3493 size prefix, except for instructions that will ignore this
3495 if (i
.tm
.opcode_modifier
.addrprefixop0
)
3497 /* The address size override prefix changes the size of the
3499 if ((flag_code
== CODE_32BIT
3500 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3501 || (flag_code
!= CODE_32BIT
3502 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3503 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3506 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3507 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3508 && !i
.tm
.opcode_modifier
.ignoresize
3509 && !i
.tm
.opcode_modifier
.floatmf
3510 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3511 || (flag_code
== CODE_64BIT
3512 && i
.tm
.opcode_modifier
.jumpbyte
)))
3514 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3516 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3517 prefix
= ADDR_PREFIX_OPCODE
;
3519 if (!add_prefix (prefix
))
3523 /* Set mode64 for an operand. */
3524 if (i
.suffix
== QWORD_MNEM_SUFFIX
3525 && flag_code
== CODE_64BIT
3526 && !i
.tm
.opcode_modifier
.norex64
)
3528 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3529 need rex64. cmpxchg8b is also a special case. */
3530 if (! (i
.operands
== 2
3531 && i
.tm
.base_opcode
== 0x90
3532 && i
.tm
.extension_opcode
== None
3533 && UINTS_EQUAL (i
.types
[0], acc64
)
3534 && UINTS_EQUAL (i
.types
[1], acc64
))
3535 && ! (i
.operands
== 1
3536 && i
.tm
.base_opcode
== 0xfc7
3537 && i
.tm
.extension_opcode
== 1
3538 && !operand_type_check (i
.types
[0], reg
)
3539 && operand_type_check (i
.types
[0], anymem
)))
3543 /* Size floating point instruction. */
3544 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3545 if (i
.tm
.opcode_modifier
.floatmf
)
3546 i
.tm
.base_opcode
^= 4;
3553 check_byte_reg (void)
3557 for (op
= i
.operands
; --op
>= 0;)
3559 /* If this is an eight bit register, it's OK. If it's the 16 or
3560 32 bit version of an eight bit register, we will just use the
3561 low portion, and that's OK too. */
3562 if (i
.types
[op
].bitfield
.reg8
)
3565 /* Don't generate this warning if not needed. */
3566 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
3569 /* crc32 doesn't generate this warning. */
3570 if (i
.tm
.base_opcode
== 0xf20f38f0)
3573 if ((i
.types
[op
].bitfield
.reg16
3574 || i
.types
[op
].bitfield
.reg32
3575 || i
.types
[op
].bitfield
.reg64
)
3576 && i
.op
[op
].regs
->reg_num
< 4)
3578 /* Prohibit these changes in the 64bit mode, since the
3579 lowering is more complicated. */
3580 if (flag_code
== CODE_64BIT
3581 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3583 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3584 register_prefix
, i
.op
[op
].regs
->reg_name
,
3588 #if REGISTER_WARNINGS
3590 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3591 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3593 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3594 ? REGNAM_AL
- REGNAM_AX
3595 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3597 i
.op
[op
].regs
->reg_name
,
3602 /* Any other register is bad. */
3603 if (i
.types
[op
].bitfield
.reg16
3604 || i
.types
[op
].bitfield
.reg32
3605 || i
.types
[op
].bitfield
.reg64
3606 || i
.types
[op
].bitfield
.regmmx
3607 || i
.types
[op
].bitfield
.regxmm
3608 || i
.types
[op
].bitfield
.sreg2
3609 || i
.types
[op
].bitfield
.sreg3
3610 || i
.types
[op
].bitfield
.control
3611 || i
.types
[op
].bitfield
.debug
3612 || i
.types
[op
].bitfield
.test
3613 || i
.types
[op
].bitfield
.floatreg
3614 || i
.types
[op
].bitfield
.floatacc
)
3616 as_bad (_("`%s%s' not allowed with `%s%c'"),
3618 i
.op
[op
].regs
->reg_name
,
3628 check_long_reg (void)
3632 for (op
= i
.operands
; --op
>= 0;)
3633 /* Reject eight bit registers, except where the template requires
3634 them. (eg. movzb) */
3635 if (i
.types
[op
].bitfield
.reg8
3636 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3637 || i
.tm
.operand_types
[op
].bitfield
.reg32
3638 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3640 as_bad (_("`%s%s' not allowed with `%s%c'"),
3642 i
.op
[op
].regs
->reg_name
,
3647 /* Warn if the e prefix on a general reg is missing. */
3648 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3649 && i
.types
[op
].bitfield
.reg16
3650 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3651 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3653 /* Prohibit these changes in the 64bit mode, since the
3654 lowering is more complicated. */
3655 if (flag_code
== CODE_64BIT
)
3657 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3658 register_prefix
, i
.op
[op
].regs
->reg_name
,
3662 #if REGISTER_WARNINGS
3664 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3666 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3668 i
.op
[op
].regs
->reg_name
,
3672 /* Warn if the r prefix on a general reg is missing. */
3673 else if (i
.types
[op
].bitfield
.reg64
3674 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3675 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3678 && i
.tm
.opcode_modifier
.toqword
3679 && !i
.types
[0].bitfield
.regxmm
)
3681 /* Convert to QWORD. We want REX byte. */
3682 i
.suffix
= QWORD_MNEM_SUFFIX
;
3686 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3687 register_prefix
, i
.op
[op
].regs
->reg_name
,
3696 check_qword_reg (void)
3700 for (op
= i
.operands
; --op
>= 0; )
3701 /* Reject eight bit registers, except where the template requires
3702 them. (eg. movzb) */
3703 if (i
.types
[op
].bitfield
.reg8
3704 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3705 || i
.tm
.operand_types
[op
].bitfield
.reg32
3706 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3708 as_bad (_("`%s%s' not allowed with `%s%c'"),
3710 i
.op
[op
].regs
->reg_name
,
3715 /* Warn if the e prefix on a general reg is missing. */
3716 else if ((i
.types
[op
].bitfield
.reg16
3717 || i
.types
[op
].bitfield
.reg32
)
3718 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3719 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3721 /* Prohibit these changes in the 64bit mode, since the
3722 lowering is more complicated. */
3724 && i
.tm
.opcode_modifier
.todword
3725 && !i
.types
[0].bitfield
.regxmm
)
3727 /* Convert to DWORD. We don't want REX byte. */
3728 i
.suffix
= LONG_MNEM_SUFFIX
;
3732 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3733 register_prefix
, i
.op
[op
].regs
->reg_name
,
3742 check_word_reg (void)
3745 for (op
= i
.operands
; --op
>= 0;)
3746 /* Reject eight bit registers, except where the template requires
3747 them. (eg. movzb) */
3748 if (i
.types
[op
].bitfield
.reg8
3749 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3750 || i
.tm
.operand_types
[op
].bitfield
.reg32
3751 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3753 as_bad (_("`%s%s' not allowed with `%s%c'"),
3755 i
.op
[op
].regs
->reg_name
,
3760 /* Warn if the e prefix on a general reg is present. */
3761 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3762 && i
.types
[op
].bitfield
.reg32
3763 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3764 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3766 /* Prohibit these changes in the 64bit mode, since the
3767 lowering is more complicated. */
3768 if (flag_code
== CODE_64BIT
)
3770 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3771 register_prefix
, i
.op
[op
].regs
->reg_name
,
3776 #if REGISTER_WARNINGS
3777 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3779 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3781 i
.op
[op
].regs
->reg_name
,
3789 update_imm (unsigned int j
)
3791 i386_operand_type overlap
;
3793 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3794 if ((overlap
.bitfield
.imm8
3795 || overlap
.bitfield
.imm8s
3796 || overlap
.bitfield
.imm16
3797 || overlap
.bitfield
.imm32
3798 || overlap
.bitfield
.imm32s
3799 || overlap
.bitfield
.imm64
)
3800 && !UINTS_EQUAL (overlap
, imm8
)
3801 && !UINTS_EQUAL (overlap
, imm8s
)
3802 && !UINTS_EQUAL (overlap
, imm16
)
3803 && !UINTS_EQUAL (overlap
, imm32
)
3804 && !UINTS_EQUAL (overlap
, imm32s
)
3805 && !UINTS_EQUAL (overlap
, imm64
))
3809 i386_operand_type temp
;
3812 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3814 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3815 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3817 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3818 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3819 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3821 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3822 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3825 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3828 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3829 || UINTS_EQUAL (overlap
, imm16_32
)
3830 || UINTS_EQUAL (overlap
, imm16_32s
))
3832 UINTS_CLEAR (overlap
);
3833 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3834 overlap
.bitfield
.imm16
= 1;
3836 overlap
.bitfield
.imm32s
= 1;
3838 if (!UINTS_EQUAL (overlap
, imm8
)
3839 && !UINTS_EQUAL (overlap
, imm8s
)
3840 && !UINTS_EQUAL (overlap
, imm16
)
3841 && !UINTS_EQUAL (overlap
, imm32
)
3842 && !UINTS_EQUAL (overlap
, imm32s
)
3843 && !UINTS_EQUAL (overlap
, imm64
))
3845 as_bad (_("no instruction mnemonic suffix given; "
3846 "can't determine immediate size"));
3850 i
.types
[j
] = overlap
;
3860 for (j
= 0; j
< 2; j
++)
3861 if (update_imm (j
) == 0)
3864 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3865 assert (operand_type_check (i
.types
[2], imm
) == 0);
3873 i
.drex
.modrm_reg
= None
;
3874 i
.drex
.modrm_regmem
= None
;
3876 /* SSE5 4 operand instructions must have the destination the same as
3877 one of the inputs. Figure out the destination register and cache
3878 it away in the drex field, and remember which fields to use for
3880 if (i
.tm
.opcode_modifier
.drex
3881 && i
.tm
.opcode_modifier
.drexv
3884 i
.tm
.extension_opcode
= None
;
3886 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3887 if (i
.types
[0].bitfield
.regxmm
!= 0
3888 && i
.types
[1].bitfield
.regxmm
!= 0
3889 && i
.types
[2].bitfield
.regxmm
!= 0
3890 && i
.types
[3].bitfield
.regxmm
!= 0
3891 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3892 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3894 /* Clear the arguments that are stored in drex. */
3895 UINTS_CLEAR (i
.types
[0]);
3896 UINTS_CLEAR (i
.types
[3]);
3897 i
.reg_operands
-= 2;
3899 /* There are two different ways to encode a 4 operand
3900 instruction with all registers that uses OC1 set to
3901 0 or 1. Favor setting OC1 to 0 since this mimics the
3902 actions of other SSE5 assemblers. Use modrm encoding 2
3903 for register/register. Include the high order bit that
3904 is normally stored in the REX byte in the register
3906 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3907 i
.drex
.modrm_reg
= 2;
3908 i
.drex
.modrm_regmem
= 1;
3909 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3910 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3913 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3914 else if (i
.types
[0].bitfield
.regxmm
!= 0
3915 && i
.types
[1].bitfield
.regxmm
!= 0
3916 && (i
.types
[2].bitfield
.regxmm
3917 || operand_type_check (i
.types
[2], anymem
))
3918 && i
.types
[3].bitfield
.regxmm
!= 0
3919 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3920 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3922 /* clear the arguments that are stored in drex */
3923 UINTS_CLEAR (i
.types
[0]);
3924 UINTS_CLEAR (i
.types
[3]);
3925 i
.reg_operands
-= 2;
3927 /* Specify the modrm encoding for memory addressing. Include
3928 the high order bit that is normally stored in the REX byte
3929 in the register field. */
3930 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
3931 i
.drex
.modrm_reg
= 1;
3932 i
.drex
.modrm_regmem
= 2;
3933 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3934 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3937 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3938 else if (i
.types
[0].bitfield
.regxmm
!= 0
3939 && operand_type_check (i
.types
[1], anymem
) != 0
3940 && i
.types
[2].bitfield
.regxmm
!= 0
3941 && i
.types
[3].bitfield
.regxmm
!= 0
3942 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3943 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3945 /* Clear the arguments that are stored in drex. */
3946 UINTS_CLEAR (i
.types
[0]);
3947 UINTS_CLEAR (i
.types
[3]);
3948 i
.reg_operands
-= 2;
3950 /* Specify the modrm encoding for memory addressing. Include
3951 the high order bit that is normally stored in the REX byte
3952 in the register field. */
3953 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3954 i
.drex
.modrm_reg
= 2;
3955 i
.drex
.modrm_regmem
= 1;
3956 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3957 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3960 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3961 else if (i
.types
[0].bitfield
.regxmm
!= 0
3962 && i
.types
[1].bitfield
.regxmm
!= 0
3963 && i
.types
[2].bitfield
.regxmm
!= 0
3964 && i
.types
[3].bitfield
.regxmm
!= 0
3965 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
3966 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3968 /* clear the arguments that are stored in drex */
3969 UINTS_CLEAR (i
.types
[2]);
3970 UINTS_CLEAR (i
.types
[3]);
3971 i
.reg_operands
-= 2;
3973 /* There are two different ways to encode a 4 operand
3974 instruction with all registers that uses OC1 set to
3975 0 or 1. Favor setting OC1 to 0 since this mimics the
3976 actions of other SSE5 assemblers. Use modrm encoding
3977 2 for register/register. Include the high order bit that
3978 is normally stored in the REX byte in the register
3980 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
3981 i
.drex
.modrm_reg
= 1;
3982 i
.drex
.modrm_regmem
= 0;
3984 /* Remember the register, including the upper bits */
3985 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3986 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3989 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
3990 else if (i
.types
[0].bitfield
.regxmm
!= 0
3991 && (i
.types
[1].bitfield
.regxmm
3992 || operand_type_check (i
.types
[1], anymem
))
3993 && i
.types
[2].bitfield
.regxmm
!= 0
3994 && i
.types
[3].bitfield
.regxmm
!= 0
3995 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
3996 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3998 /* Clear the arguments that are stored in drex. */
3999 UINTS_CLEAR (i
.types
[2]);
4000 UINTS_CLEAR (i
.types
[3]);
4001 i
.reg_operands
-= 2;
4003 /* Specify the modrm encoding and remember the register
4004 including the bits normally stored in the REX byte. */
4005 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4006 i
.drex
.modrm_reg
= 0;
4007 i
.drex
.modrm_regmem
= 1;
4008 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4009 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4012 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4013 else if (operand_type_check (i
.types
[0], anymem
) != 0
4014 && i
.types
[1].bitfield
.regxmm
!= 0
4015 && i
.types
[2].bitfield
.regxmm
!= 0
4016 && i
.types
[3].bitfield
.regxmm
!= 0
4017 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4018 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4020 /* clear the arguments that are stored in drex */
4021 UINTS_CLEAR (i
.types
[2]);
4022 UINTS_CLEAR (i
.types
[3]);
4023 i
.reg_operands
-= 2;
4025 /* Specify the modrm encoding and remember the register
4026 including the bits normally stored in the REX byte. */
4027 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4028 i
.drex
.modrm_reg
= 1;
4029 i
.drex
.modrm_regmem
= 0;
4030 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4031 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4035 as_bad (_("Incorrect operands for the '%s' instruction"),
4039 /* SSE5 instructions with the DREX byte where the only memory operand
4040 is in the 2nd argument, and the first and last xmm register must
4041 match, and is encoded in the DREX byte. */
4042 else if (i
.tm
.opcode_modifier
.drex
4043 && !i
.tm
.opcode_modifier
.drexv
4046 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4047 if (i
.types
[0].bitfield
.regxmm
!= 0
4048 && (i
.types
[1].bitfield
.regxmm
4049 || operand_type_check(i
.types
[1], anymem
))
4050 && i
.types
[2].bitfield
.regxmm
!= 0
4051 && i
.types
[3].bitfield
.regxmm
!= 0
4052 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4053 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4055 /* clear the arguments that are stored in drex */
4056 UINTS_CLEAR (i
.types
[0]);
4057 UINTS_CLEAR (i
.types
[3]);
4058 i
.reg_operands
-= 2;
4060 /* Specify the modrm encoding and remember the register
4061 including the high bit normally stored in the REX
4063 i
.drex
.modrm_reg
= 2;
4064 i
.drex
.modrm_regmem
= 1;
4065 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4066 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4070 as_bad (_("Incorrect operands for the '%s' instruction"),
4074 /* SSE5 3 operand instructions that the result is a register, being
4075 either operand can be a memory operand, using OC0 to note which
4076 one is the memory. */
4077 else if (i
.tm
.opcode_modifier
.drex
4078 && i
.tm
.opcode_modifier
.drexv
4081 i
.tm
.extension_opcode
= None
;
4083 /* Case 1: 3 operand insn, src1 = register. */
4084 if (i
.types
[0].bitfield
.regxmm
!= 0
4085 && i
.types
[1].bitfield
.regxmm
!= 0
4086 && i
.types
[2].bitfield
.regxmm
!= 0)
4088 /* Clear the arguments that are stored in drex. */
4089 UINTS_CLEAR (i
.types
[2]);
4092 /* Specify the modrm encoding and remember the register
4093 including the high bit normally stored in the REX byte. */
4094 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4095 i
.drex
.modrm_reg
= 1;
4096 i
.drex
.modrm_regmem
= 0;
4097 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4098 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4101 /* Case 2: 3 operand insn, src1 = memory. */
4102 else if (operand_type_check (i
.types
[0], anymem
) != 0
4103 && i
.types
[1].bitfield
.regxmm
!= 0
4104 && i
.types
[2].bitfield
.regxmm
!= 0)
4106 /* Clear the arguments that are stored in drex. */
4107 UINTS_CLEAR (i
.types
[2]);
4110 /* Specify the modrm encoding and remember the register
4111 including the high bit normally stored in the REX
4113 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4114 i
.drex
.modrm_reg
= 1;
4115 i
.drex
.modrm_regmem
= 0;
4116 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4117 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4120 /* Case 3: 3 operand insn, src2 = memory. */
4121 else if (i
.types
[0].bitfield
.regxmm
!= 0
4122 && operand_type_check (i
.types
[1], anymem
) != 0
4123 && i
.types
[2].bitfield
.regxmm
!= 0)
4125 /* Clear the arguments that are stored in drex. */
4126 UINTS_CLEAR (i
.types
[2]);
4129 /* Specify the modrm encoding and remember the register
4130 including the high bit normally stored in the REX byte. */
4131 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4132 i
.drex
.modrm_reg
= 0;
4133 i
.drex
.modrm_regmem
= 1;
4134 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4135 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4139 as_bad (_("Incorrect operands for the '%s' instruction"),
4143 /* SSE5 4 operand instructions that are the comparison instructions
4144 where the first operand is the immediate value of the comparison
4146 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4148 /* Case 1: 4 operand insn, src1 = reg/memory. */
4149 if (operand_type_check (i
.types
[0], imm
) != 0
4150 && (i
.types
[1].bitfield
.regxmm
4151 || operand_type_check (i
.types
[1], anymem
))
4152 && i
.types
[2].bitfield
.regxmm
!= 0
4153 && i
.types
[3].bitfield
.regxmm
!= 0)
4155 /* clear the arguments that are stored in drex */
4156 UINTS_CLEAR (i
.types
[3]);
4159 /* Specify the modrm encoding and remember the register
4160 including the high bit normally stored in the REX byte. */
4161 i
.drex
.modrm_reg
= 2;
4162 i
.drex
.modrm_regmem
= 1;
4163 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4164 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4167 /* Case 2: 3 operand insn with ImmExt that places the
4168 opcode_extension as an immediate argument. This is used for
4169 all of the varients of comparison that supplies the appropriate
4170 value as part of the instruction. */
4171 else if ((i
.types
[0].bitfield
.regxmm
4172 || operand_type_check (i
.types
[0], anymem
))
4173 && i
.types
[1].bitfield
.regxmm
!= 0
4174 && i
.types
[2].bitfield
.regxmm
!= 0
4175 && operand_type_check (i
.types
[3], imm
) != 0)
4177 /* clear the arguments that are stored in drex */
4178 UINTS_CLEAR (i
.types
[2]);
4181 /* Specify the modrm encoding and remember the register
4182 including the high bit normally stored in the REX byte. */
4183 i
.drex
.modrm_reg
= 1;
4184 i
.drex
.modrm_regmem
= 0;
4185 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4186 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4190 as_bad (_("Incorrect operands for the '%s' instruction"),
4194 else if (i
.tm
.opcode_modifier
.drex
4195 || i
.tm
.opcode_modifier
.drexv
4196 || i
.tm
.opcode_modifier
.drexc
)
4197 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4201 process_operands (void)
4203 /* Default segment register this instruction will use for memory
4204 accesses. 0 means unknown. This is only for optimizing out
4205 unnecessary segment overrides. */
4206 const seg_entry
*default_seg
= 0;
4208 /* Handle all of the DREX munging that SSE5 needs. */
4209 if (i
.tm
.opcode_modifier
.drex
4210 || i
.tm
.opcode_modifier
.drexv
4211 || i
.tm
.opcode_modifier
.drexc
)
4214 if (i
.tm
.opcode_modifier
.firstxmm0
)
4218 /* The first operand is implicit and must be xmm0. */
4219 assert (i
.reg_operands
&& UINTS_EQUAL (i
.types
[0], regxmm
));
4220 if (i
.op
[0].regs
->reg_num
!= 0)
4223 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4224 i
.tm
.name
, register_prefix
);
4226 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4227 i
.tm
.name
, register_prefix
);
4231 for (j
= 1; j
< i
.operands
; j
++)
4233 i
.op
[j
- 1] = i
.op
[j
];
4234 i
.types
[j
- 1] = i
.types
[j
];
4236 /* We need to adjust fields in i.tm since they are used by
4237 build_modrm_byte. */
4238 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4245 else if (i
.tm
.opcode_modifier
.regkludge
)
4247 /* The imul $imm, %reg instruction is converted into
4248 imul $imm, %reg, %reg, and the clr %reg instruction
4249 is converted into xor %reg, %reg. */
4251 unsigned int first_reg_op
;
4253 if (operand_type_check (i
.types
[0], reg
))
4257 /* Pretend we saw the extra register operand. */
4258 assert (i
.reg_operands
== 1
4259 && i
.op
[first_reg_op
+ 1].regs
== 0);
4260 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4261 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4266 if (i
.tm
.opcode_modifier
.shortform
)
4268 if (i
.types
[0].bitfield
.sreg2
4269 || i
.types
[0].bitfield
.sreg3
)
4271 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4272 && i
.op
[0].regs
->reg_num
== 1)
4274 as_bad (_("you can't `pop %%cs'"));
4277 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4278 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4283 /* The register or float register operand is in operand
4287 if (i
.types
[0].bitfield
.floatreg
4288 || operand_type_check (i
.types
[0], reg
))
4292 /* Register goes in low 3 bits of opcode. */
4293 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4294 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4296 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4298 /* Warn about some common errors, but press on regardless.
4299 The first case can be generated by gcc (<= 2.8.1). */
4300 if (i
.operands
== 2)
4302 /* Reversed arguments on faddp, fsubp, etc. */
4303 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4304 register_prefix
, i
.op
[1].regs
->reg_name
,
4305 register_prefix
, i
.op
[0].regs
->reg_name
);
4309 /* Extraneous `l' suffix on fp insn. */
4310 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4311 register_prefix
, i
.op
[0].regs
->reg_name
);
4316 else if (i
.tm
.opcode_modifier
.modrm
)
4318 /* The opcode is completed (modulo i.tm.extension_opcode which
4319 must be put into the modrm byte). Now, we make the modrm and
4320 index base bytes based on all the info we've collected. */
4322 default_seg
= build_modrm_byte ();
4324 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4328 else if (i
.tm
.opcode_modifier
.isstring
)
4330 /* For the string instructions that allow a segment override
4331 on one of their operands, the default segment is ds. */
4335 if (i
.tm
.base_opcode
== 0x8d /* lea */
4338 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4340 /* If a segment was explicitly specified, and the specified segment
4341 is not the default, use an opcode prefix to select it. If we
4342 never figured out what the default segment is, then default_seg
4343 will be zero at this point, and the specified segment prefix will
4345 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4347 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4353 static const seg_entry
*
4354 build_modrm_byte (void)
4356 const seg_entry
*default_seg
= 0;
4358 /* SSE5 4 operand instructions are encoded in such a way that one of
4359 the inputs must match the destination register. Process_drex hides
4360 the 3rd argument in the drex field, so that by the time we get
4361 here, it looks to GAS as if this is a 2 operand instruction. */
4362 if ((i
.tm
.opcode_modifier
.drex
4363 || i
.tm
.opcode_modifier
.drexv
4364 || i
.tm
.opcode_modifier
.drexc
)
4365 && i
.reg_operands
== 2)
4367 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
4368 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
4370 i
.rm
.reg
= reg
->reg_num
;
4371 i
.rm
.regmem
= regmem
->reg_num
;
4373 if ((reg
->reg_flags
& RegRex
) != 0)
4375 if ((regmem
->reg_flags
& RegRex
) != 0)
4379 /* i.reg_operands MUST be the number of real register operands;
4380 implicit registers do not count. */
4381 else if (i
.reg_operands
== 2)
4383 unsigned int source
, dest
;
4391 /* When there are 3 operands, one of them may be immediate,
4392 which may be the first or the last operand. Otherwise,
4393 the first operand must be shift count register (cl). */
4394 assert (i
.imm_operands
== 1
4395 || (i
.imm_operands
== 0
4396 && i
.types
[0].bitfield
.shiftcount
));
4397 if (operand_type_check (i
.types
[0], imm
)
4398 || i
.types
[0].bitfield
.shiftcount
)
4404 /* When there are 4 operands, the first two must be 8bit
4405 immediate operands. The source operand will be the 3rd
4407 assert (i
.imm_operands
== 2
4408 && i
.types
[0].bitfield
.imm8
4409 && i
.types
[1].bitfield
.imm8
);
4419 /* One of the register operands will be encoded in the i.tm.reg
4420 field, the other in the combined i.tm.mode and i.tm.regmem
4421 fields. If no form of this instruction supports a memory
4422 destination operand, then we assume the source operand may
4423 sometimes be a memory operand and so we need to store the
4424 destination in the i.rm.reg field. */
4425 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4426 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4428 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4429 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4430 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4432 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4437 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4438 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4439 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4441 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4444 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4446 if (!i
.types
[0].bitfield
.control
4447 && !i
.types
[1].bitfield
.control
)
4449 i
.rex
&= ~(REX_R
| REX_B
);
4450 add_prefix (LOCK_PREFIX_OPCODE
);
4454 { /* If it's not 2 reg operands... */
4457 unsigned int fake_zero_displacement
= 0;
4460 /* This has been precalculated for SSE5 instructions
4461 that have a DREX field earlier in process_drex. */
4462 if (i
.tm
.opcode_modifier
.drex
4463 || i
.tm
.opcode_modifier
.drexv
4464 || i
.tm
.opcode_modifier
.drexc
)
4465 op
= i
.drex
.modrm_regmem
;
4468 for (op
= 0; op
< i
.operands
; op
++)
4469 if (operand_type_check (i
.types
[op
], anymem
))
4471 assert (op
< i
.operands
);
4476 if (i
.base_reg
== 0)
4479 if (!i
.disp_operands
)
4480 fake_zero_displacement
= 1;
4481 if (i
.index_reg
== 0)
4483 /* Operand is just <disp> */
4484 if (flag_code
== CODE_64BIT
)
4486 /* 64bit mode overwrites the 32bit absolute
4487 addressing by RIP relative addressing and
4488 absolute addressing is encoded by one of the
4489 redundant SIB forms. */
4490 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4491 i
.sib
.base
= NO_BASE_REGISTER
;
4492 i
.sib
.index
= NO_INDEX_REGISTER
;
4493 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4494 ? disp32s
: disp32
);
4496 else if ((flag_code
== CODE_16BIT
)
4497 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4499 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4500 i
.types
[op
] = disp16
;
4504 i
.rm
.regmem
= NO_BASE_REGISTER
;
4505 i
.types
[op
] = disp32
;
4508 else /* !i.base_reg && i.index_reg */
4510 if (i
.index_reg
->reg_num
== RegEiz
4511 || i
.index_reg
->reg_num
== RegRiz
)
4512 i
.sib
.index
= NO_INDEX_REGISTER
;
4514 i
.sib
.index
= i
.index_reg
->reg_num
;
4515 i
.sib
.base
= NO_BASE_REGISTER
;
4516 i
.sib
.scale
= i
.log2_scale_factor
;
4517 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4518 i
.types
[op
].bitfield
.disp8
= 0;
4519 i
.types
[op
].bitfield
.disp16
= 0;
4520 i
.types
[op
].bitfield
.disp64
= 0;
4521 if (flag_code
!= CODE_64BIT
)
4523 /* Must be 32 bit */
4524 i
.types
[op
].bitfield
.disp32
= 1;
4525 i
.types
[op
].bitfield
.disp32s
= 0;
4529 i
.types
[op
].bitfield
.disp32
= 0;
4530 i
.types
[op
].bitfield
.disp32s
= 1;
4532 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4536 /* RIP addressing for 64bit mode. */
4537 else if (i
.base_reg
->reg_num
== RegRip
||
4538 i
.base_reg
->reg_num
== RegEip
)
4540 i
.rm
.regmem
= NO_BASE_REGISTER
;
4541 i
.types
[op
].bitfield
.disp8
= 0;
4542 i
.types
[op
].bitfield
.disp16
= 0;
4543 i
.types
[op
].bitfield
.disp32
= 0;
4544 i
.types
[op
].bitfield
.disp32s
= 1;
4545 i
.types
[op
].bitfield
.disp64
= 0;
4546 i
.flags
[op
] |= Operand_PCrel
;
4547 if (! i
.disp_operands
)
4548 fake_zero_displacement
= 1;
4550 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4552 switch (i
.base_reg
->reg_num
)
4555 if (i
.index_reg
== 0)
4557 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4558 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4562 if (i
.index_reg
== 0)
4565 if (operand_type_check (i
.types
[op
], disp
) == 0)
4567 /* fake (%bp) into 0(%bp) */
4568 i
.types
[op
].bitfield
.disp8
= 1;
4569 fake_zero_displacement
= 1;
4572 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4573 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4575 default: /* (%si) -> 4 or (%di) -> 5 */
4576 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4578 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4580 else /* i.base_reg and 32/64 bit mode */
4582 if (flag_code
== CODE_64BIT
4583 && operand_type_check (i
.types
[op
], disp
))
4585 i386_operand_type temp
;
4587 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4589 if (i
.prefix
[ADDR_PREFIX
] == 0)
4590 i
.types
[op
].bitfield
.disp32s
= 1;
4592 i
.types
[op
].bitfield
.disp32
= 1;
4595 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4596 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4598 i
.sib
.base
= i
.base_reg
->reg_num
;
4599 /* x86-64 ignores REX prefix bit here to avoid decoder
4601 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4604 if (i
.disp_operands
== 0)
4606 fake_zero_displacement
= 1;
4607 i
.types
[op
].bitfield
.disp8
= 1;
4610 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4614 i
.sib
.scale
= i
.log2_scale_factor
;
4615 if (i
.index_reg
== 0)
4617 /* <disp>(%esp) becomes two byte modrm with no index
4618 register. We've already stored the code for esp
4619 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4620 Any base register besides %esp will not use the
4621 extra modrm byte. */
4622 i
.sib
.index
= NO_INDEX_REGISTER
;
4626 if (i
.index_reg
->reg_num
== RegEiz
4627 || i
.index_reg
->reg_num
== RegRiz
)
4628 i
.sib
.index
= NO_INDEX_REGISTER
;
4630 i
.sib
.index
= i
.index_reg
->reg_num
;
4631 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4632 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4637 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4638 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4641 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4644 if (fake_zero_displacement
)
4646 /* Fakes a zero displacement assuming that i.types[op]
4647 holds the correct displacement size. */
4650 assert (i
.op
[op
].disps
== 0);
4651 exp
= &disp_expressions
[i
.disp_operands
++];
4652 i
.op
[op
].disps
= exp
;
4653 exp
->X_op
= O_constant
;
4654 exp
->X_add_number
= 0;
4655 exp
->X_add_symbol
= (symbolS
*) 0;
4656 exp
->X_op_symbol
= (symbolS
*) 0;
4660 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4661 (if any) based on i.tm.extension_opcode. Again, we must be
4662 careful to make sure that segment/control/debug/test/MMX
4663 registers are coded into the i.rm.reg field. */
4668 /* This has been precalculated for SSE5 instructions
4669 that have a DREX field earlier in process_drex. */
4670 if (i
.tm
.opcode_modifier
.drex
4671 || i
.tm
.opcode_modifier
.drexv
4672 || i
.tm
.opcode_modifier
.drexc
)
4674 op
= i
.drex
.modrm_reg
;
4675 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4676 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4681 for (op
= 0; op
< i
.operands
; op
++)
4682 if (i
.types
[op
].bitfield
.reg8
4683 || i
.types
[op
].bitfield
.reg16
4684 || i
.types
[op
].bitfield
.reg32
4685 || i
.types
[op
].bitfield
.reg64
4686 || i
.types
[op
].bitfield
.regmmx
4687 || i
.types
[op
].bitfield
.regxmm
4688 || i
.types
[op
].bitfield
.sreg2
4689 || i
.types
[op
].bitfield
.sreg3
4690 || i
.types
[op
].bitfield
.control
4691 || i
.types
[op
].bitfield
.debug
4692 || i
.types
[op
].bitfield
.test
)
4695 assert (op
< i
.operands
);
4697 /* If there is an extension opcode to put here, the
4698 register number must be put into the regmem field. */
4699 if (i
.tm
.extension_opcode
!= None
)
4701 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4702 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4707 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4708 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4713 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4714 must set it to 3 to indicate this is a register operand
4715 in the regmem field. */
4716 if (!i
.mem_operands
)
4720 /* Fill in i.rm.reg field with extension opcode (if any). */
4721 if (i
.tm
.extension_opcode
!= None
4722 && !(i
.tm
.opcode_modifier
.drex
4723 || i
.tm
.opcode_modifier
.drexv
4724 || i
.tm
.opcode_modifier
.drexc
))
4725 i
.rm
.reg
= i
.tm
.extension_opcode
;
4731 output_branch (void)
4736 relax_substateT subtype
;
4741 if (flag_code
== CODE_16BIT
)
4745 if (i
.prefix
[DATA_PREFIX
] != 0)
4751 /* Pentium4 branch hints. */
4752 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4753 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4758 if (i
.prefix
[REX_PREFIX
] != 0)
4764 if (i
.prefixes
!= 0 && !intel_syntax
)
4765 as_warn (_("skipping prefixes on this instruction"));
4767 /* It's always a symbol; End frag & setup for relax.
4768 Make sure there is enough room in this frag for the largest
4769 instruction we may generate in md_convert_frag. This is 2
4770 bytes for the opcode and room for the prefix and largest
4772 frag_grow (prefix
+ 2 + 4);
4773 /* Prefix and 1 opcode byte go in fr_fix. */
4774 p
= frag_more (prefix
+ 1);
4775 if (i
.prefix
[DATA_PREFIX
] != 0)
4776 *p
++ = DATA_PREFIX_OPCODE
;
4777 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4778 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4779 *p
++ = i
.prefix
[SEG_PREFIX
];
4780 if (i
.prefix
[REX_PREFIX
] != 0)
4781 *p
++ = i
.prefix
[REX_PREFIX
];
4782 *p
= i
.tm
.base_opcode
;
4784 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4785 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4786 else if (cpu_arch_flags
.bitfield
.cpui386
)
4787 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4789 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4792 sym
= i
.op
[0].disps
->X_add_symbol
;
4793 off
= i
.op
[0].disps
->X_add_number
;
4795 if (i
.op
[0].disps
->X_op
!= O_constant
4796 && i
.op
[0].disps
->X_op
!= O_symbol
)
4798 /* Handle complex expressions. */
4799 sym
= make_expr_symbol (i
.op
[0].disps
);
4803 /* 1 possible extra opcode + 4 byte displacement go in var part.
4804 Pass reloc in fr_var. */
4805 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4815 if (i
.tm
.opcode_modifier
.jumpbyte
)
4817 /* This is a loop or jecxz type instruction. */
4819 if (i
.prefix
[ADDR_PREFIX
] != 0)
4821 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4824 /* Pentium4 branch hints. */
4825 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4826 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4828 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4837 if (flag_code
== CODE_16BIT
)
4840 if (i
.prefix
[DATA_PREFIX
] != 0)
4842 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4852 if (i
.prefix
[REX_PREFIX
] != 0)
4854 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4858 if (i
.prefixes
!= 0 && !intel_syntax
)
4859 as_warn (_("skipping prefixes on this instruction"));
4861 p
= frag_more (1 + size
);
4862 *p
++ = i
.tm
.base_opcode
;
4864 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4865 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4867 /* All jumps handled here are signed, but don't use a signed limit
4868 check for 32 and 16 bit jumps as we want to allow wrap around at
4869 4G and 64k respectively. */
4871 fixP
->fx_signed
= 1;
4875 output_interseg_jump (void)
4883 if (flag_code
== CODE_16BIT
)
4887 if (i
.prefix
[DATA_PREFIX
] != 0)
4893 if (i
.prefix
[REX_PREFIX
] != 0)
4903 if (i
.prefixes
!= 0 && !intel_syntax
)
4904 as_warn (_("skipping prefixes on this instruction"));
4906 /* 1 opcode; 2 segment; offset */
4907 p
= frag_more (prefix
+ 1 + 2 + size
);
4909 if (i
.prefix
[DATA_PREFIX
] != 0)
4910 *p
++ = DATA_PREFIX_OPCODE
;
4912 if (i
.prefix
[REX_PREFIX
] != 0)
4913 *p
++ = i
.prefix
[REX_PREFIX
];
4915 *p
++ = i
.tm
.base_opcode
;
4916 if (i
.op
[1].imms
->X_op
== O_constant
)
4918 offsetT n
= i
.op
[1].imms
->X_add_number
;
4921 && !fits_in_unsigned_word (n
)
4922 && !fits_in_signed_word (n
))
4924 as_bad (_("16-bit jump out of range"));
4927 md_number_to_chars (p
, n
, size
);
4930 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4931 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4932 if (i
.op
[0].imms
->X_op
!= O_constant
)
4933 as_bad (_("can't handle non absolute segment in `%s'"),
4935 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4941 fragS
*insn_start_frag
;
4942 offsetT insn_start_off
;
4944 /* Tie dwarf2 debug info to the address at the start of the insn.
4945 We can't do this after the insn has been output as the current
4946 frag may have been closed off. eg. by frag_var. */
4947 dwarf2_emit_insn (0);
4949 insn_start_frag
= frag_now
;
4950 insn_start_off
= frag_now_fix ();
4953 if (i
.tm
.opcode_modifier
.jump
)
4955 else if (i
.tm
.opcode_modifier
.jumpbyte
4956 || i
.tm
.opcode_modifier
.jumpdword
)
4958 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
4959 output_interseg_jump ();
4962 /* Output normal instructions here. */
4966 unsigned int prefix
;
4968 switch (i
.tm
.opcode_length
)
4971 if (i
.tm
.base_opcode
& 0xff000000)
4973 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
4978 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
4980 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
4981 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
4984 if (prefix
!= REPE_PREFIX_OPCODE
4985 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
4986 add_prefix (prefix
);
4989 add_prefix (prefix
);
4998 /* The prefix bytes. */
4999 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5001 FRAG_APPEND_1_CHAR (*q
);
5003 /* Now the opcode; be careful about word order here! */
5004 if (i
.tm
.opcode_length
== 1)
5006 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5010 switch (i
.tm
.opcode_length
)
5014 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5024 /* Put out high byte first: can't use md_number_to_chars! */
5025 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5026 *p
= i
.tm
.base_opcode
& 0xff;
5028 /* On SSE5, encode the OC1 bit in the DREX field if this
5029 encoding has multiple formats. */
5030 if (i
.tm
.opcode_modifier
.drex
5031 && i
.tm
.opcode_modifier
.drexv
5032 && DREX_OC1 (i
.tm
.extension_opcode
))
5033 *p
|= DREX_OC1_MASK
;
5036 /* Now the modrm byte and sib byte (if present). */
5037 if (i
.tm
.opcode_modifier
.modrm
)
5039 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5042 /* If i.rm.regmem == ESP (4)
5043 && i.rm.mode != (Register mode)
5045 ==> need second modrm byte. */
5046 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5048 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5049 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5051 | i
.sib
.scale
<< 6));
5054 /* Write the DREX byte if needed. */
5055 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5058 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5060 /* Encode the OC0 bit if this encoding has multiple
5062 if ((i
.tm
.opcode_modifier
.drex
5063 || i
.tm
.opcode_modifier
.drexv
)
5064 && DREX_OC0 (i
.tm
.extension_opcode
))
5065 *p
|= DREX_OC0_MASK
;
5068 if (i
.disp_operands
)
5069 output_disp (insn_start_frag
, insn_start_off
);
5072 output_imm (insn_start_frag
, insn_start_off
);
5078 pi ("" /*line*/, &i
);
5080 #endif /* DEBUG386 */
5083 /* Return the size of the displacement operand N. */
5086 disp_size (unsigned int n
)
5089 if (i
.types
[n
].bitfield
.disp64
)
5091 else if (i
.types
[n
].bitfield
.disp8
)
5093 else if (i
.types
[n
].bitfield
.disp16
)
5098 /* Return the size of the immediate operand N. */
5101 imm_size (unsigned int n
)
5104 if (i
.types
[n
].bitfield
.imm64
)
5106 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5108 else if (i
.types
[n
].bitfield
.imm16
)
5114 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5119 for (n
= 0; n
< i
.operands
; n
++)
5121 if (operand_type_check (i
.types
[n
], disp
))
5123 if (i
.op
[n
].disps
->X_op
== O_constant
)
5125 int size
= disp_size (n
);
5128 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5130 p
= frag_more (size
);
5131 md_number_to_chars (p
, val
, size
);
5135 enum bfd_reloc_code_real reloc_type
;
5136 int size
= disp_size (n
);
5137 int sign
= i
.types
[n
].bitfield
.disp32s
;
5138 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5140 /* We can't have 8 bit displacement here. */
5141 assert (!i
.types
[n
].bitfield
.disp8
);
5143 /* The PC relative address is computed relative
5144 to the instruction boundary, so in case immediate
5145 fields follows, we need to adjust the value. */
5146 if (pcrel
&& i
.imm_operands
)
5151 for (n1
= 0; n1
< i
.operands
; n1
++)
5152 if (operand_type_check (i
.types
[n1
], imm
))
5154 /* Only one immediate is allowed for PC
5155 relative address. */
5158 i
.op
[n
].disps
->X_add_number
-= sz
;
5160 /* We should find the immediate. */
5164 p
= frag_more (size
);
5165 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5167 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5168 && (((reloc_type
== BFD_RELOC_32
5169 || reloc_type
== BFD_RELOC_X86_64_32S
5170 || (reloc_type
== BFD_RELOC_64
5172 && (i
.op
[n
].disps
->X_op
== O_symbol
5173 || (i
.op
[n
].disps
->X_op
== O_add
5174 && ((symbol_get_value_expression
5175 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5177 || reloc_type
== BFD_RELOC_32_PCREL
))
5181 if (insn_start_frag
== frag_now
)
5182 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5187 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5188 for (fr
= insn_start_frag
->fr_next
;
5189 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5191 add
+= p
- frag_now
->fr_literal
;
5196 reloc_type
= BFD_RELOC_386_GOTPC
;
5197 i
.op
[n
].imms
->X_add_number
+= add
;
5199 else if (reloc_type
== BFD_RELOC_64
)
5200 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5202 /* Don't do the adjustment for x86-64, as there
5203 the pcrel addressing is relative to the _next_
5204 insn, and that is taken care of in other code. */
5205 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5207 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5208 i
.op
[n
].disps
, pcrel
, reloc_type
);
5215 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5220 for (n
= 0; n
< i
.operands
; n
++)
5222 if (operand_type_check (i
.types
[n
], imm
))
5224 if (i
.op
[n
].imms
->X_op
== O_constant
)
5226 int size
= imm_size (n
);
5229 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5231 p
= frag_more (size
);
5232 md_number_to_chars (p
, val
, size
);
5236 /* Not absolute_section.
5237 Need a 32-bit fixup (don't support 8bit
5238 non-absolute imms). Try to support other
5240 enum bfd_reloc_code_real reloc_type
;
5241 int size
= imm_size (n
);
5244 if (i
.types
[n
].bitfield
.imm32s
5245 && (i
.suffix
== QWORD_MNEM_SUFFIX
5246 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5251 p
= frag_more (size
);
5252 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5254 /* This is tough to explain. We end up with this one if we
5255 * have operands that look like
5256 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5257 * obtain the absolute address of the GOT, and it is strongly
5258 * preferable from a performance point of view to avoid using
5259 * a runtime relocation for this. The actual sequence of
5260 * instructions often look something like:
5265 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5267 * The call and pop essentially return the absolute address
5268 * of the label .L66 and store it in %ebx. The linker itself
5269 * will ultimately change the first operand of the addl so
5270 * that %ebx points to the GOT, but to keep things simple, the
5271 * .o file must have this operand set so that it generates not
5272 * the absolute address of .L66, but the absolute address of
5273 * itself. This allows the linker itself simply treat a GOTPC
5274 * relocation as asking for a pcrel offset to the GOT to be
5275 * added in, and the addend of the relocation is stored in the
5276 * operand field for the instruction itself.
5278 * Our job here is to fix the operand so that it would add
5279 * the correct offset so that %ebx would point to itself. The
5280 * thing that is tricky is that .-.L66 will point to the
5281 * beginning of the instruction, so we need to further modify
5282 * the operand so that it will point to itself. There are
5283 * other cases where you have something like:
5285 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5287 * and here no correction would be required. Internally in
5288 * the assembler we treat operands of this form as not being
5289 * pcrel since the '.' is explicitly mentioned, and I wonder
5290 * whether it would simplify matters to do it this way. Who
5291 * knows. In earlier versions of the PIC patches, the
5292 * pcrel_adjust field was used to store the correction, but
5293 * since the expression is not pcrel, I felt it would be
5294 * confusing to do it this way. */
5296 if ((reloc_type
== BFD_RELOC_32
5297 || reloc_type
== BFD_RELOC_X86_64_32S
5298 || reloc_type
== BFD_RELOC_64
)
5300 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5301 && (i
.op
[n
].imms
->X_op
== O_symbol
5302 || (i
.op
[n
].imms
->X_op
== O_add
5303 && ((symbol_get_value_expression
5304 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5309 if (insn_start_frag
== frag_now
)
5310 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5315 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5316 for (fr
= insn_start_frag
->fr_next
;
5317 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5319 add
+= p
- frag_now
->fr_literal
;
5323 reloc_type
= BFD_RELOC_386_GOTPC
;
5325 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5327 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5328 i
.op
[n
].imms
->X_add_number
+= add
;
5330 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5331 i
.op
[n
].imms
, 0, reloc_type
);
5337 /* x86_cons_fix_new is called via the expression parsing code when a
5338 reloc is needed. We use this hook to get the correct .got reloc. */
5339 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5340 static int cons_sign
= -1;
5343 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5346 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5348 got_reloc
= NO_RELOC
;
5351 if (exp
->X_op
== O_secrel
)
5353 exp
->X_op
= O_symbol
;
5354 r
= BFD_RELOC_32_SECREL
;
5358 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5361 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5362 # define lex_got(reloc, adjust, types) NULL
5364 /* Parse operands of the form
5365 <symbol>@GOTOFF+<nnn>
5366 and similar .plt or .got references.
5368 If we find one, set up the correct relocation in RELOC and copy the
5369 input string, minus the `@GOTOFF' into a malloc'd buffer for
5370 parsing by the calling routine. Return this buffer, and if ADJUST
5371 is non-null set it to the length of the string we removed from the
5372 input line. Otherwise return NULL. */
5374 lex_got (enum bfd_reloc_code_real
*reloc
,
5376 i386_operand_type
*types
)
5378 /* Some of the relocations depend on the size of what field is to
5379 be relocated. But in our callers i386_immediate and i386_displacement
5380 we don't yet know the operand size (this will be set by insn
5381 matching). Hence we record the word32 relocation here,
5382 and adjust the reloc according to the real size in reloc(). */
5383 static const struct {
5385 const enum bfd_reloc_code_real rel
[2];
5386 const i386_operand_type types64
;
5389 BFD_RELOC_X86_64_PLTOFF64
},
5390 OPERAND_TYPE_IMM64
},
5391 { "PLT", { BFD_RELOC_386_PLT32
,
5392 BFD_RELOC_X86_64_PLT32
},
5393 OPERAND_TYPE_IMM32_32S_DISP32
},
5395 BFD_RELOC_X86_64_GOTPLT64
},
5396 OPERAND_TYPE_IMM64_DISP64
},
5397 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5398 BFD_RELOC_X86_64_GOTOFF64
},
5399 OPERAND_TYPE_IMM64_DISP64
},
5401 BFD_RELOC_X86_64_GOTPCREL
},
5402 OPERAND_TYPE_IMM32_32S_DISP32
},
5403 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5404 BFD_RELOC_X86_64_TLSGD
},
5405 OPERAND_TYPE_IMM32_32S_DISP32
},
5406 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5408 OPERAND_TYPE_NONE
},
5410 BFD_RELOC_X86_64_TLSLD
},
5411 OPERAND_TYPE_IMM32_32S_DISP32
},
5412 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5413 BFD_RELOC_X86_64_GOTTPOFF
},
5414 OPERAND_TYPE_IMM32_32S_DISP32
},
5415 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5416 BFD_RELOC_X86_64_TPOFF32
},
5417 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5418 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5420 OPERAND_TYPE_NONE
},
5421 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5422 BFD_RELOC_X86_64_DTPOFF32
},
5424 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5425 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5427 OPERAND_TYPE_NONE
},
5428 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5430 OPERAND_TYPE_NONE
},
5431 { "GOT", { BFD_RELOC_386_GOT32
,
5432 BFD_RELOC_X86_64_GOT32
},
5433 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5434 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5435 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5436 OPERAND_TYPE_IMM32_32S_DISP32
},
5437 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5438 BFD_RELOC_X86_64_TLSDESC_CALL
},
5439 OPERAND_TYPE_IMM32_32S_DISP32
},
5447 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5448 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5451 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5455 len
= strlen (gotrel
[j
].str
);
5456 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5458 if (gotrel
[j
].rel
[object_64bit
] != 0)
5461 char *tmpbuf
, *past_reloc
;
5463 *reloc
= gotrel
[j
].rel
[object_64bit
];
5469 if (flag_code
!= CODE_64BIT
)
5471 types
->bitfield
.imm32
= 1;
5472 types
->bitfield
.disp32
= 1;
5475 *types
= gotrel
[j
].types64
;
5478 if (GOT_symbol
== NULL
)
5479 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5481 /* The length of the first part of our input line. */
5482 first
= cp
- input_line_pointer
;
5484 /* The second part goes from after the reloc token until
5485 (and including) an end_of_line char or comma. */
5486 past_reloc
= cp
+ 1 + len
;
5488 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5490 second
= cp
+ 1 - past_reloc
;
5492 /* Allocate and copy string. The trailing NUL shouldn't
5493 be necessary, but be safe. */
5494 tmpbuf
= xmalloc (first
+ second
+ 2);
5495 memcpy (tmpbuf
, input_line_pointer
, first
);
5496 if (second
!= 0 && *past_reloc
!= ' ')
5497 /* Replace the relocation token with ' ', so that
5498 errors like foo@GOTOFF1 will be detected. */
5499 tmpbuf
[first
++] = ' ';
5500 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5501 tmpbuf
[first
+ second
] = '\0';
5505 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5506 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5511 /* Might be a symbol version string. Don't as_bad here. */
5516 x86_cons (expressionS
*exp
, int size
)
5518 if (size
== 4 || (object_64bit
&& size
== 8))
5520 /* Handle @GOTOFF and the like in an expression. */
5522 char *gotfree_input_line
;
5525 save
= input_line_pointer
;
5526 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5527 if (gotfree_input_line
)
5528 input_line_pointer
= gotfree_input_line
;
5532 if (gotfree_input_line
)
5534 /* expression () has merrily parsed up to the end of line,
5535 or a comma - in the wrong buffer. Transfer how far
5536 input_line_pointer has moved to the right buffer. */
5537 input_line_pointer
= (save
5538 + (input_line_pointer
- gotfree_input_line
)
5540 free (gotfree_input_line
);
5541 if (exp
->X_op
== O_constant
5542 || exp
->X_op
== O_absent
5543 || exp
->X_op
== O_illegal
5544 || exp
->X_op
== O_register
5545 || exp
->X_op
== O_big
)
5547 char c
= *input_line_pointer
;
5548 *input_line_pointer
= 0;
5549 as_bad (_("missing or invalid expression `%s'"), save
);
5550 *input_line_pointer
= c
;
5559 static void signed_cons (int size
)
5561 if (flag_code
== CODE_64BIT
)
5569 pe_directive_secrel (dummy
)
5570 int dummy ATTRIBUTE_UNUSED
;
5577 if (exp
.X_op
== O_symbol
)
5578 exp
.X_op
= O_secrel
;
5580 emit_expr (&exp
, 4);
5582 while (*input_line_pointer
++ == ',');
5584 input_line_pointer
--;
5585 demand_empty_rest_of_line ();
5590 i386_immediate (char *imm_start
)
5592 char *save_input_line_pointer
;
5593 char *gotfree_input_line
;
5596 i386_operand_type types
;
5598 UINTS_SET (types
, ~0);
5600 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5602 as_bad (_("at most %d immediate operands are allowed"),
5603 MAX_IMMEDIATE_OPERANDS
);
5607 exp
= &im_expressions
[i
.imm_operands
++];
5608 i
.op
[this_operand
].imms
= exp
;
5610 if (is_space_char (*imm_start
))
5613 save_input_line_pointer
= input_line_pointer
;
5614 input_line_pointer
= imm_start
;
5616 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5617 if (gotfree_input_line
)
5618 input_line_pointer
= gotfree_input_line
;
5620 exp_seg
= expression (exp
);
5623 if (*input_line_pointer
)
5624 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5626 input_line_pointer
= save_input_line_pointer
;
5627 if (gotfree_input_line
)
5628 free (gotfree_input_line
);
5630 if (exp
->X_op
== O_absent
5631 || exp
->X_op
== O_illegal
5632 || exp
->X_op
== O_big
5633 || (gotfree_input_line
5634 && (exp
->X_op
== O_constant
5635 || exp
->X_op
== O_register
)))
5637 as_bad (_("missing or invalid immediate expression `%s'"),
5641 else if (exp
->X_op
== O_constant
)
5643 /* Size it properly later. */
5644 i
.types
[this_operand
].bitfield
.imm64
= 1;
5645 /* If BFD64, sign extend val. */
5646 if (!use_rela_relocations
5647 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5649 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5651 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5652 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5653 && exp_seg
!= absolute_section
5654 && exp_seg
!= text_section
5655 && exp_seg
!= data_section
5656 && exp_seg
!= bss_section
5657 && exp_seg
!= undefined_section
5658 && !bfd_is_com_section (exp_seg
))
5660 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5664 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5666 as_bad (_("illegal immediate register operand %s"), imm_start
);
5671 /* This is an address. The size of the address will be
5672 determined later, depending on destination register,
5673 suffix, or the default for the section. */
5674 i
.types
[this_operand
].bitfield
.imm8
= 1;
5675 i
.types
[this_operand
].bitfield
.imm16
= 1;
5676 i
.types
[this_operand
].bitfield
.imm32
= 1;
5677 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5678 i
.types
[this_operand
].bitfield
.imm64
= 1;
5679 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5687 i386_scale (char *scale
)
5690 char *save
= input_line_pointer
;
5692 input_line_pointer
= scale
;
5693 val
= get_absolute_expression ();
5698 i
.log2_scale_factor
= 0;
5701 i
.log2_scale_factor
= 1;
5704 i
.log2_scale_factor
= 2;
5707 i
.log2_scale_factor
= 3;
5711 char sep
= *input_line_pointer
;
5713 *input_line_pointer
= '\0';
5714 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5716 *input_line_pointer
= sep
;
5717 input_line_pointer
= save
;
5721 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5723 as_warn (_("scale factor of %d without an index register"),
5724 1 << i
.log2_scale_factor
);
5725 i
.log2_scale_factor
= 0;
5727 scale
= input_line_pointer
;
5728 input_line_pointer
= save
;
5733 i386_displacement (char *disp_start
, char *disp_end
)
5737 char *save_input_line_pointer
;
5738 char *gotfree_input_line
;
5740 i386_operand_type bigdisp
, types
= anydisp
;
5743 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5745 as_bad (_("at most %d displacement operands are allowed"),
5746 MAX_MEMORY_OPERANDS
);
5750 UINTS_CLEAR (bigdisp
);
5751 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5752 || (!current_templates
->start
->opcode_modifier
.jump
5753 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5755 bigdisp
.bitfield
.disp32
= 1;
5756 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5757 if (flag_code
== CODE_64BIT
)
5761 bigdisp
.bitfield
.disp32s
= 1;
5762 bigdisp
.bitfield
.disp64
= 1;
5765 else if ((flag_code
== CODE_16BIT
) ^ override
)
5767 bigdisp
.bitfield
.disp32
= 0;
5768 bigdisp
.bitfield
.disp16
= 1;
5773 /* For PC-relative branches, the width of the displacement
5774 is dependent upon data size, not address size. */
5775 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5776 if (flag_code
== CODE_64BIT
)
5778 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5779 bigdisp
.bitfield
.disp16
= 1;
5782 bigdisp
.bitfield
.disp32
= 1;
5783 bigdisp
.bitfield
.disp32s
= 1;
5789 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5791 : LONG_MNEM_SUFFIX
));
5792 bigdisp
.bitfield
.disp32
= 1;
5793 if ((flag_code
== CODE_16BIT
) ^ override
)
5795 bigdisp
.bitfield
.disp32
= 0;
5796 bigdisp
.bitfield
.disp16
= 1;
5800 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5803 exp
= &disp_expressions
[i
.disp_operands
];
5804 i
.op
[this_operand
].disps
= exp
;
5806 save_input_line_pointer
= input_line_pointer
;
5807 input_line_pointer
= disp_start
;
5808 END_STRING_AND_SAVE (disp_end
);
5810 #ifndef GCC_ASM_O_HACK
5811 #define GCC_ASM_O_HACK 0
5814 END_STRING_AND_SAVE (disp_end
+ 1);
5815 if (i
.types
[this_operand
].bitfield
.baseIndex
5816 && displacement_string_end
[-1] == '+')
5818 /* This hack is to avoid a warning when using the "o"
5819 constraint within gcc asm statements.
5822 #define _set_tssldt_desc(n,addr,limit,type) \
5823 __asm__ __volatile__ ( \
5825 "movw %w1,2+%0\n\t" \
5827 "movb %b1,4+%0\n\t" \
5828 "movb %4,5+%0\n\t" \
5829 "movb $0,6+%0\n\t" \
5830 "movb %h1,7+%0\n\t" \
5832 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5834 This works great except that the output assembler ends
5835 up looking a bit weird if it turns out that there is
5836 no offset. You end up producing code that looks like:
5849 So here we provide the missing zero. */
5851 *displacement_string_end
= '0';
5854 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5855 if (gotfree_input_line
)
5856 input_line_pointer
= gotfree_input_line
;
5858 exp_seg
= expression (exp
);
5861 if (*input_line_pointer
)
5862 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5864 RESTORE_END_STRING (disp_end
+ 1);
5866 input_line_pointer
= save_input_line_pointer
;
5867 if (gotfree_input_line
)
5868 free (gotfree_input_line
);
5871 /* We do this to make sure that the section symbol is in
5872 the symbol table. We will ultimately change the relocation
5873 to be relative to the beginning of the section. */
5874 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5875 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5876 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5878 if (exp
->X_op
!= O_symbol
)
5881 if (S_IS_LOCAL (exp
->X_add_symbol
)
5882 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5883 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5884 exp
->X_op
= O_subtract
;
5885 exp
->X_op_symbol
= GOT_symbol
;
5886 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
5887 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
5888 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5889 i
.reloc
[this_operand
] = BFD_RELOC_64
;
5891 i
.reloc
[this_operand
] = BFD_RELOC_32
;
5894 else if (exp
->X_op
== O_absent
5895 || exp
->X_op
== O_illegal
5896 || exp
->X_op
== O_big
5897 || (gotfree_input_line
5898 && (exp
->X_op
== O_constant
5899 || exp
->X_op
== O_register
)))
5902 as_bad (_("missing or invalid displacement expression `%s'"),
5907 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5908 else if (exp
->X_op
!= O_constant
5909 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
5910 && exp_seg
!= absolute_section
5911 && exp_seg
!= text_section
5912 && exp_seg
!= data_section
5913 && exp_seg
!= bss_section
5914 && exp_seg
!= undefined_section
5915 && !bfd_is_com_section (exp_seg
))
5917 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5922 RESTORE_END_STRING (disp_end
);
5924 /* Check if this is a displacement only operand. */
5925 bigdisp
= i
.types
[this_operand
];
5926 bigdisp
.bitfield
.disp8
= 0;
5927 bigdisp
.bitfield
.disp16
= 0;
5928 bigdisp
.bitfield
.disp32
= 0;
5929 bigdisp
.bitfield
.disp32s
= 0;
5930 bigdisp
.bitfield
.disp64
= 0;
5931 if (UINTS_ALL_ZERO (bigdisp
))
5932 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5938 /* Make sure the memory operand we've been dealt is valid.
5939 Return 1 on success, 0 on a failure. */
5942 i386_index_check (const char *operand_string
)
5945 #if INFER_ADDR_PREFIX
5951 if (flag_code
== CODE_64BIT
)
5954 && ((i
.prefix
[ADDR_PREFIX
] == 0
5955 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
5956 || (i
.prefix
[ADDR_PREFIX
]
5957 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
5959 || i
.base_reg
->reg_num
!=
5960 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
5962 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
5963 || (i
.prefix
[ADDR_PREFIX
] == 0
5964 && i
.index_reg
->reg_num
!= RegRiz
5965 && !i
.index_reg
->reg_type
.bitfield
.reg64
5967 || (i
.prefix
[ADDR_PREFIX
]
5968 && i
.index_reg
->reg_num
!= RegEiz
5969 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
5974 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5978 && (!i
.base_reg
->reg_type
.bitfield
.reg16
5979 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
5981 && (!i
.index_reg
->reg_type
.bitfield
.reg16
5982 || !i
.index_reg
->reg_type
.bitfield
.baseindex
5984 && i
.base_reg
->reg_num
< 6
5985 && i
.index_reg
->reg_num
>= 6
5986 && i
.log2_scale_factor
== 0))))
5993 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
5995 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
5996 && i
.index_reg
->reg_num
!= RegEiz
)
5997 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6003 #if INFER_ADDR_PREFIX
6004 if (i
.prefix
[ADDR_PREFIX
] == 0)
6006 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6008 /* Change the size of any displacement too. At most one of
6009 Disp16 or Disp32 is set.
6010 FIXME. There doesn't seem to be any real need for separate
6011 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6012 Removing them would probably clean up the code quite a lot. */
6013 if (flag_code
!= CODE_64BIT
6014 && (i
.types
[this_operand
].bitfield
.disp16
6015 || i
.types
[this_operand
].bitfield
.disp32
))
6016 i
.types
[this_operand
]
6017 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6022 as_bad (_("`%s' is not a valid base/index expression"),
6026 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6028 flag_code_names
[flag_code
]);
6033 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6037 i386_operand (char *operand_string
)
6041 char *op_string
= operand_string
;
6043 if (is_space_char (*op_string
))
6046 /* We check for an absolute prefix (differentiating,
6047 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6048 if (*op_string
== ABSOLUTE_PREFIX
)
6051 if (is_space_char (*op_string
))
6053 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6056 /* Check if operand is a register. */
6057 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6059 i386_operand_type temp
;
6061 /* Check for a segment override by searching for ':' after a
6062 segment register. */
6064 if (is_space_char (*op_string
))
6066 if (*op_string
== ':'
6067 && (r
->reg_type
.bitfield
.sreg2
6068 || r
->reg_type
.bitfield
.sreg3
))
6073 i
.seg
[i
.mem_operands
] = &es
;
6076 i
.seg
[i
.mem_operands
] = &cs
;
6079 i
.seg
[i
.mem_operands
] = &ss
;
6082 i
.seg
[i
.mem_operands
] = &ds
;
6085 i
.seg
[i
.mem_operands
] = &fs
;
6088 i
.seg
[i
.mem_operands
] = &gs
;
6092 /* Skip the ':' and whitespace. */
6094 if (is_space_char (*op_string
))
6097 if (!is_digit_char (*op_string
)
6098 && !is_identifier_char (*op_string
)
6099 && *op_string
!= '('
6100 && *op_string
!= ABSOLUTE_PREFIX
)
6102 as_bad (_("bad memory operand `%s'"), op_string
);
6105 /* Handle case of %es:*foo. */
6106 if (*op_string
== ABSOLUTE_PREFIX
)
6109 if (is_space_char (*op_string
))
6111 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6113 goto do_memory_reference
;
6117 as_bad (_("junk `%s' after register"), op_string
);
6121 temp
.bitfield
.baseindex
= 0;
6122 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6124 i
.op
[this_operand
].regs
= r
;
6127 else if (*op_string
== REGISTER_PREFIX
)
6129 as_bad (_("bad register name `%s'"), op_string
);
6132 else if (*op_string
== IMMEDIATE_PREFIX
)
6135 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6137 as_bad (_("immediate operand illegal with absolute jump"));
6140 if (!i386_immediate (op_string
))
6143 else if (is_digit_char (*op_string
)
6144 || is_identifier_char (*op_string
)
6145 || *op_string
== '(')
6147 /* This is a memory reference of some sort. */
6150 /* Start and end of displacement string expression (if found). */
6151 char *displacement_string_start
;
6152 char *displacement_string_end
;
6154 do_memory_reference
:
6155 if ((i
.mem_operands
== 1
6156 && !current_templates
->start
->opcode_modifier
.isstring
)
6157 || i
.mem_operands
== 2)
6159 as_bad (_("too many memory references for `%s'"),
6160 current_templates
->start
->name
);
6164 /* Check for base index form. We detect the base index form by
6165 looking for an ')' at the end of the operand, searching
6166 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6168 base_string
= op_string
+ strlen (op_string
);
6171 if (is_space_char (*base_string
))
6174 /* If we only have a displacement, set-up for it to be parsed later. */
6175 displacement_string_start
= op_string
;
6176 displacement_string_end
= base_string
+ 1;
6178 if (*base_string
== ')')
6181 unsigned int parens_balanced
= 1;
6182 /* We've already checked that the number of left & right ()'s are
6183 equal, so this loop will not be infinite. */
6187 if (*base_string
== ')')
6189 if (*base_string
== '(')
6192 while (parens_balanced
);
6194 temp_string
= base_string
;
6196 /* Skip past '(' and whitespace. */
6198 if (is_space_char (*base_string
))
6201 if (*base_string
== ','
6202 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6205 displacement_string_end
= temp_string
;
6207 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6211 base_string
= end_op
;
6212 if (is_space_char (*base_string
))
6216 /* There may be an index reg or scale factor here. */
6217 if (*base_string
== ',')
6220 if (is_space_char (*base_string
))
6223 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6226 base_string
= end_op
;
6227 if (is_space_char (*base_string
))
6229 if (*base_string
== ',')
6232 if (is_space_char (*base_string
))
6235 else if (*base_string
!= ')')
6237 as_bad (_("expecting `,' or `)' "
6238 "after index register in `%s'"),
6243 else if (*base_string
== REGISTER_PREFIX
)
6245 as_bad (_("bad register name `%s'"), base_string
);
6249 /* Check for scale factor. */
6250 if (*base_string
!= ')')
6252 char *end_scale
= i386_scale (base_string
);
6257 base_string
= end_scale
;
6258 if (is_space_char (*base_string
))
6260 if (*base_string
!= ')')
6262 as_bad (_("expecting `)' "
6263 "after scale factor in `%s'"),
6268 else if (!i
.index_reg
)
6270 as_bad (_("expecting index register or scale factor "
6271 "after `,'; got '%c'"),
6276 else if (*base_string
!= ')')
6278 as_bad (_("expecting `,' or `)' "
6279 "after base register in `%s'"),
6284 else if (*base_string
== REGISTER_PREFIX
)
6286 as_bad (_("bad register name `%s'"), base_string
);
6291 /* If there's an expression beginning the operand, parse it,
6292 assuming displacement_string_start and
6293 displacement_string_end are meaningful. */
6294 if (displacement_string_start
!= displacement_string_end
)
6296 if (!i386_displacement (displacement_string_start
,
6297 displacement_string_end
))
6301 /* Special case for (%dx) while doing input/output op. */
6303 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
6305 && i
.log2_scale_factor
== 0
6306 && i
.seg
[i
.mem_operands
] == 0
6307 && !operand_type_check (i
.types
[this_operand
], disp
))
6309 UINTS_CLEAR (i
.types
[this_operand
]);
6310 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
6314 if (i386_index_check (operand_string
) == 0)
6320 /* It's not a memory operand; argh! */
6321 as_bad (_("invalid char %s beginning operand %d `%s'"),
6322 output_invalid (*op_string
),
6327 return 1; /* Normal return. */
6330 /* md_estimate_size_before_relax()
6332 Called just before relax() for rs_machine_dependent frags. The x86
6333 assembler uses these frags to handle variable size jump
6336 Any symbol that is now undefined will not become defined.
6337 Return the correct fr_subtype in the frag.
6338 Return the initial "guess for variable size of frag" to caller.
6339 The guess is actually the growth beyond the fixed part. Whatever
6340 we do to grow the fixed or variable part contributes to our
6344 md_estimate_size_before_relax (fragP
, segment
)
6348 /* We've already got fragP->fr_subtype right; all we have to do is
6349 check for un-relaxable symbols. On an ELF system, we can't relax
6350 an externally visible symbol, because it may be overridden by a
6352 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6355 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6356 || S_IS_WEAK (fragP
->fr_symbol
)))
6360 /* Symbol is undefined in this segment, or we need to keep a
6361 reloc so that weak symbols can be overridden. */
6362 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6363 enum bfd_reloc_code_real reloc_type
;
6364 unsigned char *opcode
;
6367 if (fragP
->fr_var
!= NO_RELOC
)
6368 reloc_type
= fragP
->fr_var
;
6370 reloc_type
= BFD_RELOC_16_PCREL
;
6372 reloc_type
= BFD_RELOC_32_PCREL
;
6374 old_fr_fix
= fragP
->fr_fix
;
6375 opcode
= (unsigned char *) fragP
->fr_opcode
;
6377 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6380 /* Make jmp (0xeb) a (d)word displacement jump. */
6382 fragP
->fr_fix
+= size
;
6383 fix_new (fragP
, old_fr_fix
, size
,
6385 fragP
->fr_offset
, 1,
6391 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6393 /* Negate the condition, and branch past an
6394 unconditional jump. */
6397 /* Insert an unconditional jump. */
6399 /* We added two extra opcode bytes, and have a two byte
6401 fragP
->fr_fix
+= 2 + 2;
6402 fix_new (fragP
, old_fr_fix
+ 2, 2,
6404 fragP
->fr_offset
, 1,
6411 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6416 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6418 fragP
->fr_offset
, 1,
6420 fixP
->fx_signed
= 1;
6424 /* This changes the byte-displacement jump 0x7N
6425 to the (d)word-displacement jump 0x0f,0x8N. */
6426 opcode
[1] = opcode
[0] + 0x10;
6427 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6428 /* We've added an opcode byte. */
6429 fragP
->fr_fix
+= 1 + size
;
6430 fix_new (fragP
, old_fr_fix
+ 1, size
,
6432 fragP
->fr_offset
, 1,
6437 BAD_CASE (fragP
->fr_subtype
);
6441 return fragP
->fr_fix
- old_fr_fix
;
6444 /* Guess size depending on current relax state. Initially the relax
6445 state will correspond to a short jump and we return 1, because
6446 the variable part of the frag (the branch offset) is one byte
6447 long. However, we can relax a section more than once and in that
6448 case we must either set fr_subtype back to the unrelaxed state,
6449 or return the value for the appropriate branch. */
6450 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6453 /* Called after relax() is finished.
6455 In: Address of frag.
6456 fr_type == rs_machine_dependent.
6457 fr_subtype is what the address relaxed to.
6459 Out: Any fixSs and constants are set up.
6460 Caller will turn frag into a ".space 0". */
6463 md_convert_frag (abfd
, sec
, fragP
)
6464 bfd
*abfd ATTRIBUTE_UNUSED
;
6465 segT sec ATTRIBUTE_UNUSED
;
6468 unsigned char *opcode
;
6469 unsigned char *where_to_put_displacement
= NULL
;
6470 offsetT target_address
;
6471 offsetT opcode_address
;
6472 unsigned int extension
= 0;
6473 offsetT displacement_from_opcode_start
;
6475 opcode
= (unsigned char *) fragP
->fr_opcode
;
6477 /* Address we want to reach in file space. */
6478 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6480 /* Address opcode resides at in file space. */
6481 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6483 /* Displacement from opcode start to fill into instruction. */
6484 displacement_from_opcode_start
= target_address
- opcode_address
;
6486 if ((fragP
->fr_subtype
& BIG
) == 0)
6488 /* Don't have to change opcode. */
6489 extension
= 1; /* 1 opcode + 1 displacement */
6490 where_to_put_displacement
= &opcode
[1];
6494 if (no_cond_jump_promotion
6495 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6496 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6497 _("long jump required"));
6499 switch (fragP
->fr_subtype
)
6501 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6502 extension
= 4; /* 1 opcode + 4 displacement */
6504 where_to_put_displacement
= &opcode
[1];
6507 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6508 extension
= 2; /* 1 opcode + 2 displacement */
6510 where_to_put_displacement
= &opcode
[1];
6513 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6514 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6515 extension
= 5; /* 2 opcode + 4 displacement */
6516 opcode
[1] = opcode
[0] + 0x10;
6517 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6518 where_to_put_displacement
= &opcode
[2];
6521 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6522 extension
= 3; /* 2 opcode + 2 displacement */
6523 opcode
[1] = opcode
[0] + 0x10;
6524 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6525 where_to_put_displacement
= &opcode
[2];
6528 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6533 where_to_put_displacement
= &opcode
[3];
6537 BAD_CASE (fragP
->fr_subtype
);
6542 /* If size if less then four we are sure that the operand fits,
6543 but if it's 4, then it could be that the displacement is larger
6545 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6547 && ((addressT
) (displacement_from_opcode_start
- extension
6548 + ((addressT
) 1 << 31))
6549 > (((addressT
) 2 << 31) - 1)))
6551 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6552 _("jump target out of range"));
6553 /* Make us emit 0. */
6554 displacement_from_opcode_start
= extension
;
6556 /* Now put displacement after opcode. */
6557 md_number_to_chars ((char *) where_to_put_displacement
,
6558 (valueT
) (displacement_from_opcode_start
- extension
),
6559 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6560 fragP
->fr_fix
+= extension
;
6563 /* Apply a fixup (fixS) to segment data, once it has been determined
6564 by our caller that we have all the info we need to fix it up.
6566 On the 386, immediates, displacements, and data pointers are all in
6567 the same (little-endian) format, so we don't need to care about which
6571 md_apply_fix (fixP
, valP
, seg
)
6572 /* The fix we're to put in. */
6574 /* Pointer to the value of the bits. */
6576 /* Segment fix is from. */
6577 segT seg ATTRIBUTE_UNUSED
;
6579 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6580 valueT value
= *valP
;
6582 #if !defined (TE_Mach)
6585 switch (fixP
->fx_r_type
)
6591 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6594 case BFD_RELOC_X86_64_32S
:
6595 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6598 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6601 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6606 if (fixP
->fx_addsy
!= NULL
6607 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6608 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6609 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6610 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6611 && !use_rela_relocations
)
6613 /* This is a hack. There should be a better way to handle this.
6614 This covers for the fact that bfd_install_relocation will
6615 subtract the current location (for partial_inplace, PC relative
6616 relocations); see more below. */
6620 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6623 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6628 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6631 || (symbol_section_p (fixP
->fx_addsy
)
6632 && sym_seg
!= absolute_section
))
6633 && !generic_force_reloc (fixP
))
6635 /* Yes, we add the values in twice. This is because
6636 bfd_install_relocation subtracts them out again. I think
6637 bfd_install_relocation is broken, but I don't dare change
6639 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6643 #if defined (OBJ_COFF) && defined (TE_PE)
6644 /* For some reason, the PE format does not store a
6645 section address offset for a PC relative symbol. */
6646 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6647 || S_IS_WEAK (fixP
->fx_addsy
))
6648 value
+= md_pcrel_from (fixP
);
6652 /* Fix a few things - the dynamic linker expects certain values here,
6653 and we must not disappoint it. */
6654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6655 if (IS_ELF
&& fixP
->fx_addsy
)
6656 switch (fixP
->fx_r_type
)
6658 case BFD_RELOC_386_PLT32
:
6659 case BFD_RELOC_X86_64_PLT32
:
6660 /* Make the jump instruction point to the address of the operand. At
6661 runtime we merely add the offset to the actual PLT entry. */
6665 case BFD_RELOC_386_TLS_GD
:
6666 case BFD_RELOC_386_TLS_LDM
:
6667 case BFD_RELOC_386_TLS_IE_32
:
6668 case BFD_RELOC_386_TLS_IE
:
6669 case BFD_RELOC_386_TLS_GOTIE
:
6670 case BFD_RELOC_386_TLS_GOTDESC
:
6671 case BFD_RELOC_X86_64_TLSGD
:
6672 case BFD_RELOC_X86_64_TLSLD
:
6673 case BFD_RELOC_X86_64_GOTTPOFF
:
6674 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6675 value
= 0; /* Fully resolved at runtime. No addend. */
6677 case BFD_RELOC_386_TLS_LE
:
6678 case BFD_RELOC_386_TLS_LDO_32
:
6679 case BFD_RELOC_386_TLS_LE_32
:
6680 case BFD_RELOC_X86_64_DTPOFF32
:
6681 case BFD_RELOC_X86_64_DTPOFF64
:
6682 case BFD_RELOC_X86_64_TPOFF32
:
6683 case BFD_RELOC_X86_64_TPOFF64
:
6684 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6687 case BFD_RELOC_386_TLS_DESC_CALL
:
6688 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6689 value
= 0; /* Fully resolved at runtime. No addend. */
6690 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6694 case BFD_RELOC_386_GOT32
:
6695 case BFD_RELOC_X86_64_GOT32
:
6696 value
= 0; /* Fully resolved at runtime. No addend. */
6699 case BFD_RELOC_VTABLE_INHERIT
:
6700 case BFD_RELOC_VTABLE_ENTRY
:
6707 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6709 #endif /* !defined (TE_Mach) */
6711 /* Are we finished with this relocation now? */
6712 if (fixP
->fx_addsy
== NULL
)
6714 else if (use_rela_relocations
)
6716 fixP
->fx_no_overflow
= 1;
6717 /* Remember value for tc_gen_reloc. */
6718 fixP
->fx_addnumber
= value
;
6722 md_number_to_chars (p
, value
, fixP
->fx_size
);
6726 md_atof (int type
, char *litP
, int *sizeP
)
6728 /* This outputs the LITTLENUMs in REVERSE order;
6729 in accord with the bigendian 386. */
6730 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
6733 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6736 output_invalid (int c
)
6739 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6742 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6743 "(0x%x)", (unsigned char) c
);
6744 return output_invalid_buf
;
6747 /* REG_STRING starts *before* REGISTER_PREFIX. */
6749 static const reg_entry
*
6750 parse_real_register (char *reg_string
, char **end_op
)
6752 char *s
= reg_string
;
6754 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6757 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6758 if (*s
== REGISTER_PREFIX
)
6761 if (is_space_char (*s
))
6765 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6767 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6768 return (const reg_entry
*) NULL
;
6772 /* For naked regs, make sure that we are not dealing with an identifier.
6773 This prevents confusing an identifier like `eax_var' with register
6775 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6776 return (const reg_entry
*) NULL
;
6780 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6782 /* Handle floating point regs, allowing spaces in the (i) part. */
6783 if (r
== i386_regtab
/* %st is first entry of table */)
6785 if (is_space_char (*s
))
6790 if (is_space_char (*s
))
6792 if (*s
>= '0' && *s
<= '7')
6796 if (is_space_char (*s
))
6801 r
= hash_find (reg_hash
, "st(0)");
6806 /* We have "%st(" then garbage. */
6807 return (const reg_entry
*) NULL
;
6811 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6814 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
6815 return (const reg_entry
*) NULL
;
6818 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6819 || r
->reg_type
.bitfield
.reg64
)
6820 && (!cpu_arch_flags
.bitfield
.cpulm
6821 || !UINTS_EQUAL (r
->reg_type
, control
))
6822 && flag_code
!= CODE_64BIT
)
6823 return (const reg_entry
*) NULL
;
6828 /* REG_STRING starts *before* REGISTER_PREFIX. */
6830 static const reg_entry
*
6831 parse_register (char *reg_string
, char **end_op
)
6835 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6836 r
= parse_real_register (reg_string
, end_op
);
6841 char *save
= input_line_pointer
;
6845 input_line_pointer
= reg_string
;
6846 c
= get_symbol_end ();
6847 symbolP
= symbol_find (reg_string
);
6848 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6850 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6852 know (e
->X_op
== O_register
);
6853 know (e
->X_add_number
>= 0
6854 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6855 r
= i386_regtab
+ e
->X_add_number
;
6856 *end_op
= input_line_pointer
;
6858 *input_line_pointer
= c
;
6859 input_line_pointer
= save
;
6865 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6868 char *end
= input_line_pointer
;
6871 r
= parse_register (name
, &input_line_pointer
);
6872 if (r
&& end
<= input_line_pointer
)
6874 *nextcharP
= *input_line_pointer
;
6875 *input_line_pointer
= 0;
6876 e
->X_op
= O_register
;
6877 e
->X_add_number
= r
- i386_regtab
;
6880 input_line_pointer
= end
;
6886 md_operand (expressionS
*e
)
6888 if (*input_line_pointer
== REGISTER_PREFIX
)
6891 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
6895 e
->X_op
= O_register
;
6896 e
->X_add_number
= r
- i386_regtab
;
6897 input_line_pointer
= end
;
6903 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6904 const char *md_shortopts
= "kVQ:sqn";
6906 const char *md_shortopts
= "qn";
6909 #define OPTION_32 (OPTION_MD_BASE + 0)
6910 #define OPTION_64 (OPTION_MD_BASE + 1)
6911 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6912 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6913 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6915 struct option md_longopts
[] =
6917 {"32", no_argument
, NULL
, OPTION_32
},
6918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6919 {"64", no_argument
, NULL
, OPTION_64
},
6921 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
6922 {"march", required_argument
, NULL
, OPTION_MARCH
},
6923 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
6924 {NULL
, no_argument
, NULL
, 0}
6926 size_t md_longopts_size
= sizeof (md_longopts
);
6929 md_parse_option (int c
, char *arg
)
6936 optimize_align_code
= 0;
6943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6944 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6945 should be emitted or not. FIXME: Not implemented. */
6949 /* -V: SVR4 argument to print version ID. */
6951 print_version_id ();
6954 /* -k: Ignore for FreeBSD compatibility. */
6959 /* -s: On i386 Solaris, this tells the native assembler to use
6960 .stab instead of .stab.excl. We always use .stab anyhow. */
6963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6966 const char **list
, **l
;
6968 list
= bfd_target_list ();
6969 for (l
= list
; *l
!= NULL
; l
++)
6970 if (CONST_STRNEQ (*l
, "elf64-x86-64")
6971 || strcmp (*l
, "coff-x86-64") == 0
6972 || strcmp (*l
, "pe-x86-64") == 0
6973 || strcmp (*l
, "pei-x86-64") == 0)
6975 default_arch
= "x86_64";
6979 as_fatal (_("No compiled in support for x86_64"));
6986 default_arch
= "i386";
6990 #ifdef SVR4_COMMENT_CHARS
6995 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6997 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7001 i386_comment_chars
= n
;
7008 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7009 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7011 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7013 cpu_arch_isa
= cpu_arch
[i
].type
;
7014 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7015 if (!cpu_arch_tune_set
)
7017 cpu_arch_tune
= cpu_arch_isa
;
7018 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7023 if (i
>= ARRAY_SIZE (cpu_arch
))
7024 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7029 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7030 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7032 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7034 cpu_arch_tune_set
= 1;
7035 cpu_arch_tune
= cpu_arch
[i
].type
;
7036 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7040 if (i
>= ARRAY_SIZE (cpu_arch
))
7041 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7051 md_show_usage (stream
)
7054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7055 fprintf (stream
, _("\
7057 -V print assembler version number\n\
7060 fprintf (stream
, _("\
7061 -n Do not optimize code alignment\n\
7062 -q quieten some warnings\n"));
7063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7064 fprintf (stream
, _("\
7067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7068 fprintf (stream
, _("\
7069 --32/--64 generate 32bit/64bit code\n"));
7071 #ifdef SVR4_COMMENT_CHARS
7072 fprintf (stream
, _("\
7073 --divide do not treat `/' as a comment character\n"));
7075 fprintf (stream
, _("\
7076 --divide ignored\n"));
7078 fprintf (stream
, _("\
7079 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7080 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7081 core, core2, k6, athlon, k8, generic32, generic64\n"));
7085 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7086 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7088 /* Pick the target format to use. */
7091 i386_target_format (void)
7093 if (!strcmp (default_arch
, "x86_64"))
7095 set_code_flag (CODE_64BIT
);
7096 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7098 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7099 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7100 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7101 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7102 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7103 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7104 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
7105 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7106 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
7107 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7108 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7110 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7112 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7113 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7114 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7115 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7116 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7117 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7118 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
7119 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7120 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
7121 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7122 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7125 else if (!strcmp (default_arch
, "i386"))
7127 set_code_flag (CODE_32BIT
);
7128 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7130 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7131 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7132 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7134 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7136 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7137 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7138 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7142 as_fatal (_("Unknown architecture"));
7143 switch (OUTPUT_FLAVOR
)
7146 case bfd_target_coff_flavour
:
7147 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
7150 #ifdef OBJ_MAYBE_AOUT
7151 case bfd_target_aout_flavour
:
7152 return AOUT_TARGET_FORMAT
;
7154 #ifdef OBJ_MAYBE_COFF
7155 case bfd_target_coff_flavour
:
7158 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7159 case bfd_target_elf_flavour
:
7161 if (flag_code
== CODE_64BIT
)
7164 use_rela_relocations
= 1;
7166 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7175 #endif /* OBJ_MAYBE_ more than one */
7177 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7179 i386_elf_emit_arch_note (void)
7181 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7184 asection
*seg
= now_seg
;
7185 subsegT subseg
= now_subseg
;
7186 Elf_Internal_Note i_note
;
7187 Elf_External_Note e_note
;
7188 asection
*note_secp
;
7191 /* Create the .note section. */
7192 note_secp
= subseg_new (".note", 0);
7193 bfd_set_section_flags (stdoutput
,
7195 SEC_HAS_CONTENTS
| SEC_READONLY
);
7197 /* Process the arch string. */
7198 len
= strlen (cpu_arch_name
);
7200 i_note
.namesz
= len
+ 1;
7202 i_note
.type
= NT_ARCH
;
7203 p
= frag_more (sizeof (e_note
.namesz
));
7204 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
7205 p
= frag_more (sizeof (e_note
.descsz
));
7206 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
7207 p
= frag_more (sizeof (e_note
.type
));
7208 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
7209 p
= frag_more (len
+ 1);
7210 strcpy (p
, cpu_arch_name
);
7212 frag_align (2, 0, 0);
7214 subseg_set (seg
, subseg
);
7220 md_undefined_symbol (name
)
7223 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
7224 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
7225 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
7226 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
7230 if (symbol_find (name
))
7231 as_bad (_("GOT already in symbol table"));
7232 GOT_symbol
= symbol_new (name
, undefined_section
,
7233 (valueT
) 0, &zero_address_frag
);
7240 /* Round up a section size to the appropriate boundary. */
7243 md_section_align (segment
, size
)
7244 segT segment ATTRIBUTE_UNUSED
;
7247 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7248 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
7250 /* For a.out, force the section size to be aligned. If we don't do
7251 this, BFD will align it for us, but it will not write out the
7252 final bytes of the section. This may be a bug in BFD, but it is
7253 easier to fix it here since that is how the other a.out targets
7257 align
= bfd_get_section_alignment (stdoutput
, segment
);
7258 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7265 /* On the i386, PC-relative offsets are relative to the start of the
7266 next instruction. That is, the address of the offset, plus its
7267 size, since the offset is always the last part of the insn. */
7270 md_pcrel_from (fixS
*fixP
)
7272 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7278 s_bss (int ignore ATTRIBUTE_UNUSED
)
7282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7284 obj_elf_section_change_hook ();
7286 temp
= get_absolute_expression ();
7287 subseg_set (bss_section
, (subsegT
) temp
);
7288 demand_empty_rest_of_line ();
7294 i386_validate_fix (fixS
*fixp
)
7296 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
7298 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
7302 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
7307 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
7309 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
7316 tc_gen_reloc (section
, fixp
)
7317 asection
*section ATTRIBUTE_UNUSED
;
7321 bfd_reloc_code_real_type code
;
7323 switch (fixp
->fx_r_type
)
7325 case BFD_RELOC_X86_64_PLT32
:
7326 case BFD_RELOC_X86_64_GOT32
:
7327 case BFD_RELOC_X86_64_GOTPCREL
:
7328 case BFD_RELOC_386_PLT32
:
7329 case BFD_RELOC_386_GOT32
:
7330 case BFD_RELOC_386_GOTOFF
:
7331 case BFD_RELOC_386_GOTPC
:
7332 case BFD_RELOC_386_TLS_GD
:
7333 case BFD_RELOC_386_TLS_LDM
:
7334 case BFD_RELOC_386_TLS_LDO_32
:
7335 case BFD_RELOC_386_TLS_IE_32
:
7336 case BFD_RELOC_386_TLS_IE
:
7337 case BFD_RELOC_386_TLS_GOTIE
:
7338 case BFD_RELOC_386_TLS_LE_32
:
7339 case BFD_RELOC_386_TLS_LE
:
7340 case BFD_RELOC_386_TLS_GOTDESC
:
7341 case BFD_RELOC_386_TLS_DESC_CALL
:
7342 case BFD_RELOC_X86_64_TLSGD
:
7343 case BFD_RELOC_X86_64_TLSLD
:
7344 case BFD_RELOC_X86_64_DTPOFF32
:
7345 case BFD_RELOC_X86_64_DTPOFF64
:
7346 case BFD_RELOC_X86_64_GOTTPOFF
:
7347 case BFD_RELOC_X86_64_TPOFF32
:
7348 case BFD_RELOC_X86_64_TPOFF64
:
7349 case BFD_RELOC_X86_64_GOTOFF64
:
7350 case BFD_RELOC_X86_64_GOTPC32
:
7351 case BFD_RELOC_X86_64_GOT64
:
7352 case BFD_RELOC_X86_64_GOTPCREL64
:
7353 case BFD_RELOC_X86_64_GOTPC64
:
7354 case BFD_RELOC_X86_64_GOTPLT64
:
7355 case BFD_RELOC_X86_64_PLTOFF64
:
7356 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7357 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7359 case BFD_RELOC_VTABLE_ENTRY
:
7360 case BFD_RELOC_VTABLE_INHERIT
:
7362 case BFD_RELOC_32_SECREL
:
7364 code
= fixp
->fx_r_type
;
7366 case BFD_RELOC_X86_64_32S
:
7367 if (!fixp
->fx_pcrel
)
7369 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7370 code
= fixp
->fx_r_type
;
7376 switch (fixp
->fx_size
)
7379 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7380 _("can not do %d byte pc-relative relocation"),
7382 code
= BFD_RELOC_32_PCREL
;
7384 case 1: code
= BFD_RELOC_8_PCREL
; break;
7385 case 2: code
= BFD_RELOC_16_PCREL
; break;
7386 case 4: code
= BFD_RELOC_32_PCREL
; break;
7388 case 8: code
= BFD_RELOC_64_PCREL
; break;
7394 switch (fixp
->fx_size
)
7397 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7398 _("can not do %d byte relocation"),
7400 code
= BFD_RELOC_32
;
7402 case 1: code
= BFD_RELOC_8
; break;
7403 case 2: code
= BFD_RELOC_16
; break;
7404 case 4: code
= BFD_RELOC_32
; break;
7406 case 8: code
= BFD_RELOC_64
; break;
7413 if ((code
== BFD_RELOC_32
7414 || code
== BFD_RELOC_32_PCREL
7415 || code
== BFD_RELOC_X86_64_32S
)
7417 && fixp
->fx_addsy
== GOT_symbol
)
7420 code
= BFD_RELOC_386_GOTPC
;
7422 code
= BFD_RELOC_X86_64_GOTPC32
;
7424 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7426 && fixp
->fx_addsy
== GOT_symbol
)
7428 code
= BFD_RELOC_X86_64_GOTPC64
;
7431 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7432 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7433 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7435 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7437 if (!use_rela_relocations
)
7439 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7440 vtable entry to be used in the relocation's section offset. */
7441 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7442 rel
->address
= fixp
->fx_offset
;
7446 /* Use the rela in 64bit mode. */
7449 if (!fixp
->fx_pcrel
)
7450 rel
->addend
= fixp
->fx_offset
;
7454 case BFD_RELOC_X86_64_PLT32
:
7455 case BFD_RELOC_X86_64_GOT32
:
7456 case BFD_RELOC_X86_64_GOTPCREL
:
7457 case BFD_RELOC_X86_64_TLSGD
:
7458 case BFD_RELOC_X86_64_TLSLD
:
7459 case BFD_RELOC_X86_64_GOTTPOFF
:
7460 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7461 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7462 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7465 rel
->addend
= (section
->vma
7467 + fixp
->fx_addnumber
7468 + md_pcrel_from (fixp
));
7473 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7474 if (rel
->howto
== NULL
)
7476 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7477 _("cannot represent relocation type %s"),
7478 bfd_get_reloc_code_name (code
));
7479 /* Set howto to a garbage value so that we can keep going. */
7480 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7481 assert (rel
->howto
!= NULL
);
7488 /* Parse operands using Intel syntax. This implements a recursive descent
7489 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7492 FIXME: We do not recognize the full operand grammar defined in the MASM
7493 documentation. In particular, all the structure/union and
7494 high-level macro operands are missing.
7496 Uppercase words are terminals, lower case words are non-terminals.
7497 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7498 bars '|' denote choices. Most grammar productions are implemented in
7499 functions called 'intel_<production>'.
7501 Initial production is 'expr'.
7507 binOp & | AND | \| | OR | ^ | XOR
7509 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7511 constant digits [[ radixOverride ]]
7513 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7551 => expr expr cmpOp e04
7554 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7555 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7557 hexdigit a | b | c | d | e | f
7558 | A | B | C | D | E | F
7564 mulOp * | / | % | MOD | << | SHL | >> | SHR
7568 register specialRegister
7572 segmentRegister CS | DS | ES | FS | GS | SS
7574 specialRegister CR0 | CR2 | CR3 | CR4
7575 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7576 | TR3 | TR4 | TR5 | TR6 | TR7
7578 We simplify the grammar in obvious places (e.g., register parsing is
7579 done by calling parse_register) and eliminate immediate left recursion
7580 to implement a recursive-descent parser.
7584 expr' cmpOp e04 expr'
7635 /* Parsing structure for the intel syntax parser. Used to implement the
7636 semantic actions for the operand grammar. */
7637 struct intel_parser_s
7639 char *op_string
; /* The string being parsed. */
7640 int got_a_float
; /* Whether the operand is a float. */
7641 int op_modifier
; /* Operand modifier. */
7642 int is_mem
; /* 1 if operand is memory reference. */
7643 int in_offset
; /* >=1 if parsing operand of offset. */
7644 int in_bracket
; /* >=1 if parsing operand in brackets. */
7645 const reg_entry
*reg
; /* Last register reference found. */
7646 char *disp
; /* Displacement string being built. */
7647 char *next_operand
; /* Resume point when splitting operands. */
7650 static struct intel_parser_s intel_parser
;
7652 /* Token structure for parsing intel syntax. */
7655 int code
; /* Token code. */
7656 const reg_entry
*reg
; /* Register entry for register tokens. */
7657 char *str
; /* String representation. */
7660 static struct intel_token cur_token
, prev_token
;
7662 /* Token codes for the intel parser. Since T_SHORT is already used
7663 by COFF, undefine it first to prevent a warning. */
7682 /* Prototypes for intel parser functions. */
7683 static int intel_match_token (int);
7684 static void intel_putback_token (void);
7685 static void intel_get_token (void);
7686 static int intel_expr (void);
7687 static int intel_e04 (void);
7688 static int intel_e05 (void);
7689 static int intel_e06 (void);
7690 static int intel_e09 (void);
7691 static int intel_e10 (void);
7692 static int intel_e11 (void);
7695 i386_intel_operand (char *operand_string
, int got_a_float
)
7700 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7701 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7705 /* Initialize token holders. */
7706 cur_token
.code
= prev_token
.code
= T_NIL
;
7707 cur_token
.reg
= prev_token
.reg
= NULL
;
7708 cur_token
.str
= prev_token
.str
= NULL
;
7710 /* Initialize parser structure. */
7711 intel_parser
.got_a_float
= got_a_float
;
7712 intel_parser
.op_modifier
= 0;
7713 intel_parser
.is_mem
= 0;
7714 intel_parser
.in_offset
= 0;
7715 intel_parser
.in_bracket
= 0;
7716 intel_parser
.reg
= NULL
;
7717 intel_parser
.disp
[0] = '\0';
7718 intel_parser
.next_operand
= NULL
;
7720 /* Read the first token and start the parser. */
7722 ret
= intel_expr ();
7727 if (cur_token
.code
!= T_NIL
)
7729 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7730 current_templates
->start
->name
, cur_token
.str
);
7733 /* If we found a memory reference, hand it over to i386_displacement
7734 to fill in the rest of the operand fields. */
7735 else if (intel_parser
.is_mem
)
7737 if ((i
.mem_operands
== 1
7738 && !current_templates
->start
->opcode_modifier
.isstring
)
7739 || i
.mem_operands
== 2)
7741 as_bad (_("too many memory references for '%s'"),
7742 current_templates
->start
->name
);
7747 char *s
= intel_parser
.disp
;
7750 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7751 /* See the comments in intel_bracket_expr. */
7752 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7754 /* Add the displacement expression. */
7756 ret
= i386_displacement (s
, s
+ strlen (s
));
7759 /* Swap base and index in 16-bit memory operands like
7760 [si+bx]. Since i386_index_check is also used in AT&T
7761 mode we have to do that here. */
7764 && i
.base_reg
->reg_type
.bitfield
.reg16
7765 && i
.index_reg
->reg_type
.bitfield
.reg16
7766 && i
.base_reg
->reg_num
>= 6
7767 && i
.index_reg
->reg_num
< 6)
7769 const reg_entry
*base
= i
.index_reg
;
7771 i
.index_reg
= i
.base_reg
;
7774 ret
= i386_index_check (operand_string
);
7779 /* Constant and OFFSET expressions are handled by i386_immediate. */
7780 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7781 || intel_parser
.reg
== NULL
)
7782 ret
= i386_immediate (intel_parser
.disp
);
7784 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7786 if (!ret
|| !intel_parser
.next_operand
)
7788 intel_parser
.op_string
= intel_parser
.next_operand
;
7789 this_operand
= i
.operands
++;
7793 free (intel_parser
.disp
);
7798 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7802 expr' cmpOp e04 expr'
7807 /* XXX Implement the comparison operators. */
7808 return intel_e04 ();
7825 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7826 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7828 if (cur_token
.code
== '+')
7830 else if (cur_token
.code
== '-')
7831 nregs
= NUM_ADDRESS_REGS
;
7835 strcat (intel_parser
.disp
, cur_token
.str
);
7836 intel_match_token (cur_token
.code
);
7847 int nregs
= ~NUM_ADDRESS_REGS
;
7854 if (cur_token
.code
== '&'
7855 || cur_token
.code
== '|'
7856 || cur_token
.code
== '^')
7860 str
[0] = cur_token
.code
;
7862 strcat (intel_parser
.disp
, str
);
7867 intel_match_token (cur_token
.code
);
7872 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7873 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
7884 int nregs
= ~NUM_ADDRESS_REGS
;
7891 if (cur_token
.code
== '*'
7892 || cur_token
.code
== '/'
7893 || cur_token
.code
== '%')
7897 str
[0] = cur_token
.code
;
7899 strcat (intel_parser
.disp
, str
);
7901 else if (cur_token
.code
== T_SHL
)
7902 strcat (intel_parser
.disp
, "<<");
7903 else if (cur_token
.code
== T_SHR
)
7904 strcat (intel_parser
.disp
, ">>");
7908 intel_match_token (cur_token
.code
);
7913 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7914 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
7932 int nregs
= ~NUM_ADDRESS_REGS
;
7937 /* Don't consume constants here. */
7938 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7940 /* Need to look one token ahead - if the next token
7941 is a constant, the current token is its sign. */
7944 intel_match_token (cur_token
.code
);
7945 next_code
= cur_token
.code
;
7946 intel_putback_token ();
7947 if (next_code
== T_CONST
)
7951 /* e09 OFFSET e09 */
7952 if (cur_token
.code
== T_OFFSET
)
7955 ++intel_parser
.in_offset
;
7959 else if (cur_token
.code
== T_SHORT
)
7960 intel_parser
.op_modifier
|= 1 << T_SHORT
;
7963 else if (cur_token
.code
== '+')
7964 strcat (intel_parser
.disp
, "+");
7969 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
7975 str
[0] = cur_token
.code
;
7977 strcat (intel_parser
.disp
, str
);
7984 intel_match_token (cur_token
.code
);
7992 /* e09' PTR e10 e09' */
7993 if (cur_token
.code
== T_PTR
)
7997 if (prev_token
.code
== T_BYTE
)
7998 suffix
= BYTE_MNEM_SUFFIX
;
8000 else if (prev_token
.code
== T_WORD
)
8002 if (current_templates
->start
->name
[0] == 'l'
8003 && current_templates
->start
->name
[2] == 's'
8004 && current_templates
->start
->name
[3] == 0)
8005 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8006 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
8007 suffix
= SHORT_MNEM_SUFFIX
;
8009 suffix
= WORD_MNEM_SUFFIX
;
8012 else if (prev_token
.code
== T_DWORD
)
8014 if (current_templates
->start
->name
[0] == 'l'
8015 && current_templates
->start
->name
[2] == 's'
8016 && current_templates
->start
->name
[3] == 0)
8017 suffix
= WORD_MNEM_SUFFIX
;
8018 else if (flag_code
== CODE_16BIT
8019 && (current_templates
->start
->opcode_modifier
.jump
8020 || current_templates
->start
->opcode_modifier
.jumpdword
))
8021 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8022 else if (intel_parser
.got_a_float
== 1) /* "f..." */
8023 suffix
= SHORT_MNEM_SUFFIX
;
8025 suffix
= LONG_MNEM_SUFFIX
;
8028 else if (prev_token
.code
== T_FWORD
)
8030 if (current_templates
->start
->name
[0] == 'l'
8031 && current_templates
->start
->name
[2] == 's'
8032 && current_templates
->start
->name
[3] == 0)
8033 suffix
= LONG_MNEM_SUFFIX
;
8034 else if (!intel_parser
.got_a_float
)
8036 if (flag_code
== CODE_16BIT
)
8037 add_prefix (DATA_PREFIX_OPCODE
);
8038 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8041 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8044 else if (prev_token
.code
== T_QWORD
)
8046 if (intel_parser
.got_a_float
== 1) /* "f..." */
8047 suffix
= LONG_MNEM_SUFFIX
;
8049 suffix
= QWORD_MNEM_SUFFIX
;
8052 else if (prev_token
.code
== T_TBYTE
)
8054 if (intel_parser
.got_a_float
== 1)
8055 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8057 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8060 else if (prev_token
.code
== T_XMMWORD
)
8062 /* XXX ignored for now, but accepted since gcc uses it */
8068 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
8072 /* Operands for jump/call using 'ptr' notation denote absolute
8074 if (current_templates
->start
->opcode_modifier
.jump
8075 || current_templates
->start
->opcode_modifier
.jumpdword
)
8076 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8078 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
8082 else if (i
.suffix
!= suffix
)
8084 as_bad (_("Conflicting operand modifiers"));
8090 /* e09' : e10 e09' */
8091 else if (cur_token
.code
== ':')
8093 if (prev_token
.code
!= T_REG
)
8095 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8096 segment/group identifier (which we don't have), using comma
8097 as the operand separator there is even less consistent, since
8098 there all branches only have a single operand. */
8099 if (this_operand
!= 0
8100 || intel_parser
.in_offset
8101 || intel_parser
.in_bracket
8102 || (!current_templates
->start
->opcode_modifier
.jump
8103 && !current_templates
->start
->opcode_modifier
.jumpdword
8104 && !current_templates
->start
->opcode_modifier
.jumpintersegment
8105 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
8106 return intel_match_token (T_NIL
);
8107 /* Remember the start of the 2nd operand and terminate 1st
8109 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8110 another expression), but it gets at least the simplest case
8111 (a plain number or symbol on the left side) right. */
8112 intel_parser
.next_operand
= intel_parser
.op_string
;
8113 *--intel_parser
.op_string
= '\0';
8114 return intel_match_token (':');
8122 intel_match_token (cur_token
.code
);
8128 --intel_parser
.in_offset
;
8131 if (NUM_ADDRESS_REGS
> nregs
)
8133 as_bad (_("Invalid operand to `OFFSET'"));
8136 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
8139 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8140 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
8145 intel_bracket_expr (void)
8147 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
8148 const char *start
= intel_parser
.op_string
;
8151 if (i
.op
[this_operand
].regs
)
8152 return intel_match_token (T_NIL
);
8154 intel_match_token ('[');
8156 /* Mark as a memory operand only if it's not already known to be an
8157 offset expression. If it's an offset expression, we need to keep
8159 if (!intel_parser
.in_offset
)
8161 ++intel_parser
.in_bracket
;
8163 /* Operands for jump/call inside brackets denote absolute addresses. */
8164 if (current_templates
->start
->opcode_modifier
.jump
8165 || current_templates
->start
->opcode_modifier
.jumpdword
)
8166 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8168 /* Unfortunately gas always diverged from MASM in a respect that can't
8169 be easily fixed without risking to break code sequences likely to be
8170 encountered (the testsuite even check for this): MASM doesn't consider
8171 an expression inside brackets unconditionally as a memory reference.
8172 When that is e.g. a constant, an offset expression, or the sum of the
8173 two, this is still taken as a constant load. gas, however, always
8174 treated these as memory references. As a compromise, we'll try to make
8175 offset expressions inside brackets work the MASM way (since that's
8176 less likely to be found in real world code), but make constants alone
8177 continue to work the traditional gas way. In either case, issue a
8179 intel_parser
.op_modifier
&= ~was_offset
;
8182 strcat (intel_parser
.disp
, "[");
8184 /* Add a '+' to the displacement string if necessary. */
8185 if (*intel_parser
.disp
!= '\0'
8186 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
8187 strcat (intel_parser
.disp
, "+");
8190 && (len
= intel_parser
.op_string
- start
- 1,
8191 intel_match_token (']')))
8193 /* Preserve brackets when the operand is an offset expression. */
8194 if (intel_parser
.in_offset
)
8195 strcat (intel_parser
.disp
, "]");
8198 --intel_parser
.in_bracket
;
8199 if (i
.base_reg
|| i
.index_reg
)
8200 intel_parser
.is_mem
= 1;
8201 if (!intel_parser
.is_mem
)
8203 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8204 /* Defer the warning until all of the operand was parsed. */
8205 intel_parser
.is_mem
= -1;
8206 else if (!quiet_warnings
)
8207 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8208 len
, start
, len
, start
);
8211 intel_parser
.op_modifier
|= was_offset
;
8228 while (cur_token
.code
== '[')
8230 if (!intel_bracket_expr ())
8255 switch (cur_token
.code
)
8259 intel_match_token ('(');
8260 strcat (intel_parser
.disp
, "(");
8262 if (intel_expr () && intel_match_token (')'))
8264 strcat (intel_parser
.disp
, ")");
8271 return intel_bracket_expr ();
8276 strcat (intel_parser
.disp
, cur_token
.str
);
8277 intel_match_token (cur_token
.code
);
8279 /* Mark as a memory operand only if it's not already known to be an
8280 offset expression. */
8281 if (!intel_parser
.in_offset
)
8282 intel_parser
.is_mem
= 1;
8289 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
8291 intel_match_token (T_REG
);
8293 /* Check for segment change. */
8294 if (cur_token
.code
== ':')
8296 if (!reg
->reg_type
.bitfield
.sreg2
8297 && !reg
->reg_type
.bitfield
.sreg3
)
8299 as_bad (_("`%s' is not a valid segment register"),
8303 else if (i
.seg
[i
.mem_operands
])
8304 as_warn (_("Extra segment override ignored"));
8307 if (!intel_parser
.in_offset
)
8308 intel_parser
.is_mem
= 1;
8309 switch (reg
->reg_num
)
8312 i
.seg
[i
.mem_operands
] = &es
;
8315 i
.seg
[i
.mem_operands
] = &cs
;
8318 i
.seg
[i
.mem_operands
] = &ss
;
8321 i
.seg
[i
.mem_operands
] = &ds
;
8324 i
.seg
[i
.mem_operands
] = &fs
;
8327 i
.seg
[i
.mem_operands
] = &gs
;
8333 /* Not a segment register. Check for register scaling. */
8334 else if (cur_token
.code
== '*')
8336 if (!intel_parser
.in_bracket
)
8338 as_bad (_("Register scaling only allowed in memory operands"));
8342 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8343 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8344 else if (i
.index_reg
)
8345 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8347 /* What follows must be a valid scale. */
8348 intel_match_token ('*');
8350 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8352 /* Set the scale after setting the register (otherwise,
8353 i386_scale will complain) */
8354 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8356 char *str
, sign
= cur_token
.code
;
8357 intel_match_token (cur_token
.code
);
8358 if (cur_token
.code
!= T_CONST
)
8360 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8364 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8365 strcpy (str
+ 1, cur_token
.str
);
8367 if (!i386_scale (str
))
8371 else if (!i386_scale (cur_token
.str
))
8373 intel_match_token (cur_token
.code
);
8376 /* No scaling. If this is a memory operand, the register is either a
8377 base register (first occurrence) or an index register (second
8379 else if (intel_parser
.in_bracket
)
8384 else if (!i
.index_reg
)
8388 as_bad (_("Too many register references in memory operand"));
8392 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8395 /* It's neither base nor index. */
8396 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8398 i386_operand_type temp
= reg
->reg_type
;
8399 temp
.bitfield
.baseindex
= 0;
8400 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8402 i
.op
[this_operand
].regs
= reg
;
8407 as_bad (_("Invalid use of register"));
8411 /* Since registers are not part of the displacement string (except
8412 when we're parsing offset operands), we may need to remove any
8413 preceding '+' from the displacement string. */
8414 if (*intel_parser
.disp
!= '\0'
8415 && !intel_parser
.in_offset
)
8417 char *s
= intel_parser
.disp
;
8418 s
+= strlen (s
) - 1;
8441 intel_match_token (cur_token
.code
);
8443 if (cur_token
.code
== T_PTR
)
8446 /* It must have been an identifier. */
8447 intel_putback_token ();
8448 cur_token
.code
= T_ID
;
8454 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8458 /* The identifier represents a memory reference only if it's not
8459 preceded by an offset modifier and if it's not an equate. */
8460 symbolP
= symbol_find(cur_token
.str
);
8461 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8462 intel_parser
.is_mem
= 1;
8470 char *save_str
, sign
= 0;
8472 /* Allow constants that start with `+' or `-'. */
8473 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8475 sign
= cur_token
.code
;
8476 intel_match_token (cur_token
.code
);
8477 if (cur_token
.code
!= T_CONST
)
8479 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8485 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8486 strcpy (save_str
+ !!sign
, cur_token
.str
);
8490 /* Get the next token to check for register scaling. */
8491 intel_match_token (cur_token
.code
);
8493 /* Check if this constant is a scaling factor for an
8495 if (cur_token
.code
== '*')
8497 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8499 const reg_entry
*reg
= cur_token
.reg
;
8501 if (!intel_parser
.in_bracket
)
8503 as_bad (_("Register scaling only allowed "
8504 "in memory operands"));
8508 /* Disallow things like [1*si].
8509 sp and esp are invalid as index. */
8510 if (reg
->reg_type
.bitfield
.reg16
)
8511 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8512 else if (i
.index_reg
)
8513 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8515 /* The constant is followed by `* reg', so it must be
8518 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8520 /* Set the scale after setting the register (otherwise,
8521 i386_scale will complain) */
8522 if (!i386_scale (save_str
))
8524 intel_match_token (T_REG
);
8526 /* Since registers are not part of the displacement
8527 string, we may need to remove any preceding '+' from
8528 the displacement string. */
8529 if (*intel_parser
.disp
!= '\0')
8531 char *s
= intel_parser
.disp
;
8532 s
+= strlen (s
) - 1;
8542 /* The constant was not used for register scaling. Since we have
8543 already consumed the token following `*' we now need to put it
8544 back in the stream. */
8545 intel_putback_token ();
8548 /* Add the constant to the displacement string. */
8549 strcat (intel_parser
.disp
, save_str
);
8556 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8560 /* Match the given token against cur_token. If they match, read the next
8561 token from the operand string. */
8563 intel_match_token (int code
)
8565 if (cur_token
.code
== code
)
8572 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8577 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8579 intel_get_token (void)
8582 const reg_entry
*reg
;
8583 struct intel_token new_token
;
8585 new_token
.code
= T_NIL
;
8586 new_token
.reg
= NULL
;
8587 new_token
.str
= NULL
;
8589 /* Free the memory allocated to the previous token and move
8590 cur_token to prev_token. */
8592 free (prev_token
.str
);
8594 prev_token
= cur_token
;
8596 /* Skip whitespace. */
8597 while (is_space_char (*intel_parser
.op_string
))
8598 intel_parser
.op_string
++;
8600 /* Return an empty token if we find nothing else on the line. */
8601 if (*intel_parser
.op_string
== '\0')
8603 cur_token
= new_token
;
8607 /* The new token cannot be larger than the remainder of the operand
8609 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8610 new_token
.str
[0] = '\0';
8612 if (strchr ("0123456789", *intel_parser
.op_string
))
8614 char *p
= new_token
.str
;
8615 char *q
= intel_parser
.op_string
;
8616 new_token
.code
= T_CONST
;
8618 /* Allow any kind of identifier char to encompass floating point and
8619 hexadecimal numbers. */
8620 while (is_identifier_char (*q
))
8624 /* Recognize special symbol names [0-9][bf]. */
8625 if (strlen (intel_parser
.op_string
) == 2
8626 && (intel_parser
.op_string
[1] == 'b'
8627 || intel_parser
.op_string
[1] == 'f'))
8628 new_token
.code
= T_ID
;
8631 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8633 size_t len
= end_op
- intel_parser
.op_string
;
8635 new_token
.code
= T_REG
;
8636 new_token
.reg
= reg
;
8638 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8639 new_token
.str
[len
] = '\0';
8642 else if (is_identifier_char (*intel_parser
.op_string
))
8644 char *p
= new_token
.str
;
8645 char *q
= intel_parser
.op_string
;
8647 /* A '.' or '$' followed by an identifier char is an identifier.
8648 Otherwise, it's operator '.' followed by an expression. */
8649 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8651 new_token
.code
= '.';
8652 new_token
.str
[0] = '.';
8653 new_token
.str
[1] = '\0';
8657 while (is_identifier_char (*q
) || *q
== '@')
8661 if (strcasecmp (new_token
.str
, "NOT") == 0)
8662 new_token
.code
= '~';
8664 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8665 new_token
.code
= '%';
8667 else if (strcasecmp (new_token
.str
, "AND") == 0)
8668 new_token
.code
= '&';
8670 else if (strcasecmp (new_token
.str
, "OR") == 0)
8671 new_token
.code
= '|';
8673 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8674 new_token
.code
= '^';
8676 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8677 new_token
.code
= T_SHL
;
8679 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8680 new_token
.code
= T_SHR
;
8682 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8683 new_token
.code
= T_BYTE
;
8685 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8686 new_token
.code
= T_WORD
;
8688 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8689 new_token
.code
= T_DWORD
;
8691 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8692 new_token
.code
= T_FWORD
;
8694 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8695 new_token
.code
= T_QWORD
;
8697 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8698 /* XXX remove (gcc still uses it) */
8699 || strcasecmp (new_token
.str
, "XWORD") == 0)
8700 new_token
.code
= T_TBYTE
;
8702 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8703 || strcasecmp (new_token
.str
, "OWORD") == 0)
8704 new_token
.code
= T_XMMWORD
;
8706 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8707 new_token
.code
= T_PTR
;
8709 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8710 new_token
.code
= T_SHORT
;
8712 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8714 new_token
.code
= T_OFFSET
;
8716 /* ??? This is not mentioned in the MASM grammar but gcc
8717 makes use of it with -mintel-syntax. OFFSET may be
8718 followed by FLAT: */
8719 if (strncasecmp (q
, " FLAT:", 6) == 0)
8720 strcat (new_token
.str
, " FLAT:");
8723 /* ??? This is not mentioned in the MASM grammar. */
8724 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8726 new_token
.code
= T_OFFSET
;
8728 strcat (new_token
.str
, ":");
8730 as_bad (_("`:' expected"));
8734 new_token
.code
= T_ID
;
8738 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8740 new_token
.code
= *intel_parser
.op_string
;
8741 new_token
.str
[0] = *intel_parser
.op_string
;
8742 new_token
.str
[1] = '\0';
8745 else if (strchr ("<>", *intel_parser
.op_string
)
8746 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8748 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8749 new_token
.str
[0] = *intel_parser
.op_string
;
8750 new_token
.str
[1] = *intel_parser
.op_string
;
8751 new_token
.str
[2] = '\0';
8755 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8757 intel_parser
.op_string
+= strlen (new_token
.str
);
8758 cur_token
= new_token
;
8761 /* Put cur_token back into the token stream and make cur_token point to
8764 intel_putback_token (void)
8766 if (cur_token
.code
!= T_NIL
)
8768 intel_parser
.op_string
-= strlen (cur_token
.str
);
8769 free (cur_token
.str
);
8771 cur_token
= prev_token
;
8773 /* Forget prev_token. */
8774 prev_token
.code
= T_NIL
;
8775 prev_token
.reg
= NULL
;
8776 prev_token
.str
= NULL
;
8780 tc_x86_regname_to_dw2regnum (char *regname
)
8782 unsigned int regnum
;
8783 unsigned int regnames_count
;
8784 static const char *const regnames_32
[] =
8786 "eax", "ecx", "edx", "ebx",
8787 "esp", "ebp", "esi", "edi",
8788 "eip", "eflags", NULL
,
8789 "st0", "st1", "st2", "st3",
8790 "st4", "st5", "st6", "st7",
8792 "xmm0", "xmm1", "xmm2", "xmm3",
8793 "xmm4", "xmm5", "xmm6", "xmm7",
8794 "mm0", "mm1", "mm2", "mm3",
8795 "mm4", "mm5", "mm6", "mm7",
8796 "fcw", "fsw", "mxcsr",
8797 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8800 static const char *const regnames_64
[] =
8802 "rax", "rdx", "rcx", "rbx",
8803 "rsi", "rdi", "rbp", "rsp",
8804 "r8", "r9", "r10", "r11",
8805 "r12", "r13", "r14", "r15",
8807 "xmm0", "xmm1", "xmm2", "xmm3",
8808 "xmm4", "xmm5", "xmm6", "xmm7",
8809 "xmm8", "xmm9", "xmm10", "xmm11",
8810 "xmm12", "xmm13", "xmm14", "xmm15",
8811 "st0", "st1", "st2", "st3",
8812 "st4", "st5", "st6", "st7",
8813 "mm0", "mm1", "mm2", "mm3",
8814 "mm4", "mm5", "mm6", "mm7",
8816 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8817 "fs.base", "gs.base", NULL
, NULL
,
8819 "mxcsr", "fcw", "fsw"
8821 const char *const *regnames
;
8823 if (flag_code
== CODE_64BIT
)
8825 regnames
= regnames_64
;
8826 regnames_count
= ARRAY_SIZE (regnames_64
);
8830 regnames
= regnames_32
;
8831 regnames_count
= ARRAY_SIZE (regnames_32
);
8834 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
8835 if (regnames
[regnum
] != NULL
8836 && strcmp (regname
, regnames
[regnum
]) == 0)
8843 tc_x86_frame_initial_instructions (void)
8845 static unsigned int sp_regno
;
8848 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
8851 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
8852 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8856 i386_elf_section_type (const char *str
, size_t len
)
8858 if (flag_code
== CODE_64BIT
8859 && len
== sizeof ("unwind") - 1
8860 && strncmp (str
, "unwind", 6) == 0)
8861 return SHT_X86_64_UNWIND
;
8868 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8872 expr
.X_op
= O_secrel
;
8873 expr
.X_add_symbol
= symbol
;
8874 expr
.X_add_number
= 0;
8875 emit_expr (&expr
, size
);
8879 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8880 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8883 x86_64_section_letter (int letter
, char **ptr_msg
)
8885 if (flag_code
== CODE_64BIT
)
8888 return SHF_X86_64_LARGE
;
8890 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8893 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8898 x86_64_section_word (char *str
, size_t len
)
8900 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8901 return SHF_X86_64_LARGE
;
8907 handle_large_common (int small ATTRIBUTE_UNUSED
)
8909 if (flag_code
!= CODE_64BIT
)
8911 s_comm_internal (0, elf_common_parse
);
8912 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8916 static segT lbss_section
;
8917 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8918 asection
*saved_bss_section
= bss_section
;
8920 if (lbss_section
== NULL
)
8922 flagword applicable
;
8924 subsegT subseg
= now_subseg
;
8926 /* The .lbss section is for local .largecomm symbols. */
8927 lbss_section
= subseg_new (".lbss", 0);
8928 applicable
= bfd_applicable_section_flags (stdoutput
);
8929 bfd_set_section_flags (stdoutput
, lbss_section
,
8930 applicable
& SEC_ALLOC
);
8931 seg_info (lbss_section
)->bss
= 1;
8933 subseg_set (seg
, subseg
);
8936 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8937 bss_section
= lbss_section
;
8939 s_comm_internal (0, elf_common_parse
);
8941 elf_com_section_ptr
= saved_com_section_ptr
;
8942 bss_section
= saved_bss_section
;
8945 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */