1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1093 CPU_RDPRU_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1095 CPU_MCOMMIT_FLAGS
, 0 },
1098 static const noarch_entry cpu_noarch
[] =
1100 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1101 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1102 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1103 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1104 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1105 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1106 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1110 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1113 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1131 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1132 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1134 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1135 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1136 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1137 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1141 /* Like s_lcomm_internal in gas/read.c but the alignment string
1142 is allowed to be optional. */
1145 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1152 && *input_line_pointer
== ',')
1154 align
= parse_align (needs_align
- 1);
1156 if (align
== (addressT
) -1)
1171 bss_alloc (symbolP
, size
, align
);
1176 pe_lcomm (int needs_align
)
1178 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1182 const pseudo_typeS md_pseudo_table
[] =
1184 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1185 {"align", s_align_bytes
, 0},
1187 {"align", s_align_ptwo
, 0},
1189 {"arch", set_cpu_arch
, 0},
1193 {"lcomm", pe_lcomm
, 1},
1195 {"ffloat", float_cons
, 'f'},
1196 {"dfloat", float_cons
, 'd'},
1197 {"tfloat", float_cons
, 'x'},
1199 {"slong", signed_cons
, 4},
1200 {"noopt", s_ignore
, 0},
1201 {"optim", s_ignore
, 0},
1202 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1203 {"code16", set_code_flag
, CODE_16BIT
},
1204 {"code32", set_code_flag
, CODE_32BIT
},
1206 {"code64", set_code_flag
, CODE_64BIT
},
1208 {"intel_syntax", set_intel_syntax
, 1},
1209 {"att_syntax", set_intel_syntax
, 0},
1210 {"intel_mnemonic", set_intel_mnemonic
, 1},
1211 {"att_mnemonic", set_intel_mnemonic
, 0},
1212 {"allow_index_reg", set_allow_index_reg
, 1},
1213 {"disallow_index_reg", set_allow_index_reg
, 0},
1214 {"sse_check", set_check
, 0},
1215 {"operand_check", set_check
, 1},
1216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1217 {"largecomm", handle_large_common
, 0},
1219 {"file", dwarf2_directive_file
, 0},
1220 {"loc", dwarf2_directive_loc
, 0},
1221 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1224 {"secrel32", pe_directive_secrel
, 0},
1229 /* For interface with expression (). */
1230 extern char *input_line_pointer
;
1232 /* Hash table for instruction mnemonic lookup. */
1233 static struct hash_control
*op_hash
;
1235 /* Hash table for register lookup. */
1236 static struct hash_control
*reg_hash
;
1238 /* Various efficient no-op patterns for aligning code labels.
1239 Note: Don't try to assemble the instructions in the comments.
1240 0L and 0w are not legal. */
1241 static const unsigned char f32_1
[] =
1243 static const unsigned char f32_2
[] =
1244 {0x66,0x90}; /* xchg %ax,%ax */
1245 static const unsigned char f32_3
[] =
1246 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1247 static const unsigned char f32_4
[] =
1248 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1249 static const unsigned char f32_6
[] =
1250 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1251 static const unsigned char f32_7
[] =
1252 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1253 static const unsigned char f16_3
[] =
1254 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1255 static const unsigned char f16_4
[] =
1256 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1257 static const unsigned char jump_disp8
[] =
1258 {0xeb}; /* jmp disp8 */
1259 static const unsigned char jump32_disp32
[] =
1260 {0xe9}; /* jmp disp32 */
1261 static const unsigned char jump16_disp32
[] =
1262 {0x66,0xe9}; /* jmp disp32 */
1263 /* 32-bit NOPs patterns. */
1264 static const unsigned char *const f32_patt
[] = {
1265 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1267 /* 16-bit NOPs patterns. */
1268 static const unsigned char *const f16_patt
[] = {
1269 f32_1
, f32_2
, f16_3
, f16_4
1271 /* nopl (%[re]ax) */
1272 static const unsigned char alt_3
[] =
1274 /* nopl 0(%[re]ax) */
1275 static const unsigned char alt_4
[] =
1276 {0x0f,0x1f,0x40,0x00};
1277 /* nopl 0(%[re]ax,%[re]ax,1) */
1278 static const unsigned char alt_5
[] =
1279 {0x0f,0x1f,0x44,0x00,0x00};
1280 /* nopw 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_6
[] =
1282 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopl 0L(%[re]ax) */
1284 static const unsigned char alt_7
[] =
1285 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1286 /* nopl 0L(%[re]ax,%[re]ax,1) */
1287 static const unsigned char alt_8
[] =
1288 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1289 /* nopw 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_9
[] =
1291 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_10
[] =
1294 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* data16 nopw %cs:0L(%eax,%eax,1) */
1296 static const unsigned char alt_11
[] =
1297 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* 32-bit and 64-bit NOPs patterns. */
1299 static const unsigned char *const alt_patt
[] = {
1300 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1301 alt_9
, alt_10
, alt_11
1304 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1305 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1308 i386_output_nops (char *where
, const unsigned char *const *patt
,
1309 int count
, int max_single_nop_size
)
1312 /* Place the longer NOP first. */
1315 const unsigned char *nops
;
1317 if (max_single_nop_size
< 1)
1319 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1320 max_single_nop_size
);
1324 nops
= patt
[max_single_nop_size
- 1];
1326 /* Use the smaller one if the requsted one isn't available. */
1329 max_single_nop_size
--;
1330 nops
= patt
[max_single_nop_size
- 1];
1333 last
= count
% max_single_nop_size
;
1336 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1337 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1341 nops
= patt
[last
- 1];
1344 /* Use the smaller one plus one-byte NOP if the needed one
1347 nops
= patt
[last
- 1];
1348 memcpy (where
+ offset
, nops
, last
);
1349 where
[offset
+ last
] = *patt
[0];
1352 memcpy (where
+ offset
, nops
, last
);
1357 fits_in_imm7 (offsetT num
)
1359 return (num
& 0x7f) == num
;
1363 fits_in_imm31 (offsetT num
)
1365 return (num
& 0x7fffffff) == num
;
1368 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1369 single NOP instruction LIMIT. */
1372 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1374 const unsigned char *const *patt
= NULL
;
1375 int max_single_nop_size
;
1376 /* Maximum number of NOPs before switching to jump over NOPs. */
1377 int max_number_of_nops
;
1379 switch (fragP
->fr_type
)
1388 /* We need to decide which NOP sequence to use for 32bit and
1389 64bit. When -mtune= is used:
1391 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1392 PROCESSOR_GENERIC32, f32_patt will be used.
1393 2. For the rest, alt_patt will be used.
1395 When -mtune= isn't used, alt_patt will be used if
1396 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1399 When -march= or .arch is used, we can't use anything beyond
1400 cpu_arch_isa_flags. */
1402 if (flag_code
== CODE_16BIT
)
1405 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1406 /* Limit number of NOPs to 2 in 16-bit mode. */
1407 max_number_of_nops
= 2;
1411 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1413 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1414 switch (cpu_arch_tune
)
1416 case PROCESSOR_UNKNOWN
:
1417 /* We use cpu_arch_isa_flags to check if we SHOULD
1418 optimize with nops. */
1419 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1424 case PROCESSOR_PENTIUM4
:
1425 case PROCESSOR_NOCONA
:
1426 case PROCESSOR_CORE
:
1427 case PROCESSOR_CORE2
:
1428 case PROCESSOR_COREI7
:
1429 case PROCESSOR_L1OM
:
1430 case PROCESSOR_K1OM
:
1431 case PROCESSOR_GENERIC64
:
1433 case PROCESSOR_ATHLON
:
1435 case PROCESSOR_AMDFAM10
:
1437 case PROCESSOR_ZNVER
:
1441 case PROCESSOR_I386
:
1442 case PROCESSOR_I486
:
1443 case PROCESSOR_PENTIUM
:
1444 case PROCESSOR_PENTIUMPRO
:
1445 case PROCESSOR_IAMCU
:
1446 case PROCESSOR_GENERIC32
:
1453 switch (fragP
->tc_frag_data
.tune
)
1455 case PROCESSOR_UNKNOWN
:
1456 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1457 PROCESSOR_UNKNOWN. */
1461 case PROCESSOR_I386
:
1462 case PROCESSOR_I486
:
1463 case PROCESSOR_PENTIUM
:
1464 case PROCESSOR_IAMCU
:
1466 case PROCESSOR_ATHLON
:
1468 case PROCESSOR_AMDFAM10
:
1470 case PROCESSOR_ZNVER
:
1472 case PROCESSOR_GENERIC32
:
1473 /* We use cpu_arch_isa_flags to check if we CAN optimize
1475 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1480 case PROCESSOR_PENTIUMPRO
:
1481 case PROCESSOR_PENTIUM4
:
1482 case PROCESSOR_NOCONA
:
1483 case PROCESSOR_CORE
:
1484 case PROCESSOR_CORE2
:
1485 case PROCESSOR_COREI7
:
1486 case PROCESSOR_L1OM
:
1487 case PROCESSOR_K1OM
:
1488 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1493 case PROCESSOR_GENERIC64
:
1499 if (patt
== f32_patt
)
1501 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1502 /* Limit number of NOPs to 2 for older processors. */
1503 max_number_of_nops
= 2;
1507 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1508 /* Limit number of NOPs to 7 for newer processors. */
1509 max_number_of_nops
= 7;
1514 limit
= max_single_nop_size
;
1516 if (fragP
->fr_type
== rs_fill_nop
)
1518 /* Output NOPs for .nop directive. */
1519 if (limit
> max_single_nop_size
)
1521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1522 _("invalid single nop size: %d "
1523 "(expect within [0, %d])"),
1524 limit
, max_single_nop_size
);
1529 fragP
->fr_var
= count
;
1531 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1533 /* Generate jump over NOPs. */
1534 offsetT disp
= count
- 2;
1535 if (fits_in_imm7 (disp
))
1537 /* Use "jmp disp8" if possible. */
1539 where
[0] = jump_disp8
[0];
1545 unsigned int size_of_jump
;
1547 if (flag_code
== CODE_16BIT
)
1549 where
[0] = jump16_disp32
[0];
1550 where
[1] = jump16_disp32
[1];
1555 where
[0] = jump32_disp32
[0];
1559 count
-= size_of_jump
+ 4;
1560 if (!fits_in_imm31 (count
))
1562 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1563 _("jump over nop padding out of range"));
1567 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1568 where
+= size_of_jump
+ 4;
1572 /* Generate multiple NOPs. */
1573 i386_output_nops (where
, patt
, count
, limit
);
1577 operand_type_all_zero (const union i386_operand_type
*x
)
1579 switch (ARRAY_SIZE(x
->array
))
1590 return !x
->array
[0];
1597 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1599 switch (ARRAY_SIZE(x
->array
))
1615 x
->bitfield
.class = ClassNone
;
1616 x
->bitfield
.instance
= InstanceNone
;
1620 operand_type_equal (const union i386_operand_type
*x
,
1621 const union i386_operand_type
*y
)
1623 switch (ARRAY_SIZE(x
->array
))
1626 if (x
->array
[2] != y
->array
[2])
1630 if (x
->array
[1] != y
->array
[1])
1634 return x
->array
[0] == y
->array
[0];
1642 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1644 switch (ARRAY_SIZE(x
->array
))
1659 return !x
->array
[0];
1666 cpu_flags_equal (const union i386_cpu_flags
*x
,
1667 const union i386_cpu_flags
*y
)
1669 switch (ARRAY_SIZE(x
->array
))
1672 if (x
->array
[3] != y
->array
[3])
1676 if (x
->array
[2] != y
->array
[2])
1680 if (x
->array
[1] != y
->array
[1])
1684 return x
->array
[0] == y
->array
[0];
1692 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1694 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1695 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1698 static INLINE i386_cpu_flags
1699 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1701 switch (ARRAY_SIZE (x
.array
))
1704 x
.array
[3] &= y
.array
[3];
1707 x
.array
[2] &= y
.array
[2];
1710 x
.array
[1] &= y
.array
[1];
1713 x
.array
[0] &= y
.array
[0];
1721 static INLINE i386_cpu_flags
1722 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1724 switch (ARRAY_SIZE (x
.array
))
1727 x
.array
[3] |= y
.array
[3];
1730 x
.array
[2] |= y
.array
[2];
1733 x
.array
[1] |= y
.array
[1];
1736 x
.array
[0] |= y
.array
[0];
1744 static INLINE i386_cpu_flags
1745 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1747 switch (ARRAY_SIZE (x
.array
))
1750 x
.array
[3] &= ~y
.array
[3];
1753 x
.array
[2] &= ~y
.array
[2];
1756 x
.array
[1] &= ~y
.array
[1];
1759 x
.array
[0] &= ~y
.array
[0];
1767 #define CPU_FLAGS_ARCH_MATCH 0x1
1768 #define CPU_FLAGS_64BIT_MATCH 0x2
1770 #define CPU_FLAGS_PERFECT_MATCH \
1771 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1773 /* Return CPU flags match bits. */
1776 cpu_flags_match (const insn_template
*t
)
1778 i386_cpu_flags x
= t
->cpu_flags
;
1779 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1781 x
.bitfield
.cpu64
= 0;
1782 x
.bitfield
.cpuno64
= 0;
1784 if (cpu_flags_all_zero (&x
))
1786 /* This instruction is available on all archs. */
1787 match
|= CPU_FLAGS_ARCH_MATCH
;
1791 /* This instruction is available only on some archs. */
1792 i386_cpu_flags cpu
= cpu_arch_flags
;
1794 /* AVX512VL is no standalone feature - match it and then strip it. */
1795 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1797 x
.bitfield
.cpuavx512vl
= 0;
1799 cpu
= cpu_flags_and (x
, cpu
);
1800 if (!cpu_flags_all_zero (&cpu
))
1802 if (x
.bitfield
.cpuavx
)
1804 /* We need to check a few extra flags with AVX. */
1805 if (cpu
.bitfield
.cpuavx
1806 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1807 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1808 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1809 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1810 match
|= CPU_FLAGS_ARCH_MATCH
;
1812 else if (x
.bitfield
.cpuavx512f
)
1814 /* We need to check a few extra flags with AVX512F. */
1815 if (cpu
.bitfield
.cpuavx512f
1816 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1817 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1818 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1819 match
|= CPU_FLAGS_ARCH_MATCH
;
1822 match
|= CPU_FLAGS_ARCH_MATCH
;
1828 static INLINE i386_operand_type
1829 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1831 if (x
.bitfield
.class != y
.bitfield
.class)
1832 x
.bitfield
.class = ClassNone
;
1833 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1834 x
.bitfield
.instance
= InstanceNone
;
1836 switch (ARRAY_SIZE (x
.array
))
1839 x
.array
[2] &= y
.array
[2];
1842 x
.array
[1] &= y
.array
[1];
1845 x
.array
[0] &= y
.array
[0];
1853 static INLINE i386_operand_type
1854 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1856 gas_assert (y
.bitfield
.class == ClassNone
);
1857 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1859 switch (ARRAY_SIZE (x
.array
))
1862 x
.array
[2] &= ~y
.array
[2];
1865 x
.array
[1] &= ~y
.array
[1];
1868 x
.array
[0] &= ~y
.array
[0];
1876 static INLINE i386_operand_type
1877 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1879 gas_assert (x
.bitfield
.class == ClassNone
||
1880 y
.bitfield
.class == ClassNone
||
1881 x
.bitfield
.class == y
.bitfield
.class);
1882 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1883 y
.bitfield
.instance
== InstanceNone
||
1884 x
.bitfield
.instance
== y
.bitfield
.instance
);
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[2] |= y
.array
[2];
1892 x
.array
[1] |= y
.array
[1];
1895 x
.array
[0] |= y
.array
[0];
1903 static INLINE i386_operand_type
1904 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1906 gas_assert (y
.bitfield
.class == ClassNone
);
1907 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1909 switch (ARRAY_SIZE (x
.array
))
1912 x
.array
[2] ^= y
.array
[2];
1915 x
.array
[1] ^= y
.array
[1];
1918 x
.array
[0] ^= y
.array
[0];
1926 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1927 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1928 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1929 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1930 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
1931 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
1932 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1933 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1934 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1935 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1936 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1937 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1938 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1939 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1940 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1941 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1942 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1953 operand_type_check (i386_operand_type t
, enum operand_type c
)
1958 return t
.bitfield
.class == Reg
;
1961 return (t
.bitfield
.imm8
1965 || t
.bitfield
.imm32s
1966 || t
.bitfield
.imm64
);
1969 return (t
.bitfield
.disp8
1970 || t
.bitfield
.disp16
1971 || t
.bitfield
.disp32
1972 || t
.bitfield
.disp32s
1973 || t
.bitfield
.disp64
);
1976 return (t
.bitfield
.disp8
1977 || t
.bitfield
.disp16
1978 || t
.bitfield
.disp32
1979 || t
.bitfield
.disp32s
1980 || t
.bitfield
.disp64
1981 || t
.bitfield
.baseindex
);
1990 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1991 between operand GIVEN and opeand WANTED for instruction template T. */
1994 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1997 return !((i
.types
[given
].bitfield
.byte
1998 && !t
->operand_types
[wanted
].bitfield
.byte
)
1999 || (i
.types
[given
].bitfield
.word
2000 && !t
->operand_types
[wanted
].bitfield
.word
)
2001 || (i
.types
[given
].bitfield
.dword
2002 && !t
->operand_types
[wanted
].bitfield
.dword
)
2003 || (i
.types
[given
].bitfield
.qword
2004 && !t
->operand_types
[wanted
].bitfield
.qword
)
2005 || (i
.types
[given
].bitfield
.tbyte
2006 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2009 /* Return 1 if there is no conflict in SIMD register between operand
2010 GIVEN and opeand WANTED for instruction template T. */
2013 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2016 return !((i
.types
[given
].bitfield
.xmmword
2017 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2018 || (i
.types
[given
].bitfield
.ymmword
2019 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2020 || (i
.types
[given
].bitfield
.zmmword
2021 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2024 /* Return 1 if there is no conflict in any size between operand GIVEN
2025 and opeand WANTED for instruction template T. */
2028 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2031 return (match_operand_size (t
, wanted
, given
)
2032 && !((i
.types
[given
].bitfield
.unspecified
2034 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2035 || (i
.types
[given
].bitfield
.fword
2036 && !t
->operand_types
[wanted
].bitfield
.fword
)
2037 /* For scalar opcode templates to allow register and memory
2038 operands at the same time, some special casing is needed
2039 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2040 down-conversion vpmov*. */
2041 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2042 && !t
->opcode_modifier
.broadcast
2043 && (t
->operand_types
[wanted
].bitfield
.byte
2044 || t
->operand_types
[wanted
].bitfield
.word
2045 || t
->operand_types
[wanted
].bitfield
.dword
2046 || t
->operand_types
[wanted
].bitfield
.qword
))
2047 ? (i
.types
[given
].bitfield
.xmmword
2048 || i
.types
[given
].bitfield
.ymmword
2049 || i
.types
[given
].bitfield
.zmmword
)
2050 : !match_simd_size(t
, wanted
, given
))));
2053 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2054 operands for instruction template T, and it has MATCH_REVERSE set if there
2055 is no size conflict on any operands for the template with operands reversed
2056 (and the template allows for reversing in the first place). */
2058 #define MATCH_STRAIGHT 1
2059 #define MATCH_REVERSE 2
2061 static INLINE
unsigned int
2062 operand_size_match (const insn_template
*t
)
2064 unsigned int j
, match
= MATCH_STRAIGHT
;
2066 /* Don't check jump instructions. */
2067 if (t
->opcode_modifier
.jump
2068 || t
->opcode_modifier
.jumpbyte
2069 || t
->opcode_modifier
.jumpdword
2070 || t
->opcode_modifier
.jumpintersegment
)
2073 /* Check memory and accumulator operand size. */
2074 for (j
= 0; j
< i
.operands
; j
++)
2076 if (i
.types
[j
].bitfield
.class != Reg
2077 && i
.types
[j
].bitfield
.class != RegSIMD
2078 && t
->operand_types
[j
].bitfield
.anysize
)
2081 if (t
->operand_types
[j
].bitfield
.class == Reg
2082 && !match_operand_size (t
, j
, j
))
2088 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2089 && !match_simd_size (t
, j
, j
))
2095 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2096 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2102 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2109 if (!t
->opcode_modifier
.d
)
2113 i
.error
= operand_size_mismatch
;
2117 /* Check reverse. */
2118 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2120 for (j
= 0; j
< i
.operands
; j
++)
2122 unsigned int given
= i
.operands
- j
- 1;
2124 if (t
->operand_types
[j
].bitfield
.class == Reg
2125 && !match_operand_size (t
, j
, given
))
2128 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2129 && !match_simd_size (t
, j
, given
))
2132 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2133 && (!match_operand_size (t
, j
, given
)
2134 || !match_simd_size (t
, j
, given
)))
2137 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2141 return match
| MATCH_REVERSE
;
2145 operand_type_match (i386_operand_type overlap
,
2146 i386_operand_type given
)
2148 i386_operand_type temp
= overlap
;
2150 temp
.bitfield
.jumpabsolute
= 0;
2151 temp
.bitfield
.unspecified
= 0;
2152 temp
.bitfield
.byte
= 0;
2153 temp
.bitfield
.word
= 0;
2154 temp
.bitfield
.dword
= 0;
2155 temp
.bitfield
.fword
= 0;
2156 temp
.bitfield
.qword
= 0;
2157 temp
.bitfield
.tbyte
= 0;
2158 temp
.bitfield
.xmmword
= 0;
2159 temp
.bitfield
.ymmword
= 0;
2160 temp
.bitfield
.zmmword
= 0;
2161 if (operand_type_all_zero (&temp
))
2164 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2165 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2169 i
.error
= operand_type_mismatch
;
2173 /* If given types g0 and g1 are registers they must be of the same type
2174 unless the expected operand type register overlap is null.
2175 Memory operand size of certain SIMD instructions is also being checked
2179 operand_type_register_match (i386_operand_type g0
,
2180 i386_operand_type t0
,
2181 i386_operand_type g1
,
2182 i386_operand_type t1
)
2184 if (g0
.bitfield
.class != Reg
2185 && g0
.bitfield
.class != RegSIMD
2186 && (!operand_type_check (g0
, anymem
)
2187 || g0
.bitfield
.unspecified
2188 || t0
.bitfield
.class != RegSIMD
))
2191 if (g1
.bitfield
.class != Reg
2192 && g1
.bitfield
.class != RegSIMD
2193 && (!operand_type_check (g1
, anymem
)
2194 || g1
.bitfield
.unspecified
2195 || t1
.bitfield
.class != RegSIMD
))
2198 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2199 && g0
.bitfield
.word
== g1
.bitfield
.word
2200 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2201 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2202 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2203 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2204 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2207 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2208 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2209 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2210 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2211 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2212 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2213 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2216 i
.error
= register_type_mismatch
;
2221 static INLINE
unsigned int
2222 register_number (const reg_entry
*r
)
2224 unsigned int nr
= r
->reg_num
;
2226 if (r
->reg_flags
& RegRex
)
2229 if (r
->reg_flags
& RegVRex
)
2235 static INLINE
unsigned int
2236 mode_from_disp_size (i386_operand_type t
)
2238 if (t
.bitfield
.disp8
)
2240 else if (t
.bitfield
.disp16
2241 || t
.bitfield
.disp32
2242 || t
.bitfield
.disp32s
)
2249 fits_in_signed_byte (addressT num
)
2251 return num
+ 0x80 <= 0xff;
2255 fits_in_unsigned_byte (addressT num
)
2261 fits_in_unsigned_word (addressT num
)
2263 return num
<= 0xffff;
2267 fits_in_signed_word (addressT num
)
2269 return num
+ 0x8000 <= 0xffff;
2273 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2278 return num
+ 0x80000000 <= 0xffffffff;
2280 } /* fits_in_signed_long() */
2283 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2288 return num
<= 0xffffffff;
2290 } /* fits_in_unsigned_long() */
2293 fits_in_disp8 (offsetT num
)
2295 int shift
= i
.memshift
;
2301 mask
= (1 << shift
) - 1;
2303 /* Return 0 if NUM isn't properly aligned. */
2307 /* Check if NUM will fit in 8bit after shift. */
2308 return fits_in_signed_byte (num
>> shift
);
2312 fits_in_imm4 (offsetT num
)
2314 return (num
& 0xf) == num
;
2317 static i386_operand_type
2318 smallest_imm_type (offsetT num
)
2320 i386_operand_type t
;
2322 operand_type_set (&t
, 0);
2323 t
.bitfield
.imm64
= 1;
2325 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2327 /* This code is disabled on the 486 because all the Imm1 forms
2328 in the opcode table are slower on the i486. They're the
2329 versions with the implicitly specified single-position
2330 displacement, which has another syntax if you really want to
2332 t
.bitfield
.imm1
= 1;
2333 t
.bitfield
.imm8
= 1;
2334 t
.bitfield
.imm8s
= 1;
2335 t
.bitfield
.imm16
= 1;
2336 t
.bitfield
.imm32
= 1;
2337 t
.bitfield
.imm32s
= 1;
2339 else if (fits_in_signed_byte (num
))
2341 t
.bitfield
.imm8
= 1;
2342 t
.bitfield
.imm8s
= 1;
2343 t
.bitfield
.imm16
= 1;
2344 t
.bitfield
.imm32
= 1;
2345 t
.bitfield
.imm32s
= 1;
2347 else if (fits_in_unsigned_byte (num
))
2349 t
.bitfield
.imm8
= 1;
2350 t
.bitfield
.imm16
= 1;
2351 t
.bitfield
.imm32
= 1;
2352 t
.bitfield
.imm32s
= 1;
2354 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2356 t
.bitfield
.imm16
= 1;
2357 t
.bitfield
.imm32
= 1;
2358 t
.bitfield
.imm32s
= 1;
2360 else if (fits_in_signed_long (num
))
2362 t
.bitfield
.imm32
= 1;
2363 t
.bitfield
.imm32s
= 1;
2365 else if (fits_in_unsigned_long (num
))
2366 t
.bitfield
.imm32
= 1;
2372 offset_in_range (offsetT val
, int size
)
2378 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2379 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2380 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2382 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2388 /* If BFD64, sign extend val for 32bit address mode. */
2389 if (flag_code
!= CODE_64BIT
2390 || i
.prefix
[ADDR_PREFIX
])
2391 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2392 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2395 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2397 char buf1
[40], buf2
[40];
2399 sprint_value (buf1
, val
);
2400 sprint_value (buf2
, val
& mask
);
2401 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2416 a. PREFIX_EXIST if attempting to add a prefix where one from the
2417 same class already exists.
2418 b. PREFIX_LOCK if lock prefix is added.
2419 c. PREFIX_REP if rep/repne prefix is added.
2420 d. PREFIX_DS if ds prefix is added.
2421 e. PREFIX_OTHER if other prefix is added.
2424 static enum PREFIX_GROUP
2425 add_prefix (unsigned int prefix
)
2427 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2430 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2431 && flag_code
== CODE_64BIT
)
2433 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2434 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2435 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2436 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2447 case DS_PREFIX_OPCODE
:
2450 case CS_PREFIX_OPCODE
:
2451 case ES_PREFIX_OPCODE
:
2452 case FS_PREFIX_OPCODE
:
2453 case GS_PREFIX_OPCODE
:
2454 case SS_PREFIX_OPCODE
:
2458 case REPNE_PREFIX_OPCODE
:
2459 case REPE_PREFIX_OPCODE
:
2464 case LOCK_PREFIX_OPCODE
:
2473 case ADDR_PREFIX_OPCODE
:
2477 case DATA_PREFIX_OPCODE
:
2481 if (i
.prefix
[q
] != 0)
2489 i
.prefix
[q
] |= prefix
;
2492 as_bad (_("same type of prefix used twice"));
2498 update_code_flag (int value
, int check
)
2500 PRINTF_LIKE ((*as_error
));
2502 flag_code
= (enum flag_code
) value
;
2503 if (flag_code
== CODE_64BIT
)
2505 cpu_arch_flags
.bitfield
.cpu64
= 1;
2506 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2510 cpu_arch_flags
.bitfield
.cpu64
= 0;
2511 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2513 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2516 as_error
= as_fatal
;
2519 (*as_error
) (_("64bit mode not supported on `%s'."),
2520 cpu_arch_name
? cpu_arch_name
: default_arch
);
2522 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2525 as_error
= as_fatal
;
2528 (*as_error
) (_("32bit mode not supported on `%s'."),
2529 cpu_arch_name
? cpu_arch_name
: default_arch
);
2531 stackop_size
= '\0';
2535 set_code_flag (int value
)
2537 update_code_flag (value
, 0);
2541 set_16bit_gcc_code_flag (int new_code_flag
)
2543 flag_code
= (enum flag_code
) new_code_flag
;
2544 if (flag_code
!= CODE_16BIT
)
2546 cpu_arch_flags
.bitfield
.cpu64
= 0;
2547 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2548 stackop_size
= LONG_MNEM_SUFFIX
;
2552 set_intel_syntax (int syntax_flag
)
2554 /* Find out if register prefixing is specified. */
2555 int ask_naked_reg
= 0;
2558 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2561 int e
= get_symbol_name (&string
);
2563 if (strcmp (string
, "prefix") == 0)
2565 else if (strcmp (string
, "noprefix") == 0)
2568 as_bad (_("bad argument to syntax directive."));
2569 (void) restore_line_pointer (e
);
2571 demand_empty_rest_of_line ();
2573 intel_syntax
= syntax_flag
;
2575 if (ask_naked_reg
== 0)
2576 allow_naked_reg
= (intel_syntax
2577 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2579 allow_naked_reg
= (ask_naked_reg
< 0);
2581 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2583 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2584 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2585 register_prefix
= allow_naked_reg
? "" : "%";
2589 set_intel_mnemonic (int mnemonic_flag
)
2591 intel_mnemonic
= mnemonic_flag
;
2595 set_allow_index_reg (int flag
)
2597 allow_index_reg
= flag
;
2601 set_check (int what
)
2603 enum check_kind
*kind
;
2608 kind
= &operand_check
;
2619 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2622 int e
= get_symbol_name (&string
);
2624 if (strcmp (string
, "none") == 0)
2626 else if (strcmp (string
, "warning") == 0)
2627 *kind
= check_warning
;
2628 else if (strcmp (string
, "error") == 0)
2629 *kind
= check_error
;
2631 as_bad (_("bad argument to %s_check directive."), str
);
2632 (void) restore_line_pointer (e
);
2635 as_bad (_("missing argument for %s_check directive"), str
);
2637 demand_empty_rest_of_line ();
2641 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2642 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2645 static const char *arch
;
2647 /* Intel LIOM is only supported on ELF. */
2653 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2654 use default_arch. */
2655 arch
= cpu_arch_name
;
2657 arch
= default_arch
;
2660 /* If we are targeting Intel MCU, we must enable it. */
2661 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2662 || new_flag
.bitfield
.cpuiamcu
)
2665 /* If we are targeting Intel L1OM, we must enable it. */
2666 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2667 || new_flag
.bitfield
.cpul1om
)
2670 /* If we are targeting Intel K1OM, we must enable it. */
2671 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2672 || new_flag
.bitfield
.cpuk1om
)
2675 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2680 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2684 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2687 int e
= get_symbol_name (&string
);
2689 i386_cpu_flags flags
;
2691 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2693 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2695 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2699 cpu_arch_name
= cpu_arch
[j
].name
;
2700 cpu_sub_arch_name
= NULL
;
2701 cpu_arch_flags
= cpu_arch
[j
].flags
;
2702 if (flag_code
== CODE_64BIT
)
2704 cpu_arch_flags
.bitfield
.cpu64
= 1;
2705 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2709 cpu_arch_flags
.bitfield
.cpu64
= 0;
2710 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2712 cpu_arch_isa
= cpu_arch
[j
].type
;
2713 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2714 if (!cpu_arch_tune_set
)
2716 cpu_arch_tune
= cpu_arch_isa
;
2717 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2722 flags
= cpu_flags_or (cpu_arch_flags
,
2725 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2727 if (cpu_sub_arch_name
)
2729 char *name
= cpu_sub_arch_name
;
2730 cpu_sub_arch_name
= concat (name
,
2732 (const char *) NULL
);
2736 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2737 cpu_arch_flags
= flags
;
2738 cpu_arch_isa_flags
= flags
;
2742 = cpu_flags_or (cpu_arch_isa_flags
,
2744 (void) restore_line_pointer (e
);
2745 demand_empty_rest_of_line ();
2750 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2752 /* Disable an ISA extension. */
2753 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2754 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2756 flags
= cpu_flags_and_not (cpu_arch_flags
,
2757 cpu_noarch
[j
].flags
);
2758 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2760 if (cpu_sub_arch_name
)
2762 char *name
= cpu_sub_arch_name
;
2763 cpu_sub_arch_name
= concat (name
, string
,
2764 (const char *) NULL
);
2768 cpu_sub_arch_name
= xstrdup (string
);
2769 cpu_arch_flags
= flags
;
2770 cpu_arch_isa_flags
= flags
;
2772 (void) restore_line_pointer (e
);
2773 demand_empty_rest_of_line ();
2777 j
= ARRAY_SIZE (cpu_arch
);
2780 if (j
>= ARRAY_SIZE (cpu_arch
))
2781 as_bad (_("no such architecture: `%s'"), string
);
2783 *input_line_pointer
= e
;
2786 as_bad (_("missing cpu architecture"));
2788 no_cond_jump_promotion
= 0;
2789 if (*input_line_pointer
== ','
2790 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2795 ++input_line_pointer
;
2796 e
= get_symbol_name (&string
);
2798 if (strcmp (string
, "nojumps") == 0)
2799 no_cond_jump_promotion
= 1;
2800 else if (strcmp (string
, "jumps") == 0)
2803 as_bad (_("no such architecture modifier: `%s'"), string
);
2805 (void) restore_line_pointer (e
);
2808 demand_empty_rest_of_line ();
2811 enum bfd_architecture
2814 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2816 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2817 || flag_code
!= CODE_64BIT
)
2818 as_fatal (_("Intel L1OM is 64bit ELF only"));
2819 return bfd_arch_l1om
;
2821 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2823 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2824 || flag_code
!= CODE_64BIT
)
2825 as_fatal (_("Intel K1OM is 64bit ELF only"));
2826 return bfd_arch_k1om
;
2828 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2830 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2831 || flag_code
== CODE_64BIT
)
2832 as_fatal (_("Intel MCU is 32bit ELF only"));
2833 return bfd_arch_iamcu
;
2836 return bfd_arch_i386
;
2842 if (!strncmp (default_arch
, "x86_64", 6))
2844 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2846 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2847 || default_arch
[6] != '\0')
2848 as_fatal (_("Intel L1OM is 64bit ELF only"));
2849 return bfd_mach_l1om
;
2851 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2853 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2854 || default_arch
[6] != '\0')
2855 as_fatal (_("Intel K1OM is 64bit ELF only"));
2856 return bfd_mach_k1om
;
2858 else if (default_arch
[6] == '\0')
2859 return bfd_mach_x86_64
;
2861 return bfd_mach_x64_32
;
2863 else if (!strcmp (default_arch
, "i386")
2864 || !strcmp (default_arch
, "iamcu"))
2866 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2868 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2869 as_fatal (_("Intel MCU is 32bit ELF only"));
2870 return bfd_mach_i386_iamcu
;
2873 return bfd_mach_i386_i386
;
2876 as_fatal (_("unknown architecture"));
2882 const char *hash_err
;
2884 /* Support pseudo prefixes like {disp32}. */
2885 lex_type
['{'] = LEX_BEGIN_NAME
;
2887 /* Initialize op_hash hash table. */
2888 op_hash
= hash_new ();
2891 const insn_template
*optab
;
2892 templates
*core_optab
;
2894 /* Setup for loop. */
2896 core_optab
= XNEW (templates
);
2897 core_optab
->start
= optab
;
2902 if (optab
->name
== NULL
2903 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2905 /* different name --> ship out current template list;
2906 add to hash table; & begin anew. */
2907 core_optab
->end
= optab
;
2908 hash_err
= hash_insert (op_hash
,
2910 (void *) core_optab
);
2913 as_fatal (_("can't hash %s: %s"),
2917 if (optab
->name
== NULL
)
2919 core_optab
= XNEW (templates
);
2920 core_optab
->start
= optab
;
2925 /* Initialize reg_hash hash table. */
2926 reg_hash
= hash_new ();
2928 const reg_entry
*regtab
;
2929 unsigned int regtab_size
= i386_regtab_size
;
2931 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2933 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2935 as_fatal (_("can't hash %s: %s"),
2941 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2946 for (c
= 0; c
< 256; c
++)
2951 mnemonic_chars
[c
] = c
;
2952 register_chars
[c
] = c
;
2953 operand_chars
[c
] = c
;
2955 else if (ISLOWER (c
))
2957 mnemonic_chars
[c
] = c
;
2958 register_chars
[c
] = c
;
2959 operand_chars
[c
] = c
;
2961 else if (ISUPPER (c
))
2963 mnemonic_chars
[c
] = TOLOWER (c
);
2964 register_chars
[c
] = mnemonic_chars
[c
];
2965 operand_chars
[c
] = c
;
2967 else if (c
== '{' || c
== '}')
2969 mnemonic_chars
[c
] = c
;
2970 operand_chars
[c
] = c
;
2973 if (ISALPHA (c
) || ISDIGIT (c
))
2974 identifier_chars
[c
] = c
;
2977 identifier_chars
[c
] = c
;
2978 operand_chars
[c
] = c
;
2983 identifier_chars
['@'] = '@';
2986 identifier_chars
['?'] = '?';
2987 operand_chars
['?'] = '?';
2989 digit_chars
['-'] = '-';
2990 mnemonic_chars
['_'] = '_';
2991 mnemonic_chars
['-'] = '-';
2992 mnemonic_chars
['.'] = '.';
2993 identifier_chars
['_'] = '_';
2994 identifier_chars
['.'] = '.';
2996 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2997 operand_chars
[(unsigned char) *p
] = *p
;
3000 if (flag_code
== CODE_64BIT
)
3002 #if defined (OBJ_COFF) && defined (TE_PE)
3003 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3006 x86_dwarf2_return_column
= 16;
3008 x86_cie_data_alignment
= -8;
3012 x86_dwarf2_return_column
= 8;
3013 x86_cie_data_alignment
= -4;
3018 i386_print_statistics (FILE *file
)
3020 hash_print_statistics (file
, "i386 opcode", op_hash
);
3021 hash_print_statistics (file
, "i386 register", reg_hash
);
3026 /* Debugging routines for md_assemble. */
3027 static void pte (insn_template
*);
3028 static void pt (i386_operand_type
);
3029 static void pe (expressionS
*);
3030 static void ps (symbolS
*);
3033 pi (const char *line
, i386_insn
*x
)
3037 fprintf (stdout
, "%s: template ", line
);
3039 fprintf (stdout
, " address: base %s index %s scale %x\n",
3040 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3041 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3042 x
->log2_scale_factor
);
3043 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3044 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3045 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3046 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3047 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3048 (x
->rex
& REX_W
) != 0,
3049 (x
->rex
& REX_R
) != 0,
3050 (x
->rex
& REX_X
) != 0,
3051 (x
->rex
& REX_B
) != 0);
3052 for (j
= 0; j
< x
->operands
; j
++)
3054 fprintf (stdout
, " #%d: ", j
+ 1);
3056 fprintf (stdout
, "\n");
3057 if (x
->types
[j
].bitfield
.class == Reg
3058 || x
->types
[j
].bitfield
.class == RegMMX
3059 || x
->types
[j
].bitfield
.class == RegSIMD
3060 || x
->types
[j
].bitfield
.class == SReg
3061 || x
->types
[j
].bitfield
.class == RegCR
3062 || x
->types
[j
].bitfield
.class == RegDR
3063 || x
->types
[j
].bitfield
.class == RegTR
)
3064 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3065 if (operand_type_check (x
->types
[j
], imm
))
3067 if (operand_type_check (x
->types
[j
], disp
))
3068 pe (x
->op
[j
].disps
);
3073 pte (insn_template
*t
)
3076 fprintf (stdout
, " %d operands ", t
->operands
);
3077 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3078 if (t
->extension_opcode
!= None
)
3079 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3080 if (t
->opcode_modifier
.d
)
3081 fprintf (stdout
, "D");
3082 if (t
->opcode_modifier
.w
)
3083 fprintf (stdout
, "W");
3084 fprintf (stdout
, "\n");
3085 for (j
= 0; j
< t
->operands
; j
++)
3087 fprintf (stdout
, " #%d type ", j
+ 1);
3088 pt (t
->operand_types
[j
]);
3089 fprintf (stdout
, "\n");
3096 fprintf (stdout
, " operation %d\n", e
->X_op
);
3097 fprintf (stdout
, " add_number %ld (%lx)\n",
3098 (long) e
->X_add_number
, (long) e
->X_add_number
);
3099 if (e
->X_add_symbol
)
3101 fprintf (stdout
, " add_symbol ");
3102 ps (e
->X_add_symbol
);
3103 fprintf (stdout
, "\n");
3107 fprintf (stdout
, " op_symbol ");
3108 ps (e
->X_op_symbol
);
3109 fprintf (stdout
, "\n");
3116 fprintf (stdout
, "%s type %s%s",
3118 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3119 segment_name (S_GET_SEGMENT (s
)));
3122 static struct type_name
3124 i386_operand_type mask
;
3127 const type_names
[] =
3129 { OPERAND_TYPE_REG8
, "r8" },
3130 { OPERAND_TYPE_REG16
, "r16" },
3131 { OPERAND_TYPE_REG32
, "r32" },
3132 { OPERAND_TYPE_REG64
, "r64" },
3133 { OPERAND_TYPE_ACC8
, "acc8" },
3134 { OPERAND_TYPE_ACC16
, "acc16" },
3135 { OPERAND_TYPE_ACC32
, "acc32" },
3136 { OPERAND_TYPE_ACC64
, "acc64" },
3137 { OPERAND_TYPE_IMM8
, "i8" },
3138 { OPERAND_TYPE_IMM8
, "i8s" },
3139 { OPERAND_TYPE_IMM16
, "i16" },
3140 { OPERAND_TYPE_IMM32
, "i32" },
3141 { OPERAND_TYPE_IMM32S
, "i32s" },
3142 { OPERAND_TYPE_IMM64
, "i64" },
3143 { OPERAND_TYPE_IMM1
, "i1" },
3144 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3145 { OPERAND_TYPE_DISP8
, "d8" },
3146 { OPERAND_TYPE_DISP16
, "d16" },
3147 { OPERAND_TYPE_DISP32
, "d32" },
3148 { OPERAND_TYPE_DISP32S
, "d32s" },
3149 { OPERAND_TYPE_DISP64
, "d64" },
3150 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3151 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3152 { OPERAND_TYPE_CONTROL
, "control reg" },
3153 { OPERAND_TYPE_TEST
, "test reg" },
3154 { OPERAND_TYPE_DEBUG
, "debug reg" },
3155 { OPERAND_TYPE_FLOATREG
, "FReg" },
3156 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3157 { OPERAND_TYPE_SREG
, "SReg" },
3158 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3159 { OPERAND_TYPE_REGMMX
, "rMMX" },
3160 { OPERAND_TYPE_REGXMM
, "rXMM" },
3161 { OPERAND_TYPE_REGYMM
, "rYMM" },
3162 { OPERAND_TYPE_REGZMM
, "rZMM" },
3163 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3167 pt (i386_operand_type t
)
3170 i386_operand_type a
;
3172 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3174 a
= operand_type_and (t
, type_names
[j
].mask
);
3175 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3176 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3181 #endif /* DEBUG386 */
3183 static bfd_reloc_code_real_type
3184 reloc (unsigned int size
,
3187 bfd_reloc_code_real_type other
)
3189 if (other
!= NO_RELOC
)
3191 reloc_howto_type
*rel
;
3196 case BFD_RELOC_X86_64_GOT32
:
3197 return BFD_RELOC_X86_64_GOT64
;
3199 case BFD_RELOC_X86_64_GOTPLT64
:
3200 return BFD_RELOC_X86_64_GOTPLT64
;
3202 case BFD_RELOC_X86_64_PLTOFF64
:
3203 return BFD_RELOC_X86_64_PLTOFF64
;
3205 case BFD_RELOC_X86_64_GOTPC32
:
3206 other
= BFD_RELOC_X86_64_GOTPC64
;
3208 case BFD_RELOC_X86_64_GOTPCREL
:
3209 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3211 case BFD_RELOC_X86_64_TPOFF32
:
3212 other
= BFD_RELOC_X86_64_TPOFF64
;
3214 case BFD_RELOC_X86_64_DTPOFF32
:
3215 other
= BFD_RELOC_X86_64_DTPOFF64
;
3221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3222 if (other
== BFD_RELOC_SIZE32
)
3225 other
= BFD_RELOC_SIZE64
;
3228 as_bad (_("there are no pc-relative size relocations"));
3234 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3235 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3238 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3240 as_bad (_("unknown relocation (%u)"), other
);
3241 else if (size
!= bfd_get_reloc_size (rel
))
3242 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3243 bfd_get_reloc_size (rel
),
3245 else if (pcrel
&& !rel
->pc_relative
)
3246 as_bad (_("non-pc-relative relocation for pc-relative field"));
3247 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3249 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3251 as_bad (_("relocated field and relocation type differ in signedness"));
3260 as_bad (_("there are no unsigned pc-relative relocations"));
3263 case 1: return BFD_RELOC_8_PCREL
;
3264 case 2: return BFD_RELOC_16_PCREL
;
3265 case 4: return BFD_RELOC_32_PCREL
;
3266 case 8: return BFD_RELOC_64_PCREL
;
3268 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3275 case 4: return BFD_RELOC_X86_64_32S
;
3280 case 1: return BFD_RELOC_8
;
3281 case 2: return BFD_RELOC_16
;
3282 case 4: return BFD_RELOC_32
;
3283 case 8: return BFD_RELOC_64
;
3285 as_bad (_("cannot do %s %u byte relocation"),
3286 sign
> 0 ? "signed" : "unsigned", size
);
3292 /* Here we decide which fixups can be adjusted to make them relative to
3293 the beginning of the section instead of the symbol. Basically we need
3294 to make sure that the dynamic relocations are done correctly, so in
3295 some cases we force the original symbol to be used. */
3298 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3304 /* Don't adjust pc-relative references to merge sections in 64-bit
3306 if (use_rela_relocations
3307 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3311 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3312 and changed later by validate_fix. */
3313 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3314 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3317 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3318 for size relocations. */
3319 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3320 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3321 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3322 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3323 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3324 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3328 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3329 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3330 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3331 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3332 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3333 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3334 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3343 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3344 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3345 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3346 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3347 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3348 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3349 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3350 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3351 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3358 intel_float_operand (const char *mnemonic
)
3360 /* Note that the value returned is meaningful only for opcodes with (memory)
3361 operands, hence the code here is free to improperly handle opcodes that
3362 have no operands (for better performance and smaller code). */
3364 if (mnemonic
[0] != 'f')
3365 return 0; /* non-math */
3367 switch (mnemonic
[1])
3369 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3370 the fs segment override prefix not currently handled because no
3371 call path can make opcodes without operands get here */
3373 return 2 /* integer op */;
3375 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3376 return 3; /* fldcw/fldenv */
3379 if (mnemonic
[2] != 'o' /* fnop */)
3380 return 3; /* non-waiting control op */
3383 if (mnemonic
[2] == 's')
3384 return 3; /* frstor/frstpm */
3387 if (mnemonic
[2] == 'a')
3388 return 3; /* fsave */
3389 if (mnemonic
[2] == 't')
3391 switch (mnemonic
[3])
3393 case 'c': /* fstcw */
3394 case 'd': /* fstdw */
3395 case 'e': /* fstenv */
3396 case 's': /* fsts[gw] */
3402 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3403 return 0; /* fxsave/fxrstor are not really math ops */
3410 /* Build the VEX prefix. */
3413 build_vex_prefix (const insn_template
*t
)
3415 unsigned int register_specifier
;
3416 unsigned int implied_prefix
;
3417 unsigned int vector_length
;
3420 /* Check register specifier. */
3421 if (i
.vex
.register_specifier
)
3423 register_specifier
=
3424 ~register_number (i
.vex
.register_specifier
) & 0xf;
3425 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3428 register_specifier
= 0xf;
3430 /* Use 2-byte VEX prefix by swapping destination and source operand
3431 if there are more than 1 register operand. */
3432 if (i
.reg_operands
> 1
3433 && i
.vec_encoding
!= vex_encoding_vex3
3434 && i
.dir_encoding
== dir_encoding_default
3435 && i
.operands
== i
.reg_operands
3436 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3437 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3438 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3441 unsigned int xchg
= i
.operands
- 1;
3442 union i386_op temp_op
;
3443 i386_operand_type temp_type
;
3445 temp_type
= i
.types
[xchg
];
3446 i
.types
[xchg
] = i
.types
[0];
3447 i
.types
[0] = temp_type
;
3448 temp_op
= i
.op
[xchg
];
3449 i
.op
[xchg
] = i
.op
[0];
3452 gas_assert (i
.rm
.mode
== 3);
3456 i
.rm
.regmem
= i
.rm
.reg
;
3459 if (i
.tm
.opcode_modifier
.d
)
3460 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3461 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3462 else /* Use the next insn. */
3466 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3467 are no memory operands and at least 3 register ones. */
3468 if (i
.reg_operands
>= 3
3469 && i
.vec_encoding
!= vex_encoding_vex3
3470 && i
.reg_operands
== i
.operands
- i
.imm_operands
3471 && i
.tm
.opcode_modifier
.vex
3472 && i
.tm
.opcode_modifier
.commutative
3473 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3475 && i
.vex
.register_specifier
3476 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3478 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3479 union i386_op temp_op
;
3480 i386_operand_type temp_type
;
3482 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3483 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3484 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3485 &i
.types
[i
.operands
- 3]));
3486 gas_assert (i
.rm
.mode
== 3);
3488 temp_type
= i
.types
[xchg
];
3489 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3490 i
.types
[xchg
+ 1] = temp_type
;
3491 temp_op
= i
.op
[xchg
];
3492 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3493 i
.op
[xchg
+ 1] = temp_op
;
3496 xchg
= i
.rm
.regmem
| 8;
3497 i
.rm
.regmem
= ~register_specifier
& 0xf;
3498 gas_assert (!(i
.rm
.regmem
& 8));
3499 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3500 register_specifier
= ~xchg
& 0xf;
3503 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3504 vector_length
= avxscalar
;
3505 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3511 /* Determine vector length from the last multi-length vector
3514 for (op
= t
->operands
; op
--;)
3515 if (t
->operand_types
[op
].bitfield
.xmmword
3516 && t
->operand_types
[op
].bitfield
.ymmword
3517 && i
.types
[op
].bitfield
.ymmword
)
3524 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE
:
3532 case REPE_PREFIX_OPCODE
:
3535 case REPNE_PREFIX_OPCODE
:
3542 /* Check the REX.W bit and VEXW. */
3543 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3544 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3545 else if (i
.tm
.opcode_modifier
.vexw
)
3546 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3548 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3550 /* Use 2-byte VEX prefix if possible. */
3552 && i
.vec_encoding
!= vex_encoding_vex3
3553 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3554 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3556 /* 2-byte VEX prefix. */
3560 i
.vex
.bytes
[0] = 0xc5;
3562 /* Check the REX.R bit. */
3563 r
= (i
.rex
& REX_R
) ? 0 : 1;
3564 i
.vex
.bytes
[1] = (r
<< 7
3565 | register_specifier
<< 3
3566 | vector_length
<< 2
3571 /* 3-byte VEX prefix. */
3576 switch (i
.tm
.opcode_modifier
.vexopcode
)
3580 i
.vex
.bytes
[0] = 0xc4;
3584 i
.vex
.bytes
[0] = 0xc4;
3588 i
.vex
.bytes
[0] = 0xc4;
3592 i
.vex
.bytes
[0] = 0x8f;
3596 i
.vex
.bytes
[0] = 0x8f;
3600 i
.vex
.bytes
[0] = 0x8f;
3606 /* The high 3 bits of the second VEX byte are 1's compliment
3607 of RXB bits from REX. */
3608 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3610 i
.vex
.bytes
[2] = (w
<< 7
3611 | register_specifier
<< 3
3612 | vector_length
<< 2
3617 static INLINE bfd_boolean
3618 is_evex_encoding (const insn_template
*t
)
3620 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3621 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3622 || t
->opcode_modifier
.sae
;
3625 static INLINE bfd_boolean
3626 is_any_vex_encoding (const insn_template
*t
)
3628 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3629 || is_evex_encoding (t
);
3632 /* Build the EVEX prefix. */
3635 build_evex_prefix (void)
3637 unsigned int register_specifier
;
3638 unsigned int implied_prefix
;
3640 rex_byte vrex_used
= 0;
3642 /* Check register specifier. */
3643 if (i
.vex
.register_specifier
)
3645 gas_assert ((i
.vrex
& REX_X
) == 0);
3647 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3648 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3649 register_specifier
+= 8;
3650 /* The upper 16 registers are encoded in the fourth byte of the
3652 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3653 i
.vex
.bytes
[3] = 0x8;
3654 register_specifier
= ~register_specifier
& 0xf;
3658 register_specifier
= 0xf;
3660 /* Encode upper 16 vector index register in the fourth byte of
3662 if (!(i
.vrex
& REX_X
))
3663 i
.vex
.bytes
[3] = 0x8;
3668 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3673 case DATA_PREFIX_OPCODE
:
3676 case REPE_PREFIX_OPCODE
:
3679 case REPNE_PREFIX_OPCODE
:
3686 /* 4 byte EVEX prefix. */
3688 i
.vex
.bytes
[0] = 0x62;
3691 switch (i
.tm
.opcode_modifier
.vexopcode
)
3707 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3709 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3711 /* The fifth bit of the second EVEX byte is 1's compliment of the
3712 REX_R bit in VREX. */
3713 if (!(i
.vrex
& REX_R
))
3714 i
.vex
.bytes
[1] |= 0x10;
3718 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3720 /* When all operands are registers, the REX_X bit in REX is not
3721 used. We reuse it to encode the upper 16 registers, which is
3722 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3723 as 1's compliment. */
3724 if ((i
.vrex
& REX_B
))
3727 i
.vex
.bytes
[1] &= ~0x40;
3731 /* EVEX instructions shouldn't need the REX prefix. */
3732 i
.vrex
&= ~vrex_used
;
3733 gas_assert (i
.vrex
== 0);
3735 /* Check the REX.W bit and VEXW. */
3736 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3737 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3738 else if (i
.tm
.opcode_modifier
.vexw
)
3739 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3741 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3743 /* Encode the U bit. */
3744 implied_prefix
|= 0x4;
3746 /* The third byte of the EVEX prefix. */
3747 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3749 /* The fourth byte of the EVEX prefix. */
3750 /* The zeroing-masking bit. */
3751 if (i
.mask
&& i
.mask
->zeroing
)
3752 i
.vex
.bytes
[3] |= 0x80;
3754 /* Don't always set the broadcast bit if there is no RC. */
3757 /* Encode the vector length. */
3758 unsigned int vec_length
;
3760 if (!i
.tm
.opcode_modifier
.evex
3761 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3765 /* Determine vector length from the last multi-length vector
3768 for (op
= i
.operands
; op
--;)
3769 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3770 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3771 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3773 if (i
.types
[op
].bitfield
.zmmword
)
3775 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3778 else if (i
.types
[op
].bitfield
.ymmword
)
3780 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3783 else if (i
.types
[op
].bitfield
.xmmword
)
3785 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3788 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3790 switch (i
.broadcast
->bytes
)
3793 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3796 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3799 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3808 if (op
>= MAX_OPERANDS
)
3812 switch (i
.tm
.opcode_modifier
.evex
)
3814 case EVEXLIG
: /* LL' is ignored */
3815 vec_length
= evexlig
<< 5;
3818 vec_length
= 0 << 5;
3821 vec_length
= 1 << 5;
3824 vec_length
= 2 << 5;
3830 i
.vex
.bytes
[3] |= vec_length
;
3831 /* Encode the broadcast bit. */
3833 i
.vex
.bytes
[3] |= 0x10;
3837 if (i
.rounding
->type
!= saeonly
)
3838 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3840 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3843 if (i
.mask
&& i
.mask
->mask
)
3844 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3848 process_immext (void)
3852 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3853 which is coded in the same place as an 8-bit immediate field
3854 would be. Here we fake an 8-bit immediate operand from the
3855 opcode suffix stored in tm.extension_opcode.
3857 AVX instructions also use this encoding, for some of
3858 3 argument instructions. */
3860 gas_assert (i
.imm_operands
<= 1
3862 || (is_any_vex_encoding (&i
.tm
)
3863 && i
.operands
<= 4)));
3865 exp
= &im_expressions
[i
.imm_operands
++];
3866 i
.op
[i
.operands
].imms
= exp
;
3867 i
.types
[i
.operands
] = imm8
;
3869 exp
->X_op
= O_constant
;
3870 exp
->X_add_number
= i
.tm
.extension_opcode
;
3871 i
.tm
.extension_opcode
= None
;
3878 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3883 as_bad (_("invalid instruction `%s' after `%s'"),
3884 i
.tm
.name
, i
.hle_prefix
);
3887 if (i
.prefix
[LOCK_PREFIX
])
3889 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3893 case HLEPrefixRelease
:
3894 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3896 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3900 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3902 as_bad (_("memory destination needed for instruction `%s'"
3903 " after `xrelease'"), i
.tm
.name
);
3910 /* Try the shortest encoding by shortening operand size. */
3913 optimize_encoding (void)
3917 if (optimize_for_space
3918 && i
.reg_operands
== 1
3919 && i
.imm_operands
== 1
3920 && !i
.types
[1].bitfield
.byte
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3923 && ((i
.tm
.base_opcode
== 0xa8
3924 && i
.tm
.extension_opcode
== None
)
3925 || (i
.tm
.base_opcode
== 0xf6
3926 && i
.tm
.extension_opcode
== 0x0)))
3929 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3931 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3932 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3934 i
.types
[1].bitfield
.byte
= 1;
3935 /* Ignore the suffix. */
3937 if (base_regnum
>= 4
3938 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3940 /* Handle SP, BP, SI and DI registers. */
3941 if (i
.types
[1].bitfield
.word
)
3943 else if (i
.types
[1].bitfield
.dword
)
3951 else if (flag_code
== CODE_64BIT
3952 && ((i
.types
[1].bitfield
.qword
3953 && i
.reg_operands
== 1
3954 && i
.imm_operands
== 1
3955 && i
.op
[0].imms
->X_op
== O_constant
3956 && ((i
.tm
.base_opcode
== 0xb8
3957 && i
.tm
.extension_opcode
== None
3958 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3959 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3960 && (((i
.tm
.base_opcode
== 0x24
3961 || i
.tm
.base_opcode
== 0xa8)
3962 && i
.tm
.extension_opcode
== None
)
3963 || (i
.tm
.base_opcode
== 0x80
3964 && i
.tm
.extension_opcode
== 0x4)
3965 || ((i
.tm
.base_opcode
== 0xf6
3966 || (i
.tm
.base_opcode
| 1) == 0xc7)
3967 && i
.tm
.extension_opcode
== 0x0)))
3968 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3969 && i
.tm
.base_opcode
== 0x83
3970 && i
.tm
.extension_opcode
== 0x4)))
3971 || (i
.types
[0].bitfield
.qword
3972 && ((i
.reg_operands
== 2
3973 && i
.op
[0].regs
== i
.op
[1].regs
3974 && ((i
.tm
.base_opcode
== 0x30
3975 || i
.tm
.base_opcode
== 0x28)
3976 && i
.tm
.extension_opcode
== None
))
3977 || (i
.reg_operands
== 1
3979 && i
.tm
.base_opcode
== 0x30
3980 && i
.tm
.extension_opcode
== None
)))))
3983 andq $imm31, %r64 -> andl $imm31, %r32
3984 andq $imm7, %r64 -> andl $imm7, %r32
3985 testq $imm31, %r64 -> testl $imm31, %r32
3986 xorq %r64, %r64 -> xorl %r32, %r32
3987 subq %r64, %r64 -> subl %r32, %r32
3988 movq $imm31, %r64 -> movl $imm31, %r32
3989 movq $imm32, %r64 -> movl $imm32, %r32
3991 i
.tm
.opcode_modifier
.norex64
= 1;
3992 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
3995 movq $imm31, %r64 -> movl $imm31, %r32
3996 movq $imm32, %r64 -> movl $imm32, %r32
3998 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3999 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4000 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4001 i
.types
[0].bitfield
.imm32
= 1;
4002 i
.types
[0].bitfield
.imm32s
= 0;
4003 i
.types
[0].bitfield
.imm64
= 0;
4004 i
.types
[1].bitfield
.dword
= 1;
4005 i
.types
[1].bitfield
.qword
= 0;
4006 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4009 movq $imm31, %r64 -> movl $imm31, %r32
4011 i
.tm
.base_opcode
= 0xb8;
4012 i
.tm
.extension_opcode
= None
;
4013 i
.tm
.opcode_modifier
.w
= 0;
4014 i
.tm
.opcode_modifier
.shortform
= 1;
4015 i
.tm
.opcode_modifier
.modrm
= 0;
4019 else if (optimize
> 1
4020 && !optimize_for_space
4021 && i
.reg_operands
== 2
4022 && i
.op
[0].regs
== i
.op
[1].regs
4023 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4024 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4025 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4028 andb %rN, %rN -> testb %rN, %rN
4029 andw %rN, %rN -> testw %rN, %rN
4030 andq %rN, %rN -> testq %rN, %rN
4031 orb %rN, %rN -> testb %rN, %rN
4032 orw %rN, %rN -> testw %rN, %rN
4033 orq %rN, %rN -> testq %rN, %rN
4035 and outside of 64-bit mode
4037 andl %rN, %rN -> testl %rN, %rN
4038 orl %rN, %rN -> testl %rN, %rN
4040 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4042 else if (i
.reg_operands
== 3
4043 && i
.op
[0].regs
== i
.op
[1].regs
4044 && !i
.types
[2].bitfield
.xmmword
4045 && (i
.tm
.opcode_modifier
.vex
4046 || ((!i
.mask
|| i
.mask
->zeroing
)
4048 && is_evex_encoding (&i
.tm
)
4049 && (i
.vec_encoding
!= vex_encoding_evex
4050 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4051 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4052 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4053 && i
.types
[2].bitfield
.ymmword
))))
4054 && ((i
.tm
.base_opcode
== 0x55
4055 || i
.tm
.base_opcode
== 0x6655
4056 || i
.tm
.base_opcode
== 0x66df
4057 || i
.tm
.base_opcode
== 0x57
4058 || i
.tm
.base_opcode
== 0x6657
4059 || i
.tm
.base_opcode
== 0x66ef
4060 || i
.tm
.base_opcode
== 0x66f8
4061 || i
.tm
.base_opcode
== 0x66f9
4062 || i
.tm
.base_opcode
== 0x66fa
4063 || i
.tm
.base_opcode
== 0x66fb
4064 || i
.tm
.base_opcode
== 0x42
4065 || i
.tm
.base_opcode
== 0x6642
4066 || i
.tm
.base_opcode
== 0x47
4067 || i
.tm
.base_opcode
== 0x6647)
4068 && i
.tm
.extension_opcode
== None
))
4071 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4073 EVEX VOP %zmmM, %zmmM, %zmmN
4074 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4075 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4076 EVEX VOP %ymmM, %ymmM, %ymmN
4077 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4078 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4079 VEX VOP %ymmM, %ymmM, %ymmN
4080 -> VEX VOP %xmmM, %xmmM, %xmmN
4081 VOP, one of vpandn and vpxor:
4082 VEX VOP %ymmM, %ymmM, %ymmN
4083 -> VEX VOP %xmmM, %xmmM, %xmmN
4084 VOP, one of vpandnd and vpandnq:
4085 EVEX VOP %zmmM, %zmmM, %zmmN
4086 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4087 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4088 EVEX VOP %ymmM, %ymmM, %ymmN
4089 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4090 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4091 VOP, one of vpxord and vpxorq:
4092 EVEX VOP %zmmM, %zmmM, %zmmN
4093 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4094 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4095 EVEX VOP %ymmM, %ymmM, %ymmN
4096 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4097 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4098 VOP, one of kxord and kxorq:
4099 VEX VOP %kM, %kM, %kN
4100 -> VEX kxorw %kM, %kM, %kN
4101 VOP, one of kandnd and kandnq:
4102 VEX VOP %kM, %kM, %kN
4103 -> VEX kandnw %kM, %kM, %kN
4105 if (is_evex_encoding (&i
.tm
))
4107 if (i
.vec_encoding
!= vex_encoding_evex
)
4109 i
.tm
.opcode_modifier
.vex
= VEX128
;
4110 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4111 i
.tm
.opcode_modifier
.evex
= 0;
4113 else if (optimize
> 1)
4114 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4118 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4120 i
.tm
.base_opcode
&= 0xff;
4121 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4124 i
.tm
.opcode_modifier
.vex
= VEX128
;
4126 if (i
.tm
.opcode_modifier
.vex
)
4127 for (j
= 0; j
< 3; j
++)
4129 i
.types
[j
].bitfield
.xmmword
= 1;
4130 i
.types
[j
].bitfield
.ymmword
= 0;
4133 else if (i
.vec_encoding
!= vex_encoding_evex
4134 && !i
.types
[0].bitfield
.zmmword
4135 && !i
.types
[1].bitfield
.zmmword
4138 && is_evex_encoding (&i
.tm
)
4139 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4140 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4141 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4142 || (i
.tm
.base_opcode
& ~4) == 0x66db
4143 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4144 && i
.tm
.extension_opcode
== None
)
4147 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4148 vmovdqu32 and vmovdqu64:
4149 EVEX VOP %xmmM, %xmmN
4150 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4151 EVEX VOP %ymmM, %ymmN
4152 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4154 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4156 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4158 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4160 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4161 VOP, one of vpand, vpandn, vpor, vpxor:
4162 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4163 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4164 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4165 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4166 EVEX VOP{d,q} mem, %xmmM, %xmmN
4167 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4168 EVEX VOP{d,q} mem, %ymmM, %ymmN
4169 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4171 for (j
= 0; j
< i
.operands
; j
++)
4172 if (operand_type_check (i
.types
[j
], disp
)
4173 && i
.op
[j
].disps
->X_op
== O_constant
)
4175 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4176 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4177 bytes, we choose EVEX Disp8 over VEX Disp32. */
4178 int evex_disp8
, vex_disp8
;
4179 unsigned int memshift
= i
.memshift
;
4180 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4182 evex_disp8
= fits_in_disp8 (n
);
4184 vex_disp8
= fits_in_disp8 (n
);
4185 if (evex_disp8
!= vex_disp8
)
4187 i
.memshift
= memshift
;
4191 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4194 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4195 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4196 i
.tm
.opcode_modifier
.vex
4197 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4198 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4199 /* VPAND, VPOR, and VPXOR are commutative. */
4200 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4201 i
.tm
.opcode_modifier
.commutative
= 1;
4202 i
.tm
.opcode_modifier
.evex
= 0;
4203 i
.tm
.opcode_modifier
.masking
= 0;
4204 i
.tm
.opcode_modifier
.broadcast
= 0;
4205 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4208 i
.types
[j
].bitfield
.disp8
4209 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4213 /* This is the guts of the machine-dependent assembler. LINE points to a
4214 machine dependent instruction. This function is supposed to emit
4215 the frags/bytes it assembles to. */
4218 md_assemble (char *line
)
4221 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4222 const insn_template
*t
;
4224 /* Initialize globals. */
4225 memset (&i
, '\0', sizeof (i
));
4226 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4227 i
.reloc
[j
] = NO_RELOC
;
4228 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4229 memset (im_expressions
, '\0', sizeof (im_expressions
));
4230 save_stack_p
= save_stack
;
4232 /* First parse an instruction mnemonic & call i386_operand for the operands.
4233 We assume that the scrubber has arranged it so that line[0] is the valid
4234 start of a (possibly prefixed) mnemonic. */
4236 line
= parse_insn (line
, mnemonic
);
4239 mnem_suffix
= i
.suffix
;
4241 line
= parse_operands (line
, mnemonic
);
4243 xfree (i
.memop1_string
);
4244 i
.memop1_string
= NULL
;
4248 /* Now we've parsed the mnemonic into a set of templates, and have the
4249 operands at hand. */
4251 /* All intel opcodes have reversed operands except for "bound" and
4252 "enter". We also don't reverse intersegment "jmp" and "call"
4253 instructions with 2 immediate operands so that the immediate segment
4254 precedes the offset, as it does when in AT&T mode. */
4257 && (strcmp (mnemonic
, "bound") != 0)
4258 && (strcmp (mnemonic
, "invlpga") != 0)
4259 && !(operand_type_check (i
.types
[0], imm
)
4260 && operand_type_check (i
.types
[1], imm
)))
4263 /* The order of the immediates should be reversed
4264 for 2 immediates extrq and insertq instructions */
4265 if (i
.imm_operands
== 2
4266 && (strcmp (mnemonic
, "extrq") == 0
4267 || strcmp (mnemonic
, "insertq") == 0))
4268 swap_2_operands (0, 1);
4273 /* Don't optimize displacement for movabs since it only takes 64bit
4276 && i
.disp_encoding
!= disp_encoding_32bit
4277 && (flag_code
!= CODE_64BIT
4278 || strcmp (mnemonic
, "movabs") != 0))
4281 /* Next, we find a template that matches the given insn,
4282 making sure the overlap of the given operands types is consistent
4283 with the template operand types. */
4285 if (!(t
= match_template (mnem_suffix
)))
4288 if (sse_check
!= check_none
4289 && !i
.tm
.opcode_modifier
.noavx
4290 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4291 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4292 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4293 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4294 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4295 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4296 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4297 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4298 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4299 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4301 (sse_check
== check_warning
4303 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4306 /* Zap movzx and movsx suffix. The suffix has been set from
4307 "word ptr" or "byte ptr" on the source operand in Intel syntax
4308 or extracted from mnemonic in AT&T syntax. But we'll use
4309 the destination register to choose the suffix for encoding. */
4310 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4312 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4313 there is no suffix, the default will be byte extension. */
4314 if (i
.reg_operands
!= 2
4317 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4322 if (i
.tm
.opcode_modifier
.fwait
)
4323 if (!add_prefix (FWAIT_OPCODE
))
4326 /* Check if REP prefix is OK. */
4327 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4329 as_bad (_("invalid instruction `%s' after `%s'"),
4330 i
.tm
.name
, i
.rep_prefix
);
4334 /* Check for lock without a lockable instruction. Destination operand
4335 must be memory unless it is xchg (0x86). */
4336 if (i
.prefix
[LOCK_PREFIX
]
4337 && (!i
.tm
.opcode_modifier
.islockable
4338 || i
.mem_operands
== 0
4339 || (i
.tm
.base_opcode
!= 0x86
4340 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4342 as_bad (_("expecting lockable instruction after `lock'"));
4346 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4347 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4349 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4353 /* Check if HLE prefix is OK. */
4354 if (i
.hle_prefix
&& !check_hle ())
4357 /* Check BND prefix. */
4358 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4359 as_bad (_("expecting valid branch instruction after `bnd'"));
4361 /* Check NOTRACK prefix. */
4362 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4363 as_bad (_("expecting indirect branch instruction after `notrack'"));
4365 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4367 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4368 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4369 else if (flag_code
!= CODE_16BIT
4370 ? i
.prefix
[ADDR_PREFIX
]
4371 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4372 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4375 /* Insert BND prefix. */
4376 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4378 if (!i
.prefix
[BND_PREFIX
])
4379 add_prefix (BND_PREFIX_OPCODE
);
4380 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4382 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4383 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4387 /* Check string instruction segment overrides. */
4388 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4390 gas_assert (i
.mem_operands
);
4391 if (!check_string ())
4393 i
.disp_operands
= 0;
4396 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4397 optimize_encoding ();
4399 if (!process_suffix ())
4402 /* Update operand types. */
4403 for (j
= 0; j
< i
.operands
; j
++)
4404 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4406 /* Make still unresolved immediate matches conform to size of immediate
4407 given in i.suffix. */
4408 if (!finalize_imm ())
4411 if (i
.types
[0].bitfield
.imm1
)
4412 i
.imm_operands
= 0; /* kludge for shift insns. */
4414 /* We only need to check those implicit registers for instructions
4415 with 3 operands or less. */
4416 if (i
.operands
<= 3)
4417 for (j
= 0; j
< i
.operands
; j
++)
4418 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4419 && !i
.types
[j
].bitfield
.xmmword
)
4422 /* ImmExt should be processed after SSE2AVX. */
4423 if (!i
.tm
.opcode_modifier
.sse2avx
4424 && i
.tm
.opcode_modifier
.immext
)
4427 /* For insns with operands there are more diddles to do to the opcode. */
4430 if (!process_operands ())
4433 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4435 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4436 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4439 if (is_any_vex_encoding (&i
.tm
))
4441 if (!cpu_arch_flags
.bitfield
.cpui286
)
4443 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4448 if (i
.tm
.opcode_modifier
.vex
)
4449 build_vex_prefix (t
);
4451 build_evex_prefix ();
4454 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4455 instructions may define INT_OPCODE as well, so avoid this corner
4456 case for those instructions that use MODRM. */
4457 if (i
.tm
.base_opcode
== INT_OPCODE
4458 && !i
.tm
.opcode_modifier
.modrm
4459 && i
.op
[0].imms
->X_add_number
== 3)
4461 i
.tm
.base_opcode
= INT3_OPCODE
;
4465 if ((i
.tm
.opcode_modifier
.jump
4466 || i
.tm
.opcode_modifier
.jumpbyte
4467 || i
.tm
.opcode_modifier
.jumpdword
)
4468 && i
.op
[0].disps
->X_op
== O_constant
)
4470 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4471 the absolute address given by the constant. Since ix86 jumps and
4472 calls are pc relative, we need to generate a reloc. */
4473 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4474 i
.op
[0].disps
->X_op
= O_symbol
;
4477 if (i
.tm
.opcode_modifier
.rex64
)
4480 /* For 8 bit registers we need an empty rex prefix. Also if the
4481 instruction already has a prefix, we need to convert old
4482 registers to new ones. */
4484 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4485 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4486 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4487 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4488 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4489 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4494 i
.rex
|= REX_OPCODE
;
4495 for (x
= 0; x
< 2; x
++)
4497 /* Look for 8 bit operand that uses old registers. */
4498 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4499 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4501 /* In case it is "hi" register, give up. */
4502 if (i
.op
[x
].regs
->reg_num
> 3)
4503 as_bad (_("can't encode register '%s%s' in an "
4504 "instruction requiring REX prefix."),
4505 register_prefix
, i
.op
[x
].regs
->reg_name
);
4507 /* Otherwise it is equivalent to the extended register.
4508 Since the encoding doesn't change this is merely
4509 cosmetic cleanup for debug output. */
4511 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4516 if (i
.rex
== 0 && i
.rex_encoding
)
4518 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4519 that uses legacy register. If it is "hi" register, don't add
4520 the REX_OPCODE byte. */
4522 for (x
= 0; x
< 2; x
++)
4523 if (i
.types
[x
].bitfield
.class == Reg
4524 && i
.types
[x
].bitfield
.byte
4525 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4526 && i
.op
[x
].regs
->reg_num
> 3)
4528 i
.rex_encoding
= FALSE
;
4537 add_prefix (REX_OPCODE
| i
.rex
);
4539 /* We are ready to output the insn. */
4544 parse_insn (char *line
, char *mnemonic
)
4547 char *token_start
= l
;
4550 const insn_template
*t
;
4556 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4561 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4563 as_bad (_("no such instruction: `%s'"), token_start
);
4568 if (!is_space_char (*l
)
4569 && *l
!= END_OF_INSN
4571 || (*l
!= PREFIX_SEPARATOR
4574 as_bad (_("invalid character %s in mnemonic"),
4575 output_invalid (*l
));
4578 if (token_start
== l
)
4580 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4581 as_bad (_("expecting prefix; got nothing"));
4583 as_bad (_("expecting mnemonic; got nothing"));
4587 /* Look up instruction (or prefix) via hash table. */
4588 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4590 if (*l
!= END_OF_INSN
4591 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4592 && current_templates
4593 && current_templates
->start
->opcode_modifier
.isprefix
)
4595 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4597 as_bad ((flag_code
!= CODE_64BIT
4598 ? _("`%s' is only supported in 64-bit mode")
4599 : _("`%s' is not supported in 64-bit mode")),
4600 current_templates
->start
->name
);
4603 /* If we are in 16-bit mode, do not allow addr16 or data16.
4604 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4605 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4606 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4607 && flag_code
!= CODE_64BIT
4608 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4609 ^ (flag_code
== CODE_16BIT
)))
4611 as_bad (_("redundant %s prefix"),
4612 current_templates
->start
->name
);
4615 if (current_templates
->start
->opcode_length
== 0)
4617 /* Handle pseudo prefixes. */
4618 switch (current_templates
->start
->base_opcode
)
4622 i
.disp_encoding
= disp_encoding_8bit
;
4626 i
.disp_encoding
= disp_encoding_32bit
;
4630 i
.dir_encoding
= dir_encoding_load
;
4634 i
.dir_encoding
= dir_encoding_store
;
4638 i
.vec_encoding
= vex_encoding_vex2
;
4642 i
.vec_encoding
= vex_encoding_vex3
;
4646 i
.vec_encoding
= vex_encoding_evex
;
4650 i
.rex_encoding
= TRUE
;
4654 i
.no_optimize
= TRUE
;
4662 /* Add prefix, checking for repeated prefixes. */
4663 switch (add_prefix (current_templates
->start
->base_opcode
))
4668 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4669 i
.notrack_prefix
= current_templates
->start
->name
;
4672 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4673 i
.hle_prefix
= current_templates
->start
->name
;
4674 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4675 i
.bnd_prefix
= current_templates
->start
->name
;
4677 i
.rep_prefix
= current_templates
->start
->name
;
4683 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4690 if (!current_templates
)
4692 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4693 Check if we should swap operand or force 32bit displacement in
4695 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4696 i
.dir_encoding
= dir_encoding_swap
;
4697 else if (mnem_p
- 3 == dot_p
4700 i
.disp_encoding
= disp_encoding_8bit
;
4701 else if (mnem_p
- 4 == dot_p
4705 i
.disp_encoding
= disp_encoding_32bit
;
4710 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4713 if (!current_templates
)
4716 if (mnem_p
> mnemonic
)
4718 /* See if we can get a match by trimming off a suffix. */
4721 case WORD_MNEM_SUFFIX
:
4722 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4723 i
.suffix
= SHORT_MNEM_SUFFIX
;
4726 case BYTE_MNEM_SUFFIX
:
4727 case QWORD_MNEM_SUFFIX
:
4728 i
.suffix
= mnem_p
[-1];
4730 current_templates
= (const templates
*) hash_find (op_hash
,
4733 case SHORT_MNEM_SUFFIX
:
4734 case LONG_MNEM_SUFFIX
:
4737 i
.suffix
= mnem_p
[-1];
4739 current_templates
= (const templates
*) hash_find (op_hash
,
4748 if (intel_float_operand (mnemonic
) == 1)
4749 i
.suffix
= SHORT_MNEM_SUFFIX
;
4751 i
.suffix
= LONG_MNEM_SUFFIX
;
4753 current_templates
= (const templates
*) hash_find (op_hash
,
4760 if (!current_templates
)
4762 as_bad (_("no such instruction: `%s'"), token_start
);
4767 if (current_templates
->start
->opcode_modifier
.jump
4768 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4770 /* Check for a branch hint. We allow ",pt" and ",pn" for
4771 predict taken and predict not taken respectively.
4772 I'm not sure that branch hints actually do anything on loop
4773 and jcxz insns (JumpByte) for current Pentium4 chips. They
4774 may work in the future and it doesn't hurt to accept them
4776 if (l
[0] == ',' && l
[1] == 'p')
4780 if (!add_prefix (DS_PREFIX_OPCODE
))
4784 else if (l
[2] == 'n')
4786 if (!add_prefix (CS_PREFIX_OPCODE
))
4792 /* Any other comma loses. */
4795 as_bad (_("invalid character %s in mnemonic"),
4796 output_invalid (*l
));
4800 /* Check if instruction is supported on specified architecture. */
4802 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4804 supported
|= cpu_flags_match (t
);
4805 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4807 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4808 as_warn (_("use .code16 to ensure correct addressing mode"));
4814 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4815 as_bad (flag_code
== CODE_64BIT
4816 ? _("`%s' is not supported in 64-bit mode")
4817 : _("`%s' is only supported in 64-bit mode"),
4818 current_templates
->start
->name
);
4820 as_bad (_("`%s' is not supported on `%s%s'"),
4821 current_templates
->start
->name
,
4822 cpu_arch_name
? cpu_arch_name
: default_arch
,
4823 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4829 parse_operands (char *l
, const char *mnemonic
)
4833 /* 1 if operand is pending after ','. */
4834 unsigned int expecting_operand
= 0;
4836 /* Non-zero if operand parens not balanced. */
4837 unsigned int paren_not_balanced
;
4839 while (*l
!= END_OF_INSN
)
4841 /* Skip optional white space before operand. */
4842 if (is_space_char (*l
))
4844 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4846 as_bad (_("invalid character %s before operand %d"),
4847 output_invalid (*l
),
4851 token_start
= l
; /* After white space. */
4852 paren_not_balanced
= 0;
4853 while (paren_not_balanced
|| *l
!= ',')
4855 if (*l
== END_OF_INSN
)
4857 if (paren_not_balanced
)
4860 as_bad (_("unbalanced parenthesis in operand %d."),
4863 as_bad (_("unbalanced brackets in operand %d."),
4868 break; /* we are done */
4870 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4872 as_bad (_("invalid character %s in operand %d"),
4873 output_invalid (*l
),
4880 ++paren_not_balanced
;
4882 --paren_not_balanced
;
4887 ++paren_not_balanced
;
4889 --paren_not_balanced
;
4893 if (l
!= token_start
)
4894 { /* Yes, we've read in another operand. */
4895 unsigned int operand_ok
;
4896 this_operand
= i
.operands
++;
4897 if (i
.operands
> MAX_OPERANDS
)
4899 as_bad (_("spurious operands; (%d operands/instruction max)"),
4903 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4904 /* Now parse operand adding info to 'i' as we go along. */
4905 END_STRING_AND_SAVE (l
);
4907 if (i
.mem_operands
> 1)
4909 as_bad (_("too many memory references for `%s'"),
4916 i386_intel_operand (token_start
,
4917 intel_float_operand (mnemonic
));
4919 operand_ok
= i386_att_operand (token_start
);
4921 RESTORE_END_STRING (l
);
4927 if (expecting_operand
)
4929 expecting_operand_after_comma
:
4930 as_bad (_("expecting operand after ','; got nothing"));
4935 as_bad (_("expecting operand before ','; got nothing"));
4940 /* Now *l must be either ',' or END_OF_INSN. */
4943 if (*++l
== END_OF_INSN
)
4945 /* Just skip it, if it's \n complain. */
4946 goto expecting_operand_after_comma
;
4948 expecting_operand
= 1;
4955 swap_2_operands (int xchg1
, int xchg2
)
4957 union i386_op temp_op
;
4958 i386_operand_type temp_type
;
4959 unsigned int temp_flags
;
4960 enum bfd_reloc_code_real temp_reloc
;
4962 temp_type
= i
.types
[xchg2
];
4963 i
.types
[xchg2
] = i
.types
[xchg1
];
4964 i
.types
[xchg1
] = temp_type
;
4966 temp_flags
= i
.flags
[xchg2
];
4967 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4968 i
.flags
[xchg1
] = temp_flags
;
4970 temp_op
= i
.op
[xchg2
];
4971 i
.op
[xchg2
] = i
.op
[xchg1
];
4972 i
.op
[xchg1
] = temp_op
;
4974 temp_reloc
= i
.reloc
[xchg2
];
4975 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4976 i
.reloc
[xchg1
] = temp_reloc
;
4980 if (i
.mask
->operand
== xchg1
)
4981 i
.mask
->operand
= xchg2
;
4982 else if (i
.mask
->operand
== xchg2
)
4983 i
.mask
->operand
= xchg1
;
4987 if (i
.broadcast
->operand
== xchg1
)
4988 i
.broadcast
->operand
= xchg2
;
4989 else if (i
.broadcast
->operand
== xchg2
)
4990 i
.broadcast
->operand
= xchg1
;
4994 if (i
.rounding
->operand
== xchg1
)
4995 i
.rounding
->operand
= xchg2
;
4996 else if (i
.rounding
->operand
== xchg2
)
4997 i
.rounding
->operand
= xchg1
;
5002 swap_operands (void)
5008 swap_2_operands (1, i
.operands
- 2);
5012 swap_2_operands (0, i
.operands
- 1);
5018 if (i
.mem_operands
== 2)
5020 const seg_entry
*temp_seg
;
5021 temp_seg
= i
.seg
[0];
5022 i
.seg
[0] = i
.seg
[1];
5023 i
.seg
[1] = temp_seg
;
5027 /* Try to ensure constant immediates are represented in the smallest
5032 char guess_suffix
= 0;
5036 guess_suffix
= i
.suffix
;
5037 else if (i
.reg_operands
)
5039 /* Figure out a suffix from the last register operand specified.
5040 We can't do this properly yet, i.e. excluding special register
5041 instances, but the following works for instructions with
5042 immediates. In any case, we can't set i.suffix yet. */
5043 for (op
= i
.operands
; --op
>= 0;)
5044 if (i
.types
[op
].bitfield
.class != Reg
)
5046 else if (i
.types
[op
].bitfield
.byte
)
5048 guess_suffix
= BYTE_MNEM_SUFFIX
;
5051 else if (i
.types
[op
].bitfield
.word
)
5053 guess_suffix
= WORD_MNEM_SUFFIX
;
5056 else if (i
.types
[op
].bitfield
.dword
)
5058 guess_suffix
= LONG_MNEM_SUFFIX
;
5061 else if (i
.types
[op
].bitfield
.qword
)
5063 guess_suffix
= QWORD_MNEM_SUFFIX
;
5067 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5068 guess_suffix
= WORD_MNEM_SUFFIX
;
5070 for (op
= i
.operands
; --op
>= 0;)
5071 if (operand_type_check (i
.types
[op
], imm
))
5073 switch (i
.op
[op
].imms
->X_op
)
5076 /* If a suffix is given, this operand may be shortened. */
5077 switch (guess_suffix
)
5079 case LONG_MNEM_SUFFIX
:
5080 i
.types
[op
].bitfield
.imm32
= 1;
5081 i
.types
[op
].bitfield
.imm64
= 1;
5083 case WORD_MNEM_SUFFIX
:
5084 i
.types
[op
].bitfield
.imm16
= 1;
5085 i
.types
[op
].bitfield
.imm32
= 1;
5086 i
.types
[op
].bitfield
.imm32s
= 1;
5087 i
.types
[op
].bitfield
.imm64
= 1;
5089 case BYTE_MNEM_SUFFIX
:
5090 i
.types
[op
].bitfield
.imm8
= 1;
5091 i
.types
[op
].bitfield
.imm8s
= 1;
5092 i
.types
[op
].bitfield
.imm16
= 1;
5093 i
.types
[op
].bitfield
.imm32
= 1;
5094 i
.types
[op
].bitfield
.imm32s
= 1;
5095 i
.types
[op
].bitfield
.imm64
= 1;
5099 /* If this operand is at most 16 bits, convert it
5100 to a signed 16 bit number before trying to see
5101 whether it will fit in an even smaller size.
5102 This allows a 16-bit operand such as $0xffe0 to
5103 be recognised as within Imm8S range. */
5104 if ((i
.types
[op
].bitfield
.imm16
)
5105 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5107 i
.op
[op
].imms
->X_add_number
=
5108 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5111 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5112 if ((i
.types
[op
].bitfield
.imm32
)
5113 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5116 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5117 ^ ((offsetT
) 1 << 31))
5118 - ((offsetT
) 1 << 31));
5122 = operand_type_or (i
.types
[op
],
5123 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5125 /* We must avoid matching of Imm32 templates when 64bit
5126 only immediate is available. */
5127 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5128 i
.types
[op
].bitfield
.imm32
= 0;
5135 /* Symbols and expressions. */
5137 /* Convert symbolic operand to proper sizes for matching, but don't
5138 prevent matching a set of insns that only supports sizes other
5139 than those matching the insn suffix. */
5141 i386_operand_type mask
, allowed
;
5142 const insn_template
*t
;
5144 operand_type_set (&mask
, 0);
5145 operand_type_set (&allowed
, 0);
5147 for (t
= current_templates
->start
;
5148 t
< current_templates
->end
;
5151 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5152 allowed
= operand_type_and (allowed
, anyimm
);
5154 switch (guess_suffix
)
5156 case QWORD_MNEM_SUFFIX
:
5157 mask
.bitfield
.imm64
= 1;
5158 mask
.bitfield
.imm32s
= 1;
5160 case LONG_MNEM_SUFFIX
:
5161 mask
.bitfield
.imm32
= 1;
5163 case WORD_MNEM_SUFFIX
:
5164 mask
.bitfield
.imm16
= 1;
5166 case BYTE_MNEM_SUFFIX
:
5167 mask
.bitfield
.imm8
= 1;
5172 allowed
= operand_type_and (mask
, allowed
);
5173 if (!operand_type_all_zero (&allowed
))
5174 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5181 /* Try to use the smallest displacement type too. */
5183 optimize_disp (void)
5187 for (op
= i
.operands
; --op
>= 0;)
5188 if (operand_type_check (i
.types
[op
], disp
))
5190 if (i
.op
[op
].disps
->X_op
== O_constant
)
5192 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5194 if (i
.types
[op
].bitfield
.disp16
5195 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5197 /* If this operand is at most 16 bits, convert
5198 to a signed 16 bit number and don't use 64bit
5200 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5201 i
.types
[op
].bitfield
.disp64
= 0;
5204 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5205 if (i
.types
[op
].bitfield
.disp32
5206 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5208 /* If this operand is at most 32 bits, convert
5209 to a signed 32 bit number and don't use 64bit
5211 op_disp
&= (((offsetT
) 2 << 31) - 1);
5212 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5213 i
.types
[op
].bitfield
.disp64
= 0;
5216 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5218 i
.types
[op
].bitfield
.disp8
= 0;
5219 i
.types
[op
].bitfield
.disp16
= 0;
5220 i
.types
[op
].bitfield
.disp32
= 0;
5221 i
.types
[op
].bitfield
.disp32s
= 0;
5222 i
.types
[op
].bitfield
.disp64
= 0;
5226 else if (flag_code
== CODE_64BIT
)
5228 if (fits_in_signed_long (op_disp
))
5230 i
.types
[op
].bitfield
.disp64
= 0;
5231 i
.types
[op
].bitfield
.disp32s
= 1;
5233 if (i
.prefix
[ADDR_PREFIX
]
5234 && fits_in_unsigned_long (op_disp
))
5235 i
.types
[op
].bitfield
.disp32
= 1;
5237 if ((i
.types
[op
].bitfield
.disp32
5238 || i
.types
[op
].bitfield
.disp32s
5239 || i
.types
[op
].bitfield
.disp16
)
5240 && fits_in_disp8 (op_disp
))
5241 i
.types
[op
].bitfield
.disp8
= 1;
5243 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5244 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5246 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5247 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5248 i
.types
[op
].bitfield
.disp8
= 0;
5249 i
.types
[op
].bitfield
.disp16
= 0;
5250 i
.types
[op
].bitfield
.disp32
= 0;
5251 i
.types
[op
].bitfield
.disp32s
= 0;
5252 i
.types
[op
].bitfield
.disp64
= 0;
5255 /* We only support 64bit displacement on constants. */
5256 i
.types
[op
].bitfield
.disp64
= 0;
5260 /* Return 1 if there is a match in broadcast bytes between operand
5261 GIVEN and instruction template T. */
5264 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5266 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5267 && i
.types
[given
].bitfield
.byte
)
5268 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5269 && i
.types
[given
].bitfield
.word
)
5270 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5271 && i
.types
[given
].bitfield
.dword
)
5272 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5273 && i
.types
[given
].bitfield
.qword
));
5276 /* Check if operands are valid for the instruction. */
5279 check_VecOperands (const insn_template
*t
)
5283 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5285 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5286 any one operand are implicity requiring AVX512VL support if the actual
5287 operand size is YMMword or XMMword. Since this function runs after
5288 template matching, there's no need to check for YMMword/XMMword in
5290 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5291 if (!cpu_flags_all_zero (&cpu
)
5292 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5293 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5295 for (op
= 0; op
< t
->operands
; ++op
)
5297 if (t
->operand_types
[op
].bitfield
.zmmword
5298 && (i
.types
[op
].bitfield
.ymmword
5299 || i
.types
[op
].bitfield
.xmmword
))
5301 i
.error
= unsupported
;
5307 /* Without VSIB byte, we can't have a vector register for index. */
5308 if (!t
->opcode_modifier
.vecsib
5310 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5311 || i
.index_reg
->reg_type
.bitfield
.ymmword
5312 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5314 i
.error
= unsupported_vector_index_register
;
5318 /* Check if default mask is allowed. */
5319 if (t
->opcode_modifier
.nodefmask
5320 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5322 i
.error
= no_default_mask
;
5326 /* For VSIB byte, we need a vector register for index, and all vector
5327 registers must be distinct. */
5328 if (t
->opcode_modifier
.vecsib
)
5331 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5332 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5333 || (t
->opcode_modifier
.vecsib
== VecSIB256
5334 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5335 || (t
->opcode_modifier
.vecsib
== VecSIB512
5336 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5338 i
.error
= invalid_vsib_address
;
5342 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5343 if (i
.reg_operands
== 2 && !i
.mask
)
5345 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5346 gas_assert (i
.types
[0].bitfield
.xmmword
5347 || i
.types
[0].bitfield
.ymmword
);
5348 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5349 gas_assert (i
.types
[2].bitfield
.xmmword
5350 || i
.types
[2].bitfield
.ymmword
);
5351 if (operand_check
== check_none
)
5353 if (register_number (i
.op
[0].regs
)
5354 != register_number (i
.index_reg
)
5355 && register_number (i
.op
[2].regs
)
5356 != register_number (i
.index_reg
)
5357 && register_number (i
.op
[0].regs
)
5358 != register_number (i
.op
[2].regs
))
5360 if (operand_check
== check_error
)
5362 i
.error
= invalid_vector_register_set
;
5365 as_warn (_("mask, index, and destination registers should be distinct"));
5367 else if (i
.reg_operands
== 1 && i
.mask
)
5369 if (i
.types
[1].bitfield
.class == RegSIMD
5370 && (i
.types
[1].bitfield
.xmmword
5371 || i
.types
[1].bitfield
.ymmword
5372 || i
.types
[1].bitfield
.zmmword
)
5373 && (register_number (i
.op
[1].regs
)
5374 == register_number (i
.index_reg
)))
5376 if (operand_check
== check_error
)
5378 i
.error
= invalid_vector_register_set
;
5381 if (operand_check
!= check_none
)
5382 as_warn (_("index and destination registers should be distinct"));
5387 /* Check if broadcast is supported by the instruction and is applied
5388 to the memory operand. */
5391 i386_operand_type type
, overlap
;
5393 /* Check if specified broadcast is supported in this instruction,
5394 and its broadcast bytes match the memory operand. */
5395 op
= i
.broadcast
->operand
;
5396 if (!t
->opcode_modifier
.broadcast
5397 || !(i
.flags
[op
] & Operand_Mem
)
5398 || (!i
.types
[op
].bitfield
.unspecified
5399 && !match_broadcast_size (t
, op
)))
5402 i
.error
= unsupported_broadcast
;
5406 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5407 * i
.broadcast
->type
);
5408 operand_type_set (&type
, 0);
5409 switch (i
.broadcast
->bytes
)
5412 type
.bitfield
.word
= 1;
5415 type
.bitfield
.dword
= 1;
5418 type
.bitfield
.qword
= 1;
5421 type
.bitfield
.xmmword
= 1;
5424 type
.bitfield
.ymmword
= 1;
5427 type
.bitfield
.zmmword
= 1;
5433 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5434 if (operand_type_all_zero (&overlap
))
5437 if (t
->opcode_modifier
.checkregsize
)
5441 type
.bitfield
.baseindex
= 1;
5442 for (j
= 0; j
< i
.operands
; ++j
)
5445 && !operand_type_register_match(i
.types
[j
],
5446 t
->operand_types
[j
],
5448 t
->operand_types
[op
]))
5453 /* If broadcast is supported in this instruction, we need to check if
5454 operand of one-element size isn't specified without broadcast. */
5455 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5457 /* Find memory operand. */
5458 for (op
= 0; op
< i
.operands
; op
++)
5459 if (i
.flags
[op
] & Operand_Mem
)
5461 gas_assert (op
< i
.operands
);
5462 /* Check size of the memory operand. */
5463 if (match_broadcast_size (t
, op
))
5465 i
.error
= broadcast_needed
;
5470 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5472 /* Check if requested masking is supported. */
5475 switch (t
->opcode_modifier
.masking
)
5479 case MERGING_MASKING
:
5480 if (i
.mask
->zeroing
)
5483 i
.error
= unsupported_masking
;
5487 case DYNAMIC_MASKING
:
5488 /* Memory destinations allow only merging masking. */
5489 if (i
.mask
->zeroing
&& i
.mem_operands
)
5491 /* Find memory operand. */
5492 for (op
= 0; op
< i
.operands
; op
++)
5493 if (i
.flags
[op
] & Operand_Mem
)
5495 gas_assert (op
< i
.operands
);
5496 if (op
== i
.operands
- 1)
5498 i
.error
= unsupported_masking
;
5508 /* Check if masking is applied to dest operand. */
5509 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5511 i
.error
= mask_not_on_destination
;
5518 if (!t
->opcode_modifier
.sae
5519 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5521 i
.error
= unsupported_rc_sae
;
5524 /* If the instruction has several immediate operands and one of
5525 them is rounding, the rounding operand should be the last
5526 immediate operand. */
5527 if (i
.imm_operands
> 1
5528 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5530 i
.error
= rc_sae_operand_not_last_imm
;
5535 /* Check vector Disp8 operand. */
5536 if (t
->opcode_modifier
.disp8memshift
5537 && i
.disp_encoding
!= disp_encoding_32bit
)
5540 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5541 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5542 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5545 const i386_operand_type
*type
= NULL
;
5548 for (op
= 0; op
< i
.operands
; op
++)
5549 if (i
.flags
[op
] & Operand_Mem
)
5551 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5552 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5553 else if (t
->operand_types
[op
].bitfield
.xmmword
5554 + t
->operand_types
[op
].bitfield
.ymmword
5555 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5556 type
= &t
->operand_types
[op
];
5557 else if (!i
.types
[op
].bitfield
.unspecified
)
5558 type
= &i
.types
[op
];
5560 else if (i
.types
[op
].bitfield
.class == RegSIMD
5561 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5563 if (i
.types
[op
].bitfield
.zmmword
)
5565 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5567 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5573 if (type
->bitfield
.zmmword
)
5575 else if (type
->bitfield
.ymmword
)
5577 else if (type
->bitfield
.xmmword
)
5581 /* For the check in fits_in_disp8(). */
5582 if (i
.memshift
== 0)
5586 for (op
= 0; op
< i
.operands
; op
++)
5587 if (operand_type_check (i
.types
[op
], disp
)
5588 && i
.op
[op
].disps
->X_op
== O_constant
)
5590 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5592 i
.types
[op
].bitfield
.disp8
= 1;
5595 i
.types
[op
].bitfield
.disp8
= 0;
5604 /* Check if operands are valid for the instruction. Update VEX
5608 VEX_check_operands (const insn_template
*t
)
5610 if (i
.vec_encoding
== vex_encoding_evex
)
5612 /* This instruction must be encoded with EVEX prefix. */
5613 if (!is_evex_encoding (t
))
5615 i
.error
= unsupported
;
5621 if (!t
->opcode_modifier
.vex
)
5623 /* This instruction template doesn't have VEX prefix. */
5624 if (i
.vec_encoding
!= vex_encoding_default
)
5626 i
.error
= unsupported
;
5632 /* Check the special Imm4 cases; must be the first operand. */
5633 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5635 if (i
.op
[0].imms
->X_op
!= O_constant
5636 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5642 /* Turn off Imm<N> so that update_imm won't complain. */
5643 operand_type_set (&i
.types
[0], 0);
5649 static const insn_template
*
5650 match_template (char mnem_suffix
)
5652 /* Points to template once we've found it. */
5653 const insn_template
*t
;
5654 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5655 i386_operand_type overlap4
;
5656 unsigned int found_reverse_match
;
5657 i386_opcode_modifier suffix_check
;
5658 i386_operand_type operand_types
[MAX_OPERANDS
];
5659 int addr_prefix_disp
;
5661 unsigned int found_cpu_match
, size_match
;
5662 unsigned int check_register
;
5663 enum i386_error specific_error
= 0;
5665 #if MAX_OPERANDS != 5
5666 # error "MAX_OPERANDS must be 5."
5669 found_reverse_match
= 0;
5670 addr_prefix_disp
= -1;
5672 /* Prepare for mnemonic suffix check. */
5673 memset (&suffix_check
, 0, sizeof (suffix_check
));
5674 switch (mnem_suffix
)
5676 case BYTE_MNEM_SUFFIX
:
5677 suffix_check
.no_bsuf
= 1;
5679 case WORD_MNEM_SUFFIX
:
5680 suffix_check
.no_wsuf
= 1;
5682 case SHORT_MNEM_SUFFIX
:
5683 suffix_check
.no_ssuf
= 1;
5685 case LONG_MNEM_SUFFIX
:
5686 suffix_check
.no_lsuf
= 1;
5688 case QWORD_MNEM_SUFFIX
:
5689 suffix_check
.no_qsuf
= 1;
5692 /* NB: In Intel syntax, normally we can check for memory operand
5693 size when there is no mnemonic suffix. But jmp and call have
5694 2 different encodings with Dword memory operand size, one with
5695 No_ldSuf and the other without. i.suffix is set to
5696 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5697 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5698 suffix_check
.no_ldsuf
= 1;
5701 /* Must have right number of operands. */
5702 i
.error
= number_of_operands_mismatch
;
5704 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5706 addr_prefix_disp
= -1;
5707 found_reverse_match
= 0;
5709 if (i
.operands
!= t
->operands
)
5712 /* Check processor support. */
5713 i
.error
= unsupported
;
5714 found_cpu_match
= (cpu_flags_match (t
)
5715 == CPU_FLAGS_PERFECT_MATCH
);
5716 if (!found_cpu_match
)
5719 /* Check AT&T mnemonic. */
5720 i
.error
= unsupported_with_intel_mnemonic
;
5721 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5724 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5725 i
.error
= unsupported_syntax
;
5726 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5727 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5728 || (intel64
&& t
->opcode_modifier
.amd64
)
5729 || (!intel64
&& t
->opcode_modifier
.intel64
))
5732 /* Check the suffix. */
5733 i
.error
= invalid_instruction_suffix
;
5734 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5735 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5736 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5737 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5738 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5739 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5742 size_match
= operand_size_match (t
);
5746 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5747 operand_types
[j
] = t
->operand_types
[j
];
5749 /* In general, don't allow 64-bit operands in 32-bit mode. */
5750 if (i
.suffix
== QWORD_MNEM_SUFFIX
5751 && flag_code
!= CODE_64BIT
5753 ? (!t
->opcode_modifier
.ignoresize
5754 && !t
->opcode_modifier
.broadcast
5755 && !intel_float_operand (t
->name
))
5756 : intel_float_operand (t
->name
) != 2)
5757 && ((operand_types
[0].bitfield
.class != RegMMX
5758 && operand_types
[0].bitfield
.class != RegSIMD
)
5759 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5760 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5761 && (t
->base_opcode
!= 0x0fc7
5762 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5765 /* In general, don't allow 32-bit operands on pre-386. */
5766 else if (i
.suffix
== LONG_MNEM_SUFFIX
5767 && !cpu_arch_flags
.bitfield
.cpui386
5769 ? (!t
->opcode_modifier
.ignoresize
5770 && !intel_float_operand (t
->name
))
5771 : intel_float_operand (t
->name
) != 2)
5772 && ((operand_types
[0].bitfield
.class != RegMMX
5773 && operand_types
[0].bitfield
.class != RegSIMD
)
5774 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5775 && operand_types
[t
->operands
> 1].bitfield
.class
5779 /* Do not verify operands when there are none. */
5783 /* We've found a match; break out of loop. */
5787 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5788 into Disp32/Disp16/Disp32 operand. */
5789 if (i
.prefix
[ADDR_PREFIX
] != 0)
5791 /* There should be only one Disp operand. */
5795 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5797 if (operand_types
[j
].bitfield
.disp16
)
5799 addr_prefix_disp
= j
;
5800 operand_types
[j
].bitfield
.disp32
= 1;
5801 operand_types
[j
].bitfield
.disp16
= 0;
5807 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5809 if (operand_types
[j
].bitfield
.disp32
)
5811 addr_prefix_disp
= j
;
5812 operand_types
[j
].bitfield
.disp32
= 0;
5813 operand_types
[j
].bitfield
.disp16
= 1;
5819 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5821 if (operand_types
[j
].bitfield
.disp64
)
5823 addr_prefix_disp
= j
;
5824 operand_types
[j
].bitfield
.disp64
= 0;
5825 operand_types
[j
].bitfield
.disp32
= 1;
5833 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5834 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5837 /* We check register size if needed. */
5838 if (t
->opcode_modifier
.checkregsize
)
5840 check_register
= (1 << t
->operands
) - 1;
5842 check_register
&= ~(1 << i
.broadcast
->operand
);
5847 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5848 switch (t
->operands
)
5851 if (!operand_type_match (overlap0
, i
.types
[0]))
5855 /* xchg %eax, %eax is a special case. It is an alias for nop
5856 only in 32bit mode and we can use opcode 0x90. In 64bit
5857 mode, we can't use 0x90 for xchg %eax, %eax since it should
5858 zero-extend %eax to %rax. */
5859 if (flag_code
== CODE_64BIT
5860 && t
->base_opcode
== 0x90
5861 && i
.types
[0].bitfield
.instance
== Accum
5862 && i
.types
[0].bitfield
.dword
5863 && i
.types
[1].bitfield
.instance
== Accum
5864 && i
.types
[1].bitfield
.dword
)
5866 /* xrelease mov %eax, <disp> is another special case. It must not
5867 match the accumulator-only encoding of mov. */
5868 if (flag_code
!= CODE_64BIT
5870 && t
->base_opcode
== 0xa0
5871 && i
.types
[0].bitfield
.instance
== Accum
5872 && (i
.flags
[1] & Operand_Mem
))
5877 if (!(size_match
& MATCH_STRAIGHT
))
5879 /* Reverse direction of operands if swapping is possible in the first
5880 place (operands need to be symmetric) and
5881 - the load form is requested, and the template is a store form,
5882 - the store form is requested, and the template is a load form,
5883 - the non-default (swapped) form is requested. */
5884 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5885 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5886 && !operand_type_all_zero (&overlap1
))
5887 switch (i
.dir_encoding
)
5889 case dir_encoding_load
:
5890 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5891 || t
->opcode_modifier
.regmem
)
5895 case dir_encoding_store
:
5896 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5897 && !t
->opcode_modifier
.regmem
)
5901 case dir_encoding_swap
:
5904 case dir_encoding_default
:
5907 /* If we want store form, we skip the current load. */
5908 if ((i
.dir_encoding
== dir_encoding_store
5909 || i
.dir_encoding
== dir_encoding_swap
)
5910 && i
.mem_operands
== 0
5911 && t
->opcode_modifier
.load
)
5916 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5917 if (!operand_type_match (overlap0
, i
.types
[0])
5918 || !operand_type_match (overlap1
, i
.types
[1])
5919 || ((check_register
& 3) == 3
5920 && !operand_type_register_match (i
.types
[0],
5925 /* Check if other direction is valid ... */
5926 if (!t
->opcode_modifier
.d
)
5930 if (!(size_match
& MATCH_REVERSE
))
5932 /* Try reversing direction of operands. */
5933 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5934 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5935 if (!operand_type_match (overlap0
, i
.types
[0])
5936 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5938 && !operand_type_register_match (i
.types
[0],
5939 operand_types
[i
.operands
- 1],
5940 i
.types
[i
.operands
- 1],
5943 /* Does not match either direction. */
5946 /* found_reverse_match holds which of D or FloatR
5948 if (!t
->opcode_modifier
.d
)
5949 found_reverse_match
= 0;
5950 else if (operand_types
[0].bitfield
.tbyte
)
5951 found_reverse_match
= Opcode_FloatD
;
5952 else if (operand_types
[0].bitfield
.xmmword
5953 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5954 || operand_types
[0].bitfield
.class == RegMMX
5955 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
5956 || is_any_vex_encoding(t
))
5957 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5958 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5960 found_reverse_match
= Opcode_D
;
5961 if (t
->opcode_modifier
.floatr
)
5962 found_reverse_match
|= Opcode_FloatR
;
5966 /* Found a forward 2 operand match here. */
5967 switch (t
->operands
)
5970 overlap4
= operand_type_and (i
.types
[4],
5974 overlap3
= operand_type_and (i
.types
[3],
5978 overlap2
= operand_type_and (i
.types
[2],
5983 switch (t
->operands
)
5986 if (!operand_type_match (overlap4
, i
.types
[4])
5987 || !operand_type_register_match (i
.types
[3],
5994 if (!operand_type_match (overlap3
, i
.types
[3])
5995 || ((check_register
& 0xa) == 0xa
5996 && !operand_type_register_match (i
.types
[1],
6000 || ((check_register
& 0xc) == 0xc
6001 && !operand_type_register_match (i
.types
[2],
6008 /* Here we make use of the fact that there are no
6009 reverse match 3 operand instructions. */
6010 if (!operand_type_match (overlap2
, i
.types
[2])
6011 || ((check_register
& 5) == 5
6012 && !operand_type_register_match (i
.types
[0],
6016 || ((check_register
& 6) == 6
6017 && !operand_type_register_match (i
.types
[1],
6025 /* Found either forward/reverse 2, 3 or 4 operand match here:
6026 slip through to break. */
6028 if (!found_cpu_match
)
6031 /* Check if vector and VEX operands are valid. */
6032 if (check_VecOperands (t
) || VEX_check_operands (t
))
6034 specific_error
= i
.error
;
6038 /* We've found a match; break out of loop. */
6042 if (t
== current_templates
->end
)
6044 /* We found no match. */
6045 const char *err_msg
;
6046 switch (specific_error
? specific_error
: i
.error
)
6050 case operand_size_mismatch
:
6051 err_msg
= _("operand size mismatch");
6053 case operand_type_mismatch
:
6054 err_msg
= _("operand type mismatch");
6056 case register_type_mismatch
:
6057 err_msg
= _("register type mismatch");
6059 case number_of_operands_mismatch
:
6060 err_msg
= _("number of operands mismatch");
6062 case invalid_instruction_suffix
:
6063 err_msg
= _("invalid instruction suffix");
6066 err_msg
= _("constant doesn't fit in 4 bits");
6068 case unsupported_with_intel_mnemonic
:
6069 err_msg
= _("unsupported with Intel mnemonic");
6071 case unsupported_syntax
:
6072 err_msg
= _("unsupported syntax");
6075 as_bad (_("unsupported instruction `%s'"),
6076 current_templates
->start
->name
);
6078 case invalid_vsib_address
:
6079 err_msg
= _("invalid VSIB address");
6081 case invalid_vector_register_set
:
6082 err_msg
= _("mask, index, and destination registers must be distinct");
6084 case unsupported_vector_index_register
:
6085 err_msg
= _("unsupported vector index register");
6087 case unsupported_broadcast
:
6088 err_msg
= _("unsupported broadcast");
6090 case broadcast_needed
:
6091 err_msg
= _("broadcast is needed for operand of such type");
6093 case unsupported_masking
:
6094 err_msg
= _("unsupported masking");
6096 case mask_not_on_destination
:
6097 err_msg
= _("mask not on destination operand");
6099 case no_default_mask
:
6100 err_msg
= _("default mask isn't allowed");
6102 case unsupported_rc_sae
:
6103 err_msg
= _("unsupported static rounding/sae");
6105 case rc_sae_operand_not_last_imm
:
6107 err_msg
= _("RC/SAE operand must precede immediate operands");
6109 err_msg
= _("RC/SAE operand must follow immediate operands");
6111 case invalid_register_operand
:
6112 err_msg
= _("invalid register operand");
6115 as_bad (_("%s for `%s'"), err_msg
,
6116 current_templates
->start
->name
);
6120 if (!quiet_warnings
)
6123 && (i
.types
[0].bitfield
.jumpabsolute
6124 != operand_types
[0].bitfield
.jumpabsolute
))
6126 as_warn (_("indirect %s without `*'"), t
->name
);
6129 if (t
->opcode_modifier
.isprefix
6130 && t
->opcode_modifier
.ignoresize
)
6132 /* Warn them that a data or address size prefix doesn't
6133 affect assembly of the next line of code. */
6134 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6138 /* Copy the template we found. */
6141 if (addr_prefix_disp
!= -1)
6142 i
.tm
.operand_types
[addr_prefix_disp
]
6143 = operand_types
[addr_prefix_disp
];
6145 if (found_reverse_match
)
6147 /* If we found a reverse match we must alter the opcode direction
6148 bit and clear/flip the regmem modifier one. found_reverse_match
6149 holds bits to change (different for int & float insns). */
6151 i
.tm
.base_opcode
^= found_reverse_match
;
6153 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6154 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6156 /* Certain SIMD insns have their load forms specified in the opcode
6157 table, and hence we need to _set_ RegMem instead of clearing it.
6158 We need to avoid setting the bit though on insns like KMOVW. */
6159 i
.tm
.opcode_modifier
.regmem
6160 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6161 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6162 && !i
.tm
.opcode_modifier
.regmem
;
6171 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6172 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6174 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6176 as_bad (_("`%s' operand %u must use `%ses' segment"),
6178 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6183 /* There's only ever one segment override allowed per instruction.
6184 This instruction possibly has a legal segment override on the
6185 second operand, so copy the segment to where non-string
6186 instructions store it, allowing common code. */
6187 i
.seg
[op
] = i
.seg
[1];
6193 process_suffix (void)
6195 /* If matched instruction specifies an explicit instruction mnemonic
6197 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6198 i
.suffix
= WORD_MNEM_SUFFIX
;
6199 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6200 i
.suffix
= LONG_MNEM_SUFFIX
;
6201 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6202 i
.suffix
= QWORD_MNEM_SUFFIX
;
6203 else if (i
.reg_operands
)
6205 /* If there's no instruction mnemonic suffix we try to invent one
6206 based on register operands. */
6209 /* We take i.suffix from the last register operand specified,
6210 Destination register type is more significant than source
6211 register type. crc32 in SSE4.2 prefers source register
6213 if (i
.tm
.base_opcode
== 0xf20f38f0
6214 && i
.types
[0].bitfield
.class == Reg
)
6216 if (i
.types
[0].bitfield
.byte
)
6217 i
.suffix
= BYTE_MNEM_SUFFIX
;
6218 else if (i
.types
[0].bitfield
.word
)
6219 i
.suffix
= WORD_MNEM_SUFFIX
;
6220 else if (i
.types
[0].bitfield
.dword
)
6221 i
.suffix
= LONG_MNEM_SUFFIX
;
6222 else if (i
.types
[0].bitfield
.qword
)
6223 i
.suffix
= QWORD_MNEM_SUFFIX
;
6230 if (i
.tm
.base_opcode
== 0xf20f38f0)
6232 /* We have to know the operand size for crc32. */
6233 as_bad (_("ambiguous memory operand size for `%s`"),
6238 for (op
= i
.operands
; --op
>= 0;)
6239 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6240 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6242 if (i
.types
[op
].bitfield
.class != Reg
)
6244 if (i
.types
[op
].bitfield
.byte
)
6245 i
.suffix
= BYTE_MNEM_SUFFIX
;
6246 else if (i
.types
[op
].bitfield
.word
)
6247 i
.suffix
= WORD_MNEM_SUFFIX
;
6248 else if (i
.types
[op
].bitfield
.dword
)
6249 i
.suffix
= LONG_MNEM_SUFFIX
;
6250 else if (i
.types
[op
].bitfield
.qword
)
6251 i
.suffix
= QWORD_MNEM_SUFFIX
;
6258 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6261 && i
.tm
.opcode_modifier
.ignoresize
6262 && i
.tm
.opcode_modifier
.no_bsuf
)
6264 else if (!check_byte_reg ())
6267 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6270 && i
.tm
.opcode_modifier
.ignoresize
6271 && i
.tm
.opcode_modifier
.no_lsuf
6272 && !i
.tm
.opcode_modifier
.todword
6273 && !i
.tm
.opcode_modifier
.toqword
)
6275 else if (!check_long_reg ())
6278 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6281 && i
.tm
.opcode_modifier
.ignoresize
6282 && i
.tm
.opcode_modifier
.no_qsuf
6283 && !i
.tm
.opcode_modifier
.todword
6284 && !i
.tm
.opcode_modifier
.toqword
)
6286 else if (!check_qword_reg ())
6289 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6292 && i
.tm
.opcode_modifier
.ignoresize
6293 && i
.tm
.opcode_modifier
.no_wsuf
)
6295 else if (!check_word_reg ())
6298 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6299 /* Do nothing if the instruction is going to ignore the prefix. */
6304 else if (i
.tm
.opcode_modifier
.defaultsize
6306 /* exclude fldenv/frstor/fsave/fstenv */
6307 && i
.tm
.opcode_modifier
.no_ssuf
)
6309 if (stackop_size
== LONG_MNEM_SUFFIX
6310 && i
.tm
.base_opcode
== 0xcf)
6312 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6313 .code16gcc directive to support 16-bit mode with
6314 32-bit address. For IRET without a suffix, generate
6315 16-bit IRET (opcode 0xcf) to return from an interrupt
6317 i
.suffix
= WORD_MNEM_SUFFIX
;
6318 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6321 i
.suffix
= stackop_size
;
6323 else if (intel_syntax
6325 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6326 || i
.tm
.opcode_modifier
.jumpbyte
6327 || i
.tm
.opcode_modifier
.jumpintersegment
6328 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6329 && i
.tm
.extension_opcode
<= 3)))
6334 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6336 i
.suffix
= QWORD_MNEM_SUFFIX
;
6341 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6342 i
.suffix
= LONG_MNEM_SUFFIX
;
6345 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6346 i
.suffix
= WORD_MNEM_SUFFIX
;
6355 if (i
.tm
.opcode_modifier
.w
)
6357 as_bad (_("no instruction mnemonic suffix given and "
6358 "no register operands; can't size instruction"));
6364 unsigned int suffixes
;
6366 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6367 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6369 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6371 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6373 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6375 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6378 /* There are more than suffix matches. */
6379 if (i
.tm
.opcode_modifier
.w
6380 || ((suffixes
& (suffixes
- 1))
6381 && !i
.tm
.opcode_modifier
.defaultsize
6382 && !i
.tm
.opcode_modifier
.ignoresize
))
6384 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6390 /* Change the opcode based on the operand size given by i.suffix. */
6393 /* Size floating point instruction. */
6394 case LONG_MNEM_SUFFIX
:
6395 if (i
.tm
.opcode_modifier
.floatmf
)
6397 i
.tm
.base_opcode
^= 4;
6401 case WORD_MNEM_SUFFIX
:
6402 case QWORD_MNEM_SUFFIX
:
6403 /* It's not a byte, select word/dword operation. */
6404 if (i
.tm
.opcode_modifier
.w
)
6406 if (i
.tm
.opcode_modifier
.shortform
)
6407 i
.tm
.base_opcode
|= 8;
6409 i
.tm
.base_opcode
|= 1;
6412 case SHORT_MNEM_SUFFIX
:
6413 /* Now select between word & dword operations via the operand
6414 size prefix, except for instructions that will ignore this
6416 if (i
.reg_operands
> 0
6417 && i
.types
[0].bitfield
.class == Reg
6418 && i
.tm
.opcode_modifier
.addrprefixopreg
6419 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6420 || i
.operands
== 1))
6422 /* The address size override prefix changes the size of the
6424 if ((flag_code
== CODE_32BIT
6425 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6426 || (flag_code
!= CODE_32BIT
6427 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6428 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6431 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6432 && !i
.tm
.opcode_modifier
.ignoresize
6433 && !i
.tm
.opcode_modifier
.floatmf
6434 && !is_any_vex_encoding (&i
.tm
)
6435 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6436 || (flag_code
== CODE_64BIT
6437 && i
.tm
.opcode_modifier
.jumpbyte
)))
6439 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6441 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6442 prefix
= ADDR_PREFIX_OPCODE
;
6444 if (!add_prefix (prefix
))
6448 /* Set mode64 for an operand. */
6449 if (i
.suffix
== QWORD_MNEM_SUFFIX
6450 && flag_code
== CODE_64BIT
6451 && !i
.tm
.opcode_modifier
.norex64
6452 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6454 && ! (i
.operands
== 2
6455 && i
.tm
.base_opcode
== 0x90
6456 && i
.tm
.extension_opcode
== None
6457 && i
.types
[0].bitfield
.instance
== Accum
6458 && i
.types
[0].bitfield
.qword
6459 && i
.types
[1].bitfield
.instance
== Accum
6460 && i
.types
[1].bitfield
.qword
))
6466 if (i
.reg_operands
!= 0
6468 && i
.tm
.opcode_modifier
.addrprefixopreg
6469 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6471 /* Check invalid register operand when the address size override
6472 prefix changes the size of register operands. */
6474 enum { need_word
, need_dword
, need_qword
} need
;
6476 if (flag_code
== CODE_32BIT
)
6477 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6480 if (i
.prefix
[ADDR_PREFIX
])
6483 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6486 for (op
= 0; op
< i
.operands
; op
++)
6487 if (i
.types
[op
].bitfield
.class == Reg
6488 && ((need
== need_word
6489 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6490 || (need
== need_dword
6491 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6492 || (need
== need_qword
6493 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6495 as_bad (_("invalid register operand size for `%s'"),
6505 check_byte_reg (void)
6509 for (op
= i
.operands
; --op
>= 0;)
6511 /* Skip non-register operands. */
6512 if (i
.types
[op
].bitfield
.class != Reg
)
6515 /* If this is an eight bit register, it's OK. If it's the 16 or
6516 32 bit version of an eight bit register, we will just use the
6517 low portion, and that's OK too. */
6518 if (i
.types
[op
].bitfield
.byte
)
6521 /* I/O port address operands are OK too. */
6522 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6523 && i
.tm
.operand_types
[op
].bitfield
.word
)
6526 /* crc32 doesn't generate this warning. */
6527 if (i
.tm
.base_opcode
== 0xf20f38f0)
6530 if ((i
.types
[op
].bitfield
.word
6531 || i
.types
[op
].bitfield
.dword
6532 || i
.types
[op
].bitfield
.qword
)
6533 && i
.op
[op
].regs
->reg_num
< 4
6534 /* Prohibit these changes in 64bit mode, since the lowering
6535 would be more complicated. */
6536 && flag_code
!= CODE_64BIT
)
6538 #if REGISTER_WARNINGS
6539 if (!quiet_warnings
)
6540 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6542 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6543 ? REGNAM_AL
- REGNAM_AX
6544 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6546 i
.op
[op
].regs
->reg_name
,
6551 /* Any other register is bad. */
6552 if (i
.types
[op
].bitfield
.class == Reg
6553 || i
.types
[op
].bitfield
.class == RegMMX
6554 || i
.types
[op
].bitfield
.class == RegSIMD
6555 || i
.types
[op
].bitfield
.class == SReg
6556 || i
.types
[op
].bitfield
.class == RegCR
6557 || i
.types
[op
].bitfield
.class == RegDR
6558 || i
.types
[op
].bitfield
.class == RegTR
)
6560 as_bad (_("`%s%s' not allowed with `%s%c'"),
6562 i
.op
[op
].regs
->reg_name
,
6572 check_long_reg (void)
6576 for (op
= i
.operands
; --op
>= 0;)
6577 /* Skip non-register operands. */
6578 if (i
.types
[op
].bitfield
.class != Reg
)
6580 /* Reject eight bit registers, except where the template requires
6581 them. (eg. movzb) */
6582 else if (i
.types
[op
].bitfield
.byte
6583 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6584 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6585 && (i
.tm
.operand_types
[op
].bitfield
.word
6586 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6588 as_bad (_("`%s%s' not allowed with `%s%c'"),
6590 i
.op
[op
].regs
->reg_name
,
6595 /* Warn if the e prefix on a general reg is missing. */
6596 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6597 && i
.types
[op
].bitfield
.word
6598 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6599 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6600 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6602 /* Prohibit these changes in the 64bit mode, since the
6603 lowering is more complicated. */
6604 if (flag_code
== CODE_64BIT
)
6606 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6607 register_prefix
, i
.op
[op
].regs
->reg_name
,
6611 #if REGISTER_WARNINGS
6612 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6614 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6615 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6618 /* Warn if the r prefix on a general reg is present. */
6619 else if (i
.types
[op
].bitfield
.qword
6620 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6621 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6622 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6625 && i
.tm
.opcode_modifier
.toqword
6626 && i
.types
[0].bitfield
.class != RegSIMD
)
6628 /* Convert to QWORD. We want REX byte. */
6629 i
.suffix
= QWORD_MNEM_SUFFIX
;
6633 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6634 register_prefix
, i
.op
[op
].regs
->reg_name
,
6643 check_qword_reg (void)
6647 for (op
= i
.operands
; --op
>= 0; )
6648 /* Skip non-register operands. */
6649 if (i
.types
[op
].bitfield
.class != Reg
)
6651 /* Reject eight bit registers, except where the template requires
6652 them. (eg. movzb) */
6653 else if (i
.types
[op
].bitfield
.byte
6654 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6655 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6656 && (i
.tm
.operand_types
[op
].bitfield
.word
6657 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6659 as_bad (_("`%s%s' not allowed with `%s%c'"),
6661 i
.op
[op
].regs
->reg_name
,
6666 /* Warn if the r prefix on a general reg is missing. */
6667 else if ((i
.types
[op
].bitfield
.word
6668 || i
.types
[op
].bitfield
.dword
)
6669 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6670 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6671 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6673 /* Prohibit these changes in the 64bit mode, since the
6674 lowering is more complicated. */
6676 && i
.tm
.opcode_modifier
.todword
6677 && i
.types
[0].bitfield
.class != RegSIMD
)
6679 /* Convert to DWORD. We don't want REX byte. */
6680 i
.suffix
= LONG_MNEM_SUFFIX
;
6684 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6685 register_prefix
, i
.op
[op
].regs
->reg_name
,
6694 check_word_reg (void)
6697 for (op
= i
.operands
; --op
>= 0;)
6698 /* Skip non-register operands. */
6699 if (i
.types
[op
].bitfield
.class != Reg
)
6701 /* Reject eight bit registers, except where the template requires
6702 them. (eg. movzb) */
6703 else if (i
.types
[op
].bitfield
.byte
6704 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6705 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6706 && (i
.tm
.operand_types
[op
].bitfield
.word
6707 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6709 as_bad (_("`%s%s' not allowed with `%s%c'"),
6711 i
.op
[op
].regs
->reg_name
,
6716 /* Warn if the e or r prefix on a general reg is present. */
6717 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6718 && (i
.types
[op
].bitfield
.dword
6719 || i
.types
[op
].bitfield
.qword
)
6720 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6721 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6722 && i
.tm
.operand_types
[op
].bitfield
.word
)
6724 /* Prohibit these changes in the 64bit mode, since the
6725 lowering is more complicated. */
6726 if (flag_code
== CODE_64BIT
)
6728 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6729 register_prefix
, i
.op
[op
].regs
->reg_name
,
6733 #if REGISTER_WARNINGS
6734 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6736 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6737 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6744 update_imm (unsigned int j
)
6746 i386_operand_type overlap
= i
.types
[j
];
6747 if ((overlap
.bitfield
.imm8
6748 || overlap
.bitfield
.imm8s
6749 || overlap
.bitfield
.imm16
6750 || overlap
.bitfield
.imm32
6751 || overlap
.bitfield
.imm32s
6752 || overlap
.bitfield
.imm64
)
6753 && !operand_type_equal (&overlap
, &imm8
)
6754 && !operand_type_equal (&overlap
, &imm8s
)
6755 && !operand_type_equal (&overlap
, &imm16
)
6756 && !operand_type_equal (&overlap
, &imm32
)
6757 && !operand_type_equal (&overlap
, &imm32s
)
6758 && !operand_type_equal (&overlap
, &imm64
))
6762 i386_operand_type temp
;
6764 operand_type_set (&temp
, 0);
6765 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6767 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6768 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6770 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6771 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6772 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6774 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6775 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6778 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6781 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6782 || operand_type_equal (&overlap
, &imm16_32
)
6783 || operand_type_equal (&overlap
, &imm16_32s
))
6785 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6790 if (!operand_type_equal (&overlap
, &imm8
)
6791 && !operand_type_equal (&overlap
, &imm8s
)
6792 && !operand_type_equal (&overlap
, &imm16
)
6793 && !operand_type_equal (&overlap
, &imm32
)
6794 && !operand_type_equal (&overlap
, &imm32s
)
6795 && !operand_type_equal (&overlap
, &imm64
))
6797 as_bad (_("no instruction mnemonic suffix given; "
6798 "can't determine immediate size"));
6802 i
.types
[j
] = overlap
;
6812 /* Update the first 2 immediate operands. */
6813 n
= i
.operands
> 2 ? 2 : i
.operands
;
6816 for (j
= 0; j
< n
; j
++)
6817 if (update_imm (j
) == 0)
6820 /* The 3rd operand can't be immediate operand. */
6821 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6828 process_operands (void)
6830 /* Default segment register this instruction will use for memory
6831 accesses. 0 means unknown. This is only for optimizing out
6832 unnecessary segment overrides. */
6833 const seg_entry
*default_seg
= 0;
6835 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6837 unsigned int dupl
= i
.operands
;
6838 unsigned int dest
= dupl
- 1;
6841 /* The destination must be an xmm register. */
6842 gas_assert (i
.reg_operands
6843 && MAX_OPERANDS
> dupl
6844 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6846 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6847 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6849 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6851 /* Keep xmm0 for instructions with VEX prefix and 3
6853 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6854 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6859 /* We remove the first xmm0 and keep the number of
6860 operands unchanged, which in fact duplicates the
6862 for (j
= 1; j
< i
.operands
; j
++)
6864 i
.op
[j
- 1] = i
.op
[j
];
6865 i
.types
[j
- 1] = i
.types
[j
];
6866 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6867 i
.flags
[j
- 1] = i
.flags
[j
];
6871 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6873 gas_assert ((MAX_OPERANDS
- 1) > dupl
6874 && (i
.tm
.opcode_modifier
.vexsources
6877 /* Add the implicit xmm0 for instructions with VEX prefix
6879 for (j
= i
.operands
; j
> 0; j
--)
6881 i
.op
[j
] = i
.op
[j
- 1];
6882 i
.types
[j
] = i
.types
[j
- 1];
6883 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6884 i
.flags
[j
] = i
.flags
[j
- 1];
6887 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6888 i
.types
[0] = regxmm
;
6889 i
.tm
.operand_types
[0] = regxmm
;
6892 i
.reg_operands
+= 2;
6897 i
.op
[dupl
] = i
.op
[dest
];
6898 i
.types
[dupl
] = i
.types
[dest
];
6899 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6900 i
.flags
[dupl
] = i
.flags
[dest
];
6909 i
.op
[dupl
] = i
.op
[dest
];
6910 i
.types
[dupl
] = i
.types
[dest
];
6911 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6912 i
.flags
[dupl
] = i
.flags
[dest
];
6915 if (i
.tm
.opcode_modifier
.immext
)
6918 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6919 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6923 for (j
= 1; j
< i
.operands
; j
++)
6925 i
.op
[j
- 1] = i
.op
[j
];
6926 i
.types
[j
- 1] = i
.types
[j
];
6928 /* We need to adjust fields in i.tm since they are used by
6929 build_modrm_byte. */
6930 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6932 i
.flags
[j
- 1] = i
.flags
[j
];
6939 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6941 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6943 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6944 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
6945 regnum
= register_number (i
.op
[1].regs
);
6946 first_reg_in_group
= regnum
& ~3;
6947 last_reg_in_group
= first_reg_in_group
+ 3;
6948 if (regnum
!= first_reg_in_group
)
6949 as_warn (_("source register `%s%s' implicitly denotes"
6950 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6951 register_prefix
, i
.op
[1].regs
->reg_name
,
6952 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6953 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6956 else if (i
.tm
.opcode_modifier
.regkludge
)
6958 /* The imul $imm, %reg instruction is converted into
6959 imul $imm, %reg, %reg, and the clr %reg instruction
6960 is converted into xor %reg, %reg. */
6962 unsigned int first_reg_op
;
6964 if (operand_type_check (i
.types
[0], reg
))
6968 /* Pretend we saw the extra register operand. */
6969 gas_assert (i
.reg_operands
== 1
6970 && i
.op
[first_reg_op
+ 1].regs
== 0);
6971 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6972 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6977 if (i
.tm
.opcode_modifier
.modrm
)
6979 /* The opcode is completed (modulo i.tm.extension_opcode which
6980 must be put into the modrm byte). Now, we make the modrm and
6981 index base bytes based on all the info we've collected. */
6983 default_seg
= build_modrm_byte ();
6985 else if (i
.types
[0].bitfield
.class == SReg
)
6987 if (flag_code
!= CODE_64BIT
6988 ? i
.tm
.base_opcode
== POP_SEG_SHORT
6989 && i
.op
[0].regs
->reg_num
== 1
6990 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
6991 && i
.op
[0].regs
->reg_num
< 4)
6993 as_bad (_("you can't `%s %s%s'"),
6994 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
6997 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
6999 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7000 i
.tm
.opcode_length
= 2;
7002 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7004 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7008 else if (i
.tm
.opcode_modifier
.isstring
)
7010 /* For the string instructions that allow a segment override
7011 on one of their operands, the default segment is ds. */
7014 else if (i
.tm
.opcode_modifier
.shortform
)
7016 /* The register or float register operand is in operand
7018 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7020 /* Register goes in low 3 bits of opcode. */
7021 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7022 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7024 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7026 /* Warn about some common errors, but press on regardless.
7027 The first case can be generated by gcc (<= 2.8.1). */
7028 if (i
.operands
== 2)
7030 /* Reversed arguments on faddp, fsubp, etc. */
7031 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7032 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7033 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7037 /* Extraneous `l' suffix on fp insn. */
7038 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7039 register_prefix
, i
.op
[0].regs
->reg_name
);
7044 if (i
.tm
.base_opcode
== 0x8d /* lea */
7047 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7049 /* If a segment was explicitly specified, and the specified segment
7050 is not the default, use an opcode prefix to select it. If we
7051 never figured out what the default segment is, then default_seg
7052 will be zero at this point, and the specified segment prefix will
7054 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7056 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7062 static const seg_entry
*
7063 build_modrm_byte (void)
7065 const seg_entry
*default_seg
= 0;
7066 unsigned int source
, dest
;
7069 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7072 unsigned int nds
, reg_slot
;
7075 dest
= i
.operands
- 1;
7078 /* There are 2 kinds of instructions:
7079 1. 5 operands: 4 register operands or 3 register operands
7080 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7081 VexW0 or VexW1. The destination must be either XMM, YMM or
7083 2. 4 operands: 4 register operands or 3 register operands
7084 plus 1 memory operand, with VexXDS. */
7085 gas_assert ((i
.reg_operands
== 4
7086 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7087 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7088 && i
.tm
.opcode_modifier
.vexw
7089 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7091 /* If VexW1 is set, the first non-immediate operand is the source and
7092 the second non-immediate one is encoded in the immediate operand. */
7093 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7095 source
= i
.imm_operands
;
7096 reg_slot
= i
.imm_operands
+ 1;
7100 source
= i
.imm_operands
+ 1;
7101 reg_slot
= i
.imm_operands
;
7104 if (i
.imm_operands
== 0)
7106 /* When there is no immediate operand, generate an 8bit
7107 immediate operand to encode the first operand. */
7108 exp
= &im_expressions
[i
.imm_operands
++];
7109 i
.op
[i
.operands
].imms
= exp
;
7110 i
.types
[i
.operands
] = imm8
;
7113 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7114 exp
->X_op
= O_constant
;
7115 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7116 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7120 gas_assert (i
.imm_operands
== 1);
7121 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7122 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7124 /* Turn on Imm8 again so that output_imm will generate it. */
7125 i
.types
[0].bitfield
.imm8
= 1;
7127 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7128 i
.op
[0].imms
->X_add_number
7129 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7130 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7133 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7134 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7139 /* i.reg_operands MUST be the number of real register operands;
7140 implicit registers do not count. If there are 3 register
7141 operands, it must be a instruction with VexNDS. For a
7142 instruction with VexNDD, the destination register is encoded
7143 in VEX prefix. If there are 4 register operands, it must be
7144 a instruction with VEX prefix and 3 sources. */
7145 if (i
.mem_operands
== 0
7146 && ((i
.reg_operands
== 2
7147 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7148 || (i
.reg_operands
== 3
7149 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7150 || (i
.reg_operands
== 4 && vex_3_sources
)))
7158 /* When there are 3 operands, one of them may be immediate,
7159 which may be the first or the last operand. Otherwise,
7160 the first operand must be shift count register (cl) or it
7161 is an instruction with VexNDS. */
7162 gas_assert (i
.imm_operands
== 1
7163 || (i
.imm_operands
== 0
7164 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7165 || (i
.types
[0].bitfield
.instance
== RegC
7166 && i
.types
[0].bitfield
.byte
))));
7167 if (operand_type_check (i
.types
[0], imm
)
7168 || (i
.types
[0].bitfield
.instance
== RegC
7169 && i
.types
[0].bitfield
.byte
))
7175 /* When there are 4 operands, the first two must be 8bit
7176 immediate operands. The source operand will be the 3rd
7179 For instructions with VexNDS, if the first operand
7180 an imm8, the source operand is the 2nd one. If the last
7181 operand is imm8, the source operand is the first one. */
7182 gas_assert ((i
.imm_operands
== 2
7183 && i
.types
[0].bitfield
.imm8
7184 && i
.types
[1].bitfield
.imm8
)
7185 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7186 && i
.imm_operands
== 1
7187 && (i
.types
[0].bitfield
.imm8
7188 || i
.types
[i
.operands
- 1].bitfield
.imm8
7190 if (i
.imm_operands
== 2)
7194 if (i
.types
[0].bitfield
.imm8
)
7201 if (is_evex_encoding (&i
.tm
))
7203 /* For EVEX instructions, when there are 5 operands, the
7204 first one must be immediate operand. If the second one
7205 is immediate operand, the source operand is the 3th
7206 one. If the last one is immediate operand, the source
7207 operand is the 2nd one. */
7208 gas_assert (i
.imm_operands
== 2
7209 && i
.tm
.opcode_modifier
.sae
7210 && operand_type_check (i
.types
[0], imm
));
7211 if (operand_type_check (i
.types
[1], imm
))
7213 else if (operand_type_check (i
.types
[4], imm
))
7227 /* RC/SAE operand could be between DEST and SRC. That happens
7228 when one operand is GPR and the other one is XMM/YMM/ZMM
7230 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7233 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7235 /* For instructions with VexNDS, the register-only source
7236 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7237 register. It is encoded in VEX prefix. */
7239 i386_operand_type op
;
7242 /* Check register-only source operand when two source
7243 operands are swapped. */
7244 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7245 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7253 op
= i
.tm
.operand_types
[vvvv
];
7254 if ((dest
+ 1) >= i
.operands
7255 || ((op
.bitfield
.class != Reg
7256 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7257 && op
.bitfield
.class != RegSIMD
7258 && !operand_type_equal (&op
, ®mask
)))
7260 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7266 /* One of the register operands will be encoded in the i.rm.reg
7267 field, the other in the combined i.rm.mode and i.rm.regmem
7268 fields. If no form of this instruction supports a memory
7269 destination operand, then we assume the source operand may
7270 sometimes be a memory operand and so we need to store the
7271 destination in the i.rm.reg field. */
7272 if (!i
.tm
.opcode_modifier
.regmem
7273 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7275 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7276 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7277 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7278 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7279 i
.has_regmmx
= TRUE
;
7280 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7281 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7283 if (i
.types
[dest
].bitfield
.zmmword
7284 || i
.types
[source
].bitfield
.zmmword
)
7285 i
.has_regzmm
= TRUE
;
7286 else if (i
.types
[dest
].bitfield
.ymmword
7287 || i
.types
[source
].bitfield
.ymmword
)
7288 i
.has_regymm
= TRUE
;
7290 i
.has_regxmm
= TRUE
;
7292 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7294 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7296 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7298 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7303 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7304 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7305 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7307 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7309 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7311 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7314 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7316 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7319 add_prefix (LOCK_PREFIX_OPCODE
);
7323 { /* If it's not 2 reg operands... */
7328 unsigned int fake_zero_displacement
= 0;
7331 for (op
= 0; op
< i
.operands
; op
++)
7332 if (i
.flags
[op
] & Operand_Mem
)
7334 gas_assert (op
< i
.operands
);
7336 if (i
.tm
.opcode_modifier
.vecsib
)
7338 if (i
.index_reg
->reg_num
== RegIZ
)
7341 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7344 i
.sib
.base
= NO_BASE_REGISTER
;
7345 i
.sib
.scale
= i
.log2_scale_factor
;
7346 i
.types
[op
].bitfield
.disp8
= 0;
7347 i
.types
[op
].bitfield
.disp16
= 0;
7348 i
.types
[op
].bitfield
.disp64
= 0;
7349 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7351 /* Must be 32 bit */
7352 i
.types
[op
].bitfield
.disp32
= 1;
7353 i
.types
[op
].bitfield
.disp32s
= 0;
7357 i
.types
[op
].bitfield
.disp32
= 0;
7358 i
.types
[op
].bitfield
.disp32s
= 1;
7361 i
.sib
.index
= i
.index_reg
->reg_num
;
7362 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7364 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7370 if (i
.base_reg
== 0)
7373 if (!i
.disp_operands
)
7374 fake_zero_displacement
= 1;
7375 if (i
.index_reg
== 0)
7377 i386_operand_type newdisp
;
7379 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7380 /* Operand is just <disp> */
7381 if (flag_code
== CODE_64BIT
)
7383 /* 64bit mode overwrites the 32bit absolute
7384 addressing by RIP relative addressing and
7385 absolute addressing is encoded by one of the
7386 redundant SIB forms. */
7387 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7388 i
.sib
.base
= NO_BASE_REGISTER
;
7389 i
.sib
.index
= NO_INDEX_REGISTER
;
7390 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7392 else if ((flag_code
== CODE_16BIT
)
7393 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7395 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7400 i
.rm
.regmem
= NO_BASE_REGISTER
;
7403 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7404 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7406 else if (!i
.tm
.opcode_modifier
.vecsib
)
7408 /* !i.base_reg && i.index_reg */
7409 if (i
.index_reg
->reg_num
== RegIZ
)
7410 i
.sib
.index
= NO_INDEX_REGISTER
;
7412 i
.sib
.index
= i
.index_reg
->reg_num
;
7413 i
.sib
.base
= NO_BASE_REGISTER
;
7414 i
.sib
.scale
= i
.log2_scale_factor
;
7415 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7416 i
.types
[op
].bitfield
.disp8
= 0;
7417 i
.types
[op
].bitfield
.disp16
= 0;
7418 i
.types
[op
].bitfield
.disp64
= 0;
7419 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7421 /* Must be 32 bit */
7422 i
.types
[op
].bitfield
.disp32
= 1;
7423 i
.types
[op
].bitfield
.disp32s
= 0;
7427 i
.types
[op
].bitfield
.disp32
= 0;
7428 i
.types
[op
].bitfield
.disp32s
= 1;
7430 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7434 /* RIP addressing for 64bit mode. */
7435 else if (i
.base_reg
->reg_num
== RegIP
)
7437 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7438 i
.rm
.regmem
= NO_BASE_REGISTER
;
7439 i
.types
[op
].bitfield
.disp8
= 0;
7440 i
.types
[op
].bitfield
.disp16
= 0;
7441 i
.types
[op
].bitfield
.disp32
= 0;
7442 i
.types
[op
].bitfield
.disp32s
= 1;
7443 i
.types
[op
].bitfield
.disp64
= 0;
7444 i
.flags
[op
] |= Operand_PCrel
;
7445 if (! i
.disp_operands
)
7446 fake_zero_displacement
= 1;
7448 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7450 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7451 switch (i
.base_reg
->reg_num
)
7454 if (i
.index_reg
== 0)
7456 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7457 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7461 if (i
.index_reg
== 0)
7464 if (operand_type_check (i
.types
[op
], disp
) == 0)
7466 /* fake (%bp) into 0(%bp) */
7467 i
.types
[op
].bitfield
.disp8
= 1;
7468 fake_zero_displacement
= 1;
7471 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7472 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7474 default: /* (%si) -> 4 or (%di) -> 5 */
7475 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7477 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7479 else /* i.base_reg and 32/64 bit mode */
7481 if (flag_code
== CODE_64BIT
7482 && operand_type_check (i
.types
[op
], disp
))
7484 i
.types
[op
].bitfield
.disp16
= 0;
7485 i
.types
[op
].bitfield
.disp64
= 0;
7486 if (i
.prefix
[ADDR_PREFIX
] == 0)
7488 i
.types
[op
].bitfield
.disp32
= 0;
7489 i
.types
[op
].bitfield
.disp32s
= 1;
7493 i
.types
[op
].bitfield
.disp32
= 1;
7494 i
.types
[op
].bitfield
.disp32s
= 0;
7498 if (!i
.tm
.opcode_modifier
.vecsib
)
7499 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7500 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7502 i
.sib
.base
= i
.base_reg
->reg_num
;
7503 /* x86-64 ignores REX prefix bit here to avoid decoder
7505 if (!(i
.base_reg
->reg_flags
& RegRex
)
7506 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7507 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7509 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7511 fake_zero_displacement
= 1;
7512 i
.types
[op
].bitfield
.disp8
= 1;
7514 i
.sib
.scale
= i
.log2_scale_factor
;
7515 if (i
.index_reg
== 0)
7517 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7518 /* <disp>(%esp) becomes two byte modrm with no index
7519 register. We've already stored the code for esp
7520 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7521 Any base register besides %esp will not use the
7522 extra modrm byte. */
7523 i
.sib
.index
= NO_INDEX_REGISTER
;
7525 else if (!i
.tm
.opcode_modifier
.vecsib
)
7527 if (i
.index_reg
->reg_num
== RegIZ
)
7528 i
.sib
.index
= NO_INDEX_REGISTER
;
7530 i
.sib
.index
= i
.index_reg
->reg_num
;
7531 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7532 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7537 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7538 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7542 if (!fake_zero_displacement
7546 fake_zero_displacement
= 1;
7547 if (i
.disp_encoding
== disp_encoding_8bit
)
7548 i
.types
[op
].bitfield
.disp8
= 1;
7550 i
.types
[op
].bitfield
.disp32
= 1;
7552 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7556 if (fake_zero_displacement
)
7558 /* Fakes a zero displacement assuming that i.types[op]
7559 holds the correct displacement size. */
7562 gas_assert (i
.op
[op
].disps
== 0);
7563 exp
= &disp_expressions
[i
.disp_operands
++];
7564 i
.op
[op
].disps
= exp
;
7565 exp
->X_op
= O_constant
;
7566 exp
->X_add_number
= 0;
7567 exp
->X_add_symbol
= (symbolS
*) 0;
7568 exp
->X_op_symbol
= (symbolS
*) 0;
7576 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7578 if (operand_type_check (i
.types
[0], imm
))
7579 i
.vex
.register_specifier
= NULL
;
7582 /* VEX.vvvv encodes one of the sources when the first
7583 operand is not an immediate. */
7584 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7585 i
.vex
.register_specifier
= i
.op
[0].regs
;
7587 i
.vex
.register_specifier
= i
.op
[1].regs
;
7590 /* Destination is a XMM register encoded in the ModRM.reg
7592 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7593 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7596 /* ModRM.rm and VEX.B encodes the other source. */
7597 if (!i
.mem_operands
)
7601 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7602 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7604 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7606 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7610 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7612 i
.vex
.register_specifier
= i
.op
[2].regs
;
7613 if (!i
.mem_operands
)
7616 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7617 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7621 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7622 (if any) based on i.tm.extension_opcode. Again, we must be
7623 careful to make sure that segment/control/debug/test/MMX
7624 registers are coded into the i.rm.reg field. */
7625 else if (i
.reg_operands
)
7628 unsigned int vex_reg
= ~0;
7630 for (op
= 0; op
< i
.operands
; op
++)
7632 if (i
.types
[op
].bitfield
.class == Reg
7633 || i
.types
[op
].bitfield
.class == RegBND
7634 || i
.types
[op
].bitfield
.class == RegMask
7635 || i
.types
[op
].bitfield
.class == SReg
7636 || i
.types
[op
].bitfield
.class == RegCR
7637 || i
.types
[op
].bitfield
.class == RegDR
7638 || i
.types
[op
].bitfield
.class == RegTR
)
7640 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7642 if (i
.types
[op
].bitfield
.zmmword
)
7643 i
.has_regzmm
= TRUE
;
7644 else if (i
.types
[op
].bitfield
.ymmword
)
7645 i
.has_regymm
= TRUE
;
7647 i
.has_regxmm
= TRUE
;
7650 if (i
.types
[op
].bitfield
.class == RegMMX
)
7652 i
.has_regmmx
= TRUE
;
7659 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7661 /* For instructions with VexNDS, the register-only
7662 source operand is encoded in VEX prefix. */
7663 gas_assert (mem
!= (unsigned int) ~0);
7668 gas_assert (op
< i
.operands
);
7672 /* Check register-only source operand when two source
7673 operands are swapped. */
7674 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7675 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7679 gas_assert (mem
== (vex_reg
+ 1)
7680 && op
< i
.operands
);
7685 gas_assert (vex_reg
< i
.operands
);
7689 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7691 /* For instructions with VexNDD, the register destination
7692 is encoded in VEX prefix. */
7693 if (i
.mem_operands
== 0)
7695 /* There is no memory operand. */
7696 gas_assert ((op
+ 2) == i
.operands
);
7701 /* There are only 2 non-immediate operands. */
7702 gas_assert (op
< i
.imm_operands
+ 2
7703 && i
.operands
== i
.imm_operands
+ 2);
7704 vex_reg
= i
.imm_operands
+ 1;
7708 gas_assert (op
< i
.operands
);
7710 if (vex_reg
!= (unsigned int) ~0)
7712 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7714 if ((type
->bitfield
.class != Reg
7715 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7716 && type
->bitfield
.class != RegSIMD
7717 && !operand_type_equal (type
, ®mask
))
7720 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7723 /* Don't set OP operand twice. */
7726 /* If there is an extension opcode to put here, the
7727 register number must be put into the regmem field. */
7728 if (i
.tm
.extension_opcode
!= None
)
7730 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7731 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7733 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7738 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7739 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7741 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7746 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7747 must set it to 3 to indicate this is a register operand
7748 in the regmem field. */
7749 if (!i
.mem_operands
)
7753 /* Fill in i.rm.reg field with extension opcode (if any). */
7754 if (i
.tm
.extension_opcode
!= None
)
7755 i
.rm
.reg
= i
.tm
.extension_opcode
;
7761 output_branch (void)
7767 relax_substateT subtype
;
7771 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7772 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7775 if (i
.prefix
[DATA_PREFIX
] != 0)
7781 /* Pentium4 branch hints. */
7782 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7783 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7788 if (i
.prefix
[REX_PREFIX
] != 0)
7794 /* BND prefixed jump. */
7795 if (i
.prefix
[BND_PREFIX
] != 0)
7797 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7801 if (i
.prefixes
!= 0 && !intel_syntax
)
7802 as_warn (_("skipping prefixes on this instruction"));
7804 /* It's always a symbol; End frag & setup for relax.
7805 Make sure there is enough room in this frag for the largest
7806 instruction we may generate in md_convert_frag. This is 2
7807 bytes for the opcode and room for the prefix and largest
7809 frag_grow (prefix
+ 2 + 4);
7810 /* Prefix and 1 opcode byte go in fr_fix. */
7811 p
= frag_more (prefix
+ 1);
7812 if (i
.prefix
[DATA_PREFIX
] != 0)
7813 *p
++ = DATA_PREFIX_OPCODE
;
7814 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7815 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7816 *p
++ = i
.prefix
[SEG_PREFIX
];
7817 if (i
.prefix
[REX_PREFIX
] != 0)
7818 *p
++ = i
.prefix
[REX_PREFIX
];
7819 *p
= i
.tm
.base_opcode
;
7821 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7822 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7823 else if (cpu_arch_flags
.bitfield
.cpui386
)
7824 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7826 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7829 sym
= i
.op
[0].disps
->X_add_symbol
;
7830 off
= i
.op
[0].disps
->X_add_number
;
7832 if (i
.op
[0].disps
->X_op
!= O_constant
7833 && i
.op
[0].disps
->X_op
!= O_symbol
)
7835 /* Handle complex expressions. */
7836 sym
= make_expr_symbol (i
.op
[0].disps
);
7840 /* 1 possible extra opcode + 4 byte displacement go in var part.
7841 Pass reloc in fr_var. */
7842 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7846 /* Return TRUE iff PLT32 relocation should be used for branching to
7850 need_plt32_p (symbolS
*s
)
7852 /* PLT32 relocation is ELF only. */
7857 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7858 krtld support it. */
7862 /* Since there is no need to prepare for PLT branch on x86-64, we
7863 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7864 be used as a marker for 32-bit PC-relative branches. */
7868 /* Weak or undefined symbol need PLT32 relocation. */
7869 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7872 /* Non-global symbol doesn't need PLT32 relocation. */
7873 if (! S_IS_EXTERNAL (s
))
7876 /* Other global symbols need PLT32 relocation. NB: Symbol with
7877 non-default visibilities are treated as normal global symbol
7878 so that PLT32 relocation can be used as a marker for 32-bit
7879 PC-relative branches. It is useful for linker relaxation. */
7890 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7892 if (i
.tm
.opcode_modifier
.jumpbyte
)
7894 /* This is a loop or jecxz type instruction. */
7896 if (i
.prefix
[ADDR_PREFIX
] != 0)
7898 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7901 /* Pentium4 branch hints. */
7902 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7903 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7905 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7914 if (flag_code
== CODE_16BIT
)
7917 if (i
.prefix
[DATA_PREFIX
] != 0)
7919 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7929 if (i
.prefix
[REX_PREFIX
] != 0)
7931 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7935 /* BND prefixed jump. */
7936 if (i
.prefix
[BND_PREFIX
] != 0)
7938 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7942 if (i
.prefixes
!= 0 && !intel_syntax
)
7943 as_warn (_("skipping prefixes on this instruction"));
7945 p
= frag_more (i
.tm
.opcode_length
+ size
);
7946 switch (i
.tm
.opcode_length
)
7949 *p
++ = i
.tm
.base_opcode
>> 8;
7952 *p
++ = i
.tm
.base_opcode
;
7958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7960 && jump_reloc
== NO_RELOC
7961 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7962 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7965 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7967 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7968 i
.op
[0].disps
, 1, jump_reloc
);
7970 /* All jumps handled here are signed, but don't use a signed limit
7971 check for 32 and 16 bit jumps as we want to allow wrap around at
7972 4G and 64k respectively. */
7974 fixP
->fx_signed
= 1;
7978 output_interseg_jump (void)
7986 if (flag_code
== CODE_16BIT
)
7990 if (i
.prefix
[DATA_PREFIX
] != 0)
7996 if (i
.prefix
[REX_PREFIX
] != 0)
8006 if (i
.prefixes
!= 0 && !intel_syntax
)
8007 as_warn (_("skipping prefixes on this instruction"));
8009 /* 1 opcode; 2 segment; offset */
8010 p
= frag_more (prefix
+ 1 + 2 + size
);
8012 if (i
.prefix
[DATA_PREFIX
] != 0)
8013 *p
++ = DATA_PREFIX_OPCODE
;
8015 if (i
.prefix
[REX_PREFIX
] != 0)
8016 *p
++ = i
.prefix
[REX_PREFIX
];
8018 *p
++ = i
.tm
.base_opcode
;
8019 if (i
.op
[1].imms
->X_op
== O_constant
)
8021 offsetT n
= i
.op
[1].imms
->X_add_number
;
8024 && !fits_in_unsigned_word (n
)
8025 && !fits_in_signed_word (n
))
8027 as_bad (_("16-bit jump out of range"));
8030 md_number_to_chars (p
, n
, size
);
8033 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8034 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8035 if (i
.op
[0].imms
->X_op
!= O_constant
)
8036 as_bad (_("can't handle non absolute segment in `%s'"),
8038 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8046 asection
*seg
= now_seg
;
8047 subsegT subseg
= now_subseg
;
8049 unsigned int alignment
, align_size_1
;
8050 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8051 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8052 unsigned int padding
;
8054 if (!IS_ELF
|| !x86_used_note
)
8057 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8059 /* The .note.gnu.property section layout:
8061 Field Length Contents
8064 n_descsz 4 The note descriptor size
8065 n_type 4 NT_GNU_PROPERTY_TYPE_0
8067 n_desc n_descsz The program property array
8071 /* Create the .note.gnu.property section. */
8072 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8073 bfd_set_section_flags (sec
,
8080 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8091 bfd_set_section_alignment (sec
, alignment
);
8092 elf_section_type (sec
) = SHT_NOTE
;
8094 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8096 isa_1_descsz_raw
= 4 + 4 + 4;
8097 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8098 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8100 feature_2_descsz_raw
= isa_1_descsz
;
8101 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8103 feature_2_descsz_raw
+= 4 + 4 + 4;
8104 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8105 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8108 descsz
= feature_2_descsz
;
8109 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8110 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8112 /* Write n_namsz. */
8113 md_number_to_chars (p
, (valueT
) 4, 4);
8115 /* Write n_descsz. */
8116 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8119 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8122 memcpy (p
+ 4 * 3, "GNU", 4);
8124 /* Write 4-byte type. */
8125 md_number_to_chars (p
+ 4 * 4,
8126 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8128 /* Write 4-byte data size. */
8129 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8131 /* Write 4-byte data. */
8132 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8134 /* Zero out paddings. */
8135 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8137 memset (p
+ 4 * 7, 0, padding
);
8139 /* Write 4-byte type. */
8140 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8141 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8143 /* Write 4-byte data size. */
8144 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8146 /* Write 4-byte data. */
8147 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8148 (valueT
) x86_feature_2_used
, 4);
8150 /* Zero out paddings. */
8151 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8153 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8155 /* We probably can't restore the current segment, for there likely
8158 subseg_set (seg
, subseg
);
8163 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8164 const char *frag_now_ptr
)
8166 unsigned int len
= 0;
8168 if (start_frag
!= frag_now
)
8170 const fragS
*fr
= start_frag
;
8175 } while (fr
&& fr
!= frag_now
);
8178 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8184 fragS
*insn_start_frag
;
8185 offsetT insn_start_off
;
8187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8188 if (IS_ELF
&& x86_used_note
)
8190 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8191 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8192 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8193 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8194 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8195 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8196 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8197 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8198 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8199 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8200 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8201 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8202 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8203 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8204 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8205 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8206 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8207 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8208 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8209 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8210 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8211 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8212 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8213 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8214 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8215 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8216 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8217 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8218 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8219 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8220 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8221 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8222 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8223 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8224 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8225 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8226 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8227 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8228 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8230 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8231 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8233 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8235 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8239 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8242 || i
.tm
.cpu_flags
.bitfield
.cpu287
8243 || i
.tm
.cpu_flags
.bitfield
.cpu387
8244 || i
.tm
.cpu_flags
.bitfield
.cpu687
8245 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8246 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8247 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8248 Xfence instructions. */
8249 if (i
.tm
.base_opcode
!= 0xf18
8250 && i
.tm
.base_opcode
!= 0xf0d
8251 && i
.tm
.base_opcode
!= 0xfaef8
8253 || i
.tm
.cpu_flags
.bitfield
.cpummx
8254 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8255 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8256 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8258 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8260 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8262 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8263 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8264 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8265 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8266 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8267 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8268 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8269 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8270 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8274 /* Tie dwarf2 debug info to the address at the start of the insn.
8275 We can't do this after the insn has been output as the current
8276 frag may have been closed off. eg. by frag_var. */
8277 dwarf2_emit_insn (0);
8279 insn_start_frag
= frag_now
;
8280 insn_start_off
= frag_now_fix ();
8283 if (i
.tm
.opcode_modifier
.jump
)
8285 else if (i
.tm
.opcode_modifier
.jumpbyte
8286 || i
.tm
.opcode_modifier
.jumpdword
)
8288 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8289 output_interseg_jump ();
8292 /* Output normal instructions here. */
8296 unsigned int prefix
;
8299 && (i
.tm
.base_opcode
== 0xfaee8
8300 || i
.tm
.base_opcode
== 0xfaef0
8301 || i
.tm
.base_opcode
== 0xfaef8))
8303 /* Encode lfence, mfence, and sfence as
8304 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8305 offsetT val
= 0x240483f0ULL
;
8307 md_number_to_chars (p
, val
, 5);
8311 /* Some processors fail on LOCK prefix. This options makes
8312 assembler ignore LOCK prefix and serves as a workaround. */
8313 if (omit_lock_prefix
)
8315 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8317 i
.prefix
[LOCK_PREFIX
] = 0;
8320 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8321 don't need the explicit prefix. */
8322 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8324 switch (i
.tm
.opcode_length
)
8327 if (i
.tm
.base_opcode
& 0xff000000)
8329 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8330 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8331 || prefix
!= REPE_PREFIX_OPCODE
8332 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8333 add_prefix (prefix
);
8337 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8339 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8340 add_prefix (prefix
);
8346 /* Check for pseudo prefixes. */
8347 as_bad_where (insn_start_frag
->fr_file
,
8348 insn_start_frag
->fr_line
,
8349 _("pseudo prefix without instruction"));
8355 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8356 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8357 R_X86_64_GOTTPOFF relocation so that linker can safely
8358 perform IE->LE optimization. */
8359 if (x86_elf_abi
== X86_64_X32_ABI
8361 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8362 && i
.prefix
[REX_PREFIX
] == 0)
8363 add_prefix (REX_OPCODE
);
8366 /* The prefix bytes. */
8367 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8369 FRAG_APPEND_1_CHAR (*q
);
8373 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8378 /* REX byte is encoded in VEX prefix. */
8382 FRAG_APPEND_1_CHAR (*q
);
8385 /* There should be no other prefixes for instructions
8390 /* For EVEX instructions i.vrex should become 0 after
8391 build_evex_prefix. For VEX instructions upper 16 registers
8392 aren't available, so VREX should be 0. */
8395 /* Now the VEX prefix. */
8396 p
= frag_more (i
.vex
.length
);
8397 for (j
= 0; j
< i
.vex
.length
; j
++)
8398 p
[j
] = i
.vex
.bytes
[j
];
8401 /* Now the opcode; be careful about word order here! */
8402 if (i
.tm
.opcode_length
== 1)
8404 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8408 switch (i
.tm
.opcode_length
)
8412 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8413 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8417 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8427 /* Put out high byte first: can't use md_number_to_chars! */
8428 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8429 *p
= i
.tm
.base_opcode
& 0xff;
8432 /* Now the modrm byte and sib byte (if present). */
8433 if (i
.tm
.opcode_modifier
.modrm
)
8435 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8438 /* If i.rm.regmem == ESP (4)
8439 && i.rm.mode != (Register mode)
8441 ==> need second modrm byte. */
8442 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8444 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8445 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8447 | i
.sib
.scale
<< 6));
8450 if (i
.disp_operands
)
8451 output_disp (insn_start_frag
, insn_start_off
);
8454 output_imm (insn_start_frag
, insn_start_off
);
8457 * frag_now_fix () returning plain abs_section_offset when we're in the
8458 * absolute section, and abs_section_offset not getting updated as data
8459 * gets added to the frag breaks the logic below.
8461 if (now_seg
!= absolute_section
)
8463 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8465 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8473 pi ("" /*line*/, &i
);
8475 #endif /* DEBUG386 */
8478 /* Return the size of the displacement operand N. */
8481 disp_size (unsigned int n
)
8485 if (i
.types
[n
].bitfield
.disp64
)
8487 else if (i
.types
[n
].bitfield
.disp8
)
8489 else if (i
.types
[n
].bitfield
.disp16
)
8494 /* Return the size of the immediate operand N. */
8497 imm_size (unsigned int n
)
8500 if (i
.types
[n
].bitfield
.imm64
)
8502 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8504 else if (i
.types
[n
].bitfield
.imm16
)
8510 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8515 for (n
= 0; n
< i
.operands
; n
++)
8517 if (operand_type_check (i
.types
[n
], disp
))
8519 if (i
.op
[n
].disps
->X_op
== O_constant
)
8521 int size
= disp_size (n
);
8522 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8524 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8526 p
= frag_more (size
);
8527 md_number_to_chars (p
, val
, size
);
8531 enum bfd_reloc_code_real reloc_type
;
8532 int size
= disp_size (n
);
8533 int sign
= i
.types
[n
].bitfield
.disp32s
;
8534 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8537 /* We can't have 8 bit displacement here. */
8538 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8540 /* The PC relative address is computed relative
8541 to the instruction boundary, so in case immediate
8542 fields follows, we need to adjust the value. */
8543 if (pcrel
&& i
.imm_operands
)
8548 for (n1
= 0; n1
< i
.operands
; n1
++)
8549 if (operand_type_check (i
.types
[n1
], imm
))
8551 /* Only one immediate is allowed for PC
8552 relative address. */
8553 gas_assert (sz
== 0);
8555 i
.op
[n
].disps
->X_add_number
-= sz
;
8557 /* We should find the immediate. */
8558 gas_assert (sz
!= 0);
8561 p
= frag_more (size
);
8562 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8564 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8565 && (((reloc_type
== BFD_RELOC_32
8566 || reloc_type
== BFD_RELOC_X86_64_32S
8567 || (reloc_type
== BFD_RELOC_64
8569 && (i
.op
[n
].disps
->X_op
== O_symbol
8570 || (i
.op
[n
].disps
->X_op
== O_add
8571 && ((symbol_get_value_expression
8572 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8574 || reloc_type
== BFD_RELOC_32_PCREL
))
8578 reloc_type
= BFD_RELOC_386_GOTPC
;
8579 i
.op
[n
].imms
->X_add_number
+=
8580 encoding_length (insn_start_frag
, insn_start_off
, p
);
8582 else if (reloc_type
== BFD_RELOC_64
)
8583 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8585 /* Don't do the adjustment for x86-64, as there
8586 the pcrel addressing is relative to the _next_
8587 insn, and that is taken care of in other code. */
8588 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8590 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8591 size
, i
.op
[n
].disps
, pcrel
,
8593 /* Check for "call/jmp *mem", "mov mem, %reg",
8594 "test %reg, mem" and "binop mem, %reg" where binop
8595 is one of adc, add, and, cmp, or, sbb, sub, xor
8596 instructions without data prefix. Always generate
8597 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8598 if (i
.prefix
[DATA_PREFIX
] == 0
8599 && (generate_relax_relocations
8602 && i
.rm
.regmem
== 5))
8604 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8605 && ((i
.operands
== 1
8606 && i
.tm
.base_opcode
== 0xff
8607 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8609 && (i
.tm
.base_opcode
== 0x8b
8610 || i
.tm
.base_opcode
== 0x85
8611 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8615 fixP
->fx_tcbit
= i
.rex
!= 0;
8617 && (i
.base_reg
->reg_num
== RegIP
))
8618 fixP
->fx_tcbit2
= 1;
8621 fixP
->fx_tcbit2
= 1;
8629 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8634 for (n
= 0; n
< i
.operands
; n
++)
8636 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8637 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8640 if (operand_type_check (i
.types
[n
], imm
))
8642 if (i
.op
[n
].imms
->X_op
== O_constant
)
8644 int size
= imm_size (n
);
8647 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8649 p
= frag_more (size
);
8650 md_number_to_chars (p
, val
, size
);
8654 /* Not absolute_section.
8655 Need a 32-bit fixup (don't support 8bit
8656 non-absolute imms). Try to support other
8658 enum bfd_reloc_code_real reloc_type
;
8659 int size
= imm_size (n
);
8662 if (i
.types
[n
].bitfield
.imm32s
8663 && (i
.suffix
== QWORD_MNEM_SUFFIX
8664 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8669 p
= frag_more (size
);
8670 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8672 /* This is tough to explain. We end up with this one if we
8673 * have operands that look like
8674 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8675 * obtain the absolute address of the GOT, and it is strongly
8676 * preferable from a performance point of view to avoid using
8677 * a runtime relocation for this. The actual sequence of
8678 * instructions often look something like:
8683 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8685 * The call and pop essentially return the absolute address
8686 * of the label .L66 and store it in %ebx. The linker itself
8687 * will ultimately change the first operand of the addl so
8688 * that %ebx points to the GOT, but to keep things simple, the
8689 * .o file must have this operand set so that it generates not
8690 * the absolute address of .L66, but the absolute address of
8691 * itself. This allows the linker itself simply treat a GOTPC
8692 * relocation as asking for a pcrel offset to the GOT to be
8693 * added in, and the addend of the relocation is stored in the
8694 * operand field for the instruction itself.
8696 * Our job here is to fix the operand so that it would add
8697 * the correct offset so that %ebx would point to itself. The
8698 * thing that is tricky is that .-.L66 will point to the
8699 * beginning of the instruction, so we need to further modify
8700 * the operand so that it will point to itself. There are
8701 * other cases where you have something like:
8703 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8705 * and here no correction would be required. Internally in
8706 * the assembler we treat operands of this form as not being
8707 * pcrel since the '.' is explicitly mentioned, and I wonder
8708 * whether it would simplify matters to do it this way. Who
8709 * knows. In earlier versions of the PIC patches, the
8710 * pcrel_adjust field was used to store the correction, but
8711 * since the expression is not pcrel, I felt it would be
8712 * confusing to do it this way. */
8714 if ((reloc_type
== BFD_RELOC_32
8715 || reloc_type
== BFD_RELOC_X86_64_32S
8716 || reloc_type
== BFD_RELOC_64
)
8718 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8719 && (i
.op
[n
].imms
->X_op
== O_symbol
8720 || (i
.op
[n
].imms
->X_op
== O_add
8721 && ((symbol_get_value_expression
8722 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8726 reloc_type
= BFD_RELOC_386_GOTPC
;
8728 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8730 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8731 i
.op
[n
].imms
->X_add_number
+=
8732 encoding_length (insn_start_frag
, insn_start_off
, p
);
8734 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8735 i
.op
[n
].imms
, 0, reloc_type
);
8741 /* x86_cons_fix_new is called via the expression parsing code when a
8742 reloc is needed. We use this hook to get the correct .got reloc. */
8743 static int cons_sign
= -1;
8746 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8747 expressionS
*exp
, bfd_reloc_code_real_type r
)
8749 r
= reloc (len
, 0, cons_sign
, r
);
8752 if (exp
->X_op
== O_secrel
)
8754 exp
->X_op
= O_symbol
;
8755 r
= BFD_RELOC_32_SECREL
;
8759 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8762 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8763 purpose of the `.dc.a' internal pseudo-op. */
8766 x86_address_bytes (void)
8768 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8770 return stdoutput
->arch_info
->bits_per_address
/ 8;
8773 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8775 # define lex_got(reloc, adjust, types) NULL
8777 /* Parse operands of the form
8778 <symbol>@GOTOFF+<nnn>
8779 and similar .plt or .got references.
8781 If we find one, set up the correct relocation in RELOC and copy the
8782 input string, minus the `@GOTOFF' into a malloc'd buffer for
8783 parsing by the calling routine. Return this buffer, and if ADJUST
8784 is non-null set it to the length of the string we removed from the
8785 input line. Otherwise return NULL. */
8787 lex_got (enum bfd_reloc_code_real
*rel
,
8789 i386_operand_type
*types
)
8791 /* Some of the relocations depend on the size of what field is to
8792 be relocated. But in our callers i386_immediate and i386_displacement
8793 we don't yet know the operand size (this will be set by insn
8794 matching). Hence we record the word32 relocation here,
8795 and adjust the reloc according to the real size in reloc(). */
8796 static const struct {
8799 const enum bfd_reloc_code_real rel
[2];
8800 const i386_operand_type types64
;
8802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8803 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8805 OPERAND_TYPE_IMM32_64
},
8807 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8808 BFD_RELOC_X86_64_PLTOFF64
},
8809 OPERAND_TYPE_IMM64
},
8810 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8811 BFD_RELOC_X86_64_PLT32
},
8812 OPERAND_TYPE_IMM32_32S_DISP32
},
8813 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8814 BFD_RELOC_X86_64_GOTPLT64
},
8815 OPERAND_TYPE_IMM64_DISP64
},
8816 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8817 BFD_RELOC_X86_64_GOTOFF64
},
8818 OPERAND_TYPE_IMM64_DISP64
},
8819 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8820 BFD_RELOC_X86_64_GOTPCREL
},
8821 OPERAND_TYPE_IMM32_32S_DISP32
},
8822 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8823 BFD_RELOC_X86_64_TLSGD
},
8824 OPERAND_TYPE_IMM32_32S_DISP32
},
8825 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8826 _dummy_first_bfd_reloc_code_real
},
8827 OPERAND_TYPE_NONE
},
8828 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8829 BFD_RELOC_X86_64_TLSLD
},
8830 OPERAND_TYPE_IMM32_32S_DISP32
},
8831 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8832 BFD_RELOC_X86_64_GOTTPOFF
},
8833 OPERAND_TYPE_IMM32_32S_DISP32
},
8834 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8835 BFD_RELOC_X86_64_TPOFF32
},
8836 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8837 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8838 _dummy_first_bfd_reloc_code_real
},
8839 OPERAND_TYPE_NONE
},
8840 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8841 BFD_RELOC_X86_64_DTPOFF32
},
8842 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8843 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8844 _dummy_first_bfd_reloc_code_real
},
8845 OPERAND_TYPE_NONE
},
8846 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8847 _dummy_first_bfd_reloc_code_real
},
8848 OPERAND_TYPE_NONE
},
8849 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8850 BFD_RELOC_X86_64_GOT32
},
8851 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8852 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8853 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8854 OPERAND_TYPE_IMM32_32S_DISP32
},
8855 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8856 BFD_RELOC_X86_64_TLSDESC_CALL
},
8857 OPERAND_TYPE_IMM32_32S_DISP32
},
8862 #if defined (OBJ_MAYBE_ELF)
8867 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8868 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8871 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8873 int len
= gotrel
[j
].len
;
8874 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8876 if (gotrel
[j
].rel
[object_64bit
] != 0)
8879 char *tmpbuf
, *past_reloc
;
8881 *rel
= gotrel
[j
].rel
[object_64bit
];
8885 if (flag_code
!= CODE_64BIT
)
8887 types
->bitfield
.imm32
= 1;
8888 types
->bitfield
.disp32
= 1;
8891 *types
= gotrel
[j
].types64
;
8894 if (j
!= 0 && GOT_symbol
== NULL
)
8895 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8897 /* The length of the first part of our input line. */
8898 first
= cp
- input_line_pointer
;
8900 /* The second part goes from after the reloc token until
8901 (and including) an end_of_line char or comma. */
8902 past_reloc
= cp
+ 1 + len
;
8904 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8906 second
= cp
+ 1 - past_reloc
;
8908 /* Allocate and copy string. The trailing NUL shouldn't
8909 be necessary, but be safe. */
8910 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8911 memcpy (tmpbuf
, input_line_pointer
, first
);
8912 if (second
!= 0 && *past_reloc
!= ' ')
8913 /* Replace the relocation token with ' ', so that
8914 errors like foo@GOTOFF1 will be detected. */
8915 tmpbuf
[first
++] = ' ';
8917 /* Increment length by 1 if the relocation token is
8922 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8923 tmpbuf
[first
+ second
] = '\0';
8927 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8928 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8933 /* Might be a symbol version string. Don't as_bad here. */
8942 /* Parse operands of the form
8943 <symbol>@SECREL32+<nnn>
8945 If we find one, set up the correct relocation in RELOC and copy the
8946 input string, minus the `@SECREL32' into a malloc'd buffer for
8947 parsing by the calling routine. Return this buffer, and if ADJUST
8948 is non-null set it to the length of the string we removed from the
8949 input line. Otherwise return NULL.
8951 This function is copied from the ELF version above adjusted for PE targets. */
8954 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8955 int *adjust ATTRIBUTE_UNUSED
,
8956 i386_operand_type
*types
)
8962 const enum bfd_reloc_code_real rel
[2];
8963 const i386_operand_type types64
;
8967 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8968 BFD_RELOC_32_SECREL
},
8969 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8975 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8976 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8979 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8981 int len
= gotrel
[j
].len
;
8983 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8985 if (gotrel
[j
].rel
[object_64bit
] != 0)
8988 char *tmpbuf
, *past_reloc
;
8990 *rel
= gotrel
[j
].rel
[object_64bit
];
8996 if (flag_code
!= CODE_64BIT
)
8998 types
->bitfield
.imm32
= 1;
8999 types
->bitfield
.disp32
= 1;
9002 *types
= gotrel
[j
].types64
;
9005 /* The length of the first part of our input line. */
9006 first
= cp
- input_line_pointer
;
9008 /* The second part goes from after the reloc token until
9009 (and including) an end_of_line char or comma. */
9010 past_reloc
= cp
+ 1 + len
;
9012 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9014 second
= cp
+ 1 - past_reloc
;
9016 /* Allocate and copy string. The trailing NUL shouldn't
9017 be necessary, but be safe. */
9018 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9019 memcpy (tmpbuf
, input_line_pointer
, first
);
9020 if (second
!= 0 && *past_reloc
!= ' ')
9021 /* Replace the relocation token with ' ', so that
9022 errors like foo@SECLREL321 will be detected. */
9023 tmpbuf
[first
++] = ' ';
9024 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9025 tmpbuf
[first
+ second
] = '\0';
9029 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9030 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9035 /* Might be a symbol version string. Don't as_bad here. */
9041 bfd_reloc_code_real_type
9042 x86_cons (expressionS
*exp
, int size
)
9044 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9046 intel_syntax
= -intel_syntax
;
9049 if (size
== 4 || (object_64bit
&& size
== 8))
9051 /* Handle @GOTOFF and the like in an expression. */
9053 char *gotfree_input_line
;
9056 save
= input_line_pointer
;
9057 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9058 if (gotfree_input_line
)
9059 input_line_pointer
= gotfree_input_line
;
9063 if (gotfree_input_line
)
9065 /* expression () has merrily parsed up to the end of line,
9066 or a comma - in the wrong buffer. Transfer how far
9067 input_line_pointer has moved to the right buffer. */
9068 input_line_pointer
= (save
9069 + (input_line_pointer
- gotfree_input_line
)
9071 free (gotfree_input_line
);
9072 if (exp
->X_op
== O_constant
9073 || exp
->X_op
== O_absent
9074 || exp
->X_op
== O_illegal
9075 || exp
->X_op
== O_register
9076 || exp
->X_op
== O_big
)
9078 char c
= *input_line_pointer
;
9079 *input_line_pointer
= 0;
9080 as_bad (_("missing or invalid expression `%s'"), save
);
9081 *input_line_pointer
= c
;
9083 else if ((got_reloc
== BFD_RELOC_386_PLT32
9084 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9085 && exp
->X_op
!= O_symbol
)
9087 char c
= *input_line_pointer
;
9088 *input_line_pointer
= 0;
9089 as_bad (_("invalid PLT expression `%s'"), save
);
9090 *input_line_pointer
= c
;
9097 intel_syntax
= -intel_syntax
;
9100 i386_intel_simplify (exp
);
9106 signed_cons (int size
)
9108 if (flag_code
== CODE_64BIT
)
9116 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9123 if (exp
.X_op
== O_symbol
)
9124 exp
.X_op
= O_secrel
;
9126 emit_expr (&exp
, 4);
9128 while (*input_line_pointer
++ == ',');
9130 input_line_pointer
--;
9131 demand_empty_rest_of_line ();
9135 /* Handle Vector operations. */
9138 check_VecOperations (char *op_string
, char *op_end
)
9140 const reg_entry
*mask
;
9145 && (op_end
== NULL
|| op_string
< op_end
))
9148 if (*op_string
== '{')
9152 /* Check broadcasts. */
9153 if (strncmp (op_string
, "1to", 3) == 0)
9158 goto duplicated_vec_op
;
9161 if (*op_string
== '8')
9163 else if (*op_string
== '4')
9165 else if (*op_string
== '2')
9167 else if (*op_string
== '1'
9168 && *(op_string
+1) == '6')
9175 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9180 broadcast_op
.type
= bcst_type
;
9181 broadcast_op
.operand
= this_operand
;
9182 broadcast_op
.bytes
= 0;
9183 i
.broadcast
= &broadcast_op
;
9185 /* Check masking operation. */
9186 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9188 /* k0 can't be used for write mask. */
9189 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9191 as_bad (_("`%s%s' can't be used for write mask"),
9192 register_prefix
, mask
->reg_name
);
9198 mask_op
.mask
= mask
;
9199 mask_op
.zeroing
= 0;
9200 mask_op
.operand
= this_operand
;
9206 goto duplicated_vec_op
;
9208 i
.mask
->mask
= mask
;
9210 /* Only "{z}" is allowed here. No need to check
9211 zeroing mask explicitly. */
9212 if (i
.mask
->operand
!= this_operand
)
9214 as_bad (_("invalid write mask `%s'"), saved
);
9221 /* Check zeroing-flag for masking operation. */
9222 else if (*op_string
== 'z')
9226 mask_op
.mask
= NULL
;
9227 mask_op
.zeroing
= 1;
9228 mask_op
.operand
= this_operand
;
9233 if (i
.mask
->zeroing
)
9236 as_bad (_("duplicated `%s'"), saved
);
9240 i
.mask
->zeroing
= 1;
9242 /* Only "{%k}" is allowed here. No need to check mask
9243 register explicitly. */
9244 if (i
.mask
->operand
!= this_operand
)
9246 as_bad (_("invalid zeroing-masking `%s'"),
9255 goto unknown_vec_op
;
9257 if (*op_string
!= '}')
9259 as_bad (_("missing `}' in `%s'"), saved
);
9264 /* Strip whitespace since the addition of pseudo prefixes
9265 changed how the scrubber treats '{'. */
9266 if (is_space_char (*op_string
))
9272 /* We don't know this one. */
9273 as_bad (_("unknown vector operation: `%s'"), saved
);
9277 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9279 as_bad (_("zeroing-masking only allowed with write mask"));
9287 i386_immediate (char *imm_start
)
9289 char *save_input_line_pointer
;
9290 char *gotfree_input_line
;
9293 i386_operand_type types
;
9295 operand_type_set (&types
, ~0);
9297 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9299 as_bad (_("at most %d immediate operands are allowed"),
9300 MAX_IMMEDIATE_OPERANDS
);
9304 exp
= &im_expressions
[i
.imm_operands
++];
9305 i
.op
[this_operand
].imms
= exp
;
9307 if (is_space_char (*imm_start
))
9310 save_input_line_pointer
= input_line_pointer
;
9311 input_line_pointer
= imm_start
;
9313 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9314 if (gotfree_input_line
)
9315 input_line_pointer
= gotfree_input_line
;
9317 exp_seg
= expression (exp
);
9321 /* Handle vector operations. */
9322 if (*input_line_pointer
== '{')
9324 input_line_pointer
= check_VecOperations (input_line_pointer
,
9326 if (input_line_pointer
== NULL
)
9330 if (*input_line_pointer
)
9331 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9333 input_line_pointer
= save_input_line_pointer
;
9334 if (gotfree_input_line
)
9336 free (gotfree_input_line
);
9338 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9339 exp
->X_op
= O_illegal
;
9342 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9346 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9347 i386_operand_type types
, const char *imm_start
)
9349 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9352 as_bad (_("missing or invalid immediate expression `%s'"),
9356 else if (exp
->X_op
== O_constant
)
9358 /* Size it properly later. */
9359 i
.types
[this_operand
].bitfield
.imm64
= 1;
9360 /* If not 64bit, sign extend val. */
9361 if (flag_code
!= CODE_64BIT
9362 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9364 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9366 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9367 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9368 && exp_seg
!= absolute_section
9369 && exp_seg
!= text_section
9370 && exp_seg
!= data_section
9371 && exp_seg
!= bss_section
9372 && exp_seg
!= undefined_section
9373 && !bfd_is_com_section (exp_seg
))
9375 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9379 else if (!intel_syntax
&& exp_seg
== reg_section
)
9382 as_bad (_("illegal immediate register operand %s"), imm_start
);
9387 /* This is an address. The size of the address will be
9388 determined later, depending on destination register,
9389 suffix, or the default for the section. */
9390 i
.types
[this_operand
].bitfield
.imm8
= 1;
9391 i
.types
[this_operand
].bitfield
.imm16
= 1;
9392 i
.types
[this_operand
].bitfield
.imm32
= 1;
9393 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9394 i
.types
[this_operand
].bitfield
.imm64
= 1;
9395 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9403 i386_scale (char *scale
)
9406 char *save
= input_line_pointer
;
9408 input_line_pointer
= scale
;
9409 val
= get_absolute_expression ();
9414 i
.log2_scale_factor
= 0;
9417 i
.log2_scale_factor
= 1;
9420 i
.log2_scale_factor
= 2;
9423 i
.log2_scale_factor
= 3;
9427 char sep
= *input_line_pointer
;
9429 *input_line_pointer
= '\0';
9430 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9432 *input_line_pointer
= sep
;
9433 input_line_pointer
= save
;
9437 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9439 as_warn (_("scale factor of %d without an index register"),
9440 1 << i
.log2_scale_factor
);
9441 i
.log2_scale_factor
= 0;
9443 scale
= input_line_pointer
;
9444 input_line_pointer
= save
;
9449 i386_displacement (char *disp_start
, char *disp_end
)
9453 char *save_input_line_pointer
;
9454 char *gotfree_input_line
;
9456 i386_operand_type bigdisp
, types
= anydisp
;
9459 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9461 as_bad (_("at most %d displacement operands are allowed"),
9462 MAX_MEMORY_OPERANDS
);
9466 operand_type_set (&bigdisp
, 0);
9467 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9468 || (!current_templates
->start
->opcode_modifier
.jump
9469 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9471 bigdisp
.bitfield
.disp32
= 1;
9472 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9473 if (flag_code
== CODE_64BIT
)
9477 bigdisp
.bitfield
.disp32s
= 1;
9478 bigdisp
.bitfield
.disp64
= 1;
9481 else if ((flag_code
== CODE_16BIT
) ^ override
)
9483 bigdisp
.bitfield
.disp32
= 0;
9484 bigdisp
.bitfield
.disp16
= 1;
9489 /* For PC-relative branches, the width of the displacement
9490 is dependent upon data size, not address size. */
9491 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9492 if (flag_code
== CODE_64BIT
)
9494 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9495 bigdisp
.bitfield
.disp16
= 1;
9498 bigdisp
.bitfield
.disp32
= 1;
9499 bigdisp
.bitfield
.disp32s
= 1;
9505 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9507 : LONG_MNEM_SUFFIX
));
9508 bigdisp
.bitfield
.disp32
= 1;
9509 if ((flag_code
== CODE_16BIT
) ^ override
)
9511 bigdisp
.bitfield
.disp32
= 0;
9512 bigdisp
.bitfield
.disp16
= 1;
9516 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9519 exp
= &disp_expressions
[i
.disp_operands
];
9520 i
.op
[this_operand
].disps
= exp
;
9522 save_input_line_pointer
= input_line_pointer
;
9523 input_line_pointer
= disp_start
;
9524 END_STRING_AND_SAVE (disp_end
);
9526 #ifndef GCC_ASM_O_HACK
9527 #define GCC_ASM_O_HACK 0
9530 END_STRING_AND_SAVE (disp_end
+ 1);
9531 if (i
.types
[this_operand
].bitfield
.baseIndex
9532 && displacement_string_end
[-1] == '+')
9534 /* This hack is to avoid a warning when using the "o"
9535 constraint within gcc asm statements.
9538 #define _set_tssldt_desc(n,addr,limit,type) \
9539 __asm__ __volatile__ ( \
9541 "movw %w1,2+%0\n\t" \
9543 "movb %b1,4+%0\n\t" \
9544 "movb %4,5+%0\n\t" \
9545 "movb $0,6+%0\n\t" \
9546 "movb %h1,7+%0\n\t" \
9548 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9550 This works great except that the output assembler ends
9551 up looking a bit weird if it turns out that there is
9552 no offset. You end up producing code that looks like:
9565 So here we provide the missing zero. */
9567 *displacement_string_end
= '0';
9570 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9571 if (gotfree_input_line
)
9572 input_line_pointer
= gotfree_input_line
;
9574 exp_seg
= expression (exp
);
9577 if (*input_line_pointer
)
9578 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9580 RESTORE_END_STRING (disp_end
+ 1);
9582 input_line_pointer
= save_input_line_pointer
;
9583 if (gotfree_input_line
)
9585 free (gotfree_input_line
);
9587 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9588 exp
->X_op
= O_illegal
;
9591 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9593 RESTORE_END_STRING (disp_end
);
9599 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9600 i386_operand_type types
, const char *disp_start
)
9602 i386_operand_type bigdisp
;
9605 /* We do this to make sure that the section symbol is in
9606 the symbol table. We will ultimately change the relocation
9607 to be relative to the beginning of the section. */
9608 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9609 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9610 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9612 if (exp
->X_op
!= O_symbol
)
9615 if (S_IS_LOCAL (exp
->X_add_symbol
)
9616 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9617 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9618 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9619 exp
->X_op
= O_subtract
;
9620 exp
->X_op_symbol
= GOT_symbol
;
9621 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9622 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9623 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9624 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9626 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9629 else if (exp
->X_op
== O_absent
9630 || exp
->X_op
== O_illegal
9631 || exp
->X_op
== O_big
)
9634 as_bad (_("missing or invalid displacement expression `%s'"),
9639 else if (flag_code
== CODE_64BIT
9640 && !i
.prefix
[ADDR_PREFIX
]
9641 && exp
->X_op
== O_constant
)
9643 /* Since displacement is signed extended to 64bit, don't allow
9644 disp32 and turn off disp32s if they are out of range. */
9645 i
.types
[this_operand
].bitfield
.disp32
= 0;
9646 if (!fits_in_signed_long (exp
->X_add_number
))
9648 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9649 if (i
.types
[this_operand
].bitfield
.baseindex
)
9651 as_bad (_("0x%lx out range of signed 32bit displacement"),
9652 (long) exp
->X_add_number
);
9658 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9659 else if (exp
->X_op
!= O_constant
9660 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9661 && exp_seg
!= absolute_section
9662 && exp_seg
!= text_section
9663 && exp_seg
!= data_section
9664 && exp_seg
!= bss_section
9665 && exp_seg
!= undefined_section
9666 && !bfd_is_com_section (exp_seg
))
9668 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9673 /* Check if this is a displacement only operand. */
9674 bigdisp
= i
.types
[this_operand
];
9675 bigdisp
.bitfield
.disp8
= 0;
9676 bigdisp
.bitfield
.disp16
= 0;
9677 bigdisp
.bitfield
.disp32
= 0;
9678 bigdisp
.bitfield
.disp32s
= 0;
9679 bigdisp
.bitfield
.disp64
= 0;
9680 if (operand_type_all_zero (&bigdisp
))
9681 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9687 /* Return the active addressing mode, taking address override and
9688 registers forming the address into consideration. Update the
9689 address override prefix if necessary. */
9691 static enum flag_code
9692 i386_addressing_mode (void)
9694 enum flag_code addr_mode
;
9696 if (i
.prefix
[ADDR_PREFIX
])
9697 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9700 addr_mode
= flag_code
;
9702 #if INFER_ADDR_PREFIX
9703 if (i
.mem_operands
== 0)
9705 /* Infer address prefix from the first memory operand. */
9706 const reg_entry
*addr_reg
= i
.base_reg
;
9708 if (addr_reg
== NULL
)
9709 addr_reg
= i
.index_reg
;
9713 if (addr_reg
->reg_type
.bitfield
.dword
)
9714 addr_mode
= CODE_32BIT
;
9715 else if (flag_code
!= CODE_64BIT
9716 && addr_reg
->reg_type
.bitfield
.word
)
9717 addr_mode
= CODE_16BIT
;
9719 if (addr_mode
!= flag_code
)
9721 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9723 /* Change the size of any displacement too. At most one
9724 of Disp16 or Disp32 is set.
9725 FIXME. There doesn't seem to be any real need for
9726 separate Disp16 and Disp32 flags. The same goes for
9727 Imm16 and Imm32. Removing them would probably clean
9728 up the code quite a lot. */
9729 if (flag_code
!= CODE_64BIT
9730 && (i
.types
[this_operand
].bitfield
.disp16
9731 || i
.types
[this_operand
].bitfield
.disp32
))
9732 i
.types
[this_operand
]
9733 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9743 /* Make sure the memory operand we've been dealt is valid.
9744 Return 1 on success, 0 on a failure. */
9747 i386_index_check (const char *operand_string
)
9749 const char *kind
= "base/index";
9750 enum flag_code addr_mode
= i386_addressing_mode ();
9752 if (current_templates
->start
->opcode_modifier
.isstring
9753 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9754 && (current_templates
->end
[-1].opcode_modifier
.isstring
9757 /* Memory operands of string insns are special in that they only allow
9758 a single register (rDI, rSI, or rBX) as their memory address. */
9759 const reg_entry
*expected_reg
;
9760 static const char *di_si
[][2] =
9766 static const char *bx
[] = { "ebx", "bx", "rbx" };
9768 kind
= "string address";
9770 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9772 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
9776 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
9777 || ((!i
.mem_operands
!= !intel_syntax
)
9778 && current_templates
->end
[-1].operand_types
[1]
9779 .bitfield
.baseindex
))
9781 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
9784 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9786 if (i
.base_reg
!= expected_reg
9788 || operand_type_check (i
.types
[this_operand
], disp
))
9790 /* The second memory operand must have the same size as
9794 && !((addr_mode
== CODE_64BIT
9795 && i
.base_reg
->reg_type
.bitfield
.qword
)
9796 || (addr_mode
== CODE_32BIT
9797 ? i
.base_reg
->reg_type
.bitfield
.dword
9798 : i
.base_reg
->reg_type
.bitfield
.word
)))
9801 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9803 intel_syntax
? '[' : '(',
9805 expected_reg
->reg_name
,
9806 intel_syntax
? ']' : ')');
9813 as_bad (_("`%s' is not a valid %s expression"),
9814 operand_string
, kind
);
9819 if (addr_mode
!= CODE_16BIT
)
9821 /* 32-bit/64-bit checks. */
9823 && ((addr_mode
== CODE_64BIT
9824 ? !i
.base_reg
->reg_type
.bitfield
.qword
9825 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9826 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9827 || i
.base_reg
->reg_num
== RegIZ
))
9829 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9830 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9831 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9832 && ((addr_mode
== CODE_64BIT
9833 ? !i
.index_reg
->reg_type
.bitfield
.qword
9834 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9835 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9838 /* bndmk, bndldx, and bndstx have special restrictions. */
9839 if (current_templates
->start
->base_opcode
== 0xf30f1b
9840 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9842 /* They cannot use RIP-relative addressing. */
9843 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9845 as_bad (_("`%s' cannot be used here"), operand_string
);
9849 /* bndldx and bndstx ignore their scale factor. */
9850 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9851 && i
.log2_scale_factor
)
9852 as_warn (_("register scaling is being ignored here"));
9857 /* 16-bit checks. */
9859 && (!i
.base_reg
->reg_type
.bitfield
.word
9860 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9862 && (!i
.index_reg
->reg_type
.bitfield
.word
9863 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9865 && i
.base_reg
->reg_num
< 6
9866 && i
.index_reg
->reg_num
>= 6
9867 && i
.log2_scale_factor
== 0))))
9874 /* Handle vector immediates. */
9877 RC_SAE_immediate (const char *imm_start
)
9879 unsigned int match_found
, j
;
9880 const char *pstr
= imm_start
;
9888 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9890 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9894 rc_op
.type
= RC_NamesTable
[j
].type
;
9895 rc_op
.operand
= this_operand
;
9896 i
.rounding
= &rc_op
;
9900 as_bad (_("duplicated `%s'"), imm_start
);
9903 pstr
+= RC_NamesTable
[j
].len
;
9913 as_bad (_("Missing '}': '%s'"), imm_start
);
9916 /* RC/SAE immediate string should contain nothing more. */;
9919 as_bad (_("Junk after '}': '%s'"), imm_start
);
9923 exp
= &im_expressions
[i
.imm_operands
++];
9924 i
.op
[this_operand
].imms
= exp
;
9926 exp
->X_op
= O_constant
;
9927 exp
->X_add_number
= 0;
9928 exp
->X_add_symbol
= (symbolS
*) 0;
9929 exp
->X_op_symbol
= (symbolS
*) 0;
9931 i
.types
[this_operand
].bitfield
.imm8
= 1;
9935 /* Only string instructions can have a second memory operand, so
9936 reduce current_templates to just those if it contains any. */
9938 maybe_adjust_templates (void)
9940 const insn_template
*t
;
9942 gas_assert (i
.mem_operands
== 1);
9944 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9945 if (t
->opcode_modifier
.isstring
)
9948 if (t
< current_templates
->end
)
9950 static templates aux_templates
;
9951 bfd_boolean recheck
;
9953 aux_templates
.start
= t
;
9954 for (; t
< current_templates
->end
; ++t
)
9955 if (!t
->opcode_modifier
.isstring
)
9957 aux_templates
.end
= t
;
9959 /* Determine whether to re-check the first memory operand. */
9960 recheck
= (aux_templates
.start
!= current_templates
->start
9961 || t
!= current_templates
->end
);
9963 current_templates
= &aux_templates
;
9968 if (i
.memop1_string
!= NULL
9969 && i386_index_check (i
.memop1_string
) == 0)
9978 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9982 i386_att_operand (char *operand_string
)
9986 char *op_string
= operand_string
;
9988 if (is_space_char (*op_string
))
9991 /* We check for an absolute prefix (differentiating,
9992 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9993 if (*op_string
== ABSOLUTE_PREFIX
)
9996 if (is_space_char (*op_string
))
9998 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10001 /* Check if operand is a register. */
10002 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10004 i386_operand_type temp
;
10006 /* Check for a segment override by searching for ':' after a
10007 segment register. */
10008 op_string
= end_op
;
10009 if (is_space_char (*op_string
))
10011 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10013 switch (r
->reg_num
)
10016 i
.seg
[i
.mem_operands
] = &es
;
10019 i
.seg
[i
.mem_operands
] = &cs
;
10022 i
.seg
[i
.mem_operands
] = &ss
;
10025 i
.seg
[i
.mem_operands
] = &ds
;
10028 i
.seg
[i
.mem_operands
] = &fs
;
10031 i
.seg
[i
.mem_operands
] = &gs
;
10035 /* Skip the ':' and whitespace. */
10037 if (is_space_char (*op_string
))
10040 if (!is_digit_char (*op_string
)
10041 && !is_identifier_char (*op_string
)
10042 && *op_string
!= '('
10043 && *op_string
!= ABSOLUTE_PREFIX
)
10045 as_bad (_("bad memory operand `%s'"), op_string
);
10048 /* Handle case of %es:*foo. */
10049 if (*op_string
== ABSOLUTE_PREFIX
)
10052 if (is_space_char (*op_string
))
10054 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10056 goto do_memory_reference
;
10059 /* Handle vector operations. */
10060 if (*op_string
== '{')
10062 op_string
= check_VecOperations (op_string
, NULL
);
10063 if (op_string
== NULL
)
10069 as_bad (_("junk `%s' after register"), op_string
);
10072 temp
= r
->reg_type
;
10073 temp
.bitfield
.baseindex
= 0;
10074 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10076 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10077 i
.op
[this_operand
].regs
= r
;
10080 else if (*op_string
== REGISTER_PREFIX
)
10082 as_bad (_("bad register name `%s'"), op_string
);
10085 else if (*op_string
== IMMEDIATE_PREFIX
)
10088 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10090 as_bad (_("immediate operand illegal with absolute jump"));
10093 if (!i386_immediate (op_string
))
10096 else if (RC_SAE_immediate (operand_string
))
10098 /* If it is a RC or SAE immediate, do nothing. */
10101 else if (is_digit_char (*op_string
)
10102 || is_identifier_char (*op_string
)
10103 || *op_string
== '"'
10104 || *op_string
== '(')
10106 /* This is a memory reference of some sort. */
10109 /* Start and end of displacement string expression (if found). */
10110 char *displacement_string_start
;
10111 char *displacement_string_end
;
10114 do_memory_reference
:
10115 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10117 if ((i
.mem_operands
== 1
10118 && !current_templates
->start
->opcode_modifier
.isstring
)
10119 || i
.mem_operands
== 2)
10121 as_bad (_("too many memory references for `%s'"),
10122 current_templates
->start
->name
);
10126 /* Check for base index form. We detect the base index form by
10127 looking for an ')' at the end of the operand, searching
10128 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10130 base_string
= op_string
+ strlen (op_string
);
10132 /* Handle vector operations. */
10133 vop_start
= strchr (op_string
, '{');
10134 if (vop_start
&& vop_start
< base_string
)
10136 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10138 base_string
= vop_start
;
10142 if (is_space_char (*base_string
))
10145 /* If we only have a displacement, set-up for it to be parsed later. */
10146 displacement_string_start
= op_string
;
10147 displacement_string_end
= base_string
+ 1;
10149 if (*base_string
== ')')
10152 unsigned int parens_balanced
= 1;
10153 /* We've already checked that the number of left & right ()'s are
10154 equal, so this loop will not be infinite. */
10158 if (*base_string
== ')')
10160 if (*base_string
== '(')
10163 while (parens_balanced
);
10165 temp_string
= base_string
;
10167 /* Skip past '(' and whitespace. */
10169 if (is_space_char (*base_string
))
10172 if (*base_string
== ','
10173 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10176 displacement_string_end
= temp_string
;
10178 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10182 base_string
= end_op
;
10183 if (is_space_char (*base_string
))
10187 /* There may be an index reg or scale factor here. */
10188 if (*base_string
== ',')
10191 if (is_space_char (*base_string
))
10194 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10197 base_string
= end_op
;
10198 if (is_space_char (*base_string
))
10200 if (*base_string
== ',')
10203 if (is_space_char (*base_string
))
10206 else if (*base_string
!= ')')
10208 as_bad (_("expecting `,' or `)' "
10209 "after index register in `%s'"),
10214 else if (*base_string
== REGISTER_PREFIX
)
10216 end_op
= strchr (base_string
, ',');
10219 as_bad (_("bad register name `%s'"), base_string
);
10223 /* Check for scale factor. */
10224 if (*base_string
!= ')')
10226 char *end_scale
= i386_scale (base_string
);
10231 base_string
= end_scale
;
10232 if (is_space_char (*base_string
))
10234 if (*base_string
!= ')')
10236 as_bad (_("expecting `)' "
10237 "after scale factor in `%s'"),
10242 else if (!i
.index_reg
)
10244 as_bad (_("expecting index register or scale factor "
10245 "after `,'; got '%c'"),
10250 else if (*base_string
!= ')')
10252 as_bad (_("expecting `,' or `)' "
10253 "after base register in `%s'"),
10258 else if (*base_string
== REGISTER_PREFIX
)
10260 end_op
= strchr (base_string
, ',');
10263 as_bad (_("bad register name `%s'"), base_string
);
10268 /* If there's an expression beginning the operand, parse it,
10269 assuming displacement_string_start and
10270 displacement_string_end are meaningful. */
10271 if (displacement_string_start
!= displacement_string_end
)
10273 if (!i386_displacement (displacement_string_start
,
10274 displacement_string_end
))
10278 /* Special case for (%dx) while doing input/output op. */
10280 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10281 && i
.base_reg
->reg_type
.bitfield
.word
10282 && i
.index_reg
== 0
10283 && i
.log2_scale_factor
== 0
10284 && i
.seg
[i
.mem_operands
] == 0
10285 && !operand_type_check (i
.types
[this_operand
], disp
))
10287 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10291 if (i386_index_check (operand_string
) == 0)
10293 i
.flags
[this_operand
] |= Operand_Mem
;
10294 if (i
.mem_operands
== 0)
10295 i
.memop1_string
= xstrdup (operand_string
);
10300 /* It's not a memory operand; argh! */
10301 as_bad (_("invalid char %s beginning operand %d `%s'"),
10302 output_invalid (*op_string
),
10307 return 1; /* Normal return. */
10310 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10311 that an rs_machine_dependent frag may reach. */
10314 i386_frag_max_var (fragS
*frag
)
10316 /* The only relaxable frags are for jumps.
10317 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10318 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10319 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10324 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10326 /* STT_GNU_IFUNC symbol must go through PLT. */
10327 if ((symbol_get_bfdsym (fr_symbol
)->flags
10328 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10331 if (!S_IS_EXTERNAL (fr_symbol
))
10332 /* Symbol may be weak or local. */
10333 return !S_IS_WEAK (fr_symbol
);
10335 /* Global symbols with non-default visibility can't be preempted. */
10336 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10339 if (fr_var
!= NO_RELOC
)
10340 switch ((enum bfd_reloc_code_real
) fr_var
)
10342 case BFD_RELOC_386_PLT32
:
10343 case BFD_RELOC_X86_64_PLT32
:
10344 /* Symbol with PLT relocation may be preempted. */
10350 /* Global symbols with default visibility in a shared library may be
10351 preempted by another definition. */
10356 /* md_estimate_size_before_relax()
10358 Called just before relax() for rs_machine_dependent frags. The x86
10359 assembler uses these frags to handle variable size jump
10362 Any symbol that is now undefined will not become defined.
10363 Return the correct fr_subtype in the frag.
10364 Return the initial "guess for variable size of frag" to caller.
10365 The guess is actually the growth beyond the fixed part. Whatever
10366 we do to grow the fixed or variable part contributes to our
10370 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10372 /* We've already got fragP->fr_subtype right; all we have to do is
10373 check for un-relaxable symbols. On an ELF system, we can't relax
10374 an externally visible symbol, because it may be overridden by a
10376 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10379 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10382 #if defined (OBJ_COFF) && defined (TE_PE)
10383 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10384 && S_IS_WEAK (fragP
->fr_symbol
))
10388 /* Symbol is undefined in this segment, or we need to keep a
10389 reloc so that weak symbols can be overridden. */
10390 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10391 enum bfd_reloc_code_real reloc_type
;
10392 unsigned char *opcode
;
10395 if (fragP
->fr_var
!= NO_RELOC
)
10396 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10397 else if (size
== 2)
10398 reloc_type
= BFD_RELOC_16_PCREL
;
10399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10400 else if (need_plt32_p (fragP
->fr_symbol
))
10401 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10404 reloc_type
= BFD_RELOC_32_PCREL
;
10406 old_fr_fix
= fragP
->fr_fix
;
10407 opcode
= (unsigned char *) fragP
->fr_opcode
;
10409 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10412 /* Make jmp (0xeb) a (d)word displacement jump. */
10414 fragP
->fr_fix
+= size
;
10415 fix_new (fragP
, old_fr_fix
, size
,
10417 fragP
->fr_offset
, 1,
10423 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10425 /* Negate the condition, and branch past an
10426 unconditional jump. */
10429 /* Insert an unconditional jump. */
10431 /* We added two extra opcode bytes, and have a two byte
10433 fragP
->fr_fix
+= 2 + 2;
10434 fix_new (fragP
, old_fr_fix
+ 2, 2,
10436 fragP
->fr_offset
, 1,
10440 /* Fall through. */
10443 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10447 fragP
->fr_fix
+= 1;
10448 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10450 fragP
->fr_offset
, 1,
10451 BFD_RELOC_8_PCREL
);
10452 fixP
->fx_signed
= 1;
10456 /* This changes the byte-displacement jump 0x7N
10457 to the (d)word-displacement jump 0x0f,0x8N. */
10458 opcode
[1] = opcode
[0] + 0x10;
10459 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10460 /* We've added an opcode byte. */
10461 fragP
->fr_fix
+= 1 + size
;
10462 fix_new (fragP
, old_fr_fix
+ 1, size
,
10464 fragP
->fr_offset
, 1,
10469 BAD_CASE (fragP
->fr_subtype
);
10473 return fragP
->fr_fix
- old_fr_fix
;
10476 /* Guess size depending on current relax state. Initially the relax
10477 state will correspond to a short jump and we return 1, because
10478 the variable part of the frag (the branch offset) is one byte
10479 long. However, we can relax a section more than once and in that
10480 case we must either set fr_subtype back to the unrelaxed state,
10481 or return the value for the appropriate branch. */
10482 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10485 /* Called after relax() is finished.
10487 In: Address of frag.
10488 fr_type == rs_machine_dependent.
10489 fr_subtype is what the address relaxed to.
10491 Out: Any fixSs and constants are set up.
10492 Caller will turn frag into a ".space 0". */
10495 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10498 unsigned char *opcode
;
10499 unsigned char *where_to_put_displacement
= NULL
;
10500 offsetT target_address
;
10501 offsetT opcode_address
;
10502 unsigned int extension
= 0;
10503 offsetT displacement_from_opcode_start
;
10505 opcode
= (unsigned char *) fragP
->fr_opcode
;
10507 /* Address we want to reach in file space. */
10508 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10510 /* Address opcode resides at in file space. */
10511 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10513 /* Displacement from opcode start to fill into instruction. */
10514 displacement_from_opcode_start
= target_address
- opcode_address
;
10516 if ((fragP
->fr_subtype
& BIG
) == 0)
10518 /* Don't have to change opcode. */
10519 extension
= 1; /* 1 opcode + 1 displacement */
10520 where_to_put_displacement
= &opcode
[1];
10524 if (no_cond_jump_promotion
10525 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10526 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10527 _("long jump required"));
10529 switch (fragP
->fr_subtype
)
10531 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10532 extension
= 4; /* 1 opcode + 4 displacement */
10534 where_to_put_displacement
= &opcode
[1];
10537 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10538 extension
= 2; /* 1 opcode + 2 displacement */
10540 where_to_put_displacement
= &opcode
[1];
10543 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10544 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10545 extension
= 5; /* 2 opcode + 4 displacement */
10546 opcode
[1] = opcode
[0] + 0x10;
10547 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10548 where_to_put_displacement
= &opcode
[2];
10551 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10552 extension
= 3; /* 2 opcode + 2 displacement */
10553 opcode
[1] = opcode
[0] + 0x10;
10554 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10555 where_to_put_displacement
= &opcode
[2];
10558 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10563 where_to_put_displacement
= &opcode
[3];
10567 BAD_CASE (fragP
->fr_subtype
);
10572 /* If size if less then four we are sure that the operand fits,
10573 but if it's 4, then it could be that the displacement is larger
10575 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10577 && ((addressT
) (displacement_from_opcode_start
- extension
10578 + ((addressT
) 1 << 31))
10579 > (((addressT
) 2 << 31) - 1)))
10581 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10582 _("jump target out of range"));
10583 /* Make us emit 0. */
10584 displacement_from_opcode_start
= extension
;
10586 /* Now put displacement after opcode. */
10587 md_number_to_chars ((char *) where_to_put_displacement
,
10588 (valueT
) (displacement_from_opcode_start
- extension
),
10589 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10590 fragP
->fr_fix
+= extension
;
10593 /* Apply a fixup (fixP) to segment data, once it has been determined
10594 by our caller that we have all the info we need to fix it up.
10596 Parameter valP is the pointer to the value of the bits.
10598 On the 386, immediates, displacements, and data pointers are all in
10599 the same (little-endian) format, so we don't need to care about which
10600 we are handling. */
10603 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10605 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10606 valueT value
= *valP
;
10608 #if !defined (TE_Mach)
10609 if (fixP
->fx_pcrel
)
10611 switch (fixP
->fx_r_type
)
10617 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10620 case BFD_RELOC_X86_64_32S
:
10621 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10624 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10627 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10632 if (fixP
->fx_addsy
!= NULL
10633 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10634 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10635 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10636 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10637 && !use_rela_relocations
)
10639 /* This is a hack. There should be a better way to handle this.
10640 This covers for the fact that bfd_install_relocation will
10641 subtract the current location (for partial_inplace, PC relative
10642 relocations); see more below. */
10646 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10649 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10651 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10654 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10656 if ((sym_seg
== seg
10657 || (symbol_section_p (fixP
->fx_addsy
)
10658 && sym_seg
!= absolute_section
))
10659 && !generic_force_reloc (fixP
))
10661 /* Yes, we add the values in twice. This is because
10662 bfd_install_relocation subtracts them out again. I think
10663 bfd_install_relocation is broken, but I don't dare change
10665 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10669 #if defined (OBJ_COFF) && defined (TE_PE)
10670 /* For some reason, the PE format does not store a
10671 section address offset for a PC relative symbol. */
10672 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10673 || S_IS_WEAK (fixP
->fx_addsy
))
10674 value
+= md_pcrel_from (fixP
);
10677 #if defined (OBJ_COFF) && defined (TE_PE)
10678 if (fixP
->fx_addsy
!= NULL
10679 && S_IS_WEAK (fixP
->fx_addsy
)
10680 /* PR 16858: Do not modify weak function references. */
10681 && ! fixP
->fx_pcrel
)
10683 #if !defined (TE_PEP)
10684 /* For x86 PE weak function symbols are neither PC-relative
10685 nor do they set S_IS_FUNCTION. So the only reliable way
10686 to detect them is to check the flags of their containing
10688 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10689 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10693 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10697 /* Fix a few things - the dynamic linker expects certain values here,
10698 and we must not disappoint it. */
10699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10700 if (IS_ELF
&& fixP
->fx_addsy
)
10701 switch (fixP
->fx_r_type
)
10703 case BFD_RELOC_386_PLT32
:
10704 case BFD_RELOC_X86_64_PLT32
:
10705 /* Make the jump instruction point to the address of the operand.
10706 At runtime we merely add the offset to the actual PLT entry.
10707 NB: Subtract the offset size only for jump instructions. */
10708 if (fixP
->fx_pcrel
)
10712 case BFD_RELOC_386_TLS_GD
:
10713 case BFD_RELOC_386_TLS_LDM
:
10714 case BFD_RELOC_386_TLS_IE_32
:
10715 case BFD_RELOC_386_TLS_IE
:
10716 case BFD_RELOC_386_TLS_GOTIE
:
10717 case BFD_RELOC_386_TLS_GOTDESC
:
10718 case BFD_RELOC_X86_64_TLSGD
:
10719 case BFD_RELOC_X86_64_TLSLD
:
10720 case BFD_RELOC_X86_64_GOTTPOFF
:
10721 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10722 value
= 0; /* Fully resolved at runtime. No addend. */
10724 case BFD_RELOC_386_TLS_LE
:
10725 case BFD_RELOC_386_TLS_LDO_32
:
10726 case BFD_RELOC_386_TLS_LE_32
:
10727 case BFD_RELOC_X86_64_DTPOFF32
:
10728 case BFD_RELOC_X86_64_DTPOFF64
:
10729 case BFD_RELOC_X86_64_TPOFF32
:
10730 case BFD_RELOC_X86_64_TPOFF64
:
10731 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10734 case BFD_RELOC_386_TLS_DESC_CALL
:
10735 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10736 value
= 0; /* Fully resolved at runtime. No addend. */
10737 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10741 case BFD_RELOC_VTABLE_INHERIT
:
10742 case BFD_RELOC_VTABLE_ENTRY
:
10749 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10751 #endif /* !defined (TE_Mach) */
10753 /* Are we finished with this relocation now? */
10754 if (fixP
->fx_addsy
== NULL
)
10756 #if defined (OBJ_COFF) && defined (TE_PE)
10757 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10760 /* Remember value for tc_gen_reloc. */
10761 fixP
->fx_addnumber
= value
;
10762 /* Clear out the frag for now. */
10766 else if (use_rela_relocations
)
10768 fixP
->fx_no_overflow
= 1;
10769 /* Remember value for tc_gen_reloc. */
10770 fixP
->fx_addnumber
= value
;
10774 md_number_to_chars (p
, value
, fixP
->fx_size
);
10778 md_atof (int type
, char *litP
, int *sizeP
)
10780 /* This outputs the LITTLENUMs in REVERSE order;
10781 in accord with the bigendian 386. */
10782 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10785 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10788 output_invalid (int c
)
10791 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10794 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10795 "(0x%x)", (unsigned char) c
);
10796 return output_invalid_buf
;
10799 /* REG_STRING starts *before* REGISTER_PREFIX. */
10801 static const reg_entry
*
10802 parse_real_register (char *reg_string
, char **end_op
)
10804 char *s
= reg_string
;
10806 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10807 const reg_entry
*r
;
10809 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10810 if (*s
== REGISTER_PREFIX
)
10813 if (is_space_char (*s
))
10816 p
= reg_name_given
;
10817 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10819 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10820 return (const reg_entry
*) NULL
;
10824 /* For naked regs, make sure that we are not dealing with an identifier.
10825 This prevents confusing an identifier like `eax_var' with register
10827 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10828 return (const reg_entry
*) NULL
;
10832 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10834 /* Handle floating point regs, allowing spaces in the (i) part. */
10835 if (r
== i386_regtab
/* %st is first entry of table */)
10837 if (!cpu_arch_flags
.bitfield
.cpu8087
10838 && !cpu_arch_flags
.bitfield
.cpu287
10839 && !cpu_arch_flags
.bitfield
.cpu387
)
10840 return (const reg_entry
*) NULL
;
10842 if (is_space_char (*s
))
10847 if (is_space_char (*s
))
10849 if (*s
>= '0' && *s
<= '7')
10851 int fpr
= *s
- '0';
10853 if (is_space_char (*s
))
10858 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10863 /* We have "%st(" then garbage. */
10864 return (const reg_entry
*) NULL
;
10868 if (r
== NULL
|| allow_pseudo_reg
)
10871 if (operand_type_all_zero (&r
->reg_type
))
10872 return (const reg_entry
*) NULL
;
10874 if ((r
->reg_type
.bitfield
.dword
10875 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
10876 || r
->reg_type
.bitfield
.class == RegCR
10877 || r
->reg_type
.bitfield
.class == RegDR
10878 || r
->reg_type
.bitfield
.class == RegTR
)
10879 && !cpu_arch_flags
.bitfield
.cpui386
)
10880 return (const reg_entry
*) NULL
;
10882 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
10883 return (const reg_entry
*) NULL
;
10885 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10887 if (r
->reg_type
.bitfield
.zmmword
10888 || r
->reg_type
.bitfield
.class == RegMask
)
10889 return (const reg_entry
*) NULL
;
10891 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10893 if (r
->reg_type
.bitfield
.ymmword
)
10894 return (const reg_entry
*) NULL
;
10896 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10897 return (const reg_entry
*) NULL
;
10901 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10902 return (const reg_entry
*) NULL
;
10904 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10905 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10906 return (const reg_entry
*) NULL
;
10908 /* Upper 16 vector registers are only available with VREX in 64bit
10909 mode, and require EVEX encoding. */
10910 if (r
->reg_flags
& RegVRex
)
10912 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10913 || flag_code
!= CODE_64BIT
)
10914 return (const reg_entry
*) NULL
;
10916 i
.vec_encoding
= vex_encoding_evex
;
10919 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10920 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
10921 && flag_code
!= CODE_64BIT
)
10922 return (const reg_entry
*) NULL
;
10924 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
10926 return (const reg_entry
*) NULL
;
10931 /* REG_STRING starts *before* REGISTER_PREFIX. */
10933 static const reg_entry
*
10934 parse_register (char *reg_string
, char **end_op
)
10936 const reg_entry
*r
;
10938 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10939 r
= parse_real_register (reg_string
, end_op
);
10944 char *save
= input_line_pointer
;
10948 input_line_pointer
= reg_string
;
10949 c
= get_symbol_name (®_string
);
10950 symbolP
= symbol_find (reg_string
);
10951 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10953 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10955 know (e
->X_op
== O_register
);
10956 know (e
->X_add_number
>= 0
10957 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10958 r
= i386_regtab
+ e
->X_add_number
;
10959 if ((r
->reg_flags
& RegVRex
))
10960 i
.vec_encoding
= vex_encoding_evex
;
10961 *end_op
= input_line_pointer
;
10963 *input_line_pointer
= c
;
10964 input_line_pointer
= save
;
10970 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10972 const reg_entry
*r
;
10973 char *end
= input_line_pointer
;
10976 r
= parse_register (name
, &input_line_pointer
);
10977 if (r
&& end
<= input_line_pointer
)
10979 *nextcharP
= *input_line_pointer
;
10980 *input_line_pointer
= 0;
10981 e
->X_op
= O_register
;
10982 e
->X_add_number
= r
- i386_regtab
;
10985 input_line_pointer
= end
;
10987 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10991 md_operand (expressionS
*e
)
10994 const reg_entry
*r
;
10996 switch (*input_line_pointer
)
10998 case REGISTER_PREFIX
:
10999 r
= parse_real_register (input_line_pointer
, &end
);
11002 e
->X_op
= O_register
;
11003 e
->X_add_number
= r
- i386_regtab
;
11004 input_line_pointer
= end
;
11009 gas_assert (intel_syntax
);
11010 end
= input_line_pointer
++;
11012 if (*input_line_pointer
== ']')
11014 ++input_line_pointer
;
11015 e
->X_op_symbol
= make_expr_symbol (e
);
11016 e
->X_add_symbol
= NULL
;
11017 e
->X_add_number
= 0;
11022 e
->X_op
= O_absent
;
11023 input_line_pointer
= end
;
11030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11031 const char *md_shortopts
= "kVQ:sqnO::";
11033 const char *md_shortopts
= "qnO::";
11036 #define OPTION_32 (OPTION_MD_BASE + 0)
11037 #define OPTION_64 (OPTION_MD_BASE + 1)
11038 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11039 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11040 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11041 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11042 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11043 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11044 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11045 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11046 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11047 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11048 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11049 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11050 #define OPTION_X32 (OPTION_MD_BASE + 14)
11051 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11052 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11053 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11054 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11055 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11056 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11057 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11058 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11059 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11060 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11061 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11062 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11064 struct option md_longopts
[] =
11066 {"32", no_argument
, NULL
, OPTION_32
},
11067 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11068 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11069 {"64", no_argument
, NULL
, OPTION_64
},
11071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11072 {"x32", no_argument
, NULL
, OPTION_X32
},
11073 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11074 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11076 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11077 {"march", required_argument
, NULL
, OPTION_MARCH
},
11078 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11079 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11080 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11081 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11082 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11083 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11084 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11085 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11086 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11087 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11088 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11089 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11090 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11091 # if defined (TE_PE) || defined (TE_PEP)
11092 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11094 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11095 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11096 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11097 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11098 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11099 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11100 {NULL
, no_argument
, NULL
, 0}
11102 size_t md_longopts_size
= sizeof (md_longopts
);
11105 md_parse_option (int c
, const char *arg
)
11108 char *arch
, *next
, *saved
;
11113 optimize_align_code
= 0;
11117 quiet_warnings
= 1;
11120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11121 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11122 should be emitted or not. FIXME: Not implemented. */
11124 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11128 /* -V: SVR4 argument to print version ID. */
11130 print_version_id ();
11133 /* -k: Ignore for FreeBSD compatibility. */
11138 /* -s: On i386 Solaris, this tells the native assembler to use
11139 .stab instead of .stab.excl. We always use .stab anyhow. */
11142 case OPTION_MSHARED
:
11146 case OPTION_X86_USED_NOTE
:
11147 if (strcasecmp (arg
, "yes") == 0)
11149 else if (strcasecmp (arg
, "no") == 0)
11152 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11157 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11158 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11161 const char **list
, **l
;
11163 list
= bfd_target_list ();
11164 for (l
= list
; *l
!= NULL
; l
++)
11165 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11166 || strcmp (*l
, "coff-x86-64") == 0
11167 || strcmp (*l
, "pe-x86-64") == 0
11168 || strcmp (*l
, "pei-x86-64") == 0
11169 || strcmp (*l
, "mach-o-x86-64") == 0)
11171 default_arch
= "x86_64";
11175 as_fatal (_("no compiled in support for x86_64"));
11181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11185 const char **list
, **l
;
11187 list
= bfd_target_list ();
11188 for (l
= list
; *l
!= NULL
; l
++)
11189 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11191 default_arch
= "x86_64:32";
11195 as_fatal (_("no compiled in support for 32bit x86_64"));
11199 as_fatal (_("32bit x86_64 is only supported for ELF"));
11204 default_arch
= "i386";
11207 case OPTION_DIVIDE
:
11208 #ifdef SVR4_COMMENT_CHARS
11213 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11215 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11219 i386_comment_chars
= n
;
11225 saved
= xstrdup (arg
);
11227 /* Allow -march=+nosse. */
11233 as_fatal (_("invalid -march= option: `%s'"), arg
);
11234 next
= strchr (arch
, '+');
11237 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11239 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11242 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11245 cpu_arch_name
= cpu_arch
[j
].name
;
11246 cpu_sub_arch_name
= NULL
;
11247 cpu_arch_flags
= cpu_arch
[j
].flags
;
11248 cpu_arch_isa
= cpu_arch
[j
].type
;
11249 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11250 if (!cpu_arch_tune_set
)
11252 cpu_arch_tune
= cpu_arch_isa
;
11253 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11257 else if (*cpu_arch
[j
].name
== '.'
11258 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11260 /* ISA extension. */
11261 i386_cpu_flags flags
;
11263 flags
= cpu_flags_or (cpu_arch_flags
,
11264 cpu_arch
[j
].flags
);
11266 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11268 if (cpu_sub_arch_name
)
11270 char *name
= cpu_sub_arch_name
;
11271 cpu_sub_arch_name
= concat (name
,
11273 (const char *) NULL
);
11277 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11278 cpu_arch_flags
= flags
;
11279 cpu_arch_isa_flags
= flags
;
11283 = cpu_flags_or (cpu_arch_isa_flags
,
11284 cpu_arch
[j
].flags
);
11289 if (j
>= ARRAY_SIZE (cpu_arch
))
11291 /* Disable an ISA extension. */
11292 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11293 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11295 i386_cpu_flags flags
;
11297 flags
= cpu_flags_and_not (cpu_arch_flags
,
11298 cpu_noarch
[j
].flags
);
11299 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11301 if (cpu_sub_arch_name
)
11303 char *name
= cpu_sub_arch_name
;
11304 cpu_sub_arch_name
= concat (arch
,
11305 (const char *) NULL
);
11309 cpu_sub_arch_name
= xstrdup (arch
);
11310 cpu_arch_flags
= flags
;
11311 cpu_arch_isa_flags
= flags
;
11316 if (j
>= ARRAY_SIZE (cpu_noarch
))
11317 j
= ARRAY_SIZE (cpu_arch
);
11320 if (j
>= ARRAY_SIZE (cpu_arch
))
11321 as_fatal (_("invalid -march= option: `%s'"), arg
);
11325 while (next
!= NULL
);
11331 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11332 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11334 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11336 cpu_arch_tune_set
= 1;
11337 cpu_arch_tune
= cpu_arch
[j
].type
;
11338 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11342 if (j
>= ARRAY_SIZE (cpu_arch
))
11343 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11346 case OPTION_MMNEMONIC
:
11347 if (strcasecmp (arg
, "att") == 0)
11348 intel_mnemonic
= 0;
11349 else if (strcasecmp (arg
, "intel") == 0)
11350 intel_mnemonic
= 1;
11352 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11355 case OPTION_MSYNTAX
:
11356 if (strcasecmp (arg
, "att") == 0)
11358 else if (strcasecmp (arg
, "intel") == 0)
11361 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11364 case OPTION_MINDEX_REG
:
11365 allow_index_reg
= 1;
11368 case OPTION_MNAKED_REG
:
11369 allow_naked_reg
= 1;
11372 case OPTION_MSSE2AVX
:
11376 case OPTION_MSSE_CHECK
:
11377 if (strcasecmp (arg
, "error") == 0)
11378 sse_check
= check_error
;
11379 else if (strcasecmp (arg
, "warning") == 0)
11380 sse_check
= check_warning
;
11381 else if (strcasecmp (arg
, "none") == 0)
11382 sse_check
= check_none
;
11384 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11387 case OPTION_MOPERAND_CHECK
:
11388 if (strcasecmp (arg
, "error") == 0)
11389 operand_check
= check_error
;
11390 else if (strcasecmp (arg
, "warning") == 0)
11391 operand_check
= check_warning
;
11392 else if (strcasecmp (arg
, "none") == 0)
11393 operand_check
= check_none
;
11395 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11398 case OPTION_MAVXSCALAR
:
11399 if (strcasecmp (arg
, "128") == 0)
11400 avxscalar
= vex128
;
11401 else if (strcasecmp (arg
, "256") == 0)
11402 avxscalar
= vex256
;
11404 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11407 case OPTION_MVEXWIG
:
11408 if (strcmp (arg
, "0") == 0)
11410 else if (strcmp (arg
, "1") == 0)
11413 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11416 case OPTION_MADD_BND_PREFIX
:
11417 add_bnd_prefix
= 1;
11420 case OPTION_MEVEXLIG
:
11421 if (strcmp (arg
, "128") == 0)
11422 evexlig
= evexl128
;
11423 else if (strcmp (arg
, "256") == 0)
11424 evexlig
= evexl256
;
11425 else if (strcmp (arg
, "512") == 0)
11426 evexlig
= evexl512
;
11428 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11431 case OPTION_MEVEXRCIG
:
11432 if (strcmp (arg
, "rne") == 0)
11434 else if (strcmp (arg
, "rd") == 0)
11436 else if (strcmp (arg
, "ru") == 0)
11438 else if (strcmp (arg
, "rz") == 0)
11441 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11444 case OPTION_MEVEXWIG
:
11445 if (strcmp (arg
, "0") == 0)
11447 else if (strcmp (arg
, "1") == 0)
11450 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11453 # if defined (TE_PE) || defined (TE_PEP)
11454 case OPTION_MBIG_OBJ
:
11459 case OPTION_MOMIT_LOCK_PREFIX
:
11460 if (strcasecmp (arg
, "yes") == 0)
11461 omit_lock_prefix
= 1;
11462 else if (strcasecmp (arg
, "no") == 0)
11463 omit_lock_prefix
= 0;
11465 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11468 case OPTION_MFENCE_AS_LOCK_ADD
:
11469 if (strcasecmp (arg
, "yes") == 0)
11471 else if (strcasecmp (arg
, "no") == 0)
11474 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11477 case OPTION_MRELAX_RELOCATIONS
:
11478 if (strcasecmp (arg
, "yes") == 0)
11479 generate_relax_relocations
= 1;
11480 else if (strcasecmp (arg
, "no") == 0)
11481 generate_relax_relocations
= 0;
11483 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11486 case OPTION_MAMD64
:
11490 case OPTION_MINTEL64
:
11498 /* Turn off -Os. */
11499 optimize_for_space
= 0;
11501 else if (*arg
== 's')
11503 optimize_for_space
= 1;
11504 /* Turn on all encoding optimizations. */
11505 optimize
= INT_MAX
;
11509 optimize
= atoi (arg
);
11510 /* Turn off -Os. */
11511 optimize_for_space
= 0;
11521 #define MESSAGE_TEMPLATE \
11525 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11526 int *left_p
, const char *name
, int len
)
11528 int size
= sizeof (MESSAGE_TEMPLATE
);
11529 int left
= *left_p
;
11531 /* Reserve 2 spaces for ", " or ",\0" */
11534 /* Check if there is any room. */
11542 p
= mempcpy (p
, name
, len
);
11546 /* Output the current message now and start a new one. */
11549 fprintf (stream
, "%s\n", message
);
11551 left
= size
- (start
- message
) - len
- 2;
11553 gas_assert (left
>= 0);
11555 p
= mempcpy (p
, name
, len
);
11563 show_arch (FILE *stream
, int ext
, int check
)
11565 static char message
[] = MESSAGE_TEMPLATE
;
11566 char *start
= message
+ 27;
11568 int size
= sizeof (MESSAGE_TEMPLATE
);
11575 left
= size
- (start
- message
);
11576 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11578 /* Should it be skipped? */
11579 if (cpu_arch
[j
].skip
)
11582 name
= cpu_arch
[j
].name
;
11583 len
= cpu_arch
[j
].len
;
11586 /* It is an extension. Skip if we aren't asked to show it. */
11597 /* It is an processor. Skip if we show only extension. */
11600 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11602 /* It is an impossible processor - skip. */
11606 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11609 /* Display disabled extensions. */
11611 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11613 name
= cpu_noarch
[j
].name
;
11614 len
= cpu_noarch
[j
].len
;
11615 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11620 fprintf (stream
, "%s\n", message
);
11624 md_show_usage (FILE *stream
)
11626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11627 fprintf (stream
, _("\
11628 -Qy, -Qn ignored\n\
11629 -V print assembler version number\n\
11632 fprintf (stream
, _("\
11633 -n Do not optimize code alignment\n\
11634 -q quieten some warnings\n"));
11635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11636 fprintf (stream
, _("\
11639 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11640 || defined (TE_PE) || defined (TE_PEP))
11641 fprintf (stream
, _("\
11642 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11644 #ifdef SVR4_COMMENT_CHARS
11645 fprintf (stream
, _("\
11646 --divide do not treat `/' as a comment character\n"));
11648 fprintf (stream
, _("\
11649 --divide ignored\n"));
11651 fprintf (stream
, _("\
11652 -march=CPU[,+EXTENSION...]\n\
11653 generate code for CPU and EXTENSION, CPU is one of:\n"));
11654 show_arch (stream
, 0, 1);
11655 fprintf (stream
, _("\
11656 EXTENSION is combination of:\n"));
11657 show_arch (stream
, 1, 0);
11658 fprintf (stream
, _("\
11659 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11660 show_arch (stream
, 0, 0);
11661 fprintf (stream
, _("\
11662 -msse2avx encode SSE instructions with VEX prefix\n"));
11663 fprintf (stream
, _("\
11664 -msse-check=[none|error|warning] (default: warning)\n\
11665 check SSE instructions\n"));
11666 fprintf (stream
, _("\
11667 -moperand-check=[none|error|warning] (default: warning)\n\
11668 check operand combinations for validity\n"));
11669 fprintf (stream
, _("\
11670 -mavxscalar=[128|256] (default: 128)\n\
11671 encode scalar AVX instructions with specific vector\n\
11673 fprintf (stream
, _("\
11674 -mvexwig=[0|1] (default: 0)\n\
11675 encode VEX instructions with specific VEX.W value\n\
11676 for VEX.W bit ignored instructions\n"));
11677 fprintf (stream
, _("\
11678 -mevexlig=[128|256|512] (default: 128)\n\
11679 encode scalar EVEX instructions with specific vector\n\
11681 fprintf (stream
, _("\
11682 -mevexwig=[0|1] (default: 0)\n\
11683 encode EVEX instructions with specific EVEX.W value\n\
11684 for EVEX.W bit ignored instructions\n"));
11685 fprintf (stream
, _("\
11686 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11687 encode EVEX instructions with specific EVEX.RC value\n\
11688 for SAE-only ignored instructions\n"));
11689 fprintf (stream
, _("\
11690 -mmnemonic=[att|intel] "));
11691 if (SYSV386_COMPAT
)
11692 fprintf (stream
, _("(default: att)\n"));
11694 fprintf (stream
, _("(default: intel)\n"));
11695 fprintf (stream
, _("\
11696 use AT&T/Intel mnemonic\n"));
11697 fprintf (stream
, _("\
11698 -msyntax=[att|intel] (default: att)\n\
11699 use AT&T/Intel syntax\n"));
11700 fprintf (stream
, _("\
11701 -mindex-reg support pseudo index registers\n"));
11702 fprintf (stream
, _("\
11703 -mnaked-reg don't require `%%' prefix for registers\n"));
11704 fprintf (stream
, _("\
11705 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11707 fprintf (stream
, _("\
11708 -mshared disable branch optimization for shared code\n"));
11709 fprintf (stream
, _("\
11710 -mx86-used-note=[no|yes] "));
11711 if (DEFAULT_X86_USED_NOTE
)
11712 fprintf (stream
, _("(default: yes)\n"));
11714 fprintf (stream
, _("(default: no)\n"));
11715 fprintf (stream
, _("\
11716 generate x86 used ISA and feature properties\n"));
11718 #if defined (TE_PE) || defined (TE_PEP)
11719 fprintf (stream
, _("\
11720 -mbig-obj generate big object files\n"));
11722 fprintf (stream
, _("\
11723 -momit-lock-prefix=[no|yes] (default: no)\n\
11724 strip all lock prefixes\n"));
11725 fprintf (stream
, _("\
11726 -mfence-as-lock-add=[no|yes] (default: no)\n\
11727 encode lfence, mfence and sfence as\n\
11728 lock addl $0x0, (%%{re}sp)\n"));
11729 fprintf (stream
, _("\
11730 -mrelax-relocations=[no|yes] "));
11731 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11732 fprintf (stream
, _("(default: yes)\n"));
11734 fprintf (stream
, _("(default: no)\n"));
11735 fprintf (stream
, _("\
11736 generate relax relocations\n"));
11737 fprintf (stream
, _("\
11738 -mamd64 accept only AMD64 ISA [default]\n"));
11739 fprintf (stream
, _("\
11740 -mintel64 accept only Intel64 ISA\n"));
11743 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11744 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11745 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11747 /* Pick the target format to use. */
11750 i386_target_format (void)
11752 if (!strncmp (default_arch
, "x86_64", 6))
11754 update_code_flag (CODE_64BIT
, 1);
11755 if (default_arch
[6] == '\0')
11756 x86_elf_abi
= X86_64_ABI
;
11758 x86_elf_abi
= X86_64_X32_ABI
;
11760 else if (!strcmp (default_arch
, "i386"))
11761 update_code_flag (CODE_32BIT
, 1);
11762 else if (!strcmp (default_arch
, "iamcu"))
11764 update_code_flag (CODE_32BIT
, 1);
11765 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11767 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11768 cpu_arch_name
= "iamcu";
11769 cpu_sub_arch_name
= NULL
;
11770 cpu_arch_flags
= iamcu_flags
;
11771 cpu_arch_isa
= PROCESSOR_IAMCU
;
11772 cpu_arch_isa_flags
= iamcu_flags
;
11773 if (!cpu_arch_tune_set
)
11775 cpu_arch_tune
= cpu_arch_isa
;
11776 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11779 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11780 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11784 as_fatal (_("unknown architecture"));
11786 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11787 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11788 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11789 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11791 switch (OUTPUT_FLAVOR
)
11793 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11794 case bfd_target_aout_flavour
:
11795 return AOUT_TARGET_FORMAT
;
11797 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11798 # if defined (TE_PE) || defined (TE_PEP)
11799 case bfd_target_coff_flavour
:
11800 if (flag_code
== CODE_64BIT
)
11801 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11804 # elif defined (TE_GO32)
11805 case bfd_target_coff_flavour
:
11806 return "coff-go32";
11808 case bfd_target_coff_flavour
:
11809 return "coff-i386";
11812 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11813 case bfd_target_elf_flavour
:
11815 const char *format
;
11817 switch (x86_elf_abi
)
11820 format
= ELF_TARGET_FORMAT
;
11823 use_rela_relocations
= 1;
11825 format
= ELF_TARGET_FORMAT64
;
11827 case X86_64_X32_ABI
:
11828 use_rela_relocations
= 1;
11830 disallow_64bit_reloc
= 1;
11831 format
= ELF_TARGET_FORMAT32
;
11834 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11836 if (x86_elf_abi
!= X86_64_ABI
)
11837 as_fatal (_("Intel L1OM is 64bit only"));
11838 return ELF_TARGET_L1OM_FORMAT
;
11840 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11842 if (x86_elf_abi
!= X86_64_ABI
)
11843 as_fatal (_("Intel K1OM is 64bit only"));
11844 return ELF_TARGET_K1OM_FORMAT
;
11846 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11848 if (x86_elf_abi
!= I386_ABI
)
11849 as_fatal (_("Intel MCU is 32bit only"));
11850 return ELF_TARGET_IAMCU_FORMAT
;
11856 #if defined (OBJ_MACH_O)
11857 case bfd_target_mach_o_flavour
:
11858 if (flag_code
== CODE_64BIT
)
11860 use_rela_relocations
= 1;
11862 return "mach-o-x86-64";
11865 return "mach-o-i386";
11873 #endif /* OBJ_MAYBE_ more than one */
11876 md_undefined_symbol (char *name
)
11878 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11879 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11880 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11881 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11885 if (symbol_find (name
))
11886 as_bad (_("GOT already in symbol table"));
11887 GOT_symbol
= symbol_new (name
, undefined_section
,
11888 (valueT
) 0, &zero_address_frag
);
11895 /* Round up a section size to the appropriate boundary. */
11898 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11900 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11901 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11903 /* For a.out, force the section size to be aligned. If we don't do
11904 this, BFD will align it for us, but it will not write out the
11905 final bytes of the section. This may be a bug in BFD, but it is
11906 easier to fix it here since that is how the other a.out targets
11910 align
= bfd_section_alignment (segment
);
11911 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11918 /* On the i386, PC-relative offsets are relative to the start of the
11919 next instruction. That is, the address of the offset, plus its
11920 size, since the offset is always the last part of the insn. */
11923 md_pcrel_from (fixS
*fixP
)
11925 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11931 s_bss (int ignore ATTRIBUTE_UNUSED
)
11935 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11937 obj_elf_section_change_hook ();
11939 temp
= get_absolute_expression ();
11940 subseg_set (bss_section
, (subsegT
) temp
);
11941 demand_empty_rest_of_line ();
11947 i386_validate_fix (fixS
*fixp
)
11949 if (fixp
->fx_subsy
)
11951 if (fixp
->fx_subsy
== GOT_symbol
)
11953 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11958 if (fixp
->fx_tcbit2
)
11959 fixp
->fx_r_type
= (fixp
->fx_tcbit
11960 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11961 : BFD_RELOC_X86_64_GOTPCRELX
);
11964 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11969 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11971 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11973 fixp
->fx_subsy
= 0;
11976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11977 else if (!object_64bit
)
11979 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11980 && fixp
->fx_tcbit2
)
11981 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11987 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11990 bfd_reloc_code_real_type code
;
11992 switch (fixp
->fx_r_type
)
11994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11995 case BFD_RELOC_SIZE32
:
11996 case BFD_RELOC_SIZE64
:
11997 if (S_IS_DEFINED (fixp
->fx_addsy
)
11998 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12000 /* Resolve size relocation against local symbol to size of
12001 the symbol plus addend. */
12002 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12003 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12004 && !fits_in_unsigned_long (value
))
12005 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12006 _("symbol size computation overflow"));
12007 fixp
->fx_addsy
= NULL
;
12008 fixp
->fx_subsy
= NULL
;
12009 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12013 /* Fall through. */
12015 case BFD_RELOC_X86_64_PLT32
:
12016 case BFD_RELOC_X86_64_GOT32
:
12017 case BFD_RELOC_X86_64_GOTPCREL
:
12018 case BFD_RELOC_X86_64_GOTPCRELX
:
12019 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12020 case BFD_RELOC_386_PLT32
:
12021 case BFD_RELOC_386_GOT32
:
12022 case BFD_RELOC_386_GOT32X
:
12023 case BFD_RELOC_386_GOTOFF
:
12024 case BFD_RELOC_386_GOTPC
:
12025 case BFD_RELOC_386_TLS_GD
:
12026 case BFD_RELOC_386_TLS_LDM
:
12027 case BFD_RELOC_386_TLS_LDO_32
:
12028 case BFD_RELOC_386_TLS_IE_32
:
12029 case BFD_RELOC_386_TLS_IE
:
12030 case BFD_RELOC_386_TLS_GOTIE
:
12031 case BFD_RELOC_386_TLS_LE_32
:
12032 case BFD_RELOC_386_TLS_LE
:
12033 case BFD_RELOC_386_TLS_GOTDESC
:
12034 case BFD_RELOC_386_TLS_DESC_CALL
:
12035 case BFD_RELOC_X86_64_TLSGD
:
12036 case BFD_RELOC_X86_64_TLSLD
:
12037 case BFD_RELOC_X86_64_DTPOFF32
:
12038 case BFD_RELOC_X86_64_DTPOFF64
:
12039 case BFD_RELOC_X86_64_GOTTPOFF
:
12040 case BFD_RELOC_X86_64_TPOFF32
:
12041 case BFD_RELOC_X86_64_TPOFF64
:
12042 case BFD_RELOC_X86_64_GOTOFF64
:
12043 case BFD_RELOC_X86_64_GOTPC32
:
12044 case BFD_RELOC_X86_64_GOT64
:
12045 case BFD_RELOC_X86_64_GOTPCREL64
:
12046 case BFD_RELOC_X86_64_GOTPC64
:
12047 case BFD_RELOC_X86_64_GOTPLT64
:
12048 case BFD_RELOC_X86_64_PLTOFF64
:
12049 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12050 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12051 case BFD_RELOC_RVA
:
12052 case BFD_RELOC_VTABLE_ENTRY
:
12053 case BFD_RELOC_VTABLE_INHERIT
:
12055 case BFD_RELOC_32_SECREL
:
12057 code
= fixp
->fx_r_type
;
12059 case BFD_RELOC_X86_64_32S
:
12060 if (!fixp
->fx_pcrel
)
12062 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12063 code
= fixp
->fx_r_type
;
12066 /* Fall through. */
12068 if (fixp
->fx_pcrel
)
12070 switch (fixp
->fx_size
)
12073 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12074 _("can not do %d byte pc-relative relocation"),
12076 code
= BFD_RELOC_32_PCREL
;
12078 case 1: code
= BFD_RELOC_8_PCREL
; break;
12079 case 2: code
= BFD_RELOC_16_PCREL
; break;
12080 case 4: code
= BFD_RELOC_32_PCREL
; break;
12082 case 8: code
= BFD_RELOC_64_PCREL
; break;
12088 switch (fixp
->fx_size
)
12091 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12092 _("can not do %d byte relocation"),
12094 code
= BFD_RELOC_32
;
12096 case 1: code
= BFD_RELOC_8
; break;
12097 case 2: code
= BFD_RELOC_16
; break;
12098 case 4: code
= BFD_RELOC_32
; break;
12100 case 8: code
= BFD_RELOC_64
; break;
12107 if ((code
== BFD_RELOC_32
12108 || code
== BFD_RELOC_32_PCREL
12109 || code
== BFD_RELOC_X86_64_32S
)
12111 && fixp
->fx_addsy
== GOT_symbol
)
12114 code
= BFD_RELOC_386_GOTPC
;
12116 code
= BFD_RELOC_X86_64_GOTPC32
;
12118 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12120 && fixp
->fx_addsy
== GOT_symbol
)
12122 code
= BFD_RELOC_X86_64_GOTPC64
;
12125 rel
= XNEW (arelent
);
12126 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12127 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12129 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12131 if (!use_rela_relocations
)
12133 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12134 vtable entry to be used in the relocation's section offset. */
12135 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12136 rel
->address
= fixp
->fx_offset
;
12137 #if defined (OBJ_COFF) && defined (TE_PE)
12138 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12139 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12144 /* Use the rela in 64bit mode. */
12147 if (disallow_64bit_reloc
)
12150 case BFD_RELOC_X86_64_DTPOFF64
:
12151 case BFD_RELOC_X86_64_TPOFF64
:
12152 case BFD_RELOC_64_PCREL
:
12153 case BFD_RELOC_X86_64_GOTOFF64
:
12154 case BFD_RELOC_X86_64_GOT64
:
12155 case BFD_RELOC_X86_64_GOTPCREL64
:
12156 case BFD_RELOC_X86_64_GOTPC64
:
12157 case BFD_RELOC_X86_64_GOTPLT64
:
12158 case BFD_RELOC_X86_64_PLTOFF64
:
12159 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12160 _("cannot represent relocation type %s in x32 mode"),
12161 bfd_get_reloc_code_name (code
));
12167 if (!fixp
->fx_pcrel
)
12168 rel
->addend
= fixp
->fx_offset
;
12172 case BFD_RELOC_X86_64_PLT32
:
12173 case BFD_RELOC_X86_64_GOT32
:
12174 case BFD_RELOC_X86_64_GOTPCREL
:
12175 case BFD_RELOC_X86_64_GOTPCRELX
:
12176 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12177 case BFD_RELOC_X86_64_TLSGD
:
12178 case BFD_RELOC_X86_64_TLSLD
:
12179 case BFD_RELOC_X86_64_GOTTPOFF
:
12180 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12181 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12182 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12185 rel
->addend
= (section
->vma
12187 + fixp
->fx_addnumber
12188 + md_pcrel_from (fixp
));
12193 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12194 if (rel
->howto
== NULL
)
12196 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12197 _("cannot represent relocation type %s"),
12198 bfd_get_reloc_code_name (code
));
12199 /* Set howto to a garbage value so that we can keep going. */
12200 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12201 gas_assert (rel
->howto
!= NULL
);
12207 #include "tc-i386-intel.c"
12210 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12212 int saved_naked_reg
;
12213 char saved_register_dot
;
12215 saved_naked_reg
= allow_naked_reg
;
12216 allow_naked_reg
= 1;
12217 saved_register_dot
= register_chars
['.'];
12218 register_chars
['.'] = '.';
12219 allow_pseudo_reg
= 1;
12220 expression_and_evaluate (exp
);
12221 allow_pseudo_reg
= 0;
12222 register_chars
['.'] = saved_register_dot
;
12223 allow_naked_reg
= saved_naked_reg
;
12225 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12227 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12229 exp
->X_op
= O_constant
;
12230 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12231 .dw2_regnum
[flag_code
>> 1];
12234 exp
->X_op
= O_illegal
;
12239 tc_x86_frame_initial_instructions (void)
12241 static unsigned int sp_regno
[2];
12243 if (!sp_regno
[flag_code
>> 1])
12245 char *saved_input
= input_line_pointer
;
12246 char sp
[][4] = {"esp", "rsp"};
12249 input_line_pointer
= sp
[flag_code
>> 1];
12250 tc_x86_parse_to_dw2regnum (&exp
);
12251 gas_assert (exp
.X_op
== O_constant
);
12252 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12253 input_line_pointer
= saved_input
;
12256 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12257 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12261 x86_dwarf2_addr_size (void)
12263 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12264 if (x86_elf_abi
== X86_64_X32_ABI
)
12267 return bfd_arch_bits_per_address (stdoutput
) / 8;
12271 i386_elf_section_type (const char *str
, size_t len
)
12273 if (flag_code
== CODE_64BIT
12274 && len
== sizeof ("unwind") - 1
12275 && strncmp (str
, "unwind", 6) == 0)
12276 return SHT_X86_64_UNWIND
;
12283 i386_solaris_fix_up_eh_frame (segT sec
)
12285 if (flag_code
== CODE_64BIT
)
12286 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12292 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12296 exp
.X_op
= O_secrel
;
12297 exp
.X_add_symbol
= symbol
;
12298 exp
.X_add_number
= 0;
12299 emit_expr (&exp
, size
);
12303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12304 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12307 x86_64_section_letter (int letter
, const char **ptr_msg
)
12309 if (flag_code
== CODE_64BIT
)
12312 return SHF_X86_64_LARGE
;
12314 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12317 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12322 x86_64_section_word (char *str
, size_t len
)
12324 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12325 return SHF_X86_64_LARGE
;
12331 handle_large_common (int small ATTRIBUTE_UNUSED
)
12333 if (flag_code
!= CODE_64BIT
)
12335 s_comm_internal (0, elf_common_parse
);
12336 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12340 static segT lbss_section
;
12341 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12342 asection
*saved_bss_section
= bss_section
;
12344 if (lbss_section
== NULL
)
12346 flagword applicable
;
12347 segT seg
= now_seg
;
12348 subsegT subseg
= now_subseg
;
12350 /* The .lbss section is for local .largecomm symbols. */
12351 lbss_section
= subseg_new (".lbss", 0);
12352 applicable
= bfd_applicable_section_flags (stdoutput
);
12353 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12354 seg_info (lbss_section
)->bss
= 1;
12356 subseg_set (seg
, subseg
);
12359 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12360 bss_section
= lbss_section
;
12362 s_comm_internal (0, elf_common_parse
);
12364 elf_com_section_ptr
= saved_com_section_ptr
;
12365 bss_section
= saved_bss_section
;
12368 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */