1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1094 static const noarch_entry cpu_noarch
[] =
1096 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1097 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1098 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1099 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1100 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1101 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1102 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1103 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1106 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1127 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1128 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1129 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1130 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1148 && *input_line_pointer
== ',')
1150 align
= parse_align (needs_align
- 1);
1152 if (align
== (addressT
) -1)
1167 bss_alloc (symbolP
, size
, align
);
1172 pe_lcomm (int needs_align
)
1174 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1178 const pseudo_typeS md_pseudo_table
[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes
, 0},
1183 {"align", s_align_ptwo
, 0},
1185 {"arch", set_cpu_arch
, 0},
1189 {"lcomm", pe_lcomm
, 1},
1191 {"ffloat", float_cons
, 'f'},
1192 {"dfloat", float_cons
, 'd'},
1193 {"tfloat", float_cons
, 'x'},
1195 {"slong", signed_cons
, 4},
1196 {"noopt", s_ignore
, 0},
1197 {"optim", s_ignore
, 0},
1198 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1199 {"code16", set_code_flag
, CODE_16BIT
},
1200 {"code32", set_code_flag
, CODE_32BIT
},
1202 {"code64", set_code_flag
, CODE_64BIT
},
1204 {"intel_syntax", set_intel_syntax
, 1},
1205 {"att_syntax", set_intel_syntax
, 0},
1206 {"intel_mnemonic", set_intel_mnemonic
, 1},
1207 {"att_mnemonic", set_intel_mnemonic
, 0},
1208 {"allow_index_reg", set_allow_index_reg
, 1},
1209 {"disallow_index_reg", set_allow_index_reg
, 0},
1210 {"sse_check", set_check
, 0},
1211 {"operand_check", set_check
, 1},
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 {"largecomm", handle_large_common
, 0},
1215 {"file", dwarf2_directive_file
, 0},
1216 {"loc", dwarf2_directive_loc
, 0},
1217 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1220 {"secrel32", pe_directive_secrel
, 0},
1225 /* For interface with expression (). */
1226 extern char *input_line_pointer
;
1228 /* Hash table for instruction mnemonic lookup. */
1229 static struct hash_control
*op_hash
;
1231 /* Hash table for register lookup. */
1232 static struct hash_control
*reg_hash
;
1234 /* Various efficient no-op patterns for aligning code labels.
1235 Note: Don't try to assemble the instructions in the comments.
1236 0L and 0w are not legal. */
1237 static const unsigned char f32_1
[] =
1239 static const unsigned char f32_2
[] =
1240 {0x66,0x90}; /* xchg %ax,%ax */
1241 static const unsigned char f32_3
[] =
1242 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1243 static const unsigned char f32_4
[] =
1244 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1245 static const unsigned char f32_6
[] =
1246 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1247 static const unsigned char f32_7
[] =
1248 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1249 static const unsigned char f16_3
[] =
1250 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1251 static const unsigned char f16_4
[] =
1252 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1253 static const unsigned char jump_disp8
[] =
1254 {0xeb}; /* jmp disp8 */
1255 static const unsigned char jump32_disp32
[] =
1256 {0xe9}; /* jmp disp32 */
1257 static const unsigned char jump16_disp32
[] =
1258 {0x66,0xe9}; /* jmp disp32 */
1259 /* 32-bit NOPs patterns. */
1260 static const unsigned char *const f32_patt
[] = {
1261 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1263 /* 16-bit NOPs patterns. */
1264 static const unsigned char *const f16_patt
[] = {
1265 f32_1
, f32_2
, f16_3
, f16_4
1267 /* nopl (%[re]ax) */
1268 static const unsigned char alt_3
[] =
1270 /* nopl 0(%[re]ax) */
1271 static const unsigned char alt_4
[] =
1272 {0x0f,0x1f,0x40,0x00};
1273 /* nopl 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_5
[] =
1275 {0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopw 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_6
[] =
1278 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopl 0L(%[re]ax) */
1280 static const unsigned char alt_7
[] =
1281 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1282 /* nopl 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_8
[] =
1284 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_9
[] =
1287 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_10
[] =
1290 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* data16 nopw %cs:0L(%eax,%eax,1) */
1292 static const unsigned char alt_11
[] =
1293 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* 32-bit and 64-bit NOPs patterns. */
1295 static const unsigned char *const alt_patt
[] = {
1296 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1297 alt_9
, alt_10
, alt_11
1300 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1301 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1304 i386_output_nops (char *where
, const unsigned char *const *patt
,
1305 int count
, int max_single_nop_size
)
1308 /* Place the longer NOP first. */
1311 const unsigned char *nops
;
1313 if (max_single_nop_size
< 1)
1315 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1316 max_single_nop_size
);
1320 nops
= patt
[max_single_nop_size
- 1];
1322 /* Use the smaller one if the requsted one isn't available. */
1325 max_single_nop_size
--;
1326 nops
= patt
[max_single_nop_size
- 1];
1329 last
= count
% max_single_nop_size
;
1332 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1333 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1337 nops
= patt
[last
- 1];
1340 /* Use the smaller one plus one-byte NOP if the needed one
1343 nops
= patt
[last
- 1];
1344 memcpy (where
+ offset
, nops
, last
);
1345 where
[offset
+ last
] = *patt
[0];
1348 memcpy (where
+ offset
, nops
, last
);
1353 fits_in_imm7 (offsetT num
)
1355 return (num
& 0x7f) == num
;
1359 fits_in_imm31 (offsetT num
)
1361 return (num
& 0x7fffffff) == num
;
1364 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1365 single NOP instruction LIMIT. */
1368 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1370 const unsigned char *const *patt
= NULL
;
1371 int max_single_nop_size
;
1372 /* Maximum number of NOPs before switching to jump over NOPs. */
1373 int max_number_of_nops
;
1375 switch (fragP
->fr_type
)
1384 /* We need to decide which NOP sequence to use for 32bit and
1385 64bit. When -mtune= is used:
1387 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1388 PROCESSOR_GENERIC32, f32_patt will be used.
1389 2. For the rest, alt_patt will be used.
1391 When -mtune= isn't used, alt_patt will be used if
1392 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1395 When -march= or .arch is used, we can't use anything beyond
1396 cpu_arch_isa_flags. */
1398 if (flag_code
== CODE_16BIT
)
1401 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1402 /* Limit number of NOPs to 2 in 16-bit mode. */
1403 max_number_of_nops
= 2;
1407 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1409 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1410 switch (cpu_arch_tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* We use cpu_arch_isa_flags to check if we SHOULD
1414 optimize with nops. */
1415 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1420 case PROCESSOR_PENTIUM4
:
1421 case PROCESSOR_NOCONA
:
1422 case PROCESSOR_CORE
:
1423 case PROCESSOR_CORE2
:
1424 case PROCESSOR_COREI7
:
1425 case PROCESSOR_L1OM
:
1426 case PROCESSOR_K1OM
:
1427 case PROCESSOR_GENERIC64
:
1429 case PROCESSOR_ATHLON
:
1431 case PROCESSOR_AMDFAM10
:
1433 case PROCESSOR_ZNVER
:
1437 case PROCESSOR_I386
:
1438 case PROCESSOR_I486
:
1439 case PROCESSOR_PENTIUM
:
1440 case PROCESSOR_PENTIUMPRO
:
1441 case PROCESSOR_IAMCU
:
1442 case PROCESSOR_GENERIC32
:
1449 switch (fragP
->tc_frag_data
.tune
)
1451 case PROCESSOR_UNKNOWN
:
1452 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1453 PROCESSOR_UNKNOWN. */
1457 case PROCESSOR_I386
:
1458 case PROCESSOR_I486
:
1459 case PROCESSOR_PENTIUM
:
1460 case PROCESSOR_IAMCU
:
1462 case PROCESSOR_ATHLON
:
1464 case PROCESSOR_AMDFAM10
:
1466 case PROCESSOR_ZNVER
:
1468 case PROCESSOR_GENERIC32
:
1469 /* We use cpu_arch_isa_flags to check if we CAN optimize
1471 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1476 case PROCESSOR_PENTIUMPRO
:
1477 case PROCESSOR_PENTIUM4
:
1478 case PROCESSOR_NOCONA
:
1479 case PROCESSOR_CORE
:
1480 case PROCESSOR_CORE2
:
1481 case PROCESSOR_COREI7
:
1482 case PROCESSOR_L1OM
:
1483 case PROCESSOR_K1OM
:
1484 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1489 case PROCESSOR_GENERIC64
:
1495 if (patt
== f32_patt
)
1497 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1498 /* Limit number of NOPs to 2 for older processors. */
1499 max_number_of_nops
= 2;
1503 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1504 /* Limit number of NOPs to 7 for newer processors. */
1505 max_number_of_nops
= 7;
1510 limit
= max_single_nop_size
;
1512 if (fragP
->fr_type
== rs_fill_nop
)
1514 /* Output NOPs for .nop directive. */
1515 if (limit
> max_single_nop_size
)
1517 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1518 _("invalid single nop size: %d "
1519 "(expect within [0, %d])"),
1520 limit
, max_single_nop_size
);
1525 fragP
->fr_var
= count
;
1527 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1529 /* Generate jump over NOPs. */
1530 offsetT disp
= count
- 2;
1531 if (fits_in_imm7 (disp
))
1533 /* Use "jmp disp8" if possible. */
1535 where
[0] = jump_disp8
[0];
1541 unsigned int size_of_jump
;
1543 if (flag_code
== CODE_16BIT
)
1545 where
[0] = jump16_disp32
[0];
1546 where
[1] = jump16_disp32
[1];
1551 where
[0] = jump32_disp32
[0];
1555 count
-= size_of_jump
+ 4;
1556 if (!fits_in_imm31 (count
))
1558 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1559 _("jump over nop padding out of range"));
1563 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1564 where
+= size_of_jump
+ 4;
1568 /* Generate multiple NOPs. */
1569 i386_output_nops (where
, patt
, count
, limit
);
1573 operand_type_all_zero (const union i386_operand_type
*x
)
1575 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1595 switch (ARRAY_SIZE(x
->array
))
1613 operand_type_equal (const union i386_operand_type
*x
,
1614 const union i386_operand_type
*y
)
1616 switch (ARRAY_SIZE(x
->array
))
1619 if (x
->array
[2] != y
->array
[2])
1623 if (x
->array
[1] != y
->array
[1])
1627 return x
->array
[0] == y
->array
[0];
1635 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1637 switch (ARRAY_SIZE(x
->array
))
1652 return !x
->array
[0];
1659 cpu_flags_equal (const union i386_cpu_flags
*x
,
1660 const union i386_cpu_flags
*y
)
1662 switch (ARRAY_SIZE(x
->array
))
1665 if (x
->array
[3] != y
->array
[3])
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1687 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1688 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1691 static INLINE i386_cpu_flags
1692 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1694 switch (ARRAY_SIZE (x
.array
))
1697 x
.array
[3] &= y
.array
[3];
1700 x
.array
[2] &= y
.array
[2];
1703 x
.array
[1] &= y
.array
[1];
1706 x
.array
[0] &= y
.array
[0];
1714 static INLINE i386_cpu_flags
1715 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1717 switch (ARRAY_SIZE (x
.array
))
1720 x
.array
[3] |= y
.array
[3];
1723 x
.array
[2] |= y
.array
[2];
1726 x
.array
[1] |= y
.array
[1];
1729 x
.array
[0] |= y
.array
[0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1740 switch (ARRAY_SIZE (x
.array
))
1743 x
.array
[3] &= ~y
.array
[3];
1746 x
.array
[2] &= ~y
.array
[2];
1749 x
.array
[1] &= ~y
.array
[1];
1752 x
.array
[0] &= ~y
.array
[0];
1760 #define CPU_FLAGS_ARCH_MATCH 0x1
1761 #define CPU_FLAGS_64BIT_MATCH 0x2
1763 #define CPU_FLAGS_PERFECT_MATCH \
1764 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1766 /* Return CPU flags match bits. */
1769 cpu_flags_match (const insn_template
*t
)
1771 i386_cpu_flags x
= t
->cpu_flags
;
1772 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1774 x
.bitfield
.cpu64
= 0;
1775 x
.bitfield
.cpuno64
= 0;
1777 if (cpu_flags_all_zero (&x
))
1779 /* This instruction is available on all archs. */
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 /* This instruction is available only on some archs. */
1785 i386_cpu_flags cpu
= cpu_arch_flags
;
1787 /* AVX512VL is no standalone feature - match it and then strip it. */
1788 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1790 x
.bitfield
.cpuavx512vl
= 0;
1792 cpu
= cpu_flags_and (x
, cpu
);
1793 if (!cpu_flags_all_zero (&cpu
))
1795 if (x
.bitfield
.cpuavx
)
1797 /* We need to check a few extra flags with AVX. */
1798 if (cpu
.bitfield
.cpuavx
1799 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1800 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1801 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1802 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1803 match
|= CPU_FLAGS_ARCH_MATCH
;
1805 else if (x
.bitfield
.cpuavx512f
)
1807 /* We need to check a few extra flags with AVX512F. */
1808 if (cpu
.bitfield
.cpuavx512f
1809 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1810 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1811 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 match
|= CPU_FLAGS_ARCH_MATCH
;
1821 static INLINE i386_operand_type
1822 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[2] &= y
.array
[2];
1830 x
.array
[1] &= y
.array
[1];
1833 x
.array
[0] &= y
.array
[0];
1841 static INLINE i386_operand_type
1842 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1844 switch (ARRAY_SIZE (x
.array
))
1847 x
.array
[2] &= ~y
.array
[2];
1850 x
.array
[1] &= ~y
.array
[1];
1853 x
.array
[0] &= ~y
.array
[0];
1861 static INLINE i386_operand_type
1862 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[2] |= y
.array
[2];
1870 x
.array
[1] |= y
.array
[1];
1873 x
.array
[0] |= y
.array
[0];
1881 static INLINE i386_operand_type
1882 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1884 switch (ARRAY_SIZE (x
.array
))
1887 x
.array
[2] ^= y
.array
[2];
1890 x
.array
[1] ^= y
.array
[1];
1893 x
.array
[0] ^= y
.array
[0];
1901 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1902 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1903 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1904 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1905 static const i386_operand_type anydisp
1906 = OPERAND_TYPE_ANYDISP
;
1907 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1908 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1909 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1910 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1911 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1912 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1913 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1914 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1915 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1916 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1917 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1918 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1929 operand_type_check (i386_operand_type t
, enum operand_type c
)
1934 return t
.bitfield
.reg
;
1937 return (t
.bitfield
.imm8
1941 || t
.bitfield
.imm32s
1942 || t
.bitfield
.imm64
);
1945 return (t
.bitfield
.disp8
1946 || t
.bitfield
.disp16
1947 || t
.bitfield
.disp32
1948 || t
.bitfield
.disp32s
1949 || t
.bitfield
.disp64
);
1952 return (t
.bitfield
.disp8
1953 || t
.bitfield
.disp16
1954 || t
.bitfield
.disp32
1955 || t
.bitfield
.disp32s
1956 || t
.bitfield
.disp64
1957 || t
.bitfield
.baseindex
);
1966 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1967 between operand GIVEN and opeand WANTED for instruction template T. */
1970 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.byte
1974 && !t
->operand_types
[wanted
].bitfield
.byte
)
1975 || (i
.types
[given
].bitfield
.word
1976 && !t
->operand_types
[wanted
].bitfield
.word
)
1977 || (i
.types
[given
].bitfield
.dword
1978 && !t
->operand_types
[wanted
].bitfield
.dword
)
1979 || (i
.types
[given
].bitfield
.qword
1980 && !t
->operand_types
[wanted
].bitfield
.qword
)
1981 || (i
.types
[given
].bitfield
.tbyte
1982 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1985 /* Return 1 if there is no conflict in SIMD register between operand
1986 GIVEN and opeand WANTED for instruction template T. */
1989 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1992 return !((i
.types
[given
].bitfield
.xmmword
1993 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1994 || (i
.types
[given
].bitfield
.ymmword
1995 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1996 || (i
.types
[given
].bitfield
.zmmword
1997 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2000 /* Return 1 if there is no conflict in any size between operand GIVEN
2001 and opeand WANTED for instruction template T. */
2004 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2007 return (match_operand_size (t
, wanted
, given
)
2008 && !((i
.types
[given
].bitfield
.unspecified
2010 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2011 || (i
.types
[given
].bitfield
.fword
2012 && !t
->operand_types
[wanted
].bitfield
.fword
)
2013 /* For scalar opcode templates to allow register and memory
2014 operands at the same time, some special casing is needed
2015 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2016 down-conversion vpmov*. */
2017 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2018 && !t
->opcode_modifier
.broadcast
2019 && (t
->operand_types
[wanted
].bitfield
.byte
2020 || t
->operand_types
[wanted
].bitfield
.word
2021 || t
->operand_types
[wanted
].bitfield
.dword
2022 || t
->operand_types
[wanted
].bitfield
.qword
))
2023 ? (i
.types
[given
].bitfield
.xmmword
2024 || i
.types
[given
].bitfield
.ymmword
2025 || i
.types
[given
].bitfield
.zmmword
)
2026 : !match_simd_size(t
, wanted
, given
))));
2029 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2030 operands for instruction template T, and it has MATCH_REVERSE set if there
2031 is no size conflict on any operands for the template with operands reversed
2032 (and the template allows for reversing in the first place). */
2034 #define MATCH_STRAIGHT 1
2035 #define MATCH_REVERSE 2
2037 static INLINE
unsigned int
2038 operand_size_match (const insn_template
*t
)
2040 unsigned int j
, match
= MATCH_STRAIGHT
;
2042 /* Don't check jump instructions. */
2043 if (t
->opcode_modifier
.jump
2044 || t
->opcode_modifier
.jumpbyte
2045 || t
->opcode_modifier
.jumpdword
2046 || t
->opcode_modifier
.jumpintersegment
)
2049 /* Check memory and accumulator operand size. */
2050 for (j
= 0; j
< i
.operands
; j
++)
2052 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2053 && t
->operand_types
[j
].bitfield
.anysize
)
2056 if (t
->operand_types
[j
].bitfield
.reg
2057 && !match_operand_size (t
, j
, j
))
2063 if (t
->operand_types
[j
].bitfield
.regsimd
2064 && !match_simd_size (t
, j
, j
))
2070 if (t
->operand_types
[j
].bitfield
.acc
2071 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2077 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2084 if (!t
->opcode_modifier
.d
)
2088 i
.error
= operand_size_mismatch
;
2092 /* Check reverse. */
2093 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2095 for (j
= 0; j
< i
.operands
; j
++)
2097 unsigned int given
= i
.operands
- j
- 1;
2099 if (t
->operand_types
[j
].bitfield
.reg
2100 && !match_operand_size (t
, j
, given
))
2103 if (t
->operand_types
[j
].bitfield
.regsimd
2104 && !match_simd_size (t
, j
, given
))
2107 if (t
->operand_types
[j
].bitfield
.acc
2108 && (!match_operand_size (t
, j
, given
)
2109 || !match_simd_size (t
, j
, given
)))
2112 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2116 return match
| MATCH_REVERSE
;
2120 operand_type_match (i386_operand_type overlap
,
2121 i386_operand_type given
)
2123 i386_operand_type temp
= overlap
;
2125 temp
.bitfield
.jumpabsolute
= 0;
2126 temp
.bitfield
.unspecified
= 0;
2127 temp
.bitfield
.byte
= 0;
2128 temp
.bitfield
.word
= 0;
2129 temp
.bitfield
.dword
= 0;
2130 temp
.bitfield
.fword
= 0;
2131 temp
.bitfield
.qword
= 0;
2132 temp
.bitfield
.tbyte
= 0;
2133 temp
.bitfield
.xmmword
= 0;
2134 temp
.bitfield
.ymmword
= 0;
2135 temp
.bitfield
.zmmword
= 0;
2136 if (operand_type_all_zero (&temp
))
2139 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2140 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2144 i
.error
= operand_type_mismatch
;
2148 /* If given types g0 and g1 are registers they must be of the same type
2149 unless the expected operand type register overlap is null.
2150 Memory operand size of certain SIMD instructions is also being checked
2154 operand_type_register_match (i386_operand_type g0
,
2155 i386_operand_type t0
,
2156 i386_operand_type g1
,
2157 i386_operand_type t1
)
2159 if (!g0
.bitfield
.reg
2160 && !g0
.bitfield
.regsimd
2161 && (!operand_type_check (g0
, anymem
)
2162 || g0
.bitfield
.unspecified
2163 || !t0
.bitfield
.regsimd
))
2166 if (!g1
.bitfield
.reg
2167 && !g1
.bitfield
.regsimd
2168 && (!operand_type_check (g1
, anymem
)
2169 || g1
.bitfield
.unspecified
2170 || !t1
.bitfield
.regsimd
))
2173 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2174 && g0
.bitfield
.word
== g1
.bitfield
.word
2175 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2176 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2177 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2178 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2179 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2182 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2183 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2184 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2185 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2186 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2187 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2188 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2191 i
.error
= register_type_mismatch
;
2196 static INLINE
unsigned int
2197 register_number (const reg_entry
*r
)
2199 unsigned int nr
= r
->reg_num
;
2201 if (r
->reg_flags
& RegRex
)
2204 if (r
->reg_flags
& RegVRex
)
2210 static INLINE
unsigned int
2211 mode_from_disp_size (i386_operand_type t
)
2213 if (t
.bitfield
.disp8
)
2215 else if (t
.bitfield
.disp16
2216 || t
.bitfield
.disp32
2217 || t
.bitfield
.disp32s
)
2224 fits_in_signed_byte (addressT num
)
2226 return num
+ 0x80 <= 0xff;
2230 fits_in_unsigned_byte (addressT num
)
2236 fits_in_unsigned_word (addressT num
)
2238 return num
<= 0xffff;
2242 fits_in_signed_word (addressT num
)
2244 return num
+ 0x8000 <= 0xffff;
2248 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2253 return num
+ 0x80000000 <= 0xffffffff;
2255 } /* fits_in_signed_long() */
2258 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2263 return num
<= 0xffffffff;
2265 } /* fits_in_unsigned_long() */
2268 fits_in_disp8 (offsetT num
)
2270 int shift
= i
.memshift
;
2276 mask
= (1 << shift
) - 1;
2278 /* Return 0 if NUM isn't properly aligned. */
2282 /* Check if NUM will fit in 8bit after shift. */
2283 return fits_in_signed_byte (num
>> shift
);
2287 fits_in_imm4 (offsetT num
)
2289 return (num
& 0xf) == num
;
2292 static i386_operand_type
2293 smallest_imm_type (offsetT num
)
2295 i386_operand_type t
;
2297 operand_type_set (&t
, 0);
2298 t
.bitfield
.imm64
= 1;
2300 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2302 /* This code is disabled on the 486 because all the Imm1 forms
2303 in the opcode table are slower on the i486. They're the
2304 versions with the implicitly specified single-position
2305 displacement, which has another syntax if you really want to
2307 t
.bitfield
.imm1
= 1;
2308 t
.bitfield
.imm8
= 1;
2309 t
.bitfield
.imm8s
= 1;
2310 t
.bitfield
.imm16
= 1;
2311 t
.bitfield
.imm32
= 1;
2312 t
.bitfield
.imm32s
= 1;
2314 else if (fits_in_signed_byte (num
))
2316 t
.bitfield
.imm8
= 1;
2317 t
.bitfield
.imm8s
= 1;
2318 t
.bitfield
.imm16
= 1;
2319 t
.bitfield
.imm32
= 1;
2320 t
.bitfield
.imm32s
= 1;
2322 else if (fits_in_unsigned_byte (num
))
2324 t
.bitfield
.imm8
= 1;
2325 t
.bitfield
.imm16
= 1;
2326 t
.bitfield
.imm32
= 1;
2327 t
.bitfield
.imm32s
= 1;
2329 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2331 t
.bitfield
.imm16
= 1;
2332 t
.bitfield
.imm32
= 1;
2333 t
.bitfield
.imm32s
= 1;
2335 else if (fits_in_signed_long (num
))
2337 t
.bitfield
.imm32
= 1;
2338 t
.bitfield
.imm32s
= 1;
2340 else if (fits_in_unsigned_long (num
))
2341 t
.bitfield
.imm32
= 1;
2347 offset_in_range (offsetT val
, int size
)
2353 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2354 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2355 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2357 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2363 /* If BFD64, sign extend val for 32bit address mode. */
2364 if (flag_code
!= CODE_64BIT
2365 || i
.prefix
[ADDR_PREFIX
])
2366 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2367 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2370 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2372 char buf1
[40], buf2
[40];
2374 sprint_value (buf1
, val
);
2375 sprint_value (buf2
, val
& mask
);
2376 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2391 a. PREFIX_EXIST if attempting to add a prefix where one from the
2392 same class already exists.
2393 b. PREFIX_LOCK if lock prefix is added.
2394 c. PREFIX_REP if rep/repne prefix is added.
2395 d. PREFIX_DS if ds prefix is added.
2396 e. PREFIX_OTHER if other prefix is added.
2399 static enum PREFIX_GROUP
2400 add_prefix (unsigned int prefix
)
2402 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2405 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2406 && flag_code
== CODE_64BIT
)
2408 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2409 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2410 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2411 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2422 case DS_PREFIX_OPCODE
:
2425 case CS_PREFIX_OPCODE
:
2426 case ES_PREFIX_OPCODE
:
2427 case FS_PREFIX_OPCODE
:
2428 case GS_PREFIX_OPCODE
:
2429 case SS_PREFIX_OPCODE
:
2433 case REPNE_PREFIX_OPCODE
:
2434 case REPE_PREFIX_OPCODE
:
2439 case LOCK_PREFIX_OPCODE
:
2448 case ADDR_PREFIX_OPCODE
:
2452 case DATA_PREFIX_OPCODE
:
2456 if (i
.prefix
[q
] != 0)
2464 i
.prefix
[q
] |= prefix
;
2467 as_bad (_("same type of prefix used twice"));
2473 update_code_flag (int value
, int check
)
2475 PRINTF_LIKE ((*as_error
));
2477 flag_code
= (enum flag_code
) value
;
2478 if (flag_code
== CODE_64BIT
)
2480 cpu_arch_flags
.bitfield
.cpu64
= 1;
2481 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2485 cpu_arch_flags
.bitfield
.cpu64
= 0;
2486 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2488 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2491 as_error
= as_fatal
;
2494 (*as_error
) (_("64bit mode not supported on `%s'."),
2495 cpu_arch_name
? cpu_arch_name
: default_arch
);
2497 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2500 as_error
= as_fatal
;
2503 (*as_error
) (_("32bit mode not supported on `%s'."),
2504 cpu_arch_name
? cpu_arch_name
: default_arch
);
2506 stackop_size
= '\0';
2510 set_code_flag (int value
)
2512 update_code_flag (value
, 0);
2516 set_16bit_gcc_code_flag (int new_code_flag
)
2518 flag_code
= (enum flag_code
) new_code_flag
;
2519 if (flag_code
!= CODE_16BIT
)
2521 cpu_arch_flags
.bitfield
.cpu64
= 0;
2522 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2523 stackop_size
= LONG_MNEM_SUFFIX
;
2527 set_intel_syntax (int syntax_flag
)
2529 /* Find out if register prefixing is specified. */
2530 int ask_naked_reg
= 0;
2533 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2536 int e
= get_symbol_name (&string
);
2538 if (strcmp (string
, "prefix") == 0)
2540 else if (strcmp (string
, "noprefix") == 0)
2543 as_bad (_("bad argument to syntax directive."));
2544 (void) restore_line_pointer (e
);
2546 demand_empty_rest_of_line ();
2548 intel_syntax
= syntax_flag
;
2550 if (ask_naked_reg
== 0)
2551 allow_naked_reg
= (intel_syntax
2552 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2554 allow_naked_reg
= (ask_naked_reg
< 0);
2556 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2558 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2559 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2560 register_prefix
= allow_naked_reg
? "" : "%";
2564 set_intel_mnemonic (int mnemonic_flag
)
2566 intel_mnemonic
= mnemonic_flag
;
2570 set_allow_index_reg (int flag
)
2572 allow_index_reg
= flag
;
2576 set_check (int what
)
2578 enum check_kind
*kind
;
2583 kind
= &operand_check
;
2594 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2597 int e
= get_symbol_name (&string
);
2599 if (strcmp (string
, "none") == 0)
2601 else if (strcmp (string
, "warning") == 0)
2602 *kind
= check_warning
;
2603 else if (strcmp (string
, "error") == 0)
2604 *kind
= check_error
;
2606 as_bad (_("bad argument to %s_check directive."), str
);
2607 (void) restore_line_pointer (e
);
2610 as_bad (_("missing argument for %s_check directive"), str
);
2612 demand_empty_rest_of_line ();
2616 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2617 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2620 static const char *arch
;
2622 /* Intel LIOM is only supported on ELF. */
2628 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2629 use default_arch. */
2630 arch
= cpu_arch_name
;
2632 arch
= default_arch
;
2635 /* If we are targeting Intel MCU, we must enable it. */
2636 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2637 || new_flag
.bitfield
.cpuiamcu
)
2640 /* If we are targeting Intel L1OM, we must enable it. */
2641 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2642 || new_flag
.bitfield
.cpul1om
)
2645 /* If we are targeting Intel K1OM, we must enable it. */
2646 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2647 || new_flag
.bitfield
.cpuk1om
)
2650 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2655 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2659 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2662 int e
= get_symbol_name (&string
);
2664 i386_cpu_flags flags
;
2666 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2668 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2670 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2674 cpu_arch_name
= cpu_arch
[j
].name
;
2675 cpu_sub_arch_name
= NULL
;
2676 cpu_arch_flags
= cpu_arch
[j
].flags
;
2677 if (flag_code
== CODE_64BIT
)
2679 cpu_arch_flags
.bitfield
.cpu64
= 1;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2684 cpu_arch_flags
.bitfield
.cpu64
= 0;
2685 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2687 cpu_arch_isa
= cpu_arch
[j
].type
;
2688 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2689 if (!cpu_arch_tune_set
)
2691 cpu_arch_tune
= cpu_arch_isa
;
2692 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2697 flags
= cpu_flags_or (cpu_arch_flags
,
2700 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2702 if (cpu_sub_arch_name
)
2704 char *name
= cpu_sub_arch_name
;
2705 cpu_sub_arch_name
= concat (name
,
2707 (const char *) NULL
);
2711 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2712 cpu_arch_flags
= flags
;
2713 cpu_arch_isa_flags
= flags
;
2717 = cpu_flags_or (cpu_arch_isa_flags
,
2719 (void) restore_line_pointer (e
);
2720 demand_empty_rest_of_line ();
2725 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2727 /* Disable an ISA extension. */
2728 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2729 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2731 flags
= cpu_flags_and_not (cpu_arch_flags
,
2732 cpu_noarch
[j
].flags
);
2733 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2735 if (cpu_sub_arch_name
)
2737 char *name
= cpu_sub_arch_name
;
2738 cpu_sub_arch_name
= concat (name
, string
,
2739 (const char *) NULL
);
2743 cpu_sub_arch_name
= xstrdup (string
);
2744 cpu_arch_flags
= flags
;
2745 cpu_arch_isa_flags
= flags
;
2747 (void) restore_line_pointer (e
);
2748 demand_empty_rest_of_line ();
2752 j
= ARRAY_SIZE (cpu_arch
);
2755 if (j
>= ARRAY_SIZE (cpu_arch
))
2756 as_bad (_("no such architecture: `%s'"), string
);
2758 *input_line_pointer
= e
;
2761 as_bad (_("missing cpu architecture"));
2763 no_cond_jump_promotion
= 0;
2764 if (*input_line_pointer
== ','
2765 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2770 ++input_line_pointer
;
2771 e
= get_symbol_name (&string
);
2773 if (strcmp (string
, "nojumps") == 0)
2774 no_cond_jump_promotion
= 1;
2775 else if (strcmp (string
, "jumps") == 0)
2778 as_bad (_("no such architecture modifier: `%s'"), string
);
2780 (void) restore_line_pointer (e
);
2783 demand_empty_rest_of_line ();
2786 enum bfd_architecture
2789 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || flag_code
!= CODE_64BIT
)
2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_arch_l1om
;
2796 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2798 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2799 || flag_code
!= CODE_64BIT
)
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_arch_k1om
;
2803 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2805 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2806 || flag_code
== CODE_64BIT
)
2807 as_fatal (_("Intel MCU is 32bit ELF only"));
2808 return bfd_arch_iamcu
;
2811 return bfd_arch_i386
;
2817 if (!strncmp (default_arch
, "x86_64", 6))
2819 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2821 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2822 || default_arch
[6] != '\0')
2823 as_fatal (_("Intel L1OM is 64bit ELF only"));
2824 return bfd_mach_l1om
;
2826 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2828 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2829 || default_arch
[6] != '\0')
2830 as_fatal (_("Intel K1OM is 64bit ELF only"));
2831 return bfd_mach_k1om
;
2833 else if (default_arch
[6] == '\0')
2834 return bfd_mach_x86_64
;
2836 return bfd_mach_x64_32
;
2838 else if (!strcmp (default_arch
, "i386")
2839 || !strcmp (default_arch
, "iamcu"))
2841 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2843 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2844 as_fatal (_("Intel MCU is 32bit ELF only"));
2845 return bfd_mach_i386_iamcu
;
2848 return bfd_mach_i386_i386
;
2851 as_fatal (_("unknown architecture"));
2857 const char *hash_err
;
2859 /* Support pseudo prefixes like {disp32}. */
2860 lex_type
['{'] = LEX_BEGIN_NAME
;
2862 /* Initialize op_hash hash table. */
2863 op_hash
= hash_new ();
2866 const insn_template
*optab
;
2867 templates
*core_optab
;
2869 /* Setup for loop. */
2871 core_optab
= XNEW (templates
);
2872 core_optab
->start
= optab
;
2877 if (optab
->name
== NULL
2878 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2880 /* different name --> ship out current template list;
2881 add to hash table; & begin anew. */
2882 core_optab
->end
= optab
;
2883 hash_err
= hash_insert (op_hash
,
2885 (void *) core_optab
);
2888 as_fatal (_("can't hash %s: %s"),
2892 if (optab
->name
== NULL
)
2894 core_optab
= XNEW (templates
);
2895 core_optab
->start
= optab
;
2900 /* Initialize reg_hash hash table. */
2901 reg_hash
= hash_new ();
2903 const reg_entry
*regtab
;
2904 unsigned int regtab_size
= i386_regtab_size
;
2906 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2908 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2910 as_fatal (_("can't hash %s: %s"),
2916 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2921 for (c
= 0; c
< 256; c
++)
2926 mnemonic_chars
[c
] = c
;
2927 register_chars
[c
] = c
;
2928 operand_chars
[c
] = c
;
2930 else if (ISLOWER (c
))
2932 mnemonic_chars
[c
] = c
;
2933 register_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2936 else if (ISUPPER (c
))
2938 mnemonic_chars
[c
] = TOLOWER (c
);
2939 register_chars
[c
] = mnemonic_chars
[c
];
2940 operand_chars
[c
] = c
;
2942 else if (c
== '{' || c
== '}')
2944 mnemonic_chars
[c
] = c
;
2945 operand_chars
[c
] = c
;
2948 if (ISALPHA (c
) || ISDIGIT (c
))
2949 identifier_chars
[c
] = c
;
2952 identifier_chars
[c
] = c
;
2953 operand_chars
[c
] = c
;
2958 identifier_chars
['@'] = '@';
2961 identifier_chars
['?'] = '?';
2962 operand_chars
['?'] = '?';
2964 digit_chars
['-'] = '-';
2965 mnemonic_chars
['_'] = '_';
2966 mnemonic_chars
['-'] = '-';
2967 mnemonic_chars
['.'] = '.';
2968 identifier_chars
['_'] = '_';
2969 identifier_chars
['.'] = '.';
2971 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2972 operand_chars
[(unsigned char) *p
] = *p
;
2975 if (flag_code
== CODE_64BIT
)
2977 #if defined (OBJ_COFF) && defined (TE_PE)
2978 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2981 x86_dwarf2_return_column
= 16;
2983 x86_cie_data_alignment
= -8;
2987 x86_dwarf2_return_column
= 8;
2988 x86_cie_data_alignment
= -4;
2993 i386_print_statistics (FILE *file
)
2995 hash_print_statistics (file
, "i386 opcode", op_hash
);
2996 hash_print_statistics (file
, "i386 register", reg_hash
);
3001 /* Debugging routines for md_assemble. */
3002 static void pte (insn_template
*);
3003 static void pt (i386_operand_type
);
3004 static void pe (expressionS
*);
3005 static void ps (symbolS
*);
3008 pi (const char *line
, i386_insn
*x
)
3012 fprintf (stdout
, "%s: template ", line
);
3014 fprintf (stdout
, " address: base %s index %s scale %x\n",
3015 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3016 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3017 x
->log2_scale_factor
);
3018 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3019 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3020 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3021 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3022 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3023 (x
->rex
& REX_W
) != 0,
3024 (x
->rex
& REX_R
) != 0,
3025 (x
->rex
& REX_X
) != 0,
3026 (x
->rex
& REX_B
) != 0);
3027 for (j
= 0; j
< x
->operands
; j
++)
3029 fprintf (stdout
, " #%d: ", j
+ 1);
3031 fprintf (stdout
, "\n");
3032 if (x
->types
[j
].bitfield
.reg
3033 || x
->types
[j
].bitfield
.regmmx
3034 || x
->types
[j
].bitfield
.regsimd
3035 || x
->types
[j
].bitfield
.sreg2
3036 || x
->types
[j
].bitfield
.sreg3
3037 || x
->types
[j
].bitfield
.control
3038 || x
->types
[j
].bitfield
.debug
3039 || x
->types
[j
].bitfield
.test
)
3040 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3041 if (operand_type_check (x
->types
[j
], imm
))
3043 if (operand_type_check (x
->types
[j
], disp
))
3044 pe (x
->op
[j
].disps
);
3049 pte (insn_template
*t
)
3052 fprintf (stdout
, " %d operands ", t
->operands
);
3053 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3054 if (t
->extension_opcode
!= None
)
3055 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3056 if (t
->opcode_modifier
.d
)
3057 fprintf (stdout
, "D");
3058 if (t
->opcode_modifier
.w
)
3059 fprintf (stdout
, "W");
3060 fprintf (stdout
, "\n");
3061 for (j
= 0; j
< t
->operands
; j
++)
3063 fprintf (stdout
, " #%d type ", j
+ 1);
3064 pt (t
->operand_types
[j
]);
3065 fprintf (stdout
, "\n");
3072 fprintf (stdout
, " operation %d\n", e
->X_op
);
3073 fprintf (stdout
, " add_number %ld (%lx)\n",
3074 (long) e
->X_add_number
, (long) e
->X_add_number
);
3075 if (e
->X_add_symbol
)
3077 fprintf (stdout
, " add_symbol ");
3078 ps (e
->X_add_symbol
);
3079 fprintf (stdout
, "\n");
3083 fprintf (stdout
, " op_symbol ");
3084 ps (e
->X_op_symbol
);
3085 fprintf (stdout
, "\n");
3092 fprintf (stdout
, "%s type %s%s",
3094 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3095 segment_name (S_GET_SEGMENT (s
)));
3098 static struct type_name
3100 i386_operand_type mask
;
3103 const type_names
[] =
3105 { OPERAND_TYPE_REG8
, "r8" },
3106 { OPERAND_TYPE_REG16
, "r16" },
3107 { OPERAND_TYPE_REG32
, "r32" },
3108 { OPERAND_TYPE_REG64
, "r64" },
3109 { OPERAND_TYPE_ACC8
, "acc8" },
3110 { OPERAND_TYPE_ACC16
, "acc16" },
3111 { OPERAND_TYPE_ACC32
, "acc32" },
3112 { OPERAND_TYPE_ACC64
, "acc64" },
3113 { OPERAND_TYPE_IMM8
, "i8" },
3114 { OPERAND_TYPE_IMM8
, "i8s" },
3115 { OPERAND_TYPE_IMM16
, "i16" },
3116 { OPERAND_TYPE_IMM32
, "i32" },
3117 { OPERAND_TYPE_IMM32S
, "i32s" },
3118 { OPERAND_TYPE_IMM64
, "i64" },
3119 { OPERAND_TYPE_IMM1
, "i1" },
3120 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3121 { OPERAND_TYPE_DISP8
, "d8" },
3122 { OPERAND_TYPE_DISP16
, "d16" },
3123 { OPERAND_TYPE_DISP32
, "d32" },
3124 { OPERAND_TYPE_DISP32S
, "d32s" },
3125 { OPERAND_TYPE_DISP64
, "d64" },
3126 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3127 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3128 { OPERAND_TYPE_CONTROL
, "control reg" },
3129 { OPERAND_TYPE_TEST
, "test reg" },
3130 { OPERAND_TYPE_DEBUG
, "debug reg" },
3131 { OPERAND_TYPE_FLOATREG
, "FReg" },
3132 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3133 { OPERAND_TYPE_SREG2
, "SReg2" },
3134 { OPERAND_TYPE_SREG3
, "SReg3" },
3135 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3136 { OPERAND_TYPE_REGMMX
, "rMMX" },
3137 { OPERAND_TYPE_REGXMM
, "rXMM" },
3138 { OPERAND_TYPE_REGYMM
, "rYMM" },
3139 { OPERAND_TYPE_REGZMM
, "rZMM" },
3140 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3141 { OPERAND_TYPE_ESSEG
, "es" },
3145 pt (i386_operand_type t
)
3148 i386_operand_type a
;
3150 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3152 a
= operand_type_and (t
, type_names
[j
].mask
);
3153 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3154 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3159 #endif /* DEBUG386 */
3161 static bfd_reloc_code_real_type
3162 reloc (unsigned int size
,
3165 bfd_reloc_code_real_type other
)
3167 if (other
!= NO_RELOC
)
3169 reloc_howto_type
*rel
;
3174 case BFD_RELOC_X86_64_GOT32
:
3175 return BFD_RELOC_X86_64_GOT64
;
3177 case BFD_RELOC_X86_64_GOTPLT64
:
3178 return BFD_RELOC_X86_64_GOTPLT64
;
3180 case BFD_RELOC_X86_64_PLTOFF64
:
3181 return BFD_RELOC_X86_64_PLTOFF64
;
3183 case BFD_RELOC_X86_64_GOTPC32
:
3184 other
= BFD_RELOC_X86_64_GOTPC64
;
3186 case BFD_RELOC_X86_64_GOTPCREL
:
3187 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3189 case BFD_RELOC_X86_64_TPOFF32
:
3190 other
= BFD_RELOC_X86_64_TPOFF64
;
3192 case BFD_RELOC_X86_64_DTPOFF32
:
3193 other
= BFD_RELOC_X86_64_DTPOFF64
;
3199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3200 if (other
== BFD_RELOC_SIZE32
)
3203 other
= BFD_RELOC_SIZE64
;
3206 as_bad (_("there are no pc-relative size relocations"));
3212 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3213 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3216 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3218 as_bad (_("unknown relocation (%u)"), other
);
3219 else if (size
!= bfd_get_reloc_size (rel
))
3220 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3221 bfd_get_reloc_size (rel
),
3223 else if (pcrel
&& !rel
->pc_relative
)
3224 as_bad (_("non-pc-relative relocation for pc-relative field"));
3225 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3227 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3229 as_bad (_("relocated field and relocation type differ in signedness"));
3238 as_bad (_("there are no unsigned pc-relative relocations"));
3241 case 1: return BFD_RELOC_8_PCREL
;
3242 case 2: return BFD_RELOC_16_PCREL
;
3243 case 4: return BFD_RELOC_32_PCREL
;
3244 case 8: return BFD_RELOC_64_PCREL
;
3246 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3253 case 4: return BFD_RELOC_X86_64_32S
;
3258 case 1: return BFD_RELOC_8
;
3259 case 2: return BFD_RELOC_16
;
3260 case 4: return BFD_RELOC_32
;
3261 case 8: return BFD_RELOC_64
;
3263 as_bad (_("cannot do %s %u byte relocation"),
3264 sign
> 0 ? "signed" : "unsigned", size
);
3270 /* Here we decide which fixups can be adjusted to make them relative to
3271 the beginning of the section instead of the symbol. Basically we need
3272 to make sure that the dynamic relocations are done correctly, so in
3273 some cases we force the original symbol to be used. */
3276 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3278 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3282 /* Don't adjust pc-relative references to merge sections in 64-bit
3284 if (use_rela_relocations
3285 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3289 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3290 and changed later by validate_fix. */
3291 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3292 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3295 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3296 for size relocations. */
3297 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3298 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3300 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3301 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3302 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3310 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3311 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3312 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3325 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3328 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3329 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3336 intel_float_operand (const char *mnemonic
)
3338 /* Note that the value returned is meaningful only for opcodes with (memory)
3339 operands, hence the code here is free to improperly handle opcodes that
3340 have no operands (for better performance and smaller code). */
3342 if (mnemonic
[0] != 'f')
3343 return 0; /* non-math */
3345 switch (mnemonic
[1])
3347 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3348 the fs segment override prefix not currently handled because no
3349 call path can make opcodes without operands get here */
3351 return 2 /* integer op */;
3353 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3354 return 3; /* fldcw/fldenv */
3357 if (mnemonic
[2] != 'o' /* fnop */)
3358 return 3; /* non-waiting control op */
3361 if (mnemonic
[2] == 's')
3362 return 3; /* frstor/frstpm */
3365 if (mnemonic
[2] == 'a')
3366 return 3; /* fsave */
3367 if (mnemonic
[2] == 't')
3369 switch (mnemonic
[3])
3371 case 'c': /* fstcw */
3372 case 'd': /* fstdw */
3373 case 'e': /* fstenv */
3374 case 's': /* fsts[gw] */
3380 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3381 return 0; /* fxsave/fxrstor are not really math ops */
3388 /* Build the VEX prefix. */
3391 build_vex_prefix (const insn_template
*t
)
3393 unsigned int register_specifier
;
3394 unsigned int implied_prefix
;
3395 unsigned int vector_length
;
3398 /* Check register specifier. */
3399 if (i
.vex
.register_specifier
)
3401 register_specifier
=
3402 ~register_number (i
.vex
.register_specifier
) & 0xf;
3403 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3406 register_specifier
= 0xf;
3408 /* Use 2-byte VEX prefix by swapping destination and source operand
3409 if there are more than 1 register operand. */
3410 if (i
.reg_operands
> 1
3411 && i
.vec_encoding
!= vex_encoding_vex3
3412 && i
.dir_encoding
== dir_encoding_default
3413 && i
.operands
== i
.reg_operands
3414 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3415 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3416 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3419 unsigned int xchg
= i
.operands
- 1;
3420 union i386_op temp_op
;
3421 i386_operand_type temp_type
;
3423 temp_type
= i
.types
[xchg
];
3424 i
.types
[xchg
] = i
.types
[0];
3425 i
.types
[0] = temp_type
;
3426 temp_op
= i
.op
[xchg
];
3427 i
.op
[xchg
] = i
.op
[0];
3430 gas_assert (i
.rm
.mode
== 3);
3434 i
.rm
.regmem
= i
.rm
.reg
;
3437 if (i
.tm
.opcode_modifier
.d
)
3438 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3439 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3440 else /* Use the next insn. */
3444 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3445 are no memory operands and at least 3 register ones. */
3446 if (i
.reg_operands
>= 3
3447 && i
.vec_encoding
!= vex_encoding_vex3
3448 && i
.reg_operands
== i
.operands
- i
.imm_operands
3449 && i
.tm
.opcode_modifier
.vex
3450 && i
.tm
.opcode_modifier
.commutative
3451 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3453 && i
.vex
.register_specifier
3454 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3456 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3457 union i386_op temp_op
;
3458 i386_operand_type temp_type
;
3460 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3461 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3462 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3463 &i
.types
[i
.operands
- 3]));
3464 gas_assert (i
.rm
.mode
== 3);
3466 temp_type
= i
.types
[xchg
];
3467 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3468 i
.types
[xchg
+ 1] = temp_type
;
3469 temp_op
= i
.op
[xchg
];
3470 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3471 i
.op
[xchg
+ 1] = temp_op
;
3474 xchg
= i
.rm
.regmem
| 8;
3475 i
.rm
.regmem
= ~register_specifier
& 0xf;
3476 gas_assert (!(i
.rm
.regmem
& 8));
3477 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3478 register_specifier
= ~xchg
& 0xf;
3481 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3482 vector_length
= avxscalar
;
3483 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3489 /* Determine vector length from the last multi-length vector
3492 for (op
= t
->operands
; op
--;)
3493 if (t
->operand_types
[op
].bitfield
.xmmword
3494 && t
->operand_types
[op
].bitfield
.ymmword
3495 && i
.types
[op
].bitfield
.ymmword
)
3502 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3507 case DATA_PREFIX_OPCODE
:
3510 case REPE_PREFIX_OPCODE
:
3513 case REPNE_PREFIX_OPCODE
:
3520 /* Check the REX.W bit and VEXW. */
3521 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3522 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3523 else if (i
.tm
.opcode_modifier
.vexw
)
3524 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3526 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3528 /* Use 2-byte VEX prefix if possible. */
3530 && i
.vec_encoding
!= vex_encoding_vex3
3531 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3532 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3534 /* 2-byte VEX prefix. */
3538 i
.vex
.bytes
[0] = 0xc5;
3540 /* Check the REX.R bit. */
3541 r
= (i
.rex
& REX_R
) ? 0 : 1;
3542 i
.vex
.bytes
[1] = (r
<< 7
3543 | register_specifier
<< 3
3544 | vector_length
<< 2
3549 /* 3-byte VEX prefix. */
3554 switch (i
.tm
.opcode_modifier
.vexopcode
)
3558 i
.vex
.bytes
[0] = 0xc4;
3562 i
.vex
.bytes
[0] = 0xc4;
3566 i
.vex
.bytes
[0] = 0xc4;
3570 i
.vex
.bytes
[0] = 0x8f;
3574 i
.vex
.bytes
[0] = 0x8f;
3578 i
.vex
.bytes
[0] = 0x8f;
3584 /* The high 3 bits of the second VEX byte are 1's compliment
3585 of RXB bits from REX. */
3586 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3588 i
.vex
.bytes
[2] = (w
<< 7
3589 | register_specifier
<< 3
3590 | vector_length
<< 2
3595 static INLINE bfd_boolean
3596 is_evex_encoding (const insn_template
*t
)
3598 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3599 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3600 || t
->opcode_modifier
.sae
;
3603 static INLINE bfd_boolean
3604 is_any_vex_encoding (const insn_template
*t
)
3606 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3607 || is_evex_encoding (t
);
3610 /* Build the EVEX prefix. */
3613 build_evex_prefix (void)
3615 unsigned int register_specifier
;
3616 unsigned int implied_prefix
;
3618 rex_byte vrex_used
= 0;
3620 /* Check register specifier. */
3621 if (i
.vex
.register_specifier
)
3623 gas_assert ((i
.vrex
& REX_X
) == 0);
3625 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3626 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3627 register_specifier
+= 8;
3628 /* The upper 16 registers are encoded in the fourth byte of the
3630 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3631 i
.vex
.bytes
[3] = 0x8;
3632 register_specifier
= ~register_specifier
& 0xf;
3636 register_specifier
= 0xf;
3638 /* Encode upper 16 vector index register in the fourth byte of
3640 if (!(i
.vrex
& REX_X
))
3641 i
.vex
.bytes
[3] = 0x8;
3646 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3651 case DATA_PREFIX_OPCODE
:
3654 case REPE_PREFIX_OPCODE
:
3657 case REPNE_PREFIX_OPCODE
:
3664 /* 4 byte EVEX prefix. */
3666 i
.vex
.bytes
[0] = 0x62;
3669 switch (i
.tm
.opcode_modifier
.vexopcode
)
3685 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3687 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3689 /* The fifth bit of the second EVEX byte is 1's compliment of the
3690 REX_R bit in VREX. */
3691 if (!(i
.vrex
& REX_R
))
3692 i
.vex
.bytes
[1] |= 0x10;
3696 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3698 /* When all operands are registers, the REX_X bit in REX is not
3699 used. We reuse it to encode the upper 16 registers, which is
3700 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3701 as 1's compliment. */
3702 if ((i
.vrex
& REX_B
))
3705 i
.vex
.bytes
[1] &= ~0x40;
3709 /* EVEX instructions shouldn't need the REX prefix. */
3710 i
.vrex
&= ~vrex_used
;
3711 gas_assert (i
.vrex
== 0);
3713 /* Check the REX.W bit and VEXW. */
3714 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3715 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3716 else if (i
.tm
.opcode_modifier
.vexw
)
3717 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3719 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3721 /* Encode the U bit. */
3722 implied_prefix
|= 0x4;
3724 /* The third byte of the EVEX prefix. */
3725 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3727 /* The fourth byte of the EVEX prefix. */
3728 /* The zeroing-masking bit. */
3729 if (i
.mask
&& i
.mask
->zeroing
)
3730 i
.vex
.bytes
[3] |= 0x80;
3732 /* Don't always set the broadcast bit if there is no RC. */
3735 /* Encode the vector length. */
3736 unsigned int vec_length
;
3738 if (!i
.tm
.opcode_modifier
.evex
3739 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3743 /* Determine vector length from the last multi-length vector
3746 for (op
= i
.operands
; op
--;)
3747 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3748 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3749 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3751 if (i
.types
[op
].bitfield
.zmmword
)
3753 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3756 else if (i
.types
[op
].bitfield
.ymmword
)
3758 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3761 else if (i
.types
[op
].bitfield
.xmmword
)
3763 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3766 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3768 switch (i
.broadcast
->bytes
)
3771 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3774 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3777 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3786 if (op
>= MAX_OPERANDS
)
3790 switch (i
.tm
.opcode_modifier
.evex
)
3792 case EVEXLIG
: /* LL' is ignored */
3793 vec_length
= evexlig
<< 5;
3796 vec_length
= 0 << 5;
3799 vec_length
= 1 << 5;
3802 vec_length
= 2 << 5;
3808 i
.vex
.bytes
[3] |= vec_length
;
3809 /* Encode the broadcast bit. */
3811 i
.vex
.bytes
[3] |= 0x10;
3815 if (i
.rounding
->type
!= saeonly
)
3816 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3818 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3821 if (i
.mask
&& i
.mask
->mask
)
3822 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3826 process_immext (void)
3830 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3833 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3834 with an opcode suffix which is coded in the same place as an
3835 8-bit immediate field would be.
3836 Here we check those operands and remove them afterwards. */
3839 for (x
= 0; x
< i
.operands
; x
++)
3840 if (register_number (i
.op
[x
].regs
) != x
)
3841 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3842 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3848 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3850 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3851 suffix which is coded in the same place as an 8-bit immediate
3853 Here we check those operands and remove them afterwards. */
3856 if (i
.operands
!= 3)
3859 for (x
= 0; x
< 2; x
++)
3860 if (register_number (i
.op
[x
].regs
) != x
)
3861 goto bad_register_operand
;
3863 /* Check for third operand for mwaitx/monitorx insn. */
3864 if (register_number (i
.op
[x
].regs
)
3865 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3867 bad_register_operand
:
3868 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3869 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3876 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3877 which is coded in the same place as an 8-bit immediate field
3878 would be. Here we fake an 8-bit immediate operand from the
3879 opcode suffix stored in tm.extension_opcode.
3881 AVX instructions also use this encoding, for some of
3882 3 argument instructions. */
3884 gas_assert (i
.imm_operands
<= 1
3886 || (is_any_vex_encoding (&i
.tm
)
3887 && i
.operands
<= 4)));
3889 exp
= &im_expressions
[i
.imm_operands
++];
3890 i
.op
[i
.operands
].imms
= exp
;
3891 i
.types
[i
.operands
] = imm8
;
3893 exp
->X_op
= O_constant
;
3894 exp
->X_add_number
= i
.tm
.extension_opcode
;
3895 i
.tm
.extension_opcode
= None
;
3902 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3907 as_bad (_("invalid instruction `%s' after `%s'"),
3908 i
.tm
.name
, i
.hle_prefix
);
3911 if (i
.prefix
[LOCK_PREFIX
])
3913 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3917 case HLEPrefixRelease
:
3918 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3920 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3924 if (i
.mem_operands
== 0
3925 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3927 as_bad (_("memory destination needed for instruction `%s'"
3928 " after `xrelease'"), i
.tm
.name
);
3935 /* Try the shortest encoding by shortening operand size. */
3938 optimize_encoding (void)
3942 if (optimize_for_space
3943 && i
.reg_operands
== 1
3944 && i
.imm_operands
== 1
3945 && !i
.types
[1].bitfield
.byte
3946 && i
.op
[0].imms
->X_op
== O_constant
3947 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3948 && ((i
.tm
.base_opcode
== 0xa8
3949 && i
.tm
.extension_opcode
== None
)
3950 || (i
.tm
.base_opcode
== 0xf6
3951 && i
.tm
.extension_opcode
== 0x0)))
3954 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3956 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3957 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3959 i
.types
[1].bitfield
.byte
= 1;
3960 /* Ignore the suffix. */
3962 if (base_regnum
>= 4
3963 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3965 /* Handle SP, BP, SI and DI registers. */
3966 if (i
.types
[1].bitfield
.word
)
3968 else if (i
.types
[1].bitfield
.dword
)
3976 else if (flag_code
== CODE_64BIT
3977 && ((i
.types
[1].bitfield
.qword
3978 && i
.reg_operands
== 1
3979 && i
.imm_operands
== 1
3980 && i
.op
[0].imms
->X_op
== O_constant
3981 && ((i
.tm
.base_opcode
== 0xb0
3982 && i
.tm
.extension_opcode
== None
3983 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3984 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3985 && (((i
.tm
.base_opcode
== 0x24
3986 || i
.tm
.base_opcode
== 0xa8)
3987 && i
.tm
.extension_opcode
== None
)
3988 || (i
.tm
.base_opcode
== 0x80
3989 && i
.tm
.extension_opcode
== 0x4)
3990 || ((i
.tm
.base_opcode
== 0xf6
3991 || i
.tm
.base_opcode
== 0xc6)
3992 && i
.tm
.extension_opcode
== 0x0)))
3993 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3994 && i
.tm
.base_opcode
== 0x83
3995 && i
.tm
.extension_opcode
== 0x4)))
3996 || (i
.types
[0].bitfield
.qword
3997 && ((i
.reg_operands
== 2
3998 && i
.op
[0].regs
== i
.op
[1].regs
3999 && ((i
.tm
.base_opcode
== 0x30
4000 || i
.tm
.base_opcode
== 0x28)
4001 && i
.tm
.extension_opcode
== None
))
4002 || (i
.reg_operands
== 1
4004 && i
.tm
.base_opcode
== 0x30
4005 && i
.tm
.extension_opcode
== None
)))))
4008 andq $imm31, %r64 -> andl $imm31, %r32
4009 andq $imm7, %r64 -> andl $imm7, %r32
4010 testq $imm31, %r64 -> testl $imm31, %r32
4011 xorq %r64, %r64 -> xorl %r32, %r32
4012 subq %r64, %r64 -> subl %r32, %r32
4013 movq $imm31, %r64 -> movl $imm31, %r32
4014 movq $imm32, %r64 -> movl $imm32, %r32
4016 i
.tm
.opcode_modifier
.norex64
= 1;
4017 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
4020 movq $imm31, %r64 -> movl $imm31, %r32
4021 movq $imm32, %r64 -> movl $imm32, %r32
4023 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4024 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4025 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4026 i
.types
[0].bitfield
.imm32
= 1;
4027 i
.types
[0].bitfield
.imm32s
= 0;
4028 i
.types
[0].bitfield
.imm64
= 0;
4029 i
.types
[1].bitfield
.dword
= 1;
4030 i
.types
[1].bitfield
.qword
= 0;
4031 if (i
.tm
.base_opcode
== 0xc6)
4034 movq $imm31, %r64 -> movl $imm31, %r32
4036 i
.tm
.base_opcode
= 0xb0;
4037 i
.tm
.extension_opcode
= None
;
4038 i
.tm
.opcode_modifier
.shortform
= 1;
4039 i
.tm
.opcode_modifier
.modrm
= 0;
4043 else if (optimize
> 1
4044 && !optimize_for_space
4045 && i
.reg_operands
== 2
4046 && i
.op
[0].regs
== i
.op
[1].regs
4047 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4048 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4049 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4052 andb %rN, %rN -> testb %rN, %rN
4053 andw %rN, %rN -> testw %rN, %rN
4054 andq %rN, %rN -> testq %rN, %rN
4055 orb %rN, %rN -> testb %rN, %rN
4056 orw %rN, %rN -> testw %rN, %rN
4057 orq %rN, %rN -> testq %rN, %rN
4059 and outside of 64-bit mode
4061 andl %rN, %rN -> testl %rN, %rN
4062 orl %rN, %rN -> testl %rN, %rN
4064 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4066 else if (i
.reg_operands
== 3
4067 && i
.op
[0].regs
== i
.op
[1].regs
4068 && !i
.types
[2].bitfield
.xmmword
4069 && (i
.tm
.opcode_modifier
.vex
4070 || ((!i
.mask
|| i
.mask
->zeroing
)
4072 && is_evex_encoding (&i
.tm
)
4073 && (i
.vec_encoding
!= vex_encoding_evex
4074 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4075 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4076 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4077 && i
.types
[2].bitfield
.ymmword
))))
4078 && ((i
.tm
.base_opcode
== 0x55
4079 || i
.tm
.base_opcode
== 0x6655
4080 || i
.tm
.base_opcode
== 0x66df
4081 || i
.tm
.base_opcode
== 0x57
4082 || i
.tm
.base_opcode
== 0x6657
4083 || i
.tm
.base_opcode
== 0x66ef
4084 || i
.tm
.base_opcode
== 0x66f8
4085 || i
.tm
.base_opcode
== 0x66f9
4086 || i
.tm
.base_opcode
== 0x66fa
4087 || i
.tm
.base_opcode
== 0x66fb
4088 || i
.tm
.base_opcode
== 0x42
4089 || i
.tm
.base_opcode
== 0x6642
4090 || i
.tm
.base_opcode
== 0x47
4091 || i
.tm
.base_opcode
== 0x6647)
4092 && i
.tm
.extension_opcode
== None
))
4095 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4097 EVEX VOP %zmmM, %zmmM, %zmmN
4098 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4099 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4100 EVEX VOP %ymmM, %ymmM, %ymmN
4101 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4102 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4103 VEX VOP %ymmM, %ymmM, %ymmN
4104 -> VEX VOP %xmmM, %xmmM, %xmmN
4105 VOP, one of vpandn and vpxor:
4106 VEX VOP %ymmM, %ymmM, %ymmN
4107 -> VEX VOP %xmmM, %xmmM, %xmmN
4108 VOP, one of vpandnd and vpandnq:
4109 EVEX VOP %zmmM, %zmmM, %zmmN
4110 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4111 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4112 EVEX VOP %ymmM, %ymmM, %ymmN
4113 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4114 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4115 VOP, one of vpxord and vpxorq:
4116 EVEX VOP %zmmM, %zmmM, %zmmN
4117 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4118 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4119 EVEX VOP %ymmM, %ymmM, %ymmN
4120 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4121 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4122 VOP, one of kxord and kxorq:
4123 VEX VOP %kM, %kM, %kN
4124 -> VEX kxorw %kM, %kM, %kN
4125 VOP, one of kandnd and kandnq:
4126 VEX VOP %kM, %kM, %kN
4127 -> VEX kandnw %kM, %kM, %kN
4129 if (is_evex_encoding (&i
.tm
))
4131 if (i
.vec_encoding
!= vex_encoding_evex
)
4133 i
.tm
.opcode_modifier
.vex
= VEX128
;
4134 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4135 i
.tm
.opcode_modifier
.evex
= 0;
4137 else if (optimize
> 1)
4138 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4142 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4144 i
.tm
.base_opcode
&= 0xff;
4145 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4148 i
.tm
.opcode_modifier
.vex
= VEX128
;
4150 if (i
.tm
.opcode_modifier
.vex
)
4151 for (j
= 0; j
< 3; j
++)
4153 i
.types
[j
].bitfield
.xmmword
= 1;
4154 i
.types
[j
].bitfield
.ymmword
= 0;
4157 else if (i
.vec_encoding
!= vex_encoding_evex
4158 && !i
.types
[0].bitfield
.zmmword
4159 && !i
.types
[1].bitfield
.zmmword
4162 && is_evex_encoding (&i
.tm
)
4163 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4164 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4165 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4166 || (i
.tm
.base_opcode
& ~4) == 0x66db
4167 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4168 && i
.tm
.extension_opcode
== None
)
4171 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4172 vmovdqu32 and vmovdqu64:
4173 EVEX VOP %xmmM, %xmmN
4174 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4175 EVEX VOP %ymmM, %ymmN
4176 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4178 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4180 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4182 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4184 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4185 VOP, one of vpand, vpandn, vpor, vpxor:
4186 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4187 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4188 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4189 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4190 EVEX VOP{d,q} mem, %xmmM, %xmmN
4191 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4192 EVEX VOP{d,q} mem, %ymmM, %ymmN
4193 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4195 for (j
= 0; j
< i
.operands
; j
++)
4196 if (operand_type_check (i
.types
[j
], disp
)
4197 && i
.op
[j
].disps
->X_op
== O_constant
)
4199 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4200 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4201 bytes, we choose EVEX Disp8 over VEX Disp32. */
4202 int evex_disp8
, vex_disp8
;
4203 unsigned int memshift
= i
.memshift
;
4204 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4206 evex_disp8
= fits_in_disp8 (n
);
4208 vex_disp8
= fits_in_disp8 (n
);
4209 if (evex_disp8
!= vex_disp8
)
4211 i
.memshift
= memshift
;
4215 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4218 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4219 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4220 i
.tm
.opcode_modifier
.vex
4221 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4222 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4223 /* VPAND, VPOR, and VPXOR are commutative. */
4224 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4225 i
.tm
.opcode_modifier
.commutative
= 1;
4226 i
.tm
.opcode_modifier
.evex
= 0;
4227 i
.tm
.opcode_modifier
.masking
= 0;
4228 i
.tm
.opcode_modifier
.broadcast
= 0;
4229 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4232 i
.types
[j
].bitfield
.disp8
4233 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4237 /* This is the guts of the machine-dependent assembler. LINE points to a
4238 machine dependent instruction. This function is supposed to emit
4239 the frags/bytes it assembles to. */
4242 md_assemble (char *line
)
4245 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4246 const insn_template
*t
;
4248 /* Initialize globals. */
4249 memset (&i
, '\0', sizeof (i
));
4250 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4251 i
.reloc
[j
] = NO_RELOC
;
4252 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4253 memset (im_expressions
, '\0', sizeof (im_expressions
));
4254 save_stack_p
= save_stack
;
4256 /* First parse an instruction mnemonic & call i386_operand for the operands.
4257 We assume that the scrubber has arranged it so that line[0] is the valid
4258 start of a (possibly prefixed) mnemonic. */
4260 line
= parse_insn (line
, mnemonic
);
4263 mnem_suffix
= i
.suffix
;
4265 line
= parse_operands (line
, mnemonic
);
4267 xfree (i
.memop1_string
);
4268 i
.memop1_string
= NULL
;
4272 /* Now we've parsed the mnemonic into a set of templates, and have the
4273 operands at hand. */
4275 /* All intel opcodes have reversed operands except for "bound" and
4276 "enter". We also don't reverse intersegment "jmp" and "call"
4277 instructions with 2 immediate operands so that the immediate segment
4278 precedes the offset, as it does when in AT&T mode. */
4281 && (strcmp (mnemonic
, "bound") != 0)
4282 && (strcmp (mnemonic
, "invlpga") != 0)
4283 && !(operand_type_check (i
.types
[0], imm
)
4284 && operand_type_check (i
.types
[1], imm
)))
4287 /* The order of the immediates should be reversed
4288 for 2 immediates extrq and insertq instructions */
4289 if (i
.imm_operands
== 2
4290 && (strcmp (mnemonic
, "extrq") == 0
4291 || strcmp (mnemonic
, "insertq") == 0))
4292 swap_2_operands (0, 1);
4297 /* Don't optimize displacement for movabs since it only takes 64bit
4300 && i
.disp_encoding
!= disp_encoding_32bit
4301 && (flag_code
!= CODE_64BIT
4302 || strcmp (mnemonic
, "movabs") != 0))
4305 /* Next, we find a template that matches the given insn,
4306 making sure the overlap of the given operands types is consistent
4307 with the template operand types. */
4309 if (!(t
= match_template (mnem_suffix
)))
4312 if (sse_check
!= check_none
4313 && !i
.tm
.opcode_modifier
.noavx
4314 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4315 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4316 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4317 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4318 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4319 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4320 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4321 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4322 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4323 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4325 (sse_check
== check_warning
4327 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4330 /* Zap movzx and movsx suffix. The suffix has been set from
4331 "word ptr" or "byte ptr" on the source operand in Intel syntax
4332 or extracted from mnemonic in AT&T syntax. But we'll use
4333 the destination register to choose the suffix for encoding. */
4334 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4336 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4337 there is no suffix, the default will be byte extension. */
4338 if (i
.reg_operands
!= 2
4341 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4346 if (i
.tm
.opcode_modifier
.fwait
)
4347 if (!add_prefix (FWAIT_OPCODE
))
4350 /* Check if REP prefix is OK. */
4351 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4353 as_bad (_("invalid instruction `%s' after `%s'"),
4354 i
.tm
.name
, i
.rep_prefix
);
4358 /* Check for lock without a lockable instruction. Destination operand
4359 must be memory unless it is xchg (0x86). */
4360 if (i
.prefix
[LOCK_PREFIX
]
4361 && (!i
.tm
.opcode_modifier
.islockable
4362 || i
.mem_operands
== 0
4363 || (i
.tm
.base_opcode
!= 0x86
4364 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4366 as_bad (_("expecting lockable instruction after `lock'"));
4370 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4371 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4373 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4377 /* Check if HLE prefix is OK. */
4378 if (i
.hle_prefix
&& !check_hle ())
4381 /* Check BND prefix. */
4382 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4383 as_bad (_("expecting valid branch instruction after `bnd'"));
4385 /* Check NOTRACK prefix. */
4386 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4387 as_bad (_("expecting indirect branch instruction after `notrack'"));
4389 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4391 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4392 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4393 else if (flag_code
!= CODE_16BIT
4394 ? i
.prefix
[ADDR_PREFIX
]
4395 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4396 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4399 /* Insert BND prefix. */
4400 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4402 if (!i
.prefix
[BND_PREFIX
])
4403 add_prefix (BND_PREFIX_OPCODE
);
4404 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4406 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4407 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4411 /* Check string instruction segment overrides. */
4412 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4414 if (!check_string ())
4416 i
.disp_operands
= 0;
4419 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4420 optimize_encoding ();
4422 if (!process_suffix ())
4425 /* Update operand types. */
4426 for (j
= 0; j
< i
.operands
; j
++)
4427 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4429 /* Make still unresolved immediate matches conform to size of immediate
4430 given in i.suffix. */
4431 if (!finalize_imm ())
4434 if (i
.types
[0].bitfield
.imm1
)
4435 i
.imm_operands
= 0; /* kludge for shift insns. */
4437 /* We only need to check those implicit registers for instructions
4438 with 3 operands or less. */
4439 if (i
.operands
<= 3)
4440 for (j
= 0; j
< i
.operands
; j
++)
4441 if (i
.types
[j
].bitfield
.inoutportreg
4442 || i
.types
[j
].bitfield
.shiftcount
4443 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4446 /* ImmExt should be processed after SSE2AVX. */
4447 if (!i
.tm
.opcode_modifier
.sse2avx
4448 && i
.tm
.opcode_modifier
.immext
)
4451 /* For insns with operands there are more diddles to do to the opcode. */
4454 if (!process_operands ())
4457 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4459 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4460 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4463 if (is_any_vex_encoding (&i
.tm
))
4465 if (!cpu_arch_flags
.bitfield
.cpui286
)
4467 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4472 if (i
.tm
.opcode_modifier
.vex
)
4473 build_vex_prefix (t
);
4475 build_evex_prefix ();
4478 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4479 instructions may define INT_OPCODE as well, so avoid this corner
4480 case for those instructions that use MODRM. */
4481 if (i
.tm
.base_opcode
== INT_OPCODE
4482 && !i
.tm
.opcode_modifier
.modrm
4483 && i
.op
[0].imms
->X_add_number
== 3)
4485 i
.tm
.base_opcode
= INT3_OPCODE
;
4489 if ((i
.tm
.opcode_modifier
.jump
4490 || i
.tm
.opcode_modifier
.jumpbyte
4491 || i
.tm
.opcode_modifier
.jumpdword
)
4492 && i
.op
[0].disps
->X_op
== O_constant
)
4494 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4495 the absolute address given by the constant. Since ix86 jumps and
4496 calls are pc relative, we need to generate a reloc. */
4497 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4498 i
.op
[0].disps
->X_op
= O_symbol
;
4501 if (i
.tm
.opcode_modifier
.rex64
)
4504 /* For 8 bit registers we need an empty rex prefix. Also if the
4505 instruction already has a prefix, we need to convert old
4506 registers to new ones. */
4508 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4509 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4510 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4511 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4512 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4513 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4518 i
.rex
|= REX_OPCODE
;
4519 for (x
= 0; x
< 2; x
++)
4521 /* Look for 8 bit operand that uses old registers. */
4522 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4523 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4525 /* In case it is "hi" register, give up. */
4526 if (i
.op
[x
].regs
->reg_num
> 3)
4527 as_bad (_("can't encode register '%s%s' in an "
4528 "instruction requiring REX prefix."),
4529 register_prefix
, i
.op
[x
].regs
->reg_name
);
4531 /* Otherwise it is equivalent to the extended register.
4532 Since the encoding doesn't change this is merely
4533 cosmetic cleanup for debug output. */
4535 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4540 if (i
.rex
== 0 && i
.rex_encoding
)
4542 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4543 that uses legacy register. If it is "hi" register, don't add
4544 the REX_OPCODE byte. */
4546 for (x
= 0; x
< 2; x
++)
4547 if (i
.types
[x
].bitfield
.reg
4548 && i
.types
[x
].bitfield
.byte
4549 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4550 && i
.op
[x
].regs
->reg_num
> 3)
4552 i
.rex_encoding
= FALSE
;
4561 add_prefix (REX_OPCODE
| i
.rex
);
4563 /* We are ready to output the insn. */
4568 parse_insn (char *line
, char *mnemonic
)
4571 char *token_start
= l
;
4574 const insn_template
*t
;
4580 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4585 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4587 as_bad (_("no such instruction: `%s'"), token_start
);
4592 if (!is_space_char (*l
)
4593 && *l
!= END_OF_INSN
4595 || (*l
!= PREFIX_SEPARATOR
4598 as_bad (_("invalid character %s in mnemonic"),
4599 output_invalid (*l
));
4602 if (token_start
== l
)
4604 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4605 as_bad (_("expecting prefix; got nothing"));
4607 as_bad (_("expecting mnemonic; got nothing"));
4611 /* Look up instruction (or prefix) via hash table. */
4612 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4614 if (*l
!= END_OF_INSN
4615 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4616 && current_templates
4617 && current_templates
->start
->opcode_modifier
.isprefix
)
4619 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4621 as_bad ((flag_code
!= CODE_64BIT
4622 ? _("`%s' is only supported in 64-bit mode")
4623 : _("`%s' is not supported in 64-bit mode")),
4624 current_templates
->start
->name
);
4627 /* If we are in 16-bit mode, do not allow addr16 or data16.
4628 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4629 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4630 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4631 && flag_code
!= CODE_64BIT
4632 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4633 ^ (flag_code
== CODE_16BIT
)))
4635 as_bad (_("redundant %s prefix"),
4636 current_templates
->start
->name
);
4639 if (current_templates
->start
->opcode_length
== 0)
4641 /* Handle pseudo prefixes. */
4642 switch (current_templates
->start
->base_opcode
)
4646 i
.disp_encoding
= disp_encoding_8bit
;
4650 i
.disp_encoding
= disp_encoding_32bit
;
4654 i
.dir_encoding
= dir_encoding_load
;
4658 i
.dir_encoding
= dir_encoding_store
;
4662 i
.vec_encoding
= vex_encoding_vex2
;
4666 i
.vec_encoding
= vex_encoding_vex3
;
4670 i
.vec_encoding
= vex_encoding_evex
;
4674 i
.rex_encoding
= TRUE
;
4678 i
.no_optimize
= TRUE
;
4686 /* Add prefix, checking for repeated prefixes. */
4687 switch (add_prefix (current_templates
->start
->base_opcode
))
4692 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4693 i
.notrack_prefix
= current_templates
->start
->name
;
4696 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4697 i
.hle_prefix
= current_templates
->start
->name
;
4698 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4699 i
.bnd_prefix
= current_templates
->start
->name
;
4701 i
.rep_prefix
= current_templates
->start
->name
;
4707 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4714 if (!current_templates
)
4716 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4717 Check if we should swap operand or force 32bit displacement in
4719 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4720 i
.dir_encoding
= dir_encoding_swap
;
4721 else if (mnem_p
- 3 == dot_p
4724 i
.disp_encoding
= disp_encoding_8bit
;
4725 else if (mnem_p
- 4 == dot_p
4729 i
.disp_encoding
= disp_encoding_32bit
;
4734 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4737 if (!current_templates
)
4740 if (mnem_p
> mnemonic
)
4742 /* See if we can get a match by trimming off a suffix. */
4745 case WORD_MNEM_SUFFIX
:
4746 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4747 i
.suffix
= SHORT_MNEM_SUFFIX
;
4750 case BYTE_MNEM_SUFFIX
:
4751 case QWORD_MNEM_SUFFIX
:
4752 i
.suffix
= mnem_p
[-1];
4754 current_templates
= (const templates
*) hash_find (op_hash
,
4757 case SHORT_MNEM_SUFFIX
:
4758 case LONG_MNEM_SUFFIX
:
4761 i
.suffix
= mnem_p
[-1];
4763 current_templates
= (const templates
*) hash_find (op_hash
,
4772 if (intel_float_operand (mnemonic
) == 1)
4773 i
.suffix
= SHORT_MNEM_SUFFIX
;
4775 i
.suffix
= LONG_MNEM_SUFFIX
;
4777 current_templates
= (const templates
*) hash_find (op_hash
,
4784 if (!current_templates
)
4786 as_bad (_("no such instruction: `%s'"), token_start
);
4791 if (current_templates
->start
->opcode_modifier
.jump
4792 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4794 /* Check for a branch hint. We allow ",pt" and ",pn" for
4795 predict taken and predict not taken respectively.
4796 I'm not sure that branch hints actually do anything on loop
4797 and jcxz insns (JumpByte) for current Pentium4 chips. They
4798 may work in the future and it doesn't hurt to accept them
4800 if (l
[0] == ',' && l
[1] == 'p')
4804 if (!add_prefix (DS_PREFIX_OPCODE
))
4808 else if (l
[2] == 'n')
4810 if (!add_prefix (CS_PREFIX_OPCODE
))
4816 /* Any other comma loses. */
4819 as_bad (_("invalid character %s in mnemonic"),
4820 output_invalid (*l
));
4824 /* Check if instruction is supported on specified architecture. */
4826 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4828 supported
|= cpu_flags_match (t
);
4829 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4831 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4832 as_warn (_("use .code16 to ensure correct addressing mode"));
4838 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4839 as_bad (flag_code
== CODE_64BIT
4840 ? _("`%s' is not supported in 64-bit mode")
4841 : _("`%s' is only supported in 64-bit mode"),
4842 current_templates
->start
->name
);
4844 as_bad (_("`%s' is not supported on `%s%s'"),
4845 current_templates
->start
->name
,
4846 cpu_arch_name
? cpu_arch_name
: default_arch
,
4847 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4853 parse_operands (char *l
, const char *mnemonic
)
4857 /* 1 if operand is pending after ','. */
4858 unsigned int expecting_operand
= 0;
4860 /* Non-zero if operand parens not balanced. */
4861 unsigned int paren_not_balanced
;
4863 while (*l
!= END_OF_INSN
)
4865 /* Skip optional white space before operand. */
4866 if (is_space_char (*l
))
4868 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4870 as_bad (_("invalid character %s before operand %d"),
4871 output_invalid (*l
),
4875 token_start
= l
; /* After white space. */
4876 paren_not_balanced
= 0;
4877 while (paren_not_balanced
|| *l
!= ',')
4879 if (*l
== END_OF_INSN
)
4881 if (paren_not_balanced
)
4884 as_bad (_("unbalanced parenthesis in operand %d."),
4887 as_bad (_("unbalanced brackets in operand %d."),
4892 break; /* we are done */
4894 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4896 as_bad (_("invalid character %s in operand %d"),
4897 output_invalid (*l
),
4904 ++paren_not_balanced
;
4906 --paren_not_balanced
;
4911 ++paren_not_balanced
;
4913 --paren_not_balanced
;
4917 if (l
!= token_start
)
4918 { /* Yes, we've read in another operand. */
4919 unsigned int operand_ok
;
4920 this_operand
= i
.operands
++;
4921 if (i
.operands
> MAX_OPERANDS
)
4923 as_bad (_("spurious operands; (%d operands/instruction max)"),
4927 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4928 /* Now parse operand adding info to 'i' as we go along. */
4929 END_STRING_AND_SAVE (l
);
4931 if (i
.mem_operands
> 1)
4933 as_bad (_("too many memory references for `%s'"),
4940 i386_intel_operand (token_start
,
4941 intel_float_operand (mnemonic
));
4943 operand_ok
= i386_att_operand (token_start
);
4945 RESTORE_END_STRING (l
);
4951 if (expecting_operand
)
4953 expecting_operand_after_comma
:
4954 as_bad (_("expecting operand after ','; got nothing"));
4959 as_bad (_("expecting operand before ','; got nothing"));
4964 /* Now *l must be either ',' or END_OF_INSN. */
4967 if (*++l
== END_OF_INSN
)
4969 /* Just skip it, if it's \n complain. */
4970 goto expecting_operand_after_comma
;
4972 expecting_operand
= 1;
4979 swap_2_operands (int xchg1
, int xchg2
)
4981 union i386_op temp_op
;
4982 i386_operand_type temp_type
;
4983 unsigned int temp_flags
;
4984 enum bfd_reloc_code_real temp_reloc
;
4986 temp_type
= i
.types
[xchg2
];
4987 i
.types
[xchg2
] = i
.types
[xchg1
];
4988 i
.types
[xchg1
] = temp_type
;
4990 temp_flags
= i
.flags
[xchg2
];
4991 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4992 i
.flags
[xchg1
] = temp_flags
;
4994 temp_op
= i
.op
[xchg2
];
4995 i
.op
[xchg2
] = i
.op
[xchg1
];
4996 i
.op
[xchg1
] = temp_op
;
4998 temp_reloc
= i
.reloc
[xchg2
];
4999 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5000 i
.reloc
[xchg1
] = temp_reloc
;
5004 if (i
.mask
->operand
== xchg1
)
5005 i
.mask
->operand
= xchg2
;
5006 else if (i
.mask
->operand
== xchg2
)
5007 i
.mask
->operand
= xchg1
;
5011 if (i
.broadcast
->operand
== xchg1
)
5012 i
.broadcast
->operand
= xchg2
;
5013 else if (i
.broadcast
->operand
== xchg2
)
5014 i
.broadcast
->operand
= xchg1
;
5018 if (i
.rounding
->operand
== xchg1
)
5019 i
.rounding
->operand
= xchg2
;
5020 else if (i
.rounding
->operand
== xchg2
)
5021 i
.rounding
->operand
= xchg1
;
5026 swap_operands (void)
5032 swap_2_operands (1, i
.operands
- 2);
5036 swap_2_operands (0, i
.operands
- 1);
5042 if (i
.mem_operands
== 2)
5044 const seg_entry
*temp_seg
;
5045 temp_seg
= i
.seg
[0];
5046 i
.seg
[0] = i
.seg
[1];
5047 i
.seg
[1] = temp_seg
;
5051 /* Try to ensure constant immediates are represented in the smallest
5056 char guess_suffix
= 0;
5060 guess_suffix
= i
.suffix
;
5061 else if (i
.reg_operands
)
5063 /* Figure out a suffix from the last register operand specified.
5064 We can't do this properly yet, ie. excluding InOutPortReg,
5065 but the following works for instructions with immediates.
5066 In any case, we can't set i.suffix yet. */
5067 for (op
= i
.operands
; --op
>= 0;)
5068 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5070 guess_suffix
= BYTE_MNEM_SUFFIX
;
5073 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5075 guess_suffix
= WORD_MNEM_SUFFIX
;
5078 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5080 guess_suffix
= LONG_MNEM_SUFFIX
;
5083 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5085 guess_suffix
= QWORD_MNEM_SUFFIX
;
5089 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5090 guess_suffix
= WORD_MNEM_SUFFIX
;
5092 for (op
= i
.operands
; --op
>= 0;)
5093 if (operand_type_check (i
.types
[op
], imm
))
5095 switch (i
.op
[op
].imms
->X_op
)
5098 /* If a suffix is given, this operand may be shortened. */
5099 switch (guess_suffix
)
5101 case LONG_MNEM_SUFFIX
:
5102 i
.types
[op
].bitfield
.imm32
= 1;
5103 i
.types
[op
].bitfield
.imm64
= 1;
5105 case WORD_MNEM_SUFFIX
:
5106 i
.types
[op
].bitfield
.imm16
= 1;
5107 i
.types
[op
].bitfield
.imm32
= 1;
5108 i
.types
[op
].bitfield
.imm32s
= 1;
5109 i
.types
[op
].bitfield
.imm64
= 1;
5111 case BYTE_MNEM_SUFFIX
:
5112 i
.types
[op
].bitfield
.imm8
= 1;
5113 i
.types
[op
].bitfield
.imm8s
= 1;
5114 i
.types
[op
].bitfield
.imm16
= 1;
5115 i
.types
[op
].bitfield
.imm32
= 1;
5116 i
.types
[op
].bitfield
.imm32s
= 1;
5117 i
.types
[op
].bitfield
.imm64
= 1;
5121 /* If this operand is at most 16 bits, convert it
5122 to a signed 16 bit number before trying to see
5123 whether it will fit in an even smaller size.
5124 This allows a 16-bit operand such as $0xffe0 to
5125 be recognised as within Imm8S range. */
5126 if ((i
.types
[op
].bitfield
.imm16
)
5127 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5129 i
.op
[op
].imms
->X_add_number
=
5130 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5133 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5134 if ((i
.types
[op
].bitfield
.imm32
)
5135 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5138 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5139 ^ ((offsetT
) 1 << 31))
5140 - ((offsetT
) 1 << 31));
5144 = operand_type_or (i
.types
[op
],
5145 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5147 /* We must avoid matching of Imm32 templates when 64bit
5148 only immediate is available. */
5149 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5150 i
.types
[op
].bitfield
.imm32
= 0;
5157 /* Symbols and expressions. */
5159 /* Convert symbolic operand to proper sizes for matching, but don't
5160 prevent matching a set of insns that only supports sizes other
5161 than those matching the insn suffix. */
5163 i386_operand_type mask
, allowed
;
5164 const insn_template
*t
;
5166 operand_type_set (&mask
, 0);
5167 operand_type_set (&allowed
, 0);
5169 for (t
= current_templates
->start
;
5170 t
< current_templates
->end
;
5172 allowed
= operand_type_or (allowed
,
5173 t
->operand_types
[op
]);
5174 switch (guess_suffix
)
5176 case QWORD_MNEM_SUFFIX
:
5177 mask
.bitfield
.imm64
= 1;
5178 mask
.bitfield
.imm32s
= 1;
5180 case LONG_MNEM_SUFFIX
:
5181 mask
.bitfield
.imm32
= 1;
5183 case WORD_MNEM_SUFFIX
:
5184 mask
.bitfield
.imm16
= 1;
5186 case BYTE_MNEM_SUFFIX
:
5187 mask
.bitfield
.imm8
= 1;
5192 allowed
= operand_type_and (mask
, allowed
);
5193 if (!operand_type_all_zero (&allowed
))
5194 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5201 /* Try to use the smallest displacement type too. */
5203 optimize_disp (void)
5207 for (op
= i
.operands
; --op
>= 0;)
5208 if (operand_type_check (i
.types
[op
], disp
))
5210 if (i
.op
[op
].disps
->X_op
== O_constant
)
5212 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5214 if (i
.types
[op
].bitfield
.disp16
5215 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5217 /* If this operand is at most 16 bits, convert
5218 to a signed 16 bit number and don't use 64bit
5220 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5221 i
.types
[op
].bitfield
.disp64
= 0;
5224 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5225 if (i
.types
[op
].bitfield
.disp32
5226 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5228 /* If this operand is at most 32 bits, convert
5229 to a signed 32 bit number and don't use 64bit
5231 op_disp
&= (((offsetT
) 2 << 31) - 1);
5232 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5233 i
.types
[op
].bitfield
.disp64
= 0;
5236 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5238 i
.types
[op
].bitfield
.disp8
= 0;
5239 i
.types
[op
].bitfield
.disp16
= 0;
5240 i
.types
[op
].bitfield
.disp32
= 0;
5241 i
.types
[op
].bitfield
.disp32s
= 0;
5242 i
.types
[op
].bitfield
.disp64
= 0;
5246 else if (flag_code
== CODE_64BIT
)
5248 if (fits_in_signed_long (op_disp
))
5250 i
.types
[op
].bitfield
.disp64
= 0;
5251 i
.types
[op
].bitfield
.disp32s
= 1;
5253 if (i
.prefix
[ADDR_PREFIX
]
5254 && fits_in_unsigned_long (op_disp
))
5255 i
.types
[op
].bitfield
.disp32
= 1;
5257 if ((i
.types
[op
].bitfield
.disp32
5258 || i
.types
[op
].bitfield
.disp32s
5259 || i
.types
[op
].bitfield
.disp16
)
5260 && fits_in_disp8 (op_disp
))
5261 i
.types
[op
].bitfield
.disp8
= 1;
5263 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5264 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5266 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5267 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5268 i
.types
[op
].bitfield
.disp8
= 0;
5269 i
.types
[op
].bitfield
.disp16
= 0;
5270 i
.types
[op
].bitfield
.disp32
= 0;
5271 i
.types
[op
].bitfield
.disp32s
= 0;
5272 i
.types
[op
].bitfield
.disp64
= 0;
5275 /* We only support 64bit displacement on constants. */
5276 i
.types
[op
].bitfield
.disp64
= 0;
5280 /* Return 1 if there is a match in broadcast bytes between operand
5281 GIVEN and instruction template T. */
5284 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5286 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5287 && i
.types
[given
].bitfield
.byte
)
5288 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5289 && i
.types
[given
].bitfield
.word
)
5290 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5291 && i
.types
[given
].bitfield
.dword
)
5292 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5293 && i
.types
[given
].bitfield
.qword
));
5296 /* Check if operands are valid for the instruction. */
5299 check_VecOperands (const insn_template
*t
)
5303 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5305 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5306 any one operand are implicity requiring AVX512VL support if the actual
5307 operand size is YMMword or XMMword. Since this function runs after
5308 template matching, there's no need to check for YMMword/XMMword in
5310 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5311 if (!cpu_flags_all_zero (&cpu
)
5312 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5313 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5315 for (op
= 0; op
< t
->operands
; ++op
)
5317 if (t
->operand_types
[op
].bitfield
.zmmword
5318 && (i
.types
[op
].bitfield
.ymmword
5319 || i
.types
[op
].bitfield
.xmmword
))
5321 i
.error
= unsupported
;
5327 /* Without VSIB byte, we can't have a vector register for index. */
5328 if (!t
->opcode_modifier
.vecsib
5330 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5331 || i
.index_reg
->reg_type
.bitfield
.ymmword
5332 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5334 i
.error
= unsupported_vector_index_register
;
5338 /* Check if default mask is allowed. */
5339 if (t
->opcode_modifier
.nodefmask
5340 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5342 i
.error
= no_default_mask
;
5346 /* For VSIB byte, we need a vector register for index, and all vector
5347 registers must be distinct. */
5348 if (t
->opcode_modifier
.vecsib
)
5351 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5352 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5353 || (t
->opcode_modifier
.vecsib
== VecSIB256
5354 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5355 || (t
->opcode_modifier
.vecsib
== VecSIB512
5356 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5358 i
.error
= invalid_vsib_address
;
5362 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5363 if (i
.reg_operands
== 2 && !i
.mask
)
5365 gas_assert (i
.types
[0].bitfield
.regsimd
);
5366 gas_assert (i
.types
[0].bitfield
.xmmword
5367 || i
.types
[0].bitfield
.ymmword
);
5368 gas_assert (i
.types
[2].bitfield
.regsimd
);
5369 gas_assert (i
.types
[2].bitfield
.xmmword
5370 || i
.types
[2].bitfield
.ymmword
);
5371 if (operand_check
== check_none
)
5373 if (register_number (i
.op
[0].regs
)
5374 != register_number (i
.index_reg
)
5375 && register_number (i
.op
[2].regs
)
5376 != register_number (i
.index_reg
)
5377 && register_number (i
.op
[0].regs
)
5378 != register_number (i
.op
[2].regs
))
5380 if (operand_check
== check_error
)
5382 i
.error
= invalid_vector_register_set
;
5385 as_warn (_("mask, index, and destination registers should be distinct"));
5387 else if (i
.reg_operands
== 1 && i
.mask
)
5389 if (i
.types
[1].bitfield
.regsimd
5390 && (i
.types
[1].bitfield
.xmmword
5391 || i
.types
[1].bitfield
.ymmword
5392 || i
.types
[1].bitfield
.zmmword
)
5393 && (register_number (i
.op
[1].regs
)
5394 == register_number (i
.index_reg
)))
5396 if (operand_check
== check_error
)
5398 i
.error
= invalid_vector_register_set
;
5401 if (operand_check
!= check_none
)
5402 as_warn (_("index and destination registers should be distinct"));
5407 /* Check if broadcast is supported by the instruction and is applied
5408 to the memory operand. */
5411 i386_operand_type type
, overlap
;
5413 /* Check if specified broadcast is supported in this instruction,
5414 and its broadcast bytes match the memory operand. */
5415 op
= i
.broadcast
->operand
;
5416 if (!t
->opcode_modifier
.broadcast
5417 || !(i
.flags
[op
] & Operand_Mem
)
5418 || (!i
.types
[op
].bitfield
.unspecified
5419 && !match_broadcast_size (t
, op
)))
5422 i
.error
= unsupported_broadcast
;
5426 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5427 * i
.broadcast
->type
);
5428 operand_type_set (&type
, 0);
5429 switch (i
.broadcast
->bytes
)
5432 type
.bitfield
.word
= 1;
5435 type
.bitfield
.dword
= 1;
5438 type
.bitfield
.qword
= 1;
5441 type
.bitfield
.xmmword
= 1;
5444 type
.bitfield
.ymmword
= 1;
5447 type
.bitfield
.zmmword
= 1;
5453 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5454 if (operand_type_all_zero (&overlap
))
5457 if (t
->opcode_modifier
.checkregsize
)
5461 type
.bitfield
.baseindex
= 1;
5462 for (j
= 0; j
< i
.operands
; ++j
)
5465 && !operand_type_register_match(i
.types
[j
],
5466 t
->operand_types
[j
],
5468 t
->operand_types
[op
]))
5473 /* If broadcast is supported in this instruction, we need to check if
5474 operand of one-element size isn't specified without broadcast. */
5475 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5477 /* Find memory operand. */
5478 for (op
= 0; op
< i
.operands
; op
++)
5479 if (operand_type_check (i
.types
[op
], anymem
))
5481 gas_assert (op
< i
.operands
);
5482 /* Check size of the memory operand. */
5483 if (match_broadcast_size (t
, op
))
5485 i
.error
= broadcast_needed
;
5490 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5492 /* Check if requested masking is supported. */
5495 switch (t
->opcode_modifier
.masking
)
5499 case MERGING_MASKING
:
5500 if (i
.mask
->zeroing
)
5503 i
.error
= unsupported_masking
;
5507 case DYNAMIC_MASKING
:
5508 /* Memory destinations allow only merging masking. */
5509 if (i
.mask
->zeroing
&& i
.mem_operands
)
5511 /* Find memory operand. */
5512 for (op
= 0; op
< i
.operands
; op
++)
5513 if (i
.flags
[op
] & Operand_Mem
)
5515 gas_assert (op
< i
.operands
);
5516 if (op
== i
.operands
- 1)
5518 i
.error
= unsupported_masking
;
5528 /* Check if masking is applied to dest operand. */
5529 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5531 i
.error
= mask_not_on_destination
;
5538 if (!t
->opcode_modifier
.sae
5539 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5541 i
.error
= unsupported_rc_sae
;
5544 /* If the instruction has several immediate operands and one of
5545 them is rounding, the rounding operand should be the last
5546 immediate operand. */
5547 if (i
.imm_operands
> 1
5548 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5550 i
.error
= rc_sae_operand_not_last_imm
;
5555 /* Check vector Disp8 operand. */
5556 if (t
->opcode_modifier
.disp8memshift
5557 && i
.disp_encoding
!= disp_encoding_32bit
)
5560 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5561 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5562 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5565 const i386_operand_type
*type
= NULL
;
5568 for (op
= 0; op
< i
.operands
; op
++)
5569 if (operand_type_check (i
.types
[op
], anymem
))
5571 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5572 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5573 else if (t
->operand_types
[op
].bitfield
.xmmword
5574 + t
->operand_types
[op
].bitfield
.ymmword
5575 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5576 type
= &t
->operand_types
[op
];
5577 else if (!i
.types
[op
].bitfield
.unspecified
)
5578 type
= &i
.types
[op
];
5580 else if (i
.types
[op
].bitfield
.regsimd
5581 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5583 if (i
.types
[op
].bitfield
.zmmword
)
5585 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5587 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5593 if (type
->bitfield
.zmmword
)
5595 else if (type
->bitfield
.ymmword
)
5597 else if (type
->bitfield
.xmmword
)
5601 /* For the check in fits_in_disp8(). */
5602 if (i
.memshift
== 0)
5606 for (op
= 0; op
< i
.operands
; op
++)
5607 if (operand_type_check (i
.types
[op
], disp
)
5608 && i
.op
[op
].disps
->X_op
== O_constant
)
5610 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5612 i
.types
[op
].bitfield
.disp8
= 1;
5615 i
.types
[op
].bitfield
.disp8
= 0;
5624 /* Check if operands are valid for the instruction. Update VEX
5628 VEX_check_operands (const insn_template
*t
)
5630 if (i
.vec_encoding
== vex_encoding_evex
)
5632 /* This instruction must be encoded with EVEX prefix. */
5633 if (!is_evex_encoding (t
))
5635 i
.error
= unsupported
;
5641 if (!t
->opcode_modifier
.vex
)
5643 /* This instruction template doesn't have VEX prefix. */
5644 if (i
.vec_encoding
!= vex_encoding_default
)
5646 i
.error
= unsupported
;
5652 /* Only check VEX_Imm4, which must be the first operand. */
5653 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5655 if (i
.op
[0].imms
->X_op
!= O_constant
5656 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5662 /* Turn off Imm8 so that update_imm won't complain. */
5663 i
.types
[0] = vec_imm4
;
5669 static const insn_template
*
5670 match_template (char mnem_suffix
)
5672 /* Points to template once we've found it. */
5673 const insn_template
*t
;
5674 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5675 i386_operand_type overlap4
;
5676 unsigned int found_reverse_match
;
5677 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5678 i386_operand_type operand_types
[MAX_OPERANDS
];
5679 int addr_prefix_disp
;
5681 unsigned int found_cpu_match
, size_match
;
5682 unsigned int check_register
;
5683 enum i386_error specific_error
= 0;
5685 #if MAX_OPERANDS != 5
5686 # error "MAX_OPERANDS must be 5."
5689 found_reverse_match
= 0;
5690 addr_prefix_disp
= -1;
5692 memset (&suffix_check
, 0, sizeof (suffix_check
));
5693 if (intel_syntax
&& i
.broadcast
)
5695 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5696 suffix_check
.no_bsuf
= 1;
5697 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5698 suffix_check
.no_wsuf
= 1;
5699 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5700 suffix_check
.no_ssuf
= 1;
5701 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5702 suffix_check
.no_lsuf
= 1;
5703 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5704 suffix_check
.no_qsuf
= 1;
5705 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5706 suffix_check
.no_ldsuf
= 1;
5708 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5711 switch (mnem_suffix
)
5713 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5714 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5715 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5716 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5717 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5721 /* Must have right number of operands. */
5722 i
.error
= number_of_operands_mismatch
;
5724 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5726 addr_prefix_disp
= -1;
5727 found_reverse_match
= 0;
5729 if (i
.operands
!= t
->operands
)
5732 /* Check processor support. */
5733 i
.error
= unsupported
;
5734 found_cpu_match
= (cpu_flags_match (t
)
5735 == CPU_FLAGS_PERFECT_MATCH
);
5736 if (!found_cpu_match
)
5739 /* Check AT&T mnemonic. */
5740 i
.error
= unsupported_with_intel_mnemonic
;
5741 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5744 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5745 i
.error
= unsupported_syntax
;
5746 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5747 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5748 || (intel64
&& t
->opcode_modifier
.amd64
)
5749 || (!intel64
&& t
->opcode_modifier
.intel64
))
5752 /* Check the suffix, except for some instructions in intel mode. */
5753 i
.error
= invalid_instruction_suffix
;
5754 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5755 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5756 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5757 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5758 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5759 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5760 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5762 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5763 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5764 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5765 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5766 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5767 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5768 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5771 size_match
= operand_size_match (t
);
5775 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5776 operand_types
[j
] = t
->operand_types
[j
];
5778 /* In general, don't allow 64-bit operands in 32-bit mode. */
5779 if (i
.suffix
== QWORD_MNEM_SUFFIX
5780 && flag_code
!= CODE_64BIT
5782 ? (!t
->opcode_modifier
.ignoresize
5783 && !t
->opcode_modifier
.broadcast
5784 && !intel_float_operand (t
->name
))
5785 : intel_float_operand (t
->name
) != 2)
5786 && ((!operand_types
[0].bitfield
.regmmx
5787 && !operand_types
[0].bitfield
.regsimd
)
5788 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5789 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5790 && (t
->base_opcode
!= 0x0fc7
5791 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5794 /* In general, don't allow 32-bit operands on pre-386. */
5795 else if (i
.suffix
== LONG_MNEM_SUFFIX
5796 && !cpu_arch_flags
.bitfield
.cpui386
5798 ? (!t
->opcode_modifier
.ignoresize
5799 && !intel_float_operand (t
->name
))
5800 : intel_float_operand (t
->name
) != 2)
5801 && ((!operand_types
[0].bitfield
.regmmx
5802 && !operand_types
[0].bitfield
.regsimd
)
5803 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5804 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5807 /* Do not verify operands when there are none. */
5811 /* We've found a match; break out of loop. */
5815 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5816 into Disp32/Disp16/Disp32 operand. */
5817 if (i
.prefix
[ADDR_PREFIX
] != 0)
5819 /* There should be only one Disp operand. */
5823 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5825 if (operand_types
[j
].bitfield
.disp16
)
5827 addr_prefix_disp
= j
;
5828 operand_types
[j
].bitfield
.disp32
= 1;
5829 operand_types
[j
].bitfield
.disp16
= 0;
5835 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5837 if (operand_types
[j
].bitfield
.disp32
)
5839 addr_prefix_disp
= j
;
5840 operand_types
[j
].bitfield
.disp32
= 0;
5841 operand_types
[j
].bitfield
.disp16
= 1;
5847 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5849 if (operand_types
[j
].bitfield
.disp64
)
5851 addr_prefix_disp
= j
;
5852 operand_types
[j
].bitfield
.disp64
= 0;
5853 operand_types
[j
].bitfield
.disp32
= 1;
5861 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5862 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5865 /* We check register size if needed. */
5866 if (t
->opcode_modifier
.checkregsize
)
5868 check_register
= (1 << t
->operands
) - 1;
5870 check_register
&= ~(1 << i
.broadcast
->operand
);
5875 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5876 switch (t
->operands
)
5879 if (!operand_type_match (overlap0
, i
.types
[0]))
5883 /* xchg %eax, %eax is a special case. It is an alias for nop
5884 only in 32bit mode and we can use opcode 0x90. In 64bit
5885 mode, we can't use 0x90 for xchg %eax, %eax since it should
5886 zero-extend %eax to %rax. */
5887 if (flag_code
== CODE_64BIT
5888 && t
->base_opcode
== 0x90
5889 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5890 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5892 /* xrelease mov %eax, <disp> is another special case. It must not
5893 match the accumulator-only encoding of mov. */
5894 if (flag_code
!= CODE_64BIT
5896 && t
->base_opcode
== 0xa0
5897 && i
.types
[0].bitfield
.acc
5898 && operand_type_check (i
.types
[1], anymem
))
5903 if (!(size_match
& MATCH_STRAIGHT
))
5905 /* Reverse direction of operands if swapping is possible in the first
5906 place (operands need to be symmetric) and
5907 - the load form is requested, and the template is a store form,
5908 - the store form is requested, and the template is a load form,
5909 - the non-default (swapped) form is requested. */
5910 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5911 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5912 && !operand_type_all_zero (&overlap1
))
5913 switch (i
.dir_encoding
)
5915 case dir_encoding_load
:
5916 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5917 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5921 case dir_encoding_store
:
5922 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5923 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5927 case dir_encoding_swap
:
5930 case dir_encoding_default
:
5933 /* If we want store form, we skip the current load. */
5934 if ((i
.dir_encoding
== dir_encoding_store
5935 || i
.dir_encoding
== dir_encoding_swap
)
5936 && i
.mem_operands
== 0
5937 && t
->opcode_modifier
.load
)
5942 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5943 if (!operand_type_match (overlap0
, i
.types
[0])
5944 || !operand_type_match (overlap1
, i
.types
[1])
5945 || ((check_register
& 3) == 3
5946 && !operand_type_register_match (i
.types
[0],
5951 /* Check if other direction is valid ... */
5952 if (!t
->opcode_modifier
.d
)
5956 if (!(size_match
& MATCH_REVERSE
))
5958 /* Try reversing direction of operands. */
5959 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5960 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5961 if (!operand_type_match (overlap0
, i
.types
[0])
5962 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5964 && !operand_type_register_match (i
.types
[0],
5965 operand_types
[i
.operands
- 1],
5966 i
.types
[i
.operands
- 1],
5969 /* Does not match either direction. */
5972 /* found_reverse_match holds which of D or FloatR
5974 if (!t
->opcode_modifier
.d
)
5975 found_reverse_match
= 0;
5976 else if (operand_types
[0].bitfield
.tbyte
)
5977 found_reverse_match
= Opcode_FloatD
;
5978 else if (operand_types
[0].bitfield
.xmmword
5979 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5980 || operand_types
[0].bitfield
.regmmx
5981 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5982 || is_any_vex_encoding(t
))
5983 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5984 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5986 found_reverse_match
= Opcode_D
;
5987 if (t
->opcode_modifier
.floatr
)
5988 found_reverse_match
|= Opcode_FloatR
;
5992 /* Found a forward 2 operand match here. */
5993 switch (t
->operands
)
5996 overlap4
= operand_type_and (i
.types
[4],
6000 overlap3
= operand_type_and (i
.types
[3],
6004 overlap2
= operand_type_and (i
.types
[2],
6009 switch (t
->operands
)
6012 if (!operand_type_match (overlap4
, i
.types
[4])
6013 || !operand_type_register_match (i
.types
[3],
6020 if (!operand_type_match (overlap3
, i
.types
[3])
6021 || ((check_register
& 0xa) == 0xa
6022 && !operand_type_register_match (i
.types
[1],
6026 || ((check_register
& 0xc) == 0xc
6027 && !operand_type_register_match (i
.types
[2],
6034 /* Here we make use of the fact that there are no
6035 reverse match 3 operand instructions. */
6036 if (!operand_type_match (overlap2
, i
.types
[2])
6037 || ((check_register
& 5) == 5
6038 && !operand_type_register_match (i
.types
[0],
6042 || ((check_register
& 6) == 6
6043 && !operand_type_register_match (i
.types
[1],
6051 /* Found either forward/reverse 2, 3 or 4 operand match here:
6052 slip through to break. */
6054 if (!found_cpu_match
)
6057 /* Check if vector and VEX operands are valid. */
6058 if (check_VecOperands (t
) || VEX_check_operands (t
))
6060 specific_error
= i
.error
;
6064 /* We've found a match; break out of loop. */
6068 if (t
== current_templates
->end
)
6070 /* We found no match. */
6071 const char *err_msg
;
6072 switch (specific_error
? specific_error
: i
.error
)
6076 case operand_size_mismatch
:
6077 err_msg
= _("operand size mismatch");
6079 case operand_type_mismatch
:
6080 err_msg
= _("operand type mismatch");
6082 case register_type_mismatch
:
6083 err_msg
= _("register type mismatch");
6085 case number_of_operands_mismatch
:
6086 err_msg
= _("number of operands mismatch");
6088 case invalid_instruction_suffix
:
6089 err_msg
= _("invalid instruction suffix");
6092 err_msg
= _("constant doesn't fit in 4 bits");
6094 case unsupported_with_intel_mnemonic
:
6095 err_msg
= _("unsupported with Intel mnemonic");
6097 case unsupported_syntax
:
6098 err_msg
= _("unsupported syntax");
6101 as_bad (_("unsupported instruction `%s'"),
6102 current_templates
->start
->name
);
6104 case invalid_vsib_address
:
6105 err_msg
= _("invalid VSIB address");
6107 case invalid_vector_register_set
:
6108 err_msg
= _("mask, index, and destination registers must be distinct");
6110 case unsupported_vector_index_register
:
6111 err_msg
= _("unsupported vector index register");
6113 case unsupported_broadcast
:
6114 err_msg
= _("unsupported broadcast");
6116 case broadcast_needed
:
6117 err_msg
= _("broadcast is needed for operand of such type");
6119 case unsupported_masking
:
6120 err_msg
= _("unsupported masking");
6122 case mask_not_on_destination
:
6123 err_msg
= _("mask not on destination operand");
6125 case no_default_mask
:
6126 err_msg
= _("default mask isn't allowed");
6128 case unsupported_rc_sae
:
6129 err_msg
= _("unsupported static rounding/sae");
6131 case rc_sae_operand_not_last_imm
:
6133 err_msg
= _("RC/SAE operand must precede immediate operands");
6135 err_msg
= _("RC/SAE operand must follow immediate operands");
6137 case invalid_register_operand
:
6138 err_msg
= _("invalid register operand");
6141 as_bad (_("%s for `%s'"), err_msg
,
6142 current_templates
->start
->name
);
6146 if (!quiet_warnings
)
6149 && (i
.types
[0].bitfield
.jumpabsolute
6150 != operand_types
[0].bitfield
.jumpabsolute
))
6152 as_warn (_("indirect %s without `*'"), t
->name
);
6155 if (t
->opcode_modifier
.isprefix
6156 && t
->opcode_modifier
.ignoresize
)
6158 /* Warn them that a data or address size prefix doesn't
6159 affect assembly of the next line of code. */
6160 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6164 /* Copy the template we found. */
6167 if (addr_prefix_disp
!= -1)
6168 i
.tm
.operand_types
[addr_prefix_disp
]
6169 = operand_types
[addr_prefix_disp
];
6171 if (found_reverse_match
)
6173 /* If we found a reverse match we must alter the opcode
6174 direction bit. found_reverse_match holds bits to change
6175 (different for int & float insns). */
6177 i
.tm
.base_opcode
^= found_reverse_match
;
6179 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6180 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6189 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6190 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6192 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6194 as_bad (_("`%s' operand %d must use `%ses' segment"),
6200 /* There's only ever one segment override allowed per instruction.
6201 This instruction possibly has a legal segment override on the
6202 second operand, so copy the segment to where non-string
6203 instructions store it, allowing common code. */
6204 i
.seg
[0] = i
.seg
[1];
6206 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6208 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6210 as_bad (_("`%s' operand %d must use `%ses' segment"),
6221 process_suffix (void)
6223 /* If matched instruction specifies an explicit instruction mnemonic
6225 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6226 i
.suffix
= WORD_MNEM_SUFFIX
;
6227 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6228 i
.suffix
= LONG_MNEM_SUFFIX
;
6229 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6230 i
.suffix
= QWORD_MNEM_SUFFIX
;
6231 else if (i
.reg_operands
)
6233 /* If there's no instruction mnemonic suffix we try to invent one
6234 based on register operands. */
6237 /* We take i.suffix from the last register operand specified,
6238 Destination register type is more significant than source
6239 register type. crc32 in SSE4.2 prefers source register
6241 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6243 if (i
.types
[0].bitfield
.byte
)
6244 i
.suffix
= BYTE_MNEM_SUFFIX
;
6245 else if (i
.types
[0].bitfield
.word
)
6246 i
.suffix
= WORD_MNEM_SUFFIX
;
6247 else if (i
.types
[0].bitfield
.dword
)
6248 i
.suffix
= LONG_MNEM_SUFFIX
;
6249 else if (i
.types
[0].bitfield
.qword
)
6250 i
.suffix
= QWORD_MNEM_SUFFIX
;
6257 if (i
.tm
.base_opcode
== 0xf20f38f0)
6259 /* We have to know the operand size for crc32. */
6260 as_bad (_("ambiguous memory operand size for `%s`"),
6265 for (op
= i
.operands
; --op
>= 0;)
6266 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6267 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6269 if (!i
.types
[op
].bitfield
.reg
)
6271 if (i
.types
[op
].bitfield
.byte
)
6272 i
.suffix
= BYTE_MNEM_SUFFIX
;
6273 else if (i
.types
[op
].bitfield
.word
)
6274 i
.suffix
= WORD_MNEM_SUFFIX
;
6275 else if (i
.types
[op
].bitfield
.dword
)
6276 i
.suffix
= LONG_MNEM_SUFFIX
;
6277 else if (i
.types
[op
].bitfield
.qword
)
6278 i
.suffix
= QWORD_MNEM_SUFFIX
;
6285 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6288 && i
.tm
.opcode_modifier
.ignoresize
6289 && i
.tm
.opcode_modifier
.no_bsuf
)
6291 else if (!check_byte_reg ())
6294 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6297 && i
.tm
.opcode_modifier
.ignoresize
6298 && i
.tm
.opcode_modifier
.no_lsuf
6299 && !i
.tm
.opcode_modifier
.todword
6300 && !i
.tm
.opcode_modifier
.toqword
)
6302 else if (!check_long_reg ())
6305 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6308 && i
.tm
.opcode_modifier
.ignoresize
6309 && i
.tm
.opcode_modifier
.no_qsuf
6310 && !i
.tm
.opcode_modifier
.todword
6311 && !i
.tm
.opcode_modifier
.toqword
)
6313 else if (!check_qword_reg ())
6316 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6319 && i
.tm
.opcode_modifier
.ignoresize
6320 && i
.tm
.opcode_modifier
.no_wsuf
)
6322 else if (!check_word_reg ())
6325 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6326 /* Do nothing if the instruction is going to ignore the prefix. */
6331 else if (i
.tm
.opcode_modifier
.defaultsize
6333 /* exclude fldenv/frstor/fsave/fstenv */
6334 && i
.tm
.opcode_modifier
.no_ssuf
)
6336 if (stackop_size
== LONG_MNEM_SUFFIX
6337 && i
.tm
.base_opcode
== 0xcf)
6339 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6340 .code16gcc directive to support 16-bit mode with
6341 32-bit address. For IRET without a suffix, generate
6342 16-bit IRET (opcode 0xcf) to return from an interrupt
6344 i
.suffix
= WORD_MNEM_SUFFIX
;
6345 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6348 i
.suffix
= stackop_size
;
6350 else if (intel_syntax
6352 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6353 || i
.tm
.opcode_modifier
.jumpbyte
6354 || i
.tm
.opcode_modifier
.jumpintersegment
6355 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6356 && i
.tm
.extension_opcode
<= 3)))
6361 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6363 i
.suffix
= QWORD_MNEM_SUFFIX
;
6368 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6369 i
.suffix
= LONG_MNEM_SUFFIX
;
6372 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6373 i
.suffix
= WORD_MNEM_SUFFIX
;
6382 if (i
.tm
.opcode_modifier
.w
)
6384 as_bad (_("no instruction mnemonic suffix given and "
6385 "no register operands; can't size instruction"));
6391 unsigned int suffixes
;
6393 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6394 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6396 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6398 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6400 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6402 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6405 /* There are more than suffix matches. */
6406 if (i
.tm
.opcode_modifier
.w
6407 || ((suffixes
& (suffixes
- 1))
6408 && !i
.tm
.opcode_modifier
.defaultsize
6409 && !i
.tm
.opcode_modifier
.ignoresize
))
6411 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6417 /* Change the opcode based on the operand size given by i.suffix. */
6420 /* Size floating point instruction. */
6421 case LONG_MNEM_SUFFIX
:
6422 if (i
.tm
.opcode_modifier
.floatmf
)
6424 i
.tm
.base_opcode
^= 4;
6428 case WORD_MNEM_SUFFIX
:
6429 case QWORD_MNEM_SUFFIX
:
6430 /* It's not a byte, select word/dword operation. */
6431 if (i
.tm
.opcode_modifier
.w
)
6433 if (i
.tm
.opcode_modifier
.shortform
)
6434 i
.tm
.base_opcode
|= 8;
6436 i
.tm
.base_opcode
|= 1;
6439 case SHORT_MNEM_SUFFIX
:
6440 /* Now select between word & dword operations via the operand
6441 size prefix, except for instructions that will ignore this
6443 if (i
.reg_operands
> 0
6444 && i
.types
[0].bitfield
.reg
6445 && i
.tm
.opcode_modifier
.addrprefixopreg
6446 && (i
.tm
.opcode_modifier
.immext
6447 || i
.operands
== 1))
6449 /* The address size override prefix changes the size of the
6451 if ((flag_code
== CODE_32BIT
6452 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6453 || (flag_code
!= CODE_32BIT
6454 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6455 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6458 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6459 && !i
.tm
.opcode_modifier
.ignoresize
6460 && !i
.tm
.opcode_modifier
.floatmf
6461 && !is_any_vex_encoding (&i
.tm
)
6462 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6463 || (flag_code
== CODE_64BIT
6464 && i
.tm
.opcode_modifier
.jumpbyte
)))
6466 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6468 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6469 prefix
= ADDR_PREFIX_OPCODE
;
6471 if (!add_prefix (prefix
))
6475 /* Set mode64 for an operand. */
6476 if (i
.suffix
== QWORD_MNEM_SUFFIX
6477 && flag_code
== CODE_64BIT
6478 && !i
.tm
.opcode_modifier
.norex64
6479 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6481 && ! (i
.operands
== 2
6482 && i
.tm
.base_opcode
== 0x90
6483 && i
.tm
.extension_opcode
== None
6484 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6485 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6491 if (i
.reg_operands
!= 0
6493 && i
.tm
.opcode_modifier
.addrprefixopreg
6494 && !i
.tm
.opcode_modifier
.immext
)
6496 /* Check invalid register operand when the address size override
6497 prefix changes the size of register operands. */
6499 enum { need_word
, need_dword
, need_qword
} need
;
6501 if (flag_code
== CODE_32BIT
)
6502 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6505 if (i
.prefix
[ADDR_PREFIX
])
6508 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6511 for (op
= 0; op
< i
.operands
; op
++)
6512 if (i
.types
[op
].bitfield
.reg
6513 && ((need
== need_word
6514 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6515 || (need
== need_dword
6516 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6517 || (need
== need_qword
6518 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6520 as_bad (_("invalid register operand size for `%s'"),
6530 check_byte_reg (void)
6534 for (op
= i
.operands
; --op
>= 0;)
6536 /* Skip non-register operands. */
6537 if (!i
.types
[op
].bitfield
.reg
)
6540 /* If this is an eight bit register, it's OK. If it's the 16 or
6541 32 bit version of an eight bit register, we will just use the
6542 low portion, and that's OK too. */
6543 if (i
.types
[op
].bitfield
.byte
)
6546 /* I/O port address operands are OK too. */
6547 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6550 /* crc32 doesn't generate this warning. */
6551 if (i
.tm
.base_opcode
== 0xf20f38f0)
6554 if ((i
.types
[op
].bitfield
.word
6555 || i
.types
[op
].bitfield
.dword
6556 || i
.types
[op
].bitfield
.qword
)
6557 && i
.op
[op
].regs
->reg_num
< 4
6558 /* Prohibit these changes in 64bit mode, since the lowering
6559 would be more complicated. */
6560 && flag_code
!= CODE_64BIT
)
6562 #if REGISTER_WARNINGS
6563 if (!quiet_warnings
)
6564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6566 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6567 ? REGNAM_AL
- REGNAM_AX
6568 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6570 i
.op
[op
].regs
->reg_name
,
6575 /* Any other register is bad. */
6576 if (i
.types
[op
].bitfield
.reg
6577 || i
.types
[op
].bitfield
.regmmx
6578 || i
.types
[op
].bitfield
.regsimd
6579 || i
.types
[op
].bitfield
.sreg2
6580 || i
.types
[op
].bitfield
.sreg3
6581 || i
.types
[op
].bitfield
.control
6582 || i
.types
[op
].bitfield
.debug
6583 || i
.types
[op
].bitfield
.test
)
6585 as_bad (_("`%s%s' not allowed with `%s%c'"),
6587 i
.op
[op
].regs
->reg_name
,
6597 check_long_reg (void)
6601 for (op
= i
.operands
; --op
>= 0;)
6602 /* Skip non-register operands. */
6603 if (!i
.types
[op
].bitfield
.reg
)
6605 /* Reject eight bit registers, except where the template requires
6606 them. (eg. movzb) */
6607 else if (i
.types
[op
].bitfield
.byte
6608 && (i
.tm
.operand_types
[op
].bitfield
.reg
6609 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6610 && (i
.tm
.operand_types
[op
].bitfield
.word
6611 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6613 as_bad (_("`%s%s' not allowed with `%s%c'"),
6615 i
.op
[op
].regs
->reg_name
,
6620 /* Warn if the e prefix on a general reg is missing. */
6621 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6622 && i
.types
[op
].bitfield
.word
6623 && (i
.tm
.operand_types
[op
].bitfield
.reg
6624 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6625 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6627 /* Prohibit these changes in the 64bit mode, since the
6628 lowering is more complicated. */
6629 if (flag_code
== CODE_64BIT
)
6631 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6632 register_prefix
, i
.op
[op
].regs
->reg_name
,
6636 #if REGISTER_WARNINGS
6637 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6639 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6640 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6643 /* Warn if the r prefix on a general reg is present. */
6644 else if (i
.types
[op
].bitfield
.qword
6645 && (i
.tm
.operand_types
[op
].bitfield
.reg
6646 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6647 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6650 && i
.tm
.opcode_modifier
.toqword
6651 && !i
.types
[0].bitfield
.regsimd
)
6653 /* Convert to QWORD. We want REX byte. */
6654 i
.suffix
= QWORD_MNEM_SUFFIX
;
6658 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6659 register_prefix
, i
.op
[op
].regs
->reg_name
,
6668 check_qword_reg (void)
6672 for (op
= i
.operands
; --op
>= 0; )
6673 /* Skip non-register operands. */
6674 if (!i
.types
[op
].bitfield
.reg
)
6676 /* Reject eight bit registers, except where the template requires
6677 them. (eg. movzb) */
6678 else if (i
.types
[op
].bitfield
.byte
6679 && (i
.tm
.operand_types
[op
].bitfield
.reg
6680 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6681 && (i
.tm
.operand_types
[op
].bitfield
.word
6682 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6684 as_bad (_("`%s%s' not allowed with `%s%c'"),
6686 i
.op
[op
].regs
->reg_name
,
6691 /* Warn if the r prefix on a general reg is missing. */
6692 else if ((i
.types
[op
].bitfield
.word
6693 || i
.types
[op
].bitfield
.dword
)
6694 && (i
.tm
.operand_types
[op
].bitfield
.reg
6695 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6696 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6698 /* Prohibit these changes in the 64bit mode, since the
6699 lowering is more complicated. */
6701 && i
.tm
.opcode_modifier
.todword
6702 && !i
.types
[0].bitfield
.regsimd
)
6704 /* Convert to DWORD. We don't want REX byte. */
6705 i
.suffix
= LONG_MNEM_SUFFIX
;
6709 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6710 register_prefix
, i
.op
[op
].regs
->reg_name
,
6719 check_word_reg (void)
6722 for (op
= i
.operands
; --op
>= 0;)
6723 /* Skip non-register operands. */
6724 if (!i
.types
[op
].bitfield
.reg
)
6726 /* Reject eight bit registers, except where the template requires
6727 them. (eg. movzb) */
6728 else if (i
.types
[op
].bitfield
.byte
6729 && (i
.tm
.operand_types
[op
].bitfield
.reg
6730 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6731 && (i
.tm
.operand_types
[op
].bitfield
.word
6732 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6734 as_bad (_("`%s%s' not allowed with `%s%c'"),
6736 i
.op
[op
].regs
->reg_name
,
6741 /* Warn if the e or r prefix on a general reg is present. */
6742 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6743 && (i
.types
[op
].bitfield
.dword
6744 || i
.types
[op
].bitfield
.qword
)
6745 && (i
.tm
.operand_types
[op
].bitfield
.reg
6746 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6747 && i
.tm
.operand_types
[op
].bitfield
.word
)
6749 /* Prohibit these changes in the 64bit mode, since the
6750 lowering is more complicated. */
6751 if (flag_code
== CODE_64BIT
)
6753 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6754 register_prefix
, i
.op
[op
].regs
->reg_name
,
6758 #if REGISTER_WARNINGS
6759 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6761 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6762 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6769 update_imm (unsigned int j
)
6771 i386_operand_type overlap
= i
.types
[j
];
6772 if ((overlap
.bitfield
.imm8
6773 || overlap
.bitfield
.imm8s
6774 || overlap
.bitfield
.imm16
6775 || overlap
.bitfield
.imm32
6776 || overlap
.bitfield
.imm32s
6777 || overlap
.bitfield
.imm64
)
6778 && !operand_type_equal (&overlap
, &imm8
)
6779 && !operand_type_equal (&overlap
, &imm8s
)
6780 && !operand_type_equal (&overlap
, &imm16
)
6781 && !operand_type_equal (&overlap
, &imm32
)
6782 && !operand_type_equal (&overlap
, &imm32s
)
6783 && !operand_type_equal (&overlap
, &imm64
))
6787 i386_operand_type temp
;
6789 operand_type_set (&temp
, 0);
6790 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6792 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6793 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6795 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6796 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6797 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6799 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6800 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6803 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6806 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6807 || operand_type_equal (&overlap
, &imm16_32
)
6808 || operand_type_equal (&overlap
, &imm16_32s
))
6810 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6815 if (!operand_type_equal (&overlap
, &imm8
)
6816 && !operand_type_equal (&overlap
, &imm8s
)
6817 && !operand_type_equal (&overlap
, &imm16
)
6818 && !operand_type_equal (&overlap
, &imm32
)
6819 && !operand_type_equal (&overlap
, &imm32s
)
6820 && !operand_type_equal (&overlap
, &imm64
))
6822 as_bad (_("no instruction mnemonic suffix given; "
6823 "can't determine immediate size"));
6827 i
.types
[j
] = overlap
;
6837 /* Update the first 2 immediate operands. */
6838 n
= i
.operands
> 2 ? 2 : i
.operands
;
6841 for (j
= 0; j
< n
; j
++)
6842 if (update_imm (j
) == 0)
6845 /* The 3rd operand can't be immediate operand. */
6846 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6853 process_operands (void)
6855 /* Default segment register this instruction will use for memory
6856 accesses. 0 means unknown. This is only for optimizing out
6857 unnecessary segment overrides. */
6858 const seg_entry
*default_seg
= 0;
6860 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6862 unsigned int dupl
= i
.operands
;
6863 unsigned int dest
= dupl
- 1;
6866 /* The destination must be an xmm register. */
6867 gas_assert (i
.reg_operands
6868 && MAX_OPERANDS
> dupl
6869 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6871 if (i
.tm
.operand_types
[0].bitfield
.acc
6872 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6874 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6876 /* Keep xmm0 for instructions with VEX prefix and 3
6878 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6879 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6884 /* We remove the first xmm0 and keep the number of
6885 operands unchanged, which in fact duplicates the
6887 for (j
= 1; j
< i
.operands
; j
++)
6889 i
.op
[j
- 1] = i
.op
[j
];
6890 i
.types
[j
- 1] = i
.types
[j
];
6891 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6895 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6897 gas_assert ((MAX_OPERANDS
- 1) > dupl
6898 && (i
.tm
.opcode_modifier
.vexsources
6901 /* Add the implicit xmm0 for instructions with VEX prefix
6903 for (j
= i
.operands
; j
> 0; j
--)
6905 i
.op
[j
] = i
.op
[j
- 1];
6906 i
.types
[j
] = i
.types
[j
- 1];
6907 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6910 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6911 i
.types
[0] = regxmm
;
6912 i
.tm
.operand_types
[0] = regxmm
;
6915 i
.reg_operands
+= 2;
6920 i
.op
[dupl
] = i
.op
[dest
];
6921 i
.types
[dupl
] = i
.types
[dest
];
6922 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6931 i
.op
[dupl
] = i
.op
[dest
];
6932 i
.types
[dupl
] = i
.types
[dest
];
6933 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6936 if (i
.tm
.opcode_modifier
.immext
)
6939 else if (i
.tm
.operand_types
[0].bitfield
.acc
6940 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6944 for (j
= 1; j
< i
.operands
; j
++)
6946 i
.op
[j
- 1] = i
.op
[j
];
6947 i
.types
[j
- 1] = i
.types
[j
];
6949 /* We need to adjust fields in i.tm since they are used by
6950 build_modrm_byte. */
6951 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6958 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6960 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6962 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6963 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6964 regnum
= register_number (i
.op
[1].regs
);
6965 first_reg_in_group
= regnum
& ~3;
6966 last_reg_in_group
= first_reg_in_group
+ 3;
6967 if (regnum
!= first_reg_in_group
)
6968 as_warn (_("source register `%s%s' implicitly denotes"
6969 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6970 register_prefix
, i
.op
[1].regs
->reg_name
,
6971 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6972 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6975 else if (i
.tm
.opcode_modifier
.regkludge
)
6977 /* The imul $imm, %reg instruction is converted into
6978 imul $imm, %reg, %reg, and the clr %reg instruction
6979 is converted into xor %reg, %reg. */
6981 unsigned int first_reg_op
;
6983 if (operand_type_check (i
.types
[0], reg
))
6987 /* Pretend we saw the extra register operand. */
6988 gas_assert (i
.reg_operands
== 1
6989 && i
.op
[first_reg_op
+ 1].regs
== 0);
6990 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6991 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6996 if (i
.tm
.opcode_modifier
.shortform
)
6998 if (i
.types
[0].bitfield
.sreg2
6999 || i
.types
[0].bitfield
.sreg3
)
7001 if (i
.tm
.base_opcode
== POP_SEG_SHORT
7002 && i
.op
[0].regs
->reg_num
== 1)
7004 as_bad (_("you can't `pop %scs'"), register_prefix
);
7007 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7008 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
7013 /* The register or float register operand is in operand
7017 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
7018 || operand_type_check (i
.types
[0], reg
))
7022 /* Register goes in low 3 bits of opcode. */
7023 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7024 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7026 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7028 /* Warn about some common errors, but press on regardless.
7029 The first case can be generated by gcc (<= 2.8.1). */
7030 if (i
.operands
== 2)
7032 /* Reversed arguments on faddp, fsubp, etc. */
7033 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7034 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7035 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7039 /* Extraneous `l' suffix on fp insn. */
7040 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7041 register_prefix
, i
.op
[0].regs
->reg_name
);
7046 else if (i
.tm
.opcode_modifier
.modrm
)
7048 /* The opcode is completed (modulo i.tm.extension_opcode which
7049 must be put into the modrm byte). Now, we make the modrm and
7050 index base bytes based on all the info we've collected. */
7052 default_seg
= build_modrm_byte ();
7054 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7058 else if (i
.tm
.opcode_modifier
.isstring
)
7060 /* For the string instructions that allow a segment override
7061 on one of their operands, the default segment is ds. */
7065 if (i
.tm
.base_opcode
== 0x8d /* lea */
7068 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7070 /* If a segment was explicitly specified, and the specified segment
7071 is not the default, use an opcode prefix to select it. If we
7072 never figured out what the default segment is, then default_seg
7073 will be zero at this point, and the specified segment prefix will
7075 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7077 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7083 static const seg_entry
*
7084 build_modrm_byte (void)
7086 const seg_entry
*default_seg
= 0;
7087 unsigned int source
, dest
;
7090 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7093 unsigned int nds
, reg_slot
;
7096 dest
= i
.operands
- 1;
7099 /* There are 2 kinds of instructions:
7100 1. 5 operands: 4 register operands or 3 register operands
7101 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7102 VexW0 or VexW1. The destination must be either XMM, YMM or
7104 2. 4 operands: 4 register operands or 3 register operands
7105 plus 1 memory operand, with VexXDS. */
7106 gas_assert ((i
.reg_operands
== 4
7107 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7108 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7109 && i
.tm
.opcode_modifier
.vexw
7110 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7112 /* If VexW1 is set, the first non-immediate operand is the source and
7113 the second non-immediate one is encoded in the immediate operand. */
7114 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7116 source
= i
.imm_operands
;
7117 reg_slot
= i
.imm_operands
+ 1;
7121 source
= i
.imm_operands
+ 1;
7122 reg_slot
= i
.imm_operands
;
7125 if (i
.imm_operands
== 0)
7127 /* When there is no immediate operand, generate an 8bit
7128 immediate operand to encode the first operand. */
7129 exp
= &im_expressions
[i
.imm_operands
++];
7130 i
.op
[i
.operands
].imms
= exp
;
7131 i
.types
[i
.operands
] = imm8
;
7134 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7135 exp
->X_op
= O_constant
;
7136 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7137 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7141 unsigned int imm_slot
;
7143 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7145 if (i
.tm
.opcode_modifier
.immext
)
7147 /* When ImmExt is set, the immediate byte is the last
7149 imm_slot
= i
.operands
- 1;
7157 /* Turn on Imm8 so that output_imm will generate it. */
7158 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7161 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7162 i
.op
[imm_slot
].imms
->X_add_number
7163 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7164 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7167 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7168 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7173 /* i.reg_operands MUST be the number of real register operands;
7174 implicit registers do not count. If there are 3 register
7175 operands, it must be a instruction with VexNDS. For a
7176 instruction with VexNDD, the destination register is encoded
7177 in VEX prefix. If there are 4 register operands, it must be
7178 a instruction with VEX prefix and 3 sources. */
7179 if (i
.mem_operands
== 0
7180 && ((i
.reg_operands
== 2
7181 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7182 || (i
.reg_operands
== 3
7183 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7184 || (i
.reg_operands
== 4 && vex_3_sources
)))
7192 /* When there are 3 operands, one of them may be immediate,
7193 which may be the first or the last operand. Otherwise,
7194 the first operand must be shift count register (cl) or it
7195 is an instruction with VexNDS. */
7196 gas_assert (i
.imm_operands
== 1
7197 || (i
.imm_operands
== 0
7198 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7199 || i
.types
[0].bitfield
.shiftcount
)));
7200 if (operand_type_check (i
.types
[0], imm
)
7201 || i
.types
[0].bitfield
.shiftcount
)
7207 /* When there are 4 operands, the first two must be 8bit
7208 immediate operands. The source operand will be the 3rd
7211 For instructions with VexNDS, if the first operand
7212 an imm8, the source operand is the 2nd one. If the last
7213 operand is imm8, the source operand is the first one. */
7214 gas_assert ((i
.imm_operands
== 2
7215 && i
.types
[0].bitfield
.imm8
7216 && i
.types
[1].bitfield
.imm8
)
7217 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7218 && i
.imm_operands
== 1
7219 && (i
.types
[0].bitfield
.imm8
7220 || i
.types
[i
.operands
- 1].bitfield
.imm8
7222 if (i
.imm_operands
== 2)
7226 if (i
.types
[0].bitfield
.imm8
)
7233 if (is_evex_encoding (&i
.tm
))
7235 /* For EVEX instructions, when there are 5 operands, the
7236 first one must be immediate operand. If the second one
7237 is immediate operand, the source operand is the 3th
7238 one. If the last one is immediate operand, the source
7239 operand is the 2nd one. */
7240 gas_assert (i
.imm_operands
== 2
7241 && i
.tm
.opcode_modifier
.sae
7242 && operand_type_check (i
.types
[0], imm
));
7243 if (operand_type_check (i
.types
[1], imm
))
7245 else if (operand_type_check (i
.types
[4], imm
))
7259 /* RC/SAE operand could be between DEST and SRC. That happens
7260 when one operand is GPR and the other one is XMM/YMM/ZMM
7262 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7265 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7267 /* For instructions with VexNDS, the register-only source
7268 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7269 register. It is encoded in VEX prefix. We need to
7270 clear RegMem bit before calling operand_type_equal. */
7272 i386_operand_type op
;
7275 /* Check register-only source operand when two source
7276 operands are swapped. */
7277 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7278 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7286 op
= i
.tm
.operand_types
[vvvv
];
7287 op
.bitfield
.regmem
= 0;
7288 if ((dest
+ 1) >= i
.operands
7289 || ((!op
.bitfield
.reg
7290 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7291 && !op
.bitfield
.regsimd
7292 && !operand_type_equal (&op
, ®mask
)))
7294 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7300 /* One of the register operands will be encoded in the i.tm.reg
7301 field, the other in the combined i.tm.mode and i.tm.regmem
7302 fields. If no form of this instruction supports a memory
7303 destination operand, then we assume the source operand may
7304 sometimes be a memory operand and so we need to store the
7305 destination in the i.rm.reg field. */
7306 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7307 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7309 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7310 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7311 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7312 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7313 i
.has_regmmx
= TRUE
;
7314 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7315 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7317 if (i
.types
[dest
].bitfield
.zmmword
7318 || i
.types
[source
].bitfield
.zmmword
)
7319 i
.has_regzmm
= TRUE
;
7320 else if (i
.types
[dest
].bitfield
.ymmword
7321 || i
.types
[source
].bitfield
.ymmword
)
7322 i
.has_regymm
= TRUE
;
7324 i
.has_regxmm
= TRUE
;
7326 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7328 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7330 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7332 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7337 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7338 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7339 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7341 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7343 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7345 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7348 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7350 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7353 add_prefix (LOCK_PREFIX_OPCODE
);
7357 { /* If it's not 2 reg operands... */
7362 unsigned int fake_zero_displacement
= 0;
7365 for (op
= 0; op
< i
.operands
; op
++)
7366 if (operand_type_check (i
.types
[op
], anymem
))
7368 gas_assert (op
< i
.operands
);
7370 if (i
.tm
.opcode_modifier
.vecsib
)
7372 if (i
.index_reg
->reg_num
== RegIZ
)
7375 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7378 i
.sib
.base
= NO_BASE_REGISTER
;
7379 i
.sib
.scale
= i
.log2_scale_factor
;
7380 i
.types
[op
].bitfield
.disp8
= 0;
7381 i
.types
[op
].bitfield
.disp16
= 0;
7382 i
.types
[op
].bitfield
.disp64
= 0;
7383 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7385 /* Must be 32 bit */
7386 i
.types
[op
].bitfield
.disp32
= 1;
7387 i
.types
[op
].bitfield
.disp32s
= 0;
7391 i
.types
[op
].bitfield
.disp32
= 0;
7392 i
.types
[op
].bitfield
.disp32s
= 1;
7395 i
.sib
.index
= i
.index_reg
->reg_num
;
7396 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7398 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7404 if (i
.base_reg
== 0)
7407 if (!i
.disp_operands
)
7408 fake_zero_displacement
= 1;
7409 if (i
.index_reg
== 0)
7411 i386_operand_type newdisp
;
7413 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7414 /* Operand is just <disp> */
7415 if (flag_code
== CODE_64BIT
)
7417 /* 64bit mode overwrites the 32bit absolute
7418 addressing by RIP relative addressing and
7419 absolute addressing is encoded by one of the
7420 redundant SIB forms. */
7421 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7422 i
.sib
.base
= NO_BASE_REGISTER
;
7423 i
.sib
.index
= NO_INDEX_REGISTER
;
7424 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7426 else if ((flag_code
== CODE_16BIT
)
7427 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7429 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7434 i
.rm
.regmem
= NO_BASE_REGISTER
;
7437 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7438 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7440 else if (!i
.tm
.opcode_modifier
.vecsib
)
7442 /* !i.base_reg && i.index_reg */
7443 if (i
.index_reg
->reg_num
== RegIZ
)
7444 i
.sib
.index
= NO_INDEX_REGISTER
;
7446 i
.sib
.index
= i
.index_reg
->reg_num
;
7447 i
.sib
.base
= NO_BASE_REGISTER
;
7448 i
.sib
.scale
= i
.log2_scale_factor
;
7449 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7450 i
.types
[op
].bitfield
.disp8
= 0;
7451 i
.types
[op
].bitfield
.disp16
= 0;
7452 i
.types
[op
].bitfield
.disp64
= 0;
7453 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7455 /* Must be 32 bit */
7456 i
.types
[op
].bitfield
.disp32
= 1;
7457 i
.types
[op
].bitfield
.disp32s
= 0;
7461 i
.types
[op
].bitfield
.disp32
= 0;
7462 i
.types
[op
].bitfield
.disp32s
= 1;
7464 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7468 /* RIP addressing for 64bit mode. */
7469 else if (i
.base_reg
->reg_num
== RegIP
)
7471 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7472 i
.rm
.regmem
= NO_BASE_REGISTER
;
7473 i
.types
[op
].bitfield
.disp8
= 0;
7474 i
.types
[op
].bitfield
.disp16
= 0;
7475 i
.types
[op
].bitfield
.disp32
= 0;
7476 i
.types
[op
].bitfield
.disp32s
= 1;
7477 i
.types
[op
].bitfield
.disp64
= 0;
7478 i
.flags
[op
] |= Operand_PCrel
;
7479 if (! i
.disp_operands
)
7480 fake_zero_displacement
= 1;
7482 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7484 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7485 switch (i
.base_reg
->reg_num
)
7488 if (i
.index_reg
== 0)
7490 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7491 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7495 if (i
.index_reg
== 0)
7498 if (operand_type_check (i
.types
[op
], disp
) == 0)
7500 /* fake (%bp) into 0(%bp) */
7501 i
.types
[op
].bitfield
.disp8
= 1;
7502 fake_zero_displacement
= 1;
7505 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7506 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7508 default: /* (%si) -> 4 or (%di) -> 5 */
7509 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7511 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7513 else /* i.base_reg and 32/64 bit mode */
7515 if (flag_code
== CODE_64BIT
7516 && operand_type_check (i
.types
[op
], disp
))
7518 i
.types
[op
].bitfield
.disp16
= 0;
7519 i
.types
[op
].bitfield
.disp64
= 0;
7520 if (i
.prefix
[ADDR_PREFIX
] == 0)
7522 i
.types
[op
].bitfield
.disp32
= 0;
7523 i
.types
[op
].bitfield
.disp32s
= 1;
7527 i
.types
[op
].bitfield
.disp32
= 1;
7528 i
.types
[op
].bitfield
.disp32s
= 0;
7532 if (!i
.tm
.opcode_modifier
.vecsib
)
7533 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7534 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7536 i
.sib
.base
= i
.base_reg
->reg_num
;
7537 /* x86-64 ignores REX prefix bit here to avoid decoder
7539 if (!(i
.base_reg
->reg_flags
& RegRex
)
7540 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7541 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7543 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7545 fake_zero_displacement
= 1;
7546 i
.types
[op
].bitfield
.disp8
= 1;
7548 i
.sib
.scale
= i
.log2_scale_factor
;
7549 if (i
.index_reg
== 0)
7551 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7552 /* <disp>(%esp) becomes two byte modrm with no index
7553 register. We've already stored the code for esp
7554 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7555 Any base register besides %esp will not use the
7556 extra modrm byte. */
7557 i
.sib
.index
= NO_INDEX_REGISTER
;
7559 else if (!i
.tm
.opcode_modifier
.vecsib
)
7561 if (i
.index_reg
->reg_num
== RegIZ
)
7562 i
.sib
.index
= NO_INDEX_REGISTER
;
7564 i
.sib
.index
= i
.index_reg
->reg_num
;
7565 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7566 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7571 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7572 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7576 if (!fake_zero_displacement
7580 fake_zero_displacement
= 1;
7581 if (i
.disp_encoding
== disp_encoding_8bit
)
7582 i
.types
[op
].bitfield
.disp8
= 1;
7584 i
.types
[op
].bitfield
.disp32
= 1;
7586 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7590 if (fake_zero_displacement
)
7592 /* Fakes a zero displacement assuming that i.types[op]
7593 holds the correct displacement size. */
7596 gas_assert (i
.op
[op
].disps
== 0);
7597 exp
= &disp_expressions
[i
.disp_operands
++];
7598 i
.op
[op
].disps
= exp
;
7599 exp
->X_op
= O_constant
;
7600 exp
->X_add_number
= 0;
7601 exp
->X_add_symbol
= (symbolS
*) 0;
7602 exp
->X_op_symbol
= (symbolS
*) 0;
7610 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7612 if (operand_type_check (i
.types
[0], imm
))
7613 i
.vex
.register_specifier
= NULL
;
7616 /* VEX.vvvv encodes one of the sources when the first
7617 operand is not an immediate. */
7618 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7619 i
.vex
.register_specifier
= i
.op
[0].regs
;
7621 i
.vex
.register_specifier
= i
.op
[1].regs
;
7624 /* Destination is a XMM register encoded in the ModRM.reg
7626 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7627 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7630 /* ModRM.rm and VEX.B encodes the other source. */
7631 if (!i
.mem_operands
)
7635 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7636 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7638 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7640 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7644 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7646 i
.vex
.register_specifier
= i
.op
[2].regs
;
7647 if (!i
.mem_operands
)
7650 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7651 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7655 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7656 (if any) based on i.tm.extension_opcode. Again, we must be
7657 careful to make sure that segment/control/debug/test/MMX
7658 registers are coded into the i.rm.reg field. */
7659 else if (i
.reg_operands
)
7662 unsigned int vex_reg
= ~0;
7664 for (op
= 0; op
< i
.operands
; op
++)
7666 if (i
.types
[op
].bitfield
.reg
7667 || i
.types
[op
].bitfield
.regbnd
7668 || i
.types
[op
].bitfield
.regmask
7669 || i
.types
[op
].bitfield
.sreg2
7670 || i
.types
[op
].bitfield
.sreg3
7671 || i
.types
[op
].bitfield
.control
7672 || i
.types
[op
].bitfield
.debug
7673 || i
.types
[op
].bitfield
.test
)
7675 if (i
.types
[op
].bitfield
.regsimd
)
7677 if (i
.types
[op
].bitfield
.zmmword
)
7678 i
.has_regzmm
= TRUE
;
7679 else if (i
.types
[op
].bitfield
.ymmword
)
7680 i
.has_regymm
= TRUE
;
7682 i
.has_regxmm
= TRUE
;
7685 if (i
.types
[op
].bitfield
.regmmx
)
7687 i
.has_regmmx
= TRUE
;
7694 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7696 /* For instructions with VexNDS, the register-only
7697 source operand is encoded in VEX prefix. */
7698 gas_assert (mem
!= (unsigned int) ~0);
7703 gas_assert (op
< i
.operands
);
7707 /* Check register-only source operand when two source
7708 operands are swapped. */
7709 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7710 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7714 gas_assert (mem
== (vex_reg
+ 1)
7715 && op
< i
.operands
);
7720 gas_assert (vex_reg
< i
.operands
);
7724 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7726 /* For instructions with VexNDD, the register destination
7727 is encoded in VEX prefix. */
7728 if (i
.mem_operands
== 0)
7730 /* There is no memory operand. */
7731 gas_assert ((op
+ 2) == i
.operands
);
7736 /* There are only 2 non-immediate operands. */
7737 gas_assert (op
< i
.imm_operands
+ 2
7738 && i
.operands
== i
.imm_operands
+ 2);
7739 vex_reg
= i
.imm_operands
+ 1;
7743 gas_assert (op
< i
.operands
);
7745 if (vex_reg
!= (unsigned int) ~0)
7747 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7749 if ((!type
->bitfield
.reg
7750 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7751 && !type
->bitfield
.regsimd
7752 && !operand_type_equal (type
, ®mask
))
7755 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7758 /* Don't set OP operand twice. */
7761 /* If there is an extension opcode to put here, the
7762 register number must be put into the regmem field. */
7763 if (i
.tm
.extension_opcode
!= None
)
7765 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7766 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7768 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7773 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7774 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7776 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7781 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7782 must set it to 3 to indicate this is a register operand
7783 in the regmem field. */
7784 if (!i
.mem_operands
)
7788 /* Fill in i.rm.reg field with extension opcode (if any). */
7789 if (i
.tm
.extension_opcode
!= None
)
7790 i
.rm
.reg
= i
.tm
.extension_opcode
;
7796 output_branch (void)
7802 relax_substateT subtype
;
7806 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7807 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7810 if (i
.prefix
[DATA_PREFIX
] != 0)
7816 /* Pentium4 branch hints. */
7817 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7818 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7823 if (i
.prefix
[REX_PREFIX
] != 0)
7829 /* BND prefixed jump. */
7830 if (i
.prefix
[BND_PREFIX
] != 0)
7832 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7836 if (i
.prefixes
!= 0 && !intel_syntax
)
7837 as_warn (_("skipping prefixes on this instruction"));
7839 /* It's always a symbol; End frag & setup for relax.
7840 Make sure there is enough room in this frag for the largest
7841 instruction we may generate in md_convert_frag. This is 2
7842 bytes for the opcode and room for the prefix and largest
7844 frag_grow (prefix
+ 2 + 4);
7845 /* Prefix and 1 opcode byte go in fr_fix. */
7846 p
= frag_more (prefix
+ 1);
7847 if (i
.prefix
[DATA_PREFIX
] != 0)
7848 *p
++ = DATA_PREFIX_OPCODE
;
7849 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7850 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7851 *p
++ = i
.prefix
[SEG_PREFIX
];
7852 if (i
.prefix
[REX_PREFIX
] != 0)
7853 *p
++ = i
.prefix
[REX_PREFIX
];
7854 *p
= i
.tm
.base_opcode
;
7856 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7857 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7858 else if (cpu_arch_flags
.bitfield
.cpui386
)
7859 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7861 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7864 sym
= i
.op
[0].disps
->X_add_symbol
;
7865 off
= i
.op
[0].disps
->X_add_number
;
7867 if (i
.op
[0].disps
->X_op
!= O_constant
7868 && i
.op
[0].disps
->X_op
!= O_symbol
)
7870 /* Handle complex expressions. */
7871 sym
= make_expr_symbol (i
.op
[0].disps
);
7875 /* 1 possible extra opcode + 4 byte displacement go in var part.
7876 Pass reloc in fr_var. */
7877 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7880 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7881 /* Return TRUE iff PLT32 relocation should be used for branching to
7885 need_plt32_p (symbolS
*s
)
7887 /* PLT32 relocation is ELF only. */
7892 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7893 krtld support it. */
7897 /* Since there is no need to prepare for PLT branch on x86-64, we
7898 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7899 be used as a marker for 32-bit PC-relative branches. */
7903 /* Weak or undefined symbol need PLT32 relocation. */
7904 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7907 /* Non-global symbol doesn't need PLT32 relocation. */
7908 if (! S_IS_EXTERNAL (s
))
7911 /* Other global symbols need PLT32 relocation. NB: Symbol with
7912 non-default visibilities are treated as normal global symbol
7913 so that PLT32 relocation can be used as a marker for 32-bit
7914 PC-relative branches. It is useful for linker relaxation. */
7925 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7927 if (i
.tm
.opcode_modifier
.jumpbyte
)
7929 /* This is a loop or jecxz type instruction. */
7931 if (i
.prefix
[ADDR_PREFIX
] != 0)
7933 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7936 /* Pentium4 branch hints. */
7937 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7938 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7940 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7949 if (flag_code
== CODE_16BIT
)
7952 if (i
.prefix
[DATA_PREFIX
] != 0)
7954 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7964 if (i
.prefix
[REX_PREFIX
] != 0)
7966 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7970 /* BND prefixed jump. */
7971 if (i
.prefix
[BND_PREFIX
] != 0)
7973 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7977 if (i
.prefixes
!= 0 && !intel_syntax
)
7978 as_warn (_("skipping prefixes on this instruction"));
7980 p
= frag_more (i
.tm
.opcode_length
+ size
);
7981 switch (i
.tm
.opcode_length
)
7984 *p
++ = i
.tm
.base_opcode
>> 8;
7987 *p
++ = i
.tm
.base_opcode
;
7993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7995 && jump_reloc
== NO_RELOC
7996 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7997 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8000 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8002 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8003 i
.op
[0].disps
, 1, jump_reloc
);
8005 /* All jumps handled here are signed, but don't use a signed limit
8006 check for 32 and 16 bit jumps as we want to allow wrap around at
8007 4G and 64k respectively. */
8009 fixP
->fx_signed
= 1;
8013 output_interseg_jump (void)
8021 if (flag_code
== CODE_16BIT
)
8025 if (i
.prefix
[DATA_PREFIX
] != 0)
8031 if (i
.prefix
[REX_PREFIX
] != 0)
8041 if (i
.prefixes
!= 0 && !intel_syntax
)
8042 as_warn (_("skipping prefixes on this instruction"));
8044 /* 1 opcode; 2 segment; offset */
8045 p
= frag_more (prefix
+ 1 + 2 + size
);
8047 if (i
.prefix
[DATA_PREFIX
] != 0)
8048 *p
++ = DATA_PREFIX_OPCODE
;
8050 if (i
.prefix
[REX_PREFIX
] != 0)
8051 *p
++ = i
.prefix
[REX_PREFIX
];
8053 *p
++ = i
.tm
.base_opcode
;
8054 if (i
.op
[1].imms
->X_op
== O_constant
)
8056 offsetT n
= i
.op
[1].imms
->X_add_number
;
8059 && !fits_in_unsigned_word (n
)
8060 && !fits_in_signed_word (n
))
8062 as_bad (_("16-bit jump out of range"));
8065 md_number_to_chars (p
, n
, size
);
8068 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8069 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8070 if (i
.op
[0].imms
->X_op
!= O_constant
)
8071 as_bad (_("can't handle non absolute segment in `%s'"),
8073 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8081 asection
*seg
= now_seg
;
8082 subsegT subseg
= now_subseg
;
8084 unsigned int alignment
, align_size_1
;
8085 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8086 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8087 unsigned int padding
;
8089 if (!IS_ELF
|| !x86_used_note
)
8092 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8094 /* The .note.gnu.property section layout:
8096 Field Length Contents
8099 n_descsz 4 The note descriptor size
8100 n_type 4 NT_GNU_PROPERTY_TYPE_0
8102 n_desc n_descsz The program property array
8106 /* Create the .note.gnu.property section. */
8107 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8108 bfd_set_section_flags (stdoutput
, sec
,
8115 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8126 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8127 elf_section_type (sec
) = SHT_NOTE
;
8129 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8131 isa_1_descsz_raw
= 4 + 4 + 4;
8132 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8133 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8135 feature_2_descsz_raw
= isa_1_descsz
;
8136 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8138 feature_2_descsz_raw
+= 4 + 4 + 4;
8139 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8140 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8143 descsz
= feature_2_descsz
;
8144 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8145 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8147 /* Write n_namsz. */
8148 md_number_to_chars (p
, (valueT
) 4, 4);
8150 /* Write n_descsz. */
8151 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8154 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8157 memcpy (p
+ 4 * 3, "GNU", 4);
8159 /* Write 4-byte type. */
8160 md_number_to_chars (p
+ 4 * 4,
8161 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8163 /* Write 4-byte data size. */
8164 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8166 /* Write 4-byte data. */
8167 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8169 /* Zero out paddings. */
8170 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8172 memset (p
+ 4 * 7, 0, padding
);
8174 /* Write 4-byte type. */
8175 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8176 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8178 /* Write 4-byte data size. */
8179 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8181 /* Write 4-byte data. */
8182 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8183 (valueT
) x86_feature_2_used
, 4);
8185 /* Zero out paddings. */
8186 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8188 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8190 /* We probably can't restore the current segment, for there likely
8193 subseg_set (seg
, subseg
);
8198 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8199 const char *frag_now_ptr
)
8201 unsigned int len
= 0;
8203 if (start_frag
!= frag_now
)
8205 const fragS
*fr
= start_frag
;
8210 } while (fr
&& fr
!= frag_now
);
8213 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8219 fragS
*insn_start_frag
;
8220 offsetT insn_start_off
;
8222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8223 if (IS_ELF
&& x86_used_note
)
8225 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8226 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8227 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8228 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8229 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8230 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8231 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8232 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8233 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8234 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8235 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8237 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8238 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8239 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8242 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8243 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8244 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8245 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8247 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8248 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8249 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8250 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8251 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8252 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8253 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8254 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8255 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8256 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8257 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8258 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8259 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8260 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8261 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8262 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8263 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8264 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8265 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8266 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8267 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8268 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8269 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8270 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8271 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8272 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8273 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8274 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8276 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8277 || i
.tm
.cpu_flags
.bitfield
.cpu287
8278 || i
.tm
.cpu_flags
.bitfield
.cpu387
8279 || i
.tm
.cpu_flags
.bitfield
.cpu687
8280 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8281 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8282 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8283 Xfence instructions. */
8284 if (i
.tm
.base_opcode
!= 0xf18
8285 && i
.tm
.base_opcode
!= 0xf0d
8286 && i
.tm
.base_opcode
!= 0xfae
8288 || i
.tm
.cpu_flags
.bitfield
.cpummx
8289 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8290 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8291 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8293 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8295 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8297 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8298 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8299 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8300 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8301 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8302 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8303 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8304 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8305 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8309 /* Tie dwarf2 debug info to the address at the start of the insn.
8310 We can't do this after the insn has been output as the current
8311 frag may have been closed off. eg. by frag_var. */
8312 dwarf2_emit_insn (0);
8314 insn_start_frag
= frag_now
;
8315 insn_start_off
= frag_now_fix ();
8318 if (i
.tm
.opcode_modifier
.jump
)
8320 else if (i
.tm
.opcode_modifier
.jumpbyte
8321 || i
.tm
.opcode_modifier
.jumpdword
)
8323 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8324 output_interseg_jump ();
8327 /* Output normal instructions here. */
8331 unsigned int prefix
;
8334 && i
.tm
.base_opcode
== 0xfae
8336 && i
.imm_operands
== 1
8337 && (i
.op
[0].imms
->X_add_number
== 0xe8
8338 || i
.op
[0].imms
->X_add_number
== 0xf0
8339 || i
.op
[0].imms
->X_add_number
== 0xf8))
8341 /* Encode lfence, mfence, and sfence as
8342 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8343 offsetT val
= 0x240483f0ULL
;
8345 md_number_to_chars (p
, val
, 5);
8349 /* Some processors fail on LOCK prefix. This options makes
8350 assembler ignore LOCK prefix and serves as a workaround. */
8351 if (omit_lock_prefix
)
8353 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8355 i
.prefix
[LOCK_PREFIX
] = 0;
8358 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8359 don't need the explicit prefix. */
8360 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8362 switch (i
.tm
.opcode_length
)
8365 if (i
.tm
.base_opcode
& 0xff000000)
8367 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8368 add_prefix (prefix
);
8372 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8374 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8375 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8376 || prefix
!= REPE_PREFIX_OPCODE
8377 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8378 add_prefix (prefix
);
8384 /* Check for pseudo prefixes. */
8385 as_bad_where (insn_start_frag
->fr_file
,
8386 insn_start_frag
->fr_line
,
8387 _("pseudo prefix without instruction"));
8393 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8394 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8395 R_X86_64_GOTTPOFF relocation so that linker can safely
8396 perform IE->LE optimization. */
8397 if (x86_elf_abi
== X86_64_X32_ABI
8399 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8400 && i
.prefix
[REX_PREFIX
] == 0)
8401 add_prefix (REX_OPCODE
);
8404 /* The prefix bytes. */
8405 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8407 FRAG_APPEND_1_CHAR (*q
);
8411 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8416 /* REX byte is encoded in VEX prefix. */
8420 FRAG_APPEND_1_CHAR (*q
);
8423 /* There should be no other prefixes for instructions
8428 /* For EVEX instructions i.vrex should become 0 after
8429 build_evex_prefix. For VEX instructions upper 16 registers
8430 aren't available, so VREX should be 0. */
8433 /* Now the VEX prefix. */
8434 p
= frag_more (i
.vex
.length
);
8435 for (j
= 0; j
< i
.vex
.length
; j
++)
8436 p
[j
] = i
.vex
.bytes
[j
];
8439 /* Now the opcode; be careful about word order here! */
8440 if (i
.tm
.opcode_length
== 1)
8442 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8446 switch (i
.tm
.opcode_length
)
8450 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8451 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8455 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8465 /* Put out high byte first: can't use md_number_to_chars! */
8466 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8467 *p
= i
.tm
.base_opcode
& 0xff;
8470 /* Now the modrm byte and sib byte (if present). */
8471 if (i
.tm
.opcode_modifier
.modrm
)
8473 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8476 /* If i.rm.regmem == ESP (4)
8477 && i.rm.mode != (Register mode)
8479 ==> need second modrm byte. */
8480 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8482 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8483 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8485 | i
.sib
.scale
<< 6));
8488 if (i
.disp_operands
)
8489 output_disp (insn_start_frag
, insn_start_off
);
8492 output_imm (insn_start_frag
, insn_start_off
);
8495 * frag_now_fix () returning plain abs_section_offset when we're in the
8496 * absolute section, and abs_section_offset not getting updated as data
8497 * gets added to the frag breaks the logic below.
8499 if (now_seg
!= absolute_section
)
8501 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8503 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8511 pi ("" /*line*/, &i
);
8513 #endif /* DEBUG386 */
8516 /* Return the size of the displacement operand N. */
8519 disp_size (unsigned int n
)
8523 if (i
.types
[n
].bitfield
.disp64
)
8525 else if (i
.types
[n
].bitfield
.disp8
)
8527 else if (i
.types
[n
].bitfield
.disp16
)
8532 /* Return the size of the immediate operand N. */
8535 imm_size (unsigned int n
)
8538 if (i
.types
[n
].bitfield
.imm64
)
8540 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8542 else if (i
.types
[n
].bitfield
.imm16
)
8548 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8553 for (n
= 0; n
< i
.operands
; n
++)
8555 if (operand_type_check (i
.types
[n
], disp
))
8557 if (i
.op
[n
].disps
->X_op
== O_constant
)
8559 int size
= disp_size (n
);
8560 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8562 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8564 p
= frag_more (size
);
8565 md_number_to_chars (p
, val
, size
);
8569 enum bfd_reloc_code_real reloc_type
;
8570 int size
= disp_size (n
);
8571 int sign
= i
.types
[n
].bitfield
.disp32s
;
8572 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8575 /* We can't have 8 bit displacement here. */
8576 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8578 /* The PC relative address is computed relative
8579 to the instruction boundary, so in case immediate
8580 fields follows, we need to adjust the value. */
8581 if (pcrel
&& i
.imm_operands
)
8586 for (n1
= 0; n1
< i
.operands
; n1
++)
8587 if (operand_type_check (i
.types
[n1
], imm
))
8589 /* Only one immediate is allowed for PC
8590 relative address. */
8591 gas_assert (sz
== 0);
8593 i
.op
[n
].disps
->X_add_number
-= sz
;
8595 /* We should find the immediate. */
8596 gas_assert (sz
!= 0);
8599 p
= frag_more (size
);
8600 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8602 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8603 && (((reloc_type
== BFD_RELOC_32
8604 || reloc_type
== BFD_RELOC_X86_64_32S
8605 || (reloc_type
== BFD_RELOC_64
8607 && (i
.op
[n
].disps
->X_op
== O_symbol
8608 || (i
.op
[n
].disps
->X_op
== O_add
8609 && ((symbol_get_value_expression
8610 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8612 || reloc_type
== BFD_RELOC_32_PCREL
))
8616 reloc_type
= BFD_RELOC_386_GOTPC
;
8617 i
.op
[n
].imms
->X_add_number
+=
8618 encoding_length (insn_start_frag
, insn_start_off
, p
);
8620 else if (reloc_type
== BFD_RELOC_64
)
8621 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8623 /* Don't do the adjustment for x86-64, as there
8624 the pcrel addressing is relative to the _next_
8625 insn, and that is taken care of in other code. */
8626 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8628 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8629 size
, i
.op
[n
].disps
, pcrel
,
8631 /* Check for "call/jmp *mem", "mov mem, %reg",
8632 "test %reg, mem" and "binop mem, %reg" where binop
8633 is one of adc, add, and, cmp, or, sbb, sub, xor
8634 instructions without data prefix. Always generate
8635 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8636 if (i
.prefix
[DATA_PREFIX
] == 0
8637 && (generate_relax_relocations
8640 && i
.rm
.regmem
== 5))
8642 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8643 && ((i
.operands
== 1
8644 && i
.tm
.base_opcode
== 0xff
8645 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8647 && (i
.tm
.base_opcode
== 0x8b
8648 || i
.tm
.base_opcode
== 0x85
8649 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8653 fixP
->fx_tcbit
= i
.rex
!= 0;
8655 && (i
.base_reg
->reg_num
== RegIP
))
8656 fixP
->fx_tcbit2
= 1;
8659 fixP
->fx_tcbit2
= 1;
8667 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8672 for (n
= 0; n
< i
.operands
; n
++)
8674 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8675 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8678 if (operand_type_check (i
.types
[n
], imm
))
8680 if (i
.op
[n
].imms
->X_op
== O_constant
)
8682 int size
= imm_size (n
);
8685 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8687 p
= frag_more (size
);
8688 md_number_to_chars (p
, val
, size
);
8692 /* Not absolute_section.
8693 Need a 32-bit fixup (don't support 8bit
8694 non-absolute imms). Try to support other
8696 enum bfd_reloc_code_real reloc_type
;
8697 int size
= imm_size (n
);
8700 if (i
.types
[n
].bitfield
.imm32s
8701 && (i
.suffix
== QWORD_MNEM_SUFFIX
8702 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8707 p
= frag_more (size
);
8708 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8710 /* This is tough to explain. We end up with this one if we
8711 * have operands that look like
8712 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8713 * obtain the absolute address of the GOT, and it is strongly
8714 * preferable from a performance point of view to avoid using
8715 * a runtime relocation for this. The actual sequence of
8716 * instructions often look something like:
8721 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8723 * The call and pop essentially return the absolute address
8724 * of the label .L66 and store it in %ebx. The linker itself
8725 * will ultimately change the first operand of the addl so
8726 * that %ebx points to the GOT, but to keep things simple, the
8727 * .o file must have this operand set so that it generates not
8728 * the absolute address of .L66, but the absolute address of
8729 * itself. This allows the linker itself simply treat a GOTPC
8730 * relocation as asking for a pcrel offset to the GOT to be
8731 * added in, and the addend of the relocation is stored in the
8732 * operand field for the instruction itself.
8734 * Our job here is to fix the operand so that it would add
8735 * the correct offset so that %ebx would point to itself. The
8736 * thing that is tricky is that .-.L66 will point to the
8737 * beginning of the instruction, so we need to further modify
8738 * the operand so that it will point to itself. There are
8739 * other cases where you have something like:
8741 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8743 * and here no correction would be required. Internally in
8744 * the assembler we treat operands of this form as not being
8745 * pcrel since the '.' is explicitly mentioned, and I wonder
8746 * whether it would simplify matters to do it this way. Who
8747 * knows. In earlier versions of the PIC patches, the
8748 * pcrel_adjust field was used to store the correction, but
8749 * since the expression is not pcrel, I felt it would be
8750 * confusing to do it this way. */
8752 if ((reloc_type
== BFD_RELOC_32
8753 || reloc_type
== BFD_RELOC_X86_64_32S
8754 || reloc_type
== BFD_RELOC_64
)
8756 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8757 && (i
.op
[n
].imms
->X_op
== O_symbol
8758 || (i
.op
[n
].imms
->X_op
== O_add
8759 && ((symbol_get_value_expression
8760 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8764 reloc_type
= BFD_RELOC_386_GOTPC
;
8766 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8768 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8769 i
.op
[n
].imms
->X_add_number
+=
8770 encoding_length (insn_start_frag
, insn_start_off
, p
);
8772 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8773 i
.op
[n
].imms
, 0, reloc_type
);
8779 /* x86_cons_fix_new is called via the expression parsing code when a
8780 reloc is needed. We use this hook to get the correct .got reloc. */
8781 static int cons_sign
= -1;
8784 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8785 expressionS
*exp
, bfd_reloc_code_real_type r
)
8787 r
= reloc (len
, 0, cons_sign
, r
);
8790 if (exp
->X_op
== O_secrel
)
8792 exp
->X_op
= O_symbol
;
8793 r
= BFD_RELOC_32_SECREL
;
8797 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8800 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8801 purpose of the `.dc.a' internal pseudo-op. */
8804 x86_address_bytes (void)
8806 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8808 return stdoutput
->arch_info
->bits_per_address
/ 8;
8811 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8813 # define lex_got(reloc, adjust, types) NULL
8815 /* Parse operands of the form
8816 <symbol>@GOTOFF+<nnn>
8817 and similar .plt or .got references.
8819 If we find one, set up the correct relocation in RELOC and copy the
8820 input string, minus the `@GOTOFF' into a malloc'd buffer for
8821 parsing by the calling routine. Return this buffer, and if ADJUST
8822 is non-null set it to the length of the string we removed from the
8823 input line. Otherwise return NULL. */
8825 lex_got (enum bfd_reloc_code_real
*rel
,
8827 i386_operand_type
*types
)
8829 /* Some of the relocations depend on the size of what field is to
8830 be relocated. But in our callers i386_immediate and i386_displacement
8831 we don't yet know the operand size (this will be set by insn
8832 matching). Hence we record the word32 relocation here,
8833 and adjust the reloc according to the real size in reloc(). */
8834 static const struct {
8837 const enum bfd_reloc_code_real rel
[2];
8838 const i386_operand_type types64
;
8840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8841 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8843 OPERAND_TYPE_IMM32_64
},
8845 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8846 BFD_RELOC_X86_64_PLTOFF64
},
8847 OPERAND_TYPE_IMM64
},
8848 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8849 BFD_RELOC_X86_64_PLT32
},
8850 OPERAND_TYPE_IMM32_32S_DISP32
},
8851 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8852 BFD_RELOC_X86_64_GOTPLT64
},
8853 OPERAND_TYPE_IMM64_DISP64
},
8854 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8855 BFD_RELOC_X86_64_GOTOFF64
},
8856 OPERAND_TYPE_IMM64_DISP64
},
8857 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8858 BFD_RELOC_X86_64_GOTPCREL
},
8859 OPERAND_TYPE_IMM32_32S_DISP32
},
8860 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8861 BFD_RELOC_X86_64_TLSGD
},
8862 OPERAND_TYPE_IMM32_32S_DISP32
},
8863 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8864 _dummy_first_bfd_reloc_code_real
},
8865 OPERAND_TYPE_NONE
},
8866 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8867 BFD_RELOC_X86_64_TLSLD
},
8868 OPERAND_TYPE_IMM32_32S_DISP32
},
8869 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8870 BFD_RELOC_X86_64_GOTTPOFF
},
8871 OPERAND_TYPE_IMM32_32S_DISP32
},
8872 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8873 BFD_RELOC_X86_64_TPOFF32
},
8874 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8875 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8876 _dummy_first_bfd_reloc_code_real
},
8877 OPERAND_TYPE_NONE
},
8878 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8879 BFD_RELOC_X86_64_DTPOFF32
},
8880 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8881 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8882 _dummy_first_bfd_reloc_code_real
},
8883 OPERAND_TYPE_NONE
},
8884 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8885 _dummy_first_bfd_reloc_code_real
},
8886 OPERAND_TYPE_NONE
},
8887 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8888 BFD_RELOC_X86_64_GOT32
},
8889 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8890 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8891 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8892 OPERAND_TYPE_IMM32_32S_DISP32
},
8893 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8894 BFD_RELOC_X86_64_TLSDESC_CALL
},
8895 OPERAND_TYPE_IMM32_32S_DISP32
},
8900 #if defined (OBJ_MAYBE_ELF)
8905 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8906 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8909 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8911 int len
= gotrel
[j
].len
;
8912 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8914 if (gotrel
[j
].rel
[object_64bit
] != 0)
8917 char *tmpbuf
, *past_reloc
;
8919 *rel
= gotrel
[j
].rel
[object_64bit
];
8923 if (flag_code
!= CODE_64BIT
)
8925 types
->bitfield
.imm32
= 1;
8926 types
->bitfield
.disp32
= 1;
8929 *types
= gotrel
[j
].types64
;
8932 if (j
!= 0 && GOT_symbol
== NULL
)
8933 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8935 /* The length of the first part of our input line. */
8936 first
= cp
- input_line_pointer
;
8938 /* The second part goes from after the reloc token until
8939 (and including) an end_of_line char or comma. */
8940 past_reloc
= cp
+ 1 + len
;
8942 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8944 second
= cp
+ 1 - past_reloc
;
8946 /* Allocate and copy string. The trailing NUL shouldn't
8947 be necessary, but be safe. */
8948 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8949 memcpy (tmpbuf
, input_line_pointer
, first
);
8950 if (second
!= 0 && *past_reloc
!= ' ')
8951 /* Replace the relocation token with ' ', so that
8952 errors like foo@GOTOFF1 will be detected. */
8953 tmpbuf
[first
++] = ' ';
8955 /* Increment length by 1 if the relocation token is
8960 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8961 tmpbuf
[first
+ second
] = '\0';
8965 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8966 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8971 /* Might be a symbol version string. Don't as_bad here. */
8980 /* Parse operands of the form
8981 <symbol>@SECREL32+<nnn>
8983 If we find one, set up the correct relocation in RELOC and copy the
8984 input string, minus the `@SECREL32' into a malloc'd buffer for
8985 parsing by the calling routine. Return this buffer, and if ADJUST
8986 is non-null set it to the length of the string we removed from the
8987 input line. Otherwise return NULL.
8989 This function is copied from the ELF version above adjusted for PE targets. */
8992 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8993 int *adjust ATTRIBUTE_UNUSED
,
8994 i386_operand_type
*types
)
9000 const enum bfd_reloc_code_real rel
[2];
9001 const i386_operand_type types64
;
9005 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9006 BFD_RELOC_32_SECREL
},
9007 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9013 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9014 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9017 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9019 int len
= gotrel
[j
].len
;
9021 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9023 if (gotrel
[j
].rel
[object_64bit
] != 0)
9026 char *tmpbuf
, *past_reloc
;
9028 *rel
= gotrel
[j
].rel
[object_64bit
];
9034 if (flag_code
!= CODE_64BIT
)
9036 types
->bitfield
.imm32
= 1;
9037 types
->bitfield
.disp32
= 1;
9040 *types
= gotrel
[j
].types64
;
9043 /* The length of the first part of our input line. */
9044 first
= cp
- input_line_pointer
;
9046 /* The second part goes from after the reloc token until
9047 (and including) an end_of_line char or comma. */
9048 past_reloc
= cp
+ 1 + len
;
9050 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9052 second
= cp
+ 1 - past_reloc
;
9054 /* Allocate and copy string. The trailing NUL shouldn't
9055 be necessary, but be safe. */
9056 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9057 memcpy (tmpbuf
, input_line_pointer
, first
);
9058 if (second
!= 0 && *past_reloc
!= ' ')
9059 /* Replace the relocation token with ' ', so that
9060 errors like foo@SECLREL321 will be detected. */
9061 tmpbuf
[first
++] = ' ';
9062 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9063 tmpbuf
[first
+ second
] = '\0';
9067 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9068 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9073 /* Might be a symbol version string. Don't as_bad here. */
9079 bfd_reloc_code_real_type
9080 x86_cons (expressionS
*exp
, int size
)
9082 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9084 intel_syntax
= -intel_syntax
;
9087 if (size
== 4 || (object_64bit
&& size
== 8))
9089 /* Handle @GOTOFF and the like in an expression. */
9091 char *gotfree_input_line
;
9094 save
= input_line_pointer
;
9095 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9096 if (gotfree_input_line
)
9097 input_line_pointer
= gotfree_input_line
;
9101 if (gotfree_input_line
)
9103 /* expression () has merrily parsed up to the end of line,
9104 or a comma - in the wrong buffer. Transfer how far
9105 input_line_pointer has moved to the right buffer. */
9106 input_line_pointer
= (save
9107 + (input_line_pointer
- gotfree_input_line
)
9109 free (gotfree_input_line
);
9110 if (exp
->X_op
== O_constant
9111 || exp
->X_op
== O_absent
9112 || exp
->X_op
== O_illegal
9113 || exp
->X_op
== O_register
9114 || exp
->X_op
== O_big
)
9116 char c
= *input_line_pointer
;
9117 *input_line_pointer
= 0;
9118 as_bad (_("missing or invalid expression `%s'"), save
);
9119 *input_line_pointer
= c
;
9121 else if ((got_reloc
== BFD_RELOC_386_PLT32
9122 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9123 && exp
->X_op
!= O_symbol
)
9125 char c
= *input_line_pointer
;
9126 *input_line_pointer
= 0;
9127 as_bad (_("invalid PLT expression `%s'"), save
);
9128 *input_line_pointer
= c
;
9135 intel_syntax
= -intel_syntax
;
9138 i386_intel_simplify (exp
);
9144 signed_cons (int size
)
9146 if (flag_code
== CODE_64BIT
)
9154 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9161 if (exp
.X_op
== O_symbol
)
9162 exp
.X_op
= O_secrel
;
9164 emit_expr (&exp
, 4);
9166 while (*input_line_pointer
++ == ',');
9168 input_line_pointer
--;
9169 demand_empty_rest_of_line ();
9173 /* Handle Vector operations. */
9176 check_VecOperations (char *op_string
, char *op_end
)
9178 const reg_entry
*mask
;
9183 && (op_end
== NULL
|| op_string
< op_end
))
9186 if (*op_string
== '{')
9190 /* Check broadcasts. */
9191 if (strncmp (op_string
, "1to", 3) == 0)
9196 goto duplicated_vec_op
;
9199 if (*op_string
== '8')
9201 else if (*op_string
== '4')
9203 else if (*op_string
== '2')
9205 else if (*op_string
== '1'
9206 && *(op_string
+1) == '6')
9213 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9218 broadcast_op
.type
= bcst_type
;
9219 broadcast_op
.operand
= this_operand
;
9220 broadcast_op
.bytes
= 0;
9221 i
.broadcast
= &broadcast_op
;
9223 /* Check masking operation. */
9224 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9226 /* k0 can't be used for write mask. */
9227 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9229 as_bad (_("`%s%s' can't be used for write mask"),
9230 register_prefix
, mask
->reg_name
);
9236 mask_op
.mask
= mask
;
9237 mask_op
.zeroing
= 0;
9238 mask_op
.operand
= this_operand
;
9244 goto duplicated_vec_op
;
9246 i
.mask
->mask
= mask
;
9248 /* Only "{z}" is allowed here. No need to check
9249 zeroing mask explicitly. */
9250 if (i
.mask
->operand
!= this_operand
)
9252 as_bad (_("invalid write mask `%s'"), saved
);
9259 /* Check zeroing-flag for masking operation. */
9260 else if (*op_string
== 'z')
9264 mask_op
.mask
= NULL
;
9265 mask_op
.zeroing
= 1;
9266 mask_op
.operand
= this_operand
;
9271 if (i
.mask
->zeroing
)
9274 as_bad (_("duplicated `%s'"), saved
);
9278 i
.mask
->zeroing
= 1;
9280 /* Only "{%k}" is allowed here. No need to check mask
9281 register explicitly. */
9282 if (i
.mask
->operand
!= this_operand
)
9284 as_bad (_("invalid zeroing-masking `%s'"),
9293 goto unknown_vec_op
;
9295 if (*op_string
!= '}')
9297 as_bad (_("missing `}' in `%s'"), saved
);
9302 /* Strip whitespace since the addition of pseudo prefixes
9303 changed how the scrubber treats '{'. */
9304 if (is_space_char (*op_string
))
9310 /* We don't know this one. */
9311 as_bad (_("unknown vector operation: `%s'"), saved
);
9315 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9317 as_bad (_("zeroing-masking only allowed with write mask"));
9325 i386_immediate (char *imm_start
)
9327 char *save_input_line_pointer
;
9328 char *gotfree_input_line
;
9331 i386_operand_type types
;
9333 operand_type_set (&types
, ~0);
9335 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9337 as_bad (_("at most %d immediate operands are allowed"),
9338 MAX_IMMEDIATE_OPERANDS
);
9342 exp
= &im_expressions
[i
.imm_operands
++];
9343 i
.op
[this_operand
].imms
= exp
;
9345 if (is_space_char (*imm_start
))
9348 save_input_line_pointer
= input_line_pointer
;
9349 input_line_pointer
= imm_start
;
9351 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9352 if (gotfree_input_line
)
9353 input_line_pointer
= gotfree_input_line
;
9355 exp_seg
= expression (exp
);
9359 /* Handle vector operations. */
9360 if (*input_line_pointer
== '{')
9362 input_line_pointer
= check_VecOperations (input_line_pointer
,
9364 if (input_line_pointer
== NULL
)
9368 if (*input_line_pointer
)
9369 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9371 input_line_pointer
= save_input_line_pointer
;
9372 if (gotfree_input_line
)
9374 free (gotfree_input_line
);
9376 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9377 exp
->X_op
= O_illegal
;
9380 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9384 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9385 i386_operand_type types
, const char *imm_start
)
9387 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9390 as_bad (_("missing or invalid immediate expression `%s'"),
9394 else if (exp
->X_op
== O_constant
)
9396 /* Size it properly later. */
9397 i
.types
[this_operand
].bitfield
.imm64
= 1;
9398 /* If not 64bit, sign extend val. */
9399 if (flag_code
!= CODE_64BIT
9400 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9402 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9404 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9405 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9406 && exp_seg
!= absolute_section
9407 && exp_seg
!= text_section
9408 && exp_seg
!= data_section
9409 && exp_seg
!= bss_section
9410 && exp_seg
!= undefined_section
9411 && !bfd_is_com_section (exp_seg
))
9413 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9417 else if (!intel_syntax
&& exp_seg
== reg_section
)
9420 as_bad (_("illegal immediate register operand %s"), imm_start
);
9425 /* This is an address. The size of the address will be
9426 determined later, depending on destination register,
9427 suffix, or the default for the section. */
9428 i
.types
[this_operand
].bitfield
.imm8
= 1;
9429 i
.types
[this_operand
].bitfield
.imm16
= 1;
9430 i
.types
[this_operand
].bitfield
.imm32
= 1;
9431 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9432 i
.types
[this_operand
].bitfield
.imm64
= 1;
9433 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9441 i386_scale (char *scale
)
9444 char *save
= input_line_pointer
;
9446 input_line_pointer
= scale
;
9447 val
= get_absolute_expression ();
9452 i
.log2_scale_factor
= 0;
9455 i
.log2_scale_factor
= 1;
9458 i
.log2_scale_factor
= 2;
9461 i
.log2_scale_factor
= 3;
9465 char sep
= *input_line_pointer
;
9467 *input_line_pointer
= '\0';
9468 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9470 *input_line_pointer
= sep
;
9471 input_line_pointer
= save
;
9475 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9477 as_warn (_("scale factor of %d without an index register"),
9478 1 << i
.log2_scale_factor
);
9479 i
.log2_scale_factor
= 0;
9481 scale
= input_line_pointer
;
9482 input_line_pointer
= save
;
9487 i386_displacement (char *disp_start
, char *disp_end
)
9491 char *save_input_line_pointer
;
9492 char *gotfree_input_line
;
9494 i386_operand_type bigdisp
, types
= anydisp
;
9497 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9499 as_bad (_("at most %d displacement operands are allowed"),
9500 MAX_MEMORY_OPERANDS
);
9504 operand_type_set (&bigdisp
, 0);
9505 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9506 || (!current_templates
->start
->opcode_modifier
.jump
9507 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9509 bigdisp
.bitfield
.disp32
= 1;
9510 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9511 if (flag_code
== CODE_64BIT
)
9515 bigdisp
.bitfield
.disp32s
= 1;
9516 bigdisp
.bitfield
.disp64
= 1;
9519 else if ((flag_code
== CODE_16BIT
) ^ override
)
9521 bigdisp
.bitfield
.disp32
= 0;
9522 bigdisp
.bitfield
.disp16
= 1;
9527 /* For PC-relative branches, the width of the displacement
9528 is dependent upon data size, not address size. */
9529 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9530 if (flag_code
== CODE_64BIT
)
9532 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9533 bigdisp
.bitfield
.disp16
= 1;
9536 bigdisp
.bitfield
.disp32
= 1;
9537 bigdisp
.bitfield
.disp32s
= 1;
9543 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9545 : LONG_MNEM_SUFFIX
));
9546 bigdisp
.bitfield
.disp32
= 1;
9547 if ((flag_code
== CODE_16BIT
) ^ override
)
9549 bigdisp
.bitfield
.disp32
= 0;
9550 bigdisp
.bitfield
.disp16
= 1;
9554 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9557 exp
= &disp_expressions
[i
.disp_operands
];
9558 i
.op
[this_operand
].disps
= exp
;
9560 save_input_line_pointer
= input_line_pointer
;
9561 input_line_pointer
= disp_start
;
9562 END_STRING_AND_SAVE (disp_end
);
9564 #ifndef GCC_ASM_O_HACK
9565 #define GCC_ASM_O_HACK 0
9568 END_STRING_AND_SAVE (disp_end
+ 1);
9569 if (i
.types
[this_operand
].bitfield
.baseIndex
9570 && displacement_string_end
[-1] == '+')
9572 /* This hack is to avoid a warning when using the "o"
9573 constraint within gcc asm statements.
9576 #define _set_tssldt_desc(n,addr,limit,type) \
9577 __asm__ __volatile__ ( \
9579 "movw %w1,2+%0\n\t" \
9581 "movb %b1,4+%0\n\t" \
9582 "movb %4,5+%0\n\t" \
9583 "movb $0,6+%0\n\t" \
9584 "movb %h1,7+%0\n\t" \
9586 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9588 This works great except that the output assembler ends
9589 up looking a bit weird if it turns out that there is
9590 no offset. You end up producing code that looks like:
9603 So here we provide the missing zero. */
9605 *displacement_string_end
= '0';
9608 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9609 if (gotfree_input_line
)
9610 input_line_pointer
= gotfree_input_line
;
9612 exp_seg
= expression (exp
);
9615 if (*input_line_pointer
)
9616 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9618 RESTORE_END_STRING (disp_end
+ 1);
9620 input_line_pointer
= save_input_line_pointer
;
9621 if (gotfree_input_line
)
9623 free (gotfree_input_line
);
9625 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9626 exp
->X_op
= O_illegal
;
9629 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9631 RESTORE_END_STRING (disp_end
);
9637 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9638 i386_operand_type types
, const char *disp_start
)
9640 i386_operand_type bigdisp
;
9643 /* We do this to make sure that the section symbol is in
9644 the symbol table. We will ultimately change the relocation
9645 to be relative to the beginning of the section. */
9646 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9647 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9648 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9650 if (exp
->X_op
!= O_symbol
)
9653 if (S_IS_LOCAL (exp
->X_add_symbol
)
9654 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9655 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9656 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9657 exp
->X_op
= O_subtract
;
9658 exp
->X_op_symbol
= GOT_symbol
;
9659 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9660 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9661 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9662 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9664 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9667 else if (exp
->X_op
== O_absent
9668 || exp
->X_op
== O_illegal
9669 || exp
->X_op
== O_big
)
9672 as_bad (_("missing or invalid displacement expression `%s'"),
9677 else if (flag_code
== CODE_64BIT
9678 && !i
.prefix
[ADDR_PREFIX
]
9679 && exp
->X_op
== O_constant
)
9681 /* Since displacement is signed extended to 64bit, don't allow
9682 disp32 and turn off disp32s if they are out of range. */
9683 i
.types
[this_operand
].bitfield
.disp32
= 0;
9684 if (!fits_in_signed_long (exp
->X_add_number
))
9686 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9687 if (i
.types
[this_operand
].bitfield
.baseindex
)
9689 as_bad (_("0x%lx out range of signed 32bit displacement"),
9690 (long) exp
->X_add_number
);
9696 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9697 else if (exp
->X_op
!= O_constant
9698 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9699 && exp_seg
!= absolute_section
9700 && exp_seg
!= text_section
9701 && exp_seg
!= data_section
9702 && exp_seg
!= bss_section
9703 && exp_seg
!= undefined_section
9704 && !bfd_is_com_section (exp_seg
))
9706 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9711 /* Check if this is a displacement only operand. */
9712 bigdisp
= i
.types
[this_operand
];
9713 bigdisp
.bitfield
.disp8
= 0;
9714 bigdisp
.bitfield
.disp16
= 0;
9715 bigdisp
.bitfield
.disp32
= 0;
9716 bigdisp
.bitfield
.disp32s
= 0;
9717 bigdisp
.bitfield
.disp64
= 0;
9718 if (operand_type_all_zero (&bigdisp
))
9719 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9725 /* Return the active addressing mode, taking address override and
9726 registers forming the address into consideration. Update the
9727 address override prefix if necessary. */
9729 static enum flag_code
9730 i386_addressing_mode (void)
9732 enum flag_code addr_mode
;
9734 if (i
.prefix
[ADDR_PREFIX
])
9735 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9738 addr_mode
= flag_code
;
9740 #if INFER_ADDR_PREFIX
9741 if (i
.mem_operands
== 0)
9743 /* Infer address prefix from the first memory operand. */
9744 const reg_entry
*addr_reg
= i
.base_reg
;
9746 if (addr_reg
== NULL
)
9747 addr_reg
= i
.index_reg
;
9751 if (addr_reg
->reg_type
.bitfield
.dword
)
9752 addr_mode
= CODE_32BIT
;
9753 else if (flag_code
!= CODE_64BIT
9754 && addr_reg
->reg_type
.bitfield
.word
)
9755 addr_mode
= CODE_16BIT
;
9757 if (addr_mode
!= flag_code
)
9759 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9761 /* Change the size of any displacement too. At most one
9762 of Disp16 or Disp32 is set.
9763 FIXME. There doesn't seem to be any real need for
9764 separate Disp16 and Disp32 flags. The same goes for
9765 Imm16 and Imm32. Removing them would probably clean
9766 up the code quite a lot. */
9767 if (flag_code
!= CODE_64BIT
9768 && (i
.types
[this_operand
].bitfield
.disp16
9769 || i
.types
[this_operand
].bitfield
.disp32
))
9770 i
.types
[this_operand
]
9771 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9781 /* Make sure the memory operand we've been dealt is valid.
9782 Return 1 on success, 0 on a failure. */
9785 i386_index_check (const char *operand_string
)
9787 const char *kind
= "base/index";
9788 enum flag_code addr_mode
= i386_addressing_mode ();
9790 if (current_templates
->start
->opcode_modifier
.isstring
9791 && !current_templates
->start
->opcode_modifier
.immext
9792 && (current_templates
->end
[-1].opcode_modifier
.isstring
9795 /* Memory operands of string insns are special in that they only allow
9796 a single register (rDI, rSI, or rBX) as their memory address. */
9797 const reg_entry
*expected_reg
;
9798 static const char *di_si
[][2] =
9804 static const char *bx
[] = { "ebx", "bx", "rbx" };
9806 kind
= "string address";
9808 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9810 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9812 if (!type
.bitfield
.baseindex
9813 || ((!i
.mem_operands
!= !intel_syntax
)
9814 && current_templates
->end
[-1].operand_types
[1]
9815 .bitfield
.baseindex
))
9816 type
= current_templates
->end
[-1].operand_types
[1];
9817 expected_reg
= hash_find (reg_hash
,
9818 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9822 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9824 if (i
.base_reg
!= expected_reg
9826 || operand_type_check (i
.types
[this_operand
], disp
))
9828 /* The second memory operand must have the same size as
9832 && !((addr_mode
== CODE_64BIT
9833 && i
.base_reg
->reg_type
.bitfield
.qword
)
9834 || (addr_mode
== CODE_32BIT
9835 ? i
.base_reg
->reg_type
.bitfield
.dword
9836 : i
.base_reg
->reg_type
.bitfield
.word
)))
9839 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9841 intel_syntax
? '[' : '(',
9843 expected_reg
->reg_name
,
9844 intel_syntax
? ']' : ')');
9851 as_bad (_("`%s' is not a valid %s expression"),
9852 operand_string
, kind
);
9857 if (addr_mode
!= CODE_16BIT
)
9859 /* 32-bit/64-bit checks. */
9861 && ((addr_mode
== CODE_64BIT
9862 ? !i
.base_reg
->reg_type
.bitfield
.qword
9863 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9864 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9865 || i
.base_reg
->reg_num
== RegIZ
))
9867 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9868 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9869 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9870 && ((addr_mode
== CODE_64BIT
9871 ? !i
.index_reg
->reg_type
.bitfield
.qword
9872 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9873 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9876 /* bndmk, bndldx, and bndstx have special restrictions. */
9877 if (current_templates
->start
->base_opcode
== 0xf30f1b
9878 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9880 /* They cannot use RIP-relative addressing. */
9881 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9883 as_bad (_("`%s' cannot be used here"), operand_string
);
9887 /* bndldx and bndstx ignore their scale factor. */
9888 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9889 && i
.log2_scale_factor
)
9890 as_warn (_("register scaling is being ignored here"));
9895 /* 16-bit checks. */
9897 && (!i
.base_reg
->reg_type
.bitfield
.word
9898 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9900 && (!i
.index_reg
->reg_type
.bitfield
.word
9901 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9903 && i
.base_reg
->reg_num
< 6
9904 && i
.index_reg
->reg_num
>= 6
9905 && i
.log2_scale_factor
== 0))))
9912 /* Handle vector immediates. */
9915 RC_SAE_immediate (const char *imm_start
)
9917 unsigned int match_found
, j
;
9918 const char *pstr
= imm_start
;
9926 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9928 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9932 rc_op
.type
= RC_NamesTable
[j
].type
;
9933 rc_op
.operand
= this_operand
;
9934 i
.rounding
= &rc_op
;
9938 as_bad (_("duplicated `%s'"), imm_start
);
9941 pstr
+= RC_NamesTable
[j
].len
;
9951 as_bad (_("Missing '}': '%s'"), imm_start
);
9954 /* RC/SAE immediate string should contain nothing more. */;
9957 as_bad (_("Junk after '}': '%s'"), imm_start
);
9961 exp
= &im_expressions
[i
.imm_operands
++];
9962 i
.op
[this_operand
].imms
= exp
;
9964 exp
->X_op
= O_constant
;
9965 exp
->X_add_number
= 0;
9966 exp
->X_add_symbol
= (symbolS
*) 0;
9967 exp
->X_op_symbol
= (symbolS
*) 0;
9969 i
.types
[this_operand
].bitfield
.imm8
= 1;
9973 /* Only string instructions can have a second memory operand, so
9974 reduce current_templates to just those if it contains any. */
9976 maybe_adjust_templates (void)
9978 const insn_template
*t
;
9980 gas_assert (i
.mem_operands
== 1);
9982 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9983 if (t
->opcode_modifier
.isstring
)
9986 if (t
< current_templates
->end
)
9988 static templates aux_templates
;
9989 bfd_boolean recheck
;
9991 aux_templates
.start
= t
;
9992 for (; t
< current_templates
->end
; ++t
)
9993 if (!t
->opcode_modifier
.isstring
)
9995 aux_templates
.end
= t
;
9997 /* Determine whether to re-check the first memory operand. */
9998 recheck
= (aux_templates
.start
!= current_templates
->start
9999 || t
!= current_templates
->end
);
10001 current_templates
= &aux_templates
;
10005 i
.mem_operands
= 0;
10006 if (i
.memop1_string
!= NULL
10007 && i386_index_check (i
.memop1_string
) == 0)
10009 i
.mem_operands
= 1;
10016 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10020 i386_att_operand (char *operand_string
)
10022 const reg_entry
*r
;
10024 char *op_string
= operand_string
;
10026 if (is_space_char (*op_string
))
10029 /* We check for an absolute prefix (differentiating,
10030 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10031 if (*op_string
== ABSOLUTE_PREFIX
)
10034 if (is_space_char (*op_string
))
10036 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10039 /* Check if operand is a register. */
10040 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10042 i386_operand_type temp
;
10044 /* Check for a segment override by searching for ':' after a
10045 segment register. */
10046 op_string
= end_op
;
10047 if (is_space_char (*op_string
))
10049 if (*op_string
== ':'
10050 && (r
->reg_type
.bitfield
.sreg2
10051 || r
->reg_type
.bitfield
.sreg3
))
10053 switch (r
->reg_num
)
10056 i
.seg
[i
.mem_operands
] = &es
;
10059 i
.seg
[i
.mem_operands
] = &cs
;
10062 i
.seg
[i
.mem_operands
] = &ss
;
10065 i
.seg
[i
.mem_operands
] = &ds
;
10068 i
.seg
[i
.mem_operands
] = &fs
;
10071 i
.seg
[i
.mem_operands
] = &gs
;
10075 /* Skip the ':' and whitespace. */
10077 if (is_space_char (*op_string
))
10080 if (!is_digit_char (*op_string
)
10081 && !is_identifier_char (*op_string
)
10082 && *op_string
!= '('
10083 && *op_string
!= ABSOLUTE_PREFIX
)
10085 as_bad (_("bad memory operand `%s'"), op_string
);
10088 /* Handle case of %es:*foo. */
10089 if (*op_string
== ABSOLUTE_PREFIX
)
10092 if (is_space_char (*op_string
))
10094 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10096 goto do_memory_reference
;
10099 /* Handle vector operations. */
10100 if (*op_string
== '{')
10102 op_string
= check_VecOperations (op_string
, NULL
);
10103 if (op_string
== NULL
)
10109 as_bad (_("junk `%s' after register"), op_string
);
10112 temp
= r
->reg_type
;
10113 temp
.bitfield
.baseindex
= 0;
10114 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10116 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10117 i
.op
[this_operand
].regs
= r
;
10120 else if (*op_string
== REGISTER_PREFIX
)
10122 as_bad (_("bad register name `%s'"), op_string
);
10125 else if (*op_string
== IMMEDIATE_PREFIX
)
10128 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10130 as_bad (_("immediate operand illegal with absolute jump"));
10133 if (!i386_immediate (op_string
))
10136 else if (RC_SAE_immediate (operand_string
))
10138 /* If it is a RC or SAE immediate, do nothing. */
10141 else if (is_digit_char (*op_string
)
10142 || is_identifier_char (*op_string
)
10143 || *op_string
== '"'
10144 || *op_string
== '(')
10146 /* This is a memory reference of some sort. */
10149 /* Start and end of displacement string expression (if found). */
10150 char *displacement_string_start
;
10151 char *displacement_string_end
;
10154 do_memory_reference
:
10155 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10157 if ((i
.mem_operands
== 1
10158 && !current_templates
->start
->opcode_modifier
.isstring
)
10159 || i
.mem_operands
== 2)
10161 as_bad (_("too many memory references for `%s'"),
10162 current_templates
->start
->name
);
10166 /* Check for base index form. We detect the base index form by
10167 looking for an ')' at the end of the operand, searching
10168 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10170 base_string
= op_string
+ strlen (op_string
);
10172 /* Handle vector operations. */
10173 vop_start
= strchr (op_string
, '{');
10174 if (vop_start
&& vop_start
< base_string
)
10176 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10178 base_string
= vop_start
;
10182 if (is_space_char (*base_string
))
10185 /* If we only have a displacement, set-up for it to be parsed later. */
10186 displacement_string_start
= op_string
;
10187 displacement_string_end
= base_string
+ 1;
10189 if (*base_string
== ')')
10192 unsigned int parens_balanced
= 1;
10193 /* We've already checked that the number of left & right ()'s are
10194 equal, so this loop will not be infinite. */
10198 if (*base_string
== ')')
10200 if (*base_string
== '(')
10203 while (parens_balanced
);
10205 temp_string
= base_string
;
10207 /* Skip past '(' and whitespace. */
10209 if (is_space_char (*base_string
))
10212 if (*base_string
== ','
10213 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10216 displacement_string_end
= temp_string
;
10218 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10222 base_string
= end_op
;
10223 if (is_space_char (*base_string
))
10227 /* There may be an index reg or scale factor here. */
10228 if (*base_string
== ',')
10231 if (is_space_char (*base_string
))
10234 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10237 base_string
= end_op
;
10238 if (is_space_char (*base_string
))
10240 if (*base_string
== ',')
10243 if (is_space_char (*base_string
))
10246 else if (*base_string
!= ')')
10248 as_bad (_("expecting `,' or `)' "
10249 "after index register in `%s'"),
10254 else if (*base_string
== REGISTER_PREFIX
)
10256 end_op
= strchr (base_string
, ',');
10259 as_bad (_("bad register name `%s'"), base_string
);
10263 /* Check for scale factor. */
10264 if (*base_string
!= ')')
10266 char *end_scale
= i386_scale (base_string
);
10271 base_string
= end_scale
;
10272 if (is_space_char (*base_string
))
10274 if (*base_string
!= ')')
10276 as_bad (_("expecting `)' "
10277 "after scale factor in `%s'"),
10282 else if (!i
.index_reg
)
10284 as_bad (_("expecting index register or scale factor "
10285 "after `,'; got '%c'"),
10290 else if (*base_string
!= ')')
10292 as_bad (_("expecting `,' or `)' "
10293 "after base register in `%s'"),
10298 else if (*base_string
== REGISTER_PREFIX
)
10300 end_op
= strchr (base_string
, ',');
10303 as_bad (_("bad register name `%s'"), base_string
);
10308 /* If there's an expression beginning the operand, parse it,
10309 assuming displacement_string_start and
10310 displacement_string_end are meaningful. */
10311 if (displacement_string_start
!= displacement_string_end
)
10313 if (!i386_displacement (displacement_string_start
,
10314 displacement_string_end
))
10318 /* Special case for (%dx) while doing input/output op. */
10320 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10321 && i
.index_reg
== 0
10322 && i
.log2_scale_factor
== 0
10323 && i
.seg
[i
.mem_operands
] == 0
10324 && !operand_type_check (i
.types
[this_operand
], disp
))
10326 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10330 if (i386_index_check (operand_string
) == 0)
10332 i
.flags
[this_operand
] |= Operand_Mem
;
10333 if (i
.mem_operands
== 0)
10334 i
.memop1_string
= xstrdup (operand_string
);
10339 /* It's not a memory operand; argh! */
10340 as_bad (_("invalid char %s beginning operand %d `%s'"),
10341 output_invalid (*op_string
),
10346 return 1; /* Normal return. */
10349 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10350 that an rs_machine_dependent frag may reach. */
10353 i386_frag_max_var (fragS
*frag
)
10355 /* The only relaxable frags are for jumps.
10356 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10357 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10358 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10363 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10365 /* STT_GNU_IFUNC symbol must go through PLT. */
10366 if ((symbol_get_bfdsym (fr_symbol
)->flags
10367 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10370 if (!S_IS_EXTERNAL (fr_symbol
))
10371 /* Symbol may be weak or local. */
10372 return !S_IS_WEAK (fr_symbol
);
10374 /* Global symbols with non-default visibility can't be preempted. */
10375 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10378 if (fr_var
!= NO_RELOC
)
10379 switch ((enum bfd_reloc_code_real
) fr_var
)
10381 case BFD_RELOC_386_PLT32
:
10382 case BFD_RELOC_X86_64_PLT32
:
10383 /* Symbol with PLT relocation may be preempted. */
10389 /* Global symbols with default visibility in a shared library may be
10390 preempted by another definition. */
10395 /* md_estimate_size_before_relax()
10397 Called just before relax() for rs_machine_dependent frags. The x86
10398 assembler uses these frags to handle variable size jump
10401 Any symbol that is now undefined will not become defined.
10402 Return the correct fr_subtype in the frag.
10403 Return the initial "guess for variable size of frag" to caller.
10404 The guess is actually the growth beyond the fixed part. Whatever
10405 we do to grow the fixed or variable part contributes to our
10409 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10411 /* We've already got fragP->fr_subtype right; all we have to do is
10412 check for un-relaxable symbols. On an ELF system, we can't relax
10413 an externally visible symbol, because it may be overridden by a
10415 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10416 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10418 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10421 #if defined (OBJ_COFF) && defined (TE_PE)
10422 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10423 && S_IS_WEAK (fragP
->fr_symbol
))
10427 /* Symbol is undefined in this segment, or we need to keep a
10428 reloc so that weak symbols can be overridden. */
10429 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10430 enum bfd_reloc_code_real reloc_type
;
10431 unsigned char *opcode
;
10434 if (fragP
->fr_var
!= NO_RELOC
)
10435 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10436 else if (size
== 2)
10437 reloc_type
= BFD_RELOC_16_PCREL
;
10438 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10439 else if (need_plt32_p (fragP
->fr_symbol
))
10440 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10443 reloc_type
= BFD_RELOC_32_PCREL
;
10445 old_fr_fix
= fragP
->fr_fix
;
10446 opcode
= (unsigned char *) fragP
->fr_opcode
;
10448 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10451 /* Make jmp (0xeb) a (d)word displacement jump. */
10453 fragP
->fr_fix
+= size
;
10454 fix_new (fragP
, old_fr_fix
, size
,
10456 fragP
->fr_offset
, 1,
10462 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10464 /* Negate the condition, and branch past an
10465 unconditional jump. */
10468 /* Insert an unconditional jump. */
10470 /* We added two extra opcode bytes, and have a two byte
10472 fragP
->fr_fix
+= 2 + 2;
10473 fix_new (fragP
, old_fr_fix
+ 2, 2,
10475 fragP
->fr_offset
, 1,
10479 /* Fall through. */
10482 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10486 fragP
->fr_fix
+= 1;
10487 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10489 fragP
->fr_offset
, 1,
10490 BFD_RELOC_8_PCREL
);
10491 fixP
->fx_signed
= 1;
10495 /* This changes the byte-displacement jump 0x7N
10496 to the (d)word-displacement jump 0x0f,0x8N. */
10497 opcode
[1] = opcode
[0] + 0x10;
10498 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10499 /* We've added an opcode byte. */
10500 fragP
->fr_fix
+= 1 + size
;
10501 fix_new (fragP
, old_fr_fix
+ 1, size
,
10503 fragP
->fr_offset
, 1,
10508 BAD_CASE (fragP
->fr_subtype
);
10512 return fragP
->fr_fix
- old_fr_fix
;
10515 /* Guess size depending on current relax state. Initially the relax
10516 state will correspond to a short jump and we return 1, because
10517 the variable part of the frag (the branch offset) is one byte
10518 long. However, we can relax a section more than once and in that
10519 case we must either set fr_subtype back to the unrelaxed state,
10520 or return the value for the appropriate branch. */
10521 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10524 /* Called after relax() is finished.
10526 In: Address of frag.
10527 fr_type == rs_machine_dependent.
10528 fr_subtype is what the address relaxed to.
10530 Out: Any fixSs and constants are set up.
10531 Caller will turn frag into a ".space 0". */
10534 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10537 unsigned char *opcode
;
10538 unsigned char *where_to_put_displacement
= NULL
;
10539 offsetT target_address
;
10540 offsetT opcode_address
;
10541 unsigned int extension
= 0;
10542 offsetT displacement_from_opcode_start
;
10544 opcode
= (unsigned char *) fragP
->fr_opcode
;
10546 /* Address we want to reach in file space. */
10547 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10549 /* Address opcode resides at in file space. */
10550 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10552 /* Displacement from opcode start to fill into instruction. */
10553 displacement_from_opcode_start
= target_address
- opcode_address
;
10555 if ((fragP
->fr_subtype
& BIG
) == 0)
10557 /* Don't have to change opcode. */
10558 extension
= 1; /* 1 opcode + 1 displacement */
10559 where_to_put_displacement
= &opcode
[1];
10563 if (no_cond_jump_promotion
10564 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10565 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10566 _("long jump required"));
10568 switch (fragP
->fr_subtype
)
10570 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10571 extension
= 4; /* 1 opcode + 4 displacement */
10573 where_to_put_displacement
= &opcode
[1];
10576 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10577 extension
= 2; /* 1 opcode + 2 displacement */
10579 where_to_put_displacement
= &opcode
[1];
10582 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10583 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10584 extension
= 5; /* 2 opcode + 4 displacement */
10585 opcode
[1] = opcode
[0] + 0x10;
10586 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10587 where_to_put_displacement
= &opcode
[2];
10590 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10591 extension
= 3; /* 2 opcode + 2 displacement */
10592 opcode
[1] = opcode
[0] + 0x10;
10593 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10594 where_to_put_displacement
= &opcode
[2];
10597 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10602 where_to_put_displacement
= &opcode
[3];
10606 BAD_CASE (fragP
->fr_subtype
);
10611 /* If size if less then four we are sure that the operand fits,
10612 but if it's 4, then it could be that the displacement is larger
10614 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10616 && ((addressT
) (displacement_from_opcode_start
- extension
10617 + ((addressT
) 1 << 31))
10618 > (((addressT
) 2 << 31) - 1)))
10620 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10621 _("jump target out of range"));
10622 /* Make us emit 0. */
10623 displacement_from_opcode_start
= extension
;
10625 /* Now put displacement after opcode. */
10626 md_number_to_chars ((char *) where_to_put_displacement
,
10627 (valueT
) (displacement_from_opcode_start
- extension
),
10628 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10629 fragP
->fr_fix
+= extension
;
10632 /* Apply a fixup (fixP) to segment data, once it has been determined
10633 by our caller that we have all the info we need to fix it up.
10635 Parameter valP is the pointer to the value of the bits.
10637 On the 386, immediates, displacements, and data pointers are all in
10638 the same (little-endian) format, so we don't need to care about which
10639 we are handling. */
10642 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10644 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10645 valueT value
= *valP
;
10647 #if !defined (TE_Mach)
10648 if (fixP
->fx_pcrel
)
10650 switch (fixP
->fx_r_type
)
10656 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10659 case BFD_RELOC_X86_64_32S
:
10660 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10663 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10666 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10671 if (fixP
->fx_addsy
!= NULL
10672 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10673 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10674 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10675 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10676 && !use_rela_relocations
)
10678 /* This is a hack. There should be a better way to handle this.
10679 This covers for the fact that bfd_install_relocation will
10680 subtract the current location (for partial_inplace, PC relative
10681 relocations); see more below. */
10685 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10688 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10690 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10693 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10695 if ((sym_seg
== seg
10696 || (symbol_section_p (fixP
->fx_addsy
)
10697 && sym_seg
!= absolute_section
))
10698 && !generic_force_reloc (fixP
))
10700 /* Yes, we add the values in twice. This is because
10701 bfd_install_relocation subtracts them out again. I think
10702 bfd_install_relocation is broken, but I don't dare change
10704 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10708 #if defined (OBJ_COFF) && defined (TE_PE)
10709 /* For some reason, the PE format does not store a
10710 section address offset for a PC relative symbol. */
10711 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10712 || S_IS_WEAK (fixP
->fx_addsy
))
10713 value
+= md_pcrel_from (fixP
);
10716 #if defined (OBJ_COFF) && defined (TE_PE)
10717 if (fixP
->fx_addsy
!= NULL
10718 && S_IS_WEAK (fixP
->fx_addsy
)
10719 /* PR 16858: Do not modify weak function references. */
10720 && ! fixP
->fx_pcrel
)
10722 #if !defined (TE_PEP)
10723 /* For x86 PE weak function symbols are neither PC-relative
10724 nor do they set S_IS_FUNCTION. So the only reliable way
10725 to detect them is to check the flags of their containing
10727 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10728 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10732 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10736 /* Fix a few things - the dynamic linker expects certain values here,
10737 and we must not disappoint it. */
10738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10739 if (IS_ELF
&& fixP
->fx_addsy
)
10740 switch (fixP
->fx_r_type
)
10742 case BFD_RELOC_386_PLT32
:
10743 case BFD_RELOC_X86_64_PLT32
:
10744 /* Make the jump instruction point to the address of the operand.
10745 At runtime we merely add the offset to the actual PLT entry.
10746 NB: Subtract the offset size only for jump instructions. */
10747 if (fixP
->fx_pcrel
)
10751 case BFD_RELOC_386_TLS_GD
:
10752 case BFD_RELOC_386_TLS_LDM
:
10753 case BFD_RELOC_386_TLS_IE_32
:
10754 case BFD_RELOC_386_TLS_IE
:
10755 case BFD_RELOC_386_TLS_GOTIE
:
10756 case BFD_RELOC_386_TLS_GOTDESC
:
10757 case BFD_RELOC_X86_64_TLSGD
:
10758 case BFD_RELOC_X86_64_TLSLD
:
10759 case BFD_RELOC_X86_64_GOTTPOFF
:
10760 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10761 value
= 0; /* Fully resolved at runtime. No addend. */
10763 case BFD_RELOC_386_TLS_LE
:
10764 case BFD_RELOC_386_TLS_LDO_32
:
10765 case BFD_RELOC_386_TLS_LE_32
:
10766 case BFD_RELOC_X86_64_DTPOFF32
:
10767 case BFD_RELOC_X86_64_DTPOFF64
:
10768 case BFD_RELOC_X86_64_TPOFF32
:
10769 case BFD_RELOC_X86_64_TPOFF64
:
10770 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10773 case BFD_RELOC_386_TLS_DESC_CALL
:
10774 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10775 value
= 0; /* Fully resolved at runtime. No addend. */
10776 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10780 case BFD_RELOC_VTABLE_INHERIT
:
10781 case BFD_RELOC_VTABLE_ENTRY
:
10788 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10790 #endif /* !defined (TE_Mach) */
10792 /* Are we finished with this relocation now? */
10793 if (fixP
->fx_addsy
== NULL
)
10795 #if defined (OBJ_COFF) && defined (TE_PE)
10796 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10799 /* Remember value for tc_gen_reloc. */
10800 fixP
->fx_addnumber
= value
;
10801 /* Clear out the frag for now. */
10805 else if (use_rela_relocations
)
10807 fixP
->fx_no_overflow
= 1;
10808 /* Remember value for tc_gen_reloc. */
10809 fixP
->fx_addnumber
= value
;
10813 md_number_to_chars (p
, value
, fixP
->fx_size
);
10817 md_atof (int type
, char *litP
, int *sizeP
)
10819 /* This outputs the LITTLENUMs in REVERSE order;
10820 in accord with the bigendian 386. */
10821 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10824 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10827 output_invalid (int c
)
10830 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10833 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10834 "(0x%x)", (unsigned char) c
);
10835 return output_invalid_buf
;
10838 /* REG_STRING starts *before* REGISTER_PREFIX. */
10840 static const reg_entry
*
10841 parse_real_register (char *reg_string
, char **end_op
)
10843 char *s
= reg_string
;
10845 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10846 const reg_entry
*r
;
10848 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10849 if (*s
== REGISTER_PREFIX
)
10852 if (is_space_char (*s
))
10855 p
= reg_name_given
;
10856 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10858 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10859 return (const reg_entry
*) NULL
;
10863 /* For naked regs, make sure that we are not dealing with an identifier.
10864 This prevents confusing an identifier like `eax_var' with register
10866 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10867 return (const reg_entry
*) NULL
;
10871 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10873 /* Handle floating point regs, allowing spaces in the (i) part. */
10874 if (r
== i386_regtab
/* %st is first entry of table */)
10876 if (!cpu_arch_flags
.bitfield
.cpu8087
10877 && !cpu_arch_flags
.bitfield
.cpu287
10878 && !cpu_arch_flags
.bitfield
.cpu387
)
10879 return (const reg_entry
*) NULL
;
10881 if (is_space_char (*s
))
10886 if (is_space_char (*s
))
10888 if (*s
>= '0' && *s
<= '7')
10890 int fpr
= *s
- '0';
10892 if (is_space_char (*s
))
10897 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10902 /* We have "%st(" then garbage. */
10903 return (const reg_entry
*) NULL
;
10907 if (r
== NULL
|| allow_pseudo_reg
)
10910 if (operand_type_all_zero (&r
->reg_type
))
10911 return (const reg_entry
*) NULL
;
10913 if ((r
->reg_type
.bitfield
.dword
10914 || r
->reg_type
.bitfield
.sreg3
10915 || r
->reg_type
.bitfield
.control
10916 || r
->reg_type
.bitfield
.debug
10917 || r
->reg_type
.bitfield
.test
)
10918 && !cpu_arch_flags
.bitfield
.cpui386
)
10919 return (const reg_entry
*) NULL
;
10921 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10922 return (const reg_entry
*) NULL
;
10924 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10926 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10927 return (const reg_entry
*) NULL
;
10929 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10931 if (r
->reg_type
.bitfield
.ymmword
)
10932 return (const reg_entry
*) NULL
;
10934 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10935 return (const reg_entry
*) NULL
;
10939 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10940 return (const reg_entry
*) NULL
;
10942 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10943 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10944 return (const reg_entry
*) NULL
;
10946 /* Upper 16 vector registers are only available with VREX in 64bit
10947 mode, and require EVEX encoding. */
10948 if (r
->reg_flags
& RegVRex
)
10950 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10951 || flag_code
!= CODE_64BIT
)
10952 return (const reg_entry
*) NULL
;
10954 i
.vec_encoding
= vex_encoding_evex
;
10957 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10958 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10959 && flag_code
!= CODE_64BIT
)
10960 return (const reg_entry
*) NULL
;
10962 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10963 return (const reg_entry
*) NULL
;
10968 /* REG_STRING starts *before* REGISTER_PREFIX. */
10970 static const reg_entry
*
10971 parse_register (char *reg_string
, char **end_op
)
10973 const reg_entry
*r
;
10975 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10976 r
= parse_real_register (reg_string
, end_op
);
10981 char *save
= input_line_pointer
;
10985 input_line_pointer
= reg_string
;
10986 c
= get_symbol_name (®_string
);
10987 symbolP
= symbol_find (reg_string
);
10988 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10990 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10992 know (e
->X_op
== O_register
);
10993 know (e
->X_add_number
>= 0
10994 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10995 r
= i386_regtab
+ e
->X_add_number
;
10996 if ((r
->reg_flags
& RegVRex
))
10997 i
.vec_encoding
= vex_encoding_evex
;
10998 *end_op
= input_line_pointer
;
11000 *input_line_pointer
= c
;
11001 input_line_pointer
= save
;
11007 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11009 const reg_entry
*r
;
11010 char *end
= input_line_pointer
;
11013 r
= parse_register (name
, &input_line_pointer
);
11014 if (r
&& end
<= input_line_pointer
)
11016 *nextcharP
= *input_line_pointer
;
11017 *input_line_pointer
= 0;
11018 e
->X_op
= O_register
;
11019 e
->X_add_number
= r
- i386_regtab
;
11022 input_line_pointer
= end
;
11024 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11028 md_operand (expressionS
*e
)
11031 const reg_entry
*r
;
11033 switch (*input_line_pointer
)
11035 case REGISTER_PREFIX
:
11036 r
= parse_real_register (input_line_pointer
, &end
);
11039 e
->X_op
= O_register
;
11040 e
->X_add_number
= r
- i386_regtab
;
11041 input_line_pointer
= end
;
11046 gas_assert (intel_syntax
);
11047 end
= input_line_pointer
++;
11049 if (*input_line_pointer
== ']')
11051 ++input_line_pointer
;
11052 e
->X_op_symbol
= make_expr_symbol (e
);
11053 e
->X_add_symbol
= NULL
;
11054 e
->X_add_number
= 0;
11059 e
->X_op
= O_absent
;
11060 input_line_pointer
= end
;
11067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11068 const char *md_shortopts
= "kVQ:sqnO::";
11070 const char *md_shortopts
= "qnO::";
11073 #define OPTION_32 (OPTION_MD_BASE + 0)
11074 #define OPTION_64 (OPTION_MD_BASE + 1)
11075 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11076 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11077 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11078 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11079 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11080 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11081 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11082 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11083 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11084 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11085 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11086 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11087 #define OPTION_X32 (OPTION_MD_BASE + 14)
11088 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11089 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11090 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11091 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11092 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11093 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11094 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11095 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11096 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11097 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11098 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11099 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11101 struct option md_longopts
[] =
11103 {"32", no_argument
, NULL
, OPTION_32
},
11104 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11105 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11106 {"64", no_argument
, NULL
, OPTION_64
},
11108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11109 {"x32", no_argument
, NULL
, OPTION_X32
},
11110 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11111 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11113 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11114 {"march", required_argument
, NULL
, OPTION_MARCH
},
11115 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11116 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11117 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11118 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11119 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11120 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11121 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11122 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11123 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11124 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11125 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11126 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11127 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11128 # if defined (TE_PE) || defined (TE_PEP)
11129 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11131 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11132 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11133 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11134 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11135 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11136 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11137 {NULL
, no_argument
, NULL
, 0}
11139 size_t md_longopts_size
= sizeof (md_longopts
);
11142 md_parse_option (int c
, const char *arg
)
11145 char *arch
, *next
, *saved
;
11150 optimize_align_code
= 0;
11154 quiet_warnings
= 1;
11157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11158 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11159 should be emitted or not. FIXME: Not implemented. */
11163 /* -V: SVR4 argument to print version ID. */
11165 print_version_id ();
11168 /* -k: Ignore for FreeBSD compatibility. */
11173 /* -s: On i386 Solaris, this tells the native assembler to use
11174 .stab instead of .stab.excl. We always use .stab anyhow. */
11177 case OPTION_MSHARED
:
11181 case OPTION_X86_USED_NOTE
:
11182 if (strcasecmp (arg
, "yes") == 0)
11184 else if (strcasecmp (arg
, "no") == 0)
11187 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11192 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11193 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11196 const char **list
, **l
;
11198 list
= bfd_target_list ();
11199 for (l
= list
; *l
!= NULL
; l
++)
11200 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11201 || strcmp (*l
, "coff-x86-64") == 0
11202 || strcmp (*l
, "pe-x86-64") == 0
11203 || strcmp (*l
, "pei-x86-64") == 0
11204 || strcmp (*l
, "mach-o-x86-64") == 0)
11206 default_arch
= "x86_64";
11210 as_fatal (_("no compiled in support for x86_64"));
11216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11220 const char **list
, **l
;
11222 list
= bfd_target_list ();
11223 for (l
= list
; *l
!= NULL
; l
++)
11224 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11226 default_arch
= "x86_64:32";
11230 as_fatal (_("no compiled in support for 32bit x86_64"));
11234 as_fatal (_("32bit x86_64 is only supported for ELF"));
11239 default_arch
= "i386";
11242 case OPTION_DIVIDE
:
11243 #ifdef SVR4_COMMENT_CHARS
11248 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11250 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11254 i386_comment_chars
= n
;
11260 saved
= xstrdup (arg
);
11262 /* Allow -march=+nosse. */
11268 as_fatal (_("invalid -march= option: `%s'"), arg
);
11269 next
= strchr (arch
, '+');
11272 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11274 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11277 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11280 cpu_arch_name
= cpu_arch
[j
].name
;
11281 cpu_sub_arch_name
= NULL
;
11282 cpu_arch_flags
= cpu_arch
[j
].flags
;
11283 cpu_arch_isa
= cpu_arch
[j
].type
;
11284 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11285 if (!cpu_arch_tune_set
)
11287 cpu_arch_tune
= cpu_arch_isa
;
11288 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11292 else if (*cpu_arch
[j
].name
== '.'
11293 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11295 /* ISA extension. */
11296 i386_cpu_flags flags
;
11298 flags
= cpu_flags_or (cpu_arch_flags
,
11299 cpu_arch
[j
].flags
);
11301 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11303 if (cpu_sub_arch_name
)
11305 char *name
= cpu_sub_arch_name
;
11306 cpu_sub_arch_name
= concat (name
,
11308 (const char *) NULL
);
11312 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11313 cpu_arch_flags
= flags
;
11314 cpu_arch_isa_flags
= flags
;
11318 = cpu_flags_or (cpu_arch_isa_flags
,
11319 cpu_arch
[j
].flags
);
11324 if (j
>= ARRAY_SIZE (cpu_arch
))
11326 /* Disable an ISA extension. */
11327 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11328 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11330 i386_cpu_flags flags
;
11332 flags
= cpu_flags_and_not (cpu_arch_flags
,
11333 cpu_noarch
[j
].flags
);
11334 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11336 if (cpu_sub_arch_name
)
11338 char *name
= cpu_sub_arch_name
;
11339 cpu_sub_arch_name
= concat (arch
,
11340 (const char *) NULL
);
11344 cpu_sub_arch_name
= xstrdup (arch
);
11345 cpu_arch_flags
= flags
;
11346 cpu_arch_isa_flags
= flags
;
11351 if (j
>= ARRAY_SIZE (cpu_noarch
))
11352 j
= ARRAY_SIZE (cpu_arch
);
11355 if (j
>= ARRAY_SIZE (cpu_arch
))
11356 as_fatal (_("invalid -march= option: `%s'"), arg
);
11360 while (next
!= NULL
);
11366 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11367 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11369 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11371 cpu_arch_tune_set
= 1;
11372 cpu_arch_tune
= cpu_arch
[j
].type
;
11373 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11377 if (j
>= ARRAY_SIZE (cpu_arch
))
11378 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11381 case OPTION_MMNEMONIC
:
11382 if (strcasecmp (arg
, "att") == 0)
11383 intel_mnemonic
= 0;
11384 else if (strcasecmp (arg
, "intel") == 0)
11385 intel_mnemonic
= 1;
11387 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11390 case OPTION_MSYNTAX
:
11391 if (strcasecmp (arg
, "att") == 0)
11393 else if (strcasecmp (arg
, "intel") == 0)
11396 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11399 case OPTION_MINDEX_REG
:
11400 allow_index_reg
= 1;
11403 case OPTION_MNAKED_REG
:
11404 allow_naked_reg
= 1;
11407 case OPTION_MSSE2AVX
:
11411 case OPTION_MSSE_CHECK
:
11412 if (strcasecmp (arg
, "error") == 0)
11413 sse_check
= check_error
;
11414 else if (strcasecmp (arg
, "warning") == 0)
11415 sse_check
= check_warning
;
11416 else if (strcasecmp (arg
, "none") == 0)
11417 sse_check
= check_none
;
11419 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11422 case OPTION_MOPERAND_CHECK
:
11423 if (strcasecmp (arg
, "error") == 0)
11424 operand_check
= check_error
;
11425 else if (strcasecmp (arg
, "warning") == 0)
11426 operand_check
= check_warning
;
11427 else if (strcasecmp (arg
, "none") == 0)
11428 operand_check
= check_none
;
11430 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11433 case OPTION_MAVXSCALAR
:
11434 if (strcasecmp (arg
, "128") == 0)
11435 avxscalar
= vex128
;
11436 else if (strcasecmp (arg
, "256") == 0)
11437 avxscalar
= vex256
;
11439 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11442 case OPTION_MVEXWIG
:
11443 if (strcmp (arg
, "0") == 0)
11445 else if (strcmp (arg
, "1") == 0)
11448 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11451 case OPTION_MADD_BND_PREFIX
:
11452 add_bnd_prefix
= 1;
11455 case OPTION_MEVEXLIG
:
11456 if (strcmp (arg
, "128") == 0)
11457 evexlig
= evexl128
;
11458 else if (strcmp (arg
, "256") == 0)
11459 evexlig
= evexl256
;
11460 else if (strcmp (arg
, "512") == 0)
11461 evexlig
= evexl512
;
11463 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11466 case OPTION_MEVEXRCIG
:
11467 if (strcmp (arg
, "rne") == 0)
11469 else if (strcmp (arg
, "rd") == 0)
11471 else if (strcmp (arg
, "ru") == 0)
11473 else if (strcmp (arg
, "rz") == 0)
11476 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11479 case OPTION_MEVEXWIG
:
11480 if (strcmp (arg
, "0") == 0)
11482 else if (strcmp (arg
, "1") == 0)
11485 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11488 # if defined (TE_PE) || defined (TE_PEP)
11489 case OPTION_MBIG_OBJ
:
11494 case OPTION_MOMIT_LOCK_PREFIX
:
11495 if (strcasecmp (arg
, "yes") == 0)
11496 omit_lock_prefix
= 1;
11497 else if (strcasecmp (arg
, "no") == 0)
11498 omit_lock_prefix
= 0;
11500 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11503 case OPTION_MFENCE_AS_LOCK_ADD
:
11504 if (strcasecmp (arg
, "yes") == 0)
11506 else if (strcasecmp (arg
, "no") == 0)
11509 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11512 case OPTION_MRELAX_RELOCATIONS
:
11513 if (strcasecmp (arg
, "yes") == 0)
11514 generate_relax_relocations
= 1;
11515 else if (strcasecmp (arg
, "no") == 0)
11516 generate_relax_relocations
= 0;
11518 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11521 case OPTION_MAMD64
:
11525 case OPTION_MINTEL64
:
11533 /* Turn off -Os. */
11534 optimize_for_space
= 0;
11536 else if (*arg
== 's')
11538 optimize_for_space
= 1;
11539 /* Turn on all encoding optimizations. */
11540 optimize
= INT_MAX
;
11544 optimize
= atoi (arg
);
11545 /* Turn off -Os. */
11546 optimize_for_space
= 0;
11556 #define MESSAGE_TEMPLATE \
11560 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11561 int *left_p
, const char *name
, int len
)
11563 int size
= sizeof (MESSAGE_TEMPLATE
);
11564 int left
= *left_p
;
11566 /* Reserve 2 spaces for ", " or ",\0" */
11569 /* Check if there is any room. */
11577 p
= mempcpy (p
, name
, len
);
11581 /* Output the current message now and start a new one. */
11584 fprintf (stream
, "%s\n", message
);
11586 left
= size
- (start
- message
) - len
- 2;
11588 gas_assert (left
>= 0);
11590 p
= mempcpy (p
, name
, len
);
11598 show_arch (FILE *stream
, int ext
, int check
)
11600 static char message
[] = MESSAGE_TEMPLATE
;
11601 char *start
= message
+ 27;
11603 int size
= sizeof (MESSAGE_TEMPLATE
);
11610 left
= size
- (start
- message
);
11611 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11613 /* Should it be skipped? */
11614 if (cpu_arch
[j
].skip
)
11617 name
= cpu_arch
[j
].name
;
11618 len
= cpu_arch
[j
].len
;
11621 /* It is an extension. Skip if we aren't asked to show it. */
11632 /* It is an processor. Skip if we show only extension. */
11635 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11637 /* It is an impossible processor - skip. */
11641 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11644 /* Display disabled extensions. */
11646 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11648 name
= cpu_noarch
[j
].name
;
11649 len
= cpu_noarch
[j
].len
;
11650 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11655 fprintf (stream
, "%s\n", message
);
11659 md_show_usage (FILE *stream
)
11661 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11662 fprintf (stream
, _("\
11664 -V print assembler version number\n\
11667 fprintf (stream
, _("\
11668 -n Do not optimize code alignment\n\
11669 -q quieten some warnings\n"));
11670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11671 fprintf (stream
, _("\
11674 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11675 || defined (TE_PE) || defined (TE_PEP))
11676 fprintf (stream
, _("\
11677 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11679 #ifdef SVR4_COMMENT_CHARS
11680 fprintf (stream
, _("\
11681 --divide do not treat `/' as a comment character\n"));
11683 fprintf (stream
, _("\
11684 --divide ignored\n"));
11686 fprintf (stream
, _("\
11687 -march=CPU[,+EXTENSION...]\n\
11688 generate code for CPU and EXTENSION, CPU is one of:\n"));
11689 show_arch (stream
, 0, 1);
11690 fprintf (stream
, _("\
11691 EXTENSION is combination of:\n"));
11692 show_arch (stream
, 1, 0);
11693 fprintf (stream
, _("\
11694 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11695 show_arch (stream
, 0, 0);
11696 fprintf (stream
, _("\
11697 -msse2avx encode SSE instructions with VEX prefix\n"));
11698 fprintf (stream
, _("\
11699 -msse-check=[none|error|warning] (default: warning)\n\
11700 check SSE instructions\n"));
11701 fprintf (stream
, _("\
11702 -moperand-check=[none|error|warning] (default: warning)\n\
11703 check operand combinations for validity\n"));
11704 fprintf (stream
, _("\
11705 -mavxscalar=[128|256] (default: 128)\n\
11706 encode scalar AVX instructions with specific vector\n\
11708 fprintf (stream
, _("\
11709 -mvexwig=[0|1] (default: 0)\n\
11710 encode VEX instructions with specific VEX.W value\n\
11711 for VEX.W bit ignored instructions\n"));
11712 fprintf (stream
, _("\
11713 -mevexlig=[128|256|512] (default: 128)\n\
11714 encode scalar EVEX instructions with specific vector\n\
11716 fprintf (stream
, _("\
11717 -mevexwig=[0|1] (default: 0)\n\
11718 encode EVEX instructions with specific EVEX.W value\n\
11719 for EVEX.W bit ignored instructions\n"));
11720 fprintf (stream
, _("\
11721 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11722 encode EVEX instructions with specific EVEX.RC value\n\
11723 for SAE-only ignored instructions\n"));
11724 fprintf (stream
, _("\
11725 -mmnemonic=[att|intel] "));
11726 if (SYSV386_COMPAT
)
11727 fprintf (stream
, _("(default: att)\n"));
11729 fprintf (stream
, _("(default: intel)\n"));
11730 fprintf (stream
, _("\
11731 use AT&T/Intel mnemonic\n"));
11732 fprintf (stream
, _("\
11733 -msyntax=[att|intel] (default: att)\n\
11734 use AT&T/Intel syntax\n"));
11735 fprintf (stream
, _("\
11736 -mindex-reg support pseudo index registers\n"));
11737 fprintf (stream
, _("\
11738 -mnaked-reg don't require `%%' prefix for registers\n"));
11739 fprintf (stream
, _("\
11740 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11742 fprintf (stream
, _("\
11743 -mshared disable branch optimization for shared code\n"));
11744 fprintf (stream
, _("\
11745 -mx86-used-note=[no|yes] "));
11746 if (DEFAULT_X86_USED_NOTE
)
11747 fprintf (stream
, _("(default: yes)\n"));
11749 fprintf (stream
, _("(default: no)\n"));
11750 fprintf (stream
, _("\
11751 generate x86 used ISA and feature properties\n"));
11753 #if defined (TE_PE) || defined (TE_PEP)
11754 fprintf (stream
, _("\
11755 -mbig-obj generate big object files\n"));
11757 fprintf (stream
, _("\
11758 -momit-lock-prefix=[no|yes] (default: no)\n\
11759 strip all lock prefixes\n"));
11760 fprintf (stream
, _("\
11761 -mfence-as-lock-add=[no|yes] (default: no)\n\
11762 encode lfence, mfence and sfence as\n\
11763 lock addl $0x0, (%%{re}sp)\n"));
11764 fprintf (stream
, _("\
11765 -mrelax-relocations=[no|yes] "));
11766 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11767 fprintf (stream
, _("(default: yes)\n"));
11769 fprintf (stream
, _("(default: no)\n"));
11770 fprintf (stream
, _("\
11771 generate relax relocations\n"));
11772 fprintf (stream
, _("\
11773 -mamd64 accept only AMD64 ISA [default]\n"));
11774 fprintf (stream
, _("\
11775 -mintel64 accept only Intel64 ISA\n"));
11778 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11779 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11780 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11782 /* Pick the target format to use. */
11785 i386_target_format (void)
11787 if (!strncmp (default_arch
, "x86_64", 6))
11789 update_code_flag (CODE_64BIT
, 1);
11790 if (default_arch
[6] == '\0')
11791 x86_elf_abi
= X86_64_ABI
;
11793 x86_elf_abi
= X86_64_X32_ABI
;
11795 else if (!strcmp (default_arch
, "i386"))
11796 update_code_flag (CODE_32BIT
, 1);
11797 else if (!strcmp (default_arch
, "iamcu"))
11799 update_code_flag (CODE_32BIT
, 1);
11800 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11802 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11803 cpu_arch_name
= "iamcu";
11804 cpu_sub_arch_name
= NULL
;
11805 cpu_arch_flags
= iamcu_flags
;
11806 cpu_arch_isa
= PROCESSOR_IAMCU
;
11807 cpu_arch_isa_flags
= iamcu_flags
;
11808 if (!cpu_arch_tune_set
)
11810 cpu_arch_tune
= cpu_arch_isa
;
11811 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11814 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11815 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11819 as_fatal (_("unknown architecture"));
11821 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11822 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11823 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11824 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11826 switch (OUTPUT_FLAVOR
)
11828 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11829 case bfd_target_aout_flavour
:
11830 return AOUT_TARGET_FORMAT
;
11832 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11833 # if defined (TE_PE) || defined (TE_PEP)
11834 case bfd_target_coff_flavour
:
11835 if (flag_code
== CODE_64BIT
)
11836 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11839 # elif defined (TE_GO32)
11840 case bfd_target_coff_flavour
:
11841 return "coff-go32";
11843 case bfd_target_coff_flavour
:
11844 return "coff-i386";
11847 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11848 case bfd_target_elf_flavour
:
11850 const char *format
;
11852 switch (x86_elf_abi
)
11855 format
= ELF_TARGET_FORMAT
;
11858 use_rela_relocations
= 1;
11860 format
= ELF_TARGET_FORMAT64
;
11862 case X86_64_X32_ABI
:
11863 use_rela_relocations
= 1;
11865 disallow_64bit_reloc
= 1;
11866 format
= ELF_TARGET_FORMAT32
;
11869 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11871 if (x86_elf_abi
!= X86_64_ABI
)
11872 as_fatal (_("Intel L1OM is 64bit only"));
11873 return ELF_TARGET_L1OM_FORMAT
;
11875 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11877 if (x86_elf_abi
!= X86_64_ABI
)
11878 as_fatal (_("Intel K1OM is 64bit only"));
11879 return ELF_TARGET_K1OM_FORMAT
;
11881 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11883 if (x86_elf_abi
!= I386_ABI
)
11884 as_fatal (_("Intel MCU is 32bit only"));
11885 return ELF_TARGET_IAMCU_FORMAT
;
11891 #if defined (OBJ_MACH_O)
11892 case bfd_target_mach_o_flavour
:
11893 if (flag_code
== CODE_64BIT
)
11895 use_rela_relocations
= 1;
11897 return "mach-o-x86-64";
11900 return "mach-o-i386";
11908 #endif /* OBJ_MAYBE_ more than one */
11911 md_undefined_symbol (char *name
)
11913 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11914 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11915 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11916 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11920 if (symbol_find (name
))
11921 as_bad (_("GOT already in symbol table"));
11922 GOT_symbol
= symbol_new (name
, undefined_section
,
11923 (valueT
) 0, &zero_address_frag
);
11930 /* Round up a section size to the appropriate boundary. */
11933 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11935 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11936 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11938 /* For a.out, force the section size to be aligned. If we don't do
11939 this, BFD will align it for us, but it will not write out the
11940 final bytes of the section. This may be a bug in BFD, but it is
11941 easier to fix it here since that is how the other a.out targets
11945 align
= bfd_get_section_alignment (stdoutput
, segment
);
11946 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11953 /* On the i386, PC-relative offsets are relative to the start of the
11954 next instruction. That is, the address of the offset, plus its
11955 size, since the offset is always the last part of the insn. */
11958 md_pcrel_from (fixS
*fixP
)
11960 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11966 s_bss (int ignore ATTRIBUTE_UNUSED
)
11970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11972 obj_elf_section_change_hook ();
11974 temp
= get_absolute_expression ();
11975 subseg_set (bss_section
, (subsegT
) temp
);
11976 demand_empty_rest_of_line ();
11982 i386_validate_fix (fixS
*fixp
)
11984 if (fixp
->fx_subsy
)
11986 if (fixp
->fx_subsy
== GOT_symbol
)
11988 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11993 if (fixp
->fx_tcbit2
)
11994 fixp
->fx_r_type
= (fixp
->fx_tcbit
11995 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11996 : BFD_RELOC_X86_64_GOTPCRELX
);
11999 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
12004 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
12006 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
12008 fixp
->fx_subsy
= 0;
12011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12012 else if (!object_64bit
)
12014 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
12015 && fixp
->fx_tcbit2
)
12016 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12022 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12025 bfd_reloc_code_real_type code
;
12027 switch (fixp
->fx_r_type
)
12029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12030 case BFD_RELOC_SIZE32
:
12031 case BFD_RELOC_SIZE64
:
12032 if (S_IS_DEFINED (fixp
->fx_addsy
)
12033 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12035 /* Resolve size relocation against local symbol to size of
12036 the symbol plus addend. */
12037 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12038 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12039 && !fits_in_unsigned_long (value
))
12040 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12041 _("symbol size computation overflow"));
12042 fixp
->fx_addsy
= NULL
;
12043 fixp
->fx_subsy
= NULL
;
12044 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12048 /* Fall through. */
12050 case BFD_RELOC_X86_64_PLT32
:
12051 case BFD_RELOC_X86_64_GOT32
:
12052 case BFD_RELOC_X86_64_GOTPCREL
:
12053 case BFD_RELOC_X86_64_GOTPCRELX
:
12054 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12055 case BFD_RELOC_386_PLT32
:
12056 case BFD_RELOC_386_GOT32
:
12057 case BFD_RELOC_386_GOT32X
:
12058 case BFD_RELOC_386_GOTOFF
:
12059 case BFD_RELOC_386_GOTPC
:
12060 case BFD_RELOC_386_TLS_GD
:
12061 case BFD_RELOC_386_TLS_LDM
:
12062 case BFD_RELOC_386_TLS_LDO_32
:
12063 case BFD_RELOC_386_TLS_IE_32
:
12064 case BFD_RELOC_386_TLS_IE
:
12065 case BFD_RELOC_386_TLS_GOTIE
:
12066 case BFD_RELOC_386_TLS_LE_32
:
12067 case BFD_RELOC_386_TLS_LE
:
12068 case BFD_RELOC_386_TLS_GOTDESC
:
12069 case BFD_RELOC_386_TLS_DESC_CALL
:
12070 case BFD_RELOC_X86_64_TLSGD
:
12071 case BFD_RELOC_X86_64_TLSLD
:
12072 case BFD_RELOC_X86_64_DTPOFF32
:
12073 case BFD_RELOC_X86_64_DTPOFF64
:
12074 case BFD_RELOC_X86_64_GOTTPOFF
:
12075 case BFD_RELOC_X86_64_TPOFF32
:
12076 case BFD_RELOC_X86_64_TPOFF64
:
12077 case BFD_RELOC_X86_64_GOTOFF64
:
12078 case BFD_RELOC_X86_64_GOTPC32
:
12079 case BFD_RELOC_X86_64_GOT64
:
12080 case BFD_RELOC_X86_64_GOTPCREL64
:
12081 case BFD_RELOC_X86_64_GOTPC64
:
12082 case BFD_RELOC_X86_64_GOTPLT64
:
12083 case BFD_RELOC_X86_64_PLTOFF64
:
12084 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12085 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12086 case BFD_RELOC_RVA
:
12087 case BFD_RELOC_VTABLE_ENTRY
:
12088 case BFD_RELOC_VTABLE_INHERIT
:
12090 case BFD_RELOC_32_SECREL
:
12092 code
= fixp
->fx_r_type
;
12094 case BFD_RELOC_X86_64_32S
:
12095 if (!fixp
->fx_pcrel
)
12097 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12098 code
= fixp
->fx_r_type
;
12101 /* Fall through. */
12103 if (fixp
->fx_pcrel
)
12105 switch (fixp
->fx_size
)
12108 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12109 _("can not do %d byte pc-relative relocation"),
12111 code
= BFD_RELOC_32_PCREL
;
12113 case 1: code
= BFD_RELOC_8_PCREL
; break;
12114 case 2: code
= BFD_RELOC_16_PCREL
; break;
12115 case 4: code
= BFD_RELOC_32_PCREL
; break;
12117 case 8: code
= BFD_RELOC_64_PCREL
; break;
12123 switch (fixp
->fx_size
)
12126 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12127 _("can not do %d byte relocation"),
12129 code
= BFD_RELOC_32
;
12131 case 1: code
= BFD_RELOC_8
; break;
12132 case 2: code
= BFD_RELOC_16
; break;
12133 case 4: code
= BFD_RELOC_32
; break;
12135 case 8: code
= BFD_RELOC_64
; break;
12142 if ((code
== BFD_RELOC_32
12143 || code
== BFD_RELOC_32_PCREL
12144 || code
== BFD_RELOC_X86_64_32S
)
12146 && fixp
->fx_addsy
== GOT_symbol
)
12149 code
= BFD_RELOC_386_GOTPC
;
12151 code
= BFD_RELOC_X86_64_GOTPC32
;
12153 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12155 && fixp
->fx_addsy
== GOT_symbol
)
12157 code
= BFD_RELOC_X86_64_GOTPC64
;
12160 rel
= XNEW (arelent
);
12161 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12162 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12164 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12166 if (!use_rela_relocations
)
12168 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12169 vtable entry to be used in the relocation's section offset. */
12170 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12171 rel
->address
= fixp
->fx_offset
;
12172 #if defined (OBJ_COFF) && defined (TE_PE)
12173 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12174 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12179 /* Use the rela in 64bit mode. */
12182 if (disallow_64bit_reloc
)
12185 case BFD_RELOC_X86_64_DTPOFF64
:
12186 case BFD_RELOC_X86_64_TPOFF64
:
12187 case BFD_RELOC_64_PCREL
:
12188 case BFD_RELOC_X86_64_GOTOFF64
:
12189 case BFD_RELOC_X86_64_GOT64
:
12190 case BFD_RELOC_X86_64_GOTPCREL64
:
12191 case BFD_RELOC_X86_64_GOTPC64
:
12192 case BFD_RELOC_X86_64_GOTPLT64
:
12193 case BFD_RELOC_X86_64_PLTOFF64
:
12194 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12195 _("cannot represent relocation type %s in x32 mode"),
12196 bfd_get_reloc_code_name (code
));
12202 if (!fixp
->fx_pcrel
)
12203 rel
->addend
= fixp
->fx_offset
;
12207 case BFD_RELOC_X86_64_PLT32
:
12208 case BFD_RELOC_X86_64_GOT32
:
12209 case BFD_RELOC_X86_64_GOTPCREL
:
12210 case BFD_RELOC_X86_64_GOTPCRELX
:
12211 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12212 case BFD_RELOC_X86_64_TLSGD
:
12213 case BFD_RELOC_X86_64_TLSLD
:
12214 case BFD_RELOC_X86_64_GOTTPOFF
:
12215 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12216 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12217 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12220 rel
->addend
= (section
->vma
12222 + fixp
->fx_addnumber
12223 + md_pcrel_from (fixp
));
12228 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12229 if (rel
->howto
== NULL
)
12231 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12232 _("cannot represent relocation type %s"),
12233 bfd_get_reloc_code_name (code
));
12234 /* Set howto to a garbage value so that we can keep going. */
12235 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12236 gas_assert (rel
->howto
!= NULL
);
12242 #include "tc-i386-intel.c"
12245 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12247 int saved_naked_reg
;
12248 char saved_register_dot
;
12250 saved_naked_reg
= allow_naked_reg
;
12251 allow_naked_reg
= 1;
12252 saved_register_dot
= register_chars
['.'];
12253 register_chars
['.'] = '.';
12254 allow_pseudo_reg
= 1;
12255 expression_and_evaluate (exp
);
12256 allow_pseudo_reg
= 0;
12257 register_chars
['.'] = saved_register_dot
;
12258 allow_naked_reg
= saved_naked_reg
;
12260 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12262 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12264 exp
->X_op
= O_constant
;
12265 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12266 .dw2_regnum
[flag_code
>> 1];
12269 exp
->X_op
= O_illegal
;
12274 tc_x86_frame_initial_instructions (void)
12276 static unsigned int sp_regno
[2];
12278 if (!sp_regno
[flag_code
>> 1])
12280 char *saved_input
= input_line_pointer
;
12281 char sp
[][4] = {"esp", "rsp"};
12284 input_line_pointer
= sp
[flag_code
>> 1];
12285 tc_x86_parse_to_dw2regnum (&exp
);
12286 gas_assert (exp
.X_op
== O_constant
);
12287 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12288 input_line_pointer
= saved_input
;
12291 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12292 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12296 x86_dwarf2_addr_size (void)
12298 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12299 if (x86_elf_abi
== X86_64_X32_ABI
)
12302 return bfd_arch_bits_per_address (stdoutput
) / 8;
12306 i386_elf_section_type (const char *str
, size_t len
)
12308 if (flag_code
== CODE_64BIT
12309 && len
== sizeof ("unwind") - 1
12310 && strncmp (str
, "unwind", 6) == 0)
12311 return SHT_X86_64_UNWIND
;
12318 i386_solaris_fix_up_eh_frame (segT sec
)
12320 if (flag_code
== CODE_64BIT
)
12321 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12327 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12331 exp
.X_op
= O_secrel
;
12332 exp
.X_add_symbol
= symbol
;
12333 exp
.X_add_number
= 0;
12334 emit_expr (&exp
, size
);
12338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12339 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12342 x86_64_section_letter (int letter
, const char **ptr_msg
)
12344 if (flag_code
== CODE_64BIT
)
12347 return SHF_X86_64_LARGE
;
12349 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12352 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12357 x86_64_section_word (char *str
, size_t len
)
12359 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12360 return SHF_X86_64_LARGE
;
12366 handle_large_common (int small ATTRIBUTE_UNUSED
)
12368 if (flag_code
!= CODE_64BIT
)
12370 s_comm_internal (0, elf_common_parse
);
12371 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12375 static segT lbss_section
;
12376 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12377 asection
*saved_bss_section
= bss_section
;
12379 if (lbss_section
== NULL
)
12381 flagword applicable
;
12382 segT seg
= now_seg
;
12383 subsegT subseg
= now_subseg
;
12385 /* The .lbss section is for local .largecomm symbols. */
12386 lbss_section
= subseg_new (".lbss", 0);
12387 applicable
= bfd_applicable_section_flags (stdoutput
);
12388 bfd_set_section_flags (stdoutput
, lbss_section
,
12389 applicable
& SEC_ALLOC
);
12390 seg_info (lbss_section
)->bss
= 1;
12392 subseg_set (seg
, subseg
);
12395 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12396 bss_section
= lbss_section
;
12398 s_comm_internal (0, elf_common_parse
);
12400 elf_com_section_ptr
= saved_com_section_ptr
;
12401 bss_section
= saved_bss_section
;
12404 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */