1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* RM and SIB are the modrm byte and the sib byte where the
372 addressing modes of this insn are encoded. */
379 /* Masking attributes. */
380 struct Mask_Operation
*mask
;
382 /* Rounding control and SAE attributes. */
383 struct RC_Operation
*rounding
;
385 /* Broadcasting attributes. */
386 struct Broadcast_Operation
*broadcast
;
388 /* Compressed disp8*N attribute. */
389 unsigned int memshift
;
391 /* Prefer load or store in encoding. */
394 dir_encoding_default
= 0,
400 /* Prefer 8bit or 32bit displacement in encoding. */
403 disp_encoding_default
= 0,
408 /* Prefer the REX byte in encoding. */
409 bfd_boolean rex_encoding
;
411 /* Disable instruction size optimization. */
412 bfd_boolean no_optimize
;
414 /* How to encode vector instructions. */
417 vex_encoding_default
= 0,
424 const char *rep_prefix
;
427 const char *hle_prefix
;
429 /* Have BND prefix. */
430 const char *bnd_prefix
;
432 /* Have NOTRACK prefix. */
433 const char *notrack_prefix
;
436 enum i386_error error
;
439 typedef struct _i386_insn i386_insn
;
441 /* Link RC type with corresponding string, that'll be looked for in
450 static const struct RC_name RC_NamesTable
[] =
452 { rne
, STRING_COMMA_LEN ("rn-sae") },
453 { rd
, STRING_COMMA_LEN ("rd-sae") },
454 { ru
, STRING_COMMA_LEN ("ru-sae") },
455 { rz
, STRING_COMMA_LEN ("rz-sae") },
456 { saeonly
, STRING_COMMA_LEN ("sae") },
459 /* List of chars besides those in app.c:symbol_chars that can start an
460 operand. Used to prevent the scrubber eating vital white-space. */
461 const char extra_symbol_chars
[] = "*%-([{}"
470 #if (defined (TE_I386AIX) \
471 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
472 && !defined (TE_GNU) \
473 && !defined (TE_LINUX) \
474 && !defined (TE_NACL) \
475 && !defined (TE_FreeBSD) \
476 && !defined (TE_DragonFly) \
477 && !defined (TE_NetBSD)))
478 /* This array holds the chars that always start a comment. If the
479 pre-processor is disabled, these aren't very useful. The option
480 --divide will remove '/' from this list. */
481 const char *i386_comment_chars
= "#/";
482 #define SVR4_COMMENT_CHARS 1
483 #define PREFIX_SEPARATOR '\\'
486 const char *i386_comment_chars
= "#";
487 #define PREFIX_SEPARATOR '/'
490 /* This array holds the chars that only start a comment at the beginning of
491 a line. If the line seems to have the form '# 123 filename'
492 .line and .file directives will appear in the pre-processed output.
493 Note that input_file.c hand checks for '#' at the beginning of the
494 first line of the input file. This is because the compiler outputs
495 #NO_APP at the beginning of its output.
496 Also note that comments started like this one will always work if
497 '/' isn't otherwise defined. */
498 const char line_comment_chars
[] = "#/";
500 const char line_separator_chars
[] = ";";
502 /* Chars that can be used to separate mant from exp in floating point
504 const char EXP_CHARS
[] = "eE";
506 /* Chars that mean this number is a floating point constant
509 const char FLT_CHARS
[] = "fFdDxX";
511 /* Tables for lexical analysis. */
512 static char mnemonic_chars
[256];
513 static char register_chars
[256];
514 static char operand_chars
[256];
515 static char identifier_chars
[256];
516 static char digit_chars
[256];
518 /* Lexical macros. */
519 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
520 #define is_operand_char(x) (operand_chars[(unsigned char) x])
521 #define is_register_char(x) (register_chars[(unsigned char) x])
522 #define is_space_char(x) ((x) == ' ')
523 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
524 #define is_digit_char(x) (digit_chars[(unsigned char) x])
526 /* All non-digit non-letter characters that may occur in an operand. */
527 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
529 /* md_assemble() always leaves the strings it's passed unaltered. To
530 effect this we maintain a stack of saved characters that we've smashed
531 with '\0's (indicating end of strings for various sub-fields of the
532 assembler instruction). */
533 static char save_stack
[32];
534 static char *save_stack_p
;
535 #define END_STRING_AND_SAVE(s) \
536 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
537 #define RESTORE_END_STRING(s) \
538 do { *(s) = *--save_stack_p; } while (0)
540 /* The instruction we're assembling. */
543 /* Possible templates for current insn. */
544 static const templates
*current_templates
;
546 /* Per instruction expressionS buffers: max displacements & immediates. */
547 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
548 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
550 /* Current operand we are working on. */
551 static int this_operand
= -1;
553 /* We support four different modes. FLAG_CODE variable is used to distinguish
561 static enum flag_code flag_code
;
562 static unsigned int object_64bit
;
563 static unsigned int disallow_64bit_reloc
;
564 static int use_rela_relocations
= 0;
566 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
567 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
570 /* The ELF ABI to use. */
578 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
581 #if defined (TE_PE) || defined (TE_PEP)
582 /* Use big object file format. */
583 static int use_big_obj
= 0;
586 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
587 /* 1 if generating code for a shared library. */
588 static int shared
= 0;
591 /* 1 for intel syntax,
593 static int intel_syntax
= 0;
595 /* 1 for Intel64 ISA,
599 /* 1 for intel mnemonic,
600 0 if att mnemonic. */
601 static int intel_mnemonic
= !SYSV386_COMPAT
;
603 /* 1 if pseudo registers are permitted. */
604 static int allow_pseudo_reg
= 0;
606 /* 1 if register prefix % not required. */
607 static int allow_naked_reg
= 0;
609 /* 1 if the assembler should add BND prefix for all control-transferring
610 instructions supporting it, even if this prefix wasn't specified
612 static int add_bnd_prefix
= 0;
614 /* 1 if pseudo index register, eiz/riz, is allowed . */
615 static int allow_index_reg
= 0;
617 /* 1 if the assembler should ignore LOCK prefix, even if it was
618 specified explicitly. */
619 static int omit_lock_prefix
= 0;
621 /* 1 if the assembler should encode lfence, mfence, and sfence as
622 "lock addl $0, (%{re}sp)". */
623 static int avoid_fence
= 0;
625 /* 1 if the assembler should generate relax relocations. */
627 static int generate_relax_relocations
628 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
630 static enum check_kind
636 sse_check
, operand_check
= check_warning
;
639 1. Clear the REX_W bit with register operand if possible.
640 2. Above plus use 128bit vector instruction to clear the full vector
643 static int optimize
= 0;
646 1. Clear the REX_W bit with register operand if possible.
647 2. Above plus use 128bit vector instruction to clear the full vector
649 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
652 static int optimize_for_space
= 0;
654 /* Register prefix used for error message. */
655 static const char *register_prefix
= "%";
657 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
658 leave, push, and pop instructions so that gcc has the same stack
659 frame as in 32 bit mode. */
660 static char stackop_size
= '\0';
662 /* Non-zero to optimize code alignment. */
663 int optimize_align_code
= 1;
665 /* Non-zero to quieten some warnings. */
666 static int quiet_warnings
= 0;
669 static const char *cpu_arch_name
= NULL
;
670 static char *cpu_sub_arch_name
= NULL
;
672 /* CPU feature flags. */
673 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
675 /* If we have selected a cpu we are generating instructions for. */
676 static int cpu_arch_tune_set
= 0;
678 /* Cpu we are generating instructions for. */
679 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of cpu we are generating instructions for. */
682 static i386_cpu_flags cpu_arch_tune_flags
;
684 /* CPU instruction set architecture used. */
685 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
687 /* CPU feature flags of instruction set architecture used. */
688 i386_cpu_flags cpu_arch_isa_flags
;
690 /* If set, conditional jumps are not automatically promoted to handle
691 larger than a byte offset. */
692 static unsigned int no_cond_jump_promotion
= 0;
694 /* Encode SSE instructions with VEX prefix. */
695 static unsigned int sse2avx
;
697 /* Encode scalar AVX instructions with specific vector length. */
704 /* Encode VEX WIG instructions with specific vex.w. */
711 /* Encode scalar EVEX LIG instructions with specific vector length. */
719 /* Encode EVEX WIG instructions with specific evex.w. */
726 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
727 static enum rc_type evexrcig
= rne
;
729 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
730 static symbolS
*GOT_symbol
;
732 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
733 unsigned int x86_dwarf2_return_column
;
735 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
736 int x86_cie_data_alignment
;
738 /* Interface to relax_segment.
739 There are 3 major relax states for 386 jump insns because the
740 different types of jumps add different sizes to frags when we're
741 figuring out what sort of jump to choose to reach a given label. */
744 #define UNCOND_JUMP 0
746 #define COND_JUMP86 2
751 #define SMALL16 (SMALL | CODE16)
753 #define BIG16 (BIG | CODE16)
757 #define INLINE __inline__
763 #define ENCODE_RELAX_STATE(type, size) \
764 ((relax_substateT) (((type) << 2) | (size)))
765 #define TYPE_FROM_RELAX_STATE(s) \
767 #define DISP_SIZE_FROM_RELAX_STATE(s) \
768 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
770 /* This table is used by relax_frag to promote short jumps to long
771 ones where necessary. SMALL (short) jumps may be promoted to BIG
772 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
773 don't allow a short jump in a 32 bit code segment to be promoted to
774 a 16 bit offset jump because it's slower (requires data size
775 prefix), and doesn't work, unless the destination is in the bottom
776 64k of the code segment (The top 16 bits of eip are zeroed). */
778 const relax_typeS md_relax_table
[] =
781 1) most positive reach of this state,
782 2) most negative reach of this state,
783 3) how many bytes this mode will have in the variable part of the frag
784 4) which index into the table to try if we can't fit into this one. */
786 /* UNCOND_JUMP states. */
787 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
788 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
789 /* dword jmp adds 4 bytes to frag:
790 0 extra opcode bytes, 4 displacement bytes. */
792 /* word jmp adds 2 byte2 to frag:
793 0 extra opcode bytes, 2 displacement bytes. */
796 /* COND_JUMP states. */
797 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
798 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
799 /* dword conditionals adds 5 bytes to frag:
800 1 extra opcode byte, 4 displacement bytes. */
802 /* word conditionals add 3 bytes to frag:
803 1 extra opcode byte, 2 displacement bytes. */
806 /* COND_JUMP86 states. */
807 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
808 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
809 /* dword conditionals adds 5 bytes to frag:
810 1 extra opcode byte, 4 displacement bytes. */
812 /* word conditionals add 4 bytes to frag:
813 1 displacement byte and a 3 byte long branch insn. */
817 static const arch_entry cpu_arch
[] =
819 /* Do not replace the first two entries - i386_target_format()
820 relies on them being there in this order. */
821 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
822 CPU_GENERIC32_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
824 CPU_GENERIC64_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
833 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
835 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
837 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
841 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
842 CPU_PENTIUMPRO_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
845 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
847 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
849 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
851 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
852 CPU_NOCONA_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
855 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
857 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
858 CPU_CORE2_FLAGS
, 1 },
859 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
860 CPU_CORE2_FLAGS
, 0 },
861 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
862 CPU_COREI7_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
865 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
867 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
868 CPU_IAMCU_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
871 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
873 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
874 CPU_ATHLON_FLAGS
, 0 },
875 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
877 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
879 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
881 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
882 CPU_AMDFAM10_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
884 CPU_BDVER1_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
886 CPU_BDVER2_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
888 CPU_BDVER3_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
890 CPU_BDVER4_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
892 CPU_ZNVER1_FLAGS
, 0 },
893 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
894 CPU_ZNVER2_FLAGS
, 0 },
895 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
896 CPU_BTVER1_FLAGS
, 0 },
897 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
898 CPU_BTVER2_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
920 CPU_SSSE3_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4_1_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
924 CPU_SSE4_2_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
926 CPU_SSE4_2_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512F_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512CD_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512ER_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512PF_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
940 CPU_AVX512DQ_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
942 CPU_AVX512BW_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
944 CPU_AVX512VL_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
948 CPU_VMFUNC_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVE_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
954 CPU_XSAVEOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
956 CPU_XSAVEC_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
958 CPU_XSAVES_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
962 CPU_PCLMUL_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
964 CPU_PCLMUL_FLAGS
, 1 },
965 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
966 CPU_FSGSBASE_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
968 CPU_RDRND_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
982 CPU_MOVBE_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
988 CPU_LZCNT_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
994 CPU_INVPCID_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
996 CPU_CLFLUSH_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1000 CPU_SYSCALL_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1002 CPU_RDTSCP_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1004 CPU_3DNOW_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1006 CPU_3DNOWA_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1008 CPU_PADLOCK_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1010 CPU_SVME_FLAGS
, 1 },
1011 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1012 CPU_SVME_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4A_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1024 CPU_RDSEED_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1026 CPU_PRFCHW_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1028 CPU_SMAP_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1034 CPU_CLFLUSHOPT_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1036 CPU_PREFETCHWT1_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1040 CPU_CLWB_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512IFMA_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512VBMI_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512_VBMI2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512_VNNI_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512_BITALG_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1058 CPU_CLZERO_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1060 CPU_MWAITX_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1062 CPU_OSPKE_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1064 CPU_RDPID_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1066 CPU_PTWRITE_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1070 CPU_SHSTK_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1072 CPU_GFNI_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1074 CPU_VAES_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1076 CPU_VPCLMULQDQ_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1078 CPU_WBNOINVD_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1080 CPU_PCONFIG_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1082 CPU_WAITPKG_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1084 CPU_CLDEMOTE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1086 CPU_MOVDIRI_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1088 CPU_MOVDIR64B_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1090 CPU_AVX512_BF16_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1092 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1094 CPU_ENQCMD_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1096 CPU_RDPRU_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1098 CPU_MCOMMIT_FLAGS
, 0 },
1101 static const noarch_entry cpu_noarch
[] =
1103 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1104 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1105 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1106 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1107 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1108 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1109 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1110 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1113 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1114 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1115 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1116 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1133 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1134 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1135 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1136 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1137 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1138 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1139 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1140 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1144 /* Like s_lcomm_internal in gas/read.c but the alignment string
1145 is allowed to be optional. */
1148 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1155 && *input_line_pointer
== ',')
1157 align
= parse_align (needs_align
- 1);
1159 if (align
== (addressT
) -1)
1174 bss_alloc (symbolP
, size
, align
);
1179 pe_lcomm (int needs_align
)
1181 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1185 const pseudo_typeS md_pseudo_table
[] =
1187 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1188 {"align", s_align_bytes
, 0},
1190 {"align", s_align_ptwo
, 0},
1192 {"arch", set_cpu_arch
, 0},
1196 {"lcomm", pe_lcomm
, 1},
1198 {"ffloat", float_cons
, 'f'},
1199 {"dfloat", float_cons
, 'd'},
1200 {"tfloat", float_cons
, 'x'},
1202 {"slong", signed_cons
, 4},
1203 {"noopt", s_ignore
, 0},
1204 {"optim", s_ignore
, 0},
1205 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1206 {"code16", set_code_flag
, CODE_16BIT
},
1207 {"code32", set_code_flag
, CODE_32BIT
},
1209 {"code64", set_code_flag
, CODE_64BIT
},
1211 {"intel_syntax", set_intel_syntax
, 1},
1212 {"att_syntax", set_intel_syntax
, 0},
1213 {"intel_mnemonic", set_intel_mnemonic
, 1},
1214 {"att_mnemonic", set_intel_mnemonic
, 0},
1215 {"allow_index_reg", set_allow_index_reg
, 1},
1216 {"disallow_index_reg", set_allow_index_reg
, 0},
1217 {"sse_check", set_check
, 0},
1218 {"operand_check", set_check
, 1},
1219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1220 {"largecomm", handle_large_common
, 0},
1222 {"file", dwarf2_directive_file
, 0},
1223 {"loc", dwarf2_directive_loc
, 0},
1224 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1227 {"secrel32", pe_directive_secrel
, 0},
1232 /* For interface with expression (). */
1233 extern char *input_line_pointer
;
1235 /* Hash table for instruction mnemonic lookup. */
1236 static struct hash_control
*op_hash
;
1238 /* Hash table for register lookup. */
1239 static struct hash_control
*reg_hash
;
1241 /* Various efficient no-op patterns for aligning code labels.
1242 Note: Don't try to assemble the instructions in the comments.
1243 0L and 0w are not legal. */
1244 static const unsigned char f32_1
[] =
1246 static const unsigned char f32_2
[] =
1247 {0x66,0x90}; /* xchg %ax,%ax */
1248 static const unsigned char f32_3
[] =
1249 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1250 static const unsigned char f32_4
[] =
1251 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1252 static const unsigned char f32_6
[] =
1253 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1254 static const unsigned char f32_7
[] =
1255 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1256 static const unsigned char f16_3
[] =
1257 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1258 static const unsigned char f16_4
[] =
1259 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1260 static const unsigned char jump_disp8
[] =
1261 {0xeb}; /* jmp disp8 */
1262 static const unsigned char jump32_disp32
[] =
1263 {0xe9}; /* jmp disp32 */
1264 static const unsigned char jump16_disp32
[] =
1265 {0x66,0xe9}; /* jmp disp32 */
1266 /* 32-bit NOPs patterns. */
1267 static const unsigned char *const f32_patt
[] = {
1268 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1270 /* 16-bit NOPs patterns. */
1271 static const unsigned char *const f16_patt
[] = {
1272 f32_1
, f32_2
, f16_3
, f16_4
1274 /* nopl (%[re]ax) */
1275 static const unsigned char alt_3
[] =
1277 /* nopl 0(%[re]ax) */
1278 static const unsigned char alt_4
[] =
1279 {0x0f,0x1f,0x40,0x00};
1280 /* nopl 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_5
[] =
1282 {0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopw 0(%[re]ax,%[re]ax,1) */
1284 static const unsigned char alt_6
[] =
1285 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1286 /* nopl 0L(%[re]ax) */
1287 static const unsigned char alt_7
[] =
1288 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1289 /* nopl 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_8
[] =
1291 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw 0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_9
[] =
1294 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1296 static const unsigned char alt_10
[] =
1297 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* data16 nopw %cs:0L(%eax,%eax,1) */
1299 static const unsigned char alt_11
[] =
1300 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1301 /* 32-bit and 64-bit NOPs patterns. */
1302 static const unsigned char *const alt_patt
[] = {
1303 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1304 alt_9
, alt_10
, alt_11
1307 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1308 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1311 i386_output_nops (char *where
, const unsigned char *const *patt
,
1312 int count
, int max_single_nop_size
)
1315 /* Place the longer NOP first. */
1318 const unsigned char *nops
;
1320 if (max_single_nop_size
< 1)
1322 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1323 max_single_nop_size
);
1327 nops
= patt
[max_single_nop_size
- 1];
1329 /* Use the smaller one if the requsted one isn't available. */
1332 max_single_nop_size
--;
1333 nops
= patt
[max_single_nop_size
- 1];
1336 last
= count
% max_single_nop_size
;
1339 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1340 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1344 nops
= patt
[last
- 1];
1347 /* Use the smaller one plus one-byte NOP if the needed one
1350 nops
= patt
[last
- 1];
1351 memcpy (where
+ offset
, nops
, last
);
1352 where
[offset
+ last
] = *patt
[0];
1355 memcpy (where
+ offset
, nops
, last
);
1360 fits_in_imm7 (offsetT num
)
1362 return (num
& 0x7f) == num
;
1366 fits_in_imm31 (offsetT num
)
1368 return (num
& 0x7fffffff) == num
;
1371 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1372 single NOP instruction LIMIT. */
1375 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1377 const unsigned char *const *patt
= NULL
;
1378 int max_single_nop_size
;
1379 /* Maximum number of NOPs before switching to jump over NOPs. */
1380 int max_number_of_nops
;
1382 switch (fragP
->fr_type
)
1391 /* We need to decide which NOP sequence to use for 32bit and
1392 64bit. When -mtune= is used:
1394 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1395 PROCESSOR_GENERIC32, f32_patt will be used.
1396 2. For the rest, alt_patt will be used.
1398 When -mtune= isn't used, alt_patt will be used if
1399 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1402 When -march= or .arch is used, we can't use anything beyond
1403 cpu_arch_isa_flags. */
1405 if (flag_code
== CODE_16BIT
)
1408 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1409 /* Limit number of NOPs to 2 in 16-bit mode. */
1410 max_number_of_nops
= 2;
1414 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1416 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1417 switch (cpu_arch_tune
)
1419 case PROCESSOR_UNKNOWN
:
1420 /* We use cpu_arch_isa_flags to check if we SHOULD
1421 optimize with nops. */
1422 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1427 case PROCESSOR_PENTIUM4
:
1428 case PROCESSOR_NOCONA
:
1429 case PROCESSOR_CORE
:
1430 case PROCESSOR_CORE2
:
1431 case PROCESSOR_COREI7
:
1432 case PROCESSOR_L1OM
:
1433 case PROCESSOR_K1OM
:
1434 case PROCESSOR_GENERIC64
:
1436 case PROCESSOR_ATHLON
:
1438 case PROCESSOR_AMDFAM10
:
1440 case PROCESSOR_ZNVER
:
1444 case PROCESSOR_I386
:
1445 case PROCESSOR_I486
:
1446 case PROCESSOR_PENTIUM
:
1447 case PROCESSOR_PENTIUMPRO
:
1448 case PROCESSOR_IAMCU
:
1449 case PROCESSOR_GENERIC32
:
1456 switch (fragP
->tc_frag_data
.tune
)
1458 case PROCESSOR_UNKNOWN
:
1459 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1460 PROCESSOR_UNKNOWN. */
1464 case PROCESSOR_I386
:
1465 case PROCESSOR_I486
:
1466 case PROCESSOR_PENTIUM
:
1467 case PROCESSOR_IAMCU
:
1469 case PROCESSOR_ATHLON
:
1471 case PROCESSOR_AMDFAM10
:
1473 case PROCESSOR_ZNVER
:
1475 case PROCESSOR_GENERIC32
:
1476 /* We use cpu_arch_isa_flags to check if we CAN optimize
1478 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1483 case PROCESSOR_PENTIUMPRO
:
1484 case PROCESSOR_PENTIUM4
:
1485 case PROCESSOR_NOCONA
:
1486 case PROCESSOR_CORE
:
1487 case PROCESSOR_CORE2
:
1488 case PROCESSOR_COREI7
:
1489 case PROCESSOR_L1OM
:
1490 case PROCESSOR_K1OM
:
1491 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1496 case PROCESSOR_GENERIC64
:
1502 if (patt
== f32_patt
)
1504 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1505 /* Limit number of NOPs to 2 for older processors. */
1506 max_number_of_nops
= 2;
1510 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1511 /* Limit number of NOPs to 7 for newer processors. */
1512 max_number_of_nops
= 7;
1517 limit
= max_single_nop_size
;
1519 if (fragP
->fr_type
== rs_fill_nop
)
1521 /* Output NOPs for .nop directive. */
1522 if (limit
> max_single_nop_size
)
1524 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1525 _("invalid single nop size: %d "
1526 "(expect within [0, %d])"),
1527 limit
, max_single_nop_size
);
1532 fragP
->fr_var
= count
;
1534 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1536 /* Generate jump over NOPs. */
1537 offsetT disp
= count
- 2;
1538 if (fits_in_imm7 (disp
))
1540 /* Use "jmp disp8" if possible. */
1542 where
[0] = jump_disp8
[0];
1548 unsigned int size_of_jump
;
1550 if (flag_code
== CODE_16BIT
)
1552 where
[0] = jump16_disp32
[0];
1553 where
[1] = jump16_disp32
[1];
1558 where
[0] = jump32_disp32
[0];
1562 count
-= size_of_jump
+ 4;
1563 if (!fits_in_imm31 (count
))
1565 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1566 _("jump over nop padding out of range"));
1570 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1571 where
+= size_of_jump
+ 4;
1575 /* Generate multiple NOPs. */
1576 i386_output_nops (where
, patt
, count
, limit
);
1580 operand_type_all_zero (const union i386_operand_type
*x
)
1582 switch (ARRAY_SIZE(x
->array
))
1593 return !x
->array
[0];
1600 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1602 switch (ARRAY_SIZE(x
->array
))
1618 x
->bitfield
.class = ClassNone
;
1619 x
->bitfield
.instance
= InstanceNone
;
1623 operand_type_equal (const union i386_operand_type
*x
,
1624 const union i386_operand_type
*y
)
1626 switch (ARRAY_SIZE(x
->array
))
1629 if (x
->array
[2] != y
->array
[2])
1633 if (x
->array
[1] != y
->array
[1])
1637 return x
->array
[0] == y
->array
[0];
1645 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1647 switch (ARRAY_SIZE(x
->array
))
1662 return !x
->array
[0];
1669 cpu_flags_equal (const union i386_cpu_flags
*x
,
1670 const union i386_cpu_flags
*y
)
1672 switch (ARRAY_SIZE(x
->array
))
1675 if (x
->array
[3] != y
->array
[3])
1679 if (x
->array
[2] != y
->array
[2])
1683 if (x
->array
[1] != y
->array
[1])
1687 return x
->array
[0] == y
->array
[0];
1695 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1697 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1698 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1701 static INLINE i386_cpu_flags
1702 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1704 switch (ARRAY_SIZE (x
.array
))
1707 x
.array
[3] &= y
.array
[3];
1710 x
.array
[2] &= y
.array
[2];
1713 x
.array
[1] &= y
.array
[1];
1716 x
.array
[0] &= y
.array
[0];
1724 static INLINE i386_cpu_flags
1725 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1727 switch (ARRAY_SIZE (x
.array
))
1730 x
.array
[3] |= y
.array
[3];
1733 x
.array
[2] |= y
.array
[2];
1736 x
.array
[1] |= y
.array
[1];
1739 x
.array
[0] |= y
.array
[0];
1747 static INLINE i386_cpu_flags
1748 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1750 switch (ARRAY_SIZE (x
.array
))
1753 x
.array
[3] &= ~y
.array
[3];
1756 x
.array
[2] &= ~y
.array
[2];
1759 x
.array
[1] &= ~y
.array
[1];
1762 x
.array
[0] &= ~y
.array
[0];
1770 #define CPU_FLAGS_ARCH_MATCH 0x1
1771 #define CPU_FLAGS_64BIT_MATCH 0x2
1773 #define CPU_FLAGS_PERFECT_MATCH \
1774 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1776 /* Return CPU flags match bits. */
1779 cpu_flags_match (const insn_template
*t
)
1781 i386_cpu_flags x
= t
->cpu_flags
;
1782 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1784 x
.bitfield
.cpu64
= 0;
1785 x
.bitfield
.cpuno64
= 0;
1787 if (cpu_flags_all_zero (&x
))
1789 /* This instruction is available on all archs. */
1790 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 /* This instruction is available only on some archs. */
1795 i386_cpu_flags cpu
= cpu_arch_flags
;
1797 /* AVX512VL is no standalone feature - match it and then strip it. */
1798 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1800 x
.bitfield
.cpuavx512vl
= 0;
1802 cpu
= cpu_flags_and (x
, cpu
);
1803 if (!cpu_flags_all_zero (&cpu
))
1805 if (x
.bitfield
.cpuavx
)
1807 /* We need to check a few extra flags with AVX. */
1808 if (cpu
.bitfield
.cpuavx
1809 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1810 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1811 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1812 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1813 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 else if (x
.bitfield
.cpuavx512f
)
1817 /* We need to check a few extra flags with AVX512F. */
1818 if (cpu
.bitfield
.cpuavx512f
1819 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1820 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1821 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1822 match
|= CPU_FLAGS_ARCH_MATCH
;
1825 match
|= CPU_FLAGS_ARCH_MATCH
;
1831 static INLINE i386_operand_type
1832 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1834 if (x
.bitfield
.class != y
.bitfield
.class)
1835 x
.bitfield
.class = ClassNone
;
1836 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1837 x
.bitfield
.instance
= InstanceNone
;
1839 switch (ARRAY_SIZE (x
.array
))
1842 x
.array
[2] &= y
.array
[2];
1845 x
.array
[1] &= y
.array
[1];
1848 x
.array
[0] &= y
.array
[0];
1856 static INLINE i386_operand_type
1857 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1859 gas_assert (y
.bitfield
.class == ClassNone
);
1860 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1862 switch (ARRAY_SIZE (x
.array
))
1865 x
.array
[2] &= ~y
.array
[2];
1868 x
.array
[1] &= ~y
.array
[1];
1871 x
.array
[0] &= ~y
.array
[0];
1879 static INLINE i386_operand_type
1880 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1882 gas_assert (x
.bitfield
.class == ClassNone
||
1883 y
.bitfield
.class == ClassNone
||
1884 x
.bitfield
.class == y
.bitfield
.class);
1885 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1886 y
.bitfield
.instance
== InstanceNone
||
1887 x
.bitfield
.instance
== y
.bitfield
.instance
);
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[2] |= y
.array
[2];
1895 x
.array
[1] |= y
.array
[1];
1898 x
.array
[0] |= y
.array
[0];
1906 static INLINE i386_operand_type
1907 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1909 gas_assert (y
.bitfield
.class == ClassNone
);
1910 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[2] ^= y
.array
[2];
1918 x
.array
[1] ^= y
.array
[1];
1921 x
.array
[0] ^= y
.array
[0];
1929 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1930 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1931 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1932 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1933 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
1934 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
1935 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1936 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1937 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1938 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1939 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1940 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1941 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1942 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1943 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1944 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1945 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1956 operand_type_check (i386_operand_type t
, enum operand_type c
)
1961 return t
.bitfield
.class == Reg
;
1964 return (t
.bitfield
.imm8
1968 || t
.bitfield
.imm32s
1969 || t
.bitfield
.imm64
);
1972 return (t
.bitfield
.disp8
1973 || t
.bitfield
.disp16
1974 || t
.bitfield
.disp32
1975 || t
.bitfield
.disp32s
1976 || t
.bitfield
.disp64
);
1979 return (t
.bitfield
.disp8
1980 || t
.bitfield
.disp16
1981 || t
.bitfield
.disp32
1982 || t
.bitfield
.disp32s
1983 || t
.bitfield
.disp64
1984 || t
.bitfield
.baseindex
);
1993 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1994 between operand GIVEN and opeand WANTED for instruction template T. */
1997 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2000 return !((i
.types
[given
].bitfield
.byte
2001 && !t
->operand_types
[wanted
].bitfield
.byte
)
2002 || (i
.types
[given
].bitfield
.word
2003 && !t
->operand_types
[wanted
].bitfield
.word
)
2004 || (i
.types
[given
].bitfield
.dword
2005 && !t
->operand_types
[wanted
].bitfield
.dword
)
2006 || (i
.types
[given
].bitfield
.qword
2007 && !t
->operand_types
[wanted
].bitfield
.qword
)
2008 || (i
.types
[given
].bitfield
.tbyte
2009 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2012 /* Return 1 if there is no conflict in SIMD register between operand
2013 GIVEN and opeand WANTED for instruction template T. */
2016 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2019 return !((i
.types
[given
].bitfield
.xmmword
2020 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2021 || (i
.types
[given
].bitfield
.ymmword
2022 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2023 || (i
.types
[given
].bitfield
.zmmword
2024 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2027 /* Return 1 if there is no conflict in any size between operand GIVEN
2028 and opeand WANTED for instruction template T. */
2031 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2034 return (match_operand_size (t
, wanted
, given
)
2035 && !((i
.types
[given
].bitfield
.unspecified
2037 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2038 || (i
.types
[given
].bitfield
.fword
2039 && !t
->operand_types
[wanted
].bitfield
.fword
)
2040 /* For scalar opcode templates to allow register and memory
2041 operands at the same time, some special casing is needed
2042 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2043 down-conversion vpmov*. */
2044 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2045 && !t
->opcode_modifier
.broadcast
2046 && (t
->operand_types
[wanted
].bitfield
.byte
2047 || t
->operand_types
[wanted
].bitfield
.word
2048 || t
->operand_types
[wanted
].bitfield
.dword
2049 || t
->operand_types
[wanted
].bitfield
.qword
))
2050 ? (i
.types
[given
].bitfield
.xmmword
2051 || i
.types
[given
].bitfield
.ymmword
2052 || i
.types
[given
].bitfield
.zmmword
)
2053 : !match_simd_size(t
, wanted
, given
))));
2056 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2057 operands for instruction template T, and it has MATCH_REVERSE set if there
2058 is no size conflict on any operands for the template with operands reversed
2059 (and the template allows for reversing in the first place). */
2061 #define MATCH_STRAIGHT 1
2062 #define MATCH_REVERSE 2
2064 static INLINE
unsigned int
2065 operand_size_match (const insn_template
*t
)
2067 unsigned int j
, match
= MATCH_STRAIGHT
;
2069 /* Don't check non-absolute jump instructions. */
2070 if (t
->opcode_modifier
.jump
2071 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2074 /* Check memory and accumulator operand size. */
2075 for (j
= 0; j
< i
.operands
; j
++)
2077 if (i
.types
[j
].bitfield
.class != Reg
2078 && i
.types
[j
].bitfield
.class != RegSIMD
2079 && t
->opcode_modifier
.anysize
)
2082 if (t
->operand_types
[j
].bitfield
.class == Reg
2083 && !match_operand_size (t
, j
, j
))
2089 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2090 && !match_simd_size (t
, j
, j
))
2096 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2097 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2103 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2110 if (!t
->opcode_modifier
.d
)
2114 i
.error
= operand_size_mismatch
;
2118 /* Check reverse. */
2119 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2121 for (j
= 0; j
< i
.operands
; j
++)
2123 unsigned int given
= i
.operands
- j
- 1;
2125 if (t
->operand_types
[j
].bitfield
.class == Reg
2126 && !match_operand_size (t
, j
, given
))
2129 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2130 && !match_simd_size (t
, j
, given
))
2133 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2134 && (!match_operand_size (t
, j
, given
)
2135 || !match_simd_size (t
, j
, given
)))
2138 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2142 return match
| MATCH_REVERSE
;
2146 operand_type_match (i386_operand_type overlap
,
2147 i386_operand_type given
)
2149 i386_operand_type temp
= overlap
;
2151 temp
.bitfield
.unspecified
= 0;
2152 temp
.bitfield
.byte
= 0;
2153 temp
.bitfield
.word
= 0;
2154 temp
.bitfield
.dword
= 0;
2155 temp
.bitfield
.fword
= 0;
2156 temp
.bitfield
.qword
= 0;
2157 temp
.bitfield
.tbyte
= 0;
2158 temp
.bitfield
.xmmword
= 0;
2159 temp
.bitfield
.ymmword
= 0;
2160 temp
.bitfield
.zmmword
= 0;
2161 if (operand_type_all_zero (&temp
))
2164 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2168 i
.error
= operand_type_mismatch
;
2172 /* If given types g0 and g1 are registers they must be of the same type
2173 unless the expected operand type register overlap is null.
2174 Memory operand size of certain SIMD instructions is also being checked
2178 operand_type_register_match (i386_operand_type g0
,
2179 i386_operand_type t0
,
2180 i386_operand_type g1
,
2181 i386_operand_type t1
)
2183 if (g0
.bitfield
.class != Reg
2184 && g0
.bitfield
.class != RegSIMD
2185 && (!operand_type_check (g0
, anymem
)
2186 || g0
.bitfield
.unspecified
2187 || t0
.bitfield
.class != RegSIMD
))
2190 if (g1
.bitfield
.class != Reg
2191 && g1
.bitfield
.class != RegSIMD
2192 && (!operand_type_check (g1
, anymem
)
2193 || g1
.bitfield
.unspecified
2194 || t1
.bitfield
.class != RegSIMD
))
2197 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2198 && g0
.bitfield
.word
== g1
.bitfield
.word
2199 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2200 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2201 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2202 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2203 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2206 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2207 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2208 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2209 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2210 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2211 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2212 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2215 i
.error
= register_type_mismatch
;
2220 static INLINE
unsigned int
2221 register_number (const reg_entry
*r
)
2223 unsigned int nr
= r
->reg_num
;
2225 if (r
->reg_flags
& RegRex
)
2228 if (r
->reg_flags
& RegVRex
)
2234 static INLINE
unsigned int
2235 mode_from_disp_size (i386_operand_type t
)
2237 if (t
.bitfield
.disp8
)
2239 else if (t
.bitfield
.disp16
2240 || t
.bitfield
.disp32
2241 || t
.bitfield
.disp32s
)
2248 fits_in_signed_byte (addressT num
)
2250 return num
+ 0x80 <= 0xff;
2254 fits_in_unsigned_byte (addressT num
)
2260 fits_in_unsigned_word (addressT num
)
2262 return num
<= 0xffff;
2266 fits_in_signed_word (addressT num
)
2268 return num
+ 0x8000 <= 0xffff;
2272 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2277 return num
+ 0x80000000 <= 0xffffffff;
2279 } /* fits_in_signed_long() */
2282 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2287 return num
<= 0xffffffff;
2289 } /* fits_in_unsigned_long() */
2292 fits_in_disp8 (offsetT num
)
2294 int shift
= i
.memshift
;
2300 mask
= (1 << shift
) - 1;
2302 /* Return 0 if NUM isn't properly aligned. */
2306 /* Check if NUM will fit in 8bit after shift. */
2307 return fits_in_signed_byte (num
>> shift
);
2311 fits_in_imm4 (offsetT num
)
2313 return (num
& 0xf) == num
;
2316 static i386_operand_type
2317 smallest_imm_type (offsetT num
)
2319 i386_operand_type t
;
2321 operand_type_set (&t
, 0);
2322 t
.bitfield
.imm64
= 1;
2324 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2326 /* This code is disabled on the 486 because all the Imm1 forms
2327 in the opcode table are slower on the i486. They're the
2328 versions with the implicitly specified single-position
2329 displacement, which has another syntax if you really want to
2331 t
.bitfield
.imm1
= 1;
2332 t
.bitfield
.imm8
= 1;
2333 t
.bitfield
.imm8s
= 1;
2334 t
.bitfield
.imm16
= 1;
2335 t
.bitfield
.imm32
= 1;
2336 t
.bitfield
.imm32s
= 1;
2338 else if (fits_in_signed_byte (num
))
2340 t
.bitfield
.imm8
= 1;
2341 t
.bitfield
.imm8s
= 1;
2342 t
.bitfield
.imm16
= 1;
2343 t
.bitfield
.imm32
= 1;
2344 t
.bitfield
.imm32s
= 1;
2346 else if (fits_in_unsigned_byte (num
))
2348 t
.bitfield
.imm8
= 1;
2349 t
.bitfield
.imm16
= 1;
2350 t
.bitfield
.imm32
= 1;
2351 t
.bitfield
.imm32s
= 1;
2353 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2355 t
.bitfield
.imm16
= 1;
2356 t
.bitfield
.imm32
= 1;
2357 t
.bitfield
.imm32s
= 1;
2359 else if (fits_in_signed_long (num
))
2361 t
.bitfield
.imm32
= 1;
2362 t
.bitfield
.imm32s
= 1;
2364 else if (fits_in_unsigned_long (num
))
2365 t
.bitfield
.imm32
= 1;
2371 offset_in_range (offsetT val
, int size
)
2377 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2378 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2379 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2381 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2387 /* If BFD64, sign extend val for 32bit address mode. */
2388 if (flag_code
!= CODE_64BIT
2389 || i
.prefix
[ADDR_PREFIX
])
2390 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2391 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2394 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2396 char buf1
[40], buf2
[40];
2398 sprint_value (buf1
, val
);
2399 sprint_value (buf2
, val
& mask
);
2400 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2415 a. PREFIX_EXIST if attempting to add a prefix where one from the
2416 same class already exists.
2417 b. PREFIX_LOCK if lock prefix is added.
2418 c. PREFIX_REP if rep/repne prefix is added.
2419 d. PREFIX_DS if ds prefix is added.
2420 e. PREFIX_OTHER if other prefix is added.
2423 static enum PREFIX_GROUP
2424 add_prefix (unsigned int prefix
)
2426 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2429 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2430 && flag_code
== CODE_64BIT
)
2432 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2433 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2434 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2435 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2446 case DS_PREFIX_OPCODE
:
2449 case CS_PREFIX_OPCODE
:
2450 case ES_PREFIX_OPCODE
:
2451 case FS_PREFIX_OPCODE
:
2452 case GS_PREFIX_OPCODE
:
2453 case SS_PREFIX_OPCODE
:
2457 case REPNE_PREFIX_OPCODE
:
2458 case REPE_PREFIX_OPCODE
:
2463 case LOCK_PREFIX_OPCODE
:
2472 case ADDR_PREFIX_OPCODE
:
2476 case DATA_PREFIX_OPCODE
:
2480 if (i
.prefix
[q
] != 0)
2488 i
.prefix
[q
] |= prefix
;
2491 as_bad (_("same type of prefix used twice"));
2497 update_code_flag (int value
, int check
)
2499 PRINTF_LIKE ((*as_error
));
2501 flag_code
= (enum flag_code
) value
;
2502 if (flag_code
== CODE_64BIT
)
2504 cpu_arch_flags
.bitfield
.cpu64
= 1;
2505 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2509 cpu_arch_flags
.bitfield
.cpu64
= 0;
2510 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2512 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2515 as_error
= as_fatal
;
2518 (*as_error
) (_("64bit mode not supported on `%s'."),
2519 cpu_arch_name
? cpu_arch_name
: default_arch
);
2521 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2524 as_error
= as_fatal
;
2527 (*as_error
) (_("32bit mode not supported on `%s'."),
2528 cpu_arch_name
? cpu_arch_name
: default_arch
);
2530 stackop_size
= '\0';
2534 set_code_flag (int value
)
2536 update_code_flag (value
, 0);
2540 set_16bit_gcc_code_flag (int new_code_flag
)
2542 flag_code
= (enum flag_code
) new_code_flag
;
2543 if (flag_code
!= CODE_16BIT
)
2545 cpu_arch_flags
.bitfield
.cpu64
= 0;
2546 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2547 stackop_size
= LONG_MNEM_SUFFIX
;
2551 set_intel_syntax (int syntax_flag
)
2553 /* Find out if register prefixing is specified. */
2554 int ask_naked_reg
= 0;
2557 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2560 int e
= get_symbol_name (&string
);
2562 if (strcmp (string
, "prefix") == 0)
2564 else if (strcmp (string
, "noprefix") == 0)
2567 as_bad (_("bad argument to syntax directive."));
2568 (void) restore_line_pointer (e
);
2570 demand_empty_rest_of_line ();
2572 intel_syntax
= syntax_flag
;
2574 if (ask_naked_reg
== 0)
2575 allow_naked_reg
= (intel_syntax
2576 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2578 allow_naked_reg
= (ask_naked_reg
< 0);
2580 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2582 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2583 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2584 register_prefix
= allow_naked_reg
? "" : "%";
2588 set_intel_mnemonic (int mnemonic_flag
)
2590 intel_mnemonic
= mnemonic_flag
;
2594 set_allow_index_reg (int flag
)
2596 allow_index_reg
= flag
;
2600 set_check (int what
)
2602 enum check_kind
*kind
;
2607 kind
= &operand_check
;
2618 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2621 int e
= get_symbol_name (&string
);
2623 if (strcmp (string
, "none") == 0)
2625 else if (strcmp (string
, "warning") == 0)
2626 *kind
= check_warning
;
2627 else if (strcmp (string
, "error") == 0)
2628 *kind
= check_error
;
2630 as_bad (_("bad argument to %s_check directive."), str
);
2631 (void) restore_line_pointer (e
);
2634 as_bad (_("missing argument for %s_check directive"), str
);
2636 demand_empty_rest_of_line ();
2640 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2641 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2644 static const char *arch
;
2646 /* Intel LIOM is only supported on ELF. */
2652 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2653 use default_arch. */
2654 arch
= cpu_arch_name
;
2656 arch
= default_arch
;
2659 /* If we are targeting Intel MCU, we must enable it. */
2660 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2661 || new_flag
.bitfield
.cpuiamcu
)
2664 /* If we are targeting Intel L1OM, we must enable it. */
2665 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2666 || new_flag
.bitfield
.cpul1om
)
2669 /* If we are targeting Intel K1OM, we must enable it. */
2670 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2671 || new_flag
.bitfield
.cpuk1om
)
2674 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2679 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2683 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2686 int e
= get_symbol_name (&string
);
2688 i386_cpu_flags flags
;
2690 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2692 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2694 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2698 cpu_arch_name
= cpu_arch
[j
].name
;
2699 cpu_sub_arch_name
= NULL
;
2700 cpu_arch_flags
= cpu_arch
[j
].flags
;
2701 if (flag_code
== CODE_64BIT
)
2703 cpu_arch_flags
.bitfield
.cpu64
= 1;
2704 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2708 cpu_arch_flags
.bitfield
.cpu64
= 0;
2709 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2711 cpu_arch_isa
= cpu_arch
[j
].type
;
2712 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2713 if (!cpu_arch_tune_set
)
2715 cpu_arch_tune
= cpu_arch_isa
;
2716 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2721 flags
= cpu_flags_or (cpu_arch_flags
,
2724 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2726 if (cpu_sub_arch_name
)
2728 char *name
= cpu_sub_arch_name
;
2729 cpu_sub_arch_name
= concat (name
,
2731 (const char *) NULL
);
2735 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2736 cpu_arch_flags
= flags
;
2737 cpu_arch_isa_flags
= flags
;
2741 = cpu_flags_or (cpu_arch_isa_flags
,
2743 (void) restore_line_pointer (e
);
2744 demand_empty_rest_of_line ();
2749 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2751 /* Disable an ISA extension. */
2752 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2753 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2755 flags
= cpu_flags_and_not (cpu_arch_flags
,
2756 cpu_noarch
[j
].flags
);
2757 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2759 if (cpu_sub_arch_name
)
2761 char *name
= cpu_sub_arch_name
;
2762 cpu_sub_arch_name
= concat (name
, string
,
2763 (const char *) NULL
);
2767 cpu_sub_arch_name
= xstrdup (string
);
2768 cpu_arch_flags
= flags
;
2769 cpu_arch_isa_flags
= flags
;
2771 (void) restore_line_pointer (e
);
2772 demand_empty_rest_of_line ();
2776 j
= ARRAY_SIZE (cpu_arch
);
2779 if (j
>= ARRAY_SIZE (cpu_arch
))
2780 as_bad (_("no such architecture: `%s'"), string
);
2782 *input_line_pointer
= e
;
2785 as_bad (_("missing cpu architecture"));
2787 no_cond_jump_promotion
= 0;
2788 if (*input_line_pointer
== ','
2789 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2794 ++input_line_pointer
;
2795 e
= get_symbol_name (&string
);
2797 if (strcmp (string
, "nojumps") == 0)
2798 no_cond_jump_promotion
= 1;
2799 else if (strcmp (string
, "jumps") == 0)
2802 as_bad (_("no such architecture modifier: `%s'"), string
);
2804 (void) restore_line_pointer (e
);
2807 demand_empty_rest_of_line ();
2810 enum bfd_architecture
2813 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2815 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2816 || flag_code
!= CODE_64BIT
)
2817 as_fatal (_("Intel L1OM is 64bit ELF only"));
2818 return bfd_arch_l1om
;
2820 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2822 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2823 || flag_code
!= CODE_64BIT
)
2824 as_fatal (_("Intel K1OM is 64bit ELF only"));
2825 return bfd_arch_k1om
;
2827 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2829 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2830 || flag_code
== CODE_64BIT
)
2831 as_fatal (_("Intel MCU is 32bit ELF only"));
2832 return bfd_arch_iamcu
;
2835 return bfd_arch_i386
;
2841 if (!strncmp (default_arch
, "x86_64", 6))
2843 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2845 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2846 || default_arch
[6] != '\0')
2847 as_fatal (_("Intel L1OM is 64bit ELF only"));
2848 return bfd_mach_l1om
;
2850 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2852 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2853 || default_arch
[6] != '\0')
2854 as_fatal (_("Intel K1OM is 64bit ELF only"));
2855 return bfd_mach_k1om
;
2857 else if (default_arch
[6] == '\0')
2858 return bfd_mach_x86_64
;
2860 return bfd_mach_x64_32
;
2862 else if (!strcmp (default_arch
, "i386")
2863 || !strcmp (default_arch
, "iamcu"))
2865 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2867 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2868 as_fatal (_("Intel MCU is 32bit ELF only"));
2869 return bfd_mach_i386_iamcu
;
2872 return bfd_mach_i386_i386
;
2875 as_fatal (_("unknown architecture"));
2881 const char *hash_err
;
2883 /* Support pseudo prefixes like {disp32}. */
2884 lex_type
['{'] = LEX_BEGIN_NAME
;
2886 /* Initialize op_hash hash table. */
2887 op_hash
= hash_new ();
2890 const insn_template
*optab
;
2891 templates
*core_optab
;
2893 /* Setup for loop. */
2895 core_optab
= XNEW (templates
);
2896 core_optab
->start
= optab
;
2901 if (optab
->name
== NULL
2902 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2904 /* different name --> ship out current template list;
2905 add to hash table; & begin anew. */
2906 core_optab
->end
= optab
;
2907 hash_err
= hash_insert (op_hash
,
2909 (void *) core_optab
);
2912 as_fatal (_("can't hash %s: %s"),
2916 if (optab
->name
== NULL
)
2918 core_optab
= XNEW (templates
);
2919 core_optab
->start
= optab
;
2924 /* Initialize reg_hash hash table. */
2925 reg_hash
= hash_new ();
2927 const reg_entry
*regtab
;
2928 unsigned int regtab_size
= i386_regtab_size
;
2930 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2932 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2934 as_fatal (_("can't hash %s: %s"),
2940 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2945 for (c
= 0; c
< 256; c
++)
2950 mnemonic_chars
[c
] = c
;
2951 register_chars
[c
] = c
;
2952 operand_chars
[c
] = c
;
2954 else if (ISLOWER (c
))
2956 mnemonic_chars
[c
] = c
;
2957 register_chars
[c
] = c
;
2958 operand_chars
[c
] = c
;
2960 else if (ISUPPER (c
))
2962 mnemonic_chars
[c
] = TOLOWER (c
);
2963 register_chars
[c
] = mnemonic_chars
[c
];
2964 operand_chars
[c
] = c
;
2966 else if (c
== '{' || c
== '}')
2968 mnemonic_chars
[c
] = c
;
2969 operand_chars
[c
] = c
;
2972 if (ISALPHA (c
) || ISDIGIT (c
))
2973 identifier_chars
[c
] = c
;
2976 identifier_chars
[c
] = c
;
2977 operand_chars
[c
] = c
;
2982 identifier_chars
['@'] = '@';
2985 identifier_chars
['?'] = '?';
2986 operand_chars
['?'] = '?';
2988 digit_chars
['-'] = '-';
2989 mnemonic_chars
['_'] = '_';
2990 mnemonic_chars
['-'] = '-';
2991 mnemonic_chars
['.'] = '.';
2992 identifier_chars
['_'] = '_';
2993 identifier_chars
['.'] = '.';
2995 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2996 operand_chars
[(unsigned char) *p
] = *p
;
2999 if (flag_code
== CODE_64BIT
)
3001 #if defined (OBJ_COFF) && defined (TE_PE)
3002 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3005 x86_dwarf2_return_column
= 16;
3007 x86_cie_data_alignment
= -8;
3011 x86_dwarf2_return_column
= 8;
3012 x86_cie_data_alignment
= -4;
3017 i386_print_statistics (FILE *file
)
3019 hash_print_statistics (file
, "i386 opcode", op_hash
);
3020 hash_print_statistics (file
, "i386 register", reg_hash
);
3025 /* Debugging routines for md_assemble. */
3026 static void pte (insn_template
*);
3027 static void pt (i386_operand_type
);
3028 static void pe (expressionS
*);
3029 static void ps (symbolS
*);
3032 pi (const char *line
, i386_insn
*x
)
3036 fprintf (stdout
, "%s: template ", line
);
3038 fprintf (stdout
, " address: base %s index %s scale %x\n",
3039 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3040 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3041 x
->log2_scale_factor
);
3042 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3043 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3044 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3045 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3046 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3047 (x
->rex
& REX_W
) != 0,
3048 (x
->rex
& REX_R
) != 0,
3049 (x
->rex
& REX_X
) != 0,
3050 (x
->rex
& REX_B
) != 0);
3051 for (j
= 0; j
< x
->operands
; j
++)
3053 fprintf (stdout
, " #%d: ", j
+ 1);
3055 fprintf (stdout
, "\n");
3056 if (x
->types
[j
].bitfield
.class == Reg
3057 || x
->types
[j
].bitfield
.class == RegMMX
3058 || x
->types
[j
].bitfield
.class == RegSIMD
3059 || x
->types
[j
].bitfield
.class == SReg
3060 || x
->types
[j
].bitfield
.class == RegCR
3061 || x
->types
[j
].bitfield
.class == RegDR
3062 || x
->types
[j
].bitfield
.class == RegTR
)
3063 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3064 if (operand_type_check (x
->types
[j
], imm
))
3066 if (operand_type_check (x
->types
[j
], disp
))
3067 pe (x
->op
[j
].disps
);
3072 pte (insn_template
*t
)
3075 fprintf (stdout
, " %d operands ", t
->operands
);
3076 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3077 if (t
->extension_opcode
!= None
)
3078 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3079 if (t
->opcode_modifier
.d
)
3080 fprintf (stdout
, "D");
3081 if (t
->opcode_modifier
.w
)
3082 fprintf (stdout
, "W");
3083 fprintf (stdout
, "\n");
3084 for (j
= 0; j
< t
->operands
; j
++)
3086 fprintf (stdout
, " #%d type ", j
+ 1);
3087 pt (t
->operand_types
[j
]);
3088 fprintf (stdout
, "\n");
3095 fprintf (stdout
, " operation %d\n", e
->X_op
);
3096 fprintf (stdout
, " add_number %ld (%lx)\n",
3097 (long) e
->X_add_number
, (long) e
->X_add_number
);
3098 if (e
->X_add_symbol
)
3100 fprintf (stdout
, " add_symbol ");
3101 ps (e
->X_add_symbol
);
3102 fprintf (stdout
, "\n");
3106 fprintf (stdout
, " op_symbol ");
3107 ps (e
->X_op_symbol
);
3108 fprintf (stdout
, "\n");
3115 fprintf (stdout
, "%s type %s%s",
3117 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3118 segment_name (S_GET_SEGMENT (s
)));
3121 static struct type_name
3123 i386_operand_type mask
;
3126 const type_names
[] =
3128 { OPERAND_TYPE_REG8
, "r8" },
3129 { OPERAND_TYPE_REG16
, "r16" },
3130 { OPERAND_TYPE_REG32
, "r32" },
3131 { OPERAND_TYPE_REG64
, "r64" },
3132 { OPERAND_TYPE_ACC8
, "acc8" },
3133 { OPERAND_TYPE_ACC16
, "acc16" },
3134 { OPERAND_TYPE_ACC32
, "acc32" },
3135 { OPERAND_TYPE_ACC64
, "acc64" },
3136 { OPERAND_TYPE_IMM8
, "i8" },
3137 { OPERAND_TYPE_IMM8
, "i8s" },
3138 { OPERAND_TYPE_IMM16
, "i16" },
3139 { OPERAND_TYPE_IMM32
, "i32" },
3140 { OPERAND_TYPE_IMM32S
, "i32s" },
3141 { OPERAND_TYPE_IMM64
, "i64" },
3142 { OPERAND_TYPE_IMM1
, "i1" },
3143 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3144 { OPERAND_TYPE_DISP8
, "d8" },
3145 { OPERAND_TYPE_DISP16
, "d16" },
3146 { OPERAND_TYPE_DISP32
, "d32" },
3147 { OPERAND_TYPE_DISP32S
, "d32s" },
3148 { OPERAND_TYPE_DISP64
, "d64" },
3149 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3150 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3151 { OPERAND_TYPE_CONTROL
, "control reg" },
3152 { OPERAND_TYPE_TEST
, "test reg" },
3153 { OPERAND_TYPE_DEBUG
, "debug reg" },
3154 { OPERAND_TYPE_FLOATREG
, "FReg" },
3155 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3156 { OPERAND_TYPE_SREG
, "SReg" },
3157 { OPERAND_TYPE_REGMMX
, "rMMX" },
3158 { OPERAND_TYPE_REGXMM
, "rXMM" },
3159 { OPERAND_TYPE_REGYMM
, "rYMM" },
3160 { OPERAND_TYPE_REGZMM
, "rZMM" },
3161 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3165 pt (i386_operand_type t
)
3168 i386_operand_type a
;
3170 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3172 a
= operand_type_and (t
, type_names
[j
].mask
);
3173 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3174 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3179 #endif /* DEBUG386 */
3181 static bfd_reloc_code_real_type
3182 reloc (unsigned int size
,
3185 bfd_reloc_code_real_type other
)
3187 if (other
!= NO_RELOC
)
3189 reloc_howto_type
*rel
;
3194 case BFD_RELOC_X86_64_GOT32
:
3195 return BFD_RELOC_X86_64_GOT64
;
3197 case BFD_RELOC_X86_64_GOTPLT64
:
3198 return BFD_RELOC_X86_64_GOTPLT64
;
3200 case BFD_RELOC_X86_64_PLTOFF64
:
3201 return BFD_RELOC_X86_64_PLTOFF64
;
3203 case BFD_RELOC_X86_64_GOTPC32
:
3204 other
= BFD_RELOC_X86_64_GOTPC64
;
3206 case BFD_RELOC_X86_64_GOTPCREL
:
3207 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3209 case BFD_RELOC_X86_64_TPOFF32
:
3210 other
= BFD_RELOC_X86_64_TPOFF64
;
3212 case BFD_RELOC_X86_64_DTPOFF32
:
3213 other
= BFD_RELOC_X86_64_DTPOFF64
;
3219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3220 if (other
== BFD_RELOC_SIZE32
)
3223 other
= BFD_RELOC_SIZE64
;
3226 as_bad (_("there are no pc-relative size relocations"));
3232 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3233 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3236 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3238 as_bad (_("unknown relocation (%u)"), other
);
3239 else if (size
!= bfd_get_reloc_size (rel
))
3240 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3241 bfd_get_reloc_size (rel
),
3243 else if (pcrel
&& !rel
->pc_relative
)
3244 as_bad (_("non-pc-relative relocation for pc-relative field"));
3245 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3247 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3249 as_bad (_("relocated field and relocation type differ in signedness"));
3258 as_bad (_("there are no unsigned pc-relative relocations"));
3261 case 1: return BFD_RELOC_8_PCREL
;
3262 case 2: return BFD_RELOC_16_PCREL
;
3263 case 4: return BFD_RELOC_32_PCREL
;
3264 case 8: return BFD_RELOC_64_PCREL
;
3266 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3273 case 4: return BFD_RELOC_X86_64_32S
;
3278 case 1: return BFD_RELOC_8
;
3279 case 2: return BFD_RELOC_16
;
3280 case 4: return BFD_RELOC_32
;
3281 case 8: return BFD_RELOC_64
;
3283 as_bad (_("cannot do %s %u byte relocation"),
3284 sign
> 0 ? "signed" : "unsigned", size
);
3290 /* Here we decide which fixups can be adjusted to make them relative to
3291 the beginning of the section instead of the symbol. Basically we need
3292 to make sure that the dynamic relocations are done correctly, so in
3293 some cases we force the original symbol to be used. */
3296 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3302 /* Don't adjust pc-relative references to merge sections in 64-bit
3304 if (use_rela_relocations
3305 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3309 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3310 and changed later by validate_fix. */
3311 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3312 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3315 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3316 for size relocations. */
3317 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3318 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3319 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3321 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3322 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3328 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3329 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3330 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3331 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3332 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3343 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3344 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3345 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3346 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3347 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3348 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3349 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3356 intel_float_operand (const char *mnemonic
)
3358 /* Note that the value returned is meaningful only for opcodes with (memory)
3359 operands, hence the code here is free to improperly handle opcodes that
3360 have no operands (for better performance and smaller code). */
3362 if (mnemonic
[0] != 'f')
3363 return 0; /* non-math */
3365 switch (mnemonic
[1])
3367 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3368 the fs segment override prefix not currently handled because no
3369 call path can make opcodes without operands get here */
3371 return 2 /* integer op */;
3373 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3374 return 3; /* fldcw/fldenv */
3377 if (mnemonic
[2] != 'o' /* fnop */)
3378 return 3; /* non-waiting control op */
3381 if (mnemonic
[2] == 's')
3382 return 3; /* frstor/frstpm */
3385 if (mnemonic
[2] == 'a')
3386 return 3; /* fsave */
3387 if (mnemonic
[2] == 't')
3389 switch (mnemonic
[3])
3391 case 'c': /* fstcw */
3392 case 'd': /* fstdw */
3393 case 'e': /* fstenv */
3394 case 's': /* fsts[gw] */
3400 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3401 return 0; /* fxsave/fxrstor are not really math ops */
3408 /* Build the VEX prefix. */
3411 build_vex_prefix (const insn_template
*t
)
3413 unsigned int register_specifier
;
3414 unsigned int implied_prefix
;
3415 unsigned int vector_length
;
3418 /* Check register specifier. */
3419 if (i
.vex
.register_specifier
)
3421 register_specifier
=
3422 ~register_number (i
.vex
.register_specifier
) & 0xf;
3423 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3426 register_specifier
= 0xf;
3428 /* Use 2-byte VEX prefix by swapping destination and source operand
3429 if there are more than 1 register operand. */
3430 if (i
.reg_operands
> 1
3431 && i
.vec_encoding
!= vex_encoding_vex3
3432 && i
.dir_encoding
== dir_encoding_default
3433 && i
.operands
== i
.reg_operands
3434 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3435 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3436 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3439 unsigned int xchg
= i
.operands
- 1;
3440 union i386_op temp_op
;
3441 i386_operand_type temp_type
;
3443 temp_type
= i
.types
[xchg
];
3444 i
.types
[xchg
] = i
.types
[0];
3445 i
.types
[0] = temp_type
;
3446 temp_op
= i
.op
[xchg
];
3447 i
.op
[xchg
] = i
.op
[0];
3450 gas_assert (i
.rm
.mode
== 3);
3454 i
.rm
.regmem
= i
.rm
.reg
;
3457 if (i
.tm
.opcode_modifier
.d
)
3458 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3459 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3460 else /* Use the next insn. */
3464 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3465 are no memory operands and at least 3 register ones. */
3466 if (i
.reg_operands
>= 3
3467 && i
.vec_encoding
!= vex_encoding_vex3
3468 && i
.reg_operands
== i
.operands
- i
.imm_operands
3469 && i
.tm
.opcode_modifier
.vex
3470 && i
.tm
.opcode_modifier
.commutative
3471 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3473 && i
.vex
.register_specifier
3474 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3476 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3477 union i386_op temp_op
;
3478 i386_operand_type temp_type
;
3480 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3481 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3482 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3483 &i
.types
[i
.operands
- 3]));
3484 gas_assert (i
.rm
.mode
== 3);
3486 temp_type
= i
.types
[xchg
];
3487 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3488 i
.types
[xchg
+ 1] = temp_type
;
3489 temp_op
= i
.op
[xchg
];
3490 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3491 i
.op
[xchg
+ 1] = temp_op
;
3494 xchg
= i
.rm
.regmem
| 8;
3495 i
.rm
.regmem
= ~register_specifier
& 0xf;
3496 gas_assert (!(i
.rm
.regmem
& 8));
3497 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3498 register_specifier
= ~xchg
& 0xf;
3501 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3502 vector_length
= avxscalar
;
3503 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3509 /* Determine vector length from the last multi-length vector
3512 for (op
= t
->operands
; op
--;)
3513 if (t
->operand_types
[op
].bitfield
.xmmword
3514 && t
->operand_types
[op
].bitfield
.ymmword
3515 && i
.types
[op
].bitfield
.ymmword
)
3522 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3527 case DATA_PREFIX_OPCODE
:
3530 case REPE_PREFIX_OPCODE
:
3533 case REPNE_PREFIX_OPCODE
:
3540 /* Check the REX.W bit and VEXW. */
3541 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3542 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3543 else if (i
.tm
.opcode_modifier
.vexw
)
3544 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3546 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3548 /* Use 2-byte VEX prefix if possible. */
3550 && i
.vec_encoding
!= vex_encoding_vex3
3551 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3552 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3554 /* 2-byte VEX prefix. */
3558 i
.vex
.bytes
[0] = 0xc5;
3560 /* Check the REX.R bit. */
3561 r
= (i
.rex
& REX_R
) ? 0 : 1;
3562 i
.vex
.bytes
[1] = (r
<< 7
3563 | register_specifier
<< 3
3564 | vector_length
<< 2
3569 /* 3-byte VEX prefix. */
3574 switch (i
.tm
.opcode_modifier
.vexopcode
)
3578 i
.vex
.bytes
[0] = 0xc4;
3582 i
.vex
.bytes
[0] = 0xc4;
3586 i
.vex
.bytes
[0] = 0xc4;
3590 i
.vex
.bytes
[0] = 0x8f;
3594 i
.vex
.bytes
[0] = 0x8f;
3598 i
.vex
.bytes
[0] = 0x8f;
3604 /* The high 3 bits of the second VEX byte are 1's compliment
3605 of RXB bits from REX. */
3606 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3608 i
.vex
.bytes
[2] = (w
<< 7
3609 | register_specifier
<< 3
3610 | vector_length
<< 2
3615 static INLINE bfd_boolean
3616 is_evex_encoding (const insn_template
*t
)
3618 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3619 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3620 || t
->opcode_modifier
.sae
;
3623 static INLINE bfd_boolean
3624 is_any_vex_encoding (const insn_template
*t
)
3626 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3627 || is_evex_encoding (t
);
3630 /* Build the EVEX prefix. */
3633 build_evex_prefix (void)
3635 unsigned int register_specifier
;
3636 unsigned int implied_prefix
;
3638 rex_byte vrex_used
= 0;
3640 /* Check register specifier. */
3641 if (i
.vex
.register_specifier
)
3643 gas_assert ((i
.vrex
& REX_X
) == 0);
3645 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3646 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3647 register_specifier
+= 8;
3648 /* The upper 16 registers are encoded in the fourth byte of the
3650 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3651 i
.vex
.bytes
[3] = 0x8;
3652 register_specifier
= ~register_specifier
& 0xf;
3656 register_specifier
= 0xf;
3658 /* Encode upper 16 vector index register in the fourth byte of
3660 if (!(i
.vrex
& REX_X
))
3661 i
.vex
.bytes
[3] = 0x8;
3666 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3671 case DATA_PREFIX_OPCODE
:
3674 case REPE_PREFIX_OPCODE
:
3677 case REPNE_PREFIX_OPCODE
:
3684 /* 4 byte EVEX prefix. */
3686 i
.vex
.bytes
[0] = 0x62;
3689 switch (i
.tm
.opcode_modifier
.vexopcode
)
3705 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3707 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3709 /* The fifth bit of the second EVEX byte is 1's compliment of the
3710 REX_R bit in VREX. */
3711 if (!(i
.vrex
& REX_R
))
3712 i
.vex
.bytes
[1] |= 0x10;
3716 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3718 /* When all operands are registers, the REX_X bit in REX is not
3719 used. We reuse it to encode the upper 16 registers, which is
3720 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3721 as 1's compliment. */
3722 if ((i
.vrex
& REX_B
))
3725 i
.vex
.bytes
[1] &= ~0x40;
3729 /* EVEX instructions shouldn't need the REX prefix. */
3730 i
.vrex
&= ~vrex_used
;
3731 gas_assert (i
.vrex
== 0);
3733 /* Check the REX.W bit and VEXW. */
3734 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3735 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3736 else if (i
.tm
.opcode_modifier
.vexw
)
3737 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3739 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3741 /* Encode the U bit. */
3742 implied_prefix
|= 0x4;
3744 /* The third byte of the EVEX prefix. */
3745 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3747 /* The fourth byte of the EVEX prefix. */
3748 /* The zeroing-masking bit. */
3749 if (i
.mask
&& i
.mask
->zeroing
)
3750 i
.vex
.bytes
[3] |= 0x80;
3752 /* Don't always set the broadcast bit if there is no RC. */
3755 /* Encode the vector length. */
3756 unsigned int vec_length
;
3758 if (!i
.tm
.opcode_modifier
.evex
3759 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3763 /* Determine vector length from the last multi-length vector
3766 for (op
= i
.operands
; op
--;)
3767 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3768 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3769 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3771 if (i
.types
[op
].bitfield
.zmmword
)
3773 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3776 else if (i
.types
[op
].bitfield
.ymmword
)
3778 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3781 else if (i
.types
[op
].bitfield
.xmmword
)
3783 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3786 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3788 switch (i
.broadcast
->bytes
)
3791 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3794 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3797 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3806 if (op
>= MAX_OPERANDS
)
3810 switch (i
.tm
.opcode_modifier
.evex
)
3812 case EVEXLIG
: /* LL' is ignored */
3813 vec_length
= evexlig
<< 5;
3816 vec_length
= 0 << 5;
3819 vec_length
= 1 << 5;
3822 vec_length
= 2 << 5;
3828 i
.vex
.bytes
[3] |= vec_length
;
3829 /* Encode the broadcast bit. */
3831 i
.vex
.bytes
[3] |= 0x10;
3835 if (i
.rounding
->type
!= saeonly
)
3836 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3838 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3841 if (i
.mask
&& i
.mask
->mask
)
3842 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3846 process_immext (void)
3850 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3851 which is coded in the same place as an 8-bit immediate field
3852 would be. Here we fake an 8-bit immediate operand from the
3853 opcode suffix stored in tm.extension_opcode.
3855 AVX instructions also use this encoding, for some of
3856 3 argument instructions. */
3858 gas_assert (i
.imm_operands
<= 1
3860 || (is_any_vex_encoding (&i
.tm
)
3861 && i
.operands
<= 4)));
3863 exp
= &im_expressions
[i
.imm_operands
++];
3864 i
.op
[i
.operands
].imms
= exp
;
3865 i
.types
[i
.operands
] = imm8
;
3867 exp
->X_op
= O_constant
;
3868 exp
->X_add_number
= i
.tm
.extension_opcode
;
3869 i
.tm
.extension_opcode
= None
;
3876 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3881 as_bad (_("invalid instruction `%s' after `%s'"),
3882 i
.tm
.name
, i
.hle_prefix
);
3885 if (i
.prefix
[LOCK_PREFIX
])
3887 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3891 case HLEPrefixRelease
:
3892 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3894 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3898 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3900 as_bad (_("memory destination needed for instruction `%s'"
3901 " after `xrelease'"), i
.tm
.name
);
3908 /* Try the shortest encoding by shortening operand size. */
3911 optimize_encoding (void)
3915 if (optimize_for_space
3916 && i
.reg_operands
== 1
3917 && i
.imm_operands
== 1
3918 && !i
.types
[1].bitfield
.byte
3919 && i
.op
[0].imms
->X_op
== O_constant
3920 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3921 && ((i
.tm
.base_opcode
== 0xa8
3922 && i
.tm
.extension_opcode
== None
)
3923 || (i
.tm
.base_opcode
== 0xf6
3924 && i
.tm
.extension_opcode
== 0x0)))
3927 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3929 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3930 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3932 i
.types
[1].bitfield
.byte
= 1;
3933 /* Ignore the suffix. */
3935 if (base_regnum
>= 4
3936 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3938 /* Handle SP, BP, SI and DI registers. */
3939 if (i
.types
[1].bitfield
.word
)
3941 else if (i
.types
[1].bitfield
.dword
)
3949 else if (flag_code
== CODE_64BIT
3950 && ((i
.types
[1].bitfield
.qword
3951 && i
.reg_operands
== 1
3952 && i
.imm_operands
== 1
3953 && i
.op
[0].imms
->X_op
== O_constant
3954 && ((i
.tm
.base_opcode
== 0xb8
3955 && i
.tm
.extension_opcode
== None
3956 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3957 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3958 && (((i
.tm
.base_opcode
== 0x24
3959 || i
.tm
.base_opcode
== 0xa8)
3960 && i
.tm
.extension_opcode
== None
)
3961 || (i
.tm
.base_opcode
== 0x80
3962 && i
.tm
.extension_opcode
== 0x4)
3963 || ((i
.tm
.base_opcode
== 0xf6
3964 || (i
.tm
.base_opcode
| 1) == 0xc7)
3965 && i
.tm
.extension_opcode
== 0x0)))
3966 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3967 && i
.tm
.base_opcode
== 0x83
3968 && i
.tm
.extension_opcode
== 0x4)))
3969 || (i
.types
[0].bitfield
.qword
3970 && ((i
.reg_operands
== 2
3971 && i
.op
[0].regs
== i
.op
[1].regs
3972 && ((i
.tm
.base_opcode
== 0x30
3973 || i
.tm
.base_opcode
== 0x28)
3974 && i
.tm
.extension_opcode
== None
))
3975 || (i
.reg_operands
== 1
3977 && i
.tm
.base_opcode
== 0x30
3978 && i
.tm
.extension_opcode
== None
)))))
3981 andq $imm31, %r64 -> andl $imm31, %r32
3982 andq $imm7, %r64 -> andl $imm7, %r32
3983 testq $imm31, %r64 -> testl $imm31, %r32
3984 xorq %r64, %r64 -> xorl %r32, %r32
3985 subq %r64, %r64 -> subl %r32, %r32
3986 movq $imm31, %r64 -> movl $imm31, %r32
3987 movq $imm32, %r64 -> movl $imm32, %r32
3989 i
.tm
.opcode_modifier
.norex64
= 1;
3990 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
3993 movq $imm31, %r64 -> movl $imm31, %r32
3994 movq $imm32, %r64 -> movl $imm32, %r32
3996 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3997 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3998 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3999 i
.types
[0].bitfield
.imm32
= 1;
4000 i
.types
[0].bitfield
.imm32s
= 0;
4001 i
.types
[0].bitfield
.imm64
= 0;
4002 i
.types
[1].bitfield
.dword
= 1;
4003 i
.types
[1].bitfield
.qword
= 0;
4004 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4007 movq $imm31, %r64 -> movl $imm31, %r32
4009 i
.tm
.base_opcode
= 0xb8;
4010 i
.tm
.extension_opcode
= None
;
4011 i
.tm
.opcode_modifier
.w
= 0;
4012 i
.tm
.opcode_modifier
.shortform
= 1;
4013 i
.tm
.opcode_modifier
.modrm
= 0;
4017 else if (optimize
> 1
4018 && !optimize_for_space
4019 && i
.reg_operands
== 2
4020 && i
.op
[0].regs
== i
.op
[1].regs
4021 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4022 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4023 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4026 andb %rN, %rN -> testb %rN, %rN
4027 andw %rN, %rN -> testw %rN, %rN
4028 andq %rN, %rN -> testq %rN, %rN
4029 orb %rN, %rN -> testb %rN, %rN
4030 orw %rN, %rN -> testw %rN, %rN
4031 orq %rN, %rN -> testq %rN, %rN
4033 and outside of 64-bit mode
4035 andl %rN, %rN -> testl %rN, %rN
4036 orl %rN, %rN -> testl %rN, %rN
4038 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4040 else if (i
.reg_operands
== 3
4041 && i
.op
[0].regs
== i
.op
[1].regs
4042 && !i
.types
[2].bitfield
.xmmword
4043 && (i
.tm
.opcode_modifier
.vex
4044 || ((!i
.mask
|| i
.mask
->zeroing
)
4046 && is_evex_encoding (&i
.tm
)
4047 && (i
.vec_encoding
!= vex_encoding_evex
4048 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4049 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4050 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4051 && i
.types
[2].bitfield
.ymmword
))))
4052 && ((i
.tm
.base_opcode
== 0x55
4053 || i
.tm
.base_opcode
== 0x6655
4054 || i
.tm
.base_opcode
== 0x66df
4055 || i
.tm
.base_opcode
== 0x57
4056 || i
.tm
.base_opcode
== 0x6657
4057 || i
.tm
.base_opcode
== 0x66ef
4058 || i
.tm
.base_opcode
== 0x66f8
4059 || i
.tm
.base_opcode
== 0x66f9
4060 || i
.tm
.base_opcode
== 0x66fa
4061 || i
.tm
.base_opcode
== 0x66fb
4062 || i
.tm
.base_opcode
== 0x42
4063 || i
.tm
.base_opcode
== 0x6642
4064 || i
.tm
.base_opcode
== 0x47
4065 || i
.tm
.base_opcode
== 0x6647)
4066 && i
.tm
.extension_opcode
== None
))
4069 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4071 EVEX VOP %zmmM, %zmmM, %zmmN
4072 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4073 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4074 EVEX VOP %ymmM, %ymmM, %ymmN
4075 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4076 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4077 VEX VOP %ymmM, %ymmM, %ymmN
4078 -> VEX VOP %xmmM, %xmmM, %xmmN
4079 VOP, one of vpandn and vpxor:
4080 VEX VOP %ymmM, %ymmM, %ymmN
4081 -> VEX VOP %xmmM, %xmmM, %xmmN
4082 VOP, one of vpandnd and vpandnq:
4083 EVEX VOP %zmmM, %zmmM, %zmmN
4084 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4085 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4086 EVEX VOP %ymmM, %ymmM, %ymmN
4087 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4088 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4089 VOP, one of vpxord and vpxorq:
4090 EVEX VOP %zmmM, %zmmM, %zmmN
4091 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4092 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4093 EVEX VOP %ymmM, %ymmM, %ymmN
4094 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4095 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4096 VOP, one of kxord and kxorq:
4097 VEX VOP %kM, %kM, %kN
4098 -> VEX kxorw %kM, %kM, %kN
4099 VOP, one of kandnd and kandnq:
4100 VEX VOP %kM, %kM, %kN
4101 -> VEX kandnw %kM, %kM, %kN
4103 if (is_evex_encoding (&i
.tm
))
4105 if (i
.vec_encoding
!= vex_encoding_evex
)
4107 i
.tm
.opcode_modifier
.vex
= VEX128
;
4108 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4109 i
.tm
.opcode_modifier
.evex
= 0;
4111 else if (optimize
> 1)
4112 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4116 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4118 i
.tm
.base_opcode
&= 0xff;
4119 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4122 i
.tm
.opcode_modifier
.vex
= VEX128
;
4124 if (i
.tm
.opcode_modifier
.vex
)
4125 for (j
= 0; j
< 3; j
++)
4127 i
.types
[j
].bitfield
.xmmword
= 1;
4128 i
.types
[j
].bitfield
.ymmword
= 0;
4131 else if (i
.vec_encoding
!= vex_encoding_evex
4132 && !i
.types
[0].bitfield
.zmmword
4133 && !i
.types
[1].bitfield
.zmmword
4136 && is_evex_encoding (&i
.tm
)
4137 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4138 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4139 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4140 || (i
.tm
.base_opcode
& ~4) == 0x66db
4141 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4142 && i
.tm
.extension_opcode
== None
)
4145 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4146 vmovdqu32 and vmovdqu64:
4147 EVEX VOP %xmmM, %xmmN
4148 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4149 EVEX VOP %ymmM, %ymmN
4150 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4152 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4154 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4156 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4158 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4159 VOP, one of vpand, vpandn, vpor, vpxor:
4160 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4161 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4162 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4163 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4164 EVEX VOP{d,q} mem, %xmmM, %xmmN
4165 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4166 EVEX VOP{d,q} mem, %ymmM, %ymmN
4167 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4169 for (j
= 0; j
< i
.operands
; j
++)
4170 if (operand_type_check (i
.types
[j
], disp
)
4171 && i
.op
[j
].disps
->X_op
== O_constant
)
4173 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4174 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4175 bytes, we choose EVEX Disp8 over VEX Disp32. */
4176 int evex_disp8
, vex_disp8
;
4177 unsigned int memshift
= i
.memshift
;
4178 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4180 evex_disp8
= fits_in_disp8 (n
);
4182 vex_disp8
= fits_in_disp8 (n
);
4183 if (evex_disp8
!= vex_disp8
)
4185 i
.memshift
= memshift
;
4189 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4192 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4193 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4194 i
.tm
.opcode_modifier
.vex
4195 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4196 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4197 /* VPAND, VPOR, and VPXOR are commutative. */
4198 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4199 i
.tm
.opcode_modifier
.commutative
= 1;
4200 i
.tm
.opcode_modifier
.evex
= 0;
4201 i
.tm
.opcode_modifier
.masking
= 0;
4202 i
.tm
.opcode_modifier
.broadcast
= 0;
4203 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4206 i
.types
[j
].bitfield
.disp8
4207 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4211 /* This is the guts of the machine-dependent assembler. LINE points to a
4212 machine dependent instruction. This function is supposed to emit
4213 the frags/bytes it assembles to. */
4216 md_assemble (char *line
)
4219 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4220 const insn_template
*t
;
4222 /* Initialize globals. */
4223 memset (&i
, '\0', sizeof (i
));
4224 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4225 i
.reloc
[j
] = NO_RELOC
;
4226 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4227 memset (im_expressions
, '\0', sizeof (im_expressions
));
4228 save_stack_p
= save_stack
;
4230 /* First parse an instruction mnemonic & call i386_operand for the operands.
4231 We assume that the scrubber has arranged it so that line[0] is the valid
4232 start of a (possibly prefixed) mnemonic. */
4234 line
= parse_insn (line
, mnemonic
);
4237 mnem_suffix
= i
.suffix
;
4239 line
= parse_operands (line
, mnemonic
);
4241 xfree (i
.memop1_string
);
4242 i
.memop1_string
= NULL
;
4246 /* Now we've parsed the mnemonic into a set of templates, and have the
4247 operands at hand. */
4249 /* All intel opcodes have reversed operands except for "bound" and
4250 "enter". We also don't reverse intersegment "jmp" and "call"
4251 instructions with 2 immediate operands so that the immediate segment
4252 precedes the offset, as it does when in AT&T mode. */
4255 && (strcmp (mnemonic
, "bound") != 0)
4256 && (strcmp (mnemonic
, "invlpga") != 0)
4257 && !(operand_type_check (i
.types
[0], imm
)
4258 && operand_type_check (i
.types
[1], imm
)))
4261 /* The order of the immediates should be reversed
4262 for 2 immediates extrq and insertq instructions */
4263 if (i
.imm_operands
== 2
4264 && (strcmp (mnemonic
, "extrq") == 0
4265 || strcmp (mnemonic
, "insertq") == 0))
4266 swap_2_operands (0, 1);
4271 /* Don't optimize displacement for movabs since it only takes 64bit
4274 && i
.disp_encoding
!= disp_encoding_32bit
4275 && (flag_code
!= CODE_64BIT
4276 || strcmp (mnemonic
, "movabs") != 0))
4279 /* Next, we find a template that matches the given insn,
4280 making sure the overlap of the given operands types is consistent
4281 with the template operand types. */
4283 if (!(t
= match_template (mnem_suffix
)))
4286 if (sse_check
!= check_none
4287 && !i
.tm
.opcode_modifier
.noavx
4288 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4289 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4290 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4291 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4292 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4293 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4294 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4295 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4296 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4297 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4298 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4299 || i
.tm
.cpu_flags
.bitfield
.cpusha
4300 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4302 (sse_check
== check_warning
4304 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4307 /* Zap movzx and movsx suffix. The suffix has been set from
4308 "word ptr" or "byte ptr" on the source operand in Intel syntax
4309 or extracted from mnemonic in AT&T syntax. But we'll use
4310 the destination register to choose the suffix for encoding. */
4311 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4313 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4314 there is no suffix, the default will be byte extension. */
4315 if (i
.reg_operands
!= 2
4318 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4323 if (i
.tm
.opcode_modifier
.fwait
)
4324 if (!add_prefix (FWAIT_OPCODE
))
4327 /* Check if REP prefix is OK. */
4328 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4330 as_bad (_("invalid instruction `%s' after `%s'"),
4331 i
.tm
.name
, i
.rep_prefix
);
4335 /* Check for lock without a lockable instruction. Destination operand
4336 must be memory unless it is xchg (0x86). */
4337 if (i
.prefix
[LOCK_PREFIX
]
4338 && (!i
.tm
.opcode_modifier
.islockable
4339 || i
.mem_operands
== 0
4340 || (i
.tm
.base_opcode
!= 0x86
4341 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4343 as_bad (_("expecting lockable instruction after `lock'"));
4347 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4348 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4350 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4354 /* Check if HLE prefix is OK. */
4355 if (i
.hle_prefix
&& !check_hle ())
4358 /* Check BND prefix. */
4359 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4360 as_bad (_("expecting valid branch instruction after `bnd'"));
4362 /* Check NOTRACK prefix. */
4363 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4364 as_bad (_("expecting indirect branch instruction after `notrack'"));
4366 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4368 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4369 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4370 else if (flag_code
!= CODE_16BIT
4371 ? i
.prefix
[ADDR_PREFIX
]
4372 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4373 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4376 /* Insert BND prefix. */
4377 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4379 if (!i
.prefix
[BND_PREFIX
])
4380 add_prefix (BND_PREFIX_OPCODE
);
4381 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4383 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4384 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4388 /* Check string instruction segment overrides. */
4389 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4391 gas_assert (i
.mem_operands
);
4392 if (!check_string ())
4394 i
.disp_operands
= 0;
4397 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4398 optimize_encoding ();
4400 if (!process_suffix ())
4403 /* Update operand types. */
4404 for (j
= 0; j
< i
.operands
; j
++)
4405 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4407 /* Make still unresolved immediate matches conform to size of immediate
4408 given in i.suffix. */
4409 if (!finalize_imm ())
4412 if (i
.types
[0].bitfield
.imm1
)
4413 i
.imm_operands
= 0; /* kludge for shift insns. */
4415 /* We only need to check those implicit registers for instructions
4416 with 3 operands or less. */
4417 if (i
.operands
<= 3)
4418 for (j
= 0; j
< i
.operands
; j
++)
4419 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4420 && !i
.types
[j
].bitfield
.xmmword
)
4423 /* ImmExt should be processed after SSE2AVX. */
4424 if (!i
.tm
.opcode_modifier
.sse2avx
4425 && i
.tm
.opcode_modifier
.immext
)
4428 /* For insns with operands there are more diddles to do to the opcode. */
4431 if (!process_operands ())
4434 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4436 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4437 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4440 if (is_any_vex_encoding (&i
.tm
))
4442 if (!cpu_arch_flags
.bitfield
.cpui286
)
4444 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4449 if (i
.tm
.opcode_modifier
.vex
)
4450 build_vex_prefix (t
);
4452 build_evex_prefix ();
4455 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4456 instructions may define INT_OPCODE as well, so avoid this corner
4457 case for those instructions that use MODRM. */
4458 if (i
.tm
.base_opcode
== INT_OPCODE
4459 && !i
.tm
.opcode_modifier
.modrm
4460 && i
.op
[0].imms
->X_add_number
== 3)
4462 i
.tm
.base_opcode
= INT3_OPCODE
;
4466 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4467 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4468 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4469 && i
.op
[0].disps
->X_op
== O_constant
)
4471 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4472 the absolute address given by the constant. Since ix86 jumps and
4473 calls are pc relative, we need to generate a reloc. */
4474 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4475 i
.op
[0].disps
->X_op
= O_symbol
;
4478 if (i
.tm
.opcode_modifier
.rex64
)
4481 /* For 8 bit registers we need an empty rex prefix. Also if the
4482 instruction already has a prefix, we need to convert old
4483 registers to new ones. */
4485 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4486 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4487 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4488 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4489 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4490 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4495 i
.rex
|= REX_OPCODE
;
4496 for (x
= 0; x
< 2; x
++)
4498 /* Look for 8 bit operand that uses old registers. */
4499 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4500 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4502 /* In case it is "hi" register, give up. */
4503 if (i
.op
[x
].regs
->reg_num
> 3)
4504 as_bad (_("can't encode register '%s%s' in an "
4505 "instruction requiring REX prefix."),
4506 register_prefix
, i
.op
[x
].regs
->reg_name
);
4508 /* Otherwise it is equivalent to the extended register.
4509 Since the encoding doesn't change this is merely
4510 cosmetic cleanup for debug output. */
4512 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4517 if (i
.rex
== 0 && i
.rex_encoding
)
4519 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4520 that uses legacy register. If it is "hi" register, don't add
4521 the REX_OPCODE byte. */
4523 for (x
= 0; x
< 2; x
++)
4524 if (i
.types
[x
].bitfield
.class == Reg
4525 && i
.types
[x
].bitfield
.byte
4526 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4527 && i
.op
[x
].regs
->reg_num
> 3)
4529 i
.rex_encoding
= FALSE
;
4538 add_prefix (REX_OPCODE
| i
.rex
);
4540 /* We are ready to output the insn. */
4545 parse_insn (char *line
, char *mnemonic
)
4548 char *token_start
= l
;
4551 const insn_template
*t
;
4557 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4562 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4564 as_bad (_("no such instruction: `%s'"), token_start
);
4569 if (!is_space_char (*l
)
4570 && *l
!= END_OF_INSN
4572 || (*l
!= PREFIX_SEPARATOR
4575 as_bad (_("invalid character %s in mnemonic"),
4576 output_invalid (*l
));
4579 if (token_start
== l
)
4581 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4582 as_bad (_("expecting prefix; got nothing"));
4584 as_bad (_("expecting mnemonic; got nothing"));
4588 /* Look up instruction (or prefix) via hash table. */
4589 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4591 if (*l
!= END_OF_INSN
4592 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4593 && current_templates
4594 && current_templates
->start
->opcode_modifier
.isprefix
)
4596 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4598 as_bad ((flag_code
!= CODE_64BIT
4599 ? _("`%s' is only supported in 64-bit mode")
4600 : _("`%s' is not supported in 64-bit mode")),
4601 current_templates
->start
->name
);
4604 /* If we are in 16-bit mode, do not allow addr16 or data16.
4605 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4606 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4607 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4608 && flag_code
!= CODE_64BIT
4609 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4610 ^ (flag_code
== CODE_16BIT
)))
4612 as_bad (_("redundant %s prefix"),
4613 current_templates
->start
->name
);
4616 if (current_templates
->start
->opcode_length
== 0)
4618 /* Handle pseudo prefixes. */
4619 switch (current_templates
->start
->base_opcode
)
4623 i
.disp_encoding
= disp_encoding_8bit
;
4627 i
.disp_encoding
= disp_encoding_32bit
;
4631 i
.dir_encoding
= dir_encoding_load
;
4635 i
.dir_encoding
= dir_encoding_store
;
4639 i
.vec_encoding
= vex_encoding_vex2
;
4643 i
.vec_encoding
= vex_encoding_vex3
;
4647 i
.vec_encoding
= vex_encoding_evex
;
4651 i
.rex_encoding
= TRUE
;
4655 i
.no_optimize
= TRUE
;
4663 /* Add prefix, checking for repeated prefixes. */
4664 switch (add_prefix (current_templates
->start
->base_opcode
))
4669 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4670 i
.notrack_prefix
= current_templates
->start
->name
;
4673 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4674 i
.hle_prefix
= current_templates
->start
->name
;
4675 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4676 i
.bnd_prefix
= current_templates
->start
->name
;
4678 i
.rep_prefix
= current_templates
->start
->name
;
4684 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4691 if (!current_templates
)
4693 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4694 Check if we should swap operand or force 32bit displacement in
4696 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4697 i
.dir_encoding
= dir_encoding_swap
;
4698 else if (mnem_p
- 3 == dot_p
4701 i
.disp_encoding
= disp_encoding_8bit
;
4702 else if (mnem_p
- 4 == dot_p
4706 i
.disp_encoding
= disp_encoding_32bit
;
4711 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4714 if (!current_templates
)
4717 if (mnem_p
> mnemonic
)
4719 /* See if we can get a match by trimming off a suffix. */
4722 case WORD_MNEM_SUFFIX
:
4723 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4724 i
.suffix
= SHORT_MNEM_SUFFIX
;
4727 case BYTE_MNEM_SUFFIX
:
4728 case QWORD_MNEM_SUFFIX
:
4729 i
.suffix
= mnem_p
[-1];
4731 current_templates
= (const templates
*) hash_find (op_hash
,
4734 case SHORT_MNEM_SUFFIX
:
4735 case LONG_MNEM_SUFFIX
:
4738 i
.suffix
= mnem_p
[-1];
4740 current_templates
= (const templates
*) hash_find (op_hash
,
4749 if (intel_float_operand (mnemonic
) == 1)
4750 i
.suffix
= SHORT_MNEM_SUFFIX
;
4752 i
.suffix
= LONG_MNEM_SUFFIX
;
4754 current_templates
= (const templates
*) hash_find (op_hash
,
4761 if (!current_templates
)
4763 as_bad (_("no such instruction: `%s'"), token_start
);
4768 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4769 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4771 /* Check for a branch hint. We allow ",pt" and ",pn" for
4772 predict taken and predict not taken respectively.
4773 I'm not sure that branch hints actually do anything on loop
4774 and jcxz insns (JumpByte) for current Pentium4 chips. They
4775 may work in the future and it doesn't hurt to accept them
4777 if (l
[0] == ',' && l
[1] == 'p')
4781 if (!add_prefix (DS_PREFIX_OPCODE
))
4785 else if (l
[2] == 'n')
4787 if (!add_prefix (CS_PREFIX_OPCODE
))
4793 /* Any other comma loses. */
4796 as_bad (_("invalid character %s in mnemonic"),
4797 output_invalid (*l
));
4801 /* Check if instruction is supported on specified architecture. */
4803 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4805 supported
|= cpu_flags_match (t
);
4806 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4808 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4809 as_warn (_("use .code16 to ensure correct addressing mode"));
4815 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4816 as_bad (flag_code
== CODE_64BIT
4817 ? _("`%s' is not supported in 64-bit mode")
4818 : _("`%s' is only supported in 64-bit mode"),
4819 current_templates
->start
->name
);
4821 as_bad (_("`%s' is not supported on `%s%s'"),
4822 current_templates
->start
->name
,
4823 cpu_arch_name
? cpu_arch_name
: default_arch
,
4824 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4830 parse_operands (char *l
, const char *mnemonic
)
4834 /* 1 if operand is pending after ','. */
4835 unsigned int expecting_operand
= 0;
4837 /* Non-zero if operand parens not balanced. */
4838 unsigned int paren_not_balanced
;
4840 while (*l
!= END_OF_INSN
)
4842 /* Skip optional white space before operand. */
4843 if (is_space_char (*l
))
4845 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4847 as_bad (_("invalid character %s before operand %d"),
4848 output_invalid (*l
),
4852 token_start
= l
; /* After white space. */
4853 paren_not_balanced
= 0;
4854 while (paren_not_balanced
|| *l
!= ',')
4856 if (*l
== END_OF_INSN
)
4858 if (paren_not_balanced
)
4861 as_bad (_("unbalanced parenthesis in operand %d."),
4864 as_bad (_("unbalanced brackets in operand %d."),
4869 break; /* we are done */
4871 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4873 as_bad (_("invalid character %s in operand %d"),
4874 output_invalid (*l
),
4881 ++paren_not_balanced
;
4883 --paren_not_balanced
;
4888 ++paren_not_balanced
;
4890 --paren_not_balanced
;
4894 if (l
!= token_start
)
4895 { /* Yes, we've read in another operand. */
4896 unsigned int operand_ok
;
4897 this_operand
= i
.operands
++;
4898 if (i
.operands
> MAX_OPERANDS
)
4900 as_bad (_("spurious operands; (%d operands/instruction max)"),
4904 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4905 /* Now parse operand adding info to 'i' as we go along. */
4906 END_STRING_AND_SAVE (l
);
4908 if (i
.mem_operands
> 1)
4910 as_bad (_("too many memory references for `%s'"),
4917 i386_intel_operand (token_start
,
4918 intel_float_operand (mnemonic
));
4920 operand_ok
= i386_att_operand (token_start
);
4922 RESTORE_END_STRING (l
);
4928 if (expecting_operand
)
4930 expecting_operand_after_comma
:
4931 as_bad (_("expecting operand after ','; got nothing"));
4936 as_bad (_("expecting operand before ','; got nothing"));
4941 /* Now *l must be either ',' or END_OF_INSN. */
4944 if (*++l
== END_OF_INSN
)
4946 /* Just skip it, if it's \n complain. */
4947 goto expecting_operand_after_comma
;
4949 expecting_operand
= 1;
4956 swap_2_operands (int xchg1
, int xchg2
)
4958 union i386_op temp_op
;
4959 i386_operand_type temp_type
;
4960 unsigned int temp_flags
;
4961 enum bfd_reloc_code_real temp_reloc
;
4963 temp_type
= i
.types
[xchg2
];
4964 i
.types
[xchg2
] = i
.types
[xchg1
];
4965 i
.types
[xchg1
] = temp_type
;
4967 temp_flags
= i
.flags
[xchg2
];
4968 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4969 i
.flags
[xchg1
] = temp_flags
;
4971 temp_op
= i
.op
[xchg2
];
4972 i
.op
[xchg2
] = i
.op
[xchg1
];
4973 i
.op
[xchg1
] = temp_op
;
4975 temp_reloc
= i
.reloc
[xchg2
];
4976 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4977 i
.reloc
[xchg1
] = temp_reloc
;
4981 if (i
.mask
->operand
== xchg1
)
4982 i
.mask
->operand
= xchg2
;
4983 else if (i
.mask
->operand
== xchg2
)
4984 i
.mask
->operand
= xchg1
;
4988 if (i
.broadcast
->operand
== xchg1
)
4989 i
.broadcast
->operand
= xchg2
;
4990 else if (i
.broadcast
->operand
== xchg2
)
4991 i
.broadcast
->operand
= xchg1
;
4995 if (i
.rounding
->operand
== xchg1
)
4996 i
.rounding
->operand
= xchg2
;
4997 else if (i
.rounding
->operand
== xchg2
)
4998 i
.rounding
->operand
= xchg1
;
5003 swap_operands (void)
5009 swap_2_operands (1, i
.operands
- 2);
5013 swap_2_operands (0, i
.operands
- 1);
5019 if (i
.mem_operands
== 2)
5021 const seg_entry
*temp_seg
;
5022 temp_seg
= i
.seg
[0];
5023 i
.seg
[0] = i
.seg
[1];
5024 i
.seg
[1] = temp_seg
;
5028 /* Try to ensure constant immediates are represented in the smallest
5033 char guess_suffix
= 0;
5037 guess_suffix
= i
.suffix
;
5038 else if (i
.reg_operands
)
5040 /* Figure out a suffix from the last register operand specified.
5041 We can't do this properly yet, i.e. excluding special register
5042 instances, but the following works for instructions with
5043 immediates. In any case, we can't set i.suffix yet. */
5044 for (op
= i
.operands
; --op
>= 0;)
5045 if (i
.types
[op
].bitfield
.class != Reg
)
5047 else if (i
.types
[op
].bitfield
.byte
)
5049 guess_suffix
= BYTE_MNEM_SUFFIX
;
5052 else if (i
.types
[op
].bitfield
.word
)
5054 guess_suffix
= WORD_MNEM_SUFFIX
;
5057 else if (i
.types
[op
].bitfield
.dword
)
5059 guess_suffix
= LONG_MNEM_SUFFIX
;
5062 else if (i
.types
[op
].bitfield
.qword
)
5064 guess_suffix
= QWORD_MNEM_SUFFIX
;
5068 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5069 guess_suffix
= WORD_MNEM_SUFFIX
;
5071 for (op
= i
.operands
; --op
>= 0;)
5072 if (operand_type_check (i
.types
[op
], imm
))
5074 switch (i
.op
[op
].imms
->X_op
)
5077 /* If a suffix is given, this operand may be shortened. */
5078 switch (guess_suffix
)
5080 case LONG_MNEM_SUFFIX
:
5081 i
.types
[op
].bitfield
.imm32
= 1;
5082 i
.types
[op
].bitfield
.imm64
= 1;
5084 case WORD_MNEM_SUFFIX
:
5085 i
.types
[op
].bitfield
.imm16
= 1;
5086 i
.types
[op
].bitfield
.imm32
= 1;
5087 i
.types
[op
].bitfield
.imm32s
= 1;
5088 i
.types
[op
].bitfield
.imm64
= 1;
5090 case BYTE_MNEM_SUFFIX
:
5091 i
.types
[op
].bitfield
.imm8
= 1;
5092 i
.types
[op
].bitfield
.imm8s
= 1;
5093 i
.types
[op
].bitfield
.imm16
= 1;
5094 i
.types
[op
].bitfield
.imm32
= 1;
5095 i
.types
[op
].bitfield
.imm32s
= 1;
5096 i
.types
[op
].bitfield
.imm64
= 1;
5100 /* If this operand is at most 16 bits, convert it
5101 to a signed 16 bit number before trying to see
5102 whether it will fit in an even smaller size.
5103 This allows a 16-bit operand such as $0xffe0 to
5104 be recognised as within Imm8S range. */
5105 if ((i
.types
[op
].bitfield
.imm16
)
5106 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5108 i
.op
[op
].imms
->X_add_number
=
5109 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5112 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5113 if ((i
.types
[op
].bitfield
.imm32
)
5114 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5117 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5118 ^ ((offsetT
) 1 << 31))
5119 - ((offsetT
) 1 << 31));
5123 = operand_type_or (i
.types
[op
],
5124 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5126 /* We must avoid matching of Imm32 templates when 64bit
5127 only immediate is available. */
5128 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5129 i
.types
[op
].bitfield
.imm32
= 0;
5136 /* Symbols and expressions. */
5138 /* Convert symbolic operand to proper sizes for matching, but don't
5139 prevent matching a set of insns that only supports sizes other
5140 than those matching the insn suffix. */
5142 i386_operand_type mask
, allowed
;
5143 const insn_template
*t
;
5145 operand_type_set (&mask
, 0);
5146 operand_type_set (&allowed
, 0);
5148 for (t
= current_templates
->start
;
5149 t
< current_templates
->end
;
5152 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5153 allowed
= operand_type_and (allowed
, anyimm
);
5155 switch (guess_suffix
)
5157 case QWORD_MNEM_SUFFIX
:
5158 mask
.bitfield
.imm64
= 1;
5159 mask
.bitfield
.imm32s
= 1;
5161 case LONG_MNEM_SUFFIX
:
5162 mask
.bitfield
.imm32
= 1;
5164 case WORD_MNEM_SUFFIX
:
5165 mask
.bitfield
.imm16
= 1;
5167 case BYTE_MNEM_SUFFIX
:
5168 mask
.bitfield
.imm8
= 1;
5173 allowed
= operand_type_and (mask
, allowed
);
5174 if (!operand_type_all_zero (&allowed
))
5175 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5182 /* Try to use the smallest displacement type too. */
5184 optimize_disp (void)
5188 for (op
= i
.operands
; --op
>= 0;)
5189 if (operand_type_check (i
.types
[op
], disp
))
5191 if (i
.op
[op
].disps
->X_op
== O_constant
)
5193 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5195 if (i
.types
[op
].bitfield
.disp16
5196 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5198 /* If this operand is at most 16 bits, convert
5199 to a signed 16 bit number and don't use 64bit
5201 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5202 i
.types
[op
].bitfield
.disp64
= 0;
5205 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5206 if (i
.types
[op
].bitfield
.disp32
5207 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5209 /* If this operand is at most 32 bits, convert
5210 to a signed 32 bit number and don't use 64bit
5212 op_disp
&= (((offsetT
) 2 << 31) - 1);
5213 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5214 i
.types
[op
].bitfield
.disp64
= 0;
5217 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5219 i
.types
[op
].bitfield
.disp8
= 0;
5220 i
.types
[op
].bitfield
.disp16
= 0;
5221 i
.types
[op
].bitfield
.disp32
= 0;
5222 i
.types
[op
].bitfield
.disp32s
= 0;
5223 i
.types
[op
].bitfield
.disp64
= 0;
5227 else if (flag_code
== CODE_64BIT
)
5229 if (fits_in_signed_long (op_disp
))
5231 i
.types
[op
].bitfield
.disp64
= 0;
5232 i
.types
[op
].bitfield
.disp32s
= 1;
5234 if (i
.prefix
[ADDR_PREFIX
]
5235 && fits_in_unsigned_long (op_disp
))
5236 i
.types
[op
].bitfield
.disp32
= 1;
5238 if ((i
.types
[op
].bitfield
.disp32
5239 || i
.types
[op
].bitfield
.disp32s
5240 || i
.types
[op
].bitfield
.disp16
)
5241 && fits_in_disp8 (op_disp
))
5242 i
.types
[op
].bitfield
.disp8
= 1;
5244 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5245 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5247 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5248 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5249 i
.types
[op
].bitfield
.disp8
= 0;
5250 i
.types
[op
].bitfield
.disp16
= 0;
5251 i
.types
[op
].bitfield
.disp32
= 0;
5252 i
.types
[op
].bitfield
.disp32s
= 0;
5253 i
.types
[op
].bitfield
.disp64
= 0;
5256 /* We only support 64bit displacement on constants. */
5257 i
.types
[op
].bitfield
.disp64
= 0;
5261 /* Return 1 if there is a match in broadcast bytes between operand
5262 GIVEN and instruction template T. */
5265 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5267 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5268 && i
.types
[given
].bitfield
.byte
)
5269 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5270 && i
.types
[given
].bitfield
.word
)
5271 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5272 && i
.types
[given
].bitfield
.dword
)
5273 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5274 && i
.types
[given
].bitfield
.qword
));
5277 /* Check if operands are valid for the instruction. */
5280 check_VecOperands (const insn_template
*t
)
5284 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5286 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5287 any one operand are implicity requiring AVX512VL support if the actual
5288 operand size is YMMword or XMMword. Since this function runs after
5289 template matching, there's no need to check for YMMword/XMMword in
5291 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5292 if (!cpu_flags_all_zero (&cpu
)
5293 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5294 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5296 for (op
= 0; op
< t
->operands
; ++op
)
5298 if (t
->operand_types
[op
].bitfield
.zmmword
5299 && (i
.types
[op
].bitfield
.ymmword
5300 || i
.types
[op
].bitfield
.xmmword
))
5302 i
.error
= unsupported
;
5308 /* Without VSIB byte, we can't have a vector register for index. */
5309 if (!t
->opcode_modifier
.vecsib
5311 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5312 || i
.index_reg
->reg_type
.bitfield
.ymmword
5313 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5315 i
.error
= unsupported_vector_index_register
;
5319 /* Check if default mask is allowed. */
5320 if (t
->opcode_modifier
.nodefmask
5321 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5323 i
.error
= no_default_mask
;
5327 /* For VSIB byte, we need a vector register for index, and all vector
5328 registers must be distinct. */
5329 if (t
->opcode_modifier
.vecsib
)
5332 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5333 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5334 || (t
->opcode_modifier
.vecsib
== VecSIB256
5335 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5336 || (t
->opcode_modifier
.vecsib
== VecSIB512
5337 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5339 i
.error
= invalid_vsib_address
;
5343 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5344 if (i
.reg_operands
== 2 && !i
.mask
)
5346 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5347 gas_assert (i
.types
[0].bitfield
.xmmword
5348 || i
.types
[0].bitfield
.ymmword
);
5349 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5350 gas_assert (i
.types
[2].bitfield
.xmmword
5351 || i
.types
[2].bitfield
.ymmword
);
5352 if (operand_check
== check_none
)
5354 if (register_number (i
.op
[0].regs
)
5355 != register_number (i
.index_reg
)
5356 && register_number (i
.op
[2].regs
)
5357 != register_number (i
.index_reg
)
5358 && register_number (i
.op
[0].regs
)
5359 != register_number (i
.op
[2].regs
))
5361 if (operand_check
== check_error
)
5363 i
.error
= invalid_vector_register_set
;
5366 as_warn (_("mask, index, and destination registers should be distinct"));
5368 else if (i
.reg_operands
== 1 && i
.mask
)
5370 if (i
.types
[1].bitfield
.class == RegSIMD
5371 && (i
.types
[1].bitfield
.xmmword
5372 || i
.types
[1].bitfield
.ymmword
5373 || i
.types
[1].bitfield
.zmmword
)
5374 && (register_number (i
.op
[1].regs
)
5375 == register_number (i
.index_reg
)))
5377 if (operand_check
== check_error
)
5379 i
.error
= invalid_vector_register_set
;
5382 if (operand_check
!= check_none
)
5383 as_warn (_("index and destination registers should be distinct"));
5388 /* Check if broadcast is supported by the instruction and is applied
5389 to the memory operand. */
5392 i386_operand_type type
, overlap
;
5394 /* Check if specified broadcast is supported in this instruction,
5395 and its broadcast bytes match the memory operand. */
5396 op
= i
.broadcast
->operand
;
5397 if (!t
->opcode_modifier
.broadcast
5398 || !(i
.flags
[op
] & Operand_Mem
)
5399 || (!i
.types
[op
].bitfield
.unspecified
5400 && !match_broadcast_size (t
, op
)))
5403 i
.error
= unsupported_broadcast
;
5407 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5408 * i
.broadcast
->type
);
5409 operand_type_set (&type
, 0);
5410 switch (i
.broadcast
->bytes
)
5413 type
.bitfield
.word
= 1;
5416 type
.bitfield
.dword
= 1;
5419 type
.bitfield
.qword
= 1;
5422 type
.bitfield
.xmmword
= 1;
5425 type
.bitfield
.ymmword
= 1;
5428 type
.bitfield
.zmmword
= 1;
5434 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5435 if (operand_type_all_zero (&overlap
))
5438 if (t
->opcode_modifier
.checkregsize
)
5442 type
.bitfield
.baseindex
= 1;
5443 for (j
= 0; j
< i
.operands
; ++j
)
5446 && !operand_type_register_match(i
.types
[j
],
5447 t
->operand_types
[j
],
5449 t
->operand_types
[op
]))
5454 /* If broadcast is supported in this instruction, we need to check if
5455 operand of one-element size isn't specified without broadcast. */
5456 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5458 /* Find memory operand. */
5459 for (op
= 0; op
< i
.operands
; op
++)
5460 if (i
.flags
[op
] & Operand_Mem
)
5462 gas_assert (op
< i
.operands
);
5463 /* Check size of the memory operand. */
5464 if (match_broadcast_size (t
, op
))
5466 i
.error
= broadcast_needed
;
5471 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5473 /* Check if requested masking is supported. */
5476 switch (t
->opcode_modifier
.masking
)
5480 case MERGING_MASKING
:
5481 if (i
.mask
->zeroing
)
5484 i
.error
= unsupported_masking
;
5488 case DYNAMIC_MASKING
:
5489 /* Memory destinations allow only merging masking. */
5490 if (i
.mask
->zeroing
&& i
.mem_operands
)
5492 /* Find memory operand. */
5493 for (op
= 0; op
< i
.operands
; op
++)
5494 if (i
.flags
[op
] & Operand_Mem
)
5496 gas_assert (op
< i
.operands
);
5497 if (op
== i
.operands
- 1)
5499 i
.error
= unsupported_masking
;
5509 /* Check if masking is applied to dest operand. */
5510 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5512 i
.error
= mask_not_on_destination
;
5519 if (!t
->opcode_modifier
.sae
5520 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5522 i
.error
= unsupported_rc_sae
;
5525 /* If the instruction has several immediate operands and one of
5526 them is rounding, the rounding operand should be the last
5527 immediate operand. */
5528 if (i
.imm_operands
> 1
5529 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5531 i
.error
= rc_sae_operand_not_last_imm
;
5536 /* Check vector Disp8 operand. */
5537 if (t
->opcode_modifier
.disp8memshift
5538 && i
.disp_encoding
!= disp_encoding_32bit
)
5541 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5542 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5543 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5546 const i386_operand_type
*type
= NULL
;
5549 for (op
= 0; op
< i
.operands
; op
++)
5550 if (i
.flags
[op
] & Operand_Mem
)
5552 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5553 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5554 else if (t
->operand_types
[op
].bitfield
.xmmword
5555 + t
->operand_types
[op
].bitfield
.ymmword
5556 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5557 type
= &t
->operand_types
[op
];
5558 else if (!i
.types
[op
].bitfield
.unspecified
)
5559 type
= &i
.types
[op
];
5561 else if (i
.types
[op
].bitfield
.class == RegSIMD
5562 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5564 if (i
.types
[op
].bitfield
.zmmword
)
5566 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5568 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5574 if (type
->bitfield
.zmmword
)
5576 else if (type
->bitfield
.ymmword
)
5578 else if (type
->bitfield
.xmmword
)
5582 /* For the check in fits_in_disp8(). */
5583 if (i
.memshift
== 0)
5587 for (op
= 0; op
< i
.operands
; op
++)
5588 if (operand_type_check (i
.types
[op
], disp
)
5589 && i
.op
[op
].disps
->X_op
== O_constant
)
5591 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5593 i
.types
[op
].bitfield
.disp8
= 1;
5596 i
.types
[op
].bitfield
.disp8
= 0;
5605 /* Check if operands are valid for the instruction. Update VEX
5609 VEX_check_operands (const insn_template
*t
)
5611 if (i
.vec_encoding
== vex_encoding_evex
)
5613 /* This instruction must be encoded with EVEX prefix. */
5614 if (!is_evex_encoding (t
))
5616 i
.error
= unsupported
;
5622 if (!t
->opcode_modifier
.vex
)
5624 /* This instruction template doesn't have VEX prefix. */
5625 if (i
.vec_encoding
!= vex_encoding_default
)
5627 i
.error
= unsupported
;
5633 /* Check the special Imm4 cases; must be the first operand. */
5634 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5636 if (i
.op
[0].imms
->X_op
!= O_constant
5637 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5643 /* Turn off Imm<N> so that update_imm won't complain. */
5644 operand_type_set (&i
.types
[0], 0);
5650 static const insn_template
*
5651 match_template (char mnem_suffix
)
5653 /* Points to template once we've found it. */
5654 const insn_template
*t
;
5655 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5656 i386_operand_type overlap4
;
5657 unsigned int found_reverse_match
;
5658 i386_opcode_modifier suffix_check
;
5659 i386_operand_type operand_types
[MAX_OPERANDS
];
5660 int addr_prefix_disp
;
5662 unsigned int found_cpu_match
, size_match
;
5663 unsigned int check_register
;
5664 enum i386_error specific_error
= 0;
5666 #if MAX_OPERANDS != 5
5667 # error "MAX_OPERANDS must be 5."
5670 found_reverse_match
= 0;
5671 addr_prefix_disp
= -1;
5673 /* Prepare for mnemonic suffix check. */
5674 memset (&suffix_check
, 0, sizeof (suffix_check
));
5675 switch (mnem_suffix
)
5677 case BYTE_MNEM_SUFFIX
:
5678 suffix_check
.no_bsuf
= 1;
5680 case WORD_MNEM_SUFFIX
:
5681 suffix_check
.no_wsuf
= 1;
5683 case SHORT_MNEM_SUFFIX
:
5684 suffix_check
.no_ssuf
= 1;
5686 case LONG_MNEM_SUFFIX
:
5687 suffix_check
.no_lsuf
= 1;
5689 case QWORD_MNEM_SUFFIX
:
5690 suffix_check
.no_qsuf
= 1;
5693 /* NB: In Intel syntax, normally we can check for memory operand
5694 size when there is no mnemonic suffix. But jmp and call have
5695 2 different encodings with Dword memory operand size, one with
5696 No_ldSuf and the other without. i.suffix is set to
5697 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5698 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5699 suffix_check
.no_ldsuf
= 1;
5702 /* Must have right number of operands. */
5703 i
.error
= number_of_operands_mismatch
;
5705 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5707 addr_prefix_disp
= -1;
5708 found_reverse_match
= 0;
5710 if (i
.operands
!= t
->operands
)
5713 /* Check processor support. */
5714 i
.error
= unsupported
;
5715 found_cpu_match
= (cpu_flags_match (t
)
5716 == CPU_FLAGS_PERFECT_MATCH
);
5717 if (!found_cpu_match
)
5720 /* Check AT&T mnemonic. */
5721 i
.error
= unsupported_with_intel_mnemonic
;
5722 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5725 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5726 i
.error
= unsupported_syntax
;
5727 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5728 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5729 || (intel64
&& t
->opcode_modifier
.amd64
)
5730 || (!intel64
&& t
->opcode_modifier
.intel64
))
5733 /* Check the suffix. */
5734 i
.error
= invalid_instruction_suffix
;
5735 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5736 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5737 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5738 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5739 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5740 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5743 size_match
= operand_size_match (t
);
5747 /* This is intentionally not
5749 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5751 as the case of a missing * on the operand is accepted (perhaps with
5752 a warning, issued further down). */
5753 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5755 i
.error
= operand_type_mismatch
;
5759 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5760 operand_types
[j
] = t
->operand_types
[j
];
5762 /* In general, don't allow 64-bit operands in 32-bit mode. */
5763 if (i
.suffix
== QWORD_MNEM_SUFFIX
5764 && flag_code
!= CODE_64BIT
5766 ? (!t
->opcode_modifier
.ignoresize
5767 && !t
->opcode_modifier
.broadcast
5768 && !intel_float_operand (t
->name
))
5769 : intel_float_operand (t
->name
) != 2)
5770 && ((operand_types
[0].bitfield
.class != RegMMX
5771 && operand_types
[0].bitfield
.class != RegSIMD
)
5772 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5773 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5774 && (t
->base_opcode
!= 0x0fc7
5775 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5778 /* In general, don't allow 32-bit operands on pre-386. */
5779 else if (i
.suffix
== LONG_MNEM_SUFFIX
5780 && !cpu_arch_flags
.bitfield
.cpui386
5782 ? (!t
->opcode_modifier
.ignoresize
5783 && !intel_float_operand (t
->name
))
5784 : intel_float_operand (t
->name
) != 2)
5785 && ((operand_types
[0].bitfield
.class != RegMMX
5786 && operand_types
[0].bitfield
.class != RegSIMD
)
5787 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5788 && operand_types
[t
->operands
> 1].bitfield
.class
5792 /* Do not verify operands when there are none. */
5796 /* We've found a match; break out of loop. */
5800 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5801 into Disp32/Disp16/Disp32 operand. */
5802 if (i
.prefix
[ADDR_PREFIX
] != 0)
5804 /* There should be only one Disp operand. */
5808 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5810 if (operand_types
[j
].bitfield
.disp16
)
5812 addr_prefix_disp
= j
;
5813 operand_types
[j
].bitfield
.disp32
= 1;
5814 operand_types
[j
].bitfield
.disp16
= 0;
5820 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5822 if (operand_types
[j
].bitfield
.disp32
)
5824 addr_prefix_disp
= j
;
5825 operand_types
[j
].bitfield
.disp32
= 0;
5826 operand_types
[j
].bitfield
.disp16
= 1;
5832 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5834 if (operand_types
[j
].bitfield
.disp64
)
5836 addr_prefix_disp
= j
;
5837 operand_types
[j
].bitfield
.disp64
= 0;
5838 operand_types
[j
].bitfield
.disp32
= 1;
5846 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5847 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5850 /* We check register size if needed. */
5851 if (t
->opcode_modifier
.checkregsize
)
5853 check_register
= (1 << t
->operands
) - 1;
5855 check_register
&= ~(1 << i
.broadcast
->operand
);
5860 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5861 switch (t
->operands
)
5864 if (!operand_type_match (overlap0
, i
.types
[0]))
5868 /* xchg %eax, %eax is a special case. It is an alias for nop
5869 only in 32bit mode and we can use opcode 0x90. In 64bit
5870 mode, we can't use 0x90 for xchg %eax, %eax since it should
5871 zero-extend %eax to %rax. */
5872 if (flag_code
== CODE_64BIT
5873 && t
->base_opcode
== 0x90
5874 && i
.types
[0].bitfield
.instance
== Accum
5875 && i
.types
[0].bitfield
.dword
5876 && i
.types
[1].bitfield
.instance
== Accum
5877 && i
.types
[1].bitfield
.dword
)
5879 /* xrelease mov %eax, <disp> is another special case. It must not
5880 match the accumulator-only encoding of mov. */
5881 if (flag_code
!= CODE_64BIT
5883 && t
->base_opcode
== 0xa0
5884 && i
.types
[0].bitfield
.instance
== Accum
5885 && (i
.flags
[1] & Operand_Mem
))
5890 if (!(size_match
& MATCH_STRAIGHT
))
5892 /* Reverse direction of operands if swapping is possible in the first
5893 place (operands need to be symmetric) and
5894 - the load form is requested, and the template is a store form,
5895 - the store form is requested, and the template is a load form,
5896 - the non-default (swapped) form is requested. */
5897 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5898 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5899 && !operand_type_all_zero (&overlap1
))
5900 switch (i
.dir_encoding
)
5902 case dir_encoding_load
:
5903 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5904 || t
->opcode_modifier
.regmem
)
5908 case dir_encoding_store
:
5909 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5910 && !t
->opcode_modifier
.regmem
)
5914 case dir_encoding_swap
:
5917 case dir_encoding_default
:
5920 /* If we want store form, we skip the current load. */
5921 if ((i
.dir_encoding
== dir_encoding_store
5922 || i
.dir_encoding
== dir_encoding_swap
)
5923 && i
.mem_operands
== 0
5924 && t
->opcode_modifier
.load
)
5929 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5930 if (!operand_type_match (overlap0
, i
.types
[0])
5931 || !operand_type_match (overlap1
, i
.types
[1])
5932 || ((check_register
& 3) == 3
5933 && !operand_type_register_match (i
.types
[0],
5938 /* Check if other direction is valid ... */
5939 if (!t
->opcode_modifier
.d
)
5943 if (!(size_match
& MATCH_REVERSE
))
5945 /* Try reversing direction of operands. */
5946 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5947 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5948 if (!operand_type_match (overlap0
, i
.types
[0])
5949 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5951 && !operand_type_register_match (i
.types
[0],
5952 operand_types
[i
.operands
- 1],
5953 i
.types
[i
.operands
- 1],
5956 /* Does not match either direction. */
5959 /* found_reverse_match holds which of D or FloatR
5961 if (!t
->opcode_modifier
.d
)
5962 found_reverse_match
= 0;
5963 else if (operand_types
[0].bitfield
.tbyte
)
5964 found_reverse_match
= Opcode_FloatD
;
5965 else if (operand_types
[0].bitfield
.xmmword
5966 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5967 || operand_types
[0].bitfield
.class == RegMMX
5968 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
5969 || is_any_vex_encoding(t
))
5970 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5971 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5973 found_reverse_match
= Opcode_D
;
5974 if (t
->opcode_modifier
.floatr
)
5975 found_reverse_match
|= Opcode_FloatR
;
5979 /* Found a forward 2 operand match here. */
5980 switch (t
->operands
)
5983 overlap4
= operand_type_and (i
.types
[4],
5987 overlap3
= operand_type_and (i
.types
[3],
5991 overlap2
= operand_type_and (i
.types
[2],
5996 switch (t
->operands
)
5999 if (!operand_type_match (overlap4
, i
.types
[4])
6000 || !operand_type_register_match (i
.types
[3],
6007 if (!operand_type_match (overlap3
, i
.types
[3])
6008 || ((check_register
& 0xa) == 0xa
6009 && !operand_type_register_match (i
.types
[1],
6013 || ((check_register
& 0xc) == 0xc
6014 && !operand_type_register_match (i
.types
[2],
6021 /* Here we make use of the fact that there are no
6022 reverse match 3 operand instructions. */
6023 if (!operand_type_match (overlap2
, i
.types
[2])
6024 || ((check_register
& 5) == 5
6025 && !operand_type_register_match (i
.types
[0],
6029 || ((check_register
& 6) == 6
6030 && !operand_type_register_match (i
.types
[1],
6038 /* Found either forward/reverse 2, 3 or 4 operand match here:
6039 slip through to break. */
6041 if (!found_cpu_match
)
6044 /* Check if vector and VEX operands are valid. */
6045 if (check_VecOperands (t
) || VEX_check_operands (t
))
6047 specific_error
= i
.error
;
6051 /* We've found a match; break out of loop. */
6055 if (t
== current_templates
->end
)
6057 /* We found no match. */
6058 const char *err_msg
;
6059 switch (specific_error
? specific_error
: i
.error
)
6063 case operand_size_mismatch
:
6064 err_msg
= _("operand size mismatch");
6066 case operand_type_mismatch
:
6067 err_msg
= _("operand type mismatch");
6069 case register_type_mismatch
:
6070 err_msg
= _("register type mismatch");
6072 case number_of_operands_mismatch
:
6073 err_msg
= _("number of operands mismatch");
6075 case invalid_instruction_suffix
:
6076 err_msg
= _("invalid instruction suffix");
6079 err_msg
= _("constant doesn't fit in 4 bits");
6081 case unsupported_with_intel_mnemonic
:
6082 err_msg
= _("unsupported with Intel mnemonic");
6084 case unsupported_syntax
:
6085 err_msg
= _("unsupported syntax");
6088 as_bad (_("unsupported instruction `%s'"),
6089 current_templates
->start
->name
);
6091 case invalid_vsib_address
:
6092 err_msg
= _("invalid VSIB address");
6094 case invalid_vector_register_set
:
6095 err_msg
= _("mask, index, and destination registers must be distinct");
6097 case unsupported_vector_index_register
:
6098 err_msg
= _("unsupported vector index register");
6100 case unsupported_broadcast
:
6101 err_msg
= _("unsupported broadcast");
6103 case broadcast_needed
:
6104 err_msg
= _("broadcast is needed for operand of such type");
6106 case unsupported_masking
:
6107 err_msg
= _("unsupported masking");
6109 case mask_not_on_destination
:
6110 err_msg
= _("mask not on destination operand");
6112 case no_default_mask
:
6113 err_msg
= _("default mask isn't allowed");
6115 case unsupported_rc_sae
:
6116 err_msg
= _("unsupported static rounding/sae");
6118 case rc_sae_operand_not_last_imm
:
6120 err_msg
= _("RC/SAE operand must precede immediate operands");
6122 err_msg
= _("RC/SAE operand must follow immediate operands");
6124 case invalid_register_operand
:
6125 err_msg
= _("invalid register operand");
6128 as_bad (_("%s for `%s'"), err_msg
,
6129 current_templates
->start
->name
);
6133 if (!quiet_warnings
)
6136 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6137 as_warn (_("indirect %s without `*'"), t
->name
);
6139 if (t
->opcode_modifier
.isprefix
6140 && t
->opcode_modifier
.ignoresize
)
6142 /* Warn them that a data or address size prefix doesn't
6143 affect assembly of the next line of code. */
6144 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6148 /* Copy the template we found. */
6151 if (addr_prefix_disp
!= -1)
6152 i
.tm
.operand_types
[addr_prefix_disp
]
6153 = operand_types
[addr_prefix_disp
];
6155 if (found_reverse_match
)
6157 /* If we found a reverse match we must alter the opcode direction
6158 bit and clear/flip the regmem modifier one. found_reverse_match
6159 holds bits to change (different for int & float insns). */
6161 i
.tm
.base_opcode
^= found_reverse_match
;
6163 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6164 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6166 /* Certain SIMD insns have their load forms specified in the opcode
6167 table, and hence we need to _set_ RegMem instead of clearing it.
6168 We need to avoid setting the bit though on insns like KMOVW. */
6169 i
.tm
.opcode_modifier
.regmem
6170 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6171 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6172 && !i
.tm
.opcode_modifier
.regmem
;
6181 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6182 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6184 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6186 as_bad (_("`%s' operand %u must use `%ses' segment"),
6188 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6193 /* There's only ever one segment override allowed per instruction.
6194 This instruction possibly has a legal segment override on the
6195 second operand, so copy the segment to where non-string
6196 instructions store it, allowing common code. */
6197 i
.seg
[op
] = i
.seg
[1];
6203 process_suffix (void)
6205 /* If matched instruction specifies an explicit instruction mnemonic
6207 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6208 i
.suffix
= WORD_MNEM_SUFFIX
;
6209 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6210 i
.suffix
= LONG_MNEM_SUFFIX
;
6211 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6212 i
.suffix
= QWORD_MNEM_SUFFIX
;
6213 else if (i
.reg_operands
6214 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6216 /* If there's no instruction mnemonic suffix we try to invent one
6217 based on GPR operands. */
6220 /* We take i.suffix from the last register operand specified,
6221 Destination register type is more significant than source
6222 register type. crc32 in SSE4.2 prefers source register
6224 if (i
.tm
.base_opcode
== 0xf20f38f0
6225 && i
.types
[0].bitfield
.class == Reg
)
6227 if (i
.types
[0].bitfield
.byte
)
6228 i
.suffix
= BYTE_MNEM_SUFFIX
;
6229 else if (i
.types
[0].bitfield
.word
)
6230 i
.suffix
= WORD_MNEM_SUFFIX
;
6231 else if (i
.types
[0].bitfield
.dword
)
6232 i
.suffix
= LONG_MNEM_SUFFIX
;
6233 else if (i
.types
[0].bitfield
.qword
)
6234 i
.suffix
= QWORD_MNEM_SUFFIX
;
6241 if (i
.tm
.base_opcode
== 0xf20f38f0)
6243 /* We have to know the operand size for crc32. */
6244 as_bad (_("ambiguous memory operand size for `%s`"),
6249 for (op
= i
.operands
; --op
>= 0;)
6250 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6251 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6253 if (i
.types
[op
].bitfield
.class != Reg
)
6255 if (i
.types
[op
].bitfield
.byte
)
6256 i
.suffix
= BYTE_MNEM_SUFFIX
;
6257 else if (i
.types
[op
].bitfield
.word
)
6258 i
.suffix
= WORD_MNEM_SUFFIX
;
6259 else if (i
.types
[op
].bitfield
.dword
)
6260 i
.suffix
= LONG_MNEM_SUFFIX
;
6261 else if (i
.types
[op
].bitfield
.qword
)
6262 i
.suffix
= QWORD_MNEM_SUFFIX
;
6269 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6272 && i
.tm
.opcode_modifier
.ignoresize
6273 && i
.tm
.opcode_modifier
.no_bsuf
)
6275 else if (!check_byte_reg ())
6278 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6281 && i
.tm
.opcode_modifier
.ignoresize
6282 && i
.tm
.opcode_modifier
.no_lsuf
6283 && !i
.tm
.opcode_modifier
.todword
6284 && !i
.tm
.opcode_modifier
.toqword
)
6286 else if (!check_long_reg ())
6289 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6292 && i
.tm
.opcode_modifier
.ignoresize
6293 && i
.tm
.opcode_modifier
.no_qsuf
6294 && !i
.tm
.opcode_modifier
.todword
6295 && !i
.tm
.opcode_modifier
.toqword
)
6297 else if (!check_qword_reg ())
6300 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6303 && i
.tm
.opcode_modifier
.ignoresize
6304 && i
.tm
.opcode_modifier
.no_wsuf
)
6306 else if (!check_word_reg ())
6309 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6310 /* Do nothing if the instruction is going to ignore the prefix. */
6315 else if (i
.tm
.opcode_modifier
.defaultsize
6317 /* exclude fldenv/frstor/fsave/fstenv */
6318 && i
.tm
.opcode_modifier
.no_ssuf
6319 /* exclude sysret */
6320 && i
.tm
.base_opcode
!= 0x0f07)
6322 i
.suffix
= stackop_size
;
6323 if (stackop_size
== LONG_MNEM_SUFFIX
)
6325 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6326 .code16gcc directive to support 16-bit mode with
6327 32-bit address. For IRET without a suffix, generate
6328 16-bit IRET (opcode 0xcf) to return from an interrupt
6330 if (i
.tm
.base_opcode
== 0xcf)
6332 i
.suffix
= WORD_MNEM_SUFFIX
;
6333 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6335 /* Warn about changed behavior for segment register push/pop. */
6336 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6337 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6341 else if (intel_syntax
6343 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6344 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6345 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6346 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6347 && i
.tm
.extension_opcode
<= 3)))
6352 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6354 i
.suffix
= QWORD_MNEM_SUFFIX
;
6359 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6360 i
.suffix
= LONG_MNEM_SUFFIX
;
6363 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6364 i
.suffix
= WORD_MNEM_SUFFIX
;
6373 if (i
.tm
.opcode_modifier
.w
)
6375 as_bad (_("no instruction mnemonic suffix given and "
6376 "no register operands; can't size instruction"));
6382 unsigned int suffixes
;
6384 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6385 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6387 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6389 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6391 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6393 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6396 /* There are more than suffix matches. */
6397 if (i
.tm
.opcode_modifier
.w
6398 || ((suffixes
& (suffixes
- 1))
6399 && !i
.tm
.opcode_modifier
.defaultsize
6400 && !i
.tm
.opcode_modifier
.ignoresize
))
6402 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6408 /* Change the opcode based on the operand size given by i.suffix. */
6411 /* Size floating point instruction. */
6412 case LONG_MNEM_SUFFIX
:
6413 if (i
.tm
.opcode_modifier
.floatmf
)
6415 i
.tm
.base_opcode
^= 4;
6419 case WORD_MNEM_SUFFIX
:
6420 case QWORD_MNEM_SUFFIX
:
6421 /* It's not a byte, select word/dword operation. */
6422 if (i
.tm
.opcode_modifier
.w
)
6424 if (i
.tm
.opcode_modifier
.shortform
)
6425 i
.tm
.base_opcode
|= 8;
6427 i
.tm
.base_opcode
|= 1;
6430 case SHORT_MNEM_SUFFIX
:
6431 /* Now select between word & dword operations via the operand
6432 size prefix, except for instructions that will ignore this
6434 if (i
.reg_operands
> 0
6435 && i
.types
[0].bitfield
.class == Reg
6436 && i
.tm
.opcode_modifier
.addrprefixopreg
6437 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6438 || i
.operands
== 1))
6440 /* The address size override prefix changes the size of the
6442 if ((flag_code
== CODE_32BIT
6443 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6444 || (flag_code
!= CODE_32BIT
6445 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6446 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6449 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6450 && !i
.tm
.opcode_modifier
.ignoresize
6451 && !i
.tm
.opcode_modifier
.floatmf
6452 && !is_any_vex_encoding (&i
.tm
)
6453 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6454 || (flag_code
== CODE_64BIT
6455 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6457 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6459 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6460 prefix
= ADDR_PREFIX_OPCODE
;
6462 if (!add_prefix (prefix
))
6466 /* Set mode64 for an operand. */
6467 if (i
.suffix
== QWORD_MNEM_SUFFIX
6468 && flag_code
== CODE_64BIT
6469 && !i
.tm
.opcode_modifier
.norex64
6470 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6472 && ! (i
.operands
== 2
6473 && i
.tm
.base_opcode
== 0x90
6474 && i
.tm
.extension_opcode
== None
6475 && i
.types
[0].bitfield
.instance
== Accum
6476 && i
.types
[0].bitfield
.qword
6477 && i
.types
[1].bitfield
.instance
== Accum
6478 && i
.types
[1].bitfield
.qword
))
6484 if (i
.reg_operands
!= 0
6486 && i
.tm
.opcode_modifier
.addrprefixopreg
6487 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6489 /* Check invalid register operand when the address size override
6490 prefix changes the size of register operands. */
6492 enum { need_word
, need_dword
, need_qword
} need
;
6494 if (flag_code
== CODE_32BIT
)
6495 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6498 if (i
.prefix
[ADDR_PREFIX
])
6501 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6504 for (op
= 0; op
< i
.operands
; op
++)
6505 if (i
.types
[op
].bitfield
.class == Reg
6506 && ((need
== need_word
6507 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6508 || (need
== need_dword
6509 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6510 || (need
== need_qword
6511 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6513 as_bad (_("invalid register operand size for `%s'"),
6523 check_byte_reg (void)
6527 for (op
= i
.operands
; --op
>= 0;)
6529 /* Skip non-register operands. */
6530 if (i
.types
[op
].bitfield
.class != Reg
)
6533 /* If this is an eight bit register, it's OK. If it's the 16 or
6534 32 bit version of an eight bit register, we will just use the
6535 low portion, and that's OK too. */
6536 if (i
.types
[op
].bitfield
.byte
)
6539 /* I/O port address operands are OK too. */
6540 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6541 && i
.tm
.operand_types
[op
].bitfield
.word
)
6544 /* crc32 doesn't generate this warning. */
6545 if (i
.tm
.base_opcode
== 0xf20f38f0)
6548 if ((i
.types
[op
].bitfield
.word
6549 || i
.types
[op
].bitfield
.dword
6550 || i
.types
[op
].bitfield
.qword
)
6551 && i
.op
[op
].regs
->reg_num
< 4
6552 /* Prohibit these changes in 64bit mode, since the lowering
6553 would be more complicated. */
6554 && flag_code
!= CODE_64BIT
)
6556 #if REGISTER_WARNINGS
6557 if (!quiet_warnings
)
6558 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6560 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6561 ? REGNAM_AL
- REGNAM_AX
6562 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6564 i
.op
[op
].regs
->reg_name
,
6569 /* Any other register is bad. */
6570 if (i
.types
[op
].bitfield
.class == Reg
6571 || i
.types
[op
].bitfield
.class == RegMMX
6572 || i
.types
[op
].bitfield
.class == RegSIMD
6573 || i
.types
[op
].bitfield
.class == SReg
6574 || i
.types
[op
].bitfield
.class == RegCR
6575 || i
.types
[op
].bitfield
.class == RegDR
6576 || i
.types
[op
].bitfield
.class == RegTR
)
6578 as_bad (_("`%s%s' not allowed with `%s%c'"),
6580 i
.op
[op
].regs
->reg_name
,
6590 check_long_reg (void)
6594 for (op
= i
.operands
; --op
>= 0;)
6595 /* Skip non-register operands. */
6596 if (i
.types
[op
].bitfield
.class != Reg
)
6598 /* Reject eight bit registers, except where the template requires
6599 them. (eg. movzb) */
6600 else if (i
.types
[op
].bitfield
.byte
6601 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6602 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6603 && (i
.tm
.operand_types
[op
].bitfield
.word
6604 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6606 as_bad (_("`%s%s' not allowed with `%s%c'"),
6608 i
.op
[op
].regs
->reg_name
,
6613 /* Warn if the e prefix on a general reg is missing. */
6614 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6615 && i
.types
[op
].bitfield
.word
6616 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6617 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6618 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6620 /* Prohibit these changes in the 64bit mode, since the
6621 lowering is more complicated. */
6622 if (flag_code
== CODE_64BIT
)
6624 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6625 register_prefix
, i
.op
[op
].regs
->reg_name
,
6629 #if REGISTER_WARNINGS
6630 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6632 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6633 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6636 /* Warn if the r prefix on a general reg is present. */
6637 else if (i
.types
[op
].bitfield
.qword
6638 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6639 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6640 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6643 && i
.tm
.opcode_modifier
.toqword
6644 && i
.types
[0].bitfield
.class != RegSIMD
)
6646 /* Convert to QWORD. We want REX byte. */
6647 i
.suffix
= QWORD_MNEM_SUFFIX
;
6651 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6652 register_prefix
, i
.op
[op
].regs
->reg_name
,
6661 check_qword_reg (void)
6665 for (op
= i
.operands
; --op
>= 0; )
6666 /* Skip non-register operands. */
6667 if (i
.types
[op
].bitfield
.class != Reg
)
6669 /* Reject eight bit registers, except where the template requires
6670 them. (eg. movzb) */
6671 else if (i
.types
[op
].bitfield
.byte
6672 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6673 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6674 && (i
.tm
.operand_types
[op
].bitfield
.word
6675 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6677 as_bad (_("`%s%s' not allowed with `%s%c'"),
6679 i
.op
[op
].regs
->reg_name
,
6684 /* Warn if the r prefix on a general reg is missing. */
6685 else if ((i
.types
[op
].bitfield
.word
6686 || i
.types
[op
].bitfield
.dword
)
6687 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6688 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6689 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6691 /* Prohibit these changes in the 64bit mode, since the
6692 lowering is more complicated. */
6694 && i
.tm
.opcode_modifier
.todword
6695 && i
.types
[0].bitfield
.class != RegSIMD
)
6697 /* Convert to DWORD. We don't want REX byte. */
6698 i
.suffix
= LONG_MNEM_SUFFIX
;
6702 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6703 register_prefix
, i
.op
[op
].regs
->reg_name
,
6712 check_word_reg (void)
6715 for (op
= i
.operands
; --op
>= 0;)
6716 /* Skip non-register operands. */
6717 if (i
.types
[op
].bitfield
.class != Reg
)
6719 /* Reject eight bit registers, except where the template requires
6720 them. (eg. movzb) */
6721 else if (i
.types
[op
].bitfield
.byte
6722 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6723 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6724 && (i
.tm
.operand_types
[op
].bitfield
.word
6725 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6727 as_bad (_("`%s%s' not allowed with `%s%c'"),
6729 i
.op
[op
].regs
->reg_name
,
6734 /* Warn if the e or r prefix on a general reg is present. */
6735 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6736 && (i
.types
[op
].bitfield
.dword
6737 || i
.types
[op
].bitfield
.qword
)
6738 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6739 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6740 && i
.tm
.operand_types
[op
].bitfield
.word
)
6742 /* Prohibit these changes in the 64bit mode, since the
6743 lowering is more complicated. */
6744 if (flag_code
== CODE_64BIT
)
6746 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6747 register_prefix
, i
.op
[op
].regs
->reg_name
,
6751 #if REGISTER_WARNINGS
6752 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6754 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6755 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6762 update_imm (unsigned int j
)
6764 i386_operand_type overlap
= i
.types
[j
];
6765 if ((overlap
.bitfield
.imm8
6766 || overlap
.bitfield
.imm8s
6767 || overlap
.bitfield
.imm16
6768 || overlap
.bitfield
.imm32
6769 || overlap
.bitfield
.imm32s
6770 || overlap
.bitfield
.imm64
)
6771 && !operand_type_equal (&overlap
, &imm8
)
6772 && !operand_type_equal (&overlap
, &imm8s
)
6773 && !operand_type_equal (&overlap
, &imm16
)
6774 && !operand_type_equal (&overlap
, &imm32
)
6775 && !operand_type_equal (&overlap
, &imm32s
)
6776 && !operand_type_equal (&overlap
, &imm64
))
6780 i386_operand_type temp
;
6782 operand_type_set (&temp
, 0);
6783 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6785 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6786 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6788 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6789 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6790 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6792 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6793 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6796 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6799 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6800 || operand_type_equal (&overlap
, &imm16_32
)
6801 || operand_type_equal (&overlap
, &imm16_32s
))
6803 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6808 if (!operand_type_equal (&overlap
, &imm8
)
6809 && !operand_type_equal (&overlap
, &imm8s
)
6810 && !operand_type_equal (&overlap
, &imm16
)
6811 && !operand_type_equal (&overlap
, &imm32
)
6812 && !operand_type_equal (&overlap
, &imm32s
)
6813 && !operand_type_equal (&overlap
, &imm64
))
6815 as_bad (_("no instruction mnemonic suffix given; "
6816 "can't determine immediate size"));
6820 i
.types
[j
] = overlap
;
6830 /* Update the first 2 immediate operands. */
6831 n
= i
.operands
> 2 ? 2 : i
.operands
;
6834 for (j
= 0; j
< n
; j
++)
6835 if (update_imm (j
) == 0)
6838 /* The 3rd operand can't be immediate operand. */
6839 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6846 process_operands (void)
6848 /* Default segment register this instruction will use for memory
6849 accesses. 0 means unknown. This is only for optimizing out
6850 unnecessary segment overrides. */
6851 const seg_entry
*default_seg
= 0;
6853 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6855 unsigned int dupl
= i
.operands
;
6856 unsigned int dest
= dupl
- 1;
6859 /* The destination must be an xmm register. */
6860 gas_assert (i
.reg_operands
6861 && MAX_OPERANDS
> dupl
6862 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6864 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6865 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6867 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6869 /* Keep xmm0 for instructions with VEX prefix and 3
6871 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6872 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6877 /* We remove the first xmm0 and keep the number of
6878 operands unchanged, which in fact duplicates the
6880 for (j
= 1; j
< i
.operands
; j
++)
6882 i
.op
[j
- 1] = i
.op
[j
];
6883 i
.types
[j
- 1] = i
.types
[j
];
6884 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6885 i
.flags
[j
- 1] = i
.flags
[j
];
6889 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6891 gas_assert ((MAX_OPERANDS
- 1) > dupl
6892 && (i
.tm
.opcode_modifier
.vexsources
6895 /* Add the implicit xmm0 for instructions with VEX prefix
6897 for (j
= i
.operands
; j
> 0; j
--)
6899 i
.op
[j
] = i
.op
[j
- 1];
6900 i
.types
[j
] = i
.types
[j
- 1];
6901 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6902 i
.flags
[j
] = i
.flags
[j
- 1];
6905 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6906 i
.types
[0] = regxmm
;
6907 i
.tm
.operand_types
[0] = regxmm
;
6910 i
.reg_operands
+= 2;
6915 i
.op
[dupl
] = i
.op
[dest
];
6916 i
.types
[dupl
] = i
.types
[dest
];
6917 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6918 i
.flags
[dupl
] = i
.flags
[dest
];
6927 i
.op
[dupl
] = i
.op
[dest
];
6928 i
.types
[dupl
] = i
.types
[dest
];
6929 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6930 i
.flags
[dupl
] = i
.flags
[dest
];
6933 if (i
.tm
.opcode_modifier
.immext
)
6936 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6937 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6941 for (j
= 1; j
< i
.operands
; j
++)
6943 i
.op
[j
- 1] = i
.op
[j
];
6944 i
.types
[j
- 1] = i
.types
[j
];
6946 /* We need to adjust fields in i.tm since they are used by
6947 build_modrm_byte. */
6948 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6950 i
.flags
[j
- 1] = i
.flags
[j
];
6957 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6959 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6961 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6962 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
6963 regnum
= register_number (i
.op
[1].regs
);
6964 first_reg_in_group
= regnum
& ~3;
6965 last_reg_in_group
= first_reg_in_group
+ 3;
6966 if (regnum
!= first_reg_in_group
)
6967 as_warn (_("source register `%s%s' implicitly denotes"
6968 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6969 register_prefix
, i
.op
[1].regs
->reg_name
,
6970 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6971 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6974 else if (i
.tm
.opcode_modifier
.regkludge
)
6976 /* The imul $imm, %reg instruction is converted into
6977 imul $imm, %reg, %reg, and the clr %reg instruction
6978 is converted into xor %reg, %reg. */
6980 unsigned int first_reg_op
;
6982 if (operand_type_check (i
.types
[0], reg
))
6986 /* Pretend we saw the extra register operand. */
6987 gas_assert (i
.reg_operands
== 1
6988 && i
.op
[first_reg_op
+ 1].regs
== 0);
6989 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6990 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6995 if (i
.tm
.opcode_modifier
.modrm
)
6997 /* The opcode is completed (modulo i.tm.extension_opcode which
6998 must be put into the modrm byte). Now, we make the modrm and
6999 index base bytes based on all the info we've collected. */
7001 default_seg
= build_modrm_byte ();
7003 else if (i
.types
[0].bitfield
.class == SReg
)
7005 if (flag_code
!= CODE_64BIT
7006 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7007 && i
.op
[0].regs
->reg_num
== 1
7008 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7009 && i
.op
[0].regs
->reg_num
< 4)
7011 as_bad (_("you can't `%s %s%s'"),
7012 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7015 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7017 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7018 i
.tm
.opcode_length
= 2;
7020 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7022 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7026 else if (i
.tm
.opcode_modifier
.isstring
)
7028 /* For the string instructions that allow a segment override
7029 on one of their operands, the default segment is ds. */
7032 else if (i
.tm
.opcode_modifier
.shortform
)
7034 /* The register or float register operand is in operand
7036 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7038 /* Register goes in low 3 bits of opcode. */
7039 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7040 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7042 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7044 /* Warn about some common errors, but press on regardless.
7045 The first case can be generated by gcc (<= 2.8.1). */
7046 if (i
.operands
== 2)
7048 /* Reversed arguments on faddp, fsubp, etc. */
7049 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7050 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7051 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7055 /* Extraneous `l' suffix on fp insn. */
7056 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7057 register_prefix
, i
.op
[0].regs
->reg_name
);
7062 if (i
.tm
.base_opcode
== 0x8d /* lea */
7065 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7067 /* If a segment was explicitly specified, and the specified segment
7068 is not the default, use an opcode prefix to select it. If we
7069 never figured out what the default segment is, then default_seg
7070 will be zero at this point, and the specified segment prefix will
7072 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7074 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7080 static const seg_entry
*
7081 build_modrm_byte (void)
7083 const seg_entry
*default_seg
= 0;
7084 unsigned int source
, dest
;
7087 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7090 unsigned int nds
, reg_slot
;
7093 dest
= i
.operands
- 1;
7096 /* There are 2 kinds of instructions:
7097 1. 5 operands: 4 register operands or 3 register operands
7098 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7099 VexW0 or VexW1. The destination must be either XMM, YMM or
7101 2. 4 operands: 4 register operands or 3 register operands
7102 plus 1 memory operand, with VexXDS. */
7103 gas_assert ((i
.reg_operands
== 4
7104 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7105 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7106 && i
.tm
.opcode_modifier
.vexw
7107 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7109 /* If VexW1 is set, the first non-immediate operand is the source and
7110 the second non-immediate one is encoded in the immediate operand. */
7111 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7113 source
= i
.imm_operands
;
7114 reg_slot
= i
.imm_operands
+ 1;
7118 source
= i
.imm_operands
+ 1;
7119 reg_slot
= i
.imm_operands
;
7122 if (i
.imm_operands
== 0)
7124 /* When there is no immediate operand, generate an 8bit
7125 immediate operand to encode the first operand. */
7126 exp
= &im_expressions
[i
.imm_operands
++];
7127 i
.op
[i
.operands
].imms
= exp
;
7128 i
.types
[i
.operands
] = imm8
;
7131 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7132 exp
->X_op
= O_constant
;
7133 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7134 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7138 gas_assert (i
.imm_operands
== 1);
7139 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7140 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7142 /* Turn on Imm8 again so that output_imm will generate it. */
7143 i
.types
[0].bitfield
.imm8
= 1;
7145 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7146 i
.op
[0].imms
->X_add_number
7147 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7148 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7151 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7152 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7157 /* i.reg_operands MUST be the number of real register operands;
7158 implicit registers do not count. If there are 3 register
7159 operands, it must be a instruction with VexNDS. For a
7160 instruction with VexNDD, the destination register is encoded
7161 in VEX prefix. If there are 4 register operands, it must be
7162 a instruction with VEX prefix and 3 sources. */
7163 if (i
.mem_operands
== 0
7164 && ((i
.reg_operands
== 2
7165 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7166 || (i
.reg_operands
== 3
7167 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7168 || (i
.reg_operands
== 4 && vex_3_sources
)))
7176 /* When there are 3 operands, one of them may be immediate,
7177 which may be the first or the last operand. Otherwise,
7178 the first operand must be shift count register (cl) or it
7179 is an instruction with VexNDS. */
7180 gas_assert (i
.imm_operands
== 1
7181 || (i
.imm_operands
== 0
7182 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7183 || (i
.types
[0].bitfield
.instance
== RegC
7184 && i
.types
[0].bitfield
.byte
))));
7185 if (operand_type_check (i
.types
[0], imm
)
7186 || (i
.types
[0].bitfield
.instance
== RegC
7187 && i
.types
[0].bitfield
.byte
))
7193 /* When there are 4 operands, the first two must be 8bit
7194 immediate operands. The source operand will be the 3rd
7197 For instructions with VexNDS, if the first operand
7198 an imm8, the source operand is the 2nd one. If the last
7199 operand is imm8, the source operand is the first one. */
7200 gas_assert ((i
.imm_operands
== 2
7201 && i
.types
[0].bitfield
.imm8
7202 && i
.types
[1].bitfield
.imm8
)
7203 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7204 && i
.imm_operands
== 1
7205 && (i
.types
[0].bitfield
.imm8
7206 || i
.types
[i
.operands
- 1].bitfield
.imm8
7208 if (i
.imm_operands
== 2)
7212 if (i
.types
[0].bitfield
.imm8
)
7219 if (is_evex_encoding (&i
.tm
))
7221 /* For EVEX instructions, when there are 5 operands, the
7222 first one must be immediate operand. If the second one
7223 is immediate operand, the source operand is the 3th
7224 one. If the last one is immediate operand, the source
7225 operand is the 2nd one. */
7226 gas_assert (i
.imm_operands
== 2
7227 && i
.tm
.opcode_modifier
.sae
7228 && operand_type_check (i
.types
[0], imm
));
7229 if (operand_type_check (i
.types
[1], imm
))
7231 else if (operand_type_check (i
.types
[4], imm
))
7245 /* RC/SAE operand could be between DEST and SRC. That happens
7246 when one operand is GPR and the other one is XMM/YMM/ZMM
7248 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7251 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7253 /* For instructions with VexNDS, the register-only source
7254 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7255 register. It is encoded in VEX prefix. */
7257 i386_operand_type op
;
7260 /* Check register-only source operand when two source
7261 operands are swapped. */
7262 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7263 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7271 op
= i
.tm
.operand_types
[vvvv
];
7272 if ((dest
+ 1) >= i
.operands
7273 || ((op
.bitfield
.class != Reg
7274 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7275 && op
.bitfield
.class != RegSIMD
7276 && !operand_type_equal (&op
, ®mask
)))
7278 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7284 /* One of the register operands will be encoded in the i.rm.reg
7285 field, the other in the combined i.rm.mode and i.rm.regmem
7286 fields. If no form of this instruction supports a memory
7287 destination operand, then we assume the source operand may
7288 sometimes be a memory operand and so we need to store the
7289 destination in the i.rm.reg field. */
7290 if (!i
.tm
.opcode_modifier
.regmem
7291 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7293 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7294 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7295 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7296 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7297 i
.has_regmmx
= TRUE
;
7298 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7299 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7301 if (i
.types
[dest
].bitfield
.zmmword
7302 || i
.types
[source
].bitfield
.zmmword
)
7303 i
.has_regzmm
= TRUE
;
7304 else if (i
.types
[dest
].bitfield
.ymmword
7305 || i
.types
[source
].bitfield
.ymmword
)
7306 i
.has_regymm
= TRUE
;
7308 i
.has_regxmm
= TRUE
;
7310 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7312 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7314 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7316 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7321 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7322 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7323 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7325 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7327 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7329 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7332 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7334 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7337 add_prefix (LOCK_PREFIX_OPCODE
);
7341 { /* If it's not 2 reg operands... */
7346 unsigned int fake_zero_displacement
= 0;
7349 for (op
= 0; op
< i
.operands
; op
++)
7350 if (i
.flags
[op
] & Operand_Mem
)
7352 gas_assert (op
< i
.operands
);
7354 if (i
.tm
.opcode_modifier
.vecsib
)
7356 if (i
.index_reg
->reg_num
== RegIZ
)
7359 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7362 i
.sib
.base
= NO_BASE_REGISTER
;
7363 i
.sib
.scale
= i
.log2_scale_factor
;
7364 i
.types
[op
].bitfield
.disp8
= 0;
7365 i
.types
[op
].bitfield
.disp16
= 0;
7366 i
.types
[op
].bitfield
.disp64
= 0;
7367 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7369 /* Must be 32 bit */
7370 i
.types
[op
].bitfield
.disp32
= 1;
7371 i
.types
[op
].bitfield
.disp32s
= 0;
7375 i
.types
[op
].bitfield
.disp32
= 0;
7376 i
.types
[op
].bitfield
.disp32s
= 1;
7379 i
.sib
.index
= i
.index_reg
->reg_num
;
7380 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7382 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7388 if (i
.base_reg
== 0)
7391 if (!i
.disp_operands
)
7392 fake_zero_displacement
= 1;
7393 if (i
.index_reg
== 0)
7395 i386_operand_type newdisp
;
7397 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7398 /* Operand is just <disp> */
7399 if (flag_code
== CODE_64BIT
)
7401 /* 64bit mode overwrites the 32bit absolute
7402 addressing by RIP relative addressing and
7403 absolute addressing is encoded by one of the
7404 redundant SIB forms. */
7405 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7406 i
.sib
.base
= NO_BASE_REGISTER
;
7407 i
.sib
.index
= NO_INDEX_REGISTER
;
7408 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7410 else if ((flag_code
== CODE_16BIT
)
7411 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7413 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7418 i
.rm
.regmem
= NO_BASE_REGISTER
;
7421 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7422 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7424 else if (!i
.tm
.opcode_modifier
.vecsib
)
7426 /* !i.base_reg && i.index_reg */
7427 if (i
.index_reg
->reg_num
== RegIZ
)
7428 i
.sib
.index
= NO_INDEX_REGISTER
;
7430 i
.sib
.index
= i
.index_reg
->reg_num
;
7431 i
.sib
.base
= NO_BASE_REGISTER
;
7432 i
.sib
.scale
= i
.log2_scale_factor
;
7433 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7434 i
.types
[op
].bitfield
.disp8
= 0;
7435 i
.types
[op
].bitfield
.disp16
= 0;
7436 i
.types
[op
].bitfield
.disp64
= 0;
7437 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7439 /* Must be 32 bit */
7440 i
.types
[op
].bitfield
.disp32
= 1;
7441 i
.types
[op
].bitfield
.disp32s
= 0;
7445 i
.types
[op
].bitfield
.disp32
= 0;
7446 i
.types
[op
].bitfield
.disp32s
= 1;
7448 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7452 /* RIP addressing for 64bit mode. */
7453 else if (i
.base_reg
->reg_num
== RegIP
)
7455 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7456 i
.rm
.regmem
= NO_BASE_REGISTER
;
7457 i
.types
[op
].bitfield
.disp8
= 0;
7458 i
.types
[op
].bitfield
.disp16
= 0;
7459 i
.types
[op
].bitfield
.disp32
= 0;
7460 i
.types
[op
].bitfield
.disp32s
= 1;
7461 i
.types
[op
].bitfield
.disp64
= 0;
7462 i
.flags
[op
] |= Operand_PCrel
;
7463 if (! i
.disp_operands
)
7464 fake_zero_displacement
= 1;
7466 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7468 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7469 switch (i
.base_reg
->reg_num
)
7472 if (i
.index_reg
== 0)
7474 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7475 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7479 if (i
.index_reg
== 0)
7482 if (operand_type_check (i
.types
[op
], disp
) == 0)
7484 /* fake (%bp) into 0(%bp) */
7485 i
.types
[op
].bitfield
.disp8
= 1;
7486 fake_zero_displacement
= 1;
7489 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7490 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7492 default: /* (%si) -> 4 or (%di) -> 5 */
7493 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7495 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7497 else /* i.base_reg and 32/64 bit mode */
7499 if (flag_code
== CODE_64BIT
7500 && operand_type_check (i
.types
[op
], disp
))
7502 i
.types
[op
].bitfield
.disp16
= 0;
7503 i
.types
[op
].bitfield
.disp64
= 0;
7504 if (i
.prefix
[ADDR_PREFIX
] == 0)
7506 i
.types
[op
].bitfield
.disp32
= 0;
7507 i
.types
[op
].bitfield
.disp32s
= 1;
7511 i
.types
[op
].bitfield
.disp32
= 1;
7512 i
.types
[op
].bitfield
.disp32s
= 0;
7516 if (!i
.tm
.opcode_modifier
.vecsib
)
7517 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7518 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7520 i
.sib
.base
= i
.base_reg
->reg_num
;
7521 /* x86-64 ignores REX prefix bit here to avoid decoder
7523 if (!(i
.base_reg
->reg_flags
& RegRex
)
7524 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7525 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7527 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7529 fake_zero_displacement
= 1;
7530 i
.types
[op
].bitfield
.disp8
= 1;
7532 i
.sib
.scale
= i
.log2_scale_factor
;
7533 if (i
.index_reg
== 0)
7535 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7536 /* <disp>(%esp) becomes two byte modrm with no index
7537 register. We've already stored the code for esp
7538 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7539 Any base register besides %esp will not use the
7540 extra modrm byte. */
7541 i
.sib
.index
= NO_INDEX_REGISTER
;
7543 else if (!i
.tm
.opcode_modifier
.vecsib
)
7545 if (i
.index_reg
->reg_num
== RegIZ
)
7546 i
.sib
.index
= NO_INDEX_REGISTER
;
7548 i
.sib
.index
= i
.index_reg
->reg_num
;
7549 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7550 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7555 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7556 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7560 if (!fake_zero_displacement
7564 fake_zero_displacement
= 1;
7565 if (i
.disp_encoding
== disp_encoding_8bit
)
7566 i
.types
[op
].bitfield
.disp8
= 1;
7568 i
.types
[op
].bitfield
.disp32
= 1;
7570 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7574 if (fake_zero_displacement
)
7576 /* Fakes a zero displacement assuming that i.types[op]
7577 holds the correct displacement size. */
7580 gas_assert (i
.op
[op
].disps
== 0);
7581 exp
= &disp_expressions
[i
.disp_operands
++];
7582 i
.op
[op
].disps
= exp
;
7583 exp
->X_op
= O_constant
;
7584 exp
->X_add_number
= 0;
7585 exp
->X_add_symbol
= (symbolS
*) 0;
7586 exp
->X_op_symbol
= (symbolS
*) 0;
7594 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7596 if (operand_type_check (i
.types
[0], imm
))
7597 i
.vex
.register_specifier
= NULL
;
7600 /* VEX.vvvv encodes one of the sources when the first
7601 operand is not an immediate. */
7602 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7603 i
.vex
.register_specifier
= i
.op
[0].regs
;
7605 i
.vex
.register_specifier
= i
.op
[1].regs
;
7608 /* Destination is a XMM register encoded in the ModRM.reg
7610 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7611 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7614 /* ModRM.rm and VEX.B encodes the other source. */
7615 if (!i
.mem_operands
)
7619 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7620 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7622 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7624 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7628 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7630 i
.vex
.register_specifier
= i
.op
[2].regs
;
7631 if (!i
.mem_operands
)
7634 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7635 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7639 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7640 (if any) based on i.tm.extension_opcode. Again, we must be
7641 careful to make sure that segment/control/debug/test/MMX
7642 registers are coded into the i.rm.reg field. */
7643 else if (i
.reg_operands
)
7646 unsigned int vex_reg
= ~0;
7648 for (op
= 0; op
< i
.operands
; op
++)
7650 if (i
.types
[op
].bitfield
.class == Reg
7651 || i
.types
[op
].bitfield
.class == RegBND
7652 || i
.types
[op
].bitfield
.class == RegMask
7653 || i
.types
[op
].bitfield
.class == SReg
7654 || i
.types
[op
].bitfield
.class == RegCR
7655 || i
.types
[op
].bitfield
.class == RegDR
7656 || i
.types
[op
].bitfield
.class == RegTR
)
7658 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7660 if (i
.types
[op
].bitfield
.zmmword
)
7661 i
.has_regzmm
= TRUE
;
7662 else if (i
.types
[op
].bitfield
.ymmword
)
7663 i
.has_regymm
= TRUE
;
7665 i
.has_regxmm
= TRUE
;
7668 if (i
.types
[op
].bitfield
.class == RegMMX
)
7670 i
.has_regmmx
= TRUE
;
7677 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7679 /* For instructions with VexNDS, the register-only
7680 source operand is encoded in VEX prefix. */
7681 gas_assert (mem
!= (unsigned int) ~0);
7686 gas_assert (op
< i
.operands
);
7690 /* Check register-only source operand when two source
7691 operands are swapped. */
7692 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7693 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7697 gas_assert (mem
== (vex_reg
+ 1)
7698 && op
< i
.operands
);
7703 gas_assert (vex_reg
< i
.operands
);
7707 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7709 /* For instructions with VexNDD, the register destination
7710 is encoded in VEX prefix. */
7711 if (i
.mem_operands
== 0)
7713 /* There is no memory operand. */
7714 gas_assert ((op
+ 2) == i
.operands
);
7719 /* There are only 2 non-immediate operands. */
7720 gas_assert (op
< i
.imm_operands
+ 2
7721 && i
.operands
== i
.imm_operands
+ 2);
7722 vex_reg
= i
.imm_operands
+ 1;
7726 gas_assert (op
< i
.operands
);
7728 if (vex_reg
!= (unsigned int) ~0)
7730 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7732 if ((type
->bitfield
.class != Reg
7733 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7734 && type
->bitfield
.class != RegSIMD
7735 && !operand_type_equal (type
, ®mask
))
7738 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7741 /* Don't set OP operand twice. */
7744 /* If there is an extension opcode to put here, the
7745 register number must be put into the regmem field. */
7746 if (i
.tm
.extension_opcode
!= None
)
7748 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7749 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7751 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7756 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7757 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7759 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7764 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7765 must set it to 3 to indicate this is a register operand
7766 in the regmem field. */
7767 if (!i
.mem_operands
)
7771 /* Fill in i.rm.reg field with extension opcode (if any). */
7772 if (i
.tm
.extension_opcode
!= None
)
7773 i
.rm
.reg
= i
.tm
.extension_opcode
;
7779 output_branch (void)
7785 relax_substateT subtype
;
7789 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7790 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7793 if (i
.prefix
[DATA_PREFIX
] != 0)
7799 /* Pentium4 branch hints. */
7800 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7801 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7806 if (i
.prefix
[REX_PREFIX
] != 0)
7812 /* BND prefixed jump. */
7813 if (i
.prefix
[BND_PREFIX
] != 0)
7815 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7819 if (i
.prefixes
!= 0 && !intel_syntax
)
7820 as_warn (_("skipping prefixes on this instruction"));
7822 /* It's always a symbol; End frag & setup for relax.
7823 Make sure there is enough room in this frag for the largest
7824 instruction we may generate in md_convert_frag. This is 2
7825 bytes for the opcode and room for the prefix and largest
7827 frag_grow (prefix
+ 2 + 4);
7828 /* Prefix and 1 opcode byte go in fr_fix. */
7829 p
= frag_more (prefix
+ 1);
7830 if (i
.prefix
[DATA_PREFIX
] != 0)
7831 *p
++ = DATA_PREFIX_OPCODE
;
7832 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7833 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7834 *p
++ = i
.prefix
[SEG_PREFIX
];
7835 if (i
.prefix
[REX_PREFIX
] != 0)
7836 *p
++ = i
.prefix
[REX_PREFIX
];
7837 *p
= i
.tm
.base_opcode
;
7839 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7840 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7841 else if (cpu_arch_flags
.bitfield
.cpui386
)
7842 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7844 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7847 sym
= i
.op
[0].disps
->X_add_symbol
;
7848 off
= i
.op
[0].disps
->X_add_number
;
7850 if (i
.op
[0].disps
->X_op
!= O_constant
7851 && i
.op
[0].disps
->X_op
!= O_symbol
)
7853 /* Handle complex expressions. */
7854 sym
= make_expr_symbol (i
.op
[0].disps
);
7858 /* 1 possible extra opcode + 4 byte displacement go in var part.
7859 Pass reloc in fr_var. */
7860 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7864 /* Return TRUE iff PLT32 relocation should be used for branching to
7868 need_plt32_p (symbolS
*s
)
7870 /* PLT32 relocation is ELF only. */
7875 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7876 krtld support it. */
7880 /* Since there is no need to prepare for PLT branch on x86-64, we
7881 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7882 be used as a marker for 32-bit PC-relative branches. */
7886 /* Weak or undefined symbol need PLT32 relocation. */
7887 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7890 /* Non-global symbol doesn't need PLT32 relocation. */
7891 if (! S_IS_EXTERNAL (s
))
7894 /* Other global symbols need PLT32 relocation. NB: Symbol with
7895 non-default visibilities are treated as normal global symbol
7896 so that PLT32 relocation can be used as a marker for 32-bit
7897 PC-relative branches. It is useful for linker relaxation. */
7908 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7910 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
7912 /* This is a loop or jecxz type instruction. */
7914 if (i
.prefix
[ADDR_PREFIX
] != 0)
7916 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7919 /* Pentium4 branch hints. */
7920 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7921 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7923 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7932 if (flag_code
== CODE_16BIT
)
7935 if (i
.prefix
[DATA_PREFIX
] != 0)
7937 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7947 if (i
.prefix
[REX_PREFIX
] != 0)
7949 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7953 /* BND prefixed jump. */
7954 if (i
.prefix
[BND_PREFIX
] != 0)
7956 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7960 if (i
.prefixes
!= 0 && !intel_syntax
)
7961 as_warn (_("skipping prefixes on this instruction"));
7963 p
= frag_more (i
.tm
.opcode_length
+ size
);
7964 switch (i
.tm
.opcode_length
)
7967 *p
++ = i
.tm
.base_opcode
>> 8;
7970 *p
++ = i
.tm
.base_opcode
;
7976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7978 && jump_reloc
== NO_RELOC
7979 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7980 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7983 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7985 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7986 i
.op
[0].disps
, 1, jump_reloc
);
7988 /* All jumps handled here are signed, but don't use a signed limit
7989 check for 32 and 16 bit jumps as we want to allow wrap around at
7990 4G and 64k respectively. */
7992 fixP
->fx_signed
= 1;
7996 output_interseg_jump (void)
8004 if (flag_code
== CODE_16BIT
)
8008 if (i
.prefix
[DATA_PREFIX
] != 0)
8014 if (i
.prefix
[REX_PREFIX
] != 0)
8024 if (i
.prefixes
!= 0 && !intel_syntax
)
8025 as_warn (_("skipping prefixes on this instruction"));
8027 /* 1 opcode; 2 segment; offset */
8028 p
= frag_more (prefix
+ 1 + 2 + size
);
8030 if (i
.prefix
[DATA_PREFIX
] != 0)
8031 *p
++ = DATA_PREFIX_OPCODE
;
8033 if (i
.prefix
[REX_PREFIX
] != 0)
8034 *p
++ = i
.prefix
[REX_PREFIX
];
8036 *p
++ = i
.tm
.base_opcode
;
8037 if (i
.op
[1].imms
->X_op
== O_constant
)
8039 offsetT n
= i
.op
[1].imms
->X_add_number
;
8042 && !fits_in_unsigned_word (n
)
8043 && !fits_in_signed_word (n
))
8045 as_bad (_("16-bit jump out of range"));
8048 md_number_to_chars (p
, n
, size
);
8051 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8052 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8053 if (i
.op
[0].imms
->X_op
!= O_constant
)
8054 as_bad (_("can't handle non absolute segment in `%s'"),
8056 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8064 asection
*seg
= now_seg
;
8065 subsegT subseg
= now_subseg
;
8067 unsigned int alignment
, align_size_1
;
8068 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8069 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8070 unsigned int padding
;
8072 if (!IS_ELF
|| !x86_used_note
)
8075 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8077 /* The .note.gnu.property section layout:
8079 Field Length Contents
8082 n_descsz 4 The note descriptor size
8083 n_type 4 NT_GNU_PROPERTY_TYPE_0
8085 n_desc n_descsz The program property array
8089 /* Create the .note.gnu.property section. */
8090 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8091 bfd_set_section_flags (sec
,
8098 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8109 bfd_set_section_alignment (sec
, alignment
);
8110 elf_section_type (sec
) = SHT_NOTE
;
8112 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8114 isa_1_descsz_raw
= 4 + 4 + 4;
8115 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8116 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8118 feature_2_descsz_raw
= isa_1_descsz
;
8119 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8121 feature_2_descsz_raw
+= 4 + 4 + 4;
8122 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8123 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8126 descsz
= feature_2_descsz
;
8127 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8128 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8130 /* Write n_namsz. */
8131 md_number_to_chars (p
, (valueT
) 4, 4);
8133 /* Write n_descsz. */
8134 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8137 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8140 memcpy (p
+ 4 * 3, "GNU", 4);
8142 /* Write 4-byte type. */
8143 md_number_to_chars (p
+ 4 * 4,
8144 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8146 /* Write 4-byte data size. */
8147 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8149 /* Write 4-byte data. */
8150 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8152 /* Zero out paddings. */
8153 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8155 memset (p
+ 4 * 7, 0, padding
);
8157 /* Write 4-byte type. */
8158 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8159 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8161 /* Write 4-byte data size. */
8162 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8164 /* Write 4-byte data. */
8165 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8166 (valueT
) x86_feature_2_used
, 4);
8168 /* Zero out paddings. */
8169 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8171 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8173 /* We probably can't restore the current segment, for there likely
8176 subseg_set (seg
, subseg
);
8181 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8182 const char *frag_now_ptr
)
8184 unsigned int len
= 0;
8186 if (start_frag
!= frag_now
)
8188 const fragS
*fr
= start_frag
;
8193 } while (fr
&& fr
!= frag_now
);
8196 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8202 fragS
*insn_start_frag
;
8203 offsetT insn_start_off
;
8205 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8206 if (IS_ELF
&& x86_used_note
)
8208 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8209 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8210 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8211 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8212 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8213 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8214 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8215 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8216 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8217 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8218 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8219 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8220 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8221 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8222 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8223 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8224 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8225 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8226 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8227 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8228 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8230 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8231 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8233 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8235 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8239 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8240 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8241 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8242 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8243 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8244 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8245 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8246 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8247 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8248 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8249 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8250 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8251 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8252 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8253 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8254 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8255 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8256 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8257 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8259 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8260 || i
.tm
.cpu_flags
.bitfield
.cpu287
8261 || i
.tm
.cpu_flags
.bitfield
.cpu387
8262 || i
.tm
.cpu_flags
.bitfield
.cpu687
8263 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8264 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8266 || i
.tm
.base_opcode
== 0xf77 /* emms */
8267 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8268 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8270 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8272 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8274 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8275 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8276 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8277 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8278 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8279 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8280 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8281 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8282 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8286 /* Tie dwarf2 debug info to the address at the start of the insn.
8287 We can't do this after the insn has been output as the current
8288 frag may have been closed off. eg. by frag_var. */
8289 dwarf2_emit_insn (0);
8291 insn_start_frag
= frag_now
;
8292 insn_start_off
= frag_now_fix ();
8295 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8297 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8298 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8300 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8301 output_interseg_jump ();
8304 /* Output normal instructions here. */
8308 unsigned int prefix
;
8311 && (i
.tm
.base_opcode
== 0xfaee8
8312 || i
.tm
.base_opcode
== 0xfaef0
8313 || i
.tm
.base_opcode
== 0xfaef8))
8315 /* Encode lfence, mfence, and sfence as
8316 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8317 offsetT val
= 0x240483f0ULL
;
8319 md_number_to_chars (p
, val
, 5);
8323 /* Some processors fail on LOCK prefix. This options makes
8324 assembler ignore LOCK prefix and serves as a workaround. */
8325 if (omit_lock_prefix
)
8327 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8329 i
.prefix
[LOCK_PREFIX
] = 0;
8332 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8333 don't need the explicit prefix. */
8334 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8336 switch (i
.tm
.opcode_length
)
8339 if (i
.tm
.base_opcode
& 0xff000000)
8341 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8342 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8343 || prefix
!= REPE_PREFIX_OPCODE
8344 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8345 add_prefix (prefix
);
8349 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8351 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8352 add_prefix (prefix
);
8358 /* Check for pseudo prefixes. */
8359 as_bad_where (insn_start_frag
->fr_file
,
8360 insn_start_frag
->fr_line
,
8361 _("pseudo prefix without instruction"));
8367 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8368 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8369 R_X86_64_GOTTPOFF relocation so that linker can safely
8370 perform IE->LE optimization. */
8371 if (x86_elf_abi
== X86_64_X32_ABI
8373 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8374 && i
.prefix
[REX_PREFIX
] == 0)
8375 add_prefix (REX_OPCODE
);
8378 /* The prefix bytes. */
8379 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8381 FRAG_APPEND_1_CHAR (*q
);
8385 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8390 /* REX byte is encoded in VEX prefix. */
8394 FRAG_APPEND_1_CHAR (*q
);
8397 /* There should be no other prefixes for instructions
8402 /* For EVEX instructions i.vrex should become 0 after
8403 build_evex_prefix. For VEX instructions upper 16 registers
8404 aren't available, so VREX should be 0. */
8407 /* Now the VEX prefix. */
8408 p
= frag_more (i
.vex
.length
);
8409 for (j
= 0; j
< i
.vex
.length
; j
++)
8410 p
[j
] = i
.vex
.bytes
[j
];
8413 /* Now the opcode; be careful about word order here! */
8414 if (i
.tm
.opcode_length
== 1)
8416 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8420 switch (i
.tm
.opcode_length
)
8424 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8425 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8429 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8439 /* Put out high byte first: can't use md_number_to_chars! */
8440 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8441 *p
= i
.tm
.base_opcode
& 0xff;
8444 /* Now the modrm byte and sib byte (if present). */
8445 if (i
.tm
.opcode_modifier
.modrm
)
8447 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8450 /* If i.rm.regmem == ESP (4)
8451 && i.rm.mode != (Register mode)
8453 ==> need second modrm byte. */
8454 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8456 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8457 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8459 | i
.sib
.scale
<< 6));
8462 if (i
.disp_operands
)
8463 output_disp (insn_start_frag
, insn_start_off
);
8466 output_imm (insn_start_frag
, insn_start_off
);
8469 * frag_now_fix () returning plain abs_section_offset when we're in the
8470 * absolute section, and abs_section_offset not getting updated as data
8471 * gets added to the frag breaks the logic below.
8473 if (now_seg
!= absolute_section
)
8475 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8477 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8485 pi ("" /*line*/, &i
);
8487 #endif /* DEBUG386 */
8490 /* Return the size of the displacement operand N. */
8493 disp_size (unsigned int n
)
8497 if (i
.types
[n
].bitfield
.disp64
)
8499 else if (i
.types
[n
].bitfield
.disp8
)
8501 else if (i
.types
[n
].bitfield
.disp16
)
8506 /* Return the size of the immediate operand N. */
8509 imm_size (unsigned int n
)
8512 if (i
.types
[n
].bitfield
.imm64
)
8514 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8516 else if (i
.types
[n
].bitfield
.imm16
)
8522 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8527 for (n
= 0; n
< i
.operands
; n
++)
8529 if (operand_type_check (i
.types
[n
], disp
))
8531 if (i
.op
[n
].disps
->X_op
== O_constant
)
8533 int size
= disp_size (n
);
8534 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8536 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8538 p
= frag_more (size
);
8539 md_number_to_chars (p
, val
, size
);
8543 enum bfd_reloc_code_real reloc_type
;
8544 int size
= disp_size (n
);
8545 int sign
= i
.types
[n
].bitfield
.disp32s
;
8546 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8549 /* We can't have 8 bit displacement here. */
8550 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8552 /* The PC relative address is computed relative
8553 to the instruction boundary, so in case immediate
8554 fields follows, we need to adjust the value. */
8555 if (pcrel
&& i
.imm_operands
)
8560 for (n1
= 0; n1
< i
.operands
; n1
++)
8561 if (operand_type_check (i
.types
[n1
], imm
))
8563 /* Only one immediate is allowed for PC
8564 relative address. */
8565 gas_assert (sz
== 0);
8567 i
.op
[n
].disps
->X_add_number
-= sz
;
8569 /* We should find the immediate. */
8570 gas_assert (sz
!= 0);
8573 p
= frag_more (size
);
8574 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8576 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8577 && (((reloc_type
== BFD_RELOC_32
8578 || reloc_type
== BFD_RELOC_X86_64_32S
8579 || (reloc_type
== BFD_RELOC_64
8581 && (i
.op
[n
].disps
->X_op
== O_symbol
8582 || (i
.op
[n
].disps
->X_op
== O_add
8583 && ((symbol_get_value_expression
8584 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8586 || reloc_type
== BFD_RELOC_32_PCREL
))
8590 reloc_type
= BFD_RELOC_386_GOTPC
;
8591 i
.op
[n
].imms
->X_add_number
+=
8592 encoding_length (insn_start_frag
, insn_start_off
, p
);
8594 else if (reloc_type
== BFD_RELOC_64
)
8595 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8597 /* Don't do the adjustment for x86-64, as there
8598 the pcrel addressing is relative to the _next_
8599 insn, and that is taken care of in other code. */
8600 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8602 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8603 size
, i
.op
[n
].disps
, pcrel
,
8605 /* Check for "call/jmp *mem", "mov mem, %reg",
8606 "test %reg, mem" and "binop mem, %reg" where binop
8607 is one of adc, add, and, cmp, or, sbb, sub, xor
8608 instructions without data prefix. Always generate
8609 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8610 if (i
.prefix
[DATA_PREFIX
] == 0
8611 && (generate_relax_relocations
8614 && i
.rm
.regmem
== 5))
8616 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8617 && ((i
.operands
== 1
8618 && i
.tm
.base_opcode
== 0xff
8619 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8621 && (i
.tm
.base_opcode
== 0x8b
8622 || i
.tm
.base_opcode
== 0x85
8623 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8627 fixP
->fx_tcbit
= i
.rex
!= 0;
8629 && (i
.base_reg
->reg_num
== RegIP
))
8630 fixP
->fx_tcbit2
= 1;
8633 fixP
->fx_tcbit2
= 1;
8641 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8646 for (n
= 0; n
< i
.operands
; n
++)
8648 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8649 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8652 if (operand_type_check (i
.types
[n
], imm
))
8654 if (i
.op
[n
].imms
->X_op
== O_constant
)
8656 int size
= imm_size (n
);
8659 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8661 p
= frag_more (size
);
8662 md_number_to_chars (p
, val
, size
);
8666 /* Not absolute_section.
8667 Need a 32-bit fixup (don't support 8bit
8668 non-absolute imms). Try to support other
8670 enum bfd_reloc_code_real reloc_type
;
8671 int size
= imm_size (n
);
8674 if (i
.types
[n
].bitfield
.imm32s
8675 && (i
.suffix
== QWORD_MNEM_SUFFIX
8676 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8681 p
= frag_more (size
);
8682 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8684 /* This is tough to explain. We end up with this one if we
8685 * have operands that look like
8686 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8687 * obtain the absolute address of the GOT, and it is strongly
8688 * preferable from a performance point of view to avoid using
8689 * a runtime relocation for this. The actual sequence of
8690 * instructions often look something like:
8695 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8697 * The call and pop essentially return the absolute address
8698 * of the label .L66 and store it in %ebx. The linker itself
8699 * will ultimately change the first operand of the addl so
8700 * that %ebx points to the GOT, but to keep things simple, the
8701 * .o file must have this operand set so that it generates not
8702 * the absolute address of .L66, but the absolute address of
8703 * itself. This allows the linker itself simply treat a GOTPC
8704 * relocation as asking for a pcrel offset to the GOT to be
8705 * added in, and the addend of the relocation is stored in the
8706 * operand field for the instruction itself.
8708 * Our job here is to fix the operand so that it would add
8709 * the correct offset so that %ebx would point to itself. The
8710 * thing that is tricky is that .-.L66 will point to the
8711 * beginning of the instruction, so we need to further modify
8712 * the operand so that it will point to itself. There are
8713 * other cases where you have something like:
8715 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8717 * and here no correction would be required. Internally in
8718 * the assembler we treat operands of this form as not being
8719 * pcrel since the '.' is explicitly mentioned, and I wonder
8720 * whether it would simplify matters to do it this way. Who
8721 * knows. In earlier versions of the PIC patches, the
8722 * pcrel_adjust field was used to store the correction, but
8723 * since the expression is not pcrel, I felt it would be
8724 * confusing to do it this way. */
8726 if ((reloc_type
== BFD_RELOC_32
8727 || reloc_type
== BFD_RELOC_X86_64_32S
8728 || reloc_type
== BFD_RELOC_64
)
8730 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8731 && (i
.op
[n
].imms
->X_op
== O_symbol
8732 || (i
.op
[n
].imms
->X_op
== O_add
8733 && ((symbol_get_value_expression
8734 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8738 reloc_type
= BFD_RELOC_386_GOTPC
;
8740 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8742 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8743 i
.op
[n
].imms
->X_add_number
+=
8744 encoding_length (insn_start_frag
, insn_start_off
, p
);
8746 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8747 i
.op
[n
].imms
, 0, reloc_type
);
8753 /* x86_cons_fix_new is called via the expression parsing code when a
8754 reloc is needed. We use this hook to get the correct .got reloc. */
8755 static int cons_sign
= -1;
8758 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8759 expressionS
*exp
, bfd_reloc_code_real_type r
)
8761 r
= reloc (len
, 0, cons_sign
, r
);
8764 if (exp
->X_op
== O_secrel
)
8766 exp
->X_op
= O_symbol
;
8767 r
= BFD_RELOC_32_SECREL
;
8771 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8774 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8775 purpose of the `.dc.a' internal pseudo-op. */
8778 x86_address_bytes (void)
8780 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8782 return stdoutput
->arch_info
->bits_per_address
/ 8;
8785 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8787 # define lex_got(reloc, adjust, types) NULL
8789 /* Parse operands of the form
8790 <symbol>@GOTOFF+<nnn>
8791 and similar .plt or .got references.
8793 If we find one, set up the correct relocation in RELOC and copy the
8794 input string, minus the `@GOTOFF' into a malloc'd buffer for
8795 parsing by the calling routine. Return this buffer, and if ADJUST
8796 is non-null set it to the length of the string we removed from the
8797 input line. Otherwise return NULL. */
8799 lex_got (enum bfd_reloc_code_real
*rel
,
8801 i386_operand_type
*types
)
8803 /* Some of the relocations depend on the size of what field is to
8804 be relocated. But in our callers i386_immediate and i386_displacement
8805 we don't yet know the operand size (this will be set by insn
8806 matching). Hence we record the word32 relocation here,
8807 and adjust the reloc according to the real size in reloc(). */
8808 static const struct {
8811 const enum bfd_reloc_code_real rel
[2];
8812 const i386_operand_type types64
;
8814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8815 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8817 OPERAND_TYPE_IMM32_64
},
8819 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8820 BFD_RELOC_X86_64_PLTOFF64
},
8821 OPERAND_TYPE_IMM64
},
8822 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8823 BFD_RELOC_X86_64_PLT32
},
8824 OPERAND_TYPE_IMM32_32S_DISP32
},
8825 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8826 BFD_RELOC_X86_64_GOTPLT64
},
8827 OPERAND_TYPE_IMM64_DISP64
},
8828 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8829 BFD_RELOC_X86_64_GOTOFF64
},
8830 OPERAND_TYPE_IMM64_DISP64
},
8831 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8832 BFD_RELOC_X86_64_GOTPCREL
},
8833 OPERAND_TYPE_IMM32_32S_DISP32
},
8834 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8835 BFD_RELOC_X86_64_TLSGD
},
8836 OPERAND_TYPE_IMM32_32S_DISP32
},
8837 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8838 _dummy_first_bfd_reloc_code_real
},
8839 OPERAND_TYPE_NONE
},
8840 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8841 BFD_RELOC_X86_64_TLSLD
},
8842 OPERAND_TYPE_IMM32_32S_DISP32
},
8843 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8844 BFD_RELOC_X86_64_GOTTPOFF
},
8845 OPERAND_TYPE_IMM32_32S_DISP32
},
8846 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8847 BFD_RELOC_X86_64_TPOFF32
},
8848 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8849 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8850 _dummy_first_bfd_reloc_code_real
},
8851 OPERAND_TYPE_NONE
},
8852 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8853 BFD_RELOC_X86_64_DTPOFF32
},
8854 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8855 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8856 _dummy_first_bfd_reloc_code_real
},
8857 OPERAND_TYPE_NONE
},
8858 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8859 _dummy_first_bfd_reloc_code_real
},
8860 OPERAND_TYPE_NONE
},
8861 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8862 BFD_RELOC_X86_64_GOT32
},
8863 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8864 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8865 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8866 OPERAND_TYPE_IMM32_32S_DISP32
},
8867 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8868 BFD_RELOC_X86_64_TLSDESC_CALL
},
8869 OPERAND_TYPE_IMM32_32S_DISP32
},
8874 #if defined (OBJ_MAYBE_ELF)
8879 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8880 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8883 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8885 int len
= gotrel
[j
].len
;
8886 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8888 if (gotrel
[j
].rel
[object_64bit
] != 0)
8891 char *tmpbuf
, *past_reloc
;
8893 *rel
= gotrel
[j
].rel
[object_64bit
];
8897 if (flag_code
!= CODE_64BIT
)
8899 types
->bitfield
.imm32
= 1;
8900 types
->bitfield
.disp32
= 1;
8903 *types
= gotrel
[j
].types64
;
8906 if (j
!= 0 && GOT_symbol
== NULL
)
8907 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8909 /* The length of the first part of our input line. */
8910 first
= cp
- input_line_pointer
;
8912 /* The second part goes from after the reloc token until
8913 (and including) an end_of_line char or comma. */
8914 past_reloc
= cp
+ 1 + len
;
8916 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8918 second
= cp
+ 1 - past_reloc
;
8920 /* Allocate and copy string. The trailing NUL shouldn't
8921 be necessary, but be safe. */
8922 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8923 memcpy (tmpbuf
, input_line_pointer
, first
);
8924 if (second
!= 0 && *past_reloc
!= ' ')
8925 /* Replace the relocation token with ' ', so that
8926 errors like foo@GOTOFF1 will be detected. */
8927 tmpbuf
[first
++] = ' ';
8929 /* Increment length by 1 if the relocation token is
8934 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8935 tmpbuf
[first
+ second
] = '\0';
8939 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8940 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8945 /* Might be a symbol version string. Don't as_bad here. */
8954 /* Parse operands of the form
8955 <symbol>@SECREL32+<nnn>
8957 If we find one, set up the correct relocation in RELOC and copy the
8958 input string, minus the `@SECREL32' into a malloc'd buffer for
8959 parsing by the calling routine. Return this buffer, and if ADJUST
8960 is non-null set it to the length of the string we removed from the
8961 input line. Otherwise return NULL.
8963 This function is copied from the ELF version above adjusted for PE targets. */
8966 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8967 int *adjust ATTRIBUTE_UNUSED
,
8968 i386_operand_type
*types
)
8974 const enum bfd_reloc_code_real rel
[2];
8975 const i386_operand_type types64
;
8979 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8980 BFD_RELOC_32_SECREL
},
8981 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8987 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8988 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8991 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8993 int len
= gotrel
[j
].len
;
8995 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8997 if (gotrel
[j
].rel
[object_64bit
] != 0)
9000 char *tmpbuf
, *past_reloc
;
9002 *rel
= gotrel
[j
].rel
[object_64bit
];
9008 if (flag_code
!= CODE_64BIT
)
9010 types
->bitfield
.imm32
= 1;
9011 types
->bitfield
.disp32
= 1;
9014 *types
= gotrel
[j
].types64
;
9017 /* The length of the first part of our input line. */
9018 first
= cp
- input_line_pointer
;
9020 /* The second part goes from after the reloc token until
9021 (and including) an end_of_line char or comma. */
9022 past_reloc
= cp
+ 1 + len
;
9024 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9026 second
= cp
+ 1 - past_reloc
;
9028 /* Allocate and copy string. The trailing NUL shouldn't
9029 be necessary, but be safe. */
9030 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9031 memcpy (tmpbuf
, input_line_pointer
, first
);
9032 if (second
!= 0 && *past_reloc
!= ' ')
9033 /* Replace the relocation token with ' ', so that
9034 errors like foo@SECLREL321 will be detected. */
9035 tmpbuf
[first
++] = ' ';
9036 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9037 tmpbuf
[first
+ second
] = '\0';
9041 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9042 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9047 /* Might be a symbol version string. Don't as_bad here. */
9053 bfd_reloc_code_real_type
9054 x86_cons (expressionS
*exp
, int size
)
9056 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9058 intel_syntax
= -intel_syntax
;
9061 if (size
== 4 || (object_64bit
&& size
== 8))
9063 /* Handle @GOTOFF and the like in an expression. */
9065 char *gotfree_input_line
;
9068 save
= input_line_pointer
;
9069 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9070 if (gotfree_input_line
)
9071 input_line_pointer
= gotfree_input_line
;
9075 if (gotfree_input_line
)
9077 /* expression () has merrily parsed up to the end of line,
9078 or a comma - in the wrong buffer. Transfer how far
9079 input_line_pointer has moved to the right buffer. */
9080 input_line_pointer
= (save
9081 + (input_line_pointer
- gotfree_input_line
)
9083 free (gotfree_input_line
);
9084 if (exp
->X_op
== O_constant
9085 || exp
->X_op
== O_absent
9086 || exp
->X_op
== O_illegal
9087 || exp
->X_op
== O_register
9088 || exp
->X_op
== O_big
)
9090 char c
= *input_line_pointer
;
9091 *input_line_pointer
= 0;
9092 as_bad (_("missing or invalid expression `%s'"), save
);
9093 *input_line_pointer
= c
;
9095 else if ((got_reloc
== BFD_RELOC_386_PLT32
9096 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9097 && exp
->X_op
!= O_symbol
)
9099 char c
= *input_line_pointer
;
9100 *input_line_pointer
= 0;
9101 as_bad (_("invalid PLT expression `%s'"), save
);
9102 *input_line_pointer
= c
;
9109 intel_syntax
= -intel_syntax
;
9112 i386_intel_simplify (exp
);
9118 signed_cons (int size
)
9120 if (flag_code
== CODE_64BIT
)
9128 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9135 if (exp
.X_op
== O_symbol
)
9136 exp
.X_op
= O_secrel
;
9138 emit_expr (&exp
, 4);
9140 while (*input_line_pointer
++ == ',');
9142 input_line_pointer
--;
9143 demand_empty_rest_of_line ();
9147 /* Handle Vector operations. */
9150 check_VecOperations (char *op_string
, char *op_end
)
9152 const reg_entry
*mask
;
9157 && (op_end
== NULL
|| op_string
< op_end
))
9160 if (*op_string
== '{')
9164 /* Check broadcasts. */
9165 if (strncmp (op_string
, "1to", 3) == 0)
9170 goto duplicated_vec_op
;
9173 if (*op_string
== '8')
9175 else if (*op_string
== '4')
9177 else if (*op_string
== '2')
9179 else if (*op_string
== '1'
9180 && *(op_string
+1) == '6')
9187 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9192 broadcast_op
.type
= bcst_type
;
9193 broadcast_op
.operand
= this_operand
;
9194 broadcast_op
.bytes
= 0;
9195 i
.broadcast
= &broadcast_op
;
9197 /* Check masking operation. */
9198 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9200 /* k0 can't be used for write mask. */
9201 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9203 as_bad (_("`%s%s' can't be used for write mask"),
9204 register_prefix
, mask
->reg_name
);
9210 mask_op
.mask
= mask
;
9211 mask_op
.zeroing
= 0;
9212 mask_op
.operand
= this_operand
;
9218 goto duplicated_vec_op
;
9220 i
.mask
->mask
= mask
;
9222 /* Only "{z}" is allowed here. No need to check
9223 zeroing mask explicitly. */
9224 if (i
.mask
->operand
!= this_operand
)
9226 as_bad (_("invalid write mask `%s'"), saved
);
9233 /* Check zeroing-flag for masking operation. */
9234 else if (*op_string
== 'z')
9238 mask_op
.mask
= NULL
;
9239 mask_op
.zeroing
= 1;
9240 mask_op
.operand
= this_operand
;
9245 if (i
.mask
->zeroing
)
9248 as_bad (_("duplicated `%s'"), saved
);
9252 i
.mask
->zeroing
= 1;
9254 /* Only "{%k}" is allowed here. No need to check mask
9255 register explicitly. */
9256 if (i
.mask
->operand
!= this_operand
)
9258 as_bad (_("invalid zeroing-masking `%s'"),
9267 goto unknown_vec_op
;
9269 if (*op_string
!= '}')
9271 as_bad (_("missing `}' in `%s'"), saved
);
9276 /* Strip whitespace since the addition of pseudo prefixes
9277 changed how the scrubber treats '{'. */
9278 if (is_space_char (*op_string
))
9284 /* We don't know this one. */
9285 as_bad (_("unknown vector operation: `%s'"), saved
);
9289 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9291 as_bad (_("zeroing-masking only allowed with write mask"));
9299 i386_immediate (char *imm_start
)
9301 char *save_input_line_pointer
;
9302 char *gotfree_input_line
;
9305 i386_operand_type types
;
9307 operand_type_set (&types
, ~0);
9309 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9311 as_bad (_("at most %d immediate operands are allowed"),
9312 MAX_IMMEDIATE_OPERANDS
);
9316 exp
= &im_expressions
[i
.imm_operands
++];
9317 i
.op
[this_operand
].imms
= exp
;
9319 if (is_space_char (*imm_start
))
9322 save_input_line_pointer
= input_line_pointer
;
9323 input_line_pointer
= imm_start
;
9325 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9326 if (gotfree_input_line
)
9327 input_line_pointer
= gotfree_input_line
;
9329 exp_seg
= expression (exp
);
9333 /* Handle vector operations. */
9334 if (*input_line_pointer
== '{')
9336 input_line_pointer
= check_VecOperations (input_line_pointer
,
9338 if (input_line_pointer
== NULL
)
9342 if (*input_line_pointer
)
9343 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9345 input_line_pointer
= save_input_line_pointer
;
9346 if (gotfree_input_line
)
9348 free (gotfree_input_line
);
9350 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9351 exp
->X_op
= O_illegal
;
9354 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9358 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9359 i386_operand_type types
, const char *imm_start
)
9361 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9364 as_bad (_("missing or invalid immediate expression `%s'"),
9368 else if (exp
->X_op
== O_constant
)
9370 /* Size it properly later. */
9371 i
.types
[this_operand
].bitfield
.imm64
= 1;
9372 /* If not 64bit, sign extend val. */
9373 if (flag_code
!= CODE_64BIT
9374 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9376 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9378 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9379 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9380 && exp_seg
!= absolute_section
9381 && exp_seg
!= text_section
9382 && exp_seg
!= data_section
9383 && exp_seg
!= bss_section
9384 && exp_seg
!= undefined_section
9385 && !bfd_is_com_section (exp_seg
))
9387 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9391 else if (!intel_syntax
&& exp_seg
== reg_section
)
9394 as_bad (_("illegal immediate register operand %s"), imm_start
);
9399 /* This is an address. The size of the address will be
9400 determined later, depending on destination register,
9401 suffix, or the default for the section. */
9402 i
.types
[this_operand
].bitfield
.imm8
= 1;
9403 i
.types
[this_operand
].bitfield
.imm16
= 1;
9404 i
.types
[this_operand
].bitfield
.imm32
= 1;
9405 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9406 i
.types
[this_operand
].bitfield
.imm64
= 1;
9407 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9415 i386_scale (char *scale
)
9418 char *save
= input_line_pointer
;
9420 input_line_pointer
= scale
;
9421 val
= get_absolute_expression ();
9426 i
.log2_scale_factor
= 0;
9429 i
.log2_scale_factor
= 1;
9432 i
.log2_scale_factor
= 2;
9435 i
.log2_scale_factor
= 3;
9439 char sep
= *input_line_pointer
;
9441 *input_line_pointer
= '\0';
9442 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9444 *input_line_pointer
= sep
;
9445 input_line_pointer
= save
;
9449 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9451 as_warn (_("scale factor of %d without an index register"),
9452 1 << i
.log2_scale_factor
);
9453 i
.log2_scale_factor
= 0;
9455 scale
= input_line_pointer
;
9456 input_line_pointer
= save
;
9461 i386_displacement (char *disp_start
, char *disp_end
)
9465 char *save_input_line_pointer
;
9466 char *gotfree_input_line
;
9468 i386_operand_type bigdisp
, types
= anydisp
;
9471 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9473 as_bad (_("at most %d displacement operands are allowed"),
9474 MAX_MEMORY_OPERANDS
);
9478 operand_type_set (&bigdisp
, 0);
9480 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9481 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9483 bigdisp
.bitfield
.disp32
= 1;
9484 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9485 if (flag_code
== CODE_64BIT
)
9489 bigdisp
.bitfield
.disp32s
= 1;
9490 bigdisp
.bitfield
.disp64
= 1;
9493 else if ((flag_code
== CODE_16BIT
) ^ override
)
9495 bigdisp
.bitfield
.disp32
= 0;
9496 bigdisp
.bitfield
.disp16
= 1;
9501 /* For PC-relative branches, the width of the displacement
9502 is dependent upon data size, not address size. */
9503 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9504 if (flag_code
== CODE_64BIT
)
9506 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9507 bigdisp
.bitfield
.disp16
= 1;
9510 bigdisp
.bitfield
.disp32
= 1;
9511 bigdisp
.bitfield
.disp32s
= 1;
9517 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9519 : LONG_MNEM_SUFFIX
));
9520 bigdisp
.bitfield
.disp32
= 1;
9521 if ((flag_code
== CODE_16BIT
) ^ override
)
9523 bigdisp
.bitfield
.disp32
= 0;
9524 bigdisp
.bitfield
.disp16
= 1;
9528 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9531 exp
= &disp_expressions
[i
.disp_operands
];
9532 i
.op
[this_operand
].disps
= exp
;
9534 save_input_line_pointer
= input_line_pointer
;
9535 input_line_pointer
= disp_start
;
9536 END_STRING_AND_SAVE (disp_end
);
9538 #ifndef GCC_ASM_O_HACK
9539 #define GCC_ASM_O_HACK 0
9542 END_STRING_AND_SAVE (disp_end
+ 1);
9543 if (i
.types
[this_operand
].bitfield
.baseIndex
9544 && displacement_string_end
[-1] == '+')
9546 /* This hack is to avoid a warning when using the "o"
9547 constraint within gcc asm statements.
9550 #define _set_tssldt_desc(n,addr,limit,type) \
9551 __asm__ __volatile__ ( \
9553 "movw %w1,2+%0\n\t" \
9555 "movb %b1,4+%0\n\t" \
9556 "movb %4,5+%0\n\t" \
9557 "movb $0,6+%0\n\t" \
9558 "movb %h1,7+%0\n\t" \
9560 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9562 This works great except that the output assembler ends
9563 up looking a bit weird if it turns out that there is
9564 no offset. You end up producing code that looks like:
9577 So here we provide the missing zero. */
9579 *displacement_string_end
= '0';
9582 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9583 if (gotfree_input_line
)
9584 input_line_pointer
= gotfree_input_line
;
9586 exp_seg
= expression (exp
);
9589 if (*input_line_pointer
)
9590 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9592 RESTORE_END_STRING (disp_end
+ 1);
9594 input_line_pointer
= save_input_line_pointer
;
9595 if (gotfree_input_line
)
9597 free (gotfree_input_line
);
9599 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9600 exp
->X_op
= O_illegal
;
9603 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9605 RESTORE_END_STRING (disp_end
);
9611 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9612 i386_operand_type types
, const char *disp_start
)
9614 i386_operand_type bigdisp
;
9617 /* We do this to make sure that the section symbol is in
9618 the symbol table. We will ultimately change the relocation
9619 to be relative to the beginning of the section. */
9620 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9621 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9622 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9624 if (exp
->X_op
!= O_symbol
)
9627 if (S_IS_LOCAL (exp
->X_add_symbol
)
9628 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9629 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9630 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9631 exp
->X_op
= O_subtract
;
9632 exp
->X_op_symbol
= GOT_symbol
;
9633 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9634 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9635 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9636 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9638 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9641 else if (exp
->X_op
== O_absent
9642 || exp
->X_op
== O_illegal
9643 || exp
->X_op
== O_big
)
9646 as_bad (_("missing or invalid displacement expression `%s'"),
9651 else if (flag_code
== CODE_64BIT
9652 && !i
.prefix
[ADDR_PREFIX
]
9653 && exp
->X_op
== O_constant
)
9655 /* Since displacement is signed extended to 64bit, don't allow
9656 disp32 and turn off disp32s if they are out of range. */
9657 i
.types
[this_operand
].bitfield
.disp32
= 0;
9658 if (!fits_in_signed_long (exp
->X_add_number
))
9660 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9661 if (i
.types
[this_operand
].bitfield
.baseindex
)
9663 as_bad (_("0x%lx out range of signed 32bit displacement"),
9664 (long) exp
->X_add_number
);
9670 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9671 else if (exp
->X_op
!= O_constant
9672 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9673 && exp_seg
!= absolute_section
9674 && exp_seg
!= text_section
9675 && exp_seg
!= data_section
9676 && exp_seg
!= bss_section
9677 && exp_seg
!= undefined_section
9678 && !bfd_is_com_section (exp_seg
))
9680 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9685 /* Check if this is a displacement only operand. */
9686 bigdisp
= i
.types
[this_operand
];
9687 bigdisp
.bitfield
.disp8
= 0;
9688 bigdisp
.bitfield
.disp16
= 0;
9689 bigdisp
.bitfield
.disp32
= 0;
9690 bigdisp
.bitfield
.disp32s
= 0;
9691 bigdisp
.bitfield
.disp64
= 0;
9692 if (operand_type_all_zero (&bigdisp
))
9693 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9699 /* Return the active addressing mode, taking address override and
9700 registers forming the address into consideration. Update the
9701 address override prefix if necessary. */
9703 static enum flag_code
9704 i386_addressing_mode (void)
9706 enum flag_code addr_mode
;
9708 if (i
.prefix
[ADDR_PREFIX
])
9709 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9712 addr_mode
= flag_code
;
9714 #if INFER_ADDR_PREFIX
9715 if (i
.mem_operands
== 0)
9717 /* Infer address prefix from the first memory operand. */
9718 const reg_entry
*addr_reg
= i
.base_reg
;
9720 if (addr_reg
== NULL
)
9721 addr_reg
= i
.index_reg
;
9725 if (addr_reg
->reg_type
.bitfield
.dword
)
9726 addr_mode
= CODE_32BIT
;
9727 else if (flag_code
!= CODE_64BIT
9728 && addr_reg
->reg_type
.bitfield
.word
)
9729 addr_mode
= CODE_16BIT
;
9731 if (addr_mode
!= flag_code
)
9733 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9735 /* Change the size of any displacement too. At most one
9736 of Disp16 or Disp32 is set.
9737 FIXME. There doesn't seem to be any real need for
9738 separate Disp16 and Disp32 flags. The same goes for
9739 Imm16 and Imm32. Removing them would probably clean
9740 up the code quite a lot. */
9741 if (flag_code
!= CODE_64BIT
9742 && (i
.types
[this_operand
].bitfield
.disp16
9743 || i
.types
[this_operand
].bitfield
.disp32
))
9744 i
.types
[this_operand
]
9745 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9755 /* Make sure the memory operand we've been dealt is valid.
9756 Return 1 on success, 0 on a failure. */
9759 i386_index_check (const char *operand_string
)
9761 const char *kind
= "base/index";
9762 enum flag_code addr_mode
= i386_addressing_mode ();
9764 if (current_templates
->start
->opcode_modifier
.isstring
9765 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9766 && (current_templates
->end
[-1].opcode_modifier
.isstring
9769 /* Memory operands of string insns are special in that they only allow
9770 a single register (rDI, rSI, or rBX) as their memory address. */
9771 const reg_entry
*expected_reg
;
9772 static const char *di_si
[][2] =
9778 static const char *bx
[] = { "ebx", "bx", "rbx" };
9780 kind
= "string address";
9782 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9784 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
9788 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
9789 || ((!i
.mem_operands
!= !intel_syntax
)
9790 && current_templates
->end
[-1].operand_types
[1]
9791 .bitfield
.baseindex
))
9793 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
9796 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9798 if (i
.base_reg
!= expected_reg
9800 || operand_type_check (i
.types
[this_operand
], disp
))
9802 /* The second memory operand must have the same size as
9806 && !((addr_mode
== CODE_64BIT
9807 && i
.base_reg
->reg_type
.bitfield
.qword
)
9808 || (addr_mode
== CODE_32BIT
9809 ? i
.base_reg
->reg_type
.bitfield
.dword
9810 : i
.base_reg
->reg_type
.bitfield
.word
)))
9813 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9815 intel_syntax
? '[' : '(',
9817 expected_reg
->reg_name
,
9818 intel_syntax
? ']' : ')');
9825 as_bad (_("`%s' is not a valid %s expression"),
9826 operand_string
, kind
);
9831 if (addr_mode
!= CODE_16BIT
)
9833 /* 32-bit/64-bit checks. */
9835 && ((addr_mode
== CODE_64BIT
9836 ? !i
.base_reg
->reg_type
.bitfield
.qword
9837 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9838 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9839 || i
.base_reg
->reg_num
== RegIZ
))
9841 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9842 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9843 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9844 && ((addr_mode
== CODE_64BIT
9845 ? !i
.index_reg
->reg_type
.bitfield
.qword
9846 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9847 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9850 /* bndmk, bndldx, and bndstx have special restrictions. */
9851 if (current_templates
->start
->base_opcode
== 0xf30f1b
9852 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9854 /* They cannot use RIP-relative addressing. */
9855 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9857 as_bad (_("`%s' cannot be used here"), operand_string
);
9861 /* bndldx and bndstx ignore their scale factor. */
9862 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9863 && i
.log2_scale_factor
)
9864 as_warn (_("register scaling is being ignored here"));
9869 /* 16-bit checks. */
9871 && (!i
.base_reg
->reg_type
.bitfield
.word
9872 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9874 && (!i
.index_reg
->reg_type
.bitfield
.word
9875 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9877 && i
.base_reg
->reg_num
< 6
9878 && i
.index_reg
->reg_num
>= 6
9879 && i
.log2_scale_factor
== 0))))
9886 /* Handle vector immediates. */
9889 RC_SAE_immediate (const char *imm_start
)
9891 unsigned int match_found
, j
;
9892 const char *pstr
= imm_start
;
9900 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9902 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9906 rc_op
.type
= RC_NamesTable
[j
].type
;
9907 rc_op
.operand
= this_operand
;
9908 i
.rounding
= &rc_op
;
9912 as_bad (_("duplicated `%s'"), imm_start
);
9915 pstr
+= RC_NamesTable
[j
].len
;
9925 as_bad (_("Missing '}': '%s'"), imm_start
);
9928 /* RC/SAE immediate string should contain nothing more. */;
9931 as_bad (_("Junk after '}': '%s'"), imm_start
);
9935 exp
= &im_expressions
[i
.imm_operands
++];
9936 i
.op
[this_operand
].imms
= exp
;
9938 exp
->X_op
= O_constant
;
9939 exp
->X_add_number
= 0;
9940 exp
->X_add_symbol
= (symbolS
*) 0;
9941 exp
->X_op_symbol
= (symbolS
*) 0;
9943 i
.types
[this_operand
].bitfield
.imm8
= 1;
9947 /* Only string instructions can have a second memory operand, so
9948 reduce current_templates to just those if it contains any. */
9950 maybe_adjust_templates (void)
9952 const insn_template
*t
;
9954 gas_assert (i
.mem_operands
== 1);
9956 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9957 if (t
->opcode_modifier
.isstring
)
9960 if (t
< current_templates
->end
)
9962 static templates aux_templates
;
9963 bfd_boolean recheck
;
9965 aux_templates
.start
= t
;
9966 for (; t
< current_templates
->end
; ++t
)
9967 if (!t
->opcode_modifier
.isstring
)
9969 aux_templates
.end
= t
;
9971 /* Determine whether to re-check the first memory operand. */
9972 recheck
= (aux_templates
.start
!= current_templates
->start
9973 || t
!= current_templates
->end
);
9975 current_templates
= &aux_templates
;
9980 if (i
.memop1_string
!= NULL
9981 && i386_index_check (i
.memop1_string
) == 0)
9990 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9994 i386_att_operand (char *operand_string
)
9998 char *op_string
= operand_string
;
10000 if (is_space_char (*op_string
))
10003 /* We check for an absolute prefix (differentiating,
10004 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10005 if (*op_string
== ABSOLUTE_PREFIX
)
10008 if (is_space_char (*op_string
))
10010 i
.jumpabsolute
= TRUE
;
10013 /* Check if operand is a register. */
10014 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10016 i386_operand_type temp
;
10018 /* Check for a segment override by searching for ':' after a
10019 segment register. */
10020 op_string
= end_op
;
10021 if (is_space_char (*op_string
))
10023 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10025 switch (r
->reg_num
)
10028 i
.seg
[i
.mem_operands
] = &es
;
10031 i
.seg
[i
.mem_operands
] = &cs
;
10034 i
.seg
[i
.mem_operands
] = &ss
;
10037 i
.seg
[i
.mem_operands
] = &ds
;
10040 i
.seg
[i
.mem_operands
] = &fs
;
10043 i
.seg
[i
.mem_operands
] = &gs
;
10047 /* Skip the ':' and whitespace. */
10049 if (is_space_char (*op_string
))
10052 if (!is_digit_char (*op_string
)
10053 && !is_identifier_char (*op_string
)
10054 && *op_string
!= '('
10055 && *op_string
!= ABSOLUTE_PREFIX
)
10057 as_bad (_("bad memory operand `%s'"), op_string
);
10060 /* Handle case of %es:*foo. */
10061 if (*op_string
== ABSOLUTE_PREFIX
)
10064 if (is_space_char (*op_string
))
10066 i
.jumpabsolute
= TRUE
;
10068 goto do_memory_reference
;
10071 /* Handle vector operations. */
10072 if (*op_string
== '{')
10074 op_string
= check_VecOperations (op_string
, NULL
);
10075 if (op_string
== NULL
)
10081 as_bad (_("junk `%s' after register"), op_string
);
10084 temp
= r
->reg_type
;
10085 temp
.bitfield
.baseindex
= 0;
10086 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10088 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10089 i
.op
[this_operand
].regs
= r
;
10092 else if (*op_string
== REGISTER_PREFIX
)
10094 as_bad (_("bad register name `%s'"), op_string
);
10097 else if (*op_string
== IMMEDIATE_PREFIX
)
10100 if (i
.jumpabsolute
)
10102 as_bad (_("immediate operand illegal with absolute jump"));
10105 if (!i386_immediate (op_string
))
10108 else if (RC_SAE_immediate (operand_string
))
10110 /* If it is a RC or SAE immediate, do nothing. */
10113 else if (is_digit_char (*op_string
)
10114 || is_identifier_char (*op_string
)
10115 || *op_string
== '"'
10116 || *op_string
== '(')
10118 /* This is a memory reference of some sort. */
10121 /* Start and end of displacement string expression (if found). */
10122 char *displacement_string_start
;
10123 char *displacement_string_end
;
10126 do_memory_reference
:
10127 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10129 if ((i
.mem_operands
== 1
10130 && !current_templates
->start
->opcode_modifier
.isstring
)
10131 || i
.mem_operands
== 2)
10133 as_bad (_("too many memory references for `%s'"),
10134 current_templates
->start
->name
);
10138 /* Check for base index form. We detect the base index form by
10139 looking for an ')' at the end of the operand, searching
10140 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10142 base_string
= op_string
+ strlen (op_string
);
10144 /* Handle vector operations. */
10145 vop_start
= strchr (op_string
, '{');
10146 if (vop_start
&& vop_start
< base_string
)
10148 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10150 base_string
= vop_start
;
10154 if (is_space_char (*base_string
))
10157 /* If we only have a displacement, set-up for it to be parsed later. */
10158 displacement_string_start
= op_string
;
10159 displacement_string_end
= base_string
+ 1;
10161 if (*base_string
== ')')
10164 unsigned int parens_balanced
= 1;
10165 /* We've already checked that the number of left & right ()'s are
10166 equal, so this loop will not be infinite. */
10170 if (*base_string
== ')')
10172 if (*base_string
== '(')
10175 while (parens_balanced
);
10177 temp_string
= base_string
;
10179 /* Skip past '(' and whitespace. */
10181 if (is_space_char (*base_string
))
10184 if (*base_string
== ','
10185 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10188 displacement_string_end
= temp_string
;
10190 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10194 base_string
= end_op
;
10195 if (is_space_char (*base_string
))
10199 /* There may be an index reg or scale factor here. */
10200 if (*base_string
== ',')
10203 if (is_space_char (*base_string
))
10206 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10209 base_string
= end_op
;
10210 if (is_space_char (*base_string
))
10212 if (*base_string
== ',')
10215 if (is_space_char (*base_string
))
10218 else if (*base_string
!= ')')
10220 as_bad (_("expecting `,' or `)' "
10221 "after index register in `%s'"),
10226 else if (*base_string
== REGISTER_PREFIX
)
10228 end_op
= strchr (base_string
, ',');
10231 as_bad (_("bad register name `%s'"), base_string
);
10235 /* Check for scale factor. */
10236 if (*base_string
!= ')')
10238 char *end_scale
= i386_scale (base_string
);
10243 base_string
= end_scale
;
10244 if (is_space_char (*base_string
))
10246 if (*base_string
!= ')')
10248 as_bad (_("expecting `)' "
10249 "after scale factor in `%s'"),
10254 else if (!i
.index_reg
)
10256 as_bad (_("expecting index register or scale factor "
10257 "after `,'; got '%c'"),
10262 else if (*base_string
!= ')')
10264 as_bad (_("expecting `,' or `)' "
10265 "after base register in `%s'"),
10270 else if (*base_string
== REGISTER_PREFIX
)
10272 end_op
= strchr (base_string
, ',');
10275 as_bad (_("bad register name `%s'"), base_string
);
10280 /* If there's an expression beginning the operand, parse it,
10281 assuming displacement_string_start and
10282 displacement_string_end are meaningful. */
10283 if (displacement_string_start
!= displacement_string_end
)
10285 if (!i386_displacement (displacement_string_start
,
10286 displacement_string_end
))
10290 /* Special case for (%dx) while doing input/output op. */
10292 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10293 && i
.base_reg
->reg_type
.bitfield
.word
10294 && i
.index_reg
== 0
10295 && i
.log2_scale_factor
== 0
10296 && i
.seg
[i
.mem_operands
] == 0
10297 && !operand_type_check (i
.types
[this_operand
], disp
))
10299 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10303 if (i386_index_check (operand_string
) == 0)
10305 i
.flags
[this_operand
] |= Operand_Mem
;
10306 if (i
.mem_operands
== 0)
10307 i
.memop1_string
= xstrdup (operand_string
);
10312 /* It's not a memory operand; argh! */
10313 as_bad (_("invalid char %s beginning operand %d `%s'"),
10314 output_invalid (*op_string
),
10319 return 1; /* Normal return. */
10322 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10323 that an rs_machine_dependent frag may reach. */
10326 i386_frag_max_var (fragS
*frag
)
10328 /* The only relaxable frags are for jumps.
10329 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10330 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10331 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10336 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10338 /* STT_GNU_IFUNC symbol must go through PLT. */
10339 if ((symbol_get_bfdsym (fr_symbol
)->flags
10340 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10343 if (!S_IS_EXTERNAL (fr_symbol
))
10344 /* Symbol may be weak or local. */
10345 return !S_IS_WEAK (fr_symbol
);
10347 /* Global symbols with non-default visibility can't be preempted. */
10348 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10351 if (fr_var
!= NO_RELOC
)
10352 switch ((enum bfd_reloc_code_real
) fr_var
)
10354 case BFD_RELOC_386_PLT32
:
10355 case BFD_RELOC_X86_64_PLT32
:
10356 /* Symbol with PLT relocation may be preempted. */
10362 /* Global symbols with default visibility in a shared library may be
10363 preempted by another definition. */
10368 /* md_estimate_size_before_relax()
10370 Called just before relax() for rs_machine_dependent frags. The x86
10371 assembler uses these frags to handle variable size jump
10374 Any symbol that is now undefined will not become defined.
10375 Return the correct fr_subtype in the frag.
10376 Return the initial "guess for variable size of frag" to caller.
10377 The guess is actually the growth beyond the fixed part. Whatever
10378 we do to grow the fixed or variable part contributes to our
10382 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10384 /* We've already got fragP->fr_subtype right; all we have to do is
10385 check for un-relaxable symbols. On an ELF system, we can't relax
10386 an externally visible symbol, because it may be overridden by a
10388 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10391 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10394 #if defined (OBJ_COFF) && defined (TE_PE)
10395 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10396 && S_IS_WEAK (fragP
->fr_symbol
))
10400 /* Symbol is undefined in this segment, or we need to keep a
10401 reloc so that weak symbols can be overridden. */
10402 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10403 enum bfd_reloc_code_real reloc_type
;
10404 unsigned char *opcode
;
10407 if (fragP
->fr_var
!= NO_RELOC
)
10408 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10409 else if (size
== 2)
10410 reloc_type
= BFD_RELOC_16_PCREL
;
10411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10412 else if (need_plt32_p (fragP
->fr_symbol
))
10413 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10416 reloc_type
= BFD_RELOC_32_PCREL
;
10418 old_fr_fix
= fragP
->fr_fix
;
10419 opcode
= (unsigned char *) fragP
->fr_opcode
;
10421 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10424 /* Make jmp (0xeb) a (d)word displacement jump. */
10426 fragP
->fr_fix
+= size
;
10427 fix_new (fragP
, old_fr_fix
, size
,
10429 fragP
->fr_offset
, 1,
10435 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10437 /* Negate the condition, and branch past an
10438 unconditional jump. */
10441 /* Insert an unconditional jump. */
10443 /* We added two extra opcode bytes, and have a two byte
10445 fragP
->fr_fix
+= 2 + 2;
10446 fix_new (fragP
, old_fr_fix
+ 2, 2,
10448 fragP
->fr_offset
, 1,
10452 /* Fall through. */
10455 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10459 fragP
->fr_fix
+= 1;
10460 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10462 fragP
->fr_offset
, 1,
10463 BFD_RELOC_8_PCREL
);
10464 fixP
->fx_signed
= 1;
10468 /* This changes the byte-displacement jump 0x7N
10469 to the (d)word-displacement jump 0x0f,0x8N. */
10470 opcode
[1] = opcode
[0] + 0x10;
10471 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10472 /* We've added an opcode byte. */
10473 fragP
->fr_fix
+= 1 + size
;
10474 fix_new (fragP
, old_fr_fix
+ 1, size
,
10476 fragP
->fr_offset
, 1,
10481 BAD_CASE (fragP
->fr_subtype
);
10485 return fragP
->fr_fix
- old_fr_fix
;
10488 /* Guess size depending on current relax state. Initially the relax
10489 state will correspond to a short jump and we return 1, because
10490 the variable part of the frag (the branch offset) is one byte
10491 long. However, we can relax a section more than once and in that
10492 case we must either set fr_subtype back to the unrelaxed state,
10493 or return the value for the appropriate branch. */
10494 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10497 /* Called after relax() is finished.
10499 In: Address of frag.
10500 fr_type == rs_machine_dependent.
10501 fr_subtype is what the address relaxed to.
10503 Out: Any fixSs and constants are set up.
10504 Caller will turn frag into a ".space 0". */
10507 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10510 unsigned char *opcode
;
10511 unsigned char *where_to_put_displacement
= NULL
;
10512 offsetT target_address
;
10513 offsetT opcode_address
;
10514 unsigned int extension
= 0;
10515 offsetT displacement_from_opcode_start
;
10517 opcode
= (unsigned char *) fragP
->fr_opcode
;
10519 /* Address we want to reach in file space. */
10520 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10522 /* Address opcode resides at in file space. */
10523 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10525 /* Displacement from opcode start to fill into instruction. */
10526 displacement_from_opcode_start
= target_address
- opcode_address
;
10528 if ((fragP
->fr_subtype
& BIG
) == 0)
10530 /* Don't have to change opcode. */
10531 extension
= 1; /* 1 opcode + 1 displacement */
10532 where_to_put_displacement
= &opcode
[1];
10536 if (no_cond_jump_promotion
10537 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10538 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10539 _("long jump required"));
10541 switch (fragP
->fr_subtype
)
10543 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10544 extension
= 4; /* 1 opcode + 4 displacement */
10546 where_to_put_displacement
= &opcode
[1];
10549 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10550 extension
= 2; /* 1 opcode + 2 displacement */
10552 where_to_put_displacement
= &opcode
[1];
10555 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10556 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10557 extension
= 5; /* 2 opcode + 4 displacement */
10558 opcode
[1] = opcode
[0] + 0x10;
10559 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10560 where_to_put_displacement
= &opcode
[2];
10563 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10564 extension
= 3; /* 2 opcode + 2 displacement */
10565 opcode
[1] = opcode
[0] + 0x10;
10566 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10567 where_to_put_displacement
= &opcode
[2];
10570 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10575 where_to_put_displacement
= &opcode
[3];
10579 BAD_CASE (fragP
->fr_subtype
);
10584 /* If size if less then four we are sure that the operand fits,
10585 but if it's 4, then it could be that the displacement is larger
10587 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10589 && ((addressT
) (displacement_from_opcode_start
- extension
10590 + ((addressT
) 1 << 31))
10591 > (((addressT
) 2 << 31) - 1)))
10593 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10594 _("jump target out of range"));
10595 /* Make us emit 0. */
10596 displacement_from_opcode_start
= extension
;
10598 /* Now put displacement after opcode. */
10599 md_number_to_chars ((char *) where_to_put_displacement
,
10600 (valueT
) (displacement_from_opcode_start
- extension
),
10601 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10602 fragP
->fr_fix
+= extension
;
10605 /* Apply a fixup (fixP) to segment data, once it has been determined
10606 by our caller that we have all the info we need to fix it up.
10608 Parameter valP is the pointer to the value of the bits.
10610 On the 386, immediates, displacements, and data pointers are all in
10611 the same (little-endian) format, so we don't need to care about which
10612 we are handling. */
10615 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10617 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10618 valueT value
= *valP
;
10620 #if !defined (TE_Mach)
10621 if (fixP
->fx_pcrel
)
10623 switch (fixP
->fx_r_type
)
10629 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10632 case BFD_RELOC_X86_64_32S
:
10633 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10636 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10639 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10644 if (fixP
->fx_addsy
!= NULL
10645 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10646 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10647 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10648 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10649 && !use_rela_relocations
)
10651 /* This is a hack. There should be a better way to handle this.
10652 This covers for the fact that bfd_install_relocation will
10653 subtract the current location (for partial_inplace, PC relative
10654 relocations); see more below. */
10658 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10661 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10663 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10666 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10668 if ((sym_seg
== seg
10669 || (symbol_section_p (fixP
->fx_addsy
)
10670 && sym_seg
!= absolute_section
))
10671 && !generic_force_reloc (fixP
))
10673 /* Yes, we add the values in twice. This is because
10674 bfd_install_relocation subtracts them out again. I think
10675 bfd_install_relocation is broken, but I don't dare change
10677 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10681 #if defined (OBJ_COFF) && defined (TE_PE)
10682 /* For some reason, the PE format does not store a
10683 section address offset for a PC relative symbol. */
10684 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10685 || S_IS_WEAK (fixP
->fx_addsy
))
10686 value
+= md_pcrel_from (fixP
);
10689 #if defined (OBJ_COFF) && defined (TE_PE)
10690 if (fixP
->fx_addsy
!= NULL
10691 && S_IS_WEAK (fixP
->fx_addsy
)
10692 /* PR 16858: Do not modify weak function references. */
10693 && ! fixP
->fx_pcrel
)
10695 #if !defined (TE_PEP)
10696 /* For x86 PE weak function symbols are neither PC-relative
10697 nor do they set S_IS_FUNCTION. So the only reliable way
10698 to detect them is to check the flags of their containing
10700 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10701 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10705 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10709 /* Fix a few things - the dynamic linker expects certain values here,
10710 and we must not disappoint it. */
10711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10712 if (IS_ELF
&& fixP
->fx_addsy
)
10713 switch (fixP
->fx_r_type
)
10715 case BFD_RELOC_386_PLT32
:
10716 case BFD_RELOC_X86_64_PLT32
:
10717 /* Make the jump instruction point to the address of the operand.
10718 At runtime we merely add the offset to the actual PLT entry.
10719 NB: Subtract the offset size only for jump instructions. */
10720 if (fixP
->fx_pcrel
)
10724 case BFD_RELOC_386_TLS_GD
:
10725 case BFD_RELOC_386_TLS_LDM
:
10726 case BFD_RELOC_386_TLS_IE_32
:
10727 case BFD_RELOC_386_TLS_IE
:
10728 case BFD_RELOC_386_TLS_GOTIE
:
10729 case BFD_RELOC_386_TLS_GOTDESC
:
10730 case BFD_RELOC_X86_64_TLSGD
:
10731 case BFD_RELOC_X86_64_TLSLD
:
10732 case BFD_RELOC_X86_64_GOTTPOFF
:
10733 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10734 value
= 0; /* Fully resolved at runtime. No addend. */
10736 case BFD_RELOC_386_TLS_LE
:
10737 case BFD_RELOC_386_TLS_LDO_32
:
10738 case BFD_RELOC_386_TLS_LE_32
:
10739 case BFD_RELOC_X86_64_DTPOFF32
:
10740 case BFD_RELOC_X86_64_DTPOFF64
:
10741 case BFD_RELOC_X86_64_TPOFF32
:
10742 case BFD_RELOC_X86_64_TPOFF64
:
10743 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10746 case BFD_RELOC_386_TLS_DESC_CALL
:
10747 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10748 value
= 0; /* Fully resolved at runtime. No addend. */
10749 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10753 case BFD_RELOC_VTABLE_INHERIT
:
10754 case BFD_RELOC_VTABLE_ENTRY
:
10761 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10763 #endif /* !defined (TE_Mach) */
10765 /* Are we finished with this relocation now? */
10766 if (fixP
->fx_addsy
== NULL
)
10768 #if defined (OBJ_COFF) && defined (TE_PE)
10769 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10772 /* Remember value for tc_gen_reloc. */
10773 fixP
->fx_addnumber
= value
;
10774 /* Clear out the frag for now. */
10778 else if (use_rela_relocations
)
10780 fixP
->fx_no_overflow
= 1;
10781 /* Remember value for tc_gen_reloc. */
10782 fixP
->fx_addnumber
= value
;
10786 md_number_to_chars (p
, value
, fixP
->fx_size
);
10790 md_atof (int type
, char *litP
, int *sizeP
)
10792 /* This outputs the LITTLENUMs in REVERSE order;
10793 in accord with the bigendian 386. */
10794 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10797 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10800 output_invalid (int c
)
10803 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10806 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10807 "(0x%x)", (unsigned char) c
);
10808 return output_invalid_buf
;
10811 /* REG_STRING starts *before* REGISTER_PREFIX. */
10813 static const reg_entry
*
10814 parse_real_register (char *reg_string
, char **end_op
)
10816 char *s
= reg_string
;
10818 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10819 const reg_entry
*r
;
10821 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10822 if (*s
== REGISTER_PREFIX
)
10825 if (is_space_char (*s
))
10828 p
= reg_name_given
;
10829 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10831 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10832 return (const reg_entry
*) NULL
;
10836 /* For naked regs, make sure that we are not dealing with an identifier.
10837 This prevents confusing an identifier like `eax_var' with register
10839 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10840 return (const reg_entry
*) NULL
;
10844 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10846 /* Handle floating point regs, allowing spaces in the (i) part. */
10847 if (r
== i386_regtab
/* %st is first entry of table */)
10849 if (!cpu_arch_flags
.bitfield
.cpu8087
10850 && !cpu_arch_flags
.bitfield
.cpu287
10851 && !cpu_arch_flags
.bitfield
.cpu387
)
10852 return (const reg_entry
*) NULL
;
10854 if (is_space_char (*s
))
10859 if (is_space_char (*s
))
10861 if (*s
>= '0' && *s
<= '7')
10863 int fpr
= *s
- '0';
10865 if (is_space_char (*s
))
10870 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10875 /* We have "%st(" then garbage. */
10876 return (const reg_entry
*) NULL
;
10880 if (r
== NULL
|| allow_pseudo_reg
)
10883 if (operand_type_all_zero (&r
->reg_type
))
10884 return (const reg_entry
*) NULL
;
10886 if ((r
->reg_type
.bitfield
.dword
10887 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
10888 || r
->reg_type
.bitfield
.class == RegCR
10889 || r
->reg_type
.bitfield
.class == RegDR
10890 || r
->reg_type
.bitfield
.class == RegTR
)
10891 && !cpu_arch_flags
.bitfield
.cpui386
)
10892 return (const reg_entry
*) NULL
;
10894 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
10895 return (const reg_entry
*) NULL
;
10897 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10899 if (r
->reg_type
.bitfield
.zmmword
10900 || r
->reg_type
.bitfield
.class == RegMask
)
10901 return (const reg_entry
*) NULL
;
10903 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10905 if (r
->reg_type
.bitfield
.ymmword
)
10906 return (const reg_entry
*) NULL
;
10908 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10909 return (const reg_entry
*) NULL
;
10913 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10914 return (const reg_entry
*) NULL
;
10916 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10917 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10918 return (const reg_entry
*) NULL
;
10920 /* Upper 16 vector registers are only available with VREX in 64bit
10921 mode, and require EVEX encoding. */
10922 if (r
->reg_flags
& RegVRex
)
10924 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10925 || flag_code
!= CODE_64BIT
)
10926 return (const reg_entry
*) NULL
;
10928 i
.vec_encoding
= vex_encoding_evex
;
10931 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10932 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
10933 && flag_code
!= CODE_64BIT
)
10934 return (const reg_entry
*) NULL
;
10936 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
10938 return (const reg_entry
*) NULL
;
10943 /* REG_STRING starts *before* REGISTER_PREFIX. */
10945 static const reg_entry
*
10946 parse_register (char *reg_string
, char **end_op
)
10948 const reg_entry
*r
;
10950 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10951 r
= parse_real_register (reg_string
, end_op
);
10956 char *save
= input_line_pointer
;
10960 input_line_pointer
= reg_string
;
10961 c
= get_symbol_name (®_string
);
10962 symbolP
= symbol_find (reg_string
);
10963 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10965 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10967 know (e
->X_op
== O_register
);
10968 know (e
->X_add_number
>= 0
10969 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10970 r
= i386_regtab
+ e
->X_add_number
;
10971 if ((r
->reg_flags
& RegVRex
))
10972 i
.vec_encoding
= vex_encoding_evex
;
10973 *end_op
= input_line_pointer
;
10975 *input_line_pointer
= c
;
10976 input_line_pointer
= save
;
10982 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10984 const reg_entry
*r
;
10985 char *end
= input_line_pointer
;
10988 r
= parse_register (name
, &input_line_pointer
);
10989 if (r
&& end
<= input_line_pointer
)
10991 *nextcharP
= *input_line_pointer
;
10992 *input_line_pointer
= 0;
10993 e
->X_op
= O_register
;
10994 e
->X_add_number
= r
- i386_regtab
;
10997 input_line_pointer
= end
;
10999 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11003 md_operand (expressionS
*e
)
11006 const reg_entry
*r
;
11008 switch (*input_line_pointer
)
11010 case REGISTER_PREFIX
:
11011 r
= parse_real_register (input_line_pointer
, &end
);
11014 e
->X_op
= O_register
;
11015 e
->X_add_number
= r
- i386_regtab
;
11016 input_line_pointer
= end
;
11021 gas_assert (intel_syntax
);
11022 end
= input_line_pointer
++;
11024 if (*input_line_pointer
== ']')
11026 ++input_line_pointer
;
11027 e
->X_op_symbol
= make_expr_symbol (e
);
11028 e
->X_add_symbol
= NULL
;
11029 e
->X_add_number
= 0;
11034 e
->X_op
= O_absent
;
11035 input_line_pointer
= end
;
11042 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11043 const char *md_shortopts
= "kVQ:sqnO::";
11045 const char *md_shortopts
= "qnO::";
11048 #define OPTION_32 (OPTION_MD_BASE + 0)
11049 #define OPTION_64 (OPTION_MD_BASE + 1)
11050 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11051 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11052 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11053 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11054 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11055 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11056 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11057 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11058 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11059 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11060 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11061 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11062 #define OPTION_X32 (OPTION_MD_BASE + 14)
11063 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11064 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11065 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11066 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11067 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11068 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11069 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11070 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11071 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11072 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11073 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11074 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11076 struct option md_longopts
[] =
11078 {"32", no_argument
, NULL
, OPTION_32
},
11079 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11080 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11081 {"64", no_argument
, NULL
, OPTION_64
},
11083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11084 {"x32", no_argument
, NULL
, OPTION_X32
},
11085 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11086 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11088 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11089 {"march", required_argument
, NULL
, OPTION_MARCH
},
11090 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11091 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11092 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11093 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11094 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11095 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11096 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11097 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11098 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11099 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11100 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11101 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11102 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11103 # if defined (TE_PE) || defined (TE_PEP)
11104 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11106 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11107 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11108 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11109 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11110 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11111 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11112 {NULL
, no_argument
, NULL
, 0}
11114 size_t md_longopts_size
= sizeof (md_longopts
);
11117 md_parse_option (int c
, const char *arg
)
11120 char *arch
, *next
, *saved
;
11125 optimize_align_code
= 0;
11129 quiet_warnings
= 1;
11132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11133 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11134 should be emitted or not. FIXME: Not implemented. */
11136 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11140 /* -V: SVR4 argument to print version ID. */
11142 print_version_id ();
11145 /* -k: Ignore for FreeBSD compatibility. */
11150 /* -s: On i386 Solaris, this tells the native assembler to use
11151 .stab instead of .stab.excl. We always use .stab anyhow. */
11154 case OPTION_MSHARED
:
11158 case OPTION_X86_USED_NOTE
:
11159 if (strcasecmp (arg
, "yes") == 0)
11161 else if (strcasecmp (arg
, "no") == 0)
11164 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11169 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11170 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11173 const char **list
, **l
;
11175 list
= bfd_target_list ();
11176 for (l
= list
; *l
!= NULL
; l
++)
11177 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11178 || strcmp (*l
, "coff-x86-64") == 0
11179 || strcmp (*l
, "pe-x86-64") == 0
11180 || strcmp (*l
, "pei-x86-64") == 0
11181 || strcmp (*l
, "mach-o-x86-64") == 0)
11183 default_arch
= "x86_64";
11187 as_fatal (_("no compiled in support for x86_64"));
11193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11197 const char **list
, **l
;
11199 list
= bfd_target_list ();
11200 for (l
= list
; *l
!= NULL
; l
++)
11201 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11203 default_arch
= "x86_64:32";
11207 as_fatal (_("no compiled in support for 32bit x86_64"));
11211 as_fatal (_("32bit x86_64 is only supported for ELF"));
11216 default_arch
= "i386";
11219 case OPTION_DIVIDE
:
11220 #ifdef SVR4_COMMENT_CHARS
11225 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11227 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11231 i386_comment_chars
= n
;
11237 saved
= xstrdup (arg
);
11239 /* Allow -march=+nosse. */
11245 as_fatal (_("invalid -march= option: `%s'"), arg
);
11246 next
= strchr (arch
, '+');
11249 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11251 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11254 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11257 cpu_arch_name
= cpu_arch
[j
].name
;
11258 cpu_sub_arch_name
= NULL
;
11259 cpu_arch_flags
= cpu_arch
[j
].flags
;
11260 cpu_arch_isa
= cpu_arch
[j
].type
;
11261 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11262 if (!cpu_arch_tune_set
)
11264 cpu_arch_tune
= cpu_arch_isa
;
11265 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11269 else if (*cpu_arch
[j
].name
== '.'
11270 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11272 /* ISA extension. */
11273 i386_cpu_flags flags
;
11275 flags
= cpu_flags_or (cpu_arch_flags
,
11276 cpu_arch
[j
].flags
);
11278 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11280 if (cpu_sub_arch_name
)
11282 char *name
= cpu_sub_arch_name
;
11283 cpu_sub_arch_name
= concat (name
,
11285 (const char *) NULL
);
11289 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11290 cpu_arch_flags
= flags
;
11291 cpu_arch_isa_flags
= flags
;
11295 = cpu_flags_or (cpu_arch_isa_flags
,
11296 cpu_arch
[j
].flags
);
11301 if (j
>= ARRAY_SIZE (cpu_arch
))
11303 /* Disable an ISA extension. */
11304 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11305 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11307 i386_cpu_flags flags
;
11309 flags
= cpu_flags_and_not (cpu_arch_flags
,
11310 cpu_noarch
[j
].flags
);
11311 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11313 if (cpu_sub_arch_name
)
11315 char *name
= cpu_sub_arch_name
;
11316 cpu_sub_arch_name
= concat (arch
,
11317 (const char *) NULL
);
11321 cpu_sub_arch_name
= xstrdup (arch
);
11322 cpu_arch_flags
= flags
;
11323 cpu_arch_isa_flags
= flags
;
11328 if (j
>= ARRAY_SIZE (cpu_noarch
))
11329 j
= ARRAY_SIZE (cpu_arch
);
11332 if (j
>= ARRAY_SIZE (cpu_arch
))
11333 as_fatal (_("invalid -march= option: `%s'"), arg
);
11337 while (next
!= NULL
);
11343 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11344 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11346 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11348 cpu_arch_tune_set
= 1;
11349 cpu_arch_tune
= cpu_arch
[j
].type
;
11350 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11354 if (j
>= ARRAY_SIZE (cpu_arch
))
11355 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11358 case OPTION_MMNEMONIC
:
11359 if (strcasecmp (arg
, "att") == 0)
11360 intel_mnemonic
= 0;
11361 else if (strcasecmp (arg
, "intel") == 0)
11362 intel_mnemonic
= 1;
11364 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11367 case OPTION_MSYNTAX
:
11368 if (strcasecmp (arg
, "att") == 0)
11370 else if (strcasecmp (arg
, "intel") == 0)
11373 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11376 case OPTION_MINDEX_REG
:
11377 allow_index_reg
= 1;
11380 case OPTION_MNAKED_REG
:
11381 allow_naked_reg
= 1;
11384 case OPTION_MSSE2AVX
:
11388 case OPTION_MSSE_CHECK
:
11389 if (strcasecmp (arg
, "error") == 0)
11390 sse_check
= check_error
;
11391 else if (strcasecmp (arg
, "warning") == 0)
11392 sse_check
= check_warning
;
11393 else if (strcasecmp (arg
, "none") == 0)
11394 sse_check
= check_none
;
11396 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11399 case OPTION_MOPERAND_CHECK
:
11400 if (strcasecmp (arg
, "error") == 0)
11401 operand_check
= check_error
;
11402 else if (strcasecmp (arg
, "warning") == 0)
11403 operand_check
= check_warning
;
11404 else if (strcasecmp (arg
, "none") == 0)
11405 operand_check
= check_none
;
11407 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11410 case OPTION_MAVXSCALAR
:
11411 if (strcasecmp (arg
, "128") == 0)
11412 avxscalar
= vex128
;
11413 else if (strcasecmp (arg
, "256") == 0)
11414 avxscalar
= vex256
;
11416 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11419 case OPTION_MVEXWIG
:
11420 if (strcmp (arg
, "0") == 0)
11422 else if (strcmp (arg
, "1") == 0)
11425 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11428 case OPTION_MADD_BND_PREFIX
:
11429 add_bnd_prefix
= 1;
11432 case OPTION_MEVEXLIG
:
11433 if (strcmp (arg
, "128") == 0)
11434 evexlig
= evexl128
;
11435 else if (strcmp (arg
, "256") == 0)
11436 evexlig
= evexl256
;
11437 else if (strcmp (arg
, "512") == 0)
11438 evexlig
= evexl512
;
11440 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11443 case OPTION_MEVEXRCIG
:
11444 if (strcmp (arg
, "rne") == 0)
11446 else if (strcmp (arg
, "rd") == 0)
11448 else if (strcmp (arg
, "ru") == 0)
11450 else if (strcmp (arg
, "rz") == 0)
11453 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11456 case OPTION_MEVEXWIG
:
11457 if (strcmp (arg
, "0") == 0)
11459 else if (strcmp (arg
, "1") == 0)
11462 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11465 # if defined (TE_PE) || defined (TE_PEP)
11466 case OPTION_MBIG_OBJ
:
11471 case OPTION_MOMIT_LOCK_PREFIX
:
11472 if (strcasecmp (arg
, "yes") == 0)
11473 omit_lock_prefix
= 1;
11474 else if (strcasecmp (arg
, "no") == 0)
11475 omit_lock_prefix
= 0;
11477 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11480 case OPTION_MFENCE_AS_LOCK_ADD
:
11481 if (strcasecmp (arg
, "yes") == 0)
11483 else if (strcasecmp (arg
, "no") == 0)
11486 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11489 case OPTION_MRELAX_RELOCATIONS
:
11490 if (strcasecmp (arg
, "yes") == 0)
11491 generate_relax_relocations
= 1;
11492 else if (strcasecmp (arg
, "no") == 0)
11493 generate_relax_relocations
= 0;
11495 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11498 case OPTION_MAMD64
:
11502 case OPTION_MINTEL64
:
11510 /* Turn off -Os. */
11511 optimize_for_space
= 0;
11513 else if (*arg
== 's')
11515 optimize_for_space
= 1;
11516 /* Turn on all encoding optimizations. */
11517 optimize
= INT_MAX
;
11521 optimize
= atoi (arg
);
11522 /* Turn off -Os. */
11523 optimize_for_space
= 0;
11533 #define MESSAGE_TEMPLATE \
11537 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11538 int *left_p
, const char *name
, int len
)
11540 int size
= sizeof (MESSAGE_TEMPLATE
);
11541 int left
= *left_p
;
11543 /* Reserve 2 spaces for ", " or ",\0" */
11546 /* Check if there is any room. */
11554 p
= mempcpy (p
, name
, len
);
11558 /* Output the current message now and start a new one. */
11561 fprintf (stream
, "%s\n", message
);
11563 left
= size
- (start
- message
) - len
- 2;
11565 gas_assert (left
>= 0);
11567 p
= mempcpy (p
, name
, len
);
11575 show_arch (FILE *stream
, int ext
, int check
)
11577 static char message
[] = MESSAGE_TEMPLATE
;
11578 char *start
= message
+ 27;
11580 int size
= sizeof (MESSAGE_TEMPLATE
);
11587 left
= size
- (start
- message
);
11588 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11590 /* Should it be skipped? */
11591 if (cpu_arch
[j
].skip
)
11594 name
= cpu_arch
[j
].name
;
11595 len
= cpu_arch
[j
].len
;
11598 /* It is an extension. Skip if we aren't asked to show it. */
11609 /* It is an processor. Skip if we show only extension. */
11612 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11614 /* It is an impossible processor - skip. */
11618 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11621 /* Display disabled extensions. */
11623 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11625 name
= cpu_noarch
[j
].name
;
11626 len
= cpu_noarch
[j
].len
;
11627 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11632 fprintf (stream
, "%s\n", message
);
11636 md_show_usage (FILE *stream
)
11638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11639 fprintf (stream
, _("\
11640 -Qy, -Qn ignored\n\
11641 -V print assembler version number\n\
11644 fprintf (stream
, _("\
11645 -n Do not optimize code alignment\n\
11646 -q quieten some warnings\n"));
11647 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11648 fprintf (stream
, _("\
11651 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11652 || defined (TE_PE) || defined (TE_PEP))
11653 fprintf (stream
, _("\
11654 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11656 #ifdef SVR4_COMMENT_CHARS
11657 fprintf (stream
, _("\
11658 --divide do not treat `/' as a comment character\n"));
11660 fprintf (stream
, _("\
11661 --divide ignored\n"));
11663 fprintf (stream
, _("\
11664 -march=CPU[,+EXTENSION...]\n\
11665 generate code for CPU and EXTENSION, CPU is one of:\n"));
11666 show_arch (stream
, 0, 1);
11667 fprintf (stream
, _("\
11668 EXTENSION is combination of:\n"));
11669 show_arch (stream
, 1, 0);
11670 fprintf (stream
, _("\
11671 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11672 show_arch (stream
, 0, 0);
11673 fprintf (stream
, _("\
11674 -msse2avx encode SSE instructions with VEX prefix\n"));
11675 fprintf (stream
, _("\
11676 -msse-check=[none|error|warning] (default: warning)\n\
11677 check SSE instructions\n"));
11678 fprintf (stream
, _("\
11679 -moperand-check=[none|error|warning] (default: warning)\n\
11680 check operand combinations for validity\n"));
11681 fprintf (stream
, _("\
11682 -mavxscalar=[128|256] (default: 128)\n\
11683 encode scalar AVX instructions with specific vector\n\
11685 fprintf (stream
, _("\
11686 -mvexwig=[0|1] (default: 0)\n\
11687 encode VEX instructions with specific VEX.W value\n\
11688 for VEX.W bit ignored instructions\n"));
11689 fprintf (stream
, _("\
11690 -mevexlig=[128|256|512] (default: 128)\n\
11691 encode scalar EVEX instructions with specific vector\n\
11693 fprintf (stream
, _("\
11694 -mevexwig=[0|1] (default: 0)\n\
11695 encode EVEX instructions with specific EVEX.W value\n\
11696 for EVEX.W bit ignored instructions\n"));
11697 fprintf (stream
, _("\
11698 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11699 encode EVEX instructions with specific EVEX.RC value\n\
11700 for SAE-only ignored instructions\n"));
11701 fprintf (stream
, _("\
11702 -mmnemonic=[att|intel] "));
11703 if (SYSV386_COMPAT
)
11704 fprintf (stream
, _("(default: att)\n"));
11706 fprintf (stream
, _("(default: intel)\n"));
11707 fprintf (stream
, _("\
11708 use AT&T/Intel mnemonic\n"));
11709 fprintf (stream
, _("\
11710 -msyntax=[att|intel] (default: att)\n\
11711 use AT&T/Intel syntax\n"));
11712 fprintf (stream
, _("\
11713 -mindex-reg support pseudo index registers\n"));
11714 fprintf (stream
, _("\
11715 -mnaked-reg don't require `%%' prefix for registers\n"));
11716 fprintf (stream
, _("\
11717 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11719 fprintf (stream
, _("\
11720 -mshared disable branch optimization for shared code\n"));
11721 fprintf (stream
, _("\
11722 -mx86-used-note=[no|yes] "));
11723 if (DEFAULT_X86_USED_NOTE
)
11724 fprintf (stream
, _("(default: yes)\n"));
11726 fprintf (stream
, _("(default: no)\n"));
11727 fprintf (stream
, _("\
11728 generate x86 used ISA and feature properties\n"));
11730 #if defined (TE_PE) || defined (TE_PEP)
11731 fprintf (stream
, _("\
11732 -mbig-obj generate big object files\n"));
11734 fprintf (stream
, _("\
11735 -momit-lock-prefix=[no|yes] (default: no)\n\
11736 strip all lock prefixes\n"));
11737 fprintf (stream
, _("\
11738 -mfence-as-lock-add=[no|yes] (default: no)\n\
11739 encode lfence, mfence and sfence as\n\
11740 lock addl $0x0, (%%{re}sp)\n"));
11741 fprintf (stream
, _("\
11742 -mrelax-relocations=[no|yes] "));
11743 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11744 fprintf (stream
, _("(default: yes)\n"));
11746 fprintf (stream
, _("(default: no)\n"));
11747 fprintf (stream
, _("\
11748 generate relax relocations\n"));
11749 fprintf (stream
, _("\
11750 -mamd64 accept only AMD64 ISA [default]\n"));
11751 fprintf (stream
, _("\
11752 -mintel64 accept only Intel64 ISA\n"));
11755 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11756 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11757 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11759 /* Pick the target format to use. */
11762 i386_target_format (void)
11764 if (!strncmp (default_arch
, "x86_64", 6))
11766 update_code_flag (CODE_64BIT
, 1);
11767 if (default_arch
[6] == '\0')
11768 x86_elf_abi
= X86_64_ABI
;
11770 x86_elf_abi
= X86_64_X32_ABI
;
11772 else if (!strcmp (default_arch
, "i386"))
11773 update_code_flag (CODE_32BIT
, 1);
11774 else if (!strcmp (default_arch
, "iamcu"))
11776 update_code_flag (CODE_32BIT
, 1);
11777 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11779 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11780 cpu_arch_name
= "iamcu";
11781 cpu_sub_arch_name
= NULL
;
11782 cpu_arch_flags
= iamcu_flags
;
11783 cpu_arch_isa
= PROCESSOR_IAMCU
;
11784 cpu_arch_isa_flags
= iamcu_flags
;
11785 if (!cpu_arch_tune_set
)
11787 cpu_arch_tune
= cpu_arch_isa
;
11788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11791 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11792 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11796 as_fatal (_("unknown architecture"));
11798 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11799 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11800 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11801 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11803 switch (OUTPUT_FLAVOR
)
11805 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11806 case bfd_target_aout_flavour
:
11807 return AOUT_TARGET_FORMAT
;
11809 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11810 # if defined (TE_PE) || defined (TE_PEP)
11811 case bfd_target_coff_flavour
:
11812 if (flag_code
== CODE_64BIT
)
11813 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11816 # elif defined (TE_GO32)
11817 case bfd_target_coff_flavour
:
11818 return "coff-go32";
11820 case bfd_target_coff_flavour
:
11821 return "coff-i386";
11824 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11825 case bfd_target_elf_flavour
:
11827 const char *format
;
11829 switch (x86_elf_abi
)
11832 format
= ELF_TARGET_FORMAT
;
11835 use_rela_relocations
= 1;
11837 format
= ELF_TARGET_FORMAT64
;
11839 case X86_64_X32_ABI
:
11840 use_rela_relocations
= 1;
11842 disallow_64bit_reloc
= 1;
11843 format
= ELF_TARGET_FORMAT32
;
11846 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11848 if (x86_elf_abi
!= X86_64_ABI
)
11849 as_fatal (_("Intel L1OM is 64bit only"));
11850 return ELF_TARGET_L1OM_FORMAT
;
11852 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11854 if (x86_elf_abi
!= X86_64_ABI
)
11855 as_fatal (_("Intel K1OM is 64bit only"));
11856 return ELF_TARGET_K1OM_FORMAT
;
11858 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11860 if (x86_elf_abi
!= I386_ABI
)
11861 as_fatal (_("Intel MCU is 32bit only"));
11862 return ELF_TARGET_IAMCU_FORMAT
;
11868 #if defined (OBJ_MACH_O)
11869 case bfd_target_mach_o_flavour
:
11870 if (flag_code
== CODE_64BIT
)
11872 use_rela_relocations
= 1;
11874 return "mach-o-x86-64";
11877 return "mach-o-i386";
11885 #endif /* OBJ_MAYBE_ more than one */
11888 md_undefined_symbol (char *name
)
11890 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11891 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11892 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11893 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11897 if (symbol_find (name
))
11898 as_bad (_("GOT already in symbol table"));
11899 GOT_symbol
= symbol_new (name
, undefined_section
,
11900 (valueT
) 0, &zero_address_frag
);
11907 /* Round up a section size to the appropriate boundary. */
11910 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11912 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11913 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11915 /* For a.out, force the section size to be aligned. If we don't do
11916 this, BFD will align it for us, but it will not write out the
11917 final bytes of the section. This may be a bug in BFD, but it is
11918 easier to fix it here since that is how the other a.out targets
11922 align
= bfd_section_alignment (segment
);
11923 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11930 /* On the i386, PC-relative offsets are relative to the start of the
11931 next instruction. That is, the address of the offset, plus its
11932 size, since the offset is always the last part of the insn. */
11935 md_pcrel_from (fixS
*fixP
)
11937 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11943 s_bss (int ignore ATTRIBUTE_UNUSED
)
11947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11949 obj_elf_section_change_hook ();
11951 temp
= get_absolute_expression ();
11952 subseg_set (bss_section
, (subsegT
) temp
);
11953 demand_empty_rest_of_line ();
11959 i386_validate_fix (fixS
*fixp
)
11961 if (fixp
->fx_subsy
)
11963 if (fixp
->fx_subsy
== GOT_symbol
)
11965 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11970 if (fixp
->fx_tcbit2
)
11971 fixp
->fx_r_type
= (fixp
->fx_tcbit
11972 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11973 : BFD_RELOC_X86_64_GOTPCRELX
);
11976 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11981 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11983 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11985 fixp
->fx_subsy
= 0;
11988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11989 else if (!object_64bit
)
11991 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11992 && fixp
->fx_tcbit2
)
11993 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11999 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12002 bfd_reloc_code_real_type code
;
12004 switch (fixp
->fx_r_type
)
12006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12007 case BFD_RELOC_SIZE32
:
12008 case BFD_RELOC_SIZE64
:
12009 if (S_IS_DEFINED (fixp
->fx_addsy
)
12010 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12012 /* Resolve size relocation against local symbol to size of
12013 the symbol plus addend. */
12014 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12015 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12016 && !fits_in_unsigned_long (value
))
12017 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12018 _("symbol size computation overflow"));
12019 fixp
->fx_addsy
= NULL
;
12020 fixp
->fx_subsy
= NULL
;
12021 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12025 /* Fall through. */
12027 case BFD_RELOC_X86_64_PLT32
:
12028 case BFD_RELOC_X86_64_GOT32
:
12029 case BFD_RELOC_X86_64_GOTPCREL
:
12030 case BFD_RELOC_X86_64_GOTPCRELX
:
12031 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12032 case BFD_RELOC_386_PLT32
:
12033 case BFD_RELOC_386_GOT32
:
12034 case BFD_RELOC_386_GOT32X
:
12035 case BFD_RELOC_386_GOTOFF
:
12036 case BFD_RELOC_386_GOTPC
:
12037 case BFD_RELOC_386_TLS_GD
:
12038 case BFD_RELOC_386_TLS_LDM
:
12039 case BFD_RELOC_386_TLS_LDO_32
:
12040 case BFD_RELOC_386_TLS_IE_32
:
12041 case BFD_RELOC_386_TLS_IE
:
12042 case BFD_RELOC_386_TLS_GOTIE
:
12043 case BFD_RELOC_386_TLS_LE_32
:
12044 case BFD_RELOC_386_TLS_LE
:
12045 case BFD_RELOC_386_TLS_GOTDESC
:
12046 case BFD_RELOC_386_TLS_DESC_CALL
:
12047 case BFD_RELOC_X86_64_TLSGD
:
12048 case BFD_RELOC_X86_64_TLSLD
:
12049 case BFD_RELOC_X86_64_DTPOFF32
:
12050 case BFD_RELOC_X86_64_DTPOFF64
:
12051 case BFD_RELOC_X86_64_GOTTPOFF
:
12052 case BFD_RELOC_X86_64_TPOFF32
:
12053 case BFD_RELOC_X86_64_TPOFF64
:
12054 case BFD_RELOC_X86_64_GOTOFF64
:
12055 case BFD_RELOC_X86_64_GOTPC32
:
12056 case BFD_RELOC_X86_64_GOT64
:
12057 case BFD_RELOC_X86_64_GOTPCREL64
:
12058 case BFD_RELOC_X86_64_GOTPC64
:
12059 case BFD_RELOC_X86_64_GOTPLT64
:
12060 case BFD_RELOC_X86_64_PLTOFF64
:
12061 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12062 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12063 case BFD_RELOC_RVA
:
12064 case BFD_RELOC_VTABLE_ENTRY
:
12065 case BFD_RELOC_VTABLE_INHERIT
:
12067 case BFD_RELOC_32_SECREL
:
12069 code
= fixp
->fx_r_type
;
12071 case BFD_RELOC_X86_64_32S
:
12072 if (!fixp
->fx_pcrel
)
12074 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12075 code
= fixp
->fx_r_type
;
12078 /* Fall through. */
12080 if (fixp
->fx_pcrel
)
12082 switch (fixp
->fx_size
)
12085 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12086 _("can not do %d byte pc-relative relocation"),
12088 code
= BFD_RELOC_32_PCREL
;
12090 case 1: code
= BFD_RELOC_8_PCREL
; break;
12091 case 2: code
= BFD_RELOC_16_PCREL
; break;
12092 case 4: code
= BFD_RELOC_32_PCREL
; break;
12094 case 8: code
= BFD_RELOC_64_PCREL
; break;
12100 switch (fixp
->fx_size
)
12103 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12104 _("can not do %d byte relocation"),
12106 code
= BFD_RELOC_32
;
12108 case 1: code
= BFD_RELOC_8
; break;
12109 case 2: code
= BFD_RELOC_16
; break;
12110 case 4: code
= BFD_RELOC_32
; break;
12112 case 8: code
= BFD_RELOC_64
; break;
12119 if ((code
== BFD_RELOC_32
12120 || code
== BFD_RELOC_32_PCREL
12121 || code
== BFD_RELOC_X86_64_32S
)
12123 && fixp
->fx_addsy
== GOT_symbol
)
12126 code
= BFD_RELOC_386_GOTPC
;
12128 code
= BFD_RELOC_X86_64_GOTPC32
;
12130 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12132 && fixp
->fx_addsy
== GOT_symbol
)
12134 code
= BFD_RELOC_X86_64_GOTPC64
;
12137 rel
= XNEW (arelent
);
12138 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12139 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12141 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12143 if (!use_rela_relocations
)
12145 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12146 vtable entry to be used in the relocation's section offset. */
12147 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12148 rel
->address
= fixp
->fx_offset
;
12149 #if defined (OBJ_COFF) && defined (TE_PE)
12150 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12151 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12156 /* Use the rela in 64bit mode. */
12159 if (disallow_64bit_reloc
)
12162 case BFD_RELOC_X86_64_DTPOFF64
:
12163 case BFD_RELOC_X86_64_TPOFF64
:
12164 case BFD_RELOC_64_PCREL
:
12165 case BFD_RELOC_X86_64_GOTOFF64
:
12166 case BFD_RELOC_X86_64_GOT64
:
12167 case BFD_RELOC_X86_64_GOTPCREL64
:
12168 case BFD_RELOC_X86_64_GOTPC64
:
12169 case BFD_RELOC_X86_64_GOTPLT64
:
12170 case BFD_RELOC_X86_64_PLTOFF64
:
12171 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12172 _("cannot represent relocation type %s in x32 mode"),
12173 bfd_get_reloc_code_name (code
));
12179 if (!fixp
->fx_pcrel
)
12180 rel
->addend
= fixp
->fx_offset
;
12184 case BFD_RELOC_X86_64_PLT32
:
12185 case BFD_RELOC_X86_64_GOT32
:
12186 case BFD_RELOC_X86_64_GOTPCREL
:
12187 case BFD_RELOC_X86_64_GOTPCRELX
:
12188 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12189 case BFD_RELOC_X86_64_TLSGD
:
12190 case BFD_RELOC_X86_64_TLSLD
:
12191 case BFD_RELOC_X86_64_GOTTPOFF
:
12192 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12193 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12194 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12197 rel
->addend
= (section
->vma
12199 + fixp
->fx_addnumber
12200 + md_pcrel_from (fixp
));
12205 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12206 if (rel
->howto
== NULL
)
12208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12209 _("cannot represent relocation type %s"),
12210 bfd_get_reloc_code_name (code
));
12211 /* Set howto to a garbage value so that we can keep going. */
12212 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12213 gas_assert (rel
->howto
!= NULL
);
12219 #include "tc-i386-intel.c"
12222 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12224 int saved_naked_reg
;
12225 char saved_register_dot
;
12227 saved_naked_reg
= allow_naked_reg
;
12228 allow_naked_reg
= 1;
12229 saved_register_dot
= register_chars
['.'];
12230 register_chars
['.'] = '.';
12231 allow_pseudo_reg
= 1;
12232 expression_and_evaluate (exp
);
12233 allow_pseudo_reg
= 0;
12234 register_chars
['.'] = saved_register_dot
;
12235 allow_naked_reg
= saved_naked_reg
;
12237 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12239 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12241 exp
->X_op
= O_constant
;
12242 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12243 .dw2_regnum
[flag_code
>> 1];
12246 exp
->X_op
= O_illegal
;
12251 tc_x86_frame_initial_instructions (void)
12253 static unsigned int sp_regno
[2];
12255 if (!sp_regno
[flag_code
>> 1])
12257 char *saved_input
= input_line_pointer
;
12258 char sp
[][4] = {"esp", "rsp"};
12261 input_line_pointer
= sp
[flag_code
>> 1];
12262 tc_x86_parse_to_dw2regnum (&exp
);
12263 gas_assert (exp
.X_op
== O_constant
);
12264 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12265 input_line_pointer
= saved_input
;
12268 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12269 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12273 x86_dwarf2_addr_size (void)
12275 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12276 if (x86_elf_abi
== X86_64_X32_ABI
)
12279 return bfd_arch_bits_per_address (stdoutput
) / 8;
12283 i386_elf_section_type (const char *str
, size_t len
)
12285 if (flag_code
== CODE_64BIT
12286 && len
== sizeof ("unwind") - 1
12287 && strncmp (str
, "unwind", 6) == 0)
12288 return SHT_X86_64_UNWIND
;
12295 i386_solaris_fix_up_eh_frame (segT sec
)
12297 if (flag_code
== CODE_64BIT
)
12298 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12304 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12308 exp
.X_op
= O_secrel
;
12309 exp
.X_add_symbol
= symbol
;
12310 exp
.X_add_number
= 0;
12311 emit_expr (&exp
, size
);
12315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12316 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12319 x86_64_section_letter (int letter
, const char **ptr_msg
)
12321 if (flag_code
== CODE_64BIT
)
12324 return SHF_X86_64_LARGE
;
12326 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12329 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12334 x86_64_section_word (char *str
, size_t len
)
12336 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12337 return SHF_X86_64_LARGE
;
12343 handle_large_common (int small ATTRIBUTE_UNUSED
)
12345 if (flag_code
!= CODE_64BIT
)
12347 s_comm_internal (0, elf_common_parse
);
12348 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12352 static segT lbss_section
;
12353 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12354 asection
*saved_bss_section
= bss_section
;
12356 if (lbss_section
== NULL
)
12358 flagword applicable
;
12359 segT seg
= now_seg
;
12360 subsegT subseg
= now_subseg
;
12362 /* The .lbss section is for local .largecomm symbols. */
12363 lbss_section
= subseg_new (".lbss", 0);
12364 applicable
= bfd_applicable_section_flags (stdoutput
);
12365 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12366 seg_info (lbss_section
)->bss
= 1;
12368 subseg_set (seg
, subseg
);
12371 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12372 bss_section
= lbss_section
;
12374 s_comm_internal (0, elf_common_parse
);
12376 elf_com_section_ptr
= saved_com_section_ptr
;
12377 bss_section
= saved_bss_section
;
12380 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */