1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1018 CPU_BTVER1_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1020 CPU_BTVER2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1022 CPU_8087_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1030 CPU_CMOV_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1032 CPU_FXSR_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE3_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4A_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1044 CPU_SSSE3_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_1_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1053 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX2_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512F_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512CD_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512ER_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512PF_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512DQ_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512BW_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512VL_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1072 CPU_VMFUNC_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1075 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVE_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEOPT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEC_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVES_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 1 },
1089 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1090 CPU_FSGSBASE_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1092 CPU_RDRND_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1094 CPU_F16C_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1096 CPU_BMI2_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1100 CPU_FMA4_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1106 CPU_MOVBE_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1108 CPU_CX16_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_LZCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_POPCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1120 CPU_INVPCID_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1122 CPU_CLFLUSH_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1126 CPU_SYSCALL_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1128 CPU_RDTSCP_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOW_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOWA_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1134 CPU_PADLOCK_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 1 },
1137 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1140 CPU_SSE4A_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1150 CPU_RDSEED_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1152 CPU_PRFCHW_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1154 CPU_SMAP_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1160 CPU_CLFLUSHOPT_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1162 CPU_PREFETCHWT1_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1165 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1166 CPU_CLWB_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512IFMA_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512VBMI_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VBMI2_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VNNI_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BITALG_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX_VNNI_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1186 CPU_CLZERO_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1188 CPU_MWAITX_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1190 CPU_OSPKE_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1192 CPU_RDPID_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1194 CPU_PTWRITE_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1197 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1198 CPU_SHSTK_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1200 CPU_GFNI_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1202 CPU_VAES_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1204 CPU_VPCLMULQDQ_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1206 CPU_WBNOINVD_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1208 CPU_PCONFIG_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1210 CPU_WAITPKG_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1212 CPU_CLDEMOTE_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_INT8_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_BF16_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1218 CPU_AMX_TILE_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1220 CPU_MOVDIRI_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1222 CPU_MOVDIR64B_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1224 CPU_AVX512_BF16_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1226 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1229 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1230 CPU_ENQCMD_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1232 CPU_SERIALIZE_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1234 CPU_RDPRU_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1236 CPU_MCOMMIT_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1238 CPU_SEV_ES_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1240 CPU_TSXLDTRK_FLAGS
, 0 },
1241 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1243 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1244 CPU_WIDEKL_FLAGS
, 0 },
1245 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1246 CPU_UINTR_FLAGS
, 0 },
1247 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1248 CPU_HRESET_FLAGS
, 0 },
1251 static const noarch_entry cpu_noarch
[] =
1253 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1254 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1255 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1256 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1257 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1258 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1259 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1260 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1261 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1262 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1263 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1264 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1266 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1286 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1287 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1288 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1289 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1290 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1291 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1292 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1293 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1294 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1295 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1296 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1297 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1298 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1299 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1300 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1301 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1302 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1303 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1307 /* Like s_lcomm_internal in gas/read.c but the alignment string
1308 is allowed to be optional. */
1311 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1318 && *input_line_pointer
== ',')
1320 align
= parse_align (needs_align
- 1);
1322 if (align
== (addressT
) -1)
1337 bss_alloc (symbolP
, size
, align
);
1342 pe_lcomm (int needs_align
)
1344 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1348 const pseudo_typeS md_pseudo_table
[] =
1350 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1351 {"align", s_align_bytes
, 0},
1353 {"align", s_align_ptwo
, 0},
1355 {"arch", set_cpu_arch
, 0},
1359 {"lcomm", pe_lcomm
, 1},
1361 {"ffloat", float_cons
, 'f'},
1362 {"dfloat", float_cons
, 'd'},
1363 {"tfloat", float_cons
, 'x'},
1365 {"slong", signed_cons
, 4},
1366 {"noopt", s_ignore
, 0},
1367 {"optim", s_ignore
, 0},
1368 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1369 {"code16", set_code_flag
, CODE_16BIT
},
1370 {"code32", set_code_flag
, CODE_32BIT
},
1372 {"code64", set_code_flag
, CODE_64BIT
},
1374 {"intel_syntax", set_intel_syntax
, 1},
1375 {"att_syntax", set_intel_syntax
, 0},
1376 {"intel_mnemonic", set_intel_mnemonic
, 1},
1377 {"att_mnemonic", set_intel_mnemonic
, 0},
1378 {"allow_index_reg", set_allow_index_reg
, 1},
1379 {"disallow_index_reg", set_allow_index_reg
, 0},
1380 {"sse_check", set_check
, 0},
1381 {"operand_check", set_check
, 1},
1382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1383 {"largecomm", handle_large_common
, 0},
1385 {"file", dwarf2_directive_file
, 0},
1386 {"loc", dwarf2_directive_loc
, 0},
1387 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1390 {"secrel32", pe_directive_secrel
, 0},
1395 /* For interface with expression (). */
1396 extern char *input_line_pointer
;
1398 /* Hash table for instruction mnemonic lookup. */
1399 static htab_t op_hash
;
1401 /* Hash table for register lookup. */
1402 static htab_t reg_hash
;
1404 /* Various efficient no-op patterns for aligning code labels.
1405 Note: Don't try to assemble the instructions in the comments.
1406 0L and 0w are not legal. */
1407 static const unsigned char f32_1
[] =
1409 static const unsigned char f32_2
[] =
1410 {0x66,0x90}; /* xchg %ax,%ax */
1411 static const unsigned char f32_3
[] =
1412 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1413 static const unsigned char f32_4
[] =
1414 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1415 static const unsigned char f32_6
[] =
1416 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1417 static const unsigned char f32_7
[] =
1418 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1419 static const unsigned char f16_3
[] =
1420 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1421 static const unsigned char f16_4
[] =
1422 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1423 static const unsigned char jump_disp8
[] =
1424 {0xeb}; /* jmp disp8 */
1425 static const unsigned char jump32_disp32
[] =
1426 {0xe9}; /* jmp disp32 */
1427 static const unsigned char jump16_disp32
[] =
1428 {0x66,0xe9}; /* jmp disp32 */
1429 /* 32-bit NOPs patterns. */
1430 static const unsigned char *const f32_patt
[] = {
1431 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1433 /* 16-bit NOPs patterns. */
1434 static const unsigned char *const f16_patt
[] = {
1435 f32_1
, f32_2
, f16_3
, f16_4
1437 /* nopl (%[re]ax) */
1438 static const unsigned char alt_3
[] =
1440 /* nopl 0(%[re]ax) */
1441 static const unsigned char alt_4
[] =
1442 {0x0f,0x1f,0x40,0x00};
1443 /* nopl 0(%[re]ax,%[re]ax,1) */
1444 static const unsigned char alt_5
[] =
1445 {0x0f,0x1f,0x44,0x00,0x00};
1446 /* nopw 0(%[re]ax,%[re]ax,1) */
1447 static const unsigned char alt_6
[] =
1448 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1449 /* nopl 0L(%[re]ax) */
1450 static const unsigned char alt_7
[] =
1451 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1452 /* nopl 0L(%[re]ax,%[re]ax,1) */
1453 static const unsigned char alt_8
[] =
1454 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1455 /* nopw 0L(%[re]ax,%[re]ax,1) */
1456 static const unsigned char alt_9
[] =
1457 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1458 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1459 static const unsigned char alt_10
[] =
1460 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1461 /* data16 nopw %cs:0L(%eax,%eax,1) */
1462 static const unsigned char alt_11
[] =
1463 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1464 /* 32-bit and 64-bit NOPs patterns. */
1465 static const unsigned char *const alt_patt
[] = {
1466 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1467 alt_9
, alt_10
, alt_11
1470 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1471 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1474 i386_output_nops (char *where
, const unsigned char *const *patt
,
1475 int count
, int max_single_nop_size
)
1478 /* Place the longer NOP first. */
1481 const unsigned char *nops
;
1483 if (max_single_nop_size
< 1)
1485 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1486 max_single_nop_size
);
1490 nops
= patt
[max_single_nop_size
- 1];
1492 /* Use the smaller one if the requsted one isn't available. */
1495 max_single_nop_size
--;
1496 nops
= patt
[max_single_nop_size
- 1];
1499 last
= count
% max_single_nop_size
;
1502 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1503 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1507 nops
= patt
[last
- 1];
1510 /* Use the smaller one plus one-byte NOP if the needed one
1513 nops
= patt
[last
- 1];
1514 memcpy (where
+ offset
, nops
, last
);
1515 where
[offset
+ last
] = *patt
[0];
1518 memcpy (where
+ offset
, nops
, last
);
1523 fits_in_imm7 (offsetT num
)
1525 return (num
& 0x7f) == num
;
1529 fits_in_imm31 (offsetT num
)
1531 return (num
& 0x7fffffff) == num
;
1534 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1535 single NOP instruction LIMIT. */
1538 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1540 const unsigned char *const *patt
= NULL
;
1541 int max_single_nop_size
;
1542 /* Maximum number of NOPs before switching to jump over NOPs. */
1543 int max_number_of_nops
;
1545 switch (fragP
->fr_type
)
1550 case rs_machine_dependent
:
1551 /* Allow NOP padding for jumps and calls. */
1552 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1553 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1560 /* We need to decide which NOP sequence to use for 32bit and
1561 64bit. When -mtune= is used:
1563 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1564 PROCESSOR_GENERIC32, f32_patt will be used.
1565 2. For the rest, alt_patt will be used.
1567 When -mtune= isn't used, alt_patt will be used if
1568 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1571 When -march= or .arch is used, we can't use anything beyond
1572 cpu_arch_isa_flags. */
1574 if (flag_code
== CODE_16BIT
)
1577 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1578 /* Limit number of NOPs to 2 in 16-bit mode. */
1579 max_number_of_nops
= 2;
1583 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1585 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1586 switch (cpu_arch_tune
)
1588 case PROCESSOR_UNKNOWN
:
1589 /* We use cpu_arch_isa_flags to check if we SHOULD
1590 optimize with nops. */
1591 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1596 case PROCESSOR_PENTIUM4
:
1597 case PROCESSOR_NOCONA
:
1598 case PROCESSOR_CORE
:
1599 case PROCESSOR_CORE2
:
1600 case PROCESSOR_COREI7
:
1601 case PROCESSOR_L1OM
:
1602 case PROCESSOR_K1OM
:
1603 case PROCESSOR_GENERIC64
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1613 case PROCESSOR_I386
:
1614 case PROCESSOR_I486
:
1615 case PROCESSOR_PENTIUM
:
1616 case PROCESSOR_PENTIUMPRO
:
1617 case PROCESSOR_IAMCU
:
1618 case PROCESSOR_GENERIC32
:
1625 switch (fragP
->tc_frag_data
.tune
)
1627 case PROCESSOR_UNKNOWN
:
1628 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1629 PROCESSOR_UNKNOWN. */
1633 case PROCESSOR_I386
:
1634 case PROCESSOR_I486
:
1635 case PROCESSOR_PENTIUM
:
1636 case PROCESSOR_IAMCU
:
1638 case PROCESSOR_ATHLON
:
1640 case PROCESSOR_AMDFAM10
:
1642 case PROCESSOR_ZNVER
:
1644 case PROCESSOR_GENERIC32
:
1645 /* We use cpu_arch_isa_flags to check if we CAN optimize
1647 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1652 case PROCESSOR_PENTIUMPRO
:
1653 case PROCESSOR_PENTIUM4
:
1654 case PROCESSOR_NOCONA
:
1655 case PROCESSOR_CORE
:
1656 case PROCESSOR_CORE2
:
1657 case PROCESSOR_COREI7
:
1658 case PROCESSOR_L1OM
:
1659 case PROCESSOR_K1OM
:
1660 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1665 case PROCESSOR_GENERIC64
:
1671 if (patt
== f32_patt
)
1673 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1674 /* Limit number of NOPs to 2 for older processors. */
1675 max_number_of_nops
= 2;
1679 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1680 /* Limit number of NOPs to 7 for newer processors. */
1681 max_number_of_nops
= 7;
1686 limit
= max_single_nop_size
;
1688 if (fragP
->fr_type
== rs_fill_nop
)
1690 /* Output NOPs for .nop directive. */
1691 if (limit
> max_single_nop_size
)
1693 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1694 _("invalid single nop size: %d "
1695 "(expect within [0, %d])"),
1696 limit
, max_single_nop_size
);
1700 else if (fragP
->fr_type
!= rs_machine_dependent
)
1701 fragP
->fr_var
= count
;
1703 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1705 /* Generate jump over NOPs. */
1706 offsetT disp
= count
- 2;
1707 if (fits_in_imm7 (disp
))
1709 /* Use "jmp disp8" if possible. */
1711 where
[0] = jump_disp8
[0];
1717 unsigned int size_of_jump
;
1719 if (flag_code
== CODE_16BIT
)
1721 where
[0] = jump16_disp32
[0];
1722 where
[1] = jump16_disp32
[1];
1727 where
[0] = jump32_disp32
[0];
1731 count
-= size_of_jump
+ 4;
1732 if (!fits_in_imm31 (count
))
1734 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1735 _("jump over nop padding out of range"));
1739 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1740 where
+= size_of_jump
+ 4;
1744 /* Generate multiple NOPs. */
1745 i386_output_nops (where
, patt
, count
, limit
);
1749 operand_type_all_zero (const union i386_operand_type
*x
)
1751 switch (ARRAY_SIZE(x
->array
))
1762 return !x
->array
[0];
1769 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1771 switch (ARRAY_SIZE(x
->array
))
1787 x
->bitfield
.class = ClassNone
;
1788 x
->bitfield
.instance
= InstanceNone
;
1792 operand_type_equal (const union i386_operand_type
*x
,
1793 const union i386_operand_type
*y
)
1795 switch (ARRAY_SIZE(x
->array
))
1798 if (x
->array
[2] != y
->array
[2])
1802 if (x
->array
[1] != y
->array
[1])
1806 return x
->array
[0] == y
->array
[0];
1814 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1816 switch (ARRAY_SIZE(x
->array
))
1831 return !x
->array
[0];
1838 cpu_flags_equal (const union i386_cpu_flags
*x
,
1839 const union i386_cpu_flags
*y
)
1841 switch (ARRAY_SIZE(x
->array
))
1844 if (x
->array
[3] != y
->array
[3])
1848 if (x
->array
[2] != y
->array
[2])
1852 if (x
->array
[1] != y
->array
[1])
1856 return x
->array
[0] == y
->array
[0];
1864 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1866 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1867 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1870 static INLINE i386_cpu_flags
1871 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1873 switch (ARRAY_SIZE (x
.array
))
1876 x
.array
[3] &= y
.array
[3];
1879 x
.array
[2] &= y
.array
[2];
1882 x
.array
[1] &= y
.array
[1];
1885 x
.array
[0] &= y
.array
[0];
1893 static INLINE i386_cpu_flags
1894 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1896 switch (ARRAY_SIZE (x
.array
))
1899 x
.array
[3] |= y
.array
[3];
1902 x
.array
[2] |= y
.array
[2];
1905 x
.array
[1] |= y
.array
[1];
1908 x
.array
[0] |= y
.array
[0];
1916 static INLINE i386_cpu_flags
1917 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1919 switch (ARRAY_SIZE (x
.array
))
1922 x
.array
[3] &= ~y
.array
[3];
1925 x
.array
[2] &= ~y
.array
[2];
1928 x
.array
[1] &= ~y
.array
[1];
1931 x
.array
[0] &= ~y
.array
[0];
1939 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1941 #define CPU_FLAGS_ARCH_MATCH 0x1
1942 #define CPU_FLAGS_64BIT_MATCH 0x2
1944 #define CPU_FLAGS_PERFECT_MATCH \
1945 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1947 /* Return CPU flags match bits. */
1950 cpu_flags_match (const insn_template
*t
)
1952 i386_cpu_flags x
= t
->cpu_flags
;
1953 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1955 x
.bitfield
.cpu64
= 0;
1956 x
.bitfield
.cpuno64
= 0;
1958 if (cpu_flags_all_zero (&x
))
1960 /* This instruction is available on all archs. */
1961 match
|= CPU_FLAGS_ARCH_MATCH
;
1965 /* This instruction is available only on some archs. */
1966 i386_cpu_flags cpu
= cpu_arch_flags
;
1968 /* AVX512VL is no standalone feature - match it and then strip it. */
1969 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1971 x
.bitfield
.cpuavx512vl
= 0;
1973 cpu
= cpu_flags_and (x
, cpu
);
1974 if (!cpu_flags_all_zero (&cpu
))
1976 if (x
.bitfield
.cpuavx
)
1978 /* We need to check a few extra flags with AVX. */
1979 if (cpu
.bitfield
.cpuavx
1980 && (!t
->opcode_modifier
.sse2avx
1981 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1982 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1983 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1984 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1985 match
|= CPU_FLAGS_ARCH_MATCH
;
1987 else if (x
.bitfield
.cpuavx512f
)
1989 /* We need to check a few extra flags with AVX512F. */
1990 if (cpu
.bitfield
.cpuavx512f
1991 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1992 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1993 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1994 match
|= CPU_FLAGS_ARCH_MATCH
;
1997 match
|= CPU_FLAGS_ARCH_MATCH
;
2003 static INLINE i386_operand_type
2004 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2006 if (x
.bitfield
.class != y
.bitfield
.class)
2007 x
.bitfield
.class = ClassNone
;
2008 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2009 x
.bitfield
.instance
= InstanceNone
;
2011 switch (ARRAY_SIZE (x
.array
))
2014 x
.array
[2] &= y
.array
[2];
2017 x
.array
[1] &= y
.array
[1];
2020 x
.array
[0] &= y
.array
[0];
2028 static INLINE i386_operand_type
2029 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2031 gas_assert (y
.bitfield
.class == ClassNone
);
2032 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2034 switch (ARRAY_SIZE (x
.array
))
2037 x
.array
[2] &= ~y
.array
[2];
2040 x
.array
[1] &= ~y
.array
[1];
2043 x
.array
[0] &= ~y
.array
[0];
2051 static INLINE i386_operand_type
2052 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2054 gas_assert (x
.bitfield
.class == ClassNone
||
2055 y
.bitfield
.class == ClassNone
||
2056 x
.bitfield
.class == y
.bitfield
.class);
2057 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2058 y
.bitfield
.instance
== InstanceNone
||
2059 x
.bitfield
.instance
== y
.bitfield
.instance
);
2061 switch (ARRAY_SIZE (x
.array
))
2064 x
.array
[2] |= y
.array
[2];
2067 x
.array
[1] |= y
.array
[1];
2070 x
.array
[0] |= y
.array
[0];
2078 static INLINE i386_operand_type
2079 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2081 gas_assert (y
.bitfield
.class == ClassNone
);
2082 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2084 switch (ARRAY_SIZE (x
.array
))
2087 x
.array
[2] ^= y
.array
[2];
2090 x
.array
[1] ^= y
.array
[1];
2093 x
.array
[0] ^= y
.array
[0];
2101 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2102 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2103 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2104 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2105 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2106 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2107 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2108 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2109 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2110 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2111 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2112 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2113 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2114 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2115 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2116 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2117 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2128 operand_type_check (i386_operand_type t
, enum operand_type c
)
2133 return t
.bitfield
.class == Reg
;
2136 return (t
.bitfield
.imm8
2140 || t
.bitfield
.imm32s
2141 || t
.bitfield
.imm64
);
2144 return (t
.bitfield
.disp8
2145 || t
.bitfield
.disp16
2146 || t
.bitfield
.disp32
2147 || t
.bitfield
.disp32s
2148 || t
.bitfield
.disp64
);
2151 return (t
.bitfield
.disp8
2152 || t
.bitfield
.disp16
2153 || t
.bitfield
.disp32
2154 || t
.bitfield
.disp32s
2155 || t
.bitfield
.disp64
2156 || t
.bitfield
.baseindex
);
2165 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2166 between operand GIVEN and opeand WANTED for instruction template T. */
2169 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2172 return !((i
.types
[given
].bitfield
.byte
2173 && !t
->operand_types
[wanted
].bitfield
.byte
)
2174 || (i
.types
[given
].bitfield
.word
2175 && !t
->operand_types
[wanted
].bitfield
.word
)
2176 || (i
.types
[given
].bitfield
.dword
2177 && !t
->operand_types
[wanted
].bitfield
.dword
)
2178 || (i
.types
[given
].bitfield
.qword
2179 && !t
->operand_types
[wanted
].bitfield
.qword
)
2180 || (i
.types
[given
].bitfield
.tbyte
2181 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2184 /* Return 1 if there is no conflict in SIMD register between operand
2185 GIVEN and opeand WANTED for instruction template T. */
2188 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2191 return !((i
.types
[given
].bitfield
.xmmword
2192 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2193 || (i
.types
[given
].bitfield
.ymmword
2194 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2195 || (i
.types
[given
].bitfield
.zmmword
2196 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2197 || (i
.types
[given
].bitfield
.tmmword
2198 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2201 /* Return 1 if there is no conflict in any size between operand GIVEN
2202 and opeand WANTED for instruction template T. */
2205 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2208 return (match_operand_size (t
, wanted
, given
)
2209 && !((i
.types
[given
].bitfield
.unspecified
2211 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2212 || (i
.types
[given
].bitfield
.fword
2213 && !t
->operand_types
[wanted
].bitfield
.fword
)
2214 /* For scalar opcode templates to allow register and memory
2215 operands at the same time, some special casing is needed
2216 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2217 down-conversion vpmov*. */
2218 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2219 && t
->operand_types
[wanted
].bitfield
.byte
2220 + t
->operand_types
[wanted
].bitfield
.word
2221 + t
->operand_types
[wanted
].bitfield
.dword
2222 + t
->operand_types
[wanted
].bitfield
.qword
2223 > !!t
->opcode_modifier
.broadcast
)
2224 ? (i
.types
[given
].bitfield
.xmmword
2225 || i
.types
[given
].bitfield
.ymmword
2226 || i
.types
[given
].bitfield
.zmmword
)
2227 : !match_simd_size(t
, wanted
, given
))));
2230 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2231 operands for instruction template T, and it has MATCH_REVERSE set if there
2232 is no size conflict on any operands for the template with operands reversed
2233 (and the template allows for reversing in the first place). */
2235 #define MATCH_STRAIGHT 1
2236 #define MATCH_REVERSE 2
2238 static INLINE
unsigned int
2239 operand_size_match (const insn_template
*t
)
2241 unsigned int j
, match
= MATCH_STRAIGHT
;
2243 /* Don't check non-absolute jump instructions. */
2244 if (t
->opcode_modifier
.jump
2245 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2248 /* Check memory and accumulator operand size. */
2249 for (j
= 0; j
< i
.operands
; j
++)
2251 if (i
.types
[j
].bitfield
.class != Reg
2252 && i
.types
[j
].bitfield
.class != RegSIMD
2253 && t
->opcode_modifier
.anysize
)
2256 if (t
->operand_types
[j
].bitfield
.class == Reg
2257 && !match_operand_size (t
, j
, j
))
2263 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2264 && !match_simd_size (t
, j
, j
))
2270 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2271 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2277 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2284 if (!t
->opcode_modifier
.d
)
2288 i
.error
= operand_size_mismatch
;
2292 /* Check reverse. */
2293 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2295 for (j
= 0; j
< i
.operands
; j
++)
2297 unsigned int given
= i
.operands
- j
- 1;
2299 if (t
->operand_types
[j
].bitfield
.class == Reg
2300 && !match_operand_size (t
, j
, given
))
2303 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2304 && !match_simd_size (t
, j
, given
))
2307 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2308 && (!match_operand_size (t
, j
, given
)
2309 || !match_simd_size (t
, j
, given
)))
2312 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2316 return match
| MATCH_REVERSE
;
2320 operand_type_match (i386_operand_type overlap
,
2321 i386_operand_type given
)
2323 i386_operand_type temp
= overlap
;
2325 temp
.bitfield
.unspecified
= 0;
2326 temp
.bitfield
.byte
= 0;
2327 temp
.bitfield
.word
= 0;
2328 temp
.bitfield
.dword
= 0;
2329 temp
.bitfield
.fword
= 0;
2330 temp
.bitfield
.qword
= 0;
2331 temp
.bitfield
.tbyte
= 0;
2332 temp
.bitfield
.xmmword
= 0;
2333 temp
.bitfield
.ymmword
= 0;
2334 temp
.bitfield
.zmmword
= 0;
2335 temp
.bitfield
.tmmword
= 0;
2336 if (operand_type_all_zero (&temp
))
2339 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2343 i
.error
= operand_type_mismatch
;
2347 /* If given types g0 and g1 are registers they must be of the same type
2348 unless the expected operand type register overlap is null.
2349 Some Intel syntax memory operand size checking also happens here. */
2352 operand_type_register_match (i386_operand_type g0
,
2353 i386_operand_type t0
,
2354 i386_operand_type g1
,
2355 i386_operand_type t1
)
2357 if (g0
.bitfield
.class != Reg
2358 && g0
.bitfield
.class != RegSIMD
2359 && (!operand_type_check (g0
, anymem
)
2360 || g0
.bitfield
.unspecified
2361 || (t0
.bitfield
.class != Reg
2362 && t0
.bitfield
.class != RegSIMD
)))
2365 if (g1
.bitfield
.class != Reg
2366 && g1
.bitfield
.class != RegSIMD
2367 && (!operand_type_check (g1
, anymem
)
2368 || g1
.bitfield
.unspecified
2369 || (t1
.bitfield
.class != Reg
2370 && t1
.bitfield
.class != RegSIMD
)))
2373 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2374 && g0
.bitfield
.word
== g1
.bitfield
.word
2375 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2376 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2377 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2378 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2379 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2382 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2383 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2384 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2385 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2386 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2387 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2388 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2391 i
.error
= register_type_mismatch
;
2396 static INLINE
unsigned int
2397 register_number (const reg_entry
*r
)
2399 unsigned int nr
= r
->reg_num
;
2401 if (r
->reg_flags
& RegRex
)
2404 if (r
->reg_flags
& RegVRex
)
2410 static INLINE
unsigned int
2411 mode_from_disp_size (i386_operand_type t
)
2413 if (t
.bitfield
.disp8
)
2415 else if (t
.bitfield
.disp16
2416 || t
.bitfield
.disp32
2417 || t
.bitfield
.disp32s
)
2424 fits_in_signed_byte (addressT num
)
2426 return num
+ 0x80 <= 0xff;
2430 fits_in_unsigned_byte (addressT num
)
2436 fits_in_unsigned_word (addressT num
)
2438 return num
<= 0xffff;
2442 fits_in_signed_word (addressT num
)
2444 return num
+ 0x8000 <= 0xffff;
2448 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2453 return num
+ 0x80000000 <= 0xffffffff;
2455 } /* fits_in_signed_long() */
2458 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2463 return num
<= 0xffffffff;
2465 } /* fits_in_unsigned_long() */
2468 fits_in_disp8 (offsetT num
)
2470 int shift
= i
.memshift
;
2476 mask
= (1 << shift
) - 1;
2478 /* Return 0 if NUM isn't properly aligned. */
2482 /* Check if NUM will fit in 8bit after shift. */
2483 return fits_in_signed_byte (num
>> shift
);
2487 fits_in_imm4 (offsetT num
)
2489 return (num
& 0xf) == num
;
2492 static i386_operand_type
2493 smallest_imm_type (offsetT num
)
2495 i386_operand_type t
;
2497 operand_type_set (&t
, 0);
2498 t
.bitfield
.imm64
= 1;
2500 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2502 /* This code is disabled on the 486 because all the Imm1 forms
2503 in the opcode table are slower on the i486. They're the
2504 versions with the implicitly specified single-position
2505 displacement, which has another syntax if you really want to
2507 t
.bitfield
.imm1
= 1;
2508 t
.bitfield
.imm8
= 1;
2509 t
.bitfield
.imm8s
= 1;
2510 t
.bitfield
.imm16
= 1;
2511 t
.bitfield
.imm32
= 1;
2512 t
.bitfield
.imm32s
= 1;
2514 else if (fits_in_signed_byte (num
))
2516 t
.bitfield
.imm8
= 1;
2517 t
.bitfield
.imm8s
= 1;
2518 t
.bitfield
.imm16
= 1;
2519 t
.bitfield
.imm32
= 1;
2520 t
.bitfield
.imm32s
= 1;
2522 else if (fits_in_unsigned_byte (num
))
2524 t
.bitfield
.imm8
= 1;
2525 t
.bitfield
.imm16
= 1;
2526 t
.bitfield
.imm32
= 1;
2527 t
.bitfield
.imm32s
= 1;
2529 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2531 t
.bitfield
.imm16
= 1;
2532 t
.bitfield
.imm32
= 1;
2533 t
.bitfield
.imm32s
= 1;
2535 else if (fits_in_signed_long (num
))
2537 t
.bitfield
.imm32
= 1;
2538 t
.bitfield
.imm32s
= 1;
2540 else if (fits_in_unsigned_long (num
))
2541 t
.bitfield
.imm32
= 1;
2547 offset_in_range (offsetT val
, int size
)
2553 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2554 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2555 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2557 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2562 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2564 char buf1
[40], buf2
[40];
2566 sprint_value (buf1
, val
);
2567 sprint_value (buf2
, val
& mask
);
2568 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2583 a. PREFIX_EXIST if attempting to add a prefix where one from the
2584 same class already exists.
2585 b. PREFIX_LOCK if lock prefix is added.
2586 c. PREFIX_REP if rep/repne prefix is added.
2587 d. PREFIX_DS if ds prefix is added.
2588 e. PREFIX_OTHER if other prefix is added.
2591 static enum PREFIX_GROUP
2592 add_prefix (unsigned int prefix
)
2594 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2597 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2598 && flag_code
== CODE_64BIT
)
2600 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2601 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2602 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2603 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2614 case DS_PREFIX_OPCODE
:
2617 case CS_PREFIX_OPCODE
:
2618 case ES_PREFIX_OPCODE
:
2619 case FS_PREFIX_OPCODE
:
2620 case GS_PREFIX_OPCODE
:
2621 case SS_PREFIX_OPCODE
:
2625 case REPNE_PREFIX_OPCODE
:
2626 case REPE_PREFIX_OPCODE
:
2631 case LOCK_PREFIX_OPCODE
:
2640 case ADDR_PREFIX_OPCODE
:
2644 case DATA_PREFIX_OPCODE
:
2648 if (i
.prefix
[q
] != 0)
2656 i
.prefix
[q
] |= prefix
;
2659 as_bad (_("same type of prefix used twice"));
2665 update_code_flag (int value
, int check
)
2667 PRINTF_LIKE ((*as_error
));
2669 flag_code
= (enum flag_code
) value
;
2670 if (flag_code
== CODE_64BIT
)
2672 cpu_arch_flags
.bitfield
.cpu64
= 1;
2673 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2677 cpu_arch_flags
.bitfield
.cpu64
= 0;
2678 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2680 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2683 as_error
= as_fatal
;
2686 (*as_error
) (_("64bit mode not supported on `%s'."),
2687 cpu_arch_name
? cpu_arch_name
: default_arch
);
2689 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2692 as_error
= as_fatal
;
2695 (*as_error
) (_("32bit mode not supported on `%s'."),
2696 cpu_arch_name
? cpu_arch_name
: default_arch
);
2698 stackop_size
= '\0';
2702 set_code_flag (int value
)
2704 update_code_flag (value
, 0);
2708 set_16bit_gcc_code_flag (int new_code_flag
)
2710 flag_code
= (enum flag_code
) new_code_flag
;
2711 if (flag_code
!= CODE_16BIT
)
2713 cpu_arch_flags
.bitfield
.cpu64
= 0;
2714 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2715 stackop_size
= LONG_MNEM_SUFFIX
;
2719 set_intel_syntax (int syntax_flag
)
2721 /* Find out if register prefixing is specified. */
2722 int ask_naked_reg
= 0;
2725 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2728 int e
= get_symbol_name (&string
);
2730 if (strcmp (string
, "prefix") == 0)
2732 else if (strcmp (string
, "noprefix") == 0)
2735 as_bad (_("bad argument to syntax directive."));
2736 (void) restore_line_pointer (e
);
2738 demand_empty_rest_of_line ();
2740 intel_syntax
= syntax_flag
;
2742 if (ask_naked_reg
== 0)
2743 allow_naked_reg
= (intel_syntax
2744 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2746 allow_naked_reg
= (ask_naked_reg
< 0);
2748 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2750 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2751 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2752 register_prefix
= allow_naked_reg
? "" : "%";
2756 set_intel_mnemonic (int mnemonic_flag
)
2758 intel_mnemonic
= mnemonic_flag
;
2762 set_allow_index_reg (int flag
)
2764 allow_index_reg
= flag
;
2768 set_check (int what
)
2770 enum check_kind
*kind
;
2775 kind
= &operand_check
;
2786 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2789 int e
= get_symbol_name (&string
);
2791 if (strcmp (string
, "none") == 0)
2793 else if (strcmp (string
, "warning") == 0)
2794 *kind
= check_warning
;
2795 else if (strcmp (string
, "error") == 0)
2796 *kind
= check_error
;
2798 as_bad (_("bad argument to %s_check directive."), str
);
2799 (void) restore_line_pointer (e
);
2802 as_bad (_("missing argument for %s_check directive"), str
);
2804 demand_empty_rest_of_line ();
2808 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2809 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2811 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2812 static const char *arch
;
2814 /* Intel LIOM is only supported on ELF. */
2820 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2821 use default_arch. */
2822 arch
= cpu_arch_name
;
2824 arch
= default_arch
;
2827 /* If we are targeting Intel MCU, we must enable it. */
2828 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2829 || new_flag
.bitfield
.cpuiamcu
)
2832 /* If we are targeting Intel L1OM, we must enable it. */
2833 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2834 || new_flag
.bitfield
.cpul1om
)
2837 /* If we are targeting Intel K1OM, we must enable it. */
2838 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2839 || new_flag
.bitfield
.cpuk1om
)
2842 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2847 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2851 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2854 int e
= get_symbol_name (&string
);
2856 i386_cpu_flags flags
;
2858 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2860 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2862 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2866 cpu_arch_name
= cpu_arch
[j
].name
;
2867 cpu_sub_arch_name
= NULL
;
2868 cpu_arch_flags
= cpu_arch
[j
].flags
;
2869 if (flag_code
== CODE_64BIT
)
2871 cpu_arch_flags
.bitfield
.cpu64
= 1;
2872 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2876 cpu_arch_flags
.bitfield
.cpu64
= 0;
2877 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2879 cpu_arch_isa
= cpu_arch
[j
].type
;
2880 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2881 if (!cpu_arch_tune_set
)
2883 cpu_arch_tune
= cpu_arch_isa
;
2884 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2889 flags
= cpu_flags_or (cpu_arch_flags
,
2892 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2894 if (cpu_sub_arch_name
)
2896 char *name
= cpu_sub_arch_name
;
2897 cpu_sub_arch_name
= concat (name
,
2899 (const char *) NULL
);
2903 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2904 cpu_arch_flags
= flags
;
2905 cpu_arch_isa_flags
= flags
;
2909 = cpu_flags_or (cpu_arch_isa_flags
,
2911 (void) restore_line_pointer (e
);
2912 demand_empty_rest_of_line ();
2917 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2919 /* Disable an ISA extension. */
2920 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2921 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2923 flags
= cpu_flags_and_not (cpu_arch_flags
,
2924 cpu_noarch
[j
].flags
);
2925 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2927 if (cpu_sub_arch_name
)
2929 char *name
= cpu_sub_arch_name
;
2930 cpu_sub_arch_name
= concat (name
, string
,
2931 (const char *) NULL
);
2935 cpu_sub_arch_name
= xstrdup (string
);
2936 cpu_arch_flags
= flags
;
2937 cpu_arch_isa_flags
= flags
;
2939 (void) restore_line_pointer (e
);
2940 demand_empty_rest_of_line ();
2944 j
= ARRAY_SIZE (cpu_arch
);
2947 if (j
>= ARRAY_SIZE (cpu_arch
))
2948 as_bad (_("no such architecture: `%s'"), string
);
2950 *input_line_pointer
= e
;
2953 as_bad (_("missing cpu architecture"));
2955 no_cond_jump_promotion
= 0;
2956 if (*input_line_pointer
== ','
2957 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2962 ++input_line_pointer
;
2963 e
= get_symbol_name (&string
);
2965 if (strcmp (string
, "nojumps") == 0)
2966 no_cond_jump_promotion
= 1;
2967 else if (strcmp (string
, "jumps") == 0)
2970 as_bad (_("no such architecture modifier: `%s'"), string
);
2972 (void) restore_line_pointer (e
);
2975 demand_empty_rest_of_line ();
2978 enum bfd_architecture
2981 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2983 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2984 || flag_code
!= CODE_64BIT
)
2985 as_fatal (_("Intel L1OM is 64bit ELF only"));
2986 return bfd_arch_l1om
;
2988 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2990 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2991 || flag_code
!= CODE_64BIT
)
2992 as_fatal (_("Intel K1OM is 64bit ELF only"));
2993 return bfd_arch_k1om
;
2995 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2997 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2998 || flag_code
== CODE_64BIT
)
2999 as_fatal (_("Intel MCU is 32bit ELF only"));
3000 return bfd_arch_iamcu
;
3003 return bfd_arch_i386
;
3009 if (!strncmp (default_arch
, "x86_64", 6))
3011 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3013 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3014 || default_arch
[6] != '\0')
3015 as_fatal (_("Intel L1OM is 64bit ELF only"));
3016 return bfd_mach_l1om
;
3018 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3020 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3021 || default_arch
[6] != '\0')
3022 as_fatal (_("Intel K1OM is 64bit ELF only"));
3023 return bfd_mach_k1om
;
3025 else if (default_arch
[6] == '\0')
3026 return bfd_mach_x86_64
;
3028 return bfd_mach_x64_32
;
3030 else if (!strcmp (default_arch
, "i386")
3031 || !strcmp (default_arch
, "iamcu"))
3033 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3035 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3036 as_fatal (_("Intel MCU is 32bit ELF only"));
3037 return bfd_mach_i386_iamcu
;
3040 return bfd_mach_i386_i386
;
3043 as_fatal (_("unknown architecture"));
3049 /* Support pseudo prefixes like {disp32}. */
3050 lex_type
['{'] = LEX_BEGIN_NAME
;
3052 /* Initialize op_hash hash table. */
3053 op_hash
= str_htab_create ();
3056 const insn_template
*optab
;
3057 templates
*core_optab
;
3059 /* Setup for loop. */
3061 core_optab
= XNEW (templates
);
3062 core_optab
->start
= optab
;
3067 if (optab
->name
== NULL
3068 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3070 /* different name --> ship out current template list;
3071 add to hash table; & begin anew. */
3072 core_optab
->end
= optab
;
3073 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3074 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3076 if (optab
->name
== NULL
)
3078 core_optab
= XNEW (templates
);
3079 core_optab
->start
= optab
;
3084 /* Initialize reg_hash hash table. */
3085 reg_hash
= str_htab_create ();
3087 const reg_entry
*regtab
;
3088 unsigned int regtab_size
= i386_regtab_size
;
3090 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3091 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3092 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3095 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3100 for (c
= 0; c
< 256; c
++)
3105 mnemonic_chars
[c
] = c
;
3106 register_chars
[c
] = c
;
3107 operand_chars
[c
] = c
;
3109 else if (ISLOWER (c
))
3111 mnemonic_chars
[c
] = c
;
3112 register_chars
[c
] = c
;
3113 operand_chars
[c
] = c
;
3115 else if (ISUPPER (c
))
3117 mnemonic_chars
[c
] = TOLOWER (c
);
3118 register_chars
[c
] = mnemonic_chars
[c
];
3119 operand_chars
[c
] = c
;
3121 else if (c
== '{' || c
== '}')
3123 mnemonic_chars
[c
] = c
;
3124 operand_chars
[c
] = c
;
3126 #ifdef SVR4_COMMENT_CHARS
3127 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3128 operand_chars
[c
] = c
;
3131 if (ISALPHA (c
) || ISDIGIT (c
))
3132 identifier_chars
[c
] = c
;
3135 identifier_chars
[c
] = c
;
3136 operand_chars
[c
] = c
;
3141 identifier_chars
['@'] = '@';
3144 identifier_chars
['?'] = '?';
3145 operand_chars
['?'] = '?';
3147 digit_chars
['-'] = '-';
3148 mnemonic_chars
['_'] = '_';
3149 mnemonic_chars
['-'] = '-';
3150 mnemonic_chars
['.'] = '.';
3151 identifier_chars
['_'] = '_';
3152 identifier_chars
['.'] = '.';
3154 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3155 operand_chars
[(unsigned char) *p
] = *p
;
3158 if (flag_code
== CODE_64BIT
)
3160 #if defined (OBJ_COFF) && defined (TE_PE)
3161 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3164 x86_dwarf2_return_column
= 16;
3166 x86_cie_data_alignment
= -8;
3170 x86_dwarf2_return_column
= 8;
3171 x86_cie_data_alignment
= -4;
3174 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3175 can be turned into BRANCH_PREFIX frag. */
3176 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3181 i386_print_statistics (FILE *file
)
3183 htab_print_statistics (file
, "i386 opcode", op_hash
);
3184 htab_print_statistics (file
, "i386 register", reg_hash
);
3189 /* Debugging routines for md_assemble. */
3190 static void pte (insn_template
*);
3191 static void pt (i386_operand_type
);
3192 static void pe (expressionS
*);
3193 static void ps (symbolS
*);
3196 pi (const char *line
, i386_insn
*x
)
3200 fprintf (stdout
, "%s: template ", line
);
3202 fprintf (stdout
, " address: base %s index %s scale %x\n",
3203 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3204 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3205 x
->log2_scale_factor
);
3206 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3207 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3208 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3209 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3210 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3211 (x
->rex
& REX_W
) != 0,
3212 (x
->rex
& REX_R
) != 0,
3213 (x
->rex
& REX_X
) != 0,
3214 (x
->rex
& REX_B
) != 0);
3215 for (j
= 0; j
< x
->operands
; j
++)
3217 fprintf (stdout
, " #%d: ", j
+ 1);
3219 fprintf (stdout
, "\n");
3220 if (x
->types
[j
].bitfield
.class == Reg
3221 || x
->types
[j
].bitfield
.class == RegMMX
3222 || x
->types
[j
].bitfield
.class == RegSIMD
3223 || x
->types
[j
].bitfield
.class == RegMask
3224 || x
->types
[j
].bitfield
.class == SReg
3225 || x
->types
[j
].bitfield
.class == RegCR
3226 || x
->types
[j
].bitfield
.class == RegDR
3227 || x
->types
[j
].bitfield
.class == RegTR
3228 || x
->types
[j
].bitfield
.class == RegBND
)
3229 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3230 if (operand_type_check (x
->types
[j
], imm
))
3232 if (operand_type_check (x
->types
[j
], disp
))
3233 pe (x
->op
[j
].disps
);
3238 pte (insn_template
*t
)
3241 fprintf (stdout
, " %d operands ", t
->operands
);
3242 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3243 if (t
->extension_opcode
!= None
)
3244 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3245 if (t
->opcode_modifier
.d
)
3246 fprintf (stdout
, "D");
3247 if (t
->opcode_modifier
.w
)
3248 fprintf (stdout
, "W");
3249 fprintf (stdout
, "\n");
3250 for (j
= 0; j
< t
->operands
; j
++)
3252 fprintf (stdout
, " #%d type ", j
+ 1);
3253 pt (t
->operand_types
[j
]);
3254 fprintf (stdout
, "\n");
3261 fprintf (stdout
, " operation %d\n", e
->X_op
);
3262 fprintf (stdout
, " add_number %ld (%lx)\n",
3263 (long) e
->X_add_number
, (long) e
->X_add_number
);
3264 if (e
->X_add_symbol
)
3266 fprintf (stdout
, " add_symbol ");
3267 ps (e
->X_add_symbol
);
3268 fprintf (stdout
, "\n");
3272 fprintf (stdout
, " op_symbol ");
3273 ps (e
->X_op_symbol
);
3274 fprintf (stdout
, "\n");
3281 fprintf (stdout
, "%s type %s%s",
3283 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3284 segment_name (S_GET_SEGMENT (s
)));
3287 static struct type_name
3289 i386_operand_type mask
;
3292 const type_names
[] =
3294 { OPERAND_TYPE_REG8
, "r8" },
3295 { OPERAND_TYPE_REG16
, "r16" },
3296 { OPERAND_TYPE_REG32
, "r32" },
3297 { OPERAND_TYPE_REG64
, "r64" },
3298 { OPERAND_TYPE_ACC8
, "acc8" },
3299 { OPERAND_TYPE_ACC16
, "acc16" },
3300 { OPERAND_TYPE_ACC32
, "acc32" },
3301 { OPERAND_TYPE_ACC64
, "acc64" },
3302 { OPERAND_TYPE_IMM8
, "i8" },
3303 { OPERAND_TYPE_IMM8
, "i8s" },
3304 { OPERAND_TYPE_IMM16
, "i16" },
3305 { OPERAND_TYPE_IMM32
, "i32" },
3306 { OPERAND_TYPE_IMM32S
, "i32s" },
3307 { OPERAND_TYPE_IMM64
, "i64" },
3308 { OPERAND_TYPE_IMM1
, "i1" },
3309 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3310 { OPERAND_TYPE_DISP8
, "d8" },
3311 { OPERAND_TYPE_DISP16
, "d16" },
3312 { OPERAND_TYPE_DISP32
, "d32" },
3313 { OPERAND_TYPE_DISP32S
, "d32s" },
3314 { OPERAND_TYPE_DISP64
, "d64" },
3315 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3316 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3317 { OPERAND_TYPE_CONTROL
, "control reg" },
3318 { OPERAND_TYPE_TEST
, "test reg" },
3319 { OPERAND_TYPE_DEBUG
, "debug reg" },
3320 { OPERAND_TYPE_FLOATREG
, "FReg" },
3321 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3322 { OPERAND_TYPE_SREG
, "SReg" },
3323 { OPERAND_TYPE_REGMMX
, "rMMX" },
3324 { OPERAND_TYPE_REGXMM
, "rXMM" },
3325 { OPERAND_TYPE_REGYMM
, "rYMM" },
3326 { OPERAND_TYPE_REGZMM
, "rZMM" },
3327 { OPERAND_TYPE_REGTMM
, "rTMM" },
3328 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3332 pt (i386_operand_type t
)
3335 i386_operand_type a
;
3337 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3339 a
= operand_type_and (t
, type_names
[j
].mask
);
3340 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3341 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3346 #endif /* DEBUG386 */
3348 static bfd_reloc_code_real_type
3349 reloc (unsigned int size
,
3352 bfd_reloc_code_real_type other
)
3354 if (other
!= NO_RELOC
)
3356 reloc_howto_type
*rel
;
3361 case BFD_RELOC_X86_64_GOT32
:
3362 return BFD_RELOC_X86_64_GOT64
;
3364 case BFD_RELOC_X86_64_GOTPLT64
:
3365 return BFD_RELOC_X86_64_GOTPLT64
;
3367 case BFD_RELOC_X86_64_PLTOFF64
:
3368 return BFD_RELOC_X86_64_PLTOFF64
;
3370 case BFD_RELOC_X86_64_GOTPC32
:
3371 other
= BFD_RELOC_X86_64_GOTPC64
;
3373 case BFD_RELOC_X86_64_GOTPCREL
:
3374 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3376 case BFD_RELOC_X86_64_TPOFF32
:
3377 other
= BFD_RELOC_X86_64_TPOFF64
;
3379 case BFD_RELOC_X86_64_DTPOFF32
:
3380 other
= BFD_RELOC_X86_64_DTPOFF64
;
3386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3387 if (other
== BFD_RELOC_SIZE32
)
3390 other
= BFD_RELOC_SIZE64
;
3393 as_bad (_("there are no pc-relative size relocations"));
3399 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3400 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3403 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3405 as_bad (_("unknown relocation (%u)"), other
);
3406 else if (size
!= bfd_get_reloc_size (rel
))
3407 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3408 bfd_get_reloc_size (rel
),
3410 else if (pcrel
&& !rel
->pc_relative
)
3411 as_bad (_("non-pc-relative relocation for pc-relative field"));
3412 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3414 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3416 as_bad (_("relocated field and relocation type differ in signedness"));
3425 as_bad (_("there are no unsigned pc-relative relocations"));
3428 case 1: return BFD_RELOC_8_PCREL
;
3429 case 2: return BFD_RELOC_16_PCREL
;
3430 case 4: return BFD_RELOC_32_PCREL
;
3431 case 8: return BFD_RELOC_64_PCREL
;
3433 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3440 case 4: return BFD_RELOC_X86_64_32S
;
3445 case 1: return BFD_RELOC_8
;
3446 case 2: return BFD_RELOC_16
;
3447 case 4: return BFD_RELOC_32
;
3448 case 8: return BFD_RELOC_64
;
3450 as_bad (_("cannot do %s %u byte relocation"),
3451 sign
> 0 ? "signed" : "unsigned", size
);
3457 /* Here we decide which fixups can be adjusted to make them relative to
3458 the beginning of the section instead of the symbol. Basically we need
3459 to make sure that the dynamic relocations are done correctly, so in
3460 some cases we force the original symbol to be used. */
3463 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3469 /* Don't adjust pc-relative references to merge sections in 64-bit
3471 if (use_rela_relocations
3472 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3476 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3477 and changed later by validate_fix. */
3478 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3479 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3482 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3483 for size relocations. */
3484 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3485 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3486 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3487 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3488 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3489 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3490 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3492 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3493 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3494 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3495 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3496 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3497 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3498 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3499 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3500 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3506 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3507 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3508 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3509 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3510 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3511 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3512 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3513 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3514 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3521 intel_float_operand (const char *mnemonic
)
3523 /* Note that the value returned is meaningful only for opcodes with (memory)
3524 operands, hence the code here is free to improperly handle opcodes that
3525 have no operands (for better performance and smaller code). */
3527 if (mnemonic
[0] != 'f')
3528 return 0; /* non-math */
3530 switch (mnemonic
[1])
3532 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3533 the fs segment override prefix not currently handled because no
3534 call path can make opcodes without operands get here */
3536 return 2 /* integer op */;
3538 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3539 return 3; /* fldcw/fldenv */
3542 if (mnemonic
[2] != 'o' /* fnop */)
3543 return 3; /* non-waiting control op */
3546 if (mnemonic
[2] == 's')
3547 return 3; /* frstor/frstpm */
3550 if (mnemonic
[2] == 'a')
3551 return 3; /* fsave */
3552 if (mnemonic
[2] == 't')
3554 switch (mnemonic
[3])
3556 case 'c': /* fstcw */
3557 case 'd': /* fstdw */
3558 case 'e': /* fstenv */
3559 case 's': /* fsts[gw] */
3565 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3566 return 0; /* fxsave/fxrstor are not really math ops */
3573 /* Build the VEX prefix. */
3576 build_vex_prefix (const insn_template
*t
)
3578 unsigned int register_specifier
;
3579 unsigned int implied_prefix
;
3580 unsigned int vector_length
;
3583 /* Check register specifier. */
3584 if (i
.vex
.register_specifier
)
3586 register_specifier
=
3587 ~register_number (i
.vex
.register_specifier
) & 0xf;
3588 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3591 register_specifier
= 0xf;
3593 /* Use 2-byte VEX prefix by swapping destination and source operand
3594 if there are more than 1 register operand. */
3595 if (i
.reg_operands
> 1
3596 && i
.vec_encoding
!= vex_encoding_vex3
3597 && i
.dir_encoding
== dir_encoding_default
3598 && i
.operands
== i
.reg_operands
3599 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3600 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3601 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3604 unsigned int xchg
= i
.operands
- 1;
3605 union i386_op temp_op
;
3606 i386_operand_type temp_type
;
3608 temp_type
= i
.types
[xchg
];
3609 i
.types
[xchg
] = i
.types
[0];
3610 i
.types
[0] = temp_type
;
3611 temp_op
= i
.op
[xchg
];
3612 i
.op
[xchg
] = i
.op
[0];
3615 gas_assert (i
.rm
.mode
== 3);
3619 i
.rm
.regmem
= i
.rm
.reg
;
3622 if (i
.tm
.opcode_modifier
.d
)
3623 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3624 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3625 else /* Use the next insn. */
3629 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3630 are no memory operands and at least 3 register ones. */
3631 if (i
.reg_operands
>= 3
3632 && i
.vec_encoding
!= vex_encoding_vex3
3633 && i
.reg_operands
== i
.operands
- i
.imm_operands
3634 && i
.tm
.opcode_modifier
.vex
3635 && i
.tm
.opcode_modifier
.commutative
3636 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3638 && i
.vex
.register_specifier
3639 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3641 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3642 union i386_op temp_op
;
3643 i386_operand_type temp_type
;
3645 gas_assert (i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
);
3646 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3647 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3648 &i
.types
[i
.operands
- 3]));
3649 gas_assert (i
.rm
.mode
== 3);
3651 temp_type
= i
.types
[xchg
];
3652 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3653 i
.types
[xchg
+ 1] = temp_type
;
3654 temp_op
= i
.op
[xchg
];
3655 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3656 i
.op
[xchg
+ 1] = temp_op
;
3659 xchg
= i
.rm
.regmem
| 8;
3660 i
.rm
.regmem
= ~register_specifier
& 0xf;
3661 gas_assert (!(i
.rm
.regmem
& 8));
3662 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3663 register_specifier
= ~xchg
& 0xf;
3666 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3667 vector_length
= avxscalar
;
3668 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3674 /* Determine vector length from the last multi-length vector
3677 for (op
= t
->operands
; op
--;)
3678 if (t
->operand_types
[op
].bitfield
.xmmword
3679 && t
->operand_types
[op
].bitfield
.ymmword
3680 && i
.types
[op
].bitfield
.ymmword
)
3687 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3692 case DATA_PREFIX_OPCODE
:
3695 case REPE_PREFIX_OPCODE
:
3698 case REPNE_PREFIX_OPCODE
:
3705 /* Check the REX.W bit and VEXW. */
3706 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3707 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3708 else if (i
.tm
.opcode_modifier
.vexw
)
3709 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3711 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3713 /* Use 2-byte VEX prefix if possible. */
3715 && i
.vec_encoding
!= vex_encoding_vex3
3716 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3717 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3719 /* 2-byte VEX prefix. */
3723 i
.vex
.bytes
[0] = 0xc5;
3725 /* Check the REX.R bit. */
3726 r
= (i
.rex
& REX_R
) ? 0 : 1;
3727 i
.vex
.bytes
[1] = (r
<< 7
3728 | register_specifier
<< 3
3729 | vector_length
<< 2
3734 /* 3-byte VEX prefix. */
3739 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3743 i
.vex
.bytes
[0] = 0xc4;
3747 i
.vex
.bytes
[0] = 0xc4;
3751 i
.vex
.bytes
[0] = 0xc4;
3755 i
.vex
.bytes
[0] = 0x8f;
3759 i
.vex
.bytes
[0] = 0x8f;
3763 i
.vex
.bytes
[0] = 0x8f;
3769 /* The high 3 bits of the second VEX byte are 1's compliment
3770 of RXB bits from REX. */
3771 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3773 i
.vex
.bytes
[2] = (w
<< 7
3774 | register_specifier
<< 3
3775 | vector_length
<< 2
3780 static INLINE bfd_boolean
3781 is_evex_encoding (const insn_template
*t
)
3783 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3784 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3785 || t
->opcode_modifier
.sae
;
3788 static INLINE bfd_boolean
3789 is_any_vex_encoding (const insn_template
*t
)
3791 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3794 /* Build the EVEX prefix. */
3797 build_evex_prefix (void)
3799 unsigned int register_specifier
;
3800 unsigned int implied_prefix
;
3802 rex_byte vrex_used
= 0;
3804 /* Check register specifier. */
3805 if (i
.vex
.register_specifier
)
3807 gas_assert ((i
.vrex
& REX_X
) == 0);
3809 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3810 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3811 register_specifier
+= 8;
3812 /* The upper 16 registers are encoded in the fourth byte of the
3814 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3815 i
.vex
.bytes
[3] = 0x8;
3816 register_specifier
= ~register_specifier
& 0xf;
3820 register_specifier
= 0xf;
3822 /* Encode upper 16 vector index register in the fourth byte of
3824 if (!(i
.vrex
& REX_X
))
3825 i
.vex
.bytes
[3] = 0x8;
3830 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3835 case DATA_PREFIX_OPCODE
:
3838 case REPE_PREFIX_OPCODE
:
3841 case REPNE_PREFIX_OPCODE
:
3848 /* 4 byte EVEX prefix. */
3850 i
.vex
.bytes
[0] = 0x62;
3853 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3869 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3871 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3873 /* The fifth bit of the second EVEX byte is 1's compliment of the
3874 REX_R bit in VREX. */
3875 if (!(i
.vrex
& REX_R
))
3876 i
.vex
.bytes
[1] |= 0x10;
3880 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3882 /* When all operands are registers, the REX_X bit in REX is not
3883 used. We reuse it to encode the upper 16 registers, which is
3884 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3885 as 1's compliment. */
3886 if ((i
.vrex
& REX_B
))
3889 i
.vex
.bytes
[1] &= ~0x40;
3893 /* EVEX instructions shouldn't need the REX prefix. */
3894 i
.vrex
&= ~vrex_used
;
3895 gas_assert (i
.vrex
== 0);
3897 /* Check the REX.W bit and VEXW. */
3898 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3899 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3900 else if (i
.tm
.opcode_modifier
.vexw
)
3901 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3903 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3905 /* Encode the U bit. */
3906 implied_prefix
|= 0x4;
3908 /* The third byte of the EVEX prefix. */
3909 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3911 /* The fourth byte of the EVEX prefix. */
3912 /* The zeroing-masking bit. */
3913 if (i
.mask
&& i
.mask
->zeroing
)
3914 i
.vex
.bytes
[3] |= 0x80;
3916 /* Don't always set the broadcast bit if there is no RC. */
3919 /* Encode the vector length. */
3920 unsigned int vec_length
;
3922 if (!i
.tm
.opcode_modifier
.evex
3923 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3927 /* Determine vector length from the last multi-length vector
3929 for (op
= i
.operands
; op
--;)
3930 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3931 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3932 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3934 if (i
.types
[op
].bitfield
.zmmword
)
3936 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3939 else if (i
.types
[op
].bitfield
.ymmword
)
3941 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3944 else if (i
.types
[op
].bitfield
.xmmword
)
3946 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3949 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3951 switch (i
.broadcast
->bytes
)
3954 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3957 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3960 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3969 if (op
>= MAX_OPERANDS
)
3973 switch (i
.tm
.opcode_modifier
.evex
)
3975 case EVEXLIG
: /* LL' is ignored */
3976 vec_length
= evexlig
<< 5;
3979 vec_length
= 0 << 5;
3982 vec_length
= 1 << 5;
3985 vec_length
= 2 << 5;
3991 i
.vex
.bytes
[3] |= vec_length
;
3992 /* Encode the broadcast bit. */
3994 i
.vex
.bytes
[3] |= 0x10;
3998 if (i
.rounding
->type
!= saeonly
)
3999 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
4001 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4004 if (i
.mask
&& i
.mask
->mask
)
4005 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4009 process_immext (void)
4013 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4014 which is coded in the same place as an 8-bit immediate field
4015 would be. Here we fake an 8-bit immediate operand from the
4016 opcode suffix stored in tm.extension_opcode.
4018 AVX instructions also use this encoding, for some of
4019 3 argument instructions. */
4021 gas_assert (i
.imm_operands
<= 1
4023 || (is_any_vex_encoding (&i
.tm
)
4024 && i
.operands
<= 4)));
4026 exp
= &im_expressions
[i
.imm_operands
++];
4027 i
.op
[i
.operands
].imms
= exp
;
4028 i
.types
[i
.operands
] = imm8
;
4030 exp
->X_op
= O_constant
;
4031 exp
->X_add_number
= i
.tm
.extension_opcode
;
4032 i
.tm
.extension_opcode
= None
;
4039 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4044 as_bad (_("invalid instruction `%s' after `%s'"),
4045 i
.tm
.name
, i
.hle_prefix
);
4048 if (i
.prefix
[LOCK_PREFIX
])
4050 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4054 case HLEPrefixRelease
:
4055 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4057 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4061 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4063 as_bad (_("memory destination needed for instruction `%s'"
4064 " after `xrelease'"), i
.tm
.name
);
4071 /* Try the shortest encoding by shortening operand size. */
4074 optimize_encoding (void)
4078 if (optimize_for_space
4079 && !is_any_vex_encoding (&i
.tm
)
4080 && i
.reg_operands
== 1
4081 && i
.imm_operands
== 1
4082 && !i
.types
[1].bitfield
.byte
4083 && i
.op
[0].imms
->X_op
== O_constant
4084 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4085 && (i
.tm
.base_opcode
== 0xa8
4086 || (i
.tm
.base_opcode
== 0xf6
4087 && i
.tm
.extension_opcode
== 0x0)))
4090 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4092 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4093 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4095 i
.types
[1].bitfield
.byte
= 1;
4096 /* Ignore the suffix. */
4098 /* Convert to byte registers. */
4099 if (i
.types
[1].bitfield
.word
)
4101 else if (i
.types
[1].bitfield
.dword
)
4105 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4110 else if (flag_code
== CODE_64BIT
4111 && !is_any_vex_encoding (&i
.tm
)
4112 && ((i
.types
[1].bitfield
.qword
4113 && i
.reg_operands
== 1
4114 && i
.imm_operands
== 1
4115 && i
.op
[0].imms
->X_op
== O_constant
4116 && ((i
.tm
.base_opcode
== 0xb8
4117 && i
.tm
.extension_opcode
== None
4118 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4119 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4120 && ((i
.tm
.base_opcode
== 0x24
4121 || i
.tm
.base_opcode
== 0xa8)
4122 || (i
.tm
.base_opcode
== 0x80
4123 && i
.tm
.extension_opcode
== 0x4)
4124 || ((i
.tm
.base_opcode
== 0xf6
4125 || (i
.tm
.base_opcode
| 1) == 0xc7)
4126 && i
.tm
.extension_opcode
== 0x0)))
4127 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4128 && i
.tm
.base_opcode
== 0x83
4129 && i
.tm
.extension_opcode
== 0x4)))
4130 || (i
.types
[0].bitfield
.qword
4131 && ((i
.reg_operands
== 2
4132 && i
.op
[0].regs
== i
.op
[1].regs
4133 && (i
.tm
.base_opcode
== 0x30
4134 || i
.tm
.base_opcode
== 0x28))
4135 || (i
.reg_operands
== 1
4137 && i
.tm
.base_opcode
== 0x30)))))
4140 andq $imm31, %r64 -> andl $imm31, %r32
4141 andq $imm7, %r64 -> andl $imm7, %r32
4142 testq $imm31, %r64 -> testl $imm31, %r32
4143 xorq %r64, %r64 -> xorl %r32, %r32
4144 subq %r64, %r64 -> subl %r32, %r32
4145 movq $imm31, %r64 -> movl $imm31, %r32
4146 movq $imm32, %r64 -> movl $imm32, %r32
4148 i
.tm
.opcode_modifier
.norex64
= 1;
4149 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4152 movq $imm31, %r64 -> movl $imm31, %r32
4153 movq $imm32, %r64 -> movl $imm32, %r32
4155 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4156 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4157 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4158 i
.types
[0].bitfield
.imm32
= 1;
4159 i
.types
[0].bitfield
.imm32s
= 0;
4160 i
.types
[0].bitfield
.imm64
= 0;
4161 i
.types
[1].bitfield
.dword
= 1;
4162 i
.types
[1].bitfield
.qword
= 0;
4163 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4166 movq $imm31, %r64 -> movl $imm31, %r32
4168 i
.tm
.base_opcode
= 0xb8;
4169 i
.tm
.extension_opcode
= None
;
4170 i
.tm
.opcode_modifier
.w
= 0;
4171 i
.tm
.opcode_modifier
.modrm
= 0;
4175 else if (optimize
> 1
4176 && !optimize_for_space
4177 && !is_any_vex_encoding (&i
.tm
)
4178 && i
.reg_operands
== 2
4179 && i
.op
[0].regs
== i
.op
[1].regs
4180 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4181 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4182 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4185 andb %rN, %rN -> testb %rN, %rN
4186 andw %rN, %rN -> testw %rN, %rN
4187 andq %rN, %rN -> testq %rN, %rN
4188 orb %rN, %rN -> testb %rN, %rN
4189 orw %rN, %rN -> testw %rN, %rN
4190 orq %rN, %rN -> testq %rN, %rN
4192 and outside of 64-bit mode
4194 andl %rN, %rN -> testl %rN, %rN
4195 orl %rN, %rN -> testl %rN, %rN
4197 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4199 else if (i
.reg_operands
== 3
4200 && i
.op
[0].regs
== i
.op
[1].regs
4201 && !i
.types
[2].bitfield
.xmmword
4202 && (i
.tm
.opcode_modifier
.vex
4203 || ((!i
.mask
|| i
.mask
->zeroing
)
4205 && is_evex_encoding (&i
.tm
)
4206 && (i
.vec_encoding
!= vex_encoding_evex
4207 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4208 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4209 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4210 && i
.types
[2].bitfield
.ymmword
))))
4211 && ((i
.tm
.base_opcode
== 0x55
4212 || i
.tm
.base_opcode
== 0x6655
4213 || i
.tm
.base_opcode
== 0x66df
4214 || i
.tm
.base_opcode
== 0x57
4215 || i
.tm
.base_opcode
== 0x6657
4216 || i
.tm
.base_opcode
== 0x66ef
4217 || i
.tm
.base_opcode
== 0x66f8
4218 || i
.tm
.base_opcode
== 0x66f9
4219 || i
.tm
.base_opcode
== 0x66fa
4220 || i
.tm
.base_opcode
== 0x66fb
4221 || i
.tm
.base_opcode
== 0x42
4222 || i
.tm
.base_opcode
== 0x6642
4223 || i
.tm
.base_opcode
== 0x47
4224 || i
.tm
.base_opcode
== 0x6647)
4225 && i
.tm
.extension_opcode
== None
))
4228 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VEX VOP %ymmM, %ymmM, %ymmN
4237 -> VEX VOP %xmmM, %xmmM, %xmmN
4238 VOP, one of vpandn and vpxor:
4239 VEX VOP %ymmM, %ymmM, %ymmN
4240 -> VEX VOP %xmmM, %xmmM, %xmmN
4241 VOP, one of vpandnd and vpandnq:
4242 EVEX VOP %zmmM, %zmmM, %zmmN
4243 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4244 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4245 EVEX VOP %ymmM, %ymmM, %ymmN
4246 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4247 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4248 VOP, one of vpxord and vpxorq:
4249 EVEX VOP %zmmM, %zmmM, %zmmN
4250 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4251 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4252 EVEX VOP %ymmM, %ymmM, %ymmN
4253 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4254 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4255 VOP, one of kxord and kxorq:
4256 VEX VOP %kM, %kM, %kN
4257 -> VEX kxorw %kM, %kM, %kN
4258 VOP, one of kandnd and kandnq:
4259 VEX VOP %kM, %kM, %kN
4260 -> VEX kandnw %kM, %kM, %kN
4262 if (is_evex_encoding (&i
.tm
))
4264 if (i
.vec_encoding
!= vex_encoding_evex
)
4266 i
.tm
.opcode_modifier
.vex
= VEX128
;
4267 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4268 i
.tm
.opcode_modifier
.evex
= 0;
4270 else if (optimize
> 1)
4271 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4275 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4277 i
.tm
.base_opcode
&= 0xff;
4278 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4281 i
.tm
.opcode_modifier
.vex
= VEX128
;
4283 if (i
.tm
.opcode_modifier
.vex
)
4284 for (j
= 0; j
< 3; j
++)
4286 i
.types
[j
].bitfield
.xmmword
= 1;
4287 i
.types
[j
].bitfield
.ymmword
= 0;
4290 else if (i
.vec_encoding
!= vex_encoding_evex
4291 && !i
.types
[0].bitfield
.zmmword
4292 && !i
.types
[1].bitfield
.zmmword
4295 && is_evex_encoding (&i
.tm
)
4296 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4297 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4298 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4299 || (i
.tm
.base_opcode
& ~4) == 0x66db
4300 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4301 && i
.tm
.extension_opcode
== None
)
4304 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4305 vmovdqu32 and vmovdqu64:
4306 EVEX VOP %xmmM, %xmmN
4307 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4308 EVEX VOP %ymmM, %ymmN
4309 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4311 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4313 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4315 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4317 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4318 VOP, one of vpand, vpandn, vpor, vpxor:
4319 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4320 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4321 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4322 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4323 EVEX VOP{d,q} mem, %xmmM, %xmmN
4324 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4325 EVEX VOP{d,q} mem, %ymmM, %ymmN
4326 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4328 for (j
= 0; j
< i
.operands
; j
++)
4329 if (operand_type_check (i
.types
[j
], disp
)
4330 && i
.op
[j
].disps
->X_op
== O_constant
)
4332 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4333 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4334 bytes, we choose EVEX Disp8 over VEX Disp32. */
4335 int evex_disp8
, vex_disp8
;
4336 unsigned int memshift
= i
.memshift
;
4337 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4339 evex_disp8
= fits_in_disp8 (n
);
4341 vex_disp8
= fits_in_disp8 (n
);
4342 if (evex_disp8
!= vex_disp8
)
4344 i
.memshift
= memshift
;
4348 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4351 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4352 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4353 i
.tm
.opcode_modifier
.vex
4354 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4355 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4356 /* VPAND, VPOR, and VPXOR are commutative. */
4357 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4358 i
.tm
.opcode_modifier
.commutative
= 1;
4359 i
.tm
.opcode_modifier
.evex
= 0;
4360 i
.tm
.opcode_modifier
.masking
= 0;
4361 i
.tm
.opcode_modifier
.broadcast
= 0;
4362 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4365 i
.types
[j
].bitfield
.disp8
4366 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4370 /* Return non-zero for load instruction. */
4376 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4377 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4381 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4382 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4383 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4384 if (i
.tm
.opcode_modifier
.anysize
)
4387 /* pop, popf, popa. */
4388 if (strcmp (i
.tm
.name
, "pop") == 0
4389 || i
.tm
.base_opcode
== 0x9d
4390 || i
.tm
.base_opcode
== 0x61)
4393 /* movs, cmps, lods, scas. */
4394 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4398 if (base_opcode
== 0x6f
4399 || i
.tm
.base_opcode
== 0xd7)
4401 /* NB: For AMD-specific insns with implicit memory operands,
4402 they're intentionally not covered. */
4405 /* No memory operand. */
4406 if (!i
.mem_operands
)
4412 if (i
.tm
.base_opcode
== 0xae
4413 && i
.tm
.opcode_modifier
.vex
4414 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
4415 && i
.tm
.extension_opcode
== 2)
4420 /* test, not, neg, mul, imul, div, idiv. */
4421 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4422 && i
.tm
.extension_opcode
!= 1)
4426 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4429 /* add, or, adc, sbb, and, sub, xor, cmp. */
4430 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4433 /* bt, bts, btr, btc. */
4434 if (i
.tm
.base_opcode
== 0xfba
4435 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4438 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4439 if ((base_opcode
== 0xc1
4440 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4441 && i
.tm
.extension_opcode
!= 6)
4444 /* cmpxchg8b, cmpxchg16b, xrstors. */
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4447 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4450 /* fxrstor, ldmxcsr, xrstor. */
4451 if (i
.tm
.base_opcode
== 0xfae
4452 && (i
.tm
.extension_opcode
== 1
4453 || i
.tm
.extension_opcode
== 2
4454 || i
.tm
.extension_opcode
== 5))
4457 /* lgdt, lidt, lmsw. */
4458 if (i
.tm
.base_opcode
== 0xf01
4459 && (i
.tm
.extension_opcode
== 2
4460 || i
.tm
.extension_opcode
== 3
4461 || i
.tm
.extension_opcode
== 6))
4465 if (i
.tm
.base_opcode
== 0xfc7
4466 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4467 && i
.tm
.extension_opcode
== 6)
4470 /* Check for x87 instructions. */
4471 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4473 /* Skip fst, fstp, fstenv, fstcw. */
4474 if (i
.tm
.base_opcode
== 0xd9
4475 && (i
.tm
.extension_opcode
== 2
4476 || i
.tm
.extension_opcode
== 3
4477 || i
.tm
.extension_opcode
== 6
4478 || i
.tm
.extension_opcode
== 7))
4481 /* Skip fisttp, fist, fistp, fstp. */
4482 if (i
.tm
.base_opcode
== 0xdb
4483 && (i
.tm
.extension_opcode
== 1
4484 || i
.tm
.extension_opcode
== 2
4485 || i
.tm
.extension_opcode
== 3
4486 || i
.tm
.extension_opcode
== 7))
4489 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4490 if (i
.tm
.base_opcode
== 0xdd
4491 && (i
.tm
.extension_opcode
== 1
4492 || i
.tm
.extension_opcode
== 2
4493 || i
.tm
.extension_opcode
== 3
4494 || i
.tm
.extension_opcode
== 6
4495 || i
.tm
.extension_opcode
== 7))
4498 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4499 if (i
.tm
.base_opcode
== 0xdf
4500 && (i
.tm
.extension_opcode
== 1
4501 || i
.tm
.extension_opcode
== 2
4502 || i
.tm
.extension_opcode
== 3
4503 || i
.tm
.extension_opcode
== 6
4504 || i
.tm
.extension_opcode
== 7))
4511 dest
= i
.operands
- 1;
4513 /* Check fake imm8 operand and 3 source operands. */
4514 if ((i
.tm
.opcode_modifier
.immext
4515 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4516 && i
.types
[dest
].bitfield
.imm8
)
4519 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4521 && (base_opcode
== 0x1
4522 || base_opcode
== 0x9
4523 || base_opcode
== 0x11
4524 || base_opcode
== 0x19
4525 || base_opcode
== 0x21
4526 || base_opcode
== 0x29
4527 || base_opcode
== 0x31
4528 || base_opcode
== 0x39
4529 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4530 || base_opcode
== 0xfc1))
4533 /* Check for load instruction. */
4534 return (i
.types
[dest
].bitfield
.class != ClassNone
4535 || i
.types
[dest
].bitfield
.instance
== Accum
);
4538 /* Output lfence, 0xfaee8, after instruction. */
4541 insert_lfence_after (void)
4543 if (lfence_after_load
&& load_insn_p ())
4545 /* There are also two REP string instructions that require
4546 special treatment. Specifically, the compare string (CMPS)
4547 and scan string (SCAS) instructions set EFLAGS in a manner
4548 that depends on the data being compared/scanned. When used
4549 with a REP prefix, the number of iterations may therefore
4550 vary depending on this data. If the data is a program secret
4551 chosen by the adversary using an LVI method,
4552 then this data-dependent behavior may leak some aspect
4554 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4555 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4556 && i
.prefix
[REP_PREFIX
])
4558 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4561 char *p
= frag_more (3);
4568 /* Output lfence, 0xfaee8, before instruction. */
4571 insert_lfence_before (void)
4575 if (is_any_vex_encoding (&i
.tm
))
4578 if (i
.tm
.base_opcode
== 0xff
4579 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4581 /* Insert lfence before indirect branch if needed. */
4583 if (lfence_before_indirect_branch
== lfence_branch_none
)
4586 if (i
.operands
!= 1)
4589 if (i
.reg_operands
== 1)
4591 /* Indirect branch via register. Don't insert lfence with
4592 -mlfence-after-load=yes. */
4593 if (lfence_after_load
4594 || lfence_before_indirect_branch
== lfence_branch_memory
)
4597 else if (i
.mem_operands
== 1
4598 && lfence_before_indirect_branch
!= lfence_branch_register
)
4600 as_warn (_("indirect `%s` with memory operand should be avoided"),
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4623 /* Output or/not/shl and lfence before near ret. */
4624 if (lfence_before_ret
!= lfence_before_ret_none
4625 && (i
.tm
.base_opcode
== 0xc2
4626 || i
.tm
.base_opcode
== 0xc3))
4628 if (last_insn
.kind
!= last_insn_other
4629 && last_insn
.seg
== now_seg
)
4631 as_warn_where (last_insn
.file
, last_insn
.line
,
4632 _("`%s` skips -mlfence-before-ret on `%s`"),
4633 last_insn
.name
, i
.tm
.name
);
4637 /* Near ret ingore operand size override under CPU64. */
4638 char prefix
= flag_code
== CODE_64BIT
4640 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4642 if (lfence_before_ret
== lfence_before_ret_not
)
4644 /* not: 0xf71424, may add prefix
4645 for operand size override or 64-bit code. */
4646 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4660 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4663 if (lfence_before_ret
== lfence_before_ret_or
)
4665 /* or: 0x830c2400, may add prefix
4666 for operand size override or 64-bit code. */
4672 /* shl: 0xc1242400, may add prefix
4673 for operand size override or 64-bit code. */
4688 /* This is the guts of the machine-dependent assembler. LINE points to a
4689 machine dependent instruction. This function is supposed to emit
4690 the frags/bytes it assembles to. */
4693 md_assemble (char *line
)
4696 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4697 const insn_template
*t
;
4699 /* Initialize globals. */
4700 memset (&i
, '\0', sizeof (i
));
4701 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4702 i
.reloc
[j
] = NO_RELOC
;
4703 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4704 memset (im_expressions
, '\0', sizeof (im_expressions
));
4705 save_stack_p
= save_stack
;
4707 /* First parse an instruction mnemonic & call i386_operand for the operands.
4708 We assume that the scrubber has arranged it so that line[0] is the valid
4709 start of a (possibly prefixed) mnemonic. */
4711 line
= parse_insn (line
, mnemonic
);
4714 mnem_suffix
= i
.suffix
;
4716 line
= parse_operands (line
, mnemonic
);
4718 xfree (i
.memop1_string
);
4719 i
.memop1_string
= NULL
;
4723 /* Now we've parsed the mnemonic into a set of templates, and have the
4724 operands at hand. */
4726 /* All Intel opcodes have reversed operands except for "bound", "enter",
4727 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4728 intersegment "jmp" and "call" instructions with 2 immediate operands so
4729 that the immediate segment precedes the offset, as it does when in AT&T
4733 && (strcmp (mnemonic
, "bound") != 0)
4734 && (strcmp (mnemonic
, "invlpga") != 0)
4735 && (strncmp (mnemonic
, "monitor", 7) != 0)
4736 && (strncmp (mnemonic
, "mwait", 5) != 0)
4737 && (strcmp (mnemonic
, "tpause") != 0)
4738 && (strcmp (mnemonic
, "umwait") != 0)
4739 && !(operand_type_check (i
.types
[0], imm
)
4740 && operand_type_check (i
.types
[1], imm
)))
4743 /* The order of the immediates should be reversed
4744 for 2 immediates extrq and insertq instructions */
4745 if (i
.imm_operands
== 2
4746 && (strcmp (mnemonic
, "extrq") == 0
4747 || strcmp (mnemonic
, "insertq") == 0))
4748 swap_2_operands (0, 1);
4753 /* Don't optimize displacement for movabs since it only takes 64bit
4756 && i
.disp_encoding
!= disp_encoding_32bit
4757 && (flag_code
!= CODE_64BIT
4758 || strcmp (mnemonic
, "movabs") != 0))
4761 /* Next, we find a template that matches the given insn,
4762 making sure the overlap of the given operands types is consistent
4763 with the template operand types. */
4765 if (!(t
= match_template (mnem_suffix
)))
4768 if (sse_check
!= check_none
4769 && !i
.tm
.opcode_modifier
.noavx
4770 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4771 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4772 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4773 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4774 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4775 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4776 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4777 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4778 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4779 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4780 || i
.tm
.cpu_flags
.bitfield
.cpusha
4781 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4783 (sse_check
== check_warning
4785 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4788 if (i
.tm
.opcode_modifier
.fwait
)
4789 if (!add_prefix (FWAIT_OPCODE
))
4792 /* Check if REP prefix is OK. */
4793 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4795 as_bad (_("invalid instruction `%s' after `%s'"),
4796 i
.tm
.name
, i
.rep_prefix
);
4800 /* Check for lock without a lockable instruction. Destination operand
4801 must be memory unless it is xchg (0x86). */
4802 if (i
.prefix
[LOCK_PREFIX
]
4803 && (!i
.tm
.opcode_modifier
.islockable
4804 || i
.mem_operands
== 0
4805 || (i
.tm
.base_opcode
!= 0x86
4806 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4808 as_bad (_("expecting lockable instruction after `lock'"));
4812 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4813 if (i
.prefix
[DATA_PREFIX
]
4814 && (is_any_vex_encoding (&i
.tm
)
4815 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4816 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4818 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4822 /* Check if HLE prefix is OK. */
4823 if (i
.hle_prefix
&& !check_hle ())
4826 /* Check BND prefix. */
4827 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4828 as_bad (_("expecting valid branch instruction after `bnd'"));
4830 /* Check NOTRACK prefix. */
4831 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4832 as_bad (_("expecting indirect branch instruction after `notrack'"));
4834 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4836 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4837 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4838 else if (flag_code
!= CODE_16BIT
4839 ? i
.prefix
[ADDR_PREFIX
]
4840 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4841 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4844 /* Insert BND prefix. */
4845 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4847 if (!i
.prefix
[BND_PREFIX
])
4848 add_prefix (BND_PREFIX_OPCODE
);
4849 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4851 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4852 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4856 /* Check string instruction segment overrides. */
4857 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4859 gas_assert (i
.mem_operands
);
4860 if (!check_string ())
4862 i
.disp_operands
= 0;
4865 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4866 optimize_encoding ();
4868 if (!process_suffix ())
4871 /* Update operand types and check extended states. */
4872 for (j
= 0; j
< i
.operands
; j
++)
4874 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4875 switch (i
.types
[j
].bitfield
.class)
4880 i
.xstate
|= xstate_mmx
;
4883 i
.xstate
|= xstate_mask
;
4886 if (i
.types
[j
].bitfield
.tmmword
)
4887 i
.xstate
|= xstate_tmm
;
4888 else if (i
.types
[j
].bitfield
.zmmword
)
4889 i
.xstate
|= xstate_zmm
;
4890 else if (i
.types
[j
].bitfield
.ymmword
)
4891 i
.xstate
|= xstate_ymm
;
4892 else if (i
.types
[j
].bitfield
.xmmword
)
4893 i
.xstate
|= xstate_xmm
;
4898 /* Make still unresolved immediate matches conform to size of immediate
4899 given in i.suffix. */
4900 if (!finalize_imm ())
4903 if (i
.types
[0].bitfield
.imm1
)
4904 i
.imm_operands
= 0; /* kludge for shift insns. */
4906 /* We only need to check those implicit registers for instructions
4907 with 3 operands or less. */
4908 if (i
.operands
<= 3)
4909 for (j
= 0; j
< i
.operands
; j
++)
4910 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4911 && !i
.types
[j
].bitfield
.xmmword
)
4914 /* For insns with operands there are more diddles to do to the opcode. */
4917 if (!process_operands ())
4920 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4922 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4923 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4926 if (is_any_vex_encoding (&i
.tm
))
4928 if (!cpu_arch_flags
.bitfield
.cpui286
)
4930 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4935 /* Check for explicit REX prefix. */
4936 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4938 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4942 if (i
.tm
.opcode_modifier
.vex
)
4943 build_vex_prefix (t
);
4945 build_evex_prefix ();
4947 /* The individual REX.RXBW bits got consumed. */
4948 i
.rex
&= REX_OPCODE
;
4951 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4952 instructions may define INT_OPCODE as well, so avoid this corner
4953 case for those instructions that use MODRM. */
4954 if (i
.tm
.base_opcode
== INT_OPCODE
4955 && !i
.tm
.opcode_modifier
.modrm
4956 && i
.op
[0].imms
->X_add_number
== 3)
4958 i
.tm
.base_opcode
= INT3_OPCODE
;
4962 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4963 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4964 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4965 && i
.op
[0].disps
->X_op
== O_constant
)
4967 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4968 the absolute address given by the constant. Since ix86 jumps and
4969 calls are pc relative, we need to generate a reloc. */
4970 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4971 i
.op
[0].disps
->X_op
= O_symbol
;
4974 /* For 8 bit registers we need an empty rex prefix. Also if the
4975 instruction already has a prefix, we need to convert old
4976 registers to new ones. */
4978 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4979 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4980 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4981 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4982 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4983 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4988 i
.rex
|= REX_OPCODE
;
4989 for (x
= 0; x
< 2; x
++)
4991 /* Look for 8 bit operand that uses old registers. */
4992 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4993 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4995 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4996 /* In case it is "hi" register, give up. */
4997 if (i
.op
[x
].regs
->reg_num
> 3)
4998 as_bad (_("can't encode register '%s%s' in an "
4999 "instruction requiring REX prefix."),
5000 register_prefix
, i
.op
[x
].regs
->reg_name
);
5002 /* Otherwise it is equivalent to the extended register.
5003 Since the encoding doesn't change this is merely
5004 cosmetic cleanup for debug output. */
5006 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5011 if (i
.rex
== 0 && i
.rex_encoding
)
5013 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5014 that uses legacy register. If it is "hi" register, don't add
5015 the REX_OPCODE byte. */
5017 for (x
= 0; x
< 2; x
++)
5018 if (i
.types
[x
].bitfield
.class == Reg
5019 && i
.types
[x
].bitfield
.byte
5020 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5021 && i
.op
[x
].regs
->reg_num
> 3)
5023 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5024 i
.rex_encoding
= FALSE
;
5033 add_prefix (REX_OPCODE
| i
.rex
);
5035 insert_lfence_before ();
5037 /* We are ready to output the insn. */
5040 insert_lfence_after ();
5042 last_insn
.seg
= now_seg
;
5044 if (i
.tm
.opcode_modifier
.isprefix
)
5046 last_insn
.kind
= last_insn_prefix
;
5047 last_insn
.name
= i
.tm
.name
;
5048 last_insn
.file
= as_where (&last_insn
.line
);
5051 last_insn
.kind
= last_insn_other
;
5055 parse_insn (char *line
, char *mnemonic
)
5058 char *token_start
= l
;
5061 const insn_template
*t
;
5067 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5072 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5074 as_bad (_("no such instruction: `%s'"), token_start
);
5079 if (!is_space_char (*l
)
5080 && *l
!= END_OF_INSN
5082 || (*l
!= PREFIX_SEPARATOR
5085 as_bad (_("invalid character %s in mnemonic"),
5086 output_invalid (*l
));
5089 if (token_start
== l
)
5091 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5092 as_bad (_("expecting prefix; got nothing"));
5094 as_bad (_("expecting mnemonic; got nothing"));
5098 /* Look up instruction (or prefix) via hash table. */
5099 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5101 if (*l
!= END_OF_INSN
5102 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5103 && current_templates
5104 && current_templates
->start
->opcode_modifier
.isprefix
)
5106 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5108 as_bad ((flag_code
!= CODE_64BIT
5109 ? _("`%s' is only supported in 64-bit mode")
5110 : _("`%s' is not supported in 64-bit mode")),
5111 current_templates
->start
->name
);
5114 /* If we are in 16-bit mode, do not allow addr16 or data16.
5115 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5116 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5117 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5118 && flag_code
!= CODE_64BIT
5119 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5120 ^ (flag_code
== CODE_16BIT
)))
5122 as_bad (_("redundant %s prefix"),
5123 current_templates
->start
->name
);
5126 if (current_templates
->start
->opcode_length
== 0)
5128 /* Handle pseudo prefixes. */
5129 switch (current_templates
->start
->base_opcode
)
5133 i
.disp_encoding
= disp_encoding_8bit
;
5137 i
.disp_encoding
= disp_encoding_16bit
;
5141 i
.disp_encoding
= disp_encoding_32bit
;
5145 i
.dir_encoding
= dir_encoding_load
;
5149 i
.dir_encoding
= dir_encoding_store
;
5153 i
.vec_encoding
= vex_encoding_vex
;
5157 i
.vec_encoding
= vex_encoding_vex3
;
5161 i
.vec_encoding
= vex_encoding_evex
;
5165 i
.rex_encoding
= TRUE
;
5167 case Prefix_NoOptimize
:
5169 i
.no_optimize
= TRUE
;
5177 /* Add prefix, checking for repeated prefixes. */
5178 switch (add_prefix (current_templates
->start
->base_opcode
))
5183 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5184 i
.notrack_prefix
= current_templates
->start
->name
;
5187 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5188 i
.hle_prefix
= current_templates
->start
->name
;
5189 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5190 i
.bnd_prefix
= current_templates
->start
->name
;
5192 i
.rep_prefix
= current_templates
->start
->name
;
5198 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5205 if (!current_templates
)
5207 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5208 Check if we should swap operand or force 32bit displacement in
5210 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5211 i
.dir_encoding
= dir_encoding_swap
;
5212 else if (mnem_p
- 3 == dot_p
5215 i
.disp_encoding
= disp_encoding_8bit
;
5216 else if (mnem_p
- 4 == dot_p
5220 i
.disp_encoding
= disp_encoding_32bit
;
5225 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5228 if (!current_templates
)
5231 if (mnem_p
> mnemonic
)
5233 /* See if we can get a match by trimming off a suffix. */
5236 case WORD_MNEM_SUFFIX
:
5237 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5238 i
.suffix
= SHORT_MNEM_SUFFIX
;
5241 case BYTE_MNEM_SUFFIX
:
5242 case QWORD_MNEM_SUFFIX
:
5243 i
.suffix
= mnem_p
[-1];
5246 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5248 case SHORT_MNEM_SUFFIX
:
5249 case LONG_MNEM_SUFFIX
:
5252 i
.suffix
= mnem_p
[-1];
5255 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5263 if (intel_float_operand (mnemonic
) == 1)
5264 i
.suffix
= SHORT_MNEM_SUFFIX
;
5266 i
.suffix
= LONG_MNEM_SUFFIX
;
5269 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5275 if (!current_templates
)
5277 as_bad (_("no such instruction: `%s'"), token_start
);
5282 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5283 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5285 /* Check for a branch hint. We allow ",pt" and ",pn" for
5286 predict taken and predict not taken respectively.
5287 I'm not sure that branch hints actually do anything on loop
5288 and jcxz insns (JumpByte) for current Pentium4 chips. They
5289 may work in the future and it doesn't hurt to accept them
5291 if (l
[0] == ',' && l
[1] == 'p')
5295 if (!add_prefix (DS_PREFIX_OPCODE
))
5299 else if (l
[2] == 'n')
5301 if (!add_prefix (CS_PREFIX_OPCODE
))
5307 /* Any other comma loses. */
5310 as_bad (_("invalid character %s in mnemonic"),
5311 output_invalid (*l
));
5315 /* Check if instruction is supported on specified architecture. */
5317 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5319 supported
|= cpu_flags_match (t
);
5320 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5322 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5323 as_warn (_("use .code16 to ensure correct addressing mode"));
5329 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5330 as_bad (flag_code
== CODE_64BIT
5331 ? _("`%s' is not supported in 64-bit mode")
5332 : _("`%s' is only supported in 64-bit mode"),
5333 current_templates
->start
->name
);
5335 as_bad (_("`%s' is not supported on `%s%s'"),
5336 current_templates
->start
->name
,
5337 cpu_arch_name
? cpu_arch_name
: default_arch
,
5338 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5344 parse_operands (char *l
, const char *mnemonic
)
5348 /* 1 if operand is pending after ','. */
5349 unsigned int expecting_operand
= 0;
5351 /* Non-zero if operand parens not balanced. */
5352 unsigned int paren_not_balanced
;
5354 while (*l
!= END_OF_INSN
)
5356 /* Skip optional white space before operand. */
5357 if (is_space_char (*l
))
5359 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5361 as_bad (_("invalid character %s before operand %d"),
5362 output_invalid (*l
),
5366 token_start
= l
; /* After white space. */
5367 paren_not_balanced
= 0;
5368 while (paren_not_balanced
|| *l
!= ',')
5370 if (*l
== END_OF_INSN
)
5372 if (paren_not_balanced
)
5375 as_bad (_("unbalanced parenthesis in operand %d."),
5378 as_bad (_("unbalanced brackets in operand %d."),
5383 break; /* we are done */
5385 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5387 as_bad (_("invalid character %s in operand %d"),
5388 output_invalid (*l
),
5395 ++paren_not_balanced
;
5397 --paren_not_balanced
;
5402 ++paren_not_balanced
;
5404 --paren_not_balanced
;
5408 if (l
!= token_start
)
5409 { /* Yes, we've read in another operand. */
5410 unsigned int operand_ok
;
5411 this_operand
= i
.operands
++;
5412 if (i
.operands
> MAX_OPERANDS
)
5414 as_bad (_("spurious operands; (%d operands/instruction max)"),
5418 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5419 /* Now parse operand adding info to 'i' as we go along. */
5420 END_STRING_AND_SAVE (l
);
5422 if (i
.mem_operands
> 1)
5424 as_bad (_("too many memory references for `%s'"),
5431 i386_intel_operand (token_start
,
5432 intel_float_operand (mnemonic
));
5434 operand_ok
= i386_att_operand (token_start
);
5436 RESTORE_END_STRING (l
);
5442 if (expecting_operand
)
5444 expecting_operand_after_comma
:
5445 as_bad (_("expecting operand after ','; got nothing"));
5450 as_bad (_("expecting operand before ','; got nothing"));
5455 /* Now *l must be either ',' or END_OF_INSN. */
5458 if (*++l
== END_OF_INSN
)
5460 /* Just skip it, if it's \n complain. */
5461 goto expecting_operand_after_comma
;
5463 expecting_operand
= 1;
5470 swap_2_operands (int xchg1
, int xchg2
)
5472 union i386_op temp_op
;
5473 i386_operand_type temp_type
;
5474 unsigned int temp_flags
;
5475 enum bfd_reloc_code_real temp_reloc
;
5477 temp_type
= i
.types
[xchg2
];
5478 i
.types
[xchg2
] = i
.types
[xchg1
];
5479 i
.types
[xchg1
] = temp_type
;
5481 temp_flags
= i
.flags
[xchg2
];
5482 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5483 i
.flags
[xchg1
] = temp_flags
;
5485 temp_op
= i
.op
[xchg2
];
5486 i
.op
[xchg2
] = i
.op
[xchg1
];
5487 i
.op
[xchg1
] = temp_op
;
5489 temp_reloc
= i
.reloc
[xchg2
];
5490 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5491 i
.reloc
[xchg1
] = temp_reloc
;
5495 if (i
.mask
->operand
== xchg1
)
5496 i
.mask
->operand
= xchg2
;
5497 else if (i
.mask
->operand
== xchg2
)
5498 i
.mask
->operand
= xchg1
;
5502 if (i
.broadcast
->operand
== xchg1
)
5503 i
.broadcast
->operand
= xchg2
;
5504 else if (i
.broadcast
->operand
== xchg2
)
5505 i
.broadcast
->operand
= xchg1
;
5509 if (i
.rounding
->operand
== xchg1
)
5510 i
.rounding
->operand
= xchg2
;
5511 else if (i
.rounding
->operand
== xchg2
)
5512 i
.rounding
->operand
= xchg1
;
5517 swap_operands (void)
5523 swap_2_operands (1, i
.operands
- 2);
5527 swap_2_operands (0, i
.operands
- 1);
5533 if (i
.mem_operands
== 2)
5535 const seg_entry
*temp_seg
;
5536 temp_seg
= i
.seg
[0];
5537 i
.seg
[0] = i
.seg
[1];
5538 i
.seg
[1] = temp_seg
;
5542 /* Try to ensure constant immediates are represented in the smallest
5547 char guess_suffix
= 0;
5551 guess_suffix
= i
.suffix
;
5552 else if (i
.reg_operands
)
5554 /* Figure out a suffix from the last register operand specified.
5555 We can't do this properly yet, i.e. excluding special register
5556 instances, but the following works for instructions with
5557 immediates. In any case, we can't set i.suffix yet. */
5558 for (op
= i
.operands
; --op
>= 0;)
5559 if (i
.types
[op
].bitfield
.class != Reg
)
5561 else if (i
.types
[op
].bitfield
.byte
)
5563 guess_suffix
= BYTE_MNEM_SUFFIX
;
5566 else if (i
.types
[op
].bitfield
.word
)
5568 guess_suffix
= WORD_MNEM_SUFFIX
;
5571 else if (i
.types
[op
].bitfield
.dword
)
5573 guess_suffix
= LONG_MNEM_SUFFIX
;
5576 else if (i
.types
[op
].bitfield
.qword
)
5578 guess_suffix
= QWORD_MNEM_SUFFIX
;
5582 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5583 guess_suffix
= WORD_MNEM_SUFFIX
;
5585 for (op
= i
.operands
; --op
>= 0;)
5586 if (operand_type_check (i
.types
[op
], imm
))
5588 switch (i
.op
[op
].imms
->X_op
)
5591 /* If a suffix is given, this operand may be shortened. */
5592 switch (guess_suffix
)
5594 case LONG_MNEM_SUFFIX
:
5595 i
.types
[op
].bitfield
.imm32
= 1;
5596 i
.types
[op
].bitfield
.imm64
= 1;
5598 case WORD_MNEM_SUFFIX
:
5599 i
.types
[op
].bitfield
.imm16
= 1;
5600 i
.types
[op
].bitfield
.imm32
= 1;
5601 i
.types
[op
].bitfield
.imm32s
= 1;
5602 i
.types
[op
].bitfield
.imm64
= 1;
5604 case BYTE_MNEM_SUFFIX
:
5605 i
.types
[op
].bitfield
.imm8
= 1;
5606 i
.types
[op
].bitfield
.imm8s
= 1;
5607 i
.types
[op
].bitfield
.imm16
= 1;
5608 i
.types
[op
].bitfield
.imm32
= 1;
5609 i
.types
[op
].bitfield
.imm32s
= 1;
5610 i
.types
[op
].bitfield
.imm64
= 1;
5614 /* If this operand is at most 16 bits, convert it
5615 to a signed 16 bit number before trying to see
5616 whether it will fit in an even smaller size.
5617 This allows a 16-bit operand such as $0xffe0 to
5618 be recognised as within Imm8S range. */
5619 if ((i
.types
[op
].bitfield
.imm16
)
5620 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5622 i
.op
[op
].imms
->X_add_number
=
5623 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5626 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5627 if ((i
.types
[op
].bitfield
.imm32
)
5628 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5631 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5632 ^ ((offsetT
) 1 << 31))
5633 - ((offsetT
) 1 << 31));
5637 = operand_type_or (i
.types
[op
],
5638 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5640 /* We must avoid matching of Imm32 templates when 64bit
5641 only immediate is available. */
5642 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5643 i
.types
[op
].bitfield
.imm32
= 0;
5650 /* Symbols and expressions. */
5652 /* Convert symbolic operand to proper sizes for matching, but don't
5653 prevent matching a set of insns that only supports sizes other
5654 than those matching the insn suffix. */
5656 i386_operand_type mask
, allowed
;
5657 const insn_template
*t
;
5659 operand_type_set (&mask
, 0);
5660 operand_type_set (&allowed
, 0);
5662 for (t
= current_templates
->start
;
5663 t
< current_templates
->end
;
5666 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5667 allowed
= operand_type_and (allowed
, anyimm
);
5669 switch (guess_suffix
)
5671 case QWORD_MNEM_SUFFIX
:
5672 mask
.bitfield
.imm64
= 1;
5673 mask
.bitfield
.imm32s
= 1;
5675 case LONG_MNEM_SUFFIX
:
5676 mask
.bitfield
.imm32
= 1;
5678 case WORD_MNEM_SUFFIX
:
5679 mask
.bitfield
.imm16
= 1;
5681 case BYTE_MNEM_SUFFIX
:
5682 mask
.bitfield
.imm8
= 1;
5687 allowed
= operand_type_and (mask
, allowed
);
5688 if (!operand_type_all_zero (&allowed
))
5689 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5696 /* Try to use the smallest displacement type too. */
5698 optimize_disp (void)
5702 for (op
= i
.operands
; --op
>= 0;)
5703 if (operand_type_check (i
.types
[op
], disp
))
5705 if (i
.op
[op
].disps
->X_op
== O_constant
)
5707 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5709 if (i
.types
[op
].bitfield
.disp16
5710 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5712 /* If this operand is at most 16 bits, convert
5713 to a signed 16 bit number and don't use 64bit
5715 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5716 i
.types
[op
].bitfield
.disp64
= 0;
5719 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5720 if (i
.types
[op
].bitfield
.disp32
5721 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5723 /* If this operand is at most 32 bits, convert
5724 to a signed 32 bit number and don't use 64bit
5726 op_disp
&= (((offsetT
) 2 << 31) - 1);
5727 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5728 i
.types
[op
].bitfield
.disp64
= 0;
5731 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5733 i
.types
[op
].bitfield
.disp8
= 0;
5734 i
.types
[op
].bitfield
.disp16
= 0;
5735 i
.types
[op
].bitfield
.disp32
= 0;
5736 i
.types
[op
].bitfield
.disp32s
= 0;
5737 i
.types
[op
].bitfield
.disp64
= 0;
5741 else if (flag_code
== CODE_64BIT
)
5743 if (fits_in_signed_long (op_disp
))
5745 i
.types
[op
].bitfield
.disp64
= 0;
5746 i
.types
[op
].bitfield
.disp32s
= 1;
5748 if (i
.prefix
[ADDR_PREFIX
]
5749 && fits_in_unsigned_long (op_disp
))
5750 i
.types
[op
].bitfield
.disp32
= 1;
5752 if ((i
.types
[op
].bitfield
.disp32
5753 || i
.types
[op
].bitfield
.disp32s
5754 || i
.types
[op
].bitfield
.disp16
)
5755 && fits_in_disp8 (op_disp
))
5756 i
.types
[op
].bitfield
.disp8
= 1;
5758 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5759 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5761 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5762 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5763 i
.types
[op
].bitfield
.disp8
= 0;
5764 i
.types
[op
].bitfield
.disp16
= 0;
5765 i
.types
[op
].bitfield
.disp32
= 0;
5766 i
.types
[op
].bitfield
.disp32s
= 0;
5767 i
.types
[op
].bitfield
.disp64
= 0;
5770 /* We only support 64bit displacement on constants. */
5771 i
.types
[op
].bitfield
.disp64
= 0;
5775 /* Return 1 if there is a match in broadcast bytes between operand
5776 GIVEN and instruction template T. */
5779 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5781 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5782 && i
.types
[given
].bitfield
.byte
)
5783 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5784 && i
.types
[given
].bitfield
.word
)
5785 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5786 && i
.types
[given
].bitfield
.dword
)
5787 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5788 && i
.types
[given
].bitfield
.qword
));
5791 /* Check if operands are valid for the instruction. */
5794 check_VecOperands (const insn_template
*t
)
5799 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5800 any one operand are implicity requiring AVX512VL support if the actual
5801 operand size is YMMword or XMMword. Since this function runs after
5802 template matching, there's no need to check for YMMword/XMMword in
5804 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5805 if (!cpu_flags_all_zero (&cpu
)
5806 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5807 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5809 for (op
= 0; op
< t
->operands
; ++op
)
5811 if (t
->operand_types
[op
].bitfield
.zmmword
5812 && (i
.types
[op
].bitfield
.ymmword
5813 || i
.types
[op
].bitfield
.xmmword
))
5815 i
.error
= unsupported
;
5821 /* Without VSIB byte, we can't have a vector register for index. */
5822 if (!t
->opcode_modifier
.sib
5824 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5825 || i
.index_reg
->reg_type
.bitfield
.ymmword
5826 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5828 i
.error
= unsupported_vector_index_register
;
5832 /* Check if default mask is allowed. */
5833 if (t
->opcode_modifier
.nodefmask
5834 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5836 i
.error
= no_default_mask
;
5840 /* For VSIB byte, we need a vector register for index, and all vector
5841 registers must be distinct. */
5842 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5845 || !((t
->opcode_modifier
.sib
== VECSIB128
5846 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5847 || (t
->opcode_modifier
.sib
== VECSIB256
5848 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5849 || (t
->opcode_modifier
.sib
== VECSIB512
5850 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5852 i
.error
= invalid_vsib_address
;
5856 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5857 if (i
.reg_operands
== 2 && !i
.mask
)
5859 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5860 gas_assert (i
.types
[0].bitfield
.xmmword
5861 || i
.types
[0].bitfield
.ymmword
);
5862 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5863 gas_assert (i
.types
[2].bitfield
.xmmword
5864 || i
.types
[2].bitfield
.ymmword
);
5865 if (operand_check
== check_none
)
5867 if (register_number (i
.op
[0].regs
)
5868 != register_number (i
.index_reg
)
5869 && register_number (i
.op
[2].regs
)
5870 != register_number (i
.index_reg
)
5871 && register_number (i
.op
[0].regs
)
5872 != register_number (i
.op
[2].regs
))
5874 if (operand_check
== check_error
)
5876 i
.error
= invalid_vector_register_set
;
5879 as_warn (_("mask, index, and destination registers should be distinct"));
5881 else if (i
.reg_operands
== 1 && i
.mask
)
5883 if (i
.types
[1].bitfield
.class == RegSIMD
5884 && (i
.types
[1].bitfield
.xmmword
5885 || i
.types
[1].bitfield
.ymmword
5886 || i
.types
[1].bitfield
.zmmword
)
5887 && (register_number (i
.op
[1].regs
)
5888 == register_number (i
.index_reg
)))
5890 if (operand_check
== check_error
)
5892 i
.error
= invalid_vector_register_set
;
5895 if (operand_check
!= check_none
)
5896 as_warn (_("index and destination registers should be distinct"));
5901 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5903 if (t
->operand_types
[0].bitfield
.tmmword
5904 && i
.reg_operands
== 3)
5906 if (register_number (i
.op
[0].regs
)
5907 == register_number (i
.op
[1].regs
)
5908 || register_number (i
.op
[0].regs
)
5909 == register_number (i
.op
[2].regs
)
5910 || register_number (i
.op
[1].regs
)
5911 == register_number (i
.op
[2].regs
))
5913 i
.error
= invalid_tmm_register_set
;
5918 /* Check if broadcast is supported by the instruction and is applied
5919 to the memory operand. */
5922 i386_operand_type type
, overlap
;
5924 /* Check if specified broadcast is supported in this instruction,
5925 and its broadcast bytes match the memory operand. */
5926 op
= i
.broadcast
->operand
;
5927 if (!t
->opcode_modifier
.broadcast
5928 || !(i
.flags
[op
] & Operand_Mem
)
5929 || (!i
.types
[op
].bitfield
.unspecified
5930 && !match_broadcast_size (t
, op
)))
5933 i
.error
= unsupported_broadcast
;
5937 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5938 * i
.broadcast
->type
);
5939 operand_type_set (&type
, 0);
5940 switch (i
.broadcast
->bytes
)
5943 type
.bitfield
.word
= 1;
5946 type
.bitfield
.dword
= 1;
5949 type
.bitfield
.qword
= 1;
5952 type
.bitfield
.xmmword
= 1;
5955 type
.bitfield
.ymmword
= 1;
5958 type
.bitfield
.zmmword
= 1;
5964 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5965 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5966 && t
->operand_types
[op
].bitfield
.byte
5967 + t
->operand_types
[op
].bitfield
.word
5968 + t
->operand_types
[op
].bitfield
.dword
5969 + t
->operand_types
[op
].bitfield
.qword
> 1)
5971 overlap
.bitfield
.xmmword
= 0;
5972 overlap
.bitfield
.ymmword
= 0;
5973 overlap
.bitfield
.zmmword
= 0;
5975 if (operand_type_all_zero (&overlap
))
5978 if (t
->opcode_modifier
.checkregsize
)
5982 type
.bitfield
.baseindex
= 1;
5983 for (j
= 0; j
< i
.operands
; ++j
)
5986 && !operand_type_register_match(i
.types
[j
],
5987 t
->operand_types
[j
],
5989 t
->operand_types
[op
]))
5994 /* If broadcast is supported in this instruction, we need to check if
5995 operand of one-element size isn't specified without broadcast. */
5996 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5998 /* Find memory operand. */
5999 for (op
= 0; op
< i
.operands
; op
++)
6000 if (i
.flags
[op
] & Operand_Mem
)
6002 gas_assert (op
< i
.operands
);
6003 /* Check size of the memory operand. */
6004 if (match_broadcast_size (t
, op
))
6006 i
.error
= broadcast_needed
;
6011 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6013 /* Check if requested masking is supported. */
6016 switch (t
->opcode_modifier
.masking
)
6020 case MERGING_MASKING
:
6021 if (i
.mask
->zeroing
)
6024 i
.error
= unsupported_masking
;
6028 case DYNAMIC_MASKING
:
6029 /* Memory destinations allow only merging masking. */
6030 if (i
.mask
->zeroing
&& i
.mem_operands
)
6032 /* Find memory operand. */
6033 for (op
= 0; op
< i
.operands
; op
++)
6034 if (i
.flags
[op
] & Operand_Mem
)
6036 gas_assert (op
< i
.operands
);
6037 if (op
== i
.operands
- 1)
6039 i
.error
= unsupported_masking
;
6049 /* Check if masking is applied to dest operand. */
6050 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6052 i
.error
= mask_not_on_destination
;
6059 if (!t
->opcode_modifier
.sae
6060 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6062 i
.error
= unsupported_rc_sae
;
6065 /* If the instruction has several immediate operands and one of
6066 them is rounding, the rounding operand should be the last
6067 immediate operand. */
6068 if (i
.imm_operands
> 1
6069 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6071 i
.error
= rc_sae_operand_not_last_imm
;
6076 /* Check the special Imm4 cases; must be the first operand. */
6077 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6079 if (i
.op
[0].imms
->X_op
!= O_constant
6080 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6086 /* Turn off Imm<N> so that update_imm won't complain. */
6087 operand_type_set (&i
.types
[0], 0);
6090 /* Check vector Disp8 operand. */
6091 if (t
->opcode_modifier
.disp8memshift
6092 && i
.disp_encoding
!= disp_encoding_32bit
)
6095 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6096 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6097 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6100 const i386_operand_type
*type
= NULL
;
6103 for (op
= 0; op
< i
.operands
; op
++)
6104 if (i
.flags
[op
] & Operand_Mem
)
6106 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6107 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6108 else if (t
->operand_types
[op
].bitfield
.xmmword
6109 + t
->operand_types
[op
].bitfield
.ymmword
6110 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6111 type
= &t
->operand_types
[op
];
6112 else if (!i
.types
[op
].bitfield
.unspecified
)
6113 type
= &i
.types
[op
];
6115 else if (i
.types
[op
].bitfield
.class == RegSIMD
6116 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6118 if (i
.types
[op
].bitfield
.zmmword
)
6120 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6122 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6128 if (type
->bitfield
.zmmword
)
6130 else if (type
->bitfield
.ymmword
)
6132 else if (type
->bitfield
.xmmword
)
6136 /* For the check in fits_in_disp8(). */
6137 if (i
.memshift
== 0)
6141 for (op
= 0; op
< i
.operands
; op
++)
6142 if (operand_type_check (i
.types
[op
], disp
)
6143 && i
.op
[op
].disps
->X_op
== O_constant
)
6145 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6147 i
.types
[op
].bitfield
.disp8
= 1;
6150 i
.types
[op
].bitfield
.disp8
= 0;
6159 /* Check if encoding requirements are met by the instruction. */
6162 VEX_check_encoding (const insn_template
*t
)
6164 if (i
.vec_encoding
== vex_encoding_error
)
6166 i
.error
= unsupported
;
6170 if (i
.vec_encoding
== vex_encoding_evex
)
6172 /* This instruction must be encoded with EVEX prefix. */
6173 if (!is_evex_encoding (t
))
6175 i
.error
= unsupported
;
6181 if (!t
->opcode_modifier
.vex
)
6183 /* This instruction template doesn't have VEX prefix. */
6184 if (i
.vec_encoding
!= vex_encoding_default
)
6186 i
.error
= unsupported
;
6195 static const insn_template
*
6196 match_template (char mnem_suffix
)
6198 /* Points to template once we've found it. */
6199 const insn_template
*t
;
6200 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6201 i386_operand_type overlap4
;
6202 unsigned int found_reverse_match
;
6203 i386_opcode_modifier suffix_check
;
6204 i386_operand_type operand_types
[MAX_OPERANDS
];
6205 int addr_prefix_disp
;
6206 unsigned int j
, size_match
, check_register
;
6207 enum i386_error specific_error
= 0;
6209 #if MAX_OPERANDS != 5
6210 # error "MAX_OPERANDS must be 5."
6213 found_reverse_match
= 0;
6214 addr_prefix_disp
= -1;
6216 /* Prepare for mnemonic suffix check. */
6217 memset (&suffix_check
, 0, sizeof (suffix_check
));
6218 switch (mnem_suffix
)
6220 case BYTE_MNEM_SUFFIX
:
6221 suffix_check
.no_bsuf
= 1;
6223 case WORD_MNEM_SUFFIX
:
6224 suffix_check
.no_wsuf
= 1;
6226 case SHORT_MNEM_SUFFIX
:
6227 suffix_check
.no_ssuf
= 1;
6229 case LONG_MNEM_SUFFIX
:
6230 suffix_check
.no_lsuf
= 1;
6232 case QWORD_MNEM_SUFFIX
:
6233 suffix_check
.no_qsuf
= 1;
6236 /* NB: In Intel syntax, normally we can check for memory operand
6237 size when there is no mnemonic suffix. But jmp and call have
6238 2 different encodings with Dword memory operand size, one with
6239 No_ldSuf and the other without. i.suffix is set to
6240 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6241 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6242 suffix_check
.no_ldsuf
= 1;
6245 /* Must have right number of operands. */
6246 i
.error
= number_of_operands_mismatch
;
6248 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6250 addr_prefix_disp
= -1;
6251 found_reverse_match
= 0;
6253 if (i
.operands
!= t
->operands
)
6256 /* Check processor support. */
6257 i
.error
= unsupported
;
6258 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6261 /* Check Pseudo Prefix. */
6262 i
.error
= unsupported
;
6263 if (t
->opcode_modifier
.pseudovexprefix
6264 && !(i
.vec_encoding
== vex_encoding_vex
6265 || i
.vec_encoding
== vex_encoding_vex3
))
6268 /* Check AT&T mnemonic. */
6269 i
.error
= unsupported_with_intel_mnemonic
;
6270 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6273 /* Check AT&T/Intel syntax. */
6274 i
.error
= unsupported_syntax
;
6275 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6276 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6279 /* Check Intel64/AMD64 ISA. */
6283 /* Default: Don't accept Intel64. */
6284 if (t
->opcode_modifier
.isa64
== INTEL64
)
6288 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6289 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6293 /* -mintel64: Don't accept AMD64. */
6294 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6299 /* Check the suffix. */
6300 i
.error
= invalid_instruction_suffix
;
6301 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6302 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6303 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6304 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6305 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6306 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6309 size_match
= operand_size_match (t
);
6313 /* This is intentionally not
6315 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6317 as the case of a missing * on the operand is accepted (perhaps with
6318 a warning, issued further down). */
6319 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6321 i
.error
= operand_type_mismatch
;
6325 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6326 operand_types
[j
] = t
->operand_types
[j
];
6328 /* In general, don't allow
6329 - 64-bit operands outside of 64-bit mode,
6330 - 32-bit operands on pre-386. */
6331 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6332 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6333 && flag_code
!= CODE_64BIT
6334 && !(t
->base_opcode
== 0xfc7
6335 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
6336 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6337 || (i
.suffix
== LONG_MNEM_SUFFIX
6338 && !cpu_arch_flags
.bitfield
.cpui386
))
6340 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6341 && !intel_float_operand (t
->name
))
6342 : intel_float_operand (t
->name
) != 2)
6343 && (t
->operands
== i
.imm_operands
6344 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6345 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6346 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6347 || (operand_types
[j
].bitfield
.class != RegMMX
6348 && operand_types
[j
].bitfield
.class != RegSIMD
6349 && operand_types
[j
].bitfield
.class != RegMask
))
6350 && !t
->opcode_modifier
.sib
)
6353 /* Do not verify operands when there are none. */
6356 if (VEX_check_encoding (t
))
6358 specific_error
= i
.error
;
6362 /* We've found a match; break out of loop. */
6366 if (!t
->opcode_modifier
.jump
6367 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6369 /* There should be only one Disp operand. */
6370 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6371 if (operand_type_check (operand_types
[j
], disp
))
6373 if (j
< MAX_OPERANDS
)
6375 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6377 addr_prefix_disp
= j
;
6379 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6380 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6384 override
= !override
;
6387 if (operand_types
[j
].bitfield
.disp32
6388 && operand_types
[j
].bitfield
.disp16
)
6390 operand_types
[j
].bitfield
.disp16
= override
;
6391 operand_types
[j
].bitfield
.disp32
= !override
;
6393 operand_types
[j
].bitfield
.disp32s
= 0;
6394 operand_types
[j
].bitfield
.disp64
= 0;
6398 if (operand_types
[j
].bitfield
.disp32s
6399 || operand_types
[j
].bitfield
.disp64
)
6401 operand_types
[j
].bitfield
.disp64
&= !override
;
6402 operand_types
[j
].bitfield
.disp32s
&= !override
;
6403 operand_types
[j
].bitfield
.disp32
= override
;
6405 operand_types
[j
].bitfield
.disp16
= 0;
6411 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6412 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6415 /* We check register size if needed. */
6416 if (t
->opcode_modifier
.checkregsize
)
6418 check_register
= (1 << t
->operands
) - 1;
6420 check_register
&= ~(1 << i
.broadcast
->operand
);
6425 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6426 switch (t
->operands
)
6429 if (!operand_type_match (overlap0
, i
.types
[0]))
6433 /* xchg %eax, %eax is a special case. It is an alias for nop
6434 only in 32bit mode and we can use opcode 0x90. In 64bit
6435 mode, we can't use 0x90 for xchg %eax, %eax since it should
6436 zero-extend %eax to %rax. */
6437 if (flag_code
== CODE_64BIT
6438 && t
->base_opcode
== 0x90
6439 && i
.types
[0].bitfield
.instance
== Accum
6440 && i
.types
[0].bitfield
.dword
6441 && i
.types
[1].bitfield
.instance
== Accum
6442 && i
.types
[1].bitfield
.dword
)
6444 /* xrelease mov %eax, <disp> is another special case. It must not
6445 match the accumulator-only encoding of mov. */
6446 if (flag_code
!= CODE_64BIT
6448 && t
->base_opcode
== 0xa0
6449 && i
.types
[0].bitfield
.instance
== Accum
6450 && (i
.flags
[1] & Operand_Mem
))
6455 if (!(size_match
& MATCH_STRAIGHT
))
6457 /* Reverse direction of operands if swapping is possible in the first
6458 place (operands need to be symmetric) and
6459 - the load form is requested, and the template is a store form,
6460 - the store form is requested, and the template is a load form,
6461 - the non-default (swapped) form is requested. */
6462 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6463 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6464 && !operand_type_all_zero (&overlap1
))
6465 switch (i
.dir_encoding
)
6467 case dir_encoding_load
:
6468 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6469 || t
->opcode_modifier
.regmem
)
6473 case dir_encoding_store
:
6474 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6475 && !t
->opcode_modifier
.regmem
)
6479 case dir_encoding_swap
:
6482 case dir_encoding_default
:
6485 /* If we want store form, we skip the current load. */
6486 if ((i
.dir_encoding
== dir_encoding_store
6487 || i
.dir_encoding
== dir_encoding_swap
)
6488 && i
.mem_operands
== 0
6489 && t
->opcode_modifier
.load
)
6494 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6495 if (!operand_type_match (overlap0
, i
.types
[0])
6496 || !operand_type_match (overlap1
, i
.types
[1])
6497 || ((check_register
& 3) == 3
6498 && !operand_type_register_match (i
.types
[0],
6503 /* Check if other direction is valid ... */
6504 if (!t
->opcode_modifier
.d
)
6508 if (!(size_match
& MATCH_REVERSE
))
6510 /* Try reversing direction of operands. */
6511 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6512 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6513 if (!operand_type_match (overlap0
, i
.types
[0])
6514 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6516 && !operand_type_register_match (i
.types
[0],
6517 operand_types
[i
.operands
- 1],
6518 i
.types
[i
.operands
- 1],
6521 /* Does not match either direction. */
6524 /* found_reverse_match holds which of D or FloatR
6526 if (!t
->opcode_modifier
.d
)
6527 found_reverse_match
= 0;
6528 else if (operand_types
[0].bitfield
.tbyte
)
6529 found_reverse_match
= Opcode_FloatD
;
6530 else if (operand_types
[0].bitfield
.xmmword
6531 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6532 || operand_types
[0].bitfield
.class == RegMMX
6533 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6534 || is_any_vex_encoding(t
))
6535 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6536 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6538 found_reverse_match
= Opcode_D
;
6539 if (t
->opcode_modifier
.floatr
)
6540 found_reverse_match
|= Opcode_FloatR
;
6544 /* Found a forward 2 operand match here. */
6545 switch (t
->operands
)
6548 overlap4
= operand_type_and (i
.types
[4],
6552 overlap3
= operand_type_and (i
.types
[3],
6556 overlap2
= operand_type_and (i
.types
[2],
6561 switch (t
->operands
)
6564 if (!operand_type_match (overlap4
, i
.types
[4])
6565 || !operand_type_register_match (i
.types
[3],
6572 if (!operand_type_match (overlap3
, i
.types
[3])
6573 || ((check_register
& 0xa) == 0xa
6574 && !operand_type_register_match (i
.types
[1],
6578 || ((check_register
& 0xc) == 0xc
6579 && !operand_type_register_match (i
.types
[2],
6586 /* Here we make use of the fact that there are no
6587 reverse match 3 operand instructions. */
6588 if (!operand_type_match (overlap2
, i
.types
[2])
6589 || ((check_register
& 5) == 5
6590 && !operand_type_register_match (i
.types
[0],
6594 || ((check_register
& 6) == 6
6595 && !operand_type_register_match (i
.types
[1],
6603 /* Found either forward/reverse 2, 3 or 4 operand match here:
6604 slip through to break. */
6607 /* Check if vector operands are valid. */
6608 if (check_VecOperands (t
))
6610 specific_error
= i
.error
;
6614 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6615 if (VEX_check_encoding (t
))
6617 specific_error
= i
.error
;
6621 /* We've found a match; break out of loop. */
6625 if (t
== current_templates
->end
)
6627 /* We found no match. */
6628 const char *err_msg
;
6629 switch (specific_error
? specific_error
: i
.error
)
6633 case operand_size_mismatch
:
6634 err_msg
= _("operand size mismatch");
6636 case operand_type_mismatch
:
6637 err_msg
= _("operand type mismatch");
6639 case register_type_mismatch
:
6640 err_msg
= _("register type mismatch");
6642 case number_of_operands_mismatch
:
6643 err_msg
= _("number of operands mismatch");
6645 case invalid_instruction_suffix
:
6646 err_msg
= _("invalid instruction suffix");
6649 err_msg
= _("constant doesn't fit in 4 bits");
6651 case unsupported_with_intel_mnemonic
:
6652 err_msg
= _("unsupported with Intel mnemonic");
6654 case unsupported_syntax
:
6655 err_msg
= _("unsupported syntax");
6658 as_bad (_("unsupported instruction `%s'"),
6659 current_templates
->start
->name
);
6661 case invalid_sib_address
:
6662 err_msg
= _("invalid SIB address");
6664 case invalid_vsib_address
:
6665 err_msg
= _("invalid VSIB address");
6667 case invalid_vector_register_set
:
6668 err_msg
= _("mask, index, and destination registers must be distinct");
6670 case invalid_tmm_register_set
:
6671 err_msg
= _("all tmm registers must be distinct");
6673 case unsupported_vector_index_register
:
6674 err_msg
= _("unsupported vector index register");
6676 case unsupported_broadcast
:
6677 err_msg
= _("unsupported broadcast");
6679 case broadcast_needed
:
6680 err_msg
= _("broadcast is needed for operand of such type");
6682 case unsupported_masking
:
6683 err_msg
= _("unsupported masking");
6685 case mask_not_on_destination
:
6686 err_msg
= _("mask not on destination operand");
6688 case no_default_mask
:
6689 err_msg
= _("default mask isn't allowed");
6691 case unsupported_rc_sae
:
6692 err_msg
= _("unsupported static rounding/sae");
6694 case rc_sae_operand_not_last_imm
:
6696 err_msg
= _("RC/SAE operand must precede immediate operands");
6698 err_msg
= _("RC/SAE operand must follow immediate operands");
6700 case invalid_register_operand
:
6701 err_msg
= _("invalid register operand");
6704 as_bad (_("%s for `%s'"), err_msg
,
6705 current_templates
->start
->name
);
6709 if (!quiet_warnings
)
6712 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6713 as_warn (_("indirect %s without `*'"), t
->name
);
6715 if (t
->opcode_modifier
.isprefix
6716 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6718 /* Warn them that a data or address size prefix doesn't
6719 affect assembly of the next line of code. */
6720 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6724 /* Copy the template we found. */
6727 if (addr_prefix_disp
!= -1)
6728 i
.tm
.operand_types
[addr_prefix_disp
]
6729 = operand_types
[addr_prefix_disp
];
6731 if (found_reverse_match
)
6733 /* If we found a reverse match we must alter the opcode direction
6734 bit and clear/flip the regmem modifier one. found_reverse_match
6735 holds bits to change (different for int & float insns). */
6737 i
.tm
.base_opcode
^= found_reverse_match
;
6739 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6740 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6742 /* Certain SIMD insns have their load forms specified in the opcode
6743 table, and hence we need to _set_ RegMem instead of clearing it.
6744 We need to avoid setting the bit though on insns like KMOVW. */
6745 i
.tm
.opcode_modifier
.regmem
6746 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6747 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6748 && !i
.tm
.opcode_modifier
.regmem
;
6757 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6758 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6760 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6762 as_bad (_("`%s' operand %u must use `%ses' segment"),
6764 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6769 /* There's only ever one segment override allowed per instruction.
6770 This instruction possibly has a legal segment override on the
6771 second operand, so copy the segment to where non-string
6772 instructions store it, allowing common code. */
6773 i
.seg
[op
] = i
.seg
[1];
6779 process_suffix (void)
6781 bfd_boolean is_crc32
= FALSE
;
6783 /* If matched instruction specifies an explicit instruction mnemonic
6785 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6786 i
.suffix
= WORD_MNEM_SUFFIX
;
6787 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6788 i
.suffix
= LONG_MNEM_SUFFIX
;
6789 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6790 i
.suffix
= QWORD_MNEM_SUFFIX
;
6791 else if (i
.reg_operands
6792 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6793 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6795 unsigned int numop
= i
.operands
;
6797 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6798 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6800 /* movsx/movzx want only their source operand considered here, for the
6801 ambiguity checking below. The suffix will be replaced afterwards
6802 to represent the destination (register). */
6803 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6804 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6807 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6808 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6811 /* If there's no instruction mnemonic suffix we try to invent one
6812 based on GPR operands. */
6815 /* We take i.suffix from the last register operand specified,
6816 Destination register type is more significant than source
6817 register type. crc32 in SSE4.2 prefers source register
6819 unsigned int op
= is_crc32
? 1 : i
.operands
;
6822 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6823 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6825 if (i
.types
[op
].bitfield
.class != Reg
)
6827 if (i
.types
[op
].bitfield
.byte
)
6828 i
.suffix
= BYTE_MNEM_SUFFIX
;
6829 else if (i
.types
[op
].bitfield
.word
)
6830 i
.suffix
= WORD_MNEM_SUFFIX
;
6831 else if (i
.types
[op
].bitfield
.dword
)
6832 i
.suffix
= LONG_MNEM_SUFFIX
;
6833 else if (i
.types
[op
].bitfield
.qword
)
6834 i
.suffix
= QWORD_MNEM_SUFFIX
;
6840 /* As an exception, movsx/movzx silently default to a byte source
6842 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6843 && !i
.suffix
&& !intel_syntax
)
6844 i
.suffix
= BYTE_MNEM_SUFFIX
;
6846 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6849 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6850 && i
.tm
.opcode_modifier
.no_bsuf
)
6852 else if (!check_byte_reg ())
6855 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6858 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6859 && i
.tm
.opcode_modifier
.no_lsuf
6860 && !i
.tm
.opcode_modifier
.todword
6861 && !i
.tm
.opcode_modifier
.toqword
)
6863 else if (!check_long_reg ())
6866 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6869 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6870 && i
.tm
.opcode_modifier
.no_qsuf
6871 && !i
.tm
.opcode_modifier
.todword
6872 && !i
.tm
.opcode_modifier
.toqword
)
6874 else if (!check_qword_reg ())
6877 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6880 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6881 && i
.tm
.opcode_modifier
.no_wsuf
)
6883 else if (!check_word_reg ())
6886 else if (intel_syntax
6887 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6888 /* Do nothing if the instruction is going to ignore the prefix. */
6893 /* Undo the movsx/movzx change done above. */
6896 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6899 i
.suffix
= stackop_size
;
6900 if (stackop_size
== LONG_MNEM_SUFFIX
)
6902 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6903 .code16gcc directive to support 16-bit mode with
6904 32-bit address. For IRET without a suffix, generate
6905 16-bit IRET (opcode 0xcf) to return from an interrupt
6907 if (i
.tm
.base_opcode
== 0xcf)
6909 i
.suffix
= WORD_MNEM_SUFFIX
;
6910 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6912 /* Warn about changed behavior for segment register push/pop. */
6913 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6914 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6919 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6920 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6921 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6922 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6923 && i
.tm
.extension_opcode
<= 3)))
6928 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6930 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6931 || i
.tm
.opcode_modifier
.no_lsuf
)
6932 i
.suffix
= QWORD_MNEM_SUFFIX
;
6937 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6938 i
.suffix
= LONG_MNEM_SUFFIX
;
6941 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6942 i
.suffix
= WORD_MNEM_SUFFIX
;
6948 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6949 /* Also cover lret/retf/iret in 64-bit mode. */
6950 || (flag_code
== CODE_64BIT
6951 && !i
.tm
.opcode_modifier
.no_lsuf
6952 && !i
.tm
.opcode_modifier
.no_qsuf
))
6953 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6954 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6955 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6956 /* Accept FLDENV et al without suffix. */
6957 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6959 unsigned int suffixes
, evex
= 0;
6961 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6962 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6964 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6966 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6968 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6970 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6973 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6974 also suitable for AT&T syntax mode, it was requested that this be
6975 restricted to just Intel syntax. */
6976 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6980 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6982 if (is_evex_encoding (&i
.tm
)
6983 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6985 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6986 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6987 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6988 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6989 if (!i
.tm
.opcode_modifier
.evex
6990 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6991 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6994 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6995 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6996 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6999 /* Any properly sized operand disambiguates the insn. */
7000 if (i
.types
[op
].bitfield
.xmmword
7001 || i
.types
[op
].bitfield
.ymmword
7002 || i
.types
[op
].bitfield
.zmmword
)
7004 suffixes
&= ~(7 << 6);
7009 if ((i
.flags
[op
] & Operand_Mem
)
7010 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7012 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7014 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7016 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7018 if (is_evex_encoding (&i
.tm
))
7024 /* Are multiple suffixes / operand sizes allowed? */
7025 if (suffixes
& (suffixes
- 1))
7028 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7029 || operand_check
== check_error
))
7031 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7034 if (operand_check
== check_error
)
7036 as_bad (_("no instruction mnemonic suffix given and "
7037 "no register operands; can't size `%s'"), i
.tm
.name
);
7040 if (operand_check
== check_warning
)
7041 as_warn (_("%s; using default for `%s'"),
7043 ? _("ambiguous operand size")
7044 : _("no instruction mnemonic suffix given and "
7045 "no register operands"),
7048 if (i
.tm
.opcode_modifier
.floatmf
)
7049 i
.suffix
= SHORT_MNEM_SUFFIX
;
7050 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7051 || (i
.tm
.base_opcode
== 0x63
7052 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7053 /* handled below */;
7055 i
.tm
.opcode_modifier
.evex
= evex
;
7056 else if (flag_code
== CODE_16BIT
)
7057 i
.suffix
= WORD_MNEM_SUFFIX
;
7058 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7059 i
.suffix
= LONG_MNEM_SUFFIX
;
7061 i
.suffix
= QWORD_MNEM_SUFFIX
;
7065 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7066 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7068 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7069 In AT&T syntax, if there is no suffix (warned about above), the default
7070 will be byte extension. */
7071 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7072 i
.tm
.base_opcode
|= 1;
7074 /* For further processing, the suffix should represent the destination
7075 (register). This is already the case when one was used with
7076 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7077 no suffix to begin with. */
7078 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7080 if (i
.types
[1].bitfield
.word
)
7081 i
.suffix
= WORD_MNEM_SUFFIX
;
7082 else if (i
.types
[1].bitfield
.qword
)
7083 i
.suffix
= QWORD_MNEM_SUFFIX
;
7085 i
.suffix
= LONG_MNEM_SUFFIX
;
7087 i
.tm
.opcode_modifier
.w
= 0;
7091 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7092 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7093 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7095 /* Change the opcode based on the operand size given by i.suffix. */
7098 /* Size floating point instruction. */
7099 case LONG_MNEM_SUFFIX
:
7100 if (i
.tm
.opcode_modifier
.floatmf
)
7102 i
.tm
.base_opcode
^= 4;
7106 case WORD_MNEM_SUFFIX
:
7107 case QWORD_MNEM_SUFFIX
:
7108 /* It's not a byte, select word/dword operation. */
7109 if (i
.tm
.opcode_modifier
.w
)
7112 i
.tm
.base_opcode
|= 8;
7114 i
.tm
.base_opcode
|= 1;
7117 case SHORT_MNEM_SUFFIX
:
7118 /* Now select between word & dword operations via the operand
7119 size prefix, except for instructions that will ignore this
7121 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7122 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7123 && !i
.tm
.opcode_modifier
.floatmf
7124 && !is_any_vex_encoding (&i
.tm
)
7125 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7126 || (flag_code
== CODE_64BIT
7127 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7129 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7131 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7132 prefix
= ADDR_PREFIX_OPCODE
;
7134 if (!add_prefix (prefix
))
7138 /* Set mode64 for an operand. */
7139 if (i
.suffix
== QWORD_MNEM_SUFFIX
7140 && flag_code
== CODE_64BIT
7141 && !i
.tm
.opcode_modifier
.norex64
7142 && !i
.tm
.opcode_modifier
.vexw
7143 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7145 && ! (i
.operands
== 2
7146 && i
.tm
.base_opcode
== 0x90
7147 && i
.tm
.extension_opcode
== None
7148 && i
.types
[0].bitfield
.instance
== Accum
7149 && i
.types
[0].bitfield
.qword
7150 && i
.types
[1].bitfield
.instance
== Accum
7151 && i
.types
[1].bitfield
.qword
))
7157 /* Select word/dword/qword operation with explict data sizing prefix
7158 when there are no suitable register operands. */
7159 if (i
.tm
.opcode_modifier
.w
7160 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7162 || (i
.reg_operands
== 1
7164 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7166 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7167 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7170 i
.tm
.base_opcode
|= 1;
7174 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7176 gas_assert (!i
.suffix
);
7177 gas_assert (i
.reg_operands
);
7179 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7182 /* The address size override prefix changes the size of the
7184 if (flag_code
== CODE_64BIT
7185 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7187 as_bad (_("16-bit addressing unavailable for `%s'"),
7192 if ((flag_code
== CODE_32BIT
7193 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7194 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7195 && !add_prefix (ADDR_PREFIX_OPCODE
))
7200 /* Check invalid register operand when the address size override
7201 prefix changes the size of register operands. */
7203 enum { need_word
, need_dword
, need_qword
} need
;
7205 /* Check the register operand for the address size prefix if
7206 the memory operand has no real registers, like symbol, DISP
7208 if (i
.mem_operands
== 1
7209 && i
.reg_operands
== 1
7211 && i
.types
[1].bitfield
.class == Reg
7212 && (flag_code
== CODE_32BIT
7213 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7214 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7215 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7217 && i
.base_reg
->reg_num
== RegIP
7218 && i
.base_reg
->reg_type
.bitfield
.qword
))
7219 && !add_prefix (ADDR_PREFIX_OPCODE
))
7222 if (flag_code
== CODE_32BIT
)
7223 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7224 else if (i
.prefix
[ADDR_PREFIX
])
7227 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7229 for (op
= 0; op
< i
.operands
; op
++)
7231 if (i
.types
[op
].bitfield
.class != Reg
)
7237 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7241 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7245 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7250 as_bad (_("invalid register operand size for `%s'"),
7261 check_byte_reg (void)
7265 for (op
= i
.operands
; --op
>= 0;)
7267 /* Skip non-register operands. */
7268 if (i
.types
[op
].bitfield
.class != Reg
)
7271 /* If this is an eight bit register, it's OK. If it's the 16 or
7272 32 bit version of an eight bit register, we will just use the
7273 low portion, and that's OK too. */
7274 if (i
.types
[op
].bitfield
.byte
)
7277 /* I/O port address operands are OK too. */
7278 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7279 && i
.tm
.operand_types
[op
].bitfield
.word
)
7282 /* crc32 only wants its source operand checked here. */
7283 if (i
.tm
.base_opcode
== 0xf38f0
7284 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7288 /* Any other register is bad. */
7289 as_bad (_("`%s%s' not allowed with `%s%c'"),
7290 register_prefix
, i
.op
[op
].regs
->reg_name
,
7291 i
.tm
.name
, i
.suffix
);
7298 check_long_reg (void)
7302 for (op
= i
.operands
; --op
>= 0;)
7303 /* Skip non-register operands. */
7304 if (i
.types
[op
].bitfield
.class != Reg
)
7306 /* Reject eight bit registers, except where the template requires
7307 them. (eg. movzb) */
7308 else if (i
.types
[op
].bitfield
.byte
7309 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7310 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7311 && (i
.tm
.operand_types
[op
].bitfield
.word
7312 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7314 as_bad (_("`%s%s' not allowed with `%s%c'"),
7316 i
.op
[op
].regs
->reg_name
,
7321 /* Error if the e prefix on a general reg is missing. */
7322 else if (i
.types
[op
].bitfield
.word
7323 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7324 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7325 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7327 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7328 register_prefix
, i
.op
[op
].regs
->reg_name
,
7332 /* Warn if the r prefix on a general reg is present. */
7333 else if (i
.types
[op
].bitfield
.qword
7334 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7335 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7336 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7339 && i
.tm
.opcode_modifier
.toqword
7340 && i
.types
[0].bitfield
.class != RegSIMD
)
7342 /* Convert to QWORD. We want REX byte. */
7343 i
.suffix
= QWORD_MNEM_SUFFIX
;
7347 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7348 register_prefix
, i
.op
[op
].regs
->reg_name
,
7357 check_qword_reg (void)
7361 for (op
= i
.operands
; --op
>= 0; )
7362 /* Skip non-register operands. */
7363 if (i
.types
[op
].bitfield
.class != Reg
)
7365 /* Reject eight bit registers, except where the template requires
7366 them. (eg. movzb) */
7367 else if (i
.types
[op
].bitfield
.byte
7368 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7369 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7370 && (i
.tm
.operand_types
[op
].bitfield
.word
7371 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7373 as_bad (_("`%s%s' not allowed with `%s%c'"),
7375 i
.op
[op
].regs
->reg_name
,
7380 /* Warn if the r prefix on a general reg is missing. */
7381 else if ((i
.types
[op
].bitfield
.word
7382 || i
.types
[op
].bitfield
.dword
)
7383 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7384 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7385 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7387 /* Prohibit these changes in the 64bit mode, since the
7388 lowering is more complicated. */
7390 && i
.tm
.opcode_modifier
.todword
7391 && i
.types
[0].bitfield
.class != RegSIMD
)
7393 /* Convert to DWORD. We don't want REX byte. */
7394 i
.suffix
= LONG_MNEM_SUFFIX
;
7398 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7399 register_prefix
, i
.op
[op
].regs
->reg_name
,
7408 check_word_reg (void)
7411 for (op
= i
.operands
; --op
>= 0;)
7412 /* Skip non-register operands. */
7413 if (i
.types
[op
].bitfield
.class != Reg
)
7415 /* Reject eight bit registers, except where the template requires
7416 them. (eg. movzb) */
7417 else if (i
.types
[op
].bitfield
.byte
7418 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7419 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7420 && (i
.tm
.operand_types
[op
].bitfield
.word
7421 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7423 as_bad (_("`%s%s' not allowed with `%s%c'"),
7425 i
.op
[op
].regs
->reg_name
,
7430 /* Error if the e or r prefix on a general reg is present. */
7431 else if ((i
.types
[op
].bitfield
.dword
7432 || i
.types
[op
].bitfield
.qword
)
7433 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7434 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7435 && i
.tm
.operand_types
[op
].bitfield
.word
)
7437 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7438 register_prefix
, i
.op
[op
].regs
->reg_name
,
7446 update_imm (unsigned int j
)
7448 i386_operand_type overlap
= i
.types
[j
];
7449 if ((overlap
.bitfield
.imm8
7450 || overlap
.bitfield
.imm8s
7451 || overlap
.bitfield
.imm16
7452 || overlap
.bitfield
.imm32
7453 || overlap
.bitfield
.imm32s
7454 || overlap
.bitfield
.imm64
)
7455 && !operand_type_equal (&overlap
, &imm8
)
7456 && !operand_type_equal (&overlap
, &imm8s
)
7457 && !operand_type_equal (&overlap
, &imm16
)
7458 && !operand_type_equal (&overlap
, &imm32
)
7459 && !operand_type_equal (&overlap
, &imm32s
)
7460 && !operand_type_equal (&overlap
, &imm64
))
7464 i386_operand_type temp
;
7466 operand_type_set (&temp
, 0);
7467 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7469 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7470 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7472 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7473 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7474 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7476 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7477 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7480 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7483 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7484 || operand_type_equal (&overlap
, &imm16_32
)
7485 || operand_type_equal (&overlap
, &imm16_32s
))
7487 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7492 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7493 overlap
= operand_type_and (overlap
, imm32s
);
7494 else if (i
.prefix
[DATA_PREFIX
])
7495 overlap
= operand_type_and (overlap
,
7496 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7497 if (!operand_type_equal (&overlap
, &imm8
)
7498 && !operand_type_equal (&overlap
, &imm8s
)
7499 && !operand_type_equal (&overlap
, &imm16
)
7500 && !operand_type_equal (&overlap
, &imm32
)
7501 && !operand_type_equal (&overlap
, &imm32s
)
7502 && !operand_type_equal (&overlap
, &imm64
))
7504 as_bad (_("no instruction mnemonic suffix given; "
7505 "can't determine immediate size"));
7509 i
.types
[j
] = overlap
;
7519 /* Update the first 2 immediate operands. */
7520 n
= i
.operands
> 2 ? 2 : i
.operands
;
7523 for (j
= 0; j
< n
; j
++)
7524 if (update_imm (j
) == 0)
7527 /* The 3rd operand can't be immediate operand. */
7528 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7535 process_operands (void)
7537 /* Default segment register this instruction will use for memory
7538 accesses. 0 means unknown. This is only for optimizing out
7539 unnecessary segment overrides. */
7540 const seg_entry
*default_seg
= 0;
7542 if (i
.tm
.opcode_modifier
.sse2avx
)
7544 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7546 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7547 i
.prefix
[REX_PREFIX
] = 0;
7550 /* ImmExt should be processed after SSE2AVX. */
7551 else if (i
.tm
.opcode_modifier
.immext
)
7554 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7556 unsigned int dupl
= i
.operands
;
7557 unsigned int dest
= dupl
- 1;
7560 /* The destination must be an xmm register. */
7561 gas_assert (i
.reg_operands
7562 && MAX_OPERANDS
> dupl
7563 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7565 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7566 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7568 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7570 /* Keep xmm0 for instructions with VEX prefix and 3
7572 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7573 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7578 /* We remove the first xmm0 and keep the number of
7579 operands unchanged, which in fact duplicates the
7581 for (j
= 1; j
< i
.operands
; j
++)
7583 i
.op
[j
- 1] = i
.op
[j
];
7584 i
.types
[j
- 1] = i
.types
[j
];
7585 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7586 i
.flags
[j
- 1] = i
.flags
[j
];
7590 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7592 gas_assert ((MAX_OPERANDS
- 1) > dupl
7593 && (i
.tm
.opcode_modifier
.vexsources
7596 /* Add the implicit xmm0 for instructions with VEX prefix
7598 for (j
= i
.operands
; j
> 0; j
--)
7600 i
.op
[j
] = i
.op
[j
- 1];
7601 i
.types
[j
] = i
.types
[j
- 1];
7602 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7603 i
.flags
[j
] = i
.flags
[j
- 1];
7606 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7607 i
.types
[0] = regxmm
;
7608 i
.tm
.operand_types
[0] = regxmm
;
7611 i
.reg_operands
+= 2;
7616 i
.op
[dupl
] = i
.op
[dest
];
7617 i
.types
[dupl
] = i
.types
[dest
];
7618 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7619 i
.flags
[dupl
] = i
.flags
[dest
];
7628 i
.op
[dupl
] = i
.op
[dest
];
7629 i
.types
[dupl
] = i
.types
[dest
];
7630 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7631 i
.flags
[dupl
] = i
.flags
[dest
];
7634 if (i
.tm
.opcode_modifier
.immext
)
7637 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7638 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7642 for (j
= 1; j
< i
.operands
; j
++)
7644 i
.op
[j
- 1] = i
.op
[j
];
7645 i
.types
[j
- 1] = i
.types
[j
];
7647 /* We need to adjust fields in i.tm since they are used by
7648 build_modrm_byte. */
7649 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7651 i
.flags
[j
- 1] = i
.flags
[j
];
7658 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7660 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7662 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7663 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7664 regnum
= register_number (i
.op
[1].regs
);
7665 first_reg_in_group
= regnum
& ~3;
7666 last_reg_in_group
= first_reg_in_group
+ 3;
7667 if (regnum
!= first_reg_in_group
)
7668 as_warn (_("source register `%s%s' implicitly denotes"
7669 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7670 register_prefix
, i
.op
[1].regs
->reg_name
,
7671 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7672 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7675 else if (i
.tm
.opcode_modifier
.regkludge
)
7677 /* The imul $imm, %reg instruction is converted into
7678 imul $imm, %reg, %reg, and the clr %reg instruction
7679 is converted into xor %reg, %reg. */
7681 unsigned int first_reg_op
;
7683 if (operand_type_check (i
.types
[0], reg
))
7687 /* Pretend we saw the extra register operand. */
7688 gas_assert (i
.reg_operands
== 1
7689 && i
.op
[first_reg_op
+ 1].regs
== 0);
7690 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7691 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7696 if (i
.tm
.opcode_modifier
.modrm
)
7698 /* The opcode is completed (modulo i.tm.extension_opcode which
7699 must be put into the modrm byte). Now, we make the modrm and
7700 index base bytes based on all the info we've collected. */
7702 default_seg
= build_modrm_byte ();
7704 else if (i
.types
[0].bitfield
.class == SReg
)
7706 if (flag_code
!= CODE_64BIT
7707 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7708 && i
.op
[0].regs
->reg_num
== 1
7709 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7710 && i
.op
[0].regs
->reg_num
< 4)
7712 as_bad (_("you can't `%s %s%s'"),
7713 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7716 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7718 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7719 i
.tm
.opcode_length
= 2;
7721 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7723 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7727 else if (i
.tm
.opcode_modifier
.isstring
)
7729 /* For the string instructions that allow a segment override
7730 on one of their operands, the default segment is ds. */
7733 else if (i
.short_form
)
7735 /* The register or float register operand is in operand
7737 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7739 /* Register goes in low 3 bits of opcode. */
7740 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7741 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7743 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7745 /* Warn about some common errors, but press on regardless.
7746 The first case can be generated by gcc (<= 2.8.1). */
7747 if (i
.operands
== 2)
7749 /* Reversed arguments on faddp, fsubp, etc. */
7750 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7751 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7752 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7756 /* Extraneous `l' suffix on fp insn. */
7757 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7758 register_prefix
, i
.op
[0].regs
->reg_name
);
7763 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7764 && i
.tm
.base_opcode
== 0x8d /* lea */
7765 && !is_any_vex_encoding(&i
.tm
))
7767 if (!quiet_warnings
)
7768 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7772 i
.prefix
[SEG_PREFIX
] = 0;
7776 /* If a segment was explicitly specified, and the specified segment
7777 is neither the default nor the one already recorded from a prefix,
7778 use an opcode prefix to select it. If we never figured out what
7779 the default segment is, then default_seg will be zero at this
7780 point, and the specified segment prefix will always be used. */
7782 && i
.seg
[0] != default_seg
7783 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7785 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7791 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7792 bfd_boolean do_sse2avx
)
7794 if (r
->reg_flags
& RegRex
)
7796 if (i
.rex
& rex_bit
)
7797 as_bad (_("same type of prefix used twice"));
7800 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7802 gas_assert (i
.vex
.register_specifier
== r
);
7803 i
.vex
.register_specifier
+= 8;
7806 if (r
->reg_flags
& RegVRex
)
7810 static const seg_entry
*
7811 build_modrm_byte (void)
7813 const seg_entry
*default_seg
= 0;
7814 unsigned int source
, dest
;
7817 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7820 unsigned int nds
, reg_slot
;
7823 dest
= i
.operands
- 1;
7826 /* There are 2 kinds of instructions:
7827 1. 5 operands: 4 register operands or 3 register operands
7828 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7829 VexW0 or VexW1. The destination must be either XMM, YMM or
7831 2. 4 operands: 4 register operands or 3 register operands
7832 plus 1 memory operand, with VexXDS. */
7833 gas_assert ((i
.reg_operands
== 4
7834 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7835 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7836 && i
.tm
.opcode_modifier
.vexw
7837 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7839 /* If VexW1 is set, the first non-immediate operand is the source and
7840 the second non-immediate one is encoded in the immediate operand. */
7841 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7843 source
= i
.imm_operands
;
7844 reg_slot
= i
.imm_operands
+ 1;
7848 source
= i
.imm_operands
+ 1;
7849 reg_slot
= i
.imm_operands
;
7852 if (i
.imm_operands
== 0)
7854 /* When there is no immediate operand, generate an 8bit
7855 immediate operand to encode the first operand. */
7856 exp
= &im_expressions
[i
.imm_operands
++];
7857 i
.op
[i
.operands
].imms
= exp
;
7858 i
.types
[i
.operands
] = imm8
;
7861 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7862 exp
->X_op
= O_constant
;
7863 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7864 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7868 gas_assert (i
.imm_operands
== 1);
7869 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7870 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7872 /* Turn on Imm8 again so that output_imm will generate it. */
7873 i
.types
[0].bitfield
.imm8
= 1;
7875 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7876 i
.op
[0].imms
->X_add_number
7877 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7878 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7881 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7882 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7887 /* i.reg_operands MUST be the number of real register operands;
7888 implicit registers do not count. If there are 3 register
7889 operands, it must be a instruction with VexNDS. For a
7890 instruction with VexNDD, the destination register is encoded
7891 in VEX prefix. If there are 4 register operands, it must be
7892 a instruction with VEX prefix and 3 sources. */
7893 if (i
.mem_operands
== 0
7894 && ((i
.reg_operands
== 2
7895 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7896 || (i
.reg_operands
== 3
7897 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7898 || (i
.reg_operands
== 4 && vex_3_sources
)))
7906 /* When there are 3 operands, one of them may be immediate,
7907 which may be the first or the last operand. Otherwise,
7908 the first operand must be shift count register (cl) or it
7909 is an instruction with VexNDS. */
7910 gas_assert (i
.imm_operands
== 1
7911 || (i
.imm_operands
== 0
7912 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7913 || (i
.types
[0].bitfield
.instance
== RegC
7914 && i
.types
[0].bitfield
.byte
))));
7915 if (operand_type_check (i
.types
[0], imm
)
7916 || (i
.types
[0].bitfield
.instance
== RegC
7917 && i
.types
[0].bitfield
.byte
))
7923 /* When there are 4 operands, the first two must be 8bit
7924 immediate operands. The source operand will be the 3rd
7927 For instructions with VexNDS, if the first operand
7928 an imm8, the source operand is the 2nd one. If the last
7929 operand is imm8, the source operand is the first one. */
7930 gas_assert ((i
.imm_operands
== 2
7931 && i
.types
[0].bitfield
.imm8
7932 && i
.types
[1].bitfield
.imm8
)
7933 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7934 && i
.imm_operands
== 1
7935 && (i
.types
[0].bitfield
.imm8
7936 || i
.types
[i
.operands
- 1].bitfield
.imm8
7938 if (i
.imm_operands
== 2)
7942 if (i
.types
[0].bitfield
.imm8
)
7949 if (is_evex_encoding (&i
.tm
))
7951 /* For EVEX instructions, when there are 5 operands, the
7952 first one must be immediate operand. If the second one
7953 is immediate operand, the source operand is the 3th
7954 one. If the last one is immediate operand, the source
7955 operand is the 2nd one. */
7956 gas_assert (i
.imm_operands
== 2
7957 && i
.tm
.opcode_modifier
.sae
7958 && operand_type_check (i
.types
[0], imm
));
7959 if (operand_type_check (i
.types
[1], imm
))
7961 else if (operand_type_check (i
.types
[4], imm
))
7975 /* RC/SAE operand could be between DEST and SRC. That happens
7976 when one operand is GPR and the other one is XMM/YMM/ZMM
7978 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7981 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7983 /* For instructions with VexNDS, the register-only source
7984 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7985 register. It is encoded in VEX prefix. */
7987 i386_operand_type op
;
7990 /* Swap two source operands if needed. */
7991 if (i
.tm
.opcode_modifier
.swapsources
)
7999 op
= i
.tm
.operand_types
[vvvv
];
8000 if ((dest
+ 1) >= i
.operands
8001 || ((op
.bitfield
.class != Reg
8002 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8003 && op
.bitfield
.class != RegSIMD
8004 && !operand_type_equal (&op
, ®mask
)))
8006 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8012 /* One of the register operands will be encoded in the i.rm.reg
8013 field, the other in the combined i.rm.mode and i.rm.regmem
8014 fields. If no form of this instruction supports a memory
8015 destination operand, then we assume the source operand may
8016 sometimes be a memory operand and so we need to store the
8017 destination in the i.rm.reg field. */
8018 if (!i
.tm
.opcode_modifier
.regmem
8019 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8021 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8022 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8023 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8024 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8028 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8029 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8030 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8031 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8033 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8035 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8038 add_prefix (LOCK_PREFIX_OPCODE
);
8042 { /* If it's not 2 reg operands... */
8047 unsigned int fake_zero_displacement
= 0;
8050 for (op
= 0; op
< i
.operands
; op
++)
8051 if (i
.flags
[op
] & Operand_Mem
)
8053 gas_assert (op
< i
.operands
);
8055 if (i
.tm
.opcode_modifier
.sib
)
8057 /* The index register of VSIB shouldn't be RegIZ. */
8058 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8059 && i
.index_reg
->reg_num
== RegIZ
)
8062 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8065 i
.sib
.base
= NO_BASE_REGISTER
;
8066 i
.sib
.scale
= i
.log2_scale_factor
;
8067 i
.types
[op
].bitfield
.disp8
= 0;
8068 i
.types
[op
].bitfield
.disp16
= 0;
8069 i
.types
[op
].bitfield
.disp64
= 0;
8070 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8072 /* Must be 32 bit */
8073 i
.types
[op
].bitfield
.disp32
= 1;
8074 i
.types
[op
].bitfield
.disp32s
= 0;
8078 i
.types
[op
].bitfield
.disp32
= 0;
8079 i
.types
[op
].bitfield
.disp32s
= 1;
8083 /* Since the mandatory SIB always has index register, so
8084 the code logic remains unchanged. The non-mandatory SIB
8085 without index register is allowed and will be handled
8089 if (i
.index_reg
->reg_num
== RegIZ
)
8090 i
.sib
.index
= NO_INDEX_REGISTER
;
8092 i
.sib
.index
= i
.index_reg
->reg_num
;
8093 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8099 if (i
.base_reg
== 0)
8102 if (!i
.disp_operands
)
8103 fake_zero_displacement
= 1;
8104 if (i
.index_reg
== 0)
8106 i386_operand_type newdisp
;
8108 /* Both check for VSIB and mandatory non-vector SIB. */
8109 gas_assert (!i
.tm
.opcode_modifier
.sib
8110 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8111 /* Operand is just <disp> */
8112 if (flag_code
== CODE_64BIT
)
8114 /* 64bit mode overwrites the 32bit absolute
8115 addressing by RIP relative addressing and
8116 absolute addressing is encoded by one of the
8117 redundant SIB forms. */
8118 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8119 i
.sib
.base
= NO_BASE_REGISTER
;
8120 i
.sib
.index
= NO_INDEX_REGISTER
;
8121 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8123 else if ((flag_code
== CODE_16BIT
)
8124 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8126 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8131 i
.rm
.regmem
= NO_BASE_REGISTER
;
8134 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8135 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8137 else if (!i
.tm
.opcode_modifier
.sib
)
8139 /* !i.base_reg && i.index_reg */
8140 if (i
.index_reg
->reg_num
== RegIZ
)
8141 i
.sib
.index
= NO_INDEX_REGISTER
;
8143 i
.sib
.index
= i
.index_reg
->reg_num
;
8144 i
.sib
.base
= NO_BASE_REGISTER
;
8145 i
.sib
.scale
= i
.log2_scale_factor
;
8146 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8147 i
.types
[op
].bitfield
.disp8
= 0;
8148 i
.types
[op
].bitfield
.disp16
= 0;
8149 i
.types
[op
].bitfield
.disp64
= 0;
8150 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8152 /* Must be 32 bit */
8153 i
.types
[op
].bitfield
.disp32
= 1;
8154 i
.types
[op
].bitfield
.disp32s
= 0;
8158 i
.types
[op
].bitfield
.disp32
= 0;
8159 i
.types
[op
].bitfield
.disp32s
= 1;
8161 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8165 /* RIP addressing for 64bit mode. */
8166 else if (i
.base_reg
->reg_num
== RegIP
)
8168 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8169 i
.rm
.regmem
= NO_BASE_REGISTER
;
8170 i
.types
[op
].bitfield
.disp8
= 0;
8171 i
.types
[op
].bitfield
.disp16
= 0;
8172 i
.types
[op
].bitfield
.disp32
= 0;
8173 i
.types
[op
].bitfield
.disp32s
= 1;
8174 i
.types
[op
].bitfield
.disp64
= 0;
8175 i
.flags
[op
] |= Operand_PCrel
;
8176 if (! i
.disp_operands
)
8177 fake_zero_displacement
= 1;
8179 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8181 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8182 switch (i
.base_reg
->reg_num
)
8185 if (i
.index_reg
== 0)
8187 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8188 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8192 if (i
.index_reg
== 0)
8195 if (operand_type_check (i
.types
[op
], disp
) == 0)
8197 /* fake (%bp) into 0(%bp) */
8198 if (i
.disp_encoding
== disp_encoding_16bit
)
8199 i
.types
[op
].bitfield
.disp16
= 1;
8201 i
.types
[op
].bitfield
.disp8
= 1;
8202 fake_zero_displacement
= 1;
8205 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8206 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8208 default: /* (%si) -> 4 or (%di) -> 5 */
8209 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8211 if (!fake_zero_displacement
8215 fake_zero_displacement
= 1;
8216 if (i
.disp_encoding
== disp_encoding_8bit
)
8217 i
.types
[op
].bitfield
.disp8
= 1;
8219 i
.types
[op
].bitfield
.disp16
= 1;
8221 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8223 else /* i.base_reg and 32/64 bit mode */
8225 if (flag_code
== CODE_64BIT
8226 && operand_type_check (i
.types
[op
], disp
))
8228 i
.types
[op
].bitfield
.disp16
= 0;
8229 i
.types
[op
].bitfield
.disp64
= 0;
8230 if (i
.prefix
[ADDR_PREFIX
] == 0)
8232 i
.types
[op
].bitfield
.disp32
= 0;
8233 i
.types
[op
].bitfield
.disp32s
= 1;
8237 i
.types
[op
].bitfield
.disp32
= 1;
8238 i
.types
[op
].bitfield
.disp32s
= 0;
8242 if (!i
.tm
.opcode_modifier
.sib
)
8243 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8244 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8246 i
.sib
.base
= i
.base_reg
->reg_num
;
8247 /* x86-64 ignores REX prefix bit here to avoid decoder
8249 if (!(i
.base_reg
->reg_flags
& RegRex
)
8250 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8251 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8253 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8255 fake_zero_displacement
= 1;
8256 if (i
.disp_encoding
== disp_encoding_32bit
)
8257 i
.types
[op
].bitfield
.disp32
= 1;
8259 i
.types
[op
].bitfield
.disp8
= 1;
8261 i
.sib
.scale
= i
.log2_scale_factor
;
8262 if (i
.index_reg
== 0)
8264 /* Only check for VSIB. */
8265 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8266 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8267 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8269 /* <disp>(%esp) becomes two byte modrm with no index
8270 register. We've already stored the code for esp
8271 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8272 Any base register besides %esp will not use the
8273 extra modrm byte. */
8274 i
.sib
.index
= NO_INDEX_REGISTER
;
8276 else if (!i
.tm
.opcode_modifier
.sib
)
8278 if (i
.index_reg
->reg_num
== RegIZ
)
8279 i
.sib
.index
= NO_INDEX_REGISTER
;
8281 i
.sib
.index
= i
.index_reg
->reg_num
;
8282 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8283 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8288 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8289 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8293 if (!fake_zero_displacement
8297 fake_zero_displacement
= 1;
8298 if (i
.disp_encoding
== disp_encoding_8bit
)
8299 i
.types
[op
].bitfield
.disp8
= 1;
8301 i
.types
[op
].bitfield
.disp32
= 1;
8303 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8307 if (fake_zero_displacement
)
8309 /* Fakes a zero displacement assuming that i.types[op]
8310 holds the correct displacement size. */
8313 gas_assert (i
.op
[op
].disps
== 0);
8314 exp
= &disp_expressions
[i
.disp_operands
++];
8315 i
.op
[op
].disps
= exp
;
8316 exp
->X_op
= O_constant
;
8317 exp
->X_add_number
= 0;
8318 exp
->X_add_symbol
= (symbolS
*) 0;
8319 exp
->X_op_symbol
= (symbolS
*) 0;
8327 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8329 if (operand_type_check (i
.types
[0], imm
))
8330 i
.vex
.register_specifier
= NULL
;
8333 /* VEX.vvvv encodes one of the sources when the first
8334 operand is not an immediate. */
8335 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8336 i
.vex
.register_specifier
= i
.op
[0].regs
;
8338 i
.vex
.register_specifier
= i
.op
[1].regs
;
8341 /* Destination is a XMM register encoded in the ModRM.reg
8343 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8344 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8347 /* ModRM.rm and VEX.B encodes the other source. */
8348 if (!i
.mem_operands
)
8352 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8353 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8355 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8357 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8361 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8363 i
.vex
.register_specifier
= i
.op
[2].regs
;
8364 if (!i
.mem_operands
)
8367 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8368 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8372 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8373 (if any) based on i.tm.extension_opcode. Again, we must be
8374 careful to make sure that segment/control/debug/test/MMX
8375 registers are coded into the i.rm.reg field. */
8376 else if (i
.reg_operands
)
8379 unsigned int vex_reg
= ~0;
8381 for (op
= 0; op
< i
.operands
; op
++)
8382 if (i
.types
[op
].bitfield
.class == Reg
8383 || i
.types
[op
].bitfield
.class == RegBND
8384 || i
.types
[op
].bitfield
.class == RegMask
8385 || i
.types
[op
].bitfield
.class == SReg
8386 || i
.types
[op
].bitfield
.class == RegCR
8387 || i
.types
[op
].bitfield
.class == RegDR
8388 || i
.types
[op
].bitfield
.class == RegTR
8389 || i
.types
[op
].bitfield
.class == RegSIMD
8390 || i
.types
[op
].bitfield
.class == RegMMX
)
8395 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8397 /* For instructions with VexNDS, the register-only
8398 source operand is encoded in VEX prefix. */
8399 gas_assert (mem
!= (unsigned int) ~0);
8404 gas_assert (op
< i
.operands
);
8408 /* Check register-only source operand when two source
8409 operands are swapped. */
8410 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8411 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8415 gas_assert (mem
== (vex_reg
+ 1)
8416 && op
< i
.operands
);
8421 gas_assert (vex_reg
< i
.operands
);
8425 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8427 /* For instructions with VexNDD, the register destination
8428 is encoded in VEX prefix. */
8429 if (i
.mem_operands
== 0)
8431 /* There is no memory operand. */
8432 gas_assert ((op
+ 2) == i
.operands
);
8437 /* There are only 2 non-immediate operands. */
8438 gas_assert (op
< i
.imm_operands
+ 2
8439 && i
.operands
== i
.imm_operands
+ 2);
8440 vex_reg
= i
.imm_operands
+ 1;
8444 gas_assert (op
< i
.operands
);
8446 if (vex_reg
!= (unsigned int) ~0)
8448 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8450 if ((type
->bitfield
.class != Reg
8451 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8452 && type
->bitfield
.class != RegSIMD
8453 && !operand_type_equal (type
, ®mask
))
8456 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8459 /* Don't set OP operand twice. */
8462 /* If there is an extension opcode to put here, the
8463 register number must be put into the regmem field. */
8464 if (i
.tm
.extension_opcode
!= None
)
8466 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8467 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8468 i
.tm
.opcode_modifier
.sse2avx
);
8472 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8473 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8474 i
.tm
.opcode_modifier
.sse2avx
);
8478 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8479 must set it to 3 to indicate this is a register operand
8480 in the regmem field. */
8481 if (!i
.mem_operands
)
8485 /* Fill in i.rm.reg field with extension opcode (if any). */
8486 if (i
.tm
.extension_opcode
!= None
)
8487 i
.rm
.reg
= i
.tm
.extension_opcode
;
8493 frag_opcode_byte (unsigned char byte
)
8495 if (now_seg
!= absolute_section
)
8496 FRAG_APPEND_1_CHAR (byte
);
8498 ++abs_section_offset
;
8502 flip_code16 (unsigned int code16
)
8504 gas_assert (i
.tm
.operands
== 1);
8506 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8507 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8508 || i
.tm
.operand_types
[0].bitfield
.disp32s
8509 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8514 output_branch (void)
8520 relax_substateT subtype
;
8524 if (now_seg
== absolute_section
)
8526 as_bad (_("relaxable branches not supported in absolute section"));
8530 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8531 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8534 if (i
.prefix
[DATA_PREFIX
] != 0)
8538 code16
^= flip_code16(code16
);
8540 /* Pentium4 branch hints. */
8541 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8542 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8547 if (i
.prefix
[REX_PREFIX
] != 0)
8553 /* BND prefixed jump. */
8554 if (i
.prefix
[BND_PREFIX
] != 0)
8560 if (i
.prefixes
!= 0)
8561 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8563 /* It's always a symbol; End frag & setup for relax.
8564 Make sure there is enough room in this frag for the largest
8565 instruction we may generate in md_convert_frag. This is 2
8566 bytes for the opcode and room for the prefix and largest
8568 frag_grow (prefix
+ 2 + 4);
8569 /* Prefix and 1 opcode byte go in fr_fix. */
8570 p
= frag_more (prefix
+ 1);
8571 if (i
.prefix
[DATA_PREFIX
] != 0)
8572 *p
++ = DATA_PREFIX_OPCODE
;
8573 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8574 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8575 *p
++ = i
.prefix
[SEG_PREFIX
];
8576 if (i
.prefix
[BND_PREFIX
] != 0)
8577 *p
++ = BND_PREFIX_OPCODE
;
8578 if (i
.prefix
[REX_PREFIX
] != 0)
8579 *p
++ = i
.prefix
[REX_PREFIX
];
8580 *p
= i
.tm
.base_opcode
;
8582 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8583 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8584 else if (cpu_arch_flags
.bitfield
.cpui386
)
8585 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8587 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8590 sym
= i
.op
[0].disps
->X_add_symbol
;
8591 off
= i
.op
[0].disps
->X_add_number
;
8593 if (i
.op
[0].disps
->X_op
!= O_constant
8594 && i
.op
[0].disps
->X_op
!= O_symbol
)
8596 /* Handle complex expressions. */
8597 sym
= make_expr_symbol (i
.op
[0].disps
);
8601 /* 1 possible extra opcode + 4 byte displacement go in var part.
8602 Pass reloc in fr_var. */
8603 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8607 /* Return TRUE iff PLT32 relocation should be used for branching to
8611 need_plt32_p (symbolS
*s
)
8613 /* PLT32 relocation is ELF only. */
8618 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8619 krtld support it. */
8623 /* Since there is no need to prepare for PLT branch on x86-64, we
8624 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8625 be used as a marker for 32-bit PC-relative branches. */
8629 /* Weak or undefined symbol need PLT32 relocation. */
8630 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8633 /* Non-global symbol doesn't need PLT32 relocation. */
8634 if (! S_IS_EXTERNAL (s
))
8637 /* Other global symbols need PLT32 relocation. NB: Symbol with
8638 non-default visibilities are treated as normal global symbol
8639 so that PLT32 relocation can be used as a marker for 32-bit
8640 PC-relative branches. It is useful for linker relaxation. */
8651 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8653 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8655 /* This is a loop or jecxz type instruction. */
8657 if (i
.prefix
[ADDR_PREFIX
] != 0)
8659 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8662 /* Pentium4 branch hints. */
8663 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8664 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8666 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8675 if (flag_code
== CODE_16BIT
)
8678 if (i
.prefix
[DATA_PREFIX
] != 0)
8680 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8682 code16
^= flip_code16(code16
);
8690 /* BND prefixed jump. */
8691 if (i
.prefix
[BND_PREFIX
] != 0)
8693 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8697 if (i
.prefix
[REX_PREFIX
] != 0)
8699 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8703 if (i
.prefixes
!= 0)
8704 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8706 if (now_seg
== absolute_section
)
8708 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8712 p
= frag_more (i
.tm
.opcode_length
+ size
);
8713 switch (i
.tm
.opcode_length
)
8716 *p
++ = i
.tm
.base_opcode
>> 8;
8719 *p
++ = i
.tm
.base_opcode
;
8725 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8727 && jump_reloc
== NO_RELOC
8728 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8729 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8732 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8734 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8735 i
.op
[0].disps
, 1, jump_reloc
);
8737 /* All jumps handled here are signed, but don't use a signed limit
8738 check for 32 and 16 bit jumps as we want to allow wrap around at
8739 4G and 64k respectively. */
8741 fixP
->fx_signed
= 1;
8745 output_interseg_jump (void)
8753 if (flag_code
== CODE_16BIT
)
8757 if (i
.prefix
[DATA_PREFIX
] != 0)
8764 gas_assert (!i
.prefix
[REX_PREFIX
]);
8770 if (i
.prefixes
!= 0)
8771 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8773 if (now_seg
== absolute_section
)
8775 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8779 /* 1 opcode; 2 segment; offset */
8780 p
= frag_more (prefix
+ 1 + 2 + size
);
8782 if (i
.prefix
[DATA_PREFIX
] != 0)
8783 *p
++ = DATA_PREFIX_OPCODE
;
8785 if (i
.prefix
[REX_PREFIX
] != 0)
8786 *p
++ = i
.prefix
[REX_PREFIX
];
8788 *p
++ = i
.tm
.base_opcode
;
8789 if (i
.op
[1].imms
->X_op
== O_constant
)
8791 offsetT n
= i
.op
[1].imms
->X_add_number
;
8794 && !fits_in_unsigned_word (n
)
8795 && !fits_in_signed_word (n
))
8797 as_bad (_("16-bit jump out of range"));
8800 md_number_to_chars (p
, n
, size
);
8803 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8804 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8807 if (i
.op
[0].imms
->X_op
== O_constant
)
8808 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8810 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8811 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8819 asection
*seg
= now_seg
;
8820 subsegT subseg
= now_subseg
;
8822 unsigned int alignment
, align_size_1
;
8823 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8824 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8825 unsigned int padding
;
8827 if (!IS_ELF
|| !x86_used_note
)
8830 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8832 /* The .note.gnu.property section layout:
8834 Field Length Contents
8837 n_descsz 4 The note descriptor size
8838 n_type 4 NT_GNU_PROPERTY_TYPE_0
8840 n_desc n_descsz The program property array
8844 /* Create the .note.gnu.property section. */
8845 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8846 bfd_set_section_flags (sec
,
8853 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8864 bfd_set_section_alignment (sec
, alignment
);
8865 elf_section_type (sec
) = SHT_NOTE
;
8867 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8869 isa_1_descsz_raw
= 4 + 4 + 4;
8870 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8871 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8873 feature_2_descsz_raw
= isa_1_descsz
;
8874 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8876 feature_2_descsz_raw
+= 4 + 4 + 4;
8877 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8878 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8881 descsz
= feature_2_descsz
;
8882 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8883 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8885 /* Write n_namsz. */
8886 md_number_to_chars (p
, (valueT
) 4, 4);
8888 /* Write n_descsz. */
8889 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8892 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8895 memcpy (p
+ 4 * 3, "GNU", 4);
8897 /* Write 4-byte type. */
8898 md_number_to_chars (p
+ 4 * 4,
8899 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8901 /* Write 4-byte data size. */
8902 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8904 /* Write 4-byte data. */
8905 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8907 /* Zero out paddings. */
8908 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8910 memset (p
+ 4 * 7, 0, padding
);
8912 /* Write 4-byte type. */
8913 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8914 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8916 /* Write 4-byte data size. */
8917 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8919 /* Write 4-byte data. */
8920 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8921 (valueT
) x86_feature_2_used
, 4);
8923 /* Zero out paddings. */
8924 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8926 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8928 /* We probably can't restore the current segment, for there likely
8931 subseg_set (seg
, subseg
);
8936 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8937 const char *frag_now_ptr
)
8939 unsigned int len
= 0;
8941 if (start_frag
!= frag_now
)
8943 const fragS
*fr
= start_frag
;
8948 } while (fr
&& fr
!= frag_now
);
8951 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8954 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8955 be macro-fused with conditional jumps.
8956 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8957 or is one of the following format:
8970 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8972 /* No RIP address. */
8973 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8976 /* No VEX/EVEX encoding. */
8977 if (is_any_vex_encoding (&i
.tm
))
8980 /* add, sub without add/sub m, imm. */
8981 if (i
.tm
.base_opcode
<= 5
8982 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8983 || ((i
.tm
.base_opcode
| 3) == 0x83
8984 && (i
.tm
.extension_opcode
== 0x5
8985 || i
.tm
.extension_opcode
== 0x0)))
8987 *mf_cmp_p
= mf_cmp_alu_cmp
;
8988 return !(i
.mem_operands
&& i
.imm_operands
);
8991 /* and without and m, imm. */
8992 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8993 || ((i
.tm
.base_opcode
| 3) == 0x83
8994 && i
.tm
.extension_opcode
== 0x4))
8996 *mf_cmp_p
= mf_cmp_test_and
;
8997 return !(i
.mem_operands
&& i
.imm_operands
);
9000 /* test without test m imm. */
9001 if ((i
.tm
.base_opcode
| 1) == 0x85
9002 || (i
.tm
.base_opcode
| 1) == 0xa9
9003 || ((i
.tm
.base_opcode
| 1) == 0xf7
9004 && i
.tm
.extension_opcode
== 0))
9006 *mf_cmp_p
= mf_cmp_test_and
;
9007 return !(i
.mem_operands
&& i
.imm_operands
);
9010 /* cmp without cmp m, imm. */
9011 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9012 || ((i
.tm
.base_opcode
| 3) == 0x83
9013 && (i
.tm
.extension_opcode
== 0x7)))
9015 *mf_cmp_p
= mf_cmp_alu_cmp
;
9016 return !(i
.mem_operands
&& i
.imm_operands
);
9019 /* inc, dec without inc/dec m. */
9020 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9021 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9022 || ((i
.tm
.base_opcode
| 1) == 0xff
9023 && i
.tm
.extension_opcode
<= 0x1))
9025 *mf_cmp_p
= mf_cmp_incdec
;
9026 return !i
.mem_operands
;
9032 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9035 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9037 /* NB: Don't work with COND_JUMP86 without i386. */
9038 if (!align_branch_power
9039 || now_seg
== absolute_section
9040 || !cpu_arch_flags
.bitfield
.cpui386
9041 || !(align_branch
& align_branch_fused_bit
))
9044 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9046 if (last_insn
.kind
== last_insn_other
9047 || last_insn
.seg
!= now_seg
)
9050 as_warn_where (last_insn
.file
, last_insn
.line
,
9051 _("`%s` skips -malign-branch-boundary on `%s`"),
9052 last_insn
.name
, i
.tm
.name
);
9058 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9061 add_branch_prefix_frag_p (void)
9063 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9064 to PadLock instructions since they include prefixes in opcode. */
9065 if (!align_branch_power
9066 || !align_branch_prefix_size
9067 || now_seg
== absolute_section
9068 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9069 || !cpu_arch_flags
.bitfield
.cpui386
)
9072 /* Don't add prefix if it is a prefix or there is no operand in case
9073 that segment prefix is special. */
9074 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9077 if (last_insn
.kind
== last_insn_other
9078 || last_insn
.seg
!= now_seg
)
9082 as_warn_where (last_insn
.file
, last_insn
.line
,
9083 _("`%s` skips -malign-branch-boundary on `%s`"),
9084 last_insn
.name
, i
.tm
.name
);
9089 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9092 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9093 enum mf_jcc_kind
*mf_jcc_p
)
9097 /* NB: Don't work with COND_JUMP86 without i386. */
9098 if (!align_branch_power
9099 || now_seg
== absolute_section
9100 || !cpu_arch_flags
.bitfield
.cpui386
)
9105 /* Check for jcc and direct jmp. */
9106 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9108 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9110 *branch_p
= align_branch_jmp
;
9111 add_padding
= align_branch
& align_branch_jmp_bit
;
9115 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9116 igore the lowest bit. */
9117 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9118 *branch_p
= align_branch_jcc
;
9119 if ((align_branch
& align_branch_jcc_bit
))
9123 else if (is_any_vex_encoding (&i
.tm
))
9125 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9128 *branch_p
= align_branch_ret
;
9129 if ((align_branch
& align_branch_ret_bit
))
9134 /* Check for indirect jmp, direct and indirect calls. */
9135 if (i
.tm
.base_opcode
== 0xe8)
9138 *branch_p
= align_branch_call
;
9139 if ((align_branch
& align_branch_call_bit
))
9142 else if (i
.tm
.base_opcode
== 0xff
9143 && (i
.tm
.extension_opcode
== 2
9144 || i
.tm
.extension_opcode
== 4))
9146 /* Indirect call and jmp. */
9147 *branch_p
= align_branch_indirect
;
9148 if ((align_branch
& align_branch_indirect_bit
))
9155 && (i
.op
[0].disps
->X_op
== O_symbol
9156 || (i
.op
[0].disps
->X_op
== O_subtract
9157 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9159 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9160 /* No padding to call to global or undefined tls_get_addr. */
9161 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9162 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9168 && last_insn
.kind
!= last_insn_other
9169 && last_insn
.seg
== now_seg
)
9172 as_warn_where (last_insn
.file
, last_insn
.line
,
9173 _("`%s` skips -malign-branch-boundary on `%s`"),
9174 last_insn
.name
, i
.tm
.name
);
9184 fragS
*insn_start_frag
;
9185 offsetT insn_start_off
;
9186 fragS
*fragP
= NULL
;
9187 enum align_branch_kind branch
= align_branch_none
;
9188 /* The initializer is arbitrary just to avoid uninitialized error.
9189 it's actually either assigned in add_branch_padding_frag_p
9190 or never be used. */
9191 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9194 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9196 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9197 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9198 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9200 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9201 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9202 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9203 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9204 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9205 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9206 /* LAHF-SAHF insns in 64-bit mode. */
9207 || (flag_code
== CODE_64BIT
9208 && (i
.tm
.base_opcode
| 1) == 0x9f))
9209 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9210 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9211 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9212 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9213 CpuAVX512DQ, LPW, TBM and AMX. */
9214 || (i
.tm
.opcode_modifier
.vex
9215 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9216 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9217 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9218 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9219 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9220 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9221 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9222 || i
.tm
.cpu_flags
.bitfield
.cpufma
9223 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9224 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9225 || i
.tm
.cpu_flags
.bitfield
.cpuxsave
9226 || i
.tm
.cpu_flags
.bitfield
.cpuxsavec
9227 || i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
9228 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
)
9229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9230 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9231 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9232 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9233 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9234 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9236 || (i
.tm
.opcode_modifier
.evex
9237 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9238 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9239 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9242 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9243 || i
.tm
.cpu_flags
.bitfield
.cpu287
9244 || i
.tm
.cpu_flags
.bitfield
.cpu387
9245 || i
.tm
.cpu_flags
.bitfield
.cpu687
9246 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9247 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9248 if ((i
.xstate
& xstate_mmx
)
9249 || i
.tm
.base_opcode
== 0xf77 /* emms */
9250 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9251 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9254 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9255 i
.xstate
|= xstate_zmm
;
9256 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9257 i
.xstate
|= xstate_ymm
;
9258 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9259 i
.xstate
|= xstate_xmm
;
9261 if ((i
.xstate
& xstate_xmm
)
9262 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9263 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9264 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9265 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9266 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9267 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9268 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9269 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9270 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9271 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9272 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9273 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9274 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9275 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9276 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9277 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9278 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9282 /* Tie dwarf2 debug info to the address at the start of the insn.
9283 We can't do this after the insn has been output as the current
9284 frag may have been closed off. eg. by frag_var. */
9285 dwarf2_emit_insn (0);
9287 insn_start_frag
= frag_now
;
9288 insn_start_off
= frag_now_fix ();
9290 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9293 /* Branch can be 8 bytes. Leave some room for prefixes. */
9294 unsigned int max_branch_padding_size
= 14;
9296 /* Align section to boundary. */
9297 record_alignment (now_seg
, align_branch_power
);
9299 /* Make room for padding. */
9300 frag_grow (max_branch_padding_size
);
9302 /* Start of the padding. */
9307 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9308 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9311 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9312 fragP
->tc_frag_data
.branch_type
= branch
;
9313 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9317 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9319 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9320 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9322 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9323 output_interseg_jump ();
9326 /* Output normal instructions here. */
9330 enum mf_cmp_kind mf_cmp
;
9333 && (i
.tm
.base_opcode
== 0xfaee8
9334 || i
.tm
.base_opcode
== 0xfaef0
9335 || i
.tm
.base_opcode
== 0xfaef8))
9337 /* Encode lfence, mfence, and sfence as
9338 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9339 if (now_seg
!= absolute_section
)
9341 offsetT val
= 0x240483f0ULL
;
9344 md_number_to_chars (p
, val
, 5);
9347 abs_section_offset
+= 5;
9351 /* Some processors fail on LOCK prefix. This options makes
9352 assembler ignore LOCK prefix and serves as a workaround. */
9353 if (omit_lock_prefix
)
9355 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9357 i
.prefix
[LOCK_PREFIX
] = 0;
9361 /* Skip if this is a branch. */
9363 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9365 /* Make room for padding. */
9366 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9371 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9372 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9375 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9376 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9377 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9379 else if (add_branch_prefix_frag_p ())
9381 unsigned int max_prefix_size
= align_branch_prefix_size
;
9383 /* Make room for padding. */
9384 frag_grow (max_prefix_size
);
9389 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9390 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9393 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9396 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9397 don't need the explicit prefix. */
9398 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9400 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9409 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9410 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9414 switch (i
.tm
.opcode_length
)
9421 /* Check for pseudo prefixes. */
9422 as_bad_where (insn_start_frag
->fr_file
,
9423 insn_start_frag
->fr_line
,
9424 _("pseudo prefix without instruction"));
9434 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9435 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9436 R_X86_64_GOTTPOFF relocation so that linker can safely
9437 perform IE->LE optimization. A dummy REX_OPCODE prefix
9438 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9439 relocation for GDesc -> IE/LE optimization. */
9440 if (x86_elf_abi
== X86_64_X32_ABI
9442 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9443 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9444 && i
.prefix
[REX_PREFIX
] == 0)
9445 add_prefix (REX_OPCODE
);
9448 /* The prefix bytes. */
9449 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9451 frag_opcode_byte (*q
);
9455 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9461 frag_opcode_byte (*q
);
9464 /* There should be no other prefixes for instructions
9469 /* For EVEX instructions i.vrex should become 0 after
9470 build_evex_prefix. For VEX instructions upper 16 registers
9471 aren't available, so VREX should be 0. */
9474 /* Now the VEX prefix. */
9475 if (now_seg
!= absolute_section
)
9477 p
= frag_more (i
.vex
.length
);
9478 for (j
= 0; j
< i
.vex
.length
; j
++)
9479 p
[j
] = i
.vex
.bytes
[j
];
9482 abs_section_offset
+= i
.vex
.length
;
9485 /* Now the opcode; be careful about word order here! */
9486 if (now_seg
== absolute_section
)
9487 abs_section_offset
+= i
.tm
.opcode_length
;
9488 else if (i
.tm
.opcode_length
== 1)
9490 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9494 switch (i
.tm
.opcode_length
)
9498 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9499 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9503 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9513 /* Put out high byte first: can't use md_number_to_chars! */
9514 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9515 *p
= i
.tm
.base_opcode
& 0xff;
9518 /* Now the modrm byte and sib byte (if present). */
9519 if (i
.tm
.opcode_modifier
.modrm
)
9521 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9523 | (i
.rm
.mode
<< 6));
9524 /* If i.rm.regmem == ESP (4)
9525 && i.rm.mode != (Register mode)
9527 ==> need second modrm byte. */
9528 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9530 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9531 frag_opcode_byte ((i
.sib
.base
<< 0)
9532 | (i
.sib
.index
<< 3)
9533 | (i
.sib
.scale
<< 6));
9536 if (i
.disp_operands
)
9537 output_disp (insn_start_frag
, insn_start_off
);
9540 output_imm (insn_start_frag
, insn_start_off
);
9543 * frag_now_fix () returning plain abs_section_offset when we're in the
9544 * absolute section, and abs_section_offset not getting updated as data
9545 * gets added to the frag breaks the logic below.
9547 if (now_seg
!= absolute_section
)
9549 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9551 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9555 /* NB: Don't add prefix with GOTPC relocation since
9556 output_disp() above depends on the fixed encoding
9557 length. Can't add prefix with TLS relocation since
9558 it breaks TLS linker optimization. */
9559 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9560 /* Prefix count on the current instruction. */
9561 unsigned int count
= i
.vex
.length
;
9563 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9564 /* REX byte is encoded in VEX/EVEX prefix. */
9565 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9568 /* Count prefixes for extended opcode maps. */
9570 switch (i
.tm
.opcode_length
)
9573 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9576 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9588 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9597 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9600 /* Set the maximum prefix size in BRANCH_PREFIX
9602 if (fragP
->tc_frag_data
.max_bytes
> max
)
9603 fragP
->tc_frag_data
.max_bytes
= max
;
9604 if (fragP
->tc_frag_data
.max_bytes
> count
)
9605 fragP
->tc_frag_data
.max_bytes
-= count
;
9607 fragP
->tc_frag_data
.max_bytes
= 0;
9611 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9613 unsigned int max_prefix_size
;
9614 if (align_branch_prefix_size
> max
)
9615 max_prefix_size
= max
;
9617 max_prefix_size
= align_branch_prefix_size
;
9618 if (max_prefix_size
> count
)
9619 fragP
->tc_frag_data
.max_prefix_length
9620 = max_prefix_size
- count
;
9623 /* Use existing segment prefix if possible. Use CS
9624 segment prefix in 64-bit mode. In 32-bit mode, use SS
9625 segment prefix with ESP/EBP base register and use DS
9626 segment prefix without ESP/EBP base register. */
9627 if (i
.prefix
[SEG_PREFIX
])
9628 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9629 else if (flag_code
== CODE_64BIT
)
9630 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9632 && (i
.base_reg
->reg_num
== 4
9633 || i
.base_reg
->reg_num
== 5))
9634 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9636 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9641 /* NB: Don't work with COND_JUMP86 without i386. */
9642 if (align_branch_power
9643 && now_seg
!= absolute_section
9644 && cpu_arch_flags
.bitfield
.cpui386
)
9646 /* Terminate each frag so that we can add prefix and check for
9648 frag_wane (frag_now
);
9655 pi ("" /*line*/, &i
);
9657 #endif /* DEBUG386 */
9660 /* Return the size of the displacement operand N. */
9663 disp_size (unsigned int n
)
9667 if (i
.types
[n
].bitfield
.disp64
)
9669 else if (i
.types
[n
].bitfield
.disp8
)
9671 else if (i
.types
[n
].bitfield
.disp16
)
9676 /* Return the size of the immediate operand N. */
9679 imm_size (unsigned int n
)
9682 if (i
.types
[n
].bitfield
.imm64
)
9684 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9686 else if (i
.types
[n
].bitfield
.imm16
)
9692 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9697 for (n
= 0; n
< i
.operands
; n
++)
9699 if (operand_type_check (i
.types
[n
], disp
))
9701 int size
= disp_size (n
);
9703 if (now_seg
== absolute_section
)
9704 abs_section_offset
+= size
;
9705 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9707 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9709 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9711 p
= frag_more (size
);
9712 md_number_to_chars (p
, val
, size
);
9716 enum bfd_reloc_code_real reloc_type
;
9717 int sign
= i
.types
[n
].bitfield
.disp32s
;
9718 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9721 /* We can't have 8 bit displacement here. */
9722 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9724 /* The PC relative address is computed relative
9725 to the instruction boundary, so in case immediate
9726 fields follows, we need to adjust the value. */
9727 if (pcrel
&& i
.imm_operands
)
9732 for (n1
= 0; n1
< i
.operands
; n1
++)
9733 if (operand_type_check (i
.types
[n1
], imm
))
9735 /* Only one immediate is allowed for PC
9736 relative address. */
9737 gas_assert (sz
== 0);
9739 i
.op
[n
].disps
->X_add_number
-= sz
;
9741 /* We should find the immediate. */
9742 gas_assert (sz
!= 0);
9745 p
= frag_more (size
);
9746 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9748 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9749 && (((reloc_type
== BFD_RELOC_32
9750 || reloc_type
== BFD_RELOC_X86_64_32S
9751 || (reloc_type
== BFD_RELOC_64
9753 && (i
.op
[n
].disps
->X_op
== O_symbol
9754 || (i
.op
[n
].disps
->X_op
== O_add
9755 && ((symbol_get_value_expression
9756 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9758 || reloc_type
== BFD_RELOC_32_PCREL
))
9762 reloc_type
= BFD_RELOC_386_GOTPC
;
9763 i
.has_gotpc_tls_reloc
= TRUE
;
9764 i
.op
[n
].imms
->X_add_number
+=
9765 encoding_length (insn_start_frag
, insn_start_off
, p
);
9767 else if (reloc_type
== BFD_RELOC_64
)
9768 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9770 /* Don't do the adjustment for x86-64, as there
9771 the pcrel addressing is relative to the _next_
9772 insn, and that is taken care of in other code. */
9773 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9775 else if (align_branch_power
)
9779 case BFD_RELOC_386_TLS_GD
:
9780 case BFD_RELOC_386_TLS_LDM
:
9781 case BFD_RELOC_386_TLS_IE
:
9782 case BFD_RELOC_386_TLS_IE_32
:
9783 case BFD_RELOC_386_TLS_GOTIE
:
9784 case BFD_RELOC_386_TLS_GOTDESC
:
9785 case BFD_RELOC_386_TLS_DESC_CALL
:
9786 case BFD_RELOC_X86_64_TLSGD
:
9787 case BFD_RELOC_X86_64_TLSLD
:
9788 case BFD_RELOC_X86_64_GOTTPOFF
:
9789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9790 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9791 i
.has_gotpc_tls_reloc
= TRUE
;
9796 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9797 size
, i
.op
[n
].disps
, pcrel
,
9799 /* Check for "call/jmp *mem", "mov mem, %reg",
9800 "test %reg, mem" and "binop mem, %reg" where binop
9801 is one of adc, add, and, cmp, or, sbb, sub, xor
9802 instructions without data prefix. Always generate
9803 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9804 if (i
.prefix
[DATA_PREFIX
] == 0
9805 && (generate_relax_relocations
9808 && i
.rm
.regmem
== 5))
9810 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9811 && !is_any_vex_encoding(&i
.tm
)
9812 && ((i
.operands
== 1
9813 && i
.tm
.base_opcode
== 0xff
9814 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9816 && (i
.tm
.base_opcode
== 0x8b
9817 || i
.tm
.base_opcode
== 0x85
9818 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9822 fixP
->fx_tcbit
= i
.rex
!= 0;
9824 && (i
.base_reg
->reg_num
== RegIP
))
9825 fixP
->fx_tcbit2
= 1;
9828 fixP
->fx_tcbit2
= 1;
9836 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9841 for (n
= 0; n
< i
.operands
; n
++)
9843 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9844 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9847 if (operand_type_check (i
.types
[n
], imm
))
9849 int size
= imm_size (n
);
9851 if (now_seg
== absolute_section
)
9852 abs_section_offset
+= size
;
9853 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9857 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9859 p
= frag_more (size
);
9860 md_number_to_chars (p
, val
, size
);
9864 /* Not absolute_section.
9865 Need a 32-bit fixup (don't support 8bit
9866 non-absolute imms). Try to support other
9868 enum bfd_reloc_code_real reloc_type
;
9871 if (i
.types
[n
].bitfield
.imm32s
9872 && (i
.suffix
== QWORD_MNEM_SUFFIX
9873 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9878 p
= frag_more (size
);
9879 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9881 /* This is tough to explain. We end up with this one if we
9882 * have operands that look like
9883 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9884 * obtain the absolute address of the GOT, and it is strongly
9885 * preferable from a performance point of view to avoid using
9886 * a runtime relocation for this. The actual sequence of
9887 * instructions often look something like:
9892 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9894 * The call and pop essentially return the absolute address
9895 * of the label .L66 and store it in %ebx. The linker itself
9896 * will ultimately change the first operand of the addl so
9897 * that %ebx points to the GOT, but to keep things simple, the
9898 * .o file must have this operand set so that it generates not
9899 * the absolute address of .L66, but the absolute address of
9900 * itself. This allows the linker itself simply treat a GOTPC
9901 * relocation as asking for a pcrel offset to the GOT to be
9902 * added in, and the addend of the relocation is stored in the
9903 * operand field for the instruction itself.
9905 * Our job here is to fix the operand so that it would add
9906 * the correct offset so that %ebx would point to itself. The
9907 * thing that is tricky is that .-.L66 will point to the
9908 * beginning of the instruction, so we need to further modify
9909 * the operand so that it will point to itself. There are
9910 * other cases where you have something like:
9912 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9914 * and here no correction would be required. Internally in
9915 * the assembler we treat operands of this form as not being
9916 * pcrel since the '.' is explicitly mentioned, and I wonder
9917 * whether it would simplify matters to do it this way. Who
9918 * knows. In earlier versions of the PIC patches, the
9919 * pcrel_adjust field was used to store the correction, but
9920 * since the expression is not pcrel, I felt it would be
9921 * confusing to do it this way. */
9923 if ((reloc_type
== BFD_RELOC_32
9924 || reloc_type
== BFD_RELOC_X86_64_32S
9925 || reloc_type
== BFD_RELOC_64
)
9927 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9928 && (i
.op
[n
].imms
->X_op
== O_symbol
9929 || (i
.op
[n
].imms
->X_op
== O_add
9930 && ((symbol_get_value_expression
9931 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9935 reloc_type
= BFD_RELOC_386_GOTPC
;
9937 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9939 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9940 i
.has_gotpc_tls_reloc
= TRUE
;
9941 i
.op
[n
].imms
->X_add_number
+=
9942 encoding_length (insn_start_frag
, insn_start_off
, p
);
9944 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9945 i
.op
[n
].imms
, 0, reloc_type
);
9951 /* x86_cons_fix_new is called via the expression parsing code when a
9952 reloc is needed. We use this hook to get the correct .got reloc. */
9953 static int cons_sign
= -1;
9956 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9957 expressionS
*exp
, bfd_reloc_code_real_type r
)
9959 r
= reloc (len
, 0, cons_sign
, r
);
9962 if (exp
->X_op
== O_secrel
)
9964 exp
->X_op
= O_symbol
;
9965 r
= BFD_RELOC_32_SECREL
;
9969 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9972 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9973 purpose of the `.dc.a' internal pseudo-op. */
9976 x86_address_bytes (void)
9978 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9980 return stdoutput
->arch_info
->bits_per_address
/ 8;
9983 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9985 # define lex_got(reloc, adjust, types) NULL
9987 /* Parse operands of the form
9988 <symbol>@GOTOFF+<nnn>
9989 and similar .plt or .got references.
9991 If we find one, set up the correct relocation in RELOC and copy the
9992 input string, minus the `@GOTOFF' into a malloc'd buffer for
9993 parsing by the calling routine. Return this buffer, and if ADJUST
9994 is non-null set it to the length of the string we removed from the
9995 input line. Otherwise return NULL. */
9997 lex_got (enum bfd_reloc_code_real
*rel
,
9999 i386_operand_type
*types
)
10001 /* Some of the relocations depend on the size of what field is to
10002 be relocated. But in our callers i386_immediate and i386_displacement
10003 we don't yet know the operand size (this will be set by insn
10004 matching). Hence we record the word32 relocation here,
10005 and adjust the reloc according to the real size in reloc(). */
10006 static const struct {
10009 const enum bfd_reloc_code_real rel
[2];
10010 const i386_operand_type types64
;
10012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10013 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10014 BFD_RELOC_SIZE32
},
10015 OPERAND_TYPE_IMM32_64
},
10017 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10018 BFD_RELOC_X86_64_PLTOFF64
},
10019 OPERAND_TYPE_IMM64
},
10020 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10021 BFD_RELOC_X86_64_PLT32
},
10022 OPERAND_TYPE_IMM32_32S_DISP32
},
10023 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10024 BFD_RELOC_X86_64_GOTPLT64
},
10025 OPERAND_TYPE_IMM64_DISP64
},
10026 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10027 BFD_RELOC_X86_64_GOTOFF64
},
10028 OPERAND_TYPE_IMM64_DISP64
},
10029 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10030 BFD_RELOC_X86_64_GOTPCREL
},
10031 OPERAND_TYPE_IMM32_32S_DISP32
},
10032 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10033 BFD_RELOC_X86_64_TLSGD
},
10034 OPERAND_TYPE_IMM32_32S_DISP32
},
10035 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10036 _dummy_first_bfd_reloc_code_real
},
10037 OPERAND_TYPE_NONE
},
10038 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10039 BFD_RELOC_X86_64_TLSLD
},
10040 OPERAND_TYPE_IMM32_32S_DISP32
},
10041 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10042 BFD_RELOC_X86_64_GOTTPOFF
},
10043 OPERAND_TYPE_IMM32_32S_DISP32
},
10044 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10045 BFD_RELOC_X86_64_TPOFF32
},
10046 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10047 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10048 _dummy_first_bfd_reloc_code_real
},
10049 OPERAND_TYPE_NONE
},
10050 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10051 BFD_RELOC_X86_64_DTPOFF32
},
10052 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10053 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10054 _dummy_first_bfd_reloc_code_real
},
10055 OPERAND_TYPE_NONE
},
10056 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10057 _dummy_first_bfd_reloc_code_real
},
10058 OPERAND_TYPE_NONE
},
10059 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10060 BFD_RELOC_X86_64_GOT32
},
10061 OPERAND_TYPE_IMM32_32S_64_DISP32
},
10062 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10063 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10064 OPERAND_TYPE_IMM32_32S_DISP32
},
10065 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10066 BFD_RELOC_X86_64_TLSDESC_CALL
},
10067 OPERAND_TYPE_IMM32_32S_DISP32
},
10072 #if defined (OBJ_MAYBE_ELF)
10077 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10078 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10081 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10083 int len
= gotrel
[j
].len
;
10084 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10086 if (gotrel
[j
].rel
[object_64bit
] != 0)
10089 char *tmpbuf
, *past_reloc
;
10091 *rel
= gotrel
[j
].rel
[object_64bit
];
10095 if (flag_code
!= CODE_64BIT
)
10097 types
->bitfield
.imm32
= 1;
10098 types
->bitfield
.disp32
= 1;
10101 *types
= gotrel
[j
].types64
;
10104 if (j
!= 0 && GOT_symbol
== NULL
)
10105 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10107 /* The length of the first part of our input line. */
10108 first
= cp
- input_line_pointer
;
10110 /* The second part goes from after the reloc token until
10111 (and including) an end_of_line char or comma. */
10112 past_reloc
= cp
+ 1 + len
;
10114 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10116 second
= cp
+ 1 - past_reloc
;
10118 /* Allocate and copy string. The trailing NUL shouldn't
10119 be necessary, but be safe. */
10120 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10121 memcpy (tmpbuf
, input_line_pointer
, first
);
10122 if (second
!= 0 && *past_reloc
!= ' ')
10123 /* Replace the relocation token with ' ', so that
10124 errors like foo@GOTOFF1 will be detected. */
10125 tmpbuf
[first
++] = ' ';
10127 /* Increment length by 1 if the relocation token is
10132 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10133 tmpbuf
[first
+ second
] = '\0';
10137 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10138 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10143 /* Might be a symbol version string. Don't as_bad here. */
10152 /* Parse operands of the form
10153 <symbol>@SECREL32+<nnn>
10155 If we find one, set up the correct relocation in RELOC and copy the
10156 input string, minus the `@SECREL32' into a malloc'd buffer for
10157 parsing by the calling routine. Return this buffer, and if ADJUST
10158 is non-null set it to the length of the string we removed from the
10159 input line. Otherwise return NULL.
10161 This function is copied from the ELF version above adjusted for PE targets. */
10164 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10165 int *adjust ATTRIBUTE_UNUSED
,
10166 i386_operand_type
*types
)
10168 static const struct
10172 const enum bfd_reloc_code_real rel
[2];
10173 const i386_operand_type types64
;
10177 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10178 BFD_RELOC_32_SECREL
},
10179 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10185 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10186 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10189 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10191 int len
= gotrel
[j
].len
;
10193 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10195 if (gotrel
[j
].rel
[object_64bit
] != 0)
10198 char *tmpbuf
, *past_reloc
;
10200 *rel
= gotrel
[j
].rel
[object_64bit
];
10206 if (flag_code
!= CODE_64BIT
)
10208 types
->bitfield
.imm32
= 1;
10209 types
->bitfield
.disp32
= 1;
10212 *types
= gotrel
[j
].types64
;
10215 /* The length of the first part of our input line. */
10216 first
= cp
- input_line_pointer
;
10218 /* The second part goes from after the reloc token until
10219 (and including) an end_of_line char or comma. */
10220 past_reloc
= cp
+ 1 + len
;
10222 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10224 second
= cp
+ 1 - past_reloc
;
10226 /* Allocate and copy string. The trailing NUL shouldn't
10227 be necessary, but be safe. */
10228 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10229 memcpy (tmpbuf
, input_line_pointer
, first
);
10230 if (second
!= 0 && *past_reloc
!= ' ')
10231 /* Replace the relocation token with ' ', so that
10232 errors like foo@SECLREL321 will be detected. */
10233 tmpbuf
[first
++] = ' ';
10234 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10235 tmpbuf
[first
+ second
] = '\0';
10239 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10240 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10245 /* Might be a symbol version string. Don't as_bad here. */
10251 bfd_reloc_code_real_type
10252 x86_cons (expressionS
*exp
, int size
)
10254 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10256 intel_syntax
= -intel_syntax
;
10259 if (size
== 4 || (object_64bit
&& size
== 8))
10261 /* Handle @GOTOFF and the like in an expression. */
10263 char *gotfree_input_line
;
10266 save
= input_line_pointer
;
10267 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10268 if (gotfree_input_line
)
10269 input_line_pointer
= gotfree_input_line
;
10273 if (gotfree_input_line
)
10275 /* expression () has merrily parsed up to the end of line,
10276 or a comma - in the wrong buffer. Transfer how far
10277 input_line_pointer has moved to the right buffer. */
10278 input_line_pointer
= (save
10279 + (input_line_pointer
- gotfree_input_line
)
10281 free (gotfree_input_line
);
10282 if (exp
->X_op
== O_constant
10283 || exp
->X_op
== O_absent
10284 || exp
->X_op
== O_illegal
10285 || exp
->X_op
== O_register
10286 || exp
->X_op
== O_big
)
10288 char c
= *input_line_pointer
;
10289 *input_line_pointer
= 0;
10290 as_bad (_("missing or invalid expression `%s'"), save
);
10291 *input_line_pointer
= c
;
10293 else if ((got_reloc
== BFD_RELOC_386_PLT32
10294 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10295 && exp
->X_op
!= O_symbol
)
10297 char c
= *input_line_pointer
;
10298 *input_line_pointer
= 0;
10299 as_bad (_("invalid PLT expression `%s'"), save
);
10300 *input_line_pointer
= c
;
10307 intel_syntax
= -intel_syntax
;
10310 i386_intel_simplify (exp
);
10316 signed_cons (int size
)
10318 if (flag_code
== CODE_64BIT
)
10326 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10333 if (exp
.X_op
== O_symbol
)
10334 exp
.X_op
= O_secrel
;
10336 emit_expr (&exp
, 4);
10338 while (*input_line_pointer
++ == ',');
10340 input_line_pointer
--;
10341 demand_empty_rest_of_line ();
10345 /* Handle Vector operations. */
10348 check_VecOperations (char *op_string
, char *op_end
)
10350 const reg_entry
*mask
;
10355 && (op_end
== NULL
|| op_string
< op_end
))
10358 if (*op_string
== '{')
10362 /* Check broadcasts. */
10363 if (strncmp (op_string
, "1to", 3) == 0)
10368 goto duplicated_vec_op
;
10371 if (*op_string
== '8')
10373 else if (*op_string
== '4')
10375 else if (*op_string
== '2')
10377 else if (*op_string
== '1'
10378 && *(op_string
+1) == '6')
10385 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10390 broadcast_op
.type
= bcst_type
;
10391 broadcast_op
.operand
= this_operand
;
10392 broadcast_op
.bytes
= 0;
10393 i
.broadcast
= &broadcast_op
;
10395 /* Check masking operation. */
10396 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10398 if (mask
== &bad_reg
)
10401 /* k0 can't be used for write mask. */
10402 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10404 as_bad (_("`%s%s' can't be used for write mask"),
10405 register_prefix
, mask
->reg_name
);
10411 mask_op
.mask
= mask
;
10412 mask_op
.zeroing
= 0;
10413 mask_op
.operand
= this_operand
;
10419 goto duplicated_vec_op
;
10421 i
.mask
->mask
= mask
;
10423 /* Only "{z}" is allowed here. No need to check
10424 zeroing mask explicitly. */
10425 if (i
.mask
->operand
!= this_operand
)
10427 as_bad (_("invalid write mask `%s'"), saved
);
10432 op_string
= end_op
;
10434 /* Check zeroing-flag for masking operation. */
10435 else if (*op_string
== 'z')
10439 mask_op
.mask
= NULL
;
10440 mask_op
.zeroing
= 1;
10441 mask_op
.operand
= this_operand
;
10446 if (i
.mask
->zeroing
)
10449 as_bad (_("duplicated `%s'"), saved
);
10453 i
.mask
->zeroing
= 1;
10455 /* Only "{%k}" is allowed here. No need to check mask
10456 register explicitly. */
10457 if (i
.mask
->operand
!= this_operand
)
10459 as_bad (_("invalid zeroing-masking `%s'"),
10468 goto unknown_vec_op
;
10470 if (*op_string
!= '}')
10472 as_bad (_("missing `}' in `%s'"), saved
);
10477 /* Strip whitespace since the addition of pseudo prefixes
10478 changed how the scrubber treats '{'. */
10479 if (is_space_char (*op_string
))
10485 /* We don't know this one. */
10486 as_bad (_("unknown vector operation: `%s'"), saved
);
10490 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10492 as_bad (_("zeroing-masking only allowed with write mask"));
10500 i386_immediate (char *imm_start
)
10502 char *save_input_line_pointer
;
10503 char *gotfree_input_line
;
10506 i386_operand_type types
;
10508 operand_type_set (&types
, ~0);
10510 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10512 as_bad (_("at most %d immediate operands are allowed"),
10513 MAX_IMMEDIATE_OPERANDS
);
10517 exp
= &im_expressions
[i
.imm_operands
++];
10518 i
.op
[this_operand
].imms
= exp
;
10520 if (is_space_char (*imm_start
))
10523 save_input_line_pointer
= input_line_pointer
;
10524 input_line_pointer
= imm_start
;
10526 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10527 if (gotfree_input_line
)
10528 input_line_pointer
= gotfree_input_line
;
10530 exp_seg
= expression (exp
);
10532 SKIP_WHITESPACE ();
10534 /* Handle vector operations. */
10535 if (*input_line_pointer
== '{')
10537 input_line_pointer
= check_VecOperations (input_line_pointer
,
10539 if (input_line_pointer
== NULL
)
10543 if (*input_line_pointer
)
10544 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10546 input_line_pointer
= save_input_line_pointer
;
10547 if (gotfree_input_line
)
10549 free (gotfree_input_line
);
10551 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10552 exp
->X_op
= O_illegal
;
10555 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10559 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10560 i386_operand_type types
, const char *imm_start
)
10562 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10565 as_bad (_("missing or invalid immediate expression `%s'"),
10569 else if (exp
->X_op
== O_constant
)
10571 /* Size it properly later. */
10572 i
.types
[this_operand
].bitfield
.imm64
= 1;
10573 /* If not 64bit, sign extend val. */
10574 if (flag_code
!= CODE_64BIT
10575 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10577 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10579 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10580 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10581 && exp_seg
!= absolute_section
10582 && exp_seg
!= text_section
10583 && exp_seg
!= data_section
10584 && exp_seg
!= bss_section
10585 && exp_seg
!= undefined_section
10586 && !bfd_is_com_section (exp_seg
))
10588 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10592 else if (!intel_syntax
&& exp_seg
== reg_section
)
10595 as_bad (_("illegal immediate register operand %s"), imm_start
);
10600 /* This is an address. The size of the address will be
10601 determined later, depending on destination register,
10602 suffix, or the default for the section. */
10603 i
.types
[this_operand
].bitfield
.imm8
= 1;
10604 i
.types
[this_operand
].bitfield
.imm16
= 1;
10605 i
.types
[this_operand
].bitfield
.imm32
= 1;
10606 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10607 i
.types
[this_operand
].bitfield
.imm64
= 1;
10608 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10616 i386_scale (char *scale
)
10619 char *save
= input_line_pointer
;
10621 input_line_pointer
= scale
;
10622 val
= get_absolute_expression ();
10627 i
.log2_scale_factor
= 0;
10630 i
.log2_scale_factor
= 1;
10633 i
.log2_scale_factor
= 2;
10636 i
.log2_scale_factor
= 3;
10640 char sep
= *input_line_pointer
;
10642 *input_line_pointer
= '\0';
10643 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10645 *input_line_pointer
= sep
;
10646 input_line_pointer
= save
;
10650 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10652 as_warn (_("scale factor of %d without an index register"),
10653 1 << i
.log2_scale_factor
);
10654 i
.log2_scale_factor
= 0;
10656 scale
= input_line_pointer
;
10657 input_line_pointer
= save
;
10662 i386_displacement (char *disp_start
, char *disp_end
)
10666 char *save_input_line_pointer
;
10667 char *gotfree_input_line
;
10669 i386_operand_type bigdisp
, types
= anydisp
;
10672 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10674 as_bad (_("at most %d displacement operands are allowed"),
10675 MAX_MEMORY_OPERANDS
);
10679 operand_type_set (&bigdisp
, 0);
10681 || i
.types
[this_operand
].bitfield
.baseindex
10682 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10683 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10685 i386_addressing_mode ();
10686 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10687 if (flag_code
== CODE_64BIT
)
10691 bigdisp
.bitfield
.disp32s
= 1;
10692 bigdisp
.bitfield
.disp64
= 1;
10695 bigdisp
.bitfield
.disp32
= 1;
10697 else if ((flag_code
== CODE_16BIT
) ^ override
)
10698 bigdisp
.bitfield
.disp16
= 1;
10700 bigdisp
.bitfield
.disp32
= 1;
10704 /* For PC-relative branches, the width of the displacement may be
10705 dependent upon data size, but is never dependent upon address size.
10706 Also make sure to not unintentionally match against a non-PC-relative
10707 branch template. */
10708 static templates aux_templates
;
10709 const insn_template
*t
= current_templates
->start
;
10710 bfd_boolean has_intel64
= FALSE
;
10712 aux_templates
.start
= t
;
10713 while (++t
< current_templates
->end
)
10715 if (t
->opcode_modifier
.jump
10716 != current_templates
->start
->opcode_modifier
.jump
)
10718 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10719 has_intel64
= TRUE
;
10721 if (t
< current_templates
->end
)
10723 aux_templates
.end
= t
;
10724 current_templates
= &aux_templates
;
10727 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10728 if (flag_code
== CODE_64BIT
)
10730 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10731 && (!intel64
|| !has_intel64
))
10732 bigdisp
.bitfield
.disp16
= 1;
10734 bigdisp
.bitfield
.disp32s
= 1;
10739 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10741 : LONG_MNEM_SUFFIX
));
10742 bigdisp
.bitfield
.disp32
= 1;
10743 if ((flag_code
== CODE_16BIT
) ^ override
)
10745 bigdisp
.bitfield
.disp32
= 0;
10746 bigdisp
.bitfield
.disp16
= 1;
10750 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10753 exp
= &disp_expressions
[i
.disp_operands
];
10754 i
.op
[this_operand
].disps
= exp
;
10756 save_input_line_pointer
= input_line_pointer
;
10757 input_line_pointer
= disp_start
;
10758 END_STRING_AND_SAVE (disp_end
);
10760 #ifndef GCC_ASM_O_HACK
10761 #define GCC_ASM_O_HACK 0
10764 END_STRING_AND_SAVE (disp_end
+ 1);
10765 if (i
.types
[this_operand
].bitfield
.baseIndex
10766 && displacement_string_end
[-1] == '+')
10768 /* This hack is to avoid a warning when using the "o"
10769 constraint within gcc asm statements.
10772 #define _set_tssldt_desc(n,addr,limit,type) \
10773 __asm__ __volatile__ ( \
10774 "movw %w2,%0\n\t" \
10775 "movw %w1,2+%0\n\t" \
10776 "rorl $16,%1\n\t" \
10777 "movb %b1,4+%0\n\t" \
10778 "movb %4,5+%0\n\t" \
10779 "movb $0,6+%0\n\t" \
10780 "movb %h1,7+%0\n\t" \
10782 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10784 This works great except that the output assembler ends
10785 up looking a bit weird if it turns out that there is
10786 no offset. You end up producing code that looks like:
10799 So here we provide the missing zero. */
10801 *displacement_string_end
= '0';
10804 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10805 if (gotfree_input_line
)
10806 input_line_pointer
= gotfree_input_line
;
10808 exp_seg
= expression (exp
);
10810 SKIP_WHITESPACE ();
10811 if (*input_line_pointer
)
10812 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10814 RESTORE_END_STRING (disp_end
+ 1);
10816 input_line_pointer
= save_input_line_pointer
;
10817 if (gotfree_input_line
)
10819 free (gotfree_input_line
);
10821 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10822 exp
->X_op
= O_illegal
;
10825 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10827 RESTORE_END_STRING (disp_end
);
10833 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10834 i386_operand_type types
, const char *disp_start
)
10836 i386_operand_type bigdisp
;
10839 /* We do this to make sure that the section symbol is in
10840 the symbol table. We will ultimately change the relocation
10841 to be relative to the beginning of the section. */
10842 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10843 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10844 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10846 if (exp
->X_op
!= O_symbol
)
10849 if (S_IS_LOCAL (exp
->X_add_symbol
)
10850 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10851 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10852 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10853 exp
->X_op
= O_subtract
;
10854 exp
->X_op_symbol
= GOT_symbol
;
10855 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10856 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10857 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10858 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10860 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10863 else if (exp
->X_op
== O_absent
10864 || exp
->X_op
== O_illegal
10865 || exp
->X_op
== O_big
)
10868 as_bad (_("missing or invalid displacement expression `%s'"),
10873 else if (flag_code
== CODE_64BIT
10874 && !i
.prefix
[ADDR_PREFIX
]
10875 && exp
->X_op
== O_constant
)
10877 /* Since displacement is signed extended to 64bit, don't allow
10878 disp32 and turn off disp32s if they are out of range. */
10879 i
.types
[this_operand
].bitfield
.disp32
= 0;
10880 if (!fits_in_signed_long (exp
->X_add_number
))
10882 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10883 if (i
.types
[this_operand
].bitfield
.baseindex
)
10885 as_bad (_("0x%lx out range of signed 32bit displacement"),
10886 (long) exp
->X_add_number
);
10892 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10893 else if (exp
->X_op
!= O_constant
10894 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10895 && exp_seg
!= absolute_section
10896 && exp_seg
!= text_section
10897 && exp_seg
!= data_section
10898 && exp_seg
!= bss_section
10899 && exp_seg
!= undefined_section
10900 && !bfd_is_com_section (exp_seg
))
10902 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10907 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10908 /* Constants get taken care of by optimize_disp(). */
10909 && exp
->X_op
!= O_constant
)
10910 i
.types
[this_operand
].bitfield
.disp8
= 1;
10912 /* Check if this is a displacement only operand. */
10913 bigdisp
= i
.types
[this_operand
];
10914 bigdisp
.bitfield
.disp8
= 0;
10915 bigdisp
.bitfield
.disp16
= 0;
10916 bigdisp
.bitfield
.disp32
= 0;
10917 bigdisp
.bitfield
.disp32s
= 0;
10918 bigdisp
.bitfield
.disp64
= 0;
10919 if (operand_type_all_zero (&bigdisp
))
10920 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10926 /* Return the active addressing mode, taking address override and
10927 registers forming the address into consideration. Update the
10928 address override prefix if necessary. */
10930 static enum flag_code
10931 i386_addressing_mode (void)
10933 enum flag_code addr_mode
;
10935 if (i
.prefix
[ADDR_PREFIX
])
10936 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10937 else if (flag_code
== CODE_16BIT
10938 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10939 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10940 from md_assemble() by "is not a valid base/index expression"
10941 when there is a base and/or index. */
10942 && !i
.types
[this_operand
].bitfield
.baseindex
)
10944 /* MPX insn memory operands with neither base nor index must be forced
10945 to use 32-bit addressing in 16-bit mode. */
10946 addr_mode
= CODE_32BIT
;
10947 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10949 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10950 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10954 addr_mode
= flag_code
;
10956 #if INFER_ADDR_PREFIX
10957 if (i
.mem_operands
== 0)
10959 /* Infer address prefix from the first memory operand. */
10960 const reg_entry
*addr_reg
= i
.base_reg
;
10962 if (addr_reg
== NULL
)
10963 addr_reg
= i
.index_reg
;
10967 if (addr_reg
->reg_type
.bitfield
.dword
)
10968 addr_mode
= CODE_32BIT
;
10969 else if (flag_code
!= CODE_64BIT
10970 && addr_reg
->reg_type
.bitfield
.word
)
10971 addr_mode
= CODE_16BIT
;
10973 if (addr_mode
!= flag_code
)
10975 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10977 /* Change the size of any displacement too. At most one
10978 of Disp16 or Disp32 is set.
10979 FIXME. There doesn't seem to be any real need for
10980 separate Disp16 and Disp32 flags. The same goes for
10981 Imm16 and Imm32. Removing them would probably clean
10982 up the code quite a lot. */
10983 if (flag_code
!= CODE_64BIT
10984 && (i
.types
[this_operand
].bitfield
.disp16
10985 || i
.types
[this_operand
].bitfield
.disp32
))
10986 i
.types
[this_operand
]
10987 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10997 /* Make sure the memory operand we've been dealt is valid.
10998 Return 1 on success, 0 on a failure. */
11001 i386_index_check (const char *operand_string
)
11003 const char *kind
= "base/index";
11004 enum flag_code addr_mode
= i386_addressing_mode ();
11006 if (current_templates
->start
->opcode_modifier
.isstring
11007 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
11008 && (current_templates
->end
[-1].opcode_modifier
.isstring
11009 || i
.mem_operands
))
11011 /* Memory operands of string insns are special in that they only allow
11012 a single register (rDI, rSI, or rBX) as their memory address. */
11013 const reg_entry
*expected_reg
;
11014 static const char *di_si
[][2] =
11020 static const char *bx
[] = { "ebx", "bx", "rbx" };
11022 kind
= "string address";
11024 if (current_templates
->start
->opcode_modifier
.repprefixok
)
11026 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11027 - IS_STRING_ES_OP0
;
11030 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11031 || ((!i
.mem_operands
!= !intel_syntax
)
11032 && current_templates
->end
[-1].operand_types
[1]
11033 .bitfield
.baseindex
))
11036 = (const reg_entry
*) str_hash_find (reg_hash
,
11037 di_si
[addr_mode
][op
== es_op
]);
11041 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11043 if (i
.base_reg
!= expected_reg
11045 || operand_type_check (i
.types
[this_operand
], disp
))
11047 /* The second memory operand must have the same size as
11051 && !((addr_mode
== CODE_64BIT
11052 && i
.base_reg
->reg_type
.bitfield
.qword
)
11053 || (addr_mode
== CODE_32BIT
11054 ? i
.base_reg
->reg_type
.bitfield
.dword
11055 : i
.base_reg
->reg_type
.bitfield
.word
)))
11058 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11060 intel_syntax
? '[' : '(',
11062 expected_reg
->reg_name
,
11063 intel_syntax
? ']' : ')');
11070 as_bad (_("`%s' is not a valid %s expression"),
11071 operand_string
, kind
);
11076 if (addr_mode
!= CODE_16BIT
)
11078 /* 32-bit/64-bit checks. */
11079 if (i
.disp_encoding
== disp_encoding_16bit
)
11082 as_bad (_("invalid `%s' prefix"),
11083 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11088 && ((addr_mode
== CODE_64BIT
11089 ? !i
.base_reg
->reg_type
.bitfield
.qword
11090 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11091 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11092 || i
.base_reg
->reg_num
== RegIZ
))
11094 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11095 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11096 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11097 && ((addr_mode
== CODE_64BIT
11098 ? !i
.index_reg
->reg_type
.bitfield
.qword
11099 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11100 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11103 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11104 if (current_templates
->start
->base_opcode
== 0xf30f1b
11105 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11106 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11108 /* They cannot use RIP-relative addressing. */
11109 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11111 as_bad (_("`%s' cannot be used here"), operand_string
);
11115 /* bndldx and bndstx ignore their scale factor. */
11116 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11117 && i
.log2_scale_factor
)
11118 as_warn (_("register scaling is being ignored here"));
11123 /* 16-bit checks. */
11124 if (i
.disp_encoding
== disp_encoding_32bit
)
11128 && (!i
.base_reg
->reg_type
.bitfield
.word
11129 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11131 && (!i
.index_reg
->reg_type
.bitfield
.word
11132 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11134 && i
.base_reg
->reg_num
< 6
11135 && i
.index_reg
->reg_num
>= 6
11136 && i
.log2_scale_factor
== 0))))
11143 /* Handle vector immediates. */
11146 RC_SAE_immediate (const char *imm_start
)
11148 unsigned int match_found
, j
;
11149 const char *pstr
= imm_start
;
11157 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11159 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11163 rc_op
.type
= RC_NamesTable
[j
].type
;
11164 rc_op
.operand
= this_operand
;
11165 i
.rounding
= &rc_op
;
11169 as_bad (_("duplicated `%s'"), imm_start
);
11172 pstr
+= RC_NamesTable
[j
].len
;
11180 if (*pstr
++ != '}')
11182 as_bad (_("Missing '}': '%s'"), imm_start
);
11185 /* RC/SAE immediate string should contain nothing more. */;
11188 as_bad (_("Junk after '}': '%s'"), imm_start
);
11192 exp
= &im_expressions
[i
.imm_operands
++];
11193 i
.op
[this_operand
].imms
= exp
;
11195 exp
->X_op
= O_constant
;
11196 exp
->X_add_number
= 0;
11197 exp
->X_add_symbol
= (symbolS
*) 0;
11198 exp
->X_op_symbol
= (symbolS
*) 0;
11200 i
.types
[this_operand
].bitfield
.imm8
= 1;
11204 /* Only string instructions can have a second memory operand, so
11205 reduce current_templates to just those if it contains any. */
11207 maybe_adjust_templates (void)
11209 const insn_template
*t
;
11211 gas_assert (i
.mem_operands
== 1);
11213 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11214 if (t
->opcode_modifier
.isstring
)
11217 if (t
< current_templates
->end
)
11219 static templates aux_templates
;
11220 bfd_boolean recheck
;
11222 aux_templates
.start
= t
;
11223 for (; t
< current_templates
->end
; ++t
)
11224 if (!t
->opcode_modifier
.isstring
)
11226 aux_templates
.end
= t
;
11228 /* Determine whether to re-check the first memory operand. */
11229 recheck
= (aux_templates
.start
!= current_templates
->start
11230 || t
!= current_templates
->end
);
11232 current_templates
= &aux_templates
;
11236 i
.mem_operands
= 0;
11237 if (i
.memop1_string
!= NULL
11238 && i386_index_check (i
.memop1_string
) == 0)
11240 i
.mem_operands
= 1;
11247 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11251 i386_att_operand (char *operand_string
)
11253 const reg_entry
*r
;
11255 char *op_string
= operand_string
;
11257 if (is_space_char (*op_string
))
11260 /* We check for an absolute prefix (differentiating,
11261 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11262 if (*op_string
== ABSOLUTE_PREFIX
)
11265 if (is_space_char (*op_string
))
11267 i
.jumpabsolute
= TRUE
;
11270 /* Check if operand is a register. */
11271 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11273 i386_operand_type temp
;
11278 /* Check for a segment override by searching for ':' after a
11279 segment register. */
11280 op_string
= end_op
;
11281 if (is_space_char (*op_string
))
11283 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11285 switch (r
->reg_num
)
11288 i
.seg
[i
.mem_operands
] = &es
;
11291 i
.seg
[i
.mem_operands
] = &cs
;
11294 i
.seg
[i
.mem_operands
] = &ss
;
11297 i
.seg
[i
.mem_operands
] = &ds
;
11300 i
.seg
[i
.mem_operands
] = &fs
;
11303 i
.seg
[i
.mem_operands
] = &gs
;
11307 /* Skip the ':' and whitespace. */
11309 if (is_space_char (*op_string
))
11312 if (!is_digit_char (*op_string
)
11313 && !is_identifier_char (*op_string
)
11314 && *op_string
!= '('
11315 && *op_string
!= ABSOLUTE_PREFIX
)
11317 as_bad (_("bad memory operand `%s'"), op_string
);
11320 /* Handle case of %es:*foo. */
11321 if (*op_string
== ABSOLUTE_PREFIX
)
11324 if (is_space_char (*op_string
))
11326 i
.jumpabsolute
= TRUE
;
11328 goto do_memory_reference
;
11331 /* Handle vector operations. */
11332 if (*op_string
== '{')
11334 op_string
= check_VecOperations (op_string
, NULL
);
11335 if (op_string
== NULL
)
11341 as_bad (_("junk `%s' after register"), op_string
);
11344 temp
= r
->reg_type
;
11345 temp
.bitfield
.baseindex
= 0;
11346 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11348 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11349 i
.op
[this_operand
].regs
= r
;
11352 else if (*op_string
== REGISTER_PREFIX
)
11354 as_bad (_("bad register name `%s'"), op_string
);
11357 else if (*op_string
== IMMEDIATE_PREFIX
)
11360 if (i
.jumpabsolute
)
11362 as_bad (_("immediate operand illegal with absolute jump"));
11365 if (!i386_immediate (op_string
))
11368 else if (RC_SAE_immediate (operand_string
))
11370 /* If it is a RC or SAE immediate, do nothing. */
11373 else if (is_digit_char (*op_string
)
11374 || is_identifier_char (*op_string
)
11375 || *op_string
== '"'
11376 || *op_string
== '(')
11378 /* This is a memory reference of some sort. */
11381 /* Start and end of displacement string expression (if found). */
11382 char *displacement_string_start
;
11383 char *displacement_string_end
;
11386 do_memory_reference
:
11387 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11389 if ((i
.mem_operands
== 1
11390 && !current_templates
->start
->opcode_modifier
.isstring
)
11391 || i
.mem_operands
== 2)
11393 as_bad (_("too many memory references for `%s'"),
11394 current_templates
->start
->name
);
11398 /* Check for base index form. We detect the base index form by
11399 looking for an ')' at the end of the operand, searching
11400 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11402 base_string
= op_string
+ strlen (op_string
);
11404 /* Handle vector operations. */
11405 vop_start
= strchr (op_string
, '{');
11406 if (vop_start
&& vop_start
< base_string
)
11408 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11410 base_string
= vop_start
;
11414 if (is_space_char (*base_string
))
11417 /* If we only have a displacement, set-up for it to be parsed later. */
11418 displacement_string_start
= op_string
;
11419 displacement_string_end
= base_string
+ 1;
11421 if (*base_string
== ')')
11424 unsigned int parens_balanced
= 1;
11425 /* We've already checked that the number of left & right ()'s are
11426 equal, so this loop will not be infinite. */
11430 if (*base_string
== ')')
11432 if (*base_string
== '(')
11435 while (parens_balanced
);
11437 temp_string
= base_string
;
11439 /* Skip past '(' and whitespace. */
11441 if (is_space_char (*base_string
))
11444 if (*base_string
== ','
11445 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11448 displacement_string_end
= temp_string
;
11450 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11454 if (i
.base_reg
== &bad_reg
)
11456 base_string
= end_op
;
11457 if (is_space_char (*base_string
))
11461 /* There may be an index reg or scale factor here. */
11462 if (*base_string
== ',')
11465 if (is_space_char (*base_string
))
11468 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11471 if (i
.index_reg
== &bad_reg
)
11473 base_string
= end_op
;
11474 if (is_space_char (*base_string
))
11476 if (*base_string
== ',')
11479 if (is_space_char (*base_string
))
11482 else if (*base_string
!= ')')
11484 as_bad (_("expecting `,' or `)' "
11485 "after index register in `%s'"),
11490 else if (*base_string
== REGISTER_PREFIX
)
11492 end_op
= strchr (base_string
, ',');
11495 as_bad (_("bad register name `%s'"), base_string
);
11499 /* Check for scale factor. */
11500 if (*base_string
!= ')')
11502 char *end_scale
= i386_scale (base_string
);
11507 base_string
= end_scale
;
11508 if (is_space_char (*base_string
))
11510 if (*base_string
!= ')')
11512 as_bad (_("expecting `)' "
11513 "after scale factor in `%s'"),
11518 else if (!i
.index_reg
)
11520 as_bad (_("expecting index register or scale factor "
11521 "after `,'; got '%c'"),
11526 else if (*base_string
!= ')')
11528 as_bad (_("expecting `,' or `)' "
11529 "after base register in `%s'"),
11534 else if (*base_string
== REGISTER_PREFIX
)
11536 end_op
= strchr (base_string
, ',');
11539 as_bad (_("bad register name `%s'"), base_string
);
11544 /* If there's an expression beginning the operand, parse it,
11545 assuming displacement_string_start and
11546 displacement_string_end are meaningful. */
11547 if (displacement_string_start
!= displacement_string_end
)
11549 if (!i386_displacement (displacement_string_start
,
11550 displacement_string_end
))
11554 /* Special case for (%dx) while doing input/output op. */
11556 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11557 && i
.base_reg
->reg_type
.bitfield
.word
11558 && i
.index_reg
== 0
11559 && i
.log2_scale_factor
== 0
11560 && i
.seg
[i
.mem_operands
] == 0
11561 && !operand_type_check (i
.types
[this_operand
], disp
))
11563 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11567 if (i386_index_check (operand_string
) == 0)
11569 i
.flags
[this_operand
] |= Operand_Mem
;
11570 if (i
.mem_operands
== 0)
11571 i
.memop1_string
= xstrdup (operand_string
);
11576 /* It's not a memory operand; argh! */
11577 as_bad (_("invalid char %s beginning operand %d `%s'"),
11578 output_invalid (*op_string
),
11583 return 1; /* Normal return. */
11586 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11587 that an rs_machine_dependent frag may reach. */
11590 i386_frag_max_var (fragS
*frag
)
11592 /* The only relaxable frags are for jumps.
11593 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11594 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11595 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11600 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11602 /* STT_GNU_IFUNC symbol must go through PLT. */
11603 if ((symbol_get_bfdsym (fr_symbol
)->flags
11604 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11607 if (!S_IS_EXTERNAL (fr_symbol
))
11608 /* Symbol may be weak or local. */
11609 return !S_IS_WEAK (fr_symbol
);
11611 /* Global symbols with non-default visibility can't be preempted. */
11612 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11615 if (fr_var
!= NO_RELOC
)
11616 switch ((enum bfd_reloc_code_real
) fr_var
)
11618 case BFD_RELOC_386_PLT32
:
11619 case BFD_RELOC_X86_64_PLT32
:
11620 /* Symbol with PLT relocation may be preempted. */
11626 /* Global symbols with default visibility in a shared library may be
11627 preempted by another definition. */
11632 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11633 Note also work for Skylake and Cascadelake.
11634 ---------------------------------------------------------------------
11635 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11636 | ------ | ----------- | ------- | -------- |
11638 | Jno | N | N | Y |
11639 | Jc/Jb | Y | N | Y |
11640 | Jae/Jnb | Y | N | Y |
11641 | Je/Jz | Y | Y | Y |
11642 | Jne/Jnz | Y | Y | Y |
11643 | Jna/Jbe | Y | N | Y |
11644 | Ja/Jnbe | Y | N | Y |
11646 | Jns | N | N | Y |
11647 | Jp/Jpe | N | N | Y |
11648 | Jnp/Jpo | N | N | Y |
11649 | Jl/Jnge | Y | Y | Y |
11650 | Jge/Jnl | Y | Y | Y |
11651 | Jle/Jng | Y | Y | Y |
11652 | Jg/Jnle | Y | Y | Y |
11653 --------------------------------------------------------------------- */
11655 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11657 if (mf_cmp
== mf_cmp_alu_cmp
)
11658 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11659 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11660 if (mf_cmp
== mf_cmp_incdec
)
11661 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11662 || mf_jcc
== mf_jcc_jle
);
11663 if (mf_cmp
== mf_cmp_test_and
)
11668 /* Return the next non-empty frag. */
11671 i386_next_non_empty_frag (fragS
*fragP
)
11673 /* There may be a frag with a ".fill 0" when there is no room in
11674 the current frag for frag_grow in output_insn. */
11675 for (fragP
= fragP
->fr_next
;
11677 && fragP
->fr_type
== rs_fill
11678 && fragP
->fr_fix
== 0);
11679 fragP
= fragP
->fr_next
)
11684 /* Return the next jcc frag after BRANCH_PADDING. */
11687 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11689 fragS
*branch_fragP
;
11693 if (pad_fragP
->fr_type
== rs_machine_dependent
11694 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11695 == BRANCH_PADDING
))
11697 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11698 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11700 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11701 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11702 pad_fragP
->tc_frag_data
.mf_type
))
11703 return branch_fragP
;
11709 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11712 i386_classify_machine_dependent_frag (fragS
*fragP
)
11716 fragS
*branch_fragP
;
11718 unsigned int max_prefix_length
;
11720 if (fragP
->tc_frag_data
.classified
)
11723 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11724 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11725 for (next_fragP
= fragP
;
11726 next_fragP
!= NULL
;
11727 next_fragP
= next_fragP
->fr_next
)
11729 next_fragP
->tc_frag_data
.classified
= 1;
11730 if (next_fragP
->fr_type
== rs_machine_dependent
)
11731 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11733 case BRANCH_PADDING
:
11734 /* The BRANCH_PADDING frag must be followed by a branch
11736 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11737 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11739 case FUSED_JCC_PADDING
:
11740 /* Check if this is a fused jcc:
11742 CMP like instruction
11746 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11747 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11748 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11751 /* The BRANCH_PADDING frag is merged with the
11752 FUSED_JCC_PADDING frag. */
11753 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11754 /* CMP like instruction size. */
11755 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11756 frag_wane (pad_fragP
);
11757 /* Skip to branch_fragP. */
11758 next_fragP
= branch_fragP
;
11760 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11762 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11764 next_fragP
->fr_subtype
11765 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11766 next_fragP
->tc_frag_data
.max_bytes
11767 = next_fragP
->tc_frag_data
.max_prefix_length
;
11768 /* This will be updated in the BRANCH_PREFIX scan. */
11769 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11772 frag_wane (next_fragP
);
11777 /* Stop if there is no BRANCH_PREFIX. */
11778 if (!align_branch_prefix_size
)
11781 /* Scan for BRANCH_PREFIX. */
11782 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11784 if (fragP
->fr_type
!= rs_machine_dependent
11785 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11789 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11790 COND_JUMP_PREFIX. */
11791 max_prefix_length
= 0;
11792 for (next_fragP
= fragP
;
11793 next_fragP
!= NULL
;
11794 next_fragP
= next_fragP
->fr_next
)
11796 if (next_fragP
->fr_type
== rs_fill
)
11797 /* Skip rs_fill frags. */
11799 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11800 /* Stop for all other frags. */
11803 /* rs_machine_dependent frags. */
11804 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11807 /* Count BRANCH_PREFIX frags. */
11808 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11810 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11811 frag_wane (next_fragP
);
11815 += next_fragP
->tc_frag_data
.max_bytes
;
11817 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11819 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11820 == FUSED_JCC_PADDING
))
11822 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11823 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11827 /* Stop for other rs_machine_dependent frags. */
11831 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11833 /* Skip to the next frag. */
11834 fragP
= next_fragP
;
11838 /* Compute padding size for
11841 CMP like instruction
11843 COND_JUMP/UNCOND_JUMP
11848 COND_JUMP/UNCOND_JUMP
11852 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11854 unsigned int offset
, size
, padding_size
;
11855 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11857 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11859 address
= fragP
->fr_address
;
11860 address
+= fragP
->fr_fix
;
11862 /* CMP like instrunction size. */
11863 size
= fragP
->tc_frag_data
.cmp_size
;
11865 /* The base size of the branch frag. */
11866 size
+= branch_fragP
->fr_fix
;
11868 /* Add opcode and displacement bytes for the rs_machine_dependent
11870 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11871 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11873 /* Check if branch is within boundary and doesn't end at the last
11875 offset
= address
& ((1U << align_branch_power
) - 1);
11876 if ((offset
+ size
) >= (1U << align_branch_power
))
11877 /* Padding needed to avoid crossing boundary. */
11878 padding_size
= (1U << align_branch_power
) - offset
;
11880 /* No padding needed. */
11883 /* The return value may be saved in tc_frag_data.length which is
11885 if (!fits_in_unsigned_byte (padding_size
))
11888 return padding_size
;
11891 /* i386_generic_table_relax_frag()
11893 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11894 grow/shrink padding to align branch frags. Hand others to
11898 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11900 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11901 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11903 long padding_size
= i386_branch_padding_size (fragP
, 0);
11904 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11906 /* When the BRANCH_PREFIX frag is used, the computed address
11907 must match the actual address and there should be no padding. */
11908 if (fragP
->tc_frag_data
.padding_address
11909 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11913 /* Update the padding size. */
11915 fragP
->tc_frag_data
.length
= padding_size
;
11919 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11921 fragS
*padding_fragP
, *next_fragP
;
11922 long padding_size
, left_size
, last_size
;
11924 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11925 if (!padding_fragP
)
11926 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11927 return (fragP
->tc_frag_data
.length
11928 - fragP
->tc_frag_data
.last_length
);
11930 /* Compute the relative address of the padding frag in the very
11931 first time where the BRANCH_PREFIX frag sizes are zero. */
11932 if (!fragP
->tc_frag_data
.padding_address
)
11933 fragP
->tc_frag_data
.padding_address
11934 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11936 /* First update the last length from the previous interation. */
11937 left_size
= fragP
->tc_frag_data
.prefix_length
;
11938 for (next_fragP
= fragP
;
11939 next_fragP
!= padding_fragP
;
11940 next_fragP
= next_fragP
->fr_next
)
11941 if (next_fragP
->fr_type
== rs_machine_dependent
11942 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11947 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11951 if (max
> left_size
)
11956 next_fragP
->tc_frag_data
.last_length
= size
;
11960 next_fragP
->tc_frag_data
.last_length
= 0;
11963 /* Check the padding size for the padding frag. */
11964 padding_size
= i386_branch_padding_size
11965 (padding_fragP
, (fragP
->fr_address
11966 + fragP
->tc_frag_data
.padding_address
));
11968 last_size
= fragP
->tc_frag_data
.prefix_length
;
11969 /* Check if there is change from the last interation. */
11970 if (padding_size
== last_size
)
11972 /* Update the expected address of the padding frag. */
11973 padding_fragP
->tc_frag_data
.padding_address
11974 = (fragP
->fr_address
+ padding_size
11975 + fragP
->tc_frag_data
.padding_address
);
11979 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11981 /* No padding if there is no sufficient room. Clear the
11982 expected address of the padding frag. */
11983 padding_fragP
->tc_frag_data
.padding_address
= 0;
11987 /* Store the expected address of the padding frag. */
11988 padding_fragP
->tc_frag_data
.padding_address
11989 = (fragP
->fr_address
+ padding_size
11990 + fragP
->tc_frag_data
.padding_address
);
11992 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11994 /* Update the length for the current interation. */
11995 left_size
= padding_size
;
11996 for (next_fragP
= fragP
;
11997 next_fragP
!= padding_fragP
;
11998 next_fragP
= next_fragP
->fr_next
)
11999 if (next_fragP
->fr_type
== rs_machine_dependent
12000 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12005 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12009 if (max
> left_size
)
12014 next_fragP
->tc_frag_data
.length
= size
;
12018 next_fragP
->tc_frag_data
.length
= 0;
12021 return (fragP
->tc_frag_data
.length
12022 - fragP
->tc_frag_data
.last_length
);
12024 return relax_frag (segment
, fragP
, stretch
);
12027 /* md_estimate_size_before_relax()
12029 Called just before relax() for rs_machine_dependent frags. The x86
12030 assembler uses these frags to handle variable size jump
12033 Any symbol that is now undefined will not become defined.
12034 Return the correct fr_subtype in the frag.
12035 Return the initial "guess for variable size of frag" to caller.
12036 The guess is actually the growth beyond the fixed part. Whatever
12037 we do to grow the fixed or variable part contributes to our
12041 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12043 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12044 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12045 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12047 i386_classify_machine_dependent_frag (fragP
);
12048 return fragP
->tc_frag_data
.length
;
12051 /* We've already got fragP->fr_subtype right; all we have to do is
12052 check for un-relaxable symbols. On an ELF system, we can't relax
12053 an externally visible symbol, because it may be overridden by a
12055 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12056 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12058 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12061 #if defined (OBJ_COFF) && defined (TE_PE)
12062 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12063 && S_IS_WEAK (fragP
->fr_symbol
))
12067 /* Symbol is undefined in this segment, or we need to keep a
12068 reloc so that weak symbols can be overridden. */
12069 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12070 enum bfd_reloc_code_real reloc_type
;
12071 unsigned char *opcode
;
12074 if (fragP
->fr_var
!= NO_RELOC
)
12075 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12076 else if (size
== 2)
12077 reloc_type
= BFD_RELOC_16_PCREL
;
12078 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12079 else if (need_plt32_p (fragP
->fr_symbol
))
12080 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12083 reloc_type
= BFD_RELOC_32_PCREL
;
12085 old_fr_fix
= fragP
->fr_fix
;
12086 opcode
= (unsigned char *) fragP
->fr_opcode
;
12088 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12091 /* Make jmp (0xeb) a (d)word displacement jump. */
12093 fragP
->fr_fix
+= size
;
12094 fix_new (fragP
, old_fr_fix
, size
,
12096 fragP
->fr_offset
, 1,
12102 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12104 /* Negate the condition, and branch past an
12105 unconditional jump. */
12108 /* Insert an unconditional jump. */
12110 /* We added two extra opcode bytes, and have a two byte
12112 fragP
->fr_fix
+= 2 + 2;
12113 fix_new (fragP
, old_fr_fix
+ 2, 2,
12115 fragP
->fr_offset
, 1,
12119 /* Fall through. */
12122 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12126 fragP
->fr_fix
+= 1;
12127 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12129 fragP
->fr_offset
, 1,
12130 BFD_RELOC_8_PCREL
);
12131 fixP
->fx_signed
= 1;
12135 /* This changes the byte-displacement jump 0x7N
12136 to the (d)word-displacement jump 0x0f,0x8N. */
12137 opcode
[1] = opcode
[0] + 0x10;
12138 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12139 /* We've added an opcode byte. */
12140 fragP
->fr_fix
+= 1 + size
;
12141 fix_new (fragP
, old_fr_fix
+ 1, size
,
12143 fragP
->fr_offset
, 1,
12148 BAD_CASE (fragP
->fr_subtype
);
12152 return fragP
->fr_fix
- old_fr_fix
;
12155 /* Guess size depending on current relax state. Initially the relax
12156 state will correspond to a short jump and we return 1, because
12157 the variable part of the frag (the branch offset) is one byte
12158 long. However, we can relax a section more than once and in that
12159 case we must either set fr_subtype back to the unrelaxed state,
12160 or return the value for the appropriate branch. */
12161 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12164 /* Called after relax() is finished.
12166 In: Address of frag.
12167 fr_type == rs_machine_dependent.
12168 fr_subtype is what the address relaxed to.
12170 Out: Any fixSs and constants are set up.
12171 Caller will turn frag into a ".space 0". */
12174 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12177 unsigned char *opcode
;
12178 unsigned char *where_to_put_displacement
= NULL
;
12179 offsetT target_address
;
12180 offsetT opcode_address
;
12181 unsigned int extension
= 0;
12182 offsetT displacement_from_opcode_start
;
12184 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12185 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12186 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12188 /* Generate nop padding. */
12189 unsigned int size
= fragP
->tc_frag_data
.length
;
12192 if (size
> fragP
->tc_frag_data
.max_bytes
)
12198 const char *branch
= "branch";
12199 const char *prefix
= "";
12200 fragS
*padding_fragP
;
12201 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12204 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12205 switch (fragP
->tc_frag_data
.default_prefix
)
12210 case CS_PREFIX_OPCODE
:
12213 case DS_PREFIX_OPCODE
:
12216 case ES_PREFIX_OPCODE
:
12219 case FS_PREFIX_OPCODE
:
12222 case GS_PREFIX_OPCODE
:
12225 case SS_PREFIX_OPCODE
:
12230 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12231 "%s within %d-byte boundary\n");
12233 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12234 "align %s within %d-byte boundary\n");
12238 padding_fragP
= fragP
;
12239 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12240 "%s within %d-byte boundary\n");
12244 switch (padding_fragP
->tc_frag_data
.branch_type
)
12246 case align_branch_jcc
:
12249 case align_branch_fused
:
12250 branch
= "fused jcc";
12252 case align_branch_jmp
:
12255 case align_branch_call
:
12258 case align_branch_indirect
:
12259 branch
= "indiret branch";
12261 case align_branch_ret
:
12268 fprintf (stdout
, msg
,
12269 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12270 (long long) fragP
->fr_address
, branch
,
12271 1 << align_branch_power
);
12273 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12274 memset (fragP
->fr_opcode
,
12275 fragP
->tc_frag_data
.default_prefix
, size
);
12277 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12279 fragP
->fr_fix
+= size
;
12284 opcode
= (unsigned char *) fragP
->fr_opcode
;
12286 /* Address we want to reach in file space. */
12287 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12289 /* Address opcode resides at in file space. */
12290 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12292 /* Displacement from opcode start to fill into instruction. */
12293 displacement_from_opcode_start
= target_address
- opcode_address
;
12295 if ((fragP
->fr_subtype
& BIG
) == 0)
12297 /* Don't have to change opcode. */
12298 extension
= 1; /* 1 opcode + 1 displacement */
12299 where_to_put_displacement
= &opcode
[1];
12303 if (no_cond_jump_promotion
12304 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12305 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12306 _("long jump required"));
12308 switch (fragP
->fr_subtype
)
12310 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12311 extension
= 4; /* 1 opcode + 4 displacement */
12313 where_to_put_displacement
= &opcode
[1];
12316 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12317 extension
= 2; /* 1 opcode + 2 displacement */
12319 where_to_put_displacement
= &opcode
[1];
12322 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12323 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12324 extension
= 5; /* 2 opcode + 4 displacement */
12325 opcode
[1] = opcode
[0] + 0x10;
12326 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12327 where_to_put_displacement
= &opcode
[2];
12330 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12331 extension
= 3; /* 2 opcode + 2 displacement */
12332 opcode
[1] = opcode
[0] + 0x10;
12333 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12334 where_to_put_displacement
= &opcode
[2];
12337 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12342 where_to_put_displacement
= &opcode
[3];
12346 BAD_CASE (fragP
->fr_subtype
);
12351 /* If size if less then four we are sure that the operand fits,
12352 but if it's 4, then it could be that the displacement is larger
12354 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12356 && ((addressT
) (displacement_from_opcode_start
- extension
12357 + ((addressT
) 1 << 31))
12358 > (((addressT
) 2 << 31) - 1)))
12360 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12361 _("jump target out of range"));
12362 /* Make us emit 0. */
12363 displacement_from_opcode_start
= extension
;
12365 /* Now put displacement after opcode. */
12366 md_number_to_chars ((char *) where_to_put_displacement
,
12367 (valueT
) (displacement_from_opcode_start
- extension
),
12368 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12369 fragP
->fr_fix
+= extension
;
12372 /* Apply a fixup (fixP) to segment data, once it has been determined
12373 by our caller that we have all the info we need to fix it up.
12375 Parameter valP is the pointer to the value of the bits.
12377 On the 386, immediates, displacements, and data pointers are all in
12378 the same (little-endian) format, so we don't need to care about which
12379 we are handling. */
12382 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12384 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12385 valueT value
= *valP
;
12387 #if !defined (TE_Mach)
12388 if (fixP
->fx_pcrel
)
12390 switch (fixP
->fx_r_type
)
12396 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12399 case BFD_RELOC_X86_64_32S
:
12400 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12403 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12406 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12411 if (fixP
->fx_addsy
!= NULL
12412 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12413 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12414 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12415 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12416 && !use_rela_relocations
)
12418 /* This is a hack. There should be a better way to handle this.
12419 This covers for the fact that bfd_install_relocation will
12420 subtract the current location (for partial_inplace, PC relative
12421 relocations); see more below. */
12425 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12428 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12433 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12435 if ((sym_seg
== seg
12436 || (symbol_section_p (fixP
->fx_addsy
)
12437 && sym_seg
!= absolute_section
))
12438 && !generic_force_reloc (fixP
))
12440 /* Yes, we add the values in twice. This is because
12441 bfd_install_relocation subtracts them out again. I think
12442 bfd_install_relocation is broken, but I don't dare change
12444 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12448 #if defined (OBJ_COFF) && defined (TE_PE)
12449 /* For some reason, the PE format does not store a
12450 section address offset for a PC relative symbol. */
12451 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12452 || S_IS_WEAK (fixP
->fx_addsy
))
12453 value
+= md_pcrel_from (fixP
);
12456 #if defined (OBJ_COFF) && defined (TE_PE)
12457 if (fixP
->fx_addsy
!= NULL
12458 && S_IS_WEAK (fixP
->fx_addsy
)
12459 /* PR 16858: Do not modify weak function references. */
12460 && ! fixP
->fx_pcrel
)
12462 #if !defined (TE_PEP)
12463 /* For x86 PE weak function symbols are neither PC-relative
12464 nor do they set S_IS_FUNCTION. So the only reliable way
12465 to detect them is to check the flags of their containing
12467 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12468 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12472 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12476 /* Fix a few things - the dynamic linker expects certain values here,
12477 and we must not disappoint it. */
12478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12479 if (IS_ELF
&& fixP
->fx_addsy
)
12480 switch (fixP
->fx_r_type
)
12482 case BFD_RELOC_386_PLT32
:
12483 case BFD_RELOC_X86_64_PLT32
:
12484 /* Make the jump instruction point to the address of the operand.
12485 At runtime we merely add the offset to the actual PLT entry.
12486 NB: Subtract the offset size only for jump instructions. */
12487 if (fixP
->fx_pcrel
)
12491 case BFD_RELOC_386_TLS_GD
:
12492 case BFD_RELOC_386_TLS_LDM
:
12493 case BFD_RELOC_386_TLS_IE_32
:
12494 case BFD_RELOC_386_TLS_IE
:
12495 case BFD_RELOC_386_TLS_GOTIE
:
12496 case BFD_RELOC_386_TLS_GOTDESC
:
12497 case BFD_RELOC_X86_64_TLSGD
:
12498 case BFD_RELOC_X86_64_TLSLD
:
12499 case BFD_RELOC_X86_64_GOTTPOFF
:
12500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12501 value
= 0; /* Fully resolved at runtime. No addend. */
12503 case BFD_RELOC_386_TLS_LE
:
12504 case BFD_RELOC_386_TLS_LDO_32
:
12505 case BFD_RELOC_386_TLS_LE_32
:
12506 case BFD_RELOC_X86_64_DTPOFF32
:
12507 case BFD_RELOC_X86_64_DTPOFF64
:
12508 case BFD_RELOC_X86_64_TPOFF32
:
12509 case BFD_RELOC_X86_64_TPOFF64
:
12510 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12513 case BFD_RELOC_386_TLS_DESC_CALL
:
12514 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12515 value
= 0; /* Fully resolved at runtime. No addend. */
12516 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12520 case BFD_RELOC_VTABLE_INHERIT
:
12521 case BFD_RELOC_VTABLE_ENTRY
:
12528 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12530 #endif /* !defined (TE_Mach) */
12532 /* Are we finished with this relocation now? */
12533 if (fixP
->fx_addsy
== NULL
)
12535 #if defined (OBJ_COFF) && defined (TE_PE)
12536 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12539 /* Remember value for tc_gen_reloc. */
12540 fixP
->fx_addnumber
= value
;
12541 /* Clear out the frag for now. */
12545 else if (use_rela_relocations
)
12547 fixP
->fx_no_overflow
= 1;
12548 /* Remember value for tc_gen_reloc. */
12549 fixP
->fx_addnumber
= value
;
12553 md_number_to_chars (p
, value
, fixP
->fx_size
);
12557 md_atof (int type
, char *litP
, int *sizeP
)
12559 /* This outputs the LITTLENUMs in REVERSE order;
12560 in accord with the bigendian 386. */
12561 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12564 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12567 output_invalid (int c
)
12570 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12573 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12574 "(0x%x)", (unsigned char) c
);
12575 return output_invalid_buf
;
12578 /* Verify that @r can be used in the current context. */
12580 static bfd_boolean
check_register (const reg_entry
*r
)
12582 if (allow_pseudo_reg
)
12585 if (operand_type_all_zero (&r
->reg_type
))
12588 if ((r
->reg_type
.bitfield
.dword
12589 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12590 || r
->reg_type
.bitfield
.class == RegCR
12591 || r
->reg_type
.bitfield
.class == RegDR
)
12592 && !cpu_arch_flags
.bitfield
.cpui386
)
12595 if (r
->reg_type
.bitfield
.class == RegTR
12596 && (flag_code
== CODE_64BIT
12597 || !cpu_arch_flags
.bitfield
.cpui386
12598 || cpu_arch_isa_flags
.bitfield
.cpui586
12599 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12602 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12605 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12607 if (r
->reg_type
.bitfield
.zmmword
12608 || r
->reg_type
.bitfield
.class == RegMask
)
12611 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12613 if (r
->reg_type
.bitfield
.ymmword
)
12616 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12621 if (r
->reg_type
.bitfield
.tmmword
12622 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12623 || flag_code
!= CODE_64BIT
))
12626 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12629 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12630 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12633 /* Upper 16 vector registers are only available with VREX in 64bit
12634 mode, and require EVEX encoding. */
12635 if (r
->reg_flags
& RegVRex
)
12637 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12638 || flag_code
!= CODE_64BIT
)
12641 if (i
.vec_encoding
== vex_encoding_default
)
12642 i
.vec_encoding
= vex_encoding_evex
;
12643 else if (i
.vec_encoding
!= vex_encoding_evex
)
12644 i
.vec_encoding
= vex_encoding_error
;
12647 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12648 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12649 && flag_code
!= CODE_64BIT
)
12652 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12659 /* REG_STRING starts *before* REGISTER_PREFIX. */
12661 static const reg_entry
*
12662 parse_real_register (char *reg_string
, char **end_op
)
12664 char *s
= reg_string
;
12666 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12667 const reg_entry
*r
;
12669 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12670 if (*s
== REGISTER_PREFIX
)
12673 if (is_space_char (*s
))
12676 p
= reg_name_given
;
12677 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12679 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12680 return (const reg_entry
*) NULL
;
12684 /* For naked regs, make sure that we are not dealing with an identifier.
12685 This prevents confusing an identifier like `eax_var' with register
12687 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12688 return (const reg_entry
*) NULL
;
12692 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12694 /* Handle floating point regs, allowing spaces in the (i) part. */
12695 if (r
== i386_regtab
/* %st is first entry of table */)
12697 if (!cpu_arch_flags
.bitfield
.cpu8087
12698 && !cpu_arch_flags
.bitfield
.cpu287
12699 && !cpu_arch_flags
.bitfield
.cpu387
12700 && !allow_pseudo_reg
)
12701 return (const reg_entry
*) NULL
;
12703 if (is_space_char (*s
))
12708 if (is_space_char (*s
))
12710 if (*s
>= '0' && *s
<= '7')
12712 int fpr
= *s
- '0';
12714 if (is_space_char (*s
))
12719 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12724 /* We have "%st(" then garbage. */
12725 return (const reg_entry
*) NULL
;
12729 return r
&& check_register (r
) ? r
: NULL
;
12732 /* REG_STRING starts *before* REGISTER_PREFIX. */
12734 static const reg_entry
*
12735 parse_register (char *reg_string
, char **end_op
)
12737 const reg_entry
*r
;
12739 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12740 r
= parse_real_register (reg_string
, end_op
);
12745 char *save
= input_line_pointer
;
12749 input_line_pointer
= reg_string
;
12750 c
= get_symbol_name (®_string
);
12751 symbolP
= symbol_find (reg_string
);
12752 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12754 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12756 know (e
->X_op
== O_register
);
12757 know (e
->X_add_number
>= 0
12758 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12759 r
= i386_regtab
+ e
->X_add_number
;
12760 if (!check_register (r
))
12762 as_bad (_("register '%s%s' cannot be used here"),
12763 register_prefix
, r
->reg_name
);
12766 *end_op
= input_line_pointer
;
12768 *input_line_pointer
= c
;
12769 input_line_pointer
= save
;
12775 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12777 const reg_entry
*r
;
12778 char *end
= input_line_pointer
;
12781 r
= parse_register (name
, &input_line_pointer
);
12782 if (r
&& end
<= input_line_pointer
)
12784 *nextcharP
= *input_line_pointer
;
12785 *input_line_pointer
= 0;
12788 e
->X_op
= O_register
;
12789 e
->X_add_number
= r
- i386_regtab
;
12792 e
->X_op
= O_illegal
;
12795 input_line_pointer
= end
;
12797 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12801 md_operand (expressionS
*e
)
12804 const reg_entry
*r
;
12806 switch (*input_line_pointer
)
12808 case REGISTER_PREFIX
:
12809 r
= parse_real_register (input_line_pointer
, &end
);
12812 e
->X_op
= O_register
;
12813 e
->X_add_number
= r
- i386_regtab
;
12814 input_line_pointer
= end
;
12819 gas_assert (intel_syntax
);
12820 end
= input_line_pointer
++;
12822 if (*input_line_pointer
== ']')
12824 ++input_line_pointer
;
12825 e
->X_op_symbol
= make_expr_symbol (e
);
12826 e
->X_add_symbol
= NULL
;
12827 e
->X_add_number
= 0;
12832 e
->X_op
= O_absent
;
12833 input_line_pointer
= end
;
12840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12841 const char *md_shortopts
= "kVQ:sqnO::";
12843 const char *md_shortopts
= "qnO::";
12846 #define OPTION_32 (OPTION_MD_BASE + 0)
12847 #define OPTION_64 (OPTION_MD_BASE + 1)
12848 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12849 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12850 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12851 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12852 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12853 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12854 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12855 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12856 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12857 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12858 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12859 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12860 #define OPTION_X32 (OPTION_MD_BASE + 14)
12861 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12862 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12863 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12864 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12865 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12866 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12867 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12868 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12869 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12870 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12871 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12872 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12873 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12874 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12875 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12876 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12877 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12878 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12879 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12881 struct option md_longopts
[] =
12883 {"32", no_argument
, NULL
, OPTION_32
},
12884 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12885 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12886 {"64", no_argument
, NULL
, OPTION_64
},
12888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12889 {"x32", no_argument
, NULL
, OPTION_X32
},
12890 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12891 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12893 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12894 {"march", required_argument
, NULL
, OPTION_MARCH
},
12895 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12896 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12897 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12898 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12899 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12900 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12901 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12902 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12903 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12904 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12905 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12906 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12907 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12908 # if defined (TE_PE) || defined (TE_PEP)
12909 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12911 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12912 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12913 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12914 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12915 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12916 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12917 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12918 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12919 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12920 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12921 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12922 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12923 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12924 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12925 {NULL
, no_argument
, NULL
, 0}
12927 size_t md_longopts_size
= sizeof (md_longopts
);
12930 md_parse_option (int c
, const char *arg
)
12933 char *arch
, *next
, *saved
, *type
;
12938 optimize_align_code
= 0;
12942 quiet_warnings
= 1;
12945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12946 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12947 should be emitted or not. FIXME: Not implemented. */
12949 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12953 /* -V: SVR4 argument to print version ID. */
12955 print_version_id ();
12958 /* -k: Ignore for FreeBSD compatibility. */
12963 /* -s: On i386 Solaris, this tells the native assembler to use
12964 .stab instead of .stab.excl. We always use .stab anyhow. */
12967 case OPTION_MSHARED
:
12971 case OPTION_X86_USED_NOTE
:
12972 if (strcasecmp (arg
, "yes") == 0)
12974 else if (strcasecmp (arg
, "no") == 0)
12977 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12982 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12983 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12986 const char **list
, **l
;
12988 list
= bfd_target_list ();
12989 for (l
= list
; *l
!= NULL
; l
++)
12990 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12991 || strcmp (*l
, "coff-x86-64") == 0
12992 || strcmp (*l
, "pe-x86-64") == 0
12993 || strcmp (*l
, "pei-x86-64") == 0
12994 || strcmp (*l
, "mach-o-x86-64") == 0)
12996 default_arch
= "x86_64";
13000 as_fatal (_("no compiled in support for x86_64"));
13006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13010 const char **list
, **l
;
13012 list
= bfd_target_list ();
13013 for (l
= list
; *l
!= NULL
; l
++)
13014 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
13016 default_arch
= "x86_64:32";
13020 as_fatal (_("no compiled in support for 32bit x86_64"));
13024 as_fatal (_("32bit x86_64 is only supported for ELF"));
13029 default_arch
= "i386";
13032 case OPTION_DIVIDE
:
13033 #ifdef SVR4_COMMENT_CHARS
13038 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13040 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13044 i386_comment_chars
= n
;
13050 saved
= xstrdup (arg
);
13052 /* Allow -march=+nosse. */
13058 as_fatal (_("invalid -march= option: `%s'"), arg
);
13059 next
= strchr (arch
, '+');
13062 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13064 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13067 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13070 cpu_arch_name
= cpu_arch
[j
].name
;
13071 cpu_sub_arch_name
= NULL
;
13072 cpu_arch_flags
= cpu_arch
[j
].flags
;
13073 cpu_arch_isa
= cpu_arch
[j
].type
;
13074 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13075 if (!cpu_arch_tune_set
)
13077 cpu_arch_tune
= cpu_arch_isa
;
13078 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13082 else if (*cpu_arch
[j
].name
== '.'
13083 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13085 /* ISA extension. */
13086 i386_cpu_flags flags
;
13088 flags
= cpu_flags_or (cpu_arch_flags
,
13089 cpu_arch
[j
].flags
);
13091 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13093 if (cpu_sub_arch_name
)
13095 char *name
= cpu_sub_arch_name
;
13096 cpu_sub_arch_name
= concat (name
,
13098 (const char *) NULL
);
13102 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13103 cpu_arch_flags
= flags
;
13104 cpu_arch_isa_flags
= flags
;
13108 = cpu_flags_or (cpu_arch_isa_flags
,
13109 cpu_arch
[j
].flags
);
13114 if (j
>= ARRAY_SIZE (cpu_arch
))
13116 /* Disable an ISA extension. */
13117 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13118 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13120 i386_cpu_flags flags
;
13122 flags
= cpu_flags_and_not (cpu_arch_flags
,
13123 cpu_noarch
[j
].flags
);
13124 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13126 if (cpu_sub_arch_name
)
13128 char *name
= cpu_sub_arch_name
;
13129 cpu_sub_arch_name
= concat (arch
,
13130 (const char *) NULL
);
13134 cpu_sub_arch_name
= xstrdup (arch
);
13135 cpu_arch_flags
= flags
;
13136 cpu_arch_isa_flags
= flags
;
13141 if (j
>= ARRAY_SIZE (cpu_noarch
))
13142 j
= ARRAY_SIZE (cpu_arch
);
13145 if (j
>= ARRAY_SIZE (cpu_arch
))
13146 as_fatal (_("invalid -march= option: `%s'"), arg
);
13150 while (next
!= NULL
);
13156 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13157 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13159 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13161 cpu_arch_tune_set
= 1;
13162 cpu_arch_tune
= cpu_arch
[j
].type
;
13163 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13167 if (j
>= ARRAY_SIZE (cpu_arch
))
13168 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13171 case OPTION_MMNEMONIC
:
13172 if (strcasecmp (arg
, "att") == 0)
13173 intel_mnemonic
= 0;
13174 else if (strcasecmp (arg
, "intel") == 0)
13175 intel_mnemonic
= 1;
13177 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13180 case OPTION_MSYNTAX
:
13181 if (strcasecmp (arg
, "att") == 0)
13183 else if (strcasecmp (arg
, "intel") == 0)
13186 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13189 case OPTION_MINDEX_REG
:
13190 allow_index_reg
= 1;
13193 case OPTION_MNAKED_REG
:
13194 allow_naked_reg
= 1;
13197 case OPTION_MSSE2AVX
:
13201 case OPTION_MSSE_CHECK
:
13202 if (strcasecmp (arg
, "error") == 0)
13203 sse_check
= check_error
;
13204 else if (strcasecmp (arg
, "warning") == 0)
13205 sse_check
= check_warning
;
13206 else if (strcasecmp (arg
, "none") == 0)
13207 sse_check
= check_none
;
13209 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13212 case OPTION_MOPERAND_CHECK
:
13213 if (strcasecmp (arg
, "error") == 0)
13214 operand_check
= check_error
;
13215 else if (strcasecmp (arg
, "warning") == 0)
13216 operand_check
= check_warning
;
13217 else if (strcasecmp (arg
, "none") == 0)
13218 operand_check
= check_none
;
13220 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13223 case OPTION_MAVXSCALAR
:
13224 if (strcasecmp (arg
, "128") == 0)
13225 avxscalar
= vex128
;
13226 else if (strcasecmp (arg
, "256") == 0)
13227 avxscalar
= vex256
;
13229 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13232 case OPTION_MVEXWIG
:
13233 if (strcmp (arg
, "0") == 0)
13235 else if (strcmp (arg
, "1") == 0)
13238 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13241 case OPTION_MADD_BND_PREFIX
:
13242 add_bnd_prefix
= 1;
13245 case OPTION_MEVEXLIG
:
13246 if (strcmp (arg
, "128") == 0)
13247 evexlig
= evexl128
;
13248 else if (strcmp (arg
, "256") == 0)
13249 evexlig
= evexl256
;
13250 else if (strcmp (arg
, "512") == 0)
13251 evexlig
= evexl512
;
13253 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13256 case OPTION_MEVEXRCIG
:
13257 if (strcmp (arg
, "rne") == 0)
13259 else if (strcmp (arg
, "rd") == 0)
13261 else if (strcmp (arg
, "ru") == 0)
13263 else if (strcmp (arg
, "rz") == 0)
13266 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13269 case OPTION_MEVEXWIG
:
13270 if (strcmp (arg
, "0") == 0)
13272 else if (strcmp (arg
, "1") == 0)
13275 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13278 # if defined (TE_PE) || defined (TE_PEP)
13279 case OPTION_MBIG_OBJ
:
13284 case OPTION_MOMIT_LOCK_PREFIX
:
13285 if (strcasecmp (arg
, "yes") == 0)
13286 omit_lock_prefix
= 1;
13287 else if (strcasecmp (arg
, "no") == 0)
13288 omit_lock_prefix
= 0;
13290 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13293 case OPTION_MFENCE_AS_LOCK_ADD
:
13294 if (strcasecmp (arg
, "yes") == 0)
13296 else if (strcasecmp (arg
, "no") == 0)
13299 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13302 case OPTION_MLFENCE_AFTER_LOAD
:
13303 if (strcasecmp (arg
, "yes") == 0)
13304 lfence_after_load
= 1;
13305 else if (strcasecmp (arg
, "no") == 0)
13306 lfence_after_load
= 0;
13308 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13311 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13312 if (strcasecmp (arg
, "all") == 0)
13314 lfence_before_indirect_branch
= lfence_branch_all
;
13315 if (lfence_before_ret
== lfence_before_ret_none
)
13316 lfence_before_ret
= lfence_before_ret_shl
;
13318 else if (strcasecmp (arg
, "memory") == 0)
13319 lfence_before_indirect_branch
= lfence_branch_memory
;
13320 else if (strcasecmp (arg
, "register") == 0)
13321 lfence_before_indirect_branch
= lfence_branch_register
;
13322 else if (strcasecmp (arg
, "none") == 0)
13323 lfence_before_indirect_branch
= lfence_branch_none
;
13325 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13329 case OPTION_MLFENCE_BEFORE_RET
:
13330 if (strcasecmp (arg
, "or") == 0)
13331 lfence_before_ret
= lfence_before_ret_or
;
13332 else if (strcasecmp (arg
, "not") == 0)
13333 lfence_before_ret
= lfence_before_ret_not
;
13334 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13335 lfence_before_ret
= lfence_before_ret_shl
;
13336 else if (strcasecmp (arg
, "none") == 0)
13337 lfence_before_ret
= lfence_before_ret_none
;
13339 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13343 case OPTION_MRELAX_RELOCATIONS
:
13344 if (strcasecmp (arg
, "yes") == 0)
13345 generate_relax_relocations
= 1;
13346 else if (strcasecmp (arg
, "no") == 0)
13347 generate_relax_relocations
= 0;
13349 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13352 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13355 long int align
= strtoul (arg
, &end
, 0);
13360 align_branch_power
= 0;
13363 else if (align
>= 16)
13366 for (align_power
= 0;
13368 align
>>= 1, align_power
++)
13370 /* Limit alignment power to 31. */
13371 if (align
== 1 && align_power
< 32)
13373 align_branch_power
= align_power
;
13378 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13382 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13385 int align
= strtoul (arg
, &end
, 0);
13386 /* Some processors only support 5 prefixes. */
13387 if (*end
== '\0' && align
>= 0 && align
< 6)
13389 align_branch_prefix_size
= align
;
13392 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13397 case OPTION_MALIGN_BRANCH
:
13399 saved
= xstrdup (arg
);
13403 next
= strchr (type
, '+');
13406 if (strcasecmp (type
, "jcc") == 0)
13407 align_branch
|= align_branch_jcc_bit
;
13408 else if (strcasecmp (type
, "fused") == 0)
13409 align_branch
|= align_branch_fused_bit
;
13410 else if (strcasecmp (type
, "jmp") == 0)
13411 align_branch
|= align_branch_jmp_bit
;
13412 else if (strcasecmp (type
, "call") == 0)
13413 align_branch
|= align_branch_call_bit
;
13414 else if (strcasecmp (type
, "ret") == 0)
13415 align_branch
|= align_branch_ret_bit
;
13416 else if (strcasecmp (type
, "indirect") == 0)
13417 align_branch
|= align_branch_indirect_bit
;
13419 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13422 while (next
!= NULL
);
13426 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13427 align_branch_power
= 5;
13428 align_branch_prefix_size
= 5;
13429 align_branch
= (align_branch_jcc_bit
13430 | align_branch_fused_bit
13431 | align_branch_jmp_bit
);
13434 case OPTION_MAMD64
:
13438 case OPTION_MINTEL64
:
13446 /* Turn off -Os. */
13447 optimize_for_space
= 0;
13449 else if (*arg
== 's')
13451 optimize_for_space
= 1;
13452 /* Turn on all encoding optimizations. */
13453 optimize
= INT_MAX
;
13457 optimize
= atoi (arg
);
13458 /* Turn off -Os. */
13459 optimize_for_space
= 0;
13469 #define MESSAGE_TEMPLATE \
13473 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13474 int *left_p
, const char *name
, int len
)
13476 int size
= sizeof (MESSAGE_TEMPLATE
);
13477 int left
= *left_p
;
13479 /* Reserve 2 spaces for ", " or ",\0" */
13482 /* Check if there is any room. */
13490 p
= mempcpy (p
, name
, len
);
13494 /* Output the current message now and start a new one. */
13497 fprintf (stream
, "%s\n", message
);
13499 left
= size
- (start
- message
) - len
- 2;
13501 gas_assert (left
>= 0);
13503 p
= mempcpy (p
, name
, len
);
13511 show_arch (FILE *stream
, int ext
, int check
)
13513 static char message
[] = MESSAGE_TEMPLATE
;
13514 char *start
= message
+ 27;
13516 int size
= sizeof (MESSAGE_TEMPLATE
);
13523 left
= size
- (start
- message
);
13524 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13526 /* Should it be skipped? */
13527 if (cpu_arch
[j
].skip
)
13530 name
= cpu_arch
[j
].name
;
13531 len
= cpu_arch
[j
].len
;
13534 /* It is an extension. Skip if we aren't asked to show it. */
13545 /* It is an processor. Skip if we show only extension. */
13548 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13550 /* It is an impossible processor - skip. */
13554 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13557 /* Display disabled extensions. */
13559 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13561 name
= cpu_noarch
[j
].name
;
13562 len
= cpu_noarch
[j
].len
;
13563 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13568 fprintf (stream
, "%s\n", message
);
13572 md_show_usage (FILE *stream
)
13574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13575 fprintf (stream
, _("\
13576 -Qy, -Qn ignored\n\
13577 -V print assembler version number\n\
13580 fprintf (stream
, _("\
13581 -n Do not optimize code alignment\n\
13582 -q quieten some warnings\n"));
13583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13584 fprintf (stream
, _("\
13587 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13588 || defined (TE_PE) || defined (TE_PEP))
13589 fprintf (stream
, _("\
13590 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13592 #ifdef SVR4_COMMENT_CHARS
13593 fprintf (stream
, _("\
13594 --divide do not treat `/' as a comment character\n"));
13596 fprintf (stream
, _("\
13597 --divide ignored\n"));
13599 fprintf (stream
, _("\
13600 -march=CPU[,+EXTENSION...]\n\
13601 generate code for CPU and EXTENSION, CPU is one of:\n"));
13602 show_arch (stream
, 0, 1);
13603 fprintf (stream
, _("\
13604 EXTENSION is combination of:\n"));
13605 show_arch (stream
, 1, 0);
13606 fprintf (stream
, _("\
13607 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13608 show_arch (stream
, 0, 0);
13609 fprintf (stream
, _("\
13610 -msse2avx encode SSE instructions with VEX prefix\n"));
13611 fprintf (stream
, _("\
13612 -msse-check=[none|error|warning] (default: warning)\n\
13613 check SSE instructions\n"));
13614 fprintf (stream
, _("\
13615 -moperand-check=[none|error|warning] (default: warning)\n\
13616 check operand combinations for validity\n"));
13617 fprintf (stream
, _("\
13618 -mavxscalar=[128|256] (default: 128)\n\
13619 encode scalar AVX instructions with specific vector\n\
13621 fprintf (stream
, _("\
13622 -mvexwig=[0|1] (default: 0)\n\
13623 encode VEX instructions with specific VEX.W value\n\
13624 for VEX.W bit ignored instructions\n"));
13625 fprintf (stream
, _("\
13626 -mevexlig=[128|256|512] (default: 128)\n\
13627 encode scalar EVEX instructions with specific vector\n\
13629 fprintf (stream
, _("\
13630 -mevexwig=[0|1] (default: 0)\n\
13631 encode EVEX instructions with specific EVEX.W value\n\
13632 for EVEX.W bit ignored instructions\n"));
13633 fprintf (stream
, _("\
13634 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13635 encode EVEX instructions with specific EVEX.RC value\n\
13636 for SAE-only ignored instructions\n"));
13637 fprintf (stream
, _("\
13638 -mmnemonic=[att|intel] "));
13639 if (SYSV386_COMPAT
)
13640 fprintf (stream
, _("(default: att)\n"));
13642 fprintf (stream
, _("(default: intel)\n"));
13643 fprintf (stream
, _("\
13644 use AT&T/Intel mnemonic\n"));
13645 fprintf (stream
, _("\
13646 -msyntax=[att|intel] (default: att)\n\
13647 use AT&T/Intel syntax\n"));
13648 fprintf (stream
, _("\
13649 -mindex-reg support pseudo index registers\n"));
13650 fprintf (stream
, _("\
13651 -mnaked-reg don't require `%%' prefix for registers\n"));
13652 fprintf (stream
, _("\
13653 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13655 fprintf (stream
, _("\
13656 -mshared disable branch optimization for shared code\n"));
13657 fprintf (stream
, _("\
13658 -mx86-used-note=[no|yes] "));
13659 if (DEFAULT_X86_USED_NOTE
)
13660 fprintf (stream
, _("(default: yes)\n"));
13662 fprintf (stream
, _("(default: no)\n"));
13663 fprintf (stream
, _("\
13664 generate x86 used ISA and feature properties\n"));
13666 #if defined (TE_PE) || defined (TE_PEP)
13667 fprintf (stream
, _("\
13668 -mbig-obj generate big object files\n"));
13670 fprintf (stream
, _("\
13671 -momit-lock-prefix=[no|yes] (default: no)\n\
13672 strip all lock prefixes\n"));
13673 fprintf (stream
, _("\
13674 -mfence-as-lock-add=[no|yes] (default: no)\n\
13675 encode lfence, mfence and sfence as\n\
13676 lock addl $0x0, (%%{re}sp)\n"));
13677 fprintf (stream
, _("\
13678 -mrelax-relocations=[no|yes] "));
13679 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13680 fprintf (stream
, _("(default: yes)\n"));
13682 fprintf (stream
, _("(default: no)\n"));
13683 fprintf (stream
, _("\
13684 generate relax relocations\n"));
13685 fprintf (stream
, _("\
13686 -malign-branch-boundary=NUM (default: 0)\n\
13687 align branches within NUM byte boundary\n"));
13688 fprintf (stream
, _("\
13689 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13690 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13692 specify types of branches to align\n"));
13693 fprintf (stream
, _("\
13694 -malign-branch-prefix-size=NUM (default: 5)\n\
13695 align branches with NUM prefixes per instruction\n"));
13696 fprintf (stream
, _("\
13697 -mbranches-within-32B-boundaries\n\
13698 align branches within 32 byte boundary\n"));
13699 fprintf (stream
, _("\
13700 -mlfence-after-load=[no|yes] (default: no)\n\
13701 generate lfence after load\n"));
13702 fprintf (stream
, _("\
13703 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13704 generate lfence before indirect near branch\n"));
13705 fprintf (stream
, _("\
13706 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13707 generate lfence before ret\n"));
13708 fprintf (stream
, _("\
13709 -mamd64 accept only AMD64 ISA [default]\n"));
13710 fprintf (stream
, _("\
13711 -mintel64 accept only Intel64 ISA\n"));
13714 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13715 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13716 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13718 /* Pick the target format to use. */
13721 i386_target_format (void)
13723 if (!strncmp (default_arch
, "x86_64", 6))
13725 update_code_flag (CODE_64BIT
, 1);
13726 if (default_arch
[6] == '\0')
13727 x86_elf_abi
= X86_64_ABI
;
13729 x86_elf_abi
= X86_64_X32_ABI
;
13731 else if (!strcmp (default_arch
, "i386"))
13732 update_code_flag (CODE_32BIT
, 1);
13733 else if (!strcmp (default_arch
, "iamcu"))
13735 update_code_flag (CODE_32BIT
, 1);
13736 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13738 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13739 cpu_arch_name
= "iamcu";
13740 cpu_sub_arch_name
= NULL
;
13741 cpu_arch_flags
= iamcu_flags
;
13742 cpu_arch_isa
= PROCESSOR_IAMCU
;
13743 cpu_arch_isa_flags
= iamcu_flags
;
13744 if (!cpu_arch_tune_set
)
13746 cpu_arch_tune
= cpu_arch_isa
;
13747 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13750 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13751 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13755 as_fatal (_("unknown architecture"));
13757 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13758 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13759 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13760 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13762 switch (OUTPUT_FLAVOR
)
13764 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13765 case bfd_target_aout_flavour
:
13766 return AOUT_TARGET_FORMAT
;
13768 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13769 # if defined (TE_PE) || defined (TE_PEP)
13770 case bfd_target_coff_flavour
:
13771 if (flag_code
== CODE_64BIT
)
13772 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13774 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13775 # elif defined (TE_GO32)
13776 case bfd_target_coff_flavour
:
13777 return "coff-go32";
13779 case bfd_target_coff_flavour
:
13780 return "coff-i386";
13783 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13784 case bfd_target_elf_flavour
:
13786 const char *format
;
13788 switch (x86_elf_abi
)
13791 format
= ELF_TARGET_FORMAT
;
13793 tls_get_addr
= "___tls_get_addr";
13797 use_rela_relocations
= 1;
13800 tls_get_addr
= "__tls_get_addr";
13802 format
= ELF_TARGET_FORMAT64
;
13804 case X86_64_X32_ABI
:
13805 use_rela_relocations
= 1;
13808 tls_get_addr
= "__tls_get_addr";
13810 disallow_64bit_reloc
= 1;
13811 format
= ELF_TARGET_FORMAT32
;
13814 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13816 if (x86_elf_abi
!= X86_64_ABI
)
13817 as_fatal (_("Intel L1OM is 64bit only"));
13818 return ELF_TARGET_L1OM_FORMAT
;
13820 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13822 if (x86_elf_abi
!= X86_64_ABI
)
13823 as_fatal (_("Intel K1OM is 64bit only"));
13824 return ELF_TARGET_K1OM_FORMAT
;
13826 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13828 if (x86_elf_abi
!= I386_ABI
)
13829 as_fatal (_("Intel MCU is 32bit only"));
13830 return ELF_TARGET_IAMCU_FORMAT
;
13836 #if defined (OBJ_MACH_O)
13837 case bfd_target_mach_o_flavour
:
13838 if (flag_code
== CODE_64BIT
)
13840 use_rela_relocations
= 1;
13842 return "mach-o-x86-64";
13845 return "mach-o-i386";
13853 #endif /* OBJ_MAYBE_ more than one */
13856 md_undefined_symbol (char *name
)
13858 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13859 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13860 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13861 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13865 if (symbol_find (name
))
13866 as_bad (_("GOT already in symbol table"));
13867 GOT_symbol
= symbol_new (name
, undefined_section
,
13868 &zero_address_frag
, 0);
13875 /* Round up a section size to the appropriate boundary. */
13878 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13880 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13881 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13883 /* For a.out, force the section size to be aligned. If we don't do
13884 this, BFD will align it for us, but it will not write out the
13885 final bytes of the section. This may be a bug in BFD, but it is
13886 easier to fix it here since that is how the other a.out targets
13890 align
= bfd_section_alignment (segment
);
13891 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13898 /* On the i386, PC-relative offsets are relative to the start of the
13899 next instruction. That is, the address of the offset, plus its
13900 size, since the offset is always the last part of the insn. */
13903 md_pcrel_from (fixS
*fixP
)
13905 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13911 s_bss (int ignore ATTRIBUTE_UNUSED
)
13915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13917 obj_elf_section_change_hook ();
13919 temp
= get_absolute_expression ();
13920 subseg_set (bss_section
, (subsegT
) temp
);
13921 demand_empty_rest_of_line ();
13926 /* Remember constant directive. */
13929 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13931 if (last_insn
.kind
!= last_insn_directive
13932 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13934 last_insn
.seg
= now_seg
;
13935 last_insn
.kind
= last_insn_directive
;
13936 last_insn
.name
= "constant directive";
13937 last_insn
.file
= as_where (&last_insn
.line
);
13938 if (lfence_before_ret
!= lfence_before_ret_none
)
13940 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13941 as_warn (_("constant directive skips -mlfence-before-ret "
13942 "and -mlfence-before-indirect-branch"));
13944 as_warn (_("constant directive skips -mlfence-before-ret"));
13946 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13947 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13952 i386_validate_fix (fixS
*fixp
)
13954 if (fixp
->fx_subsy
)
13956 if (fixp
->fx_subsy
== GOT_symbol
)
13958 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13963 if (fixp
->fx_tcbit2
)
13964 fixp
->fx_r_type
= (fixp
->fx_tcbit
13965 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13966 : BFD_RELOC_X86_64_GOTPCRELX
);
13969 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13974 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13976 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13978 fixp
->fx_subsy
= 0;
13981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13984 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13985 to section. Since PLT32 relocation must be against symbols,
13986 turn such PLT32 relocation into PC32 relocation. */
13988 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13989 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13990 && symbol_section_p (fixp
->fx_addsy
))
13991 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13994 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13995 && fixp
->fx_tcbit2
)
13996 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14003 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14006 bfd_reloc_code_real_type code
;
14008 switch (fixp
->fx_r_type
)
14010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14011 case BFD_RELOC_SIZE32
:
14012 case BFD_RELOC_SIZE64
:
14013 if (S_IS_DEFINED (fixp
->fx_addsy
)
14014 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14016 /* Resolve size relocation against local symbol to size of
14017 the symbol plus addend. */
14018 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14019 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14020 && !fits_in_unsigned_long (value
))
14021 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14022 _("symbol size computation overflow"));
14023 fixp
->fx_addsy
= NULL
;
14024 fixp
->fx_subsy
= NULL
;
14025 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14029 /* Fall through. */
14031 case BFD_RELOC_X86_64_PLT32
:
14032 case BFD_RELOC_X86_64_GOT32
:
14033 case BFD_RELOC_X86_64_GOTPCREL
:
14034 case BFD_RELOC_X86_64_GOTPCRELX
:
14035 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14036 case BFD_RELOC_386_PLT32
:
14037 case BFD_RELOC_386_GOT32
:
14038 case BFD_RELOC_386_GOT32X
:
14039 case BFD_RELOC_386_GOTOFF
:
14040 case BFD_RELOC_386_GOTPC
:
14041 case BFD_RELOC_386_TLS_GD
:
14042 case BFD_RELOC_386_TLS_LDM
:
14043 case BFD_RELOC_386_TLS_LDO_32
:
14044 case BFD_RELOC_386_TLS_IE_32
:
14045 case BFD_RELOC_386_TLS_IE
:
14046 case BFD_RELOC_386_TLS_GOTIE
:
14047 case BFD_RELOC_386_TLS_LE_32
:
14048 case BFD_RELOC_386_TLS_LE
:
14049 case BFD_RELOC_386_TLS_GOTDESC
:
14050 case BFD_RELOC_386_TLS_DESC_CALL
:
14051 case BFD_RELOC_X86_64_TLSGD
:
14052 case BFD_RELOC_X86_64_TLSLD
:
14053 case BFD_RELOC_X86_64_DTPOFF32
:
14054 case BFD_RELOC_X86_64_DTPOFF64
:
14055 case BFD_RELOC_X86_64_GOTTPOFF
:
14056 case BFD_RELOC_X86_64_TPOFF32
:
14057 case BFD_RELOC_X86_64_TPOFF64
:
14058 case BFD_RELOC_X86_64_GOTOFF64
:
14059 case BFD_RELOC_X86_64_GOTPC32
:
14060 case BFD_RELOC_X86_64_GOT64
:
14061 case BFD_RELOC_X86_64_GOTPCREL64
:
14062 case BFD_RELOC_X86_64_GOTPC64
:
14063 case BFD_RELOC_X86_64_GOTPLT64
:
14064 case BFD_RELOC_X86_64_PLTOFF64
:
14065 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14066 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14067 case BFD_RELOC_RVA
:
14068 case BFD_RELOC_VTABLE_ENTRY
:
14069 case BFD_RELOC_VTABLE_INHERIT
:
14071 case BFD_RELOC_32_SECREL
:
14073 code
= fixp
->fx_r_type
;
14075 case BFD_RELOC_X86_64_32S
:
14076 if (!fixp
->fx_pcrel
)
14078 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14079 code
= fixp
->fx_r_type
;
14082 /* Fall through. */
14084 if (fixp
->fx_pcrel
)
14086 switch (fixp
->fx_size
)
14089 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14090 _("can not do %d byte pc-relative relocation"),
14092 code
= BFD_RELOC_32_PCREL
;
14094 case 1: code
= BFD_RELOC_8_PCREL
; break;
14095 case 2: code
= BFD_RELOC_16_PCREL
; break;
14096 case 4: code
= BFD_RELOC_32_PCREL
; break;
14098 case 8: code
= BFD_RELOC_64_PCREL
; break;
14104 switch (fixp
->fx_size
)
14107 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14108 _("can not do %d byte relocation"),
14110 code
= BFD_RELOC_32
;
14112 case 1: code
= BFD_RELOC_8
; break;
14113 case 2: code
= BFD_RELOC_16
; break;
14114 case 4: code
= BFD_RELOC_32
; break;
14116 case 8: code
= BFD_RELOC_64
; break;
14123 if ((code
== BFD_RELOC_32
14124 || code
== BFD_RELOC_32_PCREL
14125 || code
== BFD_RELOC_X86_64_32S
)
14127 && fixp
->fx_addsy
== GOT_symbol
)
14130 code
= BFD_RELOC_386_GOTPC
;
14132 code
= BFD_RELOC_X86_64_GOTPC32
;
14134 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14136 && fixp
->fx_addsy
== GOT_symbol
)
14138 code
= BFD_RELOC_X86_64_GOTPC64
;
14141 rel
= XNEW (arelent
);
14142 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14143 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14145 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14147 if (!use_rela_relocations
)
14149 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14150 vtable entry to be used in the relocation's section offset. */
14151 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14152 rel
->address
= fixp
->fx_offset
;
14153 #if defined (OBJ_COFF) && defined (TE_PE)
14154 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14155 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14160 /* Use the rela in 64bit mode. */
14163 if (disallow_64bit_reloc
)
14166 case BFD_RELOC_X86_64_DTPOFF64
:
14167 case BFD_RELOC_X86_64_TPOFF64
:
14168 case BFD_RELOC_64_PCREL
:
14169 case BFD_RELOC_X86_64_GOTOFF64
:
14170 case BFD_RELOC_X86_64_GOT64
:
14171 case BFD_RELOC_X86_64_GOTPCREL64
:
14172 case BFD_RELOC_X86_64_GOTPC64
:
14173 case BFD_RELOC_X86_64_GOTPLT64
:
14174 case BFD_RELOC_X86_64_PLTOFF64
:
14175 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14176 _("cannot represent relocation type %s in x32 mode"),
14177 bfd_get_reloc_code_name (code
));
14183 if (!fixp
->fx_pcrel
)
14184 rel
->addend
= fixp
->fx_offset
;
14188 case BFD_RELOC_X86_64_PLT32
:
14189 case BFD_RELOC_X86_64_GOT32
:
14190 case BFD_RELOC_X86_64_GOTPCREL
:
14191 case BFD_RELOC_X86_64_GOTPCRELX
:
14192 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14193 case BFD_RELOC_X86_64_TLSGD
:
14194 case BFD_RELOC_X86_64_TLSLD
:
14195 case BFD_RELOC_X86_64_GOTTPOFF
:
14196 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14197 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14198 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14201 rel
->addend
= (section
->vma
14203 + fixp
->fx_addnumber
14204 + md_pcrel_from (fixp
));
14209 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14210 if (rel
->howto
== NULL
)
14212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14213 _("cannot represent relocation type %s"),
14214 bfd_get_reloc_code_name (code
));
14215 /* Set howto to a garbage value so that we can keep going. */
14216 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14217 gas_assert (rel
->howto
!= NULL
);
14223 #include "tc-i386-intel.c"
14226 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14228 int saved_naked_reg
;
14229 char saved_register_dot
;
14231 saved_naked_reg
= allow_naked_reg
;
14232 allow_naked_reg
= 1;
14233 saved_register_dot
= register_chars
['.'];
14234 register_chars
['.'] = '.';
14235 allow_pseudo_reg
= 1;
14236 expression_and_evaluate (exp
);
14237 allow_pseudo_reg
= 0;
14238 register_chars
['.'] = saved_register_dot
;
14239 allow_naked_reg
= saved_naked_reg
;
14241 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14243 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14245 exp
->X_op
= O_constant
;
14246 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14247 .dw2_regnum
[flag_code
>> 1];
14250 exp
->X_op
= O_illegal
;
14255 tc_x86_frame_initial_instructions (void)
14257 static unsigned int sp_regno
[2];
14259 if (!sp_regno
[flag_code
>> 1])
14261 char *saved_input
= input_line_pointer
;
14262 char sp
[][4] = {"esp", "rsp"};
14265 input_line_pointer
= sp
[flag_code
>> 1];
14266 tc_x86_parse_to_dw2regnum (&exp
);
14267 gas_assert (exp
.X_op
== O_constant
);
14268 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14269 input_line_pointer
= saved_input
;
14272 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14273 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14277 x86_dwarf2_addr_size (void)
14279 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14280 if (x86_elf_abi
== X86_64_X32_ABI
)
14283 return bfd_arch_bits_per_address (stdoutput
) / 8;
14287 i386_elf_section_type (const char *str
, size_t len
)
14289 if (flag_code
== CODE_64BIT
14290 && len
== sizeof ("unwind") - 1
14291 && strncmp (str
, "unwind", 6) == 0)
14292 return SHT_X86_64_UNWIND
;
14299 i386_solaris_fix_up_eh_frame (segT sec
)
14301 if (flag_code
== CODE_64BIT
)
14302 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14308 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14312 exp
.X_op
= O_secrel
;
14313 exp
.X_add_symbol
= symbol
;
14314 exp
.X_add_number
= 0;
14315 emit_expr (&exp
, size
);
14319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14320 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14323 x86_64_section_letter (int letter
, const char **ptr_msg
)
14325 if (flag_code
== CODE_64BIT
)
14328 return SHF_X86_64_LARGE
;
14330 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14333 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14338 x86_64_section_word (char *str
, size_t len
)
14340 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14341 return SHF_X86_64_LARGE
;
14347 handle_large_common (int small ATTRIBUTE_UNUSED
)
14349 if (flag_code
!= CODE_64BIT
)
14351 s_comm_internal (0, elf_common_parse
);
14352 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14356 static segT lbss_section
;
14357 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14358 asection
*saved_bss_section
= bss_section
;
14360 if (lbss_section
== NULL
)
14362 flagword applicable
;
14363 segT seg
= now_seg
;
14364 subsegT subseg
= now_subseg
;
14366 /* The .lbss section is for local .largecomm symbols. */
14367 lbss_section
= subseg_new (".lbss", 0);
14368 applicable
= bfd_applicable_section_flags (stdoutput
);
14369 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14370 seg_info (lbss_section
)->bss
= 1;
14372 subseg_set (seg
, subseg
);
14375 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14376 bss_section
= lbss_section
;
14378 s_comm_internal (0, elf_common_parse
);
14380 elf_com_section_ptr
= saved_com_section_ptr
;
14381 bss_section
= saved_bss_section
;
14384 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */