1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
71 #define REX_PREFIX 6 /* must come last. */
72 #define MAX_PREFIXES 7 /* max prefixes per opcode */
74 /* we define the syntax here (modulo base,index,scale syntax) */
75 #define REGISTER_PREFIX '%'
76 #define IMMEDIATE_PREFIX '$'
77 #define ABSOLUTE_PREFIX '*'
79 /* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81 #define WORD_MNEM_SUFFIX 'w'
82 #define BYTE_MNEM_SUFFIX 'b'
83 #define SHORT_MNEM_SUFFIX 's'
84 #define LONG_MNEM_SUFFIX 'l'
85 #define QWORD_MNEM_SUFFIX 'q'
86 #define XMMWORD_MNEM_SUFFIX 'x'
87 #define YMMWORD_MNEM_SUFFIX 'y'
88 /* Intel Syntax. Use a non-ascii letter since since it never appears
90 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
92 #define END_OF_INSN '\0'
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
103 const insn_template
*start
;
104 const insn_template
*end
;
108 /* 386 operand encoding bytes: see 386 book for details of this. */
111 unsigned int regmem
; /* codes register or memory operand */
112 unsigned int reg
; /* codes register operand (or extended opcode) */
113 unsigned int mode
; /* how to interpret regmem & reg */
117 /* x86-64 extension prefix. */
118 typedef int rex_byte
;
120 /* 386 opcode byte to code indirect addressing. */
129 /* x86 arch names, types and features */
132 const char *name
; /* arch name */
133 unsigned int len
; /* arch string length */
134 enum processor_type type
; /* arch type */
135 i386_cpu_flags flags
; /* cpu feature flags */
136 unsigned int skip
; /* show_arch should skip this. */
137 unsigned int negated
; /* turn off indicated flags. */
141 static void update_code_flag (int, int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static char *parse_insn (char *, char *);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (int, int);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (void);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const seg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 static const char *default_arch
= DEFAULT_ARCH
;
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes
[3];
197 /* Destination or source register specifier. */
198 const reg_entry
*register_specifier
;
201 /* 'md_assemble ()' gathers together information and puts it into a
208 const reg_entry
*regs
;
213 operand_size_mismatch
,
214 operand_type_mismatch
,
215 register_type_mismatch
,
216 number_of_operands_mismatch
,
217 invalid_instruction_suffix
,
220 unsupported_with_intel_mnemonic
,
223 invalid_vsib_address
,
224 invalid_vector_register_set
,
225 unsupported_vector_index_register
230 /* TM holds the template for the insn were currently assembling. */
233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
237 /* OPERANDS gives the number of given operands. */
238 unsigned int operands
;
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
243 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
245 /* TYPES [i] is the type (see above #defines) which tells us how to
246 use OP[i] for the corresponding operand. */
247 i386_operand_type types
[MAX_OPERANDS
];
249 /* Displacement expression, immediate expression, or register for each
251 union i386_op op
[MAX_OPERANDS
];
253 /* Flags for operands. */
254 unsigned int flags
[MAX_OPERANDS
];
255 #define Operand_PCrel 1
257 /* Relocation type for operand */
258 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry
*base_reg
;
263 const reg_entry
*index_reg
;
264 unsigned int log2_scale_factor
;
266 /* SEG gives the seg_entries of this insn. They are zero unless
267 explicit segment overrides are given. */
268 const seg_entry
*seg
[2];
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes
;
273 unsigned char prefix
[MAX_PREFIXES
];
275 /* RM and SIB are the modrm byte and the sib byte where the
276 addressing modes of this insn are encoded. */
282 /* Swap operand in encoding. */
283 unsigned int swap_operand
;
285 /* Prefer 8bit or 32bit displacement in encoding. */
288 disp_encoding_default
= 0,
293 /* Have HLE prefix. */
294 unsigned int have_hle
;
297 enum i386_error error
;
300 typedef struct _i386_insn i386_insn
;
302 /* List of chars besides those in app.c:symbol_chars that can start an
303 operand. Used to prevent the scrubber eating vital white-space. */
304 const char extra_symbol_chars
[] = "*%-(["
313 #if (defined (TE_I386AIX) \
314 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
315 && !defined (TE_GNU) \
316 && !defined (TE_LINUX) \
317 && !defined (TE_NACL) \
318 && !defined (TE_NETWARE) \
319 && !defined (TE_FreeBSD) \
320 && !defined (TE_DragonFly) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
= -1;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static unsigned int disallow_64bit_reloc
;
408 static int use_rela_relocations
= 0;
410 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
411 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
412 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
414 /* The ELF ABI to use. */
422 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
425 /* The names used to print error messages. */
426 static const char *flag_code_names
[] =
433 /* 1 for intel syntax,
435 static int intel_syntax
= 0;
437 /* 1 for intel mnemonic,
438 0 if att mnemonic. */
439 static int intel_mnemonic
= !SYSV386_COMPAT
;
441 /* 1 if support old (<= 2.8.1) versions of gcc. */
442 static int old_gcc
= OLDGCC_COMPAT
;
444 /* 1 if pseudo registers are permitted. */
445 static int allow_pseudo_reg
= 0;
447 /* 1 if register prefix % not required. */
448 static int allow_naked_reg
= 0;
450 /* 1 if pseudo index register, eiz/riz, is allowed . */
451 static int allow_index_reg
= 0;
453 static enum check_kind
459 sse_check
, operand_check
= check_warning
;
461 /* Register prefix used for error message. */
462 static const char *register_prefix
= "%";
464 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
465 leave, push, and pop instructions so that gcc has the same stack
466 frame as in 32 bit mode. */
467 static char stackop_size
= '\0';
469 /* Non-zero to optimize code alignment. */
470 int optimize_align_code
= 1;
472 /* Non-zero to quieten some warnings. */
473 static int quiet_warnings
= 0;
476 static const char *cpu_arch_name
= NULL
;
477 static char *cpu_sub_arch_name
= NULL
;
479 /* CPU feature flags. */
480 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
482 /* If we have selected a cpu we are generating instructions for. */
483 static int cpu_arch_tune_set
= 0;
485 /* Cpu we are generating instructions for. */
486 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
488 /* CPU feature flags of cpu we are generating instructions for. */
489 static i386_cpu_flags cpu_arch_tune_flags
;
491 /* CPU instruction set architecture used. */
492 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
494 /* CPU feature flags of instruction set architecture used. */
495 i386_cpu_flags cpu_arch_isa_flags
;
497 /* If set, conditional jumps are not automatically promoted to handle
498 larger than a byte offset. */
499 static unsigned int no_cond_jump_promotion
= 0;
501 /* Encode SSE instructions with VEX prefix. */
502 static unsigned int sse2avx
;
504 /* Encode scalar AVX instructions with specific vector length. */
511 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
512 static symbolS
*GOT_symbol
;
514 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
515 unsigned int x86_dwarf2_return_column
;
517 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
518 int x86_cie_data_alignment
;
520 /* Interface to relax_segment.
521 There are 3 major relax states for 386 jump insns because the
522 different types of jumps add different sizes to frags when we're
523 figuring out what sort of jump to choose to reach a given label. */
526 #define UNCOND_JUMP 0
528 #define COND_JUMP86 2
533 #define SMALL16 (SMALL | CODE16)
535 #define BIG16 (BIG | CODE16)
539 #define INLINE __inline__
545 #define ENCODE_RELAX_STATE(type, size) \
546 ((relax_substateT) (((type) << 2) | (size)))
547 #define TYPE_FROM_RELAX_STATE(s) \
549 #define DISP_SIZE_FROM_RELAX_STATE(s) \
550 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
552 /* This table is used by relax_frag to promote short jumps to long
553 ones where necessary. SMALL (short) jumps may be promoted to BIG
554 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
555 don't allow a short jump in a 32 bit code segment to be promoted to
556 a 16 bit offset jump because it's slower (requires data size
557 prefix), and doesn't work, unless the destination is in the bottom
558 64k of the code segment (The top 16 bits of eip are zeroed). */
560 const relax_typeS md_relax_table
[] =
563 1) most positive reach of this state,
564 2) most negative reach of this state,
565 3) how many bytes this mode will have in the variable part of the frag
566 4) which index into the table to try if we can't fit into this one. */
568 /* UNCOND_JUMP states. */
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
570 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
571 /* dword jmp adds 4 bytes to frag:
572 0 extra opcode bytes, 4 displacement bytes. */
574 /* word jmp adds 2 byte2 to frag:
575 0 extra opcode bytes, 2 displacement bytes. */
578 /* COND_JUMP states. */
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
580 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
581 /* dword conditionals adds 5 bytes to frag:
582 1 extra opcode byte, 4 displacement bytes. */
584 /* word conditionals add 3 bytes to frag:
585 1 extra opcode byte, 2 displacement bytes. */
588 /* COND_JUMP86 states. */
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
590 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
591 /* dword conditionals adds 5 bytes to frag:
592 1 extra opcode byte, 4 displacement bytes. */
594 /* word conditionals add 4 bytes to frag:
595 1 displacement byte and a 3 byte long branch insn. */
599 static const arch_entry cpu_arch
[] =
601 /* Do not replace the first two entries - i386_target_format()
602 relies on them being there in this order. */
603 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
604 CPU_GENERIC32_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
606 CPU_GENERIC64_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
608 CPU_NONE_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
610 CPU_I186_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
612 CPU_I286_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
614 CPU_I386_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
616 CPU_I486_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
618 CPU_I586_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
620 CPU_I686_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
622 CPU_I586_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
624 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
626 CPU_P2_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
628 CPU_P3_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
630 CPU_P4_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
632 CPU_CORE_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
634 CPU_NOCONA_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
636 CPU_CORE_FLAGS
, 1, 0 },
637 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
638 CPU_CORE_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
640 CPU_CORE2_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
642 CPU_CORE2_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
644 CPU_COREI7_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
646 CPU_L1OM_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
648 CPU_K1OM_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
650 CPU_K6_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
652 CPU_K6_2_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
654 CPU_ATHLON_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
656 CPU_K8_FLAGS
, 1, 0 },
657 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
658 CPU_K8_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
660 CPU_K8_FLAGS
, 0, 0 },
661 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
662 CPU_AMDFAM10_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
664 CPU_BDVER1_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
666 CPU_BDVER2_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
668 CPU_BDVER3_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
670 CPU_BTVER1_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
672 CPU_BTVER2_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
674 CPU_8087_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
676 CPU_287_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
678 CPU_387_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
680 CPU_ANY87_FLAGS
, 0, 1 },
681 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
682 CPU_MMX_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
684 CPU_3DNOWA_FLAGS
, 0, 1 },
685 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
686 CPU_SSE_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
688 CPU_SSE2_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
690 CPU_SSE3_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
692 CPU_SSSE3_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
694 CPU_SSE4_1_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
696 CPU_SSE4_2_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
698 CPU_SSE4_2_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
700 CPU_ANY_SSE_FLAGS
, 0, 1 },
701 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
702 CPU_AVX_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
704 CPU_AVX2_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
706 CPU_ANY_AVX_FLAGS
, 0, 1 },
707 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
708 CPU_VMX_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
710 CPU_VMFUNC_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
712 CPU_SMX_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
714 CPU_XSAVE_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
716 CPU_XSAVEOPT_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
718 CPU_AES_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
720 CPU_PCLMUL_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
722 CPU_PCLMUL_FLAGS
, 1, 0 },
723 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
724 CPU_FSGSBASE_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
726 CPU_RDRND_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
728 CPU_F16C_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
730 CPU_BMI2_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
732 CPU_FMA_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
734 CPU_FMA4_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
736 CPU_XOP_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
738 CPU_LWP_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
740 CPU_MOVBE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
742 CPU_CX16_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
744 CPU_EPT_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
746 CPU_LZCNT_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
748 CPU_HLE_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
750 CPU_RTM_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
752 CPU_INVPCID_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
754 CPU_CLFLUSH_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
756 CPU_NOP_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
758 CPU_SYSCALL_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
760 CPU_RDTSCP_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
762 CPU_3DNOW_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
764 CPU_3DNOWA_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
766 CPU_PADLOCK_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
768 CPU_SVME_FLAGS
, 1, 0 },
769 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
770 CPU_SVME_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
772 CPU_SSE4A_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
774 CPU_ABM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
776 CPU_BMI_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
778 CPU_TBM_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
780 CPU_ADX_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
782 CPU_RDSEED_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
784 CPU_PRFCHW_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
786 CPU_SMAP_FLAGS
, 0, 0 },
790 /* Like s_lcomm_internal in gas/read.c but the alignment string
791 is allowed to be optional. */
794 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
801 && *input_line_pointer
== ',')
803 align
= parse_align (needs_align
- 1);
805 if (align
== (addressT
) -1)
820 bss_alloc (symbolP
, size
, align
);
825 pe_lcomm (int needs_align
)
827 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
831 const pseudo_typeS md_pseudo_table
[] =
833 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
834 {"align", s_align_bytes
, 0},
836 {"align", s_align_ptwo
, 0},
838 {"arch", set_cpu_arch
, 0},
842 {"lcomm", pe_lcomm
, 1},
844 {"ffloat", float_cons
, 'f'},
845 {"dfloat", float_cons
, 'd'},
846 {"tfloat", float_cons
, 'x'},
848 {"slong", signed_cons
, 4},
849 {"noopt", s_ignore
, 0},
850 {"optim", s_ignore
, 0},
851 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
852 {"code16", set_code_flag
, CODE_16BIT
},
853 {"code32", set_code_flag
, CODE_32BIT
},
854 {"code64", set_code_flag
, CODE_64BIT
},
855 {"intel_syntax", set_intel_syntax
, 1},
856 {"att_syntax", set_intel_syntax
, 0},
857 {"intel_mnemonic", set_intel_mnemonic
, 1},
858 {"att_mnemonic", set_intel_mnemonic
, 0},
859 {"allow_index_reg", set_allow_index_reg
, 1},
860 {"disallow_index_reg", set_allow_index_reg
, 0},
861 {"sse_check", set_check
, 0},
862 {"operand_check", set_check
, 1},
863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
864 {"largecomm", handle_large_common
, 0},
866 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
867 {"loc", dwarf2_directive_loc
, 0},
868 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
871 {"secrel32", pe_directive_secrel
, 0},
876 /* For interface with expression (). */
877 extern char *input_line_pointer
;
879 /* Hash table for instruction mnemonic lookup. */
880 static struct hash_control
*op_hash
;
882 /* Hash table for register lookup. */
883 static struct hash_control
*reg_hash
;
886 i386_align_code (fragS
*fragP
, int count
)
888 /* Various efficient no-op patterns for aligning code labels.
889 Note: Don't try to assemble the instructions in the comments.
890 0L and 0w are not legal. */
891 static const char f32_1
[] =
893 static const char f32_2
[] =
894 {0x66,0x90}; /* xchg %ax,%ax */
895 static const char f32_3
[] =
896 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
897 static const char f32_4
[] =
898 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
899 static const char f32_5
[] =
901 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
902 static const char f32_6
[] =
903 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
904 static const char f32_7
[] =
905 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
906 static const char f32_8
[] =
908 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
909 static const char f32_9
[] =
910 {0x89,0xf6, /* movl %esi,%esi */
911 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
912 static const char f32_10
[] =
913 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
914 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
915 static const char f32_11
[] =
916 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
917 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
918 static const char f32_12
[] =
919 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
920 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
921 static const char f32_13
[] =
922 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
923 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
924 static const char f32_14
[] =
925 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
926 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
927 static const char f16_3
[] =
928 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
929 static const char f16_4
[] =
930 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
931 static const char f16_5
[] =
933 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
934 static const char f16_6
[] =
935 {0x89,0xf6, /* mov %si,%si */
936 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
937 static const char f16_7
[] =
938 {0x8d,0x74,0x00, /* lea 0(%si),%si */
939 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
940 static const char f16_8
[] =
941 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
942 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
943 static const char jump_31
[] =
944 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
945 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
946 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
947 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
948 static const char *const f32_patt
[] = {
949 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
950 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
952 static const char *const f16_patt
[] = {
953 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
956 static const char alt_3
[] =
958 /* nopl 0(%[re]ax) */
959 static const char alt_4
[] =
960 {0x0f,0x1f,0x40,0x00};
961 /* nopl 0(%[re]ax,%[re]ax,1) */
962 static const char alt_5
[] =
963 {0x0f,0x1f,0x44,0x00,0x00};
964 /* nopw 0(%[re]ax,%[re]ax,1) */
965 static const char alt_6
[] =
966 {0x66,0x0f,0x1f,0x44,0x00,0x00};
967 /* nopl 0L(%[re]ax) */
968 static const char alt_7
[] =
969 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
970 /* nopl 0L(%[re]ax,%[re]ax,1) */
971 static const char alt_8
[] =
972 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
973 /* nopw 0L(%[re]ax,%[re]ax,1) */
974 static const char alt_9
[] =
975 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
977 static const char alt_10
[] =
978 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
980 nopw %cs:0L(%[re]ax,%[re]ax,1) */
981 static const char alt_long_11
[] =
983 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
986 nopw %cs:0L(%[re]ax,%[re]ax,1) */
987 static const char alt_long_12
[] =
990 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
994 nopw %cs:0L(%[re]ax,%[re]ax,1) */
995 static const char alt_long_13
[] =
999 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1004 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1005 static const char alt_long_14
[] =
1010 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1016 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1017 static const char alt_long_15
[] =
1023 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1024 /* nopl 0(%[re]ax,%[re]ax,1)
1025 nopw 0(%[re]ax,%[re]ax,1) */
1026 static const char alt_short_11
[] =
1027 {0x0f,0x1f,0x44,0x00,0x00,
1028 0x66,0x0f,0x1f,0x44,0x00,0x00};
1029 /* nopw 0(%[re]ax,%[re]ax,1)
1030 nopw 0(%[re]ax,%[re]ax,1) */
1031 static const char alt_short_12
[] =
1032 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1033 0x66,0x0f,0x1f,0x44,0x00,0x00};
1034 /* nopw 0(%[re]ax,%[re]ax,1)
1036 static const char alt_short_13
[] =
1037 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1038 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1041 static const char alt_short_14
[] =
1042 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1043 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1045 nopl 0L(%[re]ax,%[re]ax,1) */
1046 static const char alt_short_15
[] =
1047 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1048 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1049 static const char *const alt_short_patt
[] = {
1050 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1051 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1052 alt_short_14
, alt_short_15
1054 static const char *const alt_long_patt
[] = {
1055 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1056 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1057 alt_long_14
, alt_long_15
1060 /* Only align for at least a positive non-zero boundary. */
1061 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1064 /* We need to decide which NOP sequence to use for 32bit and
1065 64bit. When -mtune= is used:
1067 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1068 PROCESSOR_GENERIC32, f32_patt will be used.
1069 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1070 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1071 PROCESSOR_GENERIC64, alt_long_patt will be used.
1072 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1073 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1076 When -mtune= isn't used, alt_long_patt will be used if
1077 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1080 When -march= or .arch is used, we can't use anything beyond
1081 cpu_arch_isa_flags. */
1083 if (flag_code
== CODE_16BIT
)
1087 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1089 /* Adjust jump offset. */
1090 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1093 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1094 f16_patt
[count
- 1], count
);
1098 const char *const *patt
= NULL
;
1100 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1102 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1103 switch (cpu_arch_tune
)
1105 case PROCESSOR_UNKNOWN
:
1106 /* We use cpu_arch_isa_flags to check if we SHOULD
1107 optimize with nops. */
1108 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1109 patt
= alt_long_patt
;
1113 case PROCESSOR_PENTIUM4
:
1114 case PROCESSOR_NOCONA
:
1115 case PROCESSOR_CORE
:
1116 case PROCESSOR_CORE2
:
1117 case PROCESSOR_COREI7
:
1118 case PROCESSOR_L1OM
:
1119 case PROCESSOR_K1OM
:
1120 case PROCESSOR_GENERIC64
:
1121 patt
= alt_long_patt
;
1124 case PROCESSOR_ATHLON
:
1126 case PROCESSOR_AMDFAM10
:
1129 patt
= alt_short_patt
;
1131 case PROCESSOR_I386
:
1132 case PROCESSOR_I486
:
1133 case PROCESSOR_PENTIUM
:
1134 case PROCESSOR_PENTIUMPRO
:
1135 case PROCESSOR_GENERIC32
:
1142 switch (fragP
->tc_frag_data
.tune
)
1144 case PROCESSOR_UNKNOWN
:
1145 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1146 PROCESSOR_UNKNOWN. */
1150 case PROCESSOR_I386
:
1151 case PROCESSOR_I486
:
1152 case PROCESSOR_PENTIUM
:
1154 case PROCESSOR_ATHLON
:
1156 case PROCESSOR_AMDFAM10
:
1159 case PROCESSOR_GENERIC32
:
1160 /* We use cpu_arch_isa_flags to check if we CAN optimize
1162 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1163 patt
= alt_short_patt
;
1167 case PROCESSOR_PENTIUMPRO
:
1168 case PROCESSOR_PENTIUM4
:
1169 case PROCESSOR_NOCONA
:
1170 case PROCESSOR_CORE
:
1171 case PROCESSOR_CORE2
:
1172 case PROCESSOR_COREI7
:
1173 case PROCESSOR_L1OM
:
1174 case PROCESSOR_K1OM
:
1175 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1176 patt
= alt_long_patt
;
1180 case PROCESSOR_GENERIC64
:
1181 patt
= alt_long_patt
;
1186 if (patt
== f32_patt
)
1188 /* If the padding is less than 15 bytes, we use the normal
1189 ones. Otherwise, we use a jump instruction and adjust
1193 /* For 64bit, the limit is 3 bytes. */
1194 if (flag_code
== CODE_64BIT
1195 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1200 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1201 patt
[count
- 1], count
);
1204 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1206 /* Adjust jump offset. */
1207 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1212 /* Maximum length of an instruction is 15 byte. If the
1213 padding is greater than 15 bytes and we don't use jump,
1214 we have to break it into smaller pieces. */
1215 int padding
= count
;
1216 while (padding
> 15)
1219 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1224 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1225 patt
[padding
- 1], padding
);
1228 fragP
->fr_var
= count
;
1232 operand_type_all_zero (const union i386_operand_type
*x
)
1234 switch (ARRAY_SIZE(x
->array
))
1243 return !x
->array
[0];
1250 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1252 switch (ARRAY_SIZE(x
->array
))
1267 operand_type_equal (const union i386_operand_type
*x
,
1268 const union i386_operand_type
*y
)
1270 switch (ARRAY_SIZE(x
->array
))
1273 if (x
->array
[2] != y
->array
[2])
1276 if (x
->array
[1] != y
->array
[1])
1279 return x
->array
[0] == y
->array
[0];
1287 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1289 switch (ARRAY_SIZE(x
->array
))
1298 return !x
->array
[0];
1305 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1307 switch (ARRAY_SIZE(x
->array
))
1322 cpu_flags_equal (const union i386_cpu_flags
*x
,
1323 const union i386_cpu_flags
*y
)
1325 switch (ARRAY_SIZE(x
->array
))
1328 if (x
->array
[2] != y
->array
[2])
1331 if (x
->array
[1] != y
->array
[1])
1334 return x
->array
[0] == y
->array
[0];
1342 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1344 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1345 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1348 static INLINE i386_cpu_flags
1349 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1351 switch (ARRAY_SIZE (x
.array
))
1354 x
.array
[2] &= y
.array
[2];
1356 x
.array
[1] &= y
.array
[1];
1358 x
.array
[0] &= y
.array
[0];
1366 static INLINE i386_cpu_flags
1367 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1369 switch (ARRAY_SIZE (x
.array
))
1372 x
.array
[2] |= y
.array
[2];
1374 x
.array
[1] |= y
.array
[1];
1376 x
.array
[0] |= y
.array
[0];
1384 static INLINE i386_cpu_flags
1385 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1387 switch (ARRAY_SIZE (x
.array
))
1390 x
.array
[2] &= ~y
.array
[2];
1392 x
.array
[1] &= ~y
.array
[1];
1394 x
.array
[0] &= ~y
.array
[0];
1402 #define CPU_FLAGS_ARCH_MATCH 0x1
1403 #define CPU_FLAGS_64BIT_MATCH 0x2
1404 #define CPU_FLAGS_AES_MATCH 0x4
1405 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1406 #define CPU_FLAGS_AVX_MATCH 0x10
1408 #define CPU_FLAGS_32BIT_MATCH \
1409 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1410 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1411 #define CPU_FLAGS_PERFECT_MATCH \
1412 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1414 /* Return CPU flags match bits. */
1417 cpu_flags_match (const insn_template
*t
)
1419 i386_cpu_flags x
= t
->cpu_flags
;
1420 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1422 x
.bitfield
.cpu64
= 0;
1423 x
.bitfield
.cpuno64
= 0;
1425 if (cpu_flags_all_zero (&x
))
1427 /* This instruction is available on all archs. */
1428 match
|= CPU_FLAGS_32BIT_MATCH
;
1432 /* This instruction is available only on some archs. */
1433 i386_cpu_flags cpu
= cpu_arch_flags
;
1435 cpu
.bitfield
.cpu64
= 0;
1436 cpu
.bitfield
.cpuno64
= 0;
1437 cpu
= cpu_flags_and (x
, cpu
);
1438 if (!cpu_flags_all_zero (&cpu
))
1440 if (x
.bitfield
.cpuavx
)
1442 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1443 if (cpu
.bitfield
.cpuavx
)
1445 /* Check SSE2AVX. */
1446 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1448 match
|= (CPU_FLAGS_ARCH_MATCH
1449 | CPU_FLAGS_AVX_MATCH
);
1451 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1452 match
|= CPU_FLAGS_AES_MATCH
;
1454 if (!x
.bitfield
.cpupclmul
1455 || cpu
.bitfield
.cpupclmul
)
1456 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1460 match
|= CPU_FLAGS_ARCH_MATCH
;
1463 match
|= CPU_FLAGS_32BIT_MATCH
;
1469 static INLINE i386_operand_type
1470 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1472 switch (ARRAY_SIZE (x
.array
))
1475 x
.array
[2] &= y
.array
[2];
1477 x
.array
[1] &= y
.array
[1];
1479 x
.array
[0] &= y
.array
[0];
1487 static INLINE i386_operand_type
1488 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1490 switch (ARRAY_SIZE (x
.array
))
1493 x
.array
[2] |= y
.array
[2];
1495 x
.array
[1] |= y
.array
[1];
1497 x
.array
[0] |= y
.array
[0];
1505 static INLINE i386_operand_type
1506 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1508 switch (ARRAY_SIZE (x
.array
))
1511 x
.array
[2] ^= y
.array
[2];
1513 x
.array
[1] ^= y
.array
[1];
1515 x
.array
[0] ^= y
.array
[0];
1523 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1524 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1525 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1526 static const i386_operand_type inoutportreg
1527 = OPERAND_TYPE_INOUTPORTREG
;
1528 static const i386_operand_type reg16_inoutportreg
1529 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1530 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1531 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1532 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1533 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1534 static const i386_operand_type anydisp
1535 = OPERAND_TYPE_ANYDISP
;
1536 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1537 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1538 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1539 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1540 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1541 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1542 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1543 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1544 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1545 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1546 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1547 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1558 operand_type_check (i386_operand_type t
, enum operand_type c
)
1563 return (t
.bitfield
.reg8
1566 || t
.bitfield
.reg64
);
1569 return (t
.bitfield
.imm8
1573 || t
.bitfield
.imm32s
1574 || t
.bitfield
.imm64
);
1577 return (t
.bitfield
.disp8
1578 || t
.bitfield
.disp16
1579 || t
.bitfield
.disp32
1580 || t
.bitfield
.disp32s
1581 || t
.bitfield
.disp64
);
1584 return (t
.bitfield
.disp8
1585 || t
.bitfield
.disp16
1586 || t
.bitfield
.disp32
1587 || t
.bitfield
.disp32s
1588 || t
.bitfield
.disp64
1589 || t
.bitfield
.baseindex
);
1598 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1599 operand J for instruction template T. */
1602 match_reg_size (const insn_template
*t
, unsigned int j
)
1604 return !((i
.types
[j
].bitfield
.byte
1605 && !t
->operand_types
[j
].bitfield
.byte
)
1606 || (i
.types
[j
].bitfield
.word
1607 && !t
->operand_types
[j
].bitfield
.word
)
1608 || (i
.types
[j
].bitfield
.dword
1609 && !t
->operand_types
[j
].bitfield
.dword
)
1610 || (i
.types
[j
].bitfield
.qword
1611 && !t
->operand_types
[j
].bitfield
.qword
));
1614 /* Return 1 if there is no conflict in any size on operand J for
1615 instruction template T. */
1618 match_mem_size (const insn_template
*t
, unsigned int j
)
1620 return (match_reg_size (t
, j
)
1621 && !((i
.types
[j
].bitfield
.unspecified
1622 && !t
->operand_types
[j
].bitfield
.unspecified
)
1623 || (i
.types
[j
].bitfield
.fword
1624 && !t
->operand_types
[j
].bitfield
.fword
)
1625 || (i
.types
[j
].bitfield
.tbyte
1626 && !t
->operand_types
[j
].bitfield
.tbyte
)
1627 || (i
.types
[j
].bitfield
.xmmword
1628 && !t
->operand_types
[j
].bitfield
.xmmword
)
1629 || (i
.types
[j
].bitfield
.ymmword
1630 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1633 /* Return 1 if there is no size conflict on any operands for
1634 instruction template T. */
1637 operand_size_match (const insn_template
*t
)
1642 /* Don't check jump instructions. */
1643 if (t
->opcode_modifier
.jump
1644 || t
->opcode_modifier
.jumpbyte
1645 || t
->opcode_modifier
.jumpdword
1646 || t
->opcode_modifier
.jumpintersegment
)
1649 /* Check memory and accumulator operand size. */
1650 for (j
= 0; j
< i
.operands
; j
++)
1652 if (t
->operand_types
[j
].bitfield
.anysize
)
1655 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1661 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1670 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1673 i
.error
= operand_size_mismatch
;
1677 /* Check reverse. */
1678 gas_assert (i
.operands
== 2);
1681 for (j
= 0; j
< 2; j
++)
1683 if (t
->operand_types
[j
].bitfield
.acc
1684 && !match_reg_size (t
, j
? 0 : 1))
1687 if (i
.types
[j
].bitfield
.mem
1688 && !match_mem_size (t
, j
? 0 : 1))
1696 operand_type_match (i386_operand_type overlap
,
1697 i386_operand_type given
)
1699 i386_operand_type temp
= overlap
;
1701 temp
.bitfield
.jumpabsolute
= 0;
1702 temp
.bitfield
.unspecified
= 0;
1703 temp
.bitfield
.byte
= 0;
1704 temp
.bitfield
.word
= 0;
1705 temp
.bitfield
.dword
= 0;
1706 temp
.bitfield
.fword
= 0;
1707 temp
.bitfield
.qword
= 0;
1708 temp
.bitfield
.tbyte
= 0;
1709 temp
.bitfield
.xmmword
= 0;
1710 temp
.bitfield
.ymmword
= 0;
1711 if (operand_type_all_zero (&temp
))
1714 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1715 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1719 i
.error
= operand_type_mismatch
;
1723 /* If given types g0 and g1 are registers they must be of the same type
1724 unless the expected operand type register overlap is null.
1725 Note that Acc in a template matches every size of reg. */
1728 operand_type_register_match (i386_operand_type m0
,
1729 i386_operand_type g0
,
1730 i386_operand_type t0
,
1731 i386_operand_type m1
,
1732 i386_operand_type g1
,
1733 i386_operand_type t1
)
1735 if (!operand_type_check (g0
, reg
))
1738 if (!operand_type_check (g1
, reg
))
1741 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1742 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1743 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1744 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1747 if (m0
.bitfield
.acc
)
1749 t0
.bitfield
.reg8
= 1;
1750 t0
.bitfield
.reg16
= 1;
1751 t0
.bitfield
.reg32
= 1;
1752 t0
.bitfield
.reg64
= 1;
1755 if (m1
.bitfield
.acc
)
1757 t1
.bitfield
.reg8
= 1;
1758 t1
.bitfield
.reg16
= 1;
1759 t1
.bitfield
.reg32
= 1;
1760 t1
.bitfield
.reg64
= 1;
1763 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1764 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1765 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1766 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1769 i
.error
= register_type_mismatch
;
1774 static INLINE
unsigned int
1775 register_number (const reg_entry
*r
)
1777 unsigned int nr
= r
->reg_num
;
1779 if (r
->reg_flags
& RegRex
)
1785 static INLINE
unsigned int
1786 mode_from_disp_size (i386_operand_type t
)
1788 if (t
.bitfield
.disp8
)
1790 else if (t
.bitfield
.disp16
1791 || t
.bitfield
.disp32
1792 || t
.bitfield
.disp32s
)
1799 fits_in_signed_byte (offsetT num
)
1801 return (num
>= -128) && (num
<= 127);
1805 fits_in_unsigned_byte (offsetT num
)
1807 return (num
& 0xff) == num
;
1811 fits_in_unsigned_word (offsetT num
)
1813 return (num
& 0xffff) == num
;
1817 fits_in_signed_word (offsetT num
)
1819 return (-32768 <= num
) && (num
<= 32767);
1823 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1828 return (!(((offsetT
) -1 << 31) & num
)
1829 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1831 } /* fits_in_signed_long() */
1834 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1839 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1841 } /* fits_in_unsigned_long() */
1844 fits_in_imm4 (offsetT num
)
1846 return (num
& 0xf) == num
;
1849 static i386_operand_type
1850 smallest_imm_type (offsetT num
)
1852 i386_operand_type t
;
1854 operand_type_set (&t
, 0);
1855 t
.bitfield
.imm64
= 1;
1857 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1859 /* This code is disabled on the 486 because all the Imm1 forms
1860 in the opcode table are slower on the i486. They're the
1861 versions with the implicitly specified single-position
1862 displacement, which has another syntax if you really want to
1864 t
.bitfield
.imm1
= 1;
1865 t
.bitfield
.imm8
= 1;
1866 t
.bitfield
.imm8s
= 1;
1867 t
.bitfield
.imm16
= 1;
1868 t
.bitfield
.imm32
= 1;
1869 t
.bitfield
.imm32s
= 1;
1871 else if (fits_in_signed_byte (num
))
1873 t
.bitfield
.imm8
= 1;
1874 t
.bitfield
.imm8s
= 1;
1875 t
.bitfield
.imm16
= 1;
1876 t
.bitfield
.imm32
= 1;
1877 t
.bitfield
.imm32s
= 1;
1879 else if (fits_in_unsigned_byte (num
))
1881 t
.bitfield
.imm8
= 1;
1882 t
.bitfield
.imm16
= 1;
1883 t
.bitfield
.imm32
= 1;
1884 t
.bitfield
.imm32s
= 1;
1886 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1888 t
.bitfield
.imm16
= 1;
1889 t
.bitfield
.imm32
= 1;
1890 t
.bitfield
.imm32s
= 1;
1892 else if (fits_in_signed_long (num
))
1894 t
.bitfield
.imm32
= 1;
1895 t
.bitfield
.imm32s
= 1;
1897 else if (fits_in_unsigned_long (num
))
1898 t
.bitfield
.imm32
= 1;
1904 offset_in_range (offsetT val
, int size
)
1910 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1911 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1912 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1914 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1920 /* If BFD64, sign extend val for 32bit address mode. */
1921 if (flag_code
!= CODE_64BIT
1922 || i
.prefix
[ADDR_PREFIX
])
1923 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1924 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1927 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1929 char buf1
[40], buf2
[40];
1931 sprint_value (buf1
, val
);
1932 sprint_value (buf2
, val
& mask
);
1933 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1947 a. PREFIX_EXIST if attempting to add a prefix where one from the
1948 same class already exists.
1949 b. PREFIX_LOCK if lock prefix is added.
1950 c. PREFIX_REP if rep/repne prefix is added.
1951 d. PREFIX_OTHER if other prefix is added.
1954 static enum PREFIX_GROUP
1955 add_prefix (unsigned int prefix
)
1957 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1960 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1961 && flag_code
== CODE_64BIT
)
1963 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1964 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1965 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1976 case CS_PREFIX_OPCODE
:
1977 case DS_PREFIX_OPCODE
:
1978 case ES_PREFIX_OPCODE
:
1979 case FS_PREFIX_OPCODE
:
1980 case GS_PREFIX_OPCODE
:
1981 case SS_PREFIX_OPCODE
:
1985 case REPNE_PREFIX_OPCODE
:
1986 case REPE_PREFIX_OPCODE
:
1991 case LOCK_PREFIX_OPCODE
:
2000 case ADDR_PREFIX_OPCODE
:
2004 case DATA_PREFIX_OPCODE
:
2008 if (i
.prefix
[q
] != 0)
2016 i
.prefix
[q
] |= prefix
;
2019 as_bad (_("same type of prefix used twice"));
2025 update_code_flag (int value
, int check
)
2027 PRINTF_LIKE ((*as_error
));
2029 flag_code
= (enum flag_code
) value
;
2030 if (flag_code
== CODE_64BIT
)
2032 cpu_arch_flags
.bitfield
.cpu64
= 1;
2033 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2037 cpu_arch_flags
.bitfield
.cpu64
= 0;
2038 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2040 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2043 as_error
= as_fatal
;
2046 (*as_error
) (_("64bit mode not supported on `%s'."),
2047 cpu_arch_name
? cpu_arch_name
: default_arch
);
2049 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2052 as_error
= as_fatal
;
2055 (*as_error
) (_("32bit mode not supported on `%s'."),
2056 cpu_arch_name
? cpu_arch_name
: default_arch
);
2058 stackop_size
= '\0';
2062 set_code_flag (int value
)
2064 update_code_flag (value
, 0);
2068 set_16bit_gcc_code_flag (int new_code_flag
)
2070 flag_code
= (enum flag_code
) new_code_flag
;
2071 if (flag_code
!= CODE_16BIT
)
2073 cpu_arch_flags
.bitfield
.cpu64
= 0;
2074 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2075 stackop_size
= LONG_MNEM_SUFFIX
;
2079 set_intel_syntax (int syntax_flag
)
2081 /* Find out if register prefixing is specified. */
2082 int ask_naked_reg
= 0;
2085 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2087 char *string
= input_line_pointer
;
2088 int e
= get_symbol_end ();
2090 if (strcmp (string
, "prefix") == 0)
2092 else if (strcmp (string
, "noprefix") == 0)
2095 as_bad (_("bad argument to syntax directive."));
2096 *input_line_pointer
= e
;
2098 demand_empty_rest_of_line ();
2100 intel_syntax
= syntax_flag
;
2102 if (ask_naked_reg
== 0)
2103 allow_naked_reg
= (intel_syntax
2104 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2106 allow_naked_reg
= (ask_naked_reg
< 0);
2108 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2110 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2111 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2112 register_prefix
= allow_naked_reg
? "" : "%";
2116 set_intel_mnemonic (int mnemonic_flag
)
2118 intel_mnemonic
= mnemonic_flag
;
2122 set_allow_index_reg (int flag
)
2124 allow_index_reg
= flag
;
2128 set_check (int what
)
2130 enum check_kind
*kind
;
2135 kind
= &operand_check
;
2146 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2148 char *string
= input_line_pointer
;
2149 int e
= get_symbol_end ();
2151 if (strcmp (string
, "none") == 0)
2153 else if (strcmp (string
, "warning") == 0)
2154 *kind
= check_warning
;
2155 else if (strcmp (string
, "error") == 0)
2156 *kind
= check_error
;
2158 as_bad (_("bad argument to %s_check directive."), str
);
2159 *input_line_pointer
= e
;
2162 as_bad (_("missing argument for %s_check directive"), str
);
2164 demand_empty_rest_of_line ();
2168 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2169 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2171 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2172 static const char *arch
;
2174 /* Intel LIOM is only supported on ELF. */
2180 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2181 use default_arch. */
2182 arch
= cpu_arch_name
;
2184 arch
= default_arch
;
2187 /* If we are targeting Intel L1OM, we must enable it. */
2188 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2189 || new_flag
.bitfield
.cpul1om
)
2192 /* If we are targeting Intel K1OM, we must enable it. */
2193 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2194 || new_flag
.bitfield
.cpuk1om
)
2197 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2202 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2206 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2208 char *string
= input_line_pointer
;
2209 int e
= get_symbol_end ();
2211 i386_cpu_flags flags
;
2213 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2215 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2217 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2221 cpu_arch_name
= cpu_arch
[j
].name
;
2222 cpu_sub_arch_name
= NULL
;
2223 cpu_arch_flags
= cpu_arch
[j
].flags
;
2224 if (flag_code
== CODE_64BIT
)
2226 cpu_arch_flags
.bitfield
.cpu64
= 1;
2227 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2231 cpu_arch_flags
.bitfield
.cpu64
= 0;
2232 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2234 cpu_arch_isa
= cpu_arch
[j
].type
;
2235 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2236 if (!cpu_arch_tune_set
)
2238 cpu_arch_tune
= cpu_arch_isa
;
2239 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2244 if (!cpu_arch
[j
].negated
)
2245 flags
= cpu_flags_or (cpu_arch_flags
,
2248 flags
= cpu_flags_and_not (cpu_arch_flags
,
2250 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2252 if (cpu_sub_arch_name
)
2254 char *name
= cpu_sub_arch_name
;
2255 cpu_sub_arch_name
= concat (name
,
2257 (const char *) NULL
);
2261 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2262 cpu_arch_flags
= flags
;
2263 cpu_arch_isa_flags
= flags
;
2265 *input_line_pointer
= e
;
2266 demand_empty_rest_of_line ();
2270 if (j
>= ARRAY_SIZE (cpu_arch
))
2271 as_bad (_("no such architecture: `%s'"), string
);
2273 *input_line_pointer
= e
;
2276 as_bad (_("missing cpu architecture"));
2278 no_cond_jump_promotion
= 0;
2279 if (*input_line_pointer
== ','
2280 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2282 char *string
= ++input_line_pointer
;
2283 int e
= get_symbol_end ();
2285 if (strcmp (string
, "nojumps") == 0)
2286 no_cond_jump_promotion
= 1;
2287 else if (strcmp (string
, "jumps") == 0)
2290 as_bad (_("no such architecture modifier: `%s'"), string
);
2292 *input_line_pointer
= e
;
2295 demand_empty_rest_of_line ();
2298 enum bfd_architecture
2301 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2303 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2304 || flag_code
!= CODE_64BIT
)
2305 as_fatal (_("Intel L1OM is 64bit ELF only"));
2306 return bfd_arch_l1om
;
2308 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2310 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2311 || flag_code
!= CODE_64BIT
)
2312 as_fatal (_("Intel K1OM is 64bit ELF only"));
2313 return bfd_arch_k1om
;
2316 return bfd_arch_i386
;
2322 if (!strncmp (default_arch
, "x86_64", 6))
2324 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2326 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2327 || default_arch
[6] != '\0')
2328 as_fatal (_("Intel L1OM is 64bit ELF only"));
2329 return bfd_mach_l1om
;
2331 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2333 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2334 || default_arch
[6] != '\0')
2335 as_fatal (_("Intel K1OM is 64bit ELF only"));
2336 return bfd_mach_k1om
;
2338 else if (default_arch
[6] == '\0')
2339 return bfd_mach_x86_64
;
2341 return bfd_mach_x64_32
;
2343 else if (!strcmp (default_arch
, "i386"))
2344 return bfd_mach_i386_i386
;
2346 as_fatal (_("unknown architecture"));
2352 const char *hash_err
;
2354 /* Initialize op_hash hash table. */
2355 op_hash
= hash_new ();
2358 const insn_template
*optab
;
2359 templates
*core_optab
;
2361 /* Setup for loop. */
2363 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2364 core_optab
->start
= optab
;
2369 if (optab
->name
== NULL
2370 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2372 /* different name --> ship out current template list;
2373 add to hash table; & begin anew. */
2374 core_optab
->end
= optab
;
2375 hash_err
= hash_insert (op_hash
,
2377 (void *) core_optab
);
2380 as_fatal (_("can't hash %s: %s"),
2384 if (optab
->name
== NULL
)
2386 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2387 core_optab
->start
= optab
;
2392 /* Initialize reg_hash hash table. */
2393 reg_hash
= hash_new ();
2395 const reg_entry
*regtab
;
2396 unsigned int regtab_size
= i386_regtab_size
;
2398 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2400 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2402 as_fatal (_("can't hash %s: %s"),
2408 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2413 for (c
= 0; c
< 256; c
++)
2418 mnemonic_chars
[c
] = c
;
2419 register_chars
[c
] = c
;
2420 operand_chars
[c
] = c
;
2422 else if (ISLOWER (c
))
2424 mnemonic_chars
[c
] = c
;
2425 register_chars
[c
] = c
;
2426 operand_chars
[c
] = c
;
2428 else if (ISUPPER (c
))
2430 mnemonic_chars
[c
] = TOLOWER (c
);
2431 register_chars
[c
] = mnemonic_chars
[c
];
2432 operand_chars
[c
] = c
;
2435 if (ISALPHA (c
) || ISDIGIT (c
))
2436 identifier_chars
[c
] = c
;
2439 identifier_chars
[c
] = c
;
2440 operand_chars
[c
] = c
;
2445 identifier_chars
['@'] = '@';
2448 identifier_chars
['?'] = '?';
2449 operand_chars
['?'] = '?';
2451 digit_chars
['-'] = '-';
2452 mnemonic_chars
['_'] = '_';
2453 mnemonic_chars
['-'] = '-';
2454 mnemonic_chars
['.'] = '.';
2455 identifier_chars
['_'] = '_';
2456 identifier_chars
['.'] = '.';
2458 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2459 operand_chars
[(unsigned char) *p
] = *p
;
2462 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2465 record_alignment (text_section
, 2);
2466 record_alignment (data_section
, 2);
2467 record_alignment (bss_section
, 2);
2471 if (flag_code
== CODE_64BIT
)
2473 #if defined (OBJ_COFF) && defined (TE_PE)
2474 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2477 x86_dwarf2_return_column
= 16;
2479 x86_cie_data_alignment
= -8;
2483 x86_dwarf2_return_column
= 8;
2484 x86_cie_data_alignment
= -4;
2489 i386_print_statistics (FILE *file
)
2491 hash_print_statistics (file
, "i386 opcode", op_hash
);
2492 hash_print_statistics (file
, "i386 register", reg_hash
);
2497 /* Debugging routines for md_assemble. */
2498 static void pte (insn_template
*);
2499 static void pt (i386_operand_type
);
2500 static void pe (expressionS
*);
2501 static void ps (symbolS
*);
2504 pi (char *line
, i386_insn
*x
)
2508 fprintf (stdout
, "%s: template ", line
);
2510 fprintf (stdout
, " address: base %s index %s scale %x\n",
2511 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2512 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2513 x
->log2_scale_factor
);
2514 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2515 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2516 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2517 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2518 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2519 (x
->rex
& REX_W
) != 0,
2520 (x
->rex
& REX_R
) != 0,
2521 (x
->rex
& REX_X
) != 0,
2522 (x
->rex
& REX_B
) != 0);
2523 for (j
= 0; j
< x
->operands
; j
++)
2525 fprintf (stdout
, " #%d: ", j
+ 1);
2527 fprintf (stdout
, "\n");
2528 if (x
->types
[j
].bitfield
.reg8
2529 || x
->types
[j
].bitfield
.reg16
2530 || x
->types
[j
].bitfield
.reg32
2531 || x
->types
[j
].bitfield
.reg64
2532 || x
->types
[j
].bitfield
.regmmx
2533 || x
->types
[j
].bitfield
.regxmm
2534 || x
->types
[j
].bitfield
.regymm
2535 || x
->types
[j
].bitfield
.sreg2
2536 || x
->types
[j
].bitfield
.sreg3
2537 || x
->types
[j
].bitfield
.control
2538 || x
->types
[j
].bitfield
.debug
2539 || x
->types
[j
].bitfield
.test
)
2540 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2541 if (operand_type_check (x
->types
[j
], imm
))
2543 if (operand_type_check (x
->types
[j
], disp
))
2544 pe (x
->op
[j
].disps
);
2549 pte (insn_template
*t
)
2552 fprintf (stdout
, " %d operands ", t
->operands
);
2553 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2554 if (t
->extension_opcode
!= None
)
2555 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2556 if (t
->opcode_modifier
.d
)
2557 fprintf (stdout
, "D");
2558 if (t
->opcode_modifier
.w
)
2559 fprintf (stdout
, "W");
2560 fprintf (stdout
, "\n");
2561 for (j
= 0; j
< t
->operands
; j
++)
2563 fprintf (stdout
, " #%d type ", j
+ 1);
2564 pt (t
->operand_types
[j
]);
2565 fprintf (stdout
, "\n");
2572 fprintf (stdout
, " operation %d\n", e
->X_op
);
2573 fprintf (stdout
, " add_number %ld (%lx)\n",
2574 (long) e
->X_add_number
, (long) e
->X_add_number
);
2575 if (e
->X_add_symbol
)
2577 fprintf (stdout
, " add_symbol ");
2578 ps (e
->X_add_symbol
);
2579 fprintf (stdout
, "\n");
2583 fprintf (stdout
, " op_symbol ");
2584 ps (e
->X_op_symbol
);
2585 fprintf (stdout
, "\n");
2592 fprintf (stdout
, "%s type %s%s",
2594 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2595 segment_name (S_GET_SEGMENT (s
)));
2598 static struct type_name
2600 i386_operand_type mask
;
2603 const type_names
[] =
2605 { OPERAND_TYPE_REG8
, "r8" },
2606 { OPERAND_TYPE_REG16
, "r16" },
2607 { OPERAND_TYPE_REG32
, "r32" },
2608 { OPERAND_TYPE_REG64
, "r64" },
2609 { OPERAND_TYPE_IMM8
, "i8" },
2610 { OPERAND_TYPE_IMM8
, "i8s" },
2611 { OPERAND_TYPE_IMM16
, "i16" },
2612 { OPERAND_TYPE_IMM32
, "i32" },
2613 { OPERAND_TYPE_IMM32S
, "i32s" },
2614 { OPERAND_TYPE_IMM64
, "i64" },
2615 { OPERAND_TYPE_IMM1
, "i1" },
2616 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2617 { OPERAND_TYPE_DISP8
, "d8" },
2618 { OPERAND_TYPE_DISP16
, "d16" },
2619 { OPERAND_TYPE_DISP32
, "d32" },
2620 { OPERAND_TYPE_DISP32S
, "d32s" },
2621 { OPERAND_TYPE_DISP64
, "d64" },
2622 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2623 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2624 { OPERAND_TYPE_CONTROL
, "control reg" },
2625 { OPERAND_TYPE_TEST
, "test reg" },
2626 { OPERAND_TYPE_DEBUG
, "debug reg" },
2627 { OPERAND_TYPE_FLOATREG
, "FReg" },
2628 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2629 { OPERAND_TYPE_SREG2
, "SReg2" },
2630 { OPERAND_TYPE_SREG3
, "SReg3" },
2631 { OPERAND_TYPE_ACC
, "Acc" },
2632 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2633 { OPERAND_TYPE_REGMMX
, "rMMX" },
2634 { OPERAND_TYPE_REGXMM
, "rXMM" },
2635 { OPERAND_TYPE_REGYMM
, "rYMM" },
2636 { OPERAND_TYPE_ESSEG
, "es" },
2640 pt (i386_operand_type t
)
2643 i386_operand_type a
;
2645 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2647 a
= operand_type_and (t
, type_names
[j
].mask
);
2648 if (!operand_type_all_zero (&a
))
2649 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2654 #endif /* DEBUG386 */
2656 static bfd_reloc_code_real_type
2657 reloc (unsigned int size
,
2660 bfd_reloc_code_real_type other
)
2662 if (other
!= NO_RELOC
)
2664 reloc_howto_type
*rel
;
2669 case BFD_RELOC_X86_64_GOT32
:
2670 return BFD_RELOC_X86_64_GOT64
;
2672 case BFD_RELOC_X86_64_PLTOFF64
:
2673 return BFD_RELOC_X86_64_PLTOFF64
;
2675 case BFD_RELOC_X86_64_GOTPC32
:
2676 other
= BFD_RELOC_X86_64_GOTPC64
;
2678 case BFD_RELOC_X86_64_GOTPCREL
:
2679 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2681 case BFD_RELOC_X86_64_TPOFF32
:
2682 other
= BFD_RELOC_X86_64_TPOFF64
;
2684 case BFD_RELOC_X86_64_DTPOFF32
:
2685 other
= BFD_RELOC_X86_64_DTPOFF64
;
2691 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2692 if (other
== BFD_RELOC_SIZE32
)
2695 return BFD_RELOC_SIZE64
;
2697 as_bad (_("there are no pc-relative size relocations"));
2701 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2702 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2705 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2707 as_bad (_("unknown relocation (%u)"), other
);
2708 else if (size
!= bfd_get_reloc_size (rel
))
2709 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2710 bfd_get_reloc_size (rel
),
2712 else if (pcrel
&& !rel
->pc_relative
)
2713 as_bad (_("non-pc-relative relocation for pc-relative field"));
2714 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2716 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2718 as_bad (_("relocated field and relocation type differ in signedness"));
2727 as_bad (_("there are no unsigned pc-relative relocations"));
2730 case 1: return BFD_RELOC_8_PCREL
;
2731 case 2: return BFD_RELOC_16_PCREL
;
2732 case 4: return BFD_RELOC_32_PCREL
;
2733 case 8: return BFD_RELOC_64_PCREL
;
2735 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2742 case 4: return BFD_RELOC_X86_64_32S
;
2747 case 1: return BFD_RELOC_8
;
2748 case 2: return BFD_RELOC_16
;
2749 case 4: return BFD_RELOC_32
;
2750 case 8: return BFD_RELOC_64
;
2752 as_bad (_("cannot do %s %u byte relocation"),
2753 sign
> 0 ? "signed" : "unsigned", size
);
2759 /* Here we decide which fixups can be adjusted to make them relative to
2760 the beginning of the section instead of the symbol. Basically we need
2761 to make sure that the dynamic relocations are done correctly, so in
2762 some cases we force the original symbol to be used. */
2765 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2771 /* Don't adjust pc-relative references to merge sections in 64-bit
2773 if (use_rela_relocations
2774 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2778 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2779 and changed later by validate_fix. */
2780 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2781 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2784 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2785 for size relocations. */
2786 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2787 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2788 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2789 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2790 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2791 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2792 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2793 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2794 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2795 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2796 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2797 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2798 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2799 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2800 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2801 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2802 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2803 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2804 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2805 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2806 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2807 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2808 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2809 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2810 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2811 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2812 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2813 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2814 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2815 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2822 intel_float_operand (const char *mnemonic
)
2824 /* Note that the value returned is meaningful only for opcodes with (memory)
2825 operands, hence the code here is free to improperly handle opcodes that
2826 have no operands (for better performance and smaller code). */
2828 if (mnemonic
[0] != 'f')
2829 return 0; /* non-math */
2831 switch (mnemonic
[1])
2833 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2834 the fs segment override prefix not currently handled because no
2835 call path can make opcodes without operands get here */
2837 return 2 /* integer op */;
2839 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2840 return 3; /* fldcw/fldenv */
2843 if (mnemonic
[2] != 'o' /* fnop */)
2844 return 3; /* non-waiting control op */
2847 if (mnemonic
[2] == 's')
2848 return 3; /* frstor/frstpm */
2851 if (mnemonic
[2] == 'a')
2852 return 3; /* fsave */
2853 if (mnemonic
[2] == 't')
2855 switch (mnemonic
[3])
2857 case 'c': /* fstcw */
2858 case 'd': /* fstdw */
2859 case 'e': /* fstenv */
2860 case 's': /* fsts[gw] */
2866 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2867 return 0; /* fxsave/fxrstor are not really math ops */
2874 /* Build the VEX prefix. */
2877 build_vex_prefix (const insn_template
*t
)
2879 unsigned int register_specifier
;
2880 unsigned int implied_prefix
;
2881 unsigned int vector_length
;
2883 /* Check register specifier. */
2884 if (i
.vex
.register_specifier
)
2885 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2887 register_specifier
= 0xf;
2889 /* Use 2-byte VEX prefix by swappping destination and source
2892 && i
.operands
== i
.reg_operands
2893 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2894 && i
.tm
.opcode_modifier
.s
2897 unsigned int xchg
= i
.operands
- 1;
2898 union i386_op temp_op
;
2899 i386_operand_type temp_type
;
2901 temp_type
= i
.types
[xchg
];
2902 i
.types
[xchg
] = i
.types
[0];
2903 i
.types
[0] = temp_type
;
2904 temp_op
= i
.op
[xchg
];
2905 i
.op
[xchg
] = i
.op
[0];
2908 gas_assert (i
.rm
.mode
== 3);
2912 i
.rm
.regmem
= i
.rm
.reg
;
2915 /* Use the next insn. */
2919 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2920 vector_length
= avxscalar
;
2922 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2924 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2929 case DATA_PREFIX_OPCODE
:
2932 case REPE_PREFIX_OPCODE
:
2935 case REPNE_PREFIX_OPCODE
:
2942 /* Use 2-byte VEX prefix if possible. */
2943 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2944 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2945 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2947 /* 2-byte VEX prefix. */
2951 i
.vex
.bytes
[0] = 0xc5;
2953 /* Check the REX.R bit. */
2954 r
= (i
.rex
& REX_R
) ? 0 : 1;
2955 i
.vex
.bytes
[1] = (r
<< 7
2956 | register_specifier
<< 3
2957 | vector_length
<< 2
2962 /* 3-byte VEX prefix. */
2967 switch (i
.tm
.opcode_modifier
.vexopcode
)
2971 i
.vex
.bytes
[0] = 0xc4;
2975 i
.vex
.bytes
[0] = 0xc4;
2979 i
.vex
.bytes
[0] = 0xc4;
2983 i
.vex
.bytes
[0] = 0x8f;
2987 i
.vex
.bytes
[0] = 0x8f;
2991 i
.vex
.bytes
[0] = 0x8f;
2997 /* The high 3 bits of the second VEX byte are 1's compliment
2998 of RXB bits from REX. */
2999 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3001 /* Check the REX.W bit. */
3002 w
= (i
.rex
& REX_W
) ? 1 : 0;
3003 if (i
.tm
.opcode_modifier
.vexw
)
3008 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3012 i
.vex
.bytes
[2] = (w
<< 7
3013 | register_specifier
<< 3
3014 | vector_length
<< 2
3020 process_immext (void)
3024 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3027 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3028 with an opcode suffix which is coded in the same place as an
3029 8-bit immediate field would be.
3030 Here we check those operands and remove them afterwards. */
3033 for (x
= 0; x
< i
.operands
; x
++)
3034 if (register_number (i
.op
[x
].regs
) != x
)
3035 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3036 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3042 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3043 which is coded in the same place as an 8-bit immediate field
3044 would be. Here we fake an 8-bit immediate operand from the
3045 opcode suffix stored in tm.extension_opcode.
3047 AVX instructions also use this encoding, for some of
3048 3 argument instructions. */
3050 gas_assert (i
.imm_operands
== 0
3052 || (i
.tm
.opcode_modifier
.vex
3053 && i
.operands
<= 4)));
3055 exp
= &im_expressions
[i
.imm_operands
++];
3056 i
.op
[i
.operands
].imms
= exp
;
3057 i
.types
[i
.operands
] = imm8
;
3059 exp
->X_op
= O_constant
;
3060 exp
->X_add_number
= i
.tm
.extension_opcode
;
3061 i
.tm
.extension_opcode
= None
;
3068 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3073 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3074 as_bad (_("invalid instruction `%s' after `xacquire'"),
3077 as_bad (_("invalid instruction `%s' after `xrelease'"),
3081 if (i
.prefix
[LOCK_PREFIX
])
3083 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3084 as_bad (_("missing `lock' with `xacquire'"));
3086 as_bad (_("missing `lock' with `xrelease'"));
3090 case HLEPrefixRelease
:
3091 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3093 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3097 if (i
.mem_operands
== 0
3098 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3100 as_bad (_("memory destination needed for instruction `%s'"
3101 " after `xrelease'"), i
.tm
.name
);
3108 /* This is the guts of the machine-dependent assembler. LINE points to a
3109 machine dependent instruction. This function is supposed to emit
3110 the frags/bytes it assembles to. */
3113 md_assemble (char *line
)
3116 char mnemonic
[MAX_MNEM_SIZE
];
3117 const insn_template
*t
;
3119 /* Initialize globals. */
3120 memset (&i
, '\0', sizeof (i
));
3121 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3122 i
.reloc
[j
] = NO_RELOC
;
3123 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3124 memset (im_expressions
, '\0', sizeof (im_expressions
));
3125 save_stack_p
= save_stack
;
3127 /* First parse an instruction mnemonic & call i386_operand for the operands.
3128 We assume that the scrubber has arranged it so that line[0] is the valid
3129 start of a (possibly prefixed) mnemonic. */
3131 line
= parse_insn (line
, mnemonic
);
3135 line
= parse_operands (line
, mnemonic
);
3140 /* Now we've parsed the mnemonic into a set of templates, and have the
3141 operands at hand. */
3143 /* All intel opcodes have reversed operands except for "bound" and
3144 "enter". We also don't reverse intersegment "jmp" and "call"
3145 instructions with 2 immediate operands so that the immediate segment
3146 precedes the offset, as it does when in AT&T mode. */
3149 && (strcmp (mnemonic
, "bound") != 0)
3150 && (strcmp (mnemonic
, "invlpga") != 0)
3151 && !(operand_type_check (i
.types
[0], imm
)
3152 && operand_type_check (i
.types
[1], imm
)))
3155 /* The order of the immediates should be reversed
3156 for 2 immediates extrq and insertq instructions */
3157 if (i
.imm_operands
== 2
3158 && (strcmp (mnemonic
, "extrq") == 0
3159 || strcmp (mnemonic
, "insertq") == 0))
3160 swap_2_operands (0, 1);
3165 /* Don't optimize displacement for movabs since it only takes 64bit
3168 && i
.disp_encoding
!= disp_encoding_32bit
3169 && (flag_code
!= CODE_64BIT
3170 || strcmp (mnemonic
, "movabs") != 0))
3173 /* Next, we find a template that matches the given insn,
3174 making sure the overlap of the given operands types is consistent
3175 with the template operand types. */
3177 if (!(t
= match_template ()))
3180 if (sse_check
!= check_none
3181 && !i
.tm
.opcode_modifier
.noavx
3182 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3183 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3184 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3185 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3186 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3187 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3189 (sse_check
== check_warning
3191 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3194 /* Zap movzx and movsx suffix. The suffix has been set from
3195 "word ptr" or "byte ptr" on the source operand in Intel syntax
3196 or extracted from mnemonic in AT&T syntax. But we'll use
3197 the destination register to choose the suffix for encoding. */
3198 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3200 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3201 there is no suffix, the default will be byte extension. */
3202 if (i
.reg_operands
!= 2
3205 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3210 if (i
.tm
.opcode_modifier
.fwait
)
3211 if (!add_prefix (FWAIT_OPCODE
))
3214 /* Check for lock without a lockable instruction. Destination operand
3215 must be memory unless it is xchg (0x86). */
3216 if (i
.prefix
[LOCK_PREFIX
]
3217 && (!i
.tm
.opcode_modifier
.islockable
3218 || i
.mem_operands
== 0
3219 || (i
.tm
.base_opcode
!= 0x86
3220 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3222 as_bad (_("expecting lockable instruction after `lock'"));
3226 /* Check if HLE prefix is OK. */
3227 if (i
.have_hle
&& !check_hle ())
3230 /* Check string instruction segment overrides. */
3231 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3233 if (!check_string ())
3235 i
.disp_operands
= 0;
3238 if (!process_suffix ())
3241 /* Update operand types. */
3242 for (j
= 0; j
< i
.operands
; j
++)
3243 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3245 /* Make still unresolved immediate matches conform to size of immediate
3246 given in i.suffix. */
3247 if (!finalize_imm ())
3250 if (i
.types
[0].bitfield
.imm1
)
3251 i
.imm_operands
= 0; /* kludge for shift insns. */
3253 /* We only need to check those implicit registers for instructions
3254 with 3 operands or less. */
3255 if (i
.operands
<= 3)
3256 for (j
= 0; j
< i
.operands
; j
++)
3257 if (i
.types
[j
].bitfield
.inoutportreg
3258 || i
.types
[j
].bitfield
.shiftcount
3259 || i
.types
[j
].bitfield
.acc
3260 || i
.types
[j
].bitfield
.floatacc
)
3263 /* ImmExt should be processed after SSE2AVX. */
3264 if (!i
.tm
.opcode_modifier
.sse2avx
3265 && i
.tm
.opcode_modifier
.immext
)
3268 /* For insns with operands there are more diddles to do to the opcode. */
3271 if (!process_operands ())
3274 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3276 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3277 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3280 if (i
.tm
.opcode_modifier
.vex
)
3281 build_vex_prefix (t
);
3283 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3284 instructions may define INT_OPCODE as well, so avoid this corner
3285 case for those instructions that use MODRM. */
3286 if (i
.tm
.base_opcode
== INT_OPCODE
3287 && !i
.tm
.opcode_modifier
.modrm
3288 && i
.op
[0].imms
->X_add_number
== 3)
3290 i
.tm
.base_opcode
= INT3_OPCODE
;
3294 if ((i
.tm
.opcode_modifier
.jump
3295 || i
.tm
.opcode_modifier
.jumpbyte
3296 || i
.tm
.opcode_modifier
.jumpdword
)
3297 && i
.op
[0].disps
->X_op
== O_constant
)
3299 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3300 the absolute address given by the constant. Since ix86 jumps and
3301 calls are pc relative, we need to generate a reloc. */
3302 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3303 i
.op
[0].disps
->X_op
= O_symbol
;
3306 if (i
.tm
.opcode_modifier
.rex64
)
3309 /* For 8 bit registers we need an empty rex prefix. Also if the
3310 instruction already has a prefix, we need to convert old
3311 registers to new ones. */
3313 if ((i
.types
[0].bitfield
.reg8
3314 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3315 || (i
.types
[1].bitfield
.reg8
3316 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3317 || ((i
.types
[0].bitfield
.reg8
3318 || i
.types
[1].bitfield
.reg8
)
3323 i
.rex
|= REX_OPCODE
;
3324 for (x
= 0; x
< 2; x
++)
3326 /* Look for 8 bit operand that uses old registers. */
3327 if (i
.types
[x
].bitfield
.reg8
3328 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3330 /* In case it is "hi" register, give up. */
3331 if (i
.op
[x
].regs
->reg_num
> 3)
3332 as_bad (_("can't encode register '%s%s' in an "
3333 "instruction requiring REX prefix."),
3334 register_prefix
, i
.op
[x
].regs
->reg_name
);
3336 /* Otherwise it is equivalent to the extended register.
3337 Since the encoding doesn't change this is merely
3338 cosmetic cleanup for debug output. */
3340 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3346 add_prefix (REX_OPCODE
| i
.rex
);
3348 /* We are ready to output the insn. */
3353 parse_insn (char *line
, char *mnemonic
)
3356 char *token_start
= l
;
3359 const insn_template
*t
;
3362 /* Non-zero if we found a prefix only acceptable with string insns. */
3363 const char *expecting_string_instruction
= NULL
;
3368 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3373 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3375 as_bad (_("no such instruction: `%s'"), token_start
);
3380 if (!is_space_char (*l
)
3381 && *l
!= END_OF_INSN
3383 || (*l
!= PREFIX_SEPARATOR
3386 as_bad (_("invalid character %s in mnemonic"),
3387 output_invalid (*l
));
3390 if (token_start
== l
)
3392 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3393 as_bad (_("expecting prefix; got nothing"));
3395 as_bad (_("expecting mnemonic; got nothing"));
3399 /* Look up instruction (or prefix) via hash table. */
3400 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3402 if (*l
!= END_OF_INSN
3403 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3404 && current_templates
3405 && current_templates
->start
->opcode_modifier
.isprefix
)
3407 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3409 as_bad ((flag_code
!= CODE_64BIT
3410 ? _("`%s' is only supported in 64-bit mode")
3411 : _("`%s' is not supported in 64-bit mode")),
3412 current_templates
->start
->name
);
3415 /* If we are in 16-bit mode, do not allow addr16 or data16.
3416 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3417 if ((current_templates
->start
->opcode_modifier
.size16
3418 || current_templates
->start
->opcode_modifier
.size32
)
3419 && flag_code
!= CODE_64BIT
3420 && (current_templates
->start
->opcode_modifier
.size32
3421 ^ (flag_code
== CODE_16BIT
)))
3423 as_bad (_("redundant %s prefix"),
3424 current_templates
->start
->name
);
3427 /* Add prefix, checking for repeated prefixes. */
3428 switch (add_prefix (current_templates
->start
->base_opcode
))
3433 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3436 expecting_string_instruction
= current_templates
->start
->name
;
3441 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3448 if (!current_templates
)
3450 /* Check if we should swap operand or force 32bit displacement in
3452 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3454 else if (mnem_p
- 3 == dot_p
3457 i
.disp_encoding
= disp_encoding_8bit
;
3458 else if (mnem_p
- 4 == dot_p
3462 i
.disp_encoding
= disp_encoding_32bit
;
3467 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3470 if (!current_templates
)
3473 /* See if we can get a match by trimming off a suffix. */
3476 case WORD_MNEM_SUFFIX
:
3477 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3478 i
.suffix
= SHORT_MNEM_SUFFIX
;
3480 case BYTE_MNEM_SUFFIX
:
3481 case QWORD_MNEM_SUFFIX
:
3482 i
.suffix
= mnem_p
[-1];
3484 current_templates
= (const templates
*) hash_find (op_hash
,
3487 case SHORT_MNEM_SUFFIX
:
3488 case LONG_MNEM_SUFFIX
:
3491 i
.suffix
= mnem_p
[-1];
3493 current_templates
= (const templates
*) hash_find (op_hash
,
3502 if (intel_float_operand (mnemonic
) == 1)
3503 i
.suffix
= SHORT_MNEM_SUFFIX
;
3505 i
.suffix
= LONG_MNEM_SUFFIX
;
3507 current_templates
= (const templates
*) hash_find (op_hash
,
3512 if (!current_templates
)
3514 as_bad (_("no such instruction: `%s'"), token_start
);
3519 if (current_templates
->start
->opcode_modifier
.jump
3520 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3522 /* Check for a branch hint. We allow ",pt" and ",pn" for
3523 predict taken and predict not taken respectively.
3524 I'm not sure that branch hints actually do anything on loop
3525 and jcxz insns (JumpByte) for current Pentium4 chips. They
3526 may work in the future and it doesn't hurt to accept them
3528 if (l
[0] == ',' && l
[1] == 'p')
3532 if (!add_prefix (DS_PREFIX_OPCODE
))
3536 else if (l
[2] == 'n')
3538 if (!add_prefix (CS_PREFIX_OPCODE
))
3544 /* Any other comma loses. */
3547 as_bad (_("invalid character %s in mnemonic"),
3548 output_invalid (*l
));
3552 /* Check if instruction is supported on specified architecture. */
3554 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3556 supported
|= cpu_flags_match (t
);
3557 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3561 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3563 as_bad (flag_code
== CODE_64BIT
3564 ? _("`%s' is not supported in 64-bit mode")
3565 : _("`%s' is only supported in 64-bit mode"),
3566 current_templates
->start
->name
);
3569 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3571 as_bad (_("`%s' is not supported on `%s%s'"),
3572 current_templates
->start
->name
,
3573 cpu_arch_name
? cpu_arch_name
: default_arch
,
3574 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3579 if (!cpu_arch_flags
.bitfield
.cpui386
3580 && (flag_code
!= CODE_16BIT
))
3582 as_warn (_("use .code16 to ensure correct addressing mode"));
3585 /* Check for rep/repne without a string (or other allowed) instruction. */
3586 if (expecting_string_instruction
)
3588 static templates override
;
3590 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3591 if (t
->opcode_modifier
.repprefixok
)
3593 if (t
>= current_templates
->end
)
3595 as_bad (_("expecting string instruction after `%s'"),
3596 expecting_string_instruction
);
3599 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3600 if (!t
->opcode_modifier
.repprefixok
)
3603 current_templates
= &override
;
3610 parse_operands (char *l
, const char *mnemonic
)
3614 /* 1 if operand is pending after ','. */
3615 unsigned int expecting_operand
= 0;
3617 /* Non-zero if operand parens not balanced. */
3618 unsigned int paren_not_balanced
;
3620 while (*l
!= END_OF_INSN
)
3622 /* Skip optional white space before operand. */
3623 if (is_space_char (*l
))
3625 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3627 as_bad (_("invalid character %s before operand %d"),
3628 output_invalid (*l
),
3632 token_start
= l
; /* after white space */
3633 paren_not_balanced
= 0;
3634 while (paren_not_balanced
|| *l
!= ',')
3636 if (*l
== END_OF_INSN
)
3638 if (paren_not_balanced
)
3641 as_bad (_("unbalanced parenthesis in operand %d."),
3644 as_bad (_("unbalanced brackets in operand %d."),
3649 break; /* we are done */
3651 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3653 as_bad (_("invalid character %s in operand %d"),
3654 output_invalid (*l
),
3661 ++paren_not_balanced
;
3663 --paren_not_balanced
;
3668 ++paren_not_balanced
;
3670 --paren_not_balanced
;
3674 if (l
!= token_start
)
3675 { /* Yes, we've read in another operand. */
3676 unsigned int operand_ok
;
3677 this_operand
= i
.operands
++;
3678 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3679 if (i
.operands
> MAX_OPERANDS
)
3681 as_bad (_("spurious operands; (%d operands/instruction max)"),
3685 /* Now parse operand adding info to 'i' as we go along. */
3686 END_STRING_AND_SAVE (l
);
3690 i386_intel_operand (token_start
,
3691 intel_float_operand (mnemonic
));
3693 operand_ok
= i386_att_operand (token_start
);
3695 RESTORE_END_STRING (l
);
3701 if (expecting_operand
)
3703 expecting_operand_after_comma
:
3704 as_bad (_("expecting operand after ','; got nothing"));
3709 as_bad (_("expecting operand before ','; got nothing"));
3714 /* Now *l must be either ',' or END_OF_INSN. */
3717 if (*++l
== END_OF_INSN
)
3719 /* Just skip it, if it's \n complain. */
3720 goto expecting_operand_after_comma
;
3722 expecting_operand
= 1;
3729 swap_2_operands (int xchg1
, int xchg2
)
3731 union i386_op temp_op
;
3732 i386_operand_type temp_type
;
3733 enum bfd_reloc_code_real temp_reloc
;
3735 temp_type
= i
.types
[xchg2
];
3736 i
.types
[xchg2
] = i
.types
[xchg1
];
3737 i
.types
[xchg1
] = temp_type
;
3738 temp_op
= i
.op
[xchg2
];
3739 i
.op
[xchg2
] = i
.op
[xchg1
];
3740 i
.op
[xchg1
] = temp_op
;
3741 temp_reloc
= i
.reloc
[xchg2
];
3742 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3743 i
.reloc
[xchg1
] = temp_reloc
;
3747 swap_operands (void)
3753 swap_2_operands (1, i
.operands
- 2);
3756 swap_2_operands (0, i
.operands
- 1);
3762 if (i
.mem_operands
== 2)
3764 const seg_entry
*temp_seg
;
3765 temp_seg
= i
.seg
[0];
3766 i
.seg
[0] = i
.seg
[1];
3767 i
.seg
[1] = temp_seg
;
3771 /* Try to ensure constant immediates are represented in the smallest
3776 char guess_suffix
= 0;
3780 guess_suffix
= i
.suffix
;
3781 else if (i
.reg_operands
)
3783 /* Figure out a suffix from the last register operand specified.
3784 We can't do this properly yet, ie. excluding InOutPortReg,
3785 but the following works for instructions with immediates.
3786 In any case, we can't set i.suffix yet. */
3787 for (op
= i
.operands
; --op
>= 0;)
3788 if (i
.types
[op
].bitfield
.reg8
)
3790 guess_suffix
= BYTE_MNEM_SUFFIX
;
3793 else if (i
.types
[op
].bitfield
.reg16
)
3795 guess_suffix
= WORD_MNEM_SUFFIX
;
3798 else if (i
.types
[op
].bitfield
.reg32
)
3800 guess_suffix
= LONG_MNEM_SUFFIX
;
3803 else if (i
.types
[op
].bitfield
.reg64
)
3805 guess_suffix
= QWORD_MNEM_SUFFIX
;
3809 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3810 guess_suffix
= WORD_MNEM_SUFFIX
;
3812 for (op
= i
.operands
; --op
>= 0;)
3813 if (operand_type_check (i
.types
[op
], imm
))
3815 switch (i
.op
[op
].imms
->X_op
)
3818 /* If a suffix is given, this operand may be shortened. */
3819 switch (guess_suffix
)
3821 case LONG_MNEM_SUFFIX
:
3822 i
.types
[op
].bitfield
.imm32
= 1;
3823 i
.types
[op
].bitfield
.imm64
= 1;
3825 case WORD_MNEM_SUFFIX
:
3826 i
.types
[op
].bitfield
.imm16
= 1;
3827 i
.types
[op
].bitfield
.imm32
= 1;
3828 i
.types
[op
].bitfield
.imm32s
= 1;
3829 i
.types
[op
].bitfield
.imm64
= 1;
3831 case BYTE_MNEM_SUFFIX
:
3832 i
.types
[op
].bitfield
.imm8
= 1;
3833 i
.types
[op
].bitfield
.imm8s
= 1;
3834 i
.types
[op
].bitfield
.imm16
= 1;
3835 i
.types
[op
].bitfield
.imm32
= 1;
3836 i
.types
[op
].bitfield
.imm32s
= 1;
3837 i
.types
[op
].bitfield
.imm64
= 1;
3841 /* If this operand is at most 16 bits, convert it
3842 to a signed 16 bit number before trying to see
3843 whether it will fit in an even smaller size.
3844 This allows a 16-bit operand such as $0xffe0 to
3845 be recognised as within Imm8S range. */
3846 if ((i
.types
[op
].bitfield
.imm16
)
3847 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3849 i
.op
[op
].imms
->X_add_number
=
3850 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3852 if ((i
.types
[op
].bitfield
.imm32
)
3853 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3856 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3857 ^ ((offsetT
) 1 << 31))
3858 - ((offsetT
) 1 << 31));
3861 = operand_type_or (i
.types
[op
],
3862 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3864 /* We must avoid matching of Imm32 templates when 64bit
3865 only immediate is available. */
3866 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3867 i
.types
[op
].bitfield
.imm32
= 0;
3874 /* Symbols and expressions. */
3876 /* Convert symbolic operand to proper sizes for matching, but don't
3877 prevent matching a set of insns that only supports sizes other
3878 than those matching the insn suffix. */
3880 i386_operand_type mask
, allowed
;
3881 const insn_template
*t
;
3883 operand_type_set (&mask
, 0);
3884 operand_type_set (&allowed
, 0);
3886 for (t
= current_templates
->start
;
3887 t
< current_templates
->end
;
3889 allowed
= operand_type_or (allowed
,
3890 t
->operand_types
[op
]);
3891 switch (guess_suffix
)
3893 case QWORD_MNEM_SUFFIX
:
3894 mask
.bitfield
.imm64
= 1;
3895 mask
.bitfield
.imm32s
= 1;
3897 case LONG_MNEM_SUFFIX
:
3898 mask
.bitfield
.imm32
= 1;
3900 case WORD_MNEM_SUFFIX
:
3901 mask
.bitfield
.imm16
= 1;
3903 case BYTE_MNEM_SUFFIX
:
3904 mask
.bitfield
.imm8
= 1;
3909 allowed
= operand_type_and (mask
, allowed
);
3910 if (!operand_type_all_zero (&allowed
))
3911 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3918 /* Try to use the smallest displacement type too. */
3920 optimize_disp (void)
3924 for (op
= i
.operands
; --op
>= 0;)
3925 if (operand_type_check (i
.types
[op
], disp
))
3927 if (i
.op
[op
].disps
->X_op
== O_constant
)
3929 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3931 if (i
.types
[op
].bitfield
.disp16
3932 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3934 /* If this operand is at most 16 bits, convert
3935 to a signed 16 bit number and don't use 64bit
3937 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3938 i
.types
[op
].bitfield
.disp64
= 0;
3940 if (i
.types
[op
].bitfield
.disp32
3941 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3943 /* If this operand is at most 32 bits, convert
3944 to a signed 32 bit number and don't use 64bit
3946 op_disp
&= (((offsetT
) 2 << 31) - 1);
3947 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3948 i
.types
[op
].bitfield
.disp64
= 0;
3950 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3952 i
.types
[op
].bitfield
.disp8
= 0;
3953 i
.types
[op
].bitfield
.disp16
= 0;
3954 i
.types
[op
].bitfield
.disp32
= 0;
3955 i
.types
[op
].bitfield
.disp32s
= 0;
3956 i
.types
[op
].bitfield
.disp64
= 0;
3960 else if (flag_code
== CODE_64BIT
)
3962 if (fits_in_signed_long (op_disp
))
3964 i
.types
[op
].bitfield
.disp64
= 0;
3965 i
.types
[op
].bitfield
.disp32s
= 1;
3967 if (i
.prefix
[ADDR_PREFIX
]
3968 && fits_in_unsigned_long (op_disp
))
3969 i
.types
[op
].bitfield
.disp32
= 1;
3971 if ((i
.types
[op
].bitfield
.disp32
3972 || i
.types
[op
].bitfield
.disp32s
3973 || i
.types
[op
].bitfield
.disp16
)
3974 && fits_in_signed_byte (op_disp
))
3975 i
.types
[op
].bitfield
.disp8
= 1;
3977 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3978 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3980 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3981 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3982 i
.types
[op
].bitfield
.disp8
= 0;
3983 i
.types
[op
].bitfield
.disp16
= 0;
3984 i
.types
[op
].bitfield
.disp32
= 0;
3985 i
.types
[op
].bitfield
.disp32s
= 0;
3986 i
.types
[op
].bitfield
.disp64
= 0;
3989 /* We only support 64bit displacement on constants. */
3990 i
.types
[op
].bitfield
.disp64
= 0;
3994 /* Check if operands are valid for the instruction. */
3997 check_VecOperands (const insn_template
*t
)
3999 /* Without VSIB byte, we can't have a vector register for index. */
4000 if (!t
->opcode_modifier
.vecsib
4002 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4003 || i
.index_reg
->reg_type
.bitfield
.regymm
))
4005 i
.error
= unsupported_vector_index_register
;
4009 /* For VSIB byte, we need a vector register for index, and all vector
4010 registers must be distinct. */
4011 if (t
->opcode_modifier
.vecsib
)
4014 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4015 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4016 || (t
->opcode_modifier
.vecsib
== VecSIB256
4017 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
4019 i
.error
= invalid_vsib_address
;
4023 gas_assert (i
.reg_operands
== 2);
4024 gas_assert (i
.types
[0].bitfield
.regxmm
4025 || i
.types
[0].bitfield
.regymm
);
4026 gas_assert (i
.types
[2].bitfield
.regxmm
4027 || i
.types
[2].bitfield
.regymm
);
4029 if (operand_check
== check_none
)
4031 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4032 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4033 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4035 if (operand_check
== check_error
)
4037 i
.error
= invalid_vector_register_set
;
4040 as_warn (_("mask, index, and destination registers should be distinct"));
4046 /* Check if operands are valid for the instruction. Update VEX
4050 VEX_check_operands (const insn_template
*t
)
4052 if (!t
->opcode_modifier
.vex
)
4055 /* Only check VEX_Imm4, which must be the first operand. */
4056 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4058 if (i
.op
[0].imms
->X_op
!= O_constant
4059 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4065 /* Turn off Imm8 so that update_imm won't complain. */
4066 i
.types
[0] = vec_imm4
;
4072 static const insn_template
*
4073 match_template (void)
4075 /* Points to template once we've found it. */
4076 const insn_template
*t
;
4077 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4078 i386_operand_type overlap4
;
4079 unsigned int found_reverse_match
;
4080 i386_opcode_modifier suffix_check
;
4081 i386_operand_type operand_types
[MAX_OPERANDS
];
4082 int addr_prefix_disp
;
4084 unsigned int found_cpu_match
;
4085 unsigned int check_register
;
4086 enum i386_error specific_error
= 0;
4088 #if MAX_OPERANDS != 5
4089 # error "MAX_OPERANDS must be 5."
4092 found_reverse_match
= 0;
4093 addr_prefix_disp
= -1;
4095 memset (&suffix_check
, 0, sizeof (suffix_check
));
4096 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4097 suffix_check
.no_bsuf
= 1;
4098 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4099 suffix_check
.no_wsuf
= 1;
4100 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4101 suffix_check
.no_ssuf
= 1;
4102 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4103 suffix_check
.no_lsuf
= 1;
4104 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4105 suffix_check
.no_qsuf
= 1;
4106 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4107 suffix_check
.no_ldsuf
= 1;
4109 /* Must have right number of operands. */
4110 i
.error
= number_of_operands_mismatch
;
4112 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4114 addr_prefix_disp
= -1;
4116 if (i
.operands
!= t
->operands
)
4119 /* Check processor support. */
4120 i
.error
= unsupported
;
4121 found_cpu_match
= (cpu_flags_match (t
)
4122 == CPU_FLAGS_PERFECT_MATCH
);
4123 if (!found_cpu_match
)
4126 /* Check old gcc support. */
4127 i
.error
= old_gcc_only
;
4128 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4131 /* Check AT&T mnemonic. */
4132 i
.error
= unsupported_with_intel_mnemonic
;
4133 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4136 /* Check AT&T/Intel syntax. */
4137 i
.error
= unsupported_syntax
;
4138 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4139 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4142 /* Check the suffix, except for some instructions in intel mode. */
4143 i
.error
= invalid_instruction_suffix
;
4144 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4145 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4146 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4147 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4148 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4149 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4150 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4153 if (!operand_size_match (t
))
4156 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4157 operand_types
[j
] = t
->operand_types
[j
];
4159 /* In general, don't allow 64-bit operands in 32-bit mode. */
4160 if (i
.suffix
== QWORD_MNEM_SUFFIX
4161 && flag_code
!= CODE_64BIT
4163 ? (!t
->opcode_modifier
.ignoresize
4164 && !intel_float_operand (t
->name
))
4165 : intel_float_operand (t
->name
) != 2)
4166 && ((!operand_types
[0].bitfield
.regmmx
4167 && !operand_types
[0].bitfield
.regxmm
4168 && !operand_types
[0].bitfield
.regymm
)
4169 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4170 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4171 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4172 && (t
->base_opcode
!= 0x0fc7
4173 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4176 /* In general, don't allow 32-bit operands on pre-386. */
4177 else if (i
.suffix
== LONG_MNEM_SUFFIX
4178 && !cpu_arch_flags
.bitfield
.cpui386
4180 ? (!t
->opcode_modifier
.ignoresize
4181 && !intel_float_operand (t
->name
))
4182 : intel_float_operand (t
->name
) != 2)
4183 && ((!operand_types
[0].bitfield
.regmmx
4184 && !operand_types
[0].bitfield
.regxmm
)
4185 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4186 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4189 /* Do not verify operands when there are none. */
4193 /* We've found a match; break out of loop. */
4197 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4198 into Disp32/Disp16/Disp32 operand. */
4199 if (i
.prefix
[ADDR_PREFIX
] != 0)
4201 /* There should be only one Disp operand. */
4205 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4207 if (operand_types
[j
].bitfield
.disp16
)
4209 addr_prefix_disp
= j
;
4210 operand_types
[j
].bitfield
.disp32
= 1;
4211 operand_types
[j
].bitfield
.disp16
= 0;
4217 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4219 if (operand_types
[j
].bitfield
.disp32
)
4221 addr_prefix_disp
= j
;
4222 operand_types
[j
].bitfield
.disp32
= 0;
4223 operand_types
[j
].bitfield
.disp16
= 1;
4229 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4231 if (operand_types
[j
].bitfield
.disp64
)
4233 addr_prefix_disp
= j
;
4234 operand_types
[j
].bitfield
.disp64
= 0;
4235 operand_types
[j
].bitfield
.disp32
= 1;
4243 /* We check register size if needed. */
4244 check_register
= t
->opcode_modifier
.checkregsize
;
4245 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4246 switch (t
->operands
)
4249 if (!operand_type_match (overlap0
, i
.types
[0]))
4253 /* xchg %eax, %eax is a special case. It is an aliase for nop
4254 only in 32bit mode and we can use opcode 0x90. In 64bit
4255 mode, we can't use 0x90 for xchg %eax, %eax since it should
4256 zero-extend %eax to %rax. */
4257 if (flag_code
== CODE_64BIT
4258 && t
->base_opcode
== 0x90
4259 && operand_type_equal (&i
.types
[0], &acc32
)
4260 && operand_type_equal (&i
.types
[1], &acc32
))
4264 /* If we swap operand in encoding, we either match
4265 the next one or reverse direction of operands. */
4266 if (t
->opcode_modifier
.s
)
4268 else if (t
->opcode_modifier
.d
)
4273 /* If we swap operand in encoding, we match the next one. */
4274 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4278 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4279 if (!operand_type_match (overlap0
, i
.types
[0])
4280 || !operand_type_match (overlap1
, i
.types
[1])
4282 && !operand_type_register_match (overlap0
, i
.types
[0],
4284 overlap1
, i
.types
[1],
4287 /* Check if other direction is valid ... */
4288 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4292 /* Try reversing direction of operands. */
4293 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4294 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4295 if (!operand_type_match (overlap0
, i
.types
[0])
4296 || !operand_type_match (overlap1
, i
.types
[1])
4298 && !operand_type_register_match (overlap0
,
4305 /* Does not match either direction. */
4308 /* found_reverse_match holds which of D or FloatDR
4310 if (t
->opcode_modifier
.d
)
4311 found_reverse_match
= Opcode_D
;
4312 else if (t
->opcode_modifier
.floatd
)
4313 found_reverse_match
= Opcode_FloatD
;
4315 found_reverse_match
= 0;
4316 if (t
->opcode_modifier
.floatr
)
4317 found_reverse_match
|= Opcode_FloatR
;
4321 /* Found a forward 2 operand match here. */
4322 switch (t
->operands
)
4325 overlap4
= operand_type_and (i
.types
[4],
4328 overlap3
= operand_type_and (i
.types
[3],
4331 overlap2
= operand_type_and (i
.types
[2],
4336 switch (t
->operands
)
4339 if (!operand_type_match (overlap4
, i
.types
[4])
4340 || !operand_type_register_match (overlap3
,
4348 if (!operand_type_match (overlap3
, i
.types
[3])
4350 && !operand_type_register_match (overlap2
,
4358 /* Here we make use of the fact that there are no
4359 reverse match 3 operand instructions, and all 3
4360 operand instructions only need to be checked for
4361 register consistency between operands 2 and 3. */
4362 if (!operand_type_match (overlap2
, i
.types
[2])
4364 && !operand_type_register_match (overlap1
,
4374 /* Found either forward/reverse 2, 3 or 4 operand match here:
4375 slip through to break. */
4377 if (!found_cpu_match
)
4379 found_reverse_match
= 0;
4383 /* Check if vector and VEX operands are valid. */
4384 if (check_VecOperands (t
) || VEX_check_operands (t
))
4386 specific_error
= i
.error
;
4390 /* We've found a match; break out of loop. */
4394 if (t
== current_templates
->end
)
4396 /* We found no match. */
4397 const char *err_msg
;
4398 switch (specific_error
? specific_error
: i
.error
)
4402 case operand_size_mismatch
:
4403 err_msg
= _("operand size mismatch");
4405 case operand_type_mismatch
:
4406 err_msg
= _("operand type mismatch");
4408 case register_type_mismatch
:
4409 err_msg
= _("register type mismatch");
4411 case number_of_operands_mismatch
:
4412 err_msg
= _("number of operands mismatch");
4414 case invalid_instruction_suffix
:
4415 err_msg
= _("invalid instruction suffix");
4418 err_msg
= _("constant doesn't fit in 4 bits");
4421 err_msg
= _("only supported with old gcc");
4423 case unsupported_with_intel_mnemonic
:
4424 err_msg
= _("unsupported with Intel mnemonic");
4426 case unsupported_syntax
:
4427 err_msg
= _("unsupported syntax");
4430 as_bad (_("unsupported instruction `%s'"),
4431 current_templates
->start
->name
);
4433 case invalid_vsib_address
:
4434 err_msg
= _("invalid VSIB address");
4436 case invalid_vector_register_set
:
4437 err_msg
= _("mask, index, and destination registers must be distinct");
4439 case unsupported_vector_index_register
:
4440 err_msg
= _("unsupported vector index register");
4443 as_bad (_("%s for `%s'"), err_msg
,
4444 current_templates
->start
->name
);
4448 if (!quiet_warnings
)
4451 && (i
.types
[0].bitfield
.jumpabsolute
4452 != operand_types
[0].bitfield
.jumpabsolute
))
4454 as_warn (_("indirect %s without `*'"), t
->name
);
4457 if (t
->opcode_modifier
.isprefix
4458 && t
->opcode_modifier
.ignoresize
)
4460 /* Warn them that a data or address size prefix doesn't
4461 affect assembly of the next line of code. */
4462 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4466 /* Copy the template we found. */
4469 if (addr_prefix_disp
!= -1)
4470 i
.tm
.operand_types
[addr_prefix_disp
]
4471 = operand_types
[addr_prefix_disp
];
4473 if (found_reverse_match
)
4475 /* If we found a reverse match we must alter the opcode
4476 direction bit. found_reverse_match holds bits to change
4477 (different for int & float insns). */
4479 i
.tm
.base_opcode
^= found_reverse_match
;
4481 i
.tm
.operand_types
[0] = operand_types
[1];
4482 i
.tm
.operand_types
[1] = operand_types
[0];
4491 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4492 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4494 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4496 as_bad (_("`%s' operand %d must use `%ses' segment"),
4502 /* There's only ever one segment override allowed per instruction.
4503 This instruction possibly has a legal segment override on the
4504 second operand, so copy the segment to where non-string
4505 instructions store it, allowing common code. */
4506 i
.seg
[0] = i
.seg
[1];
4508 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4510 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4512 as_bad (_("`%s' operand %d must use `%ses' segment"),
4523 process_suffix (void)
4525 /* If matched instruction specifies an explicit instruction mnemonic
4527 if (i
.tm
.opcode_modifier
.size16
)
4528 i
.suffix
= WORD_MNEM_SUFFIX
;
4529 else if (i
.tm
.opcode_modifier
.size32
)
4530 i
.suffix
= LONG_MNEM_SUFFIX
;
4531 else if (i
.tm
.opcode_modifier
.size64
)
4532 i
.suffix
= QWORD_MNEM_SUFFIX
;
4533 else if (i
.reg_operands
)
4535 /* If there's no instruction mnemonic suffix we try to invent one
4536 based on register operands. */
4539 /* We take i.suffix from the last register operand specified,
4540 Destination register type is more significant than source
4541 register type. crc32 in SSE4.2 prefers source register
4543 if (i
.tm
.base_opcode
== 0xf20f38f1)
4545 if (i
.types
[0].bitfield
.reg16
)
4546 i
.suffix
= WORD_MNEM_SUFFIX
;
4547 else if (i
.types
[0].bitfield
.reg32
)
4548 i
.suffix
= LONG_MNEM_SUFFIX
;
4549 else if (i
.types
[0].bitfield
.reg64
)
4550 i
.suffix
= QWORD_MNEM_SUFFIX
;
4552 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4554 if (i
.types
[0].bitfield
.reg8
)
4555 i
.suffix
= BYTE_MNEM_SUFFIX
;
4562 if (i
.tm
.base_opcode
== 0xf20f38f1
4563 || i
.tm
.base_opcode
== 0xf20f38f0)
4565 /* We have to know the operand size for crc32. */
4566 as_bad (_("ambiguous memory operand size for `%s`"),
4571 for (op
= i
.operands
; --op
>= 0;)
4572 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4574 if (i
.types
[op
].bitfield
.reg8
)
4576 i
.suffix
= BYTE_MNEM_SUFFIX
;
4579 else if (i
.types
[op
].bitfield
.reg16
)
4581 i
.suffix
= WORD_MNEM_SUFFIX
;
4584 else if (i
.types
[op
].bitfield
.reg32
)
4586 i
.suffix
= LONG_MNEM_SUFFIX
;
4589 else if (i
.types
[op
].bitfield
.reg64
)
4591 i
.suffix
= QWORD_MNEM_SUFFIX
;
4597 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4600 && i
.tm
.opcode_modifier
.ignoresize
4601 && i
.tm
.opcode_modifier
.no_bsuf
)
4603 else if (!check_byte_reg ())
4606 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4609 && i
.tm
.opcode_modifier
.ignoresize
4610 && i
.tm
.opcode_modifier
.no_lsuf
)
4612 else if (!check_long_reg ())
4615 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4618 && i
.tm
.opcode_modifier
.ignoresize
4619 && i
.tm
.opcode_modifier
.no_qsuf
)
4621 else if (!check_qword_reg ())
4624 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4627 && i
.tm
.opcode_modifier
.ignoresize
4628 && i
.tm
.opcode_modifier
.no_wsuf
)
4630 else if (!check_word_reg ())
4633 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4634 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4636 /* Skip if the instruction has x/y suffix. match_template
4637 should check if it is a valid suffix. */
4639 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4640 /* Do nothing if the instruction is going to ignore the prefix. */
4645 else if (i
.tm
.opcode_modifier
.defaultsize
4647 /* exclude fldenv/frstor/fsave/fstenv */
4648 && i
.tm
.opcode_modifier
.no_ssuf
)
4650 i
.suffix
= stackop_size
;
4652 else if (intel_syntax
4654 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4655 || i
.tm
.opcode_modifier
.jumpbyte
4656 || i
.tm
.opcode_modifier
.jumpintersegment
4657 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4658 && i
.tm
.extension_opcode
<= 3)))
4663 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4665 i
.suffix
= QWORD_MNEM_SUFFIX
;
4669 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4670 i
.suffix
= LONG_MNEM_SUFFIX
;
4673 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4674 i
.suffix
= WORD_MNEM_SUFFIX
;
4683 if (i
.tm
.opcode_modifier
.w
)
4685 as_bad (_("no instruction mnemonic suffix given and "
4686 "no register operands; can't size instruction"));
4692 unsigned int suffixes
;
4694 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4695 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4697 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4699 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4701 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4703 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4706 /* There are more than suffix matches. */
4707 if (i
.tm
.opcode_modifier
.w
4708 || ((suffixes
& (suffixes
- 1))
4709 && !i
.tm
.opcode_modifier
.defaultsize
4710 && !i
.tm
.opcode_modifier
.ignoresize
))
4712 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4718 /* Change the opcode based on the operand size given by i.suffix;
4719 We don't need to change things for byte insns. */
4722 && i
.suffix
!= BYTE_MNEM_SUFFIX
4723 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4724 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4726 /* It's not a byte, select word/dword operation. */
4727 if (i
.tm
.opcode_modifier
.w
)
4729 if (i
.tm
.opcode_modifier
.shortform
)
4730 i
.tm
.base_opcode
|= 8;
4732 i
.tm
.base_opcode
|= 1;
4735 /* Now select between word & dword operations via the operand
4736 size prefix, except for instructions that will ignore this
4738 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4740 /* The address size override prefix changes the size of the
4742 if ((flag_code
== CODE_32BIT
4743 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4744 || (flag_code
!= CODE_32BIT
4745 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4746 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4749 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4750 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4751 && !i
.tm
.opcode_modifier
.ignoresize
4752 && !i
.tm
.opcode_modifier
.floatmf
4753 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4754 || (flag_code
== CODE_64BIT
4755 && i
.tm
.opcode_modifier
.jumpbyte
)))
4757 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4759 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4760 prefix
= ADDR_PREFIX_OPCODE
;
4762 if (!add_prefix (prefix
))
4766 /* Set mode64 for an operand. */
4767 if (i
.suffix
== QWORD_MNEM_SUFFIX
4768 && flag_code
== CODE_64BIT
4769 && !i
.tm
.opcode_modifier
.norex64
)
4771 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4772 need rex64. cmpxchg8b is also a special case. */
4773 if (! (i
.operands
== 2
4774 && i
.tm
.base_opcode
== 0x90
4775 && i
.tm
.extension_opcode
== None
4776 && operand_type_equal (&i
.types
[0], &acc64
)
4777 && operand_type_equal (&i
.types
[1], &acc64
))
4778 && ! (i
.operands
== 1
4779 && i
.tm
.base_opcode
== 0xfc7
4780 && i
.tm
.extension_opcode
== 1
4781 && !operand_type_check (i
.types
[0], reg
)
4782 && operand_type_check (i
.types
[0], anymem
)))
4786 /* Size floating point instruction. */
4787 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4788 if (i
.tm
.opcode_modifier
.floatmf
)
4789 i
.tm
.base_opcode
^= 4;
4796 check_byte_reg (void)
4800 for (op
= i
.operands
; --op
>= 0;)
4802 /* If this is an eight bit register, it's OK. If it's the 16 or
4803 32 bit version of an eight bit register, we will just use the
4804 low portion, and that's OK too. */
4805 if (i
.types
[op
].bitfield
.reg8
)
4808 /* I/O port address operands are OK too. */
4809 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4812 /* crc32 doesn't generate this warning. */
4813 if (i
.tm
.base_opcode
== 0xf20f38f0)
4816 if ((i
.types
[op
].bitfield
.reg16
4817 || i
.types
[op
].bitfield
.reg32
4818 || i
.types
[op
].bitfield
.reg64
)
4819 && i
.op
[op
].regs
->reg_num
< 4
4820 /* Prohibit these changes in 64bit mode, since the lowering
4821 would be more complicated. */
4822 && flag_code
!= CODE_64BIT
)
4824 #if REGISTER_WARNINGS
4825 if (!quiet_warnings
)
4826 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4828 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4829 ? REGNAM_AL
- REGNAM_AX
4830 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4832 i
.op
[op
].regs
->reg_name
,
4837 /* Any other register is bad. */
4838 if (i
.types
[op
].bitfield
.reg16
4839 || i
.types
[op
].bitfield
.reg32
4840 || i
.types
[op
].bitfield
.reg64
4841 || i
.types
[op
].bitfield
.regmmx
4842 || i
.types
[op
].bitfield
.regxmm
4843 || i
.types
[op
].bitfield
.regymm
4844 || i
.types
[op
].bitfield
.sreg2
4845 || i
.types
[op
].bitfield
.sreg3
4846 || i
.types
[op
].bitfield
.control
4847 || i
.types
[op
].bitfield
.debug
4848 || i
.types
[op
].bitfield
.test
4849 || i
.types
[op
].bitfield
.floatreg
4850 || i
.types
[op
].bitfield
.floatacc
)
4852 as_bad (_("`%s%s' not allowed with `%s%c'"),
4854 i
.op
[op
].regs
->reg_name
,
4864 check_long_reg (void)
4868 for (op
= i
.operands
; --op
>= 0;)
4869 /* Reject eight bit registers, except where the template requires
4870 them. (eg. movzb) */
4871 if (i
.types
[op
].bitfield
.reg8
4872 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4873 || i
.tm
.operand_types
[op
].bitfield
.reg32
4874 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4876 as_bad (_("`%s%s' not allowed with `%s%c'"),
4878 i
.op
[op
].regs
->reg_name
,
4883 /* Warn if the e prefix on a general reg is missing. */
4884 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4885 && i
.types
[op
].bitfield
.reg16
4886 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4887 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4889 /* Prohibit these changes in the 64bit mode, since the
4890 lowering is more complicated. */
4891 if (flag_code
== CODE_64BIT
)
4893 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4894 register_prefix
, i
.op
[op
].regs
->reg_name
,
4898 #if REGISTER_WARNINGS
4900 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4902 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4904 i
.op
[op
].regs
->reg_name
,
4908 /* Warn if the r prefix on a general reg is missing. */
4909 else if (i
.types
[op
].bitfield
.reg64
4910 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4911 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4914 && i
.tm
.opcode_modifier
.toqword
4915 && !i
.types
[0].bitfield
.regxmm
)
4917 /* Convert to QWORD. We want REX byte. */
4918 i
.suffix
= QWORD_MNEM_SUFFIX
;
4922 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4923 register_prefix
, i
.op
[op
].regs
->reg_name
,
4932 check_qword_reg (void)
4936 for (op
= i
.operands
; --op
>= 0; )
4937 /* Reject eight bit registers, except where the template requires
4938 them. (eg. movzb) */
4939 if (i
.types
[op
].bitfield
.reg8
4940 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4941 || i
.tm
.operand_types
[op
].bitfield
.reg32
4942 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4944 as_bad (_("`%s%s' not allowed with `%s%c'"),
4946 i
.op
[op
].regs
->reg_name
,
4951 /* Warn if the e prefix on a general reg is missing. */
4952 else if ((i
.types
[op
].bitfield
.reg16
4953 || i
.types
[op
].bitfield
.reg32
)
4954 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4955 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4957 /* Prohibit these changes in the 64bit mode, since the
4958 lowering is more complicated. */
4960 && i
.tm
.opcode_modifier
.todword
4961 && !i
.types
[0].bitfield
.regxmm
)
4963 /* Convert to DWORD. We don't want REX byte. */
4964 i
.suffix
= LONG_MNEM_SUFFIX
;
4968 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4969 register_prefix
, i
.op
[op
].regs
->reg_name
,
4978 check_word_reg (void)
4981 for (op
= i
.operands
; --op
>= 0;)
4982 /* Reject eight bit registers, except where the template requires
4983 them. (eg. movzb) */
4984 if (i
.types
[op
].bitfield
.reg8
4985 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4986 || i
.tm
.operand_types
[op
].bitfield
.reg32
4987 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4989 as_bad (_("`%s%s' not allowed with `%s%c'"),
4991 i
.op
[op
].regs
->reg_name
,
4996 /* Warn if the e prefix on a general reg is present. */
4997 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4998 && i
.types
[op
].bitfield
.reg32
4999 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5000 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5002 /* Prohibit these changes in the 64bit mode, since the
5003 lowering is more complicated. */
5004 if (flag_code
== CODE_64BIT
)
5006 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5007 register_prefix
, i
.op
[op
].regs
->reg_name
,
5012 #if REGISTER_WARNINGS
5013 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5015 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5017 i
.op
[op
].regs
->reg_name
,
5025 update_imm (unsigned int j
)
5027 i386_operand_type overlap
= i
.types
[j
];
5028 if ((overlap
.bitfield
.imm8
5029 || overlap
.bitfield
.imm8s
5030 || overlap
.bitfield
.imm16
5031 || overlap
.bitfield
.imm32
5032 || overlap
.bitfield
.imm32s
5033 || overlap
.bitfield
.imm64
)
5034 && !operand_type_equal (&overlap
, &imm8
)
5035 && !operand_type_equal (&overlap
, &imm8s
)
5036 && !operand_type_equal (&overlap
, &imm16
)
5037 && !operand_type_equal (&overlap
, &imm32
)
5038 && !operand_type_equal (&overlap
, &imm32s
)
5039 && !operand_type_equal (&overlap
, &imm64
))
5043 i386_operand_type temp
;
5045 operand_type_set (&temp
, 0);
5046 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5048 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5049 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5051 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5052 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5053 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5055 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5056 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5059 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5062 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5063 || operand_type_equal (&overlap
, &imm16_32
)
5064 || operand_type_equal (&overlap
, &imm16_32s
))
5066 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5071 if (!operand_type_equal (&overlap
, &imm8
)
5072 && !operand_type_equal (&overlap
, &imm8s
)
5073 && !operand_type_equal (&overlap
, &imm16
)
5074 && !operand_type_equal (&overlap
, &imm32
)
5075 && !operand_type_equal (&overlap
, &imm32s
)
5076 && !operand_type_equal (&overlap
, &imm64
))
5078 as_bad (_("no instruction mnemonic suffix given; "
5079 "can't determine immediate size"));
5083 i
.types
[j
] = overlap
;
5093 /* Update the first 2 immediate operands. */
5094 n
= i
.operands
> 2 ? 2 : i
.operands
;
5097 for (j
= 0; j
< n
; j
++)
5098 if (update_imm (j
) == 0)
5101 /* The 3rd operand can't be immediate operand. */
5102 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5109 bad_implicit_operand (int xmm
)
5111 const char *ireg
= xmm
? "xmm0" : "ymm0";
5114 as_bad (_("the last operand of `%s' must be `%s%s'"),
5115 i
.tm
.name
, register_prefix
, ireg
);
5117 as_bad (_("the first operand of `%s' must be `%s%s'"),
5118 i
.tm
.name
, register_prefix
, ireg
);
5123 process_operands (void)
5125 /* Default segment register this instruction will use for memory
5126 accesses. 0 means unknown. This is only for optimizing out
5127 unnecessary segment overrides. */
5128 const seg_entry
*default_seg
= 0;
5130 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5132 unsigned int dupl
= i
.operands
;
5133 unsigned int dest
= dupl
- 1;
5136 /* The destination must be an xmm register. */
5137 gas_assert (i
.reg_operands
5138 && MAX_OPERANDS
> dupl
5139 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5141 if (i
.tm
.opcode_modifier
.firstxmm0
)
5143 /* The first operand is implicit and must be xmm0. */
5144 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5145 if (register_number (i
.op
[0].regs
) != 0)
5146 return bad_implicit_operand (1);
5148 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5150 /* Keep xmm0 for instructions with VEX prefix and 3
5156 /* We remove the first xmm0 and keep the number of
5157 operands unchanged, which in fact duplicates the
5159 for (j
= 1; j
< i
.operands
; j
++)
5161 i
.op
[j
- 1] = i
.op
[j
];
5162 i
.types
[j
- 1] = i
.types
[j
];
5163 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5167 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5169 gas_assert ((MAX_OPERANDS
- 1) > dupl
5170 && (i
.tm
.opcode_modifier
.vexsources
5173 /* Add the implicit xmm0 for instructions with VEX prefix
5175 for (j
= i
.operands
; j
> 0; j
--)
5177 i
.op
[j
] = i
.op
[j
- 1];
5178 i
.types
[j
] = i
.types
[j
- 1];
5179 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5182 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5183 i
.types
[0] = regxmm
;
5184 i
.tm
.operand_types
[0] = regxmm
;
5187 i
.reg_operands
+= 2;
5192 i
.op
[dupl
] = i
.op
[dest
];
5193 i
.types
[dupl
] = i
.types
[dest
];
5194 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5203 i
.op
[dupl
] = i
.op
[dest
];
5204 i
.types
[dupl
] = i
.types
[dest
];
5205 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5208 if (i
.tm
.opcode_modifier
.immext
)
5211 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5215 /* The first operand is implicit and must be xmm0/ymm0. */
5216 gas_assert (i
.reg_operands
5217 && (operand_type_equal (&i
.types
[0], ®xmm
)
5218 || operand_type_equal (&i
.types
[0], ®ymm
)));
5219 if (register_number (i
.op
[0].regs
) != 0)
5220 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5222 for (j
= 1; j
< i
.operands
; j
++)
5224 i
.op
[j
- 1] = i
.op
[j
];
5225 i
.types
[j
- 1] = i
.types
[j
];
5227 /* We need to adjust fields in i.tm since they are used by
5228 build_modrm_byte. */
5229 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5236 else if (i
.tm
.opcode_modifier
.regkludge
)
5238 /* The imul $imm, %reg instruction is converted into
5239 imul $imm, %reg, %reg, and the clr %reg instruction
5240 is converted into xor %reg, %reg. */
5242 unsigned int first_reg_op
;
5244 if (operand_type_check (i
.types
[0], reg
))
5248 /* Pretend we saw the extra register operand. */
5249 gas_assert (i
.reg_operands
== 1
5250 && i
.op
[first_reg_op
+ 1].regs
== 0);
5251 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5252 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5257 if (i
.tm
.opcode_modifier
.shortform
)
5259 if (i
.types
[0].bitfield
.sreg2
5260 || i
.types
[0].bitfield
.sreg3
)
5262 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5263 && i
.op
[0].regs
->reg_num
== 1)
5265 as_bad (_("you can't `pop %scs'"), register_prefix
);
5268 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5269 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5274 /* The register or float register operand is in operand
5278 if (i
.types
[0].bitfield
.floatreg
5279 || operand_type_check (i
.types
[0], reg
))
5283 /* Register goes in low 3 bits of opcode. */
5284 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5285 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5287 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5289 /* Warn about some common errors, but press on regardless.
5290 The first case can be generated by gcc (<= 2.8.1). */
5291 if (i
.operands
== 2)
5293 /* Reversed arguments on faddp, fsubp, etc. */
5294 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5295 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5296 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5300 /* Extraneous `l' suffix on fp insn. */
5301 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5302 register_prefix
, i
.op
[0].regs
->reg_name
);
5307 else if (i
.tm
.opcode_modifier
.modrm
)
5309 /* The opcode is completed (modulo i.tm.extension_opcode which
5310 must be put into the modrm byte). Now, we make the modrm and
5311 index base bytes based on all the info we've collected. */
5313 default_seg
= build_modrm_byte ();
5315 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5319 else if (i
.tm
.opcode_modifier
.isstring
)
5321 /* For the string instructions that allow a segment override
5322 on one of their operands, the default segment is ds. */
5326 if (i
.tm
.base_opcode
== 0x8d /* lea */
5329 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5331 /* If a segment was explicitly specified, and the specified segment
5332 is not the default, use an opcode prefix to select it. If we
5333 never figured out what the default segment is, then default_seg
5334 will be zero at this point, and the specified segment prefix will
5336 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5338 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5344 static const seg_entry
*
5345 build_modrm_byte (void)
5347 const seg_entry
*default_seg
= 0;
5348 unsigned int source
, dest
;
5351 /* The first operand of instructions with VEX prefix and 3 sources
5352 must be VEX_Imm4. */
5353 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5356 unsigned int nds
, reg_slot
;
5359 if (i
.tm
.opcode_modifier
.veximmext
5360 && i
.tm
.opcode_modifier
.immext
)
5362 dest
= i
.operands
- 2;
5363 gas_assert (dest
== 3);
5366 dest
= i
.operands
- 1;
5369 /* There are 2 kinds of instructions:
5370 1. 5 operands: 4 register operands or 3 register operands
5371 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5372 VexW0 or VexW1. The destination must be either XMM or YMM
5374 2. 4 operands: 4 register operands or 3 register operands
5375 plus 1 memory operand, VexXDS, and VexImmExt */
5376 gas_assert ((i
.reg_operands
== 4
5377 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5378 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5379 && (i
.tm
.opcode_modifier
.veximmext
5380 || (i
.imm_operands
== 1
5381 && i
.types
[0].bitfield
.vec_imm4
5382 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5383 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5384 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5385 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5387 if (i
.imm_operands
== 0)
5389 /* When there is no immediate operand, generate an 8bit
5390 immediate operand to encode the first operand. */
5391 exp
= &im_expressions
[i
.imm_operands
++];
5392 i
.op
[i
.operands
].imms
= exp
;
5393 i
.types
[i
.operands
] = imm8
;
5395 /* If VexW1 is set, the first operand is the source and
5396 the second operand is encoded in the immediate operand. */
5397 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5408 /* FMA swaps REG and NDS. */
5409 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5417 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5419 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5421 exp
->X_op
= O_constant
;
5422 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5426 unsigned int imm_slot
;
5428 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5430 /* If VexW0 is set, the third operand is the source and
5431 the second operand is encoded in the immediate
5438 /* VexW1 is set, the second operand is the source and
5439 the third operand is encoded in the immediate
5445 if (i
.tm
.opcode_modifier
.immext
)
5447 /* When ImmExt is set, the immdiate byte is the last
5449 imm_slot
= i
.operands
- 1;
5457 /* Turn on Imm8 so that output_imm will generate it. */
5458 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5461 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5463 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5465 i
.op
[imm_slot
].imms
->X_add_number
5466 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5469 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5470 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5472 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5477 /* i.reg_operands MUST be the number of real register operands;
5478 implicit registers do not count. If there are 3 register
5479 operands, it must be a instruction with VexNDS. For a
5480 instruction with VexNDD, the destination register is encoded
5481 in VEX prefix. If there are 4 register operands, it must be
5482 a instruction with VEX prefix and 3 sources. */
5483 if (i
.mem_operands
== 0
5484 && ((i
.reg_operands
== 2
5485 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5486 || (i
.reg_operands
== 3
5487 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5488 || (i
.reg_operands
== 4 && vex_3_sources
)))
5496 /* When there are 3 operands, one of them may be immediate,
5497 which may be the first or the last operand. Otherwise,
5498 the first operand must be shift count register (cl) or it
5499 is an instruction with VexNDS. */
5500 gas_assert (i
.imm_operands
== 1
5501 || (i
.imm_operands
== 0
5502 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5503 || i
.types
[0].bitfield
.shiftcount
)));
5504 if (operand_type_check (i
.types
[0], imm
)
5505 || i
.types
[0].bitfield
.shiftcount
)
5511 /* When there are 4 operands, the first two must be 8bit
5512 immediate operands. The source operand will be the 3rd
5515 For instructions with VexNDS, if the first operand
5516 an imm8, the source operand is the 2nd one. If the last
5517 operand is imm8, the source operand is the first one. */
5518 gas_assert ((i
.imm_operands
== 2
5519 && i
.types
[0].bitfield
.imm8
5520 && i
.types
[1].bitfield
.imm8
)
5521 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5522 && i
.imm_operands
== 1
5523 && (i
.types
[0].bitfield
.imm8
5524 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5525 if (i
.imm_operands
== 2)
5529 if (i
.types
[0].bitfield
.imm8
)
5545 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5547 /* For instructions with VexNDS, the register-only
5548 source operand must be 32/64bit integer, XMM or
5549 YMM register. It is encoded in VEX prefix. We
5550 need to clear RegMem bit before calling
5551 operand_type_equal. */
5553 i386_operand_type op
;
5556 /* Check register-only source operand when two source
5557 operands are swapped. */
5558 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5559 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5567 op
= i
.tm
.operand_types
[vvvv
];
5568 op
.bitfield
.regmem
= 0;
5569 if ((dest
+ 1) >= i
.operands
5570 || (op
.bitfield
.reg32
!= 1
5571 && !op
.bitfield
.reg64
!= 1
5572 && !operand_type_equal (&op
, ®xmm
)
5573 && !operand_type_equal (&op
, ®ymm
)))
5575 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5581 /* One of the register operands will be encoded in the i.tm.reg
5582 field, the other in the combined i.tm.mode and i.tm.regmem
5583 fields. If no form of this instruction supports a memory
5584 destination operand, then we assume the source operand may
5585 sometimes be a memory operand and so we need to store the
5586 destination in the i.rm.reg field. */
5587 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5588 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5590 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5591 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5592 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5594 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5599 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5600 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5601 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5603 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5606 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5608 if (!i
.types
[0].bitfield
.control
5609 && !i
.types
[1].bitfield
.control
)
5611 i
.rex
&= ~(REX_R
| REX_B
);
5612 add_prefix (LOCK_PREFIX_OPCODE
);
5616 { /* If it's not 2 reg operands... */
5621 unsigned int fake_zero_displacement
= 0;
5624 for (op
= 0; op
< i
.operands
; op
++)
5625 if (operand_type_check (i
.types
[op
], anymem
))
5627 gas_assert (op
< i
.operands
);
5629 if (i
.tm
.opcode_modifier
.vecsib
)
5631 if (i
.index_reg
->reg_num
== RegEiz
5632 || i
.index_reg
->reg_num
== RegRiz
)
5635 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5638 i
.sib
.base
= NO_BASE_REGISTER
;
5639 i
.sib
.scale
= i
.log2_scale_factor
;
5640 i
.types
[op
].bitfield
.disp8
= 0;
5641 i
.types
[op
].bitfield
.disp16
= 0;
5642 i
.types
[op
].bitfield
.disp64
= 0;
5643 if (flag_code
!= CODE_64BIT
)
5645 /* Must be 32 bit */
5646 i
.types
[op
].bitfield
.disp32
= 1;
5647 i
.types
[op
].bitfield
.disp32s
= 0;
5651 i
.types
[op
].bitfield
.disp32
= 0;
5652 i
.types
[op
].bitfield
.disp32s
= 1;
5655 i
.sib
.index
= i
.index_reg
->reg_num
;
5656 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5662 if (i
.base_reg
== 0)
5665 if (!i
.disp_operands
)
5667 fake_zero_displacement
= 1;
5668 /* Instructions with VSIB byte need 32bit displacement
5669 if there is no base register. */
5670 if (i
.tm
.opcode_modifier
.vecsib
)
5671 i
.types
[op
].bitfield
.disp32
= 1;
5673 if (i
.index_reg
== 0)
5675 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5676 /* Operand is just <disp> */
5677 if (flag_code
== CODE_64BIT
)
5679 /* 64bit mode overwrites the 32bit absolute
5680 addressing by RIP relative addressing and
5681 absolute addressing is encoded by one of the
5682 redundant SIB forms. */
5683 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5684 i
.sib
.base
= NO_BASE_REGISTER
;
5685 i
.sib
.index
= NO_INDEX_REGISTER
;
5686 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5687 ? disp32s
: disp32
);
5689 else if ((flag_code
== CODE_16BIT
)
5690 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5692 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5693 i
.types
[op
] = disp16
;
5697 i
.rm
.regmem
= NO_BASE_REGISTER
;
5698 i
.types
[op
] = disp32
;
5701 else if (!i
.tm
.opcode_modifier
.vecsib
)
5703 /* !i.base_reg && i.index_reg */
5704 if (i
.index_reg
->reg_num
== RegEiz
5705 || i
.index_reg
->reg_num
== RegRiz
)
5706 i
.sib
.index
= NO_INDEX_REGISTER
;
5708 i
.sib
.index
= i
.index_reg
->reg_num
;
5709 i
.sib
.base
= NO_BASE_REGISTER
;
5710 i
.sib
.scale
= i
.log2_scale_factor
;
5711 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5712 i
.types
[op
].bitfield
.disp8
= 0;
5713 i
.types
[op
].bitfield
.disp16
= 0;
5714 i
.types
[op
].bitfield
.disp64
= 0;
5715 if (flag_code
!= CODE_64BIT
)
5717 /* Must be 32 bit */
5718 i
.types
[op
].bitfield
.disp32
= 1;
5719 i
.types
[op
].bitfield
.disp32s
= 0;
5723 i
.types
[op
].bitfield
.disp32
= 0;
5724 i
.types
[op
].bitfield
.disp32s
= 1;
5726 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5730 /* RIP addressing for 64bit mode. */
5731 else if (i
.base_reg
->reg_num
== RegRip
||
5732 i
.base_reg
->reg_num
== RegEip
)
5734 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5735 i
.rm
.regmem
= NO_BASE_REGISTER
;
5736 i
.types
[op
].bitfield
.disp8
= 0;
5737 i
.types
[op
].bitfield
.disp16
= 0;
5738 i
.types
[op
].bitfield
.disp32
= 0;
5739 i
.types
[op
].bitfield
.disp32s
= 1;
5740 i
.types
[op
].bitfield
.disp64
= 0;
5741 i
.flags
[op
] |= Operand_PCrel
;
5742 if (! i
.disp_operands
)
5743 fake_zero_displacement
= 1;
5745 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5747 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5748 switch (i
.base_reg
->reg_num
)
5751 if (i
.index_reg
== 0)
5753 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5754 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5758 if (i
.index_reg
== 0)
5761 if (operand_type_check (i
.types
[op
], disp
) == 0)
5763 /* fake (%bp) into 0(%bp) */
5764 i
.types
[op
].bitfield
.disp8
= 1;
5765 fake_zero_displacement
= 1;
5768 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5769 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5771 default: /* (%si) -> 4 or (%di) -> 5 */
5772 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5774 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5776 else /* i.base_reg and 32/64 bit mode */
5778 if (flag_code
== CODE_64BIT
5779 && operand_type_check (i
.types
[op
], disp
))
5781 i386_operand_type temp
;
5782 operand_type_set (&temp
, 0);
5783 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5785 if (i
.prefix
[ADDR_PREFIX
] == 0)
5786 i
.types
[op
].bitfield
.disp32s
= 1;
5788 i
.types
[op
].bitfield
.disp32
= 1;
5791 if (!i
.tm
.opcode_modifier
.vecsib
)
5792 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5793 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5795 i
.sib
.base
= i
.base_reg
->reg_num
;
5796 /* x86-64 ignores REX prefix bit here to avoid decoder
5798 if (!(i
.base_reg
->reg_flags
& RegRex
)
5799 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5800 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5802 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5804 fake_zero_displacement
= 1;
5805 i
.types
[op
].bitfield
.disp8
= 1;
5807 i
.sib
.scale
= i
.log2_scale_factor
;
5808 if (i
.index_reg
== 0)
5810 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5811 /* <disp>(%esp) becomes two byte modrm with no index
5812 register. We've already stored the code for esp
5813 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5814 Any base register besides %esp will not use the
5815 extra modrm byte. */
5816 i
.sib
.index
= NO_INDEX_REGISTER
;
5818 else if (!i
.tm
.opcode_modifier
.vecsib
)
5820 if (i
.index_reg
->reg_num
== RegEiz
5821 || i
.index_reg
->reg_num
== RegRiz
)
5822 i
.sib
.index
= NO_INDEX_REGISTER
;
5824 i
.sib
.index
= i
.index_reg
->reg_num
;
5825 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5826 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5831 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5832 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5836 if (!fake_zero_displacement
5840 fake_zero_displacement
= 1;
5841 if (i
.disp_encoding
== disp_encoding_8bit
)
5842 i
.types
[op
].bitfield
.disp8
= 1;
5844 i
.types
[op
].bitfield
.disp32
= 1;
5846 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5850 if (fake_zero_displacement
)
5852 /* Fakes a zero displacement assuming that i.types[op]
5853 holds the correct displacement size. */
5856 gas_assert (i
.op
[op
].disps
== 0);
5857 exp
= &disp_expressions
[i
.disp_operands
++];
5858 i
.op
[op
].disps
= exp
;
5859 exp
->X_op
= O_constant
;
5860 exp
->X_add_number
= 0;
5861 exp
->X_add_symbol
= (symbolS
*) 0;
5862 exp
->X_op_symbol
= (symbolS
*) 0;
5870 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5872 if (operand_type_check (i
.types
[0], imm
))
5873 i
.vex
.register_specifier
= NULL
;
5876 /* VEX.vvvv encodes one of the sources when the first
5877 operand is not an immediate. */
5878 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5879 i
.vex
.register_specifier
= i
.op
[0].regs
;
5881 i
.vex
.register_specifier
= i
.op
[1].regs
;
5884 /* Destination is a XMM register encoded in the ModRM.reg
5886 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5887 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5890 /* ModRM.rm and VEX.B encodes the other source. */
5891 if (!i
.mem_operands
)
5895 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5896 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5898 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5900 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5904 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5906 i
.vex
.register_specifier
= i
.op
[2].regs
;
5907 if (!i
.mem_operands
)
5910 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5911 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5915 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5916 (if any) based on i.tm.extension_opcode. Again, we must be
5917 careful to make sure that segment/control/debug/test/MMX
5918 registers are coded into the i.rm.reg field. */
5919 else if (i
.reg_operands
)
5922 unsigned int vex_reg
= ~0;
5924 for (op
= 0; op
< i
.operands
; op
++)
5925 if (i
.types
[op
].bitfield
.reg8
5926 || i
.types
[op
].bitfield
.reg16
5927 || i
.types
[op
].bitfield
.reg32
5928 || i
.types
[op
].bitfield
.reg64
5929 || i
.types
[op
].bitfield
.regmmx
5930 || i
.types
[op
].bitfield
.regxmm
5931 || i
.types
[op
].bitfield
.regymm
5932 || i
.types
[op
].bitfield
.sreg2
5933 || i
.types
[op
].bitfield
.sreg3
5934 || i
.types
[op
].bitfield
.control
5935 || i
.types
[op
].bitfield
.debug
5936 || i
.types
[op
].bitfield
.test
)
5941 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5943 /* For instructions with VexNDS, the register-only
5944 source operand is encoded in VEX prefix. */
5945 gas_assert (mem
!= (unsigned int) ~0);
5950 gas_assert (op
< i
.operands
);
5954 /* Check register-only source operand when two source
5955 operands are swapped. */
5956 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5957 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5961 gas_assert (mem
== (vex_reg
+ 1)
5962 && op
< i
.operands
);
5967 gas_assert (vex_reg
< i
.operands
);
5971 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5973 /* For instructions with VexNDD, the register destination
5974 is encoded in VEX prefix. */
5975 if (i
.mem_operands
== 0)
5977 /* There is no memory operand. */
5978 gas_assert ((op
+ 2) == i
.operands
);
5983 /* There are only 2 operands. */
5984 gas_assert (op
< 2 && i
.operands
== 2);
5989 gas_assert (op
< i
.operands
);
5991 if (vex_reg
!= (unsigned int) ~0)
5993 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5995 if (type
->bitfield
.reg32
!= 1
5996 && type
->bitfield
.reg64
!= 1
5997 && !operand_type_equal (type
, ®xmm
)
5998 && !operand_type_equal (type
, ®ymm
))
6001 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6004 /* Don't set OP operand twice. */
6007 /* If there is an extension opcode to put here, the
6008 register number must be put into the regmem field. */
6009 if (i
.tm
.extension_opcode
!= None
)
6011 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6012 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6017 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6018 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6023 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6024 must set it to 3 to indicate this is a register operand
6025 in the regmem field. */
6026 if (!i
.mem_operands
)
6030 /* Fill in i.rm.reg field with extension opcode (if any). */
6031 if (i
.tm
.extension_opcode
!= None
)
6032 i
.rm
.reg
= i
.tm
.extension_opcode
;
6038 output_branch (void)
6044 relax_substateT subtype
;
6048 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6049 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6052 if (i
.prefix
[DATA_PREFIX
] != 0)
6058 /* Pentium4 branch hints. */
6059 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6060 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6065 if (i
.prefix
[REX_PREFIX
] != 0)
6071 if (i
.prefixes
!= 0 && !intel_syntax
)
6072 as_warn (_("skipping prefixes on this instruction"));
6074 /* It's always a symbol; End frag & setup for relax.
6075 Make sure there is enough room in this frag for the largest
6076 instruction we may generate in md_convert_frag. This is 2
6077 bytes for the opcode and room for the prefix and largest
6079 frag_grow (prefix
+ 2 + 4);
6080 /* Prefix and 1 opcode byte go in fr_fix. */
6081 p
= frag_more (prefix
+ 1);
6082 if (i
.prefix
[DATA_PREFIX
] != 0)
6083 *p
++ = DATA_PREFIX_OPCODE
;
6084 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6085 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6086 *p
++ = i
.prefix
[SEG_PREFIX
];
6087 if (i
.prefix
[REX_PREFIX
] != 0)
6088 *p
++ = i
.prefix
[REX_PREFIX
];
6089 *p
= i
.tm
.base_opcode
;
6091 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6092 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6093 else if (cpu_arch_flags
.bitfield
.cpui386
)
6094 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6096 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6099 sym
= i
.op
[0].disps
->X_add_symbol
;
6100 off
= i
.op
[0].disps
->X_add_number
;
6102 if (i
.op
[0].disps
->X_op
!= O_constant
6103 && i
.op
[0].disps
->X_op
!= O_symbol
)
6105 /* Handle complex expressions. */
6106 sym
= make_expr_symbol (i
.op
[0].disps
);
6110 /* 1 possible extra opcode + 4 byte displacement go in var part.
6111 Pass reloc in fr_var. */
6112 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6122 if (i
.tm
.opcode_modifier
.jumpbyte
)
6124 /* This is a loop or jecxz type instruction. */
6126 if (i
.prefix
[ADDR_PREFIX
] != 0)
6128 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6131 /* Pentium4 branch hints. */
6132 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6133 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6135 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6144 if (flag_code
== CODE_16BIT
)
6147 if (i
.prefix
[DATA_PREFIX
] != 0)
6149 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6159 if (i
.prefix
[REX_PREFIX
] != 0)
6161 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6165 if (i
.prefixes
!= 0 && !intel_syntax
)
6166 as_warn (_("skipping prefixes on this instruction"));
6168 p
= frag_more (i
.tm
.opcode_length
+ size
);
6169 switch (i
.tm
.opcode_length
)
6172 *p
++ = i
.tm
.base_opcode
>> 8;
6174 *p
++ = i
.tm
.base_opcode
;
6180 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6181 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6183 /* All jumps handled here are signed, but don't use a signed limit
6184 check for 32 and 16 bit jumps as we want to allow wrap around at
6185 4G and 64k respectively. */
6187 fixP
->fx_signed
= 1;
6191 output_interseg_jump (void)
6199 if (flag_code
== CODE_16BIT
)
6203 if (i
.prefix
[DATA_PREFIX
] != 0)
6209 if (i
.prefix
[REX_PREFIX
] != 0)
6219 if (i
.prefixes
!= 0 && !intel_syntax
)
6220 as_warn (_("skipping prefixes on this instruction"));
6222 /* 1 opcode; 2 segment; offset */
6223 p
= frag_more (prefix
+ 1 + 2 + size
);
6225 if (i
.prefix
[DATA_PREFIX
] != 0)
6226 *p
++ = DATA_PREFIX_OPCODE
;
6228 if (i
.prefix
[REX_PREFIX
] != 0)
6229 *p
++ = i
.prefix
[REX_PREFIX
];
6231 *p
++ = i
.tm
.base_opcode
;
6232 if (i
.op
[1].imms
->X_op
== O_constant
)
6234 offsetT n
= i
.op
[1].imms
->X_add_number
;
6237 && !fits_in_unsigned_word (n
)
6238 && !fits_in_signed_word (n
))
6240 as_bad (_("16-bit jump out of range"));
6243 md_number_to_chars (p
, n
, size
);
6246 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6247 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6248 if (i
.op
[0].imms
->X_op
!= O_constant
)
6249 as_bad (_("can't handle non absolute segment in `%s'"),
6251 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6257 fragS
*insn_start_frag
;
6258 offsetT insn_start_off
;
6260 /* Tie dwarf2 debug info to the address at the start of the insn.
6261 We can't do this after the insn has been output as the current
6262 frag may have been closed off. eg. by frag_var. */
6263 dwarf2_emit_insn (0);
6265 insn_start_frag
= frag_now
;
6266 insn_start_off
= frag_now_fix ();
6269 if (i
.tm
.opcode_modifier
.jump
)
6271 else if (i
.tm
.opcode_modifier
.jumpbyte
6272 || i
.tm
.opcode_modifier
.jumpdword
)
6274 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6275 output_interseg_jump ();
6278 /* Output normal instructions here. */
6282 unsigned int prefix
;
6284 /* Since the VEX prefix contains the implicit prefix, we don't
6285 need the explicit prefix. */
6286 if (!i
.tm
.opcode_modifier
.vex
)
6288 switch (i
.tm
.opcode_length
)
6291 if (i
.tm
.base_opcode
& 0xff000000)
6293 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6298 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6300 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6301 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6304 if (prefix
!= REPE_PREFIX_OPCODE
6305 || (i
.prefix
[REP_PREFIX
]
6306 != REPE_PREFIX_OPCODE
))
6307 add_prefix (prefix
);
6310 add_prefix (prefix
);
6319 /* The prefix bytes. */
6320 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6322 FRAG_APPEND_1_CHAR (*q
);
6326 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6331 /* REX byte is encoded in VEX prefix. */
6335 FRAG_APPEND_1_CHAR (*q
);
6338 /* There should be no other prefixes for instructions
6343 /* Now the VEX prefix. */
6344 p
= frag_more (i
.vex
.length
);
6345 for (j
= 0; j
< i
.vex
.length
; j
++)
6346 p
[j
] = i
.vex
.bytes
[j
];
6349 /* Now the opcode; be careful about word order here! */
6350 if (i
.tm
.opcode_length
== 1)
6352 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6356 switch (i
.tm
.opcode_length
)
6360 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6370 /* Put out high byte first: can't use md_number_to_chars! */
6371 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6372 *p
= i
.tm
.base_opcode
& 0xff;
6375 /* Now the modrm byte and sib byte (if present). */
6376 if (i
.tm
.opcode_modifier
.modrm
)
6378 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6381 /* If i.rm.regmem == ESP (4)
6382 && i.rm.mode != (Register mode)
6384 ==> need second modrm byte. */
6385 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6387 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6388 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6390 | i
.sib
.scale
<< 6));
6393 if (i
.disp_operands
)
6394 output_disp (insn_start_frag
, insn_start_off
);
6397 output_imm (insn_start_frag
, insn_start_off
);
6403 pi ("" /*line*/, &i
);
6405 #endif /* DEBUG386 */
6408 /* Return the size of the displacement operand N. */
6411 disp_size (unsigned int n
)
6414 if (i
.types
[n
].bitfield
.disp64
)
6416 else if (i
.types
[n
].bitfield
.disp8
)
6418 else if (i
.types
[n
].bitfield
.disp16
)
6423 /* Return the size of the immediate operand N. */
6426 imm_size (unsigned int n
)
6429 if (i
.types
[n
].bitfield
.imm64
)
6431 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6433 else if (i
.types
[n
].bitfield
.imm16
)
6439 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6444 for (n
= 0; n
< i
.operands
; n
++)
6446 if (operand_type_check (i
.types
[n
], disp
))
6448 if (i
.op
[n
].disps
->X_op
== O_constant
)
6450 int size
= disp_size (n
);
6453 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6455 p
= frag_more (size
);
6456 md_number_to_chars (p
, val
, size
);
6460 enum bfd_reloc_code_real reloc_type
;
6461 int size
= disp_size (n
);
6462 int sign
= i
.types
[n
].bitfield
.disp32s
;
6463 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6465 /* We can't have 8 bit displacement here. */
6466 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6468 /* The PC relative address is computed relative
6469 to the instruction boundary, so in case immediate
6470 fields follows, we need to adjust the value. */
6471 if (pcrel
&& i
.imm_operands
)
6476 for (n1
= 0; n1
< i
.operands
; n1
++)
6477 if (operand_type_check (i
.types
[n1
], imm
))
6479 /* Only one immediate is allowed for PC
6480 relative address. */
6481 gas_assert (sz
== 0);
6483 i
.op
[n
].disps
->X_add_number
-= sz
;
6485 /* We should find the immediate. */
6486 gas_assert (sz
!= 0);
6489 p
= frag_more (size
);
6490 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6492 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6493 && (((reloc_type
== BFD_RELOC_32
6494 || reloc_type
== BFD_RELOC_X86_64_32S
6495 || (reloc_type
== BFD_RELOC_64
6497 && (i
.op
[n
].disps
->X_op
== O_symbol
6498 || (i
.op
[n
].disps
->X_op
== O_add
6499 && ((symbol_get_value_expression
6500 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6502 || reloc_type
== BFD_RELOC_32_PCREL
))
6506 if (insn_start_frag
== frag_now
)
6507 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6512 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6513 for (fr
= insn_start_frag
->fr_next
;
6514 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6516 add
+= p
- frag_now
->fr_literal
;
6521 reloc_type
= BFD_RELOC_386_GOTPC
;
6522 i
.op
[n
].imms
->X_add_number
+= add
;
6524 else if (reloc_type
== BFD_RELOC_64
)
6525 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6527 /* Don't do the adjustment for x86-64, as there
6528 the pcrel addressing is relative to the _next_
6529 insn, and that is taken care of in other code. */
6530 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6532 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6533 i
.op
[n
].disps
, pcrel
, reloc_type
);
6540 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6545 for (n
= 0; n
< i
.operands
; n
++)
6547 if (operand_type_check (i
.types
[n
], imm
))
6549 if (i
.op
[n
].imms
->X_op
== O_constant
)
6551 int size
= imm_size (n
);
6554 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6556 p
= frag_more (size
);
6557 md_number_to_chars (p
, val
, size
);
6561 /* Not absolute_section.
6562 Need a 32-bit fixup (don't support 8bit
6563 non-absolute imms). Try to support other
6565 enum bfd_reloc_code_real reloc_type
;
6566 int size
= imm_size (n
);
6569 if (i
.types
[n
].bitfield
.imm32s
6570 && (i
.suffix
== QWORD_MNEM_SUFFIX
6571 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6576 p
= frag_more (size
);
6577 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6579 /* This is tough to explain. We end up with this one if we
6580 * have operands that look like
6581 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6582 * obtain the absolute address of the GOT, and it is strongly
6583 * preferable from a performance point of view to avoid using
6584 * a runtime relocation for this. The actual sequence of
6585 * instructions often look something like:
6590 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6592 * The call and pop essentially return the absolute address
6593 * of the label .L66 and store it in %ebx. The linker itself
6594 * will ultimately change the first operand of the addl so
6595 * that %ebx points to the GOT, but to keep things simple, the
6596 * .o file must have this operand set so that it generates not
6597 * the absolute address of .L66, but the absolute address of
6598 * itself. This allows the linker itself simply treat a GOTPC
6599 * relocation as asking for a pcrel offset to the GOT to be
6600 * added in, and the addend of the relocation is stored in the
6601 * operand field for the instruction itself.
6603 * Our job here is to fix the operand so that it would add
6604 * the correct offset so that %ebx would point to itself. The
6605 * thing that is tricky is that .-.L66 will point to the
6606 * beginning of the instruction, so we need to further modify
6607 * the operand so that it will point to itself. There are
6608 * other cases where you have something like:
6610 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6612 * and here no correction would be required. Internally in
6613 * the assembler we treat operands of this form as not being
6614 * pcrel since the '.' is explicitly mentioned, and I wonder
6615 * whether it would simplify matters to do it this way. Who
6616 * knows. In earlier versions of the PIC patches, the
6617 * pcrel_adjust field was used to store the correction, but
6618 * since the expression is not pcrel, I felt it would be
6619 * confusing to do it this way. */
6621 if ((reloc_type
== BFD_RELOC_32
6622 || reloc_type
== BFD_RELOC_X86_64_32S
6623 || reloc_type
== BFD_RELOC_64
)
6625 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6626 && (i
.op
[n
].imms
->X_op
== O_symbol
6627 || (i
.op
[n
].imms
->X_op
== O_add
6628 && ((symbol_get_value_expression
6629 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6634 if (insn_start_frag
== frag_now
)
6635 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6640 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6641 for (fr
= insn_start_frag
->fr_next
;
6642 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6644 add
+= p
- frag_now
->fr_literal
;
6648 reloc_type
= BFD_RELOC_386_GOTPC
;
6650 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6652 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6653 i
.op
[n
].imms
->X_add_number
+= add
;
6655 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6656 i
.op
[n
].imms
, 0, reloc_type
);
6662 /* x86_cons_fix_new is called via the expression parsing code when a
6663 reloc is needed. We use this hook to get the correct .got reloc. */
6664 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6665 static int cons_sign
= -1;
6668 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6671 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6673 got_reloc
= NO_RELOC
;
6676 if (exp
->X_op
== O_secrel
)
6678 exp
->X_op
= O_symbol
;
6679 r
= BFD_RELOC_32_SECREL
;
6683 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6686 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6687 purpose of the `.dc.a' internal pseudo-op. */
6690 x86_address_bytes (void)
6692 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6694 return stdoutput
->arch_info
->bits_per_address
/ 8;
6697 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6699 # define lex_got(reloc, adjust, types) NULL
6701 /* Parse operands of the form
6702 <symbol>@GOTOFF+<nnn>
6703 and similar .plt or .got references.
6705 If we find one, set up the correct relocation in RELOC and copy the
6706 input string, minus the `@GOTOFF' into a malloc'd buffer for
6707 parsing by the calling routine. Return this buffer, and if ADJUST
6708 is non-null set it to the length of the string we removed from the
6709 input line. Otherwise return NULL. */
6711 lex_got (enum bfd_reloc_code_real
*rel
,
6713 i386_operand_type
*types
)
6715 /* Some of the relocations depend on the size of what field is to
6716 be relocated. But in our callers i386_immediate and i386_displacement
6717 we don't yet know the operand size (this will be set by insn
6718 matching). Hence we record the word32 relocation here,
6719 and adjust the reloc according to the real size in reloc(). */
6720 static const struct {
6723 const enum bfd_reloc_code_real rel
[2];
6724 const i386_operand_type types64
;
6726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6727 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6729 OPERAND_TYPE_IMM32_64
},
6731 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6732 BFD_RELOC_X86_64_PLTOFF64
},
6733 OPERAND_TYPE_IMM64
},
6734 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6735 BFD_RELOC_X86_64_PLT32
},
6736 OPERAND_TYPE_IMM32_32S_DISP32
},
6737 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6738 BFD_RELOC_X86_64_GOTPLT64
},
6739 OPERAND_TYPE_IMM64_DISP64
},
6740 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6741 BFD_RELOC_X86_64_GOTOFF64
},
6742 OPERAND_TYPE_IMM64_DISP64
},
6743 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6744 BFD_RELOC_X86_64_GOTPCREL
},
6745 OPERAND_TYPE_IMM32_32S_DISP32
},
6746 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6747 BFD_RELOC_X86_64_TLSGD
},
6748 OPERAND_TYPE_IMM32_32S_DISP32
},
6749 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6750 _dummy_first_bfd_reloc_code_real
},
6751 OPERAND_TYPE_NONE
},
6752 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6753 BFD_RELOC_X86_64_TLSLD
},
6754 OPERAND_TYPE_IMM32_32S_DISP32
},
6755 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6756 BFD_RELOC_X86_64_GOTTPOFF
},
6757 OPERAND_TYPE_IMM32_32S_DISP32
},
6758 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6759 BFD_RELOC_X86_64_TPOFF32
},
6760 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6761 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6762 _dummy_first_bfd_reloc_code_real
},
6763 OPERAND_TYPE_NONE
},
6764 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6765 BFD_RELOC_X86_64_DTPOFF32
},
6766 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6767 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6768 _dummy_first_bfd_reloc_code_real
},
6769 OPERAND_TYPE_NONE
},
6770 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6771 _dummy_first_bfd_reloc_code_real
},
6772 OPERAND_TYPE_NONE
},
6773 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6774 BFD_RELOC_X86_64_GOT32
},
6775 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6776 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6777 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6778 OPERAND_TYPE_IMM32_32S_DISP32
},
6779 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6780 BFD_RELOC_X86_64_TLSDESC_CALL
},
6781 OPERAND_TYPE_IMM32_32S_DISP32
},
6786 #if defined (OBJ_MAYBE_ELF)
6791 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6792 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6795 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6797 int len
= gotrel
[j
].len
;
6798 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6800 if (gotrel
[j
].rel
[object_64bit
] != 0)
6803 char *tmpbuf
, *past_reloc
;
6805 *rel
= gotrel
[j
].rel
[object_64bit
];
6809 if (flag_code
!= CODE_64BIT
)
6811 types
->bitfield
.imm32
= 1;
6812 types
->bitfield
.disp32
= 1;
6815 *types
= gotrel
[j
].types64
;
6818 if (j
!= 0 && GOT_symbol
== NULL
)
6819 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6821 /* The length of the first part of our input line. */
6822 first
= cp
- input_line_pointer
;
6824 /* The second part goes from after the reloc token until
6825 (and including) an end_of_line char or comma. */
6826 past_reloc
= cp
+ 1 + len
;
6828 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6830 second
= cp
+ 1 - past_reloc
;
6832 /* Allocate and copy string. The trailing NUL shouldn't
6833 be necessary, but be safe. */
6834 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6835 memcpy (tmpbuf
, input_line_pointer
, first
);
6836 if (second
!= 0 && *past_reloc
!= ' ')
6837 /* Replace the relocation token with ' ', so that
6838 errors like foo@GOTOFF1 will be detected. */
6839 tmpbuf
[first
++] = ' ';
6841 /* Increment length by 1 if the relocation token is
6846 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6847 tmpbuf
[first
+ second
] = '\0';
6851 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6852 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6857 /* Might be a symbol version string. Don't as_bad here. */
6866 /* Parse operands of the form
6867 <symbol>@SECREL32+<nnn>
6869 If we find one, set up the correct relocation in RELOC and copy the
6870 input string, minus the `@SECREL32' into a malloc'd buffer for
6871 parsing by the calling routine. Return this buffer, and if ADJUST
6872 is non-null set it to the length of the string we removed from the
6873 input line. Otherwise return NULL.
6875 This function is copied from the ELF version above adjusted for PE targets. */
6878 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6879 int *adjust ATTRIBUTE_UNUSED
,
6880 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6886 const enum bfd_reloc_code_real rel
[2];
6887 const i386_operand_type types64
;
6891 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6892 BFD_RELOC_32_SECREL
},
6893 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6899 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6900 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6903 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6905 int len
= gotrel
[j
].len
;
6907 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6909 if (gotrel
[j
].rel
[object_64bit
] != 0)
6912 char *tmpbuf
, *past_reloc
;
6914 *rel
= gotrel
[j
].rel
[object_64bit
];
6920 if (flag_code
!= CODE_64BIT
)
6922 types
->bitfield
.imm32
= 1;
6923 types
->bitfield
.disp32
= 1;
6926 *types
= gotrel
[j
].types64
;
6929 /* The length of the first part of our input line. */
6930 first
= cp
- input_line_pointer
;
6932 /* The second part goes from after the reloc token until
6933 (and including) an end_of_line char or comma. */
6934 past_reloc
= cp
+ 1 + len
;
6936 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6938 second
= cp
+ 1 - past_reloc
;
6940 /* Allocate and copy string. The trailing NUL shouldn't
6941 be necessary, but be safe. */
6942 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6943 memcpy (tmpbuf
, input_line_pointer
, first
);
6944 if (second
!= 0 && *past_reloc
!= ' ')
6945 /* Replace the relocation token with ' ', so that
6946 errors like foo@SECLREL321 will be detected. */
6947 tmpbuf
[first
++] = ' ';
6948 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6949 tmpbuf
[first
+ second
] = '\0';
6953 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6954 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6959 /* Might be a symbol version string. Don't as_bad here. */
6966 x86_cons (expressionS
*exp
, int size
)
6968 intel_syntax
= -intel_syntax
;
6971 if (size
== 4 || (object_64bit
&& size
== 8))
6973 /* Handle @GOTOFF and the like in an expression. */
6975 char *gotfree_input_line
;
6978 save
= input_line_pointer
;
6979 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6980 if (gotfree_input_line
)
6981 input_line_pointer
= gotfree_input_line
;
6985 if (gotfree_input_line
)
6987 /* expression () has merrily parsed up to the end of line,
6988 or a comma - in the wrong buffer. Transfer how far
6989 input_line_pointer has moved to the right buffer. */
6990 input_line_pointer
= (save
6991 + (input_line_pointer
- gotfree_input_line
)
6993 free (gotfree_input_line
);
6994 if (exp
->X_op
== O_constant
6995 || exp
->X_op
== O_absent
6996 || exp
->X_op
== O_illegal
6997 || exp
->X_op
== O_register
6998 || exp
->X_op
== O_big
)
7000 char c
= *input_line_pointer
;
7001 *input_line_pointer
= 0;
7002 as_bad (_("missing or invalid expression `%s'"), save
);
7003 *input_line_pointer
= c
;
7010 intel_syntax
= -intel_syntax
;
7013 i386_intel_simplify (exp
);
7017 signed_cons (int size
)
7019 if (flag_code
== CODE_64BIT
)
7027 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7034 if (exp
.X_op
== O_symbol
)
7035 exp
.X_op
= O_secrel
;
7037 emit_expr (&exp
, 4);
7039 while (*input_line_pointer
++ == ',');
7041 input_line_pointer
--;
7042 demand_empty_rest_of_line ();
7047 i386_immediate (char *imm_start
)
7049 char *save_input_line_pointer
;
7050 char *gotfree_input_line
;
7053 i386_operand_type types
;
7055 operand_type_set (&types
, ~0);
7057 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7059 as_bad (_("at most %d immediate operands are allowed"),
7060 MAX_IMMEDIATE_OPERANDS
);
7064 exp
= &im_expressions
[i
.imm_operands
++];
7065 i
.op
[this_operand
].imms
= exp
;
7067 if (is_space_char (*imm_start
))
7070 save_input_line_pointer
= input_line_pointer
;
7071 input_line_pointer
= imm_start
;
7073 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7074 if (gotfree_input_line
)
7075 input_line_pointer
= gotfree_input_line
;
7077 exp_seg
= expression (exp
);
7080 if (*input_line_pointer
)
7081 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7083 input_line_pointer
= save_input_line_pointer
;
7084 if (gotfree_input_line
)
7086 free (gotfree_input_line
);
7088 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7089 exp
->X_op
= O_illegal
;
7092 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7096 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7097 i386_operand_type types
, const char *imm_start
)
7099 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7102 as_bad (_("missing or invalid immediate expression `%s'"),
7106 else if (exp
->X_op
== O_constant
)
7108 /* Size it properly later. */
7109 i
.types
[this_operand
].bitfield
.imm64
= 1;
7110 /* If not 64bit, sign extend val. */
7111 if (flag_code
!= CODE_64BIT
7112 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7114 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7116 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7117 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7118 && exp_seg
!= absolute_section
7119 && exp_seg
!= text_section
7120 && exp_seg
!= data_section
7121 && exp_seg
!= bss_section
7122 && exp_seg
!= undefined_section
7123 && !bfd_is_com_section (exp_seg
))
7125 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7129 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7132 as_bad (_("illegal immediate register operand %s"), imm_start
);
7137 /* This is an address. The size of the address will be
7138 determined later, depending on destination register,
7139 suffix, or the default for the section. */
7140 i
.types
[this_operand
].bitfield
.imm8
= 1;
7141 i
.types
[this_operand
].bitfield
.imm16
= 1;
7142 i
.types
[this_operand
].bitfield
.imm32
= 1;
7143 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7144 i
.types
[this_operand
].bitfield
.imm64
= 1;
7145 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7153 i386_scale (char *scale
)
7156 char *save
= input_line_pointer
;
7158 input_line_pointer
= scale
;
7159 val
= get_absolute_expression ();
7164 i
.log2_scale_factor
= 0;
7167 i
.log2_scale_factor
= 1;
7170 i
.log2_scale_factor
= 2;
7173 i
.log2_scale_factor
= 3;
7177 char sep
= *input_line_pointer
;
7179 *input_line_pointer
= '\0';
7180 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7182 *input_line_pointer
= sep
;
7183 input_line_pointer
= save
;
7187 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7189 as_warn (_("scale factor of %d without an index register"),
7190 1 << i
.log2_scale_factor
);
7191 i
.log2_scale_factor
= 0;
7193 scale
= input_line_pointer
;
7194 input_line_pointer
= save
;
7199 i386_displacement (char *disp_start
, char *disp_end
)
7203 char *save_input_line_pointer
;
7204 char *gotfree_input_line
;
7206 i386_operand_type bigdisp
, types
= anydisp
;
7209 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7211 as_bad (_("at most %d displacement operands are allowed"),
7212 MAX_MEMORY_OPERANDS
);
7216 operand_type_set (&bigdisp
, 0);
7217 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7218 || (!current_templates
->start
->opcode_modifier
.jump
7219 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7221 bigdisp
.bitfield
.disp32
= 1;
7222 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7223 if (flag_code
== CODE_64BIT
)
7227 bigdisp
.bitfield
.disp32s
= 1;
7228 bigdisp
.bitfield
.disp64
= 1;
7231 else if ((flag_code
== CODE_16BIT
) ^ override
)
7233 bigdisp
.bitfield
.disp32
= 0;
7234 bigdisp
.bitfield
.disp16
= 1;
7239 /* For PC-relative branches, the width of the displacement
7240 is dependent upon data size, not address size. */
7241 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7242 if (flag_code
== CODE_64BIT
)
7244 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7245 bigdisp
.bitfield
.disp16
= 1;
7248 bigdisp
.bitfield
.disp32
= 1;
7249 bigdisp
.bitfield
.disp32s
= 1;
7255 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7257 : LONG_MNEM_SUFFIX
));
7258 bigdisp
.bitfield
.disp32
= 1;
7259 if ((flag_code
== CODE_16BIT
) ^ override
)
7261 bigdisp
.bitfield
.disp32
= 0;
7262 bigdisp
.bitfield
.disp16
= 1;
7266 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7269 exp
= &disp_expressions
[i
.disp_operands
];
7270 i
.op
[this_operand
].disps
= exp
;
7272 save_input_line_pointer
= input_line_pointer
;
7273 input_line_pointer
= disp_start
;
7274 END_STRING_AND_SAVE (disp_end
);
7276 #ifndef GCC_ASM_O_HACK
7277 #define GCC_ASM_O_HACK 0
7280 END_STRING_AND_SAVE (disp_end
+ 1);
7281 if (i
.types
[this_operand
].bitfield
.baseIndex
7282 && displacement_string_end
[-1] == '+')
7284 /* This hack is to avoid a warning when using the "o"
7285 constraint within gcc asm statements.
7288 #define _set_tssldt_desc(n,addr,limit,type) \
7289 __asm__ __volatile__ ( \
7291 "movw %w1,2+%0\n\t" \
7293 "movb %b1,4+%0\n\t" \
7294 "movb %4,5+%0\n\t" \
7295 "movb $0,6+%0\n\t" \
7296 "movb %h1,7+%0\n\t" \
7298 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7300 This works great except that the output assembler ends
7301 up looking a bit weird if it turns out that there is
7302 no offset. You end up producing code that looks like:
7315 So here we provide the missing zero. */
7317 *displacement_string_end
= '0';
7320 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7321 if (gotfree_input_line
)
7322 input_line_pointer
= gotfree_input_line
;
7324 exp_seg
= expression (exp
);
7327 if (*input_line_pointer
)
7328 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7330 RESTORE_END_STRING (disp_end
+ 1);
7332 input_line_pointer
= save_input_line_pointer
;
7333 if (gotfree_input_line
)
7335 free (gotfree_input_line
);
7337 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7338 exp
->X_op
= O_illegal
;
7341 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7343 RESTORE_END_STRING (disp_end
);
7349 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7350 i386_operand_type types
, const char *disp_start
)
7352 i386_operand_type bigdisp
;
7355 /* We do this to make sure that the section symbol is in
7356 the symbol table. We will ultimately change the relocation
7357 to be relative to the beginning of the section. */
7358 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7359 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7360 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7362 if (exp
->X_op
!= O_symbol
)
7365 if (S_IS_LOCAL (exp
->X_add_symbol
)
7366 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7367 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7368 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7369 exp
->X_op
= O_subtract
;
7370 exp
->X_op_symbol
= GOT_symbol
;
7371 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7372 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7373 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7374 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7376 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7379 else if (exp
->X_op
== O_absent
7380 || exp
->X_op
== O_illegal
7381 || exp
->X_op
== O_big
)
7384 as_bad (_("missing or invalid displacement expression `%s'"),
7389 else if (flag_code
== CODE_64BIT
7390 && !i
.prefix
[ADDR_PREFIX
]
7391 && exp
->X_op
== O_constant
)
7393 /* Since displacement is signed extended to 64bit, don't allow
7394 disp32 and turn off disp32s if they are out of range. */
7395 i
.types
[this_operand
].bitfield
.disp32
= 0;
7396 if (!fits_in_signed_long (exp
->X_add_number
))
7398 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7399 if (i
.types
[this_operand
].bitfield
.baseindex
)
7401 as_bad (_("0x%lx out range of signed 32bit displacement"),
7402 (long) exp
->X_add_number
);
7408 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7409 else if (exp
->X_op
!= O_constant
7410 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7411 && exp_seg
!= absolute_section
7412 && exp_seg
!= text_section
7413 && exp_seg
!= data_section
7414 && exp_seg
!= bss_section
7415 && exp_seg
!= undefined_section
7416 && !bfd_is_com_section (exp_seg
))
7418 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7423 /* Check if this is a displacement only operand. */
7424 bigdisp
= i
.types
[this_operand
];
7425 bigdisp
.bitfield
.disp8
= 0;
7426 bigdisp
.bitfield
.disp16
= 0;
7427 bigdisp
.bitfield
.disp32
= 0;
7428 bigdisp
.bitfield
.disp32s
= 0;
7429 bigdisp
.bitfield
.disp64
= 0;
7430 if (operand_type_all_zero (&bigdisp
))
7431 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7437 /* Make sure the memory operand we've been dealt is valid.
7438 Return 1 on success, 0 on a failure. */
7441 i386_index_check (const char *operand_string
)
7444 const char *kind
= "base/index";
7445 #if INFER_ADDR_PREFIX
7451 if (current_templates
->start
->opcode_modifier
.isstring
7452 && !current_templates
->start
->opcode_modifier
.immext
7453 && (current_templates
->end
[-1].opcode_modifier
.isstring
7456 /* Memory operands of string insns are special in that they only allow
7457 a single register (rDI, rSI, or rBX) as their memory address. */
7458 unsigned int expected
;
7460 kind
= "string address";
7462 if (current_templates
->start
->opcode_modifier
.w
)
7464 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7466 if (!type
.bitfield
.baseindex
7467 || ((!i
.mem_operands
!= !intel_syntax
)
7468 && current_templates
->end
[-1].operand_types
[1]
7469 .bitfield
.baseindex
))
7470 type
= current_templates
->end
[-1].operand_types
[1];
7471 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7474 expected
= 3 /* rBX */;
7476 if (!i
.base_reg
|| i
.index_reg
7477 || operand_type_check (i
.types
[this_operand
], disp
))
7479 else if (!(flag_code
== CODE_64BIT
7480 ? i
.prefix
[ADDR_PREFIX
]
7481 ? i
.base_reg
->reg_type
.bitfield
.reg32
7482 : i
.base_reg
->reg_type
.bitfield
.reg64
7483 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7484 ? i
.base_reg
->reg_type
.bitfield
.reg32
7485 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7487 else if (register_number (i
.base_reg
) != expected
)
7494 for (j
= 0; j
< i386_regtab_size
; ++j
)
7495 if ((flag_code
== CODE_64BIT
7496 ? i
.prefix
[ADDR_PREFIX
]
7497 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7498 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7499 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7500 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7501 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7502 && register_number(i386_regtab
+ j
) == expected
)
7504 gas_assert (j
< i386_regtab_size
);
7505 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7507 intel_syntax
? '[' : '(',
7509 i386_regtab
[j
].reg_name
,
7510 intel_syntax
? ']' : ')');
7514 else if (flag_code
== CODE_64BIT
)
7517 && ((i
.prefix
[ADDR_PREFIX
] == 0
7518 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7519 || (i
.prefix
[ADDR_PREFIX
]
7520 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7522 || i
.base_reg
->reg_num
!=
7523 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7525 && !(i
.index_reg
->reg_type
.bitfield
.regxmm
7526 || i
.index_reg
->reg_type
.bitfield
.regymm
)
7527 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7528 || (i
.prefix
[ADDR_PREFIX
] == 0
7529 && i
.index_reg
->reg_num
!= RegRiz
7530 && !i
.index_reg
->reg_type
.bitfield
.reg64
7532 || (i
.prefix
[ADDR_PREFIX
]
7533 && i
.index_reg
->reg_num
!= RegEiz
7534 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7539 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7543 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7544 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7546 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7547 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7549 && i
.base_reg
->reg_num
< 6
7550 && i
.index_reg
->reg_num
>= 6
7551 && i
.log2_scale_factor
== 0))))
7558 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7560 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7561 && !i
.index_reg
->reg_type
.bitfield
.regymm
7562 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7563 && i
.index_reg
->reg_num
!= RegEiz
)
7564 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7570 #if INFER_ADDR_PREFIX
7571 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7573 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7575 /* Change the size of any displacement too. At most one of
7576 Disp16 or Disp32 is set.
7577 FIXME. There doesn't seem to be any real need for separate
7578 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7579 Removing them would probably clean up the code quite a lot. */
7580 if (flag_code
!= CODE_64BIT
7581 && (i
.types
[this_operand
].bitfield
.disp16
7582 || i
.types
[this_operand
].bitfield
.disp32
))
7583 i
.types
[this_operand
]
7584 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7589 as_bad (_("`%s' is not a valid %s expression"),
7594 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7596 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7597 ? flag_code
== CODE_32BIT
7606 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7610 i386_att_operand (char *operand_string
)
7614 char *op_string
= operand_string
;
7616 if (is_space_char (*op_string
))
7619 /* We check for an absolute prefix (differentiating,
7620 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7621 if (*op_string
== ABSOLUTE_PREFIX
)
7624 if (is_space_char (*op_string
))
7626 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7629 /* Check if operand is a register. */
7630 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7632 i386_operand_type temp
;
7634 /* Check for a segment override by searching for ':' after a
7635 segment register. */
7637 if (is_space_char (*op_string
))
7639 if (*op_string
== ':'
7640 && (r
->reg_type
.bitfield
.sreg2
7641 || r
->reg_type
.bitfield
.sreg3
))
7646 i
.seg
[i
.mem_operands
] = &es
;
7649 i
.seg
[i
.mem_operands
] = &cs
;
7652 i
.seg
[i
.mem_operands
] = &ss
;
7655 i
.seg
[i
.mem_operands
] = &ds
;
7658 i
.seg
[i
.mem_operands
] = &fs
;
7661 i
.seg
[i
.mem_operands
] = &gs
;
7665 /* Skip the ':' and whitespace. */
7667 if (is_space_char (*op_string
))
7670 if (!is_digit_char (*op_string
)
7671 && !is_identifier_char (*op_string
)
7672 && *op_string
!= '('
7673 && *op_string
!= ABSOLUTE_PREFIX
)
7675 as_bad (_("bad memory operand `%s'"), op_string
);
7678 /* Handle case of %es:*foo. */
7679 if (*op_string
== ABSOLUTE_PREFIX
)
7682 if (is_space_char (*op_string
))
7684 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7686 goto do_memory_reference
;
7690 as_bad (_("junk `%s' after register"), op_string
);
7694 temp
.bitfield
.baseindex
= 0;
7695 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7697 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7698 i
.op
[this_operand
].regs
= r
;
7701 else if (*op_string
== REGISTER_PREFIX
)
7703 as_bad (_("bad register name `%s'"), op_string
);
7706 else if (*op_string
== IMMEDIATE_PREFIX
)
7709 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7711 as_bad (_("immediate operand illegal with absolute jump"));
7714 if (!i386_immediate (op_string
))
7717 else if (is_digit_char (*op_string
)
7718 || is_identifier_char (*op_string
)
7719 || *op_string
== '(')
7721 /* This is a memory reference of some sort. */
7724 /* Start and end of displacement string expression (if found). */
7725 char *displacement_string_start
;
7726 char *displacement_string_end
;
7728 do_memory_reference
:
7729 if ((i
.mem_operands
== 1
7730 && !current_templates
->start
->opcode_modifier
.isstring
)
7731 || i
.mem_operands
== 2)
7733 as_bad (_("too many memory references for `%s'"),
7734 current_templates
->start
->name
);
7738 /* Check for base index form. We detect the base index form by
7739 looking for an ')' at the end of the operand, searching
7740 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7742 base_string
= op_string
+ strlen (op_string
);
7745 if (is_space_char (*base_string
))
7748 /* If we only have a displacement, set-up for it to be parsed later. */
7749 displacement_string_start
= op_string
;
7750 displacement_string_end
= base_string
+ 1;
7752 if (*base_string
== ')')
7755 unsigned int parens_balanced
= 1;
7756 /* We've already checked that the number of left & right ()'s are
7757 equal, so this loop will not be infinite. */
7761 if (*base_string
== ')')
7763 if (*base_string
== '(')
7766 while (parens_balanced
);
7768 temp_string
= base_string
;
7770 /* Skip past '(' and whitespace. */
7772 if (is_space_char (*base_string
))
7775 if (*base_string
== ','
7776 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7779 displacement_string_end
= temp_string
;
7781 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7785 base_string
= end_op
;
7786 if (is_space_char (*base_string
))
7790 /* There may be an index reg or scale factor here. */
7791 if (*base_string
== ',')
7794 if (is_space_char (*base_string
))
7797 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7800 base_string
= end_op
;
7801 if (is_space_char (*base_string
))
7803 if (*base_string
== ',')
7806 if (is_space_char (*base_string
))
7809 else if (*base_string
!= ')')
7811 as_bad (_("expecting `,' or `)' "
7812 "after index register in `%s'"),
7817 else if (*base_string
== REGISTER_PREFIX
)
7819 end_op
= strchr (base_string
, ',');
7822 as_bad (_("bad register name `%s'"), base_string
);
7826 /* Check for scale factor. */
7827 if (*base_string
!= ')')
7829 char *end_scale
= i386_scale (base_string
);
7834 base_string
= end_scale
;
7835 if (is_space_char (*base_string
))
7837 if (*base_string
!= ')')
7839 as_bad (_("expecting `)' "
7840 "after scale factor in `%s'"),
7845 else if (!i
.index_reg
)
7847 as_bad (_("expecting index register or scale factor "
7848 "after `,'; got '%c'"),
7853 else if (*base_string
!= ')')
7855 as_bad (_("expecting `,' or `)' "
7856 "after base register in `%s'"),
7861 else if (*base_string
== REGISTER_PREFIX
)
7863 end_op
= strchr (base_string
, ',');
7866 as_bad (_("bad register name `%s'"), base_string
);
7871 /* If there's an expression beginning the operand, parse it,
7872 assuming displacement_string_start and
7873 displacement_string_end are meaningful. */
7874 if (displacement_string_start
!= displacement_string_end
)
7876 if (!i386_displacement (displacement_string_start
,
7877 displacement_string_end
))
7881 /* Special case for (%dx) while doing input/output op. */
7883 && operand_type_equal (&i
.base_reg
->reg_type
,
7884 ®16_inoutportreg
)
7886 && i
.log2_scale_factor
== 0
7887 && i
.seg
[i
.mem_operands
] == 0
7888 && !operand_type_check (i
.types
[this_operand
], disp
))
7890 i
.types
[this_operand
] = inoutportreg
;
7894 if (i386_index_check (operand_string
) == 0)
7896 i
.types
[this_operand
].bitfield
.mem
= 1;
7901 /* It's not a memory operand; argh! */
7902 as_bad (_("invalid char %s beginning operand %d `%s'"),
7903 output_invalid (*op_string
),
7908 return 1; /* Normal return. */
7911 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7912 that an rs_machine_dependent frag may reach. */
7915 i386_frag_max_var (fragS
*frag
)
7917 /* The only relaxable frags are for jumps.
7918 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7919 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7920 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7923 /* md_estimate_size_before_relax()
7925 Called just before relax() for rs_machine_dependent frags. The x86
7926 assembler uses these frags to handle variable size jump
7929 Any symbol that is now undefined will not become defined.
7930 Return the correct fr_subtype in the frag.
7931 Return the initial "guess for variable size of frag" to caller.
7932 The guess is actually the growth beyond the fixed part. Whatever
7933 we do to grow the fixed or variable part contributes to our
7937 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7939 /* We've already got fragP->fr_subtype right; all we have to do is
7940 check for un-relaxable symbols. On an ELF system, we can't relax
7941 an externally visible symbol, because it may be overridden by a
7943 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7946 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7947 || S_IS_WEAK (fragP
->fr_symbol
)
7948 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7949 & BSF_GNU_INDIRECT_FUNCTION
))))
7951 #if defined (OBJ_COFF) && defined (TE_PE)
7952 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7953 && S_IS_WEAK (fragP
->fr_symbol
))
7957 /* Symbol is undefined in this segment, or we need to keep a
7958 reloc so that weak symbols can be overridden. */
7959 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7960 enum bfd_reloc_code_real reloc_type
;
7961 unsigned char *opcode
;
7964 if (fragP
->fr_var
!= NO_RELOC
)
7965 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7967 reloc_type
= BFD_RELOC_16_PCREL
;
7969 reloc_type
= BFD_RELOC_32_PCREL
;
7971 old_fr_fix
= fragP
->fr_fix
;
7972 opcode
= (unsigned char *) fragP
->fr_opcode
;
7974 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7977 /* Make jmp (0xeb) a (d)word displacement jump. */
7979 fragP
->fr_fix
+= size
;
7980 fix_new (fragP
, old_fr_fix
, size
,
7982 fragP
->fr_offset
, 1,
7988 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7990 /* Negate the condition, and branch past an
7991 unconditional jump. */
7994 /* Insert an unconditional jump. */
7996 /* We added two extra opcode bytes, and have a two byte
7998 fragP
->fr_fix
+= 2 + 2;
7999 fix_new (fragP
, old_fr_fix
+ 2, 2,
8001 fragP
->fr_offset
, 1,
8008 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8013 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8015 fragP
->fr_offset
, 1,
8017 fixP
->fx_signed
= 1;
8021 /* This changes the byte-displacement jump 0x7N
8022 to the (d)word-displacement jump 0x0f,0x8N. */
8023 opcode
[1] = opcode
[0] + 0x10;
8024 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8025 /* We've added an opcode byte. */
8026 fragP
->fr_fix
+= 1 + size
;
8027 fix_new (fragP
, old_fr_fix
+ 1, size
,
8029 fragP
->fr_offset
, 1,
8034 BAD_CASE (fragP
->fr_subtype
);
8038 return fragP
->fr_fix
- old_fr_fix
;
8041 /* Guess size depending on current relax state. Initially the relax
8042 state will correspond to a short jump and we return 1, because
8043 the variable part of the frag (the branch offset) is one byte
8044 long. However, we can relax a section more than once and in that
8045 case we must either set fr_subtype back to the unrelaxed state,
8046 or return the value for the appropriate branch. */
8047 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8050 /* Called after relax() is finished.
8052 In: Address of frag.
8053 fr_type == rs_machine_dependent.
8054 fr_subtype is what the address relaxed to.
8056 Out: Any fixSs and constants are set up.
8057 Caller will turn frag into a ".space 0". */
8060 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8063 unsigned char *opcode
;
8064 unsigned char *where_to_put_displacement
= NULL
;
8065 offsetT target_address
;
8066 offsetT opcode_address
;
8067 unsigned int extension
= 0;
8068 offsetT displacement_from_opcode_start
;
8070 opcode
= (unsigned char *) fragP
->fr_opcode
;
8072 /* Address we want to reach in file space. */
8073 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8075 /* Address opcode resides at in file space. */
8076 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8078 /* Displacement from opcode start to fill into instruction. */
8079 displacement_from_opcode_start
= target_address
- opcode_address
;
8081 if ((fragP
->fr_subtype
& BIG
) == 0)
8083 /* Don't have to change opcode. */
8084 extension
= 1; /* 1 opcode + 1 displacement */
8085 where_to_put_displacement
= &opcode
[1];
8089 if (no_cond_jump_promotion
8090 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8091 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8092 _("long jump required"));
8094 switch (fragP
->fr_subtype
)
8096 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8097 extension
= 4; /* 1 opcode + 4 displacement */
8099 where_to_put_displacement
= &opcode
[1];
8102 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8103 extension
= 2; /* 1 opcode + 2 displacement */
8105 where_to_put_displacement
= &opcode
[1];
8108 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8109 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8110 extension
= 5; /* 2 opcode + 4 displacement */
8111 opcode
[1] = opcode
[0] + 0x10;
8112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8113 where_to_put_displacement
= &opcode
[2];
8116 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8117 extension
= 3; /* 2 opcode + 2 displacement */
8118 opcode
[1] = opcode
[0] + 0x10;
8119 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8120 where_to_put_displacement
= &opcode
[2];
8123 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8128 where_to_put_displacement
= &opcode
[3];
8132 BAD_CASE (fragP
->fr_subtype
);
8137 /* If size if less then four we are sure that the operand fits,
8138 but if it's 4, then it could be that the displacement is larger
8140 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8142 && ((addressT
) (displacement_from_opcode_start
- extension
8143 + ((addressT
) 1 << 31))
8144 > (((addressT
) 2 << 31) - 1)))
8146 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8147 _("jump target out of range"));
8148 /* Make us emit 0. */
8149 displacement_from_opcode_start
= extension
;
8151 /* Now put displacement after opcode. */
8152 md_number_to_chars ((char *) where_to_put_displacement
,
8153 (valueT
) (displacement_from_opcode_start
- extension
),
8154 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8155 fragP
->fr_fix
+= extension
;
8158 /* Apply a fixup (fixP) to segment data, once it has been determined
8159 by our caller that we have all the info we need to fix it up.
8161 Parameter valP is the pointer to the value of the bits.
8163 On the 386, immediates, displacements, and data pointers are all in
8164 the same (little-endian) format, so we don't need to care about which
8168 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8170 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8171 valueT value
= *valP
;
8173 #if !defined (TE_Mach)
8176 switch (fixP
->fx_r_type
)
8182 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8185 case BFD_RELOC_X86_64_32S
:
8186 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8189 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8192 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8197 if (fixP
->fx_addsy
!= NULL
8198 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8199 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8200 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8201 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8202 && !use_rela_relocations
)
8204 /* This is a hack. There should be a better way to handle this.
8205 This covers for the fact that bfd_install_relocation will
8206 subtract the current location (for partial_inplace, PC relative
8207 relocations); see more below. */
8211 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8214 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8219 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8222 || (symbol_section_p (fixP
->fx_addsy
)
8223 && sym_seg
!= absolute_section
))
8224 && !generic_force_reloc (fixP
))
8226 /* Yes, we add the values in twice. This is because
8227 bfd_install_relocation subtracts them out again. I think
8228 bfd_install_relocation is broken, but I don't dare change
8230 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8234 #if defined (OBJ_COFF) && defined (TE_PE)
8235 /* For some reason, the PE format does not store a
8236 section address offset for a PC relative symbol. */
8237 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8238 || S_IS_WEAK (fixP
->fx_addsy
))
8239 value
+= md_pcrel_from (fixP
);
8242 #if defined (OBJ_COFF) && defined (TE_PE)
8243 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8245 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8249 /* Fix a few things - the dynamic linker expects certain values here,
8250 and we must not disappoint it. */
8251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8252 if (IS_ELF
&& fixP
->fx_addsy
)
8253 switch (fixP
->fx_r_type
)
8255 case BFD_RELOC_386_PLT32
:
8256 case BFD_RELOC_X86_64_PLT32
:
8257 /* Make the jump instruction point to the address of the operand. At
8258 runtime we merely add the offset to the actual PLT entry. */
8262 case BFD_RELOC_386_TLS_GD
:
8263 case BFD_RELOC_386_TLS_LDM
:
8264 case BFD_RELOC_386_TLS_IE_32
:
8265 case BFD_RELOC_386_TLS_IE
:
8266 case BFD_RELOC_386_TLS_GOTIE
:
8267 case BFD_RELOC_386_TLS_GOTDESC
:
8268 case BFD_RELOC_X86_64_TLSGD
:
8269 case BFD_RELOC_X86_64_TLSLD
:
8270 case BFD_RELOC_X86_64_GOTTPOFF
:
8271 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8272 value
= 0; /* Fully resolved at runtime. No addend. */
8274 case BFD_RELOC_386_TLS_LE
:
8275 case BFD_RELOC_386_TLS_LDO_32
:
8276 case BFD_RELOC_386_TLS_LE_32
:
8277 case BFD_RELOC_X86_64_DTPOFF32
:
8278 case BFD_RELOC_X86_64_DTPOFF64
:
8279 case BFD_RELOC_X86_64_TPOFF32
:
8280 case BFD_RELOC_X86_64_TPOFF64
:
8281 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8284 case BFD_RELOC_386_TLS_DESC_CALL
:
8285 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8286 value
= 0; /* Fully resolved at runtime. No addend. */
8287 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8291 case BFD_RELOC_386_GOT32
:
8292 case BFD_RELOC_X86_64_GOT32
:
8293 value
= 0; /* Fully resolved at runtime. No addend. */
8296 case BFD_RELOC_VTABLE_INHERIT
:
8297 case BFD_RELOC_VTABLE_ENTRY
:
8304 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8306 #endif /* !defined (TE_Mach) */
8308 /* Are we finished with this relocation now? */
8309 if (fixP
->fx_addsy
== NULL
)
8311 #if defined (OBJ_COFF) && defined (TE_PE)
8312 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8315 /* Remember value for tc_gen_reloc. */
8316 fixP
->fx_addnumber
= value
;
8317 /* Clear out the frag for now. */
8321 else if (use_rela_relocations
)
8323 fixP
->fx_no_overflow
= 1;
8324 /* Remember value for tc_gen_reloc. */
8325 fixP
->fx_addnumber
= value
;
8329 md_number_to_chars (p
, value
, fixP
->fx_size
);
8333 md_atof (int type
, char *litP
, int *sizeP
)
8335 /* This outputs the LITTLENUMs in REVERSE order;
8336 in accord with the bigendian 386. */
8337 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8340 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8343 output_invalid (int c
)
8346 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8349 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8350 "(0x%x)", (unsigned char) c
);
8351 return output_invalid_buf
;
8354 /* REG_STRING starts *before* REGISTER_PREFIX. */
8356 static const reg_entry
*
8357 parse_real_register (char *reg_string
, char **end_op
)
8359 char *s
= reg_string
;
8361 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8364 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8365 if (*s
== REGISTER_PREFIX
)
8368 if (is_space_char (*s
))
8372 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8374 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8375 return (const reg_entry
*) NULL
;
8379 /* For naked regs, make sure that we are not dealing with an identifier.
8380 This prevents confusing an identifier like `eax_var' with register
8382 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8383 return (const reg_entry
*) NULL
;
8387 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8389 /* Handle floating point regs, allowing spaces in the (i) part. */
8390 if (r
== i386_regtab
/* %st is first entry of table */)
8392 if (is_space_char (*s
))
8397 if (is_space_char (*s
))
8399 if (*s
>= '0' && *s
<= '7')
8403 if (is_space_char (*s
))
8408 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8413 /* We have "%st(" then garbage. */
8414 return (const reg_entry
*) NULL
;
8418 if (r
== NULL
|| allow_pseudo_reg
)
8421 if (operand_type_all_zero (&r
->reg_type
))
8422 return (const reg_entry
*) NULL
;
8424 if ((r
->reg_type
.bitfield
.reg32
8425 || r
->reg_type
.bitfield
.sreg3
8426 || r
->reg_type
.bitfield
.control
8427 || r
->reg_type
.bitfield
.debug
8428 || r
->reg_type
.bitfield
.test
)
8429 && !cpu_arch_flags
.bitfield
.cpui386
)
8430 return (const reg_entry
*) NULL
;
8432 if (r
->reg_type
.bitfield
.floatreg
8433 && !cpu_arch_flags
.bitfield
.cpu8087
8434 && !cpu_arch_flags
.bitfield
.cpu287
8435 && !cpu_arch_flags
.bitfield
.cpu387
)
8436 return (const reg_entry
*) NULL
;
8438 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8439 return (const reg_entry
*) NULL
;
8441 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8442 return (const reg_entry
*) NULL
;
8444 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8445 return (const reg_entry
*) NULL
;
8447 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8448 if (!allow_index_reg
8449 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8450 return (const reg_entry
*) NULL
;
8452 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8453 || r
->reg_type
.bitfield
.reg64
)
8454 && (!cpu_arch_flags
.bitfield
.cpulm
8455 || !operand_type_equal (&r
->reg_type
, &control
))
8456 && flag_code
!= CODE_64BIT
)
8457 return (const reg_entry
*) NULL
;
8459 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8460 return (const reg_entry
*) NULL
;
8465 /* REG_STRING starts *before* REGISTER_PREFIX. */
8467 static const reg_entry
*
8468 parse_register (char *reg_string
, char **end_op
)
8472 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8473 r
= parse_real_register (reg_string
, end_op
);
8478 char *save
= input_line_pointer
;
8482 input_line_pointer
= reg_string
;
8483 c
= get_symbol_end ();
8484 symbolP
= symbol_find (reg_string
);
8485 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8487 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8489 know (e
->X_op
== O_register
);
8490 know (e
->X_add_number
>= 0
8491 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8492 r
= i386_regtab
+ e
->X_add_number
;
8493 *end_op
= input_line_pointer
;
8495 *input_line_pointer
= c
;
8496 input_line_pointer
= save
;
8502 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8505 char *end
= input_line_pointer
;
8508 r
= parse_register (name
, &input_line_pointer
);
8509 if (r
&& end
<= input_line_pointer
)
8511 *nextcharP
= *input_line_pointer
;
8512 *input_line_pointer
= 0;
8513 e
->X_op
= O_register
;
8514 e
->X_add_number
= r
- i386_regtab
;
8517 input_line_pointer
= end
;
8519 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8523 md_operand (expressionS
*e
)
8528 switch (*input_line_pointer
)
8530 case REGISTER_PREFIX
:
8531 r
= parse_real_register (input_line_pointer
, &end
);
8534 e
->X_op
= O_register
;
8535 e
->X_add_number
= r
- i386_regtab
;
8536 input_line_pointer
= end
;
8541 gas_assert (intel_syntax
);
8542 end
= input_line_pointer
++;
8544 if (*input_line_pointer
== ']')
8546 ++input_line_pointer
;
8547 e
->X_op_symbol
= make_expr_symbol (e
);
8548 e
->X_add_symbol
= NULL
;
8549 e
->X_add_number
= 0;
8555 input_line_pointer
= end
;
8562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8563 const char *md_shortopts
= "kVQ:sqn";
8565 const char *md_shortopts
= "qn";
8568 #define OPTION_32 (OPTION_MD_BASE + 0)
8569 #define OPTION_64 (OPTION_MD_BASE + 1)
8570 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8571 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8572 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8573 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8574 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8575 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8576 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8577 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8578 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8579 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8580 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8581 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8582 #define OPTION_X32 (OPTION_MD_BASE + 14)
8584 struct option md_longopts
[] =
8586 {"32", no_argument
, NULL
, OPTION_32
},
8587 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8588 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8589 {"64", no_argument
, NULL
, OPTION_64
},
8591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8592 {"x32", no_argument
, NULL
, OPTION_X32
},
8594 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8595 {"march", required_argument
, NULL
, OPTION_MARCH
},
8596 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8597 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8598 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8599 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8600 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8601 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8602 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8603 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8604 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8605 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8606 {NULL
, no_argument
, NULL
, 0}
8608 size_t md_longopts_size
= sizeof (md_longopts
);
8611 md_parse_option (int c
, char *arg
)
8619 optimize_align_code
= 0;
8626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8627 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8628 should be emitted or not. FIXME: Not implemented. */
8632 /* -V: SVR4 argument to print version ID. */
8634 print_version_id ();
8637 /* -k: Ignore for FreeBSD compatibility. */
8642 /* -s: On i386 Solaris, this tells the native assembler to use
8643 .stab instead of .stab.excl. We always use .stab anyhow. */
8646 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8647 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8650 const char **list
, **l
;
8652 list
= bfd_target_list ();
8653 for (l
= list
; *l
!= NULL
; l
++)
8654 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8655 || strcmp (*l
, "coff-x86-64") == 0
8656 || strcmp (*l
, "pe-x86-64") == 0
8657 || strcmp (*l
, "pei-x86-64") == 0
8658 || strcmp (*l
, "mach-o-x86-64") == 0)
8660 default_arch
= "x86_64";
8664 as_fatal (_("no compiled in support for x86_64"));
8670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8674 const char **list
, **l
;
8676 list
= bfd_target_list ();
8677 for (l
= list
; *l
!= NULL
; l
++)
8678 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8680 default_arch
= "x86_64:32";
8684 as_fatal (_("no compiled in support for 32bit x86_64"));
8688 as_fatal (_("32bit x86_64 is only supported for ELF"));
8693 default_arch
= "i386";
8697 #ifdef SVR4_COMMENT_CHARS
8702 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8704 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8708 i386_comment_chars
= n
;
8714 arch
= xstrdup (arg
);
8718 as_fatal (_("invalid -march= option: `%s'"), arg
);
8719 next
= strchr (arch
, '+');
8722 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8724 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8727 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8730 cpu_arch_name
= cpu_arch
[j
].name
;
8731 cpu_sub_arch_name
= NULL
;
8732 cpu_arch_flags
= cpu_arch
[j
].flags
;
8733 cpu_arch_isa
= cpu_arch
[j
].type
;
8734 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8735 if (!cpu_arch_tune_set
)
8737 cpu_arch_tune
= cpu_arch_isa
;
8738 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8742 else if (*cpu_arch
[j
].name
== '.'
8743 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8745 /* ISA entension. */
8746 i386_cpu_flags flags
;
8748 if (!cpu_arch
[j
].negated
)
8749 flags
= cpu_flags_or (cpu_arch_flags
,
8752 flags
= cpu_flags_and_not (cpu_arch_flags
,
8754 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8756 if (cpu_sub_arch_name
)
8758 char *name
= cpu_sub_arch_name
;
8759 cpu_sub_arch_name
= concat (name
,
8761 (const char *) NULL
);
8765 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8766 cpu_arch_flags
= flags
;
8767 cpu_arch_isa_flags
= flags
;
8773 if (j
>= ARRAY_SIZE (cpu_arch
))
8774 as_fatal (_("invalid -march= option: `%s'"), arg
);
8778 while (next
!= NULL
);
8783 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8784 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8786 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8788 cpu_arch_tune_set
= 1;
8789 cpu_arch_tune
= cpu_arch
[j
].type
;
8790 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8794 if (j
>= ARRAY_SIZE (cpu_arch
))
8795 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8798 case OPTION_MMNEMONIC
:
8799 if (strcasecmp (arg
, "att") == 0)
8801 else if (strcasecmp (arg
, "intel") == 0)
8804 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8807 case OPTION_MSYNTAX
:
8808 if (strcasecmp (arg
, "att") == 0)
8810 else if (strcasecmp (arg
, "intel") == 0)
8813 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8816 case OPTION_MINDEX_REG
:
8817 allow_index_reg
= 1;
8820 case OPTION_MNAKED_REG
:
8821 allow_naked_reg
= 1;
8824 case OPTION_MOLD_GCC
:
8828 case OPTION_MSSE2AVX
:
8832 case OPTION_MSSE_CHECK
:
8833 if (strcasecmp (arg
, "error") == 0)
8834 sse_check
= check_error
;
8835 else if (strcasecmp (arg
, "warning") == 0)
8836 sse_check
= check_warning
;
8837 else if (strcasecmp (arg
, "none") == 0)
8838 sse_check
= check_none
;
8840 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8843 case OPTION_MOPERAND_CHECK
:
8844 if (strcasecmp (arg
, "error") == 0)
8845 operand_check
= check_error
;
8846 else if (strcasecmp (arg
, "warning") == 0)
8847 operand_check
= check_warning
;
8848 else if (strcasecmp (arg
, "none") == 0)
8849 operand_check
= check_none
;
8851 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8854 case OPTION_MAVXSCALAR
:
8855 if (strcasecmp (arg
, "128") == 0)
8857 else if (strcasecmp (arg
, "256") == 0)
8860 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8869 #define MESSAGE_TEMPLATE \
8873 show_arch (FILE *stream
, int ext
, int check
)
8875 static char message
[] = MESSAGE_TEMPLATE
;
8876 char *start
= message
+ 27;
8878 int size
= sizeof (MESSAGE_TEMPLATE
);
8885 left
= size
- (start
- message
);
8886 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8888 /* Should it be skipped? */
8889 if (cpu_arch
[j
].skip
)
8892 name
= cpu_arch
[j
].name
;
8893 len
= cpu_arch
[j
].len
;
8896 /* It is an extension. Skip if we aren't asked to show it. */
8907 /* It is an processor. Skip if we show only extension. */
8910 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8912 /* It is an impossible processor - skip. */
8916 /* Reserve 2 spaces for ", " or ",\0" */
8919 /* Check if there is any room. */
8927 p
= mempcpy (p
, name
, len
);
8931 /* Output the current message now and start a new one. */
8934 fprintf (stream
, "%s\n", message
);
8936 left
= size
- (start
- message
) - len
- 2;
8938 gas_assert (left
>= 0);
8940 p
= mempcpy (p
, name
, len
);
8945 fprintf (stream
, "%s\n", message
);
8949 md_show_usage (FILE *stream
)
8951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8952 fprintf (stream
, _("\
8954 -V print assembler version number\n\
8957 fprintf (stream
, _("\
8958 -n Do not optimize code alignment\n\
8959 -q quieten some warnings\n"));
8960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8961 fprintf (stream
, _("\
8964 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8965 || defined (TE_PE) || defined (TE_PEP))
8966 fprintf (stream
, _("\
8967 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8969 #ifdef SVR4_COMMENT_CHARS
8970 fprintf (stream
, _("\
8971 --divide do not treat `/' as a comment character\n"));
8973 fprintf (stream
, _("\
8974 --divide ignored\n"));
8976 fprintf (stream
, _("\
8977 -march=CPU[,+EXTENSION...]\n\
8978 generate code for CPU and EXTENSION, CPU is one of:\n"));
8979 show_arch (stream
, 0, 1);
8980 fprintf (stream
, _("\
8981 EXTENSION is combination of:\n"));
8982 show_arch (stream
, 1, 0);
8983 fprintf (stream
, _("\
8984 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8985 show_arch (stream
, 0, 0);
8986 fprintf (stream
, _("\
8987 -msse2avx encode SSE instructions with VEX prefix\n"));
8988 fprintf (stream
, _("\
8989 -msse-check=[none|error|warning]\n\
8990 check SSE instructions\n"));
8991 fprintf (stream
, _("\
8992 -moperand-check=[none|error|warning]\n\
8993 check operand combinations for validity\n"));
8994 fprintf (stream
, _("\
8995 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8997 fprintf (stream
, _("\
8998 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8999 fprintf (stream
, _("\
9000 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9001 fprintf (stream
, _("\
9002 -mindex-reg support pseudo index registers\n"));
9003 fprintf (stream
, _("\
9004 -mnaked-reg don't require `%%' prefix for registers\n"));
9005 fprintf (stream
, _("\
9006 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9009 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9010 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9011 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9013 /* Pick the target format to use. */
9016 i386_target_format (void)
9018 if (!strncmp (default_arch
, "x86_64", 6))
9020 update_code_flag (CODE_64BIT
, 1);
9021 if (default_arch
[6] == '\0')
9022 x86_elf_abi
= X86_64_ABI
;
9024 x86_elf_abi
= X86_64_X32_ABI
;
9026 else if (!strcmp (default_arch
, "i386"))
9027 update_code_flag (CODE_32BIT
, 1);
9029 as_fatal (_("unknown architecture"));
9031 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9032 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9033 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9034 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9036 switch (OUTPUT_FLAVOR
)
9038 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9039 case bfd_target_aout_flavour
:
9040 return AOUT_TARGET_FORMAT
;
9042 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9043 # if defined (TE_PE) || defined (TE_PEP)
9044 case bfd_target_coff_flavour
:
9045 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9046 # elif defined (TE_GO32)
9047 case bfd_target_coff_flavour
:
9050 case bfd_target_coff_flavour
:
9054 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9055 case bfd_target_elf_flavour
:
9059 switch (x86_elf_abi
)
9062 format
= ELF_TARGET_FORMAT
;
9065 use_rela_relocations
= 1;
9067 format
= ELF_TARGET_FORMAT64
;
9069 case X86_64_X32_ABI
:
9070 use_rela_relocations
= 1;
9072 disallow_64bit_reloc
= 1;
9073 format
= ELF_TARGET_FORMAT32
;
9076 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9078 if (x86_elf_abi
!= X86_64_ABI
)
9079 as_fatal (_("Intel L1OM is 64bit only"));
9080 return ELF_TARGET_L1OM_FORMAT
;
9082 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9084 if (x86_elf_abi
!= X86_64_ABI
)
9085 as_fatal (_("Intel K1OM is 64bit only"));
9086 return ELF_TARGET_K1OM_FORMAT
;
9092 #if defined (OBJ_MACH_O)
9093 case bfd_target_mach_o_flavour
:
9094 if (flag_code
== CODE_64BIT
)
9096 use_rela_relocations
= 1;
9098 return "mach-o-x86-64";
9101 return "mach-o-i386";
9109 #endif /* OBJ_MAYBE_ more than one */
9111 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9113 i386_elf_emit_arch_note (void)
9115 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9118 asection
*seg
= now_seg
;
9119 subsegT subseg
= now_subseg
;
9120 Elf_Internal_Note i_note
;
9121 Elf_External_Note e_note
;
9122 asection
*note_secp
;
9125 /* Create the .note section. */
9126 note_secp
= subseg_new (".note", 0);
9127 bfd_set_section_flags (stdoutput
,
9129 SEC_HAS_CONTENTS
| SEC_READONLY
);
9131 /* Process the arch string. */
9132 len
= strlen (cpu_arch_name
);
9134 i_note
.namesz
= len
+ 1;
9136 i_note
.type
= NT_ARCH
;
9137 p
= frag_more (sizeof (e_note
.namesz
));
9138 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9139 p
= frag_more (sizeof (e_note
.descsz
));
9140 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9141 p
= frag_more (sizeof (e_note
.type
));
9142 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9143 p
= frag_more (len
+ 1);
9144 strcpy (p
, cpu_arch_name
);
9146 frag_align (2, 0, 0);
9148 subseg_set (seg
, subseg
);
9154 md_undefined_symbol (char *name
)
9156 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9157 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9158 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9159 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9163 if (symbol_find (name
))
9164 as_bad (_("GOT already in symbol table"));
9165 GOT_symbol
= symbol_new (name
, undefined_section
,
9166 (valueT
) 0, &zero_address_frag
);
9173 /* Round up a section size to the appropriate boundary. */
9176 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9178 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9179 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9181 /* For a.out, force the section size to be aligned. If we don't do
9182 this, BFD will align it for us, but it will not write out the
9183 final bytes of the section. This may be a bug in BFD, but it is
9184 easier to fix it here since that is how the other a.out targets
9188 align
= bfd_get_section_alignment (stdoutput
, segment
);
9189 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9196 /* On the i386, PC-relative offsets are relative to the start of the
9197 next instruction. That is, the address of the offset, plus its
9198 size, since the offset is always the last part of the insn. */
9201 md_pcrel_from (fixS
*fixP
)
9203 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9209 s_bss (int ignore ATTRIBUTE_UNUSED
)
9213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9215 obj_elf_section_change_hook ();
9217 temp
= get_absolute_expression ();
9218 subseg_set (bss_section
, (subsegT
) temp
);
9219 demand_empty_rest_of_line ();
9225 i386_validate_fix (fixS
*fixp
)
9227 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9229 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9233 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9238 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9240 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9247 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9250 bfd_reloc_code_real_type code
;
9252 switch (fixp
->fx_r_type
)
9254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9255 case BFD_RELOC_SIZE32
:
9256 case BFD_RELOC_SIZE64
:
9257 if (S_IS_DEFINED (fixp
->fx_addsy
)
9258 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9260 /* Resolve size relocation against local symbol to size of
9261 the symbol plus addend. */
9262 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9263 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9264 && !fits_in_unsigned_long (value
))
9265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9266 _("symbol size computation overflow"));
9267 fixp
->fx_addsy
= NULL
;
9268 fixp
->fx_subsy
= NULL
;
9269 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9274 case BFD_RELOC_X86_64_PLT32
:
9275 case BFD_RELOC_X86_64_GOT32
:
9276 case BFD_RELOC_X86_64_GOTPCREL
:
9277 case BFD_RELOC_386_PLT32
:
9278 case BFD_RELOC_386_GOT32
:
9279 case BFD_RELOC_386_GOTOFF
:
9280 case BFD_RELOC_386_GOTPC
:
9281 case BFD_RELOC_386_TLS_GD
:
9282 case BFD_RELOC_386_TLS_LDM
:
9283 case BFD_RELOC_386_TLS_LDO_32
:
9284 case BFD_RELOC_386_TLS_IE_32
:
9285 case BFD_RELOC_386_TLS_IE
:
9286 case BFD_RELOC_386_TLS_GOTIE
:
9287 case BFD_RELOC_386_TLS_LE_32
:
9288 case BFD_RELOC_386_TLS_LE
:
9289 case BFD_RELOC_386_TLS_GOTDESC
:
9290 case BFD_RELOC_386_TLS_DESC_CALL
:
9291 case BFD_RELOC_X86_64_TLSGD
:
9292 case BFD_RELOC_X86_64_TLSLD
:
9293 case BFD_RELOC_X86_64_DTPOFF32
:
9294 case BFD_RELOC_X86_64_DTPOFF64
:
9295 case BFD_RELOC_X86_64_GOTTPOFF
:
9296 case BFD_RELOC_X86_64_TPOFF32
:
9297 case BFD_RELOC_X86_64_TPOFF64
:
9298 case BFD_RELOC_X86_64_GOTOFF64
:
9299 case BFD_RELOC_X86_64_GOTPC32
:
9300 case BFD_RELOC_X86_64_GOT64
:
9301 case BFD_RELOC_X86_64_GOTPCREL64
:
9302 case BFD_RELOC_X86_64_GOTPC64
:
9303 case BFD_RELOC_X86_64_GOTPLT64
:
9304 case BFD_RELOC_X86_64_PLTOFF64
:
9305 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9306 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9308 case BFD_RELOC_VTABLE_ENTRY
:
9309 case BFD_RELOC_VTABLE_INHERIT
:
9311 case BFD_RELOC_32_SECREL
:
9313 code
= fixp
->fx_r_type
;
9315 case BFD_RELOC_X86_64_32S
:
9316 if (!fixp
->fx_pcrel
)
9318 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9319 code
= fixp
->fx_r_type
;
9325 switch (fixp
->fx_size
)
9328 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9329 _("can not do %d byte pc-relative relocation"),
9331 code
= BFD_RELOC_32_PCREL
;
9333 case 1: code
= BFD_RELOC_8_PCREL
; break;
9334 case 2: code
= BFD_RELOC_16_PCREL
; break;
9335 case 4: code
= BFD_RELOC_32_PCREL
; break;
9337 case 8: code
= BFD_RELOC_64_PCREL
; break;
9343 switch (fixp
->fx_size
)
9346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9347 _("can not do %d byte relocation"),
9349 code
= BFD_RELOC_32
;
9351 case 1: code
= BFD_RELOC_8
; break;
9352 case 2: code
= BFD_RELOC_16
; break;
9353 case 4: code
= BFD_RELOC_32
; break;
9355 case 8: code
= BFD_RELOC_64
; break;
9362 if ((code
== BFD_RELOC_32
9363 || code
== BFD_RELOC_32_PCREL
9364 || code
== BFD_RELOC_X86_64_32S
)
9366 && fixp
->fx_addsy
== GOT_symbol
)
9369 code
= BFD_RELOC_386_GOTPC
;
9371 code
= BFD_RELOC_X86_64_GOTPC32
;
9373 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9375 && fixp
->fx_addsy
== GOT_symbol
)
9377 code
= BFD_RELOC_X86_64_GOTPC64
;
9380 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9381 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9382 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9384 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9386 if (!use_rela_relocations
)
9388 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9389 vtable entry to be used in the relocation's section offset. */
9390 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9391 rel
->address
= fixp
->fx_offset
;
9392 #if defined (OBJ_COFF) && defined (TE_PE)
9393 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9394 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9399 /* Use the rela in 64bit mode. */
9402 if (disallow_64bit_reloc
)
9405 case BFD_RELOC_X86_64_DTPOFF64
:
9406 case BFD_RELOC_X86_64_TPOFF64
:
9407 case BFD_RELOC_64_PCREL
:
9408 case BFD_RELOC_X86_64_GOTOFF64
:
9409 case BFD_RELOC_X86_64_GOT64
:
9410 case BFD_RELOC_X86_64_GOTPCREL64
:
9411 case BFD_RELOC_X86_64_GOTPC64
:
9412 case BFD_RELOC_X86_64_GOTPLT64
:
9413 case BFD_RELOC_X86_64_PLTOFF64
:
9414 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9415 _("cannot represent relocation type %s in x32 mode"),
9416 bfd_get_reloc_code_name (code
));
9422 if (!fixp
->fx_pcrel
)
9423 rel
->addend
= fixp
->fx_offset
;
9427 case BFD_RELOC_X86_64_PLT32
:
9428 case BFD_RELOC_X86_64_GOT32
:
9429 case BFD_RELOC_X86_64_GOTPCREL
:
9430 case BFD_RELOC_X86_64_TLSGD
:
9431 case BFD_RELOC_X86_64_TLSLD
:
9432 case BFD_RELOC_X86_64_GOTTPOFF
:
9433 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9434 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9435 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9438 rel
->addend
= (section
->vma
9440 + fixp
->fx_addnumber
9441 + md_pcrel_from (fixp
));
9446 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9447 if (rel
->howto
== NULL
)
9449 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9450 _("cannot represent relocation type %s"),
9451 bfd_get_reloc_code_name (code
));
9452 /* Set howto to a garbage value so that we can keep going. */
9453 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9454 gas_assert (rel
->howto
!= NULL
);
9460 #include "tc-i386-intel.c"
9463 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9465 int saved_naked_reg
;
9466 char saved_register_dot
;
9468 saved_naked_reg
= allow_naked_reg
;
9469 allow_naked_reg
= 1;
9470 saved_register_dot
= register_chars
['.'];
9471 register_chars
['.'] = '.';
9472 allow_pseudo_reg
= 1;
9473 expression_and_evaluate (exp
);
9474 allow_pseudo_reg
= 0;
9475 register_chars
['.'] = saved_register_dot
;
9476 allow_naked_reg
= saved_naked_reg
;
9478 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9480 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9482 exp
->X_op
= O_constant
;
9483 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9484 .dw2_regnum
[flag_code
>> 1];
9487 exp
->X_op
= O_illegal
;
9492 tc_x86_frame_initial_instructions (void)
9494 static unsigned int sp_regno
[2];
9496 if (!sp_regno
[flag_code
>> 1])
9498 char *saved_input
= input_line_pointer
;
9499 char sp
[][4] = {"esp", "rsp"};
9502 input_line_pointer
= sp
[flag_code
>> 1];
9503 tc_x86_parse_to_dw2regnum (&exp
);
9504 gas_assert (exp
.X_op
== O_constant
);
9505 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9506 input_line_pointer
= saved_input
;
9509 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9510 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9514 x86_dwarf2_addr_size (void)
9516 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9517 if (x86_elf_abi
== X86_64_X32_ABI
)
9520 return bfd_arch_bits_per_address (stdoutput
) / 8;
9524 i386_elf_section_type (const char *str
, size_t len
)
9526 if (flag_code
== CODE_64BIT
9527 && len
== sizeof ("unwind") - 1
9528 && strncmp (str
, "unwind", 6) == 0)
9529 return SHT_X86_64_UNWIND
;
9536 i386_solaris_fix_up_eh_frame (segT sec
)
9538 if (flag_code
== CODE_64BIT
)
9539 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9545 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9549 exp
.X_op
= O_secrel
;
9550 exp
.X_add_symbol
= symbol
;
9551 exp
.X_add_number
= 0;
9552 emit_expr (&exp
, size
);
9556 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9557 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9560 x86_64_section_letter (int letter
, char **ptr_msg
)
9562 if (flag_code
== CODE_64BIT
)
9565 return SHF_X86_64_LARGE
;
9567 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9570 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9575 x86_64_section_word (char *str
, size_t len
)
9577 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9578 return SHF_X86_64_LARGE
;
9584 handle_large_common (int small ATTRIBUTE_UNUSED
)
9586 if (flag_code
!= CODE_64BIT
)
9588 s_comm_internal (0, elf_common_parse
);
9589 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9593 static segT lbss_section
;
9594 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9595 asection
*saved_bss_section
= bss_section
;
9597 if (lbss_section
== NULL
)
9599 flagword applicable
;
9601 subsegT subseg
= now_subseg
;
9603 /* The .lbss section is for local .largecomm symbols. */
9604 lbss_section
= subseg_new (".lbss", 0);
9605 applicable
= bfd_applicable_section_flags (stdoutput
);
9606 bfd_set_section_flags (stdoutput
, lbss_section
,
9607 applicable
& SEC_ALLOC
);
9608 seg_info (lbss_section
)->bss
= 1;
9610 subseg_set (seg
, subseg
);
9613 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9614 bss_section
= lbss_section
;
9616 s_comm_internal (0, elf_common_parse
);
9618 elf_com_section_ptr
= saved_com_section_ptr
;
9619 bss_section
= saved_bss_section
;
9622 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */