1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "opcode/i386.h"
33 #ifndef REGISTER_WARNINGS
34 #define REGISTER_WARNINGS 1
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
41 #ifndef SCALE1_WHEN_NO_INDEX
42 /* Specifying a scale factor besides 1 when there is no index is
43 futile. eg. `mov (%ebx,2),%al' does exactly the same as
44 `mov (%ebx),%al'. To slavishly follow what the programmer
45 specified, set SCALE1_WHEN_NO_INDEX to 0. */
46 #define SCALE1_WHEN_NO_INDEX 1
52 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
53 static int fits_in_signed_byte
PARAMS ((offsetT
));
54 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_word
PARAMS ((offsetT
));
56 static int fits_in_signed_word
PARAMS ((offsetT
));
57 static int smallest_imm_type
PARAMS ((offsetT
));
58 static offsetT offset_in_range
PARAMS ((offsetT
, int));
59 static int add_prefix
PARAMS ((unsigned int));
60 static void set_16bit_code_flag
PARAMS ((int));
61 static void set_16bit_gcc_code_flag
PARAMS ((int));
62 static void set_intel_syntax
PARAMS ((int));
63 static void set_cpu_arch
PARAMS ((int));
66 static bfd_reloc_code_real_type reloc
67 PARAMS ((int, int, bfd_reloc_code_real_type
));
70 /* 'md_assemble ()' gathers together information and puts it into a
77 const reg_entry
*regs
;
82 /* TM holds the template for the insn were currently assembling. */
85 /* SUFFIX holds the instruction mnemonic suffix if given.
86 (e.g. 'l' for 'movl') */
89 /* OPERANDS gives the number of given operands. */
90 unsigned int operands
;
92 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
93 of given register, displacement, memory operands and immediate
95 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
97 /* TYPES [i] is the type (see above #defines) which tells us how to
98 use OP[i] for the corresponding operand. */
99 unsigned int types
[MAX_OPERANDS
];
101 /* Displacement expression, immediate expression, or register for each
103 union i386_op op
[MAX_OPERANDS
];
105 /* Relocation type for operand */
107 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
109 int disp_reloc
[MAX_OPERANDS
];
112 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
113 the base index byte below. */
114 const reg_entry
*base_reg
;
115 const reg_entry
*index_reg
;
116 unsigned int log2_scale_factor
;
118 /* SEG gives the seg_entries of this insn. They are zero unless
119 explicit segment overrides are given. */
120 const seg_entry
*seg
[2];
122 /* PREFIX holds all the given prefix opcodes (usually null).
123 PREFIXES is the number of prefix opcodes. */
124 unsigned int prefixes
;
125 unsigned char prefix
[MAX_PREFIXES
];
127 /* RM and SIB are the modrm byte and the sib byte where the
128 addressing modes of this insn are encoded. */
134 typedef struct _i386_insn i386_insn
;
136 /* List of chars besides those in app.c:symbol_chars that can start an
137 operand. Used to prevent the scrubber eating vital white-space. */
139 const char extra_symbol_chars
[] = "*%-(@";
141 const char extra_symbol_chars
[] = "*%-(";
144 /* This array holds the chars that always start a comment. If the
145 pre-processor is disabled, these aren't very useful. */
146 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
147 /* Putting '/' here makes it impossible to use the divide operator.
148 However, we need it for compatibility with SVR4 systems. */
149 const char comment_chars
[] = "#/";
150 #define PREFIX_SEPARATOR '\\'
152 const char comment_chars
[] = "#";
153 #define PREFIX_SEPARATOR '/'
156 /* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output.
159 Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output.
162 Also note that comments started like this one will always work if
163 '/' isn't otherwise defined. */
164 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165 const char line_comment_chars
[] = "";
167 const char line_comment_chars
[] = "/";
170 const char line_separator_chars
[] = ";";
172 /* Chars that can be used to separate mant from exp in floating point
174 const char EXP_CHARS
[] = "eE";
176 /* Chars that mean this number is a floating point constant
179 const char FLT_CHARS
[] = "fFdDxX";
181 /* Tables for lexical analysis. */
182 static char mnemonic_chars
[256];
183 static char register_chars
[256];
184 static char operand_chars
[256];
185 static char identifier_chars
[256];
186 static char digit_chars
[256];
188 /* Lexical macros. */
189 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
190 #define is_operand_char(x) (operand_chars[(unsigned char) x])
191 #define is_register_char(x) (register_chars[(unsigned char) x])
192 #define is_space_char(x) ((x) == ' ')
193 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
194 #define is_digit_char(x) (digit_chars[(unsigned char) x])
196 /* All non-digit non-letter charcters that may occur in an operand. */
197 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
199 /* md_assemble() always leaves the strings it's passed unaltered. To
200 effect this we maintain a stack of saved characters that we've smashed
201 with '\0's (indicating end of strings for various sub-fields of the
202 assembler instruction). */
203 static char save_stack
[32];
204 static char *save_stack_p
;
205 #define END_STRING_AND_SAVE(s) \
206 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
207 #define RESTORE_END_STRING(s) \
208 do { *(s) = *--save_stack_p; } while (0)
210 /* The instruction we're assembling. */
213 /* Possible templates for current insn. */
214 static const templates
*current_templates
;
216 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
217 static expressionS disp_expressions
[2], im_expressions
[2];
219 /* Current operand we are working on. */
220 static int this_operand
;
222 /* 1 if we're writing 16-bit code,
224 static int flag_16bit_code
;
226 /* 1 for intel syntax,
228 static int intel_syntax
= 0;
230 /* 1 if register prefix % not required. */
231 static int allow_naked_reg
= 0;
233 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
234 leave, push, and pop instructions so that gcc has the same stack
235 frame as in 32 bit mode. */
236 static char stackop_size
= '\0';
238 /* Non-zero to quieten some warnings. */
239 static int quiet_warnings
= 0;
242 static const char *cpu_arch_name
= NULL
;
244 /* CPU feature flags. */
245 static unsigned int cpu_arch_flags
= 0;
247 /* Interface to relax_segment.
248 There are 2 relax states for 386 jump insns: one for conditional &
249 one for unconditional jumps. This is because these two types of
250 jumps add different sizes to frags when we're figuring out what
251 sort of jump to choose to reach a given label. */
255 #define UNCOND_JUMP 2
259 #define SMALL16 (SMALL|CODE16)
261 #define BIG16 (BIG|CODE16)
265 #define INLINE __inline__
271 #define ENCODE_RELAX_STATE(type,size) \
272 ((relax_substateT)((type<<2) | (size)))
273 #define SIZE_FROM_RELAX_STATE(s) \
274 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
276 /* This table is used by relax_frag to promote short jumps to long
277 ones where necessary. SMALL (short) jumps may be promoted to BIG
278 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
279 don't allow a short jump in a 32 bit code segment to be promoted to
280 a 16 bit offset jump because it's slower (requires data size
281 prefix), and doesn't work, unless the destination is in the bottom
282 64k of the code segment (The top 16 bits of eip are zeroed). */
284 const relax_typeS md_relax_table
[] =
287 1) most positive reach of this state,
288 2) most negative reach of this state,
289 3) how many bytes this mode will add to the size of the current frag
290 4) which index into the table to try if we can't fit into this one. */
296 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
298 /* dword conditionals adds 4 bytes to frag:
299 1 extra opcode byte, 3 extra displacement bytes. */
301 /* word conditionals add 2 bytes to frag:
302 1 extra opcode byte, 1 extra displacement byte. */
305 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
307 /* dword jmp adds 3 bytes to frag:
308 0 extra opcode bytes, 3 extra displacement bytes. */
310 /* word jmp adds 1 byte to frag:
311 0 extra opcode bytes, 1 extra displacement byte. */
316 static const arch_entry cpu_arch
[] = {
318 {"i186", Cpu086
|Cpu186
},
319 {"i286", Cpu086
|Cpu186
|Cpu286
},
320 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
321 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
322 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
323 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
324 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
325 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
326 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
327 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
332 i386_align_code (fragP
, count
)
336 /* Various efficient no-op patterns for aligning code labels.
337 Note: Don't try to assemble the instructions in the comments.
338 0L and 0w are not legal. */
339 static const char f32_1
[] =
341 static const char f32_2
[] =
342 {0x89,0xf6}; /* movl %esi,%esi */
343 static const char f32_3
[] =
344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
345 static const char f32_4
[] =
346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
347 static const char f32_5
[] =
349 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
350 static const char f32_6
[] =
351 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
352 static const char f32_7
[] =
353 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
354 static const char f32_8
[] =
356 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
357 static const char f32_9
[] =
358 {0x89,0xf6, /* movl %esi,%esi */
359 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
360 static const char f32_10
[] =
361 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
362 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
363 static const char f32_11
[] =
364 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
365 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
366 static const char f32_12
[] =
367 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
368 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
369 static const char f32_13
[] =
370 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
371 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
372 static const char f32_14
[] =
373 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
374 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
375 static const char f32_15
[] =
376 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
377 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
378 static const char f16_3
[] =
379 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
380 static const char f16_4
[] =
381 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
382 static const char f16_5
[] =
384 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
385 static const char f16_6
[] =
386 {0x89,0xf6, /* mov %si,%si */
387 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
388 static const char f16_7
[] =
389 {0x8d,0x74,0x00, /* lea 0(%si),%si */
390 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
391 static const char f16_8
[] =
392 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
393 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
394 static const char *const f32_patt
[] = {
395 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
396 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
398 static const char *const f16_patt
[] = {
399 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
400 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
403 if (count
> 0 && count
<= 15)
407 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
408 f16_patt
[count
- 1], count
);
410 /* Adjust jump offset. */
411 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
414 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
415 f32_patt
[count
- 1], count
);
416 fragP
->fr_var
= count
;
420 static char *output_invalid
PARAMS ((int c
));
421 static int i386_operand
PARAMS ((char *operand_string
));
422 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
423 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
427 static void s_bss
PARAMS ((int));
430 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
432 static INLINE
unsigned int
433 mode_from_disp_size (t
)
436 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
440 fits_in_signed_byte (num
)
443 return (num
>= -128) && (num
<= 127);
447 fits_in_unsigned_byte (num
)
450 return (num
& 0xff) == num
;
454 fits_in_unsigned_word (num
)
457 return (num
& 0xffff) == num
;
461 fits_in_signed_word (num
)
464 return (-32768 <= num
) && (num
<= 32767);
468 smallest_imm_type (num
)
471 if (cpu_arch_flags
!= 0
472 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
474 /* This code is disabled on the 486 because all the Imm1 forms
475 in the opcode table are slower on the i486. They're the
476 versions with the implicitly specified single-position
477 displacement, which has another syntax if you really want to
480 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
482 return (fits_in_signed_byte (num
)
483 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
484 : fits_in_unsigned_byte (num
)
485 ? (Imm8
| Imm16
| Imm32
)
486 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
492 offset_in_range (val
, size
)
500 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
501 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
502 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
506 /* If BFD64, sign extend val. */
507 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
508 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
510 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
512 char buf1
[40], buf2
[40];
514 sprint_value (buf1
, val
);
515 sprint_value (buf2
, val
& mask
);
516 as_warn (_("%s shortened to %s"), buf1
, buf2
);
521 /* Returns 0 if attempting to add a prefix where one from the same
522 class already exists, 1 if non rep/repne added, 2 if rep/repne
536 case CS_PREFIX_OPCODE
:
537 case DS_PREFIX_OPCODE
:
538 case ES_PREFIX_OPCODE
:
539 case FS_PREFIX_OPCODE
:
540 case GS_PREFIX_OPCODE
:
541 case SS_PREFIX_OPCODE
:
545 case REPNE_PREFIX_OPCODE
:
546 case REPE_PREFIX_OPCODE
:
549 case LOCK_PREFIX_OPCODE
:
557 case ADDR_PREFIX_OPCODE
:
561 case DATA_PREFIX_OPCODE
:
568 as_bad (_("same type of prefix used twice"));
573 i
.prefix
[q
] = prefix
;
578 set_16bit_code_flag (new_16bit_code_flag
)
579 int new_16bit_code_flag
;
581 flag_16bit_code
= new_16bit_code_flag
;
586 set_16bit_gcc_code_flag (new_16bit_code_flag
)
587 int new_16bit_code_flag
;
589 flag_16bit_code
= new_16bit_code_flag
;
590 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
594 set_intel_syntax (syntax_flag
)
597 /* Find out if register prefixing is specified. */
598 int ask_naked_reg
= 0;
601 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
603 char *string
= input_line_pointer
;
604 int e
= get_symbol_end ();
606 if (strcmp (string
, "prefix") == 0)
608 else if (strcmp (string
, "noprefix") == 0)
611 as_bad (_("bad argument to syntax directive."));
612 *input_line_pointer
= e
;
614 demand_empty_rest_of_line ();
616 intel_syntax
= syntax_flag
;
618 if (ask_naked_reg
== 0)
621 allow_naked_reg
= (intel_syntax
622 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
624 /* Conservative default. */
629 allow_naked_reg
= (ask_naked_reg
< 0);
634 int dummy ATTRIBUTE_UNUSED
;
638 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
640 char *string
= input_line_pointer
;
641 int e
= get_symbol_end ();
644 for (i
= 0; cpu_arch
[i
].name
; i
++)
646 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
648 cpu_arch_name
= cpu_arch
[i
].name
;
649 cpu_arch_flags
= cpu_arch
[i
].flags
;
653 if (!cpu_arch
[i
].name
)
654 as_bad (_("no such architecture: `%s'"), string
);
656 *input_line_pointer
= e
;
659 as_bad (_("missing cpu architecture"));
661 demand_empty_rest_of_line ();
664 const pseudo_typeS md_pseudo_table
[] =
666 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
667 {"align", s_align_bytes
, 0},
669 {"align", s_align_ptwo
, 0},
671 {"arch", set_cpu_arch
, 0},
675 {"ffloat", float_cons
, 'f'},
676 {"dfloat", float_cons
, 'd'},
677 {"tfloat", float_cons
, 'x'},
679 {"noopt", s_ignore
, 0},
680 {"optim", s_ignore
, 0},
681 {"code16gcc", set_16bit_gcc_code_flag
, 1},
682 {"code16", set_16bit_code_flag
, 1},
683 {"code32", set_16bit_code_flag
, 0},
684 {"intel_syntax", set_intel_syntax
, 1},
685 {"att_syntax", set_intel_syntax
, 0},
689 /* For interface with expression (). */
690 extern char *input_line_pointer
;
692 /* Hash table for instruction mnemonic lookup. */
693 static struct hash_control
*op_hash
;
695 /* Hash table for register lookup. */
696 static struct hash_control
*reg_hash
;
701 const char *hash_err
;
703 /* Initialize op_hash hash table. */
704 op_hash
= hash_new ();
707 register const template *optab
;
708 register templates
*core_optab
;
710 /* Setup for loop. */
712 core_optab
= (templates
*) xmalloc (sizeof (templates
));
713 core_optab
->start
= optab
;
718 if (optab
->name
== NULL
719 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
721 /* different name --> ship out current template list;
722 add to hash table; & begin anew. */
723 core_optab
->end
= optab
;
724 hash_err
= hash_insert (op_hash
,
730 as_fatal (_("Internal Error: Can't hash %s: %s"),
734 if (optab
->name
== NULL
)
736 core_optab
= (templates
*) xmalloc (sizeof (templates
));
737 core_optab
->start
= optab
;
742 /* Initialize reg_hash hash table. */
743 reg_hash
= hash_new ();
745 register const reg_entry
*regtab
;
747 for (regtab
= i386_regtab
;
748 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
751 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
757 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
762 for (c
= 0; c
< 256; c
++)
767 mnemonic_chars
[c
] = c
;
768 register_chars
[c
] = c
;
769 operand_chars
[c
] = c
;
771 else if (islower (c
))
773 mnemonic_chars
[c
] = c
;
774 register_chars
[c
] = c
;
775 operand_chars
[c
] = c
;
777 else if (isupper (c
))
779 mnemonic_chars
[c
] = tolower (c
);
780 register_chars
[c
] = mnemonic_chars
[c
];
781 operand_chars
[c
] = c
;
784 if (isalpha (c
) || isdigit (c
))
785 identifier_chars
[c
] = c
;
788 identifier_chars
[c
] = c
;
789 operand_chars
[c
] = c
;
794 identifier_chars
['@'] = '@';
796 digit_chars
['-'] = '-';
797 identifier_chars
['_'] = '_';
798 identifier_chars
['.'] = '.';
800 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
801 operand_chars
[(unsigned char) *p
] = *p
;
804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
805 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
807 record_alignment (text_section
, 2);
808 record_alignment (data_section
, 2);
809 record_alignment (bss_section
, 2);
815 i386_print_statistics (file
)
818 hash_print_statistics (file
, "i386 opcode", op_hash
);
819 hash_print_statistics (file
, "i386 register", reg_hash
);
824 /* Debugging routines for md_assemble. */
825 static void pi
PARAMS ((char *, i386_insn
*));
826 static void pte
PARAMS ((template *));
827 static void pt
PARAMS ((unsigned int));
828 static void pe
PARAMS ((expressionS
*));
829 static void ps
PARAMS ((symbolS
*));
836 register template *p
;
839 fprintf (stdout
, "%s: template ", line
);
841 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
842 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
843 fprintf (stdout
, " base %x index %x scale %x\n",
844 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
845 for (i
= 0; i
< x
->operands
; i
++)
847 fprintf (stdout
, " #%d: ", i
+ 1);
849 fprintf (stdout
, "\n");
851 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
852 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
853 if (x
->types
[i
] & Imm
)
855 if (x
->types
[i
] & Disp
)
865 fprintf (stdout
, " %d operands ", t
->operands
);
866 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
867 if (t
->extension_opcode
!= None
)
868 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
869 if (t
->opcode_modifier
& D
)
870 fprintf (stdout
, "D");
871 if (t
->opcode_modifier
& W
)
872 fprintf (stdout
, "W");
873 fprintf (stdout
, "\n");
874 for (i
= 0; i
< t
->operands
; i
++)
876 fprintf (stdout
, " #%d type ", i
+ 1);
877 pt (t
->operand_types
[i
]);
878 fprintf (stdout
, "\n");
886 fprintf (stdout
, " operation %d\n", e
->X_op
);
887 fprintf (stdout
, " add_number %ld (%lx)\n",
888 (long) e
->X_add_number
, (long) e
->X_add_number
);
891 fprintf (stdout
, " add_symbol ");
892 ps (e
->X_add_symbol
);
893 fprintf (stdout
, "\n");
897 fprintf (stdout
, " op_symbol ");
899 fprintf (stdout
, "\n");
907 fprintf (stdout
, "%s type %s%s",
909 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
910 segment_name (S_GET_SEGMENT (s
)));
929 { BaseIndex
, "BaseIndex" },
933 { InOutPortReg
, "InOutPortReg" },
934 { ShiftCount
, "ShiftCount" },
935 { Control
, "control reg" },
936 { Test
, "test reg" },
937 { Debug
, "debug reg" },
938 { FloatReg
, "FReg" },
939 { FloatAcc
, "FAcc" },
943 { JumpAbsolute
, "Jump Absolute" },
954 register struct type_name
*ty
;
958 fprintf (stdout
, _("Unknown"));
962 for (ty
= type_names
; ty
->mask
; ty
++)
964 fprintf (stdout
, "%s, ", ty
->tname
);
969 #endif /* DEBUG386 */
972 tc_i386_force_relocation (fixp
)
976 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
977 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
982 return fixp
->fx_r_type
== 7;
987 static bfd_reloc_code_real_type reloc
988 PARAMS ((int, int, bfd_reloc_code_real_type
));
990 static bfd_reloc_code_real_type
991 reloc (size
, pcrel
, other
)
994 bfd_reloc_code_real_type other
;
996 if (other
!= NO_RELOC
)
1003 case 1: return BFD_RELOC_8_PCREL
;
1004 case 2: return BFD_RELOC_16_PCREL
;
1005 case 4: return BFD_RELOC_32_PCREL
;
1007 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1013 case 1: return BFD_RELOC_8
;
1014 case 2: return BFD_RELOC_16
;
1015 case 4: return BFD_RELOC_32
;
1017 as_bad (_("can not do %d byte relocation"), size
);
1020 return BFD_RELOC_NONE
;
1023 /* Here we decide which fixups can be adjusted to make them relative to
1024 the beginning of the section instead of the symbol. Basically we need
1025 to make sure that the dynamic relocations are done correctly, so in
1026 some cases we force the original symbol to be used. */
1029 tc_i386_fix_adjustable (fixP
)
1032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1033 /* Prevent all adjustments to global symbols, or else dynamic
1034 linking will not work correctly. */
1035 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1036 || S_IS_WEAK (fixP
->fx_addsy
))
1039 /* adjust_reloc_syms doesn't know about the GOT. */
1040 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1041 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1042 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1043 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1044 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1049 #define reloc(SIZE,PCREL,OTHER) 0
1050 #define BFD_RELOC_16 0
1051 #define BFD_RELOC_32 0
1052 #define BFD_RELOC_16_PCREL 0
1053 #define BFD_RELOC_32_PCREL 0
1054 #define BFD_RELOC_386_PLT32 0
1055 #define BFD_RELOC_386_GOT32 0
1056 #define BFD_RELOC_386_GOTOFF 0
1059 static int intel_float_operand
PARAMS ((char *mnemonic
));
1062 intel_float_operand (mnemonic
)
1065 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1068 if (mnemonic
[0] == 'f')
1074 /* This is the guts of the machine-dependent assembler. LINE points to a
1075 machine dependent instruction. This function is supposed to emit
1076 the frags/bytes it assembles to. */
1082 /* Points to template once we've found it. */
1085 /* Count the size of the instruction generated. */
1090 char mnemonic
[MAX_MNEM_SIZE
];
1092 /* Initialize globals. */
1093 memset (&i
, '\0', sizeof (i
));
1094 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1095 i
.disp_reloc
[j
] = NO_RELOC
;
1096 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1097 memset (im_expressions
, '\0', sizeof (im_expressions
));
1098 save_stack_p
= save_stack
;
1100 /* First parse an instruction mnemonic & call i386_operand for the operands.
1101 We assume that the scrubber has arranged it so that line[0] is the valid
1102 start of a (possibly prefixed) mnemonic. */
1105 char *token_start
= l
;
1108 /* Non-zero if we found a prefix only acceptable with string insns. */
1109 const char *expecting_string_instruction
= NULL
;
1114 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1117 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1119 as_bad (_("no such instruction: `%s'"), token_start
);
1124 if (!is_space_char (*l
)
1125 && *l
!= END_OF_INSN
1126 && *l
!= PREFIX_SEPARATOR
)
1128 as_bad (_("invalid character %s in mnemonic"),
1129 output_invalid (*l
));
1132 if (token_start
== l
)
1134 if (*l
== PREFIX_SEPARATOR
)
1135 as_bad (_("expecting prefix; got nothing"));
1137 as_bad (_("expecting mnemonic; got nothing"));
1141 /* Look up instruction (or prefix) via hash table. */
1142 current_templates
= hash_find (op_hash
, mnemonic
);
1144 if (*l
!= END_OF_INSN
1145 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1146 && current_templates
1147 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1149 /* If we are in 16-bit mode, do not allow addr16 or data16.
1150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1151 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1152 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1155 as_bad (_("redundant %s prefix"),
1156 current_templates
->start
->name
);
1159 /* Add prefix, checking for repeated prefixes. */
1160 switch (add_prefix (current_templates
->start
->base_opcode
))
1165 expecting_string_instruction
= current_templates
->start
->name
;
1168 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1175 if (!current_templates
)
1177 /* See if we can get a match by trimming off a suffix. */
1180 case WORD_MNEM_SUFFIX
:
1181 case BYTE_MNEM_SUFFIX
:
1182 case SHORT_MNEM_SUFFIX
:
1183 case LONG_MNEM_SUFFIX
:
1184 i
.suffix
= mnem_p
[-1];
1186 current_templates
= hash_find (op_hash
, mnemonic
);
1190 case DWORD_MNEM_SUFFIX
:
1193 i
.suffix
= mnem_p
[-1];
1195 current_templates
= hash_find (op_hash
, mnemonic
);
1199 if (!current_templates
)
1201 as_bad (_("no such instruction: `%s'"), token_start
);
1206 /* Check if instruction is supported on specified architecture. */
1207 if (cpu_arch_flags
!= 0)
1209 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1211 as_warn (_("`%s' is not supported on `%s'"),
1212 current_templates
->start
->name
, cpu_arch_name
);
1214 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1216 as_warn (_("use .code16 to ensure correct addressing mode"));
1220 /* Check for rep/repne without a string instruction. */
1221 if (expecting_string_instruction
1222 && !(current_templates
->start
->opcode_modifier
& IsString
))
1224 as_bad (_("expecting string instruction after `%s'"),
1225 expecting_string_instruction
);
1229 /* There may be operands to parse. */
1230 if (*l
!= END_OF_INSN
)
1232 /* 1 if operand is pending after ','. */
1233 unsigned int expecting_operand
= 0;
1235 /* Non-zero if operand parens not balanced. */
1236 unsigned int paren_not_balanced
;
1240 /* Skip optional white space before operand. */
1241 if (is_space_char (*l
))
1243 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1245 as_bad (_("invalid character %s before operand %d"),
1246 output_invalid (*l
),
1250 token_start
= l
; /* after white space */
1251 paren_not_balanced
= 0;
1252 while (paren_not_balanced
|| *l
!= ',')
1254 if (*l
== END_OF_INSN
)
1256 if (paren_not_balanced
)
1259 as_bad (_("unbalanced parenthesis in operand %d."),
1262 as_bad (_("unbalanced brackets in operand %d."),
1267 break; /* we are done */
1269 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1271 as_bad (_("invalid character %s in operand %d"),
1272 output_invalid (*l
),
1279 ++paren_not_balanced
;
1281 --paren_not_balanced
;
1286 ++paren_not_balanced
;
1288 --paren_not_balanced
;
1292 if (l
!= token_start
)
1293 { /* Yes, we've read in another operand. */
1294 unsigned int operand_ok
;
1295 this_operand
= i
.operands
++;
1296 if (i
.operands
> MAX_OPERANDS
)
1298 as_bad (_("spurious operands; (%d operands/instruction max)"),
1302 /* Now parse operand adding info to 'i' as we go along. */
1303 END_STRING_AND_SAVE (l
);
1307 i386_intel_operand (token_start
,
1308 intel_float_operand (mnemonic
));
1310 operand_ok
= i386_operand (token_start
);
1312 RESTORE_END_STRING (l
);
1318 if (expecting_operand
)
1320 expecting_operand_after_comma
:
1321 as_bad (_("expecting operand after ','; got nothing"));
1326 as_bad (_("expecting operand before ','; got nothing"));
1331 /* Now *l must be either ',' or END_OF_INSN. */
1334 if (*++l
== END_OF_INSN
)
1336 /* Just skip it, if it's \n complain. */
1337 goto expecting_operand_after_comma
;
1339 expecting_operand
= 1;
1342 while (*l
!= END_OF_INSN
);
1346 /* Now we've parsed the mnemonic into a set of templates, and have the
1349 Next, we find a template that matches the given insn,
1350 making sure the overlap of the given operands types is consistent
1351 with the template operand types. */
1353 #define MATCH(overlap, given, template) \
1354 ((overlap & ~JumpAbsolute) \
1355 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1357 /* If given types r0 and r1 are registers they must be of the same type
1358 unless the expected operand type register overlap is null.
1359 Note that Acc in a template matches every size of reg. */
1360 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1361 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1362 ((g0) & Reg) == ((g1) & Reg) || \
1363 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1366 register unsigned int overlap0
, overlap1
;
1367 unsigned int overlap2
;
1368 unsigned int found_reverse_match
;
1371 /* All intel opcodes have reversed operands except for "bound" and
1372 "enter". We also don't reverse intersegment "jmp" and "call"
1373 instructions with 2 immediate operands so that the immediate segment
1374 precedes the offset, as it does when in AT&T mode. "enter" and the
1375 intersegment "jmp" and "call" instructions are the only ones that
1376 have two immediate operands. */
1377 if (intel_syntax
&& i
.operands
> 1
1378 && (strcmp (mnemonic
, "bound") != 0)
1379 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1381 union i386_op temp_op
;
1382 unsigned int temp_type
;
1386 if (i
.operands
== 2)
1391 else if (i
.operands
== 3)
1396 temp_type
= i
.types
[xchg2
];
1397 i
.types
[xchg2
] = i
.types
[xchg1
];
1398 i
.types
[xchg1
] = temp_type
;
1399 temp_op
= i
.op
[xchg2
];
1400 i
.op
[xchg2
] = i
.op
[xchg1
];
1401 i
.op
[xchg1
] = temp_op
;
1403 if (i
.mem_operands
== 2)
1405 const seg_entry
*temp_seg
;
1406 temp_seg
= i
.seg
[0];
1407 i
.seg
[0] = i
.seg
[1];
1408 i
.seg
[1] = temp_seg
;
1414 /* Try to ensure constant immediates are represented in the smallest
1416 char guess_suffix
= 0;
1420 guess_suffix
= i
.suffix
;
1421 else if (i
.reg_operands
)
1423 /* Figure out a suffix from the last register operand specified.
1424 We can't do this properly yet, ie. excluding InOutPortReg,
1425 but the following works for instructions with immediates.
1426 In any case, we can't set i.suffix yet. */
1427 for (op
= i
.operands
; --op
>= 0;)
1428 if (i
.types
[op
] & Reg
)
1430 if (i
.types
[op
] & Reg8
)
1431 guess_suffix
= BYTE_MNEM_SUFFIX
;
1432 else if (i
.types
[op
] & Reg16
)
1433 guess_suffix
= WORD_MNEM_SUFFIX
;
1437 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1438 guess_suffix
= WORD_MNEM_SUFFIX
;
1440 for (op
= i
.operands
; --op
>= 0;)
1441 if ((i
.types
[op
] & Imm
)
1442 && i
.op
[op
].imms
->X_op
== O_constant
)
1444 /* If a suffix is given, this operand may be shortened. */
1445 switch (guess_suffix
)
1447 case WORD_MNEM_SUFFIX
:
1448 i
.types
[op
] |= Imm16
;
1450 case BYTE_MNEM_SUFFIX
:
1451 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1455 /* If this operand is at most 16 bits, convert it to a
1456 signed 16 bit number before trying to see whether it will
1457 fit in an even smaller size. This allows a 16-bit operand
1458 such as $0xffe0 to be recognised as within Imm8S range. */
1459 if ((i
.types
[op
] & Imm16
)
1460 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1462 i
.op
[op
].imms
->X_add_number
=
1463 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1465 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1469 if (i
.disp_operands
)
1471 /* Try to use the smallest displacement type too. */
1474 for (op
= i
.operands
; --op
>= 0;)
1475 if ((i
.types
[op
] & Disp
)
1476 && i
.op
[op
].imms
->X_op
== O_constant
)
1478 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1480 if (i
.types
[op
] & Disp16
)
1482 /* We know this operand is at most 16 bits, so
1483 convert to a signed 16 bit number before trying
1484 to see whether it will fit in an even smaller
1487 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1489 if (fits_in_signed_byte (disp
))
1490 i
.types
[op
] |= Disp8
;
1497 found_reverse_match
= 0;
1498 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1500 : (i
.suffix
== WORD_MNEM_SUFFIX
1502 : (i
.suffix
== SHORT_MNEM_SUFFIX
1504 : (i
.suffix
== LONG_MNEM_SUFFIX
1506 : (i
.suffix
== DWORD_MNEM_SUFFIX
1508 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1510 for (t
= current_templates
->start
;
1511 t
< current_templates
->end
;
1514 /* Must have right number of operands. */
1515 if (i
.operands
!= t
->operands
)
1518 /* Check the suffix, except for some instructions in intel mode. */
1519 if ((t
->opcode_modifier
& suffix_check
)
1521 && (t
->opcode_modifier
& IgnoreSize
))
1523 && t
->base_opcode
== 0xd9
1524 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1525 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1528 else if (!t
->operands
)
1529 /* 0 operands always matches. */
1532 overlap0
= i
.types
[0] & t
->operand_types
[0];
1533 switch (t
->operands
)
1536 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1541 overlap1
= i
.types
[1] & t
->operand_types
[1];
1542 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1543 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1544 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1545 t
->operand_types
[0],
1546 overlap1
, i
.types
[1],
1547 t
->operand_types
[1]))
1549 /* Check if other direction is valid ... */
1550 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1553 /* Try reversing direction of operands. */
1554 overlap0
= i
.types
[0] & t
->operand_types
[1];
1555 overlap1
= i
.types
[1] & t
->operand_types
[0];
1556 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1557 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1558 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1559 t
->operand_types
[1],
1560 overlap1
, i
.types
[1],
1561 t
->operand_types
[0]))
1563 /* Does not match either direction. */
1566 /* found_reverse_match holds which of D or FloatDR
1568 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1571 /* Found a forward 2 operand match here. */
1572 if (t
->operands
== 3)
1574 /* Here we make use of the fact that there are no
1575 reverse match 3 operand instructions, and all 3
1576 operand instructions only need to be checked for
1577 register consistency between operands 2 and 3. */
1578 overlap2
= i
.types
[2] & t
->operand_types
[2];
1579 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1580 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1581 t
->operand_types
[1],
1582 overlap2
, i
.types
[2],
1583 t
->operand_types
[2]))
1587 /* Found either forward/reverse 2 or 3 operand match here:
1588 slip through to break. */
1590 /* We've found a match; break out of loop. */
1593 if (t
== current_templates
->end
)
1595 /* We found no match. */
1596 as_bad (_("suffix or operands invalid for `%s'"),
1597 current_templates
->start
->name
);
1601 if (!quiet_warnings
)
1604 && ((i
.types
[0] & JumpAbsolute
)
1605 != (t
->operand_types
[0] & JumpAbsolute
)))
1607 as_warn (_("indirect %s without `*'"), t
->name
);
1610 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1611 == (IsPrefix
|IgnoreSize
))
1613 /* Warn them that a data or address size prefix doesn't
1614 affect assembly of the next line of code. */
1615 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1619 /* Copy the template we found. */
1621 if (found_reverse_match
)
1623 /* If we found a reverse match we must alter the opcode
1624 direction bit. found_reverse_match holds bits to change
1625 (different for int & float insns). */
1627 i
.tm
.base_opcode
^= found_reverse_match
;
1629 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1630 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1633 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1636 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1637 i
.tm
.base_opcode
^= FloatR
;
1639 if (i
.tm
.opcode_modifier
& FWait
)
1640 if (! add_prefix (FWAIT_OPCODE
))
1643 /* Check string instruction segment overrides. */
1644 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1646 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1647 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1649 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1651 as_bad (_("`%s' operand %d must use `%%es' segment"),
1656 /* There's only ever one segment override allowed per instruction.
1657 This instruction possibly has a legal segment override on the
1658 second operand, so copy the segment to where non-string
1659 instructions store it, allowing common code. */
1660 i
.seg
[0] = i
.seg
[1];
1662 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1664 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1666 as_bad (_("`%s' operand %d must use `%%es' segment"),
1674 /* If matched instruction specifies an explicit instruction mnemonic
1676 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1678 if (i
.tm
.opcode_modifier
& Size16
)
1679 i
.suffix
= WORD_MNEM_SUFFIX
;
1681 i
.suffix
= LONG_MNEM_SUFFIX
;
1683 else if (i
.reg_operands
)
1685 /* If there's no instruction mnemonic suffix we try to invent one
1686 based on register operands. */
1689 /* We take i.suffix from the last register operand specified,
1690 Destination register type is more significant than source
1693 for (op
= i
.operands
; --op
>= 0;)
1694 if ((i
.types
[op
] & Reg
)
1695 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1697 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1698 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1703 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1706 for (op
= i
.operands
; --op
>= 0;)
1708 /* If this is an eight bit register, it's OK. If it's
1709 the 16 or 32 bit version of an eight bit register,
1710 we will just use the low portion, and that's OK too. */
1711 if (i
.types
[op
] & Reg8
)
1714 /* movzx and movsx should not generate this warning. */
1716 && (i
.tm
.base_opcode
== 0xfb7
1717 || i
.tm
.base_opcode
== 0xfb6
1718 || i
.tm
.base_opcode
== 0xfbe
1719 || i
.tm
.base_opcode
== 0xfbf))
1722 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1724 /* Check that the template allows eight bit regs
1725 This kills insns such as `orb $1,%edx', which
1726 maybe should be allowed. */
1727 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1731 #if REGISTER_WARNINGS
1733 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1734 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1735 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1736 i
.op
[op
].regs
->reg_name
,
1741 /* Any other register is bad. */
1742 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1744 | Control
| Debug
| Test
1745 | FloatReg
| FloatAcc
))
1747 as_bad (_("`%%%s' not allowed with `%s%c'"),
1748 i
.op
[op
].regs
->reg_name
,
1755 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1759 for (op
= i
.operands
; --op
>= 0;)
1760 /* Reject eight bit registers, except where the template
1761 requires them. (eg. movzb) */
1762 if ((i
.types
[op
] & Reg8
) != 0
1763 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1765 as_bad (_("`%%%s' not allowed with `%s%c'"),
1766 i
.op
[op
].regs
->reg_name
,
1771 #if REGISTER_WARNINGS
1772 /* Warn if the e prefix on a general reg is missing. */
1773 else if (!quiet_warnings
1774 && (i
.types
[op
] & Reg16
) != 0
1775 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1777 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1778 (i
.op
[op
].regs
+ 8)->reg_name
,
1779 i
.op
[op
].regs
->reg_name
,
1784 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1787 for (op
= i
.operands
; --op
>= 0;)
1788 /* Reject eight bit registers, except where the template
1789 requires them. (eg. movzb) */
1790 if ((i
.types
[op
] & Reg8
) != 0
1791 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1793 as_bad (_("`%%%s' not allowed with `%s%c'"),
1794 i
.op
[op
].regs
->reg_name
,
1799 #if REGISTER_WARNINGS
1800 /* Warn if the e prefix on a general reg is present. */
1801 else if (!quiet_warnings
1802 && (i
.types
[op
] & Reg32
) != 0
1803 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1805 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1806 (i
.op
[op
].regs
- 8)->reg_name
,
1807 i
.op
[op
].regs
->reg_name
,
1812 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
1813 /* Do nothing if the instruction is going to ignore the prefix. */
1818 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1820 i
.suffix
= stackop_size
;
1823 /* Make still unresolved immediate matches conform to size of immediate
1824 given in i.suffix. Note: overlap2 cannot be an immediate! */
1825 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1826 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1827 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1831 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1832 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1834 else if (overlap0
== (Imm16
| Imm32
))
1837 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1841 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1845 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1846 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1847 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1851 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1852 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1854 else if (overlap1
== (Imm16
| Imm32
))
1857 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1861 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1865 assert ((overlap2
& Imm
) == 0);
1867 i
.types
[0] = overlap0
;
1868 if (overlap0
& ImplicitRegister
)
1870 if (overlap0
& Imm1
)
1871 i
.imm_operands
= 0; /* kludge for shift insns. */
1873 i
.types
[1] = overlap1
;
1874 if (overlap1
& ImplicitRegister
)
1877 i
.types
[2] = overlap2
;
1878 if (overlap2
& ImplicitRegister
)
1881 /* Finalize opcode. First, we change the opcode based on the operand
1882 size given by i.suffix: We need not change things for byte insns. */
1884 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1886 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1890 /* For movzx and movsx, need to check the register type. */
1892 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1893 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1895 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1897 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1898 if (!add_prefix (prefix
))
1902 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1904 /* It's not a byte, select word/dword operation. */
1905 if (i
.tm
.opcode_modifier
& W
)
1907 if (i
.tm
.opcode_modifier
& ShortForm
)
1908 i
.tm
.base_opcode
|= 8;
1910 i
.tm
.base_opcode
|= 1;
1912 /* Now select between word & dword operations via the operand
1913 size prefix, except for instructions that will ignore this
1915 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1916 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1917 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1919 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1920 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1921 prefix
= ADDR_PREFIX_OPCODE
;
1923 if (! add_prefix (prefix
))
1926 /* Size floating point instruction. */
1927 if (i
.suffix
== LONG_MNEM_SUFFIX
1928 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1930 if (i
.tm
.opcode_modifier
& FloatMF
)
1931 i
.tm
.base_opcode
^= 4;
1935 if (i
.tm
.opcode_modifier
& ImmExt
)
1937 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1938 opcode suffix which is coded in the same place as an 8-bit
1939 immediate field would be. Here we fake an 8-bit immediate
1940 operand from the opcode suffix stored in tm.extension_opcode. */
1944 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1946 exp
= &im_expressions
[i
.imm_operands
++];
1947 i
.op
[i
.operands
].imms
= exp
;
1948 i
.types
[i
.operands
++] = Imm8
;
1949 exp
->X_op
= O_constant
;
1950 exp
->X_add_number
= i
.tm
.extension_opcode
;
1951 i
.tm
.extension_opcode
= None
;
1954 /* For insns with operands there are more diddles to do to the opcode. */
1957 /* Default segment register this instruction will use
1958 for memory accesses. 0 means unknown.
1959 This is only for optimizing out unnecessary segment overrides. */
1960 const seg_entry
*default_seg
= 0;
1962 /* The imul $imm, %reg instruction is converted into
1963 imul $imm, %reg, %reg, and the clr %reg instruction
1964 is converted into xor %reg, %reg. */
1965 if (i
.tm
.opcode_modifier
& regKludge
)
1967 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1968 /* Pretend we saw the extra register operand. */
1969 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1970 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1971 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1975 if (i
.tm
.opcode_modifier
& ShortForm
)
1977 /* The register or float register operand is in operand 0 or 1. */
1978 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1979 /* Register goes in low 3 bits of opcode. */
1980 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1981 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1983 /* Warn about some common errors, but press on regardless.
1984 The first case can be generated by gcc (<= 2.8.1). */
1985 if (i
.operands
== 2)
1987 /* Reversed arguments on faddp, fsubp, etc. */
1988 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1989 i
.op
[1].regs
->reg_name
,
1990 i
.op
[0].regs
->reg_name
);
1994 /* Extraneous `l' suffix on fp insn. */
1995 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1996 i
.op
[0].regs
->reg_name
);
2000 else if (i
.tm
.opcode_modifier
& Modrm
)
2002 /* The opcode is completed (modulo i.tm.extension_opcode which
2003 must be put into the modrm byte).
2004 Now, we make the modrm & index base bytes based on all the
2005 info we've collected. */
2007 /* i.reg_operands MUST be the number of real register operands;
2008 implicit registers do not count. */
2009 if (i
.reg_operands
== 2)
2011 unsigned int source
, dest
;
2012 source
= ((i
.types
[0]
2013 & (Reg
| RegMMX
| RegXMM
2015 | Control
| Debug
| Test
))
2020 /* One of the register operands will be encoded in the
2021 i.tm.reg field, the other in the combined i.tm.mode
2022 and i.tm.regmem fields. If no form of this
2023 instruction supports a memory destination operand,
2024 then we assume the source operand may sometimes be
2025 a memory operand and so we need to store the
2026 destination in the i.rm.reg field. */
2027 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2029 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2030 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2034 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2035 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2039 { /* If it's not 2 reg operands... */
2042 unsigned int fake_zero_displacement
= 0;
2043 unsigned int op
= ((i
.types
[0] & AnyMem
)
2045 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2052 if (! i
.disp_operands
)
2053 fake_zero_displacement
= 1;
2056 /* Operand is just <disp> */
2057 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2059 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2060 i
.types
[op
] &= ~Disp
;
2061 i
.types
[op
] |= Disp16
;
2065 i
.rm
.regmem
= NO_BASE_REGISTER
;
2066 i
.types
[op
] &= ~Disp
;
2067 i
.types
[op
] |= Disp32
;
2070 else /* ! i.base_reg && i.index_reg */
2072 i
.sib
.index
= i
.index_reg
->reg_num
;
2073 i
.sib
.base
= NO_BASE_REGISTER
;
2074 i
.sib
.scale
= i
.log2_scale_factor
;
2075 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2076 i
.types
[op
] &= ~Disp
;
2077 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2080 else if (i
.base_reg
->reg_type
& Reg16
)
2082 switch (i
.base_reg
->reg_num
)
2087 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2088 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2095 if ((i
.types
[op
] & Disp
) == 0)
2097 /* fake (%bp) into 0(%bp) */
2098 i
.types
[op
] |= Disp8
;
2099 fake_zero_displacement
= 1;
2102 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2103 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2105 default: /* (%si) -> 4 or (%di) -> 5 */
2106 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2108 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2110 else /* i.base_reg and 32 bit mode */
2112 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2113 i
.sib
.base
= i
.base_reg
->reg_num
;
2114 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2117 if (i
.disp_operands
== 0)
2119 fake_zero_displacement
= 1;
2120 i
.types
[op
] |= Disp8
;
2123 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2127 i
.sib
.scale
= i
.log2_scale_factor
;
2130 /* <disp>(%esp) becomes two byte modrm
2131 with no index register. We've already
2132 stored the code for esp in i.rm.regmem
2133 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2134 base register besides %esp will not use
2135 the extra modrm byte. */
2136 i
.sib
.index
= NO_INDEX_REGISTER
;
2137 #if ! SCALE1_WHEN_NO_INDEX
2138 /* Another case where we force the second
2140 if (i
.log2_scale_factor
)
2141 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2146 i
.sib
.index
= i
.index_reg
->reg_num
;
2147 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2149 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2152 if (fake_zero_displacement
)
2154 /* Fakes a zero displacement assuming that i.types[op]
2155 holds the correct displacement size. */
2158 assert (i
.op
[op
].disps
== 0);
2159 exp
= &disp_expressions
[i
.disp_operands
++];
2160 i
.op
[op
].disps
= exp
;
2161 exp
->X_op
= O_constant
;
2162 exp
->X_add_number
= 0;
2163 exp
->X_add_symbol
= (symbolS
*) 0;
2164 exp
->X_op_symbol
= (symbolS
*) 0;
2168 /* Fill in i.rm.reg or i.rm.regmem field with register
2169 operand (if any) based on i.tm.extension_opcode.
2170 Again, we must be careful to make sure that
2171 segment/control/debug/test/MMX registers are coded
2172 into the i.rm.reg field. */
2177 & (Reg
| RegMMX
| RegXMM
2179 | Control
| Debug
| Test
))
2182 & (Reg
| RegMMX
| RegXMM
2184 | Control
| Debug
| Test
))
2187 /* If there is an extension opcode to put here, the
2188 register number must be put into the regmem field. */
2189 if (i
.tm
.extension_opcode
!= None
)
2190 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2192 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2194 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2195 we must set it to 3 to indicate this is a register
2196 operand in the regmem field. */
2197 if (!i
.mem_operands
)
2201 /* Fill in i.rm.reg field with extension opcode (if any). */
2202 if (i
.tm
.extension_opcode
!= None
)
2203 i
.rm
.reg
= i
.tm
.extension_opcode
;
2206 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2208 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2209 && i
.op
[0].regs
->reg_num
== 1)
2211 as_bad (_("you can't `pop %%cs'"));
2214 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2216 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2220 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2222 /* For the string instructions that allow a segment override
2223 on one of their operands, the default segment is ds. */
2227 /* If a segment was explicitly specified,
2228 and the specified segment is not the default,
2229 use an opcode prefix to select it.
2230 If we never figured out what the default segment is,
2231 then default_seg will be zero at this point,
2232 and the specified segment prefix will always be used. */
2233 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2235 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2239 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2241 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2242 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2246 /* Handle conversion of 'int $3' --> special int3 insn. */
2247 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2249 i
.tm
.base_opcode
= INT3_OPCODE
;
2253 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2254 && i
.op
[0].disps
->X_op
== O_constant
)
2256 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2257 the absolute address given by the constant. Since ix86 jumps and
2258 calls are pc relative, we need to generate a reloc. */
2259 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2260 i
.op
[0].disps
->X_op
= O_symbol
;
2263 /* We are ready to output the insn. */
2268 if (i
.tm
.opcode_modifier
& Jump
)
2275 if (flag_16bit_code
)
2279 if (i
.prefix
[DATA_PREFIX
])
2290 if (i
.prefixes
!= 0 && !intel_syntax
)
2291 as_warn (_("skipping prefixes on this instruction"));
2293 /* It's always a symbol; End frag & setup for relax.
2294 Make sure there is enough room in this frag for the largest
2295 instruction we may generate in md_convert_frag. This is 2
2296 bytes for the opcode and room for the prefix and largest
2298 frag_grow (prefix
+ 2 + size
);
2299 insn_size
+= prefix
+ 1;
2300 /* Prefix and 1 opcode byte go in fr_fix. */
2301 p
= frag_more (prefix
+ 1);
2303 *p
++ = DATA_PREFIX_OPCODE
;
2304 *p
= i
.tm
.base_opcode
;
2305 /* 1 possible extra opcode + displacement go in var part.
2306 Pass reloc in fr_var. */
2307 frag_var (rs_machine_dependent
,
2310 ((unsigned char) *p
== JUMP_PC_RELATIVE
2311 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2312 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2313 i
.op
[0].disps
->X_add_symbol
,
2314 i
.op
[0].disps
->X_add_number
,
2317 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2321 if (i
.tm
.opcode_modifier
& JumpByte
)
2323 /* This is a loop or jecxz type instruction. */
2325 if (i
.prefix
[ADDR_PREFIX
])
2328 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2337 if (flag_16bit_code
)
2340 if (i
.prefix
[DATA_PREFIX
])
2343 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2353 if (i
.prefixes
!= 0 && !intel_syntax
)
2354 as_warn (_("skipping prefixes on this instruction"));
2356 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2358 insn_size
+= 1 + size
;
2359 p
= frag_more (1 + size
);
2363 /* Opcode can be at most two bytes. */
2364 insn_size
+= 2 + size
;
2365 p
= frag_more (2 + size
);
2366 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2368 *p
++ = i
.tm
.base_opcode
& 0xff;
2370 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2371 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2373 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2380 if (flag_16bit_code
)
2384 if (i
.prefix
[DATA_PREFIX
])
2395 if (i
.prefixes
!= 0 && !intel_syntax
)
2396 as_warn (_("skipping prefixes on this instruction"));
2398 /* 1 opcode; 2 segment; offset */
2399 insn_size
+= prefix
+ 1 + 2 + size
;
2400 p
= frag_more (prefix
+ 1 + 2 + size
);
2402 *p
++ = DATA_PREFIX_OPCODE
;
2403 *p
++ = i
.tm
.base_opcode
;
2404 if (i
.op
[1].imms
->X_op
== O_constant
)
2406 offsetT n
= i
.op
[1].imms
->X_add_number
;
2409 && !fits_in_unsigned_word (n
)
2410 && !fits_in_signed_word (n
))
2412 as_bad (_("16-bit jump out of range"));
2415 md_number_to_chars (p
, n
, size
);
2418 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2419 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2420 if (i
.op
[0].imms
->X_op
!= O_constant
)
2421 as_bad (_("can't handle non absolute segment in `%s'"),
2423 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2427 /* Output normal instructions here. */
2430 /* The prefix bytes. */
2432 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2439 md_number_to_chars (p
, (valueT
) *q
, 1);
2443 /* Now the opcode; be careful about word order here! */
2444 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2447 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2449 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2453 /* Put out high byte first: can't use md_number_to_chars! */
2454 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2455 *p
= i
.tm
.base_opcode
& 0xff;
2458 { /* Opcode is either 3 or 4 bytes. */
2459 if (i
.tm
.base_opcode
& 0xff000000)
2463 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2470 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2471 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2472 *p
= (i
.tm
.base_opcode
) & 0xff;
2475 /* Now the modrm byte and sib byte (if present). */
2476 if (i
.tm
.opcode_modifier
& Modrm
)
2480 md_number_to_chars (p
,
2481 (valueT
) (i
.rm
.regmem
<< 0
2485 /* If i.rm.regmem == ESP (4)
2486 && i.rm.mode != (Register mode)
2488 ==> need second modrm byte. */
2489 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2491 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2495 md_number_to_chars (p
,
2496 (valueT
) (i
.sib
.base
<< 0
2498 | i
.sib
.scale
<< 6),
2503 if (i
.disp_operands
)
2505 register unsigned int n
;
2507 for (n
= 0; n
< i
.operands
; n
++)
2509 if (i
.types
[n
] & Disp
)
2511 if (i
.op
[n
].disps
->X_op
== O_constant
)
2517 if (i
.types
[n
] & (Disp8
| Disp16
))
2520 if (i
.types
[n
] & Disp8
)
2523 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2526 p
= frag_more (size
);
2527 md_number_to_chars (p
, val
, size
);
2533 if (i
.types
[n
] & Disp16
)
2537 p
= frag_more (size
);
2538 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2540 reloc (size
, 0, i
.disp_reloc
[n
]));
2546 /* Output immediate. */
2549 register unsigned int n
;
2551 for (n
= 0; n
< i
.operands
; n
++)
2553 if (i
.types
[n
] & Imm
)
2555 if (i
.op
[n
].imms
->X_op
== O_constant
)
2561 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2564 if (i
.types
[n
] & (Imm8
| Imm8S
))
2567 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2570 p
= frag_more (size
);
2571 md_number_to_chars (p
, val
, size
);
2575 /* Not absolute_section.
2576 Need a 32-bit fixup (don't support 8bit
2577 non-absolute imms). Try to support other
2579 #ifdef BFD_ASSEMBLER
2580 enum bfd_reloc_code_real reloc_type
;
2586 if (i
.types
[n
] & Imm16
)
2588 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2592 p
= frag_more (size
);
2593 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2594 #ifdef BFD_ASSEMBLER
2595 if (reloc_type
== BFD_RELOC_32
2597 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2598 && (i
.op
[n
].imms
->X_op
== O_symbol
2599 || (i
.op
[n
].imms
->X_op
== O_add
2600 && ((symbol_get_value_expression
2601 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2604 reloc_type
= BFD_RELOC_386_GOTPC
;
2605 i
.op
[n
].imms
->X_add_number
+= 3;
2608 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2609 i
.op
[n
].imms
, 0, reloc_type
);
2621 #endif /* DEBUG386 */
2625 static int i386_immediate
PARAMS ((char *));
2628 i386_immediate (imm_start
)
2631 char *save_input_line_pointer
;
2635 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2637 as_bad (_("only 1 or 2 immediate operands are allowed"));
2641 exp
= &im_expressions
[i
.imm_operands
++];
2642 i
.op
[this_operand
].imms
= exp
;
2644 if (is_space_char (*imm_start
))
2647 save_input_line_pointer
= input_line_pointer
;
2648 input_line_pointer
= imm_start
;
2652 /* We can have operands of the form
2653 <symbol>@GOTOFF+<nnn>
2654 Take the easy way out here and copy everything
2655 into a temporary buffer... */
2658 cp
= strchr (input_line_pointer
, '@');
2665 /* GOT relocations are not supported in 16 bit mode. */
2666 if (flag_16bit_code
)
2667 as_bad (_("GOT relocations not supported in 16 bit mode"));
2669 if (GOT_symbol
== NULL
)
2670 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2672 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2674 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2677 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2679 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2682 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2684 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2688 as_bad (_("bad reloc specifier in expression"));
2690 /* Replace the relocation token with ' ', so that errors like
2691 foo@GOTOFF1 will be detected. */
2692 first
= cp
- input_line_pointer
;
2693 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2694 memcpy (tmpbuf
, input_line_pointer
, first
);
2695 tmpbuf
[first
] = ' ';
2696 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2697 input_line_pointer
= tmpbuf
;
2702 exp_seg
= expression (exp
);
2705 if (*input_line_pointer
)
2706 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2708 input_line_pointer
= save_input_line_pointer
;
2710 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2712 /* Missing or bad expr becomes absolute 0. */
2713 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2715 exp
->X_op
= O_constant
;
2716 exp
->X_add_number
= 0;
2717 exp
->X_add_symbol
= (symbolS
*) 0;
2718 exp
->X_op_symbol
= (symbolS
*) 0;
2721 if (exp
->X_op
== O_constant
)
2723 /* Size it properly later. */
2724 i
.types
[this_operand
] |= Imm32
;
2726 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2728 #ifdef BFD_ASSEMBLER
2729 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2731 && exp_seg
!= text_section
2732 && exp_seg
!= data_section
2733 && exp_seg
!= bss_section
2734 && exp_seg
!= undefined_section
2735 #ifdef BFD_ASSEMBLER
2736 && !bfd_is_com_section (exp_seg
)
2740 #ifdef BFD_ASSEMBLER
2741 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2743 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2750 /* This is an address. The size of the address will be
2751 determined later, depending on destination register,
2752 suffix, or the default for the section. We exclude
2753 Imm8S here so that `push $foo' and other instructions
2754 with an Imm8S form will use Imm16 or Imm32. */
2755 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2761 static int i386_scale
PARAMS ((char *));
2767 if (!isdigit (*scale
))
2774 i
.log2_scale_factor
= 0;
2777 i
.log2_scale_factor
= 1;
2780 i
.log2_scale_factor
= 2;
2783 i
.log2_scale_factor
= 3;
2787 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2791 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2793 as_warn (_("scale factor of %d without an index register"),
2794 1 << i
.log2_scale_factor
);
2795 #if SCALE1_WHEN_NO_INDEX
2796 i
.log2_scale_factor
= 0;
2802 static int i386_displacement
PARAMS ((char *, char *));
2805 i386_displacement (disp_start
, disp_end
)
2809 register expressionS
*exp
;
2811 char *save_input_line_pointer
;
2812 int bigdisp
= Disp32
;
2814 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2816 i
.types
[this_operand
] |= bigdisp
;
2818 exp
= &disp_expressions
[i
.disp_operands
];
2819 i
.op
[this_operand
].disps
= exp
;
2821 save_input_line_pointer
= input_line_pointer
;
2822 input_line_pointer
= disp_start
;
2823 END_STRING_AND_SAVE (disp_end
);
2825 #ifndef GCC_ASM_O_HACK
2826 #define GCC_ASM_O_HACK 0
2829 END_STRING_AND_SAVE (disp_end
+ 1);
2830 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2831 && displacement_string_end
[-1] == '+')
2833 /* This hack is to avoid a warning when using the "o"
2834 constraint within gcc asm statements.
2837 #define _set_tssldt_desc(n,addr,limit,type) \
2838 __asm__ __volatile__ ( \
2840 "movw %w1,2+%0\n\t" \
2842 "movb %b1,4+%0\n\t" \
2843 "movb %4,5+%0\n\t" \
2844 "movb $0,6+%0\n\t" \
2845 "movb %h1,7+%0\n\t" \
2847 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2849 This works great except that the output assembler ends
2850 up looking a bit weird if it turns out that there is
2851 no offset. You end up producing code that looks like:
2864 So here we provide the missing zero. */
2866 *displacement_string_end
= '0';
2871 /* We can have operands of the form
2872 <symbol>@GOTOFF+<nnn>
2873 Take the easy way out here and copy everything
2874 into a temporary buffer... */
2877 cp
= strchr (input_line_pointer
, '@');
2884 /* GOT relocations are not supported in 16 bit mode. */
2885 if (flag_16bit_code
)
2886 as_bad (_("GOT relocations not supported in 16 bit mode"));
2888 if (GOT_symbol
== NULL
)
2889 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2891 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2893 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2896 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2898 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2901 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2903 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2907 as_bad (_("bad reloc specifier in expression"));
2909 /* Replace the relocation token with ' ', so that errors like
2910 foo@GOTOFF1 will be detected. */
2911 first
= cp
- input_line_pointer
;
2912 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2913 memcpy (tmpbuf
, input_line_pointer
, first
);
2914 tmpbuf
[first
] = ' ';
2915 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2916 input_line_pointer
= tmpbuf
;
2921 exp_seg
= expression (exp
);
2923 #ifdef BFD_ASSEMBLER
2924 /* We do this to make sure that the section symbol is in
2925 the symbol table. We will ultimately change the relocation
2926 to be relative to the beginning of the section. */
2927 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2929 if (S_IS_LOCAL(exp
->X_add_symbol
)
2930 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2931 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2932 assert (exp
->X_op
== O_symbol
);
2933 exp
->X_op
= O_subtract
;
2934 exp
->X_op_symbol
= GOT_symbol
;
2935 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2940 if (*input_line_pointer
)
2941 as_bad (_("ignoring junk `%s' after expression"),
2942 input_line_pointer
);
2944 RESTORE_END_STRING (disp_end
+ 1);
2946 RESTORE_END_STRING (disp_end
);
2947 input_line_pointer
= save_input_line_pointer
;
2949 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2951 /* Missing or bad expr becomes absolute 0. */
2952 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2954 exp
->X_op
= O_constant
;
2955 exp
->X_add_number
= 0;
2956 exp
->X_add_symbol
= (symbolS
*) 0;
2957 exp
->X_op_symbol
= (symbolS
*) 0;
2960 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2961 if (exp
->X_op
!= O_constant
2962 #ifdef BFD_ASSEMBLER
2963 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2965 && exp_seg
!= text_section
2966 && exp_seg
!= data_section
2967 && exp_seg
!= bss_section
2968 && exp_seg
!= undefined_section
)
2970 #ifdef BFD_ASSEMBLER
2971 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2973 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2981 static int i386_operand_modifier
PARAMS ((char **, int));
2984 i386_operand_modifier (op_string
, got_a_float
)
2988 if (!strncasecmp (*op_string
, "BYTE PTR", 8))
2990 i
.suffix
= BYTE_MNEM_SUFFIX
;
2995 else if (!strncasecmp (*op_string
, "WORD PTR", 8))
2997 if (got_a_float
== 2) /* "fi..." */
2998 i
.suffix
= SHORT_MNEM_SUFFIX
;
3000 i
.suffix
= WORD_MNEM_SUFFIX
;
3005 else if (!strncasecmp (*op_string
, "DWORD PTR", 9))
3007 if (got_a_float
== 1) /* "f..." */
3008 i
.suffix
= SHORT_MNEM_SUFFIX
;
3010 i
.suffix
= LONG_MNEM_SUFFIX
;
3015 else if (!strncasecmp (*op_string
, "QWORD PTR", 9))
3017 i
.suffix
= DWORD_MNEM_SUFFIX
;
3022 else if (!strncasecmp (*op_string
, "XWORD PTR", 9))
3024 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
3029 /* Compare with space separator to avoid confusing identifier `short_var'
3030 with attribute `short'. */
3031 else if (!strncasecmp (*op_string
, "SHORT ", 6))
3037 else if (!strncasecmp (*op_string
, "OFFSET FLAT:", 12))
3043 /* Compare with space separator to avoid confusing identifier `flat_var'
3044 with attribute `flat'. */
3045 else if (!strncasecmp (*op_string
, "FLAT ", 5))
3051 else return NONE_FOUND
;
3054 static char * build_displacement_string
PARAMS ((int, char *));
3057 build_displacement_string (initial_disp
, op_string
)
3061 char *temp_string
= (char *) malloc (strlen (op_string
) + 1);
3062 char *end_of_operand_string
;
3066 temp_string
[0] = '\0';
3067 tc
= end_of_operand_string
= strchr (op_string
, '[');
3068 if (initial_disp
&& !end_of_operand_string
)
3070 strcpy (temp_string
, op_string
);
3074 /* Build the whole displacement string. */
3077 strncpy (temp_string
, op_string
, end_of_operand_string
- op_string
);
3078 temp_string
[end_of_operand_string
- op_string
] = '\0';
3082 temp_disp
= op_string
;
3084 while (*temp_disp
!= '\0')
3087 int add_minus
= (*temp_disp
== '-');
3089 if (*temp_disp
== '+' || *temp_disp
== '-' || *temp_disp
== '[')
3092 if (is_space_char (*temp_disp
))
3095 /* Don't consider registers. */
3096 if ( !((*temp_disp
== REGISTER_PREFIX
|| allow_naked_reg
)
3097 && parse_register (temp_disp
, &end_op
)) )
3099 char *string_start
= temp_disp
;
3101 while (*temp_disp
!= ']'
3102 && *temp_disp
!= '+'
3103 && *temp_disp
!= '-'
3104 && *temp_disp
!= '*')
3108 strcat (temp_string
, "-");
3110 strcat (temp_string
, "+");
3112 strncat (temp_string
, string_start
, temp_disp
- string_start
);
3113 if (*temp_disp
== '+' || *temp_disp
== '-')
3117 while (*temp_disp
!= '\0'
3118 && *temp_disp
!= '+'
3119 && *temp_disp
!= '-')
3126 static int i386_parse_seg
PARAMS ((char *));
3129 i386_parse_seg (op_string
)
3132 if (is_space_char (*op_string
))
3135 /* Should be one of es, cs, ss, ds fs or gs. */
3136 switch (*op_string
++)
3139 i
.seg
[i
.mem_operands
] = &es
;
3142 i
.seg
[i
.mem_operands
] = &cs
;
3145 i
.seg
[i
.mem_operands
] = &ss
;
3148 i
.seg
[i
.mem_operands
] = &ds
;
3151 i
.seg
[i
.mem_operands
] = &fs
;
3154 i
.seg
[i
.mem_operands
] = &gs
;
3157 as_bad (_("bad segment name `%s'"), op_string
);
3161 if (*op_string
++ != 's')
3163 as_bad (_("bad segment name `%s'"), op_string
);
3167 if (is_space_char (*op_string
))
3170 if (*op_string
!= ':')
3172 as_bad (_("bad segment name `%s'"), op_string
);
3180 static int i386_index_check
PARAMS((const char *));
3182 /* Make sure the memory operand we've been dealt is valid.
3183 Return 1 on success, 0 on a failure. */
3186 i386_index_check (operand_string
)
3187 const char *operand_string
;
3189 #if INFER_ADDR_PREFIX
3194 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3195 /* 16 bit mode checks. */
3197 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3198 != (Reg16
|BaseIndex
)))
3200 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3201 != (Reg16
|BaseIndex
))
3203 && i
.base_reg
->reg_num
< 6
3204 && i
.index_reg
->reg_num
>= 6
3205 && i
.log2_scale_factor
== 0))))
3206 /* 32 bit mode checks. */
3208 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3210 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3211 != (Reg32
|BaseIndex
)))))
3213 #if INFER_ADDR_PREFIX
3214 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3216 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3218 /* Change the size of any displacement too. At most one of
3219 Disp16 or Disp32 is set.
3220 FIXME. There doesn't seem to be any real need for separate
3221 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3222 Removing them would probably clean up the code quite a lot. */
3223 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3224 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3229 as_bad (_("`%s' is not a valid base/index expression"),
3233 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3235 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3241 static int i386_intel_memory_operand
PARAMS ((char *));
3244 i386_intel_memory_operand (operand_string
)
3245 char *operand_string
;
3247 char *op_string
= operand_string
;
3248 char *end_of_operand_string
;
3250 if ((i
.mem_operands
== 1
3251 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3252 || i
.mem_operands
== 2)
3254 as_bad (_("too many memory references for `%s'"),
3255 current_templates
->start
->name
);
3259 /* First check for a segment override. */
3260 if (*op_string
!= '[')
3264 end_seg
= strchr (op_string
, ':');
3267 if (!i386_parse_seg (op_string
))
3269 op_string
= end_seg
+ 1;
3273 /* Look for displacement preceding open bracket. */
3274 if (*op_string
!= '[')
3278 if (i
.disp_operands
)
3281 temp_string
= build_displacement_string (true, op_string
);
3283 if (!i386_displacement (temp_string
, temp_string
+ strlen (temp_string
)))
3290 end_of_operand_string
= strchr (op_string
, '[');
3291 if (!end_of_operand_string
)
3292 end_of_operand_string
= op_string
+ strlen (op_string
);
3294 if (is_space_char (*end_of_operand_string
))
3295 --end_of_operand_string
;
3297 op_string
= end_of_operand_string
;
3300 if (*op_string
== '[')
3304 /* Pick off each component and figure out where it belongs. */
3306 end_of_operand_string
= op_string
;
3308 while (*op_string
!= ']')
3310 const reg_entry
*temp_reg
;
3314 while (*end_of_operand_string
!= '+'
3315 && *end_of_operand_string
!= '-'
3316 && *end_of_operand_string
!= '*'
3317 && *end_of_operand_string
!= ']')
3318 end_of_operand_string
++;
3320 temp_string
= op_string
;
3321 if (*temp_string
== '+')
3324 if (is_space_char (*temp_string
))
3328 if ((*temp_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3329 && (temp_reg
= parse_register (temp_string
, &end_op
)) != NULL
)
3331 if (i
.base_reg
== NULL
)
3332 i
.base_reg
= temp_reg
;
3334 i
.index_reg
= temp_reg
;
3336 i
.types
[this_operand
] |= BaseIndex
;
3338 else if (*temp_string
== REGISTER_PREFIX
)
3340 as_bad (_("bad register name `%s'"), temp_string
);
3343 else if (is_digit_char (*op_string
)
3344 || *op_string
== '+' || *op_string
== '-')
3348 if (i
.disp_operands
!= 0)
3351 temp_string
= build_displacement_string (false, op_string
);
3353 temp_str
= temp_string
;
3354 if (*temp_str
== '+')
3357 if (!i386_displacement (temp_str
, temp_str
+ strlen (temp_str
)))
3365 end_of_operand_string
= op_string
;
3366 while (*end_of_operand_string
!= ']'
3367 && *end_of_operand_string
!= '+'
3368 && *end_of_operand_string
!= '-'
3369 && *end_of_operand_string
!= '*')
3370 ++end_of_operand_string
;
3372 else if (*op_string
== '*')
3376 if (i
.base_reg
&& !i
.index_reg
)
3378 i
.index_reg
= i
.base_reg
;
3382 if (!i386_scale (op_string
))
3385 op_string
= end_of_operand_string
;
3386 ++end_of_operand_string
;
3390 if (i386_index_check (operand_string
) == 0)
3398 i386_intel_operand (operand_string
, got_a_float
)
3399 char *operand_string
;
3404 char *op_string
= operand_string
;
3406 int operand_modifier
= i386_operand_modifier (&op_string
, got_a_float
);
3407 if (is_space_char (*op_string
))
3410 switch (operand_modifier
)
3417 if (!i386_intel_memory_operand (op_string
))
3423 if (!i386_immediate (op_string
))
3429 /* Should be register or immediate. */
3430 if (is_digit_char (*op_string
)
3431 && strchr (op_string
, '[') == 0)
3433 if (!i386_immediate (op_string
))
3436 else if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3437 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3439 /* Check for a segment override by searching for ':' after a
3440 segment register. */
3442 if (is_space_char (*op_string
))
3444 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3449 i
.seg
[i
.mem_operands
] = &es
;
3452 i
.seg
[i
.mem_operands
] = &cs
;
3455 i
.seg
[i
.mem_operands
] = &ss
;
3458 i
.seg
[i
.mem_operands
] = &ds
;
3461 i
.seg
[i
.mem_operands
] = &fs
;
3464 i
.seg
[i
.mem_operands
] = &gs
;
3469 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3470 i
.op
[this_operand
].regs
= r
;
3473 else if (*op_string
== REGISTER_PREFIX
)
3475 as_bad (_("bad register name `%s'"), op_string
);
3478 else if (!i386_intel_memory_operand (op_string
))
3487 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3491 i386_operand (operand_string
)
3492 char *operand_string
;
3496 char *op_string
= operand_string
;
3498 if (is_space_char (*op_string
))
3501 /* We check for an absolute prefix (differentiating,
3502 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3503 if (*op_string
== ABSOLUTE_PREFIX
)
3506 if (is_space_char (*op_string
))
3508 i
.types
[this_operand
] |= JumpAbsolute
;
3511 /* Check if operand is a register. */
3512 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3513 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3515 /* Check for a segment override by searching for ':' after a
3516 segment register. */
3518 if (is_space_char (*op_string
))
3520 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3525 i
.seg
[i
.mem_operands
] = &es
;
3528 i
.seg
[i
.mem_operands
] = &cs
;
3531 i
.seg
[i
.mem_operands
] = &ss
;
3534 i
.seg
[i
.mem_operands
] = &ds
;
3537 i
.seg
[i
.mem_operands
] = &fs
;
3540 i
.seg
[i
.mem_operands
] = &gs
;
3544 /* Skip the ':' and whitespace. */
3546 if (is_space_char (*op_string
))
3549 if (!is_digit_char (*op_string
)
3550 && !is_identifier_char (*op_string
)
3551 && *op_string
!= '('
3552 && *op_string
!= ABSOLUTE_PREFIX
)
3554 as_bad (_("bad memory operand `%s'"), op_string
);
3557 /* Handle case of %es:*foo. */
3558 if (*op_string
== ABSOLUTE_PREFIX
)
3561 if (is_space_char (*op_string
))
3563 i
.types
[this_operand
] |= JumpAbsolute
;
3565 goto do_memory_reference
;
3569 as_bad (_("junk `%s' after register"), op_string
);
3572 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3573 i
.op
[this_operand
].regs
= r
;
3576 else if (*op_string
== REGISTER_PREFIX
)
3578 as_bad (_("bad register name `%s'"), op_string
);
3581 else if (*op_string
== IMMEDIATE_PREFIX
)
3584 if (i
.types
[this_operand
] & JumpAbsolute
)
3586 as_bad (_("immediate operand illegal with absolute jump"));
3589 if (!i386_immediate (op_string
))
3592 else if (is_digit_char (*op_string
)
3593 || is_identifier_char (*op_string
)
3594 || *op_string
== '(' )
3596 /* This is a memory reference of some sort. */
3599 /* Start and end of displacement string expression (if found). */
3600 char *displacement_string_start
;
3601 char *displacement_string_end
;
3603 do_memory_reference
:
3604 if ((i
.mem_operands
== 1
3605 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3606 || i
.mem_operands
== 2)
3608 as_bad (_("too many memory references for `%s'"),
3609 current_templates
->start
->name
);
3613 /* Check for base index form. We detect the base index form by
3614 looking for an ')' at the end of the operand, searching
3615 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3617 base_string
= op_string
+ strlen (op_string
);
3620 if (is_space_char (*base_string
))
3623 /* If we only have a displacement, set-up for it to be parsed later. */
3624 displacement_string_start
= op_string
;
3625 displacement_string_end
= base_string
+ 1;
3627 if (*base_string
== ')')
3630 unsigned int parens_balanced
= 1;
3631 /* We've already checked that the number of left & right ()'s are
3632 equal, so this loop will not be infinite. */
3636 if (*base_string
== ')')
3638 if (*base_string
== '(')
3641 while (parens_balanced
);
3643 temp_string
= base_string
;
3645 /* Skip past '(' and whitespace. */
3647 if (is_space_char (*base_string
))
3650 if (*base_string
== ','
3651 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3652 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3654 displacement_string_end
= temp_string
;
3656 i
.types
[this_operand
] |= BaseIndex
;
3660 base_string
= end_op
;
3661 if (is_space_char (*base_string
))
3665 /* There may be an index reg or scale factor here. */
3666 if (*base_string
== ',')
3669 if (is_space_char (*base_string
))
3672 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3673 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3675 base_string
= end_op
;
3676 if (is_space_char (*base_string
))
3678 if (*base_string
== ',')
3681 if (is_space_char (*base_string
))
3684 else if (*base_string
!= ')' )
3686 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3691 else if (*base_string
== REGISTER_PREFIX
)
3693 as_bad (_("bad register name `%s'"), base_string
);
3697 /* Check for scale factor. */
3698 if (isdigit ((unsigned char) *base_string
))
3700 if (!i386_scale (base_string
))
3704 if (is_space_char (*base_string
))
3706 if (*base_string
!= ')')
3708 as_bad (_("expecting `)' after scale factor in `%s'"),
3713 else if (!i
.index_reg
)
3715 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3720 else if (*base_string
!= ')')
3722 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3727 else if (*base_string
== REGISTER_PREFIX
)
3729 as_bad (_("bad register name `%s'"), base_string
);
3734 /* If there's an expression beginning the operand, parse it,
3735 assuming displacement_string_start and
3736 displacement_string_end are meaningful. */
3737 if (displacement_string_start
!= displacement_string_end
)
3739 if (!i386_displacement (displacement_string_start
,
3740 displacement_string_end
))
3744 /* Special case for (%dx) while doing input/output op. */
3746 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3748 && i
.log2_scale_factor
== 0
3749 && i
.seg
[i
.mem_operands
] == 0
3750 && (i
.types
[this_operand
] & Disp
) == 0)
3752 i
.types
[this_operand
] = InOutPortReg
;
3756 if (i386_index_check (operand_string
) == 0)
3762 /* It's not a memory operand; argh! */
3763 as_bad (_("invalid char %s beginning operand %d `%s'"),
3764 output_invalid (*op_string
),
3769 return 1; /* Normal return. */
3772 /* md_estimate_size_before_relax()
3774 Called just before relax() for rs_machine_dependent frags. The x86
3775 assembler uses these frags to handle variable size jump
3778 Any symbol that is now undefined will not become defined.
3779 Return the correct fr_subtype in the frag.
3780 Return the initial "guess for variable size of frag" to caller.
3781 The guess is actually the growth beyond the fixed part. Whatever
3782 we do to grow the fixed or variable part contributes to our
3786 md_estimate_size_before_relax (fragP
, segment
)
3787 register fragS
*fragP
;
3788 register segT segment
;
3790 /* We've already got fragP->fr_subtype right; all we have to do is
3791 check for un-relaxable symbols. On an ELF system, we can't relax
3792 an externally visible symbol, because it may be overridden by a
3794 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3795 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3796 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3797 || S_IS_WEAK (fragP
->fr_symbol
)
3801 /* Symbol is undefined in this segment, or we need to keep a
3802 reloc so that weak symbols can be overridden. */
3803 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3804 #ifdef BFD_ASSEMBLER
3805 enum bfd_reloc_code_real reloc_type
;
3809 unsigned char *opcode
;
3812 if (fragP
->fr_var
!= NO_RELOC
)
3813 reloc_type
= fragP
->fr_var
;
3815 reloc_type
= BFD_RELOC_16_PCREL
;
3817 reloc_type
= BFD_RELOC_32_PCREL
;
3819 old_fr_fix
= fragP
->fr_fix
;
3820 opcode
= (unsigned char *) fragP
->fr_opcode
;
3824 case JUMP_PC_RELATIVE
:
3825 /* Make jmp (0xeb) a dword displacement jump. */
3827 fragP
->fr_fix
+= size
;
3828 fix_new (fragP
, old_fr_fix
, size
,
3830 fragP
->fr_offset
, 1,
3835 /* This changes the byte-displacement jump 0x7N
3836 to the dword-displacement jump 0x0f,0x8N. */
3837 opcode
[1] = opcode
[0] + 0x10;
3838 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3839 /* We've added an opcode byte. */
3840 fragP
->fr_fix
+= 1 + size
;
3841 fix_new (fragP
, old_fr_fix
+ 1, size
,
3843 fragP
->fr_offset
, 1,
3848 return fragP
->fr_fix
- old_fr_fix
;
3850 /* Guess a short jump. */
3854 /* Called after relax() is finished.
3856 In: Address of frag.
3857 fr_type == rs_machine_dependent.
3858 fr_subtype is what the address relaxed to.
3860 Out: Any fixSs and constants are set up.
3861 Caller will turn frag into a ".space 0". */
3863 #ifndef BFD_ASSEMBLER
3865 md_convert_frag (headers
, sec
, fragP
)
3866 object_headers
*headers ATTRIBUTE_UNUSED
;
3867 segT sec ATTRIBUTE_UNUSED
;
3868 register fragS
*fragP
;
3871 md_convert_frag (abfd
, sec
, fragP
)
3872 bfd
*abfd ATTRIBUTE_UNUSED
;
3873 segT sec ATTRIBUTE_UNUSED
;
3874 register fragS
*fragP
;
3877 register unsigned char *opcode
;
3878 unsigned char *where_to_put_displacement
= NULL
;
3879 offsetT target_address
;
3880 offsetT opcode_address
;
3881 unsigned int extension
= 0;
3882 offsetT displacement_from_opcode_start
;
3884 opcode
= (unsigned char *) fragP
->fr_opcode
;
3886 /* Address we want to reach in file space. */
3887 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3888 #ifdef BFD_ASSEMBLER
3889 /* Not needed otherwise? */
3890 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3893 /* Address opcode resides at in file space. */
3894 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3896 /* Displacement from opcode start to fill into instruction. */
3897 displacement_from_opcode_start
= target_address
- opcode_address
;
3899 switch (fragP
->fr_subtype
)
3901 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3902 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3903 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3904 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3905 /* Don't have to change opcode. */
3906 extension
= 1; /* 1 opcode + 1 displacement */
3907 where_to_put_displacement
= &opcode
[1];
3910 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3911 extension
= 5; /* 2 opcode + 4 displacement */
3912 opcode
[1] = opcode
[0] + 0x10;
3913 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3914 where_to_put_displacement
= &opcode
[2];
3917 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3918 extension
= 4; /* 1 opcode + 4 displacement */
3920 where_to_put_displacement
= &opcode
[1];
3923 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3924 extension
= 3; /* 2 opcode + 2 displacement */
3925 opcode
[1] = opcode
[0] + 0x10;
3926 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3927 where_to_put_displacement
= &opcode
[2];
3930 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3931 extension
= 2; /* 1 opcode + 2 displacement */
3933 where_to_put_displacement
= &opcode
[1];
3937 BAD_CASE (fragP
->fr_subtype
);
3940 /* Now put displacement after opcode. */
3941 md_number_to_chars ((char *) where_to_put_displacement
,
3942 (valueT
) (displacement_from_opcode_start
- extension
),
3943 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3944 fragP
->fr_fix
+= extension
;
3947 /* Size of byte displacement jmp. */
3948 int md_short_jump_size
= 2;
3950 /* Size of dword displacement jmp. */
3951 int md_long_jump_size
= 5;
3953 /* Size of relocation record. */
3954 const int md_reloc_size
= 8;
3957 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3959 addressT from_addr
, to_addr
;
3960 fragS
*frag ATTRIBUTE_UNUSED
;
3961 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3965 offset
= to_addr
- (from_addr
+ 2);
3966 /* Opcode for byte-disp jump. */
3967 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3968 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3972 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3974 addressT from_addr
, to_addr
;
3975 fragS
*frag ATTRIBUTE_UNUSED
;
3976 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3980 offset
= to_addr
- (from_addr
+ 5);
3981 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3982 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3985 /* Apply a fixup (fixS) to segment data, once it has been determined
3986 by our caller that we have all the info we need to fix it up.
3988 On the 386, immediates, displacements, and data pointers are all in
3989 the same (little-endian) format, so we don't need to care about which
3993 md_apply_fix3 (fixP
, valp
, seg
)
3994 /* The fix we're to put in. */
3997 /* Pointer to the value of the bits. */
4000 /* Segment fix is from. */
4001 segT seg ATTRIBUTE_UNUSED
;
4003 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4004 valueT value
= *valp
;
4006 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4009 switch (fixP
->fx_r_type
)
4015 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4018 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4021 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4026 /* This is a hack. There should be a better way to handle this.
4027 This covers for the fact that bfd_install_relocation will
4028 subtract the current location (for partial_inplace, PC relative
4029 relocations); see more below. */
4030 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4031 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4032 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4036 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4038 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4041 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4044 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4046 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4049 || (symbol_section_p (fixP
->fx_addsy
)
4050 && fseg
!= absolute_section
))
4051 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4052 && ! S_IS_WEAK (fixP
->fx_addsy
)
4053 && S_IS_DEFINED (fixP
->fx_addsy
)
4054 && ! S_IS_COMMON (fixP
->fx_addsy
))
4056 /* Yes, we add the values in twice. This is because
4057 bfd_perform_relocation subtracts them out again. I think
4058 bfd_perform_relocation is broken, but I don't dare change
4060 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4064 #if defined (OBJ_COFF) && defined (TE_PE)
4065 /* For some reason, the PE format does not store a section
4066 address offset for a PC relative symbol. */
4067 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4068 value
+= md_pcrel_from (fixP
);
4072 /* Fix a few things - the dynamic linker expects certain values here,
4073 and we must not dissappoint it. */
4074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4075 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4077 switch (fixP
->fx_r_type
)
4079 case BFD_RELOC_386_PLT32
:
4080 /* Make the jump instruction point to the address of the operand. At
4081 runtime we merely add the offset to the actual PLT entry. */
4084 case BFD_RELOC_386_GOTPC
:
4086 /* This is tough to explain. We end up with this one if we have
4087 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4088 * here is to obtain the absolute address of the GOT, and it is strongly
4089 * preferable from a performance point of view to avoid using a runtime
4090 * relocation for this. The actual sequence of instructions often look
4096 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4098 * The call and pop essentially return the absolute address of
4099 * the label .L66 and store it in %ebx. The linker itself will
4100 * ultimately change the first operand of the addl so that %ebx points to
4101 * the GOT, but to keep things simple, the .o file must have this operand
4102 * set so that it generates not the absolute address of .L66, but the
4103 * absolute address of itself. This allows the linker itself simply
4104 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4105 * added in, and the addend of the relocation is stored in the operand
4106 * field for the instruction itself.
4108 * Our job here is to fix the operand so that it would add the correct
4109 * offset so that %ebx would point to itself. The thing that is tricky is
4110 * that .-.L66 will point to the beginning of the instruction, so we need
4111 * to further modify the operand so that it will point to itself.
4112 * There are other cases where you have something like:
4114 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4116 * and here no correction would be required. Internally in the assembler
4117 * we treat operands of this form as not being pcrel since the '.' is
4118 * explicitly mentioned, and I wonder whether it would simplify matters
4119 * to do it this way. Who knows. In earlier versions of the PIC patches,
4120 * the pcrel_adjust field was used to store the correction, but since the
4121 * expression is not pcrel, I felt it would be confusing to do it this
4126 case BFD_RELOC_386_GOT32
:
4127 value
= 0; /* Fully resolved at runtime. No addend. */
4129 case BFD_RELOC_386_GOTOFF
:
4132 case BFD_RELOC_VTABLE_INHERIT
:
4133 case BFD_RELOC_VTABLE_ENTRY
:
4140 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4142 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4143 md_number_to_chars (p
, value
, fixP
->fx_size
);
4148 #define MAX_LITTLENUMS 6
4150 /* Turn the string pointed to by litP into a floating point constant
4151 of type TYPE, and emit the appropriate bytes. The number of
4152 LITTLENUMS emitted is stored in *SIZEP. An error message is
4153 returned, or NULL on OK. */
4156 md_atof (type
, litP
, sizeP
)
4162 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4163 LITTLENUM_TYPE
*wordP
;
4185 return _("Bad call to md_atof ()");
4187 t
= atof_ieee (input_line_pointer
, type
, words
);
4189 input_line_pointer
= t
;
4191 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4192 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4193 the bigendian 386. */
4194 for (wordP
= words
+ prec
- 1; prec
--;)
4196 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4197 litP
+= sizeof (LITTLENUM_TYPE
);
4202 char output_invalid_buf
[8];
4209 sprintf (output_invalid_buf
, "'%c'", c
);
4211 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4212 return output_invalid_buf
;
4215 /* REG_STRING starts *before* REGISTER_PREFIX. */
4217 static const reg_entry
*
4218 parse_register (reg_string
, end_op
)
4222 char *s
= reg_string
;
4224 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4227 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4228 if (*s
== REGISTER_PREFIX
)
4231 if (is_space_char (*s
))
4235 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4237 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4238 return (const reg_entry
*) NULL
;
4242 /* For naked regs, make sure that we are not dealing with an identifier.
4243 This prevents confusing an identifier like `eax_var' with register
4245 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4246 return (const reg_entry
*) NULL
;
4250 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4252 /* Handle floating point regs, allowing spaces in the (i) part. */
4253 if (r
== i386_regtab
/* %st is first entry of table */)
4255 if (is_space_char (*s
))
4260 if (is_space_char (*s
))
4262 if (*s
>= '0' && *s
<= '7')
4264 r
= &i386_float_regtab
[*s
- '0'];
4266 if (is_space_char (*s
))
4274 /* We have "%st(" then garbage. */
4275 return (const reg_entry
*) NULL
;
4282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4283 const char *md_shortopts
= "kVQ:sq";
4285 const char *md_shortopts
= "q";
4287 struct option md_longopts
[] = {
4288 {NULL
, no_argument
, NULL
, 0}
4290 size_t md_longopts_size
= sizeof (md_longopts
);
4293 md_parse_option (c
, arg
)
4295 char *arg ATTRIBUTE_UNUSED
;
4303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4304 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4305 should be emitted or not. FIXME: Not implemented. */
4309 /* -V: SVR4 argument to print version ID. */
4311 print_version_id ();
4314 /* -k: Ignore for FreeBSD compatibility. */
4319 /* -s: On i386 Solaris, this tells the native assembler to use
4320 .stab instead of .stab.excl. We always use .stab anyhow. */
4331 md_show_usage (stream
)
4334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4335 fprintf (stream
, _("\
4337 -V print assembler version number\n\
4339 -q quieten some warnings\n\
4342 fprintf (stream
, _("\
4343 -q quieten some warnings\n"));
4347 #ifdef BFD_ASSEMBLER
4348 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4349 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4350 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4352 /* Pick the target format to use. */
4355 i386_target_format ()
4357 switch (OUTPUT_FLAVOR
)
4359 #ifdef OBJ_MAYBE_AOUT
4360 case bfd_target_aout_flavour
:
4361 return AOUT_TARGET_FORMAT
;
4363 #ifdef OBJ_MAYBE_COFF
4364 case bfd_target_coff_flavour
:
4367 #ifdef OBJ_MAYBE_ELF
4368 case bfd_target_elf_flavour
:
4369 return "elf32-i386";
4377 #endif /* OBJ_MAYBE_ more than one */
4378 #endif /* BFD_ASSEMBLER */
4381 md_undefined_symbol (name
)
4384 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4385 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4386 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4387 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4391 if (symbol_find (name
))
4392 as_bad (_("GOT already in symbol table"));
4393 GOT_symbol
= symbol_new (name
, undefined_section
,
4394 (valueT
) 0, &zero_address_frag
);
4401 /* Round up a section size to the appropriate boundary. */
4404 md_section_align (segment
, size
)
4405 segT segment ATTRIBUTE_UNUSED
;
4408 #ifdef BFD_ASSEMBLER
4409 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4410 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4412 /* For a.out, force the section size to be aligned. If we don't do
4413 this, BFD will align it for us, but it will not write out the
4414 final bytes of the section. This may be a bug in BFD, but it is
4415 easier to fix it here since that is how the other a.out targets
4419 align
= bfd_get_section_alignment (stdoutput
, segment
);
4420 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4428 /* On the i386, PC-relative offsets are relative to the start of the
4429 next instruction. That is, the address of the offset, plus its
4430 size, since the offset is always the last part of the insn. */
4433 md_pcrel_from (fixP
)
4436 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4443 int ignore ATTRIBUTE_UNUSED
;
4447 temp
= get_absolute_expression ();
4448 subseg_set (bss_section
, (subsegT
) temp
);
4449 demand_empty_rest_of_line ();
4454 #ifdef BFD_ASSEMBLER
4457 i386_validate_fix (fixp
)
4460 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4462 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4468 tc_gen_reloc (section
, fixp
)
4469 asection
*section ATTRIBUTE_UNUSED
;
4473 bfd_reloc_code_real_type code
;
4475 switch (fixp
->fx_r_type
)
4477 case BFD_RELOC_386_PLT32
:
4478 case BFD_RELOC_386_GOT32
:
4479 case BFD_RELOC_386_GOTOFF
:
4480 case BFD_RELOC_386_GOTPC
:
4482 case BFD_RELOC_VTABLE_ENTRY
:
4483 case BFD_RELOC_VTABLE_INHERIT
:
4484 code
= fixp
->fx_r_type
;
4489 switch (fixp
->fx_size
)
4492 as_bad (_("can not do %d byte pc-relative relocation"),
4494 code
= BFD_RELOC_32_PCREL
;
4496 case 1: code
= BFD_RELOC_8_PCREL
; break;
4497 case 2: code
= BFD_RELOC_16_PCREL
; break;
4498 case 4: code
= BFD_RELOC_32_PCREL
; break;
4503 switch (fixp
->fx_size
)
4506 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4507 code
= BFD_RELOC_32
;
4509 case 1: code
= BFD_RELOC_8
; break;
4510 case 2: code
= BFD_RELOC_16
; break;
4511 case 4: code
= BFD_RELOC_32
; break;
4517 if (code
== BFD_RELOC_32
4519 && fixp
->fx_addsy
== GOT_symbol
)
4520 code
= BFD_RELOC_386_GOTPC
;
4522 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4523 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4524 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4526 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4527 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4528 vtable entry to be used in the relocation's section offset. */
4529 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4530 rel
->address
= fixp
->fx_offset
;
4533 rel
->addend
= fixp
->fx_addnumber
;
4537 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4538 if (rel
->howto
== NULL
)
4540 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4541 _("cannot represent relocation type %s"),
4542 bfd_get_reloc_code_name (code
));
4543 /* Set howto to a garbage value so that we can keep going. */
4544 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4545 assert (rel
->howto
!= NULL
);
4551 #else /* ! BFD_ASSEMBLER */
4553 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4555 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4558 relax_addressT segment_address_in_file
;
4560 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4561 Out: GNU LD relocation length code: 0, 1, or 2. */
4563 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4566 know (fixP
->fx_addsy
!= NULL
);
4568 md_number_to_chars (where
,
4569 (valueT
) (fixP
->fx_frag
->fr_address
4570 + fixP
->fx_where
- segment_address_in_file
),
4573 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4574 ? S_GET_TYPE (fixP
->fx_addsy
)
4575 : fixP
->fx_addsy
->sy_number
);
4577 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4578 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4579 where
[4] = r_symbolnum
& 0x0ff;
4580 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4581 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4582 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4585 #endif /* OBJ_AOUT or OBJ_BOUT. */
4587 #if defined (I386COFF)
4590 tc_coff_fix2rtype (fixP
)
4593 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4596 return (fixP
->fx_pcrel
?
4597 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4598 fixP
->fx_size
== 2 ? R_PCRWORD
:
4600 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4601 fixP
->fx_size
== 2 ? R_RELWORD
:
4606 tc_coff_sizemachdep (frag
)
4610 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4615 #endif /* I386COFF */
4617 #endif /* ! BFD_ASSEMBLER */