1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
847 CPU_ZNVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
849 CPU_BTVER1_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
851 CPU_BTVER2_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
869 CPU_SSSE3_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_1_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512F_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512CD_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512ER_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512PF_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512DQ_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512BW_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512VL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
897 CPU_VMFUNC_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVE_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEOPT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEC_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVES_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
915 CPU_FSGSBASE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
917 CPU_RDRND_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
931 CPU_MOVBE_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
937 CPU_LZCNT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
943 CPU_INVPCID_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSH_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
949 CPU_SYSCALL_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
951 CPU_RDTSCP_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOW_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOWA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
957 CPU_PADLOCK_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
963 CPU_SSE4A_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
973 CPU_RDSEED_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
975 CPU_PRFCHW_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
983 CPU_CLFLUSHOPT_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
985 CPU_PREFETCHWT1_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512IFMA_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512VBMI_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4FMAPS_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4VNNIW_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VBMI2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VNNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_BITALG_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1007 CPU_CLZERO_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1009 CPU_MWAITX_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1011 CPU_OSPKE_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1013 CPU_RDPID_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1015 CPU_PTWRITE_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1019 CPU_SHSTK_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1021 CPU_GFNI_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1023 CPU_VAES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1025 CPU_VPCLMULQDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1027 CPU_WBNOINVD_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1029 CPU_PCONFIG_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1031 CPU_WAITPKG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1033 CPU_CLDEMOTE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1035 CPU_MOVDIRI_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIR64B_FLAGS
, 0 },
1040 static const noarch_entry cpu_noarch
[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1089 && *input_line_pointer
== ',')
1091 align
= parse_align (needs_align
- 1);
1093 if (align
== (addressT
) -1)
1108 bss_alloc (symbolP
, size
, align
);
1113 pe_lcomm (int needs_align
)
1115 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1119 const pseudo_typeS md_pseudo_table
[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes
, 0},
1124 {"align", s_align_ptwo
, 0},
1126 {"arch", set_cpu_arch
, 0},
1130 {"lcomm", pe_lcomm
, 1},
1132 {"ffloat", float_cons
, 'f'},
1133 {"dfloat", float_cons
, 'd'},
1134 {"tfloat", float_cons
, 'x'},
1136 {"slong", signed_cons
, 4},
1137 {"noopt", s_ignore
, 0},
1138 {"optim", s_ignore
, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1140 {"code16", set_code_flag
, CODE_16BIT
},
1141 {"code32", set_code_flag
, CODE_32BIT
},
1143 {"code64", set_code_flag
, CODE_64BIT
},
1145 {"intel_syntax", set_intel_syntax
, 1},
1146 {"att_syntax", set_intel_syntax
, 0},
1147 {"intel_mnemonic", set_intel_mnemonic
, 1},
1148 {"att_mnemonic", set_intel_mnemonic
, 0},
1149 {"allow_index_reg", set_allow_index_reg
, 1},
1150 {"disallow_index_reg", set_allow_index_reg
, 0},
1151 {"sse_check", set_check
, 0},
1152 {"operand_check", set_check
, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common
, 0},
1156 {"file", dwarf2_directive_file
, 0},
1157 {"loc", dwarf2_directive_loc
, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1161 {"secrel32", pe_directive_secrel
, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer
;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control
*op_hash
;
1172 /* Hash table for register lookup. */
1173 static struct hash_control
*reg_hash
;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1
[] =
1180 static const unsigned char f32_2
[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3
[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4
[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6
[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7
[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3
[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4
[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8
[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32
[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32
[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt
[] = {
1202 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt
[] = {
1206 f32_1
, f32_2
, f16_3
, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3
[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4
[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5
[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6
[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7
[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8
[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9
[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10
[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11
[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1238 alt_9
, alt_10
, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where
, const unsigned char *const *patt
,
1246 int count
, int max_single_nop_size
)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size
--;
1258 nops
= patt
[max_single_nop_size
- 1];
1261 last
= count
% max_single_nop_size
;
1264 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1265 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1269 nops
= patt
[last
- 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops
= patt
[last
- 1];
1276 memcpy (where
+ offset
, nops
, last
);
1277 where
[offset
+ last
] = *patt
[0];
1280 memcpy (where
+ offset
, nops
, last
);
1285 fits_in_imm7 (offsetT num
)
1287 return (num
& 0x7f) == num
;
1291 fits_in_imm31 (offsetT num
)
1293 return (num
& 0x7fffffff) == num
;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1302 const unsigned char *const *patt
= NULL
;
1303 int max_single_nop_size
;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops
;
1307 switch (fragP
->fr_type
)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code
== CODE_16BIT
)
1333 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops
= 2;
1339 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune
)
1344 case PROCESSOR_UNKNOWN
:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1352 case PROCESSOR_PENTIUM4
:
1353 case PROCESSOR_NOCONA
:
1354 case PROCESSOR_CORE
:
1355 case PROCESSOR_CORE2
:
1356 case PROCESSOR_COREI7
:
1357 case PROCESSOR_L1OM
:
1358 case PROCESSOR_K1OM
:
1359 case PROCESSOR_GENERIC64
:
1361 case PROCESSOR_ATHLON
:
1363 case PROCESSOR_AMDFAM10
:
1365 case PROCESSOR_ZNVER
:
1369 case PROCESSOR_I386
:
1370 case PROCESSOR_I486
:
1371 case PROCESSOR_PENTIUM
:
1372 case PROCESSOR_PENTIUMPRO
:
1373 case PROCESSOR_IAMCU
:
1374 case PROCESSOR_GENERIC32
:
1381 switch (fragP
->tc_frag_data
.tune
)
1383 case PROCESSOR_UNKNOWN
:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386
:
1390 case PROCESSOR_I486
:
1391 case PROCESSOR_PENTIUM
:
1392 case PROCESSOR_IAMCU
:
1394 case PROCESSOR_ATHLON
:
1396 case PROCESSOR_AMDFAM10
:
1398 case PROCESSOR_ZNVER
:
1400 case PROCESSOR_GENERIC32
:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_PENTIUM4
:
1410 case PROCESSOR_NOCONA
:
1411 case PROCESSOR_CORE
:
1412 case PROCESSOR_CORE2
:
1413 case PROCESSOR_COREI7
:
1414 case PROCESSOR_L1OM
:
1415 case PROCESSOR_K1OM
:
1416 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1421 case PROCESSOR_GENERIC64
:
1427 if (patt
== f32_patt
)
1429 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops
= 2;
1435 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops
= 7;
1442 limit
= max_single_nop_size
;
1444 if (fragP
->fr_type
== rs_fill_nop
)
1446 /* Output NOPs for .nop directive. */
1447 if (limit
> max_single_nop_size
)
1449 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit
, max_single_nop_size
);
1457 fragP
->fr_var
= count
;
1459 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1461 /* Generate jump over NOPs. */
1462 offsetT disp
= count
- 2;
1463 if (fits_in_imm7 (disp
))
1465 /* Use "jmp disp8" if possible. */
1467 where
[0] = jump_disp8
[0];
1473 unsigned int size_of_jump
;
1475 if (flag_code
== CODE_16BIT
)
1477 where
[0] = jump16_disp32
[0];
1478 where
[1] = jump16_disp32
[1];
1483 where
[0] = jump32_disp32
[0];
1487 count
-= size_of_jump
+ 4;
1488 if (!fits_in_imm31 (count
))
1490 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1496 where
+= size_of_jump
+ 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where
, patt
, count
, limit
);
1505 operand_type_all_zero (const union i386_operand_type
*x
)
1507 switch (ARRAY_SIZE(x
->array
))
1518 return !x
->array
[0];
1525 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1527 switch (ARRAY_SIZE(x
->array
))
1545 operand_type_equal (const union i386_operand_type
*x
,
1546 const union i386_operand_type
*y
)
1548 switch (ARRAY_SIZE(x
->array
))
1551 if (x
->array
[2] != y
->array
[2])
1555 if (x
->array
[1] != y
->array
[1])
1559 return x
->array
[0] == y
->array
[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1584 return !x
->array
[0];
1591 cpu_flags_equal (const union i386_cpu_flags
*x
,
1592 const union i386_cpu_flags
*y
)
1594 switch (ARRAY_SIZE(x
->array
))
1597 if (x
->array
[3] != y
->array
[3])
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1619 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1620 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[3] &= y
.array
[3];
1632 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1638 x
.array
[0] &= y
.array
[0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[3] |= y
.array
[3];
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[3] &= ~y
.array
[3];
1678 x
.array
[2] &= ~y
.array
[2];
1681 x
.array
[1] &= ~y
.array
[1];
1684 x
.array
[0] &= ~y
.array
[0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template
*t
)
1703 i386_cpu_flags x
= t
->cpu_flags
;
1704 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1706 x
.bitfield
.cpu64
= 0;
1707 x
.bitfield
.cpuno64
= 0;
1709 if (cpu_flags_all_zero (&x
))
1711 /* This instruction is available on all archs. */
1712 match
|= CPU_FLAGS_ARCH_MATCH
;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu
= cpu_arch_flags
;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1722 x
.bitfield
.cpuavx512vl
= 0;
1724 cpu
= cpu_flags_and (x
, cpu
);
1725 if (!cpu_flags_all_zero (&cpu
))
1727 if (x
.bitfield
.cpuavx
)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu
.bitfield
.cpuavx
1731 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1733 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1734 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1735 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 else if (x
.bitfield
.cpuavx512f
)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu
.bitfield
.cpuavx512f
1741 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1742 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1743 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1756 switch (ARRAY_SIZE (x
.array
))
1759 x
.array
[2] &= y
.array
[2];
1762 x
.array
[1] &= y
.array
[1];
1765 x
.array
[0] &= y
.array
[0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[2] &= ~y
.array
[2];
1782 x
.array
[1] &= ~y
.array
[1];
1785 x
.array
[0] &= ~y
.array
[0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1796 switch (ARRAY_SIZE (x
.array
))
1799 x
.array
[2] |= y
.array
[2];
1802 x
.array
[1] |= y
.array
[1];
1805 x
.array
[0] |= y
.array
[0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1816 switch (ARRAY_SIZE (x
.array
))
1819 x
.array
[2] ^= y
.array
[2];
1822 x
.array
[1] ^= y
.array
[1];
1825 x
.array
[0] ^= y
.array
[0];
1833 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1834 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1835 static const i386_operand_type inoutportreg
1836 = OPERAND_TYPE_INOUTPORTREG
;
1837 static const i386_operand_type reg16_inoutportreg
1838 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1839 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1840 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1841 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1842 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1843 static const i386_operand_type anydisp
1844 = OPERAND_TYPE_ANYDISP
;
1845 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1846 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1847 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1848 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1849 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1850 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1851 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1852 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1853 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1854 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1855 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1856 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1867 operand_type_check (i386_operand_type t
, enum operand_type c
)
1872 return t
.bitfield
.reg
;
1875 return (t
.bitfield
.imm8
1879 || t
.bitfield
.imm32s
1880 || t
.bitfield
.imm64
);
1883 return (t
.bitfield
.disp8
1884 || t
.bitfield
.disp16
1885 || t
.bitfield
.disp32
1886 || t
.bitfield
.disp32s
1887 || t
.bitfield
.disp64
);
1890 return (t
.bitfield
.disp8
1891 || t
.bitfield
.disp16
1892 || t
.bitfield
.disp32
1893 || t
.bitfield
.disp32s
1894 || t
.bitfield
.disp64
1895 || t
.bitfield
.baseindex
);
1904 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1905 operand J for instruction template T. */
1908 match_reg_size (const insn_template
*t
, unsigned int j
)
1910 return !((i
.types
[j
].bitfield
.byte
1911 && !t
->operand_types
[j
].bitfield
.byte
)
1912 || (i
.types
[j
].bitfield
.word
1913 && !t
->operand_types
[j
].bitfield
.word
)
1914 || (i
.types
[j
].bitfield
.dword
1915 && !t
->operand_types
[j
].bitfield
.dword
)
1916 || (i
.types
[j
].bitfield
.qword
1917 && !t
->operand_types
[j
].bitfield
.qword
)
1918 || (i
.types
[j
].bitfield
.tbyte
1919 && !t
->operand_types
[j
].bitfield
.tbyte
));
1922 /* Return 1 if there is no conflict in SIMD register on
1923 operand J for instruction template T. */
1926 match_simd_size (const insn_template
*t
, unsigned int j
)
1928 return !((i
.types
[j
].bitfield
.xmmword
1929 && !t
->operand_types
[j
].bitfield
.xmmword
)
1930 || (i
.types
[j
].bitfield
.ymmword
1931 && !t
->operand_types
[j
].bitfield
.ymmword
)
1932 || (i
.types
[j
].bitfield
.zmmword
1933 && !t
->operand_types
[j
].bitfield
.zmmword
));
1936 /* Return 1 if there is no conflict in any size on operand J for
1937 instruction template T. */
1940 match_mem_size (const insn_template
*t
, unsigned int j
)
1942 return (match_reg_size (t
, j
)
1943 && !((i
.types
[j
].bitfield
.unspecified
1945 && !t
->operand_types
[j
].bitfield
.unspecified
)
1946 || (i
.types
[j
].bitfield
.fword
1947 && !t
->operand_types
[j
].bitfield
.fword
)
1948 /* For scalar opcode templates to allow register and memory
1949 operands at the same time, some special casing is needed
1950 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1951 down-conversion vpmov*. */
1952 || ((t
->operand_types
[j
].bitfield
.regsimd
1953 && !t
->opcode_modifier
.broadcast
1954 && (t
->operand_types
[j
].bitfield
.byte
1955 || t
->operand_types
[j
].bitfield
.word
1956 || t
->operand_types
[j
].bitfield
.dword
1957 || t
->operand_types
[j
].bitfield
.qword
))
1958 ? (i
.types
[j
].bitfield
.xmmword
1959 || i
.types
[j
].bitfield
.ymmword
1960 || i
.types
[j
].bitfield
.zmmword
)
1961 : !match_simd_size(t
, j
))));
1964 /* Return 1 if there is no size conflict on any operands for
1965 instruction template T. */
1968 operand_size_match (const insn_template
*t
)
1973 /* Don't check jump instructions. */
1974 if (t
->opcode_modifier
.jump
1975 || t
->opcode_modifier
.jumpbyte
1976 || t
->opcode_modifier
.jumpdword
1977 || t
->opcode_modifier
.jumpintersegment
)
1980 /* Check memory and accumulator operand size. */
1981 for (j
= 0; j
< i
.operands
; j
++)
1983 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1984 && t
->operand_types
[j
].bitfield
.anysize
)
1987 if (t
->operand_types
[j
].bitfield
.reg
1988 && !match_reg_size (t
, j
))
1994 if (t
->operand_types
[j
].bitfield
.regsimd
1995 && !match_simd_size (t
, j
))
2001 if (t
->operand_types
[j
].bitfield
.acc
2002 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
2008 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2017 else if (!t
->opcode_modifier
.d
)
2020 i
.error
= operand_size_mismatch
;
2024 /* Check reverse. */
2025 gas_assert (i
.operands
== 2);
2028 for (j
= 0; j
< 2; j
++)
2030 if ((t
->operand_types
[j
].bitfield
.reg
2031 || t
->operand_types
[j
].bitfield
.acc
)
2032 && !match_reg_size (t
, j
? 0 : 1))
2035 if (i
.types
[j
].bitfield
.mem
2036 && !match_mem_size (t
, j
? 0 : 1))
2044 operand_type_match (i386_operand_type overlap
,
2045 i386_operand_type given
)
2047 i386_operand_type temp
= overlap
;
2049 temp
.bitfield
.jumpabsolute
= 0;
2050 temp
.bitfield
.unspecified
= 0;
2051 temp
.bitfield
.byte
= 0;
2052 temp
.bitfield
.word
= 0;
2053 temp
.bitfield
.dword
= 0;
2054 temp
.bitfield
.fword
= 0;
2055 temp
.bitfield
.qword
= 0;
2056 temp
.bitfield
.tbyte
= 0;
2057 temp
.bitfield
.xmmword
= 0;
2058 temp
.bitfield
.ymmword
= 0;
2059 temp
.bitfield
.zmmword
= 0;
2060 if (operand_type_all_zero (&temp
))
2063 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2064 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2068 i
.error
= operand_type_mismatch
;
2072 /* If given types g0 and g1 are registers they must be of the same type
2073 unless the expected operand type register overlap is null.
2074 Memory operand size of certain SIMD instructions is also being checked
2078 operand_type_register_match (i386_operand_type g0
,
2079 i386_operand_type t0
,
2080 i386_operand_type g1
,
2081 i386_operand_type t1
)
2083 if (!g0
.bitfield
.reg
2084 && !g0
.bitfield
.regsimd
2085 && (!operand_type_check (g0
, anymem
)
2086 || g0
.bitfield
.unspecified
2087 || !t0
.bitfield
.regsimd
))
2090 if (!g1
.bitfield
.reg
2091 && !g1
.bitfield
.regsimd
2092 && (!operand_type_check (g1
, anymem
)
2093 || g1
.bitfield
.unspecified
2094 || !t1
.bitfield
.regsimd
))
2097 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2098 && g0
.bitfield
.word
== g1
.bitfield
.word
2099 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2100 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2101 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2102 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2103 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2106 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2107 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2108 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2109 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2110 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2111 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2112 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2115 i
.error
= register_type_mismatch
;
2120 static INLINE
unsigned int
2121 register_number (const reg_entry
*r
)
2123 unsigned int nr
= r
->reg_num
;
2125 if (r
->reg_flags
& RegRex
)
2128 if (r
->reg_flags
& RegVRex
)
2134 static INLINE
unsigned int
2135 mode_from_disp_size (i386_operand_type t
)
2137 if (t
.bitfield
.disp8
)
2139 else if (t
.bitfield
.disp16
2140 || t
.bitfield
.disp32
2141 || t
.bitfield
.disp32s
)
2148 fits_in_signed_byte (addressT num
)
2150 return num
+ 0x80 <= 0xff;
2154 fits_in_unsigned_byte (addressT num
)
2160 fits_in_unsigned_word (addressT num
)
2162 return num
<= 0xffff;
2166 fits_in_signed_word (addressT num
)
2168 return num
+ 0x8000 <= 0xffff;
2172 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2177 return num
+ 0x80000000 <= 0xffffffff;
2179 } /* fits_in_signed_long() */
2182 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2187 return num
<= 0xffffffff;
2189 } /* fits_in_unsigned_long() */
2192 fits_in_disp8 (offsetT num
)
2194 int shift
= i
.memshift
;
2200 mask
= (1 << shift
) - 1;
2202 /* Return 0 if NUM isn't properly aligned. */
2206 /* Check if NUM will fit in 8bit after shift. */
2207 return fits_in_signed_byte (num
>> shift
);
2211 fits_in_imm4 (offsetT num
)
2213 return (num
& 0xf) == num
;
2216 static i386_operand_type
2217 smallest_imm_type (offsetT num
)
2219 i386_operand_type t
;
2221 operand_type_set (&t
, 0);
2222 t
.bitfield
.imm64
= 1;
2224 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2226 /* This code is disabled on the 486 because all the Imm1 forms
2227 in the opcode table are slower on the i486. They're the
2228 versions with the implicitly specified single-position
2229 displacement, which has another syntax if you really want to
2231 t
.bitfield
.imm1
= 1;
2232 t
.bitfield
.imm8
= 1;
2233 t
.bitfield
.imm8s
= 1;
2234 t
.bitfield
.imm16
= 1;
2235 t
.bitfield
.imm32
= 1;
2236 t
.bitfield
.imm32s
= 1;
2238 else if (fits_in_signed_byte (num
))
2240 t
.bitfield
.imm8
= 1;
2241 t
.bitfield
.imm8s
= 1;
2242 t
.bitfield
.imm16
= 1;
2243 t
.bitfield
.imm32
= 1;
2244 t
.bitfield
.imm32s
= 1;
2246 else if (fits_in_unsigned_byte (num
))
2248 t
.bitfield
.imm8
= 1;
2249 t
.bitfield
.imm16
= 1;
2250 t
.bitfield
.imm32
= 1;
2251 t
.bitfield
.imm32s
= 1;
2253 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2255 t
.bitfield
.imm16
= 1;
2256 t
.bitfield
.imm32
= 1;
2257 t
.bitfield
.imm32s
= 1;
2259 else if (fits_in_signed_long (num
))
2261 t
.bitfield
.imm32
= 1;
2262 t
.bitfield
.imm32s
= 1;
2264 else if (fits_in_unsigned_long (num
))
2265 t
.bitfield
.imm32
= 1;
2271 offset_in_range (offsetT val
, int size
)
2277 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2278 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2279 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2281 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2287 /* If BFD64, sign extend val for 32bit address mode. */
2288 if (flag_code
!= CODE_64BIT
2289 || i
.prefix
[ADDR_PREFIX
])
2290 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2291 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2294 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2296 char buf1
[40], buf2
[40];
2298 sprint_value (buf1
, val
);
2299 sprint_value (buf2
, val
& mask
);
2300 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2315 a. PREFIX_EXIST if attempting to add a prefix where one from the
2316 same class already exists.
2317 b. PREFIX_LOCK if lock prefix is added.
2318 c. PREFIX_REP if rep/repne prefix is added.
2319 d. PREFIX_DS if ds prefix is added.
2320 e. PREFIX_OTHER if other prefix is added.
2323 static enum PREFIX_GROUP
2324 add_prefix (unsigned int prefix
)
2326 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2329 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2330 && flag_code
== CODE_64BIT
)
2332 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2333 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2334 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2335 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2346 case DS_PREFIX_OPCODE
:
2349 case CS_PREFIX_OPCODE
:
2350 case ES_PREFIX_OPCODE
:
2351 case FS_PREFIX_OPCODE
:
2352 case GS_PREFIX_OPCODE
:
2353 case SS_PREFIX_OPCODE
:
2357 case REPNE_PREFIX_OPCODE
:
2358 case REPE_PREFIX_OPCODE
:
2363 case LOCK_PREFIX_OPCODE
:
2372 case ADDR_PREFIX_OPCODE
:
2376 case DATA_PREFIX_OPCODE
:
2380 if (i
.prefix
[q
] != 0)
2388 i
.prefix
[q
] |= prefix
;
2391 as_bad (_("same type of prefix used twice"));
2397 update_code_flag (int value
, int check
)
2399 PRINTF_LIKE ((*as_error
));
2401 flag_code
= (enum flag_code
) value
;
2402 if (flag_code
== CODE_64BIT
)
2404 cpu_arch_flags
.bitfield
.cpu64
= 1;
2405 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2409 cpu_arch_flags
.bitfield
.cpu64
= 0;
2410 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2412 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2415 as_error
= as_fatal
;
2418 (*as_error
) (_("64bit mode not supported on `%s'."),
2419 cpu_arch_name
? cpu_arch_name
: default_arch
);
2421 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2424 as_error
= as_fatal
;
2427 (*as_error
) (_("32bit mode not supported on `%s'."),
2428 cpu_arch_name
? cpu_arch_name
: default_arch
);
2430 stackop_size
= '\0';
2434 set_code_flag (int value
)
2436 update_code_flag (value
, 0);
2440 set_16bit_gcc_code_flag (int new_code_flag
)
2442 flag_code
= (enum flag_code
) new_code_flag
;
2443 if (flag_code
!= CODE_16BIT
)
2445 cpu_arch_flags
.bitfield
.cpu64
= 0;
2446 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2447 stackop_size
= LONG_MNEM_SUFFIX
;
2451 set_intel_syntax (int syntax_flag
)
2453 /* Find out if register prefixing is specified. */
2454 int ask_naked_reg
= 0;
2457 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2460 int e
= get_symbol_name (&string
);
2462 if (strcmp (string
, "prefix") == 0)
2464 else if (strcmp (string
, "noprefix") == 0)
2467 as_bad (_("bad argument to syntax directive."));
2468 (void) restore_line_pointer (e
);
2470 demand_empty_rest_of_line ();
2472 intel_syntax
= syntax_flag
;
2474 if (ask_naked_reg
== 0)
2475 allow_naked_reg
= (intel_syntax
2476 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2478 allow_naked_reg
= (ask_naked_reg
< 0);
2480 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2482 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2483 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2484 register_prefix
= allow_naked_reg
? "" : "%";
2488 set_intel_mnemonic (int mnemonic_flag
)
2490 intel_mnemonic
= mnemonic_flag
;
2494 set_allow_index_reg (int flag
)
2496 allow_index_reg
= flag
;
2500 set_check (int what
)
2502 enum check_kind
*kind
;
2507 kind
= &operand_check
;
2518 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2521 int e
= get_symbol_name (&string
);
2523 if (strcmp (string
, "none") == 0)
2525 else if (strcmp (string
, "warning") == 0)
2526 *kind
= check_warning
;
2527 else if (strcmp (string
, "error") == 0)
2528 *kind
= check_error
;
2530 as_bad (_("bad argument to %s_check directive."), str
);
2531 (void) restore_line_pointer (e
);
2534 as_bad (_("missing argument for %s_check directive"), str
);
2536 demand_empty_rest_of_line ();
2540 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2541 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2544 static const char *arch
;
2546 /* Intel LIOM is only supported on ELF. */
2552 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2553 use default_arch. */
2554 arch
= cpu_arch_name
;
2556 arch
= default_arch
;
2559 /* If we are targeting Intel MCU, we must enable it. */
2560 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2561 || new_flag
.bitfield
.cpuiamcu
)
2564 /* If we are targeting Intel L1OM, we must enable it. */
2565 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2566 || new_flag
.bitfield
.cpul1om
)
2569 /* If we are targeting Intel K1OM, we must enable it. */
2570 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2571 || new_flag
.bitfield
.cpuk1om
)
2574 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2579 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2583 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2586 int e
= get_symbol_name (&string
);
2588 i386_cpu_flags flags
;
2590 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2592 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2594 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2598 cpu_arch_name
= cpu_arch
[j
].name
;
2599 cpu_sub_arch_name
= NULL
;
2600 cpu_arch_flags
= cpu_arch
[j
].flags
;
2601 if (flag_code
== CODE_64BIT
)
2603 cpu_arch_flags
.bitfield
.cpu64
= 1;
2604 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2608 cpu_arch_flags
.bitfield
.cpu64
= 0;
2609 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2611 cpu_arch_isa
= cpu_arch
[j
].type
;
2612 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2613 if (!cpu_arch_tune_set
)
2615 cpu_arch_tune
= cpu_arch_isa
;
2616 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2621 flags
= cpu_flags_or (cpu_arch_flags
,
2624 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2626 if (cpu_sub_arch_name
)
2628 char *name
= cpu_sub_arch_name
;
2629 cpu_sub_arch_name
= concat (name
,
2631 (const char *) NULL
);
2635 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2636 cpu_arch_flags
= flags
;
2637 cpu_arch_isa_flags
= flags
;
2641 = cpu_flags_or (cpu_arch_isa_flags
,
2643 (void) restore_line_pointer (e
);
2644 demand_empty_rest_of_line ();
2649 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2651 /* Disable an ISA extension. */
2652 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2653 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2655 flags
= cpu_flags_and_not (cpu_arch_flags
,
2656 cpu_noarch
[j
].flags
);
2657 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2659 if (cpu_sub_arch_name
)
2661 char *name
= cpu_sub_arch_name
;
2662 cpu_sub_arch_name
= concat (name
, string
,
2663 (const char *) NULL
);
2667 cpu_sub_arch_name
= xstrdup (string
);
2668 cpu_arch_flags
= flags
;
2669 cpu_arch_isa_flags
= flags
;
2671 (void) restore_line_pointer (e
);
2672 demand_empty_rest_of_line ();
2676 j
= ARRAY_SIZE (cpu_arch
);
2679 if (j
>= ARRAY_SIZE (cpu_arch
))
2680 as_bad (_("no such architecture: `%s'"), string
);
2682 *input_line_pointer
= e
;
2685 as_bad (_("missing cpu architecture"));
2687 no_cond_jump_promotion
= 0;
2688 if (*input_line_pointer
== ','
2689 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2694 ++input_line_pointer
;
2695 e
= get_symbol_name (&string
);
2697 if (strcmp (string
, "nojumps") == 0)
2698 no_cond_jump_promotion
= 1;
2699 else if (strcmp (string
, "jumps") == 0)
2702 as_bad (_("no such architecture modifier: `%s'"), string
);
2704 (void) restore_line_pointer (e
);
2707 demand_empty_rest_of_line ();
2710 enum bfd_architecture
2713 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2715 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2716 || flag_code
!= CODE_64BIT
)
2717 as_fatal (_("Intel L1OM is 64bit ELF only"));
2718 return bfd_arch_l1om
;
2720 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2722 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2723 || flag_code
!= CODE_64BIT
)
2724 as_fatal (_("Intel K1OM is 64bit ELF only"));
2725 return bfd_arch_k1om
;
2727 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2729 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2730 || flag_code
== CODE_64BIT
)
2731 as_fatal (_("Intel MCU is 32bit ELF only"));
2732 return bfd_arch_iamcu
;
2735 return bfd_arch_i386
;
2741 if (!strncmp (default_arch
, "x86_64", 6))
2743 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2745 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2746 || default_arch
[6] != '\0')
2747 as_fatal (_("Intel L1OM is 64bit ELF only"));
2748 return bfd_mach_l1om
;
2750 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2752 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2753 || default_arch
[6] != '\0')
2754 as_fatal (_("Intel K1OM is 64bit ELF only"));
2755 return bfd_mach_k1om
;
2757 else if (default_arch
[6] == '\0')
2758 return bfd_mach_x86_64
;
2760 return bfd_mach_x64_32
;
2762 else if (!strcmp (default_arch
, "i386")
2763 || !strcmp (default_arch
, "iamcu"))
2765 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2767 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2768 as_fatal (_("Intel MCU is 32bit ELF only"));
2769 return bfd_mach_i386_iamcu
;
2772 return bfd_mach_i386_i386
;
2775 as_fatal (_("unknown architecture"));
2781 const char *hash_err
;
2783 /* Support pseudo prefixes like {disp32}. */
2784 lex_type
['{'] = LEX_BEGIN_NAME
;
2786 /* Initialize op_hash hash table. */
2787 op_hash
= hash_new ();
2790 const insn_template
*optab
;
2791 templates
*core_optab
;
2793 /* Setup for loop. */
2795 core_optab
= XNEW (templates
);
2796 core_optab
->start
= optab
;
2801 if (optab
->name
== NULL
2802 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2804 /* different name --> ship out current template list;
2805 add to hash table; & begin anew. */
2806 core_optab
->end
= optab
;
2807 hash_err
= hash_insert (op_hash
,
2809 (void *) core_optab
);
2812 as_fatal (_("can't hash %s: %s"),
2816 if (optab
->name
== NULL
)
2818 core_optab
= XNEW (templates
);
2819 core_optab
->start
= optab
;
2824 /* Initialize reg_hash hash table. */
2825 reg_hash
= hash_new ();
2827 const reg_entry
*regtab
;
2828 unsigned int regtab_size
= i386_regtab_size
;
2830 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2832 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2834 as_fatal (_("can't hash %s: %s"),
2840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2845 for (c
= 0; c
< 256; c
++)
2850 mnemonic_chars
[c
] = c
;
2851 register_chars
[c
] = c
;
2852 operand_chars
[c
] = c
;
2854 else if (ISLOWER (c
))
2856 mnemonic_chars
[c
] = c
;
2857 register_chars
[c
] = c
;
2858 operand_chars
[c
] = c
;
2860 else if (ISUPPER (c
))
2862 mnemonic_chars
[c
] = TOLOWER (c
);
2863 register_chars
[c
] = mnemonic_chars
[c
];
2864 operand_chars
[c
] = c
;
2866 else if (c
== '{' || c
== '}')
2868 mnemonic_chars
[c
] = c
;
2869 operand_chars
[c
] = c
;
2872 if (ISALPHA (c
) || ISDIGIT (c
))
2873 identifier_chars
[c
] = c
;
2876 identifier_chars
[c
] = c
;
2877 operand_chars
[c
] = c
;
2882 identifier_chars
['@'] = '@';
2885 identifier_chars
['?'] = '?';
2886 operand_chars
['?'] = '?';
2888 digit_chars
['-'] = '-';
2889 mnemonic_chars
['_'] = '_';
2890 mnemonic_chars
['-'] = '-';
2891 mnemonic_chars
['.'] = '.';
2892 identifier_chars
['_'] = '_';
2893 identifier_chars
['.'] = '.';
2895 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2896 operand_chars
[(unsigned char) *p
] = *p
;
2899 if (flag_code
== CODE_64BIT
)
2901 #if defined (OBJ_COFF) && defined (TE_PE)
2902 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2905 x86_dwarf2_return_column
= 16;
2907 x86_cie_data_alignment
= -8;
2911 x86_dwarf2_return_column
= 8;
2912 x86_cie_data_alignment
= -4;
2917 i386_print_statistics (FILE *file
)
2919 hash_print_statistics (file
, "i386 opcode", op_hash
);
2920 hash_print_statistics (file
, "i386 register", reg_hash
);
2925 /* Debugging routines for md_assemble. */
2926 static void pte (insn_template
*);
2927 static void pt (i386_operand_type
);
2928 static void pe (expressionS
*);
2929 static void ps (symbolS
*);
2932 pi (char *line
, i386_insn
*x
)
2936 fprintf (stdout
, "%s: template ", line
);
2938 fprintf (stdout
, " address: base %s index %s scale %x\n",
2939 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2940 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2941 x
->log2_scale_factor
);
2942 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2943 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2944 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2945 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2946 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2947 (x
->rex
& REX_W
) != 0,
2948 (x
->rex
& REX_R
) != 0,
2949 (x
->rex
& REX_X
) != 0,
2950 (x
->rex
& REX_B
) != 0);
2951 for (j
= 0; j
< x
->operands
; j
++)
2953 fprintf (stdout
, " #%d: ", j
+ 1);
2955 fprintf (stdout
, "\n");
2956 if (x
->types
[j
].bitfield
.reg
2957 || x
->types
[j
].bitfield
.regmmx
2958 || x
->types
[j
].bitfield
.regsimd
2959 || x
->types
[j
].bitfield
.sreg2
2960 || x
->types
[j
].bitfield
.sreg3
2961 || x
->types
[j
].bitfield
.control
2962 || x
->types
[j
].bitfield
.debug
2963 || x
->types
[j
].bitfield
.test
)
2964 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2965 if (operand_type_check (x
->types
[j
], imm
))
2967 if (operand_type_check (x
->types
[j
], disp
))
2968 pe (x
->op
[j
].disps
);
2973 pte (insn_template
*t
)
2976 fprintf (stdout
, " %d operands ", t
->operands
);
2977 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2978 if (t
->extension_opcode
!= None
)
2979 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2980 if (t
->opcode_modifier
.d
)
2981 fprintf (stdout
, "D");
2982 if (t
->opcode_modifier
.w
)
2983 fprintf (stdout
, "W");
2984 fprintf (stdout
, "\n");
2985 for (j
= 0; j
< t
->operands
; j
++)
2987 fprintf (stdout
, " #%d type ", j
+ 1);
2988 pt (t
->operand_types
[j
]);
2989 fprintf (stdout
, "\n");
2996 fprintf (stdout
, " operation %d\n", e
->X_op
);
2997 fprintf (stdout
, " add_number %ld (%lx)\n",
2998 (long) e
->X_add_number
, (long) e
->X_add_number
);
2999 if (e
->X_add_symbol
)
3001 fprintf (stdout
, " add_symbol ");
3002 ps (e
->X_add_symbol
);
3003 fprintf (stdout
, "\n");
3007 fprintf (stdout
, " op_symbol ");
3008 ps (e
->X_op_symbol
);
3009 fprintf (stdout
, "\n");
3016 fprintf (stdout
, "%s type %s%s",
3018 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3019 segment_name (S_GET_SEGMENT (s
)));
3022 static struct type_name
3024 i386_operand_type mask
;
3027 const type_names
[] =
3029 { OPERAND_TYPE_REG8
, "r8" },
3030 { OPERAND_TYPE_REG16
, "r16" },
3031 { OPERAND_TYPE_REG32
, "r32" },
3032 { OPERAND_TYPE_REG64
, "r64" },
3033 { OPERAND_TYPE_IMM8
, "i8" },
3034 { OPERAND_TYPE_IMM8
, "i8s" },
3035 { OPERAND_TYPE_IMM16
, "i16" },
3036 { OPERAND_TYPE_IMM32
, "i32" },
3037 { OPERAND_TYPE_IMM32S
, "i32s" },
3038 { OPERAND_TYPE_IMM64
, "i64" },
3039 { OPERAND_TYPE_IMM1
, "i1" },
3040 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3041 { OPERAND_TYPE_DISP8
, "d8" },
3042 { OPERAND_TYPE_DISP16
, "d16" },
3043 { OPERAND_TYPE_DISP32
, "d32" },
3044 { OPERAND_TYPE_DISP32S
, "d32s" },
3045 { OPERAND_TYPE_DISP64
, "d64" },
3046 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3047 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3048 { OPERAND_TYPE_CONTROL
, "control reg" },
3049 { OPERAND_TYPE_TEST
, "test reg" },
3050 { OPERAND_TYPE_DEBUG
, "debug reg" },
3051 { OPERAND_TYPE_FLOATREG
, "FReg" },
3052 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3053 { OPERAND_TYPE_SREG2
, "SReg2" },
3054 { OPERAND_TYPE_SREG3
, "SReg3" },
3055 { OPERAND_TYPE_ACC
, "Acc" },
3056 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3057 { OPERAND_TYPE_REGMMX
, "rMMX" },
3058 { OPERAND_TYPE_REGXMM
, "rXMM" },
3059 { OPERAND_TYPE_REGYMM
, "rYMM" },
3060 { OPERAND_TYPE_REGZMM
, "rZMM" },
3061 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3062 { OPERAND_TYPE_ESSEG
, "es" },
3066 pt (i386_operand_type t
)
3069 i386_operand_type a
;
3071 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3073 a
= operand_type_and (t
, type_names
[j
].mask
);
3074 if (!operand_type_all_zero (&a
))
3075 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3080 #endif /* DEBUG386 */
3082 static bfd_reloc_code_real_type
3083 reloc (unsigned int size
,
3086 bfd_reloc_code_real_type other
)
3088 if (other
!= NO_RELOC
)
3090 reloc_howto_type
*rel
;
3095 case BFD_RELOC_X86_64_GOT32
:
3096 return BFD_RELOC_X86_64_GOT64
;
3098 case BFD_RELOC_X86_64_GOTPLT64
:
3099 return BFD_RELOC_X86_64_GOTPLT64
;
3101 case BFD_RELOC_X86_64_PLTOFF64
:
3102 return BFD_RELOC_X86_64_PLTOFF64
;
3104 case BFD_RELOC_X86_64_GOTPC32
:
3105 other
= BFD_RELOC_X86_64_GOTPC64
;
3107 case BFD_RELOC_X86_64_GOTPCREL
:
3108 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3110 case BFD_RELOC_X86_64_TPOFF32
:
3111 other
= BFD_RELOC_X86_64_TPOFF64
;
3113 case BFD_RELOC_X86_64_DTPOFF32
:
3114 other
= BFD_RELOC_X86_64_DTPOFF64
;
3120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3121 if (other
== BFD_RELOC_SIZE32
)
3124 other
= BFD_RELOC_SIZE64
;
3127 as_bad (_("there are no pc-relative size relocations"));
3133 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3134 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3137 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3139 as_bad (_("unknown relocation (%u)"), other
);
3140 else if (size
!= bfd_get_reloc_size (rel
))
3141 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3142 bfd_get_reloc_size (rel
),
3144 else if (pcrel
&& !rel
->pc_relative
)
3145 as_bad (_("non-pc-relative relocation for pc-relative field"));
3146 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3148 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3150 as_bad (_("relocated field and relocation type differ in signedness"));
3159 as_bad (_("there are no unsigned pc-relative relocations"));
3162 case 1: return BFD_RELOC_8_PCREL
;
3163 case 2: return BFD_RELOC_16_PCREL
;
3164 case 4: return BFD_RELOC_32_PCREL
;
3165 case 8: return BFD_RELOC_64_PCREL
;
3167 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3174 case 4: return BFD_RELOC_X86_64_32S
;
3179 case 1: return BFD_RELOC_8
;
3180 case 2: return BFD_RELOC_16
;
3181 case 4: return BFD_RELOC_32
;
3182 case 8: return BFD_RELOC_64
;
3184 as_bad (_("cannot do %s %u byte relocation"),
3185 sign
> 0 ? "signed" : "unsigned", size
);
3191 /* Here we decide which fixups can be adjusted to make them relative to
3192 the beginning of the section instead of the symbol. Basically we need
3193 to make sure that the dynamic relocations are done correctly, so in
3194 some cases we force the original symbol to be used. */
3197 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3203 /* Don't adjust pc-relative references to merge sections in 64-bit
3205 if (use_rela_relocations
3206 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3210 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3211 and changed later by validate_fix. */
3212 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3213 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3216 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3217 for size relocations. */
3218 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3219 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3220 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3221 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3222 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3223 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3249 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3250 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3257 intel_float_operand (const char *mnemonic
)
3259 /* Note that the value returned is meaningful only for opcodes with (memory)
3260 operands, hence the code here is free to improperly handle opcodes that
3261 have no operands (for better performance and smaller code). */
3263 if (mnemonic
[0] != 'f')
3264 return 0; /* non-math */
3266 switch (mnemonic
[1])
3268 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3269 the fs segment override prefix not currently handled because no
3270 call path can make opcodes without operands get here */
3272 return 2 /* integer op */;
3274 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3275 return 3; /* fldcw/fldenv */
3278 if (mnemonic
[2] != 'o' /* fnop */)
3279 return 3; /* non-waiting control op */
3282 if (mnemonic
[2] == 's')
3283 return 3; /* frstor/frstpm */
3286 if (mnemonic
[2] == 'a')
3287 return 3; /* fsave */
3288 if (mnemonic
[2] == 't')
3290 switch (mnemonic
[3])
3292 case 'c': /* fstcw */
3293 case 'd': /* fstdw */
3294 case 'e': /* fstenv */
3295 case 's': /* fsts[gw] */
3301 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3302 return 0; /* fxsave/fxrstor are not really math ops */
3309 /* Build the VEX prefix. */
3312 build_vex_prefix (const insn_template
*t
)
3314 unsigned int register_specifier
;
3315 unsigned int implied_prefix
;
3316 unsigned int vector_length
;
3318 /* Check register specifier. */
3319 if (i
.vex
.register_specifier
)
3321 register_specifier
=
3322 ~register_number (i
.vex
.register_specifier
) & 0xf;
3323 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3326 register_specifier
= 0xf;
3328 /* Use 2-byte VEX prefix by swapping destination and source
3330 if (i
.vec_encoding
!= vex_encoding_vex3
3331 && i
.dir_encoding
== dir_encoding_default
3332 && i
.operands
== i
.reg_operands
3333 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3334 && i
.tm
.opcode_modifier
.load
3337 unsigned int xchg
= i
.operands
- 1;
3338 union i386_op temp_op
;
3339 i386_operand_type temp_type
;
3341 temp_type
= i
.types
[xchg
];
3342 i
.types
[xchg
] = i
.types
[0];
3343 i
.types
[0] = temp_type
;
3344 temp_op
= i
.op
[xchg
];
3345 i
.op
[xchg
] = i
.op
[0];
3348 gas_assert (i
.rm
.mode
== 3);
3352 i
.rm
.regmem
= i
.rm
.reg
;
3355 /* Use the next insn. */
3359 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3360 vector_length
= avxscalar
;
3361 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3368 for (op
= 0; op
< t
->operands
; ++op
)
3369 if (t
->operand_types
[op
].bitfield
.xmmword
3370 && t
->operand_types
[op
].bitfield
.ymmword
3371 && i
.types
[op
].bitfield
.ymmword
)
3378 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3383 case DATA_PREFIX_OPCODE
:
3386 case REPE_PREFIX_OPCODE
:
3389 case REPNE_PREFIX_OPCODE
:
3396 /* Use 2-byte VEX prefix if possible. */
3397 if (i
.vec_encoding
!= vex_encoding_vex3
3398 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3399 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3400 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3402 /* 2-byte VEX prefix. */
3406 i
.vex
.bytes
[0] = 0xc5;
3408 /* Check the REX.R bit. */
3409 r
= (i
.rex
& REX_R
) ? 0 : 1;
3410 i
.vex
.bytes
[1] = (r
<< 7
3411 | register_specifier
<< 3
3412 | vector_length
<< 2
3417 /* 3-byte VEX prefix. */
3422 switch (i
.tm
.opcode_modifier
.vexopcode
)
3426 i
.vex
.bytes
[0] = 0xc4;
3430 i
.vex
.bytes
[0] = 0xc4;
3434 i
.vex
.bytes
[0] = 0xc4;
3438 i
.vex
.bytes
[0] = 0x8f;
3442 i
.vex
.bytes
[0] = 0x8f;
3446 i
.vex
.bytes
[0] = 0x8f;
3452 /* The high 3 bits of the second VEX byte are 1's compliment
3453 of RXB bits from REX. */
3454 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3456 /* Check the REX.W bit. */
3457 w
= (i
.rex
& REX_W
) ? 1 : 0;
3458 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3461 i
.vex
.bytes
[2] = (w
<< 7
3462 | register_specifier
<< 3
3463 | vector_length
<< 2
3468 static INLINE bfd_boolean
3469 is_evex_encoding (const insn_template
*t
)
3471 return t
->opcode_modifier
.evex
3472 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3473 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3476 /* Build the EVEX prefix. */
3479 build_evex_prefix (void)
3481 unsigned int register_specifier
;
3482 unsigned int implied_prefix
;
3484 rex_byte vrex_used
= 0;
3486 /* Check register specifier. */
3487 if (i
.vex
.register_specifier
)
3489 gas_assert ((i
.vrex
& REX_X
) == 0);
3491 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3492 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3493 register_specifier
+= 8;
3494 /* The upper 16 registers are encoded in the fourth byte of the
3496 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3497 i
.vex
.bytes
[3] = 0x8;
3498 register_specifier
= ~register_specifier
& 0xf;
3502 register_specifier
= 0xf;
3504 /* Encode upper 16 vector index register in the fourth byte of
3506 if (!(i
.vrex
& REX_X
))
3507 i
.vex
.bytes
[3] = 0x8;
3512 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3517 case DATA_PREFIX_OPCODE
:
3520 case REPE_PREFIX_OPCODE
:
3523 case REPNE_PREFIX_OPCODE
:
3530 /* 4 byte EVEX prefix. */
3532 i
.vex
.bytes
[0] = 0x62;
3535 switch (i
.tm
.opcode_modifier
.vexopcode
)
3551 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3553 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3555 /* The fifth bit of the second EVEX byte is 1's compliment of the
3556 REX_R bit in VREX. */
3557 if (!(i
.vrex
& REX_R
))
3558 i
.vex
.bytes
[1] |= 0x10;
3562 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3564 /* When all operands are registers, the REX_X bit in REX is not
3565 used. We reuse it to encode the upper 16 registers, which is
3566 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3567 as 1's compliment. */
3568 if ((i
.vrex
& REX_B
))
3571 i
.vex
.bytes
[1] &= ~0x40;
3575 /* EVEX instructions shouldn't need the REX prefix. */
3576 i
.vrex
&= ~vrex_used
;
3577 gas_assert (i
.vrex
== 0);
3579 /* Check the REX.W bit. */
3580 w
= (i
.rex
& REX_W
) ? 1 : 0;
3581 if (i
.tm
.opcode_modifier
.vexw
)
3583 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3586 /* If w is not set it means we are dealing with WIG instruction. */
3589 if (evexwig
== evexw1
)
3593 /* Encode the U bit. */
3594 implied_prefix
|= 0x4;
3596 /* The third byte of the EVEX prefix. */
3597 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3599 /* The fourth byte of the EVEX prefix. */
3600 /* The zeroing-masking bit. */
3601 if (i
.mask
&& i
.mask
->zeroing
)
3602 i
.vex
.bytes
[3] |= 0x80;
3604 /* Don't always set the broadcast bit if there is no RC. */
3607 /* Encode the vector length. */
3608 unsigned int vec_length
;
3610 if (!i
.tm
.opcode_modifier
.evex
3611 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3616 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3617 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3618 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3619 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3621 if (i
.types
[op
].bitfield
.zmmword
)
3622 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3623 else if (i
.types
[op
].bitfield
.ymmword
)
3624 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3625 else if (i
.types
[op
].bitfield
.xmmword
)
3626 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3633 switch (i
.tm
.opcode_modifier
.evex
)
3635 case EVEXLIG
: /* LL' is ignored */
3636 vec_length
= evexlig
<< 5;
3639 vec_length
= 0 << 5;
3642 vec_length
= 1 << 5;
3645 vec_length
= 2 << 5;
3651 i
.vex
.bytes
[3] |= vec_length
;
3652 /* Encode the broadcast bit. */
3654 i
.vex
.bytes
[3] |= 0x10;
3658 if (i
.rounding
->type
!= saeonly
)
3659 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3661 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3664 if (i
.mask
&& i
.mask
->mask
)
3665 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3669 process_immext (void)
3673 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3676 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3677 with an opcode suffix which is coded in the same place as an
3678 8-bit immediate field would be.
3679 Here we check those operands and remove them afterwards. */
3682 for (x
= 0; x
< i
.operands
; x
++)
3683 if (register_number (i
.op
[x
].regs
) != x
)
3684 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3685 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3691 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3693 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3694 suffix which is coded in the same place as an 8-bit immediate
3696 Here we check those operands and remove them afterwards. */
3699 if (i
.operands
!= 3)
3702 for (x
= 0; x
< 2; x
++)
3703 if (register_number (i
.op
[x
].regs
) != x
)
3704 goto bad_register_operand
;
3706 /* Check for third operand for mwaitx/monitorx insn. */
3707 if (register_number (i
.op
[x
].regs
)
3708 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3710 bad_register_operand
:
3711 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3712 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3719 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3720 which is coded in the same place as an 8-bit immediate field
3721 would be. Here we fake an 8-bit immediate operand from the
3722 opcode suffix stored in tm.extension_opcode.
3724 AVX instructions also use this encoding, for some of
3725 3 argument instructions. */
3727 gas_assert (i
.imm_operands
<= 1
3729 || ((i
.tm
.opcode_modifier
.vex
3730 || i
.tm
.opcode_modifier
.vexopcode
3731 || is_evex_encoding (&i
.tm
))
3732 && i
.operands
<= 4)));
3734 exp
= &im_expressions
[i
.imm_operands
++];
3735 i
.op
[i
.operands
].imms
= exp
;
3736 i
.types
[i
.operands
] = imm8
;
3738 exp
->X_op
= O_constant
;
3739 exp
->X_add_number
= i
.tm
.extension_opcode
;
3740 i
.tm
.extension_opcode
= None
;
3747 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3752 as_bad (_("invalid instruction `%s' after `%s'"),
3753 i
.tm
.name
, i
.hle_prefix
);
3756 if (i
.prefix
[LOCK_PREFIX
])
3758 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3762 case HLEPrefixRelease
:
3763 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3765 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3769 if (i
.mem_operands
== 0
3770 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3772 as_bad (_("memory destination needed for instruction `%s'"
3773 " after `xrelease'"), i
.tm
.name
);
3780 /* Try the shortest encoding by shortening operand size. */
3783 optimize_encoding (void)
3787 if (optimize_for_space
3788 && i
.reg_operands
== 1
3789 && i
.imm_operands
== 1
3790 && !i
.types
[1].bitfield
.byte
3791 && i
.op
[0].imms
->X_op
== O_constant
3792 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3793 && ((i
.tm
.base_opcode
== 0xa8
3794 && i
.tm
.extension_opcode
== None
)
3795 || (i
.tm
.base_opcode
== 0xf6
3796 && i
.tm
.extension_opcode
== 0x0)))
3799 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3801 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3802 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3804 i
.types
[1].bitfield
.byte
= 1;
3805 /* Ignore the suffix. */
3807 if (base_regnum
>= 4
3808 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3810 /* Handle SP, BP, SI and DI registers. */
3811 if (i
.types
[1].bitfield
.word
)
3813 else if (i
.types
[1].bitfield
.dword
)
3821 else if (flag_code
== CODE_64BIT
3822 && ((i
.types
[1].bitfield
.qword
3823 && i
.reg_operands
== 1
3824 && i
.imm_operands
== 1
3825 && i
.op
[0].imms
->X_op
== O_constant
3826 && ((i
.tm
.base_opcode
== 0xb0
3827 && i
.tm
.extension_opcode
== None
3828 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3829 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3830 && (((i
.tm
.base_opcode
== 0x24
3831 || i
.tm
.base_opcode
== 0xa8)
3832 && i
.tm
.extension_opcode
== None
)
3833 || (i
.tm
.base_opcode
== 0x80
3834 && i
.tm
.extension_opcode
== 0x4)
3835 || ((i
.tm
.base_opcode
== 0xf6
3836 || i
.tm
.base_opcode
== 0xc6)
3837 && i
.tm
.extension_opcode
== 0x0)))))
3838 || (i
.types
[0].bitfield
.qword
3839 && ((i
.reg_operands
== 2
3840 && i
.op
[0].regs
== i
.op
[1].regs
3841 && ((i
.tm
.base_opcode
== 0x30
3842 || i
.tm
.base_opcode
== 0x28)
3843 && i
.tm
.extension_opcode
== None
))
3844 || (i
.reg_operands
== 1
3846 && i
.tm
.base_opcode
== 0x30
3847 && i
.tm
.extension_opcode
== None
)))))
3850 andq $imm31, %r64 -> andl $imm31, %r32
3851 testq $imm31, %r64 -> testl $imm31, %r32
3852 xorq %r64, %r64 -> xorl %r32, %r32
3853 subq %r64, %r64 -> subl %r32, %r32
3854 movq $imm31, %r64 -> movl $imm31, %r32
3855 movq $imm32, %r64 -> movl $imm32, %r32
3857 i
.tm
.opcode_modifier
.norex64
= 1;
3858 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3861 movq $imm31, %r64 -> movl $imm31, %r32
3862 movq $imm32, %r64 -> movl $imm32, %r32
3864 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3865 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3866 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3867 i
.types
[0].bitfield
.imm32
= 1;
3868 i
.types
[0].bitfield
.imm32s
= 0;
3869 i
.types
[0].bitfield
.imm64
= 0;
3870 i
.types
[1].bitfield
.dword
= 1;
3871 i
.types
[1].bitfield
.qword
= 0;
3872 if (i
.tm
.base_opcode
== 0xc6)
3875 movq $imm31, %r64 -> movl $imm31, %r32
3877 i
.tm
.base_opcode
= 0xb0;
3878 i
.tm
.extension_opcode
= None
;
3879 i
.tm
.opcode_modifier
.shortform
= 1;
3880 i
.tm
.opcode_modifier
.modrm
= 0;
3884 else if (optimize
> 1
3885 && i
.reg_operands
== 3
3886 && i
.op
[0].regs
== i
.op
[1].regs
3887 && !i
.types
[2].bitfield
.xmmword
3888 && (i
.tm
.opcode_modifier
.vex
3889 || ((!i
.mask
|| i
.mask
->zeroing
)
3891 && is_evex_encoding (&i
.tm
)
3892 && (i
.vec_encoding
!= vex_encoding_evex
3893 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3894 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3895 && ((i
.tm
.base_opcode
== 0x55
3896 || i
.tm
.base_opcode
== 0x6655
3897 || i
.tm
.base_opcode
== 0x66df
3898 || i
.tm
.base_opcode
== 0x57
3899 || i
.tm
.base_opcode
== 0x6657
3900 || i
.tm
.base_opcode
== 0x66ef
3901 || i
.tm
.base_opcode
== 0x66f8
3902 || i
.tm
.base_opcode
== 0x66f9
3903 || i
.tm
.base_opcode
== 0x66fa
3904 || i
.tm
.base_opcode
== 0x66fb)
3905 && i
.tm
.extension_opcode
== None
))
3908 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3910 EVEX VOP %zmmM, %zmmM, %zmmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3912 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3913 EVEX VOP %ymmM, %ymmM, %ymmN
3914 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 VEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX VOP %xmmM, %xmmM, %xmmN
3918 VOP, one of vpandn and vpxor:
3919 VEX VOP %ymmM, %ymmM, %ymmN
3920 -> VEX VOP %xmmM, %xmmM, %xmmN
3921 VOP, one of vpandnd and vpandnq:
3922 EVEX VOP %zmmM, %zmmM, %zmmN
3923 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 EVEX VOP %ymmM, %ymmM, %ymmN
3926 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 VOP, one of vpxord and vpxorq:
3929 EVEX VOP %zmmM, %zmmM, %zmmN
3930 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3931 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 EVEX VOP %ymmM, %ymmM, %ymmN
3933 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3934 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3936 if (is_evex_encoding (&i
.tm
))
3938 if (i
.vec_encoding
== vex_encoding_evex
)
3939 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3942 i
.tm
.opcode_modifier
.vex
= VEX128
;
3943 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3944 i
.tm
.opcode_modifier
.evex
= 0;
3948 i
.tm
.opcode_modifier
.vex
= VEX128
;
3950 if (i
.tm
.opcode_modifier
.vex
)
3951 for (j
= 0; j
< 3; j
++)
3953 i
.types
[j
].bitfield
.xmmword
= 1;
3954 i
.types
[j
].bitfield
.ymmword
= 0;
3959 /* This is the guts of the machine-dependent assembler. LINE points to a
3960 machine dependent instruction. This function is supposed to emit
3961 the frags/bytes it assembles to. */
3964 md_assemble (char *line
)
3967 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3968 const insn_template
*t
;
3970 /* Initialize globals. */
3971 memset (&i
, '\0', sizeof (i
));
3972 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3973 i
.reloc
[j
] = NO_RELOC
;
3974 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3975 memset (im_expressions
, '\0', sizeof (im_expressions
));
3976 save_stack_p
= save_stack
;
3978 /* First parse an instruction mnemonic & call i386_operand for the operands.
3979 We assume that the scrubber has arranged it so that line[0] is the valid
3980 start of a (possibly prefixed) mnemonic. */
3982 line
= parse_insn (line
, mnemonic
);
3985 mnem_suffix
= i
.suffix
;
3987 line
= parse_operands (line
, mnemonic
);
3989 xfree (i
.memop1_string
);
3990 i
.memop1_string
= NULL
;
3994 /* Now we've parsed the mnemonic into a set of templates, and have the
3995 operands at hand. */
3997 /* All intel opcodes have reversed operands except for "bound" and
3998 "enter". We also don't reverse intersegment "jmp" and "call"
3999 instructions with 2 immediate operands so that the immediate segment
4000 precedes the offset, as it does when in AT&T mode. */
4003 && (strcmp (mnemonic
, "bound") != 0)
4004 && (strcmp (mnemonic
, "invlpga") != 0)
4005 && !(operand_type_check (i
.types
[0], imm
)
4006 && operand_type_check (i
.types
[1], imm
)))
4009 /* The order of the immediates should be reversed
4010 for 2 immediates extrq and insertq instructions */
4011 if (i
.imm_operands
== 2
4012 && (strcmp (mnemonic
, "extrq") == 0
4013 || strcmp (mnemonic
, "insertq") == 0))
4014 swap_2_operands (0, 1);
4019 /* Don't optimize displacement for movabs since it only takes 64bit
4022 && i
.disp_encoding
!= disp_encoding_32bit
4023 && (flag_code
!= CODE_64BIT
4024 || strcmp (mnemonic
, "movabs") != 0))
4027 /* Next, we find a template that matches the given insn,
4028 making sure the overlap of the given operands types is consistent
4029 with the template operand types. */
4031 if (!(t
= match_template (mnem_suffix
)))
4034 if (sse_check
!= check_none
4035 && !i
.tm
.opcode_modifier
.noavx
4036 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4037 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4038 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4039 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4040 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4042 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4043 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4044 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4045 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4047 (sse_check
== check_warning
4049 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4052 /* Zap movzx and movsx suffix. The suffix has been set from
4053 "word ptr" or "byte ptr" on the source operand in Intel syntax
4054 or extracted from mnemonic in AT&T syntax. But we'll use
4055 the destination register to choose the suffix for encoding. */
4056 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4058 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4059 there is no suffix, the default will be byte extension. */
4060 if (i
.reg_operands
!= 2
4063 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4068 if (i
.tm
.opcode_modifier
.fwait
)
4069 if (!add_prefix (FWAIT_OPCODE
))
4072 /* Check if REP prefix is OK. */
4073 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4075 as_bad (_("invalid instruction `%s' after `%s'"),
4076 i
.tm
.name
, i
.rep_prefix
);
4080 /* Check for lock without a lockable instruction. Destination operand
4081 must be memory unless it is xchg (0x86). */
4082 if (i
.prefix
[LOCK_PREFIX
]
4083 && (!i
.tm
.opcode_modifier
.islockable
4084 || i
.mem_operands
== 0
4085 || (i
.tm
.base_opcode
!= 0x86
4086 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4088 as_bad (_("expecting lockable instruction after `lock'"));
4092 /* Check if HLE prefix is OK. */
4093 if (i
.hle_prefix
&& !check_hle ())
4096 /* Check BND prefix. */
4097 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4098 as_bad (_("expecting valid branch instruction after `bnd'"));
4100 /* Check NOTRACK prefix. */
4101 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4102 as_bad (_("expecting indirect branch instruction after `notrack'"));
4104 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4106 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4107 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4108 else if (flag_code
!= CODE_16BIT
4109 ? i
.prefix
[ADDR_PREFIX
]
4110 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4111 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4114 /* Insert BND prefix. */
4115 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4117 if (!i
.prefix
[BND_PREFIX
])
4118 add_prefix (BND_PREFIX_OPCODE
);
4119 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4121 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4122 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4126 /* Check string instruction segment overrides. */
4127 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4129 if (!check_string ())
4131 i
.disp_operands
= 0;
4134 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4135 optimize_encoding ();
4137 if (!process_suffix ())
4140 /* Update operand types. */
4141 for (j
= 0; j
< i
.operands
; j
++)
4142 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4144 /* Make still unresolved immediate matches conform to size of immediate
4145 given in i.suffix. */
4146 if (!finalize_imm ())
4149 if (i
.types
[0].bitfield
.imm1
)
4150 i
.imm_operands
= 0; /* kludge for shift insns. */
4152 /* We only need to check those implicit registers for instructions
4153 with 3 operands or less. */
4154 if (i
.operands
<= 3)
4155 for (j
= 0; j
< i
.operands
; j
++)
4156 if (i
.types
[j
].bitfield
.inoutportreg
4157 || i
.types
[j
].bitfield
.shiftcount
4158 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4161 /* ImmExt should be processed after SSE2AVX. */
4162 if (!i
.tm
.opcode_modifier
.sse2avx
4163 && i
.tm
.opcode_modifier
.immext
)
4166 /* For insns with operands there are more diddles to do to the opcode. */
4169 if (!process_operands ())
4172 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4174 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4175 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4178 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4179 || is_evex_encoding (&i
.tm
))
4181 if (flag_code
== CODE_16BIT
)
4183 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4188 if (i
.tm
.opcode_modifier
.vex
)
4189 build_vex_prefix (t
);
4191 build_evex_prefix ();
4194 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4195 instructions may define INT_OPCODE as well, so avoid this corner
4196 case for those instructions that use MODRM. */
4197 if (i
.tm
.base_opcode
== INT_OPCODE
4198 && !i
.tm
.opcode_modifier
.modrm
4199 && i
.op
[0].imms
->X_add_number
== 3)
4201 i
.tm
.base_opcode
= INT3_OPCODE
;
4205 if ((i
.tm
.opcode_modifier
.jump
4206 || i
.tm
.opcode_modifier
.jumpbyte
4207 || i
.tm
.opcode_modifier
.jumpdword
)
4208 && i
.op
[0].disps
->X_op
== O_constant
)
4210 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4211 the absolute address given by the constant. Since ix86 jumps and
4212 calls are pc relative, we need to generate a reloc. */
4213 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4214 i
.op
[0].disps
->X_op
= O_symbol
;
4217 if (i
.tm
.opcode_modifier
.rex64
)
4220 /* For 8 bit registers we need an empty rex prefix. Also if the
4221 instruction already has a prefix, we need to convert old
4222 registers to new ones. */
4224 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4225 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4226 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4227 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4228 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4229 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4234 i
.rex
|= REX_OPCODE
;
4235 for (x
= 0; x
< 2; x
++)
4237 /* Look for 8 bit operand that uses old registers. */
4238 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4239 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4241 /* In case it is "hi" register, give up. */
4242 if (i
.op
[x
].regs
->reg_num
> 3)
4243 as_bad (_("can't encode register '%s%s' in an "
4244 "instruction requiring REX prefix."),
4245 register_prefix
, i
.op
[x
].regs
->reg_name
);
4247 /* Otherwise it is equivalent to the extended register.
4248 Since the encoding doesn't change this is merely
4249 cosmetic cleanup for debug output. */
4251 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4256 if (i
.rex
== 0 && i
.rex_encoding
)
4258 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4259 that uses legacy register. If it is "hi" register, don't add
4260 the REX_OPCODE byte. */
4262 for (x
= 0; x
< 2; x
++)
4263 if (i
.types
[x
].bitfield
.reg
4264 && i
.types
[x
].bitfield
.byte
4265 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4266 && i
.op
[x
].regs
->reg_num
> 3)
4268 i
.rex_encoding
= FALSE
;
4277 add_prefix (REX_OPCODE
| i
.rex
);
4279 /* We are ready to output the insn. */
4284 parse_insn (char *line
, char *mnemonic
)
4287 char *token_start
= l
;
4290 const insn_template
*t
;
4296 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4301 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4303 as_bad (_("no such instruction: `%s'"), token_start
);
4308 if (!is_space_char (*l
)
4309 && *l
!= END_OF_INSN
4311 || (*l
!= PREFIX_SEPARATOR
4314 as_bad (_("invalid character %s in mnemonic"),
4315 output_invalid (*l
));
4318 if (token_start
== l
)
4320 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4321 as_bad (_("expecting prefix; got nothing"));
4323 as_bad (_("expecting mnemonic; got nothing"));
4327 /* Look up instruction (or prefix) via hash table. */
4328 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4330 if (*l
!= END_OF_INSN
4331 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4332 && current_templates
4333 && current_templates
->start
->opcode_modifier
.isprefix
)
4335 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4337 as_bad ((flag_code
!= CODE_64BIT
4338 ? _("`%s' is only supported in 64-bit mode")
4339 : _("`%s' is not supported in 64-bit mode")),
4340 current_templates
->start
->name
);
4343 /* If we are in 16-bit mode, do not allow addr16 or data16.
4344 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4345 if ((current_templates
->start
->opcode_modifier
.size16
4346 || current_templates
->start
->opcode_modifier
.size32
)
4347 && flag_code
!= CODE_64BIT
4348 && (current_templates
->start
->opcode_modifier
.size32
4349 ^ (flag_code
== CODE_16BIT
)))
4351 as_bad (_("redundant %s prefix"),
4352 current_templates
->start
->name
);
4355 if (current_templates
->start
->opcode_length
== 0)
4357 /* Handle pseudo prefixes. */
4358 switch (current_templates
->start
->base_opcode
)
4362 i
.disp_encoding
= disp_encoding_8bit
;
4366 i
.disp_encoding
= disp_encoding_32bit
;
4370 i
.dir_encoding
= dir_encoding_load
;
4374 i
.dir_encoding
= dir_encoding_store
;
4378 i
.vec_encoding
= vex_encoding_vex2
;
4382 i
.vec_encoding
= vex_encoding_vex3
;
4386 i
.vec_encoding
= vex_encoding_evex
;
4390 i
.rex_encoding
= TRUE
;
4394 i
.no_optimize
= TRUE
;
4402 /* Add prefix, checking for repeated prefixes. */
4403 switch (add_prefix (current_templates
->start
->base_opcode
))
4408 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4409 i
.notrack_prefix
= current_templates
->start
->name
;
4412 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4413 i
.hle_prefix
= current_templates
->start
->name
;
4414 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4415 i
.bnd_prefix
= current_templates
->start
->name
;
4417 i
.rep_prefix
= current_templates
->start
->name
;
4423 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4430 if (!current_templates
)
4432 /* Check if we should swap operand or force 32bit displacement in
4434 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4435 i
.dir_encoding
= dir_encoding_store
;
4436 else if (mnem_p
- 3 == dot_p
4439 i
.disp_encoding
= disp_encoding_8bit
;
4440 else if (mnem_p
- 4 == dot_p
4444 i
.disp_encoding
= disp_encoding_32bit
;
4449 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4452 if (!current_templates
)
4455 /* See if we can get a match by trimming off a suffix. */
4458 case WORD_MNEM_SUFFIX
:
4459 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4460 i
.suffix
= SHORT_MNEM_SUFFIX
;
4463 case BYTE_MNEM_SUFFIX
:
4464 case QWORD_MNEM_SUFFIX
:
4465 i
.suffix
= mnem_p
[-1];
4467 current_templates
= (const templates
*) hash_find (op_hash
,
4470 case SHORT_MNEM_SUFFIX
:
4471 case LONG_MNEM_SUFFIX
:
4474 i
.suffix
= mnem_p
[-1];
4476 current_templates
= (const templates
*) hash_find (op_hash
,
4485 if (intel_float_operand (mnemonic
) == 1)
4486 i
.suffix
= SHORT_MNEM_SUFFIX
;
4488 i
.suffix
= LONG_MNEM_SUFFIX
;
4490 current_templates
= (const templates
*) hash_find (op_hash
,
4495 if (!current_templates
)
4497 as_bad (_("no such instruction: `%s'"), token_start
);
4502 if (current_templates
->start
->opcode_modifier
.jump
4503 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4505 /* Check for a branch hint. We allow ",pt" and ",pn" for
4506 predict taken and predict not taken respectively.
4507 I'm not sure that branch hints actually do anything on loop
4508 and jcxz insns (JumpByte) for current Pentium4 chips. They
4509 may work in the future and it doesn't hurt to accept them
4511 if (l
[0] == ',' && l
[1] == 'p')
4515 if (!add_prefix (DS_PREFIX_OPCODE
))
4519 else if (l
[2] == 'n')
4521 if (!add_prefix (CS_PREFIX_OPCODE
))
4527 /* Any other comma loses. */
4530 as_bad (_("invalid character %s in mnemonic"),
4531 output_invalid (*l
));
4535 /* Check if instruction is supported on specified architecture. */
4537 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4539 supported
|= cpu_flags_match (t
);
4540 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4542 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4543 as_warn (_("use .code16 to ensure correct addressing mode"));
4549 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4550 as_bad (flag_code
== CODE_64BIT
4551 ? _("`%s' is not supported in 64-bit mode")
4552 : _("`%s' is only supported in 64-bit mode"),
4553 current_templates
->start
->name
);
4555 as_bad (_("`%s' is not supported on `%s%s'"),
4556 current_templates
->start
->name
,
4557 cpu_arch_name
? cpu_arch_name
: default_arch
,
4558 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4564 parse_operands (char *l
, const char *mnemonic
)
4568 /* 1 if operand is pending after ','. */
4569 unsigned int expecting_operand
= 0;
4571 /* Non-zero if operand parens not balanced. */
4572 unsigned int paren_not_balanced
;
4574 while (*l
!= END_OF_INSN
)
4576 /* Skip optional white space before operand. */
4577 if (is_space_char (*l
))
4579 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4581 as_bad (_("invalid character %s before operand %d"),
4582 output_invalid (*l
),
4586 token_start
= l
; /* After white space. */
4587 paren_not_balanced
= 0;
4588 while (paren_not_balanced
|| *l
!= ',')
4590 if (*l
== END_OF_INSN
)
4592 if (paren_not_balanced
)
4595 as_bad (_("unbalanced parenthesis in operand %d."),
4598 as_bad (_("unbalanced brackets in operand %d."),
4603 break; /* we are done */
4605 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4607 as_bad (_("invalid character %s in operand %d"),
4608 output_invalid (*l
),
4615 ++paren_not_balanced
;
4617 --paren_not_balanced
;
4622 ++paren_not_balanced
;
4624 --paren_not_balanced
;
4628 if (l
!= token_start
)
4629 { /* Yes, we've read in another operand. */
4630 unsigned int operand_ok
;
4631 this_operand
= i
.operands
++;
4632 if (i
.operands
> MAX_OPERANDS
)
4634 as_bad (_("spurious operands; (%d operands/instruction max)"),
4638 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4639 /* Now parse operand adding info to 'i' as we go along. */
4640 END_STRING_AND_SAVE (l
);
4644 i386_intel_operand (token_start
,
4645 intel_float_operand (mnemonic
));
4647 operand_ok
= i386_att_operand (token_start
);
4649 RESTORE_END_STRING (l
);
4655 if (expecting_operand
)
4657 expecting_operand_after_comma
:
4658 as_bad (_("expecting operand after ','; got nothing"));
4663 as_bad (_("expecting operand before ','; got nothing"));
4668 /* Now *l must be either ',' or END_OF_INSN. */
4671 if (*++l
== END_OF_INSN
)
4673 /* Just skip it, if it's \n complain. */
4674 goto expecting_operand_after_comma
;
4676 expecting_operand
= 1;
4683 swap_2_operands (int xchg1
, int xchg2
)
4685 union i386_op temp_op
;
4686 i386_operand_type temp_type
;
4687 enum bfd_reloc_code_real temp_reloc
;
4689 temp_type
= i
.types
[xchg2
];
4690 i
.types
[xchg2
] = i
.types
[xchg1
];
4691 i
.types
[xchg1
] = temp_type
;
4692 temp_op
= i
.op
[xchg2
];
4693 i
.op
[xchg2
] = i
.op
[xchg1
];
4694 i
.op
[xchg1
] = temp_op
;
4695 temp_reloc
= i
.reloc
[xchg2
];
4696 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4697 i
.reloc
[xchg1
] = temp_reloc
;
4701 if (i
.mask
->operand
== xchg1
)
4702 i
.mask
->operand
= xchg2
;
4703 else if (i
.mask
->operand
== xchg2
)
4704 i
.mask
->operand
= xchg1
;
4708 if (i
.broadcast
->operand
== xchg1
)
4709 i
.broadcast
->operand
= xchg2
;
4710 else if (i
.broadcast
->operand
== xchg2
)
4711 i
.broadcast
->operand
= xchg1
;
4715 if (i
.rounding
->operand
== xchg1
)
4716 i
.rounding
->operand
= xchg2
;
4717 else if (i
.rounding
->operand
== xchg2
)
4718 i
.rounding
->operand
= xchg1
;
4723 swap_operands (void)
4729 swap_2_operands (1, i
.operands
- 2);
4733 swap_2_operands (0, i
.operands
- 1);
4739 if (i
.mem_operands
== 2)
4741 const seg_entry
*temp_seg
;
4742 temp_seg
= i
.seg
[0];
4743 i
.seg
[0] = i
.seg
[1];
4744 i
.seg
[1] = temp_seg
;
4748 /* Try to ensure constant immediates are represented in the smallest
4753 char guess_suffix
= 0;
4757 guess_suffix
= i
.suffix
;
4758 else if (i
.reg_operands
)
4760 /* Figure out a suffix from the last register operand specified.
4761 We can't do this properly yet, ie. excluding InOutPortReg,
4762 but the following works for instructions with immediates.
4763 In any case, we can't set i.suffix yet. */
4764 for (op
= i
.operands
; --op
>= 0;)
4765 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4767 guess_suffix
= BYTE_MNEM_SUFFIX
;
4770 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4772 guess_suffix
= WORD_MNEM_SUFFIX
;
4775 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4777 guess_suffix
= LONG_MNEM_SUFFIX
;
4780 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4782 guess_suffix
= QWORD_MNEM_SUFFIX
;
4786 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4787 guess_suffix
= WORD_MNEM_SUFFIX
;
4789 for (op
= i
.operands
; --op
>= 0;)
4790 if (operand_type_check (i
.types
[op
], imm
))
4792 switch (i
.op
[op
].imms
->X_op
)
4795 /* If a suffix is given, this operand may be shortened. */
4796 switch (guess_suffix
)
4798 case LONG_MNEM_SUFFIX
:
4799 i
.types
[op
].bitfield
.imm32
= 1;
4800 i
.types
[op
].bitfield
.imm64
= 1;
4802 case WORD_MNEM_SUFFIX
:
4803 i
.types
[op
].bitfield
.imm16
= 1;
4804 i
.types
[op
].bitfield
.imm32
= 1;
4805 i
.types
[op
].bitfield
.imm32s
= 1;
4806 i
.types
[op
].bitfield
.imm64
= 1;
4808 case BYTE_MNEM_SUFFIX
:
4809 i
.types
[op
].bitfield
.imm8
= 1;
4810 i
.types
[op
].bitfield
.imm8s
= 1;
4811 i
.types
[op
].bitfield
.imm16
= 1;
4812 i
.types
[op
].bitfield
.imm32
= 1;
4813 i
.types
[op
].bitfield
.imm32s
= 1;
4814 i
.types
[op
].bitfield
.imm64
= 1;
4818 /* If this operand is at most 16 bits, convert it
4819 to a signed 16 bit number before trying to see
4820 whether it will fit in an even smaller size.
4821 This allows a 16-bit operand such as $0xffe0 to
4822 be recognised as within Imm8S range. */
4823 if ((i
.types
[op
].bitfield
.imm16
)
4824 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4826 i
.op
[op
].imms
->X_add_number
=
4827 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4830 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4831 if ((i
.types
[op
].bitfield
.imm32
)
4832 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4835 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4836 ^ ((offsetT
) 1 << 31))
4837 - ((offsetT
) 1 << 31));
4841 = operand_type_or (i
.types
[op
],
4842 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4844 /* We must avoid matching of Imm32 templates when 64bit
4845 only immediate is available. */
4846 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4847 i
.types
[op
].bitfield
.imm32
= 0;
4854 /* Symbols and expressions. */
4856 /* Convert symbolic operand to proper sizes for matching, but don't
4857 prevent matching a set of insns that only supports sizes other
4858 than those matching the insn suffix. */
4860 i386_operand_type mask
, allowed
;
4861 const insn_template
*t
;
4863 operand_type_set (&mask
, 0);
4864 operand_type_set (&allowed
, 0);
4866 for (t
= current_templates
->start
;
4867 t
< current_templates
->end
;
4869 allowed
= operand_type_or (allowed
,
4870 t
->operand_types
[op
]);
4871 switch (guess_suffix
)
4873 case QWORD_MNEM_SUFFIX
:
4874 mask
.bitfield
.imm64
= 1;
4875 mask
.bitfield
.imm32s
= 1;
4877 case LONG_MNEM_SUFFIX
:
4878 mask
.bitfield
.imm32
= 1;
4880 case WORD_MNEM_SUFFIX
:
4881 mask
.bitfield
.imm16
= 1;
4883 case BYTE_MNEM_SUFFIX
:
4884 mask
.bitfield
.imm8
= 1;
4889 allowed
= operand_type_and (mask
, allowed
);
4890 if (!operand_type_all_zero (&allowed
))
4891 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4898 /* Try to use the smallest displacement type too. */
4900 optimize_disp (void)
4904 for (op
= i
.operands
; --op
>= 0;)
4905 if (operand_type_check (i
.types
[op
], disp
))
4907 if (i
.op
[op
].disps
->X_op
== O_constant
)
4909 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4911 if (i
.types
[op
].bitfield
.disp16
4912 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4914 /* If this operand is at most 16 bits, convert
4915 to a signed 16 bit number and don't use 64bit
4917 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4918 i
.types
[op
].bitfield
.disp64
= 0;
4921 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4922 if (i
.types
[op
].bitfield
.disp32
4923 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4925 /* If this operand is at most 32 bits, convert
4926 to a signed 32 bit number and don't use 64bit
4928 op_disp
&= (((offsetT
) 2 << 31) - 1);
4929 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4930 i
.types
[op
].bitfield
.disp64
= 0;
4933 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4935 i
.types
[op
].bitfield
.disp8
= 0;
4936 i
.types
[op
].bitfield
.disp16
= 0;
4937 i
.types
[op
].bitfield
.disp32
= 0;
4938 i
.types
[op
].bitfield
.disp32s
= 0;
4939 i
.types
[op
].bitfield
.disp64
= 0;
4943 else if (flag_code
== CODE_64BIT
)
4945 if (fits_in_signed_long (op_disp
))
4947 i
.types
[op
].bitfield
.disp64
= 0;
4948 i
.types
[op
].bitfield
.disp32s
= 1;
4950 if (i
.prefix
[ADDR_PREFIX
]
4951 && fits_in_unsigned_long (op_disp
))
4952 i
.types
[op
].bitfield
.disp32
= 1;
4954 if ((i
.types
[op
].bitfield
.disp32
4955 || i
.types
[op
].bitfield
.disp32s
4956 || i
.types
[op
].bitfield
.disp16
)
4957 && fits_in_disp8 (op_disp
))
4958 i
.types
[op
].bitfield
.disp8
= 1;
4960 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4961 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4963 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4964 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4965 i
.types
[op
].bitfield
.disp8
= 0;
4966 i
.types
[op
].bitfield
.disp16
= 0;
4967 i
.types
[op
].bitfield
.disp32
= 0;
4968 i
.types
[op
].bitfield
.disp32s
= 0;
4969 i
.types
[op
].bitfield
.disp64
= 0;
4972 /* We only support 64bit displacement on constants. */
4973 i
.types
[op
].bitfield
.disp64
= 0;
4977 /* Check if operands are valid for the instruction. */
4980 check_VecOperands (const insn_template
*t
)
4984 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
4986 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4987 any one operand are implicity requiring AVX512VL support if the actual
4988 operand size is YMMword or XMMword. Since this function runs after
4989 template matching, there's no need to check for YMMword/XMMword in
4991 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
4992 if (!cpu_flags_all_zero (&cpu
)
4993 && !t
->cpu_flags
.bitfield
.cpuavx512vl
4994 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
4996 for (op
= 0; op
< t
->operands
; ++op
)
4998 if (t
->operand_types
[op
].bitfield
.zmmword
4999 && (i
.types
[op
].bitfield
.ymmword
5000 || i
.types
[op
].bitfield
.xmmword
))
5002 i
.error
= unsupported
;
5008 /* Without VSIB byte, we can't have a vector register for index. */
5009 if (!t
->opcode_modifier
.vecsib
5011 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5012 || i
.index_reg
->reg_type
.bitfield
.ymmword
5013 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5015 i
.error
= unsupported_vector_index_register
;
5019 /* Check if default mask is allowed. */
5020 if (t
->opcode_modifier
.nodefmask
5021 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5023 i
.error
= no_default_mask
;
5027 /* For VSIB byte, we need a vector register for index, and all vector
5028 registers must be distinct. */
5029 if (t
->opcode_modifier
.vecsib
)
5032 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5033 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5034 || (t
->opcode_modifier
.vecsib
== VecSIB256
5035 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5036 || (t
->opcode_modifier
.vecsib
== VecSIB512
5037 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5039 i
.error
= invalid_vsib_address
;
5043 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5044 if (i
.reg_operands
== 2 && !i
.mask
)
5046 gas_assert (i
.types
[0].bitfield
.regsimd
);
5047 gas_assert (i
.types
[0].bitfield
.xmmword
5048 || i
.types
[0].bitfield
.ymmword
);
5049 gas_assert (i
.types
[2].bitfield
.regsimd
);
5050 gas_assert (i
.types
[2].bitfield
.xmmword
5051 || i
.types
[2].bitfield
.ymmword
);
5052 if (operand_check
== check_none
)
5054 if (register_number (i
.op
[0].regs
)
5055 != register_number (i
.index_reg
)
5056 && register_number (i
.op
[2].regs
)
5057 != register_number (i
.index_reg
)
5058 && register_number (i
.op
[0].regs
)
5059 != register_number (i
.op
[2].regs
))
5061 if (operand_check
== check_error
)
5063 i
.error
= invalid_vector_register_set
;
5066 as_warn (_("mask, index, and destination registers should be distinct"));
5068 else if (i
.reg_operands
== 1 && i
.mask
)
5070 if (i
.types
[1].bitfield
.regsimd
5071 && (i
.types
[1].bitfield
.xmmword
5072 || i
.types
[1].bitfield
.ymmword
5073 || i
.types
[1].bitfield
.zmmword
)
5074 && (register_number (i
.op
[1].regs
)
5075 == register_number (i
.index_reg
)))
5077 if (operand_check
== check_error
)
5079 i
.error
= invalid_vector_register_set
;
5082 if (operand_check
!= check_none
)
5083 as_warn (_("index and destination registers should be distinct"));
5088 /* Check if broadcast is supported by the instruction and is applied
5089 to the memory operand. */
5092 i386_operand_type type
, overlap
;
5094 /* Check if specified broadcast is supported in this instruction,
5095 and it's applied to memory operand of DWORD or QWORD type. */
5096 op
= i
.broadcast
->operand
;
5097 if (!t
->opcode_modifier
.broadcast
5098 || !i
.types
[op
].bitfield
.mem
5099 || (!i
.types
[op
].bitfield
.unspecified
5100 && (t
->operand_types
[op
].bitfield
.dword
5101 ? !i
.types
[op
].bitfield
.dword
5102 : !i
.types
[op
].bitfield
.qword
)))
5105 i
.error
= unsupported_broadcast
;
5109 operand_type_set (&type
, 0);
5110 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5113 type
.bitfield
.qword
= 1;
5116 type
.bitfield
.xmmword
= 1;
5119 type
.bitfield
.ymmword
= 1;
5122 type
.bitfield
.zmmword
= 1;
5128 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5129 if (operand_type_all_zero (&overlap
))
5132 if (t
->opcode_modifier
.checkregsize
)
5136 type
.bitfield
.baseindex
= 1;
5137 for (j
= 0; j
< i
.operands
; ++j
)
5140 && !operand_type_register_match(i
.types
[j
],
5141 t
->operand_types
[j
],
5143 t
->operand_types
[op
]))
5148 /* If broadcast is supported in this instruction, we need to check if
5149 operand of one-element size isn't specified without broadcast. */
5150 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5152 /* Find memory operand. */
5153 for (op
= 0; op
< i
.operands
; op
++)
5154 if (operand_type_check (i
.types
[op
], anymem
))
5156 gas_assert (op
< i
.operands
);
5157 /* Check size of the memory operand. */
5158 if (t
->operand_types
[op
].bitfield
.dword
5159 ? i
.types
[op
].bitfield
.dword
5160 : i
.types
[op
].bitfield
.qword
)
5162 i
.error
= broadcast_needed
;
5167 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5169 /* Check if requested masking is supported. */
5171 && (!t
->opcode_modifier
.masking
5173 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5175 i
.error
= unsupported_masking
;
5179 /* Check if masking is applied to dest operand. */
5180 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5182 i
.error
= mask_not_on_destination
;
5189 if ((i
.rounding
->type
!= saeonly
5190 && !t
->opcode_modifier
.staticrounding
)
5191 || (i
.rounding
->type
== saeonly
5192 && (t
->opcode_modifier
.staticrounding
5193 || !t
->opcode_modifier
.sae
)))
5195 i
.error
= unsupported_rc_sae
;
5198 /* If the instruction has several immediate operands and one of
5199 them is rounding, the rounding operand should be the last
5200 immediate operand. */
5201 if (i
.imm_operands
> 1
5202 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5204 i
.error
= rc_sae_operand_not_last_imm
;
5209 /* Check vector Disp8 operand. */
5210 if (t
->opcode_modifier
.disp8memshift
5211 && i
.disp_encoding
!= disp_encoding_32bit
)
5214 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5216 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5218 for (op
= 0; op
< i
.operands
; op
++)
5219 if (operand_type_check (i
.types
[op
], disp
)
5220 && i
.op
[op
].disps
->X_op
== O_constant
)
5222 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5224 i
.types
[op
].bitfield
.disp8
= 1;
5227 i
.types
[op
].bitfield
.disp8
= 0;
5236 /* Check if operands are valid for the instruction. Update VEX
5240 VEX_check_operands (const insn_template
*t
)
5242 if (i
.vec_encoding
== vex_encoding_evex
)
5244 /* This instruction must be encoded with EVEX prefix. */
5245 if (!is_evex_encoding (t
))
5247 i
.error
= unsupported
;
5253 if (!t
->opcode_modifier
.vex
)
5255 /* This instruction template doesn't have VEX prefix. */
5256 if (i
.vec_encoding
!= vex_encoding_default
)
5258 i
.error
= unsupported
;
5264 /* Only check VEX_Imm4, which must be the first operand. */
5265 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5267 if (i
.op
[0].imms
->X_op
!= O_constant
5268 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5274 /* Turn off Imm8 so that update_imm won't complain. */
5275 i
.types
[0] = vec_imm4
;
5281 static const insn_template
*
5282 match_template (char mnem_suffix
)
5284 /* Points to template once we've found it. */
5285 const insn_template
*t
;
5286 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5287 i386_operand_type overlap4
;
5288 unsigned int found_reverse_match
;
5289 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5290 i386_operand_type operand_types
[MAX_OPERANDS
];
5291 int addr_prefix_disp
;
5293 unsigned int found_cpu_match
;
5294 unsigned int check_register
;
5295 enum i386_error specific_error
= 0;
5297 #if MAX_OPERANDS != 5
5298 # error "MAX_OPERANDS must be 5."
5301 found_reverse_match
= 0;
5302 addr_prefix_disp
= -1;
5304 memset (&suffix_check
, 0, sizeof (suffix_check
));
5305 if (intel_syntax
&& i
.broadcast
)
5307 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5308 suffix_check
.no_bsuf
= 1;
5309 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5310 suffix_check
.no_wsuf
= 1;
5311 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5312 suffix_check
.no_ssuf
= 1;
5313 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5314 suffix_check
.no_lsuf
= 1;
5315 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5316 suffix_check
.no_qsuf
= 1;
5317 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5318 suffix_check
.no_ldsuf
= 1;
5320 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5323 switch (mnem_suffix
)
5325 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5326 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5327 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5328 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5329 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5333 /* Must have right number of operands. */
5334 i
.error
= number_of_operands_mismatch
;
5336 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5338 addr_prefix_disp
= -1;
5340 if (i
.operands
!= t
->operands
)
5343 /* Check processor support. */
5344 i
.error
= unsupported
;
5345 found_cpu_match
= (cpu_flags_match (t
)
5346 == CPU_FLAGS_PERFECT_MATCH
);
5347 if (!found_cpu_match
)
5350 /* Check AT&T mnemonic. */
5351 i
.error
= unsupported_with_intel_mnemonic
;
5352 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5355 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5356 i
.error
= unsupported_syntax
;
5357 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5358 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5359 || (intel64
&& t
->opcode_modifier
.amd64
)
5360 || (!intel64
&& t
->opcode_modifier
.intel64
))
5363 /* Check the suffix, except for some instructions in intel mode. */
5364 i
.error
= invalid_instruction_suffix
;
5365 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5366 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5367 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5368 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5369 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5370 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5371 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5373 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5374 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5375 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5376 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5377 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5378 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5379 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5382 if (!operand_size_match (t
))
5385 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5386 operand_types
[j
] = t
->operand_types
[j
];
5388 /* In general, don't allow 64-bit operands in 32-bit mode. */
5389 if (i
.suffix
== QWORD_MNEM_SUFFIX
5390 && flag_code
!= CODE_64BIT
5392 ? (!t
->opcode_modifier
.ignoresize
5393 && !intel_float_operand (t
->name
))
5394 : intel_float_operand (t
->name
) != 2)
5395 && ((!operand_types
[0].bitfield
.regmmx
5396 && !operand_types
[0].bitfield
.regsimd
)
5397 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5398 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5399 && (t
->base_opcode
!= 0x0fc7
5400 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5403 /* In general, don't allow 32-bit operands on pre-386. */
5404 else if (i
.suffix
== LONG_MNEM_SUFFIX
5405 && !cpu_arch_flags
.bitfield
.cpui386
5407 ? (!t
->opcode_modifier
.ignoresize
5408 && !intel_float_operand (t
->name
))
5409 : intel_float_operand (t
->name
) != 2)
5410 && ((!operand_types
[0].bitfield
.regmmx
5411 && !operand_types
[0].bitfield
.regsimd
)
5412 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5413 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5416 /* Do not verify operands when there are none. */
5420 /* We've found a match; break out of loop. */
5424 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5425 into Disp32/Disp16/Disp32 operand. */
5426 if (i
.prefix
[ADDR_PREFIX
] != 0)
5428 /* There should be only one Disp operand. */
5432 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5434 if (operand_types
[j
].bitfield
.disp16
)
5436 addr_prefix_disp
= j
;
5437 operand_types
[j
].bitfield
.disp32
= 1;
5438 operand_types
[j
].bitfield
.disp16
= 0;
5444 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5446 if (operand_types
[j
].bitfield
.disp32
)
5448 addr_prefix_disp
= j
;
5449 operand_types
[j
].bitfield
.disp32
= 0;
5450 operand_types
[j
].bitfield
.disp16
= 1;
5456 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5458 if (operand_types
[j
].bitfield
.disp64
)
5460 addr_prefix_disp
= j
;
5461 operand_types
[j
].bitfield
.disp64
= 0;
5462 operand_types
[j
].bitfield
.disp32
= 1;
5470 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5471 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5474 /* We check register size if needed. */
5475 if (t
->opcode_modifier
.checkregsize
)
5477 check_register
= (1 << t
->operands
) - 1;
5479 check_register
&= ~(1 << i
.broadcast
->operand
);
5484 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5485 switch (t
->operands
)
5488 if (!operand_type_match (overlap0
, i
.types
[0]))
5492 /* xchg %eax, %eax is a special case. It is an alias for nop
5493 only in 32bit mode and we can use opcode 0x90. In 64bit
5494 mode, we can't use 0x90 for xchg %eax, %eax since it should
5495 zero-extend %eax to %rax. */
5496 if (flag_code
== CODE_64BIT
5497 && t
->base_opcode
== 0x90
5498 && operand_type_equal (&i
.types
[0], &acc32
)
5499 && operand_type_equal (&i
.types
[1], &acc32
))
5501 /* xrelease mov %eax, <disp> is another special case. It must not
5502 match the accumulator-only encoding of mov. */
5503 if (flag_code
!= CODE_64BIT
5505 && t
->base_opcode
== 0xa0
5506 && i
.types
[0].bitfield
.acc
5507 && operand_type_check (i
.types
[1], anymem
))
5509 /* If we want store form, we reverse direction of operands. */
5510 if (i
.dir_encoding
== dir_encoding_store
5511 && t
->opcode_modifier
.d
)
5516 /* If we want store form, we skip the current load. */
5517 if (i
.dir_encoding
== dir_encoding_store
5518 && i
.mem_operands
== 0
5519 && t
->opcode_modifier
.load
)
5524 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5525 if (!operand_type_match (overlap0
, i
.types
[0])
5526 || !operand_type_match (overlap1
, i
.types
[1])
5527 || ((check_register
& 3) == 3
5528 && !operand_type_register_match (i
.types
[0],
5533 /* Check if other direction is valid ... */
5534 if (!t
->opcode_modifier
.d
)
5538 /* Try reversing direction of operands. */
5539 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5540 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5541 if (!operand_type_match (overlap0
, i
.types
[0])
5542 || !operand_type_match (overlap1
, i
.types
[1])
5544 && !operand_type_register_match (i
.types
[0],
5549 /* Does not match either direction. */
5552 /* found_reverse_match holds which of D or FloatR
5554 if (!t
->opcode_modifier
.d
)
5555 found_reverse_match
= 0;
5556 else if (operand_types
[0].bitfield
.tbyte
)
5557 found_reverse_match
= Opcode_FloatD
;
5559 found_reverse_match
= Opcode_D
;
5560 if (t
->opcode_modifier
.floatr
)
5561 found_reverse_match
|= Opcode_FloatR
;
5565 /* Found a forward 2 operand match here. */
5566 switch (t
->operands
)
5569 overlap4
= operand_type_and (i
.types
[4],
5573 overlap3
= operand_type_and (i
.types
[3],
5577 overlap2
= operand_type_and (i
.types
[2],
5582 switch (t
->operands
)
5585 if (!operand_type_match (overlap4
, i
.types
[4])
5586 || !operand_type_register_match (i
.types
[3],
5593 if (!operand_type_match (overlap3
, i
.types
[3])
5594 || ((check_register
& 0xa) == 0xa
5595 && !operand_type_register_match (i
.types
[1],
5599 || ((check_register
& 0xc) == 0xc
5600 && !operand_type_register_match (i
.types
[2],
5607 /* Here we make use of the fact that there are no
5608 reverse match 3 operand instructions. */
5609 if (!operand_type_match (overlap2
, i
.types
[2])
5610 || ((check_register
& 5) == 5
5611 && !operand_type_register_match (i
.types
[0],
5615 || ((check_register
& 6) == 6
5616 && !operand_type_register_match (i
.types
[1],
5624 /* Found either forward/reverse 2, 3 or 4 operand match here:
5625 slip through to break. */
5627 if (!found_cpu_match
)
5629 found_reverse_match
= 0;
5633 /* Check if vector and VEX operands are valid. */
5634 if (check_VecOperands (t
) || VEX_check_operands (t
))
5636 specific_error
= i
.error
;
5640 /* We've found a match; break out of loop. */
5644 if (t
== current_templates
->end
)
5646 /* We found no match. */
5647 const char *err_msg
;
5648 switch (specific_error
? specific_error
: i
.error
)
5652 case operand_size_mismatch
:
5653 err_msg
= _("operand size mismatch");
5655 case operand_type_mismatch
:
5656 err_msg
= _("operand type mismatch");
5658 case register_type_mismatch
:
5659 err_msg
= _("register type mismatch");
5661 case number_of_operands_mismatch
:
5662 err_msg
= _("number of operands mismatch");
5664 case invalid_instruction_suffix
:
5665 err_msg
= _("invalid instruction suffix");
5668 err_msg
= _("constant doesn't fit in 4 bits");
5670 case unsupported_with_intel_mnemonic
:
5671 err_msg
= _("unsupported with Intel mnemonic");
5673 case unsupported_syntax
:
5674 err_msg
= _("unsupported syntax");
5677 as_bad (_("unsupported instruction `%s'"),
5678 current_templates
->start
->name
);
5680 case invalid_vsib_address
:
5681 err_msg
= _("invalid VSIB address");
5683 case invalid_vector_register_set
:
5684 err_msg
= _("mask, index, and destination registers must be distinct");
5686 case unsupported_vector_index_register
:
5687 err_msg
= _("unsupported vector index register");
5689 case unsupported_broadcast
:
5690 err_msg
= _("unsupported broadcast");
5692 case broadcast_not_on_src_operand
:
5693 err_msg
= _("broadcast not on source memory operand");
5695 case broadcast_needed
:
5696 err_msg
= _("broadcast is needed for operand of such type");
5698 case unsupported_masking
:
5699 err_msg
= _("unsupported masking");
5701 case mask_not_on_destination
:
5702 err_msg
= _("mask not on destination operand");
5704 case no_default_mask
:
5705 err_msg
= _("default mask isn't allowed");
5707 case unsupported_rc_sae
:
5708 err_msg
= _("unsupported static rounding/sae");
5710 case rc_sae_operand_not_last_imm
:
5712 err_msg
= _("RC/SAE operand must precede immediate operands");
5714 err_msg
= _("RC/SAE operand must follow immediate operands");
5716 case invalid_register_operand
:
5717 err_msg
= _("invalid register operand");
5720 as_bad (_("%s for `%s'"), err_msg
,
5721 current_templates
->start
->name
);
5725 if (!quiet_warnings
)
5728 && (i
.types
[0].bitfield
.jumpabsolute
5729 != operand_types
[0].bitfield
.jumpabsolute
))
5731 as_warn (_("indirect %s without `*'"), t
->name
);
5734 if (t
->opcode_modifier
.isprefix
5735 && t
->opcode_modifier
.ignoresize
)
5737 /* Warn them that a data or address size prefix doesn't
5738 affect assembly of the next line of code. */
5739 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5743 /* Copy the template we found. */
5746 if (addr_prefix_disp
!= -1)
5747 i
.tm
.operand_types
[addr_prefix_disp
]
5748 = operand_types
[addr_prefix_disp
];
5750 if (found_reverse_match
)
5752 /* If we found a reverse match we must alter the opcode
5753 direction bit. found_reverse_match holds bits to change
5754 (different for int & float insns). */
5756 i
.tm
.base_opcode
^= found_reverse_match
;
5758 i
.tm
.operand_types
[0] = operand_types
[1];
5759 i
.tm
.operand_types
[1] = operand_types
[0];
5768 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5769 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5771 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5773 as_bad (_("`%s' operand %d must use `%ses' segment"),
5779 /* There's only ever one segment override allowed per instruction.
5780 This instruction possibly has a legal segment override on the
5781 second operand, so copy the segment to where non-string
5782 instructions store it, allowing common code. */
5783 i
.seg
[0] = i
.seg
[1];
5785 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5787 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5789 as_bad (_("`%s' operand %d must use `%ses' segment"),
5800 process_suffix (void)
5802 /* If matched instruction specifies an explicit instruction mnemonic
5804 if (i
.tm
.opcode_modifier
.size16
)
5805 i
.suffix
= WORD_MNEM_SUFFIX
;
5806 else if (i
.tm
.opcode_modifier
.size32
)
5807 i
.suffix
= LONG_MNEM_SUFFIX
;
5808 else if (i
.tm
.opcode_modifier
.size64
)
5809 i
.suffix
= QWORD_MNEM_SUFFIX
;
5810 else if (i
.reg_operands
)
5812 /* If there's no instruction mnemonic suffix we try to invent one
5813 based on register operands. */
5816 /* We take i.suffix from the last register operand specified,
5817 Destination register type is more significant than source
5818 register type. crc32 in SSE4.2 prefers source register
5820 if (i
.tm
.base_opcode
== 0xf20f38f1)
5822 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5823 i
.suffix
= WORD_MNEM_SUFFIX
;
5824 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5825 i
.suffix
= LONG_MNEM_SUFFIX
;
5826 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5827 i
.suffix
= QWORD_MNEM_SUFFIX
;
5829 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5831 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5832 i
.suffix
= BYTE_MNEM_SUFFIX
;
5839 if (i
.tm
.base_opcode
== 0xf20f38f1
5840 || i
.tm
.base_opcode
== 0xf20f38f0)
5842 /* We have to know the operand size for crc32. */
5843 as_bad (_("ambiguous memory operand size for `%s`"),
5848 for (op
= i
.operands
; --op
>= 0;)
5849 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5850 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5852 if (!i
.types
[op
].bitfield
.reg
)
5854 if (i
.types
[op
].bitfield
.byte
)
5855 i
.suffix
= BYTE_MNEM_SUFFIX
;
5856 else if (i
.types
[op
].bitfield
.word
)
5857 i
.suffix
= WORD_MNEM_SUFFIX
;
5858 else if (i
.types
[op
].bitfield
.dword
)
5859 i
.suffix
= LONG_MNEM_SUFFIX
;
5860 else if (i
.types
[op
].bitfield
.qword
)
5861 i
.suffix
= QWORD_MNEM_SUFFIX
;
5868 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5871 && i
.tm
.opcode_modifier
.ignoresize
5872 && i
.tm
.opcode_modifier
.no_bsuf
)
5874 else if (!check_byte_reg ())
5877 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5880 && i
.tm
.opcode_modifier
.ignoresize
5881 && i
.tm
.opcode_modifier
.no_lsuf
5882 && !i
.tm
.opcode_modifier
.todword
5883 && !i
.tm
.opcode_modifier
.toqword
)
5885 else if (!check_long_reg ())
5888 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5891 && i
.tm
.opcode_modifier
.ignoresize
5892 && i
.tm
.opcode_modifier
.no_qsuf
5893 && !i
.tm
.opcode_modifier
.todword
5894 && !i
.tm
.opcode_modifier
.toqword
)
5896 else if (!check_qword_reg ())
5899 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5902 && i
.tm
.opcode_modifier
.ignoresize
5903 && i
.tm
.opcode_modifier
.no_wsuf
)
5905 else if (!check_word_reg ())
5908 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5909 /* Do nothing if the instruction is going to ignore the prefix. */
5914 else if (i
.tm
.opcode_modifier
.defaultsize
5916 /* exclude fldenv/frstor/fsave/fstenv */
5917 && i
.tm
.opcode_modifier
.no_ssuf
)
5919 i
.suffix
= stackop_size
;
5921 else if (intel_syntax
5923 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5924 || i
.tm
.opcode_modifier
.jumpbyte
5925 || i
.tm
.opcode_modifier
.jumpintersegment
5926 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5927 && i
.tm
.extension_opcode
<= 3)))
5932 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5934 i
.suffix
= QWORD_MNEM_SUFFIX
;
5939 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5940 i
.suffix
= LONG_MNEM_SUFFIX
;
5943 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5944 i
.suffix
= WORD_MNEM_SUFFIX
;
5953 if (i
.tm
.opcode_modifier
.w
)
5955 as_bad (_("no instruction mnemonic suffix given and "
5956 "no register operands; can't size instruction"));
5962 unsigned int suffixes
;
5964 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5965 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5967 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5969 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5971 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5973 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5976 /* There are more than suffix matches. */
5977 if (i
.tm
.opcode_modifier
.w
5978 || ((suffixes
& (suffixes
- 1))
5979 && !i
.tm
.opcode_modifier
.defaultsize
5980 && !i
.tm
.opcode_modifier
.ignoresize
))
5982 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5988 /* Change the opcode based on the operand size given by i.suffix. */
5991 /* Size floating point instruction. */
5992 case LONG_MNEM_SUFFIX
:
5993 if (i
.tm
.opcode_modifier
.floatmf
)
5995 i
.tm
.base_opcode
^= 4;
5999 case WORD_MNEM_SUFFIX
:
6000 case QWORD_MNEM_SUFFIX
:
6001 /* It's not a byte, select word/dword operation. */
6002 if (i
.tm
.opcode_modifier
.w
)
6004 if (i
.tm
.opcode_modifier
.shortform
)
6005 i
.tm
.base_opcode
|= 8;
6007 i
.tm
.base_opcode
|= 1;
6010 case SHORT_MNEM_SUFFIX
:
6011 /* Now select between word & dword operations via the operand
6012 size prefix, except for instructions that will ignore this
6014 if (i
.reg_operands
> 0
6015 && i
.types
[0].bitfield
.reg
6016 && i
.tm
.opcode_modifier
.addrprefixopreg
6017 && (i
.tm
.opcode_modifier
.immext
6018 || i
.operands
== 1))
6020 /* The address size override prefix changes the size of the
6022 if ((flag_code
== CODE_32BIT
6023 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6024 || (flag_code
!= CODE_32BIT
6025 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6026 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6029 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6030 && !i
.tm
.opcode_modifier
.ignoresize
6031 && !i
.tm
.opcode_modifier
.floatmf
6032 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6033 || (flag_code
== CODE_64BIT
6034 && i
.tm
.opcode_modifier
.jumpbyte
)))
6036 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6038 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6039 prefix
= ADDR_PREFIX_OPCODE
;
6041 if (!add_prefix (prefix
))
6045 /* Set mode64 for an operand. */
6046 if (i
.suffix
== QWORD_MNEM_SUFFIX
6047 && flag_code
== CODE_64BIT
6048 && !i
.tm
.opcode_modifier
.norex64
6049 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6051 && ! (i
.operands
== 2
6052 && i
.tm
.base_opcode
== 0x90
6053 && i
.tm
.extension_opcode
== None
6054 && operand_type_equal (&i
.types
[0], &acc64
)
6055 && operand_type_equal (&i
.types
[1], &acc64
)))
6061 if (i
.reg_operands
!= 0
6063 && i
.tm
.opcode_modifier
.addrprefixopreg
6064 && !i
.tm
.opcode_modifier
.immext
)
6066 /* Check invalid register operand when the address size override
6067 prefix changes the size of register operands. */
6069 enum { need_word
, need_dword
, need_qword
} need
;
6071 if (flag_code
== CODE_32BIT
)
6072 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6075 if (i
.prefix
[ADDR_PREFIX
])
6078 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6081 for (op
= 0; op
< i
.operands
; op
++)
6082 if (i
.types
[op
].bitfield
.reg
6083 && ((need
== need_word
6084 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6085 || (need
== need_dword
6086 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6087 || (need
== need_qword
6088 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6090 as_bad (_("invalid register operand size for `%s'"),
6100 check_byte_reg (void)
6104 for (op
= i
.operands
; --op
>= 0;)
6106 /* Skip non-register operands. */
6107 if (!i
.types
[op
].bitfield
.reg
)
6110 /* If this is an eight bit register, it's OK. If it's the 16 or
6111 32 bit version of an eight bit register, we will just use the
6112 low portion, and that's OK too. */
6113 if (i
.types
[op
].bitfield
.byte
)
6116 /* I/O port address operands are OK too. */
6117 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6120 /* crc32 doesn't generate this warning. */
6121 if (i
.tm
.base_opcode
== 0xf20f38f0)
6124 if ((i
.types
[op
].bitfield
.word
6125 || i
.types
[op
].bitfield
.dword
6126 || i
.types
[op
].bitfield
.qword
)
6127 && i
.op
[op
].regs
->reg_num
< 4
6128 /* Prohibit these changes in 64bit mode, since the lowering
6129 would be more complicated. */
6130 && flag_code
!= CODE_64BIT
)
6132 #if REGISTER_WARNINGS
6133 if (!quiet_warnings
)
6134 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6136 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6137 ? REGNAM_AL
- REGNAM_AX
6138 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6140 i
.op
[op
].regs
->reg_name
,
6145 /* Any other register is bad. */
6146 if (i
.types
[op
].bitfield
.reg
6147 || i
.types
[op
].bitfield
.regmmx
6148 || i
.types
[op
].bitfield
.regsimd
6149 || i
.types
[op
].bitfield
.sreg2
6150 || i
.types
[op
].bitfield
.sreg3
6151 || i
.types
[op
].bitfield
.control
6152 || i
.types
[op
].bitfield
.debug
6153 || i
.types
[op
].bitfield
.test
)
6155 as_bad (_("`%s%s' not allowed with `%s%c'"),
6157 i
.op
[op
].regs
->reg_name
,
6167 check_long_reg (void)
6171 for (op
= i
.operands
; --op
>= 0;)
6172 /* Skip non-register operands. */
6173 if (!i
.types
[op
].bitfield
.reg
)
6175 /* Reject eight bit registers, except where the template requires
6176 them. (eg. movzb) */
6177 else if (i
.types
[op
].bitfield
.byte
6178 && (i
.tm
.operand_types
[op
].bitfield
.reg
6179 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6180 && (i
.tm
.operand_types
[op
].bitfield
.word
6181 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6183 as_bad (_("`%s%s' not allowed with `%s%c'"),
6185 i
.op
[op
].regs
->reg_name
,
6190 /* Warn if the e prefix on a general reg is missing. */
6191 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6192 && i
.types
[op
].bitfield
.word
6193 && (i
.tm
.operand_types
[op
].bitfield
.reg
6194 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6195 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6197 /* Prohibit these changes in the 64bit mode, since the
6198 lowering is more complicated. */
6199 if (flag_code
== CODE_64BIT
)
6201 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6202 register_prefix
, i
.op
[op
].regs
->reg_name
,
6206 #if REGISTER_WARNINGS
6207 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6209 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6210 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6213 /* Warn if the r prefix on a general reg is present. */
6214 else if (i
.types
[op
].bitfield
.qword
6215 && (i
.tm
.operand_types
[op
].bitfield
.reg
6216 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6217 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6220 && i
.tm
.opcode_modifier
.toqword
6221 && !i
.types
[0].bitfield
.regsimd
)
6223 /* Convert to QWORD. We want REX byte. */
6224 i
.suffix
= QWORD_MNEM_SUFFIX
;
6228 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6229 register_prefix
, i
.op
[op
].regs
->reg_name
,
6238 check_qword_reg (void)
6242 for (op
= i
.operands
; --op
>= 0; )
6243 /* Skip non-register operands. */
6244 if (!i
.types
[op
].bitfield
.reg
)
6246 /* Reject eight bit registers, except where the template requires
6247 them. (eg. movzb) */
6248 else if (i
.types
[op
].bitfield
.byte
6249 && (i
.tm
.operand_types
[op
].bitfield
.reg
6250 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6251 && (i
.tm
.operand_types
[op
].bitfield
.word
6252 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6254 as_bad (_("`%s%s' not allowed with `%s%c'"),
6256 i
.op
[op
].regs
->reg_name
,
6261 /* Warn if the r prefix on a general reg is missing. */
6262 else if ((i
.types
[op
].bitfield
.word
6263 || i
.types
[op
].bitfield
.dword
)
6264 && (i
.tm
.operand_types
[op
].bitfield
.reg
6265 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6266 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6268 /* Prohibit these changes in the 64bit mode, since the
6269 lowering is more complicated. */
6271 && i
.tm
.opcode_modifier
.todword
6272 && !i
.types
[0].bitfield
.regsimd
)
6274 /* Convert to DWORD. We don't want REX byte. */
6275 i
.suffix
= LONG_MNEM_SUFFIX
;
6279 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6280 register_prefix
, i
.op
[op
].regs
->reg_name
,
6289 check_word_reg (void)
6292 for (op
= i
.operands
; --op
>= 0;)
6293 /* Skip non-register operands. */
6294 if (!i
.types
[op
].bitfield
.reg
)
6296 /* Reject eight bit registers, except where the template requires
6297 them. (eg. movzb) */
6298 else if (i
.types
[op
].bitfield
.byte
6299 && (i
.tm
.operand_types
[op
].bitfield
.reg
6300 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6301 && (i
.tm
.operand_types
[op
].bitfield
.word
6302 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6304 as_bad (_("`%s%s' not allowed with `%s%c'"),
6306 i
.op
[op
].regs
->reg_name
,
6311 /* Warn if the e or r prefix on a general reg is present. */
6312 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6313 && (i
.types
[op
].bitfield
.dword
6314 || i
.types
[op
].bitfield
.qword
)
6315 && (i
.tm
.operand_types
[op
].bitfield
.reg
6316 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6317 && i
.tm
.operand_types
[op
].bitfield
.word
)
6319 /* Prohibit these changes in the 64bit mode, since the
6320 lowering is more complicated. */
6321 if (flag_code
== CODE_64BIT
)
6323 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6324 register_prefix
, i
.op
[op
].regs
->reg_name
,
6328 #if REGISTER_WARNINGS
6329 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6331 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6332 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6339 update_imm (unsigned int j
)
6341 i386_operand_type overlap
= i
.types
[j
];
6342 if ((overlap
.bitfield
.imm8
6343 || overlap
.bitfield
.imm8s
6344 || overlap
.bitfield
.imm16
6345 || overlap
.bitfield
.imm32
6346 || overlap
.bitfield
.imm32s
6347 || overlap
.bitfield
.imm64
)
6348 && !operand_type_equal (&overlap
, &imm8
)
6349 && !operand_type_equal (&overlap
, &imm8s
)
6350 && !operand_type_equal (&overlap
, &imm16
)
6351 && !operand_type_equal (&overlap
, &imm32
)
6352 && !operand_type_equal (&overlap
, &imm32s
)
6353 && !operand_type_equal (&overlap
, &imm64
))
6357 i386_operand_type temp
;
6359 operand_type_set (&temp
, 0);
6360 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6362 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6363 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6365 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6366 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6367 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6369 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6370 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6373 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6376 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6377 || operand_type_equal (&overlap
, &imm16_32
)
6378 || operand_type_equal (&overlap
, &imm16_32s
))
6380 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6385 if (!operand_type_equal (&overlap
, &imm8
)
6386 && !operand_type_equal (&overlap
, &imm8s
)
6387 && !operand_type_equal (&overlap
, &imm16
)
6388 && !operand_type_equal (&overlap
, &imm32
)
6389 && !operand_type_equal (&overlap
, &imm32s
)
6390 && !operand_type_equal (&overlap
, &imm64
))
6392 as_bad (_("no instruction mnemonic suffix given; "
6393 "can't determine immediate size"));
6397 i
.types
[j
] = overlap
;
6407 /* Update the first 2 immediate operands. */
6408 n
= i
.operands
> 2 ? 2 : i
.operands
;
6411 for (j
= 0; j
< n
; j
++)
6412 if (update_imm (j
) == 0)
6415 /* The 3rd operand can't be immediate operand. */
6416 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6423 process_operands (void)
6425 /* Default segment register this instruction will use for memory
6426 accesses. 0 means unknown. This is only for optimizing out
6427 unnecessary segment overrides. */
6428 const seg_entry
*default_seg
= 0;
6430 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6432 unsigned int dupl
= i
.operands
;
6433 unsigned int dest
= dupl
- 1;
6436 /* The destination must be an xmm register. */
6437 gas_assert (i
.reg_operands
6438 && MAX_OPERANDS
> dupl
6439 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6441 if (i
.tm
.operand_types
[0].bitfield
.acc
6442 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6444 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6446 /* Keep xmm0 for instructions with VEX prefix and 3
6448 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6449 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6454 /* We remove the first xmm0 and keep the number of
6455 operands unchanged, which in fact duplicates the
6457 for (j
= 1; j
< i
.operands
; j
++)
6459 i
.op
[j
- 1] = i
.op
[j
];
6460 i
.types
[j
- 1] = i
.types
[j
];
6461 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6465 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6467 gas_assert ((MAX_OPERANDS
- 1) > dupl
6468 && (i
.tm
.opcode_modifier
.vexsources
6471 /* Add the implicit xmm0 for instructions with VEX prefix
6473 for (j
= i
.operands
; j
> 0; j
--)
6475 i
.op
[j
] = i
.op
[j
- 1];
6476 i
.types
[j
] = i
.types
[j
- 1];
6477 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6480 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6481 i
.types
[0] = regxmm
;
6482 i
.tm
.operand_types
[0] = regxmm
;
6485 i
.reg_operands
+= 2;
6490 i
.op
[dupl
] = i
.op
[dest
];
6491 i
.types
[dupl
] = i
.types
[dest
];
6492 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6501 i
.op
[dupl
] = i
.op
[dest
];
6502 i
.types
[dupl
] = i
.types
[dest
];
6503 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6506 if (i
.tm
.opcode_modifier
.immext
)
6509 else if (i
.tm
.operand_types
[0].bitfield
.acc
6510 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6514 for (j
= 1; j
< i
.operands
; j
++)
6516 i
.op
[j
- 1] = i
.op
[j
];
6517 i
.types
[j
- 1] = i
.types
[j
];
6519 /* We need to adjust fields in i.tm since they are used by
6520 build_modrm_byte. */
6521 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6528 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6530 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6532 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6533 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6534 regnum
= register_number (i
.op
[1].regs
);
6535 first_reg_in_group
= regnum
& ~3;
6536 last_reg_in_group
= first_reg_in_group
+ 3;
6537 if (regnum
!= first_reg_in_group
)
6538 as_warn (_("source register `%s%s' implicitly denotes"
6539 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6540 register_prefix
, i
.op
[1].regs
->reg_name
,
6541 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6542 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6545 else if (i
.tm
.opcode_modifier
.regkludge
)
6547 /* The imul $imm, %reg instruction is converted into
6548 imul $imm, %reg, %reg, and the clr %reg instruction
6549 is converted into xor %reg, %reg. */
6551 unsigned int first_reg_op
;
6553 if (operand_type_check (i
.types
[0], reg
))
6557 /* Pretend we saw the extra register operand. */
6558 gas_assert (i
.reg_operands
== 1
6559 && i
.op
[first_reg_op
+ 1].regs
== 0);
6560 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6561 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6566 if (i
.tm
.opcode_modifier
.shortform
)
6568 if (i
.types
[0].bitfield
.sreg2
6569 || i
.types
[0].bitfield
.sreg3
)
6571 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6572 && i
.op
[0].regs
->reg_num
== 1)
6574 as_bad (_("you can't `pop %scs'"), register_prefix
);
6577 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6578 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6583 /* The register or float register operand is in operand
6587 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6588 || operand_type_check (i
.types
[0], reg
))
6592 /* Register goes in low 3 bits of opcode. */
6593 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6594 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6596 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6598 /* Warn about some common errors, but press on regardless.
6599 The first case can be generated by gcc (<= 2.8.1). */
6600 if (i
.operands
== 2)
6602 /* Reversed arguments on faddp, fsubp, etc. */
6603 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6604 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6605 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6609 /* Extraneous `l' suffix on fp insn. */
6610 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6611 register_prefix
, i
.op
[0].regs
->reg_name
);
6616 else if (i
.tm
.opcode_modifier
.modrm
)
6618 /* The opcode is completed (modulo i.tm.extension_opcode which
6619 must be put into the modrm byte). Now, we make the modrm and
6620 index base bytes based on all the info we've collected. */
6622 default_seg
= build_modrm_byte ();
6624 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6628 else if (i
.tm
.opcode_modifier
.isstring
)
6630 /* For the string instructions that allow a segment override
6631 on one of their operands, the default segment is ds. */
6635 if (i
.tm
.base_opcode
== 0x8d /* lea */
6638 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6640 /* If a segment was explicitly specified, and the specified segment
6641 is not the default, use an opcode prefix to select it. If we
6642 never figured out what the default segment is, then default_seg
6643 will be zero at this point, and the specified segment prefix will
6645 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6647 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6653 static const seg_entry
*
6654 build_modrm_byte (void)
6656 const seg_entry
*default_seg
= 0;
6657 unsigned int source
, dest
;
6660 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6663 unsigned int nds
, reg_slot
;
6666 dest
= i
.operands
- 1;
6669 /* There are 2 kinds of instructions:
6670 1. 5 operands: 4 register operands or 3 register operands
6671 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6672 VexW0 or VexW1. The destination must be either XMM, YMM or
6674 2. 4 operands: 4 register operands or 3 register operands
6675 plus 1 memory operand, with VexXDS. */
6676 gas_assert ((i
.reg_operands
== 4
6677 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6678 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6679 && i
.tm
.opcode_modifier
.vexw
6680 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6682 /* If VexW1 is set, the first non-immediate operand is the source and
6683 the second non-immediate one is encoded in the immediate operand. */
6684 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6686 source
= i
.imm_operands
;
6687 reg_slot
= i
.imm_operands
+ 1;
6691 source
= i
.imm_operands
+ 1;
6692 reg_slot
= i
.imm_operands
;
6695 if (i
.imm_operands
== 0)
6697 /* When there is no immediate operand, generate an 8bit
6698 immediate operand to encode the first operand. */
6699 exp
= &im_expressions
[i
.imm_operands
++];
6700 i
.op
[i
.operands
].imms
= exp
;
6701 i
.types
[i
.operands
] = imm8
;
6704 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6705 exp
->X_op
= O_constant
;
6706 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6707 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6711 unsigned int imm_slot
;
6713 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6715 if (i
.tm
.opcode_modifier
.immext
)
6717 /* When ImmExt is set, the immediate byte is the last
6719 imm_slot
= i
.operands
- 1;
6727 /* Turn on Imm8 so that output_imm will generate it. */
6728 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6731 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6732 i
.op
[imm_slot
].imms
->X_add_number
6733 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6734 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6737 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6738 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6743 /* i.reg_operands MUST be the number of real register operands;
6744 implicit registers do not count. If there are 3 register
6745 operands, it must be a instruction with VexNDS. For a
6746 instruction with VexNDD, the destination register is encoded
6747 in VEX prefix. If there are 4 register operands, it must be
6748 a instruction with VEX prefix and 3 sources. */
6749 if (i
.mem_operands
== 0
6750 && ((i
.reg_operands
== 2
6751 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6752 || (i
.reg_operands
== 3
6753 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6754 || (i
.reg_operands
== 4 && vex_3_sources
)))
6762 /* When there are 3 operands, one of them may be immediate,
6763 which may be the first or the last operand. Otherwise,
6764 the first operand must be shift count register (cl) or it
6765 is an instruction with VexNDS. */
6766 gas_assert (i
.imm_operands
== 1
6767 || (i
.imm_operands
== 0
6768 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6769 || i
.types
[0].bitfield
.shiftcount
)));
6770 if (operand_type_check (i
.types
[0], imm
)
6771 || i
.types
[0].bitfield
.shiftcount
)
6777 /* When there are 4 operands, the first two must be 8bit
6778 immediate operands. The source operand will be the 3rd
6781 For instructions with VexNDS, if the first operand
6782 an imm8, the source operand is the 2nd one. If the last
6783 operand is imm8, the source operand is the first one. */
6784 gas_assert ((i
.imm_operands
== 2
6785 && i
.types
[0].bitfield
.imm8
6786 && i
.types
[1].bitfield
.imm8
)
6787 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6788 && i
.imm_operands
== 1
6789 && (i
.types
[0].bitfield
.imm8
6790 || i
.types
[i
.operands
- 1].bitfield
.imm8
6792 if (i
.imm_operands
== 2)
6796 if (i
.types
[0].bitfield
.imm8
)
6803 if (is_evex_encoding (&i
.tm
))
6805 /* For EVEX instructions, when there are 5 operands, the
6806 first one must be immediate operand. If the second one
6807 is immediate operand, the source operand is the 3th
6808 one. If the last one is immediate operand, the source
6809 operand is the 2nd one. */
6810 gas_assert (i
.imm_operands
== 2
6811 && i
.tm
.opcode_modifier
.sae
6812 && operand_type_check (i
.types
[0], imm
));
6813 if (operand_type_check (i
.types
[1], imm
))
6815 else if (operand_type_check (i
.types
[4], imm
))
6829 /* RC/SAE operand could be between DEST and SRC. That happens
6830 when one operand is GPR and the other one is XMM/YMM/ZMM
6832 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6835 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6837 /* For instructions with VexNDS, the register-only source
6838 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6839 register. It is encoded in VEX prefix. We need to
6840 clear RegMem bit before calling operand_type_equal. */
6842 i386_operand_type op
;
6845 /* Check register-only source operand when two source
6846 operands are swapped. */
6847 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6848 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6856 op
= i
.tm
.operand_types
[vvvv
];
6857 op
.bitfield
.regmem
= 0;
6858 if ((dest
+ 1) >= i
.operands
6859 || ((!op
.bitfield
.reg
6860 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6861 && !op
.bitfield
.regsimd
6862 && !operand_type_equal (&op
, ®mask
)))
6864 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6870 /* One of the register operands will be encoded in the i.tm.reg
6871 field, the other in the combined i.tm.mode and i.tm.regmem
6872 fields. If no form of this instruction supports a memory
6873 destination operand, then we assume the source operand may
6874 sometimes be a memory operand and so we need to store the
6875 destination in the i.rm.reg field. */
6876 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6877 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6879 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6880 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6881 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6883 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6885 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6887 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6892 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6893 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6894 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6896 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6898 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6900 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6903 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
6905 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
6908 add_prefix (LOCK_PREFIX_OPCODE
);
6912 { /* If it's not 2 reg operands... */
6917 unsigned int fake_zero_displacement
= 0;
6920 for (op
= 0; op
< i
.operands
; op
++)
6921 if (operand_type_check (i
.types
[op
], anymem
))
6923 gas_assert (op
< i
.operands
);
6925 if (i
.tm
.opcode_modifier
.vecsib
)
6927 if (i
.index_reg
->reg_num
== RegEiz
6928 || i
.index_reg
->reg_num
== RegRiz
)
6931 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6934 i
.sib
.base
= NO_BASE_REGISTER
;
6935 i
.sib
.scale
= i
.log2_scale_factor
;
6936 i
.types
[op
].bitfield
.disp8
= 0;
6937 i
.types
[op
].bitfield
.disp16
= 0;
6938 i
.types
[op
].bitfield
.disp64
= 0;
6939 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6941 /* Must be 32 bit */
6942 i
.types
[op
].bitfield
.disp32
= 1;
6943 i
.types
[op
].bitfield
.disp32s
= 0;
6947 i
.types
[op
].bitfield
.disp32
= 0;
6948 i
.types
[op
].bitfield
.disp32s
= 1;
6951 i
.sib
.index
= i
.index_reg
->reg_num
;
6952 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6954 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6960 if (i
.base_reg
== 0)
6963 if (!i
.disp_operands
)
6964 fake_zero_displacement
= 1;
6965 if (i
.index_reg
== 0)
6967 i386_operand_type newdisp
;
6969 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6970 /* Operand is just <disp> */
6971 if (flag_code
== CODE_64BIT
)
6973 /* 64bit mode overwrites the 32bit absolute
6974 addressing by RIP relative addressing and
6975 absolute addressing is encoded by one of the
6976 redundant SIB forms. */
6977 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6978 i
.sib
.base
= NO_BASE_REGISTER
;
6979 i
.sib
.index
= NO_INDEX_REGISTER
;
6980 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6982 else if ((flag_code
== CODE_16BIT
)
6983 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6985 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6990 i
.rm
.regmem
= NO_BASE_REGISTER
;
6993 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6994 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6996 else if (!i
.tm
.opcode_modifier
.vecsib
)
6998 /* !i.base_reg && i.index_reg */
6999 if (i
.index_reg
->reg_num
== RegEiz
7000 || i
.index_reg
->reg_num
== RegRiz
)
7001 i
.sib
.index
= NO_INDEX_REGISTER
;
7003 i
.sib
.index
= i
.index_reg
->reg_num
;
7004 i
.sib
.base
= NO_BASE_REGISTER
;
7005 i
.sib
.scale
= i
.log2_scale_factor
;
7006 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7007 i
.types
[op
].bitfield
.disp8
= 0;
7008 i
.types
[op
].bitfield
.disp16
= 0;
7009 i
.types
[op
].bitfield
.disp64
= 0;
7010 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7012 /* Must be 32 bit */
7013 i
.types
[op
].bitfield
.disp32
= 1;
7014 i
.types
[op
].bitfield
.disp32s
= 0;
7018 i
.types
[op
].bitfield
.disp32
= 0;
7019 i
.types
[op
].bitfield
.disp32s
= 1;
7021 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7025 /* RIP addressing for 64bit mode. */
7026 else if (i
.base_reg
->reg_num
== RegRip
||
7027 i
.base_reg
->reg_num
== RegEip
)
7029 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7030 i
.rm
.regmem
= NO_BASE_REGISTER
;
7031 i
.types
[op
].bitfield
.disp8
= 0;
7032 i
.types
[op
].bitfield
.disp16
= 0;
7033 i
.types
[op
].bitfield
.disp32
= 0;
7034 i
.types
[op
].bitfield
.disp32s
= 1;
7035 i
.types
[op
].bitfield
.disp64
= 0;
7036 i
.flags
[op
] |= Operand_PCrel
;
7037 if (! i
.disp_operands
)
7038 fake_zero_displacement
= 1;
7040 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7042 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7043 switch (i
.base_reg
->reg_num
)
7046 if (i
.index_reg
== 0)
7048 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7049 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7053 if (i
.index_reg
== 0)
7056 if (operand_type_check (i
.types
[op
], disp
) == 0)
7058 /* fake (%bp) into 0(%bp) */
7059 i
.types
[op
].bitfield
.disp8
= 1;
7060 fake_zero_displacement
= 1;
7063 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7064 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7066 default: /* (%si) -> 4 or (%di) -> 5 */
7067 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7069 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7071 else /* i.base_reg and 32/64 bit mode */
7073 if (flag_code
== CODE_64BIT
7074 && operand_type_check (i
.types
[op
], disp
))
7076 i
.types
[op
].bitfield
.disp16
= 0;
7077 i
.types
[op
].bitfield
.disp64
= 0;
7078 if (i
.prefix
[ADDR_PREFIX
] == 0)
7080 i
.types
[op
].bitfield
.disp32
= 0;
7081 i
.types
[op
].bitfield
.disp32s
= 1;
7085 i
.types
[op
].bitfield
.disp32
= 1;
7086 i
.types
[op
].bitfield
.disp32s
= 0;
7090 if (!i
.tm
.opcode_modifier
.vecsib
)
7091 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7092 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7094 i
.sib
.base
= i
.base_reg
->reg_num
;
7095 /* x86-64 ignores REX prefix bit here to avoid decoder
7097 if (!(i
.base_reg
->reg_flags
& RegRex
)
7098 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7099 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7101 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7103 fake_zero_displacement
= 1;
7104 i
.types
[op
].bitfield
.disp8
= 1;
7106 i
.sib
.scale
= i
.log2_scale_factor
;
7107 if (i
.index_reg
== 0)
7109 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7110 /* <disp>(%esp) becomes two byte modrm with no index
7111 register. We've already stored the code for esp
7112 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7113 Any base register besides %esp will not use the
7114 extra modrm byte. */
7115 i
.sib
.index
= NO_INDEX_REGISTER
;
7117 else if (!i
.tm
.opcode_modifier
.vecsib
)
7119 if (i
.index_reg
->reg_num
== RegEiz
7120 || i
.index_reg
->reg_num
== RegRiz
)
7121 i
.sib
.index
= NO_INDEX_REGISTER
;
7123 i
.sib
.index
= i
.index_reg
->reg_num
;
7124 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7125 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7130 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7131 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7135 if (!fake_zero_displacement
7139 fake_zero_displacement
= 1;
7140 if (i
.disp_encoding
== disp_encoding_8bit
)
7141 i
.types
[op
].bitfield
.disp8
= 1;
7143 i
.types
[op
].bitfield
.disp32
= 1;
7145 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7149 if (fake_zero_displacement
)
7151 /* Fakes a zero displacement assuming that i.types[op]
7152 holds the correct displacement size. */
7155 gas_assert (i
.op
[op
].disps
== 0);
7156 exp
= &disp_expressions
[i
.disp_operands
++];
7157 i
.op
[op
].disps
= exp
;
7158 exp
->X_op
= O_constant
;
7159 exp
->X_add_number
= 0;
7160 exp
->X_add_symbol
= (symbolS
*) 0;
7161 exp
->X_op_symbol
= (symbolS
*) 0;
7169 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7171 if (operand_type_check (i
.types
[0], imm
))
7172 i
.vex
.register_specifier
= NULL
;
7175 /* VEX.vvvv encodes one of the sources when the first
7176 operand is not an immediate. */
7177 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7178 i
.vex
.register_specifier
= i
.op
[0].regs
;
7180 i
.vex
.register_specifier
= i
.op
[1].regs
;
7183 /* Destination is a XMM register encoded in the ModRM.reg
7185 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7186 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7189 /* ModRM.rm and VEX.B encodes the other source. */
7190 if (!i
.mem_operands
)
7194 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7195 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7197 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7199 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7203 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7205 i
.vex
.register_specifier
= i
.op
[2].regs
;
7206 if (!i
.mem_operands
)
7209 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7210 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7214 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7215 (if any) based on i.tm.extension_opcode. Again, we must be
7216 careful to make sure that segment/control/debug/test/MMX
7217 registers are coded into the i.rm.reg field. */
7218 else if (i
.reg_operands
)
7221 unsigned int vex_reg
= ~0;
7223 for (op
= 0; op
< i
.operands
; op
++)
7224 if (i
.types
[op
].bitfield
.reg
7225 || i
.types
[op
].bitfield
.regmmx
7226 || i
.types
[op
].bitfield
.regsimd
7227 || i
.types
[op
].bitfield
.regbnd
7228 || i
.types
[op
].bitfield
.regmask
7229 || i
.types
[op
].bitfield
.sreg2
7230 || i
.types
[op
].bitfield
.sreg3
7231 || i
.types
[op
].bitfield
.control
7232 || i
.types
[op
].bitfield
.debug
7233 || i
.types
[op
].bitfield
.test
)
7238 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7240 /* For instructions with VexNDS, the register-only
7241 source operand is encoded in VEX prefix. */
7242 gas_assert (mem
!= (unsigned int) ~0);
7247 gas_assert (op
< i
.operands
);
7251 /* Check register-only source operand when two source
7252 operands are swapped. */
7253 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7254 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7258 gas_assert (mem
== (vex_reg
+ 1)
7259 && op
< i
.operands
);
7264 gas_assert (vex_reg
< i
.operands
);
7268 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7270 /* For instructions with VexNDD, the register destination
7271 is encoded in VEX prefix. */
7272 if (i
.mem_operands
== 0)
7274 /* There is no memory operand. */
7275 gas_assert ((op
+ 2) == i
.operands
);
7280 /* There are only 2 non-immediate operands. */
7281 gas_assert (op
< i
.imm_operands
+ 2
7282 && i
.operands
== i
.imm_operands
+ 2);
7283 vex_reg
= i
.imm_operands
+ 1;
7287 gas_assert (op
< i
.operands
);
7289 if (vex_reg
!= (unsigned int) ~0)
7291 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7293 if ((!type
->bitfield
.reg
7294 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7295 && !type
->bitfield
.regsimd
7296 && !operand_type_equal (type
, ®mask
))
7299 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7302 /* Don't set OP operand twice. */
7305 /* If there is an extension opcode to put here, the
7306 register number must be put into the regmem field. */
7307 if (i
.tm
.extension_opcode
!= None
)
7309 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7310 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7312 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7317 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7318 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7320 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7325 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7326 must set it to 3 to indicate this is a register operand
7327 in the regmem field. */
7328 if (!i
.mem_operands
)
7332 /* Fill in i.rm.reg field with extension opcode (if any). */
7333 if (i
.tm
.extension_opcode
!= None
)
7334 i
.rm
.reg
= i
.tm
.extension_opcode
;
7340 output_branch (void)
7346 relax_substateT subtype
;
7350 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7351 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7354 if (i
.prefix
[DATA_PREFIX
] != 0)
7360 /* Pentium4 branch hints. */
7361 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7362 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7367 if (i
.prefix
[REX_PREFIX
] != 0)
7373 /* BND prefixed jump. */
7374 if (i
.prefix
[BND_PREFIX
] != 0)
7376 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7380 if (i
.prefixes
!= 0 && !intel_syntax
)
7381 as_warn (_("skipping prefixes on this instruction"));
7383 /* It's always a symbol; End frag & setup for relax.
7384 Make sure there is enough room in this frag for the largest
7385 instruction we may generate in md_convert_frag. This is 2
7386 bytes for the opcode and room for the prefix and largest
7388 frag_grow (prefix
+ 2 + 4);
7389 /* Prefix and 1 opcode byte go in fr_fix. */
7390 p
= frag_more (prefix
+ 1);
7391 if (i
.prefix
[DATA_PREFIX
] != 0)
7392 *p
++ = DATA_PREFIX_OPCODE
;
7393 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7394 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7395 *p
++ = i
.prefix
[SEG_PREFIX
];
7396 if (i
.prefix
[REX_PREFIX
] != 0)
7397 *p
++ = i
.prefix
[REX_PREFIX
];
7398 *p
= i
.tm
.base_opcode
;
7400 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7401 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7402 else if (cpu_arch_flags
.bitfield
.cpui386
)
7403 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7405 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7408 sym
= i
.op
[0].disps
->X_add_symbol
;
7409 off
= i
.op
[0].disps
->X_add_number
;
7411 if (i
.op
[0].disps
->X_op
!= O_constant
7412 && i
.op
[0].disps
->X_op
!= O_symbol
)
7414 /* Handle complex expressions. */
7415 sym
= make_expr_symbol (i
.op
[0].disps
);
7419 /* 1 possible extra opcode + 4 byte displacement go in var part.
7420 Pass reloc in fr_var. */
7421 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7424 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7425 /* Return TRUE iff PLT32 relocation should be used for branching to
7429 need_plt32_p (symbolS
*s
)
7431 /* PLT32 relocation is ELF only. */
7435 /* Since there is no need to prepare for PLT branch on x86-64, we
7436 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7437 be used as a marker for 32-bit PC-relative branches. */
7441 /* Weak or undefined symbol need PLT32 relocation. */
7442 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7445 /* Non-global symbol doesn't need PLT32 relocation. */
7446 if (! S_IS_EXTERNAL (s
))
7449 /* Other global symbols need PLT32 relocation. NB: Symbol with
7450 non-default visibilities are treated as normal global symbol
7451 so that PLT32 relocation can be used as a marker for 32-bit
7452 PC-relative branches. It is useful for linker relaxation. */
7463 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7465 if (i
.tm
.opcode_modifier
.jumpbyte
)
7467 /* This is a loop or jecxz type instruction. */
7469 if (i
.prefix
[ADDR_PREFIX
] != 0)
7471 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7474 /* Pentium4 branch hints. */
7475 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7476 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7478 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7487 if (flag_code
== CODE_16BIT
)
7490 if (i
.prefix
[DATA_PREFIX
] != 0)
7492 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7502 if (i
.prefix
[REX_PREFIX
] != 0)
7504 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7508 /* BND prefixed jump. */
7509 if (i
.prefix
[BND_PREFIX
] != 0)
7511 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7515 if (i
.prefixes
!= 0 && !intel_syntax
)
7516 as_warn (_("skipping prefixes on this instruction"));
7518 p
= frag_more (i
.tm
.opcode_length
+ size
);
7519 switch (i
.tm
.opcode_length
)
7522 *p
++ = i
.tm
.base_opcode
>> 8;
7525 *p
++ = i
.tm
.base_opcode
;
7531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7533 && jump_reloc
== NO_RELOC
7534 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7535 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7538 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7540 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7541 i
.op
[0].disps
, 1, jump_reloc
);
7543 /* All jumps handled here are signed, but don't use a signed limit
7544 check for 32 and 16 bit jumps as we want to allow wrap around at
7545 4G and 64k respectively. */
7547 fixP
->fx_signed
= 1;
7551 output_interseg_jump (void)
7559 if (flag_code
== CODE_16BIT
)
7563 if (i
.prefix
[DATA_PREFIX
] != 0)
7569 if (i
.prefix
[REX_PREFIX
] != 0)
7579 if (i
.prefixes
!= 0 && !intel_syntax
)
7580 as_warn (_("skipping prefixes on this instruction"));
7582 /* 1 opcode; 2 segment; offset */
7583 p
= frag_more (prefix
+ 1 + 2 + size
);
7585 if (i
.prefix
[DATA_PREFIX
] != 0)
7586 *p
++ = DATA_PREFIX_OPCODE
;
7588 if (i
.prefix
[REX_PREFIX
] != 0)
7589 *p
++ = i
.prefix
[REX_PREFIX
];
7591 *p
++ = i
.tm
.base_opcode
;
7592 if (i
.op
[1].imms
->X_op
== O_constant
)
7594 offsetT n
= i
.op
[1].imms
->X_add_number
;
7597 && !fits_in_unsigned_word (n
)
7598 && !fits_in_signed_word (n
))
7600 as_bad (_("16-bit jump out of range"));
7603 md_number_to_chars (p
, n
, size
);
7606 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7607 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7608 if (i
.op
[0].imms
->X_op
!= O_constant
)
7609 as_bad (_("can't handle non absolute segment in `%s'"),
7611 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7617 fragS
*insn_start_frag
;
7618 offsetT insn_start_off
;
7620 /* Tie dwarf2 debug info to the address at the start of the insn.
7621 We can't do this after the insn has been output as the current
7622 frag may have been closed off. eg. by frag_var. */
7623 dwarf2_emit_insn (0);
7625 insn_start_frag
= frag_now
;
7626 insn_start_off
= frag_now_fix ();
7629 if (i
.tm
.opcode_modifier
.jump
)
7631 else if (i
.tm
.opcode_modifier
.jumpbyte
7632 || i
.tm
.opcode_modifier
.jumpdword
)
7634 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7635 output_interseg_jump ();
7638 /* Output normal instructions here. */
7642 unsigned int prefix
;
7645 && i
.tm
.base_opcode
== 0xfae
7647 && i
.imm_operands
== 1
7648 && (i
.op
[0].imms
->X_add_number
== 0xe8
7649 || i
.op
[0].imms
->X_add_number
== 0xf0
7650 || i
.op
[0].imms
->X_add_number
== 0xf8))
7652 /* Encode lfence, mfence, and sfence as
7653 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7654 offsetT val
= 0x240483f0ULL
;
7656 md_number_to_chars (p
, val
, 5);
7660 /* Some processors fail on LOCK prefix. This options makes
7661 assembler ignore LOCK prefix and serves as a workaround. */
7662 if (omit_lock_prefix
)
7664 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7666 i
.prefix
[LOCK_PREFIX
] = 0;
7669 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7670 don't need the explicit prefix. */
7671 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7673 switch (i
.tm
.opcode_length
)
7676 if (i
.tm
.base_opcode
& 0xff000000)
7678 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7683 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7685 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7686 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7689 if (prefix
!= REPE_PREFIX_OPCODE
7690 || (i
.prefix
[REP_PREFIX
]
7691 != REPE_PREFIX_OPCODE
))
7692 add_prefix (prefix
);
7695 add_prefix (prefix
);
7701 /* Check for pseudo prefixes. */
7702 as_bad_where (insn_start_frag
->fr_file
,
7703 insn_start_frag
->fr_line
,
7704 _("pseudo prefix without instruction"));
7710 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7711 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7712 R_X86_64_GOTTPOFF relocation so that linker can safely
7713 perform IE->LE optimization. */
7714 if (x86_elf_abi
== X86_64_X32_ABI
7716 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7717 && i
.prefix
[REX_PREFIX
] == 0)
7718 add_prefix (REX_OPCODE
);
7721 /* The prefix bytes. */
7722 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7724 FRAG_APPEND_1_CHAR (*q
);
7728 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7733 /* REX byte is encoded in VEX prefix. */
7737 FRAG_APPEND_1_CHAR (*q
);
7740 /* There should be no other prefixes for instructions
7745 /* For EVEX instructions i.vrex should become 0 after
7746 build_evex_prefix. For VEX instructions upper 16 registers
7747 aren't available, so VREX should be 0. */
7750 /* Now the VEX prefix. */
7751 p
= frag_more (i
.vex
.length
);
7752 for (j
= 0; j
< i
.vex
.length
; j
++)
7753 p
[j
] = i
.vex
.bytes
[j
];
7756 /* Now the opcode; be careful about word order here! */
7757 if (i
.tm
.opcode_length
== 1)
7759 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7763 switch (i
.tm
.opcode_length
)
7767 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7768 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7772 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7782 /* Put out high byte first: can't use md_number_to_chars! */
7783 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7784 *p
= i
.tm
.base_opcode
& 0xff;
7787 /* Now the modrm byte and sib byte (if present). */
7788 if (i
.tm
.opcode_modifier
.modrm
)
7790 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7793 /* If i.rm.regmem == ESP (4)
7794 && i.rm.mode != (Register mode)
7796 ==> need second modrm byte. */
7797 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7799 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7800 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7802 | i
.sib
.scale
<< 6));
7805 if (i
.disp_operands
)
7806 output_disp (insn_start_frag
, insn_start_off
);
7809 output_imm (insn_start_frag
, insn_start_off
);
7815 pi ("" /*line*/, &i
);
7817 #endif /* DEBUG386 */
7820 /* Return the size of the displacement operand N. */
7823 disp_size (unsigned int n
)
7827 if (i
.types
[n
].bitfield
.disp64
)
7829 else if (i
.types
[n
].bitfield
.disp8
)
7831 else if (i
.types
[n
].bitfield
.disp16
)
7836 /* Return the size of the immediate operand N. */
7839 imm_size (unsigned int n
)
7842 if (i
.types
[n
].bitfield
.imm64
)
7844 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7846 else if (i
.types
[n
].bitfield
.imm16
)
7852 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7857 for (n
= 0; n
< i
.operands
; n
++)
7859 if (operand_type_check (i
.types
[n
], disp
))
7861 if (i
.op
[n
].disps
->X_op
== O_constant
)
7863 int size
= disp_size (n
);
7864 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7866 val
= offset_in_range (val
>> i
.memshift
, size
);
7867 p
= frag_more (size
);
7868 md_number_to_chars (p
, val
, size
);
7872 enum bfd_reloc_code_real reloc_type
;
7873 int size
= disp_size (n
);
7874 int sign
= i
.types
[n
].bitfield
.disp32s
;
7875 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7878 /* We can't have 8 bit displacement here. */
7879 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7881 /* The PC relative address is computed relative
7882 to the instruction boundary, so in case immediate
7883 fields follows, we need to adjust the value. */
7884 if (pcrel
&& i
.imm_operands
)
7889 for (n1
= 0; n1
< i
.operands
; n1
++)
7890 if (operand_type_check (i
.types
[n1
], imm
))
7892 /* Only one immediate is allowed for PC
7893 relative address. */
7894 gas_assert (sz
== 0);
7896 i
.op
[n
].disps
->X_add_number
-= sz
;
7898 /* We should find the immediate. */
7899 gas_assert (sz
!= 0);
7902 p
= frag_more (size
);
7903 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7905 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7906 && (((reloc_type
== BFD_RELOC_32
7907 || reloc_type
== BFD_RELOC_X86_64_32S
7908 || (reloc_type
== BFD_RELOC_64
7910 && (i
.op
[n
].disps
->X_op
== O_symbol
7911 || (i
.op
[n
].disps
->X_op
== O_add
7912 && ((symbol_get_value_expression
7913 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7915 || reloc_type
== BFD_RELOC_32_PCREL
))
7919 if (insn_start_frag
== frag_now
)
7920 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7925 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7926 for (fr
= insn_start_frag
->fr_next
;
7927 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7929 add
+= p
- frag_now
->fr_literal
;
7934 reloc_type
= BFD_RELOC_386_GOTPC
;
7935 i
.op
[n
].imms
->X_add_number
+= add
;
7937 else if (reloc_type
== BFD_RELOC_64
)
7938 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7940 /* Don't do the adjustment for x86-64, as there
7941 the pcrel addressing is relative to the _next_
7942 insn, and that is taken care of in other code. */
7943 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7945 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7946 size
, i
.op
[n
].disps
, pcrel
,
7948 /* Check for "call/jmp *mem", "mov mem, %reg",
7949 "test %reg, mem" and "binop mem, %reg" where binop
7950 is one of adc, add, and, cmp, or, sbb, sub, xor
7951 instructions. Always generate R_386_GOT32X for
7952 "sym*GOT" operand in 32-bit mode. */
7953 if ((generate_relax_relocations
7956 && i
.rm
.regmem
== 5))
7958 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7959 && ((i
.operands
== 1
7960 && i
.tm
.base_opcode
== 0xff
7961 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7963 && (i
.tm
.base_opcode
== 0x8b
7964 || i
.tm
.base_opcode
== 0x85
7965 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7969 fixP
->fx_tcbit
= i
.rex
!= 0;
7971 && (i
.base_reg
->reg_num
== RegRip
7972 || i
.base_reg
->reg_num
== RegEip
))
7973 fixP
->fx_tcbit2
= 1;
7976 fixP
->fx_tcbit2
= 1;
7984 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7989 for (n
= 0; n
< i
.operands
; n
++)
7991 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7992 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7995 if (operand_type_check (i
.types
[n
], imm
))
7997 if (i
.op
[n
].imms
->X_op
== O_constant
)
7999 int size
= imm_size (n
);
8002 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8004 p
= frag_more (size
);
8005 md_number_to_chars (p
, val
, size
);
8009 /* Not absolute_section.
8010 Need a 32-bit fixup (don't support 8bit
8011 non-absolute imms). Try to support other
8013 enum bfd_reloc_code_real reloc_type
;
8014 int size
= imm_size (n
);
8017 if (i
.types
[n
].bitfield
.imm32s
8018 && (i
.suffix
== QWORD_MNEM_SUFFIX
8019 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8024 p
= frag_more (size
);
8025 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8027 /* This is tough to explain. We end up with this one if we
8028 * have operands that look like
8029 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8030 * obtain the absolute address of the GOT, and it is strongly
8031 * preferable from a performance point of view to avoid using
8032 * a runtime relocation for this. The actual sequence of
8033 * instructions often look something like:
8038 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8040 * The call and pop essentially return the absolute address
8041 * of the label .L66 and store it in %ebx. The linker itself
8042 * will ultimately change the first operand of the addl so
8043 * that %ebx points to the GOT, but to keep things simple, the
8044 * .o file must have this operand set so that it generates not
8045 * the absolute address of .L66, but the absolute address of
8046 * itself. This allows the linker itself simply treat a GOTPC
8047 * relocation as asking for a pcrel offset to the GOT to be
8048 * added in, and the addend of the relocation is stored in the
8049 * operand field for the instruction itself.
8051 * Our job here is to fix the operand so that it would add
8052 * the correct offset so that %ebx would point to itself. The
8053 * thing that is tricky is that .-.L66 will point to the
8054 * beginning of the instruction, so we need to further modify
8055 * the operand so that it will point to itself. There are
8056 * other cases where you have something like:
8058 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8060 * and here no correction would be required. Internally in
8061 * the assembler we treat operands of this form as not being
8062 * pcrel since the '.' is explicitly mentioned, and I wonder
8063 * whether it would simplify matters to do it this way. Who
8064 * knows. In earlier versions of the PIC patches, the
8065 * pcrel_adjust field was used to store the correction, but
8066 * since the expression is not pcrel, I felt it would be
8067 * confusing to do it this way. */
8069 if ((reloc_type
== BFD_RELOC_32
8070 || reloc_type
== BFD_RELOC_X86_64_32S
8071 || reloc_type
== BFD_RELOC_64
)
8073 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8074 && (i
.op
[n
].imms
->X_op
== O_symbol
8075 || (i
.op
[n
].imms
->X_op
== O_add
8076 && ((symbol_get_value_expression
8077 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8082 if (insn_start_frag
== frag_now
)
8083 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8088 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8089 for (fr
= insn_start_frag
->fr_next
;
8090 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8092 add
+= p
- frag_now
->fr_literal
;
8096 reloc_type
= BFD_RELOC_386_GOTPC
;
8098 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8100 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8101 i
.op
[n
].imms
->X_add_number
+= add
;
8103 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8104 i
.op
[n
].imms
, 0, reloc_type
);
8110 /* x86_cons_fix_new is called via the expression parsing code when a
8111 reloc is needed. We use this hook to get the correct .got reloc. */
8112 static int cons_sign
= -1;
8115 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8116 expressionS
*exp
, bfd_reloc_code_real_type r
)
8118 r
= reloc (len
, 0, cons_sign
, r
);
8121 if (exp
->X_op
== O_secrel
)
8123 exp
->X_op
= O_symbol
;
8124 r
= BFD_RELOC_32_SECREL
;
8128 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8131 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8132 purpose of the `.dc.a' internal pseudo-op. */
8135 x86_address_bytes (void)
8137 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8139 return stdoutput
->arch_info
->bits_per_address
/ 8;
8142 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8144 # define lex_got(reloc, adjust, types) NULL
8146 /* Parse operands of the form
8147 <symbol>@GOTOFF+<nnn>
8148 and similar .plt or .got references.
8150 If we find one, set up the correct relocation in RELOC and copy the
8151 input string, minus the `@GOTOFF' into a malloc'd buffer for
8152 parsing by the calling routine. Return this buffer, and if ADJUST
8153 is non-null set it to the length of the string we removed from the
8154 input line. Otherwise return NULL. */
8156 lex_got (enum bfd_reloc_code_real
*rel
,
8158 i386_operand_type
*types
)
8160 /* Some of the relocations depend on the size of what field is to
8161 be relocated. But in our callers i386_immediate and i386_displacement
8162 we don't yet know the operand size (this will be set by insn
8163 matching). Hence we record the word32 relocation here,
8164 and adjust the reloc according to the real size in reloc(). */
8165 static const struct {
8168 const enum bfd_reloc_code_real rel
[2];
8169 const i386_operand_type types64
;
8171 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8172 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8174 OPERAND_TYPE_IMM32_64
},
8176 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8177 BFD_RELOC_X86_64_PLTOFF64
},
8178 OPERAND_TYPE_IMM64
},
8179 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8180 BFD_RELOC_X86_64_PLT32
},
8181 OPERAND_TYPE_IMM32_32S_DISP32
},
8182 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8183 BFD_RELOC_X86_64_GOTPLT64
},
8184 OPERAND_TYPE_IMM64_DISP64
},
8185 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8186 BFD_RELOC_X86_64_GOTOFF64
},
8187 OPERAND_TYPE_IMM64_DISP64
},
8188 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8189 BFD_RELOC_X86_64_GOTPCREL
},
8190 OPERAND_TYPE_IMM32_32S_DISP32
},
8191 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8192 BFD_RELOC_X86_64_TLSGD
},
8193 OPERAND_TYPE_IMM32_32S_DISP32
},
8194 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8195 _dummy_first_bfd_reloc_code_real
},
8196 OPERAND_TYPE_NONE
},
8197 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8198 BFD_RELOC_X86_64_TLSLD
},
8199 OPERAND_TYPE_IMM32_32S_DISP32
},
8200 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8201 BFD_RELOC_X86_64_GOTTPOFF
},
8202 OPERAND_TYPE_IMM32_32S_DISP32
},
8203 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8204 BFD_RELOC_X86_64_TPOFF32
},
8205 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8206 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8207 _dummy_first_bfd_reloc_code_real
},
8208 OPERAND_TYPE_NONE
},
8209 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8210 BFD_RELOC_X86_64_DTPOFF32
},
8211 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8212 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8213 _dummy_first_bfd_reloc_code_real
},
8214 OPERAND_TYPE_NONE
},
8215 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8216 _dummy_first_bfd_reloc_code_real
},
8217 OPERAND_TYPE_NONE
},
8218 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8219 BFD_RELOC_X86_64_GOT32
},
8220 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8221 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8222 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8223 OPERAND_TYPE_IMM32_32S_DISP32
},
8224 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8225 BFD_RELOC_X86_64_TLSDESC_CALL
},
8226 OPERAND_TYPE_IMM32_32S_DISP32
},
8231 #if defined (OBJ_MAYBE_ELF)
8236 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8237 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8240 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8242 int len
= gotrel
[j
].len
;
8243 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8245 if (gotrel
[j
].rel
[object_64bit
] != 0)
8248 char *tmpbuf
, *past_reloc
;
8250 *rel
= gotrel
[j
].rel
[object_64bit
];
8254 if (flag_code
!= CODE_64BIT
)
8256 types
->bitfield
.imm32
= 1;
8257 types
->bitfield
.disp32
= 1;
8260 *types
= gotrel
[j
].types64
;
8263 if (j
!= 0 && GOT_symbol
== NULL
)
8264 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8266 /* The length of the first part of our input line. */
8267 first
= cp
- input_line_pointer
;
8269 /* The second part goes from after the reloc token until
8270 (and including) an end_of_line char or comma. */
8271 past_reloc
= cp
+ 1 + len
;
8273 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8275 second
= cp
+ 1 - past_reloc
;
8277 /* Allocate and copy string. The trailing NUL shouldn't
8278 be necessary, but be safe. */
8279 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8280 memcpy (tmpbuf
, input_line_pointer
, first
);
8281 if (second
!= 0 && *past_reloc
!= ' ')
8282 /* Replace the relocation token with ' ', so that
8283 errors like foo@GOTOFF1 will be detected. */
8284 tmpbuf
[first
++] = ' ';
8286 /* Increment length by 1 if the relocation token is
8291 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8292 tmpbuf
[first
+ second
] = '\0';
8296 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8297 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8302 /* Might be a symbol version string. Don't as_bad here. */
8311 /* Parse operands of the form
8312 <symbol>@SECREL32+<nnn>
8314 If we find one, set up the correct relocation in RELOC and copy the
8315 input string, minus the `@SECREL32' into a malloc'd buffer for
8316 parsing by the calling routine. Return this buffer, and if ADJUST
8317 is non-null set it to the length of the string we removed from the
8318 input line. Otherwise return NULL.
8320 This function is copied from the ELF version above adjusted for PE targets. */
8323 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8324 int *adjust ATTRIBUTE_UNUSED
,
8325 i386_operand_type
*types
)
8331 const enum bfd_reloc_code_real rel
[2];
8332 const i386_operand_type types64
;
8336 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8337 BFD_RELOC_32_SECREL
},
8338 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8344 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8345 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8348 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8350 int len
= gotrel
[j
].len
;
8352 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8354 if (gotrel
[j
].rel
[object_64bit
] != 0)
8357 char *tmpbuf
, *past_reloc
;
8359 *rel
= gotrel
[j
].rel
[object_64bit
];
8365 if (flag_code
!= CODE_64BIT
)
8367 types
->bitfield
.imm32
= 1;
8368 types
->bitfield
.disp32
= 1;
8371 *types
= gotrel
[j
].types64
;
8374 /* The length of the first part of our input line. */
8375 first
= cp
- input_line_pointer
;
8377 /* The second part goes from after the reloc token until
8378 (and including) an end_of_line char or comma. */
8379 past_reloc
= cp
+ 1 + len
;
8381 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8383 second
= cp
+ 1 - past_reloc
;
8385 /* Allocate and copy string. The trailing NUL shouldn't
8386 be necessary, but be safe. */
8387 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8388 memcpy (tmpbuf
, input_line_pointer
, first
);
8389 if (second
!= 0 && *past_reloc
!= ' ')
8390 /* Replace the relocation token with ' ', so that
8391 errors like foo@SECLREL321 will be detected. */
8392 tmpbuf
[first
++] = ' ';
8393 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8394 tmpbuf
[first
+ second
] = '\0';
8398 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8399 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8404 /* Might be a symbol version string. Don't as_bad here. */
8410 bfd_reloc_code_real_type
8411 x86_cons (expressionS
*exp
, int size
)
8413 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8415 intel_syntax
= -intel_syntax
;
8418 if (size
== 4 || (object_64bit
&& size
== 8))
8420 /* Handle @GOTOFF and the like in an expression. */
8422 char *gotfree_input_line
;
8425 save
= input_line_pointer
;
8426 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8427 if (gotfree_input_line
)
8428 input_line_pointer
= gotfree_input_line
;
8432 if (gotfree_input_line
)
8434 /* expression () has merrily parsed up to the end of line,
8435 or a comma - in the wrong buffer. Transfer how far
8436 input_line_pointer has moved to the right buffer. */
8437 input_line_pointer
= (save
8438 + (input_line_pointer
- gotfree_input_line
)
8440 free (gotfree_input_line
);
8441 if (exp
->X_op
== O_constant
8442 || exp
->X_op
== O_absent
8443 || exp
->X_op
== O_illegal
8444 || exp
->X_op
== O_register
8445 || exp
->X_op
== O_big
)
8447 char c
= *input_line_pointer
;
8448 *input_line_pointer
= 0;
8449 as_bad (_("missing or invalid expression `%s'"), save
);
8450 *input_line_pointer
= c
;
8457 intel_syntax
= -intel_syntax
;
8460 i386_intel_simplify (exp
);
8466 signed_cons (int size
)
8468 if (flag_code
== CODE_64BIT
)
8476 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8483 if (exp
.X_op
== O_symbol
)
8484 exp
.X_op
= O_secrel
;
8486 emit_expr (&exp
, 4);
8488 while (*input_line_pointer
++ == ',');
8490 input_line_pointer
--;
8491 demand_empty_rest_of_line ();
8495 /* Handle Vector operations. */
8498 check_VecOperations (char *op_string
, char *op_end
)
8500 const reg_entry
*mask
;
8505 && (op_end
== NULL
|| op_string
< op_end
))
8508 if (*op_string
== '{')
8512 /* Check broadcasts. */
8513 if (strncmp (op_string
, "1to", 3) == 0)
8518 goto duplicated_vec_op
;
8521 if (*op_string
== '8')
8523 else if (*op_string
== '4')
8525 else if (*op_string
== '2')
8527 else if (*op_string
== '1'
8528 && *(op_string
+1) == '6')
8535 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8540 broadcast_op
.type
= bcst_type
;
8541 broadcast_op
.operand
= this_operand
;
8542 i
.broadcast
= &broadcast_op
;
8544 /* Check masking operation. */
8545 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8547 /* k0 can't be used for write mask. */
8548 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8550 as_bad (_("`%s%s' can't be used for write mask"),
8551 register_prefix
, mask
->reg_name
);
8557 mask_op
.mask
= mask
;
8558 mask_op
.zeroing
= 0;
8559 mask_op
.operand
= this_operand
;
8565 goto duplicated_vec_op
;
8567 i
.mask
->mask
= mask
;
8569 /* Only "{z}" is allowed here. No need to check
8570 zeroing mask explicitly. */
8571 if (i
.mask
->operand
!= this_operand
)
8573 as_bad (_("invalid write mask `%s'"), saved
);
8580 /* Check zeroing-flag for masking operation. */
8581 else if (*op_string
== 'z')
8585 mask_op
.mask
= NULL
;
8586 mask_op
.zeroing
= 1;
8587 mask_op
.operand
= this_operand
;
8592 if (i
.mask
->zeroing
)
8595 as_bad (_("duplicated `%s'"), saved
);
8599 i
.mask
->zeroing
= 1;
8601 /* Only "{%k}" is allowed here. No need to check mask
8602 register explicitly. */
8603 if (i
.mask
->operand
!= this_operand
)
8605 as_bad (_("invalid zeroing-masking `%s'"),
8614 goto unknown_vec_op
;
8616 if (*op_string
!= '}')
8618 as_bad (_("missing `}' in `%s'"), saved
);
8623 /* Strip whitespace since the addition of pseudo prefixes
8624 changed how the scrubber treats '{'. */
8625 if (is_space_char (*op_string
))
8631 /* We don't know this one. */
8632 as_bad (_("unknown vector operation: `%s'"), saved
);
8636 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8638 as_bad (_("zeroing-masking only allowed with write mask"));
8646 i386_immediate (char *imm_start
)
8648 char *save_input_line_pointer
;
8649 char *gotfree_input_line
;
8652 i386_operand_type types
;
8654 operand_type_set (&types
, ~0);
8656 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8658 as_bad (_("at most %d immediate operands are allowed"),
8659 MAX_IMMEDIATE_OPERANDS
);
8663 exp
= &im_expressions
[i
.imm_operands
++];
8664 i
.op
[this_operand
].imms
= exp
;
8666 if (is_space_char (*imm_start
))
8669 save_input_line_pointer
= input_line_pointer
;
8670 input_line_pointer
= imm_start
;
8672 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8673 if (gotfree_input_line
)
8674 input_line_pointer
= gotfree_input_line
;
8676 exp_seg
= expression (exp
);
8680 /* Handle vector operations. */
8681 if (*input_line_pointer
== '{')
8683 input_line_pointer
= check_VecOperations (input_line_pointer
,
8685 if (input_line_pointer
== NULL
)
8689 if (*input_line_pointer
)
8690 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8692 input_line_pointer
= save_input_line_pointer
;
8693 if (gotfree_input_line
)
8695 free (gotfree_input_line
);
8697 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8698 exp
->X_op
= O_illegal
;
8701 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8705 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8706 i386_operand_type types
, const char *imm_start
)
8708 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8711 as_bad (_("missing or invalid immediate expression `%s'"),
8715 else if (exp
->X_op
== O_constant
)
8717 /* Size it properly later. */
8718 i
.types
[this_operand
].bitfield
.imm64
= 1;
8719 /* If not 64bit, sign extend val. */
8720 if (flag_code
!= CODE_64BIT
8721 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8723 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8725 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8726 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8727 && exp_seg
!= absolute_section
8728 && exp_seg
!= text_section
8729 && exp_seg
!= data_section
8730 && exp_seg
!= bss_section
8731 && exp_seg
!= undefined_section
8732 && !bfd_is_com_section (exp_seg
))
8734 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8738 else if (!intel_syntax
&& exp_seg
== reg_section
)
8741 as_bad (_("illegal immediate register operand %s"), imm_start
);
8746 /* This is an address. The size of the address will be
8747 determined later, depending on destination register,
8748 suffix, or the default for the section. */
8749 i
.types
[this_operand
].bitfield
.imm8
= 1;
8750 i
.types
[this_operand
].bitfield
.imm16
= 1;
8751 i
.types
[this_operand
].bitfield
.imm32
= 1;
8752 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8753 i
.types
[this_operand
].bitfield
.imm64
= 1;
8754 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8762 i386_scale (char *scale
)
8765 char *save
= input_line_pointer
;
8767 input_line_pointer
= scale
;
8768 val
= get_absolute_expression ();
8773 i
.log2_scale_factor
= 0;
8776 i
.log2_scale_factor
= 1;
8779 i
.log2_scale_factor
= 2;
8782 i
.log2_scale_factor
= 3;
8786 char sep
= *input_line_pointer
;
8788 *input_line_pointer
= '\0';
8789 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8791 *input_line_pointer
= sep
;
8792 input_line_pointer
= save
;
8796 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8798 as_warn (_("scale factor of %d without an index register"),
8799 1 << i
.log2_scale_factor
);
8800 i
.log2_scale_factor
= 0;
8802 scale
= input_line_pointer
;
8803 input_line_pointer
= save
;
8808 i386_displacement (char *disp_start
, char *disp_end
)
8812 char *save_input_line_pointer
;
8813 char *gotfree_input_line
;
8815 i386_operand_type bigdisp
, types
= anydisp
;
8818 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8820 as_bad (_("at most %d displacement operands are allowed"),
8821 MAX_MEMORY_OPERANDS
);
8825 operand_type_set (&bigdisp
, 0);
8826 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8827 || (!current_templates
->start
->opcode_modifier
.jump
8828 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8830 bigdisp
.bitfield
.disp32
= 1;
8831 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8832 if (flag_code
== CODE_64BIT
)
8836 bigdisp
.bitfield
.disp32s
= 1;
8837 bigdisp
.bitfield
.disp64
= 1;
8840 else if ((flag_code
== CODE_16BIT
) ^ override
)
8842 bigdisp
.bitfield
.disp32
= 0;
8843 bigdisp
.bitfield
.disp16
= 1;
8848 /* For PC-relative branches, the width of the displacement
8849 is dependent upon data size, not address size. */
8850 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8851 if (flag_code
== CODE_64BIT
)
8853 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8854 bigdisp
.bitfield
.disp16
= 1;
8857 bigdisp
.bitfield
.disp32
= 1;
8858 bigdisp
.bitfield
.disp32s
= 1;
8864 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8866 : LONG_MNEM_SUFFIX
));
8867 bigdisp
.bitfield
.disp32
= 1;
8868 if ((flag_code
== CODE_16BIT
) ^ override
)
8870 bigdisp
.bitfield
.disp32
= 0;
8871 bigdisp
.bitfield
.disp16
= 1;
8875 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8878 exp
= &disp_expressions
[i
.disp_operands
];
8879 i
.op
[this_operand
].disps
= exp
;
8881 save_input_line_pointer
= input_line_pointer
;
8882 input_line_pointer
= disp_start
;
8883 END_STRING_AND_SAVE (disp_end
);
8885 #ifndef GCC_ASM_O_HACK
8886 #define GCC_ASM_O_HACK 0
8889 END_STRING_AND_SAVE (disp_end
+ 1);
8890 if (i
.types
[this_operand
].bitfield
.baseIndex
8891 && displacement_string_end
[-1] == '+')
8893 /* This hack is to avoid a warning when using the "o"
8894 constraint within gcc asm statements.
8897 #define _set_tssldt_desc(n,addr,limit,type) \
8898 __asm__ __volatile__ ( \
8900 "movw %w1,2+%0\n\t" \
8902 "movb %b1,4+%0\n\t" \
8903 "movb %4,5+%0\n\t" \
8904 "movb $0,6+%0\n\t" \
8905 "movb %h1,7+%0\n\t" \
8907 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8909 This works great except that the output assembler ends
8910 up looking a bit weird if it turns out that there is
8911 no offset. You end up producing code that looks like:
8924 So here we provide the missing zero. */
8926 *displacement_string_end
= '0';
8929 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8930 if (gotfree_input_line
)
8931 input_line_pointer
= gotfree_input_line
;
8933 exp_seg
= expression (exp
);
8936 if (*input_line_pointer
)
8937 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8939 RESTORE_END_STRING (disp_end
+ 1);
8941 input_line_pointer
= save_input_line_pointer
;
8942 if (gotfree_input_line
)
8944 free (gotfree_input_line
);
8946 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8947 exp
->X_op
= O_illegal
;
8950 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8952 RESTORE_END_STRING (disp_end
);
8958 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8959 i386_operand_type types
, const char *disp_start
)
8961 i386_operand_type bigdisp
;
8964 /* We do this to make sure that the section symbol is in
8965 the symbol table. We will ultimately change the relocation
8966 to be relative to the beginning of the section. */
8967 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8968 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8969 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8971 if (exp
->X_op
!= O_symbol
)
8974 if (S_IS_LOCAL (exp
->X_add_symbol
)
8975 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8976 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8977 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8978 exp
->X_op
= O_subtract
;
8979 exp
->X_op_symbol
= GOT_symbol
;
8980 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8981 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8982 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8983 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8985 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8988 else if (exp
->X_op
== O_absent
8989 || exp
->X_op
== O_illegal
8990 || exp
->X_op
== O_big
)
8993 as_bad (_("missing or invalid displacement expression `%s'"),
8998 else if (flag_code
== CODE_64BIT
8999 && !i
.prefix
[ADDR_PREFIX
]
9000 && exp
->X_op
== O_constant
)
9002 /* Since displacement is signed extended to 64bit, don't allow
9003 disp32 and turn off disp32s if they are out of range. */
9004 i
.types
[this_operand
].bitfield
.disp32
= 0;
9005 if (!fits_in_signed_long (exp
->X_add_number
))
9007 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9008 if (i
.types
[this_operand
].bitfield
.baseindex
)
9010 as_bad (_("0x%lx out range of signed 32bit displacement"),
9011 (long) exp
->X_add_number
);
9017 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9018 else if (exp
->X_op
!= O_constant
9019 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9020 && exp_seg
!= absolute_section
9021 && exp_seg
!= text_section
9022 && exp_seg
!= data_section
9023 && exp_seg
!= bss_section
9024 && exp_seg
!= undefined_section
9025 && !bfd_is_com_section (exp_seg
))
9027 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9032 /* Check if this is a displacement only operand. */
9033 bigdisp
= i
.types
[this_operand
];
9034 bigdisp
.bitfield
.disp8
= 0;
9035 bigdisp
.bitfield
.disp16
= 0;
9036 bigdisp
.bitfield
.disp32
= 0;
9037 bigdisp
.bitfield
.disp32s
= 0;
9038 bigdisp
.bitfield
.disp64
= 0;
9039 if (operand_type_all_zero (&bigdisp
))
9040 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9046 /* Return the active addressing mode, taking address override and
9047 registers forming the address into consideration. Update the
9048 address override prefix if necessary. */
9050 static enum flag_code
9051 i386_addressing_mode (void)
9053 enum flag_code addr_mode
;
9055 if (i
.prefix
[ADDR_PREFIX
])
9056 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9059 addr_mode
= flag_code
;
9061 #if INFER_ADDR_PREFIX
9062 if (i
.mem_operands
== 0)
9064 /* Infer address prefix from the first memory operand. */
9065 const reg_entry
*addr_reg
= i
.base_reg
;
9067 if (addr_reg
== NULL
)
9068 addr_reg
= i
.index_reg
;
9072 if (addr_reg
->reg_num
== RegEip
9073 || addr_reg
->reg_num
== RegEiz
9074 || addr_reg
->reg_type
.bitfield
.dword
)
9075 addr_mode
= CODE_32BIT
;
9076 else if (flag_code
!= CODE_64BIT
9077 && addr_reg
->reg_type
.bitfield
.word
)
9078 addr_mode
= CODE_16BIT
;
9080 if (addr_mode
!= flag_code
)
9082 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9084 /* Change the size of any displacement too. At most one
9085 of Disp16 or Disp32 is set.
9086 FIXME. There doesn't seem to be any real need for
9087 separate Disp16 and Disp32 flags. The same goes for
9088 Imm16 and Imm32. Removing them would probably clean
9089 up the code quite a lot. */
9090 if (flag_code
!= CODE_64BIT
9091 && (i
.types
[this_operand
].bitfield
.disp16
9092 || i
.types
[this_operand
].bitfield
.disp32
))
9093 i
.types
[this_operand
]
9094 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9104 /* Make sure the memory operand we've been dealt is valid.
9105 Return 1 on success, 0 on a failure. */
9108 i386_index_check (const char *operand_string
)
9110 const char *kind
= "base/index";
9111 enum flag_code addr_mode
= i386_addressing_mode ();
9113 if (current_templates
->start
->opcode_modifier
.isstring
9114 && !current_templates
->start
->opcode_modifier
.immext
9115 && (current_templates
->end
[-1].opcode_modifier
.isstring
9118 /* Memory operands of string insns are special in that they only allow
9119 a single register (rDI, rSI, or rBX) as their memory address. */
9120 const reg_entry
*expected_reg
;
9121 static const char *di_si
[][2] =
9127 static const char *bx
[] = { "ebx", "bx", "rbx" };
9129 kind
= "string address";
9131 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9133 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9135 if (!type
.bitfield
.baseindex
9136 || ((!i
.mem_operands
!= !intel_syntax
)
9137 && current_templates
->end
[-1].operand_types
[1]
9138 .bitfield
.baseindex
))
9139 type
= current_templates
->end
[-1].operand_types
[1];
9140 expected_reg
= hash_find (reg_hash
,
9141 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9145 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9147 if (i
.base_reg
!= expected_reg
9149 || operand_type_check (i
.types
[this_operand
], disp
))
9151 /* The second memory operand must have the same size as
9155 && !((addr_mode
== CODE_64BIT
9156 && i
.base_reg
->reg_type
.bitfield
.qword
)
9157 || (addr_mode
== CODE_32BIT
9158 ? i
.base_reg
->reg_type
.bitfield
.dword
9159 : i
.base_reg
->reg_type
.bitfield
.word
)))
9162 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9164 intel_syntax
? '[' : '(',
9166 expected_reg
->reg_name
,
9167 intel_syntax
? ']' : ')');
9174 as_bad (_("`%s' is not a valid %s expression"),
9175 operand_string
, kind
);
9180 if (addr_mode
!= CODE_16BIT
)
9182 /* 32-bit/64-bit checks. */
9184 && (addr_mode
== CODE_64BIT
9185 ? !i
.base_reg
->reg_type
.bitfield
.qword
9186 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9188 || (i
.base_reg
->reg_num
9189 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9191 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9192 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9193 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9194 && ((addr_mode
== CODE_64BIT
9195 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9196 || i
.index_reg
->reg_num
== RegRiz
)
9197 : !(i
.index_reg
->reg_type
.bitfield
.dword
9198 || i
.index_reg
->reg_num
== RegEiz
))
9199 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9202 /* bndmk, bndldx, and bndstx have special restrictions. */
9203 if (current_templates
->start
->base_opcode
== 0xf30f1b
9204 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9206 /* They cannot use RIP-relative addressing. */
9207 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9209 as_bad (_("`%s' cannot be used here"), operand_string
);
9213 /* bndldx and bndstx ignore their scale factor. */
9214 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9215 && i
.log2_scale_factor
)
9216 as_warn (_("register scaling is being ignored here"));
9221 /* 16-bit checks. */
9223 && (!i
.base_reg
->reg_type
.bitfield
.word
9224 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9226 && (!i
.index_reg
->reg_type
.bitfield
.word
9227 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9229 && i
.base_reg
->reg_num
< 6
9230 && i
.index_reg
->reg_num
>= 6
9231 && i
.log2_scale_factor
== 0))))
9238 /* Handle vector immediates. */
9241 RC_SAE_immediate (const char *imm_start
)
9243 unsigned int match_found
, j
;
9244 const char *pstr
= imm_start
;
9252 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9254 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9258 rc_op
.type
= RC_NamesTable
[j
].type
;
9259 rc_op
.operand
= this_operand
;
9260 i
.rounding
= &rc_op
;
9264 as_bad (_("duplicated `%s'"), imm_start
);
9267 pstr
+= RC_NamesTable
[j
].len
;
9277 as_bad (_("Missing '}': '%s'"), imm_start
);
9280 /* RC/SAE immediate string should contain nothing more. */;
9283 as_bad (_("Junk after '}': '%s'"), imm_start
);
9287 exp
= &im_expressions
[i
.imm_operands
++];
9288 i
.op
[this_operand
].imms
= exp
;
9290 exp
->X_op
= O_constant
;
9291 exp
->X_add_number
= 0;
9292 exp
->X_add_symbol
= (symbolS
*) 0;
9293 exp
->X_op_symbol
= (symbolS
*) 0;
9295 i
.types
[this_operand
].bitfield
.imm8
= 1;
9299 /* Only string instructions can have a second memory operand, so
9300 reduce current_templates to just those if it contains any. */
9302 maybe_adjust_templates (void)
9304 const insn_template
*t
;
9306 gas_assert (i
.mem_operands
== 1);
9308 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9309 if (t
->opcode_modifier
.isstring
)
9312 if (t
< current_templates
->end
)
9314 static templates aux_templates
;
9315 bfd_boolean recheck
;
9317 aux_templates
.start
= t
;
9318 for (; t
< current_templates
->end
; ++t
)
9319 if (!t
->opcode_modifier
.isstring
)
9321 aux_templates
.end
= t
;
9323 /* Determine whether to re-check the first memory operand. */
9324 recheck
= (aux_templates
.start
!= current_templates
->start
9325 || t
!= current_templates
->end
);
9327 current_templates
= &aux_templates
;
9332 if (i
.memop1_string
!= NULL
9333 && i386_index_check (i
.memop1_string
) == 0)
9342 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9346 i386_att_operand (char *operand_string
)
9350 char *op_string
= operand_string
;
9352 if (is_space_char (*op_string
))
9355 /* We check for an absolute prefix (differentiating,
9356 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9357 if (*op_string
== ABSOLUTE_PREFIX
)
9360 if (is_space_char (*op_string
))
9362 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9365 /* Check if operand is a register. */
9366 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9368 i386_operand_type temp
;
9370 /* Check for a segment override by searching for ':' after a
9371 segment register. */
9373 if (is_space_char (*op_string
))
9375 if (*op_string
== ':'
9376 && (r
->reg_type
.bitfield
.sreg2
9377 || r
->reg_type
.bitfield
.sreg3
))
9382 i
.seg
[i
.mem_operands
] = &es
;
9385 i
.seg
[i
.mem_operands
] = &cs
;
9388 i
.seg
[i
.mem_operands
] = &ss
;
9391 i
.seg
[i
.mem_operands
] = &ds
;
9394 i
.seg
[i
.mem_operands
] = &fs
;
9397 i
.seg
[i
.mem_operands
] = &gs
;
9401 /* Skip the ':' and whitespace. */
9403 if (is_space_char (*op_string
))
9406 if (!is_digit_char (*op_string
)
9407 && !is_identifier_char (*op_string
)
9408 && *op_string
!= '('
9409 && *op_string
!= ABSOLUTE_PREFIX
)
9411 as_bad (_("bad memory operand `%s'"), op_string
);
9414 /* Handle case of %es:*foo. */
9415 if (*op_string
== ABSOLUTE_PREFIX
)
9418 if (is_space_char (*op_string
))
9420 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9422 goto do_memory_reference
;
9425 /* Handle vector operations. */
9426 if (*op_string
== '{')
9428 op_string
= check_VecOperations (op_string
, NULL
);
9429 if (op_string
== NULL
)
9435 as_bad (_("junk `%s' after register"), op_string
);
9439 temp
.bitfield
.baseindex
= 0;
9440 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9442 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9443 i
.op
[this_operand
].regs
= r
;
9446 else if (*op_string
== REGISTER_PREFIX
)
9448 as_bad (_("bad register name `%s'"), op_string
);
9451 else if (*op_string
== IMMEDIATE_PREFIX
)
9454 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9456 as_bad (_("immediate operand illegal with absolute jump"));
9459 if (!i386_immediate (op_string
))
9462 else if (RC_SAE_immediate (operand_string
))
9464 /* If it is a RC or SAE immediate, do nothing. */
9467 else if (is_digit_char (*op_string
)
9468 || is_identifier_char (*op_string
)
9469 || *op_string
== '"'
9470 || *op_string
== '(')
9472 /* This is a memory reference of some sort. */
9475 /* Start and end of displacement string expression (if found). */
9476 char *displacement_string_start
;
9477 char *displacement_string_end
;
9480 do_memory_reference
:
9481 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9483 if ((i
.mem_operands
== 1
9484 && !current_templates
->start
->opcode_modifier
.isstring
)
9485 || i
.mem_operands
== 2)
9487 as_bad (_("too many memory references for `%s'"),
9488 current_templates
->start
->name
);
9492 /* Check for base index form. We detect the base index form by
9493 looking for an ')' at the end of the operand, searching
9494 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9496 base_string
= op_string
+ strlen (op_string
);
9498 /* Handle vector operations. */
9499 vop_start
= strchr (op_string
, '{');
9500 if (vop_start
&& vop_start
< base_string
)
9502 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9504 base_string
= vop_start
;
9508 if (is_space_char (*base_string
))
9511 /* If we only have a displacement, set-up for it to be parsed later. */
9512 displacement_string_start
= op_string
;
9513 displacement_string_end
= base_string
+ 1;
9515 if (*base_string
== ')')
9518 unsigned int parens_balanced
= 1;
9519 /* We've already checked that the number of left & right ()'s are
9520 equal, so this loop will not be infinite. */
9524 if (*base_string
== ')')
9526 if (*base_string
== '(')
9529 while (parens_balanced
);
9531 temp_string
= base_string
;
9533 /* Skip past '(' and whitespace. */
9535 if (is_space_char (*base_string
))
9538 if (*base_string
== ','
9539 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9542 displacement_string_end
= temp_string
;
9544 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9548 base_string
= end_op
;
9549 if (is_space_char (*base_string
))
9553 /* There may be an index reg or scale factor here. */
9554 if (*base_string
== ',')
9557 if (is_space_char (*base_string
))
9560 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9563 base_string
= end_op
;
9564 if (is_space_char (*base_string
))
9566 if (*base_string
== ',')
9569 if (is_space_char (*base_string
))
9572 else if (*base_string
!= ')')
9574 as_bad (_("expecting `,' or `)' "
9575 "after index register in `%s'"),
9580 else if (*base_string
== REGISTER_PREFIX
)
9582 end_op
= strchr (base_string
, ',');
9585 as_bad (_("bad register name `%s'"), base_string
);
9589 /* Check for scale factor. */
9590 if (*base_string
!= ')')
9592 char *end_scale
= i386_scale (base_string
);
9597 base_string
= end_scale
;
9598 if (is_space_char (*base_string
))
9600 if (*base_string
!= ')')
9602 as_bad (_("expecting `)' "
9603 "after scale factor in `%s'"),
9608 else if (!i
.index_reg
)
9610 as_bad (_("expecting index register or scale factor "
9611 "after `,'; got '%c'"),
9616 else if (*base_string
!= ')')
9618 as_bad (_("expecting `,' or `)' "
9619 "after base register in `%s'"),
9624 else if (*base_string
== REGISTER_PREFIX
)
9626 end_op
= strchr (base_string
, ',');
9629 as_bad (_("bad register name `%s'"), base_string
);
9634 /* If there's an expression beginning the operand, parse it,
9635 assuming displacement_string_start and
9636 displacement_string_end are meaningful. */
9637 if (displacement_string_start
!= displacement_string_end
)
9639 if (!i386_displacement (displacement_string_start
,
9640 displacement_string_end
))
9644 /* Special case for (%dx) while doing input/output op. */
9646 && operand_type_equal (&i
.base_reg
->reg_type
,
9647 ®16_inoutportreg
)
9649 && i
.log2_scale_factor
== 0
9650 && i
.seg
[i
.mem_operands
] == 0
9651 && !operand_type_check (i
.types
[this_operand
], disp
))
9653 i
.types
[this_operand
] = inoutportreg
;
9657 if (i386_index_check (operand_string
) == 0)
9659 i
.types
[this_operand
].bitfield
.mem
= 1;
9660 if (i
.mem_operands
== 0)
9661 i
.memop1_string
= xstrdup (operand_string
);
9666 /* It's not a memory operand; argh! */
9667 as_bad (_("invalid char %s beginning operand %d `%s'"),
9668 output_invalid (*op_string
),
9673 return 1; /* Normal return. */
9676 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9677 that an rs_machine_dependent frag may reach. */
9680 i386_frag_max_var (fragS
*frag
)
9682 /* The only relaxable frags are for jumps.
9683 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9684 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9685 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9690 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9692 /* STT_GNU_IFUNC symbol must go through PLT. */
9693 if ((symbol_get_bfdsym (fr_symbol
)->flags
9694 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9697 if (!S_IS_EXTERNAL (fr_symbol
))
9698 /* Symbol may be weak or local. */
9699 return !S_IS_WEAK (fr_symbol
);
9701 /* Global symbols with non-default visibility can't be preempted. */
9702 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9705 if (fr_var
!= NO_RELOC
)
9706 switch ((enum bfd_reloc_code_real
) fr_var
)
9708 case BFD_RELOC_386_PLT32
:
9709 case BFD_RELOC_X86_64_PLT32
:
9710 /* Symbol with PLT relocation may be preempted. */
9716 /* Global symbols with default visibility in a shared library may be
9717 preempted by another definition. */
9722 /* md_estimate_size_before_relax()
9724 Called just before relax() for rs_machine_dependent frags. The x86
9725 assembler uses these frags to handle variable size jump
9728 Any symbol that is now undefined will not become defined.
9729 Return the correct fr_subtype in the frag.
9730 Return the initial "guess for variable size of frag" to caller.
9731 The guess is actually the growth beyond the fixed part. Whatever
9732 we do to grow the fixed or variable part contributes to our
9736 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9738 /* We've already got fragP->fr_subtype right; all we have to do is
9739 check for un-relaxable symbols. On an ELF system, we can't relax
9740 an externally visible symbol, because it may be overridden by a
9742 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9745 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9748 #if defined (OBJ_COFF) && defined (TE_PE)
9749 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9750 && S_IS_WEAK (fragP
->fr_symbol
))
9754 /* Symbol is undefined in this segment, or we need to keep a
9755 reloc so that weak symbols can be overridden. */
9756 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9757 enum bfd_reloc_code_real reloc_type
;
9758 unsigned char *opcode
;
9761 if (fragP
->fr_var
!= NO_RELOC
)
9762 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9764 reloc_type
= BFD_RELOC_16_PCREL
;
9765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9766 else if (need_plt32_p (fragP
->fr_symbol
))
9767 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9770 reloc_type
= BFD_RELOC_32_PCREL
;
9772 old_fr_fix
= fragP
->fr_fix
;
9773 opcode
= (unsigned char *) fragP
->fr_opcode
;
9775 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9778 /* Make jmp (0xeb) a (d)word displacement jump. */
9780 fragP
->fr_fix
+= size
;
9781 fix_new (fragP
, old_fr_fix
, size
,
9783 fragP
->fr_offset
, 1,
9789 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9791 /* Negate the condition, and branch past an
9792 unconditional jump. */
9795 /* Insert an unconditional jump. */
9797 /* We added two extra opcode bytes, and have a two byte
9799 fragP
->fr_fix
+= 2 + 2;
9800 fix_new (fragP
, old_fr_fix
+ 2, 2,
9802 fragP
->fr_offset
, 1,
9809 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9814 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9816 fragP
->fr_offset
, 1,
9818 fixP
->fx_signed
= 1;
9822 /* This changes the byte-displacement jump 0x7N
9823 to the (d)word-displacement jump 0x0f,0x8N. */
9824 opcode
[1] = opcode
[0] + 0x10;
9825 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9826 /* We've added an opcode byte. */
9827 fragP
->fr_fix
+= 1 + size
;
9828 fix_new (fragP
, old_fr_fix
+ 1, size
,
9830 fragP
->fr_offset
, 1,
9835 BAD_CASE (fragP
->fr_subtype
);
9839 return fragP
->fr_fix
- old_fr_fix
;
9842 /* Guess size depending on current relax state. Initially the relax
9843 state will correspond to a short jump and we return 1, because
9844 the variable part of the frag (the branch offset) is one byte
9845 long. However, we can relax a section more than once and in that
9846 case we must either set fr_subtype back to the unrelaxed state,
9847 or return the value for the appropriate branch. */
9848 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9851 /* Called after relax() is finished.
9853 In: Address of frag.
9854 fr_type == rs_machine_dependent.
9855 fr_subtype is what the address relaxed to.
9857 Out: Any fixSs and constants are set up.
9858 Caller will turn frag into a ".space 0". */
9861 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9864 unsigned char *opcode
;
9865 unsigned char *where_to_put_displacement
= NULL
;
9866 offsetT target_address
;
9867 offsetT opcode_address
;
9868 unsigned int extension
= 0;
9869 offsetT displacement_from_opcode_start
;
9871 opcode
= (unsigned char *) fragP
->fr_opcode
;
9873 /* Address we want to reach in file space. */
9874 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9876 /* Address opcode resides at in file space. */
9877 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9879 /* Displacement from opcode start to fill into instruction. */
9880 displacement_from_opcode_start
= target_address
- opcode_address
;
9882 if ((fragP
->fr_subtype
& BIG
) == 0)
9884 /* Don't have to change opcode. */
9885 extension
= 1; /* 1 opcode + 1 displacement */
9886 where_to_put_displacement
= &opcode
[1];
9890 if (no_cond_jump_promotion
9891 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9892 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9893 _("long jump required"));
9895 switch (fragP
->fr_subtype
)
9897 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9898 extension
= 4; /* 1 opcode + 4 displacement */
9900 where_to_put_displacement
= &opcode
[1];
9903 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9904 extension
= 2; /* 1 opcode + 2 displacement */
9906 where_to_put_displacement
= &opcode
[1];
9909 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9910 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9911 extension
= 5; /* 2 opcode + 4 displacement */
9912 opcode
[1] = opcode
[0] + 0x10;
9913 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9914 where_to_put_displacement
= &opcode
[2];
9917 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9918 extension
= 3; /* 2 opcode + 2 displacement */
9919 opcode
[1] = opcode
[0] + 0x10;
9920 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9921 where_to_put_displacement
= &opcode
[2];
9924 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9929 where_to_put_displacement
= &opcode
[3];
9933 BAD_CASE (fragP
->fr_subtype
);
9938 /* If size if less then four we are sure that the operand fits,
9939 but if it's 4, then it could be that the displacement is larger
9941 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9943 && ((addressT
) (displacement_from_opcode_start
- extension
9944 + ((addressT
) 1 << 31))
9945 > (((addressT
) 2 << 31) - 1)))
9947 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9948 _("jump target out of range"));
9949 /* Make us emit 0. */
9950 displacement_from_opcode_start
= extension
;
9952 /* Now put displacement after opcode. */
9953 md_number_to_chars ((char *) where_to_put_displacement
,
9954 (valueT
) (displacement_from_opcode_start
- extension
),
9955 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9956 fragP
->fr_fix
+= extension
;
9959 /* Apply a fixup (fixP) to segment data, once it has been determined
9960 by our caller that we have all the info we need to fix it up.
9962 Parameter valP is the pointer to the value of the bits.
9964 On the 386, immediates, displacements, and data pointers are all in
9965 the same (little-endian) format, so we don't need to care about which
9969 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9971 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9972 valueT value
= *valP
;
9974 #if !defined (TE_Mach)
9977 switch (fixP
->fx_r_type
)
9983 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9986 case BFD_RELOC_X86_64_32S
:
9987 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9990 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9993 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9998 if (fixP
->fx_addsy
!= NULL
9999 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10000 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10001 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10002 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10003 && !use_rela_relocations
)
10005 /* This is a hack. There should be a better way to handle this.
10006 This covers for the fact that bfd_install_relocation will
10007 subtract the current location (for partial_inplace, PC relative
10008 relocations); see more below. */
10012 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10015 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10020 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10022 if ((sym_seg
== seg
10023 || (symbol_section_p (fixP
->fx_addsy
)
10024 && sym_seg
!= absolute_section
))
10025 && !generic_force_reloc (fixP
))
10027 /* Yes, we add the values in twice. This is because
10028 bfd_install_relocation subtracts them out again. I think
10029 bfd_install_relocation is broken, but I don't dare change
10031 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10035 #if defined (OBJ_COFF) && defined (TE_PE)
10036 /* For some reason, the PE format does not store a
10037 section address offset for a PC relative symbol. */
10038 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10039 || S_IS_WEAK (fixP
->fx_addsy
))
10040 value
+= md_pcrel_from (fixP
);
10043 #if defined (OBJ_COFF) && defined (TE_PE)
10044 if (fixP
->fx_addsy
!= NULL
10045 && S_IS_WEAK (fixP
->fx_addsy
)
10046 /* PR 16858: Do not modify weak function references. */
10047 && ! fixP
->fx_pcrel
)
10049 #if !defined (TE_PEP)
10050 /* For x86 PE weak function symbols are neither PC-relative
10051 nor do they set S_IS_FUNCTION. So the only reliable way
10052 to detect them is to check the flags of their containing
10054 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10055 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10059 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10063 /* Fix a few things - the dynamic linker expects certain values here,
10064 and we must not disappoint it. */
10065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10066 if (IS_ELF
&& fixP
->fx_addsy
)
10067 switch (fixP
->fx_r_type
)
10069 case BFD_RELOC_386_PLT32
:
10070 case BFD_RELOC_X86_64_PLT32
:
10071 /* Make the jump instruction point to the address of the operand. At
10072 runtime we merely add the offset to the actual PLT entry. */
10076 case BFD_RELOC_386_TLS_GD
:
10077 case BFD_RELOC_386_TLS_LDM
:
10078 case BFD_RELOC_386_TLS_IE_32
:
10079 case BFD_RELOC_386_TLS_IE
:
10080 case BFD_RELOC_386_TLS_GOTIE
:
10081 case BFD_RELOC_386_TLS_GOTDESC
:
10082 case BFD_RELOC_X86_64_TLSGD
:
10083 case BFD_RELOC_X86_64_TLSLD
:
10084 case BFD_RELOC_X86_64_GOTTPOFF
:
10085 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10086 value
= 0; /* Fully resolved at runtime. No addend. */
10088 case BFD_RELOC_386_TLS_LE
:
10089 case BFD_RELOC_386_TLS_LDO_32
:
10090 case BFD_RELOC_386_TLS_LE_32
:
10091 case BFD_RELOC_X86_64_DTPOFF32
:
10092 case BFD_RELOC_X86_64_DTPOFF64
:
10093 case BFD_RELOC_X86_64_TPOFF32
:
10094 case BFD_RELOC_X86_64_TPOFF64
:
10095 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10098 case BFD_RELOC_386_TLS_DESC_CALL
:
10099 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10100 value
= 0; /* Fully resolved at runtime. No addend. */
10101 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10105 case BFD_RELOC_VTABLE_INHERIT
:
10106 case BFD_RELOC_VTABLE_ENTRY
:
10113 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10115 #endif /* !defined (TE_Mach) */
10117 /* Are we finished with this relocation now? */
10118 if (fixP
->fx_addsy
== NULL
)
10120 #if defined (OBJ_COFF) && defined (TE_PE)
10121 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10124 /* Remember value for tc_gen_reloc. */
10125 fixP
->fx_addnumber
= value
;
10126 /* Clear out the frag for now. */
10130 else if (use_rela_relocations
)
10132 fixP
->fx_no_overflow
= 1;
10133 /* Remember value for tc_gen_reloc. */
10134 fixP
->fx_addnumber
= value
;
10138 md_number_to_chars (p
, value
, fixP
->fx_size
);
10142 md_atof (int type
, char *litP
, int *sizeP
)
10144 /* This outputs the LITTLENUMs in REVERSE order;
10145 in accord with the bigendian 386. */
10146 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10149 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10152 output_invalid (int c
)
10155 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10158 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10159 "(0x%x)", (unsigned char) c
);
10160 return output_invalid_buf
;
10163 /* REG_STRING starts *before* REGISTER_PREFIX. */
10165 static const reg_entry
*
10166 parse_real_register (char *reg_string
, char **end_op
)
10168 char *s
= reg_string
;
10170 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10171 const reg_entry
*r
;
10173 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10174 if (*s
== REGISTER_PREFIX
)
10177 if (is_space_char (*s
))
10180 p
= reg_name_given
;
10181 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10183 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10184 return (const reg_entry
*) NULL
;
10188 /* For naked regs, make sure that we are not dealing with an identifier.
10189 This prevents confusing an identifier like `eax_var' with register
10191 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10192 return (const reg_entry
*) NULL
;
10196 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10198 /* Handle floating point regs, allowing spaces in the (i) part. */
10199 if (r
== i386_regtab
/* %st is first entry of table */)
10201 if (!cpu_arch_flags
.bitfield
.cpu8087
10202 && !cpu_arch_flags
.bitfield
.cpu287
10203 && !cpu_arch_flags
.bitfield
.cpu387
)
10204 return (const reg_entry
*) NULL
;
10206 if (is_space_char (*s
))
10211 if (is_space_char (*s
))
10213 if (*s
>= '0' && *s
<= '7')
10215 int fpr
= *s
- '0';
10217 if (is_space_char (*s
))
10222 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10227 /* We have "%st(" then garbage. */
10228 return (const reg_entry
*) NULL
;
10232 if (r
== NULL
|| allow_pseudo_reg
)
10235 if (operand_type_all_zero (&r
->reg_type
))
10236 return (const reg_entry
*) NULL
;
10238 if ((r
->reg_type
.bitfield
.dword
10239 || r
->reg_type
.bitfield
.sreg3
10240 || r
->reg_type
.bitfield
.control
10241 || r
->reg_type
.bitfield
.debug
10242 || r
->reg_type
.bitfield
.test
)
10243 && !cpu_arch_flags
.bitfield
.cpui386
)
10244 return (const reg_entry
*) NULL
;
10246 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10247 return (const reg_entry
*) NULL
;
10249 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10251 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10252 return (const reg_entry
*) NULL
;
10254 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10256 if (r
->reg_type
.bitfield
.ymmword
)
10257 return (const reg_entry
*) NULL
;
10259 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10260 return (const reg_entry
*) NULL
;
10264 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10265 return (const reg_entry
*) NULL
;
10267 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10268 if (!allow_index_reg
10269 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10270 return (const reg_entry
*) NULL
;
10272 /* Upper 16 vector registers are only available with VREX in 64bit
10273 mode, and require EVEX encoding. */
10274 if (r
->reg_flags
& RegVRex
)
10276 if (!cpu_arch_flags
.bitfield
.cpuvrex
10277 || flag_code
!= CODE_64BIT
)
10278 return (const reg_entry
*) NULL
;
10280 i
.vec_encoding
= vex_encoding_evex
;
10283 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10284 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10285 && flag_code
!= CODE_64BIT
)
10286 return (const reg_entry
*) NULL
;
10288 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10289 return (const reg_entry
*) NULL
;
10294 /* REG_STRING starts *before* REGISTER_PREFIX. */
10296 static const reg_entry
*
10297 parse_register (char *reg_string
, char **end_op
)
10299 const reg_entry
*r
;
10301 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10302 r
= parse_real_register (reg_string
, end_op
);
10307 char *save
= input_line_pointer
;
10311 input_line_pointer
= reg_string
;
10312 c
= get_symbol_name (®_string
);
10313 symbolP
= symbol_find (reg_string
);
10314 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10316 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10318 know (e
->X_op
== O_register
);
10319 know (e
->X_add_number
>= 0
10320 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10321 r
= i386_regtab
+ e
->X_add_number
;
10322 if ((r
->reg_flags
& RegVRex
))
10323 i
.vec_encoding
= vex_encoding_evex
;
10324 *end_op
= input_line_pointer
;
10326 *input_line_pointer
= c
;
10327 input_line_pointer
= save
;
10333 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10335 const reg_entry
*r
;
10336 char *end
= input_line_pointer
;
10339 r
= parse_register (name
, &input_line_pointer
);
10340 if (r
&& end
<= input_line_pointer
)
10342 *nextcharP
= *input_line_pointer
;
10343 *input_line_pointer
= 0;
10344 e
->X_op
= O_register
;
10345 e
->X_add_number
= r
- i386_regtab
;
10348 input_line_pointer
= end
;
10350 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10354 md_operand (expressionS
*e
)
10357 const reg_entry
*r
;
10359 switch (*input_line_pointer
)
10361 case REGISTER_PREFIX
:
10362 r
= parse_real_register (input_line_pointer
, &end
);
10365 e
->X_op
= O_register
;
10366 e
->X_add_number
= r
- i386_regtab
;
10367 input_line_pointer
= end
;
10372 gas_assert (intel_syntax
);
10373 end
= input_line_pointer
++;
10375 if (*input_line_pointer
== ']')
10377 ++input_line_pointer
;
10378 e
->X_op_symbol
= make_expr_symbol (e
);
10379 e
->X_add_symbol
= NULL
;
10380 e
->X_add_number
= 0;
10385 e
->X_op
= O_absent
;
10386 input_line_pointer
= end
;
10393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10394 const char *md_shortopts
= "kVQ:sqnO::";
10396 const char *md_shortopts
= "qnO::";
10399 #define OPTION_32 (OPTION_MD_BASE + 0)
10400 #define OPTION_64 (OPTION_MD_BASE + 1)
10401 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10402 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10403 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10404 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10405 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10406 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10407 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10408 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10409 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10410 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10411 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10412 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10413 #define OPTION_X32 (OPTION_MD_BASE + 14)
10414 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10415 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10416 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10417 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10418 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10419 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10420 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10421 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10422 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10423 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10425 struct option md_longopts
[] =
10427 {"32", no_argument
, NULL
, OPTION_32
},
10428 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10429 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10430 {"64", no_argument
, NULL
, OPTION_64
},
10432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10433 {"x32", no_argument
, NULL
, OPTION_X32
},
10434 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10436 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10437 {"march", required_argument
, NULL
, OPTION_MARCH
},
10438 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10439 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10440 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10441 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10442 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10443 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10444 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10445 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10446 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10447 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10448 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10449 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10450 # if defined (TE_PE) || defined (TE_PEP)
10451 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10453 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10454 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10455 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10456 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10457 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10458 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10459 {NULL
, no_argument
, NULL
, 0}
10461 size_t md_longopts_size
= sizeof (md_longopts
);
10464 md_parse_option (int c
, const char *arg
)
10467 char *arch
, *next
, *saved
;
10472 optimize_align_code
= 0;
10476 quiet_warnings
= 1;
10479 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10480 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10481 should be emitted or not. FIXME: Not implemented. */
10485 /* -V: SVR4 argument to print version ID. */
10487 print_version_id ();
10490 /* -k: Ignore for FreeBSD compatibility. */
10495 /* -s: On i386 Solaris, this tells the native assembler to use
10496 .stab instead of .stab.excl. We always use .stab anyhow. */
10499 case OPTION_MSHARED
:
10503 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10504 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10507 const char **list
, **l
;
10509 list
= bfd_target_list ();
10510 for (l
= list
; *l
!= NULL
; l
++)
10511 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10512 || strcmp (*l
, "coff-x86-64") == 0
10513 || strcmp (*l
, "pe-x86-64") == 0
10514 || strcmp (*l
, "pei-x86-64") == 0
10515 || strcmp (*l
, "mach-o-x86-64") == 0)
10517 default_arch
= "x86_64";
10521 as_fatal (_("no compiled in support for x86_64"));
10527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10531 const char **list
, **l
;
10533 list
= bfd_target_list ();
10534 for (l
= list
; *l
!= NULL
; l
++)
10535 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10537 default_arch
= "x86_64:32";
10541 as_fatal (_("no compiled in support for 32bit x86_64"));
10545 as_fatal (_("32bit x86_64 is only supported for ELF"));
10550 default_arch
= "i386";
10553 case OPTION_DIVIDE
:
10554 #ifdef SVR4_COMMENT_CHARS
10559 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10561 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10565 i386_comment_chars
= n
;
10571 saved
= xstrdup (arg
);
10573 /* Allow -march=+nosse. */
10579 as_fatal (_("invalid -march= option: `%s'"), arg
);
10580 next
= strchr (arch
, '+');
10583 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10585 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10588 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10591 cpu_arch_name
= cpu_arch
[j
].name
;
10592 cpu_sub_arch_name
= NULL
;
10593 cpu_arch_flags
= cpu_arch
[j
].flags
;
10594 cpu_arch_isa
= cpu_arch
[j
].type
;
10595 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10596 if (!cpu_arch_tune_set
)
10598 cpu_arch_tune
= cpu_arch_isa
;
10599 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10603 else if (*cpu_arch
[j
].name
== '.'
10604 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10606 /* ISA extension. */
10607 i386_cpu_flags flags
;
10609 flags
= cpu_flags_or (cpu_arch_flags
,
10610 cpu_arch
[j
].flags
);
10612 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10614 if (cpu_sub_arch_name
)
10616 char *name
= cpu_sub_arch_name
;
10617 cpu_sub_arch_name
= concat (name
,
10619 (const char *) NULL
);
10623 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10624 cpu_arch_flags
= flags
;
10625 cpu_arch_isa_flags
= flags
;
10629 = cpu_flags_or (cpu_arch_isa_flags
,
10630 cpu_arch
[j
].flags
);
10635 if (j
>= ARRAY_SIZE (cpu_arch
))
10637 /* Disable an ISA extension. */
10638 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10639 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10641 i386_cpu_flags flags
;
10643 flags
= cpu_flags_and_not (cpu_arch_flags
,
10644 cpu_noarch
[j
].flags
);
10645 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10647 if (cpu_sub_arch_name
)
10649 char *name
= cpu_sub_arch_name
;
10650 cpu_sub_arch_name
= concat (arch
,
10651 (const char *) NULL
);
10655 cpu_sub_arch_name
= xstrdup (arch
);
10656 cpu_arch_flags
= flags
;
10657 cpu_arch_isa_flags
= flags
;
10662 if (j
>= ARRAY_SIZE (cpu_noarch
))
10663 j
= ARRAY_SIZE (cpu_arch
);
10666 if (j
>= ARRAY_SIZE (cpu_arch
))
10667 as_fatal (_("invalid -march= option: `%s'"), arg
);
10671 while (next
!= NULL
);
10677 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10678 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10680 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10682 cpu_arch_tune_set
= 1;
10683 cpu_arch_tune
= cpu_arch
[j
].type
;
10684 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10688 if (j
>= ARRAY_SIZE (cpu_arch
))
10689 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10692 case OPTION_MMNEMONIC
:
10693 if (strcasecmp (arg
, "att") == 0)
10694 intel_mnemonic
= 0;
10695 else if (strcasecmp (arg
, "intel") == 0)
10696 intel_mnemonic
= 1;
10698 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10701 case OPTION_MSYNTAX
:
10702 if (strcasecmp (arg
, "att") == 0)
10704 else if (strcasecmp (arg
, "intel") == 0)
10707 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10710 case OPTION_MINDEX_REG
:
10711 allow_index_reg
= 1;
10714 case OPTION_MNAKED_REG
:
10715 allow_naked_reg
= 1;
10718 case OPTION_MSSE2AVX
:
10722 case OPTION_MSSE_CHECK
:
10723 if (strcasecmp (arg
, "error") == 0)
10724 sse_check
= check_error
;
10725 else if (strcasecmp (arg
, "warning") == 0)
10726 sse_check
= check_warning
;
10727 else if (strcasecmp (arg
, "none") == 0)
10728 sse_check
= check_none
;
10730 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10733 case OPTION_MOPERAND_CHECK
:
10734 if (strcasecmp (arg
, "error") == 0)
10735 operand_check
= check_error
;
10736 else if (strcasecmp (arg
, "warning") == 0)
10737 operand_check
= check_warning
;
10738 else if (strcasecmp (arg
, "none") == 0)
10739 operand_check
= check_none
;
10741 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10744 case OPTION_MAVXSCALAR
:
10745 if (strcasecmp (arg
, "128") == 0)
10746 avxscalar
= vex128
;
10747 else if (strcasecmp (arg
, "256") == 0)
10748 avxscalar
= vex256
;
10750 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10753 case OPTION_MADD_BND_PREFIX
:
10754 add_bnd_prefix
= 1;
10757 case OPTION_MEVEXLIG
:
10758 if (strcmp (arg
, "128") == 0)
10759 evexlig
= evexl128
;
10760 else if (strcmp (arg
, "256") == 0)
10761 evexlig
= evexl256
;
10762 else if (strcmp (arg
, "512") == 0)
10763 evexlig
= evexl512
;
10765 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10768 case OPTION_MEVEXRCIG
:
10769 if (strcmp (arg
, "rne") == 0)
10771 else if (strcmp (arg
, "rd") == 0)
10773 else if (strcmp (arg
, "ru") == 0)
10775 else if (strcmp (arg
, "rz") == 0)
10778 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10781 case OPTION_MEVEXWIG
:
10782 if (strcmp (arg
, "0") == 0)
10784 else if (strcmp (arg
, "1") == 0)
10787 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10790 # if defined (TE_PE) || defined (TE_PEP)
10791 case OPTION_MBIG_OBJ
:
10796 case OPTION_MOMIT_LOCK_PREFIX
:
10797 if (strcasecmp (arg
, "yes") == 0)
10798 omit_lock_prefix
= 1;
10799 else if (strcasecmp (arg
, "no") == 0)
10800 omit_lock_prefix
= 0;
10802 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10805 case OPTION_MFENCE_AS_LOCK_ADD
:
10806 if (strcasecmp (arg
, "yes") == 0)
10808 else if (strcasecmp (arg
, "no") == 0)
10811 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10814 case OPTION_MRELAX_RELOCATIONS
:
10815 if (strcasecmp (arg
, "yes") == 0)
10816 generate_relax_relocations
= 1;
10817 else if (strcasecmp (arg
, "no") == 0)
10818 generate_relax_relocations
= 0;
10820 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10823 case OPTION_MAMD64
:
10827 case OPTION_MINTEL64
:
10835 /* Turn off -Os. */
10836 optimize_for_space
= 0;
10838 else if (*arg
== 's')
10840 optimize_for_space
= 1;
10841 /* Turn on all encoding optimizations. */
10846 optimize
= atoi (arg
);
10847 /* Turn off -Os. */
10848 optimize_for_space
= 0;
10858 #define MESSAGE_TEMPLATE \
10862 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10863 int *left_p
, const char *name
, int len
)
10865 int size
= sizeof (MESSAGE_TEMPLATE
);
10866 int left
= *left_p
;
10868 /* Reserve 2 spaces for ", " or ",\0" */
10871 /* Check if there is any room. */
10879 p
= mempcpy (p
, name
, len
);
10883 /* Output the current message now and start a new one. */
10886 fprintf (stream
, "%s\n", message
);
10888 left
= size
- (start
- message
) - len
- 2;
10890 gas_assert (left
>= 0);
10892 p
= mempcpy (p
, name
, len
);
10900 show_arch (FILE *stream
, int ext
, int check
)
10902 static char message
[] = MESSAGE_TEMPLATE
;
10903 char *start
= message
+ 27;
10905 int size
= sizeof (MESSAGE_TEMPLATE
);
10912 left
= size
- (start
- message
);
10913 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10915 /* Should it be skipped? */
10916 if (cpu_arch
[j
].skip
)
10919 name
= cpu_arch
[j
].name
;
10920 len
= cpu_arch
[j
].len
;
10923 /* It is an extension. Skip if we aren't asked to show it. */
10934 /* It is an processor. Skip if we show only extension. */
10937 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10939 /* It is an impossible processor - skip. */
10943 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10946 /* Display disabled extensions. */
10948 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10950 name
= cpu_noarch
[j
].name
;
10951 len
= cpu_noarch
[j
].len
;
10952 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10957 fprintf (stream
, "%s\n", message
);
10961 md_show_usage (FILE *stream
)
10963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10964 fprintf (stream
, _("\
10966 -V print assembler version number\n\
10969 fprintf (stream
, _("\
10970 -n Do not optimize code alignment\n\
10971 -q quieten some warnings\n"));
10972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10973 fprintf (stream
, _("\
10976 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10977 || defined (TE_PE) || defined (TE_PEP))
10978 fprintf (stream
, _("\
10979 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10981 #ifdef SVR4_COMMENT_CHARS
10982 fprintf (stream
, _("\
10983 --divide do not treat `/' as a comment character\n"));
10985 fprintf (stream
, _("\
10986 --divide ignored\n"));
10988 fprintf (stream
, _("\
10989 -march=CPU[,+EXTENSION...]\n\
10990 generate code for CPU and EXTENSION, CPU is one of:\n"));
10991 show_arch (stream
, 0, 1);
10992 fprintf (stream
, _("\
10993 EXTENSION is combination of:\n"));
10994 show_arch (stream
, 1, 0);
10995 fprintf (stream
, _("\
10996 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10997 show_arch (stream
, 0, 0);
10998 fprintf (stream
, _("\
10999 -msse2avx encode SSE instructions with VEX prefix\n"));
11000 fprintf (stream
, _("\
11001 -msse-check=[none|error|warning]\n\
11002 check SSE instructions\n"));
11003 fprintf (stream
, _("\
11004 -moperand-check=[none|error|warning]\n\
11005 check operand combinations for validity\n"));
11006 fprintf (stream
, _("\
11007 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11009 fprintf (stream
, _("\
11010 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11012 fprintf (stream
, _("\
11013 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11014 for EVEX.W bit ignored instructions\n"));
11015 fprintf (stream
, _("\
11016 -mevexrcig=[rne|rd|ru|rz]\n\
11017 encode EVEX instructions with specific EVEX.RC value\n\
11018 for SAE-only ignored instructions\n"));
11019 fprintf (stream
, _("\
11020 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11021 fprintf (stream
, _("\
11022 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11023 fprintf (stream
, _("\
11024 -mindex-reg support pseudo index registers\n"));
11025 fprintf (stream
, _("\
11026 -mnaked-reg don't require `%%' prefix for registers\n"));
11027 fprintf (stream
, _("\
11028 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11029 fprintf (stream
, _("\
11030 -mshared disable branch optimization for shared code\n"));
11031 # if defined (TE_PE) || defined (TE_PEP)
11032 fprintf (stream
, _("\
11033 -mbig-obj generate big object files\n"));
11035 fprintf (stream
, _("\
11036 -momit-lock-prefix=[no|yes]\n\
11037 strip all lock prefixes\n"));
11038 fprintf (stream
, _("\
11039 -mfence-as-lock-add=[no|yes]\n\
11040 encode lfence, mfence and sfence as\n\
11041 lock addl $0x0, (%%{re}sp)\n"));
11042 fprintf (stream
, _("\
11043 -mrelax-relocations=[no|yes]\n\
11044 generate relax relocations\n"));
11045 fprintf (stream
, _("\
11046 -mamd64 accept only AMD64 ISA\n"));
11047 fprintf (stream
, _("\
11048 -mintel64 accept only Intel64 ISA\n"));
11051 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11052 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11053 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11055 /* Pick the target format to use. */
11058 i386_target_format (void)
11060 if (!strncmp (default_arch
, "x86_64", 6))
11062 update_code_flag (CODE_64BIT
, 1);
11063 if (default_arch
[6] == '\0')
11064 x86_elf_abi
= X86_64_ABI
;
11066 x86_elf_abi
= X86_64_X32_ABI
;
11068 else if (!strcmp (default_arch
, "i386"))
11069 update_code_flag (CODE_32BIT
, 1);
11070 else if (!strcmp (default_arch
, "iamcu"))
11072 update_code_flag (CODE_32BIT
, 1);
11073 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11075 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11076 cpu_arch_name
= "iamcu";
11077 cpu_sub_arch_name
= NULL
;
11078 cpu_arch_flags
= iamcu_flags
;
11079 cpu_arch_isa
= PROCESSOR_IAMCU
;
11080 cpu_arch_isa_flags
= iamcu_flags
;
11081 if (!cpu_arch_tune_set
)
11083 cpu_arch_tune
= cpu_arch_isa
;
11084 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11087 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11088 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11092 as_fatal (_("unknown architecture"));
11094 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11095 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11096 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11097 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11099 switch (OUTPUT_FLAVOR
)
11101 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11102 case bfd_target_aout_flavour
:
11103 return AOUT_TARGET_FORMAT
;
11105 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11106 # if defined (TE_PE) || defined (TE_PEP)
11107 case bfd_target_coff_flavour
:
11108 if (flag_code
== CODE_64BIT
)
11109 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11112 # elif defined (TE_GO32)
11113 case bfd_target_coff_flavour
:
11114 return "coff-go32";
11116 case bfd_target_coff_flavour
:
11117 return "coff-i386";
11120 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11121 case bfd_target_elf_flavour
:
11123 const char *format
;
11125 switch (x86_elf_abi
)
11128 format
= ELF_TARGET_FORMAT
;
11131 use_rela_relocations
= 1;
11133 format
= ELF_TARGET_FORMAT64
;
11135 case X86_64_X32_ABI
:
11136 use_rela_relocations
= 1;
11138 disallow_64bit_reloc
= 1;
11139 format
= ELF_TARGET_FORMAT32
;
11142 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11144 if (x86_elf_abi
!= X86_64_ABI
)
11145 as_fatal (_("Intel L1OM is 64bit only"));
11146 return ELF_TARGET_L1OM_FORMAT
;
11148 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11150 if (x86_elf_abi
!= X86_64_ABI
)
11151 as_fatal (_("Intel K1OM is 64bit only"));
11152 return ELF_TARGET_K1OM_FORMAT
;
11154 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11156 if (x86_elf_abi
!= I386_ABI
)
11157 as_fatal (_("Intel MCU is 32bit only"));
11158 return ELF_TARGET_IAMCU_FORMAT
;
11164 #if defined (OBJ_MACH_O)
11165 case bfd_target_mach_o_flavour
:
11166 if (flag_code
== CODE_64BIT
)
11168 use_rela_relocations
= 1;
11170 return "mach-o-x86-64";
11173 return "mach-o-i386";
11181 #endif /* OBJ_MAYBE_ more than one */
11184 md_undefined_symbol (char *name
)
11186 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11187 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11188 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11189 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11193 if (symbol_find (name
))
11194 as_bad (_("GOT already in symbol table"));
11195 GOT_symbol
= symbol_new (name
, undefined_section
,
11196 (valueT
) 0, &zero_address_frag
);
11203 /* Round up a section size to the appropriate boundary. */
11206 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11208 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11209 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11211 /* For a.out, force the section size to be aligned. If we don't do
11212 this, BFD will align it for us, but it will not write out the
11213 final bytes of the section. This may be a bug in BFD, but it is
11214 easier to fix it here since that is how the other a.out targets
11218 align
= bfd_get_section_alignment (stdoutput
, segment
);
11219 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11226 /* On the i386, PC-relative offsets are relative to the start of the
11227 next instruction. That is, the address of the offset, plus its
11228 size, since the offset is always the last part of the insn. */
11231 md_pcrel_from (fixS
*fixP
)
11233 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11239 s_bss (int ignore ATTRIBUTE_UNUSED
)
11243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11245 obj_elf_section_change_hook ();
11247 temp
= get_absolute_expression ();
11248 subseg_set (bss_section
, (subsegT
) temp
);
11249 demand_empty_rest_of_line ();
11255 i386_validate_fix (fixS
*fixp
)
11257 if (fixp
->fx_subsy
)
11259 if (fixp
->fx_subsy
== GOT_symbol
)
11261 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11266 if (fixp
->fx_tcbit2
)
11267 fixp
->fx_r_type
= (fixp
->fx_tcbit
11268 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11269 : BFD_RELOC_X86_64_GOTPCRELX
);
11272 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11277 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11279 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11281 fixp
->fx_subsy
= 0;
11284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11285 else if (!object_64bit
)
11287 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11288 && fixp
->fx_tcbit2
)
11289 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11295 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11298 bfd_reloc_code_real_type code
;
11300 switch (fixp
->fx_r_type
)
11302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11303 case BFD_RELOC_SIZE32
:
11304 case BFD_RELOC_SIZE64
:
11305 if (S_IS_DEFINED (fixp
->fx_addsy
)
11306 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11308 /* Resolve size relocation against local symbol to size of
11309 the symbol plus addend. */
11310 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11311 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11312 && !fits_in_unsigned_long (value
))
11313 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11314 _("symbol size computation overflow"));
11315 fixp
->fx_addsy
= NULL
;
11316 fixp
->fx_subsy
= NULL
;
11317 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11321 /* Fall through. */
11323 case BFD_RELOC_X86_64_PLT32
:
11324 case BFD_RELOC_X86_64_GOT32
:
11325 case BFD_RELOC_X86_64_GOTPCREL
:
11326 case BFD_RELOC_X86_64_GOTPCRELX
:
11327 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11328 case BFD_RELOC_386_PLT32
:
11329 case BFD_RELOC_386_GOT32
:
11330 case BFD_RELOC_386_GOT32X
:
11331 case BFD_RELOC_386_GOTOFF
:
11332 case BFD_RELOC_386_GOTPC
:
11333 case BFD_RELOC_386_TLS_GD
:
11334 case BFD_RELOC_386_TLS_LDM
:
11335 case BFD_RELOC_386_TLS_LDO_32
:
11336 case BFD_RELOC_386_TLS_IE_32
:
11337 case BFD_RELOC_386_TLS_IE
:
11338 case BFD_RELOC_386_TLS_GOTIE
:
11339 case BFD_RELOC_386_TLS_LE_32
:
11340 case BFD_RELOC_386_TLS_LE
:
11341 case BFD_RELOC_386_TLS_GOTDESC
:
11342 case BFD_RELOC_386_TLS_DESC_CALL
:
11343 case BFD_RELOC_X86_64_TLSGD
:
11344 case BFD_RELOC_X86_64_TLSLD
:
11345 case BFD_RELOC_X86_64_DTPOFF32
:
11346 case BFD_RELOC_X86_64_DTPOFF64
:
11347 case BFD_RELOC_X86_64_GOTTPOFF
:
11348 case BFD_RELOC_X86_64_TPOFF32
:
11349 case BFD_RELOC_X86_64_TPOFF64
:
11350 case BFD_RELOC_X86_64_GOTOFF64
:
11351 case BFD_RELOC_X86_64_GOTPC32
:
11352 case BFD_RELOC_X86_64_GOT64
:
11353 case BFD_RELOC_X86_64_GOTPCREL64
:
11354 case BFD_RELOC_X86_64_GOTPC64
:
11355 case BFD_RELOC_X86_64_GOTPLT64
:
11356 case BFD_RELOC_X86_64_PLTOFF64
:
11357 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11358 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11359 case BFD_RELOC_RVA
:
11360 case BFD_RELOC_VTABLE_ENTRY
:
11361 case BFD_RELOC_VTABLE_INHERIT
:
11363 case BFD_RELOC_32_SECREL
:
11365 code
= fixp
->fx_r_type
;
11367 case BFD_RELOC_X86_64_32S
:
11368 if (!fixp
->fx_pcrel
)
11370 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11371 code
= fixp
->fx_r_type
;
11374 /* Fall through. */
11376 if (fixp
->fx_pcrel
)
11378 switch (fixp
->fx_size
)
11381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11382 _("can not do %d byte pc-relative relocation"),
11384 code
= BFD_RELOC_32_PCREL
;
11386 case 1: code
= BFD_RELOC_8_PCREL
; break;
11387 case 2: code
= BFD_RELOC_16_PCREL
; break;
11388 case 4: code
= BFD_RELOC_32_PCREL
; break;
11390 case 8: code
= BFD_RELOC_64_PCREL
; break;
11396 switch (fixp
->fx_size
)
11399 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11400 _("can not do %d byte relocation"),
11402 code
= BFD_RELOC_32
;
11404 case 1: code
= BFD_RELOC_8
; break;
11405 case 2: code
= BFD_RELOC_16
; break;
11406 case 4: code
= BFD_RELOC_32
; break;
11408 case 8: code
= BFD_RELOC_64
; break;
11415 if ((code
== BFD_RELOC_32
11416 || code
== BFD_RELOC_32_PCREL
11417 || code
== BFD_RELOC_X86_64_32S
)
11419 && fixp
->fx_addsy
== GOT_symbol
)
11422 code
= BFD_RELOC_386_GOTPC
;
11424 code
= BFD_RELOC_X86_64_GOTPC32
;
11426 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11428 && fixp
->fx_addsy
== GOT_symbol
)
11430 code
= BFD_RELOC_X86_64_GOTPC64
;
11433 rel
= XNEW (arelent
);
11434 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11435 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11437 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11439 if (!use_rela_relocations
)
11441 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11442 vtable entry to be used in the relocation's section offset. */
11443 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11444 rel
->address
= fixp
->fx_offset
;
11445 #if defined (OBJ_COFF) && defined (TE_PE)
11446 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11447 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11452 /* Use the rela in 64bit mode. */
11455 if (disallow_64bit_reloc
)
11458 case BFD_RELOC_X86_64_DTPOFF64
:
11459 case BFD_RELOC_X86_64_TPOFF64
:
11460 case BFD_RELOC_64_PCREL
:
11461 case BFD_RELOC_X86_64_GOTOFF64
:
11462 case BFD_RELOC_X86_64_GOT64
:
11463 case BFD_RELOC_X86_64_GOTPCREL64
:
11464 case BFD_RELOC_X86_64_GOTPC64
:
11465 case BFD_RELOC_X86_64_GOTPLT64
:
11466 case BFD_RELOC_X86_64_PLTOFF64
:
11467 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11468 _("cannot represent relocation type %s in x32 mode"),
11469 bfd_get_reloc_code_name (code
));
11475 if (!fixp
->fx_pcrel
)
11476 rel
->addend
= fixp
->fx_offset
;
11480 case BFD_RELOC_X86_64_PLT32
:
11481 case BFD_RELOC_X86_64_GOT32
:
11482 case BFD_RELOC_X86_64_GOTPCREL
:
11483 case BFD_RELOC_X86_64_GOTPCRELX
:
11484 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11485 case BFD_RELOC_X86_64_TLSGD
:
11486 case BFD_RELOC_X86_64_TLSLD
:
11487 case BFD_RELOC_X86_64_GOTTPOFF
:
11488 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11489 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11490 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11493 rel
->addend
= (section
->vma
11495 + fixp
->fx_addnumber
11496 + md_pcrel_from (fixp
));
11501 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11502 if (rel
->howto
== NULL
)
11504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11505 _("cannot represent relocation type %s"),
11506 bfd_get_reloc_code_name (code
));
11507 /* Set howto to a garbage value so that we can keep going. */
11508 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11509 gas_assert (rel
->howto
!= NULL
);
11515 #include "tc-i386-intel.c"
11518 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11520 int saved_naked_reg
;
11521 char saved_register_dot
;
11523 saved_naked_reg
= allow_naked_reg
;
11524 allow_naked_reg
= 1;
11525 saved_register_dot
= register_chars
['.'];
11526 register_chars
['.'] = '.';
11527 allow_pseudo_reg
= 1;
11528 expression_and_evaluate (exp
);
11529 allow_pseudo_reg
= 0;
11530 register_chars
['.'] = saved_register_dot
;
11531 allow_naked_reg
= saved_naked_reg
;
11533 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11535 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11537 exp
->X_op
= O_constant
;
11538 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11539 .dw2_regnum
[flag_code
>> 1];
11542 exp
->X_op
= O_illegal
;
11547 tc_x86_frame_initial_instructions (void)
11549 static unsigned int sp_regno
[2];
11551 if (!sp_regno
[flag_code
>> 1])
11553 char *saved_input
= input_line_pointer
;
11554 char sp
[][4] = {"esp", "rsp"};
11557 input_line_pointer
= sp
[flag_code
>> 1];
11558 tc_x86_parse_to_dw2regnum (&exp
);
11559 gas_assert (exp
.X_op
== O_constant
);
11560 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11561 input_line_pointer
= saved_input
;
11564 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11565 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11569 x86_dwarf2_addr_size (void)
11571 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11572 if (x86_elf_abi
== X86_64_X32_ABI
)
11575 return bfd_arch_bits_per_address (stdoutput
) / 8;
11579 i386_elf_section_type (const char *str
, size_t len
)
11581 if (flag_code
== CODE_64BIT
11582 && len
== sizeof ("unwind") - 1
11583 && strncmp (str
, "unwind", 6) == 0)
11584 return SHT_X86_64_UNWIND
;
11591 i386_solaris_fix_up_eh_frame (segT sec
)
11593 if (flag_code
== CODE_64BIT
)
11594 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11600 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11604 exp
.X_op
= O_secrel
;
11605 exp
.X_add_symbol
= symbol
;
11606 exp
.X_add_number
= 0;
11607 emit_expr (&exp
, size
);
11611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11612 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11615 x86_64_section_letter (int letter
, const char **ptr_msg
)
11617 if (flag_code
== CODE_64BIT
)
11620 return SHF_X86_64_LARGE
;
11622 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11625 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11630 x86_64_section_word (char *str
, size_t len
)
11632 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11633 return SHF_X86_64_LARGE
;
11639 handle_large_common (int small ATTRIBUTE_UNUSED
)
11641 if (flag_code
!= CODE_64BIT
)
11643 s_comm_internal (0, elf_common_parse
);
11644 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11648 static segT lbss_section
;
11649 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11650 asection
*saved_bss_section
= bss_section
;
11652 if (lbss_section
== NULL
)
11654 flagword applicable
;
11655 segT seg
= now_seg
;
11656 subsegT subseg
= now_subseg
;
11658 /* The .lbss section is for local .largecomm symbols. */
11659 lbss_section
= subseg_new (".lbss", 0);
11660 applicable
= bfd_applicable_section_flags (stdoutput
);
11661 bfd_set_section_flags (stdoutput
, lbss_section
,
11662 applicable
& SEC_ALLOC
);
11663 seg_info (lbss_section
)->bss
= 1;
11665 subseg_set (seg
, subseg
);
11668 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11669 bss_section
= lbss_section
;
11671 s_comm_internal (0, elf_common_parse
);
11673 elf_com_section_ptr
= saved_com_section_ptr
;
11674 bss_section
= saved_bss_section
;
11677 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */