1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1085 static const noarch_entry cpu_noarch
[] =
1087 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1088 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1089 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1090 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1091 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1092 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1093 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1094 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1095 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1096 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1097 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1099 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1118 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1119 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1120 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1121 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1125 /* Like s_lcomm_internal in gas/read.c but the alignment string
1126 is allowed to be optional. */
1129 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1136 && *input_line_pointer
== ',')
1138 align
= parse_align (needs_align
- 1);
1140 if (align
== (addressT
) -1)
1155 bss_alloc (symbolP
, size
, align
);
1160 pe_lcomm (int needs_align
)
1162 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1166 const pseudo_typeS md_pseudo_table
[] =
1168 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1169 {"align", s_align_bytes
, 0},
1171 {"align", s_align_ptwo
, 0},
1173 {"arch", set_cpu_arch
, 0},
1177 {"lcomm", pe_lcomm
, 1},
1179 {"ffloat", float_cons
, 'f'},
1180 {"dfloat", float_cons
, 'd'},
1181 {"tfloat", float_cons
, 'x'},
1183 {"slong", signed_cons
, 4},
1184 {"noopt", s_ignore
, 0},
1185 {"optim", s_ignore
, 0},
1186 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1187 {"code16", set_code_flag
, CODE_16BIT
},
1188 {"code32", set_code_flag
, CODE_32BIT
},
1190 {"code64", set_code_flag
, CODE_64BIT
},
1192 {"intel_syntax", set_intel_syntax
, 1},
1193 {"att_syntax", set_intel_syntax
, 0},
1194 {"intel_mnemonic", set_intel_mnemonic
, 1},
1195 {"att_mnemonic", set_intel_mnemonic
, 0},
1196 {"allow_index_reg", set_allow_index_reg
, 1},
1197 {"disallow_index_reg", set_allow_index_reg
, 0},
1198 {"sse_check", set_check
, 0},
1199 {"operand_check", set_check
, 1},
1200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1201 {"largecomm", handle_large_common
, 0},
1203 {"file", dwarf2_directive_file
, 0},
1204 {"loc", dwarf2_directive_loc
, 0},
1205 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1208 {"secrel32", pe_directive_secrel
, 0},
1213 /* For interface with expression (). */
1214 extern char *input_line_pointer
;
1216 /* Hash table for instruction mnemonic lookup. */
1217 static struct hash_control
*op_hash
;
1219 /* Hash table for register lookup. */
1220 static struct hash_control
*reg_hash
;
1222 /* Various efficient no-op patterns for aligning code labels.
1223 Note: Don't try to assemble the instructions in the comments.
1224 0L and 0w are not legal. */
1225 static const unsigned char f32_1
[] =
1227 static const unsigned char f32_2
[] =
1228 {0x66,0x90}; /* xchg %ax,%ax */
1229 static const unsigned char f32_3
[] =
1230 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1231 static const unsigned char f32_4
[] =
1232 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1233 static const unsigned char f32_6
[] =
1234 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1235 static const unsigned char f32_7
[] =
1236 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1237 static const unsigned char f16_3
[] =
1238 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1239 static const unsigned char f16_4
[] =
1240 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1241 static const unsigned char jump_disp8
[] =
1242 {0xeb}; /* jmp disp8 */
1243 static const unsigned char jump32_disp32
[] =
1244 {0xe9}; /* jmp disp32 */
1245 static const unsigned char jump16_disp32
[] =
1246 {0x66,0xe9}; /* jmp disp32 */
1247 /* 32-bit NOPs patterns. */
1248 static const unsigned char *const f32_patt
[] = {
1249 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1251 /* 16-bit NOPs patterns. */
1252 static const unsigned char *const f16_patt
[] = {
1253 f32_1
, f32_2
, f16_3
, f16_4
1255 /* nopl (%[re]ax) */
1256 static const unsigned char alt_3
[] =
1258 /* nopl 0(%[re]ax) */
1259 static const unsigned char alt_4
[] =
1260 {0x0f,0x1f,0x40,0x00};
1261 /* nopl 0(%[re]ax,%[re]ax,1) */
1262 static const unsigned char alt_5
[] =
1263 {0x0f,0x1f,0x44,0x00,0x00};
1264 /* nopw 0(%[re]ax,%[re]ax,1) */
1265 static const unsigned char alt_6
[] =
1266 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1267 /* nopl 0L(%[re]ax) */
1268 static const unsigned char alt_7
[] =
1269 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1270 /* nopl 0L(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_8
[] =
1272 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1273 /* nopw 0L(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_9
[] =
1275 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1276 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_10
[] =
1278 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* data16 nopw %cs:0L(%eax,%eax,1) */
1280 static const unsigned char alt_11
[] =
1281 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* 32-bit and 64-bit NOPs patterns. */
1283 static const unsigned char *const alt_patt
[] = {
1284 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1285 alt_9
, alt_10
, alt_11
1288 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1289 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1292 i386_output_nops (char *where
, const unsigned char *const *patt
,
1293 int count
, int max_single_nop_size
)
1296 /* Place the longer NOP first. */
1299 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1301 /* Use the smaller one if the requsted one isn't available. */
1304 max_single_nop_size
--;
1305 nops
= patt
[max_single_nop_size
- 1];
1308 last
= count
% max_single_nop_size
;
1311 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1312 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1316 nops
= patt
[last
- 1];
1319 /* Use the smaller one plus one-byte NOP if the needed one
1322 nops
= patt
[last
- 1];
1323 memcpy (where
+ offset
, nops
, last
);
1324 where
[offset
+ last
] = *patt
[0];
1327 memcpy (where
+ offset
, nops
, last
);
1332 fits_in_imm7 (offsetT num
)
1334 return (num
& 0x7f) == num
;
1338 fits_in_imm31 (offsetT num
)
1340 return (num
& 0x7fffffff) == num
;
1343 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1344 single NOP instruction LIMIT. */
1347 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1349 const unsigned char *const *patt
= NULL
;
1350 int max_single_nop_size
;
1351 /* Maximum number of NOPs before switching to jump over NOPs. */
1352 int max_number_of_nops
;
1354 switch (fragP
->fr_type
)
1363 /* We need to decide which NOP sequence to use for 32bit and
1364 64bit. When -mtune= is used:
1366 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1367 PROCESSOR_GENERIC32, f32_patt will be used.
1368 2. For the rest, alt_patt will be used.
1370 When -mtune= isn't used, alt_patt will be used if
1371 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1374 When -march= or .arch is used, we can't use anything beyond
1375 cpu_arch_isa_flags. */
1377 if (flag_code
== CODE_16BIT
)
1380 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1381 /* Limit number of NOPs to 2 in 16-bit mode. */
1382 max_number_of_nops
= 2;
1386 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1388 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1389 switch (cpu_arch_tune
)
1391 case PROCESSOR_UNKNOWN
:
1392 /* We use cpu_arch_isa_flags to check if we SHOULD
1393 optimize with nops. */
1394 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1399 case PROCESSOR_PENTIUM4
:
1400 case PROCESSOR_NOCONA
:
1401 case PROCESSOR_CORE
:
1402 case PROCESSOR_CORE2
:
1403 case PROCESSOR_COREI7
:
1404 case PROCESSOR_L1OM
:
1405 case PROCESSOR_K1OM
:
1406 case PROCESSOR_GENERIC64
:
1408 case PROCESSOR_ATHLON
:
1410 case PROCESSOR_AMDFAM10
:
1412 case PROCESSOR_ZNVER
:
1416 case PROCESSOR_I386
:
1417 case PROCESSOR_I486
:
1418 case PROCESSOR_PENTIUM
:
1419 case PROCESSOR_PENTIUMPRO
:
1420 case PROCESSOR_IAMCU
:
1421 case PROCESSOR_GENERIC32
:
1428 switch (fragP
->tc_frag_data
.tune
)
1430 case PROCESSOR_UNKNOWN
:
1431 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1432 PROCESSOR_UNKNOWN. */
1436 case PROCESSOR_I386
:
1437 case PROCESSOR_I486
:
1438 case PROCESSOR_PENTIUM
:
1439 case PROCESSOR_IAMCU
:
1441 case PROCESSOR_ATHLON
:
1443 case PROCESSOR_AMDFAM10
:
1445 case PROCESSOR_ZNVER
:
1447 case PROCESSOR_GENERIC32
:
1448 /* We use cpu_arch_isa_flags to check if we CAN optimize
1450 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1455 case PROCESSOR_PENTIUMPRO
:
1456 case PROCESSOR_PENTIUM4
:
1457 case PROCESSOR_NOCONA
:
1458 case PROCESSOR_CORE
:
1459 case PROCESSOR_CORE2
:
1460 case PROCESSOR_COREI7
:
1461 case PROCESSOR_L1OM
:
1462 case PROCESSOR_K1OM
:
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_GENERIC64
:
1474 if (patt
== f32_patt
)
1476 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1477 /* Limit number of NOPs to 2 for older processors. */
1478 max_number_of_nops
= 2;
1482 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1483 /* Limit number of NOPs to 7 for newer processors. */
1484 max_number_of_nops
= 7;
1489 limit
= max_single_nop_size
;
1491 if (fragP
->fr_type
== rs_fill_nop
)
1493 /* Output NOPs for .nop directive. */
1494 if (limit
> max_single_nop_size
)
1496 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1497 _("invalid single nop size: %d "
1498 "(expect within [0, %d])"),
1499 limit
, max_single_nop_size
);
1504 fragP
->fr_var
= count
;
1506 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1508 /* Generate jump over NOPs. */
1509 offsetT disp
= count
- 2;
1510 if (fits_in_imm7 (disp
))
1512 /* Use "jmp disp8" if possible. */
1514 where
[0] = jump_disp8
[0];
1520 unsigned int size_of_jump
;
1522 if (flag_code
== CODE_16BIT
)
1524 where
[0] = jump16_disp32
[0];
1525 where
[1] = jump16_disp32
[1];
1530 where
[0] = jump32_disp32
[0];
1534 count
-= size_of_jump
+ 4;
1535 if (!fits_in_imm31 (count
))
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("jump over nop padding out of range"));
1542 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1543 where
+= size_of_jump
+ 4;
1547 /* Generate multiple NOPs. */
1548 i386_output_nops (where
, patt
, count
, limit
);
1552 operand_type_all_zero (const union i386_operand_type
*x
)
1554 switch (ARRAY_SIZE(x
->array
))
1565 return !x
->array
[0];
1572 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1574 switch (ARRAY_SIZE(x
->array
))
1592 operand_type_equal (const union i386_operand_type
*x
,
1593 const union i386_operand_type
*y
)
1595 switch (ARRAY_SIZE(x
->array
))
1598 if (x
->array
[2] != y
->array
[2])
1602 if (x
->array
[1] != y
->array
[1])
1606 return x
->array
[0] == y
->array
[0];
1614 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1616 switch (ARRAY_SIZE(x
->array
))
1631 return !x
->array
[0];
1638 cpu_flags_equal (const union i386_cpu_flags
*x
,
1639 const union i386_cpu_flags
*y
)
1641 switch (ARRAY_SIZE(x
->array
))
1644 if (x
->array
[3] != y
->array
[3])
1648 if (x
->array
[2] != y
->array
[2])
1652 if (x
->array
[1] != y
->array
[1])
1656 return x
->array
[0] == y
->array
[0];
1664 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1666 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1667 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1670 static INLINE i386_cpu_flags
1671 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1673 switch (ARRAY_SIZE (x
.array
))
1676 x
.array
[3] &= y
.array
[3];
1679 x
.array
[2] &= y
.array
[2];
1682 x
.array
[1] &= y
.array
[1];
1685 x
.array
[0] &= y
.array
[0];
1693 static INLINE i386_cpu_flags
1694 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1696 switch (ARRAY_SIZE (x
.array
))
1699 x
.array
[3] |= y
.array
[3];
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_cpu_flags
1717 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[3] &= ~y
.array
[3];
1725 x
.array
[2] &= ~y
.array
[2];
1728 x
.array
[1] &= ~y
.array
[1];
1731 x
.array
[0] &= ~y
.array
[0];
1739 #define CPU_FLAGS_ARCH_MATCH 0x1
1740 #define CPU_FLAGS_64BIT_MATCH 0x2
1742 #define CPU_FLAGS_PERFECT_MATCH \
1743 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1745 /* Return CPU flags match bits. */
1748 cpu_flags_match (const insn_template
*t
)
1750 i386_cpu_flags x
= t
->cpu_flags
;
1751 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1753 x
.bitfield
.cpu64
= 0;
1754 x
.bitfield
.cpuno64
= 0;
1756 if (cpu_flags_all_zero (&x
))
1758 /* This instruction is available on all archs. */
1759 match
|= CPU_FLAGS_ARCH_MATCH
;
1763 /* This instruction is available only on some archs. */
1764 i386_cpu_flags cpu
= cpu_arch_flags
;
1766 /* AVX512VL is no standalone feature - match it and then strip it. */
1767 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1769 x
.bitfield
.cpuavx512vl
= 0;
1771 cpu
= cpu_flags_and (x
, cpu
);
1772 if (!cpu_flags_all_zero (&cpu
))
1774 if (x
.bitfield
.cpuavx
)
1776 /* We need to check a few extra flags with AVX. */
1777 if (cpu
.bitfield
.cpuavx
1778 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1779 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1780 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1781 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1782 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 else if (x
.bitfield
.cpuavx512f
)
1786 /* We need to check a few extra flags with AVX512F. */
1787 if (cpu
.bitfield
.cpuavx512f
1788 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1789 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1790 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1791 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 match
|= CPU_FLAGS_ARCH_MATCH
;
1800 static INLINE i386_operand_type
1801 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_operand_type
1821 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[2] &= ~y
.array
[2];
1829 x
.array
[1] &= ~y
.array
[1];
1832 x
.array
[0] &= ~y
.array
[0];
1840 static INLINE i386_operand_type
1841 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1843 switch (ARRAY_SIZE (x
.array
))
1846 x
.array
[2] |= y
.array
[2];
1849 x
.array
[1] |= y
.array
[1];
1852 x
.array
[0] |= y
.array
[0];
1860 static INLINE i386_operand_type
1861 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[2] ^= y
.array
[2];
1869 x
.array
[1] ^= y
.array
[1];
1872 x
.array
[0] ^= y
.array
[0];
1880 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1881 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1882 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1883 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1884 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1885 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1886 static const i386_operand_type anydisp
1887 = OPERAND_TYPE_ANYDISP
;
1888 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1889 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1890 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1891 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1892 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1893 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1894 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1895 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1896 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1897 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1898 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1899 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1910 operand_type_check (i386_operand_type t
, enum operand_type c
)
1915 return t
.bitfield
.reg
;
1918 return (t
.bitfield
.imm8
1922 || t
.bitfield
.imm32s
1923 || t
.bitfield
.imm64
);
1926 return (t
.bitfield
.disp8
1927 || t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
1930 || t
.bitfield
.disp64
);
1933 return (t
.bitfield
.disp8
1934 || t
.bitfield
.disp16
1935 || t
.bitfield
.disp32
1936 || t
.bitfield
.disp32s
1937 || t
.bitfield
.disp64
1938 || t
.bitfield
.baseindex
);
1947 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1948 between operand GIVEN and opeand WANTED for instruction template T. */
1951 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1954 return !((i
.types
[given
].bitfield
.byte
1955 && !t
->operand_types
[wanted
].bitfield
.byte
)
1956 || (i
.types
[given
].bitfield
.word
1957 && !t
->operand_types
[wanted
].bitfield
.word
)
1958 || (i
.types
[given
].bitfield
.dword
1959 && !t
->operand_types
[wanted
].bitfield
.dword
)
1960 || (i
.types
[given
].bitfield
.qword
1961 && !t
->operand_types
[wanted
].bitfield
.qword
)
1962 || (i
.types
[given
].bitfield
.tbyte
1963 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1966 /* Return 1 if there is no conflict in SIMD register between operand
1967 GIVEN and opeand WANTED for instruction template T. */
1970 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.xmmword
1974 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1975 || (i
.types
[given
].bitfield
.ymmword
1976 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1977 || (i
.types
[given
].bitfield
.zmmword
1978 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1981 /* Return 1 if there is no conflict in any size between operand GIVEN
1982 and opeand WANTED for instruction template T. */
1985 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1988 return (match_operand_size (t
, wanted
, given
)
1989 && !((i
.types
[given
].bitfield
.unspecified
1991 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1992 || (i
.types
[given
].bitfield
.fword
1993 && !t
->operand_types
[wanted
].bitfield
.fword
)
1994 /* For scalar opcode templates to allow register and memory
1995 operands at the same time, some special casing is needed
1996 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1997 down-conversion vpmov*. */
1998 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1999 && !t
->opcode_modifier
.broadcast
2000 && (t
->operand_types
[wanted
].bitfield
.byte
2001 || t
->operand_types
[wanted
].bitfield
.word
2002 || t
->operand_types
[wanted
].bitfield
.dword
2003 || t
->operand_types
[wanted
].bitfield
.qword
))
2004 ? (i
.types
[given
].bitfield
.xmmword
2005 || i
.types
[given
].bitfield
.ymmword
2006 || i
.types
[given
].bitfield
.zmmword
)
2007 : !match_simd_size(t
, wanted
, given
))));
2010 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2011 operands for instruction template T, and it has MATCH_REVERSE set if there
2012 is no size conflict on any operands for the template with operands reversed
2013 (and the template allows for reversing in the first place). */
2015 #define MATCH_STRAIGHT 1
2016 #define MATCH_REVERSE 2
2018 static INLINE
unsigned int
2019 operand_size_match (const insn_template
*t
)
2021 unsigned int j
, match
= MATCH_STRAIGHT
;
2023 /* Don't check jump instructions. */
2024 if (t
->opcode_modifier
.jump
2025 || t
->opcode_modifier
.jumpbyte
2026 || t
->opcode_modifier
.jumpdword
2027 || t
->opcode_modifier
.jumpintersegment
)
2030 /* Check memory and accumulator operand size. */
2031 for (j
= 0; j
< i
.operands
; j
++)
2033 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2034 && t
->operand_types
[j
].bitfield
.anysize
)
2037 if (t
->operand_types
[j
].bitfield
.reg
2038 && !match_operand_size (t
, j
, j
))
2044 if (t
->operand_types
[j
].bitfield
.regsimd
2045 && !match_simd_size (t
, j
, j
))
2051 if (t
->operand_types
[j
].bitfield
.acc
2052 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2058 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2065 if (!t
->opcode_modifier
.d
)
2069 i
.error
= operand_size_mismatch
;
2073 /* Check reverse. */
2074 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2076 for (j
= 0; j
< i
.operands
; j
++)
2078 unsigned int given
= i
.operands
- j
- 1;
2080 if (t
->operand_types
[j
].bitfield
.reg
2081 && !match_operand_size (t
, j
, given
))
2084 if (t
->operand_types
[j
].bitfield
.regsimd
2085 && !match_simd_size (t
, j
, given
))
2088 if (t
->operand_types
[j
].bitfield
.acc
2089 && (!match_operand_size (t
, j
, given
)
2090 || !match_simd_size (t
, j
, given
)))
2093 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2097 return match
| MATCH_REVERSE
;
2101 operand_type_match (i386_operand_type overlap
,
2102 i386_operand_type given
)
2104 i386_operand_type temp
= overlap
;
2106 temp
.bitfield
.jumpabsolute
= 0;
2107 temp
.bitfield
.unspecified
= 0;
2108 temp
.bitfield
.byte
= 0;
2109 temp
.bitfield
.word
= 0;
2110 temp
.bitfield
.dword
= 0;
2111 temp
.bitfield
.fword
= 0;
2112 temp
.bitfield
.qword
= 0;
2113 temp
.bitfield
.tbyte
= 0;
2114 temp
.bitfield
.xmmword
= 0;
2115 temp
.bitfield
.ymmword
= 0;
2116 temp
.bitfield
.zmmword
= 0;
2117 if (operand_type_all_zero (&temp
))
2120 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2121 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2125 i
.error
= operand_type_mismatch
;
2129 /* If given types g0 and g1 are registers they must be of the same type
2130 unless the expected operand type register overlap is null.
2131 Memory operand size of certain SIMD instructions is also being checked
2135 operand_type_register_match (i386_operand_type g0
,
2136 i386_operand_type t0
,
2137 i386_operand_type g1
,
2138 i386_operand_type t1
)
2140 if (!g0
.bitfield
.reg
2141 && !g0
.bitfield
.regsimd
2142 && (!operand_type_check (g0
, anymem
)
2143 || g0
.bitfield
.unspecified
2144 || !t0
.bitfield
.regsimd
))
2147 if (!g1
.bitfield
.reg
2148 && !g1
.bitfield
.regsimd
2149 && (!operand_type_check (g1
, anymem
)
2150 || g1
.bitfield
.unspecified
2151 || !t1
.bitfield
.regsimd
))
2154 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2155 && g0
.bitfield
.word
== g1
.bitfield
.word
2156 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2157 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2158 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2159 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2160 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2163 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2164 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2165 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2166 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2167 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2168 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2169 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2172 i
.error
= register_type_mismatch
;
2177 static INLINE
unsigned int
2178 register_number (const reg_entry
*r
)
2180 unsigned int nr
= r
->reg_num
;
2182 if (r
->reg_flags
& RegRex
)
2185 if (r
->reg_flags
& RegVRex
)
2191 static INLINE
unsigned int
2192 mode_from_disp_size (i386_operand_type t
)
2194 if (t
.bitfield
.disp8
)
2196 else if (t
.bitfield
.disp16
2197 || t
.bitfield
.disp32
2198 || t
.bitfield
.disp32s
)
2205 fits_in_signed_byte (addressT num
)
2207 return num
+ 0x80 <= 0xff;
2211 fits_in_unsigned_byte (addressT num
)
2217 fits_in_unsigned_word (addressT num
)
2219 return num
<= 0xffff;
2223 fits_in_signed_word (addressT num
)
2225 return num
+ 0x8000 <= 0xffff;
2229 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2234 return num
+ 0x80000000 <= 0xffffffff;
2236 } /* fits_in_signed_long() */
2239 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2244 return num
<= 0xffffffff;
2246 } /* fits_in_unsigned_long() */
2249 fits_in_disp8 (offsetT num
)
2251 int shift
= i
.memshift
;
2257 mask
= (1 << shift
) - 1;
2259 /* Return 0 if NUM isn't properly aligned. */
2263 /* Check if NUM will fit in 8bit after shift. */
2264 return fits_in_signed_byte (num
>> shift
);
2268 fits_in_imm4 (offsetT num
)
2270 return (num
& 0xf) == num
;
2273 static i386_operand_type
2274 smallest_imm_type (offsetT num
)
2276 i386_operand_type t
;
2278 operand_type_set (&t
, 0);
2279 t
.bitfield
.imm64
= 1;
2281 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2283 /* This code is disabled on the 486 because all the Imm1 forms
2284 in the opcode table are slower on the i486. They're the
2285 versions with the implicitly specified single-position
2286 displacement, which has another syntax if you really want to
2288 t
.bitfield
.imm1
= 1;
2289 t
.bitfield
.imm8
= 1;
2290 t
.bitfield
.imm8s
= 1;
2291 t
.bitfield
.imm16
= 1;
2292 t
.bitfield
.imm32
= 1;
2293 t
.bitfield
.imm32s
= 1;
2295 else if (fits_in_signed_byte (num
))
2297 t
.bitfield
.imm8
= 1;
2298 t
.bitfield
.imm8s
= 1;
2299 t
.bitfield
.imm16
= 1;
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_byte (num
))
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm16
= 1;
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2312 t
.bitfield
.imm16
= 1;
2313 t
.bitfield
.imm32
= 1;
2314 t
.bitfield
.imm32s
= 1;
2316 else if (fits_in_signed_long (num
))
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_long (num
))
2322 t
.bitfield
.imm32
= 1;
2328 offset_in_range (offsetT val
, int size
)
2334 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2335 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2336 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2338 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2344 /* If BFD64, sign extend val for 32bit address mode. */
2345 if (flag_code
!= CODE_64BIT
2346 || i
.prefix
[ADDR_PREFIX
])
2347 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2348 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2351 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2353 char buf1
[40], buf2
[40];
2355 sprint_value (buf1
, val
);
2356 sprint_value (buf2
, val
& mask
);
2357 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2372 a. PREFIX_EXIST if attempting to add a prefix where one from the
2373 same class already exists.
2374 b. PREFIX_LOCK if lock prefix is added.
2375 c. PREFIX_REP if rep/repne prefix is added.
2376 d. PREFIX_DS if ds prefix is added.
2377 e. PREFIX_OTHER if other prefix is added.
2380 static enum PREFIX_GROUP
2381 add_prefix (unsigned int prefix
)
2383 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2386 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2387 && flag_code
== CODE_64BIT
)
2389 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2390 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2391 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2392 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2403 case DS_PREFIX_OPCODE
:
2406 case CS_PREFIX_OPCODE
:
2407 case ES_PREFIX_OPCODE
:
2408 case FS_PREFIX_OPCODE
:
2409 case GS_PREFIX_OPCODE
:
2410 case SS_PREFIX_OPCODE
:
2414 case REPNE_PREFIX_OPCODE
:
2415 case REPE_PREFIX_OPCODE
:
2420 case LOCK_PREFIX_OPCODE
:
2429 case ADDR_PREFIX_OPCODE
:
2433 case DATA_PREFIX_OPCODE
:
2437 if (i
.prefix
[q
] != 0)
2445 i
.prefix
[q
] |= prefix
;
2448 as_bad (_("same type of prefix used twice"));
2454 update_code_flag (int value
, int check
)
2456 PRINTF_LIKE ((*as_error
));
2458 flag_code
= (enum flag_code
) value
;
2459 if (flag_code
== CODE_64BIT
)
2461 cpu_arch_flags
.bitfield
.cpu64
= 1;
2462 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2466 cpu_arch_flags
.bitfield
.cpu64
= 0;
2467 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2469 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2472 as_error
= as_fatal
;
2475 (*as_error
) (_("64bit mode not supported on `%s'."),
2476 cpu_arch_name
? cpu_arch_name
: default_arch
);
2478 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2481 as_error
= as_fatal
;
2484 (*as_error
) (_("32bit mode not supported on `%s'."),
2485 cpu_arch_name
? cpu_arch_name
: default_arch
);
2487 stackop_size
= '\0';
2491 set_code_flag (int value
)
2493 update_code_flag (value
, 0);
2497 set_16bit_gcc_code_flag (int new_code_flag
)
2499 flag_code
= (enum flag_code
) new_code_flag
;
2500 if (flag_code
!= CODE_16BIT
)
2502 cpu_arch_flags
.bitfield
.cpu64
= 0;
2503 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2504 stackop_size
= LONG_MNEM_SUFFIX
;
2508 set_intel_syntax (int syntax_flag
)
2510 /* Find out if register prefixing is specified. */
2511 int ask_naked_reg
= 0;
2514 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2517 int e
= get_symbol_name (&string
);
2519 if (strcmp (string
, "prefix") == 0)
2521 else if (strcmp (string
, "noprefix") == 0)
2524 as_bad (_("bad argument to syntax directive."));
2525 (void) restore_line_pointer (e
);
2527 demand_empty_rest_of_line ();
2529 intel_syntax
= syntax_flag
;
2531 if (ask_naked_reg
== 0)
2532 allow_naked_reg
= (intel_syntax
2533 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2535 allow_naked_reg
= (ask_naked_reg
< 0);
2537 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2539 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2540 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2541 register_prefix
= allow_naked_reg
? "" : "%";
2545 set_intel_mnemonic (int mnemonic_flag
)
2547 intel_mnemonic
= mnemonic_flag
;
2551 set_allow_index_reg (int flag
)
2553 allow_index_reg
= flag
;
2557 set_check (int what
)
2559 enum check_kind
*kind
;
2564 kind
= &operand_check
;
2575 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2578 int e
= get_symbol_name (&string
);
2580 if (strcmp (string
, "none") == 0)
2582 else if (strcmp (string
, "warning") == 0)
2583 *kind
= check_warning
;
2584 else if (strcmp (string
, "error") == 0)
2585 *kind
= check_error
;
2587 as_bad (_("bad argument to %s_check directive."), str
);
2588 (void) restore_line_pointer (e
);
2591 as_bad (_("missing argument for %s_check directive"), str
);
2593 demand_empty_rest_of_line ();
2597 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2598 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2601 static const char *arch
;
2603 /* Intel LIOM is only supported on ELF. */
2609 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2610 use default_arch. */
2611 arch
= cpu_arch_name
;
2613 arch
= default_arch
;
2616 /* If we are targeting Intel MCU, we must enable it. */
2617 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2618 || new_flag
.bitfield
.cpuiamcu
)
2621 /* If we are targeting Intel L1OM, we must enable it. */
2622 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2623 || new_flag
.bitfield
.cpul1om
)
2626 /* If we are targeting Intel K1OM, we must enable it. */
2627 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2628 || new_flag
.bitfield
.cpuk1om
)
2631 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2636 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2643 int e
= get_symbol_name (&string
);
2645 i386_cpu_flags flags
;
2647 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2649 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2651 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2655 cpu_arch_name
= cpu_arch
[j
].name
;
2656 cpu_sub_arch_name
= NULL
;
2657 cpu_arch_flags
= cpu_arch
[j
].flags
;
2658 if (flag_code
== CODE_64BIT
)
2660 cpu_arch_flags
.bitfield
.cpu64
= 1;
2661 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2665 cpu_arch_flags
.bitfield
.cpu64
= 0;
2666 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2668 cpu_arch_isa
= cpu_arch
[j
].type
;
2669 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2670 if (!cpu_arch_tune_set
)
2672 cpu_arch_tune
= cpu_arch_isa
;
2673 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2678 flags
= cpu_flags_or (cpu_arch_flags
,
2681 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2683 if (cpu_sub_arch_name
)
2685 char *name
= cpu_sub_arch_name
;
2686 cpu_sub_arch_name
= concat (name
,
2688 (const char *) NULL
);
2692 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2693 cpu_arch_flags
= flags
;
2694 cpu_arch_isa_flags
= flags
;
2698 = cpu_flags_or (cpu_arch_isa_flags
,
2700 (void) restore_line_pointer (e
);
2701 demand_empty_rest_of_line ();
2706 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2708 /* Disable an ISA extension. */
2709 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2710 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2712 flags
= cpu_flags_and_not (cpu_arch_flags
,
2713 cpu_noarch
[j
].flags
);
2714 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2716 if (cpu_sub_arch_name
)
2718 char *name
= cpu_sub_arch_name
;
2719 cpu_sub_arch_name
= concat (name
, string
,
2720 (const char *) NULL
);
2724 cpu_sub_arch_name
= xstrdup (string
);
2725 cpu_arch_flags
= flags
;
2726 cpu_arch_isa_flags
= flags
;
2728 (void) restore_line_pointer (e
);
2729 demand_empty_rest_of_line ();
2733 j
= ARRAY_SIZE (cpu_arch
);
2736 if (j
>= ARRAY_SIZE (cpu_arch
))
2737 as_bad (_("no such architecture: `%s'"), string
);
2739 *input_line_pointer
= e
;
2742 as_bad (_("missing cpu architecture"));
2744 no_cond_jump_promotion
= 0;
2745 if (*input_line_pointer
== ','
2746 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2751 ++input_line_pointer
;
2752 e
= get_symbol_name (&string
);
2754 if (strcmp (string
, "nojumps") == 0)
2755 no_cond_jump_promotion
= 1;
2756 else if (strcmp (string
, "jumps") == 0)
2759 as_bad (_("no such architecture modifier: `%s'"), string
);
2761 (void) restore_line_pointer (e
);
2764 demand_empty_rest_of_line ();
2767 enum bfd_architecture
2770 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2772 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2773 || flag_code
!= CODE_64BIT
)
2774 as_fatal (_("Intel L1OM is 64bit ELF only"));
2775 return bfd_arch_l1om
;
2777 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2779 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2780 || flag_code
!= CODE_64BIT
)
2781 as_fatal (_("Intel K1OM is 64bit ELF only"));
2782 return bfd_arch_k1om
;
2784 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2786 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2787 || flag_code
== CODE_64BIT
)
2788 as_fatal (_("Intel MCU is 32bit ELF only"));
2789 return bfd_arch_iamcu
;
2792 return bfd_arch_i386
;
2798 if (!strncmp (default_arch
, "x86_64", 6))
2800 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || default_arch
[6] != '\0')
2804 as_fatal (_("Intel L1OM is 64bit ELF only"));
2805 return bfd_mach_l1om
;
2807 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2809 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2810 || default_arch
[6] != '\0')
2811 as_fatal (_("Intel K1OM is 64bit ELF only"));
2812 return bfd_mach_k1om
;
2814 else if (default_arch
[6] == '\0')
2815 return bfd_mach_x86_64
;
2817 return bfd_mach_x64_32
;
2819 else if (!strcmp (default_arch
, "i386")
2820 || !strcmp (default_arch
, "iamcu"))
2822 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2825 as_fatal (_("Intel MCU is 32bit ELF only"));
2826 return bfd_mach_i386_iamcu
;
2829 return bfd_mach_i386_i386
;
2832 as_fatal (_("unknown architecture"));
2838 const char *hash_err
;
2840 /* Support pseudo prefixes like {disp32}. */
2841 lex_type
['{'] = LEX_BEGIN_NAME
;
2843 /* Initialize op_hash hash table. */
2844 op_hash
= hash_new ();
2847 const insn_template
*optab
;
2848 templates
*core_optab
;
2850 /* Setup for loop. */
2852 core_optab
= XNEW (templates
);
2853 core_optab
->start
= optab
;
2858 if (optab
->name
== NULL
2859 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2861 /* different name --> ship out current template list;
2862 add to hash table; & begin anew. */
2863 core_optab
->end
= optab
;
2864 hash_err
= hash_insert (op_hash
,
2866 (void *) core_optab
);
2869 as_fatal (_("can't hash %s: %s"),
2873 if (optab
->name
== NULL
)
2875 core_optab
= XNEW (templates
);
2876 core_optab
->start
= optab
;
2881 /* Initialize reg_hash hash table. */
2882 reg_hash
= hash_new ();
2884 const reg_entry
*regtab
;
2885 unsigned int regtab_size
= i386_regtab_size
;
2887 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2889 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2891 as_fatal (_("can't hash %s: %s"),
2897 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2902 for (c
= 0; c
< 256; c
++)
2907 mnemonic_chars
[c
] = c
;
2908 register_chars
[c
] = c
;
2909 operand_chars
[c
] = c
;
2911 else if (ISLOWER (c
))
2913 mnemonic_chars
[c
] = c
;
2914 register_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2917 else if (ISUPPER (c
))
2919 mnemonic_chars
[c
] = TOLOWER (c
);
2920 register_chars
[c
] = mnemonic_chars
[c
];
2921 operand_chars
[c
] = c
;
2923 else if (c
== '{' || c
== '}')
2925 mnemonic_chars
[c
] = c
;
2926 operand_chars
[c
] = c
;
2929 if (ISALPHA (c
) || ISDIGIT (c
))
2930 identifier_chars
[c
] = c
;
2933 identifier_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2939 identifier_chars
['@'] = '@';
2942 identifier_chars
['?'] = '?';
2943 operand_chars
['?'] = '?';
2945 digit_chars
['-'] = '-';
2946 mnemonic_chars
['_'] = '_';
2947 mnemonic_chars
['-'] = '-';
2948 mnemonic_chars
['.'] = '.';
2949 identifier_chars
['_'] = '_';
2950 identifier_chars
['.'] = '.';
2952 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2953 operand_chars
[(unsigned char) *p
] = *p
;
2956 if (flag_code
== CODE_64BIT
)
2958 #if defined (OBJ_COFF) && defined (TE_PE)
2959 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2962 x86_dwarf2_return_column
= 16;
2964 x86_cie_data_alignment
= -8;
2968 x86_dwarf2_return_column
= 8;
2969 x86_cie_data_alignment
= -4;
2974 i386_print_statistics (FILE *file
)
2976 hash_print_statistics (file
, "i386 opcode", op_hash
);
2977 hash_print_statistics (file
, "i386 register", reg_hash
);
2982 /* Debugging routines for md_assemble. */
2983 static void pte (insn_template
*);
2984 static void pt (i386_operand_type
);
2985 static void pe (expressionS
*);
2986 static void ps (symbolS
*);
2989 pi (char *line
, i386_insn
*x
)
2993 fprintf (stdout
, "%s: template ", line
);
2995 fprintf (stdout
, " address: base %s index %s scale %x\n",
2996 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2997 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2998 x
->log2_scale_factor
);
2999 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3000 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3001 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3002 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3003 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3004 (x
->rex
& REX_W
) != 0,
3005 (x
->rex
& REX_R
) != 0,
3006 (x
->rex
& REX_X
) != 0,
3007 (x
->rex
& REX_B
) != 0);
3008 for (j
= 0; j
< x
->operands
; j
++)
3010 fprintf (stdout
, " #%d: ", j
+ 1);
3012 fprintf (stdout
, "\n");
3013 if (x
->types
[j
].bitfield
.reg
3014 || x
->types
[j
].bitfield
.regmmx
3015 || x
->types
[j
].bitfield
.regsimd
3016 || x
->types
[j
].bitfield
.sreg2
3017 || x
->types
[j
].bitfield
.sreg3
3018 || x
->types
[j
].bitfield
.control
3019 || x
->types
[j
].bitfield
.debug
3020 || x
->types
[j
].bitfield
.test
)
3021 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3022 if (operand_type_check (x
->types
[j
], imm
))
3024 if (operand_type_check (x
->types
[j
], disp
))
3025 pe (x
->op
[j
].disps
);
3030 pte (insn_template
*t
)
3033 fprintf (stdout
, " %d operands ", t
->operands
);
3034 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3035 if (t
->extension_opcode
!= None
)
3036 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3037 if (t
->opcode_modifier
.d
)
3038 fprintf (stdout
, "D");
3039 if (t
->opcode_modifier
.w
)
3040 fprintf (stdout
, "W");
3041 fprintf (stdout
, "\n");
3042 for (j
= 0; j
< t
->operands
; j
++)
3044 fprintf (stdout
, " #%d type ", j
+ 1);
3045 pt (t
->operand_types
[j
]);
3046 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " operation %d\n", e
->X_op
);
3054 fprintf (stdout
, " add_number %ld (%lx)\n",
3055 (long) e
->X_add_number
, (long) e
->X_add_number
);
3056 if (e
->X_add_symbol
)
3058 fprintf (stdout
, " add_symbol ");
3059 ps (e
->X_add_symbol
);
3060 fprintf (stdout
, "\n");
3064 fprintf (stdout
, " op_symbol ");
3065 ps (e
->X_op_symbol
);
3066 fprintf (stdout
, "\n");
3073 fprintf (stdout
, "%s type %s%s",
3075 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3076 segment_name (S_GET_SEGMENT (s
)));
3079 static struct type_name
3081 i386_operand_type mask
;
3084 const type_names
[] =
3086 { OPERAND_TYPE_REG8
, "r8" },
3087 { OPERAND_TYPE_REG16
, "r16" },
3088 { OPERAND_TYPE_REG32
, "r32" },
3089 { OPERAND_TYPE_REG64
, "r64" },
3090 { OPERAND_TYPE_IMM8
, "i8" },
3091 { OPERAND_TYPE_IMM8
, "i8s" },
3092 { OPERAND_TYPE_IMM16
, "i16" },
3093 { OPERAND_TYPE_IMM32
, "i32" },
3094 { OPERAND_TYPE_IMM32S
, "i32s" },
3095 { OPERAND_TYPE_IMM64
, "i64" },
3096 { OPERAND_TYPE_IMM1
, "i1" },
3097 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3098 { OPERAND_TYPE_DISP8
, "d8" },
3099 { OPERAND_TYPE_DISP16
, "d16" },
3100 { OPERAND_TYPE_DISP32
, "d32" },
3101 { OPERAND_TYPE_DISP32S
, "d32s" },
3102 { OPERAND_TYPE_DISP64
, "d64" },
3103 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3104 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3105 { OPERAND_TYPE_CONTROL
, "control reg" },
3106 { OPERAND_TYPE_TEST
, "test reg" },
3107 { OPERAND_TYPE_DEBUG
, "debug reg" },
3108 { OPERAND_TYPE_FLOATREG
, "FReg" },
3109 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3110 { OPERAND_TYPE_SREG2
, "SReg2" },
3111 { OPERAND_TYPE_SREG3
, "SReg3" },
3112 { OPERAND_TYPE_ACC
, "Acc" },
3113 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3114 { OPERAND_TYPE_REGMMX
, "rMMX" },
3115 { OPERAND_TYPE_REGXMM
, "rXMM" },
3116 { OPERAND_TYPE_REGYMM
, "rYMM" },
3117 { OPERAND_TYPE_REGZMM
, "rZMM" },
3118 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3119 { OPERAND_TYPE_ESSEG
, "es" },
3123 pt (i386_operand_type t
)
3126 i386_operand_type a
;
3128 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3130 a
= operand_type_and (t
, type_names
[j
].mask
);
3131 if (!operand_type_all_zero (&a
))
3132 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3137 #endif /* DEBUG386 */
3139 static bfd_reloc_code_real_type
3140 reloc (unsigned int size
,
3143 bfd_reloc_code_real_type other
)
3145 if (other
!= NO_RELOC
)
3147 reloc_howto_type
*rel
;
3152 case BFD_RELOC_X86_64_GOT32
:
3153 return BFD_RELOC_X86_64_GOT64
;
3155 case BFD_RELOC_X86_64_GOTPLT64
:
3156 return BFD_RELOC_X86_64_GOTPLT64
;
3158 case BFD_RELOC_X86_64_PLTOFF64
:
3159 return BFD_RELOC_X86_64_PLTOFF64
;
3161 case BFD_RELOC_X86_64_GOTPC32
:
3162 other
= BFD_RELOC_X86_64_GOTPC64
;
3164 case BFD_RELOC_X86_64_GOTPCREL
:
3165 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3167 case BFD_RELOC_X86_64_TPOFF32
:
3168 other
= BFD_RELOC_X86_64_TPOFF64
;
3170 case BFD_RELOC_X86_64_DTPOFF32
:
3171 other
= BFD_RELOC_X86_64_DTPOFF64
;
3177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3178 if (other
== BFD_RELOC_SIZE32
)
3181 other
= BFD_RELOC_SIZE64
;
3184 as_bad (_("there are no pc-relative size relocations"));
3190 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3191 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3194 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3196 as_bad (_("unknown relocation (%u)"), other
);
3197 else if (size
!= bfd_get_reloc_size (rel
))
3198 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3199 bfd_get_reloc_size (rel
),
3201 else if (pcrel
&& !rel
->pc_relative
)
3202 as_bad (_("non-pc-relative relocation for pc-relative field"));
3203 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3205 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3207 as_bad (_("relocated field and relocation type differ in signedness"));
3216 as_bad (_("there are no unsigned pc-relative relocations"));
3219 case 1: return BFD_RELOC_8_PCREL
;
3220 case 2: return BFD_RELOC_16_PCREL
;
3221 case 4: return BFD_RELOC_32_PCREL
;
3222 case 8: return BFD_RELOC_64_PCREL
;
3224 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3231 case 4: return BFD_RELOC_X86_64_32S
;
3236 case 1: return BFD_RELOC_8
;
3237 case 2: return BFD_RELOC_16
;
3238 case 4: return BFD_RELOC_32
;
3239 case 8: return BFD_RELOC_64
;
3241 as_bad (_("cannot do %s %u byte relocation"),
3242 sign
> 0 ? "signed" : "unsigned", size
);
3248 /* Here we decide which fixups can be adjusted to make them relative to
3249 the beginning of the section instead of the symbol. Basically we need
3250 to make sure that the dynamic relocations are done correctly, so in
3251 some cases we force the original symbol to be used. */
3254 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3260 /* Don't adjust pc-relative references to merge sections in 64-bit
3262 if (use_rela_relocations
3263 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3267 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3268 and changed later by validate_fix. */
3269 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3270 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3273 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3274 for size relocations. */
3275 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3276 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3277 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3278 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3279 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3305 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3306 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3307 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3314 intel_float_operand (const char *mnemonic
)
3316 /* Note that the value returned is meaningful only for opcodes with (memory)
3317 operands, hence the code here is free to improperly handle opcodes that
3318 have no operands (for better performance and smaller code). */
3320 if (mnemonic
[0] != 'f')
3321 return 0; /* non-math */
3323 switch (mnemonic
[1])
3325 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3326 the fs segment override prefix not currently handled because no
3327 call path can make opcodes without operands get here */
3329 return 2 /* integer op */;
3331 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3332 return 3; /* fldcw/fldenv */
3335 if (mnemonic
[2] != 'o' /* fnop */)
3336 return 3; /* non-waiting control op */
3339 if (mnemonic
[2] == 's')
3340 return 3; /* frstor/frstpm */
3343 if (mnemonic
[2] == 'a')
3344 return 3; /* fsave */
3345 if (mnemonic
[2] == 't')
3347 switch (mnemonic
[3])
3349 case 'c': /* fstcw */
3350 case 'd': /* fstdw */
3351 case 'e': /* fstenv */
3352 case 's': /* fsts[gw] */
3358 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3359 return 0; /* fxsave/fxrstor are not really math ops */
3366 /* Build the VEX prefix. */
3369 build_vex_prefix (const insn_template
*t
)
3371 unsigned int register_specifier
;
3372 unsigned int implied_prefix
;
3373 unsigned int vector_length
;
3376 /* Check register specifier. */
3377 if (i
.vex
.register_specifier
)
3379 register_specifier
=
3380 ~register_number (i
.vex
.register_specifier
) & 0xf;
3381 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3384 register_specifier
= 0xf;
3386 /* Use 2-byte VEX prefix by swapping destination and source operand
3387 if there are more than 1 register operand. */
3388 if (i
.reg_operands
> 1
3389 && i
.vec_encoding
!= vex_encoding_vex3
3390 && i
.dir_encoding
== dir_encoding_default
3391 && i
.operands
== i
.reg_operands
3392 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3393 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3394 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3397 unsigned int xchg
= i
.operands
- 1;
3398 union i386_op temp_op
;
3399 i386_operand_type temp_type
;
3401 temp_type
= i
.types
[xchg
];
3402 i
.types
[xchg
] = i
.types
[0];
3403 i
.types
[0] = temp_type
;
3404 temp_op
= i
.op
[xchg
];
3405 i
.op
[xchg
] = i
.op
[0];
3408 gas_assert (i
.rm
.mode
== 3);
3412 i
.rm
.regmem
= i
.rm
.reg
;
3415 if (i
.tm
.opcode_modifier
.d
)
3416 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3417 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3418 else /* Use the next insn. */
3422 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3423 vector_length
= avxscalar
;
3424 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3430 /* Determine vector length from the last multi-length vector
3433 for (op
= t
->operands
; op
--;)
3434 if (t
->operand_types
[op
].bitfield
.xmmword
3435 && t
->operand_types
[op
].bitfield
.ymmword
3436 && i
.types
[op
].bitfield
.ymmword
)
3443 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3448 case DATA_PREFIX_OPCODE
:
3451 case REPE_PREFIX_OPCODE
:
3454 case REPNE_PREFIX_OPCODE
:
3461 /* Check the REX.W bit and VEXW. */
3462 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3463 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3464 else if (i
.tm
.opcode_modifier
.vexw
)
3465 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3467 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3469 /* Use 2-byte VEX prefix if possible. */
3471 && i
.vec_encoding
!= vex_encoding_vex3
3472 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3473 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3475 /* 2-byte VEX prefix. */
3479 i
.vex
.bytes
[0] = 0xc5;
3481 /* Check the REX.R bit. */
3482 r
= (i
.rex
& REX_R
) ? 0 : 1;
3483 i
.vex
.bytes
[1] = (r
<< 7
3484 | register_specifier
<< 3
3485 | vector_length
<< 2
3490 /* 3-byte VEX prefix. */
3495 switch (i
.tm
.opcode_modifier
.vexopcode
)
3499 i
.vex
.bytes
[0] = 0xc4;
3503 i
.vex
.bytes
[0] = 0xc4;
3507 i
.vex
.bytes
[0] = 0xc4;
3511 i
.vex
.bytes
[0] = 0x8f;
3515 i
.vex
.bytes
[0] = 0x8f;
3519 i
.vex
.bytes
[0] = 0x8f;
3525 /* The high 3 bits of the second VEX byte are 1's compliment
3526 of RXB bits from REX. */
3527 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3529 i
.vex
.bytes
[2] = (w
<< 7
3530 | register_specifier
<< 3
3531 | vector_length
<< 2
3536 static INLINE bfd_boolean
3537 is_evex_encoding (const insn_template
*t
)
3539 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3540 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3541 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3544 static INLINE bfd_boolean
3545 is_any_vex_encoding (const insn_template
*t
)
3547 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3548 || is_evex_encoding (t
);
3551 /* Build the EVEX prefix. */
3554 build_evex_prefix (void)
3556 unsigned int register_specifier
;
3557 unsigned int implied_prefix
;
3559 rex_byte vrex_used
= 0;
3561 /* Check register specifier. */
3562 if (i
.vex
.register_specifier
)
3564 gas_assert ((i
.vrex
& REX_X
) == 0);
3566 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3567 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3568 register_specifier
+= 8;
3569 /* The upper 16 registers are encoded in the fourth byte of the
3571 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3572 i
.vex
.bytes
[3] = 0x8;
3573 register_specifier
= ~register_specifier
& 0xf;
3577 register_specifier
= 0xf;
3579 /* Encode upper 16 vector index register in the fourth byte of
3581 if (!(i
.vrex
& REX_X
))
3582 i
.vex
.bytes
[3] = 0x8;
3587 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3592 case DATA_PREFIX_OPCODE
:
3595 case REPE_PREFIX_OPCODE
:
3598 case REPNE_PREFIX_OPCODE
:
3605 /* 4 byte EVEX prefix. */
3607 i
.vex
.bytes
[0] = 0x62;
3610 switch (i
.tm
.opcode_modifier
.vexopcode
)
3626 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3628 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3630 /* The fifth bit of the second EVEX byte is 1's compliment of the
3631 REX_R bit in VREX. */
3632 if (!(i
.vrex
& REX_R
))
3633 i
.vex
.bytes
[1] |= 0x10;
3637 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3639 /* When all operands are registers, the REX_X bit in REX is not
3640 used. We reuse it to encode the upper 16 registers, which is
3641 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3642 as 1's compliment. */
3643 if ((i
.vrex
& REX_B
))
3646 i
.vex
.bytes
[1] &= ~0x40;
3650 /* EVEX instructions shouldn't need the REX prefix. */
3651 i
.vrex
&= ~vrex_used
;
3652 gas_assert (i
.vrex
== 0);
3654 /* Check the REX.W bit and VEXW. */
3655 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3656 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3657 else if (i
.tm
.opcode_modifier
.vexw
)
3658 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3660 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3662 /* Encode the U bit. */
3663 implied_prefix
|= 0x4;
3665 /* The third byte of the EVEX prefix. */
3666 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3668 /* The fourth byte of the EVEX prefix. */
3669 /* The zeroing-masking bit. */
3670 if (i
.mask
&& i
.mask
->zeroing
)
3671 i
.vex
.bytes
[3] |= 0x80;
3673 /* Don't always set the broadcast bit if there is no RC. */
3676 /* Encode the vector length. */
3677 unsigned int vec_length
;
3679 if (!i
.tm
.opcode_modifier
.evex
3680 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3684 /* Determine vector length from the last multi-length vector
3687 for (op
= i
.operands
; op
--;)
3688 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3689 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3690 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3692 if (i
.types
[op
].bitfield
.zmmword
)
3694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3697 else if (i
.types
[op
].bitfield
.ymmword
)
3699 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3702 else if (i
.types
[op
].bitfield
.xmmword
)
3704 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3707 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3709 switch (i
.broadcast
->bytes
)
3712 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3715 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3718 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3727 if (op
>= MAX_OPERANDS
)
3731 switch (i
.tm
.opcode_modifier
.evex
)
3733 case EVEXLIG
: /* LL' is ignored */
3734 vec_length
= evexlig
<< 5;
3737 vec_length
= 0 << 5;
3740 vec_length
= 1 << 5;
3743 vec_length
= 2 << 5;
3749 i
.vex
.bytes
[3] |= vec_length
;
3750 /* Encode the broadcast bit. */
3752 i
.vex
.bytes
[3] |= 0x10;
3756 if (i
.rounding
->type
!= saeonly
)
3757 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3759 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3762 if (i
.mask
&& i
.mask
->mask
)
3763 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3767 process_immext (void)
3771 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3774 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3775 with an opcode suffix which is coded in the same place as an
3776 8-bit immediate field would be.
3777 Here we check those operands and remove them afterwards. */
3780 for (x
= 0; x
< i
.operands
; x
++)
3781 if (register_number (i
.op
[x
].regs
) != x
)
3782 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3783 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3789 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3791 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3792 suffix which is coded in the same place as an 8-bit immediate
3794 Here we check those operands and remove them afterwards. */
3797 if (i
.operands
!= 3)
3800 for (x
= 0; x
< 2; x
++)
3801 if (register_number (i
.op
[x
].regs
) != x
)
3802 goto bad_register_operand
;
3804 /* Check for third operand for mwaitx/monitorx insn. */
3805 if (register_number (i
.op
[x
].regs
)
3806 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3808 bad_register_operand
:
3809 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3810 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3818 which is coded in the same place as an 8-bit immediate field
3819 would be. Here we fake an 8-bit immediate operand from the
3820 opcode suffix stored in tm.extension_opcode.
3822 AVX instructions also use this encoding, for some of
3823 3 argument instructions. */
3825 gas_assert (i
.imm_operands
<= 1
3827 || (is_any_vex_encoding (&i
.tm
)
3828 && i
.operands
<= 4)));
3830 exp
= &im_expressions
[i
.imm_operands
++];
3831 i
.op
[i
.operands
].imms
= exp
;
3832 i
.types
[i
.operands
] = imm8
;
3834 exp
->X_op
= O_constant
;
3835 exp
->X_add_number
= i
.tm
.extension_opcode
;
3836 i
.tm
.extension_opcode
= None
;
3843 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3848 as_bad (_("invalid instruction `%s' after `%s'"),
3849 i
.tm
.name
, i
.hle_prefix
);
3852 if (i
.prefix
[LOCK_PREFIX
])
3854 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3858 case HLEPrefixRelease
:
3859 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3861 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3865 if (i
.mem_operands
== 0
3866 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3868 as_bad (_("memory destination needed for instruction `%s'"
3869 " after `xrelease'"), i
.tm
.name
);
3876 /* Try the shortest encoding by shortening operand size. */
3879 optimize_encoding (void)
3883 if (optimize_for_space
3884 && i
.reg_operands
== 1
3885 && i
.imm_operands
== 1
3886 && !i
.types
[1].bitfield
.byte
3887 && i
.op
[0].imms
->X_op
== O_constant
3888 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3889 && ((i
.tm
.base_opcode
== 0xa8
3890 && i
.tm
.extension_opcode
== None
)
3891 || (i
.tm
.base_opcode
== 0xf6
3892 && i
.tm
.extension_opcode
== 0x0)))
3895 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3897 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3898 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3900 i
.types
[1].bitfield
.byte
= 1;
3901 /* Ignore the suffix. */
3903 if (base_regnum
>= 4
3904 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3906 /* Handle SP, BP, SI and DI registers. */
3907 if (i
.types
[1].bitfield
.word
)
3909 else if (i
.types
[1].bitfield
.dword
)
3917 else if (flag_code
== CODE_64BIT
3918 && ((i
.types
[1].bitfield
.qword
3919 && i
.reg_operands
== 1
3920 && i
.imm_operands
== 1
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && ((i
.tm
.base_opcode
== 0xb0
3923 && i
.tm
.extension_opcode
== None
3924 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3925 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3926 && (((i
.tm
.base_opcode
== 0x24
3927 || i
.tm
.base_opcode
== 0xa8)
3928 && i
.tm
.extension_opcode
== None
)
3929 || (i
.tm
.base_opcode
== 0x80
3930 && i
.tm
.extension_opcode
== 0x4)
3931 || ((i
.tm
.base_opcode
== 0xf6
3932 || i
.tm
.base_opcode
== 0xc6)
3933 && i
.tm
.extension_opcode
== 0x0)))))
3934 || (i
.types
[0].bitfield
.qword
3935 && ((i
.reg_operands
== 2
3936 && i
.op
[0].regs
== i
.op
[1].regs
3937 && ((i
.tm
.base_opcode
== 0x30
3938 || i
.tm
.base_opcode
== 0x28)
3939 && i
.tm
.extension_opcode
== None
))
3940 || (i
.reg_operands
== 1
3942 && i
.tm
.base_opcode
== 0x30
3943 && i
.tm
.extension_opcode
== None
)))))
3946 andq $imm31, %r64 -> andl $imm31, %r32
3947 testq $imm31, %r64 -> testl $imm31, %r32
3948 xorq %r64, %r64 -> xorl %r32, %r32
3949 subq %r64, %r64 -> subl %r32, %r32
3950 movq $imm31, %r64 -> movl $imm31, %r32
3951 movq $imm32, %r64 -> movl $imm32, %r32
3953 i
.tm
.opcode_modifier
.norex64
= 1;
3954 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3957 movq $imm31, %r64 -> movl $imm31, %r32
3958 movq $imm32, %r64 -> movl $imm32, %r32
3960 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3961 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3962 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3963 i
.types
[0].bitfield
.imm32
= 1;
3964 i
.types
[0].bitfield
.imm32s
= 0;
3965 i
.types
[0].bitfield
.imm64
= 0;
3966 i
.types
[1].bitfield
.dword
= 1;
3967 i
.types
[1].bitfield
.qword
= 0;
3968 if (i
.tm
.base_opcode
== 0xc6)
3971 movq $imm31, %r64 -> movl $imm31, %r32
3973 i
.tm
.base_opcode
= 0xb0;
3974 i
.tm
.extension_opcode
= None
;
3975 i
.tm
.opcode_modifier
.shortform
= 1;
3976 i
.tm
.opcode_modifier
.modrm
= 0;
3980 else if (i
.reg_operands
== 3
3981 && i
.op
[0].regs
== i
.op
[1].regs
3982 && !i
.types
[2].bitfield
.xmmword
3983 && (i
.tm
.opcode_modifier
.vex
3984 || ((!i
.mask
|| i
.mask
->zeroing
)
3986 && is_evex_encoding (&i
.tm
)
3987 && (i
.vec_encoding
!= vex_encoding_evex
3988 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
3989 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3990 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3991 && i
.types
[2].bitfield
.ymmword
))))
3992 && ((i
.tm
.base_opcode
== 0x55
3993 || i
.tm
.base_opcode
== 0x6655
3994 || i
.tm
.base_opcode
== 0x66df
3995 || i
.tm
.base_opcode
== 0x57
3996 || i
.tm
.base_opcode
== 0x6657
3997 || i
.tm
.base_opcode
== 0x66ef
3998 || i
.tm
.base_opcode
== 0x66f8
3999 || i
.tm
.base_opcode
== 0x66f9
4000 || i
.tm
.base_opcode
== 0x66fa
4001 || i
.tm
.base_opcode
== 0x66fb
4002 || i
.tm
.base_opcode
== 0x42
4003 || i
.tm
.base_opcode
== 0x6642
4004 || i
.tm
.base_opcode
== 0x47
4005 || i
.tm
.base_opcode
== 0x6647)
4006 && i
.tm
.extension_opcode
== None
))
4009 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4011 EVEX VOP %zmmM, %zmmM, %zmmN
4012 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4013 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4014 EVEX VOP %ymmM, %ymmM, %ymmN
4015 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4017 VEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX VOP %xmmM, %xmmM, %xmmN
4019 VOP, one of vpandn and vpxor:
4020 VEX VOP %ymmM, %ymmM, %ymmN
4021 -> VEX VOP %xmmM, %xmmM, %xmmN
4022 VOP, one of vpandnd and vpandnq:
4023 EVEX VOP %zmmM, %zmmM, %zmmN
4024 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4026 EVEX VOP %ymmM, %ymmM, %ymmN
4027 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 VOP, one of vpxord and vpxorq:
4030 EVEX VOP %zmmM, %zmmM, %zmmN
4031 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4032 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4033 EVEX VOP %ymmM, %ymmM, %ymmN
4034 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 VOP, one of kxord and kxorq:
4037 VEX VOP %kM, %kM, %kN
4038 -> VEX kxorw %kM, %kM, %kN
4039 VOP, one of kandnd and kandnq:
4040 VEX VOP %kM, %kM, %kN
4041 -> VEX kandnw %kM, %kM, %kN
4043 if (is_evex_encoding (&i
.tm
))
4045 if (i
.vec_encoding
!= vex_encoding_evex
)
4047 i
.tm
.opcode_modifier
.vex
= VEX128
;
4048 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4049 i
.tm
.opcode_modifier
.evex
= 0;
4051 else if (optimize
> 1)
4052 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4056 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4058 i
.tm
.base_opcode
&= 0xff;
4059 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4062 i
.tm
.opcode_modifier
.vex
= VEX128
;
4064 if (i
.tm
.opcode_modifier
.vex
)
4065 for (j
= 0; j
< 3; j
++)
4067 i
.types
[j
].bitfield
.xmmword
= 1;
4068 i
.types
[j
].bitfield
.ymmword
= 0;
4071 else if ((cpu_arch_flags
.bitfield
.cpuavx
4072 || cpu_arch_isa_flags
.bitfield
.cpuavx
)
4073 && i
.vec_encoding
!= vex_encoding_evex
4074 && !i
.types
[0].bitfield
.zmmword
4076 && is_evex_encoding (&i
.tm
)
4077 && (i
.tm
.base_opcode
== 0x666f
4078 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0x666f
4079 || i
.tm
.base_opcode
== 0xf36f
4080 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf36f
4081 || i
.tm
.base_opcode
== 0xf26f
4082 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf26f)
4083 && i
.tm
.extension_opcode
== None
)
4086 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4087 vmovdqu32 and vmovdqu64:
4088 EVEX VOP %xmmM, %xmmN
4089 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4090 EVEX VOP %ymmM, %ymmN
4091 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4093 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4095 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4097 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4099 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4101 if (i
.tm
.base_opcode
== 0xf26f)
4102 i
.tm
.base_opcode
= 0xf36f;
4103 else if ((i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf26f)
4104 i
.tm
.base_opcode
= 0xf36f ^ Opcode_SIMD_IntD
;
4105 i
.tm
.opcode_modifier
.vex
4106 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4107 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4108 i
.tm
.opcode_modifier
.evex
= 0;
4109 i
.tm
.opcode_modifier
.masking
= 0;
4110 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4112 for (j
= 0; j
< 2; j
++)
4113 if (operand_type_check (i
.types
[j
], disp
)
4114 && i
.op
[j
].disps
->X_op
== O_constant
)
4116 i
.types
[j
].bitfield
.disp8
4117 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4123 /* This is the guts of the machine-dependent assembler. LINE points to a
4124 machine dependent instruction. This function is supposed to emit
4125 the frags/bytes it assembles to. */
4128 md_assemble (char *line
)
4131 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4132 const insn_template
*t
;
4134 /* Initialize globals. */
4135 memset (&i
, '\0', sizeof (i
));
4136 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4137 i
.reloc
[j
] = NO_RELOC
;
4138 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4139 memset (im_expressions
, '\0', sizeof (im_expressions
));
4140 save_stack_p
= save_stack
;
4142 /* First parse an instruction mnemonic & call i386_operand for the operands.
4143 We assume that the scrubber has arranged it so that line[0] is the valid
4144 start of a (possibly prefixed) mnemonic. */
4146 line
= parse_insn (line
, mnemonic
);
4149 mnem_suffix
= i
.suffix
;
4151 line
= parse_operands (line
, mnemonic
);
4153 xfree (i
.memop1_string
);
4154 i
.memop1_string
= NULL
;
4158 /* Now we've parsed the mnemonic into a set of templates, and have the
4159 operands at hand. */
4161 /* All intel opcodes have reversed operands except for "bound" and
4162 "enter". We also don't reverse intersegment "jmp" and "call"
4163 instructions with 2 immediate operands so that the immediate segment
4164 precedes the offset, as it does when in AT&T mode. */
4167 && (strcmp (mnemonic
, "bound") != 0)
4168 && (strcmp (mnemonic
, "invlpga") != 0)
4169 && !(operand_type_check (i
.types
[0], imm
)
4170 && operand_type_check (i
.types
[1], imm
)))
4173 /* The order of the immediates should be reversed
4174 for 2 immediates extrq and insertq instructions */
4175 if (i
.imm_operands
== 2
4176 && (strcmp (mnemonic
, "extrq") == 0
4177 || strcmp (mnemonic
, "insertq") == 0))
4178 swap_2_operands (0, 1);
4183 /* Don't optimize displacement for movabs since it only takes 64bit
4186 && i
.disp_encoding
!= disp_encoding_32bit
4187 && (flag_code
!= CODE_64BIT
4188 || strcmp (mnemonic
, "movabs") != 0))
4191 /* Next, we find a template that matches the given insn,
4192 making sure the overlap of the given operands types is consistent
4193 with the template operand types. */
4195 if (!(t
= match_template (mnem_suffix
)))
4198 if (sse_check
!= check_none
4199 && !i
.tm
.opcode_modifier
.noavx
4200 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4201 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4202 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4203 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4204 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4205 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4206 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4207 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4208 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4209 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4211 (sse_check
== check_warning
4213 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4216 /* Zap movzx and movsx suffix. The suffix has been set from
4217 "word ptr" or "byte ptr" on the source operand in Intel syntax
4218 or extracted from mnemonic in AT&T syntax. But we'll use
4219 the destination register to choose the suffix for encoding. */
4220 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4222 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4223 there is no suffix, the default will be byte extension. */
4224 if (i
.reg_operands
!= 2
4227 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4232 if (i
.tm
.opcode_modifier
.fwait
)
4233 if (!add_prefix (FWAIT_OPCODE
))
4236 /* Check if REP prefix is OK. */
4237 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4239 as_bad (_("invalid instruction `%s' after `%s'"),
4240 i
.tm
.name
, i
.rep_prefix
);
4244 /* Check for lock without a lockable instruction. Destination operand
4245 must be memory unless it is xchg (0x86). */
4246 if (i
.prefix
[LOCK_PREFIX
]
4247 && (!i
.tm
.opcode_modifier
.islockable
4248 || i
.mem_operands
== 0
4249 || (i
.tm
.base_opcode
!= 0x86
4250 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4252 as_bad (_("expecting lockable instruction after `lock'"));
4256 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4257 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4259 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4263 /* Check if HLE prefix is OK. */
4264 if (i
.hle_prefix
&& !check_hle ())
4267 /* Check BND prefix. */
4268 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4269 as_bad (_("expecting valid branch instruction after `bnd'"));
4271 /* Check NOTRACK prefix. */
4272 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4273 as_bad (_("expecting indirect branch instruction after `notrack'"));
4275 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4277 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4278 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4279 else if (flag_code
!= CODE_16BIT
4280 ? i
.prefix
[ADDR_PREFIX
]
4281 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4282 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4285 /* Insert BND prefix. */
4286 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4288 if (!i
.prefix
[BND_PREFIX
])
4289 add_prefix (BND_PREFIX_OPCODE
);
4290 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4292 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4293 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4297 /* Check string instruction segment overrides. */
4298 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4300 if (!check_string ())
4302 i
.disp_operands
= 0;
4305 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4306 optimize_encoding ();
4308 if (!process_suffix ())
4311 /* Update operand types. */
4312 for (j
= 0; j
< i
.operands
; j
++)
4313 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4315 /* Make still unresolved immediate matches conform to size of immediate
4316 given in i.suffix. */
4317 if (!finalize_imm ())
4320 if (i
.types
[0].bitfield
.imm1
)
4321 i
.imm_operands
= 0; /* kludge for shift insns. */
4323 /* We only need to check those implicit registers for instructions
4324 with 3 operands or less. */
4325 if (i
.operands
<= 3)
4326 for (j
= 0; j
< i
.operands
; j
++)
4327 if (i
.types
[j
].bitfield
.inoutportreg
4328 || i
.types
[j
].bitfield
.shiftcount
4329 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4332 /* ImmExt should be processed after SSE2AVX. */
4333 if (!i
.tm
.opcode_modifier
.sse2avx
4334 && i
.tm
.opcode_modifier
.immext
)
4337 /* For insns with operands there are more diddles to do to the opcode. */
4340 if (!process_operands ())
4343 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4345 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4346 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4349 if (is_any_vex_encoding (&i
.tm
))
4351 if (flag_code
== CODE_16BIT
)
4353 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4358 if (i
.tm
.opcode_modifier
.vex
)
4359 build_vex_prefix (t
);
4361 build_evex_prefix ();
4364 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4365 instructions may define INT_OPCODE as well, so avoid this corner
4366 case for those instructions that use MODRM. */
4367 if (i
.tm
.base_opcode
== INT_OPCODE
4368 && !i
.tm
.opcode_modifier
.modrm
4369 && i
.op
[0].imms
->X_add_number
== 3)
4371 i
.tm
.base_opcode
= INT3_OPCODE
;
4375 if ((i
.tm
.opcode_modifier
.jump
4376 || i
.tm
.opcode_modifier
.jumpbyte
4377 || i
.tm
.opcode_modifier
.jumpdword
)
4378 && i
.op
[0].disps
->X_op
== O_constant
)
4380 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4381 the absolute address given by the constant. Since ix86 jumps and
4382 calls are pc relative, we need to generate a reloc. */
4383 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4384 i
.op
[0].disps
->X_op
= O_symbol
;
4387 if (i
.tm
.opcode_modifier
.rex64
)
4390 /* For 8 bit registers we need an empty rex prefix. Also if the
4391 instruction already has a prefix, we need to convert old
4392 registers to new ones. */
4394 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4395 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4396 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4397 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4398 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4399 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4404 i
.rex
|= REX_OPCODE
;
4405 for (x
= 0; x
< 2; x
++)
4407 /* Look for 8 bit operand that uses old registers. */
4408 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4409 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4411 /* In case it is "hi" register, give up. */
4412 if (i
.op
[x
].regs
->reg_num
> 3)
4413 as_bad (_("can't encode register '%s%s' in an "
4414 "instruction requiring REX prefix."),
4415 register_prefix
, i
.op
[x
].regs
->reg_name
);
4417 /* Otherwise it is equivalent to the extended register.
4418 Since the encoding doesn't change this is merely
4419 cosmetic cleanup for debug output. */
4421 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4426 if (i
.rex
== 0 && i
.rex_encoding
)
4428 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4429 that uses legacy register. If it is "hi" register, don't add
4430 the REX_OPCODE byte. */
4432 for (x
= 0; x
< 2; x
++)
4433 if (i
.types
[x
].bitfield
.reg
4434 && i
.types
[x
].bitfield
.byte
4435 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4436 && i
.op
[x
].regs
->reg_num
> 3)
4438 i
.rex_encoding
= FALSE
;
4447 add_prefix (REX_OPCODE
| i
.rex
);
4449 /* We are ready to output the insn. */
4454 parse_insn (char *line
, char *mnemonic
)
4457 char *token_start
= l
;
4460 const insn_template
*t
;
4466 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4471 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4473 as_bad (_("no such instruction: `%s'"), token_start
);
4478 if (!is_space_char (*l
)
4479 && *l
!= END_OF_INSN
4481 || (*l
!= PREFIX_SEPARATOR
4484 as_bad (_("invalid character %s in mnemonic"),
4485 output_invalid (*l
));
4488 if (token_start
== l
)
4490 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4491 as_bad (_("expecting prefix; got nothing"));
4493 as_bad (_("expecting mnemonic; got nothing"));
4497 /* Look up instruction (or prefix) via hash table. */
4498 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4500 if (*l
!= END_OF_INSN
4501 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4502 && current_templates
4503 && current_templates
->start
->opcode_modifier
.isprefix
)
4505 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4507 as_bad ((flag_code
!= CODE_64BIT
4508 ? _("`%s' is only supported in 64-bit mode")
4509 : _("`%s' is not supported in 64-bit mode")),
4510 current_templates
->start
->name
);
4513 /* If we are in 16-bit mode, do not allow addr16 or data16.
4514 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4515 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4516 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4517 && flag_code
!= CODE_64BIT
4518 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4519 ^ (flag_code
== CODE_16BIT
)))
4521 as_bad (_("redundant %s prefix"),
4522 current_templates
->start
->name
);
4525 if (current_templates
->start
->opcode_length
== 0)
4527 /* Handle pseudo prefixes. */
4528 switch (current_templates
->start
->base_opcode
)
4532 i
.disp_encoding
= disp_encoding_8bit
;
4536 i
.disp_encoding
= disp_encoding_32bit
;
4540 i
.dir_encoding
= dir_encoding_load
;
4544 i
.dir_encoding
= dir_encoding_store
;
4548 i
.vec_encoding
= vex_encoding_vex2
;
4552 i
.vec_encoding
= vex_encoding_vex3
;
4556 i
.vec_encoding
= vex_encoding_evex
;
4560 i
.rex_encoding
= TRUE
;
4564 i
.no_optimize
= TRUE
;
4572 /* Add prefix, checking for repeated prefixes. */
4573 switch (add_prefix (current_templates
->start
->base_opcode
))
4578 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4579 i
.notrack_prefix
= current_templates
->start
->name
;
4582 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4583 i
.hle_prefix
= current_templates
->start
->name
;
4584 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4585 i
.bnd_prefix
= current_templates
->start
->name
;
4587 i
.rep_prefix
= current_templates
->start
->name
;
4593 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4600 if (!current_templates
)
4602 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4603 Check if we should swap operand or force 32bit displacement in
4605 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4606 i
.dir_encoding
= dir_encoding_swap
;
4607 else if (mnem_p
- 3 == dot_p
4610 i
.disp_encoding
= disp_encoding_8bit
;
4611 else if (mnem_p
- 4 == dot_p
4615 i
.disp_encoding
= disp_encoding_32bit
;
4620 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4623 if (!current_templates
)
4626 if (mnem_p
> mnemonic
)
4628 /* See if we can get a match by trimming off a suffix. */
4631 case WORD_MNEM_SUFFIX
:
4632 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4633 i
.suffix
= SHORT_MNEM_SUFFIX
;
4636 case BYTE_MNEM_SUFFIX
:
4637 case QWORD_MNEM_SUFFIX
:
4638 i
.suffix
= mnem_p
[-1];
4640 current_templates
= (const templates
*) hash_find (op_hash
,
4643 case SHORT_MNEM_SUFFIX
:
4644 case LONG_MNEM_SUFFIX
:
4647 i
.suffix
= mnem_p
[-1];
4649 current_templates
= (const templates
*) hash_find (op_hash
,
4658 if (intel_float_operand (mnemonic
) == 1)
4659 i
.suffix
= SHORT_MNEM_SUFFIX
;
4661 i
.suffix
= LONG_MNEM_SUFFIX
;
4663 current_templates
= (const templates
*) hash_find (op_hash
,
4670 if (!current_templates
)
4672 as_bad (_("no such instruction: `%s'"), token_start
);
4677 if (current_templates
->start
->opcode_modifier
.jump
4678 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4680 /* Check for a branch hint. We allow ",pt" and ",pn" for
4681 predict taken and predict not taken respectively.
4682 I'm not sure that branch hints actually do anything on loop
4683 and jcxz insns (JumpByte) for current Pentium4 chips. They
4684 may work in the future and it doesn't hurt to accept them
4686 if (l
[0] == ',' && l
[1] == 'p')
4690 if (!add_prefix (DS_PREFIX_OPCODE
))
4694 else if (l
[2] == 'n')
4696 if (!add_prefix (CS_PREFIX_OPCODE
))
4702 /* Any other comma loses. */
4705 as_bad (_("invalid character %s in mnemonic"),
4706 output_invalid (*l
));
4710 /* Check if instruction is supported on specified architecture. */
4712 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4714 supported
|= cpu_flags_match (t
);
4715 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4717 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4718 as_warn (_("use .code16 to ensure correct addressing mode"));
4724 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4725 as_bad (flag_code
== CODE_64BIT
4726 ? _("`%s' is not supported in 64-bit mode")
4727 : _("`%s' is only supported in 64-bit mode"),
4728 current_templates
->start
->name
);
4730 as_bad (_("`%s' is not supported on `%s%s'"),
4731 current_templates
->start
->name
,
4732 cpu_arch_name
? cpu_arch_name
: default_arch
,
4733 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4739 parse_operands (char *l
, const char *mnemonic
)
4743 /* 1 if operand is pending after ','. */
4744 unsigned int expecting_operand
= 0;
4746 /* Non-zero if operand parens not balanced. */
4747 unsigned int paren_not_balanced
;
4749 while (*l
!= END_OF_INSN
)
4751 /* Skip optional white space before operand. */
4752 if (is_space_char (*l
))
4754 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4756 as_bad (_("invalid character %s before operand %d"),
4757 output_invalid (*l
),
4761 token_start
= l
; /* After white space. */
4762 paren_not_balanced
= 0;
4763 while (paren_not_balanced
|| *l
!= ',')
4765 if (*l
== END_OF_INSN
)
4767 if (paren_not_balanced
)
4770 as_bad (_("unbalanced parenthesis in operand %d."),
4773 as_bad (_("unbalanced brackets in operand %d."),
4778 break; /* we are done */
4780 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4782 as_bad (_("invalid character %s in operand %d"),
4783 output_invalid (*l
),
4790 ++paren_not_balanced
;
4792 --paren_not_balanced
;
4797 ++paren_not_balanced
;
4799 --paren_not_balanced
;
4803 if (l
!= token_start
)
4804 { /* Yes, we've read in another operand. */
4805 unsigned int operand_ok
;
4806 this_operand
= i
.operands
++;
4807 if (i
.operands
> MAX_OPERANDS
)
4809 as_bad (_("spurious operands; (%d operands/instruction max)"),
4813 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4814 /* Now parse operand adding info to 'i' as we go along. */
4815 END_STRING_AND_SAVE (l
);
4817 if (i
.mem_operands
> 1)
4819 as_bad (_("too many memory references for `%s'"),
4826 i386_intel_operand (token_start
,
4827 intel_float_operand (mnemonic
));
4829 operand_ok
= i386_att_operand (token_start
);
4831 RESTORE_END_STRING (l
);
4837 if (expecting_operand
)
4839 expecting_operand_after_comma
:
4840 as_bad (_("expecting operand after ','; got nothing"));
4845 as_bad (_("expecting operand before ','; got nothing"));
4850 /* Now *l must be either ',' or END_OF_INSN. */
4853 if (*++l
== END_OF_INSN
)
4855 /* Just skip it, if it's \n complain. */
4856 goto expecting_operand_after_comma
;
4858 expecting_operand
= 1;
4865 swap_2_operands (int xchg1
, int xchg2
)
4867 union i386_op temp_op
;
4868 i386_operand_type temp_type
;
4869 unsigned int temp_flags
;
4870 enum bfd_reloc_code_real temp_reloc
;
4872 temp_type
= i
.types
[xchg2
];
4873 i
.types
[xchg2
] = i
.types
[xchg1
];
4874 i
.types
[xchg1
] = temp_type
;
4876 temp_flags
= i
.flags
[xchg2
];
4877 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4878 i
.flags
[xchg1
] = temp_flags
;
4880 temp_op
= i
.op
[xchg2
];
4881 i
.op
[xchg2
] = i
.op
[xchg1
];
4882 i
.op
[xchg1
] = temp_op
;
4884 temp_reloc
= i
.reloc
[xchg2
];
4885 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4886 i
.reloc
[xchg1
] = temp_reloc
;
4890 if (i
.mask
->operand
== xchg1
)
4891 i
.mask
->operand
= xchg2
;
4892 else if (i
.mask
->operand
== xchg2
)
4893 i
.mask
->operand
= xchg1
;
4897 if (i
.broadcast
->operand
== xchg1
)
4898 i
.broadcast
->operand
= xchg2
;
4899 else if (i
.broadcast
->operand
== xchg2
)
4900 i
.broadcast
->operand
= xchg1
;
4904 if (i
.rounding
->operand
== xchg1
)
4905 i
.rounding
->operand
= xchg2
;
4906 else if (i
.rounding
->operand
== xchg2
)
4907 i
.rounding
->operand
= xchg1
;
4912 swap_operands (void)
4918 swap_2_operands (1, i
.operands
- 2);
4922 swap_2_operands (0, i
.operands
- 1);
4928 if (i
.mem_operands
== 2)
4930 const seg_entry
*temp_seg
;
4931 temp_seg
= i
.seg
[0];
4932 i
.seg
[0] = i
.seg
[1];
4933 i
.seg
[1] = temp_seg
;
4937 /* Try to ensure constant immediates are represented in the smallest
4942 char guess_suffix
= 0;
4946 guess_suffix
= i
.suffix
;
4947 else if (i
.reg_operands
)
4949 /* Figure out a suffix from the last register operand specified.
4950 We can't do this properly yet, ie. excluding InOutPortReg,
4951 but the following works for instructions with immediates.
4952 In any case, we can't set i.suffix yet. */
4953 for (op
= i
.operands
; --op
>= 0;)
4954 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4956 guess_suffix
= BYTE_MNEM_SUFFIX
;
4959 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4961 guess_suffix
= WORD_MNEM_SUFFIX
;
4964 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4966 guess_suffix
= LONG_MNEM_SUFFIX
;
4969 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4971 guess_suffix
= QWORD_MNEM_SUFFIX
;
4975 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4976 guess_suffix
= WORD_MNEM_SUFFIX
;
4978 for (op
= i
.operands
; --op
>= 0;)
4979 if (operand_type_check (i
.types
[op
], imm
))
4981 switch (i
.op
[op
].imms
->X_op
)
4984 /* If a suffix is given, this operand may be shortened. */
4985 switch (guess_suffix
)
4987 case LONG_MNEM_SUFFIX
:
4988 i
.types
[op
].bitfield
.imm32
= 1;
4989 i
.types
[op
].bitfield
.imm64
= 1;
4991 case WORD_MNEM_SUFFIX
:
4992 i
.types
[op
].bitfield
.imm16
= 1;
4993 i
.types
[op
].bitfield
.imm32
= 1;
4994 i
.types
[op
].bitfield
.imm32s
= 1;
4995 i
.types
[op
].bitfield
.imm64
= 1;
4997 case BYTE_MNEM_SUFFIX
:
4998 i
.types
[op
].bitfield
.imm8
= 1;
4999 i
.types
[op
].bitfield
.imm8s
= 1;
5000 i
.types
[op
].bitfield
.imm16
= 1;
5001 i
.types
[op
].bitfield
.imm32
= 1;
5002 i
.types
[op
].bitfield
.imm32s
= 1;
5003 i
.types
[op
].bitfield
.imm64
= 1;
5007 /* If this operand is at most 16 bits, convert it
5008 to a signed 16 bit number before trying to see
5009 whether it will fit in an even smaller size.
5010 This allows a 16-bit operand such as $0xffe0 to
5011 be recognised as within Imm8S range. */
5012 if ((i
.types
[op
].bitfield
.imm16
)
5013 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5015 i
.op
[op
].imms
->X_add_number
=
5016 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5019 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5020 if ((i
.types
[op
].bitfield
.imm32
)
5021 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5024 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5025 ^ ((offsetT
) 1 << 31))
5026 - ((offsetT
) 1 << 31));
5030 = operand_type_or (i
.types
[op
],
5031 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5033 /* We must avoid matching of Imm32 templates when 64bit
5034 only immediate is available. */
5035 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5036 i
.types
[op
].bitfield
.imm32
= 0;
5043 /* Symbols and expressions. */
5045 /* Convert symbolic operand to proper sizes for matching, but don't
5046 prevent matching a set of insns that only supports sizes other
5047 than those matching the insn suffix. */
5049 i386_operand_type mask
, allowed
;
5050 const insn_template
*t
;
5052 operand_type_set (&mask
, 0);
5053 operand_type_set (&allowed
, 0);
5055 for (t
= current_templates
->start
;
5056 t
< current_templates
->end
;
5058 allowed
= operand_type_or (allowed
,
5059 t
->operand_types
[op
]);
5060 switch (guess_suffix
)
5062 case QWORD_MNEM_SUFFIX
:
5063 mask
.bitfield
.imm64
= 1;
5064 mask
.bitfield
.imm32s
= 1;
5066 case LONG_MNEM_SUFFIX
:
5067 mask
.bitfield
.imm32
= 1;
5069 case WORD_MNEM_SUFFIX
:
5070 mask
.bitfield
.imm16
= 1;
5072 case BYTE_MNEM_SUFFIX
:
5073 mask
.bitfield
.imm8
= 1;
5078 allowed
= operand_type_and (mask
, allowed
);
5079 if (!operand_type_all_zero (&allowed
))
5080 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5087 /* Try to use the smallest displacement type too. */
5089 optimize_disp (void)
5093 for (op
= i
.operands
; --op
>= 0;)
5094 if (operand_type_check (i
.types
[op
], disp
))
5096 if (i
.op
[op
].disps
->X_op
== O_constant
)
5098 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5100 if (i
.types
[op
].bitfield
.disp16
5101 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5103 /* If this operand is at most 16 bits, convert
5104 to a signed 16 bit number and don't use 64bit
5106 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5107 i
.types
[op
].bitfield
.disp64
= 0;
5110 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5111 if (i
.types
[op
].bitfield
.disp32
5112 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5114 /* If this operand is at most 32 bits, convert
5115 to a signed 32 bit number and don't use 64bit
5117 op_disp
&= (((offsetT
) 2 << 31) - 1);
5118 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5119 i
.types
[op
].bitfield
.disp64
= 0;
5122 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5124 i
.types
[op
].bitfield
.disp8
= 0;
5125 i
.types
[op
].bitfield
.disp16
= 0;
5126 i
.types
[op
].bitfield
.disp32
= 0;
5127 i
.types
[op
].bitfield
.disp32s
= 0;
5128 i
.types
[op
].bitfield
.disp64
= 0;
5132 else if (flag_code
== CODE_64BIT
)
5134 if (fits_in_signed_long (op_disp
))
5136 i
.types
[op
].bitfield
.disp64
= 0;
5137 i
.types
[op
].bitfield
.disp32s
= 1;
5139 if (i
.prefix
[ADDR_PREFIX
]
5140 && fits_in_unsigned_long (op_disp
))
5141 i
.types
[op
].bitfield
.disp32
= 1;
5143 if ((i
.types
[op
].bitfield
.disp32
5144 || i
.types
[op
].bitfield
.disp32s
5145 || i
.types
[op
].bitfield
.disp16
)
5146 && fits_in_disp8 (op_disp
))
5147 i
.types
[op
].bitfield
.disp8
= 1;
5149 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5150 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5152 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5153 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5154 i
.types
[op
].bitfield
.disp8
= 0;
5155 i
.types
[op
].bitfield
.disp16
= 0;
5156 i
.types
[op
].bitfield
.disp32
= 0;
5157 i
.types
[op
].bitfield
.disp32s
= 0;
5158 i
.types
[op
].bitfield
.disp64
= 0;
5161 /* We only support 64bit displacement on constants. */
5162 i
.types
[op
].bitfield
.disp64
= 0;
5166 /* Return 1 if there is a match in broadcast bytes between operand
5167 GIVEN and instruction template T. */
5170 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5172 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5173 && i
.types
[given
].bitfield
.byte
)
5174 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5175 && i
.types
[given
].bitfield
.word
)
5176 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5177 && i
.types
[given
].bitfield
.dword
)
5178 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5179 && i
.types
[given
].bitfield
.qword
));
5182 /* Check if operands are valid for the instruction. */
5185 check_VecOperands (const insn_template
*t
)
5189 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5191 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5192 any one operand are implicity requiring AVX512VL support if the actual
5193 operand size is YMMword or XMMword. Since this function runs after
5194 template matching, there's no need to check for YMMword/XMMword in
5196 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5197 if (!cpu_flags_all_zero (&cpu
)
5198 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5199 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5201 for (op
= 0; op
< t
->operands
; ++op
)
5203 if (t
->operand_types
[op
].bitfield
.zmmword
5204 && (i
.types
[op
].bitfield
.ymmword
5205 || i
.types
[op
].bitfield
.xmmword
))
5207 i
.error
= unsupported
;
5213 /* Without VSIB byte, we can't have a vector register for index. */
5214 if (!t
->opcode_modifier
.vecsib
5216 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5217 || i
.index_reg
->reg_type
.bitfield
.ymmword
5218 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5220 i
.error
= unsupported_vector_index_register
;
5224 /* Check if default mask is allowed. */
5225 if (t
->opcode_modifier
.nodefmask
5226 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5228 i
.error
= no_default_mask
;
5232 /* For VSIB byte, we need a vector register for index, and all vector
5233 registers must be distinct. */
5234 if (t
->opcode_modifier
.vecsib
)
5237 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5238 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5239 || (t
->opcode_modifier
.vecsib
== VecSIB256
5240 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5241 || (t
->opcode_modifier
.vecsib
== VecSIB512
5242 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5244 i
.error
= invalid_vsib_address
;
5248 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5249 if (i
.reg_operands
== 2 && !i
.mask
)
5251 gas_assert (i
.types
[0].bitfield
.regsimd
);
5252 gas_assert (i
.types
[0].bitfield
.xmmword
5253 || i
.types
[0].bitfield
.ymmword
);
5254 gas_assert (i
.types
[2].bitfield
.regsimd
);
5255 gas_assert (i
.types
[2].bitfield
.xmmword
5256 || i
.types
[2].bitfield
.ymmword
);
5257 if (operand_check
== check_none
)
5259 if (register_number (i
.op
[0].regs
)
5260 != register_number (i
.index_reg
)
5261 && register_number (i
.op
[2].regs
)
5262 != register_number (i
.index_reg
)
5263 && register_number (i
.op
[0].regs
)
5264 != register_number (i
.op
[2].regs
))
5266 if (operand_check
== check_error
)
5268 i
.error
= invalid_vector_register_set
;
5271 as_warn (_("mask, index, and destination registers should be distinct"));
5273 else if (i
.reg_operands
== 1 && i
.mask
)
5275 if (i
.types
[1].bitfield
.regsimd
5276 && (i
.types
[1].bitfield
.xmmword
5277 || i
.types
[1].bitfield
.ymmword
5278 || i
.types
[1].bitfield
.zmmword
)
5279 && (register_number (i
.op
[1].regs
)
5280 == register_number (i
.index_reg
)))
5282 if (operand_check
== check_error
)
5284 i
.error
= invalid_vector_register_set
;
5287 if (operand_check
!= check_none
)
5288 as_warn (_("index and destination registers should be distinct"));
5293 /* Check if broadcast is supported by the instruction and is applied
5294 to the memory operand. */
5297 i386_operand_type type
, overlap
;
5299 /* Check if specified broadcast is supported in this instruction,
5300 and its broadcast bytes match the memory operand. */
5301 op
= i
.broadcast
->operand
;
5302 if (!t
->opcode_modifier
.broadcast
5303 || !(i
.flags
[op
] & Operand_Mem
)
5304 || (!i
.types
[op
].bitfield
.unspecified
5305 && !match_broadcast_size (t
, op
)))
5308 i
.error
= unsupported_broadcast
;
5312 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5313 * i
.broadcast
->type
);
5314 operand_type_set (&type
, 0);
5315 switch (i
.broadcast
->bytes
)
5318 type
.bitfield
.word
= 1;
5321 type
.bitfield
.dword
= 1;
5324 type
.bitfield
.qword
= 1;
5327 type
.bitfield
.xmmword
= 1;
5330 type
.bitfield
.ymmword
= 1;
5333 type
.bitfield
.zmmword
= 1;
5339 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5340 if (operand_type_all_zero (&overlap
))
5343 if (t
->opcode_modifier
.checkregsize
)
5347 type
.bitfield
.baseindex
= 1;
5348 for (j
= 0; j
< i
.operands
; ++j
)
5351 && !operand_type_register_match(i
.types
[j
],
5352 t
->operand_types
[j
],
5354 t
->operand_types
[op
]))
5359 /* If broadcast is supported in this instruction, we need to check if
5360 operand of one-element size isn't specified without broadcast. */
5361 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5363 /* Find memory operand. */
5364 for (op
= 0; op
< i
.operands
; op
++)
5365 if (operand_type_check (i
.types
[op
], anymem
))
5367 gas_assert (op
< i
.operands
);
5368 /* Check size of the memory operand. */
5369 if (match_broadcast_size (t
, op
))
5371 i
.error
= broadcast_needed
;
5376 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5378 /* Check if requested masking is supported. */
5381 switch (t
->opcode_modifier
.masking
)
5385 case MERGING_MASKING
:
5386 if (i
.mask
->zeroing
)
5389 i
.error
= unsupported_masking
;
5393 case DYNAMIC_MASKING
:
5394 /* Memory destinations allow only merging masking. */
5395 if (i
.mask
->zeroing
&& i
.mem_operands
)
5397 /* Find memory operand. */
5398 for (op
= 0; op
< i
.operands
; op
++)
5399 if (i
.flags
[op
] & Operand_Mem
)
5401 gas_assert (op
< i
.operands
);
5402 if (op
== i
.operands
- 1)
5404 i
.error
= unsupported_masking
;
5414 /* Check if masking is applied to dest operand. */
5415 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5417 i
.error
= mask_not_on_destination
;
5424 if ((i
.rounding
->type
!= saeonly
5425 && !t
->opcode_modifier
.staticrounding
)
5426 || (i
.rounding
->type
== saeonly
5427 && (t
->opcode_modifier
.staticrounding
5428 || !t
->opcode_modifier
.sae
)))
5430 i
.error
= unsupported_rc_sae
;
5433 /* If the instruction has several immediate operands and one of
5434 them is rounding, the rounding operand should be the last
5435 immediate operand. */
5436 if (i
.imm_operands
> 1
5437 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5439 i
.error
= rc_sae_operand_not_last_imm
;
5444 /* Check vector Disp8 operand. */
5445 if (t
->opcode_modifier
.disp8memshift
5446 && i
.disp_encoding
!= disp_encoding_32bit
)
5449 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5450 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5451 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5454 const i386_operand_type
*type
= NULL
;
5457 for (op
= 0; op
< i
.operands
; op
++)
5458 if (operand_type_check (i
.types
[op
], anymem
))
5460 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5461 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5462 else if (t
->operand_types
[op
].bitfield
.xmmword
5463 + t
->operand_types
[op
].bitfield
.ymmword
5464 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5465 type
= &t
->operand_types
[op
];
5466 else if (!i
.types
[op
].bitfield
.unspecified
)
5467 type
= &i
.types
[op
];
5469 else if (i
.types
[op
].bitfield
.regsimd
5470 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5472 if (i
.types
[op
].bitfield
.zmmword
)
5474 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5476 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5482 if (type
->bitfield
.zmmword
)
5484 else if (type
->bitfield
.ymmword
)
5486 else if (type
->bitfield
.xmmword
)
5490 /* For the check in fits_in_disp8(). */
5491 if (i
.memshift
== 0)
5495 for (op
= 0; op
< i
.operands
; op
++)
5496 if (operand_type_check (i
.types
[op
], disp
)
5497 && i
.op
[op
].disps
->X_op
== O_constant
)
5499 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5501 i
.types
[op
].bitfield
.disp8
= 1;
5504 i
.types
[op
].bitfield
.disp8
= 0;
5513 /* Check if operands are valid for the instruction. Update VEX
5517 VEX_check_operands (const insn_template
*t
)
5519 if (i
.vec_encoding
== vex_encoding_evex
)
5521 /* This instruction must be encoded with EVEX prefix. */
5522 if (!is_evex_encoding (t
))
5524 i
.error
= unsupported
;
5530 if (!t
->opcode_modifier
.vex
)
5532 /* This instruction template doesn't have VEX prefix. */
5533 if (i
.vec_encoding
!= vex_encoding_default
)
5535 i
.error
= unsupported
;
5541 /* Only check VEX_Imm4, which must be the first operand. */
5542 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5544 if (i
.op
[0].imms
->X_op
!= O_constant
5545 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5551 /* Turn off Imm8 so that update_imm won't complain. */
5552 i
.types
[0] = vec_imm4
;
5558 static const insn_template
*
5559 match_template (char mnem_suffix
)
5561 /* Points to template once we've found it. */
5562 const insn_template
*t
;
5563 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5564 i386_operand_type overlap4
;
5565 unsigned int found_reverse_match
;
5566 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5567 i386_operand_type operand_types
[MAX_OPERANDS
];
5568 int addr_prefix_disp
;
5570 unsigned int found_cpu_match
, size_match
;
5571 unsigned int check_register
;
5572 enum i386_error specific_error
= 0;
5574 #if MAX_OPERANDS != 5
5575 # error "MAX_OPERANDS must be 5."
5578 found_reverse_match
= 0;
5579 addr_prefix_disp
= -1;
5581 memset (&suffix_check
, 0, sizeof (suffix_check
));
5582 if (intel_syntax
&& i
.broadcast
)
5584 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5585 suffix_check
.no_bsuf
= 1;
5586 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5587 suffix_check
.no_wsuf
= 1;
5588 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5589 suffix_check
.no_ssuf
= 1;
5590 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5591 suffix_check
.no_lsuf
= 1;
5592 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5593 suffix_check
.no_qsuf
= 1;
5594 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5595 suffix_check
.no_ldsuf
= 1;
5597 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5600 switch (mnem_suffix
)
5602 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5603 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5604 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5605 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5606 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5610 /* Must have right number of operands. */
5611 i
.error
= number_of_operands_mismatch
;
5613 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5615 addr_prefix_disp
= -1;
5616 found_reverse_match
= 0;
5618 if (i
.operands
!= t
->operands
)
5621 /* Check processor support. */
5622 i
.error
= unsupported
;
5623 found_cpu_match
= (cpu_flags_match (t
)
5624 == CPU_FLAGS_PERFECT_MATCH
);
5625 if (!found_cpu_match
)
5628 /* Check AT&T mnemonic. */
5629 i
.error
= unsupported_with_intel_mnemonic
;
5630 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5633 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5634 i
.error
= unsupported_syntax
;
5635 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5636 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5637 || (intel64
&& t
->opcode_modifier
.amd64
)
5638 || (!intel64
&& t
->opcode_modifier
.intel64
))
5641 /* Check the suffix, except for some instructions in intel mode. */
5642 i
.error
= invalid_instruction_suffix
;
5643 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5644 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5645 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5646 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5647 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5648 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5649 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5651 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5652 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5653 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5654 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5655 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5656 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5657 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5660 size_match
= operand_size_match (t
);
5664 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5665 operand_types
[j
] = t
->operand_types
[j
];
5667 /* In general, don't allow 64-bit operands in 32-bit mode. */
5668 if (i
.suffix
== QWORD_MNEM_SUFFIX
5669 && flag_code
!= CODE_64BIT
5671 ? (!t
->opcode_modifier
.ignoresize
5672 && !t
->opcode_modifier
.broadcast
5673 && !intel_float_operand (t
->name
))
5674 : intel_float_operand (t
->name
) != 2)
5675 && ((!operand_types
[0].bitfield
.regmmx
5676 && !operand_types
[0].bitfield
.regsimd
)
5677 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5678 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5679 && (t
->base_opcode
!= 0x0fc7
5680 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5683 /* In general, don't allow 32-bit operands on pre-386. */
5684 else if (i
.suffix
== LONG_MNEM_SUFFIX
5685 && !cpu_arch_flags
.bitfield
.cpui386
5687 ? (!t
->opcode_modifier
.ignoresize
5688 && !intel_float_operand (t
->name
))
5689 : intel_float_operand (t
->name
) != 2)
5690 && ((!operand_types
[0].bitfield
.regmmx
5691 && !operand_types
[0].bitfield
.regsimd
)
5692 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5693 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5696 /* Do not verify operands when there are none. */
5700 /* We've found a match; break out of loop. */
5704 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5705 into Disp32/Disp16/Disp32 operand. */
5706 if (i
.prefix
[ADDR_PREFIX
] != 0)
5708 /* There should be only one Disp operand. */
5712 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5714 if (operand_types
[j
].bitfield
.disp16
)
5716 addr_prefix_disp
= j
;
5717 operand_types
[j
].bitfield
.disp32
= 1;
5718 operand_types
[j
].bitfield
.disp16
= 0;
5724 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5726 if (operand_types
[j
].bitfield
.disp32
)
5728 addr_prefix_disp
= j
;
5729 operand_types
[j
].bitfield
.disp32
= 0;
5730 operand_types
[j
].bitfield
.disp16
= 1;
5736 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5738 if (operand_types
[j
].bitfield
.disp64
)
5740 addr_prefix_disp
= j
;
5741 operand_types
[j
].bitfield
.disp64
= 0;
5742 operand_types
[j
].bitfield
.disp32
= 1;
5750 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5751 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5754 /* We check register size if needed. */
5755 if (t
->opcode_modifier
.checkregsize
)
5757 check_register
= (1 << t
->operands
) - 1;
5759 check_register
&= ~(1 << i
.broadcast
->operand
);
5764 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5765 switch (t
->operands
)
5768 if (!operand_type_match (overlap0
, i
.types
[0]))
5772 /* xchg %eax, %eax is a special case. It is an alias for nop
5773 only in 32bit mode and we can use opcode 0x90. In 64bit
5774 mode, we can't use 0x90 for xchg %eax, %eax since it should
5775 zero-extend %eax to %rax. */
5776 if (flag_code
== CODE_64BIT
5777 && t
->base_opcode
== 0x90
5778 && operand_type_equal (&i
.types
[0], &acc32
)
5779 && operand_type_equal (&i
.types
[1], &acc32
))
5781 /* xrelease mov %eax, <disp> is another special case. It must not
5782 match the accumulator-only encoding of mov. */
5783 if (flag_code
!= CODE_64BIT
5785 && t
->base_opcode
== 0xa0
5786 && i
.types
[0].bitfield
.acc
5787 && operand_type_check (i
.types
[1], anymem
))
5792 if (!(size_match
& MATCH_STRAIGHT
))
5794 /* Reverse direction of operands if swapping is possible in the first
5795 place (operands need to be symmetric) and
5796 - the load form is requested, and the template is a store form,
5797 - the store form is requested, and the template is a load form,
5798 - the non-default (swapped) form is requested. */
5799 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5800 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5801 && !operand_type_all_zero (&overlap1
))
5802 switch (i
.dir_encoding
)
5804 case dir_encoding_load
:
5805 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5806 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5810 case dir_encoding_store
:
5811 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5812 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5816 case dir_encoding_swap
:
5819 case dir_encoding_default
:
5822 /* If we want store form, we skip the current load. */
5823 if ((i
.dir_encoding
== dir_encoding_store
5824 || i
.dir_encoding
== dir_encoding_swap
)
5825 && i
.mem_operands
== 0
5826 && t
->opcode_modifier
.load
)
5831 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5832 if (!operand_type_match (overlap0
, i
.types
[0])
5833 || !operand_type_match (overlap1
, i
.types
[1])
5834 || ((check_register
& 3) == 3
5835 && !operand_type_register_match (i
.types
[0],
5840 /* Check if other direction is valid ... */
5841 if (!t
->opcode_modifier
.d
)
5845 if (!(size_match
& MATCH_REVERSE
))
5847 /* Try reversing direction of operands. */
5848 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5849 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5850 if (!operand_type_match (overlap0
, i
.types
[0])
5851 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5853 && !operand_type_register_match (i
.types
[0],
5854 operand_types
[i
.operands
- 1],
5855 i
.types
[i
.operands
- 1],
5858 /* Does not match either direction. */
5861 /* found_reverse_match holds which of D or FloatR
5863 if (!t
->opcode_modifier
.d
)
5864 found_reverse_match
= 0;
5865 else if (operand_types
[0].bitfield
.tbyte
)
5866 found_reverse_match
= Opcode_FloatD
;
5867 else if (operand_types
[0].bitfield
.xmmword
5868 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5869 || operand_types
[0].bitfield
.regmmx
5870 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5871 || is_any_vex_encoding(t
))
5872 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5873 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5875 found_reverse_match
= Opcode_D
;
5876 if (t
->opcode_modifier
.floatr
)
5877 found_reverse_match
|= Opcode_FloatR
;
5881 /* Found a forward 2 operand match here. */
5882 switch (t
->operands
)
5885 overlap4
= operand_type_and (i
.types
[4],
5889 overlap3
= operand_type_and (i
.types
[3],
5893 overlap2
= operand_type_and (i
.types
[2],
5898 switch (t
->operands
)
5901 if (!operand_type_match (overlap4
, i
.types
[4])
5902 || !operand_type_register_match (i
.types
[3],
5909 if (!operand_type_match (overlap3
, i
.types
[3])
5910 || ((check_register
& 0xa) == 0xa
5911 && !operand_type_register_match (i
.types
[1],
5915 || ((check_register
& 0xc) == 0xc
5916 && !operand_type_register_match (i
.types
[2],
5923 /* Here we make use of the fact that there are no
5924 reverse match 3 operand instructions. */
5925 if (!operand_type_match (overlap2
, i
.types
[2])
5926 || ((check_register
& 5) == 5
5927 && !operand_type_register_match (i
.types
[0],
5931 || ((check_register
& 6) == 6
5932 && !operand_type_register_match (i
.types
[1],
5940 /* Found either forward/reverse 2, 3 or 4 operand match here:
5941 slip through to break. */
5943 if (!found_cpu_match
)
5946 /* Check if vector and VEX operands are valid. */
5947 if (check_VecOperands (t
) || VEX_check_operands (t
))
5949 specific_error
= i
.error
;
5953 /* We've found a match; break out of loop. */
5957 if (t
== current_templates
->end
)
5959 /* We found no match. */
5960 const char *err_msg
;
5961 switch (specific_error
? specific_error
: i
.error
)
5965 case operand_size_mismatch
:
5966 err_msg
= _("operand size mismatch");
5968 case operand_type_mismatch
:
5969 err_msg
= _("operand type mismatch");
5971 case register_type_mismatch
:
5972 err_msg
= _("register type mismatch");
5974 case number_of_operands_mismatch
:
5975 err_msg
= _("number of operands mismatch");
5977 case invalid_instruction_suffix
:
5978 err_msg
= _("invalid instruction suffix");
5981 err_msg
= _("constant doesn't fit in 4 bits");
5983 case unsupported_with_intel_mnemonic
:
5984 err_msg
= _("unsupported with Intel mnemonic");
5986 case unsupported_syntax
:
5987 err_msg
= _("unsupported syntax");
5990 as_bad (_("unsupported instruction `%s'"),
5991 current_templates
->start
->name
);
5993 case invalid_vsib_address
:
5994 err_msg
= _("invalid VSIB address");
5996 case invalid_vector_register_set
:
5997 err_msg
= _("mask, index, and destination registers must be distinct");
5999 case unsupported_vector_index_register
:
6000 err_msg
= _("unsupported vector index register");
6002 case unsupported_broadcast
:
6003 err_msg
= _("unsupported broadcast");
6005 case broadcast_needed
:
6006 err_msg
= _("broadcast is needed for operand of such type");
6008 case unsupported_masking
:
6009 err_msg
= _("unsupported masking");
6011 case mask_not_on_destination
:
6012 err_msg
= _("mask not on destination operand");
6014 case no_default_mask
:
6015 err_msg
= _("default mask isn't allowed");
6017 case unsupported_rc_sae
:
6018 err_msg
= _("unsupported static rounding/sae");
6020 case rc_sae_operand_not_last_imm
:
6022 err_msg
= _("RC/SAE operand must precede immediate operands");
6024 err_msg
= _("RC/SAE operand must follow immediate operands");
6026 case invalid_register_operand
:
6027 err_msg
= _("invalid register operand");
6030 as_bad (_("%s for `%s'"), err_msg
,
6031 current_templates
->start
->name
);
6035 if (!quiet_warnings
)
6038 && (i
.types
[0].bitfield
.jumpabsolute
6039 != operand_types
[0].bitfield
.jumpabsolute
))
6041 as_warn (_("indirect %s without `*'"), t
->name
);
6044 if (t
->opcode_modifier
.isprefix
6045 && t
->opcode_modifier
.ignoresize
)
6047 /* Warn them that a data or address size prefix doesn't
6048 affect assembly of the next line of code. */
6049 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6053 /* Copy the template we found. */
6056 if (addr_prefix_disp
!= -1)
6057 i
.tm
.operand_types
[addr_prefix_disp
]
6058 = operand_types
[addr_prefix_disp
];
6060 if (found_reverse_match
)
6062 /* If we found a reverse match we must alter the opcode
6063 direction bit. found_reverse_match holds bits to change
6064 (different for int & float insns). */
6066 i
.tm
.base_opcode
^= found_reverse_match
;
6068 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6069 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6078 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6079 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6081 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6083 as_bad (_("`%s' operand %d must use `%ses' segment"),
6089 /* There's only ever one segment override allowed per instruction.
6090 This instruction possibly has a legal segment override on the
6091 second operand, so copy the segment to where non-string
6092 instructions store it, allowing common code. */
6093 i
.seg
[0] = i
.seg
[1];
6095 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6097 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6099 as_bad (_("`%s' operand %d must use `%ses' segment"),
6110 process_suffix (void)
6112 /* If matched instruction specifies an explicit instruction mnemonic
6114 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6115 i
.suffix
= WORD_MNEM_SUFFIX
;
6116 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6117 i
.suffix
= LONG_MNEM_SUFFIX
;
6118 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6119 i
.suffix
= QWORD_MNEM_SUFFIX
;
6120 else if (i
.reg_operands
)
6122 /* If there's no instruction mnemonic suffix we try to invent one
6123 based on register operands. */
6126 /* We take i.suffix from the last register operand specified,
6127 Destination register type is more significant than source
6128 register type. crc32 in SSE4.2 prefers source register
6130 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6132 if (i
.types
[0].bitfield
.byte
)
6133 i
.suffix
= BYTE_MNEM_SUFFIX
;
6134 else if (i
.types
[0].bitfield
.word
)
6135 i
.suffix
= WORD_MNEM_SUFFIX
;
6136 else if (i
.types
[0].bitfield
.dword
)
6137 i
.suffix
= LONG_MNEM_SUFFIX
;
6138 else if (i
.types
[0].bitfield
.qword
)
6139 i
.suffix
= QWORD_MNEM_SUFFIX
;
6146 if (i
.tm
.base_opcode
== 0xf20f38f0)
6148 /* We have to know the operand size for crc32. */
6149 as_bad (_("ambiguous memory operand size for `%s`"),
6154 for (op
= i
.operands
; --op
>= 0;)
6155 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6156 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6158 if (!i
.types
[op
].bitfield
.reg
)
6160 if (i
.types
[op
].bitfield
.byte
)
6161 i
.suffix
= BYTE_MNEM_SUFFIX
;
6162 else if (i
.types
[op
].bitfield
.word
)
6163 i
.suffix
= WORD_MNEM_SUFFIX
;
6164 else if (i
.types
[op
].bitfield
.dword
)
6165 i
.suffix
= LONG_MNEM_SUFFIX
;
6166 else if (i
.types
[op
].bitfield
.qword
)
6167 i
.suffix
= QWORD_MNEM_SUFFIX
;
6174 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6177 && i
.tm
.opcode_modifier
.ignoresize
6178 && i
.tm
.opcode_modifier
.no_bsuf
)
6180 else if (!check_byte_reg ())
6183 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6186 && i
.tm
.opcode_modifier
.ignoresize
6187 && i
.tm
.opcode_modifier
.no_lsuf
6188 && !i
.tm
.opcode_modifier
.todword
6189 && !i
.tm
.opcode_modifier
.toqword
)
6191 else if (!check_long_reg ())
6194 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6197 && i
.tm
.opcode_modifier
.ignoresize
6198 && i
.tm
.opcode_modifier
.no_qsuf
6199 && !i
.tm
.opcode_modifier
.todword
6200 && !i
.tm
.opcode_modifier
.toqword
)
6202 else if (!check_qword_reg ())
6205 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6208 && i
.tm
.opcode_modifier
.ignoresize
6209 && i
.tm
.opcode_modifier
.no_wsuf
)
6211 else if (!check_word_reg ())
6214 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6215 /* Do nothing if the instruction is going to ignore the prefix. */
6220 else if (i
.tm
.opcode_modifier
.defaultsize
6222 /* exclude fldenv/frstor/fsave/fstenv */
6223 && i
.tm
.opcode_modifier
.no_ssuf
)
6225 i
.suffix
= stackop_size
;
6227 else if (intel_syntax
6229 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6230 || i
.tm
.opcode_modifier
.jumpbyte
6231 || i
.tm
.opcode_modifier
.jumpintersegment
6232 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6233 && i
.tm
.extension_opcode
<= 3)))
6238 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6240 i
.suffix
= QWORD_MNEM_SUFFIX
;
6245 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6246 i
.suffix
= LONG_MNEM_SUFFIX
;
6249 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6250 i
.suffix
= WORD_MNEM_SUFFIX
;
6259 if (i
.tm
.opcode_modifier
.w
)
6261 as_bad (_("no instruction mnemonic suffix given and "
6262 "no register operands; can't size instruction"));
6268 unsigned int suffixes
;
6270 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6271 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6273 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6275 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6277 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6279 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6282 /* There are more than suffix matches. */
6283 if (i
.tm
.opcode_modifier
.w
6284 || ((suffixes
& (suffixes
- 1))
6285 && !i
.tm
.opcode_modifier
.defaultsize
6286 && !i
.tm
.opcode_modifier
.ignoresize
))
6288 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6294 /* Change the opcode based on the operand size given by i.suffix. */
6297 /* Size floating point instruction. */
6298 case LONG_MNEM_SUFFIX
:
6299 if (i
.tm
.opcode_modifier
.floatmf
)
6301 i
.tm
.base_opcode
^= 4;
6305 case WORD_MNEM_SUFFIX
:
6306 case QWORD_MNEM_SUFFIX
:
6307 /* It's not a byte, select word/dword operation. */
6308 if (i
.tm
.opcode_modifier
.w
)
6310 if (i
.tm
.opcode_modifier
.shortform
)
6311 i
.tm
.base_opcode
|= 8;
6313 i
.tm
.base_opcode
|= 1;
6316 case SHORT_MNEM_SUFFIX
:
6317 /* Now select between word & dword operations via the operand
6318 size prefix, except for instructions that will ignore this
6320 if (i
.reg_operands
> 0
6321 && i
.types
[0].bitfield
.reg
6322 && i
.tm
.opcode_modifier
.addrprefixopreg
6323 && (i
.tm
.opcode_modifier
.immext
6324 || i
.operands
== 1))
6326 /* The address size override prefix changes the size of the
6328 if ((flag_code
== CODE_32BIT
6329 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6330 || (flag_code
!= CODE_32BIT
6331 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6332 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6335 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6336 && !i
.tm
.opcode_modifier
.ignoresize
6337 && !i
.tm
.opcode_modifier
.floatmf
6338 && !i
.tm
.opcode_modifier
.vex
6339 && !i
.tm
.opcode_modifier
.vexopcode
6340 && !is_evex_encoding (&i
.tm
)
6341 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6342 || (flag_code
== CODE_64BIT
6343 && i
.tm
.opcode_modifier
.jumpbyte
)))
6345 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6347 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6348 prefix
= ADDR_PREFIX_OPCODE
;
6350 if (!add_prefix (prefix
))
6354 /* Set mode64 for an operand. */
6355 if (i
.suffix
== QWORD_MNEM_SUFFIX
6356 && flag_code
== CODE_64BIT
6357 && !i
.tm
.opcode_modifier
.norex64
6358 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6360 && ! (i
.operands
== 2
6361 && i
.tm
.base_opcode
== 0x90
6362 && i
.tm
.extension_opcode
== None
6363 && operand_type_equal (&i
.types
[0], &acc64
)
6364 && operand_type_equal (&i
.types
[1], &acc64
)))
6370 if (i
.reg_operands
!= 0
6372 && i
.tm
.opcode_modifier
.addrprefixopreg
6373 && !i
.tm
.opcode_modifier
.immext
)
6375 /* Check invalid register operand when the address size override
6376 prefix changes the size of register operands. */
6378 enum { need_word
, need_dword
, need_qword
} need
;
6380 if (flag_code
== CODE_32BIT
)
6381 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6384 if (i
.prefix
[ADDR_PREFIX
])
6387 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6390 for (op
= 0; op
< i
.operands
; op
++)
6391 if (i
.types
[op
].bitfield
.reg
6392 && ((need
== need_word
6393 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6394 || (need
== need_dword
6395 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6396 || (need
== need_qword
6397 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6399 as_bad (_("invalid register operand size for `%s'"),
6409 check_byte_reg (void)
6413 for (op
= i
.operands
; --op
>= 0;)
6415 /* Skip non-register operands. */
6416 if (!i
.types
[op
].bitfield
.reg
)
6419 /* If this is an eight bit register, it's OK. If it's the 16 or
6420 32 bit version of an eight bit register, we will just use the
6421 low portion, and that's OK too. */
6422 if (i
.types
[op
].bitfield
.byte
)
6425 /* I/O port address operands are OK too. */
6426 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6429 /* crc32 doesn't generate this warning. */
6430 if (i
.tm
.base_opcode
== 0xf20f38f0)
6433 if ((i
.types
[op
].bitfield
.word
6434 || i
.types
[op
].bitfield
.dword
6435 || i
.types
[op
].bitfield
.qword
)
6436 && i
.op
[op
].regs
->reg_num
< 4
6437 /* Prohibit these changes in 64bit mode, since the lowering
6438 would be more complicated. */
6439 && flag_code
!= CODE_64BIT
)
6441 #if REGISTER_WARNINGS
6442 if (!quiet_warnings
)
6443 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6445 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6446 ? REGNAM_AL
- REGNAM_AX
6447 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6449 i
.op
[op
].regs
->reg_name
,
6454 /* Any other register is bad. */
6455 if (i
.types
[op
].bitfield
.reg
6456 || i
.types
[op
].bitfield
.regmmx
6457 || i
.types
[op
].bitfield
.regsimd
6458 || i
.types
[op
].bitfield
.sreg2
6459 || i
.types
[op
].bitfield
.sreg3
6460 || i
.types
[op
].bitfield
.control
6461 || i
.types
[op
].bitfield
.debug
6462 || i
.types
[op
].bitfield
.test
)
6464 as_bad (_("`%s%s' not allowed with `%s%c'"),
6466 i
.op
[op
].regs
->reg_name
,
6476 check_long_reg (void)
6480 for (op
= i
.operands
; --op
>= 0;)
6481 /* Skip non-register operands. */
6482 if (!i
.types
[op
].bitfield
.reg
)
6484 /* Reject eight bit registers, except where the template requires
6485 them. (eg. movzb) */
6486 else if (i
.types
[op
].bitfield
.byte
6487 && (i
.tm
.operand_types
[op
].bitfield
.reg
6488 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6489 && (i
.tm
.operand_types
[op
].bitfield
.word
6490 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6492 as_bad (_("`%s%s' not allowed with `%s%c'"),
6494 i
.op
[op
].regs
->reg_name
,
6499 /* Warn if the e prefix on a general reg is missing. */
6500 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6501 && i
.types
[op
].bitfield
.word
6502 && (i
.tm
.operand_types
[op
].bitfield
.reg
6503 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6504 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6506 /* Prohibit these changes in the 64bit mode, since the
6507 lowering is more complicated. */
6508 if (flag_code
== CODE_64BIT
)
6510 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6511 register_prefix
, i
.op
[op
].regs
->reg_name
,
6515 #if REGISTER_WARNINGS
6516 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6518 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6519 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6522 /* Warn if the r prefix on a general reg is present. */
6523 else if (i
.types
[op
].bitfield
.qword
6524 && (i
.tm
.operand_types
[op
].bitfield
.reg
6525 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6526 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6529 && i
.tm
.opcode_modifier
.toqword
6530 && !i
.types
[0].bitfield
.regsimd
)
6532 /* Convert to QWORD. We want REX byte. */
6533 i
.suffix
= QWORD_MNEM_SUFFIX
;
6537 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6538 register_prefix
, i
.op
[op
].regs
->reg_name
,
6547 check_qword_reg (void)
6551 for (op
= i
.operands
; --op
>= 0; )
6552 /* Skip non-register operands. */
6553 if (!i
.types
[op
].bitfield
.reg
)
6555 /* Reject eight bit registers, except where the template requires
6556 them. (eg. movzb) */
6557 else if (i
.types
[op
].bitfield
.byte
6558 && (i
.tm
.operand_types
[op
].bitfield
.reg
6559 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6560 && (i
.tm
.operand_types
[op
].bitfield
.word
6561 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6563 as_bad (_("`%s%s' not allowed with `%s%c'"),
6565 i
.op
[op
].regs
->reg_name
,
6570 /* Warn if the r prefix on a general reg is missing. */
6571 else if ((i
.types
[op
].bitfield
.word
6572 || i
.types
[op
].bitfield
.dword
)
6573 && (i
.tm
.operand_types
[op
].bitfield
.reg
6574 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6575 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6577 /* Prohibit these changes in the 64bit mode, since the
6578 lowering is more complicated. */
6580 && i
.tm
.opcode_modifier
.todword
6581 && !i
.types
[0].bitfield
.regsimd
)
6583 /* Convert to DWORD. We don't want REX byte. */
6584 i
.suffix
= LONG_MNEM_SUFFIX
;
6588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6589 register_prefix
, i
.op
[op
].regs
->reg_name
,
6598 check_word_reg (void)
6601 for (op
= i
.operands
; --op
>= 0;)
6602 /* Skip non-register operands. */
6603 if (!i
.types
[op
].bitfield
.reg
)
6605 /* Reject eight bit registers, except where the template requires
6606 them. (eg. movzb) */
6607 else if (i
.types
[op
].bitfield
.byte
6608 && (i
.tm
.operand_types
[op
].bitfield
.reg
6609 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6610 && (i
.tm
.operand_types
[op
].bitfield
.word
6611 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6613 as_bad (_("`%s%s' not allowed with `%s%c'"),
6615 i
.op
[op
].regs
->reg_name
,
6620 /* Warn if the e or r prefix on a general reg is present. */
6621 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6622 && (i
.types
[op
].bitfield
.dword
6623 || i
.types
[op
].bitfield
.qword
)
6624 && (i
.tm
.operand_types
[op
].bitfield
.reg
6625 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6626 && i
.tm
.operand_types
[op
].bitfield
.word
)
6628 /* Prohibit these changes in the 64bit mode, since the
6629 lowering is more complicated. */
6630 if (flag_code
== CODE_64BIT
)
6632 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6633 register_prefix
, i
.op
[op
].regs
->reg_name
,
6637 #if REGISTER_WARNINGS
6638 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6640 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6641 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6648 update_imm (unsigned int j
)
6650 i386_operand_type overlap
= i
.types
[j
];
6651 if ((overlap
.bitfield
.imm8
6652 || overlap
.bitfield
.imm8s
6653 || overlap
.bitfield
.imm16
6654 || overlap
.bitfield
.imm32
6655 || overlap
.bitfield
.imm32s
6656 || overlap
.bitfield
.imm64
)
6657 && !operand_type_equal (&overlap
, &imm8
)
6658 && !operand_type_equal (&overlap
, &imm8s
)
6659 && !operand_type_equal (&overlap
, &imm16
)
6660 && !operand_type_equal (&overlap
, &imm32
)
6661 && !operand_type_equal (&overlap
, &imm32s
)
6662 && !operand_type_equal (&overlap
, &imm64
))
6666 i386_operand_type temp
;
6668 operand_type_set (&temp
, 0);
6669 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6671 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6672 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6674 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6675 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6676 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6678 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6679 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6682 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6685 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6686 || operand_type_equal (&overlap
, &imm16_32
)
6687 || operand_type_equal (&overlap
, &imm16_32s
))
6689 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6694 if (!operand_type_equal (&overlap
, &imm8
)
6695 && !operand_type_equal (&overlap
, &imm8s
)
6696 && !operand_type_equal (&overlap
, &imm16
)
6697 && !operand_type_equal (&overlap
, &imm32
)
6698 && !operand_type_equal (&overlap
, &imm32s
)
6699 && !operand_type_equal (&overlap
, &imm64
))
6701 as_bad (_("no instruction mnemonic suffix given; "
6702 "can't determine immediate size"));
6706 i
.types
[j
] = overlap
;
6716 /* Update the first 2 immediate operands. */
6717 n
= i
.operands
> 2 ? 2 : i
.operands
;
6720 for (j
= 0; j
< n
; j
++)
6721 if (update_imm (j
) == 0)
6724 /* The 3rd operand can't be immediate operand. */
6725 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6732 process_operands (void)
6734 /* Default segment register this instruction will use for memory
6735 accesses. 0 means unknown. This is only for optimizing out
6736 unnecessary segment overrides. */
6737 const seg_entry
*default_seg
= 0;
6739 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6741 unsigned int dupl
= i
.operands
;
6742 unsigned int dest
= dupl
- 1;
6745 /* The destination must be an xmm register. */
6746 gas_assert (i
.reg_operands
6747 && MAX_OPERANDS
> dupl
6748 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6750 if (i
.tm
.operand_types
[0].bitfield
.acc
6751 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6753 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6755 /* Keep xmm0 for instructions with VEX prefix and 3
6757 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6758 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6763 /* We remove the first xmm0 and keep the number of
6764 operands unchanged, which in fact duplicates the
6766 for (j
= 1; j
< i
.operands
; j
++)
6768 i
.op
[j
- 1] = i
.op
[j
];
6769 i
.types
[j
- 1] = i
.types
[j
];
6770 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6774 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6776 gas_assert ((MAX_OPERANDS
- 1) > dupl
6777 && (i
.tm
.opcode_modifier
.vexsources
6780 /* Add the implicit xmm0 for instructions with VEX prefix
6782 for (j
= i
.operands
; j
> 0; j
--)
6784 i
.op
[j
] = i
.op
[j
- 1];
6785 i
.types
[j
] = i
.types
[j
- 1];
6786 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6789 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6790 i
.types
[0] = regxmm
;
6791 i
.tm
.operand_types
[0] = regxmm
;
6794 i
.reg_operands
+= 2;
6799 i
.op
[dupl
] = i
.op
[dest
];
6800 i
.types
[dupl
] = i
.types
[dest
];
6801 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6810 i
.op
[dupl
] = i
.op
[dest
];
6811 i
.types
[dupl
] = i
.types
[dest
];
6812 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6815 if (i
.tm
.opcode_modifier
.immext
)
6818 else if (i
.tm
.operand_types
[0].bitfield
.acc
6819 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6823 for (j
= 1; j
< i
.operands
; j
++)
6825 i
.op
[j
- 1] = i
.op
[j
];
6826 i
.types
[j
- 1] = i
.types
[j
];
6828 /* We need to adjust fields in i.tm since they are used by
6829 build_modrm_byte. */
6830 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6837 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6839 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6841 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6842 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6843 regnum
= register_number (i
.op
[1].regs
);
6844 first_reg_in_group
= regnum
& ~3;
6845 last_reg_in_group
= first_reg_in_group
+ 3;
6846 if (regnum
!= first_reg_in_group
)
6847 as_warn (_("source register `%s%s' implicitly denotes"
6848 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6849 register_prefix
, i
.op
[1].regs
->reg_name
,
6850 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6851 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6854 else if (i
.tm
.opcode_modifier
.regkludge
)
6856 /* The imul $imm, %reg instruction is converted into
6857 imul $imm, %reg, %reg, and the clr %reg instruction
6858 is converted into xor %reg, %reg. */
6860 unsigned int first_reg_op
;
6862 if (operand_type_check (i
.types
[0], reg
))
6866 /* Pretend we saw the extra register operand. */
6867 gas_assert (i
.reg_operands
== 1
6868 && i
.op
[first_reg_op
+ 1].regs
== 0);
6869 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6870 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6875 if (i
.tm
.opcode_modifier
.shortform
)
6877 if (i
.types
[0].bitfield
.sreg2
6878 || i
.types
[0].bitfield
.sreg3
)
6880 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6881 && i
.op
[0].regs
->reg_num
== 1)
6883 as_bad (_("you can't `pop %scs'"), register_prefix
);
6886 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6887 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6892 /* The register or float register operand is in operand
6896 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6897 || operand_type_check (i
.types
[0], reg
))
6901 /* Register goes in low 3 bits of opcode. */
6902 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6903 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6905 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6907 /* Warn about some common errors, but press on regardless.
6908 The first case can be generated by gcc (<= 2.8.1). */
6909 if (i
.operands
== 2)
6911 /* Reversed arguments on faddp, fsubp, etc. */
6912 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6913 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6914 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6918 /* Extraneous `l' suffix on fp insn. */
6919 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6920 register_prefix
, i
.op
[0].regs
->reg_name
);
6925 else if (i
.tm
.opcode_modifier
.modrm
)
6927 /* The opcode is completed (modulo i.tm.extension_opcode which
6928 must be put into the modrm byte). Now, we make the modrm and
6929 index base bytes based on all the info we've collected. */
6931 default_seg
= build_modrm_byte ();
6933 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6937 else if (i
.tm
.opcode_modifier
.isstring
)
6939 /* For the string instructions that allow a segment override
6940 on one of their operands, the default segment is ds. */
6944 if (i
.tm
.base_opcode
== 0x8d /* lea */
6947 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6949 /* If a segment was explicitly specified, and the specified segment
6950 is not the default, use an opcode prefix to select it. If we
6951 never figured out what the default segment is, then default_seg
6952 will be zero at this point, and the specified segment prefix will
6954 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6956 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6962 static const seg_entry
*
6963 build_modrm_byte (void)
6965 const seg_entry
*default_seg
= 0;
6966 unsigned int source
, dest
;
6969 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6972 unsigned int nds
, reg_slot
;
6975 dest
= i
.operands
- 1;
6978 /* There are 2 kinds of instructions:
6979 1. 5 operands: 4 register operands or 3 register operands
6980 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6981 VexW0 or VexW1. The destination must be either XMM, YMM or
6983 2. 4 operands: 4 register operands or 3 register operands
6984 plus 1 memory operand, with VexXDS. */
6985 gas_assert ((i
.reg_operands
== 4
6986 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6987 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6988 && i
.tm
.opcode_modifier
.vexw
6989 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6991 /* If VexW1 is set, the first non-immediate operand is the source and
6992 the second non-immediate one is encoded in the immediate operand. */
6993 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6995 source
= i
.imm_operands
;
6996 reg_slot
= i
.imm_operands
+ 1;
7000 source
= i
.imm_operands
+ 1;
7001 reg_slot
= i
.imm_operands
;
7004 if (i
.imm_operands
== 0)
7006 /* When there is no immediate operand, generate an 8bit
7007 immediate operand to encode the first operand. */
7008 exp
= &im_expressions
[i
.imm_operands
++];
7009 i
.op
[i
.operands
].imms
= exp
;
7010 i
.types
[i
.operands
] = imm8
;
7013 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7014 exp
->X_op
= O_constant
;
7015 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7016 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7020 unsigned int imm_slot
;
7022 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7024 if (i
.tm
.opcode_modifier
.immext
)
7026 /* When ImmExt is set, the immediate byte is the last
7028 imm_slot
= i
.operands
- 1;
7036 /* Turn on Imm8 so that output_imm will generate it. */
7037 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7040 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7041 i
.op
[imm_slot
].imms
->X_add_number
7042 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7043 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7046 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7047 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7052 /* i.reg_operands MUST be the number of real register operands;
7053 implicit registers do not count. If there are 3 register
7054 operands, it must be a instruction with VexNDS. For a
7055 instruction with VexNDD, the destination register is encoded
7056 in VEX prefix. If there are 4 register operands, it must be
7057 a instruction with VEX prefix and 3 sources. */
7058 if (i
.mem_operands
== 0
7059 && ((i
.reg_operands
== 2
7060 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7061 || (i
.reg_operands
== 3
7062 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7063 || (i
.reg_operands
== 4 && vex_3_sources
)))
7071 /* When there are 3 operands, one of them may be immediate,
7072 which may be the first or the last operand. Otherwise,
7073 the first operand must be shift count register (cl) or it
7074 is an instruction with VexNDS. */
7075 gas_assert (i
.imm_operands
== 1
7076 || (i
.imm_operands
== 0
7077 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7078 || i
.types
[0].bitfield
.shiftcount
)));
7079 if (operand_type_check (i
.types
[0], imm
)
7080 || i
.types
[0].bitfield
.shiftcount
)
7086 /* When there are 4 operands, the first two must be 8bit
7087 immediate operands. The source operand will be the 3rd
7090 For instructions with VexNDS, if the first operand
7091 an imm8, the source operand is the 2nd one. If the last
7092 operand is imm8, the source operand is the first one. */
7093 gas_assert ((i
.imm_operands
== 2
7094 && i
.types
[0].bitfield
.imm8
7095 && i
.types
[1].bitfield
.imm8
)
7096 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7097 && i
.imm_operands
== 1
7098 && (i
.types
[0].bitfield
.imm8
7099 || i
.types
[i
.operands
- 1].bitfield
.imm8
7101 if (i
.imm_operands
== 2)
7105 if (i
.types
[0].bitfield
.imm8
)
7112 if (is_evex_encoding (&i
.tm
))
7114 /* For EVEX instructions, when there are 5 operands, the
7115 first one must be immediate operand. If the second one
7116 is immediate operand, the source operand is the 3th
7117 one. If the last one is immediate operand, the source
7118 operand is the 2nd one. */
7119 gas_assert (i
.imm_operands
== 2
7120 && i
.tm
.opcode_modifier
.sae
7121 && operand_type_check (i
.types
[0], imm
));
7122 if (operand_type_check (i
.types
[1], imm
))
7124 else if (operand_type_check (i
.types
[4], imm
))
7138 /* RC/SAE operand could be between DEST and SRC. That happens
7139 when one operand is GPR and the other one is XMM/YMM/ZMM
7141 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7144 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7146 /* For instructions with VexNDS, the register-only source
7147 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7148 register. It is encoded in VEX prefix. We need to
7149 clear RegMem bit before calling operand_type_equal. */
7151 i386_operand_type op
;
7154 /* Check register-only source operand when two source
7155 operands are swapped. */
7156 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7157 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7165 op
= i
.tm
.operand_types
[vvvv
];
7166 op
.bitfield
.regmem
= 0;
7167 if ((dest
+ 1) >= i
.operands
7168 || ((!op
.bitfield
.reg
7169 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7170 && !op
.bitfield
.regsimd
7171 && !operand_type_equal (&op
, ®mask
)))
7173 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7179 /* One of the register operands will be encoded in the i.tm.reg
7180 field, the other in the combined i.tm.mode and i.tm.regmem
7181 fields. If no form of this instruction supports a memory
7182 destination operand, then we assume the source operand may
7183 sometimes be a memory operand and so we need to store the
7184 destination in the i.rm.reg field. */
7185 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7186 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7188 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7189 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7190 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7191 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7192 i
.has_regmmx
= TRUE
;
7193 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7194 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7196 if (i
.types
[dest
].bitfield
.zmmword
7197 || i
.types
[source
].bitfield
.zmmword
)
7198 i
.has_regzmm
= TRUE
;
7199 else if (i
.types
[dest
].bitfield
.ymmword
7200 || i
.types
[source
].bitfield
.ymmword
)
7201 i
.has_regymm
= TRUE
;
7203 i
.has_regxmm
= TRUE
;
7205 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7207 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7209 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7211 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7216 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7217 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7218 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7220 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7222 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7224 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7227 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7229 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7232 add_prefix (LOCK_PREFIX_OPCODE
);
7236 { /* If it's not 2 reg operands... */
7241 unsigned int fake_zero_displacement
= 0;
7244 for (op
= 0; op
< i
.operands
; op
++)
7245 if (operand_type_check (i
.types
[op
], anymem
))
7247 gas_assert (op
< i
.operands
);
7249 if (i
.tm
.opcode_modifier
.vecsib
)
7251 if (i
.index_reg
->reg_num
== RegIZ
)
7254 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7257 i
.sib
.base
= NO_BASE_REGISTER
;
7258 i
.sib
.scale
= i
.log2_scale_factor
;
7259 i
.types
[op
].bitfield
.disp8
= 0;
7260 i
.types
[op
].bitfield
.disp16
= 0;
7261 i
.types
[op
].bitfield
.disp64
= 0;
7262 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7264 /* Must be 32 bit */
7265 i
.types
[op
].bitfield
.disp32
= 1;
7266 i
.types
[op
].bitfield
.disp32s
= 0;
7270 i
.types
[op
].bitfield
.disp32
= 0;
7271 i
.types
[op
].bitfield
.disp32s
= 1;
7274 i
.sib
.index
= i
.index_reg
->reg_num
;
7275 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7277 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7283 if (i
.base_reg
== 0)
7286 if (!i
.disp_operands
)
7287 fake_zero_displacement
= 1;
7288 if (i
.index_reg
== 0)
7290 i386_operand_type newdisp
;
7292 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7293 /* Operand is just <disp> */
7294 if (flag_code
== CODE_64BIT
)
7296 /* 64bit mode overwrites the 32bit absolute
7297 addressing by RIP relative addressing and
7298 absolute addressing is encoded by one of the
7299 redundant SIB forms. */
7300 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7301 i
.sib
.base
= NO_BASE_REGISTER
;
7302 i
.sib
.index
= NO_INDEX_REGISTER
;
7303 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7305 else if ((flag_code
== CODE_16BIT
)
7306 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7308 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7313 i
.rm
.regmem
= NO_BASE_REGISTER
;
7316 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7317 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7319 else if (!i
.tm
.opcode_modifier
.vecsib
)
7321 /* !i.base_reg && i.index_reg */
7322 if (i
.index_reg
->reg_num
== RegIZ
)
7323 i
.sib
.index
= NO_INDEX_REGISTER
;
7325 i
.sib
.index
= i
.index_reg
->reg_num
;
7326 i
.sib
.base
= NO_BASE_REGISTER
;
7327 i
.sib
.scale
= i
.log2_scale_factor
;
7328 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7329 i
.types
[op
].bitfield
.disp8
= 0;
7330 i
.types
[op
].bitfield
.disp16
= 0;
7331 i
.types
[op
].bitfield
.disp64
= 0;
7332 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7334 /* Must be 32 bit */
7335 i
.types
[op
].bitfield
.disp32
= 1;
7336 i
.types
[op
].bitfield
.disp32s
= 0;
7340 i
.types
[op
].bitfield
.disp32
= 0;
7341 i
.types
[op
].bitfield
.disp32s
= 1;
7343 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7347 /* RIP addressing for 64bit mode. */
7348 else if (i
.base_reg
->reg_num
== RegIP
)
7350 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7351 i
.rm
.regmem
= NO_BASE_REGISTER
;
7352 i
.types
[op
].bitfield
.disp8
= 0;
7353 i
.types
[op
].bitfield
.disp16
= 0;
7354 i
.types
[op
].bitfield
.disp32
= 0;
7355 i
.types
[op
].bitfield
.disp32s
= 1;
7356 i
.types
[op
].bitfield
.disp64
= 0;
7357 i
.flags
[op
] |= Operand_PCrel
;
7358 if (! i
.disp_operands
)
7359 fake_zero_displacement
= 1;
7361 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7363 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7364 switch (i
.base_reg
->reg_num
)
7367 if (i
.index_reg
== 0)
7369 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7370 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7374 if (i
.index_reg
== 0)
7377 if (operand_type_check (i
.types
[op
], disp
) == 0)
7379 /* fake (%bp) into 0(%bp) */
7380 i
.types
[op
].bitfield
.disp8
= 1;
7381 fake_zero_displacement
= 1;
7384 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7385 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7387 default: /* (%si) -> 4 or (%di) -> 5 */
7388 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7390 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7392 else /* i.base_reg and 32/64 bit mode */
7394 if (flag_code
== CODE_64BIT
7395 && operand_type_check (i
.types
[op
], disp
))
7397 i
.types
[op
].bitfield
.disp16
= 0;
7398 i
.types
[op
].bitfield
.disp64
= 0;
7399 if (i
.prefix
[ADDR_PREFIX
] == 0)
7401 i
.types
[op
].bitfield
.disp32
= 0;
7402 i
.types
[op
].bitfield
.disp32s
= 1;
7406 i
.types
[op
].bitfield
.disp32
= 1;
7407 i
.types
[op
].bitfield
.disp32s
= 0;
7411 if (!i
.tm
.opcode_modifier
.vecsib
)
7412 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7413 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7415 i
.sib
.base
= i
.base_reg
->reg_num
;
7416 /* x86-64 ignores REX prefix bit here to avoid decoder
7418 if (!(i
.base_reg
->reg_flags
& RegRex
)
7419 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7420 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7422 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7424 fake_zero_displacement
= 1;
7425 i
.types
[op
].bitfield
.disp8
= 1;
7427 i
.sib
.scale
= i
.log2_scale_factor
;
7428 if (i
.index_reg
== 0)
7430 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7431 /* <disp>(%esp) becomes two byte modrm with no index
7432 register. We've already stored the code for esp
7433 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7434 Any base register besides %esp will not use the
7435 extra modrm byte. */
7436 i
.sib
.index
= NO_INDEX_REGISTER
;
7438 else if (!i
.tm
.opcode_modifier
.vecsib
)
7440 if (i
.index_reg
->reg_num
== RegIZ
)
7441 i
.sib
.index
= NO_INDEX_REGISTER
;
7443 i
.sib
.index
= i
.index_reg
->reg_num
;
7444 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7445 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7450 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7451 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7455 if (!fake_zero_displacement
7459 fake_zero_displacement
= 1;
7460 if (i
.disp_encoding
== disp_encoding_8bit
)
7461 i
.types
[op
].bitfield
.disp8
= 1;
7463 i
.types
[op
].bitfield
.disp32
= 1;
7465 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7469 if (fake_zero_displacement
)
7471 /* Fakes a zero displacement assuming that i.types[op]
7472 holds the correct displacement size. */
7475 gas_assert (i
.op
[op
].disps
== 0);
7476 exp
= &disp_expressions
[i
.disp_operands
++];
7477 i
.op
[op
].disps
= exp
;
7478 exp
->X_op
= O_constant
;
7479 exp
->X_add_number
= 0;
7480 exp
->X_add_symbol
= (symbolS
*) 0;
7481 exp
->X_op_symbol
= (symbolS
*) 0;
7489 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7491 if (operand_type_check (i
.types
[0], imm
))
7492 i
.vex
.register_specifier
= NULL
;
7495 /* VEX.vvvv encodes one of the sources when the first
7496 operand is not an immediate. */
7497 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7498 i
.vex
.register_specifier
= i
.op
[0].regs
;
7500 i
.vex
.register_specifier
= i
.op
[1].regs
;
7503 /* Destination is a XMM register encoded in the ModRM.reg
7505 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7506 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7509 /* ModRM.rm and VEX.B encodes the other source. */
7510 if (!i
.mem_operands
)
7514 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7515 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7517 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7519 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7523 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7525 i
.vex
.register_specifier
= i
.op
[2].regs
;
7526 if (!i
.mem_operands
)
7529 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7530 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7534 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7535 (if any) based on i.tm.extension_opcode. Again, we must be
7536 careful to make sure that segment/control/debug/test/MMX
7537 registers are coded into the i.rm.reg field. */
7538 else if (i
.reg_operands
)
7541 unsigned int vex_reg
= ~0;
7543 for (op
= 0; op
< i
.operands
; op
++)
7545 if (i
.types
[op
].bitfield
.reg
7546 || i
.types
[op
].bitfield
.regbnd
7547 || i
.types
[op
].bitfield
.regmask
7548 || i
.types
[op
].bitfield
.sreg2
7549 || i
.types
[op
].bitfield
.sreg3
7550 || i
.types
[op
].bitfield
.control
7551 || i
.types
[op
].bitfield
.debug
7552 || i
.types
[op
].bitfield
.test
)
7554 if (i
.types
[op
].bitfield
.regsimd
)
7556 if (i
.types
[op
].bitfield
.zmmword
)
7557 i
.has_regzmm
= TRUE
;
7558 else if (i
.types
[op
].bitfield
.ymmword
)
7559 i
.has_regymm
= TRUE
;
7561 i
.has_regxmm
= TRUE
;
7564 if (i
.types
[op
].bitfield
.regmmx
)
7566 i
.has_regmmx
= TRUE
;
7573 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7575 /* For instructions with VexNDS, the register-only
7576 source operand is encoded in VEX prefix. */
7577 gas_assert (mem
!= (unsigned int) ~0);
7582 gas_assert (op
< i
.operands
);
7586 /* Check register-only source operand when two source
7587 operands are swapped. */
7588 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7589 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7593 gas_assert (mem
== (vex_reg
+ 1)
7594 && op
< i
.operands
);
7599 gas_assert (vex_reg
< i
.operands
);
7603 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7605 /* For instructions with VexNDD, the register destination
7606 is encoded in VEX prefix. */
7607 if (i
.mem_operands
== 0)
7609 /* There is no memory operand. */
7610 gas_assert ((op
+ 2) == i
.operands
);
7615 /* There are only 2 non-immediate operands. */
7616 gas_assert (op
< i
.imm_operands
+ 2
7617 && i
.operands
== i
.imm_operands
+ 2);
7618 vex_reg
= i
.imm_operands
+ 1;
7622 gas_assert (op
< i
.operands
);
7624 if (vex_reg
!= (unsigned int) ~0)
7626 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7628 if ((!type
->bitfield
.reg
7629 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7630 && !type
->bitfield
.regsimd
7631 && !operand_type_equal (type
, ®mask
))
7634 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7637 /* Don't set OP operand twice. */
7640 /* If there is an extension opcode to put here, the
7641 register number must be put into the regmem field. */
7642 if (i
.tm
.extension_opcode
!= None
)
7644 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7645 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7647 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7652 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7653 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7655 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7660 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7661 must set it to 3 to indicate this is a register operand
7662 in the regmem field. */
7663 if (!i
.mem_operands
)
7667 /* Fill in i.rm.reg field with extension opcode (if any). */
7668 if (i
.tm
.extension_opcode
!= None
)
7669 i
.rm
.reg
= i
.tm
.extension_opcode
;
7675 output_branch (void)
7681 relax_substateT subtype
;
7685 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7686 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7689 if (i
.prefix
[DATA_PREFIX
] != 0)
7695 /* Pentium4 branch hints. */
7696 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7697 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7702 if (i
.prefix
[REX_PREFIX
] != 0)
7708 /* BND prefixed jump. */
7709 if (i
.prefix
[BND_PREFIX
] != 0)
7711 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7715 if (i
.prefixes
!= 0 && !intel_syntax
)
7716 as_warn (_("skipping prefixes on this instruction"));
7718 /* It's always a symbol; End frag & setup for relax.
7719 Make sure there is enough room in this frag for the largest
7720 instruction we may generate in md_convert_frag. This is 2
7721 bytes for the opcode and room for the prefix and largest
7723 frag_grow (prefix
+ 2 + 4);
7724 /* Prefix and 1 opcode byte go in fr_fix. */
7725 p
= frag_more (prefix
+ 1);
7726 if (i
.prefix
[DATA_PREFIX
] != 0)
7727 *p
++ = DATA_PREFIX_OPCODE
;
7728 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7729 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7730 *p
++ = i
.prefix
[SEG_PREFIX
];
7731 if (i
.prefix
[REX_PREFIX
] != 0)
7732 *p
++ = i
.prefix
[REX_PREFIX
];
7733 *p
= i
.tm
.base_opcode
;
7735 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7736 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7737 else if (cpu_arch_flags
.bitfield
.cpui386
)
7738 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7740 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7743 sym
= i
.op
[0].disps
->X_add_symbol
;
7744 off
= i
.op
[0].disps
->X_add_number
;
7746 if (i
.op
[0].disps
->X_op
!= O_constant
7747 && i
.op
[0].disps
->X_op
!= O_symbol
)
7749 /* Handle complex expressions. */
7750 sym
= make_expr_symbol (i
.op
[0].disps
);
7754 /* 1 possible extra opcode + 4 byte displacement go in var part.
7755 Pass reloc in fr_var. */
7756 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7760 /* Return TRUE iff PLT32 relocation should be used for branching to
7764 need_plt32_p (symbolS
*s
)
7766 /* PLT32 relocation is ELF only. */
7770 /* Since there is no need to prepare for PLT branch on x86-64, we
7771 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7772 be used as a marker for 32-bit PC-relative branches. */
7776 /* Weak or undefined symbol need PLT32 relocation. */
7777 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7780 /* Non-global symbol doesn't need PLT32 relocation. */
7781 if (! S_IS_EXTERNAL (s
))
7784 /* Other global symbols need PLT32 relocation. NB: Symbol with
7785 non-default visibilities are treated as normal global symbol
7786 so that PLT32 relocation can be used as a marker for 32-bit
7787 PC-relative branches. It is useful for linker relaxation. */
7798 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7800 if (i
.tm
.opcode_modifier
.jumpbyte
)
7802 /* This is a loop or jecxz type instruction. */
7804 if (i
.prefix
[ADDR_PREFIX
] != 0)
7806 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7809 /* Pentium4 branch hints. */
7810 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7811 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7813 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7822 if (flag_code
== CODE_16BIT
)
7825 if (i
.prefix
[DATA_PREFIX
] != 0)
7827 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7837 if (i
.prefix
[REX_PREFIX
] != 0)
7839 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7843 /* BND prefixed jump. */
7844 if (i
.prefix
[BND_PREFIX
] != 0)
7846 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7850 if (i
.prefixes
!= 0 && !intel_syntax
)
7851 as_warn (_("skipping prefixes on this instruction"));
7853 p
= frag_more (i
.tm
.opcode_length
+ size
);
7854 switch (i
.tm
.opcode_length
)
7857 *p
++ = i
.tm
.base_opcode
>> 8;
7860 *p
++ = i
.tm
.base_opcode
;
7866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7868 && jump_reloc
== NO_RELOC
7869 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7870 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7873 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7875 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7876 i
.op
[0].disps
, 1, jump_reloc
);
7878 /* All jumps handled here are signed, but don't use a signed limit
7879 check for 32 and 16 bit jumps as we want to allow wrap around at
7880 4G and 64k respectively. */
7882 fixP
->fx_signed
= 1;
7886 output_interseg_jump (void)
7894 if (flag_code
== CODE_16BIT
)
7898 if (i
.prefix
[DATA_PREFIX
] != 0)
7904 if (i
.prefix
[REX_PREFIX
] != 0)
7914 if (i
.prefixes
!= 0 && !intel_syntax
)
7915 as_warn (_("skipping prefixes on this instruction"));
7917 /* 1 opcode; 2 segment; offset */
7918 p
= frag_more (prefix
+ 1 + 2 + size
);
7920 if (i
.prefix
[DATA_PREFIX
] != 0)
7921 *p
++ = DATA_PREFIX_OPCODE
;
7923 if (i
.prefix
[REX_PREFIX
] != 0)
7924 *p
++ = i
.prefix
[REX_PREFIX
];
7926 *p
++ = i
.tm
.base_opcode
;
7927 if (i
.op
[1].imms
->X_op
== O_constant
)
7929 offsetT n
= i
.op
[1].imms
->X_add_number
;
7932 && !fits_in_unsigned_word (n
)
7933 && !fits_in_signed_word (n
))
7935 as_bad (_("16-bit jump out of range"));
7938 md_number_to_chars (p
, n
, size
);
7941 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7942 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7943 if (i
.op
[0].imms
->X_op
!= O_constant
)
7944 as_bad (_("can't handle non absolute segment in `%s'"),
7946 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7954 asection
*seg
= now_seg
;
7955 subsegT subseg
= now_subseg
;
7957 unsigned int alignment
, align_size_1
;
7958 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7959 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7960 unsigned int padding
;
7962 if (!IS_ELF
|| !x86_used_note
)
7965 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7967 /* The .note.gnu.property section layout:
7969 Field Length Contents
7972 n_descsz 4 The note descriptor size
7973 n_type 4 NT_GNU_PROPERTY_TYPE_0
7975 n_desc n_descsz The program property array
7979 /* Create the .note.gnu.property section. */
7980 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7981 bfd_set_section_flags (stdoutput
, sec
,
7988 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7999 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8000 elf_section_type (sec
) = SHT_NOTE
;
8002 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8004 isa_1_descsz_raw
= 4 + 4 + 4;
8005 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8006 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8008 feature_2_descsz_raw
= isa_1_descsz
;
8009 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8011 feature_2_descsz_raw
+= 4 + 4 + 4;
8012 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8013 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8016 descsz
= feature_2_descsz
;
8017 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8018 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8020 /* Write n_namsz. */
8021 md_number_to_chars (p
, (valueT
) 4, 4);
8023 /* Write n_descsz. */
8024 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8027 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8030 memcpy (p
+ 4 * 3, "GNU", 4);
8032 /* Write 4-byte type. */
8033 md_number_to_chars (p
+ 4 * 4,
8034 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8036 /* Write 4-byte data size. */
8037 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8039 /* Write 4-byte data. */
8040 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8042 /* Zero out paddings. */
8043 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8045 memset (p
+ 4 * 7, 0, padding
);
8047 /* Write 4-byte type. */
8048 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8049 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8051 /* Write 4-byte data size. */
8052 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8054 /* Write 4-byte data. */
8055 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8056 (valueT
) x86_feature_2_used
, 4);
8058 /* Zero out paddings. */
8059 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8061 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8063 /* We probably can't restore the current segment, for there likely
8066 subseg_set (seg
, subseg
);
8073 fragS
*insn_start_frag
;
8074 offsetT insn_start_off
;
8076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8077 if (IS_ELF
&& x86_used_note
)
8079 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8080 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8081 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8082 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8083 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8084 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8085 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8086 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8087 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8088 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8089 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8090 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8091 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8092 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8093 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8094 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8095 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8096 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8097 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8098 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8099 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8100 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8101 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8102 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8103 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8104 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8105 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8106 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8107 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8108 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8109 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8110 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8111 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8112 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8113 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8114 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8115 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8116 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8117 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8118 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8119 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8120 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8121 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8122 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8123 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8124 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8125 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8126 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8128 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8129 || i
.tm
.cpu_flags
.bitfield
.cpu287
8130 || i
.tm
.cpu_flags
.bitfield
.cpu387
8131 || i
.tm
.cpu_flags
.bitfield
.cpu687
8132 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8133 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8134 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8135 Xfence instructions. */
8136 if (i
.tm
.base_opcode
!= 0xf18
8137 && i
.tm
.base_opcode
!= 0xf0d
8138 && i
.tm
.base_opcode
!= 0xfae
8140 || i
.tm
.cpu_flags
.bitfield
.cpummx
8141 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8142 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8143 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8145 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8147 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8149 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8150 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8151 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8152 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8153 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8154 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8155 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8156 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8157 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8161 /* Tie dwarf2 debug info to the address at the start of the insn.
8162 We can't do this after the insn has been output as the current
8163 frag may have been closed off. eg. by frag_var. */
8164 dwarf2_emit_insn (0);
8166 insn_start_frag
= frag_now
;
8167 insn_start_off
= frag_now_fix ();
8170 if (i
.tm
.opcode_modifier
.jump
)
8172 else if (i
.tm
.opcode_modifier
.jumpbyte
8173 || i
.tm
.opcode_modifier
.jumpdword
)
8175 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8176 output_interseg_jump ();
8179 /* Output normal instructions here. */
8183 unsigned int prefix
;
8186 && i
.tm
.base_opcode
== 0xfae
8188 && i
.imm_operands
== 1
8189 && (i
.op
[0].imms
->X_add_number
== 0xe8
8190 || i
.op
[0].imms
->X_add_number
== 0xf0
8191 || i
.op
[0].imms
->X_add_number
== 0xf8))
8193 /* Encode lfence, mfence, and sfence as
8194 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8195 offsetT val
= 0x240483f0ULL
;
8197 md_number_to_chars (p
, val
, 5);
8201 /* Some processors fail on LOCK prefix. This options makes
8202 assembler ignore LOCK prefix and serves as a workaround. */
8203 if (omit_lock_prefix
)
8205 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8207 i
.prefix
[LOCK_PREFIX
] = 0;
8210 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8211 don't need the explicit prefix. */
8212 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8214 switch (i
.tm
.opcode_length
)
8217 if (i
.tm
.base_opcode
& 0xff000000)
8219 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8220 add_prefix (prefix
);
8224 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8226 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8227 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8228 || prefix
!= REPE_PREFIX_OPCODE
8229 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8230 add_prefix (prefix
);
8236 /* Check for pseudo prefixes. */
8237 as_bad_where (insn_start_frag
->fr_file
,
8238 insn_start_frag
->fr_line
,
8239 _("pseudo prefix without instruction"));
8245 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8246 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8247 R_X86_64_GOTTPOFF relocation so that linker can safely
8248 perform IE->LE optimization. */
8249 if (x86_elf_abi
== X86_64_X32_ABI
8251 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8252 && i
.prefix
[REX_PREFIX
] == 0)
8253 add_prefix (REX_OPCODE
);
8256 /* The prefix bytes. */
8257 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8259 FRAG_APPEND_1_CHAR (*q
);
8263 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8268 /* REX byte is encoded in VEX prefix. */
8272 FRAG_APPEND_1_CHAR (*q
);
8275 /* There should be no other prefixes for instructions
8280 /* For EVEX instructions i.vrex should become 0 after
8281 build_evex_prefix. For VEX instructions upper 16 registers
8282 aren't available, so VREX should be 0. */
8285 /* Now the VEX prefix. */
8286 p
= frag_more (i
.vex
.length
);
8287 for (j
= 0; j
< i
.vex
.length
; j
++)
8288 p
[j
] = i
.vex
.bytes
[j
];
8291 /* Now the opcode; be careful about word order here! */
8292 if (i
.tm
.opcode_length
== 1)
8294 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8298 switch (i
.tm
.opcode_length
)
8302 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8303 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8307 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8317 /* Put out high byte first: can't use md_number_to_chars! */
8318 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8319 *p
= i
.tm
.base_opcode
& 0xff;
8322 /* Now the modrm byte and sib byte (if present). */
8323 if (i
.tm
.opcode_modifier
.modrm
)
8325 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8328 /* If i.rm.regmem == ESP (4)
8329 && i.rm.mode != (Register mode)
8331 ==> need second modrm byte. */
8332 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8334 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8335 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8337 | i
.sib
.scale
<< 6));
8340 if (i
.disp_operands
)
8341 output_disp (insn_start_frag
, insn_start_off
);
8344 output_imm (insn_start_frag
, insn_start_off
);
8350 pi ("" /*line*/, &i
);
8352 #endif /* DEBUG386 */
8355 /* Return the size of the displacement operand N. */
8358 disp_size (unsigned int n
)
8362 if (i
.types
[n
].bitfield
.disp64
)
8364 else if (i
.types
[n
].bitfield
.disp8
)
8366 else if (i
.types
[n
].bitfield
.disp16
)
8371 /* Return the size of the immediate operand N. */
8374 imm_size (unsigned int n
)
8377 if (i
.types
[n
].bitfield
.imm64
)
8379 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8381 else if (i
.types
[n
].bitfield
.imm16
)
8387 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8392 for (n
= 0; n
< i
.operands
; n
++)
8394 if (operand_type_check (i
.types
[n
], disp
))
8396 if (i
.op
[n
].disps
->X_op
== O_constant
)
8398 int size
= disp_size (n
);
8399 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8401 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8403 p
= frag_more (size
);
8404 md_number_to_chars (p
, val
, size
);
8408 enum bfd_reloc_code_real reloc_type
;
8409 int size
= disp_size (n
);
8410 int sign
= i
.types
[n
].bitfield
.disp32s
;
8411 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8414 /* We can't have 8 bit displacement here. */
8415 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8417 /* The PC relative address is computed relative
8418 to the instruction boundary, so in case immediate
8419 fields follows, we need to adjust the value. */
8420 if (pcrel
&& i
.imm_operands
)
8425 for (n1
= 0; n1
< i
.operands
; n1
++)
8426 if (operand_type_check (i
.types
[n1
], imm
))
8428 /* Only one immediate is allowed for PC
8429 relative address. */
8430 gas_assert (sz
== 0);
8432 i
.op
[n
].disps
->X_add_number
-= sz
;
8434 /* We should find the immediate. */
8435 gas_assert (sz
!= 0);
8438 p
= frag_more (size
);
8439 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8441 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8442 && (((reloc_type
== BFD_RELOC_32
8443 || reloc_type
== BFD_RELOC_X86_64_32S
8444 || (reloc_type
== BFD_RELOC_64
8446 && (i
.op
[n
].disps
->X_op
== O_symbol
8447 || (i
.op
[n
].disps
->X_op
== O_add
8448 && ((symbol_get_value_expression
8449 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8451 || reloc_type
== BFD_RELOC_32_PCREL
))
8455 if (insn_start_frag
== frag_now
)
8456 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8461 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8462 for (fr
= insn_start_frag
->fr_next
;
8463 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8465 add
+= p
- frag_now
->fr_literal
;
8470 reloc_type
= BFD_RELOC_386_GOTPC
;
8471 i
.op
[n
].imms
->X_add_number
+= add
;
8473 else if (reloc_type
== BFD_RELOC_64
)
8474 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8476 /* Don't do the adjustment for x86-64, as there
8477 the pcrel addressing is relative to the _next_
8478 insn, and that is taken care of in other code. */
8479 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8481 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8482 size
, i
.op
[n
].disps
, pcrel
,
8484 /* Check for "call/jmp *mem", "mov mem, %reg",
8485 "test %reg, mem" and "binop mem, %reg" where binop
8486 is one of adc, add, and, cmp, or, sbb, sub, xor
8487 instructions without data prefix. Always generate
8488 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8489 if (i
.prefix
[DATA_PREFIX
] == 0
8490 && (generate_relax_relocations
8493 && i
.rm
.regmem
== 5))
8495 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8496 && ((i
.operands
== 1
8497 && i
.tm
.base_opcode
== 0xff
8498 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8500 && (i
.tm
.base_opcode
== 0x8b
8501 || i
.tm
.base_opcode
== 0x85
8502 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8506 fixP
->fx_tcbit
= i
.rex
!= 0;
8508 && (i
.base_reg
->reg_num
== RegIP
))
8509 fixP
->fx_tcbit2
= 1;
8512 fixP
->fx_tcbit2
= 1;
8520 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8525 for (n
= 0; n
< i
.operands
; n
++)
8527 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8528 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8531 if (operand_type_check (i
.types
[n
], imm
))
8533 if (i
.op
[n
].imms
->X_op
== O_constant
)
8535 int size
= imm_size (n
);
8538 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8540 p
= frag_more (size
);
8541 md_number_to_chars (p
, val
, size
);
8545 /* Not absolute_section.
8546 Need a 32-bit fixup (don't support 8bit
8547 non-absolute imms). Try to support other
8549 enum bfd_reloc_code_real reloc_type
;
8550 int size
= imm_size (n
);
8553 if (i
.types
[n
].bitfield
.imm32s
8554 && (i
.suffix
== QWORD_MNEM_SUFFIX
8555 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8560 p
= frag_more (size
);
8561 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8563 /* This is tough to explain. We end up with this one if we
8564 * have operands that look like
8565 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8566 * obtain the absolute address of the GOT, and it is strongly
8567 * preferable from a performance point of view to avoid using
8568 * a runtime relocation for this. The actual sequence of
8569 * instructions often look something like:
8574 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8576 * The call and pop essentially return the absolute address
8577 * of the label .L66 and store it in %ebx. The linker itself
8578 * will ultimately change the first operand of the addl so
8579 * that %ebx points to the GOT, but to keep things simple, the
8580 * .o file must have this operand set so that it generates not
8581 * the absolute address of .L66, but the absolute address of
8582 * itself. This allows the linker itself simply treat a GOTPC
8583 * relocation as asking for a pcrel offset to the GOT to be
8584 * added in, and the addend of the relocation is stored in the
8585 * operand field for the instruction itself.
8587 * Our job here is to fix the operand so that it would add
8588 * the correct offset so that %ebx would point to itself. The
8589 * thing that is tricky is that .-.L66 will point to the
8590 * beginning of the instruction, so we need to further modify
8591 * the operand so that it will point to itself. There are
8592 * other cases where you have something like:
8594 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8596 * and here no correction would be required. Internally in
8597 * the assembler we treat operands of this form as not being
8598 * pcrel since the '.' is explicitly mentioned, and I wonder
8599 * whether it would simplify matters to do it this way. Who
8600 * knows. In earlier versions of the PIC patches, the
8601 * pcrel_adjust field was used to store the correction, but
8602 * since the expression is not pcrel, I felt it would be
8603 * confusing to do it this way. */
8605 if ((reloc_type
== BFD_RELOC_32
8606 || reloc_type
== BFD_RELOC_X86_64_32S
8607 || reloc_type
== BFD_RELOC_64
)
8609 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8610 && (i
.op
[n
].imms
->X_op
== O_symbol
8611 || (i
.op
[n
].imms
->X_op
== O_add
8612 && ((symbol_get_value_expression
8613 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8618 if (insn_start_frag
== frag_now
)
8619 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8624 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8625 for (fr
= insn_start_frag
->fr_next
;
8626 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8628 add
+= p
- frag_now
->fr_literal
;
8632 reloc_type
= BFD_RELOC_386_GOTPC
;
8634 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8636 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8637 i
.op
[n
].imms
->X_add_number
+= add
;
8639 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8640 i
.op
[n
].imms
, 0, reloc_type
);
8646 /* x86_cons_fix_new is called via the expression parsing code when a
8647 reloc is needed. We use this hook to get the correct .got reloc. */
8648 static int cons_sign
= -1;
8651 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8652 expressionS
*exp
, bfd_reloc_code_real_type r
)
8654 r
= reloc (len
, 0, cons_sign
, r
);
8657 if (exp
->X_op
== O_secrel
)
8659 exp
->X_op
= O_symbol
;
8660 r
= BFD_RELOC_32_SECREL
;
8664 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8668 purpose of the `.dc.a' internal pseudo-op. */
8671 x86_address_bytes (void)
8673 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8675 return stdoutput
->arch_info
->bits_per_address
/ 8;
8678 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8680 # define lex_got(reloc, adjust, types) NULL
8682 /* Parse operands of the form
8683 <symbol>@GOTOFF+<nnn>
8684 and similar .plt or .got references.
8686 If we find one, set up the correct relocation in RELOC and copy the
8687 input string, minus the `@GOTOFF' into a malloc'd buffer for
8688 parsing by the calling routine. Return this buffer, and if ADJUST
8689 is non-null set it to the length of the string we removed from the
8690 input line. Otherwise return NULL. */
8692 lex_got (enum bfd_reloc_code_real
*rel
,
8694 i386_operand_type
*types
)
8696 /* Some of the relocations depend on the size of what field is to
8697 be relocated. But in our callers i386_immediate and i386_displacement
8698 we don't yet know the operand size (this will be set by insn
8699 matching). Hence we record the word32 relocation here,
8700 and adjust the reloc according to the real size in reloc(). */
8701 static const struct {
8704 const enum bfd_reloc_code_real rel
[2];
8705 const i386_operand_type types64
;
8707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8708 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8710 OPERAND_TYPE_IMM32_64
},
8712 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8713 BFD_RELOC_X86_64_PLTOFF64
},
8714 OPERAND_TYPE_IMM64
},
8715 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8716 BFD_RELOC_X86_64_PLT32
},
8717 OPERAND_TYPE_IMM32_32S_DISP32
},
8718 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8719 BFD_RELOC_X86_64_GOTPLT64
},
8720 OPERAND_TYPE_IMM64_DISP64
},
8721 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8722 BFD_RELOC_X86_64_GOTOFF64
},
8723 OPERAND_TYPE_IMM64_DISP64
},
8724 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8725 BFD_RELOC_X86_64_GOTPCREL
},
8726 OPERAND_TYPE_IMM32_32S_DISP32
},
8727 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8728 BFD_RELOC_X86_64_TLSGD
},
8729 OPERAND_TYPE_IMM32_32S_DISP32
},
8730 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8731 _dummy_first_bfd_reloc_code_real
},
8732 OPERAND_TYPE_NONE
},
8733 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8734 BFD_RELOC_X86_64_TLSLD
},
8735 OPERAND_TYPE_IMM32_32S_DISP32
},
8736 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8737 BFD_RELOC_X86_64_GOTTPOFF
},
8738 OPERAND_TYPE_IMM32_32S_DISP32
},
8739 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8740 BFD_RELOC_X86_64_TPOFF32
},
8741 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8742 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8743 _dummy_first_bfd_reloc_code_real
},
8744 OPERAND_TYPE_NONE
},
8745 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8746 BFD_RELOC_X86_64_DTPOFF32
},
8747 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8748 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8749 _dummy_first_bfd_reloc_code_real
},
8750 OPERAND_TYPE_NONE
},
8751 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8752 _dummy_first_bfd_reloc_code_real
},
8753 OPERAND_TYPE_NONE
},
8754 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8755 BFD_RELOC_X86_64_GOT32
},
8756 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8757 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8758 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8759 OPERAND_TYPE_IMM32_32S_DISP32
},
8760 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8761 BFD_RELOC_X86_64_TLSDESC_CALL
},
8762 OPERAND_TYPE_IMM32_32S_DISP32
},
8767 #if defined (OBJ_MAYBE_ELF)
8772 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8773 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8776 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8778 int len
= gotrel
[j
].len
;
8779 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8781 if (gotrel
[j
].rel
[object_64bit
] != 0)
8784 char *tmpbuf
, *past_reloc
;
8786 *rel
= gotrel
[j
].rel
[object_64bit
];
8790 if (flag_code
!= CODE_64BIT
)
8792 types
->bitfield
.imm32
= 1;
8793 types
->bitfield
.disp32
= 1;
8796 *types
= gotrel
[j
].types64
;
8799 if (j
!= 0 && GOT_symbol
== NULL
)
8800 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8802 /* The length of the first part of our input line. */
8803 first
= cp
- input_line_pointer
;
8805 /* The second part goes from after the reloc token until
8806 (and including) an end_of_line char or comma. */
8807 past_reloc
= cp
+ 1 + len
;
8809 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8811 second
= cp
+ 1 - past_reloc
;
8813 /* Allocate and copy string. The trailing NUL shouldn't
8814 be necessary, but be safe. */
8815 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8816 memcpy (tmpbuf
, input_line_pointer
, first
);
8817 if (second
!= 0 && *past_reloc
!= ' ')
8818 /* Replace the relocation token with ' ', so that
8819 errors like foo@GOTOFF1 will be detected. */
8820 tmpbuf
[first
++] = ' ';
8822 /* Increment length by 1 if the relocation token is
8827 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8828 tmpbuf
[first
+ second
] = '\0';
8832 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8833 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8838 /* Might be a symbol version string. Don't as_bad here. */
8847 /* Parse operands of the form
8848 <symbol>@SECREL32+<nnn>
8850 If we find one, set up the correct relocation in RELOC and copy the
8851 input string, minus the `@SECREL32' into a malloc'd buffer for
8852 parsing by the calling routine. Return this buffer, and if ADJUST
8853 is non-null set it to the length of the string we removed from the
8854 input line. Otherwise return NULL.
8856 This function is copied from the ELF version above adjusted for PE targets. */
8859 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8860 int *adjust ATTRIBUTE_UNUSED
,
8861 i386_operand_type
*types
)
8867 const enum bfd_reloc_code_real rel
[2];
8868 const i386_operand_type types64
;
8872 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8873 BFD_RELOC_32_SECREL
},
8874 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8880 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8881 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8884 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8886 int len
= gotrel
[j
].len
;
8888 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8890 if (gotrel
[j
].rel
[object_64bit
] != 0)
8893 char *tmpbuf
, *past_reloc
;
8895 *rel
= gotrel
[j
].rel
[object_64bit
];
8901 if (flag_code
!= CODE_64BIT
)
8903 types
->bitfield
.imm32
= 1;
8904 types
->bitfield
.disp32
= 1;
8907 *types
= gotrel
[j
].types64
;
8910 /* The length of the first part of our input line. */
8911 first
= cp
- input_line_pointer
;
8913 /* The second part goes from after the reloc token until
8914 (and including) an end_of_line char or comma. */
8915 past_reloc
= cp
+ 1 + len
;
8917 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8919 second
= cp
+ 1 - past_reloc
;
8921 /* Allocate and copy string. The trailing NUL shouldn't
8922 be necessary, but be safe. */
8923 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8924 memcpy (tmpbuf
, input_line_pointer
, first
);
8925 if (second
!= 0 && *past_reloc
!= ' ')
8926 /* Replace the relocation token with ' ', so that
8927 errors like foo@SECLREL321 will be detected. */
8928 tmpbuf
[first
++] = ' ';
8929 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8930 tmpbuf
[first
+ second
] = '\0';
8934 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8935 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8940 /* Might be a symbol version string. Don't as_bad here. */
8946 bfd_reloc_code_real_type
8947 x86_cons (expressionS
*exp
, int size
)
8949 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8951 intel_syntax
= -intel_syntax
;
8954 if (size
== 4 || (object_64bit
&& size
== 8))
8956 /* Handle @GOTOFF and the like in an expression. */
8958 char *gotfree_input_line
;
8961 save
= input_line_pointer
;
8962 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8963 if (gotfree_input_line
)
8964 input_line_pointer
= gotfree_input_line
;
8968 if (gotfree_input_line
)
8970 /* expression () has merrily parsed up to the end of line,
8971 or a comma - in the wrong buffer. Transfer how far
8972 input_line_pointer has moved to the right buffer. */
8973 input_line_pointer
= (save
8974 + (input_line_pointer
- gotfree_input_line
)
8976 free (gotfree_input_line
);
8977 if (exp
->X_op
== O_constant
8978 || exp
->X_op
== O_absent
8979 || exp
->X_op
== O_illegal
8980 || exp
->X_op
== O_register
8981 || exp
->X_op
== O_big
)
8983 char c
= *input_line_pointer
;
8984 *input_line_pointer
= 0;
8985 as_bad (_("missing or invalid expression `%s'"), save
);
8986 *input_line_pointer
= c
;
8988 else if ((got_reloc
== BFD_RELOC_386_PLT32
8989 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
8990 && exp
->X_op
!= O_symbol
)
8992 char c
= *input_line_pointer
;
8993 *input_line_pointer
= 0;
8994 as_bad (_("invalid PLT expression `%s'"), save
);
8995 *input_line_pointer
= c
;
9002 intel_syntax
= -intel_syntax
;
9005 i386_intel_simplify (exp
);
9011 signed_cons (int size
)
9013 if (flag_code
== CODE_64BIT
)
9021 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9028 if (exp
.X_op
== O_symbol
)
9029 exp
.X_op
= O_secrel
;
9031 emit_expr (&exp
, 4);
9033 while (*input_line_pointer
++ == ',');
9035 input_line_pointer
--;
9036 demand_empty_rest_of_line ();
9040 /* Handle Vector operations. */
9043 check_VecOperations (char *op_string
, char *op_end
)
9045 const reg_entry
*mask
;
9050 && (op_end
== NULL
|| op_string
< op_end
))
9053 if (*op_string
== '{')
9057 /* Check broadcasts. */
9058 if (strncmp (op_string
, "1to", 3) == 0)
9063 goto duplicated_vec_op
;
9066 if (*op_string
== '8')
9068 else if (*op_string
== '4')
9070 else if (*op_string
== '2')
9072 else if (*op_string
== '1'
9073 && *(op_string
+1) == '6')
9080 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9085 broadcast_op
.type
= bcst_type
;
9086 broadcast_op
.operand
= this_operand
;
9087 broadcast_op
.bytes
= 0;
9088 i
.broadcast
= &broadcast_op
;
9090 /* Check masking operation. */
9091 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9093 /* k0 can't be used for write mask. */
9094 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9096 as_bad (_("`%s%s' can't be used for write mask"),
9097 register_prefix
, mask
->reg_name
);
9103 mask_op
.mask
= mask
;
9104 mask_op
.zeroing
= 0;
9105 mask_op
.operand
= this_operand
;
9111 goto duplicated_vec_op
;
9113 i
.mask
->mask
= mask
;
9115 /* Only "{z}" is allowed here. No need to check
9116 zeroing mask explicitly. */
9117 if (i
.mask
->operand
!= this_operand
)
9119 as_bad (_("invalid write mask `%s'"), saved
);
9126 /* Check zeroing-flag for masking operation. */
9127 else if (*op_string
== 'z')
9131 mask_op
.mask
= NULL
;
9132 mask_op
.zeroing
= 1;
9133 mask_op
.operand
= this_operand
;
9138 if (i
.mask
->zeroing
)
9141 as_bad (_("duplicated `%s'"), saved
);
9145 i
.mask
->zeroing
= 1;
9147 /* Only "{%k}" is allowed here. No need to check mask
9148 register explicitly. */
9149 if (i
.mask
->operand
!= this_operand
)
9151 as_bad (_("invalid zeroing-masking `%s'"),
9160 goto unknown_vec_op
;
9162 if (*op_string
!= '}')
9164 as_bad (_("missing `}' in `%s'"), saved
);
9169 /* Strip whitespace since the addition of pseudo prefixes
9170 changed how the scrubber treats '{'. */
9171 if (is_space_char (*op_string
))
9177 /* We don't know this one. */
9178 as_bad (_("unknown vector operation: `%s'"), saved
);
9182 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9184 as_bad (_("zeroing-masking only allowed with write mask"));
9192 i386_immediate (char *imm_start
)
9194 char *save_input_line_pointer
;
9195 char *gotfree_input_line
;
9198 i386_operand_type types
;
9200 operand_type_set (&types
, ~0);
9202 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9204 as_bad (_("at most %d immediate operands are allowed"),
9205 MAX_IMMEDIATE_OPERANDS
);
9209 exp
= &im_expressions
[i
.imm_operands
++];
9210 i
.op
[this_operand
].imms
= exp
;
9212 if (is_space_char (*imm_start
))
9215 save_input_line_pointer
= input_line_pointer
;
9216 input_line_pointer
= imm_start
;
9218 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9219 if (gotfree_input_line
)
9220 input_line_pointer
= gotfree_input_line
;
9222 exp_seg
= expression (exp
);
9226 /* Handle vector operations. */
9227 if (*input_line_pointer
== '{')
9229 input_line_pointer
= check_VecOperations (input_line_pointer
,
9231 if (input_line_pointer
== NULL
)
9235 if (*input_line_pointer
)
9236 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9238 input_line_pointer
= save_input_line_pointer
;
9239 if (gotfree_input_line
)
9241 free (gotfree_input_line
);
9243 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9244 exp
->X_op
= O_illegal
;
9247 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9251 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9252 i386_operand_type types
, const char *imm_start
)
9254 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9257 as_bad (_("missing or invalid immediate expression `%s'"),
9261 else if (exp
->X_op
== O_constant
)
9263 /* Size it properly later. */
9264 i
.types
[this_operand
].bitfield
.imm64
= 1;
9265 /* If not 64bit, sign extend val. */
9266 if (flag_code
!= CODE_64BIT
9267 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9269 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9271 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9272 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9273 && exp_seg
!= absolute_section
9274 && exp_seg
!= text_section
9275 && exp_seg
!= data_section
9276 && exp_seg
!= bss_section
9277 && exp_seg
!= undefined_section
9278 && !bfd_is_com_section (exp_seg
))
9280 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9284 else if (!intel_syntax
&& exp_seg
== reg_section
)
9287 as_bad (_("illegal immediate register operand %s"), imm_start
);
9292 /* This is an address. The size of the address will be
9293 determined later, depending on destination register,
9294 suffix, or the default for the section. */
9295 i
.types
[this_operand
].bitfield
.imm8
= 1;
9296 i
.types
[this_operand
].bitfield
.imm16
= 1;
9297 i
.types
[this_operand
].bitfield
.imm32
= 1;
9298 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9299 i
.types
[this_operand
].bitfield
.imm64
= 1;
9300 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9308 i386_scale (char *scale
)
9311 char *save
= input_line_pointer
;
9313 input_line_pointer
= scale
;
9314 val
= get_absolute_expression ();
9319 i
.log2_scale_factor
= 0;
9322 i
.log2_scale_factor
= 1;
9325 i
.log2_scale_factor
= 2;
9328 i
.log2_scale_factor
= 3;
9332 char sep
= *input_line_pointer
;
9334 *input_line_pointer
= '\0';
9335 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9337 *input_line_pointer
= sep
;
9338 input_line_pointer
= save
;
9342 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9344 as_warn (_("scale factor of %d without an index register"),
9345 1 << i
.log2_scale_factor
);
9346 i
.log2_scale_factor
= 0;
9348 scale
= input_line_pointer
;
9349 input_line_pointer
= save
;
9354 i386_displacement (char *disp_start
, char *disp_end
)
9358 char *save_input_line_pointer
;
9359 char *gotfree_input_line
;
9361 i386_operand_type bigdisp
, types
= anydisp
;
9364 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9366 as_bad (_("at most %d displacement operands are allowed"),
9367 MAX_MEMORY_OPERANDS
);
9371 operand_type_set (&bigdisp
, 0);
9372 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9373 || (!current_templates
->start
->opcode_modifier
.jump
9374 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9376 bigdisp
.bitfield
.disp32
= 1;
9377 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9378 if (flag_code
== CODE_64BIT
)
9382 bigdisp
.bitfield
.disp32s
= 1;
9383 bigdisp
.bitfield
.disp64
= 1;
9386 else if ((flag_code
== CODE_16BIT
) ^ override
)
9388 bigdisp
.bitfield
.disp32
= 0;
9389 bigdisp
.bitfield
.disp16
= 1;
9394 /* For PC-relative branches, the width of the displacement
9395 is dependent upon data size, not address size. */
9396 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9397 if (flag_code
== CODE_64BIT
)
9399 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9400 bigdisp
.bitfield
.disp16
= 1;
9403 bigdisp
.bitfield
.disp32
= 1;
9404 bigdisp
.bitfield
.disp32s
= 1;
9410 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9412 : LONG_MNEM_SUFFIX
));
9413 bigdisp
.bitfield
.disp32
= 1;
9414 if ((flag_code
== CODE_16BIT
) ^ override
)
9416 bigdisp
.bitfield
.disp32
= 0;
9417 bigdisp
.bitfield
.disp16
= 1;
9421 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9424 exp
= &disp_expressions
[i
.disp_operands
];
9425 i
.op
[this_operand
].disps
= exp
;
9427 save_input_line_pointer
= input_line_pointer
;
9428 input_line_pointer
= disp_start
;
9429 END_STRING_AND_SAVE (disp_end
);
9431 #ifndef GCC_ASM_O_HACK
9432 #define GCC_ASM_O_HACK 0
9435 END_STRING_AND_SAVE (disp_end
+ 1);
9436 if (i
.types
[this_operand
].bitfield
.baseIndex
9437 && displacement_string_end
[-1] == '+')
9439 /* This hack is to avoid a warning when using the "o"
9440 constraint within gcc asm statements.
9443 #define _set_tssldt_desc(n,addr,limit,type) \
9444 __asm__ __volatile__ ( \
9446 "movw %w1,2+%0\n\t" \
9448 "movb %b1,4+%0\n\t" \
9449 "movb %4,5+%0\n\t" \
9450 "movb $0,6+%0\n\t" \
9451 "movb %h1,7+%0\n\t" \
9453 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9455 This works great except that the output assembler ends
9456 up looking a bit weird if it turns out that there is
9457 no offset. You end up producing code that looks like:
9470 So here we provide the missing zero. */
9472 *displacement_string_end
= '0';
9475 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9476 if (gotfree_input_line
)
9477 input_line_pointer
= gotfree_input_line
;
9479 exp_seg
= expression (exp
);
9482 if (*input_line_pointer
)
9483 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9485 RESTORE_END_STRING (disp_end
+ 1);
9487 input_line_pointer
= save_input_line_pointer
;
9488 if (gotfree_input_line
)
9490 free (gotfree_input_line
);
9492 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9493 exp
->X_op
= O_illegal
;
9496 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9498 RESTORE_END_STRING (disp_end
);
9504 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9505 i386_operand_type types
, const char *disp_start
)
9507 i386_operand_type bigdisp
;
9510 /* We do this to make sure that the section symbol is in
9511 the symbol table. We will ultimately change the relocation
9512 to be relative to the beginning of the section. */
9513 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9514 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9515 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9517 if (exp
->X_op
!= O_symbol
)
9520 if (S_IS_LOCAL (exp
->X_add_symbol
)
9521 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9522 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9523 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9524 exp
->X_op
= O_subtract
;
9525 exp
->X_op_symbol
= GOT_symbol
;
9526 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9527 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9528 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9529 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9531 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9534 else if (exp
->X_op
== O_absent
9535 || exp
->X_op
== O_illegal
9536 || exp
->X_op
== O_big
)
9539 as_bad (_("missing or invalid displacement expression `%s'"),
9544 else if (flag_code
== CODE_64BIT
9545 && !i
.prefix
[ADDR_PREFIX
]
9546 && exp
->X_op
== O_constant
)
9548 /* Since displacement is signed extended to 64bit, don't allow
9549 disp32 and turn off disp32s if they are out of range. */
9550 i
.types
[this_operand
].bitfield
.disp32
= 0;
9551 if (!fits_in_signed_long (exp
->X_add_number
))
9553 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9554 if (i
.types
[this_operand
].bitfield
.baseindex
)
9556 as_bad (_("0x%lx out range of signed 32bit displacement"),
9557 (long) exp
->X_add_number
);
9563 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9564 else if (exp
->X_op
!= O_constant
9565 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9566 && exp_seg
!= absolute_section
9567 && exp_seg
!= text_section
9568 && exp_seg
!= data_section
9569 && exp_seg
!= bss_section
9570 && exp_seg
!= undefined_section
9571 && !bfd_is_com_section (exp_seg
))
9573 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9578 /* Check if this is a displacement only operand. */
9579 bigdisp
= i
.types
[this_operand
];
9580 bigdisp
.bitfield
.disp8
= 0;
9581 bigdisp
.bitfield
.disp16
= 0;
9582 bigdisp
.bitfield
.disp32
= 0;
9583 bigdisp
.bitfield
.disp32s
= 0;
9584 bigdisp
.bitfield
.disp64
= 0;
9585 if (operand_type_all_zero (&bigdisp
))
9586 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9592 /* Return the active addressing mode, taking address override and
9593 registers forming the address into consideration. Update the
9594 address override prefix if necessary. */
9596 static enum flag_code
9597 i386_addressing_mode (void)
9599 enum flag_code addr_mode
;
9601 if (i
.prefix
[ADDR_PREFIX
])
9602 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9605 addr_mode
= flag_code
;
9607 #if INFER_ADDR_PREFIX
9608 if (i
.mem_operands
== 0)
9610 /* Infer address prefix from the first memory operand. */
9611 const reg_entry
*addr_reg
= i
.base_reg
;
9613 if (addr_reg
== NULL
)
9614 addr_reg
= i
.index_reg
;
9618 if (addr_reg
->reg_type
.bitfield
.dword
)
9619 addr_mode
= CODE_32BIT
;
9620 else if (flag_code
!= CODE_64BIT
9621 && addr_reg
->reg_type
.bitfield
.word
)
9622 addr_mode
= CODE_16BIT
;
9624 if (addr_mode
!= flag_code
)
9626 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9628 /* Change the size of any displacement too. At most one
9629 of Disp16 or Disp32 is set.
9630 FIXME. There doesn't seem to be any real need for
9631 separate Disp16 and Disp32 flags. The same goes for
9632 Imm16 and Imm32. Removing them would probably clean
9633 up the code quite a lot. */
9634 if (flag_code
!= CODE_64BIT
9635 && (i
.types
[this_operand
].bitfield
.disp16
9636 || i
.types
[this_operand
].bitfield
.disp32
))
9637 i
.types
[this_operand
]
9638 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9648 /* Make sure the memory operand we've been dealt is valid.
9649 Return 1 on success, 0 on a failure. */
9652 i386_index_check (const char *operand_string
)
9654 const char *kind
= "base/index";
9655 enum flag_code addr_mode
= i386_addressing_mode ();
9657 if (current_templates
->start
->opcode_modifier
.isstring
9658 && !current_templates
->start
->opcode_modifier
.immext
9659 && (current_templates
->end
[-1].opcode_modifier
.isstring
9662 /* Memory operands of string insns are special in that they only allow
9663 a single register (rDI, rSI, or rBX) as their memory address. */
9664 const reg_entry
*expected_reg
;
9665 static const char *di_si
[][2] =
9671 static const char *bx
[] = { "ebx", "bx", "rbx" };
9673 kind
= "string address";
9675 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9677 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9679 if (!type
.bitfield
.baseindex
9680 || ((!i
.mem_operands
!= !intel_syntax
)
9681 && current_templates
->end
[-1].operand_types
[1]
9682 .bitfield
.baseindex
))
9683 type
= current_templates
->end
[-1].operand_types
[1];
9684 expected_reg
= hash_find (reg_hash
,
9685 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9689 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9691 if (i
.base_reg
!= expected_reg
9693 || operand_type_check (i
.types
[this_operand
], disp
))
9695 /* The second memory operand must have the same size as
9699 && !((addr_mode
== CODE_64BIT
9700 && i
.base_reg
->reg_type
.bitfield
.qword
)
9701 || (addr_mode
== CODE_32BIT
9702 ? i
.base_reg
->reg_type
.bitfield
.dword
9703 : i
.base_reg
->reg_type
.bitfield
.word
)))
9706 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9708 intel_syntax
? '[' : '(',
9710 expected_reg
->reg_name
,
9711 intel_syntax
? ']' : ')');
9718 as_bad (_("`%s' is not a valid %s expression"),
9719 operand_string
, kind
);
9724 if (addr_mode
!= CODE_16BIT
)
9726 /* 32-bit/64-bit checks. */
9728 && ((addr_mode
== CODE_64BIT
9729 ? !i
.base_reg
->reg_type
.bitfield
.qword
9730 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9731 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9732 || i
.base_reg
->reg_num
== RegIZ
))
9734 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9735 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9736 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9737 && ((addr_mode
== CODE_64BIT
9738 ? !i
.index_reg
->reg_type
.bitfield
.qword
9739 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9740 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9743 /* bndmk, bndldx, and bndstx have special restrictions. */
9744 if (current_templates
->start
->base_opcode
== 0xf30f1b
9745 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9747 /* They cannot use RIP-relative addressing. */
9748 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9750 as_bad (_("`%s' cannot be used here"), operand_string
);
9754 /* bndldx and bndstx ignore their scale factor. */
9755 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9756 && i
.log2_scale_factor
)
9757 as_warn (_("register scaling is being ignored here"));
9762 /* 16-bit checks. */
9764 && (!i
.base_reg
->reg_type
.bitfield
.word
9765 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9767 && (!i
.index_reg
->reg_type
.bitfield
.word
9768 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9770 && i
.base_reg
->reg_num
< 6
9771 && i
.index_reg
->reg_num
>= 6
9772 && i
.log2_scale_factor
== 0))))
9779 /* Handle vector immediates. */
9782 RC_SAE_immediate (const char *imm_start
)
9784 unsigned int match_found
, j
;
9785 const char *pstr
= imm_start
;
9793 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9795 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9799 rc_op
.type
= RC_NamesTable
[j
].type
;
9800 rc_op
.operand
= this_operand
;
9801 i
.rounding
= &rc_op
;
9805 as_bad (_("duplicated `%s'"), imm_start
);
9808 pstr
+= RC_NamesTable
[j
].len
;
9818 as_bad (_("Missing '}': '%s'"), imm_start
);
9821 /* RC/SAE immediate string should contain nothing more. */;
9824 as_bad (_("Junk after '}': '%s'"), imm_start
);
9828 exp
= &im_expressions
[i
.imm_operands
++];
9829 i
.op
[this_operand
].imms
= exp
;
9831 exp
->X_op
= O_constant
;
9832 exp
->X_add_number
= 0;
9833 exp
->X_add_symbol
= (symbolS
*) 0;
9834 exp
->X_op_symbol
= (symbolS
*) 0;
9836 i
.types
[this_operand
].bitfield
.imm8
= 1;
9840 /* Only string instructions can have a second memory operand, so
9841 reduce current_templates to just those if it contains any. */
9843 maybe_adjust_templates (void)
9845 const insn_template
*t
;
9847 gas_assert (i
.mem_operands
== 1);
9849 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9850 if (t
->opcode_modifier
.isstring
)
9853 if (t
< current_templates
->end
)
9855 static templates aux_templates
;
9856 bfd_boolean recheck
;
9858 aux_templates
.start
= t
;
9859 for (; t
< current_templates
->end
; ++t
)
9860 if (!t
->opcode_modifier
.isstring
)
9862 aux_templates
.end
= t
;
9864 /* Determine whether to re-check the first memory operand. */
9865 recheck
= (aux_templates
.start
!= current_templates
->start
9866 || t
!= current_templates
->end
);
9868 current_templates
= &aux_templates
;
9873 if (i
.memop1_string
!= NULL
9874 && i386_index_check (i
.memop1_string
) == 0)
9883 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9887 i386_att_operand (char *operand_string
)
9891 char *op_string
= operand_string
;
9893 if (is_space_char (*op_string
))
9896 /* We check for an absolute prefix (differentiating,
9897 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9898 if (*op_string
== ABSOLUTE_PREFIX
)
9901 if (is_space_char (*op_string
))
9903 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9906 /* Check if operand is a register. */
9907 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9909 i386_operand_type temp
;
9911 /* Check for a segment override by searching for ':' after a
9912 segment register. */
9914 if (is_space_char (*op_string
))
9916 if (*op_string
== ':'
9917 && (r
->reg_type
.bitfield
.sreg2
9918 || r
->reg_type
.bitfield
.sreg3
))
9923 i
.seg
[i
.mem_operands
] = &es
;
9926 i
.seg
[i
.mem_operands
] = &cs
;
9929 i
.seg
[i
.mem_operands
] = &ss
;
9932 i
.seg
[i
.mem_operands
] = &ds
;
9935 i
.seg
[i
.mem_operands
] = &fs
;
9938 i
.seg
[i
.mem_operands
] = &gs
;
9942 /* Skip the ':' and whitespace. */
9944 if (is_space_char (*op_string
))
9947 if (!is_digit_char (*op_string
)
9948 && !is_identifier_char (*op_string
)
9949 && *op_string
!= '('
9950 && *op_string
!= ABSOLUTE_PREFIX
)
9952 as_bad (_("bad memory operand `%s'"), op_string
);
9955 /* Handle case of %es:*foo. */
9956 if (*op_string
== ABSOLUTE_PREFIX
)
9959 if (is_space_char (*op_string
))
9961 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9963 goto do_memory_reference
;
9966 /* Handle vector operations. */
9967 if (*op_string
== '{')
9969 op_string
= check_VecOperations (op_string
, NULL
);
9970 if (op_string
== NULL
)
9976 as_bad (_("junk `%s' after register"), op_string
);
9980 temp
.bitfield
.baseindex
= 0;
9981 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9983 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9984 i
.op
[this_operand
].regs
= r
;
9987 else if (*op_string
== REGISTER_PREFIX
)
9989 as_bad (_("bad register name `%s'"), op_string
);
9992 else if (*op_string
== IMMEDIATE_PREFIX
)
9995 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9997 as_bad (_("immediate operand illegal with absolute jump"));
10000 if (!i386_immediate (op_string
))
10003 else if (RC_SAE_immediate (operand_string
))
10005 /* If it is a RC or SAE immediate, do nothing. */
10008 else if (is_digit_char (*op_string
)
10009 || is_identifier_char (*op_string
)
10010 || *op_string
== '"'
10011 || *op_string
== '(')
10013 /* This is a memory reference of some sort. */
10016 /* Start and end of displacement string expression (if found). */
10017 char *displacement_string_start
;
10018 char *displacement_string_end
;
10021 do_memory_reference
:
10022 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10024 if ((i
.mem_operands
== 1
10025 && !current_templates
->start
->opcode_modifier
.isstring
)
10026 || i
.mem_operands
== 2)
10028 as_bad (_("too many memory references for `%s'"),
10029 current_templates
->start
->name
);
10033 /* Check for base index form. We detect the base index form by
10034 looking for an ')' at the end of the operand, searching
10035 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10037 base_string
= op_string
+ strlen (op_string
);
10039 /* Handle vector operations. */
10040 vop_start
= strchr (op_string
, '{');
10041 if (vop_start
&& vop_start
< base_string
)
10043 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10045 base_string
= vop_start
;
10049 if (is_space_char (*base_string
))
10052 /* If we only have a displacement, set-up for it to be parsed later. */
10053 displacement_string_start
= op_string
;
10054 displacement_string_end
= base_string
+ 1;
10056 if (*base_string
== ')')
10059 unsigned int parens_balanced
= 1;
10060 /* We've already checked that the number of left & right ()'s are
10061 equal, so this loop will not be infinite. */
10065 if (*base_string
== ')')
10067 if (*base_string
== '(')
10070 while (parens_balanced
);
10072 temp_string
= base_string
;
10074 /* Skip past '(' and whitespace. */
10076 if (is_space_char (*base_string
))
10079 if (*base_string
== ','
10080 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10083 displacement_string_end
= temp_string
;
10085 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10089 base_string
= end_op
;
10090 if (is_space_char (*base_string
))
10094 /* There may be an index reg or scale factor here. */
10095 if (*base_string
== ',')
10098 if (is_space_char (*base_string
))
10101 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10104 base_string
= end_op
;
10105 if (is_space_char (*base_string
))
10107 if (*base_string
== ',')
10110 if (is_space_char (*base_string
))
10113 else if (*base_string
!= ')')
10115 as_bad (_("expecting `,' or `)' "
10116 "after index register in `%s'"),
10121 else if (*base_string
== REGISTER_PREFIX
)
10123 end_op
= strchr (base_string
, ',');
10126 as_bad (_("bad register name `%s'"), base_string
);
10130 /* Check for scale factor. */
10131 if (*base_string
!= ')')
10133 char *end_scale
= i386_scale (base_string
);
10138 base_string
= end_scale
;
10139 if (is_space_char (*base_string
))
10141 if (*base_string
!= ')')
10143 as_bad (_("expecting `)' "
10144 "after scale factor in `%s'"),
10149 else if (!i
.index_reg
)
10151 as_bad (_("expecting index register or scale factor "
10152 "after `,'; got '%c'"),
10157 else if (*base_string
!= ')')
10159 as_bad (_("expecting `,' or `)' "
10160 "after base register in `%s'"),
10165 else if (*base_string
== REGISTER_PREFIX
)
10167 end_op
= strchr (base_string
, ',');
10170 as_bad (_("bad register name `%s'"), base_string
);
10175 /* If there's an expression beginning the operand, parse it,
10176 assuming displacement_string_start and
10177 displacement_string_end are meaningful. */
10178 if (displacement_string_start
!= displacement_string_end
)
10180 if (!i386_displacement (displacement_string_start
,
10181 displacement_string_end
))
10185 /* Special case for (%dx) while doing input/output op. */
10187 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10188 && i
.index_reg
== 0
10189 && i
.log2_scale_factor
== 0
10190 && i
.seg
[i
.mem_operands
] == 0
10191 && !operand_type_check (i
.types
[this_operand
], disp
))
10193 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10197 if (i386_index_check (operand_string
) == 0)
10199 i
.flags
[this_operand
] |= Operand_Mem
;
10200 if (i
.mem_operands
== 0)
10201 i
.memop1_string
= xstrdup (operand_string
);
10206 /* It's not a memory operand; argh! */
10207 as_bad (_("invalid char %s beginning operand %d `%s'"),
10208 output_invalid (*op_string
),
10213 return 1; /* Normal return. */
10216 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10217 that an rs_machine_dependent frag may reach. */
10220 i386_frag_max_var (fragS
*frag
)
10222 /* The only relaxable frags are for jumps.
10223 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10224 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10225 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10230 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10232 /* STT_GNU_IFUNC symbol must go through PLT. */
10233 if ((symbol_get_bfdsym (fr_symbol
)->flags
10234 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10237 if (!S_IS_EXTERNAL (fr_symbol
))
10238 /* Symbol may be weak or local. */
10239 return !S_IS_WEAK (fr_symbol
);
10241 /* Global symbols with non-default visibility can't be preempted. */
10242 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10245 if (fr_var
!= NO_RELOC
)
10246 switch ((enum bfd_reloc_code_real
) fr_var
)
10248 case BFD_RELOC_386_PLT32
:
10249 case BFD_RELOC_X86_64_PLT32
:
10250 /* Symbol with PLT relocation may be preempted. */
10256 /* Global symbols with default visibility in a shared library may be
10257 preempted by another definition. */
10262 /* md_estimate_size_before_relax()
10264 Called just before relax() for rs_machine_dependent frags. The x86
10265 assembler uses these frags to handle variable size jump
10268 Any symbol that is now undefined will not become defined.
10269 Return the correct fr_subtype in the frag.
10270 Return the initial "guess for variable size of frag" to caller.
10271 The guess is actually the growth beyond the fixed part. Whatever
10272 we do to grow the fixed or variable part contributes to our
10276 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10278 /* We've already got fragP->fr_subtype right; all we have to do is
10279 check for un-relaxable symbols. On an ELF system, we can't relax
10280 an externally visible symbol, because it may be overridden by a
10282 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10285 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10288 #if defined (OBJ_COFF) && defined (TE_PE)
10289 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10290 && S_IS_WEAK (fragP
->fr_symbol
))
10294 /* Symbol is undefined in this segment, or we need to keep a
10295 reloc so that weak symbols can be overridden. */
10296 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10297 enum bfd_reloc_code_real reloc_type
;
10298 unsigned char *opcode
;
10301 if (fragP
->fr_var
!= NO_RELOC
)
10302 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10303 else if (size
== 2)
10304 reloc_type
= BFD_RELOC_16_PCREL
;
10305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10306 else if (need_plt32_p (fragP
->fr_symbol
))
10307 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10310 reloc_type
= BFD_RELOC_32_PCREL
;
10312 old_fr_fix
= fragP
->fr_fix
;
10313 opcode
= (unsigned char *) fragP
->fr_opcode
;
10315 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10318 /* Make jmp (0xeb) a (d)word displacement jump. */
10320 fragP
->fr_fix
+= size
;
10321 fix_new (fragP
, old_fr_fix
, size
,
10323 fragP
->fr_offset
, 1,
10329 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10331 /* Negate the condition, and branch past an
10332 unconditional jump. */
10335 /* Insert an unconditional jump. */
10337 /* We added two extra opcode bytes, and have a two byte
10339 fragP
->fr_fix
+= 2 + 2;
10340 fix_new (fragP
, old_fr_fix
+ 2, 2,
10342 fragP
->fr_offset
, 1,
10346 /* Fall through. */
10349 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10353 fragP
->fr_fix
+= 1;
10354 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10356 fragP
->fr_offset
, 1,
10357 BFD_RELOC_8_PCREL
);
10358 fixP
->fx_signed
= 1;
10362 /* This changes the byte-displacement jump 0x7N
10363 to the (d)word-displacement jump 0x0f,0x8N. */
10364 opcode
[1] = opcode
[0] + 0x10;
10365 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10366 /* We've added an opcode byte. */
10367 fragP
->fr_fix
+= 1 + size
;
10368 fix_new (fragP
, old_fr_fix
+ 1, size
,
10370 fragP
->fr_offset
, 1,
10375 BAD_CASE (fragP
->fr_subtype
);
10379 return fragP
->fr_fix
- old_fr_fix
;
10382 /* Guess size depending on current relax state. Initially the relax
10383 state will correspond to a short jump and we return 1, because
10384 the variable part of the frag (the branch offset) is one byte
10385 long. However, we can relax a section more than once and in that
10386 case we must either set fr_subtype back to the unrelaxed state,
10387 or return the value for the appropriate branch. */
10388 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10391 /* Called after relax() is finished.
10393 In: Address of frag.
10394 fr_type == rs_machine_dependent.
10395 fr_subtype is what the address relaxed to.
10397 Out: Any fixSs and constants are set up.
10398 Caller will turn frag into a ".space 0". */
10401 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10404 unsigned char *opcode
;
10405 unsigned char *where_to_put_displacement
= NULL
;
10406 offsetT target_address
;
10407 offsetT opcode_address
;
10408 unsigned int extension
= 0;
10409 offsetT displacement_from_opcode_start
;
10411 opcode
= (unsigned char *) fragP
->fr_opcode
;
10413 /* Address we want to reach in file space. */
10414 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10416 /* Address opcode resides at in file space. */
10417 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10419 /* Displacement from opcode start to fill into instruction. */
10420 displacement_from_opcode_start
= target_address
- opcode_address
;
10422 if ((fragP
->fr_subtype
& BIG
) == 0)
10424 /* Don't have to change opcode. */
10425 extension
= 1; /* 1 opcode + 1 displacement */
10426 where_to_put_displacement
= &opcode
[1];
10430 if (no_cond_jump_promotion
10431 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10432 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10433 _("long jump required"));
10435 switch (fragP
->fr_subtype
)
10437 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10438 extension
= 4; /* 1 opcode + 4 displacement */
10440 where_to_put_displacement
= &opcode
[1];
10443 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10444 extension
= 2; /* 1 opcode + 2 displacement */
10446 where_to_put_displacement
= &opcode
[1];
10449 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10450 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10451 extension
= 5; /* 2 opcode + 4 displacement */
10452 opcode
[1] = opcode
[0] + 0x10;
10453 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10454 where_to_put_displacement
= &opcode
[2];
10457 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10458 extension
= 3; /* 2 opcode + 2 displacement */
10459 opcode
[1] = opcode
[0] + 0x10;
10460 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10461 where_to_put_displacement
= &opcode
[2];
10464 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10469 where_to_put_displacement
= &opcode
[3];
10473 BAD_CASE (fragP
->fr_subtype
);
10478 /* If size if less then four we are sure that the operand fits,
10479 but if it's 4, then it could be that the displacement is larger
10481 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10483 && ((addressT
) (displacement_from_opcode_start
- extension
10484 + ((addressT
) 1 << 31))
10485 > (((addressT
) 2 << 31) - 1)))
10487 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10488 _("jump target out of range"));
10489 /* Make us emit 0. */
10490 displacement_from_opcode_start
= extension
;
10492 /* Now put displacement after opcode. */
10493 md_number_to_chars ((char *) where_to_put_displacement
,
10494 (valueT
) (displacement_from_opcode_start
- extension
),
10495 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10496 fragP
->fr_fix
+= extension
;
10499 /* Apply a fixup (fixP) to segment data, once it has been determined
10500 by our caller that we have all the info we need to fix it up.
10502 Parameter valP is the pointer to the value of the bits.
10504 On the 386, immediates, displacements, and data pointers are all in
10505 the same (little-endian) format, so we don't need to care about which
10506 we are handling. */
10509 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10511 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10512 valueT value
= *valP
;
10514 #if !defined (TE_Mach)
10515 if (fixP
->fx_pcrel
)
10517 switch (fixP
->fx_r_type
)
10523 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10526 case BFD_RELOC_X86_64_32S
:
10527 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10530 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10533 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10538 if (fixP
->fx_addsy
!= NULL
10539 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10540 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10541 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10542 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10543 && !use_rela_relocations
)
10545 /* This is a hack. There should be a better way to handle this.
10546 This covers for the fact that bfd_install_relocation will
10547 subtract the current location (for partial_inplace, PC relative
10548 relocations); see more below. */
10552 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10555 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10560 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10562 if ((sym_seg
== seg
10563 || (symbol_section_p (fixP
->fx_addsy
)
10564 && sym_seg
!= absolute_section
))
10565 && !generic_force_reloc (fixP
))
10567 /* Yes, we add the values in twice. This is because
10568 bfd_install_relocation subtracts them out again. I think
10569 bfd_install_relocation is broken, but I don't dare change
10571 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10575 #if defined (OBJ_COFF) && defined (TE_PE)
10576 /* For some reason, the PE format does not store a
10577 section address offset for a PC relative symbol. */
10578 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10579 || S_IS_WEAK (fixP
->fx_addsy
))
10580 value
+= md_pcrel_from (fixP
);
10583 #if defined (OBJ_COFF) && defined (TE_PE)
10584 if (fixP
->fx_addsy
!= NULL
10585 && S_IS_WEAK (fixP
->fx_addsy
)
10586 /* PR 16858: Do not modify weak function references. */
10587 && ! fixP
->fx_pcrel
)
10589 #if !defined (TE_PEP)
10590 /* For x86 PE weak function symbols are neither PC-relative
10591 nor do they set S_IS_FUNCTION. So the only reliable way
10592 to detect them is to check the flags of their containing
10594 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10595 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10599 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10603 /* Fix a few things - the dynamic linker expects certain values here,
10604 and we must not disappoint it. */
10605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10606 if (IS_ELF
&& fixP
->fx_addsy
)
10607 switch (fixP
->fx_r_type
)
10609 case BFD_RELOC_386_PLT32
:
10610 case BFD_RELOC_X86_64_PLT32
:
10611 /* Make the jump instruction point to the address of the operand.
10612 At runtime we merely add the offset to the actual PLT entry.
10613 NB: Subtract the offset size only for jump instructions. */
10614 if (fixP
->fx_pcrel
)
10618 case BFD_RELOC_386_TLS_GD
:
10619 case BFD_RELOC_386_TLS_LDM
:
10620 case BFD_RELOC_386_TLS_IE_32
:
10621 case BFD_RELOC_386_TLS_IE
:
10622 case BFD_RELOC_386_TLS_GOTIE
:
10623 case BFD_RELOC_386_TLS_GOTDESC
:
10624 case BFD_RELOC_X86_64_TLSGD
:
10625 case BFD_RELOC_X86_64_TLSLD
:
10626 case BFD_RELOC_X86_64_GOTTPOFF
:
10627 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10628 value
= 0; /* Fully resolved at runtime. No addend. */
10630 case BFD_RELOC_386_TLS_LE
:
10631 case BFD_RELOC_386_TLS_LDO_32
:
10632 case BFD_RELOC_386_TLS_LE_32
:
10633 case BFD_RELOC_X86_64_DTPOFF32
:
10634 case BFD_RELOC_X86_64_DTPOFF64
:
10635 case BFD_RELOC_X86_64_TPOFF32
:
10636 case BFD_RELOC_X86_64_TPOFF64
:
10637 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10640 case BFD_RELOC_386_TLS_DESC_CALL
:
10641 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10642 value
= 0; /* Fully resolved at runtime. No addend. */
10643 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10647 case BFD_RELOC_VTABLE_INHERIT
:
10648 case BFD_RELOC_VTABLE_ENTRY
:
10655 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10657 #endif /* !defined (TE_Mach) */
10659 /* Are we finished with this relocation now? */
10660 if (fixP
->fx_addsy
== NULL
)
10662 #if defined (OBJ_COFF) && defined (TE_PE)
10663 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10666 /* Remember value for tc_gen_reloc. */
10667 fixP
->fx_addnumber
= value
;
10668 /* Clear out the frag for now. */
10672 else if (use_rela_relocations
)
10674 fixP
->fx_no_overflow
= 1;
10675 /* Remember value for tc_gen_reloc. */
10676 fixP
->fx_addnumber
= value
;
10680 md_number_to_chars (p
, value
, fixP
->fx_size
);
10684 md_atof (int type
, char *litP
, int *sizeP
)
10686 /* This outputs the LITTLENUMs in REVERSE order;
10687 in accord with the bigendian 386. */
10688 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10691 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10694 output_invalid (int c
)
10697 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10700 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10701 "(0x%x)", (unsigned char) c
);
10702 return output_invalid_buf
;
10705 /* REG_STRING starts *before* REGISTER_PREFIX. */
10707 static const reg_entry
*
10708 parse_real_register (char *reg_string
, char **end_op
)
10710 char *s
= reg_string
;
10712 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10713 const reg_entry
*r
;
10715 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10716 if (*s
== REGISTER_PREFIX
)
10719 if (is_space_char (*s
))
10722 p
= reg_name_given
;
10723 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10725 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10726 return (const reg_entry
*) NULL
;
10730 /* For naked regs, make sure that we are not dealing with an identifier.
10731 This prevents confusing an identifier like `eax_var' with register
10733 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10734 return (const reg_entry
*) NULL
;
10738 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10740 /* Handle floating point regs, allowing spaces in the (i) part. */
10741 if (r
== i386_regtab
/* %st is first entry of table */)
10743 if (!cpu_arch_flags
.bitfield
.cpu8087
10744 && !cpu_arch_flags
.bitfield
.cpu287
10745 && !cpu_arch_flags
.bitfield
.cpu387
)
10746 return (const reg_entry
*) NULL
;
10748 if (is_space_char (*s
))
10753 if (is_space_char (*s
))
10755 if (*s
>= '0' && *s
<= '7')
10757 int fpr
= *s
- '0';
10759 if (is_space_char (*s
))
10764 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10769 /* We have "%st(" then garbage. */
10770 return (const reg_entry
*) NULL
;
10774 if (r
== NULL
|| allow_pseudo_reg
)
10777 if (operand_type_all_zero (&r
->reg_type
))
10778 return (const reg_entry
*) NULL
;
10780 if ((r
->reg_type
.bitfield
.dword
10781 || r
->reg_type
.bitfield
.sreg3
10782 || r
->reg_type
.bitfield
.control
10783 || r
->reg_type
.bitfield
.debug
10784 || r
->reg_type
.bitfield
.test
)
10785 && !cpu_arch_flags
.bitfield
.cpui386
)
10786 return (const reg_entry
*) NULL
;
10788 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10789 return (const reg_entry
*) NULL
;
10791 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10793 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10794 return (const reg_entry
*) NULL
;
10796 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10798 if (r
->reg_type
.bitfield
.ymmword
)
10799 return (const reg_entry
*) NULL
;
10801 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10802 return (const reg_entry
*) NULL
;
10806 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10807 return (const reg_entry
*) NULL
;
10809 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10810 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10811 return (const reg_entry
*) NULL
;
10813 /* Upper 16 vector registers are only available with VREX in 64bit
10814 mode, and require EVEX encoding. */
10815 if (r
->reg_flags
& RegVRex
)
10817 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10818 || flag_code
!= CODE_64BIT
)
10819 return (const reg_entry
*) NULL
;
10821 i
.vec_encoding
= vex_encoding_evex
;
10824 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10825 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10826 && flag_code
!= CODE_64BIT
)
10827 return (const reg_entry
*) NULL
;
10829 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10830 return (const reg_entry
*) NULL
;
10835 /* REG_STRING starts *before* REGISTER_PREFIX. */
10837 static const reg_entry
*
10838 parse_register (char *reg_string
, char **end_op
)
10840 const reg_entry
*r
;
10842 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10843 r
= parse_real_register (reg_string
, end_op
);
10848 char *save
= input_line_pointer
;
10852 input_line_pointer
= reg_string
;
10853 c
= get_symbol_name (®_string
);
10854 symbolP
= symbol_find (reg_string
);
10855 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10857 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10859 know (e
->X_op
== O_register
);
10860 know (e
->X_add_number
>= 0
10861 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10862 r
= i386_regtab
+ e
->X_add_number
;
10863 if ((r
->reg_flags
& RegVRex
))
10864 i
.vec_encoding
= vex_encoding_evex
;
10865 *end_op
= input_line_pointer
;
10867 *input_line_pointer
= c
;
10868 input_line_pointer
= save
;
10874 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10876 const reg_entry
*r
;
10877 char *end
= input_line_pointer
;
10880 r
= parse_register (name
, &input_line_pointer
);
10881 if (r
&& end
<= input_line_pointer
)
10883 *nextcharP
= *input_line_pointer
;
10884 *input_line_pointer
= 0;
10885 e
->X_op
= O_register
;
10886 e
->X_add_number
= r
- i386_regtab
;
10889 input_line_pointer
= end
;
10891 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10895 md_operand (expressionS
*e
)
10898 const reg_entry
*r
;
10900 switch (*input_line_pointer
)
10902 case REGISTER_PREFIX
:
10903 r
= parse_real_register (input_line_pointer
, &end
);
10906 e
->X_op
= O_register
;
10907 e
->X_add_number
= r
- i386_regtab
;
10908 input_line_pointer
= end
;
10913 gas_assert (intel_syntax
);
10914 end
= input_line_pointer
++;
10916 if (*input_line_pointer
== ']')
10918 ++input_line_pointer
;
10919 e
->X_op_symbol
= make_expr_symbol (e
);
10920 e
->X_add_symbol
= NULL
;
10921 e
->X_add_number
= 0;
10926 e
->X_op
= O_absent
;
10927 input_line_pointer
= end
;
10934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10935 const char *md_shortopts
= "kVQ:sqnO::";
10937 const char *md_shortopts
= "qnO::";
10940 #define OPTION_32 (OPTION_MD_BASE + 0)
10941 #define OPTION_64 (OPTION_MD_BASE + 1)
10942 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10943 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10944 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10945 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10946 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10947 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10948 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10949 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10950 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10951 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10952 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10953 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10954 #define OPTION_X32 (OPTION_MD_BASE + 14)
10955 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10956 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10957 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10958 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10959 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10960 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10961 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10962 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10963 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10964 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10965 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10966 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10968 struct option md_longopts
[] =
10970 {"32", no_argument
, NULL
, OPTION_32
},
10971 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10972 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10973 {"64", no_argument
, NULL
, OPTION_64
},
10975 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10976 {"x32", no_argument
, NULL
, OPTION_X32
},
10977 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10978 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10980 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10981 {"march", required_argument
, NULL
, OPTION_MARCH
},
10982 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10983 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10984 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10985 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10986 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10987 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10988 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10989 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10990 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10991 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
10992 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10993 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10994 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10995 # if defined (TE_PE) || defined (TE_PEP)
10996 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10998 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10999 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11000 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11001 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11002 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11003 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11004 {NULL
, no_argument
, NULL
, 0}
11006 size_t md_longopts_size
= sizeof (md_longopts
);
11009 md_parse_option (int c
, const char *arg
)
11012 char *arch
, *next
, *saved
;
11017 optimize_align_code
= 0;
11021 quiet_warnings
= 1;
11024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11025 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11026 should be emitted or not. FIXME: Not implemented. */
11030 /* -V: SVR4 argument to print version ID. */
11032 print_version_id ();
11035 /* -k: Ignore for FreeBSD compatibility. */
11040 /* -s: On i386 Solaris, this tells the native assembler to use
11041 .stab instead of .stab.excl. We always use .stab anyhow. */
11044 case OPTION_MSHARED
:
11048 case OPTION_X86_USED_NOTE
:
11049 if (strcasecmp (arg
, "yes") == 0)
11051 else if (strcasecmp (arg
, "no") == 0)
11054 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11059 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11060 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11063 const char **list
, **l
;
11065 list
= bfd_target_list ();
11066 for (l
= list
; *l
!= NULL
; l
++)
11067 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11068 || strcmp (*l
, "coff-x86-64") == 0
11069 || strcmp (*l
, "pe-x86-64") == 0
11070 || strcmp (*l
, "pei-x86-64") == 0
11071 || strcmp (*l
, "mach-o-x86-64") == 0)
11073 default_arch
= "x86_64";
11077 as_fatal (_("no compiled in support for x86_64"));
11083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11087 const char **list
, **l
;
11089 list
= bfd_target_list ();
11090 for (l
= list
; *l
!= NULL
; l
++)
11091 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11093 default_arch
= "x86_64:32";
11097 as_fatal (_("no compiled in support for 32bit x86_64"));
11101 as_fatal (_("32bit x86_64 is only supported for ELF"));
11106 default_arch
= "i386";
11109 case OPTION_DIVIDE
:
11110 #ifdef SVR4_COMMENT_CHARS
11115 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11117 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11121 i386_comment_chars
= n
;
11127 saved
= xstrdup (arg
);
11129 /* Allow -march=+nosse. */
11135 as_fatal (_("invalid -march= option: `%s'"), arg
);
11136 next
= strchr (arch
, '+');
11139 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11141 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11144 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11147 cpu_arch_name
= cpu_arch
[j
].name
;
11148 cpu_sub_arch_name
= NULL
;
11149 cpu_arch_flags
= cpu_arch
[j
].flags
;
11150 cpu_arch_isa
= cpu_arch
[j
].type
;
11151 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11152 if (!cpu_arch_tune_set
)
11154 cpu_arch_tune
= cpu_arch_isa
;
11155 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11159 else if (*cpu_arch
[j
].name
== '.'
11160 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11162 /* ISA extension. */
11163 i386_cpu_flags flags
;
11165 flags
= cpu_flags_or (cpu_arch_flags
,
11166 cpu_arch
[j
].flags
);
11168 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11170 if (cpu_sub_arch_name
)
11172 char *name
= cpu_sub_arch_name
;
11173 cpu_sub_arch_name
= concat (name
,
11175 (const char *) NULL
);
11179 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11180 cpu_arch_flags
= flags
;
11181 cpu_arch_isa_flags
= flags
;
11185 = cpu_flags_or (cpu_arch_isa_flags
,
11186 cpu_arch
[j
].flags
);
11191 if (j
>= ARRAY_SIZE (cpu_arch
))
11193 /* Disable an ISA extension. */
11194 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11195 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11197 i386_cpu_flags flags
;
11199 flags
= cpu_flags_and_not (cpu_arch_flags
,
11200 cpu_noarch
[j
].flags
);
11201 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11203 if (cpu_sub_arch_name
)
11205 char *name
= cpu_sub_arch_name
;
11206 cpu_sub_arch_name
= concat (arch
,
11207 (const char *) NULL
);
11211 cpu_sub_arch_name
= xstrdup (arch
);
11212 cpu_arch_flags
= flags
;
11213 cpu_arch_isa_flags
= flags
;
11218 if (j
>= ARRAY_SIZE (cpu_noarch
))
11219 j
= ARRAY_SIZE (cpu_arch
);
11222 if (j
>= ARRAY_SIZE (cpu_arch
))
11223 as_fatal (_("invalid -march= option: `%s'"), arg
);
11227 while (next
!= NULL
);
11233 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11234 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11236 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11238 cpu_arch_tune_set
= 1;
11239 cpu_arch_tune
= cpu_arch
[j
].type
;
11240 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11244 if (j
>= ARRAY_SIZE (cpu_arch
))
11245 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11248 case OPTION_MMNEMONIC
:
11249 if (strcasecmp (arg
, "att") == 0)
11250 intel_mnemonic
= 0;
11251 else if (strcasecmp (arg
, "intel") == 0)
11252 intel_mnemonic
= 1;
11254 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11257 case OPTION_MSYNTAX
:
11258 if (strcasecmp (arg
, "att") == 0)
11260 else if (strcasecmp (arg
, "intel") == 0)
11263 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11266 case OPTION_MINDEX_REG
:
11267 allow_index_reg
= 1;
11270 case OPTION_MNAKED_REG
:
11271 allow_naked_reg
= 1;
11274 case OPTION_MSSE2AVX
:
11278 case OPTION_MSSE_CHECK
:
11279 if (strcasecmp (arg
, "error") == 0)
11280 sse_check
= check_error
;
11281 else if (strcasecmp (arg
, "warning") == 0)
11282 sse_check
= check_warning
;
11283 else if (strcasecmp (arg
, "none") == 0)
11284 sse_check
= check_none
;
11286 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11289 case OPTION_MOPERAND_CHECK
:
11290 if (strcasecmp (arg
, "error") == 0)
11291 operand_check
= check_error
;
11292 else if (strcasecmp (arg
, "warning") == 0)
11293 operand_check
= check_warning
;
11294 else if (strcasecmp (arg
, "none") == 0)
11295 operand_check
= check_none
;
11297 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11300 case OPTION_MAVXSCALAR
:
11301 if (strcasecmp (arg
, "128") == 0)
11302 avxscalar
= vex128
;
11303 else if (strcasecmp (arg
, "256") == 0)
11304 avxscalar
= vex256
;
11306 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11309 case OPTION_MVEXWIG
:
11310 if (strcmp (arg
, "0") == 0)
11312 else if (strcmp (arg
, "1") == 0)
11315 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11318 case OPTION_MADD_BND_PREFIX
:
11319 add_bnd_prefix
= 1;
11322 case OPTION_MEVEXLIG
:
11323 if (strcmp (arg
, "128") == 0)
11324 evexlig
= evexl128
;
11325 else if (strcmp (arg
, "256") == 0)
11326 evexlig
= evexl256
;
11327 else if (strcmp (arg
, "512") == 0)
11328 evexlig
= evexl512
;
11330 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11333 case OPTION_MEVEXRCIG
:
11334 if (strcmp (arg
, "rne") == 0)
11336 else if (strcmp (arg
, "rd") == 0)
11338 else if (strcmp (arg
, "ru") == 0)
11340 else if (strcmp (arg
, "rz") == 0)
11343 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11346 case OPTION_MEVEXWIG
:
11347 if (strcmp (arg
, "0") == 0)
11349 else if (strcmp (arg
, "1") == 0)
11352 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11355 # if defined (TE_PE) || defined (TE_PEP)
11356 case OPTION_MBIG_OBJ
:
11361 case OPTION_MOMIT_LOCK_PREFIX
:
11362 if (strcasecmp (arg
, "yes") == 0)
11363 omit_lock_prefix
= 1;
11364 else if (strcasecmp (arg
, "no") == 0)
11365 omit_lock_prefix
= 0;
11367 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11370 case OPTION_MFENCE_AS_LOCK_ADD
:
11371 if (strcasecmp (arg
, "yes") == 0)
11373 else if (strcasecmp (arg
, "no") == 0)
11376 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11379 case OPTION_MRELAX_RELOCATIONS
:
11380 if (strcasecmp (arg
, "yes") == 0)
11381 generate_relax_relocations
= 1;
11382 else if (strcasecmp (arg
, "no") == 0)
11383 generate_relax_relocations
= 0;
11385 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11388 case OPTION_MAMD64
:
11392 case OPTION_MINTEL64
:
11400 /* Turn off -Os. */
11401 optimize_for_space
= 0;
11403 else if (*arg
== 's')
11405 optimize_for_space
= 1;
11406 /* Turn on all encoding optimizations. */
11407 optimize
= INT_MAX
;
11411 optimize
= atoi (arg
);
11412 /* Turn off -Os. */
11413 optimize_for_space
= 0;
11423 #define MESSAGE_TEMPLATE \
11427 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11428 int *left_p
, const char *name
, int len
)
11430 int size
= sizeof (MESSAGE_TEMPLATE
);
11431 int left
= *left_p
;
11433 /* Reserve 2 spaces for ", " or ",\0" */
11436 /* Check if there is any room. */
11444 p
= mempcpy (p
, name
, len
);
11448 /* Output the current message now and start a new one. */
11451 fprintf (stream
, "%s\n", message
);
11453 left
= size
- (start
- message
) - len
- 2;
11455 gas_assert (left
>= 0);
11457 p
= mempcpy (p
, name
, len
);
11465 show_arch (FILE *stream
, int ext
, int check
)
11467 static char message
[] = MESSAGE_TEMPLATE
;
11468 char *start
= message
+ 27;
11470 int size
= sizeof (MESSAGE_TEMPLATE
);
11477 left
= size
- (start
- message
);
11478 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11480 /* Should it be skipped? */
11481 if (cpu_arch
[j
].skip
)
11484 name
= cpu_arch
[j
].name
;
11485 len
= cpu_arch
[j
].len
;
11488 /* It is an extension. Skip if we aren't asked to show it. */
11499 /* It is an processor. Skip if we show only extension. */
11502 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11504 /* It is an impossible processor - skip. */
11508 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11511 /* Display disabled extensions. */
11513 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11515 name
= cpu_noarch
[j
].name
;
11516 len
= cpu_noarch
[j
].len
;
11517 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11522 fprintf (stream
, "%s\n", message
);
11526 md_show_usage (FILE *stream
)
11528 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11529 fprintf (stream
, _("\
11531 -V print assembler version number\n\
11534 fprintf (stream
, _("\
11535 -n Do not optimize code alignment\n\
11536 -q quieten some warnings\n"));
11537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11538 fprintf (stream
, _("\
11541 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11542 || defined (TE_PE) || defined (TE_PEP))
11543 fprintf (stream
, _("\
11544 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11546 #ifdef SVR4_COMMENT_CHARS
11547 fprintf (stream
, _("\
11548 --divide do not treat `/' as a comment character\n"));
11550 fprintf (stream
, _("\
11551 --divide ignored\n"));
11553 fprintf (stream
, _("\
11554 -march=CPU[,+EXTENSION...]\n\
11555 generate code for CPU and EXTENSION, CPU is one of:\n"));
11556 show_arch (stream
, 0, 1);
11557 fprintf (stream
, _("\
11558 EXTENSION is combination of:\n"));
11559 show_arch (stream
, 1, 0);
11560 fprintf (stream
, _("\
11561 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11562 show_arch (stream
, 0, 0);
11563 fprintf (stream
, _("\
11564 -msse2avx encode SSE instructions with VEX prefix\n"));
11565 fprintf (stream
, _("\
11566 -msse-check=[none|error|warning] (default: warning)\n\
11567 check SSE instructions\n"));
11568 fprintf (stream
, _("\
11569 -moperand-check=[none|error|warning] (default: warning)\n\
11570 check operand combinations for validity\n"));
11571 fprintf (stream
, _("\
11572 -mavxscalar=[128|256] (default: 128)\n\
11573 encode scalar AVX instructions with specific vector\n\
11575 fprintf (stream
, _("\
11576 -mvexwig=[0|1] (default: 0)\n\
11577 encode VEX instructions with specific VEX.W value\n\
11578 for VEX.W bit ignored instructions\n"));
11579 fprintf (stream
, _("\
11580 -mevexlig=[128|256|512] (default: 128)\n\
11581 encode scalar EVEX instructions with specific vector\n\
11583 fprintf (stream
, _("\
11584 -mevexwig=[0|1] (default: 0)\n\
11585 encode EVEX instructions with specific EVEX.W value\n\
11586 for EVEX.W bit ignored instructions\n"));
11587 fprintf (stream
, _("\
11588 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11589 encode EVEX instructions with specific EVEX.RC value\n\
11590 for SAE-only ignored instructions\n"));
11591 fprintf (stream
, _("\
11592 -mmnemonic=[att|intel] "));
11593 if (SYSV386_COMPAT
)
11594 fprintf (stream
, _("(default: att)\n"));
11596 fprintf (stream
, _("(default: intel)\n"));
11597 fprintf (stream
, _("\
11598 use AT&T/Intel mnemonic\n"));
11599 fprintf (stream
, _("\
11600 -msyntax=[att|intel] (default: att)\n\
11601 use AT&T/Intel syntax\n"));
11602 fprintf (stream
, _("\
11603 -mindex-reg support pseudo index registers\n"));
11604 fprintf (stream
, _("\
11605 -mnaked-reg don't require `%%' prefix for registers\n"));
11606 fprintf (stream
, _("\
11607 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11609 fprintf (stream
, _("\
11610 -mshared disable branch optimization for shared code\n"));
11611 fprintf (stream
, _("\
11612 -mx86-used-note=[no|yes] "));
11613 if (DEFAULT_X86_USED_NOTE
)
11614 fprintf (stream
, _("(default: yes)\n"));
11616 fprintf (stream
, _("(default: no)\n"));
11617 fprintf (stream
, _("\
11618 generate x86 used ISA and feature properties\n"));
11620 #if defined (TE_PE) || defined (TE_PEP)
11621 fprintf (stream
, _("\
11622 -mbig-obj generate big object files\n"));
11624 fprintf (stream
, _("\
11625 -momit-lock-prefix=[no|yes] (default: no)\n\
11626 strip all lock prefixes\n"));
11627 fprintf (stream
, _("\
11628 -mfence-as-lock-add=[no|yes] (default: no)\n\
11629 encode lfence, mfence and sfence as\n\
11630 lock addl $0x0, (%%{re}sp)\n"));
11631 fprintf (stream
, _("\
11632 -mrelax-relocations=[no|yes] "));
11633 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11634 fprintf (stream
, _("(default: yes)\n"));
11636 fprintf (stream
, _("(default: no)\n"));
11637 fprintf (stream
, _("\
11638 generate relax relocations\n"));
11639 fprintf (stream
, _("\
11640 -mamd64 accept only AMD64 ISA [default]\n"));
11641 fprintf (stream
, _("\
11642 -mintel64 accept only Intel64 ISA\n"));
11645 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11646 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11647 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11649 /* Pick the target format to use. */
11652 i386_target_format (void)
11654 if (!strncmp (default_arch
, "x86_64", 6))
11656 update_code_flag (CODE_64BIT
, 1);
11657 if (default_arch
[6] == '\0')
11658 x86_elf_abi
= X86_64_ABI
;
11660 x86_elf_abi
= X86_64_X32_ABI
;
11662 else if (!strcmp (default_arch
, "i386"))
11663 update_code_flag (CODE_32BIT
, 1);
11664 else if (!strcmp (default_arch
, "iamcu"))
11666 update_code_flag (CODE_32BIT
, 1);
11667 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11669 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11670 cpu_arch_name
= "iamcu";
11671 cpu_sub_arch_name
= NULL
;
11672 cpu_arch_flags
= iamcu_flags
;
11673 cpu_arch_isa
= PROCESSOR_IAMCU
;
11674 cpu_arch_isa_flags
= iamcu_flags
;
11675 if (!cpu_arch_tune_set
)
11677 cpu_arch_tune
= cpu_arch_isa
;
11678 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11681 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11682 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11686 as_fatal (_("unknown architecture"));
11688 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11689 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11690 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11691 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11693 switch (OUTPUT_FLAVOR
)
11695 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11696 case bfd_target_aout_flavour
:
11697 return AOUT_TARGET_FORMAT
;
11699 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11700 # if defined (TE_PE) || defined (TE_PEP)
11701 case bfd_target_coff_flavour
:
11702 if (flag_code
== CODE_64BIT
)
11703 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11706 # elif defined (TE_GO32)
11707 case bfd_target_coff_flavour
:
11708 return "coff-go32";
11710 case bfd_target_coff_flavour
:
11711 return "coff-i386";
11714 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11715 case bfd_target_elf_flavour
:
11717 const char *format
;
11719 switch (x86_elf_abi
)
11722 format
= ELF_TARGET_FORMAT
;
11725 use_rela_relocations
= 1;
11727 format
= ELF_TARGET_FORMAT64
;
11729 case X86_64_X32_ABI
:
11730 use_rela_relocations
= 1;
11732 disallow_64bit_reloc
= 1;
11733 format
= ELF_TARGET_FORMAT32
;
11736 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11738 if (x86_elf_abi
!= X86_64_ABI
)
11739 as_fatal (_("Intel L1OM is 64bit only"));
11740 return ELF_TARGET_L1OM_FORMAT
;
11742 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11744 if (x86_elf_abi
!= X86_64_ABI
)
11745 as_fatal (_("Intel K1OM is 64bit only"));
11746 return ELF_TARGET_K1OM_FORMAT
;
11748 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11750 if (x86_elf_abi
!= I386_ABI
)
11751 as_fatal (_("Intel MCU is 32bit only"));
11752 return ELF_TARGET_IAMCU_FORMAT
;
11758 #if defined (OBJ_MACH_O)
11759 case bfd_target_mach_o_flavour
:
11760 if (flag_code
== CODE_64BIT
)
11762 use_rela_relocations
= 1;
11764 return "mach-o-x86-64";
11767 return "mach-o-i386";
11775 #endif /* OBJ_MAYBE_ more than one */
11778 md_undefined_symbol (char *name
)
11780 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11781 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11782 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11783 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11787 if (symbol_find (name
))
11788 as_bad (_("GOT already in symbol table"));
11789 GOT_symbol
= symbol_new (name
, undefined_section
,
11790 (valueT
) 0, &zero_address_frag
);
11797 /* Round up a section size to the appropriate boundary. */
11800 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11802 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11803 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11805 /* For a.out, force the section size to be aligned. If we don't do
11806 this, BFD will align it for us, but it will not write out the
11807 final bytes of the section. This may be a bug in BFD, but it is
11808 easier to fix it here since that is how the other a.out targets
11812 align
= bfd_get_section_alignment (stdoutput
, segment
);
11813 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11820 /* On the i386, PC-relative offsets are relative to the start of the
11821 next instruction. That is, the address of the offset, plus its
11822 size, since the offset is always the last part of the insn. */
11825 md_pcrel_from (fixS
*fixP
)
11827 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11833 s_bss (int ignore ATTRIBUTE_UNUSED
)
11837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11839 obj_elf_section_change_hook ();
11841 temp
= get_absolute_expression ();
11842 subseg_set (bss_section
, (subsegT
) temp
);
11843 demand_empty_rest_of_line ();
11849 i386_validate_fix (fixS
*fixp
)
11851 if (fixp
->fx_subsy
)
11853 if (fixp
->fx_subsy
== GOT_symbol
)
11855 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11860 if (fixp
->fx_tcbit2
)
11861 fixp
->fx_r_type
= (fixp
->fx_tcbit
11862 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11863 : BFD_RELOC_X86_64_GOTPCRELX
);
11866 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11871 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11873 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11875 fixp
->fx_subsy
= 0;
11878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11879 else if (!object_64bit
)
11881 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11882 && fixp
->fx_tcbit2
)
11883 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11889 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11892 bfd_reloc_code_real_type code
;
11894 switch (fixp
->fx_r_type
)
11896 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11897 case BFD_RELOC_SIZE32
:
11898 case BFD_RELOC_SIZE64
:
11899 if (S_IS_DEFINED (fixp
->fx_addsy
)
11900 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11902 /* Resolve size relocation against local symbol to size of
11903 the symbol plus addend. */
11904 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11905 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11906 && !fits_in_unsigned_long (value
))
11907 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11908 _("symbol size computation overflow"));
11909 fixp
->fx_addsy
= NULL
;
11910 fixp
->fx_subsy
= NULL
;
11911 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11915 /* Fall through. */
11917 case BFD_RELOC_X86_64_PLT32
:
11918 case BFD_RELOC_X86_64_GOT32
:
11919 case BFD_RELOC_X86_64_GOTPCREL
:
11920 case BFD_RELOC_X86_64_GOTPCRELX
:
11921 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11922 case BFD_RELOC_386_PLT32
:
11923 case BFD_RELOC_386_GOT32
:
11924 case BFD_RELOC_386_GOT32X
:
11925 case BFD_RELOC_386_GOTOFF
:
11926 case BFD_RELOC_386_GOTPC
:
11927 case BFD_RELOC_386_TLS_GD
:
11928 case BFD_RELOC_386_TLS_LDM
:
11929 case BFD_RELOC_386_TLS_LDO_32
:
11930 case BFD_RELOC_386_TLS_IE_32
:
11931 case BFD_RELOC_386_TLS_IE
:
11932 case BFD_RELOC_386_TLS_GOTIE
:
11933 case BFD_RELOC_386_TLS_LE_32
:
11934 case BFD_RELOC_386_TLS_LE
:
11935 case BFD_RELOC_386_TLS_GOTDESC
:
11936 case BFD_RELOC_386_TLS_DESC_CALL
:
11937 case BFD_RELOC_X86_64_TLSGD
:
11938 case BFD_RELOC_X86_64_TLSLD
:
11939 case BFD_RELOC_X86_64_DTPOFF32
:
11940 case BFD_RELOC_X86_64_DTPOFF64
:
11941 case BFD_RELOC_X86_64_GOTTPOFF
:
11942 case BFD_RELOC_X86_64_TPOFF32
:
11943 case BFD_RELOC_X86_64_TPOFF64
:
11944 case BFD_RELOC_X86_64_GOTOFF64
:
11945 case BFD_RELOC_X86_64_GOTPC32
:
11946 case BFD_RELOC_X86_64_GOT64
:
11947 case BFD_RELOC_X86_64_GOTPCREL64
:
11948 case BFD_RELOC_X86_64_GOTPC64
:
11949 case BFD_RELOC_X86_64_GOTPLT64
:
11950 case BFD_RELOC_X86_64_PLTOFF64
:
11951 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11952 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11953 case BFD_RELOC_RVA
:
11954 case BFD_RELOC_VTABLE_ENTRY
:
11955 case BFD_RELOC_VTABLE_INHERIT
:
11957 case BFD_RELOC_32_SECREL
:
11959 code
= fixp
->fx_r_type
;
11961 case BFD_RELOC_X86_64_32S
:
11962 if (!fixp
->fx_pcrel
)
11964 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11965 code
= fixp
->fx_r_type
;
11968 /* Fall through. */
11970 if (fixp
->fx_pcrel
)
11972 switch (fixp
->fx_size
)
11975 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11976 _("can not do %d byte pc-relative relocation"),
11978 code
= BFD_RELOC_32_PCREL
;
11980 case 1: code
= BFD_RELOC_8_PCREL
; break;
11981 case 2: code
= BFD_RELOC_16_PCREL
; break;
11982 case 4: code
= BFD_RELOC_32_PCREL
; break;
11984 case 8: code
= BFD_RELOC_64_PCREL
; break;
11990 switch (fixp
->fx_size
)
11993 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11994 _("can not do %d byte relocation"),
11996 code
= BFD_RELOC_32
;
11998 case 1: code
= BFD_RELOC_8
; break;
11999 case 2: code
= BFD_RELOC_16
; break;
12000 case 4: code
= BFD_RELOC_32
; break;
12002 case 8: code
= BFD_RELOC_64
; break;
12009 if ((code
== BFD_RELOC_32
12010 || code
== BFD_RELOC_32_PCREL
12011 || code
== BFD_RELOC_X86_64_32S
)
12013 && fixp
->fx_addsy
== GOT_symbol
)
12016 code
= BFD_RELOC_386_GOTPC
;
12018 code
= BFD_RELOC_X86_64_GOTPC32
;
12020 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12022 && fixp
->fx_addsy
== GOT_symbol
)
12024 code
= BFD_RELOC_X86_64_GOTPC64
;
12027 rel
= XNEW (arelent
);
12028 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12029 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12031 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12033 if (!use_rela_relocations
)
12035 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12036 vtable entry to be used in the relocation's section offset. */
12037 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12038 rel
->address
= fixp
->fx_offset
;
12039 #if defined (OBJ_COFF) && defined (TE_PE)
12040 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12041 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12046 /* Use the rela in 64bit mode. */
12049 if (disallow_64bit_reloc
)
12052 case BFD_RELOC_X86_64_DTPOFF64
:
12053 case BFD_RELOC_X86_64_TPOFF64
:
12054 case BFD_RELOC_64_PCREL
:
12055 case BFD_RELOC_X86_64_GOTOFF64
:
12056 case BFD_RELOC_X86_64_GOT64
:
12057 case BFD_RELOC_X86_64_GOTPCREL64
:
12058 case BFD_RELOC_X86_64_GOTPC64
:
12059 case BFD_RELOC_X86_64_GOTPLT64
:
12060 case BFD_RELOC_X86_64_PLTOFF64
:
12061 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12062 _("cannot represent relocation type %s in x32 mode"),
12063 bfd_get_reloc_code_name (code
));
12069 if (!fixp
->fx_pcrel
)
12070 rel
->addend
= fixp
->fx_offset
;
12074 case BFD_RELOC_X86_64_PLT32
:
12075 case BFD_RELOC_X86_64_GOT32
:
12076 case BFD_RELOC_X86_64_GOTPCREL
:
12077 case BFD_RELOC_X86_64_GOTPCRELX
:
12078 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12079 case BFD_RELOC_X86_64_TLSGD
:
12080 case BFD_RELOC_X86_64_TLSLD
:
12081 case BFD_RELOC_X86_64_GOTTPOFF
:
12082 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12083 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12084 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12087 rel
->addend
= (section
->vma
12089 + fixp
->fx_addnumber
12090 + md_pcrel_from (fixp
));
12095 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12096 if (rel
->howto
== NULL
)
12098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12099 _("cannot represent relocation type %s"),
12100 bfd_get_reloc_code_name (code
));
12101 /* Set howto to a garbage value so that we can keep going. */
12102 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12103 gas_assert (rel
->howto
!= NULL
);
12109 #include "tc-i386-intel.c"
12112 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12114 int saved_naked_reg
;
12115 char saved_register_dot
;
12117 saved_naked_reg
= allow_naked_reg
;
12118 allow_naked_reg
= 1;
12119 saved_register_dot
= register_chars
['.'];
12120 register_chars
['.'] = '.';
12121 allow_pseudo_reg
= 1;
12122 expression_and_evaluate (exp
);
12123 allow_pseudo_reg
= 0;
12124 register_chars
['.'] = saved_register_dot
;
12125 allow_naked_reg
= saved_naked_reg
;
12127 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12129 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12131 exp
->X_op
= O_constant
;
12132 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12133 .dw2_regnum
[flag_code
>> 1];
12136 exp
->X_op
= O_illegal
;
12141 tc_x86_frame_initial_instructions (void)
12143 static unsigned int sp_regno
[2];
12145 if (!sp_regno
[flag_code
>> 1])
12147 char *saved_input
= input_line_pointer
;
12148 char sp
[][4] = {"esp", "rsp"};
12151 input_line_pointer
= sp
[flag_code
>> 1];
12152 tc_x86_parse_to_dw2regnum (&exp
);
12153 gas_assert (exp
.X_op
== O_constant
);
12154 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12155 input_line_pointer
= saved_input
;
12158 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12159 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12163 x86_dwarf2_addr_size (void)
12165 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12166 if (x86_elf_abi
== X86_64_X32_ABI
)
12169 return bfd_arch_bits_per_address (stdoutput
) / 8;
12173 i386_elf_section_type (const char *str
, size_t len
)
12175 if (flag_code
== CODE_64BIT
12176 && len
== sizeof ("unwind") - 1
12177 && strncmp (str
, "unwind", 6) == 0)
12178 return SHT_X86_64_UNWIND
;
12185 i386_solaris_fix_up_eh_frame (segT sec
)
12187 if (flag_code
== CODE_64BIT
)
12188 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12194 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12198 exp
.X_op
= O_secrel
;
12199 exp
.X_add_symbol
= symbol
;
12200 exp
.X_add_number
= 0;
12201 emit_expr (&exp
, size
);
12205 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12206 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12209 x86_64_section_letter (int letter
, const char **ptr_msg
)
12211 if (flag_code
== CODE_64BIT
)
12214 return SHF_X86_64_LARGE
;
12216 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12219 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12224 x86_64_section_word (char *str
, size_t len
)
12226 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12227 return SHF_X86_64_LARGE
;
12233 handle_large_common (int small ATTRIBUTE_UNUSED
)
12235 if (flag_code
!= CODE_64BIT
)
12237 s_comm_internal (0, elf_common_parse
);
12238 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12242 static segT lbss_section
;
12243 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12244 asection
*saved_bss_section
= bss_section
;
12246 if (lbss_section
== NULL
)
12248 flagword applicable
;
12249 segT seg
= now_seg
;
12250 subsegT subseg
= now_subseg
;
12252 /* The .lbss section is for local .largecomm symbols. */
12253 lbss_section
= subseg_new (".lbss", 0);
12254 applicable
= bfd_applicable_section_flags (stdoutput
);
12255 bfd_set_section_flags (stdoutput
, lbss_section
,
12256 applicable
& SEC_ALLOC
);
12257 seg_info (lbss_section
)->bss
= 1;
12259 subseg_set (seg
, subseg
);
12262 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12263 bss_section
= lbss_section
;
12265 s_comm_internal (0, elf_common_parse
);
12267 elf_com_section_ptr
= saved_com_section_ptr
;
12268 bss_section
= saved_bss_section
;
12271 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */