1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1084 CPU_AVX512_BF16_FLAGS
, 0 },
1087 static const noarch_entry cpu_noarch
[] =
1089 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1090 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1091 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1092 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1093 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1094 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1095 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1096 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1097 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1099 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1101 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1102 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1120 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1121 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1122 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1123 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1128 /* Like s_lcomm_internal in gas/read.c but the alignment string
1129 is allowed to be optional. */
1132 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1139 && *input_line_pointer
== ',')
1141 align
= parse_align (needs_align
- 1);
1143 if (align
== (addressT
) -1)
1158 bss_alloc (symbolP
, size
, align
);
1163 pe_lcomm (int needs_align
)
1165 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1169 const pseudo_typeS md_pseudo_table
[] =
1171 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1172 {"align", s_align_bytes
, 0},
1174 {"align", s_align_ptwo
, 0},
1176 {"arch", set_cpu_arch
, 0},
1180 {"lcomm", pe_lcomm
, 1},
1182 {"ffloat", float_cons
, 'f'},
1183 {"dfloat", float_cons
, 'd'},
1184 {"tfloat", float_cons
, 'x'},
1186 {"slong", signed_cons
, 4},
1187 {"noopt", s_ignore
, 0},
1188 {"optim", s_ignore
, 0},
1189 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1190 {"code16", set_code_flag
, CODE_16BIT
},
1191 {"code32", set_code_flag
, CODE_32BIT
},
1193 {"code64", set_code_flag
, CODE_64BIT
},
1195 {"intel_syntax", set_intel_syntax
, 1},
1196 {"att_syntax", set_intel_syntax
, 0},
1197 {"intel_mnemonic", set_intel_mnemonic
, 1},
1198 {"att_mnemonic", set_intel_mnemonic
, 0},
1199 {"allow_index_reg", set_allow_index_reg
, 1},
1200 {"disallow_index_reg", set_allow_index_reg
, 0},
1201 {"sse_check", set_check
, 0},
1202 {"operand_check", set_check
, 1},
1203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1204 {"largecomm", handle_large_common
, 0},
1206 {"file", dwarf2_directive_file
, 0},
1207 {"loc", dwarf2_directive_loc
, 0},
1208 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1211 {"secrel32", pe_directive_secrel
, 0},
1216 /* For interface with expression (). */
1217 extern char *input_line_pointer
;
1219 /* Hash table for instruction mnemonic lookup. */
1220 static struct hash_control
*op_hash
;
1222 /* Hash table for register lookup. */
1223 static struct hash_control
*reg_hash
;
1225 /* Various efficient no-op patterns for aligning code labels.
1226 Note: Don't try to assemble the instructions in the comments.
1227 0L and 0w are not legal. */
1228 static const unsigned char f32_1
[] =
1230 static const unsigned char f32_2
[] =
1231 {0x66,0x90}; /* xchg %ax,%ax */
1232 static const unsigned char f32_3
[] =
1233 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1234 static const unsigned char f32_4
[] =
1235 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1236 static const unsigned char f32_6
[] =
1237 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1238 static const unsigned char f32_7
[] =
1239 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1240 static const unsigned char f16_3
[] =
1241 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1242 static const unsigned char f16_4
[] =
1243 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1244 static const unsigned char jump_disp8
[] =
1245 {0xeb}; /* jmp disp8 */
1246 static const unsigned char jump32_disp32
[] =
1247 {0xe9}; /* jmp disp32 */
1248 static const unsigned char jump16_disp32
[] =
1249 {0x66,0xe9}; /* jmp disp32 */
1250 /* 32-bit NOPs patterns. */
1251 static const unsigned char *const f32_patt
[] = {
1252 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1254 /* 16-bit NOPs patterns. */
1255 static const unsigned char *const f16_patt
[] = {
1256 f32_1
, f32_2
, f16_3
, f16_4
1258 /* nopl (%[re]ax) */
1259 static const unsigned char alt_3
[] =
1261 /* nopl 0(%[re]ax) */
1262 static const unsigned char alt_4
[] =
1263 {0x0f,0x1f,0x40,0x00};
1264 /* nopl 0(%[re]ax,%[re]ax,1) */
1265 static const unsigned char alt_5
[] =
1266 {0x0f,0x1f,0x44,0x00,0x00};
1267 /* nopw 0(%[re]ax,%[re]ax,1) */
1268 static const unsigned char alt_6
[] =
1269 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1270 /* nopl 0L(%[re]ax) */
1271 static const unsigned char alt_7
[] =
1272 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1273 /* nopl 0L(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_8
[] =
1275 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1276 /* nopw 0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_9
[] =
1278 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_10
[] =
1281 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* data16 nopw %cs:0L(%eax,%eax,1) */
1283 static const unsigned char alt_11
[] =
1284 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* 32-bit and 64-bit NOPs patterns. */
1286 static const unsigned char *const alt_patt
[] = {
1287 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1288 alt_9
, alt_10
, alt_11
1291 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1292 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1295 i386_output_nops (char *where
, const unsigned char *const *patt
,
1296 int count
, int max_single_nop_size
)
1299 /* Place the longer NOP first. */
1302 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1304 /* Use the smaller one if the requsted one isn't available. */
1307 max_single_nop_size
--;
1308 nops
= patt
[max_single_nop_size
- 1];
1311 last
= count
% max_single_nop_size
;
1314 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1315 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1319 nops
= patt
[last
- 1];
1322 /* Use the smaller one plus one-byte NOP if the needed one
1325 nops
= patt
[last
- 1];
1326 memcpy (where
+ offset
, nops
, last
);
1327 where
[offset
+ last
] = *patt
[0];
1330 memcpy (where
+ offset
, nops
, last
);
1335 fits_in_imm7 (offsetT num
)
1337 return (num
& 0x7f) == num
;
1341 fits_in_imm31 (offsetT num
)
1343 return (num
& 0x7fffffff) == num
;
1346 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1347 single NOP instruction LIMIT. */
1350 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1352 const unsigned char *const *patt
= NULL
;
1353 int max_single_nop_size
;
1354 /* Maximum number of NOPs before switching to jump over NOPs. */
1355 int max_number_of_nops
;
1357 switch (fragP
->fr_type
)
1366 /* We need to decide which NOP sequence to use for 32bit and
1367 64bit. When -mtune= is used:
1369 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1370 PROCESSOR_GENERIC32, f32_patt will be used.
1371 2. For the rest, alt_patt will be used.
1373 When -mtune= isn't used, alt_patt will be used if
1374 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1377 When -march= or .arch is used, we can't use anything beyond
1378 cpu_arch_isa_flags. */
1380 if (flag_code
== CODE_16BIT
)
1383 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1384 /* Limit number of NOPs to 2 in 16-bit mode. */
1385 max_number_of_nops
= 2;
1389 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1391 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1392 switch (cpu_arch_tune
)
1394 case PROCESSOR_UNKNOWN
:
1395 /* We use cpu_arch_isa_flags to check if we SHOULD
1396 optimize with nops. */
1397 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1402 case PROCESSOR_PENTIUM4
:
1403 case PROCESSOR_NOCONA
:
1404 case PROCESSOR_CORE
:
1405 case PROCESSOR_CORE2
:
1406 case PROCESSOR_COREI7
:
1407 case PROCESSOR_L1OM
:
1408 case PROCESSOR_K1OM
:
1409 case PROCESSOR_GENERIC64
:
1411 case PROCESSOR_ATHLON
:
1413 case PROCESSOR_AMDFAM10
:
1415 case PROCESSOR_ZNVER
:
1419 case PROCESSOR_I386
:
1420 case PROCESSOR_I486
:
1421 case PROCESSOR_PENTIUM
:
1422 case PROCESSOR_PENTIUMPRO
:
1423 case PROCESSOR_IAMCU
:
1424 case PROCESSOR_GENERIC32
:
1431 switch (fragP
->tc_frag_data
.tune
)
1433 case PROCESSOR_UNKNOWN
:
1434 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1435 PROCESSOR_UNKNOWN. */
1439 case PROCESSOR_I386
:
1440 case PROCESSOR_I486
:
1441 case PROCESSOR_PENTIUM
:
1442 case PROCESSOR_IAMCU
:
1444 case PROCESSOR_ATHLON
:
1446 case PROCESSOR_AMDFAM10
:
1448 case PROCESSOR_ZNVER
:
1450 case PROCESSOR_GENERIC32
:
1451 /* We use cpu_arch_isa_flags to check if we CAN optimize
1453 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1458 case PROCESSOR_PENTIUMPRO
:
1459 case PROCESSOR_PENTIUM4
:
1460 case PROCESSOR_NOCONA
:
1461 case PROCESSOR_CORE
:
1462 case PROCESSOR_CORE2
:
1463 case PROCESSOR_COREI7
:
1464 case PROCESSOR_L1OM
:
1465 case PROCESSOR_K1OM
:
1466 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1471 case PROCESSOR_GENERIC64
:
1477 if (patt
== f32_patt
)
1479 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1480 /* Limit number of NOPs to 2 for older processors. */
1481 max_number_of_nops
= 2;
1485 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1486 /* Limit number of NOPs to 7 for newer processors. */
1487 max_number_of_nops
= 7;
1492 limit
= max_single_nop_size
;
1494 if (fragP
->fr_type
== rs_fill_nop
)
1496 /* Output NOPs for .nop directive. */
1497 if (limit
> max_single_nop_size
)
1499 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1500 _("invalid single nop size: %d "
1501 "(expect within [0, %d])"),
1502 limit
, max_single_nop_size
);
1507 fragP
->fr_var
= count
;
1509 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1511 /* Generate jump over NOPs. */
1512 offsetT disp
= count
- 2;
1513 if (fits_in_imm7 (disp
))
1515 /* Use "jmp disp8" if possible. */
1517 where
[0] = jump_disp8
[0];
1523 unsigned int size_of_jump
;
1525 if (flag_code
== CODE_16BIT
)
1527 where
[0] = jump16_disp32
[0];
1528 where
[1] = jump16_disp32
[1];
1533 where
[0] = jump32_disp32
[0];
1537 count
-= size_of_jump
+ 4;
1538 if (!fits_in_imm31 (count
))
1540 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1541 _("jump over nop padding out of range"));
1545 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1546 where
+= size_of_jump
+ 4;
1550 /* Generate multiple NOPs. */
1551 i386_output_nops (where
, patt
, count
, limit
);
1555 operand_type_all_zero (const union i386_operand_type
*x
)
1557 switch (ARRAY_SIZE(x
->array
))
1568 return !x
->array
[0];
1575 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1577 switch (ARRAY_SIZE(x
->array
))
1595 operand_type_equal (const union i386_operand_type
*x
,
1596 const union i386_operand_type
*y
)
1598 switch (ARRAY_SIZE(x
->array
))
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1619 switch (ARRAY_SIZE(x
->array
))
1634 return !x
->array
[0];
1641 cpu_flags_equal (const union i386_cpu_flags
*x
,
1642 const union i386_cpu_flags
*y
)
1644 switch (ARRAY_SIZE(x
->array
))
1647 if (x
->array
[3] != y
->array
[3])
1651 if (x
->array
[2] != y
->array
[2])
1655 if (x
->array
[1] != y
->array
[1])
1659 return x
->array
[0] == y
->array
[0];
1667 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1669 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1670 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1673 static INLINE i386_cpu_flags
1674 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1676 switch (ARRAY_SIZE (x
.array
))
1679 x
.array
[3] &= y
.array
[3];
1682 x
.array
[2] &= y
.array
[2];
1685 x
.array
[1] &= y
.array
[1];
1688 x
.array
[0] &= y
.array
[0];
1696 static INLINE i386_cpu_flags
1697 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1699 switch (ARRAY_SIZE (x
.array
))
1702 x
.array
[3] |= y
.array
[3];
1705 x
.array
[2] |= y
.array
[2];
1708 x
.array
[1] |= y
.array
[1];
1711 x
.array
[0] |= y
.array
[0];
1719 static INLINE i386_cpu_flags
1720 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1722 switch (ARRAY_SIZE (x
.array
))
1725 x
.array
[3] &= ~y
.array
[3];
1728 x
.array
[2] &= ~y
.array
[2];
1731 x
.array
[1] &= ~y
.array
[1];
1734 x
.array
[0] &= ~y
.array
[0];
1742 #define CPU_FLAGS_ARCH_MATCH 0x1
1743 #define CPU_FLAGS_64BIT_MATCH 0x2
1745 #define CPU_FLAGS_PERFECT_MATCH \
1746 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1748 /* Return CPU flags match bits. */
1751 cpu_flags_match (const insn_template
*t
)
1753 i386_cpu_flags x
= t
->cpu_flags
;
1754 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1756 x
.bitfield
.cpu64
= 0;
1757 x
.bitfield
.cpuno64
= 0;
1759 if (cpu_flags_all_zero (&x
))
1761 /* This instruction is available on all archs. */
1762 match
|= CPU_FLAGS_ARCH_MATCH
;
1766 /* This instruction is available only on some archs. */
1767 i386_cpu_flags cpu
= cpu_arch_flags
;
1769 /* AVX512VL is no standalone feature - match it and then strip it. */
1770 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1772 x
.bitfield
.cpuavx512vl
= 0;
1774 cpu
= cpu_flags_and (x
, cpu
);
1775 if (!cpu_flags_all_zero (&cpu
))
1777 if (x
.bitfield
.cpuavx
)
1779 /* We need to check a few extra flags with AVX. */
1780 if (cpu
.bitfield
.cpuavx
1781 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1782 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1783 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1784 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1785 match
|= CPU_FLAGS_ARCH_MATCH
;
1787 else if (x
.bitfield
.cpuavx512f
)
1789 /* We need to check a few extra flags with AVX512F. */
1790 if (cpu
.bitfield
.cpuavx512f
1791 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1792 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1793 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1794 match
|= CPU_FLAGS_ARCH_MATCH
;
1797 match
|= CPU_FLAGS_ARCH_MATCH
;
1803 static INLINE i386_operand_type
1804 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1806 switch (ARRAY_SIZE (x
.array
))
1809 x
.array
[2] &= y
.array
[2];
1812 x
.array
[1] &= y
.array
[1];
1815 x
.array
[0] &= y
.array
[0];
1823 static INLINE i386_operand_type
1824 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1826 switch (ARRAY_SIZE (x
.array
))
1829 x
.array
[2] &= ~y
.array
[2];
1832 x
.array
[1] &= ~y
.array
[1];
1835 x
.array
[0] &= ~y
.array
[0];
1843 static INLINE i386_operand_type
1844 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1846 switch (ARRAY_SIZE (x
.array
))
1849 x
.array
[2] |= y
.array
[2];
1852 x
.array
[1] |= y
.array
[1];
1855 x
.array
[0] |= y
.array
[0];
1863 static INLINE i386_operand_type
1864 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1866 switch (ARRAY_SIZE (x
.array
))
1869 x
.array
[2] ^= y
.array
[2];
1872 x
.array
[1] ^= y
.array
[1];
1875 x
.array
[0] ^= y
.array
[0];
1883 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1884 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1885 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1886 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1887 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1888 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1889 static const i386_operand_type anydisp
1890 = OPERAND_TYPE_ANYDISP
;
1891 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1892 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1893 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1894 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1895 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1896 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1897 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1898 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1899 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1900 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1901 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1902 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1913 operand_type_check (i386_operand_type t
, enum operand_type c
)
1918 return t
.bitfield
.reg
;
1921 return (t
.bitfield
.imm8
1925 || t
.bitfield
.imm32s
1926 || t
.bitfield
.imm64
);
1929 return (t
.bitfield
.disp8
1930 || t
.bitfield
.disp16
1931 || t
.bitfield
.disp32
1932 || t
.bitfield
.disp32s
1933 || t
.bitfield
.disp64
);
1936 return (t
.bitfield
.disp8
1937 || t
.bitfield
.disp16
1938 || t
.bitfield
.disp32
1939 || t
.bitfield
.disp32s
1940 || t
.bitfield
.disp64
1941 || t
.bitfield
.baseindex
);
1950 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1951 between operand GIVEN and opeand WANTED for instruction template T. */
1954 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1957 return !((i
.types
[given
].bitfield
.byte
1958 && !t
->operand_types
[wanted
].bitfield
.byte
)
1959 || (i
.types
[given
].bitfield
.word
1960 && !t
->operand_types
[wanted
].bitfield
.word
)
1961 || (i
.types
[given
].bitfield
.dword
1962 && !t
->operand_types
[wanted
].bitfield
.dword
)
1963 || (i
.types
[given
].bitfield
.qword
1964 && !t
->operand_types
[wanted
].bitfield
.qword
)
1965 || (i
.types
[given
].bitfield
.tbyte
1966 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1969 /* Return 1 if there is no conflict in SIMD register between operand
1970 GIVEN and opeand WANTED for instruction template T. */
1973 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1976 return !((i
.types
[given
].bitfield
.xmmword
1977 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1978 || (i
.types
[given
].bitfield
.ymmword
1979 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1980 || (i
.types
[given
].bitfield
.zmmword
1981 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1984 /* Return 1 if there is no conflict in any size between operand GIVEN
1985 and opeand WANTED for instruction template T. */
1988 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1991 return (match_operand_size (t
, wanted
, given
)
1992 && !((i
.types
[given
].bitfield
.unspecified
1994 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1995 || (i
.types
[given
].bitfield
.fword
1996 && !t
->operand_types
[wanted
].bitfield
.fword
)
1997 /* For scalar opcode templates to allow register and memory
1998 operands at the same time, some special casing is needed
1999 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2000 down-conversion vpmov*. */
2001 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2002 && !t
->opcode_modifier
.broadcast
2003 && (t
->operand_types
[wanted
].bitfield
.byte
2004 || t
->operand_types
[wanted
].bitfield
.word
2005 || t
->operand_types
[wanted
].bitfield
.dword
2006 || t
->operand_types
[wanted
].bitfield
.qword
))
2007 ? (i
.types
[given
].bitfield
.xmmword
2008 || i
.types
[given
].bitfield
.ymmword
2009 || i
.types
[given
].bitfield
.zmmword
)
2010 : !match_simd_size(t
, wanted
, given
))));
2013 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2014 operands for instruction template T, and it has MATCH_REVERSE set if there
2015 is no size conflict on any operands for the template with operands reversed
2016 (and the template allows for reversing in the first place). */
2018 #define MATCH_STRAIGHT 1
2019 #define MATCH_REVERSE 2
2021 static INLINE
unsigned int
2022 operand_size_match (const insn_template
*t
)
2024 unsigned int j
, match
= MATCH_STRAIGHT
;
2026 /* Don't check jump instructions. */
2027 if (t
->opcode_modifier
.jump
2028 || t
->opcode_modifier
.jumpbyte
2029 || t
->opcode_modifier
.jumpdword
2030 || t
->opcode_modifier
.jumpintersegment
)
2033 /* Check memory and accumulator operand size. */
2034 for (j
= 0; j
< i
.operands
; j
++)
2036 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2037 && t
->operand_types
[j
].bitfield
.anysize
)
2040 if (t
->operand_types
[j
].bitfield
.reg
2041 && !match_operand_size (t
, j
, j
))
2047 if (t
->operand_types
[j
].bitfield
.regsimd
2048 && !match_simd_size (t
, j
, j
))
2054 if (t
->operand_types
[j
].bitfield
.acc
2055 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2061 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2068 if (!t
->opcode_modifier
.d
)
2072 i
.error
= operand_size_mismatch
;
2076 /* Check reverse. */
2077 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2079 for (j
= 0; j
< i
.operands
; j
++)
2081 unsigned int given
= i
.operands
- j
- 1;
2083 if (t
->operand_types
[j
].bitfield
.reg
2084 && !match_operand_size (t
, j
, given
))
2087 if (t
->operand_types
[j
].bitfield
.regsimd
2088 && !match_simd_size (t
, j
, given
))
2091 if (t
->operand_types
[j
].bitfield
.acc
2092 && (!match_operand_size (t
, j
, given
)
2093 || !match_simd_size (t
, j
, given
)))
2096 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2100 return match
| MATCH_REVERSE
;
2104 operand_type_match (i386_operand_type overlap
,
2105 i386_operand_type given
)
2107 i386_operand_type temp
= overlap
;
2109 temp
.bitfield
.jumpabsolute
= 0;
2110 temp
.bitfield
.unspecified
= 0;
2111 temp
.bitfield
.byte
= 0;
2112 temp
.bitfield
.word
= 0;
2113 temp
.bitfield
.dword
= 0;
2114 temp
.bitfield
.fword
= 0;
2115 temp
.bitfield
.qword
= 0;
2116 temp
.bitfield
.tbyte
= 0;
2117 temp
.bitfield
.xmmword
= 0;
2118 temp
.bitfield
.ymmword
= 0;
2119 temp
.bitfield
.zmmword
= 0;
2120 if (operand_type_all_zero (&temp
))
2123 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2124 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2128 i
.error
= operand_type_mismatch
;
2132 /* If given types g0 and g1 are registers they must be of the same type
2133 unless the expected operand type register overlap is null.
2134 Memory operand size of certain SIMD instructions is also being checked
2138 operand_type_register_match (i386_operand_type g0
,
2139 i386_operand_type t0
,
2140 i386_operand_type g1
,
2141 i386_operand_type t1
)
2143 if (!g0
.bitfield
.reg
2144 && !g0
.bitfield
.regsimd
2145 && (!operand_type_check (g0
, anymem
)
2146 || g0
.bitfield
.unspecified
2147 || !t0
.bitfield
.regsimd
))
2150 if (!g1
.bitfield
.reg
2151 && !g1
.bitfield
.regsimd
2152 && (!operand_type_check (g1
, anymem
)
2153 || g1
.bitfield
.unspecified
2154 || !t1
.bitfield
.regsimd
))
2157 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2158 && g0
.bitfield
.word
== g1
.bitfield
.word
2159 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2160 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2161 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2162 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2163 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2166 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2167 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2168 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2169 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2170 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2171 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2172 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2175 i
.error
= register_type_mismatch
;
2180 static INLINE
unsigned int
2181 register_number (const reg_entry
*r
)
2183 unsigned int nr
= r
->reg_num
;
2185 if (r
->reg_flags
& RegRex
)
2188 if (r
->reg_flags
& RegVRex
)
2194 static INLINE
unsigned int
2195 mode_from_disp_size (i386_operand_type t
)
2197 if (t
.bitfield
.disp8
)
2199 else if (t
.bitfield
.disp16
2200 || t
.bitfield
.disp32
2201 || t
.bitfield
.disp32s
)
2208 fits_in_signed_byte (addressT num
)
2210 return num
+ 0x80 <= 0xff;
2214 fits_in_unsigned_byte (addressT num
)
2220 fits_in_unsigned_word (addressT num
)
2222 return num
<= 0xffff;
2226 fits_in_signed_word (addressT num
)
2228 return num
+ 0x8000 <= 0xffff;
2232 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2237 return num
+ 0x80000000 <= 0xffffffff;
2239 } /* fits_in_signed_long() */
2242 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2247 return num
<= 0xffffffff;
2249 } /* fits_in_unsigned_long() */
2252 fits_in_disp8 (offsetT num
)
2254 int shift
= i
.memshift
;
2260 mask
= (1 << shift
) - 1;
2262 /* Return 0 if NUM isn't properly aligned. */
2266 /* Check if NUM will fit in 8bit after shift. */
2267 return fits_in_signed_byte (num
>> shift
);
2271 fits_in_imm4 (offsetT num
)
2273 return (num
& 0xf) == num
;
2276 static i386_operand_type
2277 smallest_imm_type (offsetT num
)
2279 i386_operand_type t
;
2281 operand_type_set (&t
, 0);
2282 t
.bitfield
.imm64
= 1;
2284 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2286 /* This code is disabled on the 486 because all the Imm1 forms
2287 in the opcode table are slower on the i486. They're the
2288 versions with the implicitly specified single-position
2289 displacement, which has another syntax if you really want to
2291 t
.bitfield
.imm1
= 1;
2292 t
.bitfield
.imm8
= 1;
2293 t
.bitfield
.imm8s
= 1;
2294 t
.bitfield
.imm16
= 1;
2295 t
.bitfield
.imm32
= 1;
2296 t
.bitfield
.imm32s
= 1;
2298 else if (fits_in_signed_byte (num
))
2300 t
.bitfield
.imm8
= 1;
2301 t
.bitfield
.imm8s
= 1;
2302 t
.bitfield
.imm16
= 1;
2303 t
.bitfield
.imm32
= 1;
2304 t
.bitfield
.imm32s
= 1;
2306 else if (fits_in_unsigned_byte (num
))
2308 t
.bitfield
.imm8
= 1;
2309 t
.bitfield
.imm16
= 1;
2310 t
.bitfield
.imm32
= 1;
2311 t
.bitfield
.imm32s
= 1;
2313 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2315 t
.bitfield
.imm16
= 1;
2316 t
.bitfield
.imm32
= 1;
2317 t
.bitfield
.imm32s
= 1;
2319 else if (fits_in_signed_long (num
))
2321 t
.bitfield
.imm32
= 1;
2322 t
.bitfield
.imm32s
= 1;
2324 else if (fits_in_unsigned_long (num
))
2325 t
.bitfield
.imm32
= 1;
2331 offset_in_range (offsetT val
, int size
)
2337 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2338 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2339 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2341 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2347 /* If BFD64, sign extend val for 32bit address mode. */
2348 if (flag_code
!= CODE_64BIT
2349 || i
.prefix
[ADDR_PREFIX
])
2350 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2351 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2354 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2356 char buf1
[40], buf2
[40];
2358 sprint_value (buf1
, val
);
2359 sprint_value (buf2
, val
& mask
);
2360 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2375 a. PREFIX_EXIST if attempting to add a prefix where one from the
2376 same class already exists.
2377 b. PREFIX_LOCK if lock prefix is added.
2378 c. PREFIX_REP if rep/repne prefix is added.
2379 d. PREFIX_DS if ds prefix is added.
2380 e. PREFIX_OTHER if other prefix is added.
2383 static enum PREFIX_GROUP
2384 add_prefix (unsigned int prefix
)
2386 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2389 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2390 && flag_code
== CODE_64BIT
)
2392 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2393 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2394 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2395 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2406 case DS_PREFIX_OPCODE
:
2409 case CS_PREFIX_OPCODE
:
2410 case ES_PREFIX_OPCODE
:
2411 case FS_PREFIX_OPCODE
:
2412 case GS_PREFIX_OPCODE
:
2413 case SS_PREFIX_OPCODE
:
2417 case REPNE_PREFIX_OPCODE
:
2418 case REPE_PREFIX_OPCODE
:
2423 case LOCK_PREFIX_OPCODE
:
2432 case ADDR_PREFIX_OPCODE
:
2436 case DATA_PREFIX_OPCODE
:
2440 if (i
.prefix
[q
] != 0)
2448 i
.prefix
[q
] |= prefix
;
2451 as_bad (_("same type of prefix used twice"));
2457 update_code_flag (int value
, int check
)
2459 PRINTF_LIKE ((*as_error
));
2461 flag_code
= (enum flag_code
) value
;
2462 if (flag_code
== CODE_64BIT
)
2464 cpu_arch_flags
.bitfield
.cpu64
= 1;
2465 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2469 cpu_arch_flags
.bitfield
.cpu64
= 0;
2470 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2472 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2475 as_error
= as_fatal
;
2478 (*as_error
) (_("64bit mode not supported on `%s'."),
2479 cpu_arch_name
? cpu_arch_name
: default_arch
);
2481 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2484 as_error
= as_fatal
;
2487 (*as_error
) (_("32bit mode not supported on `%s'."),
2488 cpu_arch_name
? cpu_arch_name
: default_arch
);
2490 stackop_size
= '\0';
2494 set_code_flag (int value
)
2496 update_code_flag (value
, 0);
2500 set_16bit_gcc_code_flag (int new_code_flag
)
2502 flag_code
= (enum flag_code
) new_code_flag
;
2503 if (flag_code
!= CODE_16BIT
)
2505 cpu_arch_flags
.bitfield
.cpu64
= 0;
2506 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2507 stackop_size
= LONG_MNEM_SUFFIX
;
2511 set_intel_syntax (int syntax_flag
)
2513 /* Find out if register prefixing is specified. */
2514 int ask_naked_reg
= 0;
2517 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2520 int e
= get_symbol_name (&string
);
2522 if (strcmp (string
, "prefix") == 0)
2524 else if (strcmp (string
, "noprefix") == 0)
2527 as_bad (_("bad argument to syntax directive."));
2528 (void) restore_line_pointer (e
);
2530 demand_empty_rest_of_line ();
2532 intel_syntax
= syntax_flag
;
2534 if (ask_naked_reg
== 0)
2535 allow_naked_reg
= (intel_syntax
2536 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2538 allow_naked_reg
= (ask_naked_reg
< 0);
2540 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2542 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2543 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2544 register_prefix
= allow_naked_reg
? "" : "%";
2548 set_intel_mnemonic (int mnemonic_flag
)
2550 intel_mnemonic
= mnemonic_flag
;
2554 set_allow_index_reg (int flag
)
2556 allow_index_reg
= flag
;
2560 set_check (int what
)
2562 enum check_kind
*kind
;
2567 kind
= &operand_check
;
2578 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2581 int e
= get_symbol_name (&string
);
2583 if (strcmp (string
, "none") == 0)
2585 else if (strcmp (string
, "warning") == 0)
2586 *kind
= check_warning
;
2587 else if (strcmp (string
, "error") == 0)
2588 *kind
= check_error
;
2590 as_bad (_("bad argument to %s_check directive."), str
);
2591 (void) restore_line_pointer (e
);
2594 as_bad (_("missing argument for %s_check directive"), str
);
2596 demand_empty_rest_of_line ();
2600 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2601 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2604 static const char *arch
;
2606 /* Intel LIOM is only supported on ELF. */
2612 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2613 use default_arch. */
2614 arch
= cpu_arch_name
;
2616 arch
= default_arch
;
2619 /* If we are targeting Intel MCU, we must enable it. */
2620 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2621 || new_flag
.bitfield
.cpuiamcu
)
2624 /* If we are targeting Intel L1OM, we must enable it. */
2625 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2626 || new_flag
.bitfield
.cpul1om
)
2629 /* If we are targeting Intel K1OM, we must enable it. */
2630 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2631 || new_flag
.bitfield
.cpuk1om
)
2634 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2639 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2643 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2646 int e
= get_symbol_name (&string
);
2648 i386_cpu_flags flags
;
2650 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2652 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2654 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2658 cpu_arch_name
= cpu_arch
[j
].name
;
2659 cpu_sub_arch_name
= NULL
;
2660 cpu_arch_flags
= cpu_arch
[j
].flags
;
2661 if (flag_code
== CODE_64BIT
)
2663 cpu_arch_flags
.bitfield
.cpu64
= 1;
2664 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2668 cpu_arch_flags
.bitfield
.cpu64
= 0;
2669 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2671 cpu_arch_isa
= cpu_arch
[j
].type
;
2672 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2673 if (!cpu_arch_tune_set
)
2675 cpu_arch_tune
= cpu_arch_isa
;
2676 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2681 flags
= cpu_flags_or (cpu_arch_flags
,
2684 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2686 if (cpu_sub_arch_name
)
2688 char *name
= cpu_sub_arch_name
;
2689 cpu_sub_arch_name
= concat (name
,
2691 (const char *) NULL
);
2695 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2696 cpu_arch_flags
= flags
;
2697 cpu_arch_isa_flags
= flags
;
2701 = cpu_flags_or (cpu_arch_isa_flags
,
2703 (void) restore_line_pointer (e
);
2704 demand_empty_rest_of_line ();
2709 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2711 /* Disable an ISA extension. */
2712 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2713 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2715 flags
= cpu_flags_and_not (cpu_arch_flags
,
2716 cpu_noarch
[j
].flags
);
2717 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2719 if (cpu_sub_arch_name
)
2721 char *name
= cpu_sub_arch_name
;
2722 cpu_sub_arch_name
= concat (name
, string
,
2723 (const char *) NULL
);
2727 cpu_sub_arch_name
= xstrdup (string
);
2728 cpu_arch_flags
= flags
;
2729 cpu_arch_isa_flags
= flags
;
2731 (void) restore_line_pointer (e
);
2732 demand_empty_rest_of_line ();
2736 j
= ARRAY_SIZE (cpu_arch
);
2739 if (j
>= ARRAY_SIZE (cpu_arch
))
2740 as_bad (_("no such architecture: `%s'"), string
);
2742 *input_line_pointer
= e
;
2745 as_bad (_("missing cpu architecture"));
2747 no_cond_jump_promotion
= 0;
2748 if (*input_line_pointer
== ','
2749 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2754 ++input_line_pointer
;
2755 e
= get_symbol_name (&string
);
2757 if (strcmp (string
, "nojumps") == 0)
2758 no_cond_jump_promotion
= 1;
2759 else if (strcmp (string
, "jumps") == 0)
2762 as_bad (_("no such architecture modifier: `%s'"), string
);
2764 (void) restore_line_pointer (e
);
2767 demand_empty_rest_of_line ();
2770 enum bfd_architecture
2773 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2775 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2776 || flag_code
!= CODE_64BIT
)
2777 as_fatal (_("Intel L1OM is 64bit ELF only"));
2778 return bfd_arch_l1om
;
2780 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2782 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2783 || flag_code
!= CODE_64BIT
)
2784 as_fatal (_("Intel K1OM is 64bit ELF only"));
2785 return bfd_arch_k1om
;
2787 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2789 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2790 || flag_code
== CODE_64BIT
)
2791 as_fatal (_("Intel MCU is 32bit ELF only"));
2792 return bfd_arch_iamcu
;
2795 return bfd_arch_i386
;
2801 if (!strncmp (default_arch
, "x86_64", 6))
2803 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2805 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2806 || default_arch
[6] != '\0')
2807 as_fatal (_("Intel L1OM is 64bit ELF only"));
2808 return bfd_mach_l1om
;
2810 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2812 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2813 || default_arch
[6] != '\0')
2814 as_fatal (_("Intel K1OM is 64bit ELF only"));
2815 return bfd_mach_k1om
;
2817 else if (default_arch
[6] == '\0')
2818 return bfd_mach_x86_64
;
2820 return bfd_mach_x64_32
;
2822 else if (!strcmp (default_arch
, "i386")
2823 || !strcmp (default_arch
, "iamcu"))
2825 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2827 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2828 as_fatal (_("Intel MCU is 32bit ELF only"));
2829 return bfd_mach_i386_iamcu
;
2832 return bfd_mach_i386_i386
;
2835 as_fatal (_("unknown architecture"));
2841 const char *hash_err
;
2843 /* Support pseudo prefixes like {disp32}. */
2844 lex_type
['{'] = LEX_BEGIN_NAME
;
2846 /* Initialize op_hash hash table. */
2847 op_hash
= hash_new ();
2850 const insn_template
*optab
;
2851 templates
*core_optab
;
2853 /* Setup for loop. */
2855 core_optab
= XNEW (templates
);
2856 core_optab
->start
= optab
;
2861 if (optab
->name
== NULL
2862 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2864 /* different name --> ship out current template list;
2865 add to hash table; & begin anew. */
2866 core_optab
->end
= optab
;
2867 hash_err
= hash_insert (op_hash
,
2869 (void *) core_optab
);
2872 as_fatal (_("can't hash %s: %s"),
2876 if (optab
->name
== NULL
)
2878 core_optab
= XNEW (templates
);
2879 core_optab
->start
= optab
;
2884 /* Initialize reg_hash hash table. */
2885 reg_hash
= hash_new ();
2887 const reg_entry
*regtab
;
2888 unsigned int regtab_size
= i386_regtab_size
;
2890 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2892 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2894 as_fatal (_("can't hash %s: %s"),
2900 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2905 for (c
= 0; c
< 256; c
++)
2910 mnemonic_chars
[c
] = c
;
2911 register_chars
[c
] = c
;
2912 operand_chars
[c
] = c
;
2914 else if (ISLOWER (c
))
2916 mnemonic_chars
[c
] = c
;
2917 register_chars
[c
] = c
;
2918 operand_chars
[c
] = c
;
2920 else if (ISUPPER (c
))
2922 mnemonic_chars
[c
] = TOLOWER (c
);
2923 register_chars
[c
] = mnemonic_chars
[c
];
2924 operand_chars
[c
] = c
;
2926 else if (c
== '{' || c
== '}')
2928 mnemonic_chars
[c
] = c
;
2929 operand_chars
[c
] = c
;
2932 if (ISALPHA (c
) || ISDIGIT (c
))
2933 identifier_chars
[c
] = c
;
2936 identifier_chars
[c
] = c
;
2937 operand_chars
[c
] = c
;
2942 identifier_chars
['@'] = '@';
2945 identifier_chars
['?'] = '?';
2946 operand_chars
['?'] = '?';
2948 digit_chars
['-'] = '-';
2949 mnemonic_chars
['_'] = '_';
2950 mnemonic_chars
['-'] = '-';
2951 mnemonic_chars
['.'] = '.';
2952 identifier_chars
['_'] = '_';
2953 identifier_chars
['.'] = '.';
2955 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2956 operand_chars
[(unsigned char) *p
] = *p
;
2959 if (flag_code
== CODE_64BIT
)
2961 #if defined (OBJ_COFF) && defined (TE_PE)
2962 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2965 x86_dwarf2_return_column
= 16;
2967 x86_cie_data_alignment
= -8;
2971 x86_dwarf2_return_column
= 8;
2972 x86_cie_data_alignment
= -4;
2977 i386_print_statistics (FILE *file
)
2979 hash_print_statistics (file
, "i386 opcode", op_hash
);
2980 hash_print_statistics (file
, "i386 register", reg_hash
);
2985 /* Debugging routines for md_assemble. */
2986 static void pte (insn_template
*);
2987 static void pt (i386_operand_type
);
2988 static void pe (expressionS
*);
2989 static void ps (symbolS
*);
2992 pi (char *line
, i386_insn
*x
)
2996 fprintf (stdout
, "%s: template ", line
);
2998 fprintf (stdout
, " address: base %s index %s scale %x\n",
2999 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3000 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3001 x
->log2_scale_factor
);
3002 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3003 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3004 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3005 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3006 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3007 (x
->rex
& REX_W
) != 0,
3008 (x
->rex
& REX_R
) != 0,
3009 (x
->rex
& REX_X
) != 0,
3010 (x
->rex
& REX_B
) != 0);
3011 for (j
= 0; j
< x
->operands
; j
++)
3013 fprintf (stdout
, " #%d: ", j
+ 1);
3015 fprintf (stdout
, "\n");
3016 if (x
->types
[j
].bitfield
.reg
3017 || x
->types
[j
].bitfield
.regmmx
3018 || x
->types
[j
].bitfield
.regsimd
3019 || x
->types
[j
].bitfield
.sreg2
3020 || x
->types
[j
].bitfield
.sreg3
3021 || x
->types
[j
].bitfield
.control
3022 || x
->types
[j
].bitfield
.debug
3023 || x
->types
[j
].bitfield
.test
)
3024 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3025 if (operand_type_check (x
->types
[j
], imm
))
3027 if (operand_type_check (x
->types
[j
], disp
))
3028 pe (x
->op
[j
].disps
);
3033 pte (insn_template
*t
)
3036 fprintf (stdout
, " %d operands ", t
->operands
);
3037 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3038 if (t
->extension_opcode
!= None
)
3039 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3040 if (t
->opcode_modifier
.d
)
3041 fprintf (stdout
, "D");
3042 if (t
->opcode_modifier
.w
)
3043 fprintf (stdout
, "W");
3044 fprintf (stdout
, "\n");
3045 for (j
= 0; j
< t
->operands
; j
++)
3047 fprintf (stdout
, " #%d type ", j
+ 1);
3048 pt (t
->operand_types
[j
]);
3049 fprintf (stdout
, "\n");
3056 fprintf (stdout
, " operation %d\n", e
->X_op
);
3057 fprintf (stdout
, " add_number %ld (%lx)\n",
3058 (long) e
->X_add_number
, (long) e
->X_add_number
);
3059 if (e
->X_add_symbol
)
3061 fprintf (stdout
, " add_symbol ");
3062 ps (e
->X_add_symbol
);
3063 fprintf (stdout
, "\n");
3067 fprintf (stdout
, " op_symbol ");
3068 ps (e
->X_op_symbol
);
3069 fprintf (stdout
, "\n");
3076 fprintf (stdout
, "%s type %s%s",
3078 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3079 segment_name (S_GET_SEGMENT (s
)));
3082 static struct type_name
3084 i386_operand_type mask
;
3087 const type_names
[] =
3089 { OPERAND_TYPE_REG8
, "r8" },
3090 { OPERAND_TYPE_REG16
, "r16" },
3091 { OPERAND_TYPE_REG32
, "r32" },
3092 { OPERAND_TYPE_REG64
, "r64" },
3093 { OPERAND_TYPE_IMM8
, "i8" },
3094 { OPERAND_TYPE_IMM8
, "i8s" },
3095 { OPERAND_TYPE_IMM16
, "i16" },
3096 { OPERAND_TYPE_IMM32
, "i32" },
3097 { OPERAND_TYPE_IMM32S
, "i32s" },
3098 { OPERAND_TYPE_IMM64
, "i64" },
3099 { OPERAND_TYPE_IMM1
, "i1" },
3100 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3101 { OPERAND_TYPE_DISP8
, "d8" },
3102 { OPERAND_TYPE_DISP16
, "d16" },
3103 { OPERAND_TYPE_DISP32
, "d32" },
3104 { OPERAND_TYPE_DISP32S
, "d32s" },
3105 { OPERAND_TYPE_DISP64
, "d64" },
3106 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3107 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3108 { OPERAND_TYPE_CONTROL
, "control reg" },
3109 { OPERAND_TYPE_TEST
, "test reg" },
3110 { OPERAND_TYPE_DEBUG
, "debug reg" },
3111 { OPERAND_TYPE_FLOATREG
, "FReg" },
3112 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3113 { OPERAND_TYPE_SREG2
, "SReg2" },
3114 { OPERAND_TYPE_SREG3
, "SReg3" },
3115 { OPERAND_TYPE_ACC
, "Acc" },
3116 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3117 { OPERAND_TYPE_REGMMX
, "rMMX" },
3118 { OPERAND_TYPE_REGXMM
, "rXMM" },
3119 { OPERAND_TYPE_REGYMM
, "rYMM" },
3120 { OPERAND_TYPE_REGZMM
, "rZMM" },
3121 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3122 { OPERAND_TYPE_ESSEG
, "es" },
3126 pt (i386_operand_type t
)
3129 i386_operand_type a
;
3131 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3133 a
= operand_type_and (t
, type_names
[j
].mask
);
3134 if (!operand_type_all_zero (&a
))
3135 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3140 #endif /* DEBUG386 */
3142 static bfd_reloc_code_real_type
3143 reloc (unsigned int size
,
3146 bfd_reloc_code_real_type other
)
3148 if (other
!= NO_RELOC
)
3150 reloc_howto_type
*rel
;
3155 case BFD_RELOC_X86_64_GOT32
:
3156 return BFD_RELOC_X86_64_GOT64
;
3158 case BFD_RELOC_X86_64_GOTPLT64
:
3159 return BFD_RELOC_X86_64_GOTPLT64
;
3161 case BFD_RELOC_X86_64_PLTOFF64
:
3162 return BFD_RELOC_X86_64_PLTOFF64
;
3164 case BFD_RELOC_X86_64_GOTPC32
:
3165 other
= BFD_RELOC_X86_64_GOTPC64
;
3167 case BFD_RELOC_X86_64_GOTPCREL
:
3168 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3170 case BFD_RELOC_X86_64_TPOFF32
:
3171 other
= BFD_RELOC_X86_64_TPOFF64
;
3173 case BFD_RELOC_X86_64_DTPOFF32
:
3174 other
= BFD_RELOC_X86_64_DTPOFF64
;
3180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3181 if (other
== BFD_RELOC_SIZE32
)
3184 other
= BFD_RELOC_SIZE64
;
3187 as_bad (_("there are no pc-relative size relocations"));
3193 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3194 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3197 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3199 as_bad (_("unknown relocation (%u)"), other
);
3200 else if (size
!= bfd_get_reloc_size (rel
))
3201 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3202 bfd_get_reloc_size (rel
),
3204 else if (pcrel
&& !rel
->pc_relative
)
3205 as_bad (_("non-pc-relative relocation for pc-relative field"));
3206 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3208 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3210 as_bad (_("relocated field and relocation type differ in signedness"));
3219 as_bad (_("there are no unsigned pc-relative relocations"));
3222 case 1: return BFD_RELOC_8_PCREL
;
3223 case 2: return BFD_RELOC_16_PCREL
;
3224 case 4: return BFD_RELOC_32_PCREL
;
3225 case 8: return BFD_RELOC_64_PCREL
;
3227 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3234 case 4: return BFD_RELOC_X86_64_32S
;
3239 case 1: return BFD_RELOC_8
;
3240 case 2: return BFD_RELOC_16
;
3241 case 4: return BFD_RELOC_32
;
3242 case 8: return BFD_RELOC_64
;
3244 as_bad (_("cannot do %s %u byte relocation"),
3245 sign
> 0 ? "signed" : "unsigned", size
);
3251 /* Here we decide which fixups can be adjusted to make them relative to
3252 the beginning of the section instead of the symbol. Basically we need
3253 to make sure that the dynamic relocations are done correctly, so in
3254 some cases we force the original symbol to be used. */
3257 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3263 /* Don't adjust pc-relative references to merge sections in 64-bit
3265 if (use_rela_relocations
3266 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3270 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3271 and changed later by validate_fix. */
3272 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3273 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3276 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3277 for size relocations. */
3278 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3279 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3280 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3281 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3282 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3283 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3291 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3292 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3293 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3305 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3306 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3307 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3308 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3309 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3310 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3317 intel_float_operand (const char *mnemonic
)
3319 /* Note that the value returned is meaningful only for opcodes with (memory)
3320 operands, hence the code here is free to improperly handle opcodes that
3321 have no operands (for better performance and smaller code). */
3323 if (mnemonic
[0] != 'f')
3324 return 0; /* non-math */
3326 switch (mnemonic
[1])
3328 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3329 the fs segment override prefix not currently handled because no
3330 call path can make opcodes without operands get here */
3332 return 2 /* integer op */;
3334 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3335 return 3; /* fldcw/fldenv */
3338 if (mnemonic
[2] != 'o' /* fnop */)
3339 return 3; /* non-waiting control op */
3342 if (mnemonic
[2] == 's')
3343 return 3; /* frstor/frstpm */
3346 if (mnemonic
[2] == 'a')
3347 return 3; /* fsave */
3348 if (mnemonic
[2] == 't')
3350 switch (mnemonic
[3])
3352 case 'c': /* fstcw */
3353 case 'd': /* fstdw */
3354 case 'e': /* fstenv */
3355 case 's': /* fsts[gw] */
3361 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3362 return 0; /* fxsave/fxrstor are not really math ops */
3369 /* Build the VEX prefix. */
3372 build_vex_prefix (const insn_template
*t
)
3374 unsigned int register_specifier
;
3375 unsigned int implied_prefix
;
3376 unsigned int vector_length
;
3379 /* Check register specifier. */
3380 if (i
.vex
.register_specifier
)
3382 register_specifier
=
3383 ~register_number (i
.vex
.register_specifier
) & 0xf;
3384 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3387 register_specifier
= 0xf;
3389 /* Use 2-byte VEX prefix by swapping destination and source operand
3390 if there are more than 1 register operand. */
3391 if (i
.reg_operands
> 1
3392 && i
.vec_encoding
!= vex_encoding_vex3
3393 && i
.dir_encoding
== dir_encoding_default
3394 && i
.operands
== i
.reg_operands
3395 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3396 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3397 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3400 unsigned int xchg
= i
.operands
- 1;
3401 union i386_op temp_op
;
3402 i386_operand_type temp_type
;
3404 temp_type
= i
.types
[xchg
];
3405 i
.types
[xchg
] = i
.types
[0];
3406 i
.types
[0] = temp_type
;
3407 temp_op
= i
.op
[xchg
];
3408 i
.op
[xchg
] = i
.op
[0];
3411 gas_assert (i
.rm
.mode
== 3);
3415 i
.rm
.regmem
= i
.rm
.reg
;
3418 if (i
.tm
.opcode_modifier
.d
)
3419 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3420 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3421 else /* Use the next insn. */
3425 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3426 vector_length
= avxscalar
;
3427 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3433 /* Determine vector length from the last multi-length vector
3436 for (op
= t
->operands
; op
--;)
3437 if (t
->operand_types
[op
].bitfield
.xmmword
3438 && t
->operand_types
[op
].bitfield
.ymmword
3439 && i
.types
[op
].bitfield
.ymmword
)
3446 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3451 case DATA_PREFIX_OPCODE
:
3454 case REPE_PREFIX_OPCODE
:
3457 case REPNE_PREFIX_OPCODE
:
3464 /* Check the REX.W bit and VEXW. */
3465 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3466 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3467 else if (i
.tm
.opcode_modifier
.vexw
)
3468 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3470 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3472 /* Use 2-byte VEX prefix if possible. */
3474 && i
.vec_encoding
!= vex_encoding_vex3
3475 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3476 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3478 /* 2-byte VEX prefix. */
3482 i
.vex
.bytes
[0] = 0xc5;
3484 /* Check the REX.R bit. */
3485 r
= (i
.rex
& REX_R
) ? 0 : 1;
3486 i
.vex
.bytes
[1] = (r
<< 7
3487 | register_specifier
<< 3
3488 | vector_length
<< 2
3493 /* 3-byte VEX prefix. */
3498 switch (i
.tm
.opcode_modifier
.vexopcode
)
3502 i
.vex
.bytes
[0] = 0xc4;
3506 i
.vex
.bytes
[0] = 0xc4;
3510 i
.vex
.bytes
[0] = 0xc4;
3514 i
.vex
.bytes
[0] = 0x8f;
3518 i
.vex
.bytes
[0] = 0x8f;
3522 i
.vex
.bytes
[0] = 0x8f;
3528 /* The high 3 bits of the second VEX byte are 1's compliment
3529 of RXB bits from REX. */
3530 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3532 i
.vex
.bytes
[2] = (w
<< 7
3533 | register_specifier
<< 3
3534 | vector_length
<< 2
3539 static INLINE bfd_boolean
3540 is_evex_encoding (const insn_template
*t
)
3542 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3543 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3544 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3547 static INLINE bfd_boolean
3548 is_any_vex_encoding (const insn_template
*t
)
3550 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3551 || is_evex_encoding (t
);
3554 /* Build the EVEX prefix. */
3557 build_evex_prefix (void)
3559 unsigned int register_specifier
;
3560 unsigned int implied_prefix
;
3562 rex_byte vrex_used
= 0;
3564 /* Check register specifier. */
3565 if (i
.vex
.register_specifier
)
3567 gas_assert ((i
.vrex
& REX_X
) == 0);
3569 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3570 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3571 register_specifier
+= 8;
3572 /* The upper 16 registers are encoded in the fourth byte of the
3574 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3575 i
.vex
.bytes
[3] = 0x8;
3576 register_specifier
= ~register_specifier
& 0xf;
3580 register_specifier
= 0xf;
3582 /* Encode upper 16 vector index register in the fourth byte of
3584 if (!(i
.vrex
& REX_X
))
3585 i
.vex
.bytes
[3] = 0x8;
3590 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3595 case DATA_PREFIX_OPCODE
:
3598 case REPE_PREFIX_OPCODE
:
3601 case REPNE_PREFIX_OPCODE
:
3608 /* 4 byte EVEX prefix. */
3610 i
.vex
.bytes
[0] = 0x62;
3613 switch (i
.tm
.opcode_modifier
.vexopcode
)
3629 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3631 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3633 /* The fifth bit of the second EVEX byte is 1's compliment of the
3634 REX_R bit in VREX. */
3635 if (!(i
.vrex
& REX_R
))
3636 i
.vex
.bytes
[1] |= 0x10;
3640 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3642 /* When all operands are registers, the REX_X bit in REX is not
3643 used. We reuse it to encode the upper 16 registers, which is
3644 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3645 as 1's compliment. */
3646 if ((i
.vrex
& REX_B
))
3649 i
.vex
.bytes
[1] &= ~0x40;
3653 /* EVEX instructions shouldn't need the REX prefix. */
3654 i
.vrex
&= ~vrex_used
;
3655 gas_assert (i
.vrex
== 0);
3657 /* Check the REX.W bit and VEXW. */
3658 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3659 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3660 else if (i
.tm
.opcode_modifier
.vexw
)
3661 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3663 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3665 /* Encode the U bit. */
3666 implied_prefix
|= 0x4;
3668 /* The third byte of the EVEX prefix. */
3669 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3671 /* The fourth byte of the EVEX prefix. */
3672 /* The zeroing-masking bit. */
3673 if (i
.mask
&& i
.mask
->zeroing
)
3674 i
.vex
.bytes
[3] |= 0x80;
3676 /* Don't always set the broadcast bit if there is no RC. */
3679 /* Encode the vector length. */
3680 unsigned int vec_length
;
3682 if (!i
.tm
.opcode_modifier
.evex
3683 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3687 /* Determine vector length from the last multi-length vector
3690 for (op
= i
.operands
; op
--;)
3691 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3692 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3693 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3695 if (i
.types
[op
].bitfield
.zmmword
)
3697 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3700 else if (i
.types
[op
].bitfield
.ymmword
)
3702 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3705 else if (i
.types
[op
].bitfield
.xmmword
)
3707 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3710 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3712 switch (i
.broadcast
->bytes
)
3715 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3718 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3721 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3730 if (op
>= MAX_OPERANDS
)
3734 switch (i
.tm
.opcode_modifier
.evex
)
3736 case EVEXLIG
: /* LL' is ignored */
3737 vec_length
= evexlig
<< 5;
3740 vec_length
= 0 << 5;
3743 vec_length
= 1 << 5;
3746 vec_length
= 2 << 5;
3752 i
.vex
.bytes
[3] |= vec_length
;
3753 /* Encode the broadcast bit. */
3755 i
.vex
.bytes
[3] |= 0x10;
3759 if (i
.rounding
->type
!= saeonly
)
3760 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3762 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3765 if (i
.mask
&& i
.mask
->mask
)
3766 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3770 process_immext (void)
3774 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3777 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3778 with an opcode suffix which is coded in the same place as an
3779 8-bit immediate field would be.
3780 Here we check those operands and remove them afterwards. */
3783 for (x
= 0; x
< i
.operands
; x
++)
3784 if (register_number (i
.op
[x
].regs
) != x
)
3785 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3786 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3792 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3794 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3795 suffix which is coded in the same place as an 8-bit immediate
3797 Here we check those operands and remove them afterwards. */
3800 if (i
.operands
!= 3)
3803 for (x
= 0; x
< 2; x
++)
3804 if (register_number (i
.op
[x
].regs
) != x
)
3805 goto bad_register_operand
;
3807 /* Check for third operand for mwaitx/monitorx insn. */
3808 if (register_number (i
.op
[x
].regs
)
3809 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3811 bad_register_operand
:
3812 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3813 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3820 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3821 which is coded in the same place as an 8-bit immediate field
3822 would be. Here we fake an 8-bit immediate operand from the
3823 opcode suffix stored in tm.extension_opcode.
3825 AVX instructions also use this encoding, for some of
3826 3 argument instructions. */
3828 gas_assert (i
.imm_operands
<= 1
3830 || (is_any_vex_encoding (&i
.tm
)
3831 && i
.operands
<= 4)));
3833 exp
= &im_expressions
[i
.imm_operands
++];
3834 i
.op
[i
.operands
].imms
= exp
;
3835 i
.types
[i
.operands
] = imm8
;
3837 exp
->X_op
= O_constant
;
3838 exp
->X_add_number
= i
.tm
.extension_opcode
;
3839 i
.tm
.extension_opcode
= None
;
3846 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3851 as_bad (_("invalid instruction `%s' after `%s'"),
3852 i
.tm
.name
, i
.hle_prefix
);
3855 if (i
.prefix
[LOCK_PREFIX
])
3857 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3861 case HLEPrefixRelease
:
3862 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3864 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3868 if (i
.mem_operands
== 0
3869 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3871 as_bad (_("memory destination needed for instruction `%s'"
3872 " after `xrelease'"), i
.tm
.name
);
3879 /* Try the shortest encoding by shortening operand size. */
3882 optimize_encoding (void)
3886 if (optimize_for_space
3887 && i
.reg_operands
== 1
3888 && i
.imm_operands
== 1
3889 && !i
.types
[1].bitfield
.byte
3890 && i
.op
[0].imms
->X_op
== O_constant
3891 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3892 && ((i
.tm
.base_opcode
== 0xa8
3893 && i
.tm
.extension_opcode
== None
)
3894 || (i
.tm
.base_opcode
== 0xf6
3895 && i
.tm
.extension_opcode
== 0x0)))
3898 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3900 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3901 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3903 i
.types
[1].bitfield
.byte
= 1;
3904 /* Ignore the suffix. */
3906 if (base_regnum
>= 4
3907 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3909 /* Handle SP, BP, SI and DI registers. */
3910 if (i
.types
[1].bitfield
.word
)
3912 else if (i
.types
[1].bitfield
.dword
)
3920 else if (flag_code
== CODE_64BIT
3921 && ((i
.types
[1].bitfield
.qword
3922 && i
.reg_operands
== 1
3923 && i
.imm_operands
== 1
3924 && i
.op
[0].imms
->X_op
== O_constant
3925 && ((i
.tm
.base_opcode
== 0xb0
3926 && i
.tm
.extension_opcode
== None
3927 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3928 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3929 && (((i
.tm
.base_opcode
== 0x24
3930 || i
.tm
.base_opcode
== 0xa8)
3931 && i
.tm
.extension_opcode
== None
)
3932 || (i
.tm
.base_opcode
== 0x80
3933 && i
.tm
.extension_opcode
== 0x4)
3934 || ((i
.tm
.base_opcode
== 0xf6
3935 || i
.tm
.base_opcode
== 0xc6)
3936 && i
.tm
.extension_opcode
== 0x0)))))
3937 || (i
.types
[0].bitfield
.qword
3938 && ((i
.reg_operands
== 2
3939 && i
.op
[0].regs
== i
.op
[1].regs
3940 && ((i
.tm
.base_opcode
== 0x30
3941 || i
.tm
.base_opcode
== 0x28)
3942 && i
.tm
.extension_opcode
== None
))
3943 || (i
.reg_operands
== 1
3945 && i
.tm
.base_opcode
== 0x30
3946 && i
.tm
.extension_opcode
== None
)))))
3949 andq $imm31, %r64 -> andl $imm31, %r32
3950 testq $imm31, %r64 -> testl $imm31, %r32
3951 xorq %r64, %r64 -> xorl %r32, %r32
3952 subq %r64, %r64 -> subl %r32, %r32
3953 movq $imm31, %r64 -> movl $imm31, %r32
3954 movq $imm32, %r64 -> movl $imm32, %r32
3956 i
.tm
.opcode_modifier
.norex64
= 1;
3957 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3960 movq $imm31, %r64 -> movl $imm31, %r32
3961 movq $imm32, %r64 -> movl $imm32, %r32
3963 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3964 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3965 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3966 i
.types
[0].bitfield
.imm32
= 1;
3967 i
.types
[0].bitfield
.imm32s
= 0;
3968 i
.types
[0].bitfield
.imm64
= 0;
3969 i
.types
[1].bitfield
.dword
= 1;
3970 i
.types
[1].bitfield
.qword
= 0;
3971 if (i
.tm
.base_opcode
== 0xc6)
3974 movq $imm31, %r64 -> movl $imm31, %r32
3976 i
.tm
.base_opcode
= 0xb0;
3977 i
.tm
.extension_opcode
= None
;
3978 i
.tm
.opcode_modifier
.shortform
= 1;
3979 i
.tm
.opcode_modifier
.modrm
= 0;
3983 else if (i
.reg_operands
== 3
3984 && i
.op
[0].regs
== i
.op
[1].regs
3985 && !i
.types
[2].bitfield
.xmmword
3986 && (i
.tm
.opcode_modifier
.vex
3987 || ((!i
.mask
|| i
.mask
->zeroing
)
3989 && is_evex_encoding (&i
.tm
)
3990 && (i
.vec_encoding
!= vex_encoding_evex
3991 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
3992 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3993 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3994 && i
.types
[2].bitfield
.ymmword
))))
3995 && ((i
.tm
.base_opcode
== 0x55
3996 || i
.tm
.base_opcode
== 0x6655
3997 || i
.tm
.base_opcode
== 0x66df
3998 || i
.tm
.base_opcode
== 0x57
3999 || i
.tm
.base_opcode
== 0x6657
4000 || i
.tm
.base_opcode
== 0x66ef
4001 || i
.tm
.base_opcode
== 0x66f8
4002 || i
.tm
.base_opcode
== 0x66f9
4003 || i
.tm
.base_opcode
== 0x66fa
4004 || i
.tm
.base_opcode
== 0x66fb
4005 || i
.tm
.base_opcode
== 0x42
4006 || i
.tm
.base_opcode
== 0x6642
4007 || i
.tm
.base_opcode
== 0x47
4008 || i
.tm
.base_opcode
== 0x6647)
4009 && i
.tm
.extension_opcode
== None
))
4012 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4014 EVEX VOP %zmmM, %zmmM, %zmmN
4015 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4017 EVEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4019 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4020 VEX VOP %ymmM, %ymmM, %ymmN
4021 -> VEX VOP %xmmM, %xmmM, %xmmN
4022 VOP, one of vpandn and vpxor:
4023 VEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX VOP %xmmM, %xmmM, %xmmN
4025 VOP, one of vpandnd and vpandnq:
4026 EVEX VOP %zmmM, %zmmM, %zmmN
4027 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 EVEX VOP %ymmM, %ymmM, %ymmN
4030 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4031 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4032 VOP, one of vpxord and vpxorq:
4033 EVEX VOP %zmmM, %zmmM, %zmmN
4034 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 EVEX VOP %ymmM, %ymmM, %ymmN
4037 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4038 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4039 VOP, one of kxord and kxorq:
4040 VEX VOP %kM, %kM, %kN
4041 -> VEX kxorw %kM, %kM, %kN
4042 VOP, one of kandnd and kandnq:
4043 VEX VOP %kM, %kM, %kN
4044 -> VEX kandnw %kM, %kM, %kN
4046 if (is_evex_encoding (&i
.tm
))
4048 if (i
.vec_encoding
!= vex_encoding_evex
)
4050 i
.tm
.opcode_modifier
.vex
= VEX128
;
4051 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4052 i
.tm
.opcode_modifier
.evex
= 0;
4054 else if (optimize
> 1)
4055 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4059 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4061 i
.tm
.base_opcode
&= 0xff;
4062 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4065 i
.tm
.opcode_modifier
.vex
= VEX128
;
4067 if (i
.tm
.opcode_modifier
.vex
)
4068 for (j
= 0; j
< 3; j
++)
4070 i
.types
[j
].bitfield
.xmmword
= 1;
4071 i
.types
[j
].bitfield
.ymmword
= 0;
4074 else if (i
.vec_encoding
!= vex_encoding_evex
4075 && !i
.types
[0].bitfield
.zmmword
4076 && !i
.types
[1].bitfield
.zmmword
4078 && is_evex_encoding (&i
.tm
)
4079 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4080 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4081 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4082 && i
.tm
.extension_opcode
== None
)
4085 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4086 vmovdqu32 and vmovdqu64:
4087 EVEX VOP %xmmM, %xmmN
4088 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4089 EVEX VOP %ymmM, %ymmN
4090 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4092 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4094 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4096 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4098 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4100 for (j
= 0; j
< 2; j
++)
4101 if (operand_type_check (i
.types
[j
], disp
)
4102 && i
.op
[j
].disps
->X_op
== O_constant
)
4104 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4105 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4106 bytes, we choose EVEX Disp8 over VEX Disp32. */
4107 int evex_disp8
, vex_disp8
;
4108 unsigned int memshift
= i
.memshift
;
4109 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4111 evex_disp8
= fits_in_disp8 (n
);
4113 vex_disp8
= fits_in_disp8 (n
);
4114 if (evex_disp8
!= vex_disp8
)
4116 i
.memshift
= memshift
;
4120 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4123 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4124 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4125 i
.tm
.opcode_modifier
.vex
4126 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4127 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4128 i
.tm
.opcode_modifier
.evex
= 0;
4129 i
.tm
.opcode_modifier
.masking
= 0;
4130 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4132 for (j
= 0; j
< 2; j
++)
4133 if (operand_type_check (i
.types
[j
], disp
)
4134 && i
.op
[j
].disps
->X_op
== O_constant
)
4136 i
.types
[j
].bitfield
.disp8
4137 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4143 /* This is the guts of the machine-dependent assembler. LINE points to a
4144 machine dependent instruction. This function is supposed to emit
4145 the frags/bytes it assembles to. */
4148 md_assemble (char *line
)
4151 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4152 const insn_template
*t
;
4154 /* Initialize globals. */
4155 memset (&i
, '\0', sizeof (i
));
4156 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4157 i
.reloc
[j
] = NO_RELOC
;
4158 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4159 memset (im_expressions
, '\0', sizeof (im_expressions
));
4160 save_stack_p
= save_stack
;
4162 /* First parse an instruction mnemonic & call i386_operand for the operands.
4163 We assume that the scrubber has arranged it so that line[0] is the valid
4164 start of a (possibly prefixed) mnemonic. */
4166 line
= parse_insn (line
, mnemonic
);
4169 mnem_suffix
= i
.suffix
;
4171 line
= parse_operands (line
, mnemonic
);
4173 xfree (i
.memop1_string
);
4174 i
.memop1_string
= NULL
;
4178 /* Now we've parsed the mnemonic into a set of templates, and have the
4179 operands at hand. */
4181 /* All intel opcodes have reversed operands except for "bound" and
4182 "enter". We also don't reverse intersegment "jmp" and "call"
4183 instructions with 2 immediate operands so that the immediate segment
4184 precedes the offset, as it does when in AT&T mode. */
4187 && (strcmp (mnemonic
, "bound") != 0)
4188 && (strcmp (mnemonic
, "invlpga") != 0)
4189 && !(operand_type_check (i
.types
[0], imm
)
4190 && operand_type_check (i
.types
[1], imm
)))
4193 /* The order of the immediates should be reversed
4194 for 2 immediates extrq and insertq instructions */
4195 if (i
.imm_operands
== 2
4196 && (strcmp (mnemonic
, "extrq") == 0
4197 || strcmp (mnemonic
, "insertq") == 0))
4198 swap_2_operands (0, 1);
4203 /* Don't optimize displacement for movabs since it only takes 64bit
4206 && i
.disp_encoding
!= disp_encoding_32bit
4207 && (flag_code
!= CODE_64BIT
4208 || strcmp (mnemonic
, "movabs") != 0))
4211 /* Next, we find a template that matches the given insn,
4212 making sure the overlap of the given operands types is consistent
4213 with the template operand types. */
4215 if (!(t
= match_template (mnem_suffix
)))
4218 if (sse_check
!= check_none
4219 && !i
.tm
.opcode_modifier
.noavx
4220 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4221 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4222 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4223 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4224 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4225 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4226 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4227 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4228 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4229 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4231 (sse_check
== check_warning
4233 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4236 /* Zap movzx and movsx suffix. The suffix has been set from
4237 "word ptr" or "byte ptr" on the source operand in Intel syntax
4238 or extracted from mnemonic in AT&T syntax. But we'll use
4239 the destination register to choose the suffix for encoding. */
4240 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4242 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4243 there is no suffix, the default will be byte extension. */
4244 if (i
.reg_operands
!= 2
4247 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4252 if (i
.tm
.opcode_modifier
.fwait
)
4253 if (!add_prefix (FWAIT_OPCODE
))
4256 /* Check if REP prefix is OK. */
4257 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4259 as_bad (_("invalid instruction `%s' after `%s'"),
4260 i
.tm
.name
, i
.rep_prefix
);
4264 /* Check for lock without a lockable instruction. Destination operand
4265 must be memory unless it is xchg (0x86). */
4266 if (i
.prefix
[LOCK_PREFIX
]
4267 && (!i
.tm
.opcode_modifier
.islockable
4268 || i
.mem_operands
== 0
4269 || (i
.tm
.base_opcode
!= 0x86
4270 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4272 as_bad (_("expecting lockable instruction after `lock'"));
4276 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4277 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4279 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4283 /* Check if HLE prefix is OK. */
4284 if (i
.hle_prefix
&& !check_hle ())
4287 /* Check BND prefix. */
4288 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4289 as_bad (_("expecting valid branch instruction after `bnd'"));
4291 /* Check NOTRACK prefix. */
4292 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4293 as_bad (_("expecting indirect branch instruction after `notrack'"));
4295 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4297 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4298 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4299 else if (flag_code
!= CODE_16BIT
4300 ? i
.prefix
[ADDR_PREFIX
]
4301 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4302 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4305 /* Insert BND prefix. */
4306 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4308 if (!i
.prefix
[BND_PREFIX
])
4309 add_prefix (BND_PREFIX_OPCODE
);
4310 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4312 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4313 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4317 /* Check string instruction segment overrides. */
4318 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4320 if (!check_string ())
4322 i
.disp_operands
= 0;
4325 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4326 optimize_encoding ();
4328 if (!process_suffix ())
4331 /* Update operand types. */
4332 for (j
= 0; j
< i
.operands
; j
++)
4333 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4335 /* Make still unresolved immediate matches conform to size of immediate
4336 given in i.suffix. */
4337 if (!finalize_imm ())
4340 if (i
.types
[0].bitfield
.imm1
)
4341 i
.imm_operands
= 0; /* kludge for shift insns. */
4343 /* We only need to check those implicit registers for instructions
4344 with 3 operands or less. */
4345 if (i
.operands
<= 3)
4346 for (j
= 0; j
< i
.operands
; j
++)
4347 if (i
.types
[j
].bitfield
.inoutportreg
4348 || i
.types
[j
].bitfield
.shiftcount
4349 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4352 /* ImmExt should be processed after SSE2AVX. */
4353 if (!i
.tm
.opcode_modifier
.sse2avx
4354 && i
.tm
.opcode_modifier
.immext
)
4357 /* For insns with operands there are more diddles to do to the opcode. */
4360 if (!process_operands ())
4363 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4365 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4366 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4369 if (is_any_vex_encoding (&i
.tm
))
4371 if (flag_code
== CODE_16BIT
)
4373 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4378 if (i
.tm
.opcode_modifier
.vex
)
4379 build_vex_prefix (t
);
4381 build_evex_prefix ();
4384 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4385 instructions may define INT_OPCODE as well, so avoid this corner
4386 case for those instructions that use MODRM. */
4387 if (i
.tm
.base_opcode
== INT_OPCODE
4388 && !i
.tm
.opcode_modifier
.modrm
4389 && i
.op
[0].imms
->X_add_number
== 3)
4391 i
.tm
.base_opcode
= INT3_OPCODE
;
4395 if ((i
.tm
.opcode_modifier
.jump
4396 || i
.tm
.opcode_modifier
.jumpbyte
4397 || i
.tm
.opcode_modifier
.jumpdword
)
4398 && i
.op
[0].disps
->X_op
== O_constant
)
4400 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4401 the absolute address given by the constant. Since ix86 jumps and
4402 calls are pc relative, we need to generate a reloc. */
4403 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4404 i
.op
[0].disps
->X_op
= O_symbol
;
4407 if (i
.tm
.opcode_modifier
.rex64
)
4410 /* For 8 bit registers we need an empty rex prefix. Also if the
4411 instruction already has a prefix, we need to convert old
4412 registers to new ones. */
4414 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4415 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4416 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4417 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4418 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4419 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4424 i
.rex
|= REX_OPCODE
;
4425 for (x
= 0; x
< 2; x
++)
4427 /* Look for 8 bit operand that uses old registers. */
4428 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4429 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4431 /* In case it is "hi" register, give up. */
4432 if (i
.op
[x
].regs
->reg_num
> 3)
4433 as_bad (_("can't encode register '%s%s' in an "
4434 "instruction requiring REX prefix."),
4435 register_prefix
, i
.op
[x
].regs
->reg_name
);
4437 /* Otherwise it is equivalent to the extended register.
4438 Since the encoding doesn't change this is merely
4439 cosmetic cleanup for debug output. */
4441 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4446 if (i
.rex
== 0 && i
.rex_encoding
)
4448 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4449 that uses legacy register. If it is "hi" register, don't add
4450 the REX_OPCODE byte. */
4452 for (x
= 0; x
< 2; x
++)
4453 if (i
.types
[x
].bitfield
.reg
4454 && i
.types
[x
].bitfield
.byte
4455 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4456 && i
.op
[x
].regs
->reg_num
> 3)
4458 i
.rex_encoding
= FALSE
;
4467 add_prefix (REX_OPCODE
| i
.rex
);
4469 /* We are ready to output the insn. */
4474 parse_insn (char *line
, char *mnemonic
)
4477 char *token_start
= l
;
4480 const insn_template
*t
;
4486 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4491 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4493 as_bad (_("no such instruction: `%s'"), token_start
);
4498 if (!is_space_char (*l
)
4499 && *l
!= END_OF_INSN
4501 || (*l
!= PREFIX_SEPARATOR
4504 as_bad (_("invalid character %s in mnemonic"),
4505 output_invalid (*l
));
4508 if (token_start
== l
)
4510 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4511 as_bad (_("expecting prefix; got nothing"));
4513 as_bad (_("expecting mnemonic; got nothing"));
4517 /* Look up instruction (or prefix) via hash table. */
4518 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4520 if (*l
!= END_OF_INSN
4521 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4522 && current_templates
4523 && current_templates
->start
->opcode_modifier
.isprefix
)
4525 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4527 as_bad ((flag_code
!= CODE_64BIT
4528 ? _("`%s' is only supported in 64-bit mode")
4529 : _("`%s' is not supported in 64-bit mode")),
4530 current_templates
->start
->name
);
4533 /* If we are in 16-bit mode, do not allow addr16 or data16.
4534 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4535 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4536 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4537 && flag_code
!= CODE_64BIT
4538 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4539 ^ (flag_code
== CODE_16BIT
)))
4541 as_bad (_("redundant %s prefix"),
4542 current_templates
->start
->name
);
4545 if (current_templates
->start
->opcode_length
== 0)
4547 /* Handle pseudo prefixes. */
4548 switch (current_templates
->start
->base_opcode
)
4552 i
.disp_encoding
= disp_encoding_8bit
;
4556 i
.disp_encoding
= disp_encoding_32bit
;
4560 i
.dir_encoding
= dir_encoding_load
;
4564 i
.dir_encoding
= dir_encoding_store
;
4568 i
.vec_encoding
= vex_encoding_vex2
;
4572 i
.vec_encoding
= vex_encoding_vex3
;
4576 i
.vec_encoding
= vex_encoding_evex
;
4580 i
.rex_encoding
= TRUE
;
4584 i
.no_optimize
= TRUE
;
4592 /* Add prefix, checking for repeated prefixes. */
4593 switch (add_prefix (current_templates
->start
->base_opcode
))
4598 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4599 i
.notrack_prefix
= current_templates
->start
->name
;
4602 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4603 i
.hle_prefix
= current_templates
->start
->name
;
4604 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4605 i
.bnd_prefix
= current_templates
->start
->name
;
4607 i
.rep_prefix
= current_templates
->start
->name
;
4613 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4620 if (!current_templates
)
4622 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4623 Check if we should swap operand or force 32bit displacement in
4625 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4626 i
.dir_encoding
= dir_encoding_swap
;
4627 else if (mnem_p
- 3 == dot_p
4630 i
.disp_encoding
= disp_encoding_8bit
;
4631 else if (mnem_p
- 4 == dot_p
4635 i
.disp_encoding
= disp_encoding_32bit
;
4640 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4643 if (!current_templates
)
4646 if (mnem_p
> mnemonic
)
4648 /* See if we can get a match by trimming off a suffix. */
4651 case WORD_MNEM_SUFFIX
:
4652 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4653 i
.suffix
= SHORT_MNEM_SUFFIX
;
4656 case BYTE_MNEM_SUFFIX
:
4657 case QWORD_MNEM_SUFFIX
:
4658 i
.suffix
= mnem_p
[-1];
4660 current_templates
= (const templates
*) hash_find (op_hash
,
4663 case SHORT_MNEM_SUFFIX
:
4664 case LONG_MNEM_SUFFIX
:
4667 i
.suffix
= mnem_p
[-1];
4669 current_templates
= (const templates
*) hash_find (op_hash
,
4678 if (intel_float_operand (mnemonic
) == 1)
4679 i
.suffix
= SHORT_MNEM_SUFFIX
;
4681 i
.suffix
= LONG_MNEM_SUFFIX
;
4683 current_templates
= (const templates
*) hash_find (op_hash
,
4690 if (!current_templates
)
4692 as_bad (_("no such instruction: `%s'"), token_start
);
4697 if (current_templates
->start
->opcode_modifier
.jump
4698 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4700 /* Check for a branch hint. We allow ",pt" and ",pn" for
4701 predict taken and predict not taken respectively.
4702 I'm not sure that branch hints actually do anything on loop
4703 and jcxz insns (JumpByte) for current Pentium4 chips. They
4704 may work in the future and it doesn't hurt to accept them
4706 if (l
[0] == ',' && l
[1] == 'p')
4710 if (!add_prefix (DS_PREFIX_OPCODE
))
4714 else if (l
[2] == 'n')
4716 if (!add_prefix (CS_PREFIX_OPCODE
))
4722 /* Any other comma loses. */
4725 as_bad (_("invalid character %s in mnemonic"),
4726 output_invalid (*l
));
4730 /* Check if instruction is supported on specified architecture. */
4732 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4734 supported
|= cpu_flags_match (t
);
4735 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4737 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4738 as_warn (_("use .code16 to ensure correct addressing mode"));
4744 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4745 as_bad (flag_code
== CODE_64BIT
4746 ? _("`%s' is not supported in 64-bit mode")
4747 : _("`%s' is only supported in 64-bit mode"),
4748 current_templates
->start
->name
);
4750 as_bad (_("`%s' is not supported on `%s%s'"),
4751 current_templates
->start
->name
,
4752 cpu_arch_name
? cpu_arch_name
: default_arch
,
4753 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4759 parse_operands (char *l
, const char *mnemonic
)
4763 /* 1 if operand is pending after ','. */
4764 unsigned int expecting_operand
= 0;
4766 /* Non-zero if operand parens not balanced. */
4767 unsigned int paren_not_balanced
;
4769 while (*l
!= END_OF_INSN
)
4771 /* Skip optional white space before operand. */
4772 if (is_space_char (*l
))
4774 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4776 as_bad (_("invalid character %s before operand %d"),
4777 output_invalid (*l
),
4781 token_start
= l
; /* After white space. */
4782 paren_not_balanced
= 0;
4783 while (paren_not_balanced
|| *l
!= ',')
4785 if (*l
== END_OF_INSN
)
4787 if (paren_not_balanced
)
4790 as_bad (_("unbalanced parenthesis in operand %d."),
4793 as_bad (_("unbalanced brackets in operand %d."),
4798 break; /* we are done */
4800 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4802 as_bad (_("invalid character %s in operand %d"),
4803 output_invalid (*l
),
4810 ++paren_not_balanced
;
4812 --paren_not_balanced
;
4817 ++paren_not_balanced
;
4819 --paren_not_balanced
;
4823 if (l
!= token_start
)
4824 { /* Yes, we've read in another operand. */
4825 unsigned int operand_ok
;
4826 this_operand
= i
.operands
++;
4827 if (i
.operands
> MAX_OPERANDS
)
4829 as_bad (_("spurious operands; (%d operands/instruction max)"),
4833 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4834 /* Now parse operand adding info to 'i' as we go along. */
4835 END_STRING_AND_SAVE (l
);
4837 if (i
.mem_operands
> 1)
4839 as_bad (_("too many memory references for `%s'"),
4846 i386_intel_operand (token_start
,
4847 intel_float_operand (mnemonic
));
4849 operand_ok
= i386_att_operand (token_start
);
4851 RESTORE_END_STRING (l
);
4857 if (expecting_operand
)
4859 expecting_operand_after_comma
:
4860 as_bad (_("expecting operand after ','; got nothing"));
4865 as_bad (_("expecting operand before ','; got nothing"));
4870 /* Now *l must be either ',' or END_OF_INSN. */
4873 if (*++l
== END_OF_INSN
)
4875 /* Just skip it, if it's \n complain. */
4876 goto expecting_operand_after_comma
;
4878 expecting_operand
= 1;
4885 swap_2_operands (int xchg1
, int xchg2
)
4887 union i386_op temp_op
;
4888 i386_operand_type temp_type
;
4889 unsigned int temp_flags
;
4890 enum bfd_reloc_code_real temp_reloc
;
4892 temp_type
= i
.types
[xchg2
];
4893 i
.types
[xchg2
] = i
.types
[xchg1
];
4894 i
.types
[xchg1
] = temp_type
;
4896 temp_flags
= i
.flags
[xchg2
];
4897 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4898 i
.flags
[xchg1
] = temp_flags
;
4900 temp_op
= i
.op
[xchg2
];
4901 i
.op
[xchg2
] = i
.op
[xchg1
];
4902 i
.op
[xchg1
] = temp_op
;
4904 temp_reloc
= i
.reloc
[xchg2
];
4905 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4906 i
.reloc
[xchg1
] = temp_reloc
;
4910 if (i
.mask
->operand
== xchg1
)
4911 i
.mask
->operand
= xchg2
;
4912 else if (i
.mask
->operand
== xchg2
)
4913 i
.mask
->operand
= xchg1
;
4917 if (i
.broadcast
->operand
== xchg1
)
4918 i
.broadcast
->operand
= xchg2
;
4919 else if (i
.broadcast
->operand
== xchg2
)
4920 i
.broadcast
->operand
= xchg1
;
4924 if (i
.rounding
->operand
== xchg1
)
4925 i
.rounding
->operand
= xchg2
;
4926 else if (i
.rounding
->operand
== xchg2
)
4927 i
.rounding
->operand
= xchg1
;
4932 swap_operands (void)
4938 swap_2_operands (1, i
.operands
- 2);
4942 swap_2_operands (0, i
.operands
- 1);
4948 if (i
.mem_operands
== 2)
4950 const seg_entry
*temp_seg
;
4951 temp_seg
= i
.seg
[0];
4952 i
.seg
[0] = i
.seg
[1];
4953 i
.seg
[1] = temp_seg
;
4957 /* Try to ensure constant immediates are represented in the smallest
4962 char guess_suffix
= 0;
4966 guess_suffix
= i
.suffix
;
4967 else if (i
.reg_operands
)
4969 /* Figure out a suffix from the last register operand specified.
4970 We can't do this properly yet, ie. excluding InOutPortReg,
4971 but the following works for instructions with immediates.
4972 In any case, we can't set i.suffix yet. */
4973 for (op
= i
.operands
; --op
>= 0;)
4974 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4976 guess_suffix
= BYTE_MNEM_SUFFIX
;
4979 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4981 guess_suffix
= WORD_MNEM_SUFFIX
;
4984 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4986 guess_suffix
= LONG_MNEM_SUFFIX
;
4989 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4991 guess_suffix
= QWORD_MNEM_SUFFIX
;
4995 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4996 guess_suffix
= WORD_MNEM_SUFFIX
;
4998 for (op
= i
.operands
; --op
>= 0;)
4999 if (operand_type_check (i
.types
[op
], imm
))
5001 switch (i
.op
[op
].imms
->X_op
)
5004 /* If a suffix is given, this operand may be shortened. */
5005 switch (guess_suffix
)
5007 case LONG_MNEM_SUFFIX
:
5008 i
.types
[op
].bitfield
.imm32
= 1;
5009 i
.types
[op
].bitfield
.imm64
= 1;
5011 case WORD_MNEM_SUFFIX
:
5012 i
.types
[op
].bitfield
.imm16
= 1;
5013 i
.types
[op
].bitfield
.imm32
= 1;
5014 i
.types
[op
].bitfield
.imm32s
= 1;
5015 i
.types
[op
].bitfield
.imm64
= 1;
5017 case BYTE_MNEM_SUFFIX
:
5018 i
.types
[op
].bitfield
.imm8
= 1;
5019 i
.types
[op
].bitfield
.imm8s
= 1;
5020 i
.types
[op
].bitfield
.imm16
= 1;
5021 i
.types
[op
].bitfield
.imm32
= 1;
5022 i
.types
[op
].bitfield
.imm32s
= 1;
5023 i
.types
[op
].bitfield
.imm64
= 1;
5027 /* If this operand is at most 16 bits, convert it
5028 to a signed 16 bit number before trying to see
5029 whether it will fit in an even smaller size.
5030 This allows a 16-bit operand such as $0xffe0 to
5031 be recognised as within Imm8S range. */
5032 if ((i
.types
[op
].bitfield
.imm16
)
5033 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5035 i
.op
[op
].imms
->X_add_number
=
5036 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5039 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5040 if ((i
.types
[op
].bitfield
.imm32
)
5041 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5044 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5045 ^ ((offsetT
) 1 << 31))
5046 - ((offsetT
) 1 << 31));
5050 = operand_type_or (i
.types
[op
],
5051 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5053 /* We must avoid matching of Imm32 templates when 64bit
5054 only immediate is available. */
5055 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5056 i
.types
[op
].bitfield
.imm32
= 0;
5063 /* Symbols and expressions. */
5065 /* Convert symbolic operand to proper sizes for matching, but don't
5066 prevent matching a set of insns that only supports sizes other
5067 than those matching the insn suffix. */
5069 i386_operand_type mask
, allowed
;
5070 const insn_template
*t
;
5072 operand_type_set (&mask
, 0);
5073 operand_type_set (&allowed
, 0);
5075 for (t
= current_templates
->start
;
5076 t
< current_templates
->end
;
5078 allowed
= operand_type_or (allowed
,
5079 t
->operand_types
[op
]);
5080 switch (guess_suffix
)
5082 case QWORD_MNEM_SUFFIX
:
5083 mask
.bitfield
.imm64
= 1;
5084 mask
.bitfield
.imm32s
= 1;
5086 case LONG_MNEM_SUFFIX
:
5087 mask
.bitfield
.imm32
= 1;
5089 case WORD_MNEM_SUFFIX
:
5090 mask
.bitfield
.imm16
= 1;
5092 case BYTE_MNEM_SUFFIX
:
5093 mask
.bitfield
.imm8
= 1;
5098 allowed
= operand_type_and (mask
, allowed
);
5099 if (!operand_type_all_zero (&allowed
))
5100 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5107 /* Try to use the smallest displacement type too. */
5109 optimize_disp (void)
5113 for (op
= i
.operands
; --op
>= 0;)
5114 if (operand_type_check (i
.types
[op
], disp
))
5116 if (i
.op
[op
].disps
->X_op
== O_constant
)
5118 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5120 if (i
.types
[op
].bitfield
.disp16
5121 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5123 /* If this operand is at most 16 bits, convert
5124 to a signed 16 bit number and don't use 64bit
5126 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5127 i
.types
[op
].bitfield
.disp64
= 0;
5130 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5131 if (i
.types
[op
].bitfield
.disp32
5132 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5134 /* If this operand is at most 32 bits, convert
5135 to a signed 32 bit number and don't use 64bit
5137 op_disp
&= (((offsetT
) 2 << 31) - 1);
5138 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5139 i
.types
[op
].bitfield
.disp64
= 0;
5142 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5144 i
.types
[op
].bitfield
.disp8
= 0;
5145 i
.types
[op
].bitfield
.disp16
= 0;
5146 i
.types
[op
].bitfield
.disp32
= 0;
5147 i
.types
[op
].bitfield
.disp32s
= 0;
5148 i
.types
[op
].bitfield
.disp64
= 0;
5152 else if (flag_code
== CODE_64BIT
)
5154 if (fits_in_signed_long (op_disp
))
5156 i
.types
[op
].bitfield
.disp64
= 0;
5157 i
.types
[op
].bitfield
.disp32s
= 1;
5159 if (i
.prefix
[ADDR_PREFIX
]
5160 && fits_in_unsigned_long (op_disp
))
5161 i
.types
[op
].bitfield
.disp32
= 1;
5163 if ((i
.types
[op
].bitfield
.disp32
5164 || i
.types
[op
].bitfield
.disp32s
5165 || i
.types
[op
].bitfield
.disp16
)
5166 && fits_in_disp8 (op_disp
))
5167 i
.types
[op
].bitfield
.disp8
= 1;
5169 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5170 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5172 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5173 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5174 i
.types
[op
].bitfield
.disp8
= 0;
5175 i
.types
[op
].bitfield
.disp16
= 0;
5176 i
.types
[op
].bitfield
.disp32
= 0;
5177 i
.types
[op
].bitfield
.disp32s
= 0;
5178 i
.types
[op
].bitfield
.disp64
= 0;
5181 /* We only support 64bit displacement on constants. */
5182 i
.types
[op
].bitfield
.disp64
= 0;
5186 /* Return 1 if there is a match in broadcast bytes between operand
5187 GIVEN and instruction template T. */
5190 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5192 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5193 && i
.types
[given
].bitfield
.byte
)
5194 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5195 && i
.types
[given
].bitfield
.word
)
5196 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5197 && i
.types
[given
].bitfield
.dword
)
5198 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5199 && i
.types
[given
].bitfield
.qword
));
5202 /* Check if operands are valid for the instruction. */
5205 check_VecOperands (const insn_template
*t
)
5209 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5211 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5212 any one operand are implicity requiring AVX512VL support if the actual
5213 operand size is YMMword or XMMword. Since this function runs after
5214 template matching, there's no need to check for YMMword/XMMword in
5216 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5217 if (!cpu_flags_all_zero (&cpu
)
5218 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5219 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5221 for (op
= 0; op
< t
->operands
; ++op
)
5223 if (t
->operand_types
[op
].bitfield
.zmmword
5224 && (i
.types
[op
].bitfield
.ymmword
5225 || i
.types
[op
].bitfield
.xmmword
))
5227 i
.error
= unsupported
;
5233 /* Without VSIB byte, we can't have a vector register for index. */
5234 if (!t
->opcode_modifier
.vecsib
5236 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5237 || i
.index_reg
->reg_type
.bitfield
.ymmword
5238 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5240 i
.error
= unsupported_vector_index_register
;
5244 /* Check if default mask is allowed. */
5245 if (t
->opcode_modifier
.nodefmask
5246 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5248 i
.error
= no_default_mask
;
5252 /* For VSIB byte, we need a vector register for index, and all vector
5253 registers must be distinct. */
5254 if (t
->opcode_modifier
.vecsib
)
5257 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5258 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5259 || (t
->opcode_modifier
.vecsib
== VecSIB256
5260 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5261 || (t
->opcode_modifier
.vecsib
== VecSIB512
5262 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5264 i
.error
= invalid_vsib_address
;
5268 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5269 if (i
.reg_operands
== 2 && !i
.mask
)
5271 gas_assert (i
.types
[0].bitfield
.regsimd
);
5272 gas_assert (i
.types
[0].bitfield
.xmmword
5273 || i
.types
[0].bitfield
.ymmword
);
5274 gas_assert (i
.types
[2].bitfield
.regsimd
);
5275 gas_assert (i
.types
[2].bitfield
.xmmword
5276 || i
.types
[2].bitfield
.ymmword
);
5277 if (operand_check
== check_none
)
5279 if (register_number (i
.op
[0].regs
)
5280 != register_number (i
.index_reg
)
5281 && register_number (i
.op
[2].regs
)
5282 != register_number (i
.index_reg
)
5283 && register_number (i
.op
[0].regs
)
5284 != register_number (i
.op
[2].regs
))
5286 if (operand_check
== check_error
)
5288 i
.error
= invalid_vector_register_set
;
5291 as_warn (_("mask, index, and destination registers should be distinct"));
5293 else if (i
.reg_operands
== 1 && i
.mask
)
5295 if (i
.types
[1].bitfield
.regsimd
5296 && (i
.types
[1].bitfield
.xmmword
5297 || i
.types
[1].bitfield
.ymmword
5298 || i
.types
[1].bitfield
.zmmword
)
5299 && (register_number (i
.op
[1].regs
)
5300 == register_number (i
.index_reg
)))
5302 if (operand_check
== check_error
)
5304 i
.error
= invalid_vector_register_set
;
5307 if (operand_check
!= check_none
)
5308 as_warn (_("index and destination registers should be distinct"));
5313 /* Check if broadcast is supported by the instruction and is applied
5314 to the memory operand. */
5317 i386_operand_type type
, overlap
;
5319 /* Check if specified broadcast is supported in this instruction,
5320 and its broadcast bytes match the memory operand. */
5321 op
= i
.broadcast
->operand
;
5322 if (!t
->opcode_modifier
.broadcast
5323 || !(i
.flags
[op
] & Operand_Mem
)
5324 || (!i
.types
[op
].bitfield
.unspecified
5325 && !match_broadcast_size (t
, op
)))
5328 i
.error
= unsupported_broadcast
;
5332 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5333 * i
.broadcast
->type
);
5334 operand_type_set (&type
, 0);
5335 switch (i
.broadcast
->bytes
)
5338 type
.bitfield
.word
= 1;
5341 type
.bitfield
.dword
= 1;
5344 type
.bitfield
.qword
= 1;
5347 type
.bitfield
.xmmword
= 1;
5350 type
.bitfield
.ymmword
= 1;
5353 type
.bitfield
.zmmword
= 1;
5359 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5360 if (operand_type_all_zero (&overlap
))
5363 if (t
->opcode_modifier
.checkregsize
)
5367 type
.bitfield
.baseindex
= 1;
5368 for (j
= 0; j
< i
.operands
; ++j
)
5371 && !operand_type_register_match(i
.types
[j
],
5372 t
->operand_types
[j
],
5374 t
->operand_types
[op
]))
5379 /* If broadcast is supported in this instruction, we need to check if
5380 operand of one-element size isn't specified without broadcast. */
5381 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5383 /* Find memory operand. */
5384 for (op
= 0; op
< i
.operands
; op
++)
5385 if (operand_type_check (i
.types
[op
], anymem
))
5387 gas_assert (op
< i
.operands
);
5388 /* Check size of the memory operand. */
5389 if (match_broadcast_size (t
, op
))
5391 i
.error
= broadcast_needed
;
5396 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5398 /* Check if requested masking is supported. */
5401 switch (t
->opcode_modifier
.masking
)
5405 case MERGING_MASKING
:
5406 if (i
.mask
->zeroing
)
5409 i
.error
= unsupported_masking
;
5413 case DYNAMIC_MASKING
:
5414 /* Memory destinations allow only merging masking. */
5415 if (i
.mask
->zeroing
&& i
.mem_operands
)
5417 /* Find memory operand. */
5418 for (op
= 0; op
< i
.operands
; op
++)
5419 if (i
.flags
[op
] & Operand_Mem
)
5421 gas_assert (op
< i
.operands
);
5422 if (op
== i
.operands
- 1)
5424 i
.error
= unsupported_masking
;
5434 /* Check if masking is applied to dest operand. */
5435 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5437 i
.error
= mask_not_on_destination
;
5444 if ((i
.rounding
->type
!= saeonly
5445 && !t
->opcode_modifier
.staticrounding
)
5446 || (i
.rounding
->type
== saeonly
5447 && (t
->opcode_modifier
.staticrounding
5448 || !t
->opcode_modifier
.sae
)))
5450 i
.error
= unsupported_rc_sae
;
5453 /* If the instruction has several immediate operands and one of
5454 them is rounding, the rounding operand should be the last
5455 immediate operand. */
5456 if (i
.imm_operands
> 1
5457 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5459 i
.error
= rc_sae_operand_not_last_imm
;
5464 /* Check vector Disp8 operand. */
5465 if (t
->opcode_modifier
.disp8memshift
5466 && i
.disp_encoding
!= disp_encoding_32bit
)
5469 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5470 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5471 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5474 const i386_operand_type
*type
= NULL
;
5477 for (op
= 0; op
< i
.operands
; op
++)
5478 if (operand_type_check (i
.types
[op
], anymem
))
5480 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5481 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5482 else if (t
->operand_types
[op
].bitfield
.xmmword
5483 + t
->operand_types
[op
].bitfield
.ymmword
5484 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5485 type
= &t
->operand_types
[op
];
5486 else if (!i
.types
[op
].bitfield
.unspecified
)
5487 type
= &i
.types
[op
];
5489 else if (i
.types
[op
].bitfield
.regsimd
5490 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5492 if (i
.types
[op
].bitfield
.zmmword
)
5494 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5496 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5502 if (type
->bitfield
.zmmword
)
5504 else if (type
->bitfield
.ymmword
)
5506 else if (type
->bitfield
.xmmword
)
5510 /* For the check in fits_in_disp8(). */
5511 if (i
.memshift
== 0)
5515 for (op
= 0; op
< i
.operands
; op
++)
5516 if (operand_type_check (i
.types
[op
], disp
)
5517 && i
.op
[op
].disps
->X_op
== O_constant
)
5519 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5521 i
.types
[op
].bitfield
.disp8
= 1;
5524 i
.types
[op
].bitfield
.disp8
= 0;
5533 /* Check if operands are valid for the instruction. Update VEX
5537 VEX_check_operands (const insn_template
*t
)
5539 if (i
.vec_encoding
== vex_encoding_evex
)
5541 /* This instruction must be encoded with EVEX prefix. */
5542 if (!is_evex_encoding (t
))
5544 i
.error
= unsupported
;
5550 if (!t
->opcode_modifier
.vex
)
5552 /* This instruction template doesn't have VEX prefix. */
5553 if (i
.vec_encoding
!= vex_encoding_default
)
5555 i
.error
= unsupported
;
5561 /* Only check VEX_Imm4, which must be the first operand. */
5562 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5564 if (i
.op
[0].imms
->X_op
!= O_constant
5565 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5571 /* Turn off Imm8 so that update_imm won't complain. */
5572 i
.types
[0] = vec_imm4
;
5578 static const insn_template
*
5579 match_template (char mnem_suffix
)
5581 /* Points to template once we've found it. */
5582 const insn_template
*t
;
5583 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5584 i386_operand_type overlap4
;
5585 unsigned int found_reverse_match
;
5586 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5587 i386_operand_type operand_types
[MAX_OPERANDS
];
5588 int addr_prefix_disp
;
5590 unsigned int found_cpu_match
, size_match
;
5591 unsigned int check_register
;
5592 enum i386_error specific_error
= 0;
5594 #if MAX_OPERANDS != 5
5595 # error "MAX_OPERANDS must be 5."
5598 found_reverse_match
= 0;
5599 addr_prefix_disp
= -1;
5601 memset (&suffix_check
, 0, sizeof (suffix_check
));
5602 if (intel_syntax
&& i
.broadcast
)
5604 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5605 suffix_check
.no_bsuf
= 1;
5606 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5607 suffix_check
.no_wsuf
= 1;
5608 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5609 suffix_check
.no_ssuf
= 1;
5610 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5611 suffix_check
.no_lsuf
= 1;
5612 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5613 suffix_check
.no_qsuf
= 1;
5614 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5615 suffix_check
.no_ldsuf
= 1;
5617 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5620 switch (mnem_suffix
)
5622 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5623 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5624 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5625 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5626 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5630 /* Must have right number of operands. */
5631 i
.error
= number_of_operands_mismatch
;
5633 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5635 addr_prefix_disp
= -1;
5636 found_reverse_match
= 0;
5638 if (i
.operands
!= t
->operands
)
5641 /* Check processor support. */
5642 i
.error
= unsupported
;
5643 found_cpu_match
= (cpu_flags_match (t
)
5644 == CPU_FLAGS_PERFECT_MATCH
);
5645 if (!found_cpu_match
)
5648 /* Check AT&T mnemonic. */
5649 i
.error
= unsupported_with_intel_mnemonic
;
5650 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5653 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5654 i
.error
= unsupported_syntax
;
5655 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5656 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5657 || (intel64
&& t
->opcode_modifier
.amd64
)
5658 || (!intel64
&& t
->opcode_modifier
.intel64
))
5661 /* Check the suffix, except for some instructions in intel mode. */
5662 i
.error
= invalid_instruction_suffix
;
5663 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5664 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5665 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5666 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5667 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5668 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5669 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5671 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5672 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5673 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5674 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5675 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5676 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5677 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5680 size_match
= operand_size_match (t
);
5684 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5685 operand_types
[j
] = t
->operand_types
[j
];
5687 /* In general, don't allow 64-bit operands in 32-bit mode. */
5688 if (i
.suffix
== QWORD_MNEM_SUFFIX
5689 && flag_code
!= CODE_64BIT
5691 ? (!t
->opcode_modifier
.ignoresize
5692 && !t
->opcode_modifier
.broadcast
5693 && !intel_float_operand (t
->name
))
5694 : intel_float_operand (t
->name
) != 2)
5695 && ((!operand_types
[0].bitfield
.regmmx
5696 && !operand_types
[0].bitfield
.regsimd
)
5697 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5698 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5699 && (t
->base_opcode
!= 0x0fc7
5700 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5703 /* In general, don't allow 32-bit operands on pre-386. */
5704 else if (i
.suffix
== LONG_MNEM_SUFFIX
5705 && !cpu_arch_flags
.bitfield
.cpui386
5707 ? (!t
->opcode_modifier
.ignoresize
5708 && !intel_float_operand (t
->name
))
5709 : intel_float_operand (t
->name
) != 2)
5710 && ((!operand_types
[0].bitfield
.regmmx
5711 && !operand_types
[0].bitfield
.regsimd
)
5712 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5713 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5716 /* Do not verify operands when there are none. */
5720 /* We've found a match; break out of loop. */
5724 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5725 into Disp32/Disp16/Disp32 operand. */
5726 if (i
.prefix
[ADDR_PREFIX
] != 0)
5728 /* There should be only one Disp operand. */
5732 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5734 if (operand_types
[j
].bitfield
.disp16
)
5736 addr_prefix_disp
= j
;
5737 operand_types
[j
].bitfield
.disp32
= 1;
5738 operand_types
[j
].bitfield
.disp16
= 0;
5744 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5746 if (operand_types
[j
].bitfield
.disp32
)
5748 addr_prefix_disp
= j
;
5749 operand_types
[j
].bitfield
.disp32
= 0;
5750 operand_types
[j
].bitfield
.disp16
= 1;
5756 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5758 if (operand_types
[j
].bitfield
.disp64
)
5760 addr_prefix_disp
= j
;
5761 operand_types
[j
].bitfield
.disp64
= 0;
5762 operand_types
[j
].bitfield
.disp32
= 1;
5770 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5771 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5774 /* We check register size if needed. */
5775 if (t
->opcode_modifier
.checkregsize
)
5777 check_register
= (1 << t
->operands
) - 1;
5779 check_register
&= ~(1 << i
.broadcast
->operand
);
5784 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5785 switch (t
->operands
)
5788 if (!operand_type_match (overlap0
, i
.types
[0]))
5792 /* xchg %eax, %eax is a special case. It is an alias for nop
5793 only in 32bit mode and we can use opcode 0x90. In 64bit
5794 mode, we can't use 0x90 for xchg %eax, %eax since it should
5795 zero-extend %eax to %rax. */
5796 if (flag_code
== CODE_64BIT
5797 && t
->base_opcode
== 0x90
5798 && operand_type_equal (&i
.types
[0], &acc32
)
5799 && operand_type_equal (&i
.types
[1], &acc32
))
5801 /* xrelease mov %eax, <disp> is another special case. It must not
5802 match the accumulator-only encoding of mov. */
5803 if (flag_code
!= CODE_64BIT
5805 && t
->base_opcode
== 0xa0
5806 && i
.types
[0].bitfield
.acc
5807 && operand_type_check (i
.types
[1], anymem
))
5812 if (!(size_match
& MATCH_STRAIGHT
))
5814 /* Reverse direction of operands if swapping is possible in the first
5815 place (operands need to be symmetric) and
5816 - the load form is requested, and the template is a store form,
5817 - the store form is requested, and the template is a load form,
5818 - the non-default (swapped) form is requested. */
5819 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5820 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5821 && !operand_type_all_zero (&overlap1
))
5822 switch (i
.dir_encoding
)
5824 case dir_encoding_load
:
5825 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5826 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5830 case dir_encoding_store
:
5831 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5832 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5836 case dir_encoding_swap
:
5839 case dir_encoding_default
:
5842 /* If we want store form, we skip the current load. */
5843 if ((i
.dir_encoding
== dir_encoding_store
5844 || i
.dir_encoding
== dir_encoding_swap
)
5845 && i
.mem_operands
== 0
5846 && t
->opcode_modifier
.load
)
5851 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5852 if (!operand_type_match (overlap0
, i
.types
[0])
5853 || !operand_type_match (overlap1
, i
.types
[1])
5854 || ((check_register
& 3) == 3
5855 && !operand_type_register_match (i
.types
[0],
5860 /* Check if other direction is valid ... */
5861 if (!t
->opcode_modifier
.d
)
5865 if (!(size_match
& MATCH_REVERSE
))
5867 /* Try reversing direction of operands. */
5868 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5869 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5870 if (!operand_type_match (overlap0
, i
.types
[0])
5871 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5873 && !operand_type_register_match (i
.types
[0],
5874 operand_types
[i
.operands
- 1],
5875 i
.types
[i
.operands
- 1],
5878 /* Does not match either direction. */
5881 /* found_reverse_match holds which of D or FloatR
5883 if (!t
->opcode_modifier
.d
)
5884 found_reverse_match
= 0;
5885 else if (operand_types
[0].bitfield
.tbyte
)
5886 found_reverse_match
= Opcode_FloatD
;
5887 else if (operand_types
[0].bitfield
.xmmword
5888 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5889 || operand_types
[0].bitfield
.regmmx
5890 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5891 || is_any_vex_encoding(t
))
5892 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5893 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5895 found_reverse_match
= Opcode_D
;
5896 if (t
->opcode_modifier
.floatr
)
5897 found_reverse_match
|= Opcode_FloatR
;
5901 /* Found a forward 2 operand match here. */
5902 switch (t
->operands
)
5905 overlap4
= operand_type_and (i
.types
[4],
5909 overlap3
= operand_type_and (i
.types
[3],
5913 overlap2
= operand_type_and (i
.types
[2],
5918 switch (t
->operands
)
5921 if (!operand_type_match (overlap4
, i
.types
[4])
5922 || !operand_type_register_match (i
.types
[3],
5929 if (!operand_type_match (overlap3
, i
.types
[3])
5930 || ((check_register
& 0xa) == 0xa
5931 && !operand_type_register_match (i
.types
[1],
5935 || ((check_register
& 0xc) == 0xc
5936 && !operand_type_register_match (i
.types
[2],
5943 /* Here we make use of the fact that there are no
5944 reverse match 3 operand instructions. */
5945 if (!operand_type_match (overlap2
, i
.types
[2])
5946 || ((check_register
& 5) == 5
5947 && !operand_type_register_match (i
.types
[0],
5951 || ((check_register
& 6) == 6
5952 && !operand_type_register_match (i
.types
[1],
5960 /* Found either forward/reverse 2, 3 or 4 operand match here:
5961 slip through to break. */
5963 if (!found_cpu_match
)
5966 /* Check if vector and VEX operands are valid. */
5967 if (check_VecOperands (t
) || VEX_check_operands (t
))
5969 specific_error
= i
.error
;
5973 /* We've found a match; break out of loop. */
5977 if (t
== current_templates
->end
)
5979 /* We found no match. */
5980 const char *err_msg
;
5981 switch (specific_error
? specific_error
: i
.error
)
5985 case operand_size_mismatch
:
5986 err_msg
= _("operand size mismatch");
5988 case operand_type_mismatch
:
5989 err_msg
= _("operand type mismatch");
5991 case register_type_mismatch
:
5992 err_msg
= _("register type mismatch");
5994 case number_of_operands_mismatch
:
5995 err_msg
= _("number of operands mismatch");
5997 case invalid_instruction_suffix
:
5998 err_msg
= _("invalid instruction suffix");
6001 err_msg
= _("constant doesn't fit in 4 bits");
6003 case unsupported_with_intel_mnemonic
:
6004 err_msg
= _("unsupported with Intel mnemonic");
6006 case unsupported_syntax
:
6007 err_msg
= _("unsupported syntax");
6010 as_bad (_("unsupported instruction `%s'"),
6011 current_templates
->start
->name
);
6013 case invalid_vsib_address
:
6014 err_msg
= _("invalid VSIB address");
6016 case invalid_vector_register_set
:
6017 err_msg
= _("mask, index, and destination registers must be distinct");
6019 case unsupported_vector_index_register
:
6020 err_msg
= _("unsupported vector index register");
6022 case unsupported_broadcast
:
6023 err_msg
= _("unsupported broadcast");
6025 case broadcast_needed
:
6026 err_msg
= _("broadcast is needed for operand of such type");
6028 case unsupported_masking
:
6029 err_msg
= _("unsupported masking");
6031 case mask_not_on_destination
:
6032 err_msg
= _("mask not on destination operand");
6034 case no_default_mask
:
6035 err_msg
= _("default mask isn't allowed");
6037 case unsupported_rc_sae
:
6038 err_msg
= _("unsupported static rounding/sae");
6040 case rc_sae_operand_not_last_imm
:
6042 err_msg
= _("RC/SAE operand must precede immediate operands");
6044 err_msg
= _("RC/SAE operand must follow immediate operands");
6046 case invalid_register_operand
:
6047 err_msg
= _("invalid register operand");
6050 as_bad (_("%s for `%s'"), err_msg
,
6051 current_templates
->start
->name
);
6055 if (!quiet_warnings
)
6058 && (i
.types
[0].bitfield
.jumpabsolute
6059 != operand_types
[0].bitfield
.jumpabsolute
))
6061 as_warn (_("indirect %s without `*'"), t
->name
);
6064 if (t
->opcode_modifier
.isprefix
6065 && t
->opcode_modifier
.ignoresize
)
6067 /* Warn them that a data or address size prefix doesn't
6068 affect assembly of the next line of code. */
6069 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6073 /* Copy the template we found. */
6076 if (addr_prefix_disp
!= -1)
6077 i
.tm
.operand_types
[addr_prefix_disp
]
6078 = operand_types
[addr_prefix_disp
];
6080 if (found_reverse_match
)
6082 /* If we found a reverse match we must alter the opcode
6083 direction bit. found_reverse_match holds bits to change
6084 (different for int & float insns). */
6086 i
.tm
.base_opcode
^= found_reverse_match
;
6088 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6089 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6098 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6099 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6101 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6103 as_bad (_("`%s' operand %d must use `%ses' segment"),
6109 /* There's only ever one segment override allowed per instruction.
6110 This instruction possibly has a legal segment override on the
6111 second operand, so copy the segment to where non-string
6112 instructions store it, allowing common code. */
6113 i
.seg
[0] = i
.seg
[1];
6115 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6117 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6119 as_bad (_("`%s' operand %d must use `%ses' segment"),
6130 process_suffix (void)
6132 /* If matched instruction specifies an explicit instruction mnemonic
6134 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6135 i
.suffix
= WORD_MNEM_SUFFIX
;
6136 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6137 i
.suffix
= LONG_MNEM_SUFFIX
;
6138 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6139 i
.suffix
= QWORD_MNEM_SUFFIX
;
6140 else if (i
.reg_operands
)
6142 /* If there's no instruction mnemonic suffix we try to invent one
6143 based on register operands. */
6146 /* We take i.suffix from the last register operand specified,
6147 Destination register type is more significant than source
6148 register type. crc32 in SSE4.2 prefers source register
6150 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6152 if (i
.types
[0].bitfield
.byte
)
6153 i
.suffix
= BYTE_MNEM_SUFFIX
;
6154 else if (i
.types
[0].bitfield
.word
)
6155 i
.suffix
= WORD_MNEM_SUFFIX
;
6156 else if (i
.types
[0].bitfield
.dword
)
6157 i
.suffix
= LONG_MNEM_SUFFIX
;
6158 else if (i
.types
[0].bitfield
.qword
)
6159 i
.suffix
= QWORD_MNEM_SUFFIX
;
6166 if (i
.tm
.base_opcode
== 0xf20f38f0)
6168 /* We have to know the operand size for crc32. */
6169 as_bad (_("ambiguous memory operand size for `%s`"),
6174 for (op
= i
.operands
; --op
>= 0;)
6175 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6176 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6178 if (!i
.types
[op
].bitfield
.reg
)
6180 if (i
.types
[op
].bitfield
.byte
)
6181 i
.suffix
= BYTE_MNEM_SUFFIX
;
6182 else if (i
.types
[op
].bitfield
.word
)
6183 i
.suffix
= WORD_MNEM_SUFFIX
;
6184 else if (i
.types
[op
].bitfield
.dword
)
6185 i
.suffix
= LONG_MNEM_SUFFIX
;
6186 else if (i
.types
[op
].bitfield
.qword
)
6187 i
.suffix
= QWORD_MNEM_SUFFIX
;
6194 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6197 && i
.tm
.opcode_modifier
.ignoresize
6198 && i
.tm
.opcode_modifier
.no_bsuf
)
6200 else if (!check_byte_reg ())
6203 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6206 && i
.tm
.opcode_modifier
.ignoresize
6207 && i
.tm
.opcode_modifier
.no_lsuf
6208 && !i
.tm
.opcode_modifier
.todword
6209 && !i
.tm
.opcode_modifier
.toqword
)
6211 else if (!check_long_reg ())
6214 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6217 && i
.tm
.opcode_modifier
.ignoresize
6218 && i
.tm
.opcode_modifier
.no_qsuf
6219 && !i
.tm
.opcode_modifier
.todword
6220 && !i
.tm
.opcode_modifier
.toqword
)
6222 else if (!check_qword_reg ())
6225 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6228 && i
.tm
.opcode_modifier
.ignoresize
6229 && i
.tm
.opcode_modifier
.no_wsuf
)
6231 else if (!check_word_reg ())
6234 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6235 /* Do nothing if the instruction is going to ignore the prefix. */
6240 else if (i
.tm
.opcode_modifier
.defaultsize
6242 /* exclude fldenv/frstor/fsave/fstenv */
6243 && i
.tm
.opcode_modifier
.no_ssuf
)
6245 i
.suffix
= stackop_size
;
6247 else if (intel_syntax
6249 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6250 || i
.tm
.opcode_modifier
.jumpbyte
6251 || i
.tm
.opcode_modifier
.jumpintersegment
6252 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6253 && i
.tm
.extension_opcode
<= 3)))
6258 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6260 i
.suffix
= QWORD_MNEM_SUFFIX
;
6265 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6266 i
.suffix
= LONG_MNEM_SUFFIX
;
6269 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6270 i
.suffix
= WORD_MNEM_SUFFIX
;
6279 if (i
.tm
.opcode_modifier
.w
)
6281 as_bad (_("no instruction mnemonic suffix given and "
6282 "no register operands; can't size instruction"));
6288 unsigned int suffixes
;
6290 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6291 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6293 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6295 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6297 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6299 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6302 /* There are more than suffix matches. */
6303 if (i
.tm
.opcode_modifier
.w
6304 || ((suffixes
& (suffixes
- 1))
6305 && !i
.tm
.opcode_modifier
.defaultsize
6306 && !i
.tm
.opcode_modifier
.ignoresize
))
6308 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6314 /* Change the opcode based on the operand size given by i.suffix. */
6317 /* Size floating point instruction. */
6318 case LONG_MNEM_SUFFIX
:
6319 if (i
.tm
.opcode_modifier
.floatmf
)
6321 i
.tm
.base_opcode
^= 4;
6325 case WORD_MNEM_SUFFIX
:
6326 case QWORD_MNEM_SUFFIX
:
6327 /* It's not a byte, select word/dword operation. */
6328 if (i
.tm
.opcode_modifier
.w
)
6330 if (i
.tm
.opcode_modifier
.shortform
)
6331 i
.tm
.base_opcode
|= 8;
6333 i
.tm
.base_opcode
|= 1;
6336 case SHORT_MNEM_SUFFIX
:
6337 /* Now select between word & dword operations via the operand
6338 size prefix, except for instructions that will ignore this
6340 if (i
.reg_operands
> 0
6341 && i
.types
[0].bitfield
.reg
6342 && i
.tm
.opcode_modifier
.addrprefixopreg
6343 && (i
.tm
.opcode_modifier
.immext
6344 || i
.operands
== 1))
6346 /* The address size override prefix changes the size of the
6348 if ((flag_code
== CODE_32BIT
6349 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6350 || (flag_code
!= CODE_32BIT
6351 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6352 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6355 /* stackop_size is set to LONG_MNEM_SUFFIX for the .code16gcc
6356 directive to support 16bit mode with 32-bit address. Since
6357 IRET (opcode 0xcf) in 16bit mode returns from an interrupt
6358 in 16bit mode, we shouldn't add DATA_PREFIX_OPCODE here. */
6359 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6360 && (stackop_size
!= LONG_MNEM_SUFFIX
6361 || i
.tm
.base_opcode
!= 0xcf)
6362 && !i
.tm
.opcode_modifier
.ignoresize
6363 && !i
.tm
.opcode_modifier
.floatmf
6364 && !i
.tm
.opcode_modifier
.vex
6365 && !i
.tm
.opcode_modifier
.vexopcode
6366 && !is_evex_encoding (&i
.tm
)
6367 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6368 || (flag_code
== CODE_64BIT
6369 && i
.tm
.opcode_modifier
.jumpbyte
)))
6371 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6373 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6374 prefix
= ADDR_PREFIX_OPCODE
;
6376 if (!add_prefix (prefix
))
6380 /* Set mode64 for an operand. */
6381 if (i
.suffix
== QWORD_MNEM_SUFFIX
6382 && flag_code
== CODE_64BIT
6383 && !i
.tm
.opcode_modifier
.norex64
6384 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6386 && ! (i
.operands
== 2
6387 && i
.tm
.base_opcode
== 0x90
6388 && i
.tm
.extension_opcode
== None
6389 && operand_type_equal (&i
.types
[0], &acc64
)
6390 && operand_type_equal (&i
.types
[1], &acc64
)))
6396 if (i
.reg_operands
!= 0
6398 && i
.tm
.opcode_modifier
.addrprefixopreg
6399 && !i
.tm
.opcode_modifier
.immext
)
6401 /* Check invalid register operand when the address size override
6402 prefix changes the size of register operands. */
6404 enum { need_word
, need_dword
, need_qword
} need
;
6406 if (flag_code
== CODE_32BIT
)
6407 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6410 if (i
.prefix
[ADDR_PREFIX
])
6413 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6416 for (op
= 0; op
< i
.operands
; op
++)
6417 if (i
.types
[op
].bitfield
.reg
6418 && ((need
== need_word
6419 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6420 || (need
== need_dword
6421 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6422 || (need
== need_qword
6423 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6425 as_bad (_("invalid register operand size for `%s'"),
6435 check_byte_reg (void)
6439 for (op
= i
.operands
; --op
>= 0;)
6441 /* Skip non-register operands. */
6442 if (!i
.types
[op
].bitfield
.reg
)
6445 /* If this is an eight bit register, it's OK. If it's the 16 or
6446 32 bit version of an eight bit register, we will just use the
6447 low portion, and that's OK too. */
6448 if (i
.types
[op
].bitfield
.byte
)
6451 /* I/O port address operands are OK too. */
6452 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6455 /* crc32 doesn't generate this warning. */
6456 if (i
.tm
.base_opcode
== 0xf20f38f0)
6459 if ((i
.types
[op
].bitfield
.word
6460 || i
.types
[op
].bitfield
.dword
6461 || i
.types
[op
].bitfield
.qword
)
6462 && i
.op
[op
].regs
->reg_num
< 4
6463 /* Prohibit these changes in 64bit mode, since the lowering
6464 would be more complicated. */
6465 && flag_code
!= CODE_64BIT
)
6467 #if REGISTER_WARNINGS
6468 if (!quiet_warnings
)
6469 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6471 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6472 ? REGNAM_AL
- REGNAM_AX
6473 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6475 i
.op
[op
].regs
->reg_name
,
6480 /* Any other register is bad. */
6481 if (i
.types
[op
].bitfield
.reg
6482 || i
.types
[op
].bitfield
.regmmx
6483 || i
.types
[op
].bitfield
.regsimd
6484 || i
.types
[op
].bitfield
.sreg2
6485 || i
.types
[op
].bitfield
.sreg3
6486 || i
.types
[op
].bitfield
.control
6487 || i
.types
[op
].bitfield
.debug
6488 || i
.types
[op
].bitfield
.test
)
6490 as_bad (_("`%s%s' not allowed with `%s%c'"),
6492 i
.op
[op
].regs
->reg_name
,
6502 check_long_reg (void)
6506 for (op
= i
.operands
; --op
>= 0;)
6507 /* Skip non-register operands. */
6508 if (!i
.types
[op
].bitfield
.reg
)
6510 /* Reject eight bit registers, except where the template requires
6511 them. (eg. movzb) */
6512 else if (i
.types
[op
].bitfield
.byte
6513 && (i
.tm
.operand_types
[op
].bitfield
.reg
6514 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6515 && (i
.tm
.operand_types
[op
].bitfield
.word
6516 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6518 as_bad (_("`%s%s' not allowed with `%s%c'"),
6520 i
.op
[op
].regs
->reg_name
,
6525 /* Warn if the e prefix on a general reg is missing. */
6526 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6527 && i
.types
[op
].bitfield
.word
6528 && (i
.tm
.operand_types
[op
].bitfield
.reg
6529 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6530 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6532 /* Prohibit these changes in the 64bit mode, since the
6533 lowering is more complicated. */
6534 if (flag_code
== CODE_64BIT
)
6536 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6537 register_prefix
, i
.op
[op
].regs
->reg_name
,
6541 #if REGISTER_WARNINGS
6542 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6544 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6545 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6548 /* Warn if the r prefix on a general reg is present. */
6549 else if (i
.types
[op
].bitfield
.qword
6550 && (i
.tm
.operand_types
[op
].bitfield
.reg
6551 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6552 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6555 && i
.tm
.opcode_modifier
.toqword
6556 && !i
.types
[0].bitfield
.regsimd
)
6558 /* Convert to QWORD. We want REX byte. */
6559 i
.suffix
= QWORD_MNEM_SUFFIX
;
6563 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6564 register_prefix
, i
.op
[op
].regs
->reg_name
,
6573 check_qword_reg (void)
6577 for (op
= i
.operands
; --op
>= 0; )
6578 /* Skip non-register operands. */
6579 if (!i
.types
[op
].bitfield
.reg
)
6581 /* Reject eight bit registers, except where the template requires
6582 them. (eg. movzb) */
6583 else if (i
.types
[op
].bitfield
.byte
6584 && (i
.tm
.operand_types
[op
].bitfield
.reg
6585 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6586 && (i
.tm
.operand_types
[op
].bitfield
.word
6587 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6589 as_bad (_("`%s%s' not allowed with `%s%c'"),
6591 i
.op
[op
].regs
->reg_name
,
6596 /* Warn if the r prefix on a general reg is missing. */
6597 else if ((i
.types
[op
].bitfield
.word
6598 || i
.types
[op
].bitfield
.dword
)
6599 && (i
.tm
.operand_types
[op
].bitfield
.reg
6600 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6601 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6603 /* Prohibit these changes in the 64bit mode, since the
6604 lowering is more complicated. */
6606 && i
.tm
.opcode_modifier
.todword
6607 && !i
.types
[0].bitfield
.regsimd
)
6609 /* Convert to DWORD. We don't want REX byte. */
6610 i
.suffix
= LONG_MNEM_SUFFIX
;
6614 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6615 register_prefix
, i
.op
[op
].regs
->reg_name
,
6624 check_word_reg (void)
6627 for (op
= i
.operands
; --op
>= 0;)
6628 /* Skip non-register operands. */
6629 if (!i
.types
[op
].bitfield
.reg
)
6631 /* Reject eight bit registers, except where the template requires
6632 them. (eg. movzb) */
6633 else if (i
.types
[op
].bitfield
.byte
6634 && (i
.tm
.operand_types
[op
].bitfield
.reg
6635 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6636 && (i
.tm
.operand_types
[op
].bitfield
.word
6637 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6639 as_bad (_("`%s%s' not allowed with `%s%c'"),
6641 i
.op
[op
].regs
->reg_name
,
6646 /* Warn if the e or r prefix on a general reg is present. */
6647 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6648 && (i
.types
[op
].bitfield
.dword
6649 || i
.types
[op
].bitfield
.qword
)
6650 && (i
.tm
.operand_types
[op
].bitfield
.reg
6651 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6652 && i
.tm
.operand_types
[op
].bitfield
.word
)
6654 /* Prohibit these changes in the 64bit mode, since the
6655 lowering is more complicated. */
6656 if (flag_code
== CODE_64BIT
)
6658 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6659 register_prefix
, i
.op
[op
].regs
->reg_name
,
6663 #if REGISTER_WARNINGS
6664 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6666 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6667 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6674 update_imm (unsigned int j
)
6676 i386_operand_type overlap
= i
.types
[j
];
6677 if ((overlap
.bitfield
.imm8
6678 || overlap
.bitfield
.imm8s
6679 || overlap
.bitfield
.imm16
6680 || overlap
.bitfield
.imm32
6681 || overlap
.bitfield
.imm32s
6682 || overlap
.bitfield
.imm64
)
6683 && !operand_type_equal (&overlap
, &imm8
)
6684 && !operand_type_equal (&overlap
, &imm8s
)
6685 && !operand_type_equal (&overlap
, &imm16
)
6686 && !operand_type_equal (&overlap
, &imm32
)
6687 && !operand_type_equal (&overlap
, &imm32s
)
6688 && !operand_type_equal (&overlap
, &imm64
))
6692 i386_operand_type temp
;
6694 operand_type_set (&temp
, 0);
6695 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6697 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6698 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6700 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6701 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6702 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6704 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6705 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6708 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6711 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6712 || operand_type_equal (&overlap
, &imm16_32
)
6713 || operand_type_equal (&overlap
, &imm16_32s
))
6715 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6720 if (!operand_type_equal (&overlap
, &imm8
)
6721 && !operand_type_equal (&overlap
, &imm8s
)
6722 && !operand_type_equal (&overlap
, &imm16
)
6723 && !operand_type_equal (&overlap
, &imm32
)
6724 && !operand_type_equal (&overlap
, &imm32s
)
6725 && !operand_type_equal (&overlap
, &imm64
))
6727 as_bad (_("no instruction mnemonic suffix given; "
6728 "can't determine immediate size"));
6732 i
.types
[j
] = overlap
;
6742 /* Update the first 2 immediate operands. */
6743 n
= i
.operands
> 2 ? 2 : i
.operands
;
6746 for (j
= 0; j
< n
; j
++)
6747 if (update_imm (j
) == 0)
6750 /* The 3rd operand can't be immediate operand. */
6751 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6758 process_operands (void)
6760 /* Default segment register this instruction will use for memory
6761 accesses. 0 means unknown. This is only for optimizing out
6762 unnecessary segment overrides. */
6763 const seg_entry
*default_seg
= 0;
6765 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6767 unsigned int dupl
= i
.operands
;
6768 unsigned int dest
= dupl
- 1;
6771 /* The destination must be an xmm register. */
6772 gas_assert (i
.reg_operands
6773 && MAX_OPERANDS
> dupl
6774 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6776 if (i
.tm
.operand_types
[0].bitfield
.acc
6777 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6779 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6781 /* Keep xmm0 for instructions with VEX prefix and 3
6783 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6784 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6789 /* We remove the first xmm0 and keep the number of
6790 operands unchanged, which in fact duplicates the
6792 for (j
= 1; j
< i
.operands
; j
++)
6794 i
.op
[j
- 1] = i
.op
[j
];
6795 i
.types
[j
- 1] = i
.types
[j
];
6796 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6800 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6802 gas_assert ((MAX_OPERANDS
- 1) > dupl
6803 && (i
.tm
.opcode_modifier
.vexsources
6806 /* Add the implicit xmm0 for instructions with VEX prefix
6808 for (j
= i
.operands
; j
> 0; j
--)
6810 i
.op
[j
] = i
.op
[j
- 1];
6811 i
.types
[j
] = i
.types
[j
- 1];
6812 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6815 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6816 i
.types
[0] = regxmm
;
6817 i
.tm
.operand_types
[0] = regxmm
;
6820 i
.reg_operands
+= 2;
6825 i
.op
[dupl
] = i
.op
[dest
];
6826 i
.types
[dupl
] = i
.types
[dest
];
6827 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6836 i
.op
[dupl
] = i
.op
[dest
];
6837 i
.types
[dupl
] = i
.types
[dest
];
6838 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6841 if (i
.tm
.opcode_modifier
.immext
)
6844 else if (i
.tm
.operand_types
[0].bitfield
.acc
6845 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6849 for (j
= 1; j
< i
.operands
; j
++)
6851 i
.op
[j
- 1] = i
.op
[j
];
6852 i
.types
[j
- 1] = i
.types
[j
];
6854 /* We need to adjust fields in i.tm since they are used by
6855 build_modrm_byte. */
6856 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6863 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6865 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6867 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6868 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6869 regnum
= register_number (i
.op
[1].regs
);
6870 first_reg_in_group
= regnum
& ~3;
6871 last_reg_in_group
= first_reg_in_group
+ 3;
6872 if (regnum
!= first_reg_in_group
)
6873 as_warn (_("source register `%s%s' implicitly denotes"
6874 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6875 register_prefix
, i
.op
[1].regs
->reg_name
,
6876 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6877 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6880 else if (i
.tm
.opcode_modifier
.regkludge
)
6882 /* The imul $imm, %reg instruction is converted into
6883 imul $imm, %reg, %reg, and the clr %reg instruction
6884 is converted into xor %reg, %reg. */
6886 unsigned int first_reg_op
;
6888 if (operand_type_check (i
.types
[0], reg
))
6892 /* Pretend we saw the extra register operand. */
6893 gas_assert (i
.reg_operands
== 1
6894 && i
.op
[first_reg_op
+ 1].regs
== 0);
6895 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6896 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6901 if (i
.tm
.opcode_modifier
.shortform
)
6903 if (i
.types
[0].bitfield
.sreg2
6904 || i
.types
[0].bitfield
.sreg3
)
6906 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6907 && i
.op
[0].regs
->reg_num
== 1)
6909 as_bad (_("you can't `pop %scs'"), register_prefix
);
6912 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6913 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6918 /* The register or float register operand is in operand
6922 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6923 || operand_type_check (i
.types
[0], reg
))
6927 /* Register goes in low 3 bits of opcode. */
6928 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6929 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6931 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6933 /* Warn about some common errors, but press on regardless.
6934 The first case can be generated by gcc (<= 2.8.1). */
6935 if (i
.operands
== 2)
6937 /* Reversed arguments on faddp, fsubp, etc. */
6938 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6939 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6940 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6944 /* Extraneous `l' suffix on fp insn. */
6945 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6946 register_prefix
, i
.op
[0].regs
->reg_name
);
6951 else if (i
.tm
.opcode_modifier
.modrm
)
6953 /* The opcode is completed (modulo i.tm.extension_opcode which
6954 must be put into the modrm byte). Now, we make the modrm and
6955 index base bytes based on all the info we've collected. */
6957 default_seg
= build_modrm_byte ();
6959 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6963 else if (i
.tm
.opcode_modifier
.isstring
)
6965 /* For the string instructions that allow a segment override
6966 on one of their operands, the default segment is ds. */
6970 if (i
.tm
.base_opcode
== 0x8d /* lea */
6973 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6975 /* If a segment was explicitly specified, and the specified segment
6976 is not the default, use an opcode prefix to select it. If we
6977 never figured out what the default segment is, then default_seg
6978 will be zero at this point, and the specified segment prefix will
6980 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6982 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6988 static const seg_entry
*
6989 build_modrm_byte (void)
6991 const seg_entry
*default_seg
= 0;
6992 unsigned int source
, dest
;
6995 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6998 unsigned int nds
, reg_slot
;
7001 dest
= i
.operands
- 1;
7004 /* There are 2 kinds of instructions:
7005 1. 5 operands: 4 register operands or 3 register operands
7006 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7007 VexW0 or VexW1. The destination must be either XMM, YMM or
7009 2. 4 operands: 4 register operands or 3 register operands
7010 plus 1 memory operand, with VexXDS. */
7011 gas_assert ((i
.reg_operands
== 4
7012 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7013 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7014 && i
.tm
.opcode_modifier
.vexw
7015 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7017 /* If VexW1 is set, the first non-immediate operand is the source and
7018 the second non-immediate one is encoded in the immediate operand. */
7019 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7021 source
= i
.imm_operands
;
7022 reg_slot
= i
.imm_operands
+ 1;
7026 source
= i
.imm_operands
+ 1;
7027 reg_slot
= i
.imm_operands
;
7030 if (i
.imm_operands
== 0)
7032 /* When there is no immediate operand, generate an 8bit
7033 immediate operand to encode the first operand. */
7034 exp
= &im_expressions
[i
.imm_operands
++];
7035 i
.op
[i
.operands
].imms
= exp
;
7036 i
.types
[i
.operands
] = imm8
;
7039 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7040 exp
->X_op
= O_constant
;
7041 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7042 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7046 unsigned int imm_slot
;
7048 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7050 if (i
.tm
.opcode_modifier
.immext
)
7052 /* When ImmExt is set, the immediate byte is the last
7054 imm_slot
= i
.operands
- 1;
7062 /* Turn on Imm8 so that output_imm will generate it. */
7063 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7066 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7067 i
.op
[imm_slot
].imms
->X_add_number
7068 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7069 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7072 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7073 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7078 /* i.reg_operands MUST be the number of real register operands;
7079 implicit registers do not count. If there are 3 register
7080 operands, it must be a instruction with VexNDS. For a
7081 instruction with VexNDD, the destination register is encoded
7082 in VEX prefix. If there are 4 register operands, it must be
7083 a instruction with VEX prefix and 3 sources. */
7084 if (i
.mem_operands
== 0
7085 && ((i
.reg_operands
== 2
7086 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7087 || (i
.reg_operands
== 3
7088 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7089 || (i
.reg_operands
== 4 && vex_3_sources
)))
7097 /* When there are 3 operands, one of them may be immediate,
7098 which may be the first or the last operand. Otherwise,
7099 the first operand must be shift count register (cl) or it
7100 is an instruction with VexNDS. */
7101 gas_assert (i
.imm_operands
== 1
7102 || (i
.imm_operands
== 0
7103 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7104 || i
.types
[0].bitfield
.shiftcount
)));
7105 if (operand_type_check (i
.types
[0], imm
)
7106 || i
.types
[0].bitfield
.shiftcount
)
7112 /* When there are 4 operands, the first two must be 8bit
7113 immediate operands. The source operand will be the 3rd
7116 For instructions with VexNDS, if the first operand
7117 an imm8, the source operand is the 2nd one. If the last
7118 operand is imm8, the source operand is the first one. */
7119 gas_assert ((i
.imm_operands
== 2
7120 && i
.types
[0].bitfield
.imm8
7121 && i
.types
[1].bitfield
.imm8
)
7122 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7123 && i
.imm_operands
== 1
7124 && (i
.types
[0].bitfield
.imm8
7125 || i
.types
[i
.operands
- 1].bitfield
.imm8
7127 if (i
.imm_operands
== 2)
7131 if (i
.types
[0].bitfield
.imm8
)
7138 if (is_evex_encoding (&i
.tm
))
7140 /* For EVEX instructions, when there are 5 operands, the
7141 first one must be immediate operand. If the second one
7142 is immediate operand, the source operand is the 3th
7143 one. If the last one is immediate operand, the source
7144 operand is the 2nd one. */
7145 gas_assert (i
.imm_operands
== 2
7146 && i
.tm
.opcode_modifier
.sae
7147 && operand_type_check (i
.types
[0], imm
));
7148 if (operand_type_check (i
.types
[1], imm
))
7150 else if (operand_type_check (i
.types
[4], imm
))
7164 /* RC/SAE operand could be between DEST and SRC. That happens
7165 when one operand is GPR and the other one is XMM/YMM/ZMM
7167 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7170 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7172 /* For instructions with VexNDS, the register-only source
7173 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7174 register. It is encoded in VEX prefix. We need to
7175 clear RegMem bit before calling operand_type_equal. */
7177 i386_operand_type op
;
7180 /* Check register-only source operand when two source
7181 operands are swapped. */
7182 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7183 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7191 op
= i
.tm
.operand_types
[vvvv
];
7192 op
.bitfield
.regmem
= 0;
7193 if ((dest
+ 1) >= i
.operands
7194 || ((!op
.bitfield
.reg
7195 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7196 && !op
.bitfield
.regsimd
7197 && !operand_type_equal (&op
, ®mask
)))
7199 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7205 /* One of the register operands will be encoded in the i.tm.reg
7206 field, the other in the combined i.tm.mode and i.tm.regmem
7207 fields. If no form of this instruction supports a memory
7208 destination operand, then we assume the source operand may
7209 sometimes be a memory operand and so we need to store the
7210 destination in the i.rm.reg field. */
7211 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7212 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7214 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7215 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7216 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7217 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7218 i
.has_regmmx
= TRUE
;
7219 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7220 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7222 if (i
.types
[dest
].bitfield
.zmmword
7223 || i
.types
[source
].bitfield
.zmmword
)
7224 i
.has_regzmm
= TRUE
;
7225 else if (i
.types
[dest
].bitfield
.ymmword
7226 || i
.types
[source
].bitfield
.ymmword
)
7227 i
.has_regymm
= TRUE
;
7229 i
.has_regxmm
= TRUE
;
7231 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7233 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7235 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7237 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7242 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7243 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7244 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7246 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7248 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7250 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7253 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7255 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7258 add_prefix (LOCK_PREFIX_OPCODE
);
7262 { /* If it's not 2 reg operands... */
7267 unsigned int fake_zero_displacement
= 0;
7270 for (op
= 0; op
< i
.operands
; op
++)
7271 if (operand_type_check (i
.types
[op
], anymem
))
7273 gas_assert (op
< i
.operands
);
7275 if (i
.tm
.opcode_modifier
.vecsib
)
7277 if (i
.index_reg
->reg_num
== RegIZ
)
7280 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7283 i
.sib
.base
= NO_BASE_REGISTER
;
7284 i
.sib
.scale
= i
.log2_scale_factor
;
7285 i
.types
[op
].bitfield
.disp8
= 0;
7286 i
.types
[op
].bitfield
.disp16
= 0;
7287 i
.types
[op
].bitfield
.disp64
= 0;
7288 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7290 /* Must be 32 bit */
7291 i
.types
[op
].bitfield
.disp32
= 1;
7292 i
.types
[op
].bitfield
.disp32s
= 0;
7296 i
.types
[op
].bitfield
.disp32
= 0;
7297 i
.types
[op
].bitfield
.disp32s
= 1;
7300 i
.sib
.index
= i
.index_reg
->reg_num
;
7301 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7303 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7309 if (i
.base_reg
== 0)
7312 if (!i
.disp_operands
)
7313 fake_zero_displacement
= 1;
7314 if (i
.index_reg
== 0)
7316 i386_operand_type newdisp
;
7318 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7319 /* Operand is just <disp> */
7320 if (flag_code
== CODE_64BIT
)
7322 /* 64bit mode overwrites the 32bit absolute
7323 addressing by RIP relative addressing and
7324 absolute addressing is encoded by one of the
7325 redundant SIB forms. */
7326 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7327 i
.sib
.base
= NO_BASE_REGISTER
;
7328 i
.sib
.index
= NO_INDEX_REGISTER
;
7329 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7331 else if ((flag_code
== CODE_16BIT
)
7332 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7334 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7339 i
.rm
.regmem
= NO_BASE_REGISTER
;
7342 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7343 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7345 else if (!i
.tm
.opcode_modifier
.vecsib
)
7347 /* !i.base_reg && i.index_reg */
7348 if (i
.index_reg
->reg_num
== RegIZ
)
7349 i
.sib
.index
= NO_INDEX_REGISTER
;
7351 i
.sib
.index
= i
.index_reg
->reg_num
;
7352 i
.sib
.base
= NO_BASE_REGISTER
;
7353 i
.sib
.scale
= i
.log2_scale_factor
;
7354 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7355 i
.types
[op
].bitfield
.disp8
= 0;
7356 i
.types
[op
].bitfield
.disp16
= 0;
7357 i
.types
[op
].bitfield
.disp64
= 0;
7358 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7360 /* Must be 32 bit */
7361 i
.types
[op
].bitfield
.disp32
= 1;
7362 i
.types
[op
].bitfield
.disp32s
= 0;
7366 i
.types
[op
].bitfield
.disp32
= 0;
7367 i
.types
[op
].bitfield
.disp32s
= 1;
7369 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7373 /* RIP addressing for 64bit mode. */
7374 else if (i
.base_reg
->reg_num
== RegIP
)
7376 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7377 i
.rm
.regmem
= NO_BASE_REGISTER
;
7378 i
.types
[op
].bitfield
.disp8
= 0;
7379 i
.types
[op
].bitfield
.disp16
= 0;
7380 i
.types
[op
].bitfield
.disp32
= 0;
7381 i
.types
[op
].bitfield
.disp32s
= 1;
7382 i
.types
[op
].bitfield
.disp64
= 0;
7383 i
.flags
[op
] |= Operand_PCrel
;
7384 if (! i
.disp_operands
)
7385 fake_zero_displacement
= 1;
7387 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7389 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7390 switch (i
.base_reg
->reg_num
)
7393 if (i
.index_reg
== 0)
7395 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7396 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7400 if (i
.index_reg
== 0)
7403 if (operand_type_check (i
.types
[op
], disp
) == 0)
7405 /* fake (%bp) into 0(%bp) */
7406 i
.types
[op
].bitfield
.disp8
= 1;
7407 fake_zero_displacement
= 1;
7410 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7411 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7413 default: /* (%si) -> 4 or (%di) -> 5 */
7414 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7416 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7418 else /* i.base_reg and 32/64 bit mode */
7420 if (flag_code
== CODE_64BIT
7421 && operand_type_check (i
.types
[op
], disp
))
7423 i
.types
[op
].bitfield
.disp16
= 0;
7424 i
.types
[op
].bitfield
.disp64
= 0;
7425 if (i
.prefix
[ADDR_PREFIX
] == 0)
7427 i
.types
[op
].bitfield
.disp32
= 0;
7428 i
.types
[op
].bitfield
.disp32s
= 1;
7432 i
.types
[op
].bitfield
.disp32
= 1;
7433 i
.types
[op
].bitfield
.disp32s
= 0;
7437 if (!i
.tm
.opcode_modifier
.vecsib
)
7438 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7439 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7441 i
.sib
.base
= i
.base_reg
->reg_num
;
7442 /* x86-64 ignores REX prefix bit here to avoid decoder
7444 if (!(i
.base_reg
->reg_flags
& RegRex
)
7445 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7446 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7448 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7450 fake_zero_displacement
= 1;
7451 i
.types
[op
].bitfield
.disp8
= 1;
7453 i
.sib
.scale
= i
.log2_scale_factor
;
7454 if (i
.index_reg
== 0)
7456 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7457 /* <disp>(%esp) becomes two byte modrm with no index
7458 register. We've already stored the code for esp
7459 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7460 Any base register besides %esp will not use the
7461 extra modrm byte. */
7462 i
.sib
.index
= NO_INDEX_REGISTER
;
7464 else if (!i
.tm
.opcode_modifier
.vecsib
)
7466 if (i
.index_reg
->reg_num
== RegIZ
)
7467 i
.sib
.index
= NO_INDEX_REGISTER
;
7469 i
.sib
.index
= i
.index_reg
->reg_num
;
7470 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7471 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7476 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7477 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7481 if (!fake_zero_displacement
7485 fake_zero_displacement
= 1;
7486 if (i
.disp_encoding
== disp_encoding_8bit
)
7487 i
.types
[op
].bitfield
.disp8
= 1;
7489 i
.types
[op
].bitfield
.disp32
= 1;
7491 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7495 if (fake_zero_displacement
)
7497 /* Fakes a zero displacement assuming that i.types[op]
7498 holds the correct displacement size. */
7501 gas_assert (i
.op
[op
].disps
== 0);
7502 exp
= &disp_expressions
[i
.disp_operands
++];
7503 i
.op
[op
].disps
= exp
;
7504 exp
->X_op
= O_constant
;
7505 exp
->X_add_number
= 0;
7506 exp
->X_add_symbol
= (symbolS
*) 0;
7507 exp
->X_op_symbol
= (symbolS
*) 0;
7515 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7517 if (operand_type_check (i
.types
[0], imm
))
7518 i
.vex
.register_specifier
= NULL
;
7521 /* VEX.vvvv encodes one of the sources when the first
7522 operand is not an immediate. */
7523 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7524 i
.vex
.register_specifier
= i
.op
[0].regs
;
7526 i
.vex
.register_specifier
= i
.op
[1].regs
;
7529 /* Destination is a XMM register encoded in the ModRM.reg
7531 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7532 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7535 /* ModRM.rm and VEX.B encodes the other source. */
7536 if (!i
.mem_operands
)
7540 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7541 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7543 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7545 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7549 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7551 i
.vex
.register_specifier
= i
.op
[2].regs
;
7552 if (!i
.mem_operands
)
7555 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7556 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7560 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7561 (if any) based on i.tm.extension_opcode. Again, we must be
7562 careful to make sure that segment/control/debug/test/MMX
7563 registers are coded into the i.rm.reg field. */
7564 else if (i
.reg_operands
)
7567 unsigned int vex_reg
= ~0;
7569 for (op
= 0; op
< i
.operands
; op
++)
7571 if (i
.types
[op
].bitfield
.reg
7572 || i
.types
[op
].bitfield
.regbnd
7573 || i
.types
[op
].bitfield
.regmask
7574 || i
.types
[op
].bitfield
.sreg2
7575 || i
.types
[op
].bitfield
.sreg3
7576 || i
.types
[op
].bitfield
.control
7577 || i
.types
[op
].bitfield
.debug
7578 || i
.types
[op
].bitfield
.test
)
7580 if (i
.types
[op
].bitfield
.regsimd
)
7582 if (i
.types
[op
].bitfield
.zmmword
)
7583 i
.has_regzmm
= TRUE
;
7584 else if (i
.types
[op
].bitfield
.ymmword
)
7585 i
.has_regymm
= TRUE
;
7587 i
.has_regxmm
= TRUE
;
7590 if (i
.types
[op
].bitfield
.regmmx
)
7592 i
.has_regmmx
= TRUE
;
7599 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7601 /* For instructions with VexNDS, the register-only
7602 source operand is encoded in VEX prefix. */
7603 gas_assert (mem
!= (unsigned int) ~0);
7608 gas_assert (op
< i
.operands
);
7612 /* Check register-only source operand when two source
7613 operands are swapped. */
7614 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7615 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7619 gas_assert (mem
== (vex_reg
+ 1)
7620 && op
< i
.operands
);
7625 gas_assert (vex_reg
< i
.operands
);
7629 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7631 /* For instructions with VexNDD, the register destination
7632 is encoded in VEX prefix. */
7633 if (i
.mem_operands
== 0)
7635 /* There is no memory operand. */
7636 gas_assert ((op
+ 2) == i
.operands
);
7641 /* There are only 2 non-immediate operands. */
7642 gas_assert (op
< i
.imm_operands
+ 2
7643 && i
.operands
== i
.imm_operands
+ 2);
7644 vex_reg
= i
.imm_operands
+ 1;
7648 gas_assert (op
< i
.operands
);
7650 if (vex_reg
!= (unsigned int) ~0)
7652 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7654 if ((!type
->bitfield
.reg
7655 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7656 && !type
->bitfield
.regsimd
7657 && !operand_type_equal (type
, ®mask
))
7660 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7663 /* Don't set OP operand twice. */
7666 /* If there is an extension opcode to put here, the
7667 register number must be put into the regmem field. */
7668 if (i
.tm
.extension_opcode
!= None
)
7670 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7671 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7673 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7678 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7679 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7681 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7686 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7687 must set it to 3 to indicate this is a register operand
7688 in the regmem field. */
7689 if (!i
.mem_operands
)
7693 /* Fill in i.rm.reg field with extension opcode (if any). */
7694 if (i
.tm
.extension_opcode
!= None
)
7695 i
.rm
.reg
= i
.tm
.extension_opcode
;
7701 output_branch (void)
7707 relax_substateT subtype
;
7711 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7712 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7715 if (i
.prefix
[DATA_PREFIX
] != 0)
7721 /* Pentium4 branch hints. */
7722 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7723 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7728 if (i
.prefix
[REX_PREFIX
] != 0)
7734 /* BND prefixed jump. */
7735 if (i
.prefix
[BND_PREFIX
] != 0)
7737 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7741 if (i
.prefixes
!= 0 && !intel_syntax
)
7742 as_warn (_("skipping prefixes on this instruction"));
7744 /* It's always a symbol; End frag & setup for relax.
7745 Make sure there is enough room in this frag for the largest
7746 instruction we may generate in md_convert_frag. This is 2
7747 bytes for the opcode and room for the prefix and largest
7749 frag_grow (prefix
+ 2 + 4);
7750 /* Prefix and 1 opcode byte go in fr_fix. */
7751 p
= frag_more (prefix
+ 1);
7752 if (i
.prefix
[DATA_PREFIX
] != 0)
7753 *p
++ = DATA_PREFIX_OPCODE
;
7754 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7755 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7756 *p
++ = i
.prefix
[SEG_PREFIX
];
7757 if (i
.prefix
[REX_PREFIX
] != 0)
7758 *p
++ = i
.prefix
[REX_PREFIX
];
7759 *p
= i
.tm
.base_opcode
;
7761 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7762 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7763 else if (cpu_arch_flags
.bitfield
.cpui386
)
7764 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7766 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7769 sym
= i
.op
[0].disps
->X_add_symbol
;
7770 off
= i
.op
[0].disps
->X_add_number
;
7772 if (i
.op
[0].disps
->X_op
!= O_constant
7773 && i
.op
[0].disps
->X_op
!= O_symbol
)
7775 /* Handle complex expressions. */
7776 sym
= make_expr_symbol (i
.op
[0].disps
);
7780 /* 1 possible extra opcode + 4 byte displacement go in var part.
7781 Pass reloc in fr_var. */
7782 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7786 /* Return TRUE iff PLT32 relocation should be used for branching to
7790 need_plt32_p (symbolS
*s
)
7792 /* PLT32 relocation is ELF only. */
7797 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7798 krtld support it. */
7802 /* Since there is no need to prepare for PLT branch on x86-64, we
7803 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7804 be used as a marker for 32-bit PC-relative branches. */
7808 /* Weak or undefined symbol need PLT32 relocation. */
7809 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7812 /* Non-global symbol doesn't need PLT32 relocation. */
7813 if (! S_IS_EXTERNAL (s
))
7816 /* Other global symbols need PLT32 relocation. NB: Symbol with
7817 non-default visibilities are treated as normal global symbol
7818 so that PLT32 relocation can be used as a marker for 32-bit
7819 PC-relative branches. It is useful for linker relaxation. */
7830 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7832 if (i
.tm
.opcode_modifier
.jumpbyte
)
7834 /* This is a loop or jecxz type instruction. */
7836 if (i
.prefix
[ADDR_PREFIX
] != 0)
7838 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7841 /* Pentium4 branch hints. */
7842 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7843 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7845 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7854 if (flag_code
== CODE_16BIT
)
7857 if (i
.prefix
[DATA_PREFIX
] != 0)
7859 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7869 if (i
.prefix
[REX_PREFIX
] != 0)
7871 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7875 /* BND prefixed jump. */
7876 if (i
.prefix
[BND_PREFIX
] != 0)
7878 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7882 if (i
.prefixes
!= 0 && !intel_syntax
)
7883 as_warn (_("skipping prefixes on this instruction"));
7885 p
= frag_more (i
.tm
.opcode_length
+ size
);
7886 switch (i
.tm
.opcode_length
)
7889 *p
++ = i
.tm
.base_opcode
>> 8;
7892 *p
++ = i
.tm
.base_opcode
;
7898 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7900 && jump_reloc
== NO_RELOC
7901 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7902 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7905 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7907 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7908 i
.op
[0].disps
, 1, jump_reloc
);
7910 /* All jumps handled here are signed, but don't use a signed limit
7911 check for 32 and 16 bit jumps as we want to allow wrap around at
7912 4G and 64k respectively. */
7914 fixP
->fx_signed
= 1;
7918 output_interseg_jump (void)
7926 if (flag_code
== CODE_16BIT
)
7930 if (i
.prefix
[DATA_PREFIX
] != 0)
7936 if (i
.prefix
[REX_PREFIX
] != 0)
7946 if (i
.prefixes
!= 0 && !intel_syntax
)
7947 as_warn (_("skipping prefixes on this instruction"));
7949 /* 1 opcode; 2 segment; offset */
7950 p
= frag_more (prefix
+ 1 + 2 + size
);
7952 if (i
.prefix
[DATA_PREFIX
] != 0)
7953 *p
++ = DATA_PREFIX_OPCODE
;
7955 if (i
.prefix
[REX_PREFIX
] != 0)
7956 *p
++ = i
.prefix
[REX_PREFIX
];
7958 *p
++ = i
.tm
.base_opcode
;
7959 if (i
.op
[1].imms
->X_op
== O_constant
)
7961 offsetT n
= i
.op
[1].imms
->X_add_number
;
7964 && !fits_in_unsigned_word (n
)
7965 && !fits_in_signed_word (n
))
7967 as_bad (_("16-bit jump out of range"));
7970 md_number_to_chars (p
, n
, size
);
7973 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7974 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7975 if (i
.op
[0].imms
->X_op
!= O_constant
)
7976 as_bad (_("can't handle non absolute segment in `%s'"),
7978 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7986 asection
*seg
= now_seg
;
7987 subsegT subseg
= now_subseg
;
7989 unsigned int alignment
, align_size_1
;
7990 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7991 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7992 unsigned int padding
;
7994 if (!IS_ELF
|| !x86_used_note
)
7997 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7999 /* The .note.gnu.property section layout:
8001 Field Length Contents
8004 n_descsz 4 The note descriptor size
8005 n_type 4 NT_GNU_PROPERTY_TYPE_0
8007 n_desc n_descsz The program property array
8011 /* Create the .note.gnu.property section. */
8012 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8013 bfd_set_section_flags (stdoutput
, sec
,
8020 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8031 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8032 elf_section_type (sec
) = SHT_NOTE
;
8034 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8036 isa_1_descsz_raw
= 4 + 4 + 4;
8037 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8038 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8040 feature_2_descsz_raw
= isa_1_descsz
;
8041 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8043 feature_2_descsz_raw
+= 4 + 4 + 4;
8044 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8045 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8048 descsz
= feature_2_descsz
;
8049 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8050 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8052 /* Write n_namsz. */
8053 md_number_to_chars (p
, (valueT
) 4, 4);
8055 /* Write n_descsz. */
8056 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8059 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8062 memcpy (p
+ 4 * 3, "GNU", 4);
8064 /* Write 4-byte type. */
8065 md_number_to_chars (p
+ 4 * 4,
8066 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8068 /* Write 4-byte data size. */
8069 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8071 /* Write 4-byte data. */
8072 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8074 /* Zero out paddings. */
8075 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8077 memset (p
+ 4 * 7, 0, padding
);
8079 /* Write 4-byte type. */
8080 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8081 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8083 /* Write 4-byte data size. */
8084 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8086 /* Write 4-byte data. */
8087 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8088 (valueT
) x86_feature_2_used
, 4);
8090 /* Zero out paddings. */
8091 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8093 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8095 /* We probably can't restore the current segment, for there likely
8098 subseg_set (seg
, subseg
);
8105 fragS
*insn_start_frag
;
8106 offsetT insn_start_off
;
8108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8109 if (IS_ELF
&& x86_used_note
)
8111 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8112 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8113 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8114 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8115 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8116 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8117 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8118 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8119 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8120 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8121 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8122 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8123 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8124 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8125 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8126 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8127 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8128 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8129 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8130 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8131 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8132 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8133 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8134 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8135 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8136 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8137 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8138 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8139 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8140 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8141 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8142 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8143 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8144 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8145 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8146 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8147 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8148 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8149 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8150 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8151 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8152 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8153 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8154 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8155 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8156 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8157 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8158 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8159 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8160 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8162 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8163 || i
.tm
.cpu_flags
.bitfield
.cpu287
8164 || i
.tm
.cpu_flags
.bitfield
.cpu387
8165 || i
.tm
.cpu_flags
.bitfield
.cpu687
8166 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8167 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8168 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8169 Xfence instructions. */
8170 if (i
.tm
.base_opcode
!= 0xf18
8171 && i
.tm
.base_opcode
!= 0xf0d
8172 && i
.tm
.base_opcode
!= 0xfae
8174 || i
.tm
.cpu_flags
.bitfield
.cpummx
8175 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8176 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8177 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8179 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8181 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8183 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8184 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8185 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8186 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8187 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8188 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8189 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8190 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8191 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8195 /* Tie dwarf2 debug info to the address at the start of the insn.
8196 We can't do this after the insn has been output as the current
8197 frag may have been closed off. eg. by frag_var. */
8198 dwarf2_emit_insn (0);
8200 insn_start_frag
= frag_now
;
8201 insn_start_off
= frag_now_fix ();
8204 if (i
.tm
.opcode_modifier
.jump
)
8206 else if (i
.tm
.opcode_modifier
.jumpbyte
8207 || i
.tm
.opcode_modifier
.jumpdword
)
8209 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8210 output_interseg_jump ();
8213 /* Output normal instructions here. */
8217 unsigned int prefix
;
8220 && i
.tm
.base_opcode
== 0xfae
8222 && i
.imm_operands
== 1
8223 && (i
.op
[0].imms
->X_add_number
== 0xe8
8224 || i
.op
[0].imms
->X_add_number
== 0xf0
8225 || i
.op
[0].imms
->X_add_number
== 0xf8))
8227 /* Encode lfence, mfence, and sfence as
8228 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8229 offsetT val
= 0x240483f0ULL
;
8231 md_number_to_chars (p
, val
, 5);
8235 /* Some processors fail on LOCK prefix. This options makes
8236 assembler ignore LOCK prefix and serves as a workaround. */
8237 if (omit_lock_prefix
)
8239 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8241 i
.prefix
[LOCK_PREFIX
] = 0;
8244 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8245 don't need the explicit prefix. */
8246 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8248 switch (i
.tm
.opcode_length
)
8251 if (i
.tm
.base_opcode
& 0xff000000)
8253 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8254 add_prefix (prefix
);
8258 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8260 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8261 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8262 || prefix
!= REPE_PREFIX_OPCODE
8263 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8264 add_prefix (prefix
);
8270 /* Check for pseudo prefixes. */
8271 as_bad_where (insn_start_frag
->fr_file
,
8272 insn_start_frag
->fr_line
,
8273 _("pseudo prefix without instruction"));
8279 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8280 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8281 R_X86_64_GOTTPOFF relocation so that linker can safely
8282 perform IE->LE optimization. */
8283 if (x86_elf_abi
== X86_64_X32_ABI
8285 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8286 && i
.prefix
[REX_PREFIX
] == 0)
8287 add_prefix (REX_OPCODE
);
8290 /* The prefix bytes. */
8291 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8293 FRAG_APPEND_1_CHAR (*q
);
8297 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8302 /* REX byte is encoded in VEX prefix. */
8306 FRAG_APPEND_1_CHAR (*q
);
8309 /* There should be no other prefixes for instructions
8314 /* For EVEX instructions i.vrex should become 0 after
8315 build_evex_prefix. For VEX instructions upper 16 registers
8316 aren't available, so VREX should be 0. */
8319 /* Now the VEX prefix. */
8320 p
= frag_more (i
.vex
.length
);
8321 for (j
= 0; j
< i
.vex
.length
; j
++)
8322 p
[j
] = i
.vex
.bytes
[j
];
8325 /* Now the opcode; be careful about word order here! */
8326 if (i
.tm
.opcode_length
== 1)
8328 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8332 switch (i
.tm
.opcode_length
)
8336 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8337 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8341 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8351 /* Put out high byte first: can't use md_number_to_chars! */
8352 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8353 *p
= i
.tm
.base_opcode
& 0xff;
8356 /* Now the modrm byte and sib byte (if present). */
8357 if (i
.tm
.opcode_modifier
.modrm
)
8359 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8362 /* If i.rm.regmem == ESP (4)
8363 && i.rm.mode != (Register mode)
8365 ==> need second modrm byte. */
8366 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8368 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8369 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8371 | i
.sib
.scale
<< 6));
8374 if (i
.disp_operands
)
8375 output_disp (insn_start_frag
, insn_start_off
);
8378 output_imm (insn_start_frag
, insn_start_off
);
8384 pi ("" /*line*/, &i
);
8386 #endif /* DEBUG386 */
8389 /* Return the size of the displacement operand N. */
8392 disp_size (unsigned int n
)
8396 if (i
.types
[n
].bitfield
.disp64
)
8398 else if (i
.types
[n
].bitfield
.disp8
)
8400 else if (i
.types
[n
].bitfield
.disp16
)
8405 /* Return the size of the immediate operand N. */
8408 imm_size (unsigned int n
)
8411 if (i
.types
[n
].bitfield
.imm64
)
8413 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8415 else if (i
.types
[n
].bitfield
.imm16
)
8421 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8426 for (n
= 0; n
< i
.operands
; n
++)
8428 if (operand_type_check (i
.types
[n
], disp
))
8430 if (i
.op
[n
].disps
->X_op
== O_constant
)
8432 int size
= disp_size (n
);
8433 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8435 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8437 p
= frag_more (size
);
8438 md_number_to_chars (p
, val
, size
);
8442 enum bfd_reloc_code_real reloc_type
;
8443 int size
= disp_size (n
);
8444 int sign
= i
.types
[n
].bitfield
.disp32s
;
8445 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8448 /* We can't have 8 bit displacement here. */
8449 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8451 /* The PC relative address is computed relative
8452 to the instruction boundary, so in case immediate
8453 fields follows, we need to adjust the value. */
8454 if (pcrel
&& i
.imm_operands
)
8459 for (n1
= 0; n1
< i
.operands
; n1
++)
8460 if (operand_type_check (i
.types
[n1
], imm
))
8462 /* Only one immediate is allowed for PC
8463 relative address. */
8464 gas_assert (sz
== 0);
8466 i
.op
[n
].disps
->X_add_number
-= sz
;
8468 /* We should find the immediate. */
8469 gas_assert (sz
!= 0);
8472 p
= frag_more (size
);
8473 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8475 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8476 && (((reloc_type
== BFD_RELOC_32
8477 || reloc_type
== BFD_RELOC_X86_64_32S
8478 || (reloc_type
== BFD_RELOC_64
8480 && (i
.op
[n
].disps
->X_op
== O_symbol
8481 || (i
.op
[n
].disps
->X_op
== O_add
8482 && ((symbol_get_value_expression
8483 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8485 || reloc_type
== BFD_RELOC_32_PCREL
))
8489 if (insn_start_frag
== frag_now
)
8490 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8495 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8496 for (fr
= insn_start_frag
->fr_next
;
8497 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8499 add
+= p
- frag_now
->fr_literal
;
8504 reloc_type
= BFD_RELOC_386_GOTPC
;
8505 i
.op
[n
].imms
->X_add_number
+= add
;
8507 else if (reloc_type
== BFD_RELOC_64
)
8508 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8510 /* Don't do the adjustment for x86-64, as there
8511 the pcrel addressing is relative to the _next_
8512 insn, and that is taken care of in other code. */
8513 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8515 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8516 size
, i
.op
[n
].disps
, pcrel
,
8518 /* Check for "call/jmp *mem", "mov mem, %reg",
8519 "test %reg, mem" and "binop mem, %reg" where binop
8520 is one of adc, add, and, cmp, or, sbb, sub, xor
8521 instructions without data prefix. Always generate
8522 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8523 if (i
.prefix
[DATA_PREFIX
] == 0
8524 && (generate_relax_relocations
8527 && i
.rm
.regmem
== 5))
8529 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8530 && ((i
.operands
== 1
8531 && i
.tm
.base_opcode
== 0xff
8532 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8534 && (i
.tm
.base_opcode
== 0x8b
8535 || i
.tm
.base_opcode
== 0x85
8536 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8540 fixP
->fx_tcbit
= i
.rex
!= 0;
8542 && (i
.base_reg
->reg_num
== RegIP
))
8543 fixP
->fx_tcbit2
= 1;
8546 fixP
->fx_tcbit2
= 1;
8554 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8559 for (n
= 0; n
< i
.operands
; n
++)
8561 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8562 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8565 if (operand_type_check (i
.types
[n
], imm
))
8567 if (i
.op
[n
].imms
->X_op
== O_constant
)
8569 int size
= imm_size (n
);
8572 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8574 p
= frag_more (size
);
8575 md_number_to_chars (p
, val
, size
);
8579 /* Not absolute_section.
8580 Need a 32-bit fixup (don't support 8bit
8581 non-absolute imms). Try to support other
8583 enum bfd_reloc_code_real reloc_type
;
8584 int size
= imm_size (n
);
8587 if (i
.types
[n
].bitfield
.imm32s
8588 && (i
.suffix
== QWORD_MNEM_SUFFIX
8589 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8594 p
= frag_more (size
);
8595 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8597 /* This is tough to explain. We end up with this one if we
8598 * have operands that look like
8599 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8600 * obtain the absolute address of the GOT, and it is strongly
8601 * preferable from a performance point of view to avoid using
8602 * a runtime relocation for this. The actual sequence of
8603 * instructions often look something like:
8608 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8610 * The call and pop essentially return the absolute address
8611 * of the label .L66 and store it in %ebx. The linker itself
8612 * will ultimately change the first operand of the addl so
8613 * that %ebx points to the GOT, but to keep things simple, the
8614 * .o file must have this operand set so that it generates not
8615 * the absolute address of .L66, but the absolute address of
8616 * itself. This allows the linker itself simply treat a GOTPC
8617 * relocation as asking for a pcrel offset to the GOT to be
8618 * added in, and the addend of the relocation is stored in the
8619 * operand field for the instruction itself.
8621 * Our job here is to fix the operand so that it would add
8622 * the correct offset so that %ebx would point to itself. The
8623 * thing that is tricky is that .-.L66 will point to the
8624 * beginning of the instruction, so we need to further modify
8625 * the operand so that it will point to itself. There are
8626 * other cases where you have something like:
8628 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8630 * and here no correction would be required. Internally in
8631 * the assembler we treat operands of this form as not being
8632 * pcrel since the '.' is explicitly mentioned, and I wonder
8633 * whether it would simplify matters to do it this way. Who
8634 * knows. In earlier versions of the PIC patches, the
8635 * pcrel_adjust field was used to store the correction, but
8636 * since the expression is not pcrel, I felt it would be
8637 * confusing to do it this way. */
8639 if ((reloc_type
== BFD_RELOC_32
8640 || reloc_type
== BFD_RELOC_X86_64_32S
8641 || reloc_type
== BFD_RELOC_64
)
8643 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8644 && (i
.op
[n
].imms
->X_op
== O_symbol
8645 || (i
.op
[n
].imms
->X_op
== O_add
8646 && ((symbol_get_value_expression
8647 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8652 if (insn_start_frag
== frag_now
)
8653 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8658 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8659 for (fr
= insn_start_frag
->fr_next
;
8660 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8662 add
+= p
- frag_now
->fr_literal
;
8666 reloc_type
= BFD_RELOC_386_GOTPC
;
8668 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8670 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8671 i
.op
[n
].imms
->X_add_number
+= add
;
8673 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8674 i
.op
[n
].imms
, 0, reloc_type
);
8680 /* x86_cons_fix_new is called via the expression parsing code when a
8681 reloc is needed. We use this hook to get the correct .got reloc. */
8682 static int cons_sign
= -1;
8685 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8686 expressionS
*exp
, bfd_reloc_code_real_type r
)
8688 r
= reloc (len
, 0, cons_sign
, r
);
8691 if (exp
->X_op
== O_secrel
)
8693 exp
->X_op
= O_symbol
;
8694 r
= BFD_RELOC_32_SECREL
;
8698 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8701 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8702 purpose of the `.dc.a' internal pseudo-op. */
8705 x86_address_bytes (void)
8707 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8709 return stdoutput
->arch_info
->bits_per_address
/ 8;
8712 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8714 # define lex_got(reloc, adjust, types) NULL
8716 /* Parse operands of the form
8717 <symbol>@GOTOFF+<nnn>
8718 and similar .plt or .got references.
8720 If we find one, set up the correct relocation in RELOC and copy the
8721 input string, minus the `@GOTOFF' into a malloc'd buffer for
8722 parsing by the calling routine. Return this buffer, and if ADJUST
8723 is non-null set it to the length of the string we removed from the
8724 input line. Otherwise return NULL. */
8726 lex_got (enum bfd_reloc_code_real
*rel
,
8728 i386_operand_type
*types
)
8730 /* Some of the relocations depend on the size of what field is to
8731 be relocated. But in our callers i386_immediate and i386_displacement
8732 we don't yet know the operand size (this will be set by insn
8733 matching). Hence we record the word32 relocation here,
8734 and adjust the reloc according to the real size in reloc(). */
8735 static const struct {
8738 const enum bfd_reloc_code_real rel
[2];
8739 const i386_operand_type types64
;
8741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8742 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8744 OPERAND_TYPE_IMM32_64
},
8746 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8747 BFD_RELOC_X86_64_PLTOFF64
},
8748 OPERAND_TYPE_IMM64
},
8749 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8750 BFD_RELOC_X86_64_PLT32
},
8751 OPERAND_TYPE_IMM32_32S_DISP32
},
8752 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8753 BFD_RELOC_X86_64_GOTPLT64
},
8754 OPERAND_TYPE_IMM64_DISP64
},
8755 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8756 BFD_RELOC_X86_64_GOTOFF64
},
8757 OPERAND_TYPE_IMM64_DISP64
},
8758 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8759 BFD_RELOC_X86_64_GOTPCREL
},
8760 OPERAND_TYPE_IMM32_32S_DISP32
},
8761 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8762 BFD_RELOC_X86_64_TLSGD
},
8763 OPERAND_TYPE_IMM32_32S_DISP32
},
8764 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8765 _dummy_first_bfd_reloc_code_real
},
8766 OPERAND_TYPE_NONE
},
8767 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8768 BFD_RELOC_X86_64_TLSLD
},
8769 OPERAND_TYPE_IMM32_32S_DISP32
},
8770 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8771 BFD_RELOC_X86_64_GOTTPOFF
},
8772 OPERAND_TYPE_IMM32_32S_DISP32
},
8773 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8774 BFD_RELOC_X86_64_TPOFF32
},
8775 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8776 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8777 _dummy_first_bfd_reloc_code_real
},
8778 OPERAND_TYPE_NONE
},
8779 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8780 BFD_RELOC_X86_64_DTPOFF32
},
8781 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8782 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8783 _dummy_first_bfd_reloc_code_real
},
8784 OPERAND_TYPE_NONE
},
8785 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8786 _dummy_first_bfd_reloc_code_real
},
8787 OPERAND_TYPE_NONE
},
8788 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8789 BFD_RELOC_X86_64_GOT32
},
8790 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8791 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8792 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8793 OPERAND_TYPE_IMM32_32S_DISP32
},
8794 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8795 BFD_RELOC_X86_64_TLSDESC_CALL
},
8796 OPERAND_TYPE_IMM32_32S_DISP32
},
8801 #if defined (OBJ_MAYBE_ELF)
8806 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8807 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8810 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8812 int len
= gotrel
[j
].len
;
8813 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8815 if (gotrel
[j
].rel
[object_64bit
] != 0)
8818 char *tmpbuf
, *past_reloc
;
8820 *rel
= gotrel
[j
].rel
[object_64bit
];
8824 if (flag_code
!= CODE_64BIT
)
8826 types
->bitfield
.imm32
= 1;
8827 types
->bitfield
.disp32
= 1;
8830 *types
= gotrel
[j
].types64
;
8833 if (j
!= 0 && GOT_symbol
== NULL
)
8834 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8836 /* The length of the first part of our input line. */
8837 first
= cp
- input_line_pointer
;
8839 /* The second part goes from after the reloc token until
8840 (and including) an end_of_line char or comma. */
8841 past_reloc
= cp
+ 1 + len
;
8843 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8845 second
= cp
+ 1 - past_reloc
;
8847 /* Allocate and copy string. The trailing NUL shouldn't
8848 be necessary, but be safe. */
8849 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8850 memcpy (tmpbuf
, input_line_pointer
, first
);
8851 if (second
!= 0 && *past_reloc
!= ' ')
8852 /* Replace the relocation token with ' ', so that
8853 errors like foo@GOTOFF1 will be detected. */
8854 tmpbuf
[first
++] = ' ';
8856 /* Increment length by 1 if the relocation token is
8861 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8862 tmpbuf
[first
+ second
] = '\0';
8866 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8867 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8872 /* Might be a symbol version string. Don't as_bad here. */
8881 /* Parse operands of the form
8882 <symbol>@SECREL32+<nnn>
8884 If we find one, set up the correct relocation in RELOC and copy the
8885 input string, minus the `@SECREL32' into a malloc'd buffer for
8886 parsing by the calling routine. Return this buffer, and if ADJUST
8887 is non-null set it to the length of the string we removed from the
8888 input line. Otherwise return NULL.
8890 This function is copied from the ELF version above adjusted for PE targets. */
8893 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8894 int *adjust ATTRIBUTE_UNUSED
,
8895 i386_operand_type
*types
)
8901 const enum bfd_reloc_code_real rel
[2];
8902 const i386_operand_type types64
;
8906 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8907 BFD_RELOC_32_SECREL
},
8908 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8914 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8915 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8918 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8920 int len
= gotrel
[j
].len
;
8922 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8924 if (gotrel
[j
].rel
[object_64bit
] != 0)
8927 char *tmpbuf
, *past_reloc
;
8929 *rel
= gotrel
[j
].rel
[object_64bit
];
8935 if (flag_code
!= CODE_64BIT
)
8937 types
->bitfield
.imm32
= 1;
8938 types
->bitfield
.disp32
= 1;
8941 *types
= gotrel
[j
].types64
;
8944 /* The length of the first part of our input line. */
8945 first
= cp
- input_line_pointer
;
8947 /* The second part goes from after the reloc token until
8948 (and including) an end_of_line char or comma. */
8949 past_reloc
= cp
+ 1 + len
;
8951 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8953 second
= cp
+ 1 - past_reloc
;
8955 /* Allocate and copy string. The trailing NUL shouldn't
8956 be necessary, but be safe. */
8957 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8958 memcpy (tmpbuf
, input_line_pointer
, first
);
8959 if (second
!= 0 && *past_reloc
!= ' ')
8960 /* Replace the relocation token with ' ', so that
8961 errors like foo@SECLREL321 will be detected. */
8962 tmpbuf
[first
++] = ' ';
8963 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8964 tmpbuf
[first
+ second
] = '\0';
8968 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8969 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8974 /* Might be a symbol version string. Don't as_bad here. */
8980 bfd_reloc_code_real_type
8981 x86_cons (expressionS
*exp
, int size
)
8983 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8985 intel_syntax
= -intel_syntax
;
8988 if (size
== 4 || (object_64bit
&& size
== 8))
8990 /* Handle @GOTOFF and the like in an expression. */
8992 char *gotfree_input_line
;
8995 save
= input_line_pointer
;
8996 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8997 if (gotfree_input_line
)
8998 input_line_pointer
= gotfree_input_line
;
9002 if (gotfree_input_line
)
9004 /* expression () has merrily parsed up to the end of line,
9005 or a comma - in the wrong buffer. Transfer how far
9006 input_line_pointer has moved to the right buffer. */
9007 input_line_pointer
= (save
9008 + (input_line_pointer
- gotfree_input_line
)
9010 free (gotfree_input_line
);
9011 if (exp
->X_op
== O_constant
9012 || exp
->X_op
== O_absent
9013 || exp
->X_op
== O_illegal
9014 || exp
->X_op
== O_register
9015 || exp
->X_op
== O_big
)
9017 char c
= *input_line_pointer
;
9018 *input_line_pointer
= 0;
9019 as_bad (_("missing or invalid expression `%s'"), save
);
9020 *input_line_pointer
= c
;
9022 else if ((got_reloc
== BFD_RELOC_386_PLT32
9023 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9024 && exp
->X_op
!= O_symbol
)
9026 char c
= *input_line_pointer
;
9027 *input_line_pointer
= 0;
9028 as_bad (_("invalid PLT expression `%s'"), save
);
9029 *input_line_pointer
= c
;
9036 intel_syntax
= -intel_syntax
;
9039 i386_intel_simplify (exp
);
9045 signed_cons (int size
)
9047 if (flag_code
== CODE_64BIT
)
9055 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9062 if (exp
.X_op
== O_symbol
)
9063 exp
.X_op
= O_secrel
;
9065 emit_expr (&exp
, 4);
9067 while (*input_line_pointer
++ == ',');
9069 input_line_pointer
--;
9070 demand_empty_rest_of_line ();
9074 /* Handle Vector operations. */
9077 check_VecOperations (char *op_string
, char *op_end
)
9079 const reg_entry
*mask
;
9084 && (op_end
== NULL
|| op_string
< op_end
))
9087 if (*op_string
== '{')
9091 /* Check broadcasts. */
9092 if (strncmp (op_string
, "1to", 3) == 0)
9097 goto duplicated_vec_op
;
9100 if (*op_string
== '8')
9102 else if (*op_string
== '4')
9104 else if (*op_string
== '2')
9106 else if (*op_string
== '1'
9107 && *(op_string
+1) == '6')
9114 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9119 broadcast_op
.type
= bcst_type
;
9120 broadcast_op
.operand
= this_operand
;
9121 broadcast_op
.bytes
= 0;
9122 i
.broadcast
= &broadcast_op
;
9124 /* Check masking operation. */
9125 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9127 /* k0 can't be used for write mask. */
9128 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9130 as_bad (_("`%s%s' can't be used for write mask"),
9131 register_prefix
, mask
->reg_name
);
9137 mask_op
.mask
= mask
;
9138 mask_op
.zeroing
= 0;
9139 mask_op
.operand
= this_operand
;
9145 goto duplicated_vec_op
;
9147 i
.mask
->mask
= mask
;
9149 /* Only "{z}" is allowed here. No need to check
9150 zeroing mask explicitly. */
9151 if (i
.mask
->operand
!= this_operand
)
9153 as_bad (_("invalid write mask `%s'"), saved
);
9160 /* Check zeroing-flag for masking operation. */
9161 else if (*op_string
== 'z')
9165 mask_op
.mask
= NULL
;
9166 mask_op
.zeroing
= 1;
9167 mask_op
.operand
= this_operand
;
9172 if (i
.mask
->zeroing
)
9175 as_bad (_("duplicated `%s'"), saved
);
9179 i
.mask
->zeroing
= 1;
9181 /* Only "{%k}" is allowed here. No need to check mask
9182 register explicitly. */
9183 if (i
.mask
->operand
!= this_operand
)
9185 as_bad (_("invalid zeroing-masking `%s'"),
9194 goto unknown_vec_op
;
9196 if (*op_string
!= '}')
9198 as_bad (_("missing `}' in `%s'"), saved
);
9203 /* Strip whitespace since the addition of pseudo prefixes
9204 changed how the scrubber treats '{'. */
9205 if (is_space_char (*op_string
))
9211 /* We don't know this one. */
9212 as_bad (_("unknown vector operation: `%s'"), saved
);
9216 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9218 as_bad (_("zeroing-masking only allowed with write mask"));
9226 i386_immediate (char *imm_start
)
9228 char *save_input_line_pointer
;
9229 char *gotfree_input_line
;
9232 i386_operand_type types
;
9234 operand_type_set (&types
, ~0);
9236 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9238 as_bad (_("at most %d immediate operands are allowed"),
9239 MAX_IMMEDIATE_OPERANDS
);
9243 exp
= &im_expressions
[i
.imm_operands
++];
9244 i
.op
[this_operand
].imms
= exp
;
9246 if (is_space_char (*imm_start
))
9249 save_input_line_pointer
= input_line_pointer
;
9250 input_line_pointer
= imm_start
;
9252 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9253 if (gotfree_input_line
)
9254 input_line_pointer
= gotfree_input_line
;
9256 exp_seg
= expression (exp
);
9260 /* Handle vector operations. */
9261 if (*input_line_pointer
== '{')
9263 input_line_pointer
= check_VecOperations (input_line_pointer
,
9265 if (input_line_pointer
== NULL
)
9269 if (*input_line_pointer
)
9270 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9272 input_line_pointer
= save_input_line_pointer
;
9273 if (gotfree_input_line
)
9275 free (gotfree_input_line
);
9277 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9278 exp
->X_op
= O_illegal
;
9281 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9285 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9286 i386_operand_type types
, const char *imm_start
)
9288 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9291 as_bad (_("missing or invalid immediate expression `%s'"),
9295 else if (exp
->X_op
== O_constant
)
9297 /* Size it properly later. */
9298 i
.types
[this_operand
].bitfield
.imm64
= 1;
9299 /* If not 64bit, sign extend val. */
9300 if (flag_code
!= CODE_64BIT
9301 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9303 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9305 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9306 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9307 && exp_seg
!= absolute_section
9308 && exp_seg
!= text_section
9309 && exp_seg
!= data_section
9310 && exp_seg
!= bss_section
9311 && exp_seg
!= undefined_section
9312 && !bfd_is_com_section (exp_seg
))
9314 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9318 else if (!intel_syntax
&& exp_seg
== reg_section
)
9321 as_bad (_("illegal immediate register operand %s"), imm_start
);
9326 /* This is an address. The size of the address will be
9327 determined later, depending on destination register,
9328 suffix, or the default for the section. */
9329 i
.types
[this_operand
].bitfield
.imm8
= 1;
9330 i
.types
[this_operand
].bitfield
.imm16
= 1;
9331 i
.types
[this_operand
].bitfield
.imm32
= 1;
9332 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9333 i
.types
[this_operand
].bitfield
.imm64
= 1;
9334 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9342 i386_scale (char *scale
)
9345 char *save
= input_line_pointer
;
9347 input_line_pointer
= scale
;
9348 val
= get_absolute_expression ();
9353 i
.log2_scale_factor
= 0;
9356 i
.log2_scale_factor
= 1;
9359 i
.log2_scale_factor
= 2;
9362 i
.log2_scale_factor
= 3;
9366 char sep
= *input_line_pointer
;
9368 *input_line_pointer
= '\0';
9369 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9371 *input_line_pointer
= sep
;
9372 input_line_pointer
= save
;
9376 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9378 as_warn (_("scale factor of %d without an index register"),
9379 1 << i
.log2_scale_factor
);
9380 i
.log2_scale_factor
= 0;
9382 scale
= input_line_pointer
;
9383 input_line_pointer
= save
;
9388 i386_displacement (char *disp_start
, char *disp_end
)
9392 char *save_input_line_pointer
;
9393 char *gotfree_input_line
;
9395 i386_operand_type bigdisp
, types
= anydisp
;
9398 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9400 as_bad (_("at most %d displacement operands are allowed"),
9401 MAX_MEMORY_OPERANDS
);
9405 operand_type_set (&bigdisp
, 0);
9406 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9407 || (!current_templates
->start
->opcode_modifier
.jump
9408 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9410 bigdisp
.bitfield
.disp32
= 1;
9411 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9412 if (flag_code
== CODE_64BIT
)
9416 bigdisp
.bitfield
.disp32s
= 1;
9417 bigdisp
.bitfield
.disp64
= 1;
9420 else if ((flag_code
== CODE_16BIT
) ^ override
)
9422 bigdisp
.bitfield
.disp32
= 0;
9423 bigdisp
.bitfield
.disp16
= 1;
9428 /* For PC-relative branches, the width of the displacement
9429 is dependent upon data size, not address size. */
9430 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9431 if (flag_code
== CODE_64BIT
)
9433 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9434 bigdisp
.bitfield
.disp16
= 1;
9437 bigdisp
.bitfield
.disp32
= 1;
9438 bigdisp
.bitfield
.disp32s
= 1;
9444 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9446 : LONG_MNEM_SUFFIX
));
9447 bigdisp
.bitfield
.disp32
= 1;
9448 if ((flag_code
== CODE_16BIT
) ^ override
)
9450 bigdisp
.bitfield
.disp32
= 0;
9451 bigdisp
.bitfield
.disp16
= 1;
9455 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9458 exp
= &disp_expressions
[i
.disp_operands
];
9459 i
.op
[this_operand
].disps
= exp
;
9461 save_input_line_pointer
= input_line_pointer
;
9462 input_line_pointer
= disp_start
;
9463 END_STRING_AND_SAVE (disp_end
);
9465 #ifndef GCC_ASM_O_HACK
9466 #define GCC_ASM_O_HACK 0
9469 END_STRING_AND_SAVE (disp_end
+ 1);
9470 if (i
.types
[this_operand
].bitfield
.baseIndex
9471 && displacement_string_end
[-1] == '+')
9473 /* This hack is to avoid a warning when using the "o"
9474 constraint within gcc asm statements.
9477 #define _set_tssldt_desc(n,addr,limit,type) \
9478 __asm__ __volatile__ ( \
9480 "movw %w1,2+%0\n\t" \
9482 "movb %b1,4+%0\n\t" \
9483 "movb %4,5+%0\n\t" \
9484 "movb $0,6+%0\n\t" \
9485 "movb %h1,7+%0\n\t" \
9487 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9489 This works great except that the output assembler ends
9490 up looking a bit weird if it turns out that there is
9491 no offset. You end up producing code that looks like:
9504 So here we provide the missing zero. */
9506 *displacement_string_end
= '0';
9509 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9510 if (gotfree_input_line
)
9511 input_line_pointer
= gotfree_input_line
;
9513 exp_seg
= expression (exp
);
9516 if (*input_line_pointer
)
9517 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9519 RESTORE_END_STRING (disp_end
+ 1);
9521 input_line_pointer
= save_input_line_pointer
;
9522 if (gotfree_input_line
)
9524 free (gotfree_input_line
);
9526 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9527 exp
->X_op
= O_illegal
;
9530 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9532 RESTORE_END_STRING (disp_end
);
9538 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9539 i386_operand_type types
, const char *disp_start
)
9541 i386_operand_type bigdisp
;
9544 /* We do this to make sure that the section symbol is in
9545 the symbol table. We will ultimately change the relocation
9546 to be relative to the beginning of the section. */
9547 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9548 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9549 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9551 if (exp
->X_op
!= O_symbol
)
9554 if (S_IS_LOCAL (exp
->X_add_symbol
)
9555 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9556 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9557 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9558 exp
->X_op
= O_subtract
;
9559 exp
->X_op_symbol
= GOT_symbol
;
9560 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9561 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9562 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9563 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9565 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9568 else if (exp
->X_op
== O_absent
9569 || exp
->X_op
== O_illegal
9570 || exp
->X_op
== O_big
)
9573 as_bad (_("missing or invalid displacement expression `%s'"),
9578 else if (flag_code
== CODE_64BIT
9579 && !i
.prefix
[ADDR_PREFIX
]
9580 && exp
->X_op
== O_constant
)
9582 /* Since displacement is signed extended to 64bit, don't allow
9583 disp32 and turn off disp32s if they are out of range. */
9584 i
.types
[this_operand
].bitfield
.disp32
= 0;
9585 if (!fits_in_signed_long (exp
->X_add_number
))
9587 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9588 if (i
.types
[this_operand
].bitfield
.baseindex
)
9590 as_bad (_("0x%lx out range of signed 32bit displacement"),
9591 (long) exp
->X_add_number
);
9597 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9598 else if (exp
->X_op
!= O_constant
9599 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9600 && exp_seg
!= absolute_section
9601 && exp_seg
!= text_section
9602 && exp_seg
!= data_section
9603 && exp_seg
!= bss_section
9604 && exp_seg
!= undefined_section
9605 && !bfd_is_com_section (exp_seg
))
9607 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9612 /* Check if this is a displacement only operand. */
9613 bigdisp
= i
.types
[this_operand
];
9614 bigdisp
.bitfield
.disp8
= 0;
9615 bigdisp
.bitfield
.disp16
= 0;
9616 bigdisp
.bitfield
.disp32
= 0;
9617 bigdisp
.bitfield
.disp32s
= 0;
9618 bigdisp
.bitfield
.disp64
= 0;
9619 if (operand_type_all_zero (&bigdisp
))
9620 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9626 /* Return the active addressing mode, taking address override and
9627 registers forming the address into consideration. Update the
9628 address override prefix if necessary. */
9630 static enum flag_code
9631 i386_addressing_mode (void)
9633 enum flag_code addr_mode
;
9635 if (i
.prefix
[ADDR_PREFIX
])
9636 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9639 addr_mode
= flag_code
;
9641 #if INFER_ADDR_PREFIX
9642 if (i
.mem_operands
== 0)
9644 /* Infer address prefix from the first memory operand. */
9645 const reg_entry
*addr_reg
= i
.base_reg
;
9647 if (addr_reg
== NULL
)
9648 addr_reg
= i
.index_reg
;
9652 if (addr_reg
->reg_type
.bitfield
.dword
)
9653 addr_mode
= CODE_32BIT
;
9654 else if (flag_code
!= CODE_64BIT
9655 && addr_reg
->reg_type
.bitfield
.word
)
9656 addr_mode
= CODE_16BIT
;
9658 if (addr_mode
!= flag_code
)
9660 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9662 /* Change the size of any displacement too. At most one
9663 of Disp16 or Disp32 is set.
9664 FIXME. There doesn't seem to be any real need for
9665 separate Disp16 and Disp32 flags. The same goes for
9666 Imm16 and Imm32. Removing them would probably clean
9667 up the code quite a lot. */
9668 if (flag_code
!= CODE_64BIT
9669 && (i
.types
[this_operand
].bitfield
.disp16
9670 || i
.types
[this_operand
].bitfield
.disp32
))
9671 i
.types
[this_operand
]
9672 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9682 /* Make sure the memory operand we've been dealt is valid.
9683 Return 1 on success, 0 on a failure. */
9686 i386_index_check (const char *operand_string
)
9688 const char *kind
= "base/index";
9689 enum flag_code addr_mode
= i386_addressing_mode ();
9691 if (current_templates
->start
->opcode_modifier
.isstring
9692 && !current_templates
->start
->opcode_modifier
.immext
9693 && (current_templates
->end
[-1].opcode_modifier
.isstring
9696 /* Memory operands of string insns are special in that they only allow
9697 a single register (rDI, rSI, or rBX) as their memory address. */
9698 const reg_entry
*expected_reg
;
9699 static const char *di_si
[][2] =
9705 static const char *bx
[] = { "ebx", "bx", "rbx" };
9707 kind
= "string address";
9709 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9711 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9713 if (!type
.bitfield
.baseindex
9714 || ((!i
.mem_operands
!= !intel_syntax
)
9715 && current_templates
->end
[-1].operand_types
[1]
9716 .bitfield
.baseindex
))
9717 type
= current_templates
->end
[-1].operand_types
[1];
9718 expected_reg
= hash_find (reg_hash
,
9719 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9723 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9725 if (i
.base_reg
!= expected_reg
9727 || operand_type_check (i
.types
[this_operand
], disp
))
9729 /* The second memory operand must have the same size as
9733 && !((addr_mode
== CODE_64BIT
9734 && i
.base_reg
->reg_type
.bitfield
.qword
)
9735 || (addr_mode
== CODE_32BIT
9736 ? i
.base_reg
->reg_type
.bitfield
.dword
9737 : i
.base_reg
->reg_type
.bitfield
.word
)))
9740 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9742 intel_syntax
? '[' : '(',
9744 expected_reg
->reg_name
,
9745 intel_syntax
? ']' : ')');
9752 as_bad (_("`%s' is not a valid %s expression"),
9753 operand_string
, kind
);
9758 if (addr_mode
!= CODE_16BIT
)
9760 /* 32-bit/64-bit checks. */
9762 && ((addr_mode
== CODE_64BIT
9763 ? !i
.base_reg
->reg_type
.bitfield
.qword
9764 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9765 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9766 || i
.base_reg
->reg_num
== RegIZ
))
9768 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9769 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9770 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9771 && ((addr_mode
== CODE_64BIT
9772 ? !i
.index_reg
->reg_type
.bitfield
.qword
9773 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9774 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9777 /* bndmk, bndldx, and bndstx have special restrictions. */
9778 if (current_templates
->start
->base_opcode
== 0xf30f1b
9779 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9781 /* They cannot use RIP-relative addressing. */
9782 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9784 as_bad (_("`%s' cannot be used here"), operand_string
);
9788 /* bndldx and bndstx ignore their scale factor. */
9789 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9790 && i
.log2_scale_factor
)
9791 as_warn (_("register scaling is being ignored here"));
9796 /* 16-bit checks. */
9798 && (!i
.base_reg
->reg_type
.bitfield
.word
9799 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9801 && (!i
.index_reg
->reg_type
.bitfield
.word
9802 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9804 && i
.base_reg
->reg_num
< 6
9805 && i
.index_reg
->reg_num
>= 6
9806 && i
.log2_scale_factor
== 0))))
9813 /* Handle vector immediates. */
9816 RC_SAE_immediate (const char *imm_start
)
9818 unsigned int match_found
, j
;
9819 const char *pstr
= imm_start
;
9827 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9829 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9833 rc_op
.type
= RC_NamesTable
[j
].type
;
9834 rc_op
.operand
= this_operand
;
9835 i
.rounding
= &rc_op
;
9839 as_bad (_("duplicated `%s'"), imm_start
);
9842 pstr
+= RC_NamesTable
[j
].len
;
9852 as_bad (_("Missing '}': '%s'"), imm_start
);
9855 /* RC/SAE immediate string should contain nothing more. */;
9858 as_bad (_("Junk after '}': '%s'"), imm_start
);
9862 exp
= &im_expressions
[i
.imm_operands
++];
9863 i
.op
[this_operand
].imms
= exp
;
9865 exp
->X_op
= O_constant
;
9866 exp
->X_add_number
= 0;
9867 exp
->X_add_symbol
= (symbolS
*) 0;
9868 exp
->X_op_symbol
= (symbolS
*) 0;
9870 i
.types
[this_operand
].bitfield
.imm8
= 1;
9874 /* Only string instructions can have a second memory operand, so
9875 reduce current_templates to just those if it contains any. */
9877 maybe_adjust_templates (void)
9879 const insn_template
*t
;
9881 gas_assert (i
.mem_operands
== 1);
9883 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9884 if (t
->opcode_modifier
.isstring
)
9887 if (t
< current_templates
->end
)
9889 static templates aux_templates
;
9890 bfd_boolean recheck
;
9892 aux_templates
.start
= t
;
9893 for (; t
< current_templates
->end
; ++t
)
9894 if (!t
->opcode_modifier
.isstring
)
9896 aux_templates
.end
= t
;
9898 /* Determine whether to re-check the first memory operand. */
9899 recheck
= (aux_templates
.start
!= current_templates
->start
9900 || t
!= current_templates
->end
);
9902 current_templates
= &aux_templates
;
9907 if (i
.memop1_string
!= NULL
9908 && i386_index_check (i
.memop1_string
) == 0)
9917 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9921 i386_att_operand (char *operand_string
)
9925 char *op_string
= operand_string
;
9927 if (is_space_char (*op_string
))
9930 /* We check for an absolute prefix (differentiating,
9931 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9932 if (*op_string
== ABSOLUTE_PREFIX
)
9935 if (is_space_char (*op_string
))
9937 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9940 /* Check if operand is a register. */
9941 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9943 i386_operand_type temp
;
9945 /* Check for a segment override by searching for ':' after a
9946 segment register. */
9948 if (is_space_char (*op_string
))
9950 if (*op_string
== ':'
9951 && (r
->reg_type
.bitfield
.sreg2
9952 || r
->reg_type
.bitfield
.sreg3
))
9957 i
.seg
[i
.mem_operands
] = &es
;
9960 i
.seg
[i
.mem_operands
] = &cs
;
9963 i
.seg
[i
.mem_operands
] = &ss
;
9966 i
.seg
[i
.mem_operands
] = &ds
;
9969 i
.seg
[i
.mem_operands
] = &fs
;
9972 i
.seg
[i
.mem_operands
] = &gs
;
9976 /* Skip the ':' and whitespace. */
9978 if (is_space_char (*op_string
))
9981 if (!is_digit_char (*op_string
)
9982 && !is_identifier_char (*op_string
)
9983 && *op_string
!= '('
9984 && *op_string
!= ABSOLUTE_PREFIX
)
9986 as_bad (_("bad memory operand `%s'"), op_string
);
9989 /* Handle case of %es:*foo. */
9990 if (*op_string
== ABSOLUTE_PREFIX
)
9993 if (is_space_char (*op_string
))
9995 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9997 goto do_memory_reference
;
10000 /* Handle vector operations. */
10001 if (*op_string
== '{')
10003 op_string
= check_VecOperations (op_string
, NULL
);
10004 if (op_string
== NULL
)
10010 as_bad (_("junk `%s' after register"), op_string
);
10013 temp
= r
->reg_type
;
10014 temp
.bitfield
.baseindex
= 0;
10015 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10017 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10018 i
.op
[this_operand
].regs
= r
;
10021 else if (*op_string
== REGISTER_PREFIX
)
10023 as_bad (_("bad register name `%s'"), op_string
);
10026 else if (*op_string
== IMMEDIATE_PREFIX
)
10029 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10031 as_bad (_("immediate operand illegal with absolute jump"));
10034 if (!i386_immediate (op_string
))
10037 else if (RC_SAE_immediate (operand_string
))
10039 /* If it is a RC or SAE immediate, do nothing. */
10042 else if (is_digit_char (*op_string
)
10043 || is_identifier_char (*op_string
)
10044 || *op_string
== '"'
10045 || *op_string
== '(')
10047 /* This is a memory reference of some sort. */
10050 /* Start and end of displacement string expression (if found). */
10051 char *displacement_string_start
;
10052 char *displacement_string_end
;
10055 do_memory_reference
:
10056 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10058 if ((i
.mem_operands
== 1
10059 && !current_templates
->start
->opcode_modifier
.isstring
)
10060 || i
.mem_operands
== 2)
10062 as_bad (_("too many memory references for `%s'"),
10063 current_templates
->start
->name
);
10067 /* Check for base index form. We detect the base index form by
10068 looking for an ')' at the end of the operand, searching
10069 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10071 base_string
= op_string
+ strlen (op_string
);
10073 /* Handle vector operations. */
10074 vop_start
= strchr (op_string
, '{');
10075 if (vop_start
&& vop_start
< base_string
)
10077 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10079 base_string
= vop_start
;
10083 if (is_space_char (*base_string
))
10086 /* If we only have a displacement, set-up for it to be parsed later. */
10087 displacement_string_start
= op_string
;
10088 displacement_string_end
= base_string
+ 1;
10090 if (*base_string
== ')')
10093 unsigned int parens_balanced
= 1;
10094 /* We've already checked that the number of left & right ()'s are
10095 equal, so this loop will not be infinite. */
10099 if (*base_string
== ')')
10101 if (*base_string
== '(')
10104 while (parens_balanced
);
10106 temp_string
= base_string
;
10108 /* Skip past '(' and whitespace. */
10110 if (is_space_char (*base_string
))
10113 if (*base_string
== ','
10114 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10117 displacement_string_end
= temp_string
;
10119 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10123 base_string
= end_op
;
10124 if (is_space_char (*base_string
))
10128 /* There may be an index reg or scale factor here. */
10129 if (*base_string
== ',')
10132 if (is_space_char (*base_string
))
10135 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10138 base_string
= end_op
;
10139 if (is_space_char (*base_string
))
10141 if (*base_string
== ',')
10144 if (is_space_char (*base_string
))
10147 else if (*base_string
!= ')')
10149 as_bad (_("expecting `,' or `)' "
10150 "after index register in `%s'"),
10155 else if (*base_string
== REGISTER_PREFIX
)
10157 end_op
= strchr (base_string
, ',');
10160 as_bad (_("bad register name `%s'"), base_string
);
10164 /* Check for scale factor. */
10165 if (*base_string
!= ')')
10167 char *end_scale
= i386_scale (base_string
);
10172 base_string
= end_scale
;
10173 if (is_space_char (*base_string
))
10175 if (*base_string
!= ')')
10177 as_bad (_("expecting `)' "
10178 "after scale factor in `%s'"),
10183 else if (!i
.index_reg
)
10185 as_bad (_("expecting index register or scale factor "
10186 "after `,'; got '%c'"),
10191 else if (*base_string
!= ')')
10193 as_bad (_("expecting `,' or `)' "
10194 "after base register in `%s'"),
10199 else if (*base_string
== REGISTER_PREFIX
)
10201 end_op
= strchr (base_string
, ',');
10204 as_bad (_("bad register name `%s'"), base_string
);
10209 /* If there's an expression beginning the operand, parse it,
10210 assuming displacement_string_start and
10211 displacement_string_end are meaningful. */
10212 if (displacement_string_start
!= displacement_string_end
)
10214 if (!i386_displacement (displacement_string_start
,
10215 displacement_string_end
))
10219 /* Special case for (%dx) while doing input/output op. */
10221 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10222 && i
.index_reg
== 0
10223 && i
.log2_scale_factor
== 0
10224 && i
.seg
[i
.mem_operands
] == 0
10225 && !operand_type_check (i
.types
[this_operand
], disp
))
10227 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10231 if (i386_index_check (operand_string
) == 0)
10233 i
.flags
[this_operand
] |= Operand_Mem
;
10234 if (i
.mem_operands
== 0)
10235 i
.memop1_string
= xstrdup (operand_string
);
10240 /* It's not a memory operand; argh! */
10241 as_bad (_("invalid char %s beginning operand %d `%s'"),
10242 output_invalid (*op_string
),
10247 return 1; /* Normal return. */
10250 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10251 that an rs_machine_dependent frag may reach. */
10254 i386_frag_max_var (fragS
*frag
)
10256 /* The only relaxable frags are for jumps.
10257 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10258 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10259 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10264 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10266 /* STT_GNU_IFUNC symbol must go through PLT. */
10267 if ((symbol_get_bfdsym (fr_symbol
)->flags
10268 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10271 if (!S_IS_EXTERNAL (fr_symbol
))
10272 /* Symbol may be weak or local. */
10273 return !S_IS_WEAK (fr_symbol
);
10275 /* Global symbols with non-default visibility can't be preempted. */
10276 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10279 if (fr_var
!= NO_RELOC
)
10280 switch ((enum bfd_reloc_code_real
) fr_var
)
10282 case BFD_RELOC_386_PLT32
:
10283 case BFD_RELOC_X86_64_PLT32
:
10284 /* Symbol with PLT relocation may be preempted. */
10290 /* Global symbols with default visibility in a shared library may be
10291 preempted by another definition. */
10296 /* md_estimate_size_before_relax()
10298 Called just before relax() for rs_machine_dependent frags. The x86
10299 assembler uses these frags to handle variable size jump
10302 Any symbol that is now undefined will not become defined.
10303 Return the correct fr_subtype in the frag.
10304 Return the initial "guess for variable size of frag" to caller.
10305 The guess is actually the growth beyond the fixed part. Whatever
10306 we do to grow the fixed or variable part contributes to our
10310 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10312 /* We've already got fragP->fr_subtype right; all we have to do is
10313 check for un-relaxable symbols. On an ELF system, we can't relax
10314 an externally visible symbol, because it may be overridden by a
10316 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10317 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10319 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10322 #if defined (OBJ_COFF) && defined (TE_PE)
10323 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10324 && S_IS_WEAK (fragP
->fr_symbol
))
10328 /* Symbol is undefined in this segment, or we need to keep a
10329 reloc so that weak symbols can be overridden. */
10330 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10331 enum bfd_reloc_code_real reloc_type
;
10332 unsigned char *opcode
;
10335 if (fragP
->fr_var
!= NO_RELOC
)
10336 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10337 else if (size
== 2)
10338 reloc_type
= BFD_RELOC_16_PCREL
;
10339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10340 else if (need_plt32_p (fragP
->fr_symbol
))
10341 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10344 reloc_type
= BFD_RELOC_32_PCREL
;
10346 old_fr_fix
= fragP
->fr_fix
;
10347 opcode
= (unsigned char *) fragP
->fr_opcode
;
10349 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10352 /* Make jmp (0xeb) a (d)word displacement jump. */
10354 fragP
->fr_fix
+= size
;
10355 fix_new (fragP
, old_fr_fix
, size
,
10357 fragP
->fr_offset
, 1,
10363 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10365 /* Negate the condition, and branch past an
10366 unconditional jump. */
10369 /* Insert an unconditional jump. */
10371 /* We added two extra opcode bytes, and have a two byte
10373 fragP
->fr_fix
+= 2 + 2;
10374 fix_new (fragP
, old_fr_fix
+ 2, 2,
10376 fragP
->fr_offset
, 1,
10380 /* Fall through. */
10383 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10387 fragP
->fr_fix
+= 1;
10388 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10390 fragP
->fr_offset
, 1,
10391 BFD_RELOC_8_PCREL
);
10392 fixP
->fx_signed
= 1;
10396 /* This changes the byte-displacement jump 0x7N
10397 to the (d)word-displacement jump 0x0f,0x8N. */
10398 opcode
[1] = opcode
[0] + 0x10;
10399 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10400 /* We've added an opcode byte. */
10401 fragP
->fr_fix
+= 1 + size
;
10402 fix_new (fragP
, old_fr_fix
+ 1, size
,
10404 fragP
->fr_offset
, 1,
10409 BAD_CASE (fragP
->fr_subtype
);
10413 return fragP
->fr_fix
- old_fr_fix
;
10416 /* Guess size depending on current relax state. Initially the relax
10417 state will correspond to a short jump and we return 1, because
10418 the variable part of the frag (the branch offset) is one byte
10419 long. However, we can relax a section more than once and in that
10420 case we must either set fr_subtype back to the unrelaxed state,
10421 or return the value for the appropriate branch. */
10422 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10425 /* Called after relax() is finished.
10427 In: Address of frag.
10428 fr_type == rs_machine_dependent.
10429 fr_subtype is what the address relaxed to.
10431 Out: Any fixSs and constants are set up.
10432 Caller will turn frag into a ".space 0". */
10435 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10438 unsigned char *opcode
;
10439 unsigned char *where_to_put_displacement
= NULL
;
10440 offsetT target_address
;
10441 offsetT opcode_address
;
10442 unsigned int extension
= 0;
10443 offsetT displacement_from_opcode_start
;
10445 opcode
= (unsigned char *) fragP
->fr_opcode
;
10447 /* Address we want to reach in file space. */
10448 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10450 /* Address opcode resides at in file space. */
10451 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10453 /* Displacement from opcode start to fill into instruction. */
10454 displacement_from_opcode_start
= target_address
- opcode_address
;
10456 if ((fragP
->fr_subtype
& BIG
) == 0)
10458 /* Don't have to change opcode. */
10459 extension
= 1; /* 1 opcode + 1 displacement */
10460 where_to_put_displacement
= &opcode
[1];
10464 if (no_cond_jump_promotion
10465 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10466 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10467 _("long jump required"));
10469 switch (fragP
->fr_subtype
)
10471 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10472 extension
= 4; /* 1 opcode + 4 displacement */
10474 where_to_put_displacement
= &opcode
[1];
10477 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10478 extension
= 2; /* 1 opcode + 2 displacement */
10480 where_to_put_displacement
= &opcode
[1];
10483 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10484 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10485 extension
= 5; /* 2 opcode + 4 displacement */
10486 opcode
[1] = opcode
[0] + 0x10;
10487 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10488 where_to_put_displacement
= &opcode
[2];
10491 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10492 extension
= 3; /* 2 opcode + 2 displacement */
10493 opcode
[1] = opcode
[0] + 0x10;
10494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10495 where_to_put_displacement
= &opcode
[2];
10498 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10503 where_to_put_displacement
= &opcode
[3];
10507 BAD_CASE (fragP
->fr_subtype
);
10512 /* If size if less then four we are sure that the operand fits,
10513 but if it's 4, then it could be that the displacement is larger
10515 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10517 && ((addressT
) (displacement_from_opcode_start
- extension
10518 + ((addressT
) 1 << 31))
10519 > (((addressT
) 2 << 31) - 1)))
10521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10522 _("jump target out of range"));
10523 /* Make us emit 0. */
10524 displacement_from_opcode_start
= extension
;
10526 /* Now put displacement after opcode. */
10527 md_number_to_chars ((char *) where_to_put_displacement
,
10528 (valueT
) (displacement_from_opcode_start
- extension
),
10529 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10530 fragP
->fr_fix
+= extension
;
10533 /* Apply a fixup (fixP) to segment data, once it has been determined
10534 by our caller that we have all the info we need to fix it up.
10536 Parameter valP is the pointer to the value of the bits.
10538 On the 386, immediates, displacements, and data pointers are all in
10539 the same (little-endian) format, so we don't need to care about which
10540 we are handling. */
10543 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10545 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10546 valueT value
= *valP
;
10548 #if !defined (TE_Mach)
10549 if (fixP
->fx_pcrel
)
10551 switch (fixP
->fx_r_type
)
10557 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10560 case BFD_RELOC_X86_64_32S
:
10561 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10564 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10567 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10572 if (fixP
->fx_addsy
!= NULL
10573 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10574 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10575 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10576 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10577 && !use_rela_relocations
)
10579 /* This is a hack. There should be a better way to handle this.
10580 This covers for the fact that bfd_install_relocation will
10581 subtract the current location (for partial_inplace, PC relative
10582 relocations); see more below. */
10586 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10589 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10594 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10596 if ((sym_seg
== seg
10597 || (symbol_section_p (fixP
->fx_addsy
)
10598 && sym_seg
!= absolute_section
))
10599 && !generic_force_reloc (fixP
))
10601 /* Yes, we add the values in twice. This is because
10602 bfd_install_relocation subtracts them out again. I think
10603 bfd_install_relocation is broken, but I don't dare change
10605 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10609 #if defined (OBJ_COFF) && defined (TE_PE)
10610 /* For some reason, the PE format does not store a
10611 section address offset for a PC relative symbol. */
10612 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10613 || S_IS_WEAK (fixP
->fx_addsy
))
10614 value
+= md_pcrel_from (fixP
);
10617 #if defined (OBJ_COFF) && defined (TE_PE)
10618 if (fixP
->fx_addsy
!= NULL
10619 && S_IS_WEAK (fixP
->fx_addsy
)
10620 /* PR 16858: Do not modify weak function references. */
10621 && ! fixP
->fx_pcrel
)
10623 #if !defined (TE_PEP)
10624 /* For x86 PE weak function symbols are neither PC-relative
10625 nor do they set S_IS_FUNCTION. So the only reliable way
10626 to detect them is to check the flags of their containing
10628 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10629 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10633 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10637 /* Fix a few things - the dynamic linker expects certain values here,
10638 and we must not disappoint it. */
10639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10640 if (IS_ELF
&& fixP
->fx_addsy
)
10641 switch (fixP
->fx_r_type
)
10643 case BFD_RELOC_386_PLT32
:
10644 case BFD_RELOC_X86_64_PLT32
:
10645 /* Make the jump instruction point to the address of the operand.
10646 At runtime we merely add the offset to the actual PLT entry.
10647 NB: Subtract the offset size only for jump instructions. */
10648 if (fixP
->fx_pcrel
)
10652 case BFD_RELOC_386_TLS_GD
:
10653 case BFD_RELOC_386_TLS_LDM
:
10654 case BFD_RELOC_386_TLS_IE_32
:
10655 case BFD_RELOC_386_TLS_IE
:
10656 case BFD_RELOC_386_TLS_GOTIE
:
10657 case BFD_RELOC_386_TLS_GOTDESC
:
10658 case BFD_RELOC_X86_64_TLSGD
:
10659 case BFD_RELOC_X86_64_TLSLD
:
10660 case BFD_RELOC_X86_64_GOTTPOFF
:
10661 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10662 value
= 0; /* Fully resolved at runtime. No addend. */
10664 case BFD_RELOC_386_TLS_LE
:
10665 case BFD_RELOC_386_TLS_LDO_32
:
10666 case BFD_RELOC_386_TLS_LE_32
:
10667 case BFD_RELOC_X86_64_DTPOFF32
:
10668 case BFD_RELOC_X86_64_DTPOFF64
:
10669 case BFD_RELOC_X86_64_TPOFF32
:
10670 case BFD_RELOC_X86_64_TPOFF64
:
10671 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10674 case BFD_RELOC_386_TLS_DESC_CALL
:
10675 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10676 value
= 0; /* Fully resolved at runtime. No addend. */
10677 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10681 case BFD_RELOC_VTABLE_INHERIT
:
10682 case BFD_RELOC_VTABLE_ENTRY
:
10689 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10691 #endif /* !defined (TE_Mach) */
10693 /* Are we finished with this relocation now? */
10694 if (fixP
->fx_addsy
== NULL
)
10696 #if defined (OBJ_COFF) && defined (TE_PE)
10697 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10700 /* Remember value for tc_gen_reloc. */
10701 fixP
->fx_addnumber
= value
;
10702 /* Clear out the frag for now. */
10706 else if (use_rela_relocations
)
10708 fixP
->fx_no_overflow
= 1;
10709 /* Remember value for tc_gen_reloc. */
10710 fixP
->fx_addnumber
= value
;
10714 md_number_to_chars (p
, value
, fixP
->fx_size
);
10718 md_atof (int type
, char *litP
, int *sizeP
)
10720 /* This outputs the LITTLENUMs in REVERSE order;
10721 in accord with the bigendian 386. */
10722 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10725 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10728 output_invalid (int c
)
10731 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10734 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10735 "(0x%x)", (unsigned char) c
);
10736 return output_invalid_buf
;
10739 /* REG_STRING starts *before* REGISTER_PREFIX. */
10741 static const reg_entry
*
10742 parse_real_register (char *reg_string
, char **end_op
)
10744 char *s
= reg_string
;
10746 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10747 const reg_entry
*r
;
10749 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10750 if (*s
== REGISTER_PREFIX
)
10753 if (is_space_char (*s
))
10756 p
= reg_name_given
;
10757 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10759 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10760 return (const reg_entry
*) NULL
;
10764 /* For naked regs, make sure that we are not dealing with an identifier.
10765 This prevents confusing an identifier like `eax_var' with register
10767 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10768 return (const reg_entry
*) NULL
;
10772 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10774 /* Handle floating point regs, allowing spaces in the (i) part. */
10775 if (r
== i386_regtab
/* %st is first entry of table */)
10777 if (!cpu_arch_flags
.bitfield
.cpu8087
10778 && !cpu_arch_flags
.bitfield
.cpu287
10779 && !cpu_arch_flags
.bitfield
.cpu387
)
10780 return (const reg_entry
*) NULL
;
10782 if (is_space_char (*s
))
10787 if (is_space_char (*s
))
10789 if (*s
>= '0' && *s
<= '7')
10791 int fpr
= *s
- '0';
10793 if (is_space_char (*s
))
10798 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10803 /* We have "%st(" then garbage. */
10804 return (const reg_entry
*) NULL
;
10808 if (r
== NULL
|| allow_pseudo_reg
)
10811 if (operand_type_all_zero (&r
->reg_type
))
10812 return (const reg_entry
*) NULL
;
10814 if ((r
->reg_type
.bitfield
.dword
10815 || r
->reg_type
.bitfield
.sreg3
10816 || r
->reg_type
.bitfield
.control
10817 || r
->reg_type
.bitfield
.debug
10818 || r
->reg_type
.bitfield
.test
)
10819 && !cpu_arch_flags
.bitfield
.cpui386
)
10820 return (const reg_entry
*) NULL
;
10822 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10823 return (const reg_entry
*) NULL
;
10825 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10827 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10828 return (const reg_entry
*) NULL
;
10830 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10832 if (r
->reg_type
.bitfield
.ymmword
)
10833 return (const reg_entry
*) NULL
;
10835 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10836 return (const reg_entry
*) NULL
;
10840 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10841 return (const reg_entry
*) NULL
;
10843 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10844 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10845 return (const reg_entry
*) NULL
;
10847 /* Upper 16 vector registers are only available with VREX in 64bit
10848 mode, and require EVEX encoding. */
10849 if (r
->reg_flags
& RegVRex
)
10851 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10852 || flag_code
!= CODE_64BIT
)
10853 return (const reg_entry
*) NULL
;
10855 i
.vec_encoding
= vex_encoding_evex
;
10858 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10859 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10860 && flag_code
!= CODE_64BIT
)
10861 return (const reg_entry
*) NULL
;
10863 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10864 return (const reg_entry
*) NULL
;
10869 /* REG_STRING starts *before* REGISTER_PREFIX. */
10871 static const reg_entry
*
10872 parse_register (char *reg_string
, char **end_op
)
10874 const reg_entry
*r
;
10876 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10877 r
= parse_real_register (reg_string
, end_op
);
10882 char *save
= input_line_pointer
;
10886 input_line_pointer
= reg_string
;
10887 c
= get_symbol_name (®_string
);
10888 symbolP
= symbol_find (reg_string
);
10889 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10891 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10893 know (e
->X_op
== O_register
);
10894 know (e
->X_add_number
>= 0
10895 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10896 r
= i386_regtab
+ e
->X_add_number
;
10897 if ((r
->reg_flags
& RegVRex
))
10898 i
.vec_encoding
= vex_encoding_evex
;
10899 *end_op
= input_line_pointer
;
10901 *input_line_pointer
= c
;
10902 input_line_pointer
= save
;
10908 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10910 const reg_entry
*r
;
10911 char *end
= input_line_pointer
;
10914 r
= parse_register (name
, &input_line_pointer
);
10915 if (r
&& end
<= input_line_pointer
)
10917 *nextcharP
= *input_line_pointer
;
10918 *input_line_pointer
= 0;
10919 e
->X_op
= O_register
;
10920 e
->X_add_number
= r
- i386_regtab
;
10923 input_line_pointer
= end
;
10925 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10929 md_operand (expressionS
*e
)
10932 const reg_entry
*r
;
10934 switch (*input_line_pointer
)
10936 case REGISTER_PREFIX
:
10937 r
= parse_real_register (input_line_pointer
, &end
);
10940 e
->X_op
= O_register
;
10941 e
->X_add_number
= r
- i386_regtab
;
10942 input_line_pointer
= end
;
10947 gas_assert (intel_syntax
);
10948 end
= input_line_pointer
++;
10950 if (*input_line_pointer
== ']')
10952 ++input_line_pointer
;
10953 e
->X_op_symbol
= make_expr_symbol (e
);
10954 e
->X_add_symbol
= NULL
;
10955 e
->X_add_number
= 0;
10960 e
->X_op
= O_absent
;
10961 input_line_pointer
= end
;
10968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10969 const char *md_shortopts
= "kVQ:sqnO::";
10971 const char *md_shortopts
= "qnO::";
10974 #define OPTION_32 (OPTION_MD_BASE + 0)
10975 #define OPTION_64 (OPTION_MD_BASE + 1)
10976 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10977 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10978 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10979 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10980 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10981 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10982 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10983 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10984 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10985 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10986 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10987 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10988 #define OPTION_X32 (OPTION_MD_BASE + 14)
10989 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10990 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10991 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10992 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10993 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10994 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10995 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10996 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10997 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10998 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10999 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11000 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11002 struct option md_longopts
[] =
11004 {"32", no_argument
, NULL
, OPTION_32
},
11005 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11006 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11007 {"64", no_argument
, NULL
, OPTION_64
},
11009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11010 {"x32", no_argument
, NULL
, OPTION_X32
},
11011 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11012 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11014 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11015 {"march", required_argument
, NULL
, OPTION_MARCH
},
11016 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11017 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11018 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11019 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11020 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11021 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11022 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11023 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11024 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11025 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11026 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11027 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11028 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11029 # if defined (TE_PE) || defined (TE_PEP)
11030 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11032 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11033 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11034 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11035 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11036 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11037 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11038 {NULL
, no_argument
, NULL
, 0}
11040 size_t md_longopts_size
= sizeof (md_longopts
);
11043 md_parse_option (int c
, const char *arg
)
11046 char *arch
, *next
, *saved
;
11051 optimize_align_code
= 0;
11055 quiet_warnings
= 1;
11058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11059 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11060 should be emitted or not. FIXME: Not implemented. */
11064 /* -V: SVR4 argument to print version ID. */
11066 print_version_id ();
11069 /* -k: Ignore for FreeBSD compatibility. */
11074 /* -s: On i386 Solaris, this tells the native assembler to use
11075 .stab instead of .stab.excl. We always use .stab anyhow. */
11078 case OPTION_MSHARED
:
11082 case OPTION_X86_USED_NOTE
:
11083 if (strcasecmp (arg
, "yes") == 0)
11085 else if (strcasecmp (arg
, "no") == 0)
11088 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11093 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11094 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11097 const char **list
, **l
;
11099 list
= bfd_target_list ();
11100 for (l
= list
; *l
!= NULL
; l
++)
11101 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11102 || strcmp (*l
, "coff-x86-64") == 0
11103 || strcmp (*l
, "pe-x86-64") == 0
11104 || strcmp (*l
, "pei-x86-64") == 0
11105 || strcmp (*l
, "mach-o-x86-64") == 0)
11107 default_arch
= "x86_64";
11111 as_fatal (_("no compiled in support for x86_64"));
11117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11121 const char **list
, **l
;
11123 list
= bfd_target_list ();
11124 for (l
= list
; *l
!= NULL
; l
++)
11125 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11127 default_arch
= "x86_64:32";
11131 as_fatal (_("no compiled in support for 32bit x86_64"));
11135 as_fatal (_("32bit x86_64 is only supported for ELF"));
11140 default_arch
= "i386";
11143 case OPTION_DIVIDE
:
11144 #ifdef SVR4_COMMENT_CHARS
11149 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11151 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11155 i386_comment_chars
= n
;
11161 saved
= xstrdup (arg
);
11163 /* Allow -march=+nosse. */
11169 as_fatal (_("invalid -march= option: `%s'"), arg
);
11170 next
= strchr (arch
, '+');
11173 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11175 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11178 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11181 cpu_arch_name
= cpu_arch
[j
].name
;
11182 cpu_sub_arch_name
= NULL
;
11183 cpu_arch_flags
= cpu_arch
[j
].flags
;
11184 cpu_arch_isa
= cpu_arch
[j
].type
;
11185 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11186 if (!cpu_arch_tune_set
)
11188 cpu_arch_tune
= cpu_arch_isa
;
11189 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11193 else if (*cpu_arch
[j
].name
== '.'
11194 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11196 /* ISA extension. */
11197 i386_cpu_flags flags
;
11199 flags
= cpu_flags_or (cpu_arch_flags
,
11200 cpu_arch
[j
].flags
);
11202 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11204 if (cpu_sub_arch_name
)
11206 char *name
= cpu_sub_arch_name
;
11207 cpu_sub_arch_name
= concat (name
,
11209 (const char *) NULL
);
11213 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11214 cpu_arch_flags
= flags
;
11215 cpu_arch_isa_flags
= flags
;
11219 = cpu_flags_or (cpu_arch_isa_flags
,
11220 cpu_arch
[j
].flags
);
11225 if (j
>= ARRAY_SIZE (cpu_arch
))
11227 /* Disable an ISA extension. */
11228 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11229 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11231 i386_cpu_flags flags
;
11233 flags
= cpu_flags_and_not (cpu_arch_flags
,
11234 cpu_noarch
[j
].flags
);
11235 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11237 if (cpu_sub_arch_name
)
11239 char *name
= cpu_sub_arch_name
;
11240 cpu_sub_arch_name
= concat (arch
,
11241 (const char *) NULL
);
11245 cpu_sub_arch_name
= xstrdup (arch
);
11246 cpu_arch_flags
= flags
;
11247 cpu_arch_isa_flags
= flags
;
11252 if (j
>= ARRAY_SIZE (cpu_noarch
))
11253 j
= ARRAY_SIZE (cpu_arch
);
11256 if (j
>= ARRAY_SIZE (cpu_arch
))
11257 as_fatal (_("invalid -march= option: `%s'"), arg
);
11261 while (next
!= NULL
);
11267 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11268 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11270 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11272 cpu_arch_tune_set
= 1;
11273 cpu_arch_tune
= cpu_arch
[j
].type
;
11274 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11278 if (j
>= ARRAY_SIZE (cpu_arch
))
11279 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11282 case OPTION_MMNEMONIC
:
11283 if (strcasecmp (arg
, "att") == 0)
11284 intel_mnemonic
= 0;
11285 else if (strcasecmp (arg
, "intel") == 0)
11286 intel_mnemonic
= 1;
11288 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11291 case OPTION_MSYNTAX
:
11292 if (strcasecmp (arg
, "att") == 0)
11294 else if (strcasecmp (arg
, "intel") == 0)
11297 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11300 case OPTION_MINDEX_REG
:
11301 allow_index_reg
= 1;
11304 case OPTION_MNAKED_REG
:
11305 allow_naked_reg
= 1;
11308 case OPTION_MSSE2AVX
:
11312 case OPTION_MSSE_CHECK
:
11313 if (strcasecmp (arg
, "error") == 0)
11314 sse_check
= check_error
;
11315 else if (strcasecmp (arg
, "warning") == 0)
11316 sse_check
= check_warning
;
11317 else if (strcasecmp (arg
, "none") == 0)
11318 sse_check
= check_none
;
11320 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11323 case OPTION_MOPERAND_CHECK
:
11324 if (strcasecmp (arg
, "error") == 0)
11325 operand_check
= check_error
;
11326 else if (strcasecmp (arg
, "warning") == 0)
11327 operand_check
= check_warning
;
11328 else if (strcasecmp (arg
, "none") == 0)
11329 operand_check
= check_none
;
11331 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11334 case OPTION_MAVXSCALAR
:
11335 if (strcasecmp (arg
, "128") == 0)
11336 avxscalar
= vex128
;
11337 else if (strcasecmp (arg
, "256") == 0)
11338 avxscalar
= vex256
;
11340 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11343 case OPTION_MVEXWIG
:
11344 if (strcmp (arg
, "0") == 0)
11346 else if (strcmp (arg
, "1") == 0)
11349 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11352 case OPTION_MADD_BND_PREFIX
:
11353 add_bnd_prefix
= 1;
11356 case OPTION_MEVEXLIG
:
11357 if (strcmp (arg
, "128") == 0)
11358 evexlig
= evexl128
;
11359 else if (strcmp (arg
, "256") == 0)
11360 evexlig
= evexl256
;
11361 else if (strcmp (arg
, "512") == 0)
11362 evexlig
= evexl512
;
11364 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11367 case OPTION_MEVEXRCIG
:
11368 if (strcmp (arg
, "rne") == 0)
11370 else if (strcmp (arg
, "rd") == 0)
11372 else if (strcmp (arg
, "ru") == 0)
11374 else if (strcmp (arg
, "rz") == 0)
11377 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11380 case OPTION_MEVEXWIG
:
11381 if (strcmp (arg
, "0") == 0)
11383 else if (strcmp (arg
, "1") == 0)
11386 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11389 # if defined (TE_PE) || defined (TE_PEP)
11390 case OPTION_MBIG_OBJ
:
11395 case OPTION_MOMIT_LOCK_PREFIX
:
11396 if (strcasecmp (arg
, "yes") == 0)
11397 omit_lock_prefix
= 1;
11398 else if (strcasecmp (arg
, "no") == 0)
11399 omit_lock_prefix
= 0;
11401 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11404 case OPTION_MFENCE_AS_LOCK_ADD
:
11405 if (strcasecmp (arg
, "yes") == 0)
11407 else if (strcasecmp (arg
, "no") == 0)
11410 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11413 case OPTION_MRELAX_RELOCATIONS
:
11414 if (strcasecmp (arg
, "yes") == 0)
11415 generate_relax_relocations
= 1;
11416 else if (strcasecmp (arg
, "no") == 0)
11417 generate_relax_relocations
= 0;
11419 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11422 case OPTION_MAMD64
:
11426 case OPTION_MINTEL64
:
11434 /* Turn off -Os. */
11435 optimize_for_space
= 0;
11437 else if (*arg
== 's')
11439 optimize_for_space
= 1;
11440 /* Turn on all encoding optimizations. */
11441 optimize
= INT_MAX
;
11445 optimize
= atoi (arg
);
11446 /* Turn off -Os. */
11447 optimize_for_space
= 0;
11457 #define MESSAGE_TEMPLATE \
11461 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11462 int *left_p
, const char *name
, int len
)
11464 int size
= sizeof (MESSAGE_TEMPLATE
);
11465 int left
= *left_p
;
11467 /* Reserve 2 spaces for ", " or ",\0" */
11470 /* Check if there is any room. */
11478 p
= mempcpy (p
, name
, len
);
11482 /* Output the current message now and start a new one. */
11485 fprintf (stream
, "%s\n", message
);
11487 left
= size
- (start
- message
) - len
- 2;
11489 gas_assert (left
>= 0);
11491 p
= mempcpy (p
, name
, len
);
11499 show_arch (FILE *stream
, int ext
, int check
)
11501 static char message
[] = MESSAGE_TEMPLATE
;
11502 char *start
= message
+ 27;
11504 int size
= sizeof (MESSAGE_TEMPLATE
);
11511 left
= size
- (start
- message
);
11512 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11514 /* Should it be skipped? */
11515 if (cpu_arch
[j
].skip
)
11518 name
= cpu_arch
[j
].name
;
11519 len
= cpu_arch
[j
].len
;
11522 /* It is an extension. Skip if we aren't asked to show it. */
11533 /* It is an processor. Skip if we show only extension. */
11536 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11538 /* It is an impossible processor - skip. */
11542 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11545 /* Display disabled extensions. */
11547 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11549 name
= cpu_noarch
[j
].name
;
11550 len
= cpu_noarch
[j
].len
;
11551 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11556 fprintf (stream
, "%s\n", message
);
11560 md_show_usage (FILE *stream
)
11562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11563 fprintf (stream
, _("\
11565 -V print assembler version number\n\
11568 fprintf (stream
, _("\
11569 -n Do not optimize code alignment\n\
11570 -q quieten some warnings\n"));
11571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11572 fprintf (stream
, _("\
11575 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11576 || defined (TE_PE) || defined (TE_PEP))
11577 fprintf (stream
, _("\
11578 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11580 #ifdef SVR4_COMMENT_CHARS
11581 fprintf (stream
, _("\
11582 --divide do not treat `/' as a comment character\n"));
11584 fprintf (stream
, _("\
11585 --divide ignored\n"));
11587 fprintf (stream
, _("\
11588 -march=CPU[,+EXTENSION...]\n\
11589 generate code for CPU and EXTENSION, CPU is one of:\n"));
11590 show_arch (stream
, 0, 1);
11591 fprintf (stream
, _("\
11592 EXTENSION is combination of:\n"));
11593 show_arch (stream
, 1, 0);
11594 fprintf (stream
, _("\
11595 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11596 show_arch (stream
, 0, 0);
11597 fprintf (stream
, _("\
11598 -msse2avx encode SSE instructions with VEX prefix\n"));
11599 fprintf (stream
, _("\
11600 -msse-check=[none|error|warning] (default: warning)\n\
11601 check SSE instructions\n"));
11602 fprintf (stream
, _("\
11603 -moperand-check=[none|error|warning] (default: warning)\n\
11604 check operand combinations for validity\n"));
11605 fprintf (stream
, _("\
11606 -mavxscalar=[128|256] (default: 128)\n\
11607 encode scalar AVX instructions with specific vector\n\
11609 fprintf (stream
, _("\
11610 -mvexwig=[0|1] (default: 0)\n\
11611 encode VEX instructions with specific VEX.W value\n\
11612 for VEX.W bit ignored instructions\n"));
11613 fprintf (stream
, _("\
11614 -mevexlig=[128|256|512] (default: 128)\n\
11615 encode scalar EVEX instructions with specific vector\n\
11617 fprintf (stream
, _("\
11618 -mevexwig=[0|1] (default: 0)\n\
11619 encode EVEX instructions with specific EVEX.W value\n\
11620 for EVEX.W bit ignored instructions\n"));
11621 fprintf (stream
, _("\
11622 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11623 encode EVEX instructions with specific EVEX.RC value\n\
11624 for SAE-only ignored instructions\n"));
11625 fprintf (stream
, _("\
11626 -mmnemonic=[att|intel] "));
11627 if (SYSV386_COMPAT
)
11628 fprintf (stream
, _("(default: att)\n"));
11630 fprintf (stream
, _("(default: intel)\n"));
11631 fprintf (stream
, _("\
11632 use AT&T/Intel mnemonic\n"));
11633 fprintf (stream
, _("\
11634 -msyntax=[att|intel] (default: att)\n\
11635 use AT&T/Intel syntax\n"));
11636 fprintf (stream
, _("\
11637 -mindex-reg support pseudo index registers\n"));
11638 fprintf (stream
, _("\
11639 -mnaked-reg don't require `%%' prefix for registers\n"));
11640 fprintf (stream
, _("\
11641 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11642 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11643 fprintf (stream
, _("\
11644 -mshared disable branch optimization for shared code\n"));
11645 fprintf (stream
, _("\
11646 -mx86-used-note=[no|yes] "));
11647 if (DEFAULT_X86_USED_NOTE
)
11648 fprintf (stream
, _("(default: yes)\n"));
11650 fprintf (stream
, _("(default: no)\n"));
11651 fprintf (stream
, _("\
11652 generate x86 used ISA and feature properties\n"));
11654 #if defined (TE_PE) || defined (TE_PEP)
11655 fprintf (stream
, _("\
11656 -mbig-obj generate big object files\n"));
11658 fprintf (stream
, _("\
11659 -momit-lock-prefix=[no|yes] (default: no)\n\
11660 strip all lock prefixes\n"));
11661 fprintf (stream
, _("\
11662 -mfence-as-lock-add=[no|yes] (default: no)\n\
11663 encode lfence, mfence and sfence as\n\
11664 lock addl $0x0, (%%{re}sp)\n"));
11665 fprintf (stream
, _("\
11666 -mrelax-relocations=[no|yes] "));
11667 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11668 fprintf (stream
, _("(default: yes)\n"));
11670 fprintf (stream
, _("(default: no)\n"));
11671 fprintf (stream
, _("\
11672 generate relax relocations\n"));
11673 fprintf (stream
, _("\
11674 -mamd64 accept only AMD64 ISA [default]\n"));
11675 fprintf (stream
, _("\
11676 -mintel64 accept only Intel64 ISA\n"));
11679 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11680 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11681 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11683 /* Pick the target format to use. */
11686 i386_target_format (void)
11688 if (!strncmp (default_arch
, "x86_64", 6))
11690 update_code_flag (CODE_64BIT
, 1);
11691 if (default_arch
[6] == '\0')
11692 x86_elf_abi
= X86_64_ABI
;
11694 x86_elf_abi
= X86_64_X32_ABI
;
11696 else if (!strcmp (default_arch
, "i386"))
11697 update_code_flag (CODE_32BIT
, 1);
11698 else if (!strcmp (default_arch
, "iamcu"))
11700 update_code_flag (CODE_32BIT
, 1);
11701 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11703 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11704 cpu_arch_name
= "iamcu";
11705 cpu_sub_arch_name
= NULL
;
11706 cpu_arch_flags
= iamcu_flags
;
11707 cpu_arch_isa
= PROCESSOR_IAMCU
;
11708 cpu_arch_isa_flags
= iamcu_flags
;
11709 if (!cpu_arch_tune_set
)
11711 cpu_arch_tune
= cpu_arch_isa
;
11712 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11715 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11716 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11720 as_fatal (_("unknown architecture"));
11722 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11723 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11724 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11725 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11727 switch (OUTPUT_FLAVOR
)
11729 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11730 case bfd_target_aout_flavour
:
11731 return AOUT_TARGET_FORMAT
;
11733 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11734 # if defined (TE_PE) || defined (TE_PEP)
11735 case bfd_target_coff_flavour
:
11736 if (flag_code
== CODE_64BIT
)
11737 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11740 # elif defined (TE_GO32)
11741 case bfd_target_coff_flavour
:
11742 return "coff-go32";
11744 case bfd_target_coff_flavour
:
11745 return "coff-i386";
11748 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11749 case bfd_target_elf_flavour
:
11751 const char *format
;
11753 switch (x86_elf_abi
)
11756 format
= ELF_TARGET_FORMAT
;
11759 use_rela_relocations
= 1;
11761 format
= ELF_TARGET_FORMAT64
;
11763 case X86_64_X32_ABI
:
11764 use_rela_relocations
= 1;
11766 disallow_64bit_reloc
= 1;
11767 format
= ELF_TARGET_FORMAT32
;
11770 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11772 if (x86_elf_abi
!= X86_64_ABI
)
11773 as_fatal (_("Intel L1OM is 64bit only"));
11774 return ELF_TARGET_L1OM_FORMAT
;
11776 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11778 if (x86_elf_abi
!= X86_64_ABI
)
11779 as_fatal (_("Intel K1OM is 64bit only"));
11780 return ELF_TARGET_K1OM_FORMAT
;
11782 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11784 if (x86_elf_abi
!= I386_ABI
)
11785 as_fatal (_("Intel MCU is 32bit only"));
11786 return ELF_TARGET_IAMCU_FORMAT
;
11792 #if defined (OBJ_MACH_O)
11793 case bfd_target_mach_o_flavour
:
11794 if (flag_code
== CODE_64BIT
)
11796 use_rela_relocations
= 1;
11798 return "mach-o-x86-64";
11801 return "mach-o-i386";
11809 #endif /* OBJ_MAYBE_ more than one */
11812 md_undefined_symbol (char *name
)
11814 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11815 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11816 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11817 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11821 if (symbol_find (name
))
11822 as_bad (_("GOT already in symbol table"));
11823 GOT_symbol
= symbol_new (name
, undefined_section
,
11824 (valueT
) 0, &zero_address_frag
);
11831 /* Round up a section size to the appropriate boundary. */
11834 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11836 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11837 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11839 /* For a.out, force the section size to be aligned. If we don't do
11840 this, BFD will align it for us, but it will not write out the
11841 final bytes of the section. This may be a bug in BFD, but it is
11842 easier to fix it here since that is how the other a.out targets
11846 align
= bfd_get_section_alignment (stdoutput
, segment
);
11847 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11854 /* On the i386, PC-relative offsets are relative to the start of the
11855 next instruction. That is, the address of the offset, plus its
11856 size, since the offset is always the last part of the insn. */
11859 md_pcrel_from (fixS
*fixP
)
11861 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11867 s_bss (int ignore ATTRIBUTE_UNUSED
)
11871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11873 obj_elf_section_change_hook ();
11875 temp
= get_absolute_expression ();
11876 subseg_set (bss_section
, (subsegT
) temp
);
11877 demand_empty_rest_of_line ();
11883 i386_validate_fix (fixS
*fixp
)
11885 if (fixp
->fx_subsy
)
11887 if (fixp
->fx_subsy
== GOT_symbol
)
11889 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11894 if (fixp
->fx_tcbit2
)
11895 fixp
->fx_r_type
= (fixp
->fx_tcbit
11896 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11897 : BFD_RELOC_X86_64_GOTPCRELX
);
11900 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11905 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11907 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11909 fixp
->fx_subsy
= 0;
11912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11913 else if (!object_64bit
)
11915 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11916 && fixp
->fx_tcbit2
)
11917 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11923 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11926 bfd_reloc_code_real_type code
;
11928 switch (fixp
->fx_r_type
)
11930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11931 case BFD_RELOC_SIZE32
:
11932 case BFD_RELOC_SIZE64
:
11933 if (S_IS_DEFINED (fixp
->fx_addsy
)
11934 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11936 /* Resolve size relocation against local symbol to size of
11937 the symbol plus addend. */
11938 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11939 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11940 && !fits_in_unsigned_long (value
))
11941 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11942 _("symbol size computation overflow"));
11943 fixp
->fx_addsy
= NULL
;
11944 fixp
->fx_subsy
= NULL
;
11945 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11949 /* Fall through. */
11951 case BFD_RELOC_X86_64_PLT32
:
11952 case BFD_RELOC_X86_64_GOT32
:
11953 case BFD_RELOC_X86_64_GOTPCREL
:
11954 case BFD_RELOC_X86_64_GOTPCRELX
:
11955 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11956 case BFD_RELOC_386_PLT32
:
11957 case BFD_RELOC_386_GOT32
:
11958 case BFD_RELOC_386_GOT32X
:
11959 case BFD_RELOC_386_GOTOFF
:
11960 case BFD_RELOC_386_GOTPC
:
11961 case BFD_RELOC_386_TLS_GD
:
11962 case BFD_RELOC_386_TLS_LDM
:
11963 case BFD_RELOC_386_TLS_LDO_32
:
11964 case BFD_RELOC_386_TLS_IE_32
:
11965 case BFD_RELOC_386_TLS_IE
:
11966 case BFD_RELOC_386_TLS_GOTIE
:
11967 case BFD_RELOC_386_TLS_LE_32
:
11968 case BFD_RELOC_386_TLS_LE
:
11969 case BFD_RELOC_386_TLS_GOTDESC
:
11970 case BFD_RELOC_386_TLS_DESC_CALL
:
11971 case BFD_RELOC_X86_64_TLSGD
:
11972 case BFD_RELOC_X86_64_TLSLD
:
11973 case BFD_RELOC_X86_64_DTPOFF32
:
11974 case BFD_RELOC_X86_64_DTPOFF64
:
11975 case BFD_RELOC_X86_64_GOTTPOFF
:
11976 case BFD_RELOC_X86_64_TPOFF32
:
11977 case BFD_RELOC_X86_64_TPOFF64
:
11978 case BFD_RELOC_X86_64_GOTOFF64
:
11979 case BFD_RELOC_X86_64_GOTPC32
:
11980 case BFD_RELOC_X86_64_GOT64
:
11981 case BFD_RELOC_X86_64_GOTPCREL64
:
11982 case BFD_RELOC_X86_64_GOTPC64
:
11983 case BFD_RELOC_X86_64_GOTPLT64
:
11984 case BFD_RELOC_X86_64_PLTOFF64
:
11985 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11986 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11987 case BFD_RELOC_RVA
:
11988 case BFD_RELOC_VTABLE_ENTRY
:
11989 case BFD_RELOC_VTABLE_INHERIT
:
11991 case BFD_RELOC_32_SECREL
:
11993 code
= fixp
->fx_r_type
;
11995 case BFD_RELOC_X86_64_32S
:
11996 if (!fixp
->fx_pcrel
)
11998 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11999 code
= fixp
->fx_r_type
;
12002 /* Fall through. */
12004 if (fixp
->fx_pcrel
)
12006 switch (fixp
->fx_size
)
12009 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12010 _("can not do %d byte pc-relative relocation"),
12012 code
= BFD_RELOC_32_PCREL
;
12014 case 1: code
= BFD_RELOC_8_PCREL
; break;
12015 case 2: code
= BFD_RELOC_16_PCREL
; break;
12016 case 4: code
= BFD_RELOC_32_PCREL
; break;
12018 case 8: code
= BFD_RELOC_64_PCREL
; break;
12024 switch (fixp
->fx_size
)
12027 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12028 _("can not do %d byte relocation"),
12030 code
= BFD_RELOC_32
;
12032 case 1: code
= BFD_RELOC_8
; break;
12033 case 2: code
= BFD_RELOC_16
; break;
12034 case 4: code
= BFD_RELOC_32
; break;
12036 case 8: code
= BFD_RELOC_64
; break;
12043 if ((code
== BFD_RELOC_32
12044 || code
== BFD_RELOC_32_PCREL
12045 || code
== BFD_RELOC_X86_64_32S
)
12047 && fixp
->fx_addsy
== GOT_symbol
)
12050 code
= BFD_RELOC_386_GOTPC
;
12052 code
= BFD_RELOC_X86_64_GOTPC32
;
12054 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12056 && fixp
->fx_addsy
== GOT_symbol
)
12058 code
= BFD_RELOC_X86_64_GOTPC64
;
12061 rel
= XNEW (arelent
);
12062 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12063 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12065 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12067 if (!use_rela_relocations
)
12069 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12070 vtable entry to be used in the relocation's section offset. */
12071 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12072 rel
->address
= fixp
->fx_offset
;
12073 #if defined (OBJ_COFF) && defined (TE_PE)
12074 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12075 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12080 /* Use the rela in 64bit mode. */
12083 if (disallow_64bit_reloc
)
12086 case BFD_RELOC_X86_64_DTPOFF64
:
12087 case BFD_RELOC_X86_64_TPOFF64
:
12088 case BFD_RELOC_64_PCREL
:
12089 case BFD_RELOC_X86_64_GOTOFF64
:
12090 case BFD_RELOC_X86_64_GOT64
:
12091 case BFD_RELOC_X86_64_GOTPCREL64
:
12092 case BFD_RELOC_X86_64_GOTPC64
:
12093 case BFD_RELOC_X86_64_GOTPLT64
:
12094 case BFD_RELOC_X86_64_PLTOFF64
:
12095 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12096 _("cannot represent relocation type %s in x32 mode"),
12097 bfd_get_reloc_code_name (code
));
12103 if (!fixp
->fx_pcrel
)
12104 rel
->addend
= fixp
->fx_offset
;
12108 case BFD_RELOC_X86_64_PLT32
:
12109 case BFD_RELOC_X86_64_GOT32
:
12110 case BFD_RELOC_X86_64_GOTPCREL
:
12111 case BFD_RELOC_X86_64_GOTPCRELX
:
12112 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12113 case BFD_RELOC_X86_64_TLSGD
:
12114 case BFD_RELOC_X86_64_TLSLD
:
12115 case BFD_RELOC_X86_64_GOTTPOFF
:
12116 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12117 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12118 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12121 rel
->addend
= (section
->vma
12123 + fixp
->fx_addnumber
12124 + md_pcrel_from (fixp
));
12129 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12130 if (rel
->howto
== NULL
)
12132 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12133 _("cannot represent relocation type %s"),
12134 bfd_get_reloc_code_name (code
));
12135 /* Set howto to a garbage value so that we can keep going. */
12136 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12137 gas_assert (rel
->howto
!= NULL
);
12143 #include "tc-i386-intel.c"
12146 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12148 int saved_naked_reg
;
12149 char saved_register_dot
;
12151 saved_naked_reg
= allow_naked_reg
;
12152 allow_naked_reg
= 1;
12153 saved_register_dot
= register_chars
['.'];
12154 register_chars
['.'] = '.';
12155 allow_pseudo_reg
= 1;
12156 expression_and_evaluate (exp
);
12157 allow_pseudo_reg
= 0;
12158 register_chars
['.'] = saved_register_dot
;
12159 allow_naked_reg
= saved_naked_reg
;
12161 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12163 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12165 exp
->X_op
= O_constant
;
12166 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12167 .dw2_regnum
[flag_code
>> 1];
12170 exp
->X_op
= O_illegal
;
12175 tc_x86_frame_initial_instructions (void)
12177 static unsigned int sp_regno
[2];
12179 if (!sp_regno
[flag_code
>> 1])
12181 char *saved_input
= input_line_pointer
;
12182 char sp
[][4] = {"esp", "rsp"};
12185 input_line_pointer
= sp
[flag_code
>> 1];
12186 tc_x86_parse_to_dw2regnum (&exp
);
12187 gas_assert (exp
.X_op
== O_constant
);
12188 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12189 input_line_pointer
= saved_input
;
12192 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12193 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12197 x86_dwarf2_addr_size (void)
12199 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12200 if (x86_elf_abi
== X86_64_X32_ABI
)
12203 return bfd_arch_bits_per_address (stdoutput
) / 8;
12207 i386_elf_section_type (const char *str
, size_t len
)
12209 if (flag_code
== CODE_64BIT
12210 && len
== sizeof ("unwind") - 1
12211 && strncmp (str
, "unwind", 6) == 0)
12212 return SHT_X86_64_UNWIND
;
12219 i386_solaris_fix_up_eh_frame (segT sec
)
12221 if (flag_code
== CODE_64BIT
)
12222 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12228 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12232 exp
.X_op
= O_secrel
;
12233 exp
.X_add_symbol
= symbol
;
12234 exp
.X_add_number
= 0;
12235 emit_expr (&exp
, size
);
12239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12240 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12243 x86_64_section_letter (int letter
, const char **ptr_msg
)
12245 if (flag_code
== CODE_64BIT
)
12248 return SHF_X86_64_LARGE
;
12250 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12253 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12258 x86_64_section_word (char *str
, size_t len
)
12260 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12261 return SHF_X86_64_LARGE
;
12267 handle_large_common (int small ATTRIBUTE_UNUSED
)
12269 if (flag_code
!= CODE_64BIT
)
12271 s_comm_internal (0, elf_common_parse
);
12272 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12276 static segT lbss_section
;
12277 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12278 asection
*saved_bss_section
= bss_section
;
12280 if (lbss_section
== NULL
)
12282 flagword applicable
;
12283 segT seg
= now_seg
;
12284 subsegT subseg
= now_subseg
;
12286 /* The .lbss section is for local .largecomm symbols. */
12287 lbss_section
= subseg_new (".lbss", 0);
12288 applicable
= bfd_applicable_section_flags (stdoutput
);
12289 bfd_set_section_flags (stdoutput
, lbss_section
,
12290 applicable
& SEC_ALLOC
);
12291 seg_info (lbss_section
)->bss
= 1;
12293 subseg_set (seg
, subseg
);
12296 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12297 bss_section
= lbss_section
;
12299 s_comm_internal (0, elf_common_parse
);
12301 elf_com_section_ptr
= saved_com_section_ptr
;
12302 bss_section
= saved_bss_section
;
12305 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */