1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c
);
69 static int i386_att_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry
*parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry
*build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS
*, offsetT
);
91 static void output_disp (fragS
*, offsetT
);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
99 static const char *default_arch
= DEFAULT_ARCH
;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry
*regs
;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands
;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types
[MAX_OPERANDS
];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op
[MAX_OPERANDS
];
136 /* Flags for operands. */
137 unsigned int flags
[MAX_OPERANDS
];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry
*base_reg
;
146 const reg_entry
*index_reg
;
147 unsigned int log2_scale_factor
;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry
*seg
[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes
;
156 unsigned char prefix
[MAX_PREFIXES
];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn
;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars
[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars
= "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars
= "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "#/";
210 const char line_separator_chars
[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS
[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS
[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars
[256];
223 static char register_chars
[256];
224 static char operand_chars
[256];
225 static char identifier_chars
[256];
226 static char digit_chars
[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack
[32];
244 static char *save_stack_p
;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates
*current_templates
;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
258 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
260 /* Current operand we are working on. */
261 static int this_operand
;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code
;
272 static unsigned int object_64bit
;
273 static int use_rela_relocations
= 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names
[] =
283 /* 1 for intel syntax,
285 static int intel_syntax
= 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic
= !SYSV386_COMPAT
;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc
= OLDGCC_COMPAT
;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg
= 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg
= 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix
= "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size
= '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code
= 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings
= 0;
315 static const char *cpu_arch_name
= NULL
;
316 static const char *cpu_sub_arch_name
= NULL
;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set
= 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags
;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags
;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion
= 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS
*GOT_symbol
;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column
;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment
;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table
[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch
[] =
430 {"generic32", PROCESSOR_GENERIC32
,
431 CPU_GENERIC32_FLAGS
},
432 {"generic64", PROCESSOR_GENERIC64
,
433 CPU_GENERIC64_FLAGS
},
434 {"i8086", PROCESSOR_UNKNOWN
,
436 {"i186", PROCESSOR_UNKNOWN
,
438 {"i286", PROCESSOR_UNKNOWN
,
440 {"i386", PROCESSOR_I386
,
442 {"i486", PROCESSOR_I486
,
444 {"i586", PROCESSOR_PENTIUM
,
446 {"i686", PROCESSOR_PENTIUMPRO
,
448 {"pentium", PROCESSOR_PENTIUM
,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
452 {"pentiumii", PROCESSOR_PENTIUMPRO
,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
456 {"pentium4", PROCESSOR_PENTIUM4
,
458 {"prescott", PROCESSOR_NOCONA
,
460 {"nocona", PROCESSOR_NOCONA
,
462 {"yonah", PROCESSOR_CORE
,
464 {"core", PROCESSOR_CORE
,
466 {"merom", PROCESSOR_CORE2
,
468 {"core2", PROCESSOR_CORE2
,
472 {"k6_2", PROCESSOR_K6
,
474 {"athlon", PROCESSOR_ATHLON
,
476 {"sledgehammer", PROCESSOR_K8
,
478 {"opteron", PROCESSOR_K8
,
482 {"amdfam10", PROCESSOR_AMDFAM10
,
483 CPU_AMDFAM10_FLAGS
},
484 {".mmx", PROCESSOR_UNKNOWN
,
486 {".sse", PROCESSOR_UNKNOWN
,
488 {".sse2", PROCESSOR_UNKNOWN
,
490 {".sse3", PROCESSOR_UNKNOWN
,
492 {".ssse3", PROCESSOR_UNKNOWN
,
494 {".sse4.1", PROCESSOR_UNKNOWN
,
496 {".sse4.2", PROCESSOR_UNKNOWN
,
498 {".sse4", PROCESSOR_UNKNOWN
,
500 {".3dnow", PROCESSOR_UNKNOWN
,
502 {".3dnowa", PROCESSOR_UNKNOWN
,
504 {".padlock", PROCESSOR_UNKNOWN
,
506 {".pacifica", PROCESSOR_UNKNOWN
,
508 {".svme", PROCESSOR_UNKNOWN
,
510 {".sse4a", PROCESSOR_UNKNOWN
,
512 {".abm", PROCESSOR_UNKNOWN
,
514 {".sse5", PROCESSOR_UNKNOWN
,
518 const pseudo_typeS md_pseudo_table
[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes
, 0},
523 {"align", s_align_ptwo
, 0},
525 {"arch", set_cpu_arch
, 0},
529 {"ffloat", float_cons
, 'f'},
530 {"dfloat", float_cons
, 'd'},
531 {"tfloat", float_cons
, 'x'},
533 {"slong", signed_cons
, 4},
534 {"noopt", s_ignore
, 0},
535 {"optim", s_ignore
, 0},
536 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
537 {"code16", set_code_flag
, CODE_16BIT
},
538 {"code32", set_code_flag
, CODE_32BIT
},
539 {"code64", set_code_flag
, CODE_64BIT
},
540 {"intel_syntax", set_intel_syntax
, 1},
541 {"att_syntax", set_intel_syntax
, 0},
542 {"intel_mnemonic", set_intel_mnemonic
, 1},
543 {"att_mnemonic", set_intel_mnemonic
, 0},
544 {"allow_index_reg", set_allow_index_reg
, 1},
545 {"disallow_index_reg", set_allow_index_reg
, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common
, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
550 {"loc", dwarf2_directive_loc
, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
554 {"secrel32", pe_directive_secrel
, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer
;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control
*op_hash
;
565 /* Hash table for register lookup. */
566 static struct hash_control
*reg_hash
;
569 i386_align_code (fragS
*fragP
, int count
)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1
[] =
576 static const char f32_2
[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3
[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4
[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5
[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6
[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7
[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8
[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9
[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10
[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11
[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12
[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13
[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14
[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3
[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4
[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5
[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6
[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7
[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8
[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31
[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt
[] = {
632 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
633 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
635 static const char *const f16_patt
[] = {
636 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
639 static const char alt_3
[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4
[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5
[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6
[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7
[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8
[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9
[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10
[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14
[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15
[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11
[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13
[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15
[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
735 alt_short_14
, alt_short_15
737 static const char *const alt_long_patt
[] = {
738 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
739 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
740 alt_long_14
, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code
== CODE_16BIT
)
769 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
771 /* Adjust jump offset. */
772 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
775 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
776 f16_patt
[count
- 1], count
);
780 const char *const *patt
= NULL
;
782 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune
)
787 case PROCESSOR_UNKNOWN
:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
791 patt
= alt_long_patt
;
795 case PROCESSOR_PENTIUMPRO
:
796 case PROCESSOR_PENTIUM4
:
797 case PROCESSOR_NOCONA
:
799 case PROCESSOR_CORE2
:
800 case PROCESSOR_GENERIC64
:
801 patt
= alt_long_patt
;
804 case PROCESSOR_ATHLON
:
806 case PROCESSOR_AMDFAM10
:
807 patt
= alt_short_patt
;
811 case PROCESSOR_PENTIUM
:
812 case PROCESSOR_GENERIC32
:
819 switch (cpu_arch_tune
)
821 case PROCESSOR_UNKNOWN
:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM
:
831 case PROCESSOR_ATHLON
:
833 case PROCESSOR_AMDFAM10
:
834 case PROCESSOR_GENERIC32
:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
838 patt
= alt_short_patt
;
842 case PROCESSOR_PENTIUMPRO
:
843 case PROCESSOR_PENTIUM4
:
844 case PROCESSOR_NOCONA
:
846 case PROCESSOR_CORE2
:
847 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
848 patt
= alt_long_patt
;
852 case PROCESSOR_GENERIC64
:
853 patt
= alt_long_patt
;
858 if (patt
== f32_patt
)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
865 patt
[count
- 1], count
);
868 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
870 /* Adjust jump offset. */
871 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
888 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
889 patt
[padding
- 1], padding
);
892 fragP
->fr_var
= count
;
896 uints_all_zero (const unsigned int *x
, unsigned int size
)
914 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
931 uints_equal (const unsigned int *x
, const unsigned int *y
,
943 return x
[0] == y
[0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f
)
962 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
963 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
969 switch (ARRAY_SIZE (x
.array
))
972 x
.array
[2] &= y
.array
[2];
974 x
.array
[1] &= y
.array
[1];
976 x
.array
[0] &= y
.array
[0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
987 switch (ARRAY_SIZE (x
.array
))
990 x
.array
[2] |= y
.array
[2];
992 x
.array
[1] |= y
.array
[1];
994 x
.array
[0] |= y
.array
[0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x
)
1008 int overlap
= cpu_flags_check_cpu64 (x
) ? 2 : 0;
1010 x
.bitfield
.cpu64
= 0;
1011 x
.bitfield
.cpuno64
= 0;
1013 if (UINTS_ALL_ZERO (x
))
1017 i386_cpu_flags cpu
= cpu_arch_flags
;
1019 cpu
.bitfield
.cpu64
= 0;
1020 cpu
.bitfield
.cpuno64
= 0;
1021 cpu
= cpu_flags_and (x
, cpu
);
1022 overlap
|= UINTS_ALL_ZERO (cpu
) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1030 switch (ARRAY_SIZE (x
.array
))
1033 x
.array
[2] &= y
.array
[2];
1035 x
.array
[1] &= y
.array
[1];
1037 x
.array
[0] &= y
.array
[0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1048 switch (ARRAY_SIZE (x
.array
))
1051 x
.array
[2] |= y
.array
[2];
1053 x
.array
[1] |= y
.array
[1];
1055 x
.array
[0] |= y
.array
[0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1066 switch (ARRAY_SIZE (x
.array
))
1069 x
.array
[2] ^= y
.array
[2];
1071 x
.array
[1] ^= y
.array
[1];
1073 x
.array
[0] ^= y
.array
[0];
1081 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1082 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1083 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1086 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1087 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1088 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1089 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP
;
1092 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1093 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1094 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1095 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1096 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1097 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1098 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1099 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1100 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1101 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1112 operand_type_check (i386_operand_type t
, enum operand_type c
)
1117 return (t
.bitfield
.reg8
1120 || t
.bitfield
.reg64
);
1123 return (t
.bitfield
.imm8
1127 || t
.bitfield
.imm32s
1128 || t
.bitfield
.imm64
);
1131 return (t
.bitfield
.disp8
1132 || t
.bitfield
.disp16
1133 || t
.bitfield
.disp32
1134 || t
.bitfield
.disp32s
1135 || t
.bitfield
.disp64
);
1138 return (t
.bitfield
.disp8
1139 || t
.bitfield
.disp16
1140 || t
.bitfield
.disp32
1141 || t
.bitfield
.disp32s
1142 || t
.bitfield
.disp64
1143 || t
.bitfield
.baseindex
);
1151 operand_type_match (i386_operand_type overlap
,
1152 i386_operand_type given
)
1154 i386_operand_type temp
= overlap
;
1156 temp
.bitfield
.jumpabsolute
= 0;
1157 temp
.bitfield
.unspecified
= 0;
1158 if (UINTS_ALL_ZERO (temp
))
1161 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1162 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1165 /* If given types g0 and g1 are registers they must be of the same type
1166 unless the expected operand type register overlap is null.
1167 Note that Acc in a template matches every size of reg. */
1170 operand_type_register_match (i386_operand_type m0
,
1171 i386_operand_type g0
,
1172 i386_operand_type t0
,
1173 i386_operand_type m1
,
1174 i386_operand_type g1
,
1175 i386_operand_type t1
)
1177 if (!operand_type_check (g0
, reg
))
1180 if (!operand_type_check (g1
, reg
))
1183 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1184 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1185 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1186 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1189 if (m0
.bitfield
.acc
)
1191 t0
.bitfield
.reg8
= 1;
1192 t0
.bitfield
.reg16
= 1;
1193 t0
.bitfield
.reg32
= 1;
1194 t0
.bitfield
.reg64
= 1;
1197 if (m1
.bitfield
.acc
)
1199 t1
.bitfield
.reg8
= 1;
1200 t1
.bitfield
.reg16
= 1;
1201 t1
.bitfield
.reg32
= 1;
1202 t1
.bitfield
.reg64
= 1;
1205 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1206 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1207 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1208 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1211 static INLINE
unsigned int
1212 mode_from_disp_size (i386_operand_type t
)
1214 if (t
.bitfield
.disp8
)
1216 else if (t
.bitfield
.disp16
1217 || t
.bitfield
.disp32
1218 || t
.bitfield
.disp32s
)
1225 fits_in_signed_byte (offsetT num
)
1227 return (num
>= -128) && (num
<= 127);
1231 fits_in_unsigned_byte (offsetT num
)
1233 return (num
& 0xff) == num
;
1237 fits_in_unsigned_word (offsetT num
)
1239 return (num
& 0xffff) == num
;
1243 fits_in_signed_word (offsetT num
)
1245 return (-32768 <= num
) && (num
<= 32767);
1249 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1254 return (!(((offsetT
) -1 << 31) & num
)
1255 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1257 } /* fits_in_signed_long() */
1260 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1265 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1267 } /* fits_in_unsigned_long() */
1269 static i386_operand_type
1270 smallest_imm_type (offsetT num
)
1272 i386_operand_type t
;
1275 t
.bitfield
.imm64
= 1;
1277 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1279 /* This code is disabled on the 486 because all the Imm1 forms
1280 in the opcode table are slower on the i486. They're the
1281 versions with the implicitly specified single-position
1282 displacement, which has another syntax if you really want to
1284 t
.bitfield
.imm1
= 1;
1285 t
.bitfield
.imm8
= 1;
1286 t
.bitfield
.imm8s
= 1;
1287 t
.bitfield
.imm16
= 1;
1288 t
.bitfield
.imm32
= 1;
1289 t
.bitfield
.imm32s
= 1;
1291 else if (fits_in_signed_byte (num
))
1293 t
.bitfield
.imm8
= 1;
1294 t
.bitfield
.imm8s
= 1;
1295 t
.bitfield
.imm16
= 1;
1296 t
.bitfield
.imm32
= 1;
1297 t
.bitfield
.imm32s
= 1;
1299 else if (fits_in_unsigned_byte (num
))
1301 t
.bitfield
.imm8
= 1;
1302 t
.bitfield
.imm16
= 1;
1303 t
.bitfield
.imm32
= 1;
1304 t
.bitfield
.imm32s
= 1;
1306 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1308 t
.bitfield
.imm16
= 1;
1309 t
.bitfield
.imm32
= 1;
1310 t
.bitfield
.imm32s
= 1;
1312 else if (fits_in_signed_long (num
))
1314 t
.bitfield
.imm32
= 1;
1315 t
.bitfield
.imm32s
= 1;
1317 else if (fits_in_unsigned_long (num
))
1318 t
.bitfield
.imm32
= 1;
1324 offset_in_range (offsetT val
, int size
)
1330 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1331 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1332 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1334 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1339 /* If BFD64, sign extend val. */
1340 if (!use_rela_relocations
)
1341 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1342 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1344 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1346 char buf1
[40], buf2
[40];
1348 sprint_value (buf1
, val
);
1349 sprint_value (buf2
, val
& mask
);
1350 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1355 /* Returns 0 if attempting to add a prefix where one from the same
1356 class already exists, 1 if non rep/repne added, 2 if rep/repne
1359 add_prefix (unsigned int prefix
)
1364 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1365 && flag_code
== CODE_64BIT
)
1367 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1368 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1369 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1380 case CS_PREFIX_OPCODE
:
1381 case DS_PREFIX_OPCODE
:
1382 case ES_PREFIX_OPCODE
:
1383 case FS_PREFIX_OPCODE
:
1384 case GS_PREFIX_OPCODE
:
1385 case SS_PREFIX_OPCODE
:
1389 case REPNE_PREFIX_OPCODE
:
1390 case REPE_PREFIX_OPCODE
:
1393 case LOCK_PREFIX_OPCODE
:
1401 case ADDR_PREFIX_OPCODE
:
1405 case DATA_PREFIX_OPCODE
:
1409 if (i
.prefix
[q
] != 0)
1417 i
.prefix
[q
] |= prefix
;
1420 as_bad (_("same type of prefix used twice"));
1426 set_code_flag (int value
)
1429 if (flag_code
== CODE_64BIT
)
1431 cpu_arch_flags
.bitfield
.cpu64
= 1;
1432 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1436 cpu_arch_flags
.bitfield
.cpu64
= 0;
1437 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1439 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1441 as_bad (_("64bit mode not supported on this CPU."));
1443 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1445 as_bad (_("32bit mode not supported on this CPU."));
1447 stackop_size
= '\0';
1451 set_16bit_gcc_code_flag (int new_code_flag
)
1453 flag_code
= new_code_flag
;
1454 if (flag_code
!= CODE_16BIT
)
1456 cpu_arch_flags
.bitfield
.cpu64
= 0;
1457 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1458 stackop_size
= LONG_MNEM_SUFFIX
;
1462 set_intel_syntax (int syntax_flag
)
1464 /* Find out if register prefixing is specified. */
1465 int ask_naked_reg
= 0;
1468 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1470 char *string
= input_line_pointer
;
1471 int e
= get_symbol_end ();
1473 if (strcmp (string
, "prefix") == 0)
1475 else if (strcmp (string
, "noprefix") == 0)
1478 as_bad (_("bad argument to syntax directive."));
1479 *input_line_pointer
= e
;
1481 demand_empty_rest_of_line ();
1483 intel_syntax
= syntax_flag
;
1485 if (ask_naked_reg
== 0)
1486 allow_naked_reg
= (intel_syntax
1487 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1489 allow_naked_reg
= (ask_naked_reg
< 0);
1491 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1492 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1493 register_prefix
= allow_naked_reg
? "" : "%";
1497 set_intel_mnemonic (int mnemonic_flag
)
1499 intel_mnemonic
= mnemonic_flag
;
1503 set_allow_index_reg (int flag
)
1505 allow_index_reg
= flag
;
1509 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1513 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1515 char *string
= input_line_pointer
;
1516 int e
= get_symbol_end ();
1518 i386_cpu_flags flags
;
1520 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1522 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1526 cpu_arch_name
= cpu_arch
[i
].name
;
1527 cpu_sub_arch_name
= NULL
;
1528 cpu_arch_flags
= cpu_arch
[i
].flags
;
1529 if (flag_code
== CODE_64BIT
)
1531 cpu_arch_flags
.bitfield
.cpu64
= 1;
1532 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1536 cpu_arch_flags
.bitfield
.cpu64
= 0;
1537 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1539 cpu_arch_isa
= cpu_arch
[i
].type
;
1540 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1541 if (!cpu_arch_tune_set
)
1543 cpu_arch_tune
= cpu_arch_isa
;
1544 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1549 flags
= cpu_flags_or (cpu_arch_flags
,
1551 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1553 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1554 cpu_arch_flags
= flags
;
1556 *input_line_pointer
= e
;
1557 demand_empty_rest_of_line ();
1561 if (i
>= ARRAY_SIZE (cpu_arch
))
1562 as_bad (_("no such architecture: `%s'"), string
);
1564 *input_line_pointer
= e
;
1567 as_bad (_("missing cpu architecture"));
1569 no_cond_jump_promotion
= 0;
1570 if (*input_line_pointer
== ','
1571 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1573 char *string
= ++input_line_pointer
;
1574 int e
= get_symbol_end ();
1576 if (strcmp (string
, "nojumps") == 0)
1577 no_cond_jump_promotion
= 1;
1578 else if (strcmp (string
, "jumps") == 0)
1581 as_bad (_("no such architecture modifier: `%s'"), string
);
1583 *input_line_pointer
= e
;
1586 demand_empty_rest_of_line ();
1592 if (!strcmp (default_arch
, "x86_64"))
1593 return bfd_mach_x86_64
;
1594 else if (!strcmp (default_arch
, "i386"))
1595 return bfd_mach_i386_i386
;
1597 as_fatal (_("Unknown architecture"));
1603 const char *hash_err
;
1605 /* Initialize op_hash hash table. */
1606 op_hash
= hash_new ();
1609 const template *optab
;
1610 templates
*core_optab
;
1612 /* Setup for loop. */
1614 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1615 core_optab
->start
= optab
;
1620 if (optab
->name
== NULL
1621 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1623 /* different name --> ship out current template list;
1624 add to hash table; & begin anew. */
1625 core_optab
->end
= optab
;
1626 hash_err
= hash_insert (op_hash
,
1631 as_fatal (_("Internal Error: Can't hash %s: %s"),
1635 if (optab
->name
== NULL
)
1637 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1638 core_optab
->start
= optab
;
1643 /* Initialize reg_hash hash table. */
1644 reg_hash
= hash_new ();
1646 const reg_entry
*regtab
;
1647 unsigned int regtab_size
= i386_regtab_size
;
1649 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1651 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1653 as_fatal (_("Internal Error: Can't hash %s: %s"),
1659 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1664 for (c
= 0; c
< 256; c
++)
1669 mnemonic_chars
[c
] = c
;
1670 register_chars
[c
] = c
;
1671 operand_chars
[c
] = c
;
1673 else if (ISLOWER (c
))
1675 mnemonic_chars
[c
] = c
;
1676 register_chars
[c
] = c
;
1677 operand_chars
[c
] = c
;
1679 else if (ISUPPER (c
))
1681 mnemonic_chars
[c
] = TOLOWER (c
);
1682 register_chars
[c
] = mnemonic_chars
[c
];
1683 operand_chars
[c
] = c
;
1686 if (ISALPHA (c
) || ISDIGIT (c
))
1687 identifier_chars
[c
] = c
;
1690 identifier_chars
[c
] = c
;
1691 operand_chars
[c
] = c
;
1696 identifier_chars
['@'] = '@';
1699 identifier_chars
['?'] = '?';
1700 operand_chars
['?'] = '?';
1702 digit_chars
['-'] = '-';
1703 mnemonic_chars
['-'] = '-';
1704 mnemonic_chars
['.'] = '.';
1705 identifier_chars
['_'] = '_';
1706 identifier_chars
['.'] = '.';
1708 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1709 operand_chars
[(unsigned char) *p
] = *p
;
1712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1715 record_alignment (text_section
, 2);
1716 record_alignment (data_section
, 2);
1717 record_alignment (bss_section
, 2);
1721 if (flag_code
== CODE_64BIT
)
1723 x86_dwarf2_return_column
= 16;
1724 x86_cie_data_alignment
= -8;
1728 x86_dwarf2_return_column
= 8;
1729 x86_cie_data_alignment
= -4;
1734 i386_print_statistics (FILE *file
)
1736 hash_print_statistics (file
, "i386 opcode", op_hash
);
1737 hash_print_statistics (file
, "i386 register", reg_hash
);
1742 /* Debugging routines for md_assemble. */
1743 static void pte (template *);
1744 static void pt (i386_operand_type
);
1745 static void pe (expressionS
*);
1746 static void ps (symbolS
*);
1749 pi (char *line
, i386_insn
*x
)
1753 fprintf (stdout
, "%s: template ", line
);
1755 fprintf (stdout
, " address: base %s index %s scale %x\n",
1756 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1757 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1758 x
->log2_scale_factor
);
1759 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1760 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1761 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1762 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1763 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1764 (x
->rex
& REX_W
) != 0,
1765 (x
->rex
& REX_R
) != 0,
1766 (x
->rex
& REX_X
) != 0,
1767 (x
->rex
& REX_B
) != 0);
1768 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
1769 x
->drex
.reg
, x
->drex
.rex
);
1770 for (i
= 0; i
< x
->operands
; i
++)
1772 fprintf (stdout
, " #%d: ", i
+ 1);
1774 fprintf (stdout
, "\n");
1775 if (x
->types
[i
].bitfield
.reg8
1776 || x
->types
[i
].bitfield
.reg16
1777 || x
->types
[i
].bitfield
.reg32
1778 || x
->types
[i
].bitfield
.reg64
1779 || x
->types
[i
].bitfield
.regmmx
1780 || x
->types
[i
].bitfield
.regxmm
1781 || x
->types
[i
].bitfield
.sreg2
1782 || x
->types
[i
].bitfield
.sreg3
1783 || x
->types
[i
].bitfield
.control
1784 || x
->types
[i
].bitfield
.debug
1785 || x
->types
[i
].bitfield
.test
)
1786 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1787 if (operand_type_check (x
->types
[i
], imm
))
1789 if (operand_type_check (x
->types
[i
], disp
))
1790 pe (x
->op
[i
].disps
);
1798 fprintf (stdout
, " %d operands ", t
->operands
);
1799 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1800 if (t
->extension_opcode
!= None
)
1801 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1802 if (t
->opcode_modifier
.d
)
1803 fprintf (stdout
, "D");
1804 if (t
->opcode_modifier
.w
)
1805 fprintf (stdout
, "W");
1806 fprintf (stdout
, "\n");
1807 for (i
= 0; i
< t
->operands
; i
++)
1809 fprintf (stdout
, " #%d type ", i
+ 1);
1810 pt (t
->operand_types
[i
]);
1811 fprintf (stdout
, "\n");
1818 fprintf (stdout
, " operation %d\n", e
->X_op
);
1819 fprintf (stdout
, " add_number %ld (%lx)\n",
1820 (long) e
->X_add_number
, (long) e
->X_add_number
);
1821 if (e
->X_add_symbol
)
1823 fprintf (stdout
, " add_symbol ");
1824 ps (e
->X_add_symbol
);
1825 fprintf (stdout
, "\n");
1829 fprintf (stdout
, " op_symbol ");
1830 ps (e
->X_op_symbol
);
1831 fprintf (stdout
, "\n");
1838 fprintf (stdout
, "%s type %s%s",
1840 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1841 segment_name (S_GET_SEGMENT (s
)));
1844 static struct type_name
1846 i386_operand_type mask
;
1849 const type_names
[] =
1851 { OPERAND_TYPE_REG8
, "r8" },
1852 { OPERAND_TYPE_REG16
, "r16" },
1853 { OPERAND_TYPE_REG32
, "r32" },
1854 { OPERAND_TYPE_REG64
, "r64" },
1855 { OPERAND_TYPE_IMM8
, "i8" },
1856 { OPERAND_TYPE_IMM8
, "i8s" },
1857 { OPERAND_TYPE_IMM16
, "i16" },
1858 { OPERAND_TYPE_IMM32
, "i32" },
1859 { OPERAND_TYPE_IMM32S
, "i32s" },
1860 { OPERAND_TYPE_IMM64
, "i64" },
1861 { OPERAND_TYPE_IMM1
, "i1" },
1862 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1863 { OPERAND_TYPE_DISP8
, "d8" },
1864 { OPERAND_TYPE_DISP16
, "d16" },
1865 { OPERAND_TYPE_DISP32
, "d32" },
1866 { OPERAND_TYPE_DISP32S
, "d32s" },
1867 { OPERAND_TYPE_DISP64
, "d64" },
1868 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1869 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1870 { OPERAND_TYPE_CONTROL
, "control reg" },
1871 { OPERAND_TYPE_TEST
, "test reg" },
1872 { OPERAND_TYPE_DEBUG
, "debug reg" },
1873 { OPERAND_TYPE_FLOATREG
, "FReg" },
1874 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1875 { OPERAND_TYPE_SREG2
, "SReg2" },
1876 { OPERAND_TYPE_SREG3
, "SReg3" },
1877 { OPERAND_TYPE_ACC
, "Acc" },
1878 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1879 { OPERAND_TYPE_REGMMX
, "rMMX" },
1880 { OPERAND_TYPE_REGXMM
, "rXMM" },
1881 { OPERAND_TYPE_ESSEG
, "es" },
1885 pt (i386_operand_type t
)
1888 i386_operand_type a
;
1890 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1892 a
= operand_type_and (t
, type_names
[j
].mask
);
1893 if (!UINTS_ALL_ZERO (a
))
1894 fprintf (stdout
, "%s, ", type_names
[j
].name
);
1899 #endif /* DEBUG386 */
1901 static bfd_reloc_code_real_type
1902 reloc (unsigned int size
,
1905 bfd_reloc_code_real_type other
)
1907 if (other
!= NO_RELOC
)
1909 reloc_howto_type
*reloc
;
1914 case BFD_RELOC_X86_64_GOT32
:
1915 return BFD_RELOC_X86_64_GOT64
;
1917 case BFD_RELOC_X86_64_PLTOFF64
:
1918 return BFD_RELOC_X86_64_PLTOFF64
;
1920 case BFD_RELOC_X86_64_GOTPC32
:
1921 other
= BFD_RELOC_X86_64_GOTPC64
;
1923 case BFD_RELOC_X86_64_GOTPCREL
:
1924 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1926 case BFD_RELOC_X86_64_TPOFF32
:
1927 other
= BFD_RELOC_X86_64_TPOFF64
;
1929 case BFD_RELOC_X86_64_DTPOFF32
:
1930 other
= BFD_RELOC_X86_64_DTPOFF64
;
1936 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1937 if (size
== 4 && flag_code
!= CODE_64BIT
)
1940 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1942 as_bad (_("unknown relocation (%u)"), other
);
1943 else if (size
!= bfd_get_reloc_size (reloc
))
1944 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1945 bfd_get_reloc_size (reloc
),
1947 else if (pcrel
&& !reloc
->pc_relative
)
1948 as_bad (_("non-pc-relative relocation for pc-relative field"));
1949 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1951 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1953 as_bad (_("relocated field and relocation type differ in signedness"));
1962 as_bad (_("there are no unsigned pc-relative relocations"));
1965 case 1: return BFD_RELOC_8_PCREL
;
1966 case 2: return BFD_RELOC_16_PCREL
;
1967 case 4: return BFD_RELOC_32_PCREL
;
1968 case 8: return BFD_RELOC_64_PCREL
;
1970 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1977 case 4: return BFD_RELOC_X86_64_32S
;
1982 case 1: return BFD_RELOC_8
;
1983 case 2: return BFD_RELOC_16
;
1984 case 4: return BFD_RELOC_32
;
1985 case 8: return BFD_RELOC_64
;
1987 as_bad (_("cannot do %s %u byte relocation"),
1988 sign
> 0 ? "signed" : "unsigned", size
);
1992 return BFD_RELOC_NONE
;
1995 /* Here we decide which fixups can be adjusted to make them relative to
1996 the beginning of the section instead of the symbol. Basically we need
1997 to make sure that the dynamic relocations are done correctly, so in
1998 some cases we force the original symbol to be used. */
2001 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2007 /* Don't adjust pc-relative references to merge sections in 64-bit
2009 if (use_rela_relocations
2010 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2014 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2015 and changed later by validate_fix. */
2016 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2017 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2020 /* adjust_reloc_syms doesn't know about the GOT. */
2021 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2022 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2023 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2024 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2025 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2026 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2027 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2028 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2029 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2030 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2031 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2032 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2034 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2035 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2036 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2037 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2038 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2039 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2040 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2041 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2047 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2048 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2055 intel_float_operand (const char *mnemonic
)
2057 /* Note that the value returned is meaningful only for opcodes with (memory)
2058 operands, hence the code here is free to improperly handle opcodes that
2059 have no operands (for better performance and smaller code). */
2061 if (mnemonic
[0] != 'f')
2062 return 0; /* non-math */
2064 switch (mnemonic
[1])
2066 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2067 the fs segment override prefix not currently handled because no
2068 call path can make opcodes without operands get here */
2070 return 2 /* integer op */;
2072 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2073 return 3; /* fldcw/fldenv */
2076 if (mnemonic
[2] != 'o' /* fnop */)
2077 return 3; /* non-waiting control op */
2080 if (mnemonic
[2] == 's')
2081 return 3; /* frstor/frstpm */
2084 if (mnemonic
[2] == 'a')
2085 return 3; /* fsave */
2086 if (mnemonic
[2] == 't')
2088 switch (mnemonic
[3])
2090 case 'c': /* fstcw */
2091 case 'd': /* fstdw */
2092 case 'e': /* fstenv */
2093 case 's': /* fsts[gw] */
2099 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2100 return 0; /* fxsave/fxrstor are not really math ops */
2107 /* This is the guts of the machine-dependent assembler. LINE points to a
2108 machine dependent instruction. This function is supposed to emit
2109 the frags/bytes it assembles to. */
2116 char mnemonic
[MAX_MNEM_SIZE
];
2118 /* Initialize globals. */
2119 memset (&i
, '\0', sizeof (i
));
2120 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2121 i
.reloc
[j
] = NO_RELOC
;
2122 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2123 memset (im_expressions
, '\0', sizeof (im_expressions
));
2124 save_stack_p
= save_stack
;
2126 /* First parse an instruction mnemonic & call i386_operand for the operands.
2127 We assume that the scrubber has arranged it so that line[0] is the valid
2128 start of a (possibly prefixed) mnemonic. */
2130 line
= parse_insn (line
, mnemonic
);
2134 line
= parse_operands (line
, mnemonic
);
2138 /* Now we've parsed the mnemonic into a set of templates, and have the
2139 operands at hand. */
2141 /* All intel opcodes have reversed operands except for "bound" and
2142 "enter". We also don't reverse intersegment "jmp" and "call"
2143 instructions with 2 immediate operands so that the immediate segment
2144 precedes the offset, as it does when in AT&T mode. */
2147 && (strcmp (mnemonic
, "bound") != 0)
2148 && (strcmp (mnemonic
, "invlpga") != 0)
2149 && !(operand_type_check (i
.types
[0], imm
)
2150 && operand_type_check (i
.types
[1], imm
)))
2153 /* The order of the immediates should be reversed
2154 for 2 immediates extrq and insertq instructions */
2155 if (i
.imm_operands
== 2
2156 && (strcmp (mnemonic
, "extrq") == 0
2157 || strcmp (mnemonic
, "insertq") == 0))
2158 swap_2_operands (0, 1);
2163 /* Don't optimize displacement for movabs since it only takes 64bit
2166 && (flag_code
!= CODE_64BIT
2167 || strcmp (mnemonic
, "movabs") != 0))
2170 /* Next, we find a template that matches the given insn,
2171 making sure the overlap of the given operands types is consistent
2172 with the template operand types. */
2174 if (!match_template ())
2179 /* Zap movzx and movsx suffix. The suffix may have been set from
2180 "word ptr" or "byte ptr" on the source operand, but we'll use
2181 the suffix later to choose the destination register. */
2182 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2184 if (i
.reg_operands
< 2
2186 && (!i
.tm
.opcode_modifier
.no_bsuf
2187 || !i
.tm
.opcode_modifier
.no_wsuf
2188 || !i
.tm
.opcode_modifier
.no_lsuf
2189 || !i
.tm
.opcode_modifier
.no_ssuf
2190 || !i
.tm
.opcode_modifier
.no_ldsuf
2191 || !i
.tm
.opcode_modifier
.no_qsuf
))
2192 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2198 if (i
.tm
.opcode_modifier
.fwait
)
2199 if (!add_prefix (FWAIT_OPCODE
))
2202 /* Check string instruction segment overrides. */
2203 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2205 if (!check_string ())
2209 if (!process_suffix ())
2212 /* Make still unresolved immediate matches conform to size of immediate
2213 given in i.suffix. */
2214 if (!finalize_imm ())
2217 if (i
.types
[0].bitfield
.imm1
)
2218 i
.imm_operands
= 0; /* kludge for shift insns. */
2220 for (j
= 0; j
< 3; j
++)
2221 if (i
.types
[j
].bitfield
.inoutportreg
2222 || i
.types
[j
].bitfield
.shiftcount
2223 || i
.types
[j
].bitfield
.acc
2224 || i
.types
[j
].bitfield
.floatacc
)
2227 if (i
.tm
.opcode_modifier
.immext
)
2231 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2233 /* Streaming SIMD extensions 3 Instructions have the fixed
2234 operands with an opcode suffix which is coded in the same
2235 place as an 8-bit immediate field would be. Here we check
2236 those operands and remove them afterwards. */
2239 for (x
= 0; x
< i
.operands
; x
++)
2240 if (i
.op
[x
].regs
->reg_num
!= x
)
2241 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2243 i
.op
[x
].regs
->reg_name
,
2249 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2250 opcode suffix which is coded in the same place as an 8-bit
2251 immediate field would be. Here we fake an 8-bit immediate
2252 operand from the opcode suffix stored in tm.extension_opcode.
2253 SSE5 also uses this encoding, for some of its 3 argument
2256 assert (i
.imm_operands
== 0
2258 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2259 && i
.operands
<= 3)));
2261 exp
= &im_expressions
[i
.imm_operands
++];
2262 i
.op
[i
.operands
].imms
= exp
;
2263 UINTS_CLEAR (i
.types
[i
.operands
]);
2264 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2266 exp
->X_op
= O_constant
;
2267 exp
->X_add_number
= i
.tm
.extension_opcode
;
2268 i
.tm
.extension_opcode
= None
;
2271 /* For insns with operands there are more diddles to do to the opcode. */
2274 if (!process_operands ())
2277 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2279 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2280 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2283 /* Handle conversion of 'int $3' --> special int3 insn. */
2284 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2286 i
.tm
.base_opcode
= INT3_OPCODE
;
2290 if ((i
.tm
.opcode_modifier
.jump
2291 || i
.tm
.opcode_modifier
.jumpbyte
2292 || i
.tm
.opcode_modifier
.jumpdword
)
2293 && i
.op
[0].disps
->X_op
== O_constant
)
2295 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2296 the absolute address given by the constant. Since ix86 jumps and
2297 calls are pc relative, we need to generate a reloc. */
2298 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2299 i
.op
[0].disps
->X_op
= O_symbol
;
2302 if (i
.tm
.opcode_modifier
.rex64
)
2305 /* For 8 bit registers we need an empty rex prefix. Also if the
2306 instruction already has a prefix, we need to convert old
2307 registers to new ones. */
2309 if ((i
.types
[0].bitfield
.reg8
2310 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2311 || (i
.types
[1].bitfield
.reg8
2312 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2313 || ((i
.types
[0].bitfield
.reg8
2314 || i
.types
[1].bitfield
.reg8
)
2319 i
.rex
|= REX_OPCODE
;
2320 for (x
= 0; x
< 2; x
++)
2322 /* Look for 8 bit operand that uses old registers. */
2323 if (i
.types
[x
].bitfield
.reg8
2324 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2326 /* In case it is "hi" register, give up. */
2327 if (i
.op
[x
].regs
->reg_num
> 3)
2328 as_bad (_("can't encode register '%s%s' in an "
2329 "instruction requiring REX prefix."),
2330 register_prefix
, i
.op
[x
].regs
->reg_name
);
2332 /* Otherwise it is equivalent to the extended register.
2333 Since the encoding doesn't change this is merely
2334 cosmetic cleanup for debug output. */
2336 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2341 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2343 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2348 else if (i
.rex
!= 0)
2349 add_prefix (REX_OPCODE
| i
.rex
);
2351 /* We are ready to output the insn. */
2356 parse_insn (char *line
, char *mnemonic
)
2359 char *token_start
= l
;
2364 /* Non-zero if we found a prefix only acceptable with string insns. */
2365 const char *expecting_string_instruction
= NULL
;
2370 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2373 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2375 as_bad (_("no such instruction: `%s'"), token_start
);
2380 if (!is_space_char (*l
)
2381 && *l
!= END_OF_INSN
2383 || (*l
!= PREFIX_SEPARATOR
2386 as_bad (_("invalid character %s in mnemonic"),
2387 output_invalid (*l
));
2390 if (token_start
== l
)
2392 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2393 as_bad (_("expecting prefix; got nothing"));
2395 as_bad (_("expecting mnemonic; got nothing"));
2399 /* Look up instruction (or prefix) via hash table. */
2400 current_templates
= hash_find (op_hash
, mnemonic
);
2402 if (*l
!= END_OF_INSN
2403 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2404 && current_templates
2405 && current_templates
->start
->opcode_modifier
.isprefix
)
2407 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2409 as_bad ((flag_code
!= CODE_64BIT
2410 ? _("`%s' is only supported in 64-bit mode")
2411 : _("`%s' is not supported in 64-bit mode")),
2412 current_templates
->start
->name
);
2415 /* If we are in 16-bit mode, do not allow addr16 or data16.
2416 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2417 if ((current_templates
->start
->opcode_modifier
.size16
2418 || current_templates
->start
->opcode_modifier
.size32
)
2419 && flag_code
!= CODE_64BIT
2420 && (current_templates
->start
->opcode_modifier
.size32
2421 ^ (flag_code
== CODE_16BIT
)))
2423 as_bad (_("redundant %s prefix"),
2424 current_templates
->start
->name
);
2427 /* Add prefix, checking for repeated prefixes. */
2428 switch (add_prefix (current_templates
->start
->base_opcode
))
2433 expecting_string_instruction
= current_templates
->start
->name
;
2436 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2443 if (!current_templates
)
2445 /* See if we can get a match by trimming off a suffix. */
2448 case WORD_MNEM_SUFFIX
:
2449 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2450 i
.suffix
= SHORT_MNEM_SUFFIX
;
2452 case BYTE_MNEM_SUFFIX
:
2453 case QWORD_MNEM_SUFFIX
:
2454 i
.suffix
= mnem_p
[-1];
2456 current_templates
= hash_find (op_hash
, mnemonic
);
2458 case SHORT_MNEM_SUFFIX
:
2459 case LONG_MNEM_SUFFIX
:
2462 i
.suffix
= mnem_p
[-1];
2464 current_templates
= hash_find (op_hash
, mnemonic
);
2472 if (intel_float_operand (mnemonic
) == 1)
2473 i
.suffix
= SHORT_MNEM_SUFFIX
;
2475 i
.suffix
= LONG_MNEM_SUFFIX
;
2477 current_templates
= hash_find (op_hash
, mnemonic
);
2481 if (!current_templates
)
2483 as_bad (_("no such instruction: `%s'"), token_start
);
2488 if (current_templates
->start
->opcode_modifier
.jump
2489 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2491 /* Check for a branch hint. We allow ",pt" and ",pn" for
2492 predict taken and predict not taken respectively.
2493 I'm not sure that branch hints actually do anything on loop
2494 and jcxz insns (JumpByte) for current Pentium4 chips. They
2495 may work in the future and it doesn't hurt to accept them
2497 if (l
[0] == ',' && l
[1] == 'p')
2501 if (!add_prefix (DS_PREFIX_OPCODE
))
2505 else if (l
[2] == 'n')
2507 if (!add_prefix (CS_PREFIX_OPCODE
))
2513 /* Any other comma loses. */
2516 as_bad (_("invalid character %s in mnemonic"),
2517 output_invalid (*l
));
2521 /* Check if instruction is supported on specified architecture. */
2523 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2525 supported
|= cpu_flags_match (t
->cpu_flags
);
2530 if (!(supported
& 2))
2532 as_bad (flag_code
== CODE_64BIT
2533 ? _("`%s' is not supported in 64-bit mode")
2534 : _("`%s' is only supported in 64-bit mode"),
2535 current_templates
->start
->name
);
2538 if (!(supported
& 1))
2540 as_bad (_("`%s' is not supported on `%s%s'"),
2541 current_templates
->start
->name
, cpu_arch_name
,
2542 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2547 if (!cpu_arch_flags
.bitfield
.cpui386
2548 && (flag_code
!= CODE_16BIT
))
2550 as_warn (_("use .code16 to ensure correct addressing mode"));
2553 /* Check for rep/repne without a string instruction. */
2554 if (expecting_string_instruction
)
2556 static templates override
;
2558 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2559 if (t
->opcode_modifier
.isstring
)
2561 if (t
>= current_templates
->end
)
2563 as_bad (_("expecting string instruction after `%s'"),
2564 expecting_string_instruction
);
2567 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2568 if (!t
->opcode_modifier
.isstring
)
2571 current_templates
= &override
;
2578 parse_operands (char *l
, const char *mnemonic
)
2582 /* 1 if operand is pending after ','. */
2583 unsigned int expecting_operand
= 0;
2585 /* Non-zero if operand parens not balanced. */
2586 unsigned int paren_not_balanced
;
2588 while (*l
!= END_OF_INSN
)
2590 /* Skip optional white space before operand. */
2591 if (is_space_char (*l
))
2593 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2595 as_bad (_("invalid character %s before operand %d"),
2596 output_invalid (*l
),
2600 token_start
= l
; /* after white space */
2601 paren_not_balanced
= 0;
2602 while (paren_not_balanced
|| *l
!= ',')
2604 if (*l
== END_OF_INSN
)
2606 if (paren_not_balanced
)
2609 as_bad (_("unbalanced parenthesis in operand %d."),
2612 as_bad (_("unbalanced brackets in operand %d."),
2617 break; /* we are done */
2619 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2621 as_bad (_("invalid character %s in operand %d"),
2622 output_invalid (*l
),
2629 ++paren_not_balanced
;
2631 --paren_not_balanced
;
2636 ++paren_not_balanced
;
2638 --paren_not_balanced
;
2642 if (l
!= token_start
)
2643 { /* Yes, we've read in another operand. */
2644 unsigned int operand_ok
;
2645 this_operand
= i
.operands
++;
2646 i
.types
[this_operand
].bitfield
.unspecified
= 1;
2647 if (i
.operands
> MAX_OPERANDS
)
2649 as_bad (_("spurious operands; (%d operands/instruction max)"),
2653 /* Now parse operand adding info to 'i' as we go along. */
2654 END_STRING_AND_SAVE (l
);
2658 i386_intel_operand (token_start
,
2659 intel_float_operand (mnemonic
));
2661 operand_ok
= i386_att_operand (token_start
);
2663 RESTORE_END_STRING (l
);
2669 if (expecting_operand
)
2671 expecting_operand_after_comma
:
2672 as_bad (_("expecting operand after ','; got nothing"));
2677 as_bad (_("expecting operand before ','; got nothing"));
2682 /* Now *l must be either ',' or END_OF_INSN. */
2685 if (*++l
== END_OF_INSN
)
2687 /* Just skip it, if it's \n complain. */
2688 goto expecting_operand_after_comma
;
2690 expecting_operand
= 1;
2697 swap_2_operands (int xchg1
, int xchg2
)
2699 union i386_op temp_op
;
2700 i386_operand_type temp_type
;
2701 enum bfd_reloc_code_real temp_reloc
;
2703 temp_type
= i
.types
[xchg2
];
2704 i
.types
[xchg2
] = i
.types
[xchg1
];
2705 i
.types
[xchg1
] = temp_type
;
2706 temp_op
= i
.op
[xchg2
];
2707 i
.op
[xchg2
] = i
.op
[xchg1
];
2708 i
.op
[xchg1
] = temp_op
;
2709 temp_reloc
= i
.reloc
[xchg2
];
2710 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2711 i
.reloc
[xchg1
] = temp_reloc
;
2715 swap_operands (void)
2720 swap_2_operands (1, i
.operands
- 2);
2723 swap_2_operands (0, i
.operands
- 1);
2729 if (i
.mem_operands
== 2)
2731 const seg_entry
*temp_seg
;
2732 temp_seg
= i
.seg
[0];
2733 i
.seg
[0] = i
.seg
[1];
2734 i
.seg
[1] = temp_seg
;
2738 /* Try to ensure constant immediates are represented in the smallest
2743 char guess_suffix
= 0;
2747 guess_suffix
= i
.suffix
;
2748 else if (i
.reg_operands
)
2750 /* Figure out a suffix from the last register operand specified.
2751 We can't do this properly yet, ie. excluding InOutPortReg,
2752 but the following works for instructions with immediates.
2753 In any case, we can't set i.suffix yet. */
2754 for (op
= i
.operands
; --op
>= 0;)
2755 if (i
.types
[op
].bitfield
.reg8
)
2757 guess_suffix
= BYTE_MNEM_SUFFIX
;
2760 else if (i
.types
[op
].bitfield
.reg16
)
2762 guess_suffix
= WORD_MNEM_SUFFIX
;
2765 else if (i
.types
[op
].bitfield
.reg32
)
2767 guess_suffix
= LONG_MNEM_SUFFIX
;
2770 else if (i
.types
[op
].bitfield
.reg64
)
2772 guess_suffix
= QWORD_MNEM_SUFFIX
;
2776 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2777 guess_suffix
= WORD_MNEM_SUFFIX
;
2779 for (op
= i
.operands
; --op
>= 0;)
2780 if (operand_type_check (i
.types
[op
], imm
))
2782 switch (i
.op
[op
].imms
->X_op
)
2785 /* If a suffix is given, this operand may be shortened. */
2786 switch (guess_suffix
)
2788 case LONG_MNEM_SUFFIX
:
2789 i
.types
[op
].bitfield
.imm32
= 1;
2790 i
.types
[op
].bitfield
.imm64
= 1;
2792 case WORD_MNEM_SUFFIX
:
2793 i
.types
[op
].bitfield
.imm16
= 1;
2794 i
.types
[op
].bitfield
.imm32
= 1;
2795 i
.types
[op
].bitfield
.imm32s
= 1;
2796 i
.types
[op
].bitfield
.imm64
= 1;
2798 case BYTE_MNEM_SUFFIX
:
2799 i
.types
[op
].bitfield
.imm8
= 1;
2800 i
.types
[op
].bitfield
.imm8s
= 1;
2801 i
.types
[op
].bitfield
.imm16
= 1;
2802 i
.types
[op
].bitfield
.imm32
= 1;
2803 i
.types
[op
].bitfield
.imm32s
= 1;
2804 i
.types
[op
].bitfield
.imm64
= 1;
2808 /* If this operand is at most 16 bits, convert it
2809 to a signed 16 bit number before trying to see
2810 whether it will fit in an even smaller size.
2811 This allows a 16-bit operand such as $0xffe0 to
2812 be recognised as within Imm8S range. */
2813 if ((i
.types
[op
].bitfield
.imm16
)
2814 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2816 i
.op
[op
].imms
->X_add_number
=
2817 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2819 if ((i
.types
[op
].bitfield
.imm32
)
2820 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2823 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2824 ^ ((offsetT
) 1 << 31))
2825 - ((offsetT
) 1 << 31));
2828 = operand_type_or (i
.types
[op
],
2829 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2831 /* We must avoid matching of Imm32 templates when 64bit
2832 only immediate is available. */
2833 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2834 i
.types
[op
].bitfield
.imm32
= 0;
2841 /* Symbols and expressions. */
2843 /* Convert symbolic operand to proper sizes for matching, but don't
2844 prevent matching a set of insns that only supports sizes other
2845 than those matching the insn suffix. */
2847 i386_operand_type mask
, allowed
;
2851 UINTS_CLEAR (allowed
);
2853 for (t
= current_templates
->start
;
2854 t
< current_templates
->end
;
2856 allowed
= operand_type_or (allowed
,
2857 t
->operand_types
[op
]);
2858 switch (guess_suffix
)
2860 case QWORD_MNEM_SUFFIX
:
2861 mask
.bitfield
.imm64
= 1;
2862 mask
.bitfield
.imm32s
= 1;
2864 case LONG_MNEM_SUFFIX
:
2865 mask
.bitfield
.imm32
= 1;
2867 case WORD_MNEM_SUFFIX
:
2868 mask
.bitfield
.imm16
= 1;
2870 case BYTE_MNEM_SUFFIX
:
2871 mask
.bitfield
.imm8
= 1;
2876 allowed
= operand_type_and (mask
, allowed
);
2877 if (!UINTS_ALL_ZERO (allowed
))
2878 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2885 /* Try to use the smallest displacement type too. */
2887 optimize_disp (void)
2891 for (op
= i
.operands
; --op
>= 0;)
2892 if (operand_type_check (i
.types
[op
], disp
))
2894 if (i
.op
[op
].disps
->X_op
== O_constant
)
2896 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2898 if (i
.types
[op
].bitfield
.disp16
2899 && (disp
& ~(offsetT
) 0xffff) == 0)
2901 /* If this operand is at most 16 bits, convert
2902 to a signed 16 bit number and don't use 64bit
2904 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2905 i
.types
[op
].bitfield
.disp64
= 0;
2907 if (i
.types
[op
].bitfield
.disp32
2908 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2910 /* If this operand is at most 32 bits, convert
2911 to a signed 32 bit number and don't use 64bit
2913 disp
&= (((offsetT
) 2 << 31) - 1);
2914 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2915 i
.types
[op
].bitfield
.disp64
= 0;
2917 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
2919 i
.types
[op
].bitfield
.disp8
= 0;
2920 i
.types
[op
].bitfield
.disp16
= 0;
2921 i
.types
[op
].bitfield
.disp32
= 0;
2922 i
.types
[op
].bitfield
.disp32s
= 0;
2923 i
.types
[op
].bitfield
.disp64
= 0;
2927 else if (flag_code
== CODE_64BIT
)
2929 if (fits_in_signed_long (disp
))
2931 i
.types
[op
].bitfield
.disp64
= 0;
2932 i
.types
[op
].bitfield
.disp32s
= 1;
2934 if (fits_in_unsigned_long (disp
))
2935 i
.types
[op
].bitfield
.disp32
= 1;
2937 if ((i
.types
[op
].bitfield
.disp32
2938 || i
.types
[op
].bitfield
.disp32s
2939 || i
.types
[op
].bitfield
.disp16
)
2940 && fits_in_signed_byte (disp
))
2941 i
.types
[op
].bitfield
.disp8
= 1;
2943 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2944 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2946 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2947 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2948 i
.types
[op
].bitfield
.disp8
= 0;
2949 i
.types
[op
].bitfield
.disp16
= 0;
2950 i
.types
[op
].bitfield
.disp32
= 0;
2951 i
.types
[op
].bitfield
.disp32s
= 0;
2952 i
.types
[op
].bitfield
.disp64
= 0;
2955 /* We only support 64bit displacement on constants. */
2956 i
.types
[op
].bitfield
.disp64
= 0;
2961 match_template (void)
2963 /* Points to template once we've found it. */
2965 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
2966 unsigned int found_reverse_match
;
2967 i386_opcode_modifier suffix_check
;
2968 i386_operand_type operand_types
[MAX_OPERANDS
];
2969 int addr_prefix_disp
;
2971 unsigned int found_cpu_match
;
2972 unsigned int check_register
;
2973 unsigned int size_match
;
2975 #if MAX_OPERANDS != 4
2976 # error "MAX_OPERANDS must be 4."
2979 found_reverse_match
= 0;
2980 addr_prefix_disp
= -1;
2982 memset (&suffix_check
, 0, sizeof (suffix_check
));
2983 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2984 suffix_check
.no_bsuf
= 1;
2985 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2986 suffix_check
.no_wsuf
= 1;
2987 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
2988 suffix_check
.no_ssuf
= 1;
2989 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2990 suffix_check
.no_lsuf
= 1;
2991 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2992 suffix_check
.no_qsuf
= 1;
2993 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
2994 suffix_check
.no_ldsuf
= 1;
2996 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2998 addr_prefix_disp
= -1;
3000 /* Must have right number of operands. */
3001 if (i
.operands
!= t
->operands
)
3004 /* Check processor support. */
3005 found_cpu_match
= cpu_flags_match (t
->cpu_flags
) == 3;
3006 if (!found_cpu_match
)
3009 /* Check old gcc support. */
3010 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3013 /* Check AT&T mnemonic. */
3014 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3017 /* Check Intel syntax. */
3018 if (intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3021 /* Check the suffix, except for some instructions in intel mode. */
3022 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3023 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3024 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3025 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3026 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3027 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3028 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3032 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3034 operand_types
[j
] = t
->operand_types
[j
];
3036 /* Check memory and accumulator operand size. We check
3037 operand_types for accumulator, and both operand_types
3038 and i.types for memory. */
3040 && !operand_types
[j
].bitfield
.anysize
3041 && ((operand_types
[j
].bitfield
.acc
3042 && ((i
.types
[j
].bitfield
.byte
3043 && !operand_types
[j
].bitfield
.byte
)
3044 || (i
.types
[j
].bitfield
.word
3045 && !operand_types
[j
].bitfield
.word
)
3046 || (i
.types
[j
].bitfield
.dword
3047 && !operand_types
[j
].bitfield
.dword
)
3048 || (i
.types
[j
].bitfield
.qword
3049 && !operand_types
[j
].bitfield
.qword
)))
3050 || (operand_types
[j
].bitfield
.baseindex
3051 && i
.types
[j
].bitfield
.baseindex
3052 && ((i
.types
[j
].bitfield
.unspecified
3053 && !operand_types
[j
].bitfield
.unspecified
)
3054 || (i
.types
[j
].bitfield
.byte
3055 && !operand_types
[j
].bitfield
.byte
)
3056 || (i
.types
[j
].bitfield
.word
3057 && !operand_types
[j
].bitfield
.word
)
3058 || (i
.types
[j
].bitfield
.dword
3059 && !operand_types
[j
].bitfield
.dword
)
3060 || (i
.types
[j
].bitfield
.fword
3061 && !operand_types
[j
].bitfield
.fword
)
3062 || (i
.types
[j
].bitfield
.qword
3063 && !operand_types
[j
].bitfield
.qword
)
3064 || (i
.types
[j
].bitfield
.tbyte
3065 && !operand_types
[j
].bitfield
.tbyte
)
3066 || (i
.types
[j
].bitfield
.xmmword
3067 && !operand_types
[j
].bitfield
.xmmword
)))))
3077 /* In general, don't allow 64-bit operands in 32-bit mode. */
3078 if (i
.suffix
== QWORD_MNEM_SUFFIX
3079 && flag_code
!= CODE_64BIT
3081 ? (!t
->opcode_modifier
.ignoresize
3082 && !intel_float_operand (t
->name
))
3083 : intel_float_operand (t
->name
) != 2)
3084 && ((!operand_types
[0].bitfield
.regmmx
3085 && !operand_types
[0].bitfield
.regxmm
)
3086 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3087 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3088 && (t
->base_opcode
!= 0x0fc7
3089 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3092 /* Do not verify operands when there are none. */
3096 /* We've found a match; break out of loop. */
3100 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3101 into Disp32/Disp16/Disp32 operand. */
3102 if (i
.prefix
[ADDR_PREFIX
] != 0)
3104 /* There should be only one Disp operand. */
3108 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3110 if (operand_types
[j
].bitfield
.disp16
)
3112 addr_prefix_disp
= j
;
3113 operand_types
[j
].bitfield
.disp32
= 1;
3114 operand_types
[j
].bitfield
.disp16
= 0;
3120 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3122 if (operand_types
[j
].bitfield
.disp32
)
3124 addr_prefix_disp
= j
;
3125 operand_types
[j
].bitfield
.disp32
= 0;
3126 operand_types
[j
].bitfield
.disp16
= 1;
3132 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3134 if (operand_types
[j
].bitfield
.disp64
)
3136 addr_prefix_disp
= j
;
3137 operand_types
[j
].bitfield
.disp64
= 0;
3138 operand_types
[j
].bitfield
.disp32
= 1;
3146 /* We check register size only if size of operands can be
3147 encoded the canonical way. */
3148 check_register
= t
->opcode_modifier
.w
;
3149 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3150 switch (t
->operands
)
3153 if (!operand_type_match (overlap0
, i
.types
[0]))
3157 /* xchg %eax, %eax is a special case. It is an aliase for nop
3158 only in 32bit mode and we can use opcode 0x90. In 64bit
3159 mode, we can't use 0x90 for xchg %eax, %eax since it should
3160 zero-extend %eax to %rax. */
3161 if (flag_code
== CODE_64BIT
3162 && t
->base_opcode
== 0x90
3163 && UINTS_EQUAL (i
.types
[0], acc32
)
3164 && UINTS_EQUAL (i
.types
[1], acc32
))
3168 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3169 if (!operand_type_match (overlap0
, i
.types
[0])
3170 || !operand_type_match (overlap1
, i
.types
[1])
3172 && !operand_type_register_match (overlap0
, i
.types
[0],
3174 overlap1
, i
.types
[1],
3177 /* Check if other direction is valid ... */
3178 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3181 /* Try reversing direction of operands. */
3182 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3183 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3184 if (!operand_type_match (overlap0
, i
.types
[0])
3185 || !operand_type_match (overlap1
, i
.types
[1])
3187 && !operand_type_register_match (overlap0
,
3194 /* Does not match either direction. */
3197 /* found_reverse_match holds which of D or FloatDR
3199 if (t
->opcode_modifier
.d
)
3200 found_reverse_match
= Opcode_D
;
3201 else if (t
->opcode_modifier
.floatd
)
3202 found_reverse_match
= Opcode_FloatD
;
3204 found_reverse_match
= 0;
3205 if (t
->opcode_modifier
.floatr
)
3206 found_reverse_match
|= Opcode_FloatR
;
3210 /* Found a forward 2 operand match here. */
3211 switch (t
->operands
)
3214 overlap3
= operand_type_and (i
.types
[3],
3217 overlap2
= operand_type_and (i
.types
[2],
3222 switch (t
->operands
)
3225 if (!operand_type_match (overlap3
, i
.types
[3])
3227 && !operand_type_register_match (overlap2
,
3235 /* Here we make use of the fact that there are no
3236 reverse match 3 operand instructions, and all 3
3237 operand instructions only need to be checked for
3238 register consistency between operands 2 and 3. */
3239 if (!operand_type_match (overlap2
, i
.types
[2])
3241 && !operand_type_register_match (overlap1
,
3251 /* Found either forward/reverse 2, 3 or 4 operand match here:
3252 slip through to break. */
3254 if (!found_cpu_match
)
3256 found_reverse_match
= 0;
3259 /* We've found a match; break out of loop. */
3263 if (t
== current_templates
->end
)
3265 /* We found no match. */
3266 as_bad (_("suffix or operands invalid for `%s'"),
3267 current_templates
->start
->name
);
3271 if (!quiet_warnings
)
3274 && (i
.types
[0].bitfield
.jumpabsolute
3275 != operand_types
[0].bitfield
.jumpabsolute
))
3277 as_warn (_("indirect %s without `*'"), t
->name
);
3280 if (t
->opcode_modifier
.isprefix
3281 && t
->opcode_modifier
.ignoresize
)
3283 /* Warn them that a data or address size prefix doesn't
3284 affect assembly of the next line of code. */
3285 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3289 /* Copy the template we found. */
3292 if (addr_prefix_disp
!= -1)
3293 i
.tm
.operand_types
[addr_prefix_disp
]
3294 = operand_types
[addr_prefix_disp
];
3296 if (found_reverse_match
)
3298 /* If we found a reverse match we must alter the opcode
3299 direction bit. found_reverse_match holds bits to change
3300 (different for int & float insns). */
3302 i
.tm
.base_opcode
^= found_reverse_match
;
3304 i
.tm
.operand_types
[0] = operand_types
[1];
3305 i
.tm
.operand_types
[1] = operand_types
[0];
3314 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3315 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3317 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3319 as_bad (_("`%s' operand %d must use `%%es' segment"),
3324 /* There's only ever one segment override allowed per instruction.
3325 This instruction possibly has a legal segment override on the
3326 second operand, so copy the segment to where non-string
3327 instructions store it, allowing common code. */
3328 i
.seg
[0] = i
.seg
[1];
3330 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3332 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3334 as_bad (_("`%s' operand %d must use `%%es' segment"),
3344 process_suffix (void)
3346 /* If matched instruction specifies an explicit instruction mnemonic
3348 if (i
.tm
.opcode_modifier
.size16
)
3349 i
.suffix
= WORD_MNEM_SUFFIX
;
3350 else if (i
.tm
.opcode_modifier
.size32
)
3351 i
.suffix
= LONG_MNEM_SUFFIX
;
3352 else if (i
.tm
.opcode_modifier
.size64
)
3353 i
.suffix
= QWORD_MNEM_SUFFIX
;
3354 else if (i
.reg_operands
)
3356 /* If there's no instruction mnemonic suffix we try to invent one
3357 based on register operands. */
3360 /* We take i.suffix from the last register operand specified,
3361 Destination register type is more significant than source
3362 register type. crc32 in SSE4.2 prefers source register
3364 if (i
.tm
.base_opcode
== 0xf20f38f1)
3366 if (i
.types
[0].bitfield
.reg16
)
3367 i
.suffix
= WORD_MNEM_SUFFIX
;
3368 else if (i
.types
[0].bitfield
.reg32
)
3369 i
.suffix
= LONG_MNEM_SUFFIX
;
3370 else if (i
.types
[0].bitfield
.reg64
)
3371 i
.suffix
= QWORD_MNEM_SUFFIX
;
3373 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3375 if (i
.types
[0].bitfield
.reg8
)
3376 i
.suffix
= BYTE_MNEM_SUFFIX
;
3383 if (i
.tm
.base_opcode
== 0xf20f38f1
3384 || i
.tm
.base_opcode
== 0xf20f38f0)
3386 /* We have to know the operand size for crc32. */
3387 as_bad (_("ambiguous memory operand size for `%s`"),
3392 for (op
= i
.operands
; --op
>= 0;)
3393 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3395 if (i
.types
[op
].bitfield
.reg8
)
3397 i
.suffix
= BYTE_MNEM_SUFFIX
;
3400 else if (i
.types
[op
].bitfield
.reg16
)
3402 i
.suffix
= WORD_MNEM_SUFFIX
;
3405 else if (i
.types
[op
].bitfield
.reg32
)
3407 i
.suffix
= LONG_MNEM_SUFFIX
;
3410 else if (i
.types
[op
].bitfield
.reg64
)
3412 i
.suffix
= QWORD_MNEM_SUFFIX
;
3418 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3420 if (!check_byte_reg ())
3423 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3425 if (!check_long_reg ())
3428 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3431 && i
.tm
.opcode_modifier
.ignoresize
3432 && i
.tm
.opcode_modifier
.no_qsuf
)
3434 else if (!check_qword_reg ())
3437 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3439 if (!check_word_reg ())
3442 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
)
3444 /* Skip if the instruction has x suffix. match_template
3445 should check if it is a valid suffix. */
3447 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3448 /* Do nothing if the instruction is going to ignore the prefix. */
3453 else if (i
.tm
.opcode_modifier
.defaultsize
3455 /* exclude fldenv/frstor/fsave/fstenv */
3456 && i
.tm
.opcode_modifier
.no_ssuf
)
3458 i
.suffix
= stackop_size
;
3460 else if (intel_syntax
3462 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3463 || i
.tm
.opcode_modifier
.jumpbyte
3464 || i
.tm
.opcode_modifier
.jumpintersegment
3465 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3466 && i
.tm
.extension_opcode
<= 3)))
3471 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3473 i
.suffix
= QWORD_MNEM_SUFFIX
;
3477 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3478 i
.suffix
= LONG_MNEM_SUFFIX
;
3481 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3482 i
.suffix
= WORD_MNEM_SUFFIX
;
3491 if (i
.tm
.opcode_modifier
.w
)
3493 as_bad (_("no instruction mnemonic suffix given and "
3494 "no register operands; can't size instruction"));
3500 unsigned int suffixes
;
3502 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3503 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3505 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3507 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
3509 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3511 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3514 /* There are more than suffix matches. */
3515 if (i
.tm
.opcode_modifier
.w
3516 || ((suffixes
& (suffixes
- 1))
3517 && !i
.tm
.opcode_modifier
.defaultsize
3518 && !i
.tm
.opcode_modifier
.ignoresize
))
3520 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3526 /* Change the opcode based on the operand size given by i.suffix;
3527 We don't need to change things for byte insns. */
3530 && i
.suffix
!= BYTE_MNEM_SUFFIX
3531 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
)
3533 /* It's not a byte, select word/dword operation. */
3534 if (i
.tm
.opcode_modifier
.w
)
3536 if (i
.tm
.opcode_modifier
.shortform
)
3537 i
.tm
.base_opcode
|= 8;
3539 i
.tm
.base_opcode
|= 1;
3542 /* Now select between word & dword operations via the operand
3543 size prefix, except for instructions that will ignore this
3545 if (i
.tm
.opcode_modifier
.addrprefixop0
)
3547 /* The address size override prefix changes the size of the
3549 if ((flag_code
== CODE_32BIT
3550 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3551 || (flag_code
!= CODE_32BIT
3552 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3553 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3556 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3557 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3558 && !i
.tm
.opcode_modifier
.ignoresize
3559 && !i
.tm
.opcode_modifier
.floatmf
3560 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3561 || (flag_code
== CODE_64BIT
3562 && i
.tm
.opcode_modifier
.jumpbyte
)))
3564 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3566 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3567 prefix
= ADDR_PREFIX_OPCODE
;
3569 if (!add_prefix (prefix
))
3573 /* Set mode64 for an operand. */
3574 if (i
.suffix
== QWORD_MNEM_SUFFIX
3575 && flag_code
== CODE_64BIT
3576 && !i
.tm
.opcode_modifier
.norex64
)
3578 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3579 need rex64. cmpxchg8b is also a special case. */
3580 if (! (i
.operands
== 2
3581 && i
.tm
.base_opcode
== 0x90
3582 && i
.tm
.extension_opcode
== None
3583 && UINTS_EQUAL (i
.types
[0], acc64
)
3584 && UINTS_EQUAL (i
.types
[1], acc64
))
3585 && ! (i
.operands
== 1
3586 && i
.tm
.base_opcode
== 0xfc7
3587 && i
.tm
.extension_opcode
== 1
3588 && !operand_type_check (i
.types
[0], reg
)
3589 && operand_type_check (i
.types
[0], anymem
)))
3593 /* Size floating point instruction. */
3594 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3595 if (i
.tm
.opcode_modifier
.floatmf
)
3596 i
.tm
.base_opcode
^= 4;
3603 check_byte_reg (void)
3607 for (op
= i
.operands
; --op
>= 0;)
3609 /* If this is an eight bit register, it's OK. If it's the 16 or
3610 32 bit version of an eight bit register, we will just use the
3611 low portion, and that's OK too. */
3612 if (i
.types
[op
].bitfield
.reg8
)
3615 /* Don't generate this warning if not needed. */
3616 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
3619 /* crc32 doesn't generate this warning. */
3620 if (i
.tm
.base_opcode
== 0xf20f38f0)
3623 if ((i
.types
[op
].bitfield
.reg16
3624 || i
.types
[op
].bitfield
.reg32
3625 || i
.types
[op
].bitfield
.reg64
)
3626 && i
.op
[op
].regs
->reg_num
< 4)
3628 /* Prohibit these changes in the 64bit mode, since the
3629 lowering is more complicated. */
3630 if (flag_code
== CODE_64BIT
3631 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3633 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3634 register_prefix
, i
.op
[op
].regs
->reg_name
,
3638 #if REGISTER_WARNINGS
3640 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3641 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3643 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3644 ? REGNAM_AL
- REGNAM_AX
3645 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3647 i
.op
[op
].regs
->reg_name
,
3652 /* Any other register is bad. */
3653 if (i
.types
[op
].bitfield
.reg16
3654 || i
.types
[op
].bitfield
.reg32
3655 || i
.types
[op
].bitfield
.reg64
3656 || i
.types
[op
].bitfield
.regmmx
3657 || i
.types
[op
].bitfield
.regxmm
3658 || i
.types
[op
].bitfield
.sreg2
3659 || i
.types
[op
].bitfield
.sreg3
3660 || i
.types
[op
].bitfield
.control
3661 || i
.types
[op
].bitfield
.debug
3662 || i
.types
[op
].bitfield
.test
3663 || i
.types
[op
].bitfield
.floatreg
3664 || i
.types
[op
].bitfield
.floatacc
)
3666 as_bad (_("`%s%s' not allowed with `%s%c'"),
3668 i
.op
[op
].regs
->reg_name
,
3678 check_long_reg (void)
3682 for (op
= i
.operands
; --op
>= 0;)
3683 /* Reject eight bit registers, except where the template requires
3684 them. (eg. movzb) */
3685 if (i
.types
[op
].bitfield
.reg8
3686 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3687 || i
.tm
.operand_types
[op
].bitfield
.reg32
3688 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3690 as_bad (_("`%s%s' not allowed with `%s%c'"),
3692 i
.op
[op
].regs
->reg_name
,
3697 /* Warn if the e prefix on a general reg is missing. */
3698 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3699 && i
.types
[op
].bitfield
.reg16
3700 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3701 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3703 /* Prohibit these changes in the 64bit mode, since the
3704 lowering is more complicated. */
3705 if (flag_code
== CODE_64BIT
)
3707 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3708 register_prefix
, i
.op
[op
].regs
->reg_name
,
3712 #if REGISTER_WARNINGS
3714 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3716 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3718 i
.op
[op
].regs
->reg_name
,
3722 /* Warn if the r prefix on a general reg is missing. */
3723 else if (i
.types
[op
].bitfield
.reg64
3724 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3725 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3728 && i
.tm
.opcode_modifier
.toqword
3729 && !i
.types
[0].bitfield
.regxmm
)
3731 /* Convert to QWORD. We want REX byte. */
3732 i
.suffix
= QWORD_MNEM_SUFFIX
;
3736 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3737 register_prefix
, i
.op
[op
].regs
->reg_name
,
3746 check_qword_reg (void)
3750 for (op
= i
.operands
; --op
>= 0; )
3751 /* Reject eight bit registers, except where the template requires
3752 them. (eg. movzb) */
3753 if (i
.types
[op
].bitfield
.reg8
3754 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3755 || i
.tm
.operand_types
[op
].bitfield
.reg32
3756 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3758 as_bad (_("`%s%s' not allowed with `%s%c'"),
3760 i
.op
[op
].regs
->reg_name
,
3765 /* Warn if the e prefix on a general reg is missing. */
3766 else if ((i
.types
[op
].bitfield
.reg16
3767 || i
.types
[op
].bitfield
.reg32
)
3768 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3769 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3771 /* Prohibit these changes in the 64bit mode, since the
3772 lowering is more complicated. */
3774 && i
.tm
.opcode_modifier
.todword
3775 && !i
.types
[0].bitfield
.regxmm
)
3777 /* Convert to DWORD. We don't want REX byte. */
3778 i
.suffix
= LONG_MNEM_SUFFIX
;
3782 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3783 register_prefix
, i
.op
[op
].regs
->reg_name
,
3792 check_word_reg (void)
3795 for (op
= i
.operands
; --op
>= 0;)
3796 /* Reject eight bit registers, except where the template requires
3797 them. (eg. movzb) */
3798 if (i
.types
[op
].bitfield
.reg8
3799 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3800 || i
.tm
.operand_types
[op
].bitfield
.reg32
3801 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3803 as_bad (_("`%s%s' not allowed with `%s%c'"),
3805 i
.op
[op
].regs
->reg_name
,
3810 /* Warn if the e prefix on a general reg is present. */
3811 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3812 && i
.types
[op
].bitfield
.reg32
3813 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3814 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3816 /* Prohibit these changes in the 64bit mode, since the
3817 lowering is more complicated. */
3818 if (flag_code
== CODE_64BIT
)
3820 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3821 register_prefix
, i
.op
[op
].regs
->reg_name
,
3826 #if REGISTER_WARNINGS
3827 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3829 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3831 i
.op
[op
].regs
->reg_name
,
3839 update_imm (unsigned int j
)
3841 i386_operand_type overlap
;
3843 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3844 if ((overlap
.bitfield
.imm8
3845 || overlap
.bitfield
.imm8s
3846 || overlap
.bitfield
.imm16
3847 || overlap
.bitfield
.imm32
3848 || overlap
.bitfield
.imm32s
3849 || overlap
.bitfield
.imm64
)
3850 && !UINTS_EQUAL (overlap
, imm8
)
3851 && !UINTS_EQUAL (overlap
, imm8s
)
3852 && !UINTS_EQUAL (overlap
, imm16
)
3853 && !UINTS_EQUAL (overlap
, imm32
)
3854 && !UINTS_EQUAL (overlap
, imm32s
)
3855 && !UINTS_EQUAL (overlap
, imm64
))
3859 i386_operand_type temp
;
3862 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3864 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3865 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3867 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3868 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3869 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3871 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3872 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3875 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3878 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3879 || UINTS_EQUAL (overlap
, imm16_32
)
3880 || UINTS_EQUAL (overlap
, imm16_32s
))
3882 UINTS_CLEAR (overlap
);
3883 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3884 overlap
.bitfield
.imm16
= 1;
3886 overlap
.bitfield
.imm32s
= 1;
3888 if (!UINTS_EQUAL (overlap
, imm8
)
3889 && !UINTS_EQUAL (overlap
, imm8s
)
3890 && !UINTS_EQUAL (overlap
, imm16
)
3891 && !UINTS_EQUAL (overlap
, imm32
)
3892 && !UINTS_EQUAL (overlap
, imm32s
)
3893 && !UINTS_EQUAL (overlap
, imm64
))
3895 as_bad (_("no instruction mnemonic suffix given; "
3896 "can't determine immediate size"));
3900 i
.types
[j
] = overlap
;
3910 for (j
= 0; j
< 2; j
++)
3911 if (update_imm (j
) == 0)
3914 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3915 assert (operand_type_check (i
.types
[2], imm
) == 0);
3923 i
.drex
.modrm_reg
= 0;
3924 i
.drex
.modrm_regmem
= 0;
3926 /* SSE5 4 operand instructions must have the destination the same as
3927 one of the inputs. Figure out the destination register and cache
3928 it away in the drex field, and remember which fields to use for
3930 if (i
.tm
.opcode_modifier
.drex
3931 && i
.tm
.opcode_modifier
.drexv
3934 i
.tm
.extension_opcode
= None
;
3936 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3937 if (i
.types
[0].bitfield
.regxmm
!= 0
3938 && i
.types
[1].bitfield
.regxmm
!= 0
3939 && i
.types
[2].bitfield
.regxmm
!= 0
3940 && i
.types
[3].bitfield
.regxmm
!= 0
3941 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3942 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3944 /* Clear the arguments that are stored in drex. */
3945 UINTS_CLEAR (i
.types
[0]);
3946 UINTS_CLEAR (i
.types
[3]);
3947 i
.reg_operands
-= 2;
3949 /* There are two different ways to encode a 4 operand
3950 instruction with all registers that uses OC1 set to
3951 0 or 1. Favor setting OC1 to 0 since this mimics the
3952 actions of other SSE5 assemblers. Use modrm encoding 2
3953 for register/register. Include the high order bit that
3954 is normally stored in the REX byte in the register
3956 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3957 i
.drex
.modrm_reg
= 2;
3958 i
.drex
.modrm_regmem
= 1;
3959 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3960 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3963 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3964 else if (i
.types
[0].bitfield
.regxmm
!= 0
3965 && i
.types
[1].bitfield
.regxmm
!= 0
3966 && (i
.types
[2].bitfield
.regxmm
3967 || operand_type_check (i
.types
[2], anymem
))
3968 && i
.types
[3].bitfield
.regxmm
!= 0
3969 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3970 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3972 /* clear the arguments that are stored in drex */
3973 UINTS_CLEAR (i
.types
[0]);
3974 UINTS_CLEAR (i
.types
[3]);
3975 i
.reg_operands
-= 2;
3977 /* Specify the modrm encoding for memory addressing. Include
3978 the high order bit that is normally stored in the REX byte
3979 in the register field. */
3980 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
3981 i
.drex
.modrm_reg
= 1;
3982 i
.drex
.modrm_regmem
= 2;
3983 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3984 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3987 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3988 else if (i
.types
[0].bitfield
.regxmm
!= 0
3989 && operand_type_check (i
.types
[1], anymem
) != 0
3990 && i
.types
[2].bitfield
.regxmm
!= 0
3991 && i
.types
[3].bitfield
.regxmm
!= 0
3992 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3993 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3995 /* Clear the arguments that are stored in drex. */
3996 UINTS_CLEAR (i
.types
[0]);
3997 UINTS_CLEAR (i
.types
[3]);
3998 i
.reg_operands
-= 2;
4000 /* Specify the modrm encoding for memory addressing. Include
4001 the high order bit that is normally stored in the REX byte
4002 in the register field. */
4003 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4004 i
.drex
.modrm_reg
= 2;
4005 i
.drex
.modrm_regmem
= 1;
4006 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4007 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4010 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4011 else if (i
.types
[0].bitfield
.regxmm
!= 0
4012 && i
.types
[1].bitfield
.regxmm
!= 0
4013 && i
.types
[2].bitfield
.regxmm
!= 0
4014 && i
.types
[3].bitfield
.regxmm
!= 0
4015 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4016 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4018 /* clear the arguments that are stored in drex */
4019 UINTS_CLEAR (i
.types
[2]);
4020 UINTS_CLEAR (i
.types
[3]);
4021 i
.reg_operands
-= 2;
4023 /* There are two different ways to encode a 4 operand
4024 instruction with all registers that uses OC1 set to
4025 0 or 1. Favor setting OC1 to 0 since this mimics the
4026 actions of other SSE5 assemblers. Use modrm encoding
4027 2 for register/register. Include the high order bit that
4028 is normally stored in the REX byte in the register
4030 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4031 i
.drex
.modrm_reg
= 1;
4032 i
.drex
.modrm_regmem
= 0;
4034 /* Remember the register, including the upper bits */
4035 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4036 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4039 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4040 else if (i
.types
[0].bitfield
.regxmm
!= 0
4041 && (i
.types
[1].bitfield
.regxmm
4042 || operand_type_check (i
.types
[1], anymem
))
4043 && i
.types
[2].bitfield
.regxmm
!= 0
4044 && i
.types
[3].bitfield
.regxmm
!= 0
4045 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4046 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4048 /* Clear the arguments that are stored in drex. */
4049 UINTS_CLEAR (i
.types
[2]);
4050 UINTS_CLEAR (i
.types
[3]);
4051 i
.reg_operands
-= 2;
4053 /* Specify the modrm encoding and remember the register
4054 including the bits normally stored in the REX byte. */
4055 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4056 i
.drex
.modrm_reg
= 0;
4057 i
.drex
.modrm_regmem
= 1;
4058 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4059 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4062 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4063 else if (operand_type_check (i
.types
[0], anymem
) != 0
4064 && i
.types
[1].bitfield
.regxmm
!= 0
4065 && i
.types
[2].bitfield
.regxmm
!= 0
4066 && i
.types
[3].bitfield
.regxmm
!= 0
4067 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4068 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4070 /* clear the arguments that are stored in drex */
4071 UINTS_CLEAR (i
.types
[2]);
4072 UINTS_CLEAR (i
.types
[3]);
4073 i
.reg_operands
-= 2;
4075 /* Specify the modrm encoding and remember the register
4076 including the bits normally stored in the REX byte. */
4077 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4078 i
.drex
.modrm_reg
= 1;
4079 i
.drex
.modrm_regmem
= 0;
4080 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4081 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4085 as_bad (_("Incorrect operands for the '%s' instruction"),
4089 /* SSE5 instructions with the DREX byte where the only memory operand
4090 is in the 2nd argument, and the first and last xmm register must
4091 match, and is encoded in the DREX byte. */
4092 else if (i
.tm
.opcode_modifier
.drex
4093 && !i
.tm
.opcode_modifier
.drexv
4096 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4097 if (i
.types
[0].bitfield
.regxmm
!= 0
4098 && (i
.types
[1].bitfield
.regxmm
4099 || operand_type_check(i
.types
[1], anymem
))
4100 && i
.types
[2].bitfield
.regxmm
!= 0
4101 && i
.types
[3].bitfield
.regxmm
!= 0
4102 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4103 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4105 /* clear the arguments that are stored in drex */
4106 UINTS_CLEAR (i
.types
[0]);
4107 UINTS_CLEAR (i
.types
[3]);
4108 i
.reg_operands
-= 2;
4110 /* Specify the modrm encoding and remember the register
4111 including the high bit normally stored in the REX
4113 i
.drex
.modrm_reg
= 2;
4114 i
.drex
.modrm_regmem
= 1;
4115 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4116 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4120 as_bad (_("Incorrect operands for the '%s' instruction"),
4124 /* SSE5 3 operand instructions that the result is a register, being
4125 either operand can be a memory operand, using OC0 to note which
4126 one is the memory. */
4127 else if (i
.tm
.opcode_modifier
.drex
4128 && i
.tm
.opcode_modifier
.drexv
4131 i
.tm
.extension_opcode
= None
;
4133 /* Case 1: 3 operand insn, src1 = register. */
4134 if (i
.types
[0].bitfield
.regxmm
!= 0
4135 && i
.types
[1].bitfield
.regxmm
!= 0
4136 && i
.types
[2].bitfield
.regxmm
!= 0)
4138 /* Clear the arguments that are stored in drex. */
4139 UINTS_CLEAR (i
.types
[2]);
4142 /* Specify the modrm encoding and remember the register
4143 including the high bit normally stored in the REX byte. */
4144 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4145 i
.drex
.modrm_reg
= 1;
4146 i
.drex
.modrm_regmem
= 0;
4147 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4148 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4151 /* Case 2: 3 operand insn, src1 = memory. */
4152 else if (operand_type_check (i
.types
[0], anymem
) != 0
4153 && i
.types
[1].bitfield
.regxmm
!= 0
4154 && i
.types
[2].bitfield
.regxmm
!= 0)
4156 /* Clear the arguments that are stored in drex. */
4157 UINTS_CLEAR (i
.types
[2]);
4160 /* Specify the modrm encoding and remember the register
4161 including the high bit normally stored in the REX
4163 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4164 i
.drex
.modrm_reg
= 1;
4165 i
.drex
.modrm_regmem
= 0;
4166 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4167 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4170 /* Case 3: 3 operand insn, src2 = memory. */
4171 else if (i
.types
[0].bitfield
.regxmm
!= 0
4172 && operand_type_check (i
.types
[1], anymem
) != 0
4173 && i
.types
[2].bitfield
.regxmm
!= 0)
4175 /* Clear the arguments that are stored in drex. */
4176 UINTS_CLEAR (i
.types
[2]);
4179 /* Specify the modrm encoding and remember the register
4180 including the high bit normally stored in the REX byte. */
4181 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4182 i
.drex
.modrm_reg
= 0;
4183 i
.drex
.modrm_regmem
= 1;
4184 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4185 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4189 as_bad (_("Incorrect operands for the '%s' instruction"),
4193 /* SSE5 4 operand instructions that are the comparison instructions
4194 where the first operand is the immediate value of the comparison
4196 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4198 /* Case 1: 4 operand insn, src1 = reg/memory. */
4199 if (operand_type_check (i
.types
[0], imm
) != 0
4200 && (i
.types
[1].bitfield
.regxmm
4201 || operand_type_check (i
.types
[1], anymem
))
4202 && i
.types
[2].bitfield
.regxmm
!= 0
4203 && i
.types
[3].bitfield
.regxmm
!= 0)
4205 /* clear the arguments that are stored in drex */
4206 UINTS_CLEAR (i
.types
[3]);
4209 /* Specify the modrm encoding and remember the register
4210 including the high bit normally stored in the REX byte. */
4211 i
.drex
.modrm_reg
= 2;
4212 i
.drex
.modrm_regmem
= 1;
4213 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4214 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4217 /* Case 2: 3 operand insn with ImmExt that places the
4218 opcode_extension as an immediate argument. This is used for
4219 all of the varients of comparison that supplies the appropriate
4220 value as part of the instruction. */
4221 else if ((i
.types
[0].bitfield
.regxmm
4222 || operand_type_check (i
.types
[0], anymem
))
4223 && i
.types
[1].bitfield
.regxmm
!= 0
4224 && i
.types
[2].bitfield
.regxmm
!= 0
4225 && operand_type_check (i
.types
[3], imm
) != 0)
4227 /* clear the arguments that are stored in drex */
4228 UINTS_CLEAR (i
.types
[2]);
4231 /* Specify the modrm encoding and remember the register
4232 including the high bit normally stored in the REX byte. */
4233 i
.drex
.modrm_reg
= 1;
4234 i
.drex
.modrm_regmem
= 0;
4235 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4236 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4240 as_bad (_("Incorrect operands for the '%s' instruction"),
4244 else if (i
.tm
.opcode_modifier
.drex
4245 || i
.tm
.opcode_modifier
.drexv
4246 || i
.tm
.opcode_modifier
.drexc
)
4247 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4251 process_operands (void)
4253 /* Default segment register this instruction will use for memory
4254 accesses. 0 means unknown. This is only for optimizing out
4255 unnecessary segment overrides. */
4256 const seg_entry
*default_seg
= 0;
4258 /* Handle all of the DREX munging that SSE5 needs. */
4259 if (i
.tm
.opcode_modifier
.drex
4260 || i
.tm
.opcode_modifier
.drexv
4261 || i
.tm
.opcode_modifier
.drexc
)
4264 if (i
.tm
.opcode_modifier
.firstxmm0
)
4268 /* The first operand is implicit and must be xmm0. */
4269 assert (i
.reg_operands
&& UINTS_EQUAL (i
.types
[0], regxmm
));
4270 if (i
.op
[0].regs
->reg_num
!= 0)
4273 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4274 i
.tm
.name
, register_prefix
);
4276 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4277 i
.tm
.name
, register_prefix
);
4281 for (j
= 1; j
< i
.operands
; j
++)
4283 i
.op
[j
- 1] = i
.op
[j
];
4284 i
.types
[j
- 1] = i
.types
[j
];
4286 /* We need to adjust fields in i.tm since they are used by
4287 build_modrm_byte. */
4288 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4295 else if (i
.tm
.opcode_modifier
.regkludge
)
4297 /* The imul $imm, %reg instruction is converted into
4298 imul $imm, %reg, %reg, and the clr %reg instruction
4299 is converted into xor %reg, %reg. */
4301 unsigned int first_reg_op
;
4303 if (operand_type_check (i
.types
[0], reg
))
4307 /* Pretend we saw the extra register operand. */
4308 assert (i
.reg_operands
== 1
4309 && i
.op
[first_reg_op
+ 1].regs
== 0);
4310 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4311 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4316 if (i
.tm
.opcode_modifier
.shortform
)
4318 if (i
.types
[0].bitfield
.sreg2
4319 || i
.types
[0].bitfield
.sreg3
)
4321 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4322 && i
.op
[0].regs
->reg_num
== 1)
4324 as_bad (_("you can't `pop %%cs'"));
4327 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4328 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4333 /* The register or float register operand is in operand
4337 if (i
.types
[0].bitfield
.floatreg
4338 || operand_type_check (i
.types
[0], reg
))
4342 /* Register goes in low 3 bits of opcode. */
4343 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4344 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4346 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4348 /* Warn about some common errors, but press on regardless.
4349 The first case can be generated by gcc (<= 2.8.1). */
4350 if (i
.operands
== 2)
4352 /* Reversed arguments on faddp, fsubp, etc. */
4353 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4354 register_prefix
, i
.op
[1].regs
->reg_name
,
4355 register_prefix
, i
.op
[0].regs
->reg_name
);
4359 /* Extraneous `l' suffix on fp insn. */
4360 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4361 register_prefix
, i
.op
[0].regs
->reg_name
);
4366 else if (i
.tm
.opcode_modifier
.modrm
)
4368 /* The opcode is completed (modulo i.tm.extension_opcode which
4369 must be put into the modrm byte). Now, we make the modrm and
4370 index base bytes based on all the info we've collected. */
4372 default_seg
= build_modrm_byte ();
4374 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4378 else if (i
.tm
.opcode_modifier
.isstring
)
4380 /* For the string instructions that allow a segment override
4381 on one of their operands, the default segment is ds. */
4385 if (i
.tm
.base_opcode
== 0x8d /* lea */
4388 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4390 /* If a segment was explicitly specified, and the specified segment
4391 is not the default, use an opcode prefix to select it. If we
4392 never figured out what the default segment is, then default_seg
4393 will be zero at this point, and the specified segment prefix will
4395 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4397 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4403 static const seg_entry
*
4404 build_modrm_byte (void)
4406 const seg_entry
*default_seg
= 0;
4408 /* SSE5 4 operand instructions are encoded in such a way that one of
4409 the inputs must match the destination register. Process_drex hides
4410 the 3rd argument in the drex field, so that by the time we get
4411 here, it looks to GAS as if this is a 2 operand instruction. */
4412 if ((i
.tm
.opcode_modifier
.drex
4413 || i
.tm
.opcode_modifier
.drexv
4414 || i
.tm
.opcode_modifier
.drexc
)
4415 && i
.reg_operands
== 2)
4417 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
4418 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
4420 i
.rm
.reg
= reg
->reg_num
;
4421 i
.rm
.regmem
= regmem
->reg_num
;
4423 if ((reg
->reg_flags
& RegRex
) != 0)
4425 if ((regmem
->reg_flags
& RegRex
) != 0)
4429 /* i.reg_operands MUST be the number of real register operands;
4430 implicit registers do not count. */
4431 else if (i
.reg_operands
== 2)
4433 unsigned int source
, dest
;
4441 /* When there are 3 operands, one of them may be immediate,
4442 which may be the first or the last operand. Otherwise,
4443 the first operand must be shift count register (cl). */
4444 assert (i
.imm_operands
== 1
4445 || (i
.imm_operands
== 0
4446 && i
.types
[0].bitfield
.shiftcount
));
4447 if (operand_type_check (i
.types
[0], imm
)
4448 || i
.types
[0].bitfield
.shiftcount
)
4454 /* When there are 4 operands, the first two must be 8bit
4455 immediate operands. The source operand will be the 3rd
4457 assert (i
.imm_operands
== 2
4458 && i
.types
[0].bitfield
.imm8
4459 && i
.types
[1].bitfield
.imm8
);
4469 /* One of the register operands will be encoded in the i.tm.reg
4470 field, the other in the combined i.tm.mode and i.tm.regmem
4471 fields. If no form of this instruction supports a memory
4472 destination operand, then we assume the source operand may
4473 sometimes be a memory operand and so we need to store the
4474 destination in the i.rm.reg field. */
4475 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4476 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4478 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4479 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4480 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4482 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4487 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4488 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4489 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4491 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4494 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4496 if (!i
.types
[0].bitfield
.control
4497 && !i
.types
[1].bitfield
.control
)
4499 i
.rex
&= ~(REX_R
| REX_B
);
4500 add_prefix (LOCK_PREFIX_OPCODE
);
4504 { /* If it's not 2 reg operands... */
4507 unsigned int fake_zero_displacement
= 0;
4510 /* This has been precalculated for SSE5 instructions
4511 that have a DREX field earlier in process_drex. */
4512 if (i
.tm
.opcode_modifier
.drex
4513 || i
.tm
.opcode_modifier
.drexv
4514 || i
.tm
.opcode_modifier
.drexc
)
4515 op
= i
.drex
.modrm_regmem
;
4518 for (op
= 0; op
< i
.operands
; op
++)
4519 if (operand_type_check (i
.types
[op
], anymem
))
4521 assert (op
< i
.operands
);
4526 if (i
.base_reg
== 0)
4529 if (!i
.disp_operands
)
4530 fake_zero_displacement
= 1;
4531 if (i
.index_reg
== 0)
4533 /* Operand is just <disp> */
4534 if (flag_code
== CODE_64BIT
)
4536 /* 64bit mode overwrites the 32bit absolute
4537 addressing by RIP relative addressing and
4538 absolute addressing is encoded by one of the
4539 redundant SIB forms. */
4540 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4541 i
.sib
.base
= NO_BASE_REGISTER
;
4542 i
.sib
.index
= NO_INDEX_REGISTER
;
4543 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4544 ? disp32s
: disp32
);
4546 else if ((flag_code
== CODE_16BIT
)
4547 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4549 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4550 i
.types
[op
] = disp16
;
4554 i
.rm
.regmem
= NO_BASE_REGISTER
;
4555 i
.types
[op
] = disp32
;
4558 else /* !i.base_reg && i.index_reg */
4560 if (i
.index_reg
->reg_num
== RegEiz
4561 || i
.index_reg
->reg_num
== RegRiz
)
4562 i
.sib
.index
= NO_INDEX_REGISTER
;
4564 i
.sib
.index
= i
.index_reg
->reg_num
;
4565 i
.sib
.base
= NO_BASE_REGISTER
;
4566 i
.sib
.scale
= i
.log2_scale_factor
;
4567 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4568 i
.types
[op
].bitfield
.disp8
= 0;
4569 i
.types
[op
].bitfield
.disp16
= 0;
4570 i
.types
[op
].bitfield
.disp64
= 0;
4571 if (flag_code
!= CODE_64BIT
)
4573 /* Must be 32 bit */
4574 i
.types
[op
].bitfield
.disp32
= 1;
4575 i
.types
[op
].bitfield
.disp32s
= 0;
4579 i
.types
[op
].bitfield
.disp32
= 0;
4580 i
.types
[op
].bitfield
.disp32s
= 1;
4582 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4586 /* RIP addressing for 64bit mode. */
4587 else if (i
.base_reg
->reg_num
== RegRip
||
4588 i
.base_reg
->reg_num
== RegEip
)
4590 i
.rm
.regmem
= NO_BASE_REGISTER
;
4591 i
.types
[op
].bitfield
.disp8
= 0;
4592 i
.types
[op
].bitfield
.disp16
= 0;
4593 i
.types
[op
].bitfield
.disp32
= 0;
4594 i
.types
[op
].bitfield
.disp32s
= 1;
4595 i
.types
[op
].bitfield
.disp64
= 0;
4596 i
.flags
[op
] |= Operand_PCrel
;
4597 if (! i
.disp_operands
)
4598 fake_zero_displacement
= 1;
4600 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4602 switch (i
.base_reg
->reg_num
)
4605 if (i
.index_reg
== 0)
4607 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4608 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4612 if (i
.index_reg
== 0)
4615 if (operand_type_check (i
.types
[op
], disp
) == 0)
4617 /* fake (%bp) into 0(%bp) */
4618 i
.types
[op
].bitfield
.disp8
= 1;
4619 fake_zero_displacement
= 1;
4622 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4623 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4625 default: /* (%si) -> 4 or (%di) -> 5 */
4626 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4628 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4630 else /* i.base_reg and 32/64 bit mode */
4632 if (flag_code
== CODE_64BIT
4633 && operand_type_check (i
.types
[op
], disp
))
4635 i386_operand_type temp
;
4637 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4639 if (i
.prefix
[ADDR_PREFIX
] == 0)
4640 i
.types
[op
].bitfield
.disp32s
= 1;
4642 i
.types
[op
].bitfield
.disp32
= 1;
4645 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4646 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4648 i
.sib
.base
= i
.base_reg
->reg_num
;
4649 /* x86-64 ignores REX prefix bit here to avoid decoder
4651 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4654 if (i
.disp_operands
== 0)
4656 fake_zero_displacement
= 1;
4657 i
.types
[op
].bitfield
.disp8
= 1;
4660 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4664 i
.sib
.scale
= i
.log2_scale_factor
;
4665 if (i
.index_reg
== 0)
4667 /* <disp>(%esp) becomes two byte modrm with no index
4668 register. We've already stored the code for esp
4669 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4670 Any base register besides %esp will not use the
4671 extra modrm byte. */
4672 i
.sib
.index
= NO_INDEX_REGISTER
;
4676 if (i
.index_reg
->reg_num
== RegEiz
4677 || i
.index_reg
->reg_num
== RegRiz
)
4678 i
.sib
.index
= NO_INDEX_REGISTER
;
4680 i
.sib
.index
= i
.index_reg
->reg_num
;
4681 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4682 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4687 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4688 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4691 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4694 if (fake_zero_displacement
)
4696 /* Fakes a zero displacement assuming that i.types[op]
4697 holds the correct displacement size. */
4700 assert (i
.op
[op
].disps
== 0);
4701 exp
= &disp_expressions
[i
.disp_operands
++];
4702 i
.op
[op
].disps
= exp
;
4703 exp
->X_op
= O_constant
;
4704 exp
->X_add_number
= 0;
4705 exp
->X_add_symbol
= (symbolS
*) 0;
4706 exp
->X_op_symbol
= (symbolS
*) 0;
4710 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4711 (if any) based on i.tm.extension_opcode. Again, we must be
4712 careful to make sure that segment/control/debug/test/MMX
4713 registers are coded into the i.rm.reg field. */
4718 /* This has been precalculated for SSE5 instructions
4719 that have a DREX field earlier in process_drex. */
4720 if (i
.tm
.opcode_modifier
.drex
4721 || i
.tm
.opcode_modifier
.drexv
4722 || i
.tm
.opcode_modifier
.drexc
)
4724 op
= i
.drex
.modrm_reg
;
4725 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4726 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4731 for (op
= 0; op
< i
.operands
; op
++)
4732 if (i
.types
[op
].bitfield
.reg8
4733 || i
.types
[op
].bitfield
.reg16
4734 || i
.types
[op
].bitfield
.reg32
4735 || i
.types
[op
].bitfield
.reg64
4736 || i
.types
[op
].bitfield
.regmmx
4737 || i
.types
[op
].bitfield
.regxmm
4738 || i
.types
[op
].bitfield
.sreg2
4739 || i
.types
[op
].bitfield
.sreg3
4740 || i
.types
[op
].bitfield
.control
4741 || i
.types
[op
].bitfield
.debug
4742 || i
.types
[op
].bitfield
.test
)
4745 assert (op
< i
.operands
);
4747 /* If there is an extension opcode to put here, the
4748 register number must be put into the regmem field. */
4749 if (i
.tm
.extension_opcode
!= None
)
4751 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4752 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4757 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4758 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4763 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4764 must set it to 3 to indicate this is a register operand
4765 in the regmem field. */
4766 if (!i
.mem_operands
)
4770 /* Fill in i.rm.reg field with extension opcode (if any). */
4771 if (i
.tm
.extension_opcode
!= None
4772 && !(i
.tm
.opcode_modifier
.drex
4773 || i
.tm
.opcode_modifier
.drexv
4774 || i
.tm
.opcode_modifier
.drexc
))
4775 i
.rm
.reg
= i
.tm
.extension_opcode
;
4781 output_branch (void)
4786 relax_substateT subtype
;
4791 if (flag_code
== CODE_16BIT
)
4795 if (i
.prefix
[DATA_PREFIX
] != 0)
4801 /* Pentium4 branch hints. */
4802 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4803 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4808 if (i
.prefix
[REX_PREFIX
] != 0)
4814 if (i
.prefixes
!= 0 && !intel_syntax
)
4815 as_warn (_("skipping prefixes on this instruction"));
4817 /* It's always a symbol; End frag & setup for relax.
4818 Make sure there is enough room in this frag for the largest
4819 instruction we may generate in md_convert_frag. This is 2
4820 bytes for the opcode and room for the prefix and largest
4822 frag_grow (prefix
+ 2 + 4);
4823 /* Prefix and 1 opcode byte go in fr_fix. */
4824 p
= frag_more (prefix
+ 1);
4825 if (i
.prefix
[DATA_PREFIX
] != 0)
4826 *p
++ = DATA_PREFIX_OPCODE
;
4827 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4828 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4829 *p
++ = i
.prefix
[SEG_PREFIX
];
4830 if (i
.prefix
[REX_PREFIX
] != 0)
4831 *p
++ = i
.prefix
[REX_PREFIX
];
4832 *p
= i
.tm
.base_opcode
;
4834 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4835 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4836 else if (cpu_arch_flags
.bitfield
.cpui386
)
4837 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4839 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4842 sym
= i
.op
[0].disps
->X_add_symbol
;
4843 off
= i
.op
[0].disps
->X_add_number
;
4845 if (i
.op
[0].disps
->X_op
!= O_constant
4846 && i
.op
[0].disps
->X_op
!= O_symbol
)
4848 /* Handle complex expressions. */
4849 sym
= make_expr_symbol (i
.op
[0].disps
);
4853 /* 1 possible extra opcode + 4 byte displacement go in var part.
4854 Pass reloc in fr_var. */
4855 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4865 if (i
.tm
.opcode_modifier
.jumpbyte
)
4867 /* This is a loop or jecxz type instruction. */
4869 if (i
.prefix
[ADDR_PREFIX
] != 0)
4871 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4874 /* Pentium4 branch hints. */
4875 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4876 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4878 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4887 if (flag_code
== CODE_16BIT
)
4890 if (i
.prefix
[DATA_PREFIX
] != 0)
4892 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4902 if (i
.prefix
[REX_PREFIX
] != 0)
4904 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4908 if (i
.prefixes
!= 0 && !intel_syntax
)
4909 as_warn (_("skipping prefixes on this instruction"));
4911 p
= frag_more (1 + size
);
4912 *p
++ = i
.tm
.base_opcode
;
4914 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4915 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4917 /* All jumps handled here are signed, but don't use a signed limit
4918 check for 32 and 16 bit jumps as we want to allow wrap around at
4919 4G and 64k respectively. */
4921 fixP
->fx_signed
= 1;
4925 output_interseg_jump (void)
4933 if (flag_code
== CODE_16BIT
)
4937 if (i
.prefix
[DATA_PREFIX
] != 0)
4943 if (i
.prefix
[REX_PREFIX
] != 0)
4953 if (i
.prefixes
!= 0 && !intel_syntax
)
4954 as_warn (_("skipping prefixes on this instruction"));
4956 /* 1 opcode; 2 segment; offset */
4957 p
= frag_more (prefix
+ 1 + 2 + size
);
4959 if (i
.prefix
[DATA_PREFIX
] != 0)
4960 *p
++ = DATA_PREFIX_OPCODE
;
4962 if (i
.prefix
[REX_PREFIX
] != 0)
4963 *p
++ = i
.prefix
[REX_PREFIX
];
4965 *p
++ = i
.tm
.base_opcode
;
4966 if (i
.op
[1].imms
->X_op
== O_constant
)
4968 offsetT n
= i
.op
[1].imms
->X_add_number
;
4971 && !fits_in_unsigned_word (n
)
4972 && !fits_in_signed_word (n
))
4974 as_bad (_("16-bit jump out of range"));
4977 md_number_to_chars (p
, n
, size
);
4980 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4981 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4982 if (i
.op
[0].imms
->X_op
!= O_constant
)
4983 as_bad (_("can't handle non absolute segment in `%s'"),
4985 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4991 fragS
*insn_start_frag
;
4992 offsetT insn_start_off
;
4994 /* Tie dwarf2 debug info to the address at the start of the insn.
4995 We can't do this after the insn has been output as the current
4996 frag may have been closed off. eg. by frag_var. */
4997 dwarf2_emit_insn (0);
4999 insn_start_frag
= frag_now
;
5000 insn_start_off
= frag_now_fix ();
5003 if (i
.tm
.opcode_modifier
.jump
)
5005 else if (i
.tm
.opcode_modifier
.jumpbyte
5006 || i
.tm
.opcode_modifier
.jumpdword
)
5008 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5009 output_interseg_jump ();
5012 /* Output normal instructions here. */
5016 unsigned int prefix
;
5018 switch (i
.tm
.opcode_length
)
5021 if (i
.tm
.base_opcode
& 0xff000000)
5023 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5028 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5030 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5031 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5034 if (prefix
!= REPE_PREFIX_OPCODE
5035 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
5036 add_prefix (prefix
);
5039 add_prefix (prefix
);
5048 /* The prefix bytes. */
5049 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5051 FRAG_APPEND_1_CHAR (*q
);
5053 /* Now the opcode; be careful about word order here! */
5054 if (i
.tm
.opcode_length
== 1)
5056 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5060 switch (i
.tm
.opcode_length
)
5064 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5074 /* Put out high byte first: can't use md_number_to_chars! */
5075 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5076 *p
= i
.tm
.base_opcode
& 0xff;
5078 /* On SSE5, encode the OC1 bit in the DREX field if this
5079 encoding has multiple formats. */
5080 if (i
.tm
.opcode_modifier
.drex
5081 && i
.tm
.opcode_modifier
.drexv
5082 && DREX_OC1 (i
.tm
.extension_opcode
))
5083 *p
|= DREX_OC1_MASK
;
5086 /* Now the modrm byte and sib byte (if present). */
5087 if (i
.tm
.opcode_modifier
.modrm
)
5089 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5092 /* If i.rm.regmem == ESP (4)
5093 && i.rm.mode != (Register mode)
5095 ==> need second modrm byte. */
5096 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5098 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5099 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5101 | i
.sib
.scale
<< 6));
5104 /* Write the DREX byte if needed. */
5105 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5108 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5110 /* Encode the OC0 bit if this encoding has multiple
5112 if ((i
.tm
.opcode_modifier
.drex
5113 || i
.tm
.opcode_modifier
.drexv
)
5114 && DREX_OC0 (i
.tm
.extension_opcode
))
5115 *p
|= DREX_OC0_MASK
;
5118 if (i
.disp_operands
)
5119 output_disp (insn_start_frag
, insn_start_off
);
5122 output_imm (insn_start_frag
, insn_start_off
);
5128 pi ("" /*line*/, &i
);
5130 #endif /* DEBUG386 */
5133 /* Return the size of the displacement operand N. */
5136 disp_size (unsigned int n
)
5139 if (i
.types
[n
].bitfield
.disp64
)
5141 else if (i
.types
[n
].bitfield
.disp8
)
5143 else if (i
.types
[n
].bitfield
.disp16
)
5148 /* Return the size of the immediate operand N. */
5151 imm_size (unsigned int n
)
5154 if (i
.types
[n
].bitfield
.imm64
)
5156 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5158 else if (i
.types
[n
].bitfield
.imm16
)
5164 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5169 for (n
= 0; n
< i
.operands
; n
++)
5171 if (operand_type_check (i
.types
[n
], disp
))
5173 if (i
.op
[n
].disps
->X_op
== O_constant
)
5175 int size
= disp_size (n
);
5178 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5180 p
= frag_more (size
);
5181 md_number_to_chars (p
, val
, size
);
5185 enum bfd_reloc_code_real reloc_type
;
5186 int size
= disp_size (n
);
5187 int sign
= i
.types
[n
].bitfield
.disp32s
;
5188 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5190 /* We can't have 8 bit displacement here. */
5191 assert (!i
.types
[n
].bitfield
.disp8
);
5193 /* The PC relative address is computed relative
5194 to the instruction boundary, so in case immediate
5195 fields follows, we need to adjust the value. */
5196 if (pcrel
&& i
.imm_operands
)
5201 for (n1
= 0; n1
< i
.operands
; n1
++)
5202 if (operand_type_check (i
.types
[n1
], imm
))
5204 /* Only one immediate is allowed for PC
5205 relative address. */
5208 i
.op
[n
].disps
->X_add_number
-= sz
;
5210 /* We should find the immediate. */
5214 p
= frag_more (size
);
5215 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5217 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5218 && (((reloc_type
== BFD_RELOC_32
5219 || reloc_type
== BFD_RELOC_X86_64_32S
5220 || (reloc_type
== BFD_RELOC_64
5222 && (i
.op
[n
].disps
->X_op
== O_symbol
5223 || (i
.op
[n
].disps
->X_op
== O_add
5224 && ((symbol_get_value_expression
5225 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5227 || reloc_type
== BFD_RELOC_32_PCREL
))
5231 if (insn_start_frag
== frag_now
)
5232 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5237 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5238 for (fr
= insn_start_frag
->fr_next
;
5239 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5241 add
+= p
- frag_now
->fr_literal
;
5246 reloc_type
= BFD_RELOC_386_GOTPC
;
5247 i
.op
[n
].imms
->X_add_number
+= add
;
5249 else if (reloc_type
== BFD_RELOC_64
)
5250 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5252 /* Don't do the adjustment for x86-64, as there
5253 the pcrel addressing is relative to the _next_
5254 insn, and that is taken care of in other code. */
5255 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5257 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5258 i
.op
[n
].disps
, pcrel
, reloc_type
);
5265 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5270 for (n
= 0; n
< i
.operands
; n
++)
5272 if (operand_type_check (i
.types
[n
], imm
))
5274 if (i
.op
[n
].imms
->X_op
== O_constant
)
5276 int size
= imm_size (n
);
5279 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5281 p
= frag_more (size
);
5282 md_number_to_chars (p
, val
, size
);
5286 /* Not absolute_section.
5287 Need a 32-bit fixup (don't support 8bit
5288 non-absolute imms). Try to support other
5290 enum bfd_reloc_code_real reloc_type
;
5291 int size
= imm_size (n
);
5294 if (i
.types
[n
].bitfield
.imm32s
5295 && (i
.suffix
== QWORD_MNEM_SUFFIX
5296 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5301 p
= frag_more (size
);
5302 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5304 /* This is tough to explain. We end up with this one if we
5305 * have operands that look like
5306 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5307 * obtain the absolute address of the GOT, and it is strongly
5308 * preferable from a performance point of view to avoid using
5309 * a runtime relocation for this. The actual sequence of
5310 * instructions often look something like:
5315 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5317 * The call and pop essentially return the absolute address
5318 * of the label .L66 and store it in %ebx. The linker itself
5319 * will ultimately change the first operand of the addl so
5320 * that %ebx points to the GOT, but to keep things simple, the
5321 * .o file must have this operand set so that it generates not
5322 * the absolute address of .L66, but the absolute address of
5323 * itself. This allows the linker itself simply treat a GOTPC
5324 * relocation as asking for a pcrel offset to the GOT to be
5325 * added in, and the addend of the relocation is stored in the
5326 * operand field for the instruction itself.
5328 * Our job here is to fix the operand so that it would add
5329 * the correct offset so that %ebx would point to itself. The
5330 * thing that is tricky is that .-.L66 will point to the
5331 * beginning of the instruction, so we need to further modify
5332 * the operand so that it will point to itself. There are
5333 * other cases where you have something like:
5335 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5337 * and here no correction would be required. Internally in
5338 * the assembler we treat operands of this form as not being
5339 * pcrel since the '.' is explicitly mentioned, and I wonder
5340 * whether it would simplify matters to do it this way. Who
5341 * knows. In earlier versions of the PIC patches, the
5342 * pcrel_adjust field was used to store the correction, but
5343 * since the expression is not pcrel, I felt it would be
5344 * confusing to do it this way. */
5346 if ((reloc_type
== BFD_RELOC_32
5347 || reloc_type
== BFD_RELOC_X86_64_32S
5348 || reloc_type
== BFD_RELOC_64
)
5350 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5351 && (i
.op
[n
].imms
->X_op
== O_symbol
5352 || (i
.op
[n
].imms
->X_op
== O_add
5353 && ((symbol_get_value_expression
5354 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5359 if (insn_start_frag
== frag_now
)
5360 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5365 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5366 for (fr
= insn_start_frag
->fr_next
;
5367 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5369 add
+= p
- frag_now
->fr_literal
;
5373 reloc_type
= BFD_RELOC_386_GOTPC
;
5375 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5377 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5378 i
.op
[n
].imms
->X_add_number
+= add
;
5380 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5381 i
.op
[n
].imms
, 0, reloc_type
);
5387 /* x86_cons_fix_new is called via the expression parsing code when a
5388 reloc is needed. We use this hook to get the correct .got reloc. */
5389 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5390 static int cons_sign
= -1;
5393 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5396 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5398 got_reloc
= NO_RELOC
;
5401 if (exp
->X_op
== O_secrel
)
5403 exp
->X_op
= O_symbol
;
5404 r
= BFD_RELOC_32_SECREL
;
5408 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5411 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5412 # define lex_got(reloc, adjust, types) NULL
5414 /* Parse operands of the form
5415 <symbol>@GOTOFF+<nnn>
5416 and similar .plt or .got references.
5418 If we find one, set up the correct relocation in RELOC and copy the
5419 input string, minus the `@GOTOFF' into a malloc'd buffer for
5420 parsing by the calling routine. Return this buffer, and if ADJUST
5421 is non-null set it to the length of the string we removed from the
5422 input line. Otherwise return NULL. */
5424 lex_got (enum bfd_reloc_code_real
*reloc
,
5426 i386_operand_type
*types
)
5428 /* Some of the relocations depend on the size of what field is to
5429 be relocated. But in our callers i386_immediate and i386_displacement
5430 we don't yet know the operand size (this will be set by insn
5431 matching). Hence we record the word32 relocation here,
5432 and adjust the reloc according to the real size in reloc(). */
5433 static const struct {
5435 const enum bfd_reloc_code_real rel
[2];
5436 const i386_operand_type types64
;
5439 BFD_RELOC_X86_64_PLTOFF64
},
5440 OPERAND_TYPE_IMM64
},
5441 { "PLT", { BFD_RELOC_386_PLT32
,
5442 BFD_RELOC_X86_64_PLT32
},
5443 OPERAND_TYPE_IMM32_32S_DISP32
},
5445 BFD_RELOC_X86_64_GOTPLT64
},
5446 OPERAND_TYPE_IMM64_DISP64
},
5447 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5448 BFD_RELOC_X86_64_GOTOFF64
},
5449 OPERAND_TYPE_IMM64_DISP64
},
5451 BFD_RELOC_X86_64_GOTPCREL
},
5452 OPERAND_TYPE_IMM32_32S_DISP32
},
5453 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5454 BFD_RELOC_X86_64_TLSGD
},
5455 OPERAND_TYPE_IMM32_32S_DISP32
},
5456 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5458 OPERAND_TYPE_NONE
},
5460 BFD_RELOC_X86_64_TLSLD
},
5461 OPERAND_TYPE_IMM32_32S_DISP32
},
5462 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5463 BFD_RELOC_X86_64_GOTTPOFF
},
5464 OPERAND_TYPE_IMM32_32S_DISP32
},
5465 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5466 BFD_RELOC_X86_64_TPOFF32
},
5467 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5468 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5470 OPERAND_TYPE_NONE
},
5471 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5472 BFD_RELOC_X86_64_DTPOFF32
},
5474 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5475 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5477 OPERAND_TYPE_NONE
},
5478 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5480 OPERAND_TYPE_NONE
},
5481 { "GOT", { BFD_RELOC_386_GOT32
,
5482 BFD_RELOC_X86_64_GOT32
},
5483 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5484 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5485 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5486 OPERAND_TYPE_IMM32_32S_DISP32
},
5487 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5488 BFD_RELOC_X86_64_TLSDESC_CALL
},
5489 OPERAND_TYPE_IMM32_32S_DISP32
},
5497 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5498 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5501 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5505 len
= strlen (gotrel
[j
].str
);
5506 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5508 if (gotrel
[j
].rel
[object_64bit
] != 0)
5511 char *tmpbuf
, *past_reloc
;
5513 *reloc
= gotrel
[j
].rel
[object_64bit
];
5519 if (flag_code
!= CODE_64BIT
)
5521 types
->bitfield
.imm32
= 1;
5522 types
->bitfield
.disp32
= 1;
5525 *types
= gotrel
[j
].types64
;
5528 if (GOT_symbol
== NULL
)
5529 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5531 /* The length of the first part of our input line. */
5532 first
= cp
- input_line_pointer
;
5534 /* The second part goes from after the reloc token until
5535 (and including) an end_of_line char or comma. */
5536 past_reloc
= cp
+ 1 + len
;
5538 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5540 second
= cp
+ 1 - past_reloc
;
5542 /* Allocate and copy string. The trailing NUL shouldn't
5543 be necessary, but be safe. */
5544 tmpbuf
= xmalloc (first
+ second
+ 2);
5545 memcpy (tmpbuf
, input_line_pointer
, first
);
5546 if (second
!= 0 && *past_reloc
!= ' ')
5547 /* Replace the relocation token with ' ', so that
5548 errors like foo@GOTOFF1 will be detected. */
5549 tmpbuf
[first
++] = ' ';
5550 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5551 tmpbuf
[first
+ second
] = '\0';
5555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5556 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5561 /* Might be a symbol version string. Don't as_bad here. */
5566 x86_cons (expressionS
*exp
, int size
)
5568 if (size
== 4 || (object_64bit
&& size
== 8))
5570 /* Handle @GOTOFF and the like in an expression. */
5572 char *gotfree_input_line
;
5575 save
= input_line_pointer
;
5576 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5577 if (gotfree_input_line
)
5578 input_line_pointer
= gotfree_input_line
;
5582 if (gotfree_input_line
)
5584 /* expression () has merrily parsed up to the end of line,
5585 or a comma - in the wrong buffer. Transfer how far
5586 input_line_pointer has moved to the right buffer. */
5587 input_line_pointer
= (save
5588 + (input_line_pointer
- gotfree_input_line
)
5590 free (gotfree_input_line
);
5591 if (exp
->X_op
== O_constant
5592 || exp
->X_op
== O_absent
5593 || exp
->X_op
== O_illegal
5594 || exp
->X_op
== O_register
5595 || exp
->X_op
== O_big
)
5597 char c
= *input_line_pointer
;
5598 *input_line_pointer
= 0;
5599 as_bad (_("missing or invalid expression `%s'"), save
);
5600 *input_line_pointer
= c
;
5609 static void signed_cons (int size
)
5611 if (flag_code
== CODE_64BIT
)
5619 pe_directive_secrel (dummy
)
5620 int dummy ATTRIBUTE_UNUSED
;
5627 if (exp
.X_op
== O_symbol
)
5628 exp
.X_op
= O_secrel
;
5630 emit_expr (&exp
, 4);
5632 while (*input_line_pointer
++ == ',');
5634 input_line_pointer
--;
5635 demand_empty_rest_of_line ();
5640 i386_immediate (char *imm_start
)
5642 char *save_input_line_pointer
;
5643 char *gotfree_input_line
;
5646 i386_operand_type types
;
5648 UINTS_SET (types
, ~0);
5650 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5652 as_bad (_("at most %d immediate operands are allowed"),
5653 MAX_IMMEDIATE_OPERANDS
);
5657 exp
= &im_expressions
[i
.imm_operands
++];
5658 i
.op
[this_operand
].imms
= exp
;
5660 if (is_space_char (*imm_start
))
5663 save_input_line_pointer
= input_line_pointer
;
5664 input_line_pointer
= imm_start
;
5666 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5667 if (gotfree_input_line
)
5668 input_line_pointer
= gotfree_input_line
;
5670 exp_seg
= expression (exp
);
5673 if (*input_line_pointer
)
5674 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5676 input_line_pointer
= save_input_line_pointer
;
5677 if (gotfree_input_line
)
5678 free (gotfree_input_line
);
5680 if (exp
->X_op
== O_absent
5681 || exp
->X_op
== O_illegal
5682 || exp
->X_op
== O_big
5683 || (gotfree_input_line
5684 && (exp
->X_op
== O_constant
5685 || exp
->X_op
== O_register
)))
5687 as_bad (_("missing or invalid immediate expression `%s'"),
5691 else if (exp
->X_op
== O_constant
)
5693 /* Size it properly later. */
5694 i
.types
[this_operand
].bitfield
.imm64
= 1;
5695 /* If BFD64, sign extend val. */
5696 if (!use_rela_relocations
5697 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5699 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5701 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5702 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5703 && exp_seg
!= absolute_section
5704 && exp_seg
!= text_section
5705 && exp_seg
!= data_section
5706 && exp_seg
!= bss_section
5707 && exp_seg
!= undefined_section
5708 && !bfd_is_com_section (exp_seg
))
5710 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5714 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5716 as_bad (_("illegal immediate register operand %s"), imm_start
);
5721 /* This is an address. The size of the address will be
5722 determined later, depending on destination register,
5723 suffix, or the default for the section. */
5724 i
.types
[this_operand
].bitfield
.imm8
= 1;
5725 i
.types
[this_operand
].bitfield
.imm16
= 1;
5726 i
.types
[this_operand
].bitfield
.imm32
= 1;
5727 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5728 i
.types
[this_operand
].bitfield
.imm64
= 1;
5729 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5737 i386_scale (char *scale
)
5740 char *save
= input_line_pointer
;
5742 input_line_pointer
= scale
;
5743 val
= get_absolute_expression ();
5748 i
.log2_scale_factor
= 0;
5751 i
.log2_scale_factor
= 1;
5754 i
.log2_scale_factor
= 2;
5757 i
.log2_scale_factor
= 3;
5761 char sep
= *input_line_pointer
;
5763 *input_line_pointer
= '\0';
5764 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5766 *input_line_pointer
= sep
;
5767 input_line_pointer
= save
;
5771 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5773 as_warn (_("scale factor of %d without an index register"),
5774 1 << i
.log2_scale_factor
);
5775 i
.log2_scale_factor
= 0;
5777 scale
= input_line_pointer
;
5778 input_line_pointer
= save
;
5783 i386_displacement (char *disp_start
, char *disp_end
)
5787 char *save_input_line_pointer
;
5788 char *gotfree_input_line
;
5790 i386_operand_type bigdisp
, types
= anydisp
;
5793 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5795 as_bad (_("at most %d displacement operands are allowed"),
5796 MAX_MEMORY_OPERANDS
);
5800 UINTS_CLEAR (bigdisp
);
5801 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5802 || (!current_templates
->start
->opcode_modifier
.jump
5803 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5805 bigdisp
.bitfield
.disp32
= 1;
5806 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5807 if (flag_code
== CODE_64BIT
)
5811 bigdisp
.bitfield
.disp32s
= 1;
5812 bigdisp
.bitfield
.disp64
= 1;
5815 else if ((flag_code
== CODE_16BIT
) ^ override
)
5817 bigdisp
.bitfield
.disp32
= 0;
5818 bigdisp
.bitfield
.disp16
= 1;
5823 /* For PC-relative branches, the width of the displacement
5824 is dependent upon data size, not address size. */
5825 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5826 if (flag_code
== CODE_64BIT
)
5828 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5829 bigdisp
.bitfield
.disp16
= 1;
5832 bigdisp
.bitfield
.disp32
= 1;
5833 bigdisp
.bitfield
.disp32s
= 1;
5839 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5841 : LONG_MNEM_SUFFIX
));
5842 bigdisp
.bitfield
.disp32
= 1;
5843 if ((flag_code
== CODE_16BIT
) ^ override
)
5845 bigdisp
.bitfield
.disp32
= 0;
5846 bigdisp
.bitfield
.disp16
= 1;
5850 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5853 exp
= &disp_expressions
[i
.disp_operands
];
5854 i
.op
[this_operand
].disps
= exp
;
5856 save_input_line_pointer
= input_line_pointer
;
5857 input_line_pointer
= disp_start
;
5858 END_STRING_AND_SAVE (disp_end
);
5860 #ifndef GCC_ASM_O_HACK
5861 #define GCC_ASM_O_HACK 0
5864 END_STRING_AND_SAVE (disp_end
+ 1);
5865 if (i
.types
[this_operand
].bitfield
.baseIndex
5866 && displacement_string_end
[-1] == '+')
5868 /* This hack is to avoid a warning when using the "o"
5869 constraint within gcc asm statements.
5872 #define _set_tssldt_desc(n,addr,limit,type) \
5873 __asm__ __volatile__ ( \
5875 "movw %w1,2+%0\n\t" \
5877 "movb %b1,4+%0\n\t" \
5878 "movb %4,5+%0\n\t" \
5879 "movb $0,6+%0\n\t" \
5880 "movb %h1,7+%0\n\t" \
5882 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5884 This works great except that the output assembler ends
5885 up looking a bit weird if it turns out that there is
5886 no offset. You end up producing code that looks like:
5899 So here we provide the missing zero. */
5901 *displacement_string_end
= '0';
5904 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5905 if (gotfree_input_line
)
5906 input_line_pointer
= gotfree_input_line
;
5908 exp_seg
= expression (exp
);
5911 if (*input_line_pointer
)
5912 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5914 RESTORE_END_STRING (disp_end
+ 1);
5916 input_line_pointer
= save_input_line_pointer
;
5917 if (gotfree_input_line
)
5918 free (gotfree_input_line
);
5921 /* We do this to make sure that the section symbol is in
5922 the symbol table. We will ultimately change the relocation
5923 to be relative to the beginning of the section. */
5924 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5925 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5926 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5928 if (exp
->X_op
!= O_symbol
)
5931 if (S_IS_LOCAL (exp
->X_add_symbol
)
5932 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5933 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5934 exp
->X_op
= O_subtract
;
5935 exp
->X_op_symbol
= GOT_symbol
;
5936 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
5937 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
5938 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5939 i
.reloc
[this_operand
] = BFD_RELOC_64
;
5941 i
.reloc
[this_operand
] = BFD_RELOC_32
;
5944 else if (exp
->X_op
== O_absent
5945 || exp
->X_op
== O_illegal
5946 || exp
->X_op
== O_big
5947 || (gotfree_input_line
5948 && (exp
->X_op
== O_constant
5949 || exp
->X_op
== O_register
)))
5952 as_bad (_("missing or invalid displacement expression `%s'"),
5957 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5958 else if (exp
->X_op
!= O_constant
5959 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
5960 && exp_seg
!= absolute_section
5961 && exp_seg
!= text_section
5962 && exp_seg
!= data_section
5963 && exp_seg
!= bss_section
5964 && exp_seg
!= undefined_section
5965 && !bfd_is_com_section (exp_seg
))
5967 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5972 RESTORE_END_STRING (disp_end
);
5974 /* Check if this is a displacement only operand. */
5975 bigdisp
= i
.types
[this_operand
];
5976 bigdisp
.bitfield
.disp8
= 0;
5977 bigdisp
.bitfield
.disp16
= 0;
5978 bigdisp
.bitfield
.disp32
= 0;
5979 bigdisp
.bitfield
.disp32s
= 0;
5980 bigdisp
.bitfield
.disp64
= 0;
5981 if (UINTS_ALL_ZERO (bigdisp
))
5982 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5988 /* Make sure the memory operand we've been dealt is valid.
5989 Return 1 on success, 0 on a failure. */
5992 i386_index_check (const char *operand_string
)
5995 #if INFER_ADDR_PREFIX
6001 if (flag_code
== CODE_64BIT
)
6004 && ((i
.prefix
[ADDR_PREFIX
] == 0
6005 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6006 || (i
.prefix
[ADDR_PREFIX
]
6007 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6009 || i
.base_reg
->reg_num
!=
6010 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6012 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6013 || (i
.prefix
[ADDR_PREFIX
] == 0
6014 && i
.index_reg
->reg_num
!= RegRiz
6015 && !i
.index_reg
->reg_type
.bitfield
.reg64
6017 || (i
.prefix
[ADDR_PREFIX
]
6018 && i
.index_reg
->reg_num
!= RegEiz
6019 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6024 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6028 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6029 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6031 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6032 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6034 && i
.base_reg
->reg_num
< 6
6035 && i
.index_reg
->reg_num
>= 6
6036 && i
.log2_scale_factor
== 0))))
6043 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6045 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6046 && i
.index_reg
->reg_num
!= RegEiz
)
6047 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6053 #if INFER_ADDR_PREFIX
6054 if (i
.prefix
[ADDR_PREFIX
] == 0)
6056 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6058 /* Change the size of any displacement too. At most one of
6059 Disp16 or Disp32 is set.
6060 FIXME. There doesn't seem to be any real need for separate
6061 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6062 Removing them would probably clean up the code quite a lot. */
6063 if (flag_code
!= CODE_64BIT
6064 && (i
.types
[this_operand
].bitfield
.disp16
6065 || i
.types
[this_operand
].bitfield
.disp32
))
6066 i
.types
[this_operand
]
6067 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6072 as_bad (_("`%s' is not a valid base/index expression"),
6076 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6078 flag_code_names
[flag_code
]);
6083 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6087 i386_att_operand (char *operand_string
)
6091 char *op_string
= operand_string
;
6093 if (is_space_char (*op_string
))
6096 /* We check for an absolute prefix (differentiating,
6097 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6098 if (*op_string
== ABSOLUTE_PREFIX
)
6101 if (is_space_char (*op_string
))
6103 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6106 /* Check if operand is a register. */
6107 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6109 i386_operand_type temp
;
6111 /* Check for a segment override by searching for ':' after a
6112 segment register. */
6114 if (is_space_char (*op_string
))
6116 if (*op_string
== ':'
6117 && (r
->reg_type
.bitfield
.sreg2
6118 || r
->reg_type
.bitfield
.sreg3
))
6123 i
.seg
[i
.mem_operands
] = &es
;
6126 i
.seg
[i
.mem_operands
] = &cs
;
6129 i
.seg
[i
.mem_operands
] = &ss
;
6132 i
.seg
[i
.mem_operands
] = &ds
;
6135 i
.seg
[i
.mem_operands
] = &fs
;
6138 i
.seg
[i
.mem_operands
] = &gs
;
6142 /* Skip the ':' and whitespace. */
6144 if (is_space_char (*op_string
))
6147 if (!is_digit_char (*op_string
)
6148 && !is_identifier_char (*op_string
)
6149 && *op_string
!= '('
6150 && *op_string
!= ABSOLUTE_PREFIX
)
6152 as_bad (_("bad memory operand `%s'"), op_string
);
6155 /* Handle case of %es:*foo. */
6156 if (*op_string
== ABSOLUTE_PREFIX
)
6159 if (is_space_char (*op_string
))
6161 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6163 goto do_memory_reference
;
6167 as_bad (_("junk `%s' after register"), op_string
);
6171 temp
.bitfield
.baseindex
= 0;
6172 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6174 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6175 i
.op
[this_operand
].regs
= r
;
6178 else if (*op_string
== REGISTER_PREFIX
)
6180 as_bad (_("bad register name `%s'"), op_string
);
6183 else if (*op_string
== IMMEDIATE_PREFIX
)
6186 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6188 as_bad (_("immediate operand illegal with absolute jump"));
6191 if (!i386_immediate (op_string
))
6194 else if (is_digit_char (*op_string
)
6195 || is_identifier_char (*op_string
)
6196 || *op_string
== '(')
6198 /* This is a memory reference of some sort. */
6201 /* Start and end of displacement string expression (if found). */
6202 char *displacement_string_start
;
6203 char *displacement_string_end
;
6205 do_memory_reference
:
6206 if ((i
.mem_operands
== 1
6207 && !current_templates
->start
->opcode_modifier
.isstring
)
6208 || i
.mem_operands
== 2)
6210 as_bad (_("too many memory references for `%s'"),
6211 current_templates
->start
->name
);
6215 /* Check for base index form. We detect the base index form by
6216 looking for an ')' at the end of the operand, searching
6217 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6219 base_string
= op_string
+ strlen (op_string
);
6222 if (is_space_char (*base_string
))
6225 /* If we only have a displacement, set-up for it to be parsed later. */
6226 displacement_string_start
= op_string
;
6227 displacement_string_end
= base_string
+ 1;
6229 if (*base_string
== ')')
6232 unsigned int parens_balanced
= 1;
6233 /* We've already checked that the number of left & right ()'s are
6234 equal, so this loop will not be infinite. */
6238 if (*base_string
== ')')
6240 if (*base_string
== '(')
6243 while (parens_balanced
);
6245 temp_string
= base_string
;
6247 /* Skip past '(' and whitespace. */
6249 if (is_space_char (*base_string
))
6252 if (*base_string
== ','
6253 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6256 displacement_string_end
= temp_string
;
6258 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6262 base_string
= end_op
;
6263 if (is_space_char (*base_string
))
6267 /* There may be an index reg or scale factor here. */
6268 if (*base_string
== ',')
6271 if (is_space_char (*base_string
))
6274 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6277 base_string
= end_op
;
6278 if (is_space_char (*base_string
))
6280 if (*base_string
== ',')
6283 if (is_space_char (*base_string
))
6286 else if (*base_string
!= ')')
6288 as_bad (_("expecting `,' or `)' "
6289 "after index register in `%s'"),
6294 else if (*base_string
== REGISTER_PREFIX
)
6296 as_bad (_("bad register name `%s'"), base_string
);
6300 /* Check for scale factor. */
6301 if (*base_string
!= ')')
6303 char *end_scale
= i386_scale (base_string
);
6308 base_string
= end_scale
;
6309 if (is_space_char (*base_string
))
6311 if (*base_string
!= ')')
6313 as_bad (_("expecting `)' "
6314 "after scale factor in `%s'"),
6319 else if (!i
.index_reg
)
6321 as_bad (_("expecting index register or scale factor "
6322 "after `,'; got '%c'"),
6327 else if (*base_string
!= ')')
6329 as_bad (_("expecting `,' or `)' "
6330 "after base register in `%s'"),
6335 else if (*base_string
== REGISTER_PREFIX
)
6337 as_bad (_("bad register name `%s'"), base_string
);
6342 /* If there's an expression beginning the operand, parse it,
6343 assuming displacement_string_start and
6344 displacement_string_end are meaningful. */
6345 if (displacement_string_start
!= displacement_string_end
)
6347 if (!i386_displacement (displacement_string_start
,
6348 displacement_string_end
))
6352 /* Special case for (%dx) while doing input/output op. */
6354 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
6356 && i
.log2_scale_factor
== 0
6357 && i
.seg
[i
.mem_operands
] == 0
6358 && !operand_type_check (i
.types
[this_operand
], disp
))
6360 UINTS_CLEAR (i
.types
[this_operand
]);
6361 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
6365 if (i386_index_check (operand_string
) == 0)
6371 /* It's not a memory operand; argh! */
6372 as_bad (_("invalid char %s beginning operand %d `%s'"),
6373 output_invalid (*op_string
),
6378 return 1; /* Normal return. */
6381 /* md_estimate_size_before_relax()
6383 Called just before relax() for rs_machine_dependent frags. The x86
6384 assembler uses these frags to handle variable size jump
6387 Any symbol that is now undefined will not become defined.
6388 Return the correct fr_subtype in the frag.
6389 Return the initial "guess for variable size of frag" to caller.
6390 The guess is actually the growth beyond the fixed part. Whatever
6391 we do to grow the fixed or variable part contributes to our
6395 md_estimate_size_before_relax (fragP
, segment
)
6399 /* We've already got fragP->fr_subtype right; all we have to do is
6400 check for un-relaxable symbols. On an ELF system, we can't relax
6401 an externally visible symbol, because it may be overridden by a
6403 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6406 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6407 || S_IS_WEAK (fragP
->fr_symbol
)))
6411 /* Symbol is undefined in this segment, or we need to keep a
6412 reloc so that weak symbols can be overridden. */
6413 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6414 enum bfd_reloc_code_real reloc_type
;
6415 unsigned char *opcode
;
6418 if (fragP
->fr_var
!= NO_RELOC
)
6419 reloc_type
= fragP
->fr_var
;
6421 reloc_type
= BFD_RELOC_16_PCREL
;
6423 reloc_type
= BFD_RELOC_32_PCREL
;
6425 old_fr_fix
= fragP
->fr_fix
;
6426 opcode
= (unsigned char *) fragP
->fr_opcode
;
6428 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6431 /* Make jmp (0xeb) a (d)word displacement jump. */
6433 fragP
->fr_fix
+= size
;
6434 fix_new (fragP
, old_fr_fix
, size
,
6436 fragP
->fr_offset
, 1,
6442 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6444 /* Negate the condition, and branch past an
6445 unconditional jump. */
6448 /* Insert an unconditional jump. */
6450 /* We added two extra opcode bytes, and have a two byte
6452 fragP
->fr_fix
+= 2 + 2;
6453 fix_new (fragP
, old_fr_fix
+ 2, 2,
6455 fragP
->fr_offset
, 1,
6462 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6467 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6469 fragP
->fr_offset
, 1,
6471 fixP
->fx_signed
= 1;
6475 /* This changes the byte-displacement jump 0x7N
6476 to the (d)word-displacement jump 0x0f,0x8N. */
6477 opcode
[1] = opcode
[0] + 0x10;
6478 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6479 /* We've added an opcode byte. */
6480 fragP
->fr_fix
+= 1 + size
;
6481 fix_new (fragP
, old_fr_fix
+ 1, size
,
6483 fragP
->fr_offset
, 1,
6488 BAD_CASE (fragP
->fr_subtype
);
6492 return fragP
->fr_fix
- old_fr_fix
;
6495 /* Guess size depending on current relax state. Initially the relax
6496 state will correspond to a short jump and we return 1, because
6497 the variable part of the frag (the branch offset) is one byte
6498 long. However, we can relax a section more than once and in that
6499 case we must either set fr_subtype back to the unrelaxed state,
6500 or return the value for the appropriate branch. */
6501 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6504 /* Called after relax() is finished.
6506 In: Address of frag.
6507 fr_type == rs_machine_dependent.
6508 fr_subtype is what the address relaxed to.
6510 Out: Any fixSs and constants are set up.
6511 Caller will turn frag into a ".space 0". */
6514 md_convert_frag (abfd
, sec
, fragP
)
6515 bfd
*abfd ATTRIBUTE_UNUSED
;
6516 segT sec ATTRIBUTE_UNUSED
;
6519 unsigned char *opcode
;
6520 unsigned char *where_to_put_displacement
= NULL
;
6521 offsetT target_address
;
6522 offsetT opcode_address
;
6523 unsigned int extension
= 0;
6524 offsetT displacement_from_opcode_start
;
6526 opcode
= (unsigned char *) fragP
->fr_opcode
;
6528 /* Address we want to reach in file space. */
6529 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6531 /* Address opcode resides at in file space. */
6532 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6534 /* Displacement from opcode start to fill into instruction. */
6535 displacement_from_opcode_start
= target_address
- opcode_address
;
6537 if ((fragP
->fr_subtype
& BIG
) == 0)
6539 /* Don't have to change opcode. */
6540 extension
= 1; /* 1 opcode + 1 displacement */
6541 where_to_put_displacement
= &opcode
[1];
6545 if (no_cond_jump_promotion
6546 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6547 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6548 _("long jump required"));
6550 switch (fragP
->fr_subtype
)
6552 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6553 extension
= 4; /* 1 opcode + 4 displacement */
6555 where_to_put_displacement
= &opcode
[1];
6558 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6559 extension
= 2; /* 1 opcode + 2 displacement */
6561 where_to_put_displacement
= &opcode
[1];
6564 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6565 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6566 extension
= 5; /* 2 opcode + 4 displacement */
6567 opcode
[1] = opcode
[0] + 0x10;
6568 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6569 where_to_put_displacement
= &opcode
[2];
6572 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6573 extension
= 3; /* 2 opcode + 2 displacement */
6574 opcode
[1] = opcode
[0] + 0x10;
6575 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6576 where_to_put_displacement
= &opcode
[2];
6579 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6584 where_to_put_displacement
= &opcode
[3];
6588 BAD_CASE (fragP
->fr_subtype
);
6593 /* If size if less then four we are sure that the operand fits,
6594 but if it's 4, then it could be that the displacement is larger
6596 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6598 && ((addressT
) (displacement_from_opcode_start
- extension
6599 + ((addressT
) 1 << 31))
6600 > (((addressT
) 2 << 31) - 1)))
6602 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6603 _("jump target out of range"));
6604 /* Make us emit 0. */
6605 displacement_from_opcode_start
= extension
;
6607 /* Now put displacement after opcode. */
6608 md_number_to_chars ((char *) where_to_put_displacement
,
6609 (valueT
) (displacement_from_opcode_start
- extension
),
6610 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6611 fragP
->fr_fix
+= extension
;
6614 /* Apply a fixup (fixS) to segment data, once it has been determined
6615 by our caller that we have all the info we need to fix it up.
6617 On the 386, immediates, displacements, and data pointers are all in
6618 the same (little-endian) format, so we don't need to care about which
6622 md_apply_fix (fixP
, valP
, seg
)
6623 /* The fix we're to put in. */
6625 /* Pointer to the value of the bits. */
6627 /* Segment fix is from. */
6628 segT seg ATTRIBUTE_UNUSED
;
6630 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6631 valueT value
= *valP
;
6633 #if !defined (TE_Mach)
6636 switch (fixP
->fx_r_type
)
6642 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6645 case BFD_RELOC_X86_64_32S
:
6646 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6649 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6652 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6657 if (fixP
->fx_addsy
!= NULL
6658 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6659 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6660 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6661 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6662 && !use_rela_relocations
)
6664 /* This is a hack. There should be a better way to handle this.
6665 This covers for the fact that bfd_install_relocation will
6666 subtract the current location (for partial_inplace, PC relative
6667 relocations); see more below. */
6671 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6674 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6676 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6679 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6682 || (symbol_section_p (fixP
->fx_addsy
)
6683 && sym_seg
!= absolute_section
))
6684 && !generic_force_reloc (fixP
))
6686 /* Yes, we add the values in twice. This is because
6687 bfd_install_relocation subtracts them out again. I think
6688 bfd_install_relocation is broken, but I don't dare change
6690 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6694 #if defined (OBJ_COFF) && defined (TE_PE)
6695 /* For some reason, the PE format does not store a
6696 section address offset for a PC relative symbol. */
6697 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6698 || S_IS_WEAK (fixP
->fx_addsy
))
6699 value
+= md_pcrel_from (fixP
);
6703 /* Fix a few things - the dynamic linker expects certain values here,
6704 and we must not disappoint it. */
6705 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6706 if (IS_ELF
&& fixP
->fx_addsy
)
6707 switch (fixP
->fx_r_type
)
6709 case BFD_RELOC_386_PLT32
:
6710 case BFD_RELOC_X86_64_PLT32
:
6711 /* Make the jump instruction point to the address of the operand. At
6712 runtime we merely add the offset to the actual PLT entry. */
6716 case BFD_RELOC_386_TLS_GD
:
6717 case BFD_RELOC_386_TLS_LDM
:
6718 case BFD_RELOC_386_TLS_IE_32
:
6719 case BFD_RELOC_386_TLS_IE
:
6720 case BFD_RELOC_386_TLS_GOTIE
:
6721 case BFD_RELOC_386_TLS_GOTDESC
:
6722 case BFD_RELOC_X86_64_TLSGD
:
6723 case BFD_RELOC_X86_64_TLSLD
:
6724 case BFD_RELOC_X86_64_GOTTPOFF
:
6725 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6726 value
= 0; /* Fully resolved at runtime. No addend. */
6728 case BFD_RELOC_386_TLS_LE
:
6729 case BFD_RELOC_386_TLS_LDO_32
:
6730 case BFD_RELOC_386_TLS_LE_32
:
6731 case BFD_RELOC_X86_64_DTPOFF32
:
6732 case BFD_RELOC_X86_64_DTPOFF64
:
6733 case BFD_RELOC_X86_64_TPOFF32
:
6734 case BFD_RELOC_X86_64_TPOFF64
:
6735 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6738 case BFD_RELOC_386_TLS_DESC_CALL
:
6739 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6740 value
= 0; /* Fully resolved at runtime. No addend. */
6741 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6745 case BFD_RELOC_386_GOT32
:
6746 case BFD_RELOC_X86_64_GOT32
:
6747 value
= 0; /* Fully resolved at runtime. No addend. */
6750 case BFD_RELOC_VTABLE_INHERIT
:
6751 case BFD_RELOC_VTABLE_ENTRY
:
6758 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6760 #endif /* !defined (TE_Mach) */
6762 /* Are we finished with this relocation now? */
6763 if (fixP
->fx_addsy
== NULL
)
6765 else if (use_rela_relocations
)
6767 fixP
->fx_no_overflow
= 1;
6768 /* Remember value for tc_gen_reloc. */
6769 fixP
->fx_addnumber
= value
;
6773 md_number_to_chars (p
, value
, fixP
->fx_size
);
6777 md_atof (int type
, char *litP
, int *sizeP
)
6779 /* This outputs the LITTLENUMs in REVERSE order;
6780 in accord with the bigendian 386. */
6781 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
6784 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6787 output_invalid (int c
)
6790 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6793 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6794 "(0x%x)", (unsigned char) c
);
6795 return output_invalid_buf
;
6798 /* REG_STRING starts *before* REGISTER_PREFIX. */
6800 static const reg_entry
*
6801 parse_real_register (char *reg_string
, char **end_op
)
6803 char *s
= reg_string
;
6805 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6808 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6809 if (*s
== REGISTER_PREFIX
)
6812 if (is_space_char (*s
))
6816 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6818 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6819 return (const reg_entry
*) NULL
;
6823 /* For naked regs, make sure that we are not dealing with an identifier.
6824 This prevents confusing an identifier like `eax_var' with register
6826 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6827 return (const reg_entry
*) NULL
;
6831 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6833 /* Handle floating point regs, allowing spaces in the (i) part. */
6834 if (r
== i386_regtab
/* %st is first entry of table */)
6836 if (is_space_char (*s
))
6841 if (is_space_char (*s
))
6843 if (*s
>= '0' && *s
<= '7')
6847 if (is_space_char (*s
))
6852 r
= hash_find (reg_hash
, "st(0)");
6857 /* We have "%st(" then garbage. */
6858 return (const reg_entry
*) NULL
;
6862 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6865 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
6866 return (const reg_entry
*) NULL
;
6869 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6870 || r
->reg_type
.bitfield
.reg64
)
6871 && (!cpu_arch_flags
.bitfield
.cpulm
6872 || !UINTS_EQUAL (r
->reg_type
, control
))
6873 && flag_code
!= CODE_64BIT
)
6874 return (const reg_entry
*) NULL
;
6879 /* REG_STRING starts *before* REGISTER_PREFIX. */
6881 static const reg_entry
*
6882 parse_register (char *reg_string
, char **end_op
)
6886 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6887 r
= parse_real_register (reg_string
, end_op
);
6892 char *save
= input_line_pointer
;
6896 input_line_pointer
= reg_string
;
6897 c
= get_symbol_end ();
6898 symbolP
= symbol_find (reg_string
);
6899 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6901 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6903 know (e
->X_op
== O_register
);
6904 know (e
->X_add_number
>= 0
6905 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6906 r
= i386_regtab
+ e
->X_add_number
;
6907 *end_op
= input_line_pointer
;
6909 *input_line_pointer
= c
;
6910 input_line_pointer
= save
;
6916 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6919 char *end
= input_line_pointer
;
6922 r
= parse_register (name
, &input_line_pointer
);
6923 if (r
&& end
<= input_line_pointer
)
6925 *nextcharP
= *input_line_pointer
;
6926 *input_line_pointer
= 0;
6927 e
->X_op
= O_register
;
6928 e
->X_add_number
= r
- i386_regtab
;
6931 input_line_pointer
= end
;
6937 md_operand (expressionS
*e
)
6939 if (*input_line_pointer
== REGISTER_PREFIX
)
6942 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
6946 e
->X_op
= O_register
;
6947 e
->X_add_number
= r
- i386_regtab
;
6948 input_line_pointer
= end
;
6954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6955 const char *md_shortopts
= "kVQ:sqn";
6957 const char *md_shortopts
= "qn";
6960 #define OPTION_32 (OPTION_MD_BASE + 0)
6961 #define OPTION_64 (OPTION_MD_BASE + 1)
6962 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6963 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6964 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6965 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6966 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6967 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6968 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6969 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6971 struct option md_longopts
[] =
6973 {"32", no_argument
, NULL
, OPTION_32
},
6974 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6975 {"64", no_argument
, NULL
, OPTION_64
},
6977 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
6978 {"march", required_argument
, NULL
, OPTION_MARCH
},
6979 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
6980 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
6981 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
6982 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
6983 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
6984 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
6985 {NULL
, no_argument
, NULL
, 0}
6987 size_t md_longopts_size
= sizeof (md_longopts
);
6990 md_parse_option (int c
, char *arg
)
6997 optimize_align_code
= 0;
7004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7005 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7006 should be emitted or not. FIXME: Not implemented. */
7010 /* -V: SVR4 argument to print version ID. */
7012 print_version_id ();
7015 /* -k: Ignore for FreeBSD compatibility. */
7020 /* -s: On i386 Solaris, this tells the native assembler to use
7021 .stab instead of .stab.excl. We always use .stab anyhow. */
7024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7027 const char **list
, **l
;
7029 list
= bfd_target_list ();
7030 for (l
= list
; *l
!= NULL
; l
++)
7031 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7032 || strcmp (*l
, "coff-x86-64") == 0
7033 || strcmp (*l
, "pe-x86-64") == 0
7034 || strcmp (*l
, "pei-x86-64") == 0)
7036 default_arch
= "x86_64";
7040 as_fatal (_("No compiled in support for x86_64"));
7047 default_arch
= "i386";
7051 #ifdef SVR4_COMMENT_CHARS
7056 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7058 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7062 i386_comment_chars
= n
;
7069 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7070 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7072 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7074 cpu_arch_isa
= cpu_arch
[i
].type
;
7075 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7076 if (!cpu_arch_tune_set
)
7078 cpu_arch_tune
= cpu_arch_isa
;
7079 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7084 if (i
>= ARRAY_SIZE (cpu_arch
))
7085 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7090 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7091 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7093 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7095 cpu_arch_tune_set
= 1;
7096 cpu_arch_tune
= cpu_arch
[i
].type
;
7097 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7101 if (i
>= ARRAY_SIZE (cpu_arch
))
7102 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7105 case OPTION_MMNEMONIC
:
7106 if (strcasecmp (arg
, "att") == 0)
7108 else if (strcasecmp (arg
, "intel") == 0)
7111 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7114 case OPTION_MSYNTAX
:
7115 if (strcasecmp (arg
, "att") == 0)
7117 else if (strcasecmp (arg
, "intel") == 0)
7120 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7123 case OPTION_MINDEX_REG
:
7124 allow_index_reg
= 1;
7127 case OPTION_MNAKED_REG
:
7128 allow_naked_reg
= 1;
7131 case OPTION_MOLD_GCC
:
7142 md_show_usage (stream
)
7145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7146 fprintf (stream
, _("\
7148 -V print assembler version number\n\
7151 fprintf (stream
, _("\
7152 -n Do not optimize code alignment\n\
7153 -q quieten some warnings\n"));
7154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7155 fprintf (stream
, _("\
7158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7159 fprintf (stream
, _("\
7160 --32/--64 generate 32bit/64bit code\n"));
7162 #ifdef SVR4_COMMENT_CHARS
7163 fprintf (stream
, _("\
7164 --divide do not treat `/' as a comment character\n"));
7166 fprintf (stream
, _("\
7167 --divide ignored\n"));
7169 fprintf (stream
, _("\
7170 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7171 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7172 core, core2, k6, athlon, k8, generic32, generic64\n"));
7173 fprintf (stream
, _("\
7174 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7175 fprintf (stream
, _("\
7176 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7177 fprintf (stream
, _("\
7178 -mindex-reg support pseudo index registers\n"));
7179 fprintf (stream
, _("\
7180 -mnaked-reg don't require `%%' prefix for registers\n"));
7181 fprintf (stream
, _("\
7182 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7185 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7186 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7188 /* Pick the target format to use. */
7191 i386_target_format (void)
7193 if (!strcmp (default_arch
, "x86_64"))
7195 set_code_flag (CODE_64BIT
);
7196 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7198 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7199 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7200 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7201 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7202 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7203 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7204 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
7205 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7206 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
7207 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7208 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7210 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7212 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7213 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7214 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7215 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7216 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7217 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7218 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
7219 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7220 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
7221 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7222 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7225 else if (!strcmp (default_arch
, "i386"))
7227 set_code_flag (CODE_32BIT
);
7228 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7230 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7231 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7232 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7234 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7236 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7237 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7238 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7242 as_fatal (_("Unknown architecture"));
7243 switch (OUTPUT_FLAVOR
)
7246 case bfd_target_coff_flavour
:
7247 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
7250 #ifdef OBJ_MAYBE_AOUT
7251 case bfd_target_aout_flavour
:
7252 return AOUT_TARGET_FORMAT
;
7254 #ifdef OBJ_MAYBE_COFF
7255 case bfd_target_coff_flavour
:
7258 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7259 case bfd_target_elf_flavour
:
7261 if (flag_code
== CODE_64BIT
)
7264 use_rela_relocations
= 1;
7266 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7275 #endif /* OBJ_MAYBE_ more than one */
7277 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7279 i386_elf_emit_arch_note (void)
7281 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7284 asection
*seg
= now_seg
;
7285 subsegT subseg
= now_subseg
;
7286 Elf_Internal_Note i_note
;
7287 Elf_External_Note e_note
;
7288 asection
*note_secp
;
7291 /* Create the .note section. */
7292 note_secp
= subseg_new (".note", 0);
7293 bfd_set_section_flags (stdoutput
,
7295 SEC_HAS_CONTENTS
| SEC_READONLY
);
7297 /* Process the arch string. */
7298 len
= strlen (cpu_arch_name
);
7300 i_note
.namesz
= len
+ 1;
7302 i_note
.type
= NT_ARCH
;
7303 p
= frag_more (sizeof (e_note
.namesz
));
7304 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
7305 p
= frag_more (sizeof (e_note
.descsz
));
7306 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
7307 p
= frag_more (sizeof (e_note
.type
));
7308 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
7309 p
= frag_more (len
+ 1);
7310 strcpy (p
, cpu_arch_name
);
7312 frag_align (2, 0, 0);
7314 subseg_set (seg
, subseg
);
7320 md_undefined_symbol (name
)
7323 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
7324 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
7325 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
7326 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
7330 if (symbol_find (name
))
7331 as_bad (_("GOT already in symbol table"));
7332 GOT_symbol
= symbol_new (name
, undefined_section
,
7333 (valueT
) 0, &zero_address_frag
);
7340 /* Round up a section size to the appropriate boundary. */
7343 md_section_align (segment
, size
)
7344 segT segment ATTRIBUTE_UNUSED
;
7347 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7348 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
7350 /* For a.out, force the section size to be aligned. If we don't do
7351 this, BFD will align it for us, but it will not write out the
7352 final bytes of the section. This may be a bug in BFD, but it is
7353 easier to fix it here since that is how the other a.out targets
7357 align
= bfd_get_section_alignment (stdoutput
, segment
);
7358 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7365 /* On the i386, PC-relative offsets are relative to the start of the
7366 next instruction. That is, the address of the offset, plus its
7367 size, since the offset is always the last part of the insn. */
7370 md_pcrel_from (fixS
*fixP
)
7372 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7378 s_bss (int ignore ATTRIBUTE_UNUSED
)
7382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7384 obj_elf_section_change_hook ();
7386 temp
= get_absolute_expression ();
7387 subseg_set (bss_section
, (subsegT
) temp
);
7388 demand_empty_rest_of_line ();
7394 i386_validate_fix (fixS
*fixp
)
7396 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
7398 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
7402 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
7407 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
7409 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
7416 tc_gen_reloc (section
, fixp
)
7417 asection
*section ATTRIBUTE_UNUSED
;
7421 bfd_reloc_code_real_type code
;
7423 switch (fixp
->fx_r_type
)
7425 case BFD_RELOC_X86_64_PLT32
:
7426 case BFD_RELOC_X86_64_GOT32
:
7427 case BFD_RELOC_X86_64_GOTPCREL
:
7428 case BFD_RELOC_386_PLT32
:
7429 case BFD_RELOC_386_GOT32
:
7430 case BFD_RELOC_386_GOTOFF
:
7431 case BFD_RELOC_386_GOTPC
:
7432 case BFD_RELOC_386_TLS_GD
:
7433 case BFD_RELOC_386_TLS_LDM
:
7434 case BFD_RELOC_386_TLS_LDO_32
:
7435 case BFD_RELOC_386_TLS_IE_32
:
7436 case BFD_RELOC_386_TLS_IE
:
7437 case BFD_RELOC_386_TLS_GOTIE
:
7438 case BFD_RELOC_386_TLS_LE_32
:
7439 case BFD_RELOC_386_TLS_LE
:
7440 case BFD_RELOC_386_TLS_GOTDESC
:
7441 case BFD_RELOC_386_TLS_DESC_CALL
:
7442 case BFD_RELOC_X86_64_TLSGD
:
7443 case BFD_RELOC_X86_64_TLSLD
:
7444 case BFD_RELOC_X86_64_DTPOFF32
:
7445 case BFD_RELOC_X86_64_DTPOFF64
:
7446 case BFD_RELOC_X86_64_GOTTPOFF
:
7447 case BFD_RELOC_X86_64_TPOFF32
:
7448 case BFD_RELOC_X86_64_TPOFF64
:
7449 case BFD_RELOC_X86_64_GOTOFF64
:
7450 case BFD_RELOC_X86_64_GOTPC32
:
7451 case BFD_RELOC_X86_64_GOT64
:
7452 case BFD_RELOC_X86_64_GOTPCREL64
:
7453 case BFD_RELOC_X86_64_GOTPC64
:
7454 case BFD_RELOC_X86_64_GOTPLT64
:
7455 case BFD_RELOC_X86_64_PLTOFF64
:
7456 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7457 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7459 case BFD_RELOC_VTABLE_ENTRY
:
7460 case BFD_RELOC_VTABLE_INHERIT
:
7462 case BFD_RELOC_32_SECREL
:
7464 code
= fixp
->fx_r_type
;
7466 case BFD_RELOC_X86_64_32S
:
7467 if (!fixp
->fx_pcrel
)
7469 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7470 code
= fixp
->fx_r_type
;
7476 switch (fixp
->fx_size
)
7479 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7480 _("can not do %d byte pc-relative relocation"),
7482 code
= BFD_RELOC_32_PCREL
;
7484 case 1: code
= BFD_RELOC_8_PCREL
; break;
7485 case 2: code
= BFD_RELOC_16_PCREL
; break;
7486 case 4: code
= BFD_RELOC_32_PCREL
; break;
7488 case 8: code
= BFD_RELOC_64_PCREL
; break;
7494 switch (fixp
->fx_size
)
7497 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7498 _("can not do %d byte relocation"),
7500 code
= BFD_RELOC_32
;
7502 case 1: code
= BFD_RELOC_8
; break;
7503 case 2: code
= BFD_RELOC_16
; break;
7504 case 4: code
= BFD_RELOC_32
; break;
7506 case 8: code
= BFD_RELOC_64
; break;
7513 if ((code
== BFD_RELOC_32
7514 || code
== BFD_RELOC_32_PCREL
7515 || code
== BFD_RELOC_X86_64_32S
)
7517 && fixp
->fx_addsy
== GOT_symbol
)
7520 code
= BFD_RELOC_386_GOTPC
;
7522 code
= BFD_RELOC_X86_64_GOTPC32
;
7524 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7526 && fixp
->fx_addsy
== GOT_symbol
)
7528 code
= BFD_RELOC_X86_64_GOTPC64
;
7531 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7532 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7533 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7535 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7537 if (!use_rela_relocations
)
7539 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7540 vtable entry to be used in the relocation's section offset. */
7541 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7542 rel
->address
= fixp
->fx_offset
;
7546 /* Use the rela in 64bit mode. */
7549 if (!fixp
->fx_pcrel
)
7550 rel
->addend
= fixp
->fx_offset
;
7554 case BFD_RELOC_X86_64_PLT32
:
7555 case BFD_RELOC_X86_64_GOT32
:
7556 case BFD_RELOC_X86_64_GOTPCREL
:
7557 case BFD_RELOC_X86_64_TLSGD
:
7558 case BFD_RELOC_X86_64_TLSLD
:
7559 case BFD_RELOC_X86_64_GOTTPOFF
:
7560 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7561 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7562 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7565 rel
->addend
= (section
->vma
7567 + fixp
->fx_addnumber
7568 + md_pcrel_from (fixp
));
7573 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7574 if (rel
->howto
== NULL
)
7576 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7577 _("cannot represent relocation type %s"),
7578 bfd_get_reloc_code_name (code
));
7579 /* Set howto to a garbage value so that we can keep going. */
7580 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7581 assert (rel
->howto
!= NULL
);
7588 /* Parse operands using Intel syntax. This implements a recursive descent
7589 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7592 FIXME: We do not recognize the full operand grammar defined in the MASM
7593 documentation. In particular, all the structure/union and
7594 high-level macro operands are missing.
7596 Uppercase words are terminals, lower case words are non-terminals.
7597 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7598 bars '|' denote choices. Most grammar productions are implemented in
7599 functions called 'intel_<production>'.
7601 Initial production is 'expr'.
7607 binOp & | AND | \| | OR | ^ | XOR
7609 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7611 constant digits [[ radixOverride ]]
7613 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7651 => expr expr cmpOp e04
7654 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7655 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7657 hexdigit a | b | c | d | e | f
7658 | A | B | C | D | E | F
7664 mulOp * | / | % | MOD | << | SHL | >> | SHR
7668 register specialRegister
7672 segmentRegister CS | DS | ES | FS | GS | SS
7674 specialRegister CR0 | CR2 | CR3 | CR4
7675 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7676 | TR3 | TR4 | TR5 | TR6 | TR7
7678 We simplify the grammar in obvious places (e.g., register parsing is
7679 done by calling parse_register) and eliminate immediate left recursion
7680 to implement a recursive-descent parser.
7684 expr' cmpOp e04 expr'
7735 /* Parsing structure for the intel syntax parser. Used to implement the
7736 semantic actions for the operand grammar. */
7737 struct intel_parser_s
7739 char *op_string
; /* The string being parsed. */
7740 int got_a_float
; /* Whether the operand is a float. */
7741 int op_modifier
; /* Operand modifier. */
7742 int is_mem
; /* 1 if operand is memory reference. */
7743 int in_offset
; /* >=1 if parsing operand of offset. */
7744 int in_bracket
; /* >=1 if parsing operand in brackets. */
7745 const reg_entry
*reg
; /* Last register reference found. */
7746 char *disp
; /* Displacement string being built. */
7747 char *next_operand
; /* Resume point when splitting operands. */
7750 static struct intel_parser_s intel_parser
;
7752 /* Token structure for parsing intel syntax. */
7755 int code
; /* Token code. */
7756 const reg_entry
*reg
; /* Register entry for register tokens. */
7757 char *str
; /* String representation. */
7760 static struct intel_token cur_token
, prev_token
;
7762 /* Token codes for the intel parser. Since T_SHORT is already used
7763 by COFF, undefine it first to prevent a warning. */
7782 /* Prototypes for intel parser functions. */
7783 static int intel_match_token (int);
7784 static void intel_putback_token (void);
7785 static void intel_get_token (void);
7786 static int intel_expr (void);
7787 static int intel_e04 (void);
7788 static int intel_e05 (void);
7789 static int intel_e06 (void);
7790 static int intel_e09 (void);
7791 static int intel_e10 (void);
7792 static int intel_e11 (void);
7795 i386_intel_operand (char *operand_string
, int got_a_float
)
7800 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7801 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7805 /* Initialize token holders. */
7806 cur_token
.code
= prev_token
.code
= T_NIL
;
7807 cur_token
.reg
= prev_token
.reg
= NULL
;
7808 cur_token
.str
= prev_token
.str
= NULL
;
7810 /* Initialize parser structure. */
7811 intel_parser
.got_a_float
= got_a_float
;
7812 intel_parser
.op_modifier
= 0;
7813 intel_parser
.is_mem
= 0;
7814 intel_parser
.in_offset
= 0;
7815 intel_parser
.in_bracket
= 0;
7816 intel_parser
.reg
= NULL
;
7817 intel_parser
.disp
[0] = '\0';
7818 intel_parser
.next_operand
= NULL
;
7820 /* Read the first token and start the parser. */
7822 ret
= intel_expr ();
7827 if (cur_token
.code
!= T_NIL
)
7829 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7830 current_templates
->start
->name
, cur_token
.str
);
7833 /* If we found a memory reference, hand it over to i386_displacement
7834 to fill in the rest of the operand fields. */
7835 else if (intel_parser
.is_mem
)
7837 if ((i
.mem_operands
== 1
7838 && !current_templates
->start
->opcode_modifier
.isstring
)
7839 || i
.mem_operands
== 2)
7841 as_bad (_("too many memory references for '%s'"),
7842 current_templates
->start
->name
);
7847 char *s
= intel_parser
.disp
;
7850 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7851 /* See the comments in intel_bracket_expr. */
7852 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7854 /* Add the displacement expression. */
7856 ret
= i386_displacement (s
, s
+ strlen (s
));
7859 /* Swap base and index in 16-bit memory operands like
7860 [si+bx]. Since i386_index_check is also used in AT&T
7861 mode we have to do that here. */
7864 && i
.base_reg
->reg_type
.bitfield
.reg16
7865 && i
.index_reg
->reg_type
.bitfield
.reg16
7866 && i
.base_reg
->reg_num
>= 6
7867 && i
.index_reg
->reg_num
< 6)
7869 const reg_entry
*base
= i
.index_reg
;
7871 i
.index_reg
= i
.base_reg
;
7874 ret
= i386_index_check (operand_string
);
7879 /* Constant and OFFSET expressions are handled by i386_immediate. */
7880 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7881 || intel_parser
.reg
== NULL
)
7882 ret
= i386_immediate (intel_parser
.disp
);
7884 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7886 if (!ret
|| !intel_parser
.next_operand
)
7888 intel_parser
.op_string
= intel_parser
.next_operand
;
7889 this_operand
= i
.operands
++;
7890 i
.types
[this_operand
].bitfield
.unspecified
= 1;
7894 free (intel_parser
.disp
);
7899 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7903 expr' cmpOp e04 expr'
7908 /* XXX Implement the comparison operators. */
7909 return intel_e04 ();
7926 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7927 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7929 if (cur_token
.code
== '+')
7931 else if (cur_token
.code
== '-')
7932 nregs
= NUM_ADDRESS_REGS
;
7936 strcat (intel_parser
.disp
, cur_token
.str
);
7937 intel_match_token (cur_token
.code
);
7948 int nregs
= ~NUM_ADDRESS_REGS
;
7955 if (cur_token
.code
== '&'
7956 || cur_token
.code
== '|'
7957 || cur_token
.code
== '^')
7961 str
[0] = cur_token
.code
;
7963 strcat (intel_parser
.disp
, str
);
7968 intel_match_token (cur_token
.code
);
7973 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7974 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
7985 int nregs
= ~NUM_ADDRESS_REGS
;
7992 if (cur_token
.code
== '*'
7993 || cur_token
.code
== '/'
7994 || cur_token
.code
== '%')
7998 str
[0] = cur_token
.code
;
8000 strcat (intel_parser
.disp
, str
);
8002 else if (cur_token
.code
== T_SHL
)
8003 strcat (intel_parser
.disp
, "<<");
8004 else if (cur_token
.code
== T_SHR
)
8005 strcat (intel_parser
.disp
, ">>");
8009 intel_match_token (cur_token
.code
);
8014 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8015 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8033 int nregs
= ~NUM_ADDRESS_REGS
;
8038 /* Don't consume constants here. */
8039 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8041 /* Need to look one token ahead - if the next token
8042 is a constant, the current token is its sign. */
8045 intel_match_token (cur_token
.code
);
8046 next_code
= cur_token
.code
;
8047 intel_putback_token ();
8048 if (next_code
== T_CONST
)
8052 /* e09 OFFSET e09 */
8053 if (cur_token
.code
== T_OFFSET
)
8056 ++intel_parser
.in_offset
;
8060 else if (cur_token
.code
== T_SHORT
)
8061 intel_parser
.op_modifier
|= 1 << T_SHORT
;
8064 else if (cur_token
.code
== '+')
8065 strcat (intel_parser
.disp
, "+");
8070 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
8076 str
[0] = cur_token
.code
;
8078 strcat (intel_parser
.disp
, str
);
8085 intel_match_token (cur_token
.code
);
8093 /* e09' PTR e10 e09' */
8094 if (cur_token
.code
== T_PTR
)
8098 if (prev_token
.code
== T_BYTE
)
8100 suffix
= BYTE_MNEM_SUFFIX
;
8101 i
.types
[this_operand
].bitfield
.byte
= 1;
8104 else if (prev_token
.code
== T_WORD
)
8106 if (current_templates
->start
->name
[0] == 'l'
8107 && current_templates
->start
->name
[2] == 's'
8108 && current_templates
->start
->name
[3] == 0)
8109 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8110 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
8111 suffix
= SHORT_MNEM_SUFFIX
;
8113 suffix
= WORD_MNEM_SUFFIX
;
8114 i
.types
[this_operand
].bitfield
.word
= 1;
8117 else if (prev_token
.code
== T_DWORD
)
8119 if (current_templates
->start
->name
[0] == 'l'
8120 && current_templates
->start
->name
[2] == 's'
8121 && current_templates
->start
->name
[3] == 0)
8122 suffix
= WORD_MNEM_SUFFIX
;
8123 else if (flag_code
== CODE_16BIT
8124 && (current_templates
->start
->opcode_modifier
.jump
8125 || current_templates
->start
->opcode_modifier
.jumpdword
))
8126 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8127 else if (intel_parser
.got_a_float
== 1) /* "f..." */
8128 suffix
= SHORT_MNEM_SUFFIX
;
8130 suffix
= LONG_MNEM_SUFFIX
;
8131 i
.types
[this_operand
].bitfield
.dword
= 1;
8134 else if (prev_token
.code
== T_FWORD
)
8136 if (current_templates
->start
->name
[0] == 'l'
8137 && current_templates
->start
->name
[2] == 's'
8138 && current_templates
->start
->name
[3] == 0)
8139 suffix
= LONG_MNEM_SUFFIX
;
8140 else if (!intel_parser
.got_a_float
)
8142 if (flag_code
== CODE_16BIT
)
8143 add_prefix (DATA_PREFIX_OPCODE
);
8144 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8147 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8148 i
.types
[this_operand
].bitfield
.fword
= 1;
8151 else if (prev_token
.code
== T_QWORD
)
8153 if (intel_parser
.got_a_float
== 1) /* "f..." */
8154 suffix
= LONG_MNEM_SUFFIX
;
8156 suffix
= QWORD_MNEM_SUFFIX
;
8157 i
.types
[this_operand
].bitfield
.qword
= 1;
8160 else if (prev_token
.code
== T_TBYTE
)
8162 if (intel_parser
.got_a_float
== 1)
8163 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8165 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8168 else if (prev_token
.code
== T_XMMWORD
)
8170 suffix
= XMMWORD_MNEM_SUFFIX
;
8171 i
.types
[this_operand
].bitfield
.xmmword
= 1;
8176 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
8180 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8182 /* Operands for jump/call using 'ptr' notation denote absolute
8184 if (current_templates
->start
->opcode_modifier
.jump
8185 || current_templates
->start
->opcode_modifier
.jumpdword
)
8186 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8188 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
8192 else if (i
.suffix
!= suffix
)
8194 as_bad (_("Conflicting operand modifiers"));
8200 /* e09' : e10 e09' */
8201 else if (cur_token
.code
== ':')
8203 if (prev_token
.code
!= T_REG
)
8205 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8206 segment/group identifier (which we don't have), using comma
8207 as the operand separator there is even less consistent, since
8208 there all branches only have a single operand. */
8209 if (this_operand
!= 0
8210 || intel_parser
.in_offset
8211 || intel_parser
.in_bracket
8212 || (!current_templates
->start
->opcode_modifier
.jump
8213 && !current_templates
->start
->opcode_modifier
.jumpdword
8214 && !current_templates
->start
->opcode_modifier
.jumpintersegment
8215 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
8216 return intel_match_token (T_NIL
);
8217 /* Remember the start of the 2nd operand and terminate 1st
8219 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8220 another expression), but it gets at least the simplest case
8221 (a plain number or symbol on the left side) right. */
8222 intel_parser
.next_operand
= intel_parser
.op_string
;
8223 *--intel_parser
.op_string
= '\0';
8224 return intel_match_token (':');
8232 intel_match_token (cur_token
.code
);
8238 --intel_parser
.in_offset
;
8241 if (NUM_ADDRESS_REGS
> nregs
)
8243 as_bad (_("Invalid operand to `OFFSET'"));
8246 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
8249 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8250 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
8255 intel_bracket_expr (void)
8257 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
8258 const char *start
= intel_parser
.op_string
;
8261 if (i
.op
[this_operand
].regs
)
8262 return intel_match_token (T_NIL
);
8264 intel_match_token ('[');
8266 /* Mark as a memory operand only if it's not already known to be an
8267 offset expression. If it's an offset expression, we need to keep
8269 if (!intel_parser
.in_offset
)
8271 ++intel_parser
.in_bracket
;
8273 /* Operands for jump/call inside brackets denote absolute addresses. */
8274 if (current_templates
->start
->opcode_modifier
.jump
8275 || current_templates
->start
->opcode_modifier
.jumpdword
)
8276 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8278 /* Unfortunately gas always diverged from MASM in a respect that can't
8279 be easily fixed without risking to break code sequences likely to be
8280 encountered (the testsuite even check for this): MASM doesn't consider
8281 an expression inside brackets unconditionally as a memory reference.
8282 When that is e.g. a constant, an offset expression, or the sum of the
8283 two, this is still taken as a constant load. gas, however, always
8284 treated these as memory references. As a compromise, we'll try to make
8285 offset expressions inside brackets work the MASM way (since that's
8286 less likely to be found in real world code), but make constants alone
8287 continue to work the traditional gas way. In either case, issue a
8289 intel_parser
.op_modifier
&= ~was_offset
;
8292 strcat (intel_parser
.disp
, "[");
8294 /* Add a '+' to the displacement string if necessary. */
8295 if (*intel_parser
.disp
!= '\0'
8296 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
8297 strcat (intel_parser
.disp
, "+");
8300 && (len
= intel_parser
.op_string
- start
- 1,
8301 intel_match_token (']')))
8303 /* Preserve brackets when the operand is an offset expression. */
8304 if (intel_parser
.in_offset
)
8305 strcat (intel_parser
.disp
, "]");
8308 --intel_parser
.in_bracket
;
8309 if (i
.base_reg
|| i
.index_reg
)
8310 intel_parser
.is_mem
= 1;
8311 if (!intel_parser
.is_mem
)
8313 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8314 /* Defer the warning until all of the operand was parsed. */
8315 intel_parser
.is_mem
= -1;
8316 else if (!quiet_warnings
)
8317 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8318 len
, start
, len
, start
);
8321 intel_parser
.op_modifier
|= was_offset
;
8338 while (cur_token
.code
== '[')
8340 if (!intel_bracket_expr ())
8365 switch (cur_token
.code
)
8369 intel_match_token ('(');
8370 strcat (intel_parser
.disp
, "(");
8372 if (intel_expr () && intel_match_token (')'))
8374 strcat (intel_parser
.disp
, ")");
8381 return intel_bracket_expr ();
8386 strcat (intel_parser
.disp
, cur_token
.str
);
8387 intel_match_token (cur_token
.code
);
8389 /* Mark as a memory operand only if it's not already known to be an
8390 offset expression. */
8391 if (!intel_parser
.in_offset
)
8392 intel_parser
.is_mem
= 1;
8399 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
8401 intel_match_token (T_REG
);
8403 /* Check for segment change. */
8404 if (cur_token
.code
== ':')
8406 if (!reg
->reg_type
.bitfield
.sreg2
8407 && !reg
->reg_type
.bitfield
.sreg3
)
8409 as_bad (_("`%s' is not a valid segment register"),
8413 else if (i
.seg
[i
.mem_operands
])
8414 as_warn (_("Extra segment override ignored"));
8417 if (!intel_parser
.in_offset
)
8418 intel_parser
.is_mem
= 1;
8419 switch (reg
->reg_num
)
8422 i
.seg
[i
.mem_operands
] = &es
;
8425 i
.seg
[i
.mem_operands
] = &cs
;
8428 i
.seg
[i
.mem_operands
] = &ss
;
8431 i
.seg
[i
.mem_operands
] = &ds
;
8434 i
.seg
[i
.mem_operands
] = &fs
;
8437 i
.seg
[i
.mem_operands
] = &gs
;
8443 /* Not a segment register. Check for register scaling. */
8444 else if (cur_token
.code
== '*')
8446 if (!intel_parser
.in_bracket
)
8448 as_bad (_("Register scaling only allowed in memory operands"));
8452 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8453 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8454 else if (i
.index_reg
)
8455 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8457 /* What follows must be a valid scale. */
8458 intel_match_token ('*');
8460 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8462 /* Set the scale after setting the register (otherwise,
8463 i386_scale will complain) */
8464 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8466 char *str
, sign
= cur_token
.code
;
8467 intel_match_token (cur_token
.code
);
8468 if (cur_token
.code
!= T_CONST
)
8470 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8474 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8475 strcpy (str
+ 1, cur_token
.str
);
8477 if (!i386_scale (str
))
8481 else if (!i386_scale (cur_token
.str
))
8483 intel_match_token (cur_token
.code
);
8486 /* No scaling. If this is a memory operand, the register is either a
8487 base register (first occurrence) or an index register (second
8489 else if (intel_parser
.in_bracket
)
8494 else if (!i
.index_reg
)
8498 as_bad (_("Too many register references in memory operand"));
8502 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8505 /* It's neither base nor index. */
8506 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8508 i386_operand_type temp
= reg
->reg_type
;
8509 temp
.bitfield
.baseindex
= 0;
8510 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8512 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8513 i
.op
[this_operand
].regs
= reg
;
8518 as_bad (_("Invalid use of register"));
8522 /* Since registers are not part of the displacement string (except
8523 when we're parsing offset operands), we may need to remove any
8524 preceding '+' from the displacement string. */
8525 if (*intel_parser
.disp
!= '\0'
8526 && !intel_parser
.in_offset
)
8528 char *s
= intel_parser
.disp
;
8529 s
+= strlen (s
) - 1;
8552 intel_match_token (cur_token
.code
);
8554 if (cur_token
.code
== T_PTR
)
8557 /* It must have been an identifier. */
8558 intel_putback_token ();
8559 cur_token
.code
= T_ID
;
8565 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8569 /* The identifier represents a memory reference only if it's not
8570 preceded by an offset modifier and if it's not an equate. */
8571 symbolP
= symbol_find(cur_token
.str
);
8572 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8573 intel_parser
.is_mem
= 1;
8581 char *save_str
, sign
= 0;
8583 /* Allow constants that start with `+' or `-'. */
8584 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8586 sign
= cur_token
.code
;
8587 intel_match_token (cur_token
.code
);
8588 if (cur_token
.code
!= T_CONST
)
8590 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8596 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8597 strcpy (save_str
+ !!sign
, cur_token
.str
);
8601 /* Get the next token to check for register scaling. */
8602 intel_match_token (cur_token
.code
);
8604 /* Check if this constant is a scaling factor for an
8606 if (cur_token
.code
== '*')
8608 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8610 const reg_entry
*reg
= cur_token
.reg
;
8612 if (!intel_parser
.in_bracket
)
8614 as_bad (_("Register scaling only allowed "
8615 "in memory operands"));
8619 /* Disallow things like [1*si].
8620 sp and esp are invalid as index. */
8621 if (reg
->reg_type
.bitfield
.reg16
)
8622 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8623 else if (i
.index_reg
)
8624 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8626 /* The constant is followed by `* reg', so it must be
8629 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8631 /* Set the scale after setting the register (otherwise,
8632 i386_scale will complain) */
8633 if (!i386_scale (save_str
))
8635 intel_match_token (T_REG
);
8637 /* Since registers are not part of the displacement
8638 string, we may need to remove any preceding '+' from
8639 the displacement string. */
8640 if (*intel_parser
.disp
!= '\0')
8642 char *s
= intel_parser
.disp
;
8643 s
+= strlen (s
) - 1;
8653 /* The constant was not used for register scaling. Since we have
8654 already consumed the token following `*' we now need to put it
8655 back in the stream. */
8656 intel_putback_token ();
8659 /* Add the constant to the displacement string. */
8660 strcat (intel_parser
.disp
, save_str
);
8667 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8671 /* Match the given token against cur_token. If they match, read the next
8672 token from the operand string. */
8674 intel_match_token (int code
)
8676 if (cur_token
.code
== code
)
8683 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8688 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8690 intel_get_token (void)
8693 const reg_entry
*reg
;
8694 struct intel_token new_token
;
8696 new_token
.code
= T_NIL
;
8697 new_token
.reg
= NULL
;
8698 new_token
.str
= NULL
;
8700 /* Free the memory allocated to the previous token and move
8701 cur_token to prev_token. */
8703 free (prev_token
.str
);
8705 prev_token
= cur_token
;
8707 /* Skip whitespace. */
8708 while (is_space_char (*intel_parser
.op_string
))
8709 intel_parser
.op_string
++;
8711 /* Return an empty token if we find nothing else on the line. */
8712 if (*intel_parser
.op_string
== '\0')
8714 cur_token
= new_token
;
8718 /* The new token cannot be larger than the remainder of the operand
8720 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8721 new_token
.str
[0] = '\0';
8723 if (strchr ("0123456789", *intel_parser
.op_string
))
8725 char *p
= new_token
.str
;
8726 char *q
= intel_parser
.op_string
;
8727 new_token
.code
= T_CONST
;
8729 /* Allow any kind of identifier char to encompass floating point and
8730 hexadecimal numbers. */
8731 while (is_identifier_char (*q
))
8735 /* Recognize special symbol names [0-9][bf]. */
8736 if (strlen (intel_parser
.op_string
) == 2
8737 && (intel_parser
.op_string
[1] == 'b'
8738 || intel_parser
.op_string
[1] == 'f'))
8739 new_token
.code
= T_ID
;
8742 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8744 size_t len
= end_op
- intel_parser
.op_string
;
8746 new_token
.code
= T_REG
;
8747 new_token
.reg
= reg
;
8749 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8750 new_token
.str
[len
] = '\0';
8753 else if (is_identifier_char (*intel_parser
.op_string
))
8755 char *p
= new_token
.str
;
8756 char *q
= intel_parser
.op_string
;
8758 /* A '.' or '$' followed by an identifier char is an identifier.
8759 Otherwise, it's operator '.' followed by an expression. */
8760 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8762 new_token
.code
= '.';
8763 new_token
.str
[0] = '.';
8764 new_token
.str
[1] = '\0';
8768 while (is_identifier_char (*q
) || *q
== '@')
8772 if (strcasecmp (new_token
.str
, "NOT") == 0)
8773 new_token
.code
= '~';
8775 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8776 new_token
.code
= '%';
8778 else if (strcasecmp (new_token
.str
, "AND") == 0)
8779 new_token
.code
= '&';
8781 else if (strcasecmp (new_token
.str
, "OR") == 0)
8782 new_token
.code
= '|';
8784 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8785 new_token
.code
= '^';
8787 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8788 new_token
.code
= T_SHL
;
8790 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8791 new_token
.code
= T_SHR
;
8793 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8794 new_token
.code
= T_BYTE
;
8796 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8797 new_token
.code
= T_WORD
;
8799 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8800 new_token
.code
= T_DWORD
;
8802 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8803 new_token
.code
= T_FWORD
;
8805 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8806 new_token
.code
= T_QWORD
;
8808 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8809 /* XXX remove (gcc still uses it) */
8810 || strcasecmp (new_token
.str
, "XWORD") == 0)
8811 new_token
.code
= T_TBYTE
;
8813 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8814 || strcasecmp (new_token
.str
, "OWORD") == 0)
8815 new_token
.code
= T_XMMWORD
;
8817 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8818 new_token
.code
= T_PTR
;
8820 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8821 new_token
.code
= T_SHORT
;
8823 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8825 new_token
.code
= T_OFFSET
;
8827 /* ??? This is not mentioned in the MASM grammar but gcc
8828 makes use of it with -mintel-syntax. OFFSET may be
8829 followed by FLAT: */
8830 if (strncasecmp (q
, " FLAT:", 6) == 0)
8831 strcat (new_token
.str
, " FLAT:");
8834 /* ??? This is not mentioned in the MASM grammar. */
8835 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8837 new_token
.code
= T_OFFSET
;
8839 strcat (new_token
.str
, ":");
8841 as_bad (_("`:' expected"));
8845 new_token
.code
= T_ID
;
8849 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8851 new_token
.code
= *intel_parser
.op_string
;
8852 new_token
.str
[0] = *intel_parser
.op_string
;
8853 new_token
.str
[1] = '\0';
8856 else if (strchr ("<>", *intel_parser
.op_string
)
8857 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8859 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8860 new_token
.str
[0] = *intel_parser
.op_string
;
8861 new_token
.str
[1] = *intel_parser
.op_string
;
8862 new_token
.str
[2] = '\0';
8866 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8868 intel_parser
.op_string
+= strlen (new_token
.str
);
8869 cur_token
= new_token
;
8872 /* Put cur_token back into the token stream and make cur_token point to
8875 intel_putback_token (void)
8877 if (cur_token
.code
!= T_NIL
)
8879 intel_parser
.op_string
-= strlen (cur_token
.str
);
8880 free (cur_token
.str
);
8882 cur_token
= prev_token
;
8884 /* Forget prev_token. */
8885 prev_token
.code
= T_NIL
;
8886 prev_token
.reg
= NULL
;
8887 prev_token
.str
= NULL
;
8891 tc_x86_regname_to_dw2regnum (char *regname
)
8893 unsigned int regnum
;
8894 unsigned int regnames_count
;
8895 static const char *const regnames_32
[] =
8897 "eax", "ecx", "edx", "ebx",
8898 "esp", "ebp", "esi", "edi",
8899 "eip", "eflags", NULL
,
8900 "st0", "st1", "st2", "st3",
8901 "st4", "st5", "st6", "st7",
8903 "xmm0", "xmm1", "xmm2", "xmm3",
8904 "xmm4", "xmm5", "xmm6", "xmm7",
8905 "mm0", "mm1", "mm2", "mm3",
8906 "mm4", "mm5", "mm6", "mm7",
8907 "fcw", "fsw", "mxcsr",
8908 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8911 static const char *const regnames_64
[] =
8913 "rax", "rdx", "rcx", "rbx",
8914 "rsi", "rdi", "rbp", "rsp",
8915 "r8", "r9", "r10", "r11",
8916 "r12", "r13", "r14", "r15",
8918 "xmm0", "xmm1", "xmm2", "xmm3",
8919 "xmm4", "xmm5", "xmm6", "xmm7",
8920 "xmm8", "xmm9", "xmm10", "xmm11",
8921 "xmm12", "xmm13", "xmm14", "xmm15",
8922 "st0", "st1", "st2", "st3",
8923 "st4", "st5", "st6", "st7",
8924 "mm0", "mm1", "mm2", "mm3",
8925 "mm4", "mm5", "mm6", "mm7",
8927 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8928 "fs.base", "gs.base", NULL
, NULL
,
8930 "mxcsr", "fcw", "fsw"
8932 const char *const *regnames
;
8934 if (flag_code
== CODE_64BIT
)
8936 regnames
= regnames_64
;
8937 regnames_count
= ARRAY_SIZE (regnames_64
);
8941 regnames
= regnames_32
;
8942 regnames_count
= ARRAY_SIZE (regnames_32
);
8945 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
8946 if (regnames
[regnum
] != NULL
8947 && strcmp (regname
, regnames
[regnum
]) == 0)
8954 tc_x86_frame_initial_instructions (void)
8956 static unsigned int sp_regno
;
8959 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
8962 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
8963 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8967 i386_elf_section_type (const char *str
, size_t len
)
8969 if (flag_code
== CODE_64BIT
8970 && len
== sizeof ("unwind") - 1
8971 && strncmp (str
, "unwind", 6) == 0)
8972 return SHT_X86_64_UNWIND
;
8979 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8983 expr
.X_op
= O_secrel
;
8984 expr
.X_add_symbol
= symbol
;
8985 expr
.X_add_number
= 0;
8986 emit_expr (&expr
, size
);
8990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8991 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8994 x86_64_section_letter (int letter
, char **ptr_msg
)
8996 if (flag_code
== CODE_64BIT
)
8999 return SHF_X86_64_LARGE
;
9001 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9004 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9009 x86_64_section_word (char *str
, size_t len
)
9011 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9012 return SHF_X86_64_LARGE
;
9018 handle_large_common (int small ATTRIBUTE_UNUSED
)
9020 if (flag_code
!= CODE_64BIT
)
9022 s_comm_internal (0, elf_common_parse
);
9023 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9027 static segT lbss_section
;
9028 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9029 asection
*saved_bss_section
= bss_section
;
9031 if (lbss_section
== NULL
)
9033 flagword applicable
;
9035 subsegT subseg
= now_subseg
;
9037 /* The .lbss section is for local .largecomm symbols. */
9038 lbss_section
= subseg_new (".lbss", 0);
9039 applicable
= bfd_applicable_section_flags (stdoutput
);
9040 bfd_set_section_flags (stdoutput
, lbss_section
,
9041 applicable
& SEC_ALLOC
);
9042 seg_info (lbss_section
)->bss
= 1;
9044 subseg_set (seg
, subseg
);
9047 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9048 bss_section
= lbss_section
;
9050 s_comm_internal (0, elf_common_parse
);
9052 elf_com_section_ptr
= saved_com_section_ptr
;
9053 bss_section
= saved_bss_section
;
9056 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */