1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 /* Intel Syntax. Use a non-ascii letter since since it never appears
91 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
93 #define END_OF_INSN '\0'
96 'templates' is for grouping together 'template' structures for opcodes
97 of the same name. This is only used for storing the insns in the grand
98 ole hash table of insns.
99 The templates themselves start at START and range up to (but not including)
104 const insn_template
*start
;
105 const insn_template
*end
;
109 /* 386 operand encoding bytes: see 386 book for details of this. */
112 unsigned int regmem
; /* codes register or memory operand */
113 unsigned int reg
; /* codes register operand (or extended opcode) */
114 unsigned int mode
; /* how to interpret regmem & reg */
118 /* x86-64 extension prefix. */
119 typedef int rex_byte
;
121 /* 386 opcode byte to code indirect addressing. */
130 /* x86 arch names, types and features */
133 const char *name
; /* arch name */
134 unsigned int len
; /* arch string length */
135 enum processor_type type
; /* arch type */
136 i386_cpu_flags flags
; /* cpu feature flags */
137 unsigned int skip
; /* show_arch should skip this. */
138 unsigned int negated
; /* turn off indicated flags. */
142 static void update_code_flag (int, int);
143 static void set_code_flag (int);
144 static void set_16bit_gcc_code_flag (int);
145 static void set_intel_syntax (int);
146 static void set_intel_mnemonic (int);
147 static void set_allow_index_reg (int);
148 static void set_check (int);
149 static void set_cpu_arch (int);
151 static void pe_directive_secrel (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (char *, char **);
164 static char *parse_insn (char *, char *);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (int, int);
168 static void optimize_imm (void);
169 static void optimize_disp (void);
170 static const insn_template
*match_template (void);
171 static int check_string (void);
172 static int process_suffix (void);
173 static int check_byte_reg (void);
174 static int check_long_reg (void);
175 static int check_qword_reg (void);
176 static int check_word_reg (void);
177 static int finalize_imm (void);
178 static int process_operands (void);
179 static const seg_entry
*build_modrm_byte (void);
180 static void output_insn (void);
181 static void output_imm (fragS
*, offsetT
);
182 static void output_disp (fragS
*, offsetT
);
184 static void s_bss (int);
186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
187 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 static const char *default_arch
= DEFAULT_ARCH
;
195 /* VEX prefix is either 2 byte or 3 byte. */
196 unsigned char bytes
[3];
198 /* Destination or source register specifier. */
199 const reg_entry
*register_specifier
;
202 /* 'md_assemble ()' gathers together information and puts it into a
209 const reg_entry
*regs
;
214 operand_size_mismatch
,
215 operand_type_mismatch
,
216 register_type_mismatch
,
217 number_of_operands_mismatch
,
218 invalid_instruction_suffix
,
221 unsupported_with_intel_mnemonic
,
224 invalid_vsib_address
,
225 invalid_vector_register_set
,
226 unsupported_vector_index_register
231 /* TM holds the template for the insn were currently assembling. */
234 /* SUFFIX holds the instruction size suffix for byte, word, dword
235 or qword, if given. */
238 /* OPERANDS gives the number of given operands. */
239 unsigned int operands
;
241 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
242 of given register, displacement, memory operands and immediate
244 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
246 /* TYPES [i] is the type (see above #defines) which tells us how to
247 use OP[i] for the corresponding operand. */
248 i386_operand_type types
[MAX_OPERANDS
];
250 /* Displacement expression, immediate expression, or register for each
252 union i386_op op
[MAX_OPERANDS
];
254 /* Flags for operands. */
255 unsigned int flags
[MAX_OPERANDS
];
256 #define Operand_PCrel 1
258 /* Relocation type for operand */
259 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
261 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
262 the base index byte below. */
263 const reg_entry
*base_reg
;
264 const reg_entry
*index_reg
;
265 unsigned int log2_scale_factor
;
267 /* SEG gives the seg_entries of this insn. They are zero unless
268 explicit segment overrides are given. */
269 const seg_entry
*seg
[2];
271 /* PREFIX holds all the given prefix opcodes (usually null).
272 PREFIXES is the number of prefix opcodes. */
273 unsigned int prefixes
;
274 unsigned char prefix
[MAX_PREFIXES
];
276 /* RM and SIB are the modrm byte and the sib byte where the
277 addressing modes of this insn are encoded. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
;
286 /* Prefer 8bit or 32bit displacement in encoding. */
289 disp_encoding_default
= 0,
295 const char *rep_prefix
;
298 const char *hle_prefix
;
300 /* Have BND prefix. */
301 const char *bnd_prefix
;
304 enum i386_error error
;
307 typedef struct _i386_insn i386_insn
;
309 /* List of chars besides those in app.c:symbol_chars that can start an
310 operand. Used to prevent the scrubber eating vital white-space. */
311 const char extra_symbol_chars
[] = "*%-(["
320 #if (defined (TE_I386AIX) \
321 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
322 && !defined (TE_GNU) \
323 && !defined (TE_LINUX) \
324 && !defined (TE_NACL) \
325 && !defined (TE_NETWARE) \
326 && !defined (TE_FreeBSD) \
327 && !defined (TE_DragonFly) \
328 && !defined (TE_NetBSD)))
329 /* This array holds the chars that always start a comment. If the
330 pre-processor is disabled, these aren't very useful. The option
331 --divide will remove '/' from this list. */
332 const char *i386_comment_chars
= "#/";
333 #define SVR4_COMMENT_CHARS 1
334 #define PREFIX_SEPARATOR '\\'
337 const char *i386_comment_chars
= "#";
338 #define PREFIX_SEPARATOR '/'
341 /* This array holds the chars that only start a comment at the beginning of
342 a line. If the line seems to have the form '# 123 filename'
343 .line and .file directives will appear in the pre-processed output.
344 Note that input_file.c hand checks for '#' at the beginning of the
345 first line of the input file. This is because the compiler outputs
346 #NO_APP at the beginning of its output.
347 Also note that comments started like this one will always work if
348 '/' isn't otherwise defined. */
349 const char line_comment_chars
[] = "#/";
351 const char line_separator_chars
[] = ";";
353 /* Chars that can be used to separate mant from exp in floating point
355 const char EXP_CHARS
[] = "eE";
357 /* Chars that mean this number is a floating point constant
360 const char FLT_CHARS
[] = "fFdDxX";
362 /* Tables for lexical analysis. */
363 static char mnemonic_chars
[256];
364 static char register_chars
[256];
365 static char operand_chars
[256];
366 static char identifier_chars
[256];
367 static char digit_chars
[256];
369 /* Lexical macros. */
370 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
371 #define is_operand_char(x) (operand_chars[(unsigned char) x])
372 #define is_register_char(x) (register_chars[(unsigned char) x])
373 #define is_space_char(x) ((x) == ' ')
374 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
375 #define is_digit_char(x) (digit_chars[(unsigned char) x])
377 /* All non-digit non-letter characters that may occur in an operand. */
378 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
380 /* md_assemble() always leaves the strings it's passed unaltered. To
381 effect this we maintain a stack of saved characters that we've smashed
382 with '\0's (indicating end of strings for various sub-fields of the
383 assembler instruction). */
384 static char save_stack
[32];
385 static char *save_stack_p
;
386 #define END_STRING_AND_SAVE(s) \
387 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
388 #define RESTORE_END_STRING(s) \
389 do { *(s) = *--save_stack_p; } while (0)
391 /* The instruction we're assembling. */
394 /* Possible templates for current insn. */
395 static const templates
*current_templates
;
397 /* Per instruction expressionS buffers: max displacements & immediates. */
398 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
399 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
401 /* Current operand we are working on. */
402 static int this_operand
= -1;
404 /* We support four different modes. FLAG_CODE variable is used to distinguish
412 static enum flag_code flag_code
;
413 static unsigned int object_64bit
;
414 static unsigned int disallow_64bit_reloc
;
415 static int use_rela_relocations
= 0;
417 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
418 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
419 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
421 /* The ELF ABI to use. */
429 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
432 /* 1 for intel syntax,
434 static int intel_syntax
= 0;
436 /* 1 for intel mnemonic,
437 0 if att mnemonic. */
438 static int intel_mnemonic
= !SYSV386_COMPAT
;
440 /* 1 if support old (<= 2.8.1) versions of gcc. */
441 static int old_gcc
= OLDGCC_COMPAT
;
443 /* 1 if pseudo registers are permitted. */
444 static int allow_pseudo_reg
= 0;
446 /* 1 if register prefix % not required. */
447 static int allow_naked_reg
= 0;
449 /* 1 if the assembler should add BND prefix for all control-tranferring
450 instructions supporting it, even if this prefix wasn't specified
452 static int add_bnd_prefix
= 0;
454 /* 1 if pseudo index register, eiz/riz, is allowed . */
455 static int allow_index_reg
= 0;
457 static enum check_kind
463 sse_check
, operand_check
= check_warning
;
465 /* Register prefix used for error message. */
466 static const char *register_prefix
= "%";
468 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
469 leave, push, and pop instructions so that gcc has the same stack
470 frame as in 32 bit mode. */
471 static char stackop_size
= '\0';
473 /* Non-zero to optimize code alignment. */
474 int optimize_align_code
= 1;
476 /* Non-zero to quieten some warnings. */
477 static int quiet_warnings
= 0;
480 static const char *cpu_arch_name
= NULL
;
481 static char *cpu_sub_arch_name
= NULL
;
483 /* CPU feature flags. */
484 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
486 /* If we have selected a cpu we are generating instructions for. */
487 static int cpu_arch_tune_set
= 0;
489 /* Cpu we are generating instructions for. */
490 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
492 /* CPU feature flags of cpu we are generating instructions for. */
493 static i386_cpu_flags cpu_arch_tune_flags
;
495 /* CPU instruction set architecture used. */
496 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
498 /* CPU feature flags of instruction set architecture used. */
499 i386_cpu_flags cpu_arch_isa_flags
;
501 /* If set, conditional jumps are not automatically promoted to handle
502 larger than a byte offset. */
503 static unsigned int no_cond_jump_promotion
= 0;
505 /* Encode SSE instructions with VEX prefix. */
506 static unsigned int sse2avx
;
508 /* Encode scalar AVX instructions with specific vector length. */
515 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
516 static symbolS
*GOT_symbol
;
518 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
519 unsigned int x86_dwarf2_return_column
;
521 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
522 int x86_cie_data_alignment
;
524 /* Interface to relax_segment.
525 There are 3 major relax states for 386 jump insns because the
526 different types of jumps add different sizes to frags when we're
527 figuring out what sort of jump to choose to reach a given label. */
530 #define UNCOND_JUMP 0
532 #define COND_JUMP86 2
537 #define SMALL16 (SMALL | CODE16)
539 #define BIG16 (BIG | CODE16)
543 #define INLINE __inline__
549 #define ENCODE_RELAX_STATE(type, size) \
550 ((relax_substateT) (((type) << 2) | (size)))
551 #define TYPE_FROM_RELAX_STATE(s) \
553 #define DISP_SIZE_FROM_RELAX_STATE(s) \
554 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
556 /* This table is used by relax_frag to promote short jumps to long
557 ones where necessary. SMALL (short) jumps may be promoted to BIG
558 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
559 don't allow a short jump in a 32 bit code segment to be promoted to
560 a 16 bit offset jump because it's slower (requires data size
561 prefix), and doesn't work, unless the destination is in the bottom
562 64k of the code segment (The top 16 bits of eip are zeroed). */
564 const relax_typeS md_relax_table
[] =
567 1) most positive reach of this state,
568 2) most negative reach of this state,
569 3) how many bytes this mode will have in the variable part of the frag
570 4) which index into the table to try if we can't fit into this one. */
572 /* UNCOND_JUMP states. */
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
575 /* dword jmp adds 4 bytes to frag:
576 0 extra opcode bytes, 4 displacement bytes. */
578 /* word jmp adds 2 byte2 to frag:
579 0 extra opcode bytes, 2 displacement bytes. */
582 /* COND_JUMP states. */
583 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
584 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
585 /* dword conditionals adds 5 bytes to frag:
586 1 extra opcode byte, 4 displacement bytes. */
588 /* word conditionals add 3 bytes to frag:
589 1 extra opcode byte, 2 displacement bytes. */
592 /* COND_JUMP86 states. */
593 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
594 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
595 /* dword conditionals adds 5 bytes to frag:
596 1 extra opcode byte, 4 displacement bytes. */
598 /* word conditionals add 4 bytes to frag:
599 1 displacement byte and a 3 byte long branch insn. */
603 static const arch_entry cpu_arch
[] =
605 /* Do not replace the first two entries - i386_target_format()
606 relies on them being there in this order. */
607 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
608 CPU_GENERIC32_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
610 CPU_GENERIC64_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
612 CPU_NONE_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
614 CPU_I186_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
616 CPU_I286_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
618 CPU_I386_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
620 CPU_I486_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
622 CPU_I586_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
624 CPU_I686_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
626 CPU_I586_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
628 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
630 CPU_P2_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
632 CPU_P3_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
634 CPU_P4_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
636 CPU_CORE_FLAGS
, 0, 0 },
637 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
638 CPU_NOCONA_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
640 CPU_CORE_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
642 CPU_CORE_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
644 CPU_CORE2_FLAGS
, 1, 0 },
645 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
646 CPU_CORE2_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
648 CPU_COREI7_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
650 CPU_L1OM_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
652 CPU_K1OM_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
654 CPU_K6_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
656 CPU_K6_2_FLAGS
, 0, 0 },
657 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
658 CPU_ATHLON_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
660 CPU_K8_FLAGS
, 1, 0 },
661 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
662 CPU_K8_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
664 CPU_K8_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
666 CPU_AMDFAM10_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
668 CPU_BDVER1_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
670 CPU_BDVER2_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
672 CPU_BDVER3_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
674 CPU_BTVER1_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
676 CPU_BTVER2_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
678 CPU_8087_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
680 CPU_287_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
682 CPU_387_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
684 CPU_ANY87_FLAGS
, 0, 1 },
685 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
686 CPU_MMX_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
688 CPU_3DNOWA_FLAGS
, 0, 1 },
689 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
690 CPU_SSE_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
692 CPU_SSE2_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
694 CPU_SSE3_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
696 CPU_SSSE3_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
698 CPU_SSE4_1_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
700 CPU_SSE4_2_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
702 CPU_SSE4_2_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
704 CPU_ANY_SSE_FLAGS
, 0, 1 },
705 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
706 CPU_AVX_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
708 CPU_AVX2_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
710 CPU_ANY_AVX_FLAGS
, 0, 1 },
711 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
712 CPU_VMX_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
714 CPU_VMFUNC_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
716 CPU_SMX_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
718 CPU_XSAVE_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
720 CPU_XSAVEOPT_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
722 CPU_AES_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
724 CPU_PCLMUL_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
726 CPU_PCLMUL_FLAGS
, 1, 0 },
727 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
728 CPU_FSGSBASE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
730 CPU_RDRND_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
732 CPU_F16C_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
734 CPU_BMI2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
736 CPU_FMA_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
738 CPU_FMA4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
740 CPU_XOP_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
742 CPU_LWP_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
744 CPU_MOVBE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
746 CPU_CX16_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
748 CPU_EPT_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
750 CPU_LZCNT_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
752 CPU_HLE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
754 CPU_RTM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
756 CPU_INVPCID_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
758 CPU_CLFLUSH_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
760 CPU_NOP_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
762 CPU_SYSCALL_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
764 CPU_RDTSCP_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
766 CPU_3DNOW_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
768 CPU_3DNOWA_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
770 CPU_PADLOCK_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
772 CPU_SVME_FLAGS
, 1, 0 },
773 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
774 CPU_SVME_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
776 CPU_SSE4A_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
778 CPU_ABM_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
780 CPU_BMI_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
782 CPU_TBM_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
784 CPU_ADX_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
786 CPU_RDSEED_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
788 CPU_PRFCHW_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
790 CPU_SMAP_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
792 CPU_MPX_FLAGS
, 0, 0 },
796 /* Like s_lcomm_internal in gas/read.c but the alignment string
797 is allowed to be optional. */
800 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
807 && *input_line_pointer
== ',')
809 align
= parse_align (needs_align
- 1);
811 if (align
== (addressT
) -1)
826 bss_alloc (symbolP
, size
, align
);
831 pe_lcomm (int needs_align
)
833 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
837 const pseudo_typeS md_pseudo_table
[] =
839 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
840 {"align", s_align_bytes
, 0},
842 {"align", s_align_ptwo
, 0},
844 {"arch", set_cpu_arch
, 0},
848 {"lcomm", pe_lcomm
, 1},
850 {"ffloat", float_cons
, 'f'},
851 {"dfloat", float_cons
, 'd'},
852 {"tfloat", float_cons
, 'x'},
854 {"slong", signed_cons
, 4},
855 {"noopt", s_ignore
, 0},
856 {"optim", s_ignore
, 0},
857 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
858 {"code16", set_code_flag
, CODE_16BIT
},
859 {"code32", set_code_flag
, CODE_32BIT
},
860 {"code64", set_code_flag
, CODE_64BIT
},
861 {"intel_syntax", set_intel_syntax
, 1},
862 {"att_syntax", set_intel_syntax
, 0},
863 {"intel_mnemonic", set_intel_mnemonic
, 1},
864 {"att_mnemonic", set_intel_mnemonic
, 0},
865 {"allow_index_reg", set_allow_index_reg
, 1},
866 {"disallow_index_reg", set_allow_index_reg
, 0},
867 {"sse_check", set_check
, 0},
868 {"operand_check", set_check
, 1},
869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
870 {"largecomm", handle_large_common
, 0},
872 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
873 {"loc", dwarf2_directive_loc
, 0},
874 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
877 {"secrel32", pe_directive_secrel
, 0},
882 /* For interface with expression (). */
883 extern char *input_line_pointer
;
885 /* Hash table for instruction mnemonic lookup. */
886 static struct hash_control
*op_hash
;
888 /* Hash table for register lookup. */
889 static struct hash_control
*reg_hash
;
892 i386_align_code (fragS
*fragP
, int count
)
894 /* Various efficient no-op patterns for aligning code labels.
895 Note: Don't try to assemble the instructions in the comments.
896 0L and 0w are not legal. */
897 static const char f32_1
[] =
899 static const char f32_2
[] =
900 {0x66,0x90}; /* xchg %ax,%ax */
901 static const char f32_3
[] =
902 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
903 static const char f32_4
[] =
904 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
905 static const char f32_5
[] =
907 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
908 static const char f32_6
[] =
909 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
910 static const char f32_7
[] =
911 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
912 static const char f32_8
[] =
914 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
915 static const char f32_9
[] =
916 {0x89,0xf6, /* movl %esi,%esi */
917 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
918 static const char f32_10
[] =
919 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
920 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
921 static const char f32_11
[] =
922 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
923 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
924 static const char f32_12
[] =
925 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
926 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
927 static const char f32_13
[] =
928 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
929 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
930 static const char f32_14
[] =
931 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
932 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
933 static const char f16_3
[] =
934 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
935 static const char f16_4
[] =
936 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
937 static const char f16_5
[] =
939 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
940 static const char f16_6
[] =
941 {0x89,0xf6, /* mov %si,%si */
942 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
943 static const char f16_7
[] =
944 {0x8d,0x74,0x00, /* lea 0(%si),%si */
945 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
946 static const char f16_8
[] =
947 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
948 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
949 static const char jump_31
[] =
950 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
951 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
952 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
953 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
954 static const char *const f32_patt
[] = {
955 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
956 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
958 static const char *const f16_patt
[] = {
959 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
962 static const char alt_3
[] =
964 /* nopl 0(%[re]ax) */
965 static const char alt_4
[] =
966 {0x0f,0x1f,0x40,0x00};
967 /* nopl 0(%[re]ax,%[re]ax,1) */
968 static const char alt_5
[] =
969 {0x0f,0x1f,0x44,0x00,0x00};
970 /* nopw 0(%[re]ax,%[re]ax,1) */
971 static const char alt_6
[] =
972 {0x66,0x0f,0x1f,0x44,0x00,0x00};
973 /* nopl 0L(%[re]ax) */
974 static const char alt_7
[] =
975 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
976 /* nopl 0L(%[re]ax,%[re]ax,1) */
977 static const char alt_8
[] =
978 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* nopw 0L(%[re]ax,%[re]ax,1) */
980 static const char alt_9
[] =
981 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_10
[] =
984 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
986 nopw %cs:0L(%[re]ax,%[re]ax,1) */
987 static const char alt_long_11
[] =
989 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_12
[] =
996 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1000 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1001 static const char alt_long_13
[] =
1005 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1010 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1011 static const char alt_long_14
[] =
1016 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1022 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1023 static const char alt_long_15
[] =
1029 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1030 /* nopl 0(%[re]ax,%[re]ax,1)
1031 nopw 0(%[re]ax,%[re]ax,1) */
1032 static const char alt_short_11
[] =
1033 {0x0f,0x1f,0x44,0x00,0x00,
1034 0x66,0x0f,0x1f,0x44,0x00,0x00};
1035 /* nopw 0(%[re]ax,%[re]ax,1)
1036 nopw 0(%[re]ax,%[re]ax,1) */
1037 static const char alt_short_12
[] =
1038 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1039 0x66,0x0f,0x1f,0x44,0x00,0x00};
1040 /* nopw 0(%[re]ax,%[re]ax,1)
1042 static const char alt_short_13
[] =
1043 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1044 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1047 static const char alt_short_14
[] =
1048 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1049 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1051 nopl 0L(%[re]ax,%[re]ax,1) */
1052 static const char alt_short_15
[] =
1053 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1054 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1055 static const char *const alt_short_patt
[] = {
1056 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1057 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1058 alt_short_14
, alt_short_15
1060 static const char *const alt_long_patt
[] = {
1061 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1062 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1063 alt_long_14
, alt_long_15
1066 /* Only align for at least a positive non-zero boundary. */
1067 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1070 /* We need to decide which NOP sequence to use for 32bit and
1071 64bit. When -mtune= is used:
1073 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1074 PROCESSOR_GENERIC32, f32_patt will be used.
1075 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1076 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1077 PROCESSOR_GENERIC64, alt_long_patt will be used.
1078 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1079 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1082 When -mtune= isn't used, alt_long_patt will be used if
1083 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1086 When -march= or .arch is used, we can't use anything beyond
1087 cpu_arch_isa_flags. */
1089 if (flag_code
== CODE_16BIT
)
1093 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1095 /* Adjust jump offset. */
1096 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1100 f16_patt
[count
- 1], count
);
1104 const char *const *patt
= NULL
;
1106 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1108 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1109 switch (cpu_arch_tune
)
1111 case PROCESSOR_UNKNOWN
:
1112 /* We use cpu_arch_isa_flags to check if we SHOULD
1113 optimize with nops. */
1114 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1115 patt
= alt_long_patt
;
1119 case PROCESSOR_PENTIUM4
:
1120 case PROCESSOR_NOCONA
:
1121 case PROCESSOR_CORE
:
1122 case PROCESSOR_CORE2
:
1123 case PROCESSOR_COREI7
:
1124 case PROCESSOR_L1OM
:
1125 case PROCESSOR_K1OM
:
1126 case PROCESSOR_GENERIC64
:
1127 patt
= alt_long_patt
;
1130 case PROCESSOR_ATHLON
:
1132 case PROCESSOR_AMDFAM10
:
1135 patt
= alt_short_patt
;
1137 case PROCESSOR_I386
:
1138 case PROCESSOR_I486
:
1139 case PROCESSOR_PENTIUM
:
1140 case PROCESSOR_PENTIUMPRO
:
1141 case PROCESSOR_GENERIC32
:
1148 switch (fragP
->tc_frag_data
.tune
)
1150 case PROCESSOR_UNKNOWN
:
1151 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1152 PROCESSOR_UNKNOWN. */
1156 case PROCESSOR_I386
:
1157 case PROCESSOR_I486
:
1158 case PROCESSOR_PENTIUM
:
1160 case PROCESSOR_ATHLON
:
1162 case PROCESSOR_AMDFAM10
:
1165 case PROCESSOR_GENERIC32
:
1166 /* We use cpu_arch_isa_flags to check if we CAN optimize
1168 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1169 patt
= alt_short_patt
;
1173 case PROCESSOR_PENTIUMPRO
:
1174 case PROCESSOR_PENTIUM4
:
1175 case PROCESSOR_NOCONA
:
1176 case PROCESSOR_CORE
:
1177 case PROCESSOR_CORE2
:
1178 case PROCESSOR_COREI7
:
1179 case PROCESSOR_L1OM
:
1180 case PROCESSOR_K1OM
:
1181 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1182 patt
= alt_long_patt
;
1186 case PROCESSOR_GENERIC64
:
1187 patt
= alt_long_patt
;
1192 if (patt
== f32_patt
)
1194 /* If the padding is less than 15 bytes, we use the normal
1195 ones. Otherwise, we use a jump instruction and adjust
1199 /* For 64bit, the limit is 3 bytes. */
1200 if (flag_code
== CODE_64BIT
1201 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1206 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1207 patt
[count
- 1], count
);
1210 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1212 /* Adjust jump offset. */
1213 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1218 /* Maximum length of an instruction is 15 byte. If the
1219 padding is greater than 15 bytes and we don't use jump,
1220 we have to break it into smaller pieces. */
1221 int padding
= count
;
1222 while (padding
> 15)
1225 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1230 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1231 patt
[padding
- 1], padding
);
1234 fragP
->fr_var
= count
;
1238 operand_type_all_zero (const union i386_operand_type
*x
)
1240 switch (ARRAY_SIZE(x
->array
))
1249 return !x
->array
[0];
1256 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1258 switch (ARRAY_SIZE(x
->array
))
1273 operand_type_equal (const union i386_operand_type
*x
,
1274 const union i386_operand_type
*y
)
1276 switch (ARRAY_SIZE(x
->array
))
1279 if (x
->array
[2] != y
->array
[2])
1282 if (x
->array
[1] != y
->array
[1])
1285 return x
->array
[0] == y
->array
[0];
1293 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1295 switch (ARRAY_SIZE(x
->array
))
1304 return !x
->array
[0];
1311 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1313 switch (ARRAY_SIZE(x
->array
))
1328 cpu_flags_equal (const union i386_cpu_flags
*x
,
1329 const union i386_cpu_flags
*y
)
1331 switch (ARRAY_SIZE(x
->array
))
1334 if (x
->array
[2] != y
->array
[2])
1337 if (x
->array
[1] != y
->array
[1])
1340 return x
->array
[0] == y
->array
[0];
1348 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1350 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1351 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1354 static INLINE i386_cpu_flags
1355 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1357 switch (ARRAY_SIZE (x
.array
))
1360 x
.array
[2] &= y
.array
[2];
1362 x
.array
[1] &= y
.array
[1];
1364 x
.array
[0] &= y
.array
[0];
1372 static INLINE i386_cpu_flags
1373 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1375 switch (ARRAY_SIZE (x
.array
))
1378 x
.array
[2] |= y
.array
[2];
1380 x
.array
[1] |= y
.array
[1];
1382 x
.array
[0] |= y
.array
[0];
1390 static INLINE i386_cpu_flags
1391 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1393 switch (ARRAY_SIZE (x
.array
))
1396 x
.array
[2] &= ~y
.array
[2];
1398 x
.array
[1] &= ~y
.array
[1];
1400 x
.array
[0] &= ~y
.array
[0];
1408 #define CPU_FLAGS_ARCH_MATCH 0x1
1409 #define CPU_FLAGS_64BIT_MATCH 0x2
1410 #define CPU_FLAGS_AES_MATCH 0x4
1411 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1412 #define CPU_FLAGS_AVX_MATCH 0x10
1414 #define CPU_FLAGS_32BIT_MATCH \
1415 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1416 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1417 #define CPU_FLAGS_PERFECT_MATCH \
1418 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1420 /* Return CPU flags match bits. */
1423 cpu_flags_match (const insn_template
*t
)
1425 i386_cpu_flags x
= t
->cpu_flags
;
1426 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1428 x
.bitfield
.cpu64
= 0;
1429 x
.bitfield
.cpuno64
= 0;
1431 if (cpu_flags_all_zero (&x
))
1433 /* This instruction is available on all archs. */
1434 match
|= CPU_FLAGS_32BIT_MATCH
;
1438 /* This instruction is available only on some archs. */
1439 i386_cpu_flags cpu
= cpu_arch_flags
;
1441 cpu
.bitfield
.cpu64
= 0;
1442 cpu
.bitfield
.cpuno64
= 0;
1443 cpu
= cpu_flags_and (x
, cpu
);
1444 if (!cpu_flags_all_zero (&cpu
))
1446 if (x
.bitfield
.cpuavx
)
1448 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1449 if (cpu
.bitfield
.cpuavx
)
1451 /* Check SSE2AVX. */
1452 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1454 match
|= (CPU_FLAGS_ARCH_MATCH
1455 | CPU_FLAGS_AVX_MATCH
);
1457 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1458 match
|= CPU_FLAGS_AES_MATCH
;
1460 if (!x
.bitfield
.cpupclmul
1461 || cpu
.bitfield
.cpupclmul
)
1462 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1466 match
|= CPU_FLAGS_ARCH_MATCH
;
1469 match
|= CPU_FLAGS_32BIT_MATCH
;
1475 static INLINE i386_operand_type
1476 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1478 switch (ARRAY_SIZE (x
.array
))
1481 x
.array
[2] &= y
.array
[2];
1483 x
.array
[1] &= y
.array
[1];
1485 x
.array
[0] &= y
.array
[0];
1493 static INLINE i386_operand_type
1494 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1496 switch (ARRAY_SIZE (x
.array
))
1499 x
.array
[2] |= y
.array
[2];
1501 x
.array
[1] |= y
.array
[1];
1503 x
.array
[0] |= y
.array
[0];
1511 static INLINE i386_operand_type
1512 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1514 switch (ARRAY_SIZE (x
.array
))
1517 x
.array
[2] ^= y
.array
[2];
1519 x
.array
[1] ^= y
.array
[1];
1521 x
.array
[0] ^= y
.array
[0];
1529 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1530 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1531 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1532 static const i386_operand_type inoutportreg
1533 = OPERAND_TYPE_INOUTPORTREG
;
1534 static const i386_operand_type reg16_inoutportreg
1535 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1536 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1537 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1538 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1539 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1540 static const i386_operand_type anydisp
1541 = OPERAND_TYPE_ANYDISP
;
1542 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1543 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1544 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1545 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1546 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1547 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1548 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1549 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1550 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1551 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1552 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1553 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1554 static const i386_operand_type regbnd
= OPERAND_TYPE_REGBND
;
1565 operand_type_check (i386_operand_type t
, enum operand_type c
)
1570 return (t
.bitfield
.reg8
1573 || t
.bitfield
.reg64
);
1576 return (t
.bitfield
.imm8
1580 || t
.bitfield
.imm32s
1581 || t
.bitfield
.imm64
);
1584 return (t
.bitfield
.disp8
1585 || t
.bitfield
.disp16
1586 || t
.bitfield
.disp32
1587 || t
.bitfield
.disp32s
1588 || t
.bitfield
.disp64
);
1591 return (t
.bitfield
.disp8
1592 || t
.bitfield
.disp16
1593 || t
.bitfield
.disp32
1594 || t
.bitfield
.disp32s
1595 || t
.bitfield
.disp64
1596 || t
.bitfield
.baseindex
);
1605 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1606 operand J for instruction template T. */
1609 match_reg_size (const insn_template
*t
, unsigned int j
)
1611 return !((i
.types
[j
].bitfield
.byte
1612 && !t
->operand_types
[j
].bitfield
.byte
)
1613 || (i
.types
[j
].bitfield
.word
1614 && !t
->operand_types
[j
].bitfield
.word
)
1615 || (i
.types
[j
].bitfield
.dword
1616 && !t
->operand_types
[j
].bitfield
.dword
)
1617 || (i
.types
[j
].bitfield
.qword
1618 && !t
->operand_types
[j
].bitfield
.qword
));
1621 /* Return 1 if there is no conflict in any size on operand J for
1622 instruction template T. */
1625 match_mem_size (const insn_template
*t
, unsigned int j
)
1627 return (match_reg_size (t
, j
)
1628 && !((i
.types
[j
].bitfield
.unspecified
1629 && !t
->operand_types
[j
].bitfield
.unspecified
)
1630 || (i
.types
[j
].bitfield
.fword
1631 && !t
->operand_types
[j
].bitfield
.fword
)
1632 || (i
.types
[j
].bitfield
.tbyte
1633 && !t
->operand_types
[j
].bitfield
.tbyte
)
1634 || (i
.types
[j
].bitfield
.xmmword
1635 && !t
->operand_types
[j
].bitfield
.xmmword
)
1636 || (i
.types
[j
].bitfield
.ymmword
1637 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1640 /* Return 1 if there is no size conflict on any operands for
1641 instruction template T. */
1644 operand_size_match (const insn_template
*t
)
1649 /* Don't check jump instructions. */
1650 if (t
->opcode_modifier
.jump
1651 || t
->opcode_modifier
.jumpbyte
1652 || t
->opcode_modifier
.jumpdword
1653 || t
->opcode_modifier
.jumpintersegment
)
1656 /* Check memory and accumulator operand size. */
1657 for (j
= 0; j
< i
.operands
; j
++)
1659 if (t
->operand_types
[j
].bitfield
.anysize
)
1662 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1668 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1677 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1680 i
.error
= operand_size_mismatch
;
1684 /* Check reverse. */
1685 gas_assert (i
.operands
== 2);
1688 for (j
= 0; j
< 2; j
++)
1690 if (t
->operand_types
[j
].bitfield
.acc
1691 && !match_reg_size (t
, j
? 0 : 1))
1694 if (i
.types
[j
].bitfield
.mem
1695 && !match_mem_size (t
, j
? 0 : 1))
1703 operand_type_match (i386_operand_type overlap
,
1704 i386_operand_type given
)
1706 i386_operand_type temp
= overlap
;
1708 temp
.bitfield
.jumpabsolute
= 0;
1709 temp
.bitfield
.unspecified
= 0;
1710 temp
.bitfield
.byte
= 0;
1711 temp
.bitfield
.word
= 0;
1712 temp
.bitfield
.dword
= 0;
1713 temp
.bitfield
.fword
= 0;
1714 temp
.bitfield
.qword
= 0;
1715 temp
.bitfield
.tbyte
= 0;
1716 temp
.bitfield
.xmmword
= 0;
1717 temp
.bitfield
.ymmword
= 0;
1718 if (operand_type_all_zero (&temp
))
1721 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1722 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1726 i
.error
= operand_type_mismatch
;
1730 /* If given types g0 and g1 are registers they must be of the same type
1731 unless the expected operand type register overlap is null.
1732 Note that Acc in a template matches every size of reg. */
1735 operand_type_register_match (i386_operand_type m0
,
1736 i386_operand_type g0
,
1737 i386_operand_type t0
,
1738 i386_operand_type m1
,
1739 i386_operand_type g1
,
1740 i386_operand_type t1
)
1742 if (!operand_type_check (g0
, reg
))
1745 if (!operand_type_check (g1
, reg
))
1748 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1749 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1750 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1751 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1754 if (m0
.bitfield
.acc
)
1756 t0
.bitfield
.reg8
= 1;
1757 t0
.bitfield
.reg16
= 1;
1758 t0
.bitfield
.reg32
= 1;
1759 t0
.bitfield
.reg64
= 1;
1762 if (m1
.bitfield
.acc
)
1764 t1
.bitfield
.reg8
= 1;
1765 t1
.bitfield
.reg16
= 1;
1766 t1
.bitfield
.reg32
= 1;
1767 t1
.bitfield
.reg64
= 1;
1770 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1771 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1772 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1773 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1776 i
.error
= register_type_mismatch
;
1781 static INLINE
unsigned int
1782 register_number (const reg_entry
*r
)
1784 unsigned int nr
= r
->reg_num
;
1786 if (r
->reg_flags
& RegRex
)
1792 static INLINE
unsigned int
1793 mode_from_disp_size (i386_operand_type t
)
1795 if (t
.bitfield
.disp8
)
1797 else if (t
.bitfield
.disp16
1798 || t
.bitfield
.disp32
1799 || t
.bitfield
.disp32s
)
1806 fits_in_signed_byte (offsetT num
)
1808 return (num
>= -128) && (num
<= 127);
1812 fits_in_unsigned_byte (offsetT num
)
1814 return (num
& 0xff) == num
;
1818 fits_in_unsigned_word (offsetT num
)
1820 return (num
& 0xffff) == num
;
1824 fits_in_signed_word (offsetT num
)
1826 return (-32768 <= num
) && (num
<= 32767);
1830 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1835 return (!(((offsetT
) -1 << 31) & num
)
1836 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1838 } /* fits_in_signed_long() */
1841 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1846 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1848 } /* fits_in_unsigned_long() */
1851 fits_in_imm4 (offsetT num
)
1853 return (num
& 0xf) == num
;
1856 static i386_operand_type
1857 smallest_imm_type (offsetT num
)
1859 i386_operand_type t
;
1861 operand_type_set (&t
, 0);
1862 t
.bitfield
.imm64
= 1;
1864 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1866 /* This code is disabled on the 486 because all the Imm1 forms
1867 in the opcode table are slower on the i486. They're the
1868 versions with the implicitly specified single-position
1869 displacement, which has another syntax if you really want to
1871 t
.bitfield
.imm1
= 1;
1872 t
.bitfield
.imm8
= 1;
1873 t
.bitfield
.imm8s
= 1;
1874 t
.bitfield
.imm16
= 1;
1875 t
.bitfield
.imm32
= 1;
1876 t
.bitfield
.imm32s
= 1;
1878 else if (fits_in_signed_byte (num
))
1880 t
.bitfield
.imm8
= 1;
1881 t
.bitfield
.imm8s
= 1;
1882 t
.bitfield
.imm16
= 1;
1883 t
.bitfield
.imm32
= 1;
1884 t
.bitfield
.imm32s
= 1;
1886 else if (fits_in_unsigned_byte (num
))
1888 t
.bitfield
.imm8
= 1;
1889 t
.bitfield
.imm16
= 1;
1890 t
.bitfield
.imm32
= 1;
1891 t
.bitfield
.imm32s
= 1;
1893 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1895 t
.bitfield
.imm16
= 1;
1896 t
.bitfield
.imm32
= 1;
1897 t
.bitfield
.imm32s
= 1;
1899 else if (fits_in_signed_long (num
))
1901 t
.bitfield
.imm32
= 1;
1902 t
.bitfield
.imm32s
= 1;
1904 else if (fits_in_unsigned_long (num
))
1905 t
.bitfield
.imm32
= 1;
1911 offset_in_range (offsetT val
, int size
)
1917 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1918 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1919 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1921 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1927 /* If BFD64, sign extend val for 32bit address mode. */
1928 if (flag_code
!= CODE_64BIT
1929 || i
.prefix
[ADDR_PREFIX
])
1930 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1931 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1934 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1936 char buf1
[40], buf2
[40];
1938 sprint_value (buf1
, val
);
1939 sprint_value (buf2
, val
& mask
);
1940 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1954 a. PREFIX_EXIST if attempting to add a prefix where one from the
1955 same class already exists.
1956 b. PREFIX_LOCK if lock prefix is added.
1957 c. PREFIX_REP if rep/repne prefix is added.
1958 d. PREFIX_OTHER if other prefix is added.
1961 static enum PREFIX_GROUP
1962 add_prefix (unsigned int prefix
)
1964 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1967 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1968 && flag_code
== CODE_64BIT
)
1970 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1971 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1972 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1983 case CS_PREFIX_OPCODE
:
1984 case DS_PREFIX_OPCODE
:
1985 case ES_PREFIX_OPCODE
:
1986 case FS_PREFIX_OPCODE
:
1987 case GS_PREFIX_OPCODE
:
1988 case SS_PREFIX_OPCODE
:
1992 case REPNE_PREFIX_OPCODE
:
1993 case REPE_PREFIX_OPCODE
:
1998 case LOCK_PREFIX_OPCODE
:
2007 case ADDR_PREFIX_OPCODE
:
2011 case DATA_PREFIX_OPCODE
:
2015 if (i
.prefix
[q
] != 0)
2023 i
.prefix
[q
] |= prefix
;
2026 as_bad (_("same type of prefix used twice"));
2032 update_code_flag (int value
, int check
)
2034 PRINTF_LIKE ((*as_error
));
2036 flag_code
= (enum flag_code
) value
;
2037 if (flag_code
== CODE_64BIT
)
2039 cpu_arch_flags
.bitfield
.cpu64
= 1;
2040 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2044 cpu_arch_flags
.bitfield
.cpu64
= 0;
2045 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2047 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2050 as_error
= as_fatal
;
2053 (*as_error
) (_("64bit mode not supported on `%s'."),
2054 cpu_arch_name
? cpu_arch_name
: default_arch
);
2056 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2059 as_error
= as_fatal
;
2062 (*as_error
) (_("32bit mode not supported on `%s'."),
2063 cpu_arch_name
? cpu_arch_name
: default_arch
);
2065 stackop_size
= '\0';
2069 set_code_flag (int value
)
2071 update_code_flag (value
, 0);
2075 set_16bit_gcc_code_flag (int new_code_flag
)
2077 flag_code
= (enum flag_code
) new_code_flag
;
2078 if (flag_code
!= CODE_16BIT
)
2080 cpu_arch_flags
.bitfield
.cpu64
= 0;
2081 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2082 stackop_size
= LONG_MNEM_SUFFIX
;
2086 set_intel_syntax (int syntax_flag
)
2088 /* Find out if register prefixing is specified. */
2089 int ask_naked_reg
= 0;
2092 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2094 char *string
= input_line_pointer
;
2095 int e
= get_symbol_end ();
2097 if (strcmp (string
, "prefix") == 0)
2099 else if (strcmp (string
, "noprefix") == 0)
2102 as_bad (_("bad argument to syntax directive."));
2103 *input_line_pointer
= e
;
2105 demand_empty_rest_of_line ();
2107 intel_syntax
= syntax_flag
;
2109 if (ask_naked_reg
== 0)
2110 allow_naked_reg
= (intel_syntax
2111 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2113 allow_naked_reg
= (ask_naked_reg
< 0);
2115 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2117 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2118 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2119 register_prefix
= allow_naked_reg
? "" : "%";
2123 set_intel_mnemonic (int mnemonic_flag
)
2125 intel_mnemonic
= mnemonic_flag
;
2129 set_allow_index_reg (int flag
)
2131 allow_index_reg
= flag
;
2135 set_check (int what
)
2137 enum check_kind
*kind
;
2142 kind
= &operand_check
;
2153 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2155 char *string
= input_line_pointer
;
2156 int e
= get_symbol_end ();
2158 if (strcmp (string
, "none") == 0)
2160 else if (strcmp (string
, "warning") == 0)
2161 *kind
= check_warning
;
2162 else if (strcmp (string
, "error") == 0)
2163 *kind
= check_error
;
2165 as_bad (_("bad argument to %s_check directive."), str
);
2166 *input_line_pointer
= e
;
2169 as_bad (_("missing argument for %s_check directive"), str
);
2171 demand_empty_rest_of_line ();
2175 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2176 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2179 static const char *arch
;
2181 /* Intel LIOM is only supported on ELF. */
2187 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2188 use default_arch. */
2189 arch
= cpu_arch_name
;
2191 arch
= default_arch
;
2194 /* If we are targeting Intel L1OM, we must enable it. */
2195 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2196 || new_flag
.bitfield
.cpul1om
)
2199 /* If we are targeting Intel K1OM, we must enable it. */
2200 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2201 || new_flag
.bitfield
.cpuk1om
)
2204 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2209 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2213 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2215 char *string
= input_line_pointer
;
2216 int e
= get_symbol_end ();
2218 i386_cpu_flags flags
;
2220 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2222 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2224 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2228 cpu_arch_name
= cpu_arch
[j
].name
;
2229 cpu_sub_arch_name
= NULL
;
2230 cpu_arch_flags
= cpu_arch
[j
].flags
;
2231 if (flag_code
== CODE_64BIT
)
2233 cpu_arch_flags
.bitfield
.cpu64
= 1;
2234 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2238 cpu_arch_flags
.bitfield
.cpu64
= 0;
2239 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2241 cpu_arch_isa
= cpu_arch
[j
].type
;
2242 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2243 if (!cpu_arch_tune_set
)
2245 cpu_arch_tune
= cpu_arch_isa
;
2246 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2251 if (!cpu_arch
[j
].negated
)
2252 flags
= cpu_flags_or (cpu_arch_flags
,
2255 flags
= cpu_flags_and_not (cpu_arch_flags
,
2257 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2259 if (cpu_sub_arch_name
)
2261 char *name
= cpu_sub_arch_name
;
2262 cpu_sub_arch_name
= concat (name
,
2264 (const char *) NULL
);
2268 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2269 cpu_arch_flags
= flags
;
2270 cpu_arch_isa_flags
= flags
;
2272 *input_line_pointer
= e
;
2273 demand_empty_rest_of_line ();
2277 if (j
>= ARRAY_SIZE (cpu_arch
))
2278 as_bad (_("no such architecture: `%s'"), string
);
2280 *input_line_pointer
= e
;
2283 as_bad (_("missing cpu architecture"));
2285 no_cond_jump_promotion
= 0;
2286 if (*input_line_pointer
== ','
2287 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2289 char *string
= ++input_line_pointer
;
2290 int e
= get_symbol_end ();
2292 if (strcmp (string
, "nojumps") == 0)
2293 no_cond_jump_promotion
= 1;
2294 else if (strcmp (string
, "jumps") == 0)
2297 as_bad (_("no such architecture modifier: `%s'"), string
);
2299 *input_line_pointer
= e
;
2302 demand_empty_rest_of_line ();
2305 enum bfd_architecture
2308 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2310 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2311 || flag_code
!= CODE_64BIT
)
2312 as_fatal (_("Intel L1OM is 64bit ELF only"));
2313 return bfd_arch_l1om
;
2315 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2317 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2318 || flag_code
!= CODE_64BIT
)
2319 as_fatal (_("Intel K1OM is 64bit ELF only"));
2320 return bfd_arch_k1om
;
2323 return bfd_arch_i386
;
2329 if (!strncmp (default_arch
, "x86_64", 6))
2331 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2333 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2334 || default_arch
[6] != '\0')
2335 as_fatal (_("Intel L1OM is 64bit ELF only"));
2336 return bfd_mach_l1om
;
2338 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2340 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2341 || default_arch
[6] != '\0')
2342 as_fatal (_("Intel K1OM is 64bit ELF only"));
2343 return bfd_mach_k1om
;
2345 else if (default_arch
[6] == '\0')
2346 return bfd_mach_x86_64
;
2348 return bfd_mach_x64_32
;
2350 else if (!strcmp (default_arch
, "i386"))
2351 return bfd_mach_i386_i386
;
2353 as_fatal (_("unknown architecture"));
2359 const char *hash_err
;
2361 /* Initialize op_hash hash table. */
2362 op_hash
= hash_new ();
2365 const insn_template
*optab
;
2366 templates
*core_optab
;
2368 /* Setup for loop. */
2370 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2371 core_optab
->start
= optab
;
2376 if (optab
->name
== NULL
2377 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2379 /* different name --> ship out current template list;
2380 add to hash table; & begin anew. */
2381 core_optab
->end
= optab
;
2382 hash_err
= hash_insert (op_hash
,
2384 (void *) core_optab
);
2387 as_fatal (_("can't hash %s: %s"),
2391 if (optab
->name
== NULL
)
2393 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2394 core_optab
->start
= optab
;
2399 /* Initialize reg_hash hash table. */
2400 reg_hash
= hash_new ();
2402 const reg_entry
*regtab
;
2403 unsigned int regtab_size
= i386_regtab_size
;
2405 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2407 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2409 as_fatal (_("can't hash %s: %s"),
2415 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2420 for (c
= 0; c
< 256; c
++)
2425 mnemonic_chars
[c
] = c
;
2426 register_chars
[c
] = c
;
2427 operand_chars
[c
] = c
;
2429 else if (ISLOWER (c
))
2431 mnemonic_chars
[c
] = c
;
2432 register_chars
[c
] = c
;
2433 operand_chars
[c
] = c
;
2435 else if (ISUPPER (c
))
2437 mnemonic_chars
[c
] = TOLOWER (c
);
2438 register_chars
[c
] = mnemonic_chars
[c
];
2439 operand_chars
[c
] = c
;
2442 if (ISALPHA (c
) || ISDIGIT (c
))
2443 identifier_chars
[c
] = c
;
2446 identifier_chars
[c
] = c
;
2447 operand_chars
[c
] = c
;
2452 identifier_chars
['@'] = '@';
2455 identifier_chars
['?'] = '?';
2456 operand_chars
['?'] = '?';
2458 digit_chars
['-'] = '-';
2459 mnemonic_chars
['_'] = '_';
2460 mnemonic_chars
['-'] = '-';
2461 mnemonic_chars
['.'] = '.';
2462 identifier_chars
['_'] = '_';
2463 identifier_chars
['.'] = '.';
2465 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2466 operand_chars
[(unsigned char) *p
] = *p
;
2469 if (flag_code
== CODE_64BIT
)
2471 #if defined (OBJ_COFF) && defined (TE_PE)
2472 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2475 x86_dwarf2_return_column
= 16;
2477 x86_cie_data_alignment
= -8;
2481 x86_dwarf2_return_column
= 8;
2482 x86_cie_data_alignment
= -4;
2487 i386_print_statistics (FILE *file
)
2489 hash_print_statistics (file
, "i386 opcode", op_hash
);
2490 hash_print_statistics (file
, "i386 register", reg_hash
);
2495 /* Debugging routines for md_assemble. */
2496 static void pte (insn_template
*);
2497 static void pt (i386_operand_type
);
2498 static void pe (expressionS
*);
2499 static void ps (symbolS
*);
2502 pi (char *line
, i386_insn
*x
)
2506 fprintf (stdout
, "%s: template ", line
);
2508 fprintf (stdout
, " address: base %s index %s scale %x\n",
2509 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2510 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2511 x
->log2_scale_factor
);
2512 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2513 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2514 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2515 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2516 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2517 (x
->rex
& REX_W
) != 0,
2518 (x
->rex
& REX_R
) != 0,
2519 (x
->rex
& REX_X
) != 0,
2520 (x
->rex
& REX_B
) != 0);
2521 for (j
= 0; j
< x
->operands
; j
++)
2523 fprintf (stdout
, " #%d: ", j
+ 1);
2525 fprintf (stdout
, "\n");
2526 if (x
->types
[j
].bitfield
.reg8
2527 || x
->types
[j
].bitfield
.reg16
2528 || x
->types
[j
].bitfield
.reg32
2529 || x
->types
[j
].bitfield
.reg64
2530 || x
->types
[j
].bitfield
.regmmx
2531 || x
->types
[j
].bitfield
.regxmm
2532 || x
->types
[j
].bitfield
.regymm
2533 || x
->types
[j
].bitfield
.sreg2
2534 || x
->types
[j
].bitfield
.sreg3
2535 || x
->types
[j
].bitfield
.control
2536 || x
->types
[j
].bitfield
.debug
2537 || x
->types
[j
].bitfield
.test
)
2538 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2539 if (operand_type_check (x
->types
[j
], imm
))
2541 if (operand_type_check (x
->types
[j
], disp
))
2542 pe (x
->op
[j
].disps
);
2547 pte (insn_template
*t
)
2550 fprintf (stdout
, " %d operands ", t
->operands
);
2551 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2552 if (t
->extension_opcode
!= None
)
2553 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2554 if (t
->opcode_modifier
.d
)
2555 fprintf (stdout
, "D");
2556 if (t
->opcode_modifier
.w
)
2557 fprintf (stdout
, "W");
2558 fprintf (stdout
, "\n");
2559 for (j
= 0; j
< t
->operands
; j
++)
2561 fprintf (stdout
, " #%d type ", j
+ 1);
2562 pt (t
->operand_types
[j
]);
2563 fprintf (stdout
, "\n");
2570 fprintf (stdout
, " operation %d\n", e
->X_op
);
2571 fprintf (stdout
, " add_number %ld (%lx)\n",
2572 (long) e
->X_add_number
, (long) e
->X_add_number
);
2573 if (e
->X_add_symbol
)
2575 fprintf (stdout
, " add_symbol ");
2576 ps (e
->X_add_symbol
);
2577 fprintf (stdout
, "\n");
2581 fprintf (stdout
, " op_symbol ");
2582 ps (e
->X_op_symbol
);
2583 fprintf (stdout
, "\n");
2590 fprintf (stdout
, "%s type %s%s",
2592 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2593 segment_name (S_GET_SEGMENT (s
)));
2596 static struct type_name
2598 i386_operand_type mask
;
2601 const type_names
[] =
2603 { OPERAND_TYPE_REG8
, "r8" },
2604 { OPERAND_TYPE_REG16
, "r16" },
2605 { OPERAND_TYPE_REG32
, "r32" },
2606 { OPERAND_TYPE_REG64
, "r64" },
2607 { OPERAND_TYPE_IMM8
, "i8" },
2608 { OPERAND_TYPE_IMM8
, "i8s" },
2609 { OPERAND_TYPE_IMM16
, "i16" },
2610 { OPERAND_TYPE_IMM32
, "i32" },
2611 { OPERAND_TYPE_IMM32S
, "i32s" },
2612 { OPERAND_TYPE_IMM64
, "i64" },
2613 { OPERAND_TYPE_IMM1
, "i1" },
2614 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2615 { OPERAND_TYPE_DISP8
, "d8" },
2616 { OPERAND_TYPE_DISP16
, "d16" },
2617 { OPERAND_TYPE_DISP32
, "d32" },
2618 { OPERAND_TYPE_DISP32S
, "d32s" },
2619 { OPERAND_TYPE_DISP64
, "d64" },
2620 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2621 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2622 { OPERAND_TYPE_CONTROL
, "control reg" },
2623 { OPERAND_TYPE_TEST
, "test reg" },
2624 { OPERAND_TYPE_DEBUG
, "debug reg" },
2625 { OPERAND_TYPE_FLOATREG
, "FReg" },
2626 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2627 { OPERAND_TYPE_SREG2
, "SReg2" },
2628 { OPERAND_TYPE_SREG3
, "SReg3" },
2629 { OPERAND_TYPE_ACC
, "Acc" },
2630 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2631 { OPERAND_TYPE_REGMMX
, "rMMX" },
2632 { OPERAND_TYPE_REGXMM
, "rXMM" },
2633 { OPERAND_TYPE_REGYMM
, "rYMM" },
2634 { OPERAND_TYPE_ESSEG
, "es" },
2638 pt (i386_operand_type t
)
2641 i386_operand_type a
;
2643 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2645 a
= operand_type_and (t
, type_names
[j
].mask
);
2646 if (!operand_type_all_zero (&a
))
2647 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2652 #endif /* DEBUG386 */
2654 static bfd_reloc_code_real_type
2655 reloc (unsigned int size
,
2658 bfd_reloc_code_real_type other
)
2660 if (other
!= NO_RELOC
)
2662 reloc_howto_type
*rel
;
2667 case BFD_RELOC_X86_64_GOT32
:
2668 return BFD_RELOC_X86_64_GOT64
;
2670 case BFD_RELOC_X86_64_PLTOFF64
:
2671 return BFD_RELOC_X86_64_PLTOFF64
;
2673 case BFD_RELOC_X86_64_GOTPC32
:
2674 other
= BFD_RELOC_X86_64_GOTPC64
;
2676 case BFD_RELOC_X86_64_GOTPCREL
:
2677 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2679 case BFD_RELOC_X86_64_TPOFF32
:
2680 other
= BFD_RELOC_X86_64_TPOFF64
;
2682 case BFD_RELOC_X86_64_DTPOFF32
:
2683 other
= BFD_RELOC_X86_64_DTPOFF64
;
2689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2690 if (other
== BFD_RELOC_SIZE32
)
2693 return BFD_RELOC_SIZE64
;
2695 as_bad (_("there are no pc-relative size relocations"));
2699 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2700 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2703 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2705 as_bad (_("unknown relocation (%u)"), other
);
2706 else if (size
!= bfd_get_reloc_size (rel
))
2707 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2708 bfd_get_reloc_size (rel
),
2710 else if (pcrel
&& !rel
->pc_relative
)
2711 as_bad (_("non-pc-relative relocation for pc-relative field"));
2712 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2714 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2716 as_bad (_("relocated field and relocation type differ in signedness"));
2725 as_bad (_("there are no unsigned pc-relative relocations"));
2728 case 1: return BFD_RELOC_8_PCREL
;
2729 case 2: return BFD_RELOC_16_PCREL
;
2730 case 4: return BFD_RELOC_32_PCREL
;
2731 case 8: return BFD_RELOC_64_PCREL
;
2733 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2740 case 4: return BFD_RELOC_X86_64_32S
;
2745 case 1: return BFD_RELOC_8
;
2746 case 2: return BFD_RELOC_16
;
2747 case 4: return BFD_RELOC_32
;
2748 case 8: return BFD_RELOC_64
;
2750 as_bad (_("cannot do %s %u byte relocation"),
2751 sign
> 0 ? "signed" : "unsigned", size
);
2757 /* Here we decide which fixups can be adjusted to make them relative to
2758 the beginning of the section instead of the symbol. Basically we need
2759 to make sure that the dynamic relocations are done correctly, so in
2760 some cases we force the original symbol to be used. */
2763 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2769 /* Don't adjust pc-relative references to merge sections in 64-bit
2771 if (use_rela_relocations
2772 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2776 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2777 and changed later by validate_fix. */
2778 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2779 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2782 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2783 for size relocations. */
2784 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2785 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2786 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2787 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2788 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2789 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2790 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2791 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2792 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2793 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2794 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2795 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2796 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2797 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2798 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2799 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2800 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2801 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2802 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2803 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2804 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2805 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2806 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2807 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2808 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2809 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2810 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2811 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2812 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2813 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2820 intel_float_operand (const char *mnemonic
)
2822 /* Note that the value returned is meaningful only for opcodes with (memory)
2823 operands, hence the code here is free to improperly handle opcodes that
2824 have no operands (for better performance and smaller code). */
2826 if (mnemonic
[0] != 'f')
2827 return 0; /* non-math */
2829 switch (mnemonic
[1])
2831 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2832 the fs segment override prefix not currently handled because no
2833 call path can make opcodes without operands get here */
2835 return 2 /* integer op */;
2837 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2838 return 3; /* fldcw/fldenv */
2841 if (mnemonic
[2] != 'o' /* fnop */)
2842 return 3; /* non-waiting control op */
2845 if (mnemonic
[2] == 's')
2846 return 3; /* frstor/frstpm */
2849 if (mnemonic
[2] == 'a')
2850 return 3; /* fsave */
2851 if (mnemonic
[2] == 't')
2853 switch (mnemonic
[3])
2855 case 'c': /* fstcw */
2856 case 'd': /* fstdw */
2857 case 'e': /* fstenv */
2858 case 's': /* fsts[gw] */
2864 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2865 return 0; /* fxsave/fxrstor are not really math ops */
2872 /* Build the VEX prefix. */
2875 build_vex_prefix (const insn_template
*t
)
2877 unsigned int register_specifier
;
2878 unsigned int implied_prefix
;
2879 unsigned int vector_length
;
2881 /* Check register specifier. */
2882 if (i
.vex
.register_specifier
)
2883 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2885 register_specifier
= 0xf;
2887 /* Use 2-byte VEX prefix by swappping destination and source
2890 && i
.operands
== i
.reg_operands
2891 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2892 && i
.tm
.opcode_modifier
.s
2895 unsigned int xchg
= i
.operands
- 1;
2896 union i386_op temp_op
;
2897 i386_operand_type temp_type
;
2899 temp_type
= i
.types
[xchg
];
2900 i
.types
[xchg
] = i
.types
[0];
2901 i
.types
[0] = temp_type
;
2902 temp_op
= i
.op
[xchg
];
2903 i
.op
[xchg
] = i
.op
[0];
2906 gas_assert (i
.rm
.mode
== 3);
2910 i
.rm
.regmem
= i
.rm
.reg
;
2913 /* Use the next insn. */
2917 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2918 vector_length
= avxscalar
;
2920 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2922 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2927 case DATA_PREFIX_OPCODE
:
2930 case REPE_PREFIX_OPCODE
:
2933 case REPNE_PREFIX_OPCODE
:
2940 /* Use 2-byte VEX prefix if possible. */
2941 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2942 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2943 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2945 /* 2-byte VEX prefix. */
2949 i
.vex
.bytes
[0] = 0xc5;
2951 /* Check the REX.R bit. */
2952 r
= (i
.rex
& REX_R
) ? 0 : 1;
2953 i
.vex
.bytes
[1] = (r
<< 7
2954 | register_specifier
<< 3
2955 | vector_length
<< 2
2960 /* 3-byte VEX prefix. */
2965 switch (i
.tm
.opcode_modifier
.vexopcode
)
2969 i
.vex
.bytes
[0] = 0xc4;
2973 i
.vex
.bytes
[0] = 0xc4;
2977 i
.vex
.bytes
[0] = 0xc4;
2981 i
.vex
.bytes
[0] = 0x8f;
2985 i
.vex
.bytes
[0] = 0x8f;
2989 i
.vex
.bytes
[0] = 0x8f;
2995 /* The high 3 bits of the second VEX byte are 1's compliment
2996 of RXB bits from REX. */
2997 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2999 /* Check the REX.W bit. */
3000 w
= (i
.rex
& REX_W
) ? 1 : 0;
3001 if (i
.tm
.opcode_modifier
.vexw
)
3006 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3010 i
.vex
.bytes
[2] = (w
<< 7
3011 | register_specifier
<< 3
3012 | vector_length
<< 2
3018 process_immext (void)
3022 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3025 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3026 with an opcode suffix which is coded in the same place as an
3027 8-bit immediate field would be.
3028 Here we check those operands and remove them afterwards. */
3031 for (x
= 0; x
< i
.operands
; x
++)
3032 if (register_number (i
.op
[x
].regs
) != x
)
3033 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3034 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3040 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3041 which is coded in the same place as an 8-bit immediate field
3042 would be. Here we fake an 8-bit immediate operand from the
3043 opcode suffix stored in tm.extension_opcode.
3045 AVX instructions also use this encoding, for some of
3046 3 argument instructions. */
3048 gas_assert (i
.imm_operands
== 0
3050 || (i
.tm
.opcode_modifier
.vex
3051 && i
.operands
<= 4)));
3053 exp
= &im_expressions
[i
.imm_operands
++];
3054 i
.op
[i
.operands
].imms
= exp
;
3055 i
.types
[i
.operands
] = imm8
;
3057 exp
->X_op
= O_constant
;
3058 exp
->X_add_number
= i
.tm
.extension_opcode
;
3059 i
.tm
.extension_opcode
= None
;
3066 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3071 as_bad (_("invalid instruction `%s' after `%s'"),
3072 i
.tm
.name
, i
.hle_prefix
);
3075 if (i
.prefix
[LOCK_PREFIX
])
3077 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3081 case HLEPrefixRelease
:
3082 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3084 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3088 if (i
.mem_operands
== 0
3089 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3091 as_bad (_("memory destination needed for instruction `%s'"
3092 " after `xrelease'"), i
.tm
.name
);
3099 /* This is the guts of the machine-dependent assembler. LINE points to a
3100 machine dependent instruction. This function is supposed to emit
3101 the frags/bytes it assembles to. */
3104 md_assemble (char *line
)
3107 char mnemonic
[MAX_MNEM_SIZE
];
3108 const insn_template
*t
;
3110 /* Initialize globals. */
3111 memset (&i
, '\0', sizeof (i
));
3112 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3113 i
.reloc
[j
] = NO_RELOC
;
3114 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3115 memset (im_expressions
, '\0', sizeof (im_expressions
));
3116 save_stack_p
= save_stack
;
3118 /* First parse an instruction mnemonic & call i386_operand for the operands.
3119 We assume that the scrubber has arranged it so that line[0] is the valid
3120 start of a (possibly prefixed) mnemonic. */
3122 line
= parse_insn (line
, mnemonic
);
3126 line
= parse_operands (line
, mnemonic
);
3131 /* Now we've parsed the mnemonic into a set of templates, and have the
3132 operands at hand. */
3134 /* All intel opcodes have reversed operands except for "bound" and
3135 "enter". We also don't reverse intersegment "jmp" and "call"
3136 instructions with 2 immediate operands so that the immediate segment
3137 precedes the offset, as it does when in AT&T mode. */
3140 && (strcmp (mnemonic
, "bound") != 0)
3141 && (strcmp (mnemonic
, "invlpga") != 0)
3142 && !(operand_type_check (i
.types
[0], imm
)
3143 && operand_type_check (i
.types
[1], imm
)))
3146 /* The order of the immediates should be reversed
3147 for 2 immediates extrq and insertq instructions */
3148 if (i
.imm_operands
== 2
3149 && (strcmp (mnemonic
, "extrq") == 0
3150 || strcmp (mnemonic
, "insertq") == 0))
3151 swap_2_operands (0, 1);
3156 /* Don't optimize displacement for movabs since it only takes 64bit
3159 && i
.disp_encoding
!= disp_encoding_32bit
3160 && (flag_code
!= CODE_64BIT
3161 || strcmp (mnemonic
, "movabs") != 0))
3164 /* Next, we find a template that matches the given insn,
3165 making sure the overlap of the given operands types is consistent
3166 with the template operand types. */
3168 if (!(t
= match_template ()))
3171 if (sse_check
!= check_none
3172 && !i
.tm
.opcode_modifier
.noavx
3173 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3174 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3175 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3176 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3177 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3178 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3180 (sse_check
== check_warning
3182 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3185 /* Zap movzx and movsx suffix. The suffix has been set from
3186 "word ptr" or "byte ptr" on the source operand in Intel syntax
3187 or extracted from mnemonic in AT&T syntax. But we'll use
3188 the destination register to choose the suffix for encoding. */
3189 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3191 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3192 there is no suffix, the default will be byte extension. */
3193 if (i
.reg_operands
!= 2
3196 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3201 if (i
.tm
.opcode_modifier
.fwait
)
3202 if (!add_prefix (FWAIT_OPCODE
))
3205 /* Check if REP prefix is OK. */
3206 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3208 as_bad (_("invalid instruction `%s' after `%s'"),
3209 i
.tm
.name
, i
.rep_prefix
);
3213 /* Check for lock without a lockable instruction. Destination operand
3214 must be memory unless it is xchg (0x86). */
3215 if (i
.prefix
[LOCK_PREFIX
]
3216 && (!i
.tm
.opcode_modifier
.islockable
3217 || i
.mem_operands
== 0
3218 || (i
.tm
.base_opcode
!= 0x86
3219 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3221 as_bad (_("expecting lockable instruction after `lock'"));
3225 /* Check if HLE prefix is OK. */
3226 if (i
.hle_prefix
&& !check_hle ())
3229 /* Check BND prefix. */
3230 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3231 as_bad (_("expecting valid branch instruction after `bnd'"));
3233 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3234 && flag_code
== CODE_64BIT
3235 && i
.prefix
[ADDR_PREFIX
])
3236 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3238 /* Insert BND prefix. */
3240 && i
.tm
.opcode_modifier
.bndprefixok
3241 && !i
.prefix
[BND_PREFIX
])
3242 add_prefix (BND_PREFIX_OPCODE
);
3244 /* Check string instruction segment overrides. */
3245 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3247 if (!check_string ())
3249 i
.disp_operands
= 0;
3252 if (!process_suffix ())
3255 /* Update operand types. */
3256 for (j
= 0; j
< i
.operands
; j
++)
3257 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3259 /* Make still unresolved immediate matches conform to size of immediate
3260 given in i.suffix. */
3261 if (!finalize_imm ())
3264 if (i
.types
[0].bitfield
.imm1
)
3265 i
.imm_operands
= 0; /* kludge for shift insns. */
3267 /* We only need to check those implicit registers for instructions
3268 with 3 operands or less. */
3269 if (i
.operands
<= 3)
3270 for (j
= 0; j
< i
.operands
; j
++)
3271 if (i
.types
[j
].bitfield
.inoutportreg
3272 || i
.types
[j
].bitfield
.shiftcount
3273 || i
.types
[j
].bitfield
.acc
3274 || i
.types
[j
].bitfield
.floatacc
)
3277 /* ImmExt should be processed after SSE2AVX. */
3278 if (!i
.tm
.opcode_modifier
.sse2avx
3279 && i
.tm
.opcode_modifier
.immext
)
3282 /* For insns with operands there are more diddles to do to the opcode. */
3285 if (!process_operands ())
3288 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3290 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3291 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3294 if (i
.tm
.opcode_modifier
.vex
)
3295 build_vex_prefix (t
);
3297 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3298 instructions may define INT_OPCODE as well, so avoid this corner
3299 case for those instructions that use MODRM. */
3300 if (i
.tm
.base_opcode
== INT_OPCODE
3301 && !i
.tm
.opcode_modifier
.modrm
3302 && i
.op
[0].imms
->X_add_number
== 3)
3304 i
.tm
.base_opcode
= INT3_OPCODE
;
3308 if ((i
.tm
.opcode_modifier
.jump
3309 || i
.tm
.opcode_modifier
.jumpbyte
3310 || i
.tm
.opcode_modifier
.jumpdword
)
3311 && i
.op
[0].disps
->X_op
== O_constant
)
3313 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3314 the absolute address given by the constant. Since ix86 jumps and
3315 calls are pc relative, we need to generate a reloc. */
3316 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3317 i
.op
[0].disps
->X_op
= O_symbol
;
3320 if (i
.tm
.opcode_modifier
.rex64
)
3323 /* For 8 bit registers we need an empty rex prefix. Also if the
3324 instruction already has a prefix, we need to convert old
3325 registers to new ones. */
3327 if ((i
.types
[0].bitfield
.reg8
3328 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3329 || (i
.types
[1].bitfield
.reg8
3330 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3331 || ((i
.types
[0].bitfield
.reg8
3332 || i
.types
[1].bitfield
.reg8
)
3337 i
.rex
|= REX_OPCODE
;
3338 for (x
= 0; x
< 2; x
++)
3340 /* Look for 8 bit operand that uses old registers. */
3341 if (i
.types
[x
].bitfield
.reg8
3342 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3344 /* In case it is "hi" register, give up. */
3345 if (i
.op
[x
].regs
->reg_num
> 3)
3346 as_bad (_("can't encode register '%s%s' in an "
3347 "instruction requiring REX prefix."),
3348 register_prefix
, i
.op
[x
].regs
->reg_name
);
3350 /* Otherwise it is equivalent to the extended register.
3351 Since the encoding doesn't change this is merely
3352 cosmetic cleanup for debug output. */
3354 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3360 add_prefix (REX_OPCODE
| i
.rex
);
3362 /* We are ready to output the insn. */
3367 parse_insn (char *line
, char *mnemonic
)
3370 char *token_start
= l
;
3373 const insn_template
*t
;
3379 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3384 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3386 as_bad (_("no such instruction: `%s'"), token_start
);
3391 if (!is_space_char (*l
)
3392 && *l
!= END_OF_INSN
3394 || (*l
!= PREFIX_SEPARATOR
3397 as_bad (_("invalid character %s in mnemonic"),
3398 output_invalid (*l
));
3401 if (token_start
== l
)
3403 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3404 as_bad (_("expecting prefix; got nothing"));
3406 as_bad (_("expecting mnemonic; got nothing"));
3410 /* Look up instruction (or prefix) via hash table. */
3411 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3413 if (*l
!= END_OF_INSN
3414 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3415 && current_templates
3416 && current_templates
->start
->opcode_modifier
.isprefix
)
3418 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3420 as_bad ((flag_code
!= CODE_64BIT
3421 ? _("`%s' is only supported in 64-bit mode")
3422 : _("`%s' is not supported in 64-bit mode")),
3423 current_templates
->start
->name
);
3426 /* If we are in 16-bit mode, do not allow addr16 or data16.
3427 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3428 if ((current_templates
->start
->opcode_modifier
.size16
3429 || current_templates
->start
->opcode_modifier
.size32
)
3430 && flag_code
!= CODE_64BIT
3431 && (current_templates
->start
->opcode_modifier
.size32
3432 ^ (flag_code
== CODE_16BIT
)))
3434 as_bad (_("redundant %s prefix"),
3435 current_templates
->start
->name
);
3438 /* Add prefix, checking for repeated prefixes. */
3439 switch (add_prefix (current_templates
->start
->base_opcode
))
3444 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3445 i
.hle_prefix
= current_templates
->start
->name
;
3446 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3447 i
.bnd_prefix
= current_templates
->start
->name
;
3449 i
.rep_prefix
= current_templates
->start
->name
;
3454 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3461 if (!current_templates
)
3463 /* Check if we should swap operand or force 32bit displacement in
3465 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3467 else if (mnem_p
- 3 == dot_p
3470 i
.disp_encoding
= disp_encoding_8bit
;
3471 else if (mnem_p
- 4 == dot_p
3475 i
.disp_encoding
= disp_encoding_32bit
;
3480 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3483 if (!current_templates
)
3486 /* See if we can get a match by trimming off a suffix. */
3489 case WORD_MNEM_SUFFIX
:
3490 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3491 i
.suffix
= SHORT_MNEM_SUFFIX
;
3493 case BYTE_MNEM_SUFFIX
:
3494 case QWORD_MNEM_SUFFIX
:
3495 i
.suffix
= mnem_p
[-1];
3497 current_templates
= (const templates
*) hash_find (op_hash
,
3500 case SHORT_MNEM_SUFFIX
:
3501 case LONG_MNEM_SUFFIX
:
3504 i
.suffix
= mnem_p
[-1];
3506 current_templates
= (const templates
*) hash_find (op_hash
,
3515 if (intel_float_operand (mnemonic
) == 1)
3516 i
.suffix
= SHORT_MNEM_SUFFIX
;
3518 i
.suffix
= LONG_MNEM_SUFFIX
;
3520 current_templates
= (const templates
*) hash_find (op_hash
,
3525 if (!current_templates
)
3527 as_bad (_("no such instruction: `%s'"), token_start
);
3532 if (current_templates
->start
->opcode_modifier
.jump
3533 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3535 /* Check for a branch hint. We allow ",pt" and ",pn" for
3536 predict taken and predict not taken respectively.
3537 I'm not sure that branch hints actually do anything on loop
3538 and jcxz insns (JumpByte) for current Pentium4 chips. They
3539 may work in the future and it doesn't hurt to accept them
3541 if (l
[0] == ',' && l
[1] == 'p')
3545 if (!add_prefix (DS_PREFIX_OPCODE
))
3549 else if (l
[2] == 'n')
3551 if (!add_prefix (CS_PREFIX_OPCODE
))
3557 /* Any other comma loses. */
3560 as_bad (_("invalid character %s in mnemonic"),
3561 output_invalid (*l
));
3565 /* Check if instruction is supported on specified architecture. */
3567 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3569 supported
|= cpu_flags_match (t
);
3570 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3574 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3576 as_bad (flag_code
== CODE_64BIT
3577 ? _("`%s' is not supported in 64-bit mode")
3578 : _("`%s' is only supported in 64-bit mode"),
3579 current_templates
->start
->name
);
3582 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3584 as_bad (_("`%s' is not supported on `%s%s'"),
3585 current_templates
->start
->name
,
3586 cpu_arch_name
? cpu_arch_name
: default_arch
,
3587 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3592 if (!cpu_arch_flags
.bitfield
.cpui386
3593 && (flag_code
!= CODE_16BIT
))
3595 as_warn (_("use .code16 to ensure correct addressing mode"));
3602 parse_operands (char *l
, const char *mnemonic
)
3606 /* 1 if operand is pending after ','. */
3607 unsigned int expecting_operand
= 0;
3609 /* Non-zero if operand parens not balanced. */
3610 unsigned int paren_not_balanced
;
3612 while (*l
!= END_OF_INSN
)
3614 /* Skip optional white space before operand. */
3615 if (is_space_char (*l
))
3617 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3619 as_bad (_("invalid character %s before operand %d"),
3620 output_invalid (*l
),
3624 token_start
= l
; /* after white space */
3625 paren_not_balanced
= 0;
3626 while (paren_not_balanced
|| *l
!= ',')
3628 if (*l
== END_OF_INSN
)
3630 if (paren_not_balanced
)
3633 as_bad (_("unbalanced parenthesis in operand %d."),
3636 as_bad (_("unbalanced brackets in operand %d."),
3641 break; /* we are done */
3643 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3645 as_bad (_("invalid character %s in operand %d"),
3646 output_invalid (*l
),
3653 ++paren_not_balanced
;
3655 --paren_not_balanced
;
3660 ++paren_not_balanced
;
3662 --paren_not_balanced
;
3666 if (l
!= token_start
)
3667 { /* Yes, we've read in another operand. */
3668 unsigned int operand_ok
;
3669 this_operand
= i
.operands
++;
3670 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3671 if (i
.operands
> MAX_OPERANDS
)
3673 as_bad (_("spurious operands; (%d operands/instruction max)"),
3677 /* Now parse operand adding info to 'i' as we go along. */
3678 END_STRING_AND_SAVE (l
);
3682 i386_intel_operand (token_start
,
3683 intel_float_operand (mnemonic
));
3685 operand_ok
= i386_att_operand (token_start
);
3687 RESTORE_END_STRING (l
);
3693 if (expecting_operand
)
3695 expecting_operand_after_comma
:
3696 as_bad (_("expecting operand after ','; got nothing"));
3701 as_bad (_("expecting operand before ','; got nothing"));
3706 /* Now *l must be either ',' or END_OF_INSN. */
3709 if (*++l
== END_OF_INSN
)
3711 /* Just skip it, if it's \n complain. */
3712 goto expecting_operand_after_comma
;
3714 expecting_operand
= 1;
3721 swap_2_operands (int xchg1
, int xchg2
)
3723 union i386_op temp_op
;
3724 i386_operand_type temp_type
;
3725 enum bfd_reloc_code_real temp_reloc
;
3727 temp_type
= i
.types
[xchg2
];
3728 i
.types
[xchg2
] = i
.types
[xchg1
];
3729 i
.types
[xchg1
] = temp_type
;
3730 temp_op
= i
.op
[xchg2
];
3731 i
.op
[xchg2
] = i
.op
[xchg1
];
3732 i
.op
[xchg1
] = temp_op
;
3733 temp_reloc
= i
.reloc
[xchg2
];
3734 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3735 i
.reloc
[xchg1
] = temp_reloc
;
3739 swap_operands (void)
3745 swap_2_operands (1, i
.operands
- 2);
3748 swap_2_operands (0, i
.operands
- 1);
3754 if (i
.mem_operands
== 2)
3756 const seg_entry
*temp_seg
;
3757 temp_seg
= i
.seg
[0];
3758 i
.seg
[0] = i
.seg
[1];
3759 i
.seg
[1] = temp_seg
;
3763 /* Try to ensure constant immediates are represented in the smallest
3768 char guess_suffix
= 0;
3772 guess_suffix
= i
.suffix
;
3773 else if (i
.reg_operands
)
3775 /* Figure out a suffix from the last register operand specified.
3776 We can't do this properly yet, ie. excluding InOutPortReg,
3777 but the following works for instructions with immediates.
3778 In any case, we can't set i.suffix yet. */
3779 for (op
= i
.operands
; --op
>= 0;)
3780 if (i
.types
[op
].bitfield
.reg8
)
3782 guess_suffix
= BYTE_MNEM_SUFFIX
;
3785 else if (i
.types
[op
].bitfield
.reg16
)
3787 guess_suffix
= WORD_MNEM_SUFFIX
;
3790 else if (i
.types
[op
].bitfield
.reg32
)
3792 guess_suffix
= LONG_MNEM_SUFFIX
;
3795 else if (i
.types
[op
].bitfield
.reg64
)
3797 guess_suffix
= QWORD_MNEM_SUFFIX
;
3801 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3802 guess_suffix
= WORD_MNEM_SUFFIX
;
3804 for (op
= i
.operands
; --op
>= 0;)
3805 if (operand_type_check (i
.types
[op
], imm
))
3807 switch (i
.op
[op
].imms
->X_op
)
3810 /* If a suffix is given, this operand may be shortened. */
3811 switch (guess_suffix
)
3813 case LONG_MNEM_SUFFIX
:
3814 i
.types
[op
].bitfield
.imm32
= 1;
3815 i
.types
[op
].bitfield
.imm64
= 1;
3817 case WORD_MNEM_SUFFIX
:
3818 i
.types
[op
].bitfield
.imm16
= 1;
3819 i
.types
[op
].bitfield
.imm32
= 1;
3820 i
.types
[op
].bitfield
.imm32s
= 1;
3821 i
.types
[op
].bitfield
.imm64
= 1;
3823 case BYTE_MNEM_SUFFIX
:
3824 i
.types
[op
].bitfield
.imm8
= 1;
3825 i
.types
[op
].bitfield
.imm8s
= 1;
3826 i
.types
[op
].bitfield
.imm16
= 1;
3827 i
.types
[op
].bitfield
.imm32
= 1;
3828 i
.types
[op
].bitfield
.imm32s
= 1;
3829 i
.types
[op
].bitfield
.imm64
= 1;
3833 /* If this operand is at most 16 bits, convert it
3834 to a signed 16 bit number before trying to see
3835 whether it will fit in an even smaller size.
3836 This allows a 16-bit operand such as $0xffe0 to
3837 be recognised as within Imm8S range. */
3838 if ((i
.types
[op
].bitfield
.imm16
)
3839 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3841 i
.op
[op
].imms
->X_add_number
=
3842 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3844 if ((i
.types
[op
].bitfield
.imm32
)
3845 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3848 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3849 ^ ((offsetT
) 1 << 31))
3850 - ((offsetT
) 1 << 31));
3853 = operand_type_or (i
.types
[op
],
3854 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3856 /* We must avoid matching of Imm32 templates when 64bit
3857 only immediate is available. */
3858 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3859 i
.types
[op
].bitfield
.imm32
= 0;
3866 /* Symbols and expressions. */
3868 /* Convert symbolic operand to proper sizes for matching, but don't
3869 prevent matching a set of insns that only supports sizes other
3870 than those matching the insn suffix. */
3872 i386_operand_type mask
, allowed
;
3873 const insn_template
*t
;
3875 operand_type_set (&mask
, 0);
3876 operand_type_set (&allowed
, 0);
3878 for (t
= current_templates
->start
;
3879 t
< current_templates
->end
;
3881 allowed
= operand_type_or (allowed
,
3882 t
->operand_types
[op
]);
3883 switch (guess_suffix
)
3885 case QWORD_MNEM_SUFFIX
:
3886 mask
.bitfield
.imm64
= 1;
3887 mask
.bitfield
.imm32s
= 1;
3889 case LONG_MNEM_SUFFIX
:
3890 mask
.bitfield
.imm32
= 1;
3892 case WORD_MNEM_SUFFIX
:
3893 mask
.bitfield
.imm16
= 1;
3895 case BYTE_MNEM_SUFFIX
:
3896 mask
.bitfield
.imm8
= 1;
3901 allowed
= operand_type_and (mask
, allowed
);
3902 if (!operand_type_all_zero (&allowed
))
3903 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3910 /* Try to use the smallest displacement type too. */
3912 optimize_disp (void)
3916 for (op
= i
.operands
; --op
>= 0;)
3917 if (operand_type_check (i
.types
[op
], disp
))
3919 if (i
.op
[op
].disps
->X_op
== O_constant
)
3921 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3923 if (i
.types
[op
].bitfield
.disp16
3924 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3926 /* If this operand is at most 16 bits, convert
3927 to a signed 16 bit number and don't use 64bit
3929 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3930 i
.types
[op
].bitfield
.disp64
= 0;
3932 if (i
.types
[op
].bitfield
.disp32
3933 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3935 /* If this operand is at most 32 bits, convert
3936 to a signed 32 bit number and don't use 64bit
3938 op_disp
&= (((offsetT
) 2 << 31) - 1);
3939 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3940 i
.types
[op
].bitfield
.disp64
= 0;
3942 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3944 i
.types
[op
].bitfield
.disp8
= 0;
3945 i
.types
[op
].bitfield
.disp16
= 0;
3946 i
.types
[op
].bitfield
.disp32
= 0;
3947 i
.types
[op
].bitfield
.disp32s
= 0;
3948 i
.types
[op
].bitfield
.disp64
= 0;
3952 else if (flag_code
== CODE_64BIT
)
3954 if (fits_in_signed_long (op_disp
))
3956 i
.types
[op
].bitfield
.disp64
= 0;
3957 i
.types
[op
].bitfield
.disp32s
= 1;
3959 if (i
.prefix
[ADDR_PREFIX
]
3960 && fits_in_unsigned_long (op_disp
))
3961 i
.types
[op
].bitfield
.disp32
= 1;
3963 if ((i
.types
[op
].bitfield
.disp32
3964 || i
.types
[op
].bitfield
.disp32s
3965 || i
.types
[op
].bitfield
.disp16
)
3966 && fits_in_signed_byte (op_disp
))
3967 i
.types
[op
].bitfield
.disp8
= 1;
3969 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3970 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3972 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3973 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3974 i
.types
[op
].bitfield
.disp8
= 0;
3975 i
.types
[op
].bitfield
.disp16
= 0;
3976 i
.types
[op
].bitfield
.disp32
= 0;
3977 i
.types
[op
].bitfield
.disp32s
= 0;
3978 i
.types
[op
].bitfield
.disp64
= 0;
3981 /* We only support 64bit displacement on constants. */
3982 i
.types
[op
].bitfield
.disp64
= 0;
3986 /* Check if operands are valid for the instruction. */
3989 check_VecOperands (const insn_template
*t
)
3991 /* Without VSIB byte, we can't have a vector register for index. */
3992 if (!t
->opcode_modifier
.vecsib
3994 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3995 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3997 i
.error
= unsupported_vector_index_register
;
4001 /* For VSIB byte, we need a vector register for index, and all vector
4002 registers must be distinct. */
4003 if (t
->opcode_modifier
.vecsib
)
4006 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4007 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4008 || (t
->opcode_modifier
.vecsib
== VecSIB256
4009 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
4011 i
.error
= invalid_vsib_address
;
4015 gas_assert (i
.reg_operands
== 2);
4016 gas_assert (i
.types
[0].bitfield
.regxmm
4017 || i
.types
[0].bitfield
.regymm
);
4018 gas_assert (i
.types
[2].bitfield
.regxmm
4019 || i
.types
[2].bitfield
.regymm
);
4021 if (operand_check
== check_none
)
4023 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4024 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4025 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4027 if (operand_check
== check_error
)
4029 i
.error
= invalid_vector_register_set
;
4032 as_warn (_("mask, index, and destination registers should be distinct"));
4038 /* Check if operands are valid for the instruction. Update VEX
4042 VEX_check_operands (const insn_template
*t
)
4044 if (!t
->opcode_modifier
.vex
)
4047 /* Only check VEX_Imm4, which must be the first operand. */
4048 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4050 if (i
.op
[0].imms
->X_op
!= O_constant
4051 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4057 /* Turn off Imm8 so that update_imm won't complain. */
4058 i
.types
[0] = vec_imm4
;
4064 static const insn_template
*
4065 match_template (void)
4067 /* Points to template once we've found it. */
4068 const insn_template
*t
;
4069 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4070 i386_operand_type overlap4
;
4071 unsigned int found_reverse_match
;
4072 i386_opcode_modifier suffix_check
;
4073 i386_operand_type operand_types
[MAX_OPERANDS
];
4074 int addr_prefix_disp
;
4076 unsigned int found_cpu_match
;
4077 unsigned int check_register
;
4078 enum i386_error specific_error
= 0;
4080 #if MAX_OPERANDS != 5
4081 # error "MAX_OPERANDS must be 5."
4084 found_reverse_match
= 0;
4085 addr_prefix_disp
= -1;
4087 memset (&suffix_check
, 0, sizeof (suffix_check
));
4088 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4089 suffix_check
.no_bsuf
= 1;
4090 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4091 suffix_check
.no_wsuf
= 1;
4092 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4093 suffix_check
.no_ssuf
= 1;
4094 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4095 suffix_check
.no_lsuf
= 1;
4096 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4097 suffix_check
.no_qsuf
= 1;
4098 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4099 suffix_check
.no_ldsuf
= 1;
4101 /* Must have right number of operands. */
4102 i
.error
= number_of_operands_mismatch
;
4104 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4106 addr_prefix_disp
= -1;
4108 if (i
.operands
!= t
->operands
)
4111 /* Check processor support. */
4112 i
.error
= unsupported
;
4113 found_cpu_match
= (cpu_flags_match (t
)
4114 == CPU_FLAGS_PERFECT_MATCH
);
4115 if (!found_cpu_match
)
4118 /* Check old gcc support. */
4119 i
.error
= old_gcc_only
;
4120 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4123 /* Check AT&T mnemonic. */
4124 i
.error
= unsupported_with_intel_mnemonic
;
4125 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4128 /* Check AT&T/Intel syntax. */
4129 i
.error
= unsupported_syntax
;
4130 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4131 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4134 /* Check the suffix, except for some instructions in intel mode. */
4135 i
.error
= invalid_instruction_suffix
;
4136 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4137 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4138 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4139 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4140 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4141 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4142 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4145 if (!operand_size_match (t
))
4148 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4149 operand_types
[j
] = t
->operand_types
[j
];
4151 /* In general, don't allow 64-bit operands in 32-bit mode. */
4152 if (i
.suffix
== QWORD_MNEM_SUFFIX
4153 && flag_code
!= CODE_64BIT
4155 ? (!t
->opcode_modifier
.ignoresize
4156 && !intel_float_operand (t
->name
))
4157 : intel_float_operand (t
->name
) != 2)
4158 && ((!operand_types
[0].bitfield
.regmmx
4159 && !operand_types
[0].bitfield
.regxmm
4160 && !operand_types
[0].bitfield
.regymm
)
4161 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4162 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4163 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4164 && (t
->base_opcode
!= 0x0fc7
4165 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4168 /* In general, don't allow 32-bit operands on pre-386. */
4169 else if (i
.suffix
== LONG_MNEM_SUFFIX
4170 && !cpu_arch_flags
.bitfield
.cpui386
4172 ? (!t
->opcode_modifier
.ignoresize
4173 && !intel_float_operand (t
->name
))
4174 : intel_float_operand (t
->name
) != 2)
4175 && ((!operand_types
[0].bitfield
.regmmx
4176 && !operand_types
[0].bitfield
.regxmm
)
4177 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4178 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4181 /* Do not verify operands when there are none. */
4185 /* We've found a match; break out of loop. */
4189 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4190 into Disp32/Disp16/Disp32 operand. */
4191 if (i
.prefix
[ADDR_PREFIX
] != 0)
4193 /* There should be only one Disp operand. */
4197 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4199 if (operand_types
[j
].bitfield
.disp16
)
4201 addr_prefix_disp
= j
;
4202 operand_types
[j
].bitfield
.disp32
= 1;
4203 operand_types
[j
].bitfield
.disp16
= 0;
4209 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4211 if (operand_types
[j
].bitfield
.disp32
)
4213 addr_prefix_disp
= j
;
4214 operand_types
[j
].bitfield
.disp32
= 0;
4215 operand_types
[j
].bitfield
.disp16
= 1;
4221 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4223 if (operand_types
[j
].bitfield
.disp64
)
4225 addr_prefix_disp
= j
;
4226 operand_types
[j
].bitfield
.disp64
= 0;
4227 operand_types
[j
].bitfield
.disp32
= 1;
4235 /* We check register size if needed. */
4236 check_register
= t
->opcode_modifier
.checkregsize
;
4237 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4238 switch (t
->operands
)
4241 if (!operand_type_match (overlap0
, i
.types
[0]))
4245 /* xchg %eax, %eax is a special case. It is an aliase for nop
4246 only in 32bit mode and we can use opcode 0x90. In 64bit
4247 mode, we can't use 0x90 for xchg %eax, %eax since it should
4248 zero-extend %eax to %rax. */
4249 if (flag_code
== CODE_64BIT
4250 && t
->base_opcode
== 0x90
4251 && operand_type_equal (&i
.types
[0], &acc32
)
4252 && operand_type_equal (&i
.types
[1], &acc32
))
4256 /* If we swap operand in encoding, we either match
4257 the next one or reverse direction of operands. */
4258 if (t
->opcode_modifier
.s
)
4260 else if (t
->opcode_modifier
.d
)
4265 /* If we swap operand in encoding, we match the next one. */
4266 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4270 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4271 if (!operand_type_match (overlap0
, i
.types
[0])
4272 || !operand_type_match (overlap1
, i
.types
[1])
4274 && !operand_type_register_match (overlap0
, i
.types
[0],
4276 overlap1
, i
.types
[1],
4279 /* Check if other direction is valid ... */
4280 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4284 /* Try reversing direction of operands. */
4285 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4286 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4287 if (!operand_type_match (overlap0
, i
.types
[0])
4288 || !operand_type_match (overlap1
, i
.types
[1])
4290 && !operand_type_register_match (overlap0
,
4297 /* Does not match either direction. */
4300 /* found_reverse_match holds which of D or FloatDR
4302 if (t
->opcode_modifier
.d
)
4303 found_reverse_match
= Opcode_D
;
4304 else if (t
->opcode_modifier
.floatd
)
4305 found_reverse_match
= Opcode_FloatD
;
4307 found_reverse_match
= 0;
4308 if (t
->opcode_modifier
.floatr
)
4309 found_reverse_match
|= Opcode_FloatR
;
4313 /* Found a forward 2 operand match here. */
4314 switch (t
->operands
)
4317 overlap4
= operand_type_and (i
.types
[4],
4320 overlap3
= operand_type_and (i
.types
[3],
4323 overlap2
= operand_type_and (i
.types
[2],
4328 switch (t
->operands
)
4331 if (!operand_type_match (overlap4
, i
.types
[4])
4332 || !operand_type_register_match (overlap3
,
4340 if (!operand_type_match (overlap3
, i
.types
[3])
4342 && !operand_type_register_match (overlap2
,
4350 /* Here we make use of the fact that there are no
4351 reverse match 3 operand instructions, and all 3
4352 operand instructions only need to be checked for
4353 register consistency between operands 2 and 3. */
4354 if (!operand_type_match (overlap2
, i
.types
[2])
4356 && !operand_type_register_match (overlap1
,
4366 /* Found either forward/reverse 2, 3 or 4 operand match here:
4367 slip through to break. */
4369 if (!found_cpu_match
)
4371 found_reverse_match
= 0;
4375 /* Check if vector and VEX operands are valid. */
4376 if (check_VecOperands (t
) || VEX_check_operands (t
))
4378 specific_error
= i
.error
;
4382 /* We've found a match; break out of loop. */
4386 if (t
== current_templates
->end
)
4388 /* We found no match. */
4389 const char *err_msg
;
4390 switch (specific_error
? specific_error
: i
.error
)
4394 case operand_size_mismatch
:
4395 err_msg
= _("operand size mismatch");
4397 case operand_type_mismatch
:
4398 err_msg
= _("operand type mismatch");
4400 case register_type_mismatch
:
4401 err_msg
= _("register type mismatch");
4403 case number_of_operands_mismatch
:
4404 err_msg
= _("number of operands mismatch");
4406 case invalid_instruction_suffix
:
4407 err_msg
= _("invalid instruction suffix");
4410 err_msg
= _("constant doesn't fit in 4 bits");
4413 err_msg
= _("only supported with old gcc");
4415 case unsupported_with_intel_mnemonic
:
4416 err_msg
= _("unsupported with Intel mnemonic");
4418 case unsupported_syntax
:
4419 err_msg
= _("unsupported syntax");
4422 as_bad (_("unsupported instruction `%s'"),
4423 current_templates
->start
->name
);
4425 case invalid_vsib_address
:
4426 err_msg
= _("invalid VSIB address");
4428 case invalid_vector_register_set
:
4429 err_msg
= _("mask, index, and destination registers must be distinct");
4431 case unsupported_vector_index_register
:
4432 err_msg
= _("unsupported vector index register");
4435 as_bad (_("%s for `%s'"), err_msg
,
4436 current_templates
->start
->name
);
4440 if (!quiet_warnings
)
4443 && (i
.types
[0].bitfield
.jumpabsolute
4444 != operand_types
[0].bitfield
.jumpabsolute
))
4446 as_warn (_("indirect %s without `*'"), t
->name
);
4449 if (t
->opcode_modifier
.isprefix
4450 && t
->opcode_modifier
.ignoresize
)
4452 /* Warn them that a data or address size prefix doesn't
4453 affect assembly of the next line of code. */
4454 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4458 /* Copy the template we found. */
4461 if (addr_prefix_disp
!= -1)
4462 i
.tm
.operand_types
[addr_prefix_disp
]
4463 = operand_types
[addr_prefix_disp
];
4465 if (found_reverse_match
)
4467 /* If we found a reverse match we must alter the opcode
4468 direction bit. found_reverse_match holds bits to change
4469 (different for int & float insns). */
4471 i
.tm
.base_opcode
^= found_reverse_match
;
4473 i
.tm
.operand_types
[0] = operand_types
[1];
4474 i
.tm
.operand_types
[1] = operand_types
[0];
4483 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4484 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4486 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4488 as_bad (_("`%s' operand %d must use `%ses' segment"),
4494 /* There's only ever one segment override allowed per instruction.
4495 This instruction possibly has a legal segment override on the
4496 second operand, so copy the segment to where non-string
4497 instructions store it, allowing common code. */
4498 i
.seg
[0] = i
.seg
[1];
4500 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4502 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4504 as_bad (_("`%s' operand %d must use `%ses' segment"),
4515 process_suffix (void)
4517 /* If matched instruction specifies an explicit instruction mnemonic
4519 if (i
.tm
.opcode_modifier
.size16
)
4520 i
.suffix
= WORD_MNEM_SUFFIX
;
4521 else if (i
.tm
.opcode_modifier
.size32
)
4522 i
.suffix
= LONG_MNEM_SUFFIX
;
4523 else if (i
.tm
.opcode_modifier
.size64
)
4524 i
.suffix
= QWORD_MNEM_SUFFIX
;
4525 else if (i
.reg_operands
)
4527 /* If there's no instruction mnemonic suffix we try to invent one
4528 based on register operands. */
4531 /* We take i.suffix from the last register operand specified,
4532 Destination register type is more significant than source
4533 register type. crc32 in SSE4.2 prefers source register
4535 if (i
.tm
.base_opcode
== 0xf20f38f1)
4537 if (i
.types
[0].bitfield
.reg16
)
4538 i
.suffix
= WORD_MNEM_SUFFIX
;
4539 else if (i
.types
[0].bitfield
.reg32
)
4540 i
.suffix
= LONG_MNEM_SUFFIX
;
4541 else if (i
.types
[0].bitfield
.reg64
)
4542 i
.suffix
= QWORD_MNEM_SUFFIX
;
4544 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4546 if (i
.types
[0].bitfield
.reg8
)
4547 i
.suffix
= BYTE_MNEM_SUFFIX
;
4554 if (i
.tm
.base_opcode
== 0xf20f38f1
4555 || i
.tm
.base_opcode
== 0xf20f38f0)
4557 /* We have to know the operand size for crc32. */
4558 as_bad (_("ambiguous memory operand size for `%s`"),
4563 for (op
= i
.operands
; --op
>= 0;)
4564 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4566 if (i
.types
[op
].bitfield
.reg8
)
4568 i
.suffix
= BYTE_MNEM_SUFFIX
;
4571 else if (i
.types
[op
].bitfield
.reg16
)
4573 i
.suffix
= WORD_MNEM_SUFFIX
;
4576 else if (i
.types
[op
].bitfield
.reg32
)
4578 i
.suffix
= LONG_MNEM_SUFFIX
;
4581 else if (i
.types
[op
].bitfield
.reg64
)
4583 i
.suffix
= QWORD_MNEM_SUFFIX
;
4589 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4592 && i
.tm
.opcode_modifier
.ignoresize
4593 && i
.tm
.opcode_modifier
.no_bsuf
)
4595 else if (!check_byte_reg ())
4598 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4601 && i
.tm
.opcode_modifier
.ignoresize
4602 && i
.tm
.opcode_modifier
.no_lsuf
)
4604 else if (!check_long_reg ())
4607 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4610 && i
.tm
.opcode_modifier
.ignoresize
4611 && i
.tm
.opcode_modifier
.no_qsuf
)
4613 else if (!check_qword_reg ())
4616 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4619 && i
.tm
.opcode_modifier
.ignoresize
4620 && i
.tm
.opcode_modifier
.no_wsuf
)
4622 else if (!check_word_reg ())
4625 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4626 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4628 /* Skip if the instruction has x/y suffix. match_template
4629 should check if it is a valid suffix. */
4631 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4632 /* Do nothing if the instruction is going to ignore the prefix. */
4637 else if (i
.tm
.opcode_modifier
.defaultsize
4639 /* exclude fldenv/frstor/fsave/fstenv */
4640 && i
.tm
.opcode_modifier
.no_ssuf
)
4642 i
.suffix
= stackop_size
;
4644 else if (intel_syntax
4646 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4647 || i
.tm
.opcode_modifier
.jumpbyte
4648 || i
.tm
.opcode_modifier
.jumpintersegment
4649 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4650 && i
.tm
.extension_opcode
<= 3)))
4655 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4657 i
.suffix
= QWORD_MNEM_SUFFIX
;
4661 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4662 i
.suffix
= LONG_MNEM_SUFFIX
;
4665 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4666 i
.suffix
= WORD_MNEM_SUFFIX
;
4675 if (i
.tm
.opcode_modifier
.w
)
4677 as_bad (_("no instruction mnemonic suffix given and "
4678 "no register operands; can't size instruction"));
4684 unsigned int suffixes
;
4686 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4687 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4689 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4691 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4693 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4695 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4698 /* There are more than suffix matches. */
4699 if (i
.tm
.opcode_modifier
.w
4700 || ((suffixes
& (suffixes
- 1))
4701 && !i
.tm
.opcode_modifier
.defaultsize
4702 && !i
.tm
.opcode_modifier
.ignoresize
))
4704 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4710 /* Change the opcode based on the operand size given by i.suffix;
4711 We don't need to change things for byte insns. */
4714 && i
.suffix
!= BYTE_MNEM_SUFFIX
4715 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4716 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4718 /* It's not a byte, select word/dword operation. */
4719 if (i
.tm
.opcode_modifier
.w
)
4721 if (i
.tm
.opcode_modifier
.shortform
)
4722 i
.tm
.base_opcode
|= 8;
4724 i
.tm
.base_opcode
|= 1;
4727 /* Now select between word & dword operations via the operand
4728 size prefix, except for instructions that will ignore this
4730 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4732 /* The address size override prefix changes the size of the
4734 if ((flag_code
== CODE_32BIT
4735 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4736 || (flag_code
!= CODE_32BIT
4737 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4738 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4741 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4742 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4743 && !i
.tm
.opcode_modifier
.ignoresize
4744 && !i
.tm
.opcode_modifier
.floatmf
4745 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4746 || (flag_code
== CODE_64BIT
4747 && i
.tm
.opcode_modifier
.jumpbyte
)))
4749 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4751 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4752 prefix
= ADDR_PREFIX_OPCODE
;
4754 if (!add_prefix (prefix
))
4758 /* Set mode64 for an operand. */
4759 if (i
.suffix
== QWORD_MNEM_SUFFIX
4760 && flag_code
== CODE_64BIT
4761 && !i
.tm
.opcode_modifier
.norex64
)
4763 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4764 need rex64. cmpxchg8b is also a special case. */
4765 if (! (i
.operands
== 2
4766 && i
.tm
.base_opcode
== 0x90
4767 && i
.tm
.extension_opcode
== None
4768 && operand_type_equal (&i
.types
[0], &acc64
)
4769 && operand_type_equal (&i
.types
[1], &acc64
))
4770 && ! (i
.operands
== 1
4771 && i
.tm
.base_opcode
== 0xfc7
4772 && i
.tm
.extension_opcode
== 1
4773 && !operand_type_check (i
.types
[0], reg
)
4774 && operand_type_check (i
.types
[0], anymem
)))
4778 /* Size floating point instruction. */
4779 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4780 if (i
.tm
.opcode_modifier
.floatmf
)
4781 i
.tm
.base_opcode
^= 4;
4788 check_byte_reg (void)
4792 for (op
= i
.operands
; --op
>= 0;)
4794 /* If this is an eight bit register, it's OK. If it's the 16 or
4795 32 bit version of an eight bit register, we will just use the
4796 low portion, and that's OK too. */
4797 if (i
.types
[op
].bitfield
.reg8
)
4800 /* I/O port address operands are OK too. */
4801 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4804 /* crc32 doesn't generate this warning. */
4805 if (i
.tm
.base_opcode
== 0xf20f38f0)
4808 if ((i
.types
[op
].bitfield
.reg16
4809 || i
.types
[op
].bitfield
.reg32
4810 || i
.types
[op
].bitfield
.reg64
)
4811 && i
.op
[op
].regs
->reg_num
< 4
4812 /* Prohibit these changes in 64bit mode, since the lowering
4813 would be more complicated. */
4814 && flag_code
!= CODE_64BIT
)
4816 #if REGISTER_WARNINGS
4817 if (!quiet_warnings
)
4818 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4820 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4821 ? REGNAM_AL
- REGNAM_AX
4822 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4824 i
.op
[op
].regs
->reg_name
,
4829 /* Any other register is bad. */
4830 if (i
.types
[op
].bitfield
.reg16
4831 || i
.types
[op
].bitfield
.reg32
4832 || i
.types
[op
].bitfield
.reg64
4833 || i
.types
[op
].bitfield
.regmmx
4834 || i
.types
[op
].bitfield
.regxmm
4835 || i
.types
[op
].bitfield
.regymm
4836 || i
.types
[op
].bitfield
.sreg2
4837 || i
.types
[op
].bitfield
.sreg3
4838 || i
.types
[op
].bitfield
.control
4839 || i
.types
[op
].bitfield
.debug
4840 || i
.types
[op
].bitfield
.test
4841 || i
.types
[op
].bitfield
.floatreg
4842 || i
.types
[op
].bitfield
.floatacc
)
4844 as_bad (_("`%s%s' not allowed with `%s%c'"),
4846 i
.op
[op
].regs
->reg_name
,
4856 check_long_reg (void)
4860 for (op
= i
.operands
; --op
>= 0;)
4861 /* Reject eight bit registers, except where the template requires
4862 them. (eg. movzb) */
4863 if (i
.types
[op
].bitfield
.reg8
4864 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4865 || i
.tm
.operand_types
[op
].bitfield
.reg32
4866 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4868 as_bad (_("`%s%s' not allowed with `%s%c'"),
4870 i
.op
[op
].regs
->reg_name
,
4875 /* Warn if the e prefix on a general reg is missing. */
4876 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4877 && i
.types
[op
].bitfield
.reg16
4878 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4879 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4881 /* Prohibit these changes in the 64bit mode, since the
4882 lowering is more complicated. */
4883 if (flag_code
== CODE_64BIT
)
4885 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4886 register_prefix
, i
.op
[op
].regs
->reg_name
,
4890 #if REGISTER_WARNINGS
4892 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4894 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4896 i
.op
[op
].regs
->reg_name
,
4900 /* Warn if the r prefix on a general reg is missing. */
4901 else if (i
.types
[op
].bitfield
.reg64
4902 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4903 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4906 && i
.tm
.opcode_modifier
.toqword
4907 && !i
.types
[0].bitfield
.regxmm
)
4909 /* Convert to QWORD. We want REX byte. */
4910 i
.suffix
= QWORD_MNEM_SUFFIX
;
4914 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4915 register_prefix
, i
.op
[op
].regs
->reg_name
,
4924 check_qword_reg (void)
4928 for (op
= i
.operands
; --op
>= 0; )
4929 /* Reject eight bit registers, except where the template requires
4930 them. (eg. movzb) */
4931 if (i
.types
[op
].bitfield
.reg8
4932 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4933 || i
.tm
.operand_types
[op
].bitfield
.reg32
4934 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4936 as_bad (_("`%s%s' not allowed with `%s%c'"),
4938 i
.op
[op
].regs
->reg_name
,
4943 /* Warn if the e prefix on a general reg is missing. */
4944 else if ((i
.types
[op
].bitfield
.reg16
4945 || i
.types
[op
].bitfield
.reg32
)
4946 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4947 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4949 /* Prohibit these changes in the 64bit mode, since the
4950 lowering is more complicated. */
4952 && i
.tm
.opcode_modifier
.todword
4953 && !i
.types
[0].bitfield
.regxmm
)
4955 /* Convert to DWORD. We don't want REX byte. */
4956 i
.suffix
= LONG_MNEM_SUFFIX
;
4960 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4961 register_prefix
, i
.op
[op
].regs
->reg_name
,
4970 check_word_reg (void)
4973 for (op
= i
.operands
; --op
>= 0;)
4974 /* Reject eight bit registers, except where the template requires
4975 them. (eg. movzb) */
4976 if (i
.types
[op
].bitfield
.reg8
4977 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4978 || i
.tm
.operand_types
[op
].bitfield
.reg32
4979 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4981 as_bad (_("`%s%s' not allowed with `%s%c'"),
4983 i
.op
[op
].regs
->reg_name
,
4988 /* Warn if the e prefix on a general reg is present. */
4989 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4990 && i
.types
[op
].bitfield
.reg32
4991 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4992 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4994 /* Prohibit these changes in the 64bit mode, since the
4995 lowering is more complicated. */
4996 if (flag_code
== CODE_64BIT
)
4998 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4999 register_prefix
, i
.op
[op
].regs
->reg_name
,
5004 #if REGISTER_WARNINGS
5005 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5007 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5009 i
.op
[op
].regs
->reg_name
,
5017 update_imm (unsigned int j
)
5019 i386_operand_type overlap
= i
.types
[j
];
5020 if ((overlap
.bitfield
.imm8
5021 || overlap
.bitfield
.imm8s
5022 || overlap
.bitfield
.imm16
5023 || overlap
.bitfield
.imm32
5024 || overlap
.bitfield
.imm32s
5025 || overlap
.bitfield
.imm64
)
5026 && !operand_type_equal (&overlap
, &imm8
)
5027 && !operand_type_equal (&overlap
, &imm8s
)
5028 && !operand_type_equal (&overlap
, &imm16
)
5029 && !operand_type_equal (&overlap
, &imm32
)
5030 && !operand_type_equal (&overlap
, &imm32s
)
5031 && !operand_type_equal (&overlap
, &imm64
))
5035 i386_operand_type temp
;
5037 operand_type_set (&temp
, 0);
5038 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5040 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5041 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5043 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5044 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5045 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5047 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5048 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5051 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5054 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5055 || operand_type_equal (&overlap
, &imm16_32
)
5056 || operand_type_equal (&overlap
, &imm16_32s
))
5058 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5063 if (!operand_type_equal (&overlap
, &imm8
)
5064 && !operand_type_equal (&overlap
, &imm8s
)
5065 && !operand_type_equal (&overlap
, &imm16
)
5066 && !operand_type_equal (&overlap
, &imm32
)
5067 && !operand_type_equal (&overlap
, &imm32s
)
5068 && !operand_type_equal (&overlap
, &imm64
))
5070 as_bad (_("no instruction mnemonic suffix given; "
5071 "can't determine immediate size"));
5075 i
.types
[j
] = overlap
;
5085 /* Update the first 2 immediate operands. */
5086 n
= i
.operands
> 2 ? 2 : i
.operands
;
5089 for (j
= 0; j
< n
; j
++)
5090 if (update_imm (j
) == 0)
5093 /* The 3rd operand can't be immediate operand. */
5094 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5101 bad_implicit_operand (int xmm
)
5103 const char *ireg
= xmm
? "xmm0" : "ymm0";
5106 as_bad (_("the last operand of `%s' must be `%s%s'"),
5107 i
.tm
.name
, register_prefix
, ireg
);
5109 as_bad (_("the first operand of `%s' must be `%s%s'"),
5110 i
.tm
.name
, register_prefix
, ireg
);
5115 process_operands (void)
5117 /* Default segment register this instruction will use for memory
5118 accesses. 0 means unknown. This is only for optimizing out
5119 unnecessary segment overrides. */
5120 const seg_entry
*default_seg
= 0;
5122 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5124 unsigned int dupl
= i
.operands
;
5125 unsigned int dest
= dupl
- 1;
5128 /* The destination must be an xmm register. */
5129 gas_assert (i
.reg_operands
5130 && MAX_OPERANDS
> dupl
5131 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5133 if (i
.tm
.opcode_modifier
.firstxmm0
)
5135 /* The first operand is implicit and must be xmm0. */
5136 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5137 if (register_number (i
.op
[0].regs
) != 0)
5138 return bad_implicit_operand (1);
5140 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5142 /* Keep xmm0 for instructions with VEX prefix and 3
5148 /* We remove the first xmm0 and keep the number of
5149 operands unchanged, which in fact duplicates the
5151 for (j
= 1; j
< i
.operands
; j
++)
5153 i
.op
[j
- 1] = i
.op
[j
];
5154 i
.types
[j
- 1] = i
.types
[j
];
5155 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5159 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5161 gas_assert ((MAX_OPERANDS
- 1) > dupl
5162 && (i
.tm
.opcode_modifier
.vexsources
5165 /* Add the implicit xmm0 for instructions with VEX prefix
5167 for (j
= i
.operands
; j
> 0; j
--)
5169 i
.op
[j
] = i
.op
[j
- 1];
5170 i
.types
[j
] = i
.types
[j
- 1];
5171 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5174 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5175 i
.types
[0] = regxmm
;
5176 i
.tm
.operand_types
[0] = regxmm
;
5179 i
.reg_operands
+= 2;
5184 i
.op
[dupl
] = i
.op
[dest
];
5185 i
.types
[dupl
] = i
.types
[dest
];
5186 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5195 i
.op
[dupl
] = i
.op
[dest
];
5196 i
.types
[dupl
] = i
.types
[dest
];
5197 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5200 if (i
.tm
.opcode_modifier
.immext
)
5203 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5207 /* The first operand is implicit and must be xmm0/ymm0. */
5208 gas_assert (i
.reg_operands
5209 && (operand_type_equal (&i
.types
[0], ®xmm
)
5210 || operand_type_equal (&i
.types
[0], ®ymm
)));
5211 if (register_number (i
.op
[0].regs
) != 0)
5212 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5214 for (j
= 1; j
< i
.operands
; j
++)
5216 i
.op
[j
- 1] = i
.op
[j
];
5217 i
.types
[j
- 1] = i
.types
[j
];
5219 /* We need to adjust fields in i.tm since they are used by
5220 build_modrm_byte. */
5221 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5228 else if (i
.tm
.opcode_modifier
.regkludge
)
5230 /* The imul $imm, %reg instruction is converted into
5231 imul $imm, %reg, %reg, and the clr %reg instruction
5232 is converted into xor %reg, %reg. */
5234 unsigned int first_reg_op
;
5236 if (operand_type_check (i
.types
[0], reg
))
5240 /* Pretend we saw the extra register operand. */
5241 gas_assert (i
.reg_operands
== 1
5242 && i
.op
[first_reg_op
+ 1].regs
== 0);
5243 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5244 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5249 if (i
.tm
.opcode_modifier
.shortform
)
5251 if (i
.types
[0].bitfield
.sreg2
5252 || i
.types
[0].bitfield
.sreg3
)
5254 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5255 && i
.op
[0].regs
->reg_num
== 1)
5257 as_bad (_("you can't `pop %scs'"), register_prefix
);
5260 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5261 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5266 /* The register or float register operand is in operand
5270 if (i
.types
[0].bitfield
.floatreg
5271 || operand_type_check (i
.types
[0], reg
))
5275 /* Register goes in low 3 bits of opcode. */
5276 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5277 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5279 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5281 /* Warn about some common errors, but press on regardless.
5282 The first case can be generated by gcc (<= 2.8.1). */
5283 if (i
.operands
== 2)
5285 /* Reversed arguments on faddp, fsubp, etc. */
5286 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5287 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5288 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5292 /* Extraneous `l' suffix on fp insn. */
5293 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5294 register_prefix
, i
.op
[0].regs
->reg_name
);
5299 else if (i
.tm
.opcode_modifier
.modrm
)
5301 /* The opcode is completed (modulo i.tm.extension_opcode which
5302 must be put into the modrm byte). Now, we make the modrm and
5303 index base bytes based on all the info we've collected. */
5305 default_seg
= build_modrm_byte ();
5307 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5311 else if (i
.tm
.opcode_modifier
.isstring
)
5313 /* For the string instructions that allow a segment override
5314 on one of their operands, the default segment is ds. */
5318 if (i
.tm
.base_opcode
== 0x8d /* lea */
5321 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5323 /* If a segment was explicitly specified, and the specified segment
5324 is not the default, use an opcode prefix to select it. If we
5325 never figured out what the default segment is, then default_seg
5326 will be zero at this point, and the specified segment prefix will
5328 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5330 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5336 static const seg_entry
*
5337 build_modrm_byte (void)
5339 const seg_entry
*default_seg
= 0;
5340 unsigned int source
, dest
;
5343 /* The first operand of instructions with VEX prefix and 3 sources
5344 must be VEX_Imm4. */
5345 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5348 unsigned int nds
, reg_slot
;
5351 if (i
.tm
.opcode_modifier
.veximmext
5352 && i
.tm
.opcode_modifier
.immext
)
5354 dest
= i
.operands
- 2;
5355 gas_assert (dest
== 3);
5358 dest
= i
.operands
- 1;
5361 /* There are 2 kinds of instructions:
5362 1. 5 operands: 4 register operands or 3 register operands
5363 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5364 VexW0 or VexW1. The destination must be either XMM or YMM
5366 2. 4 operands: 4 register operands or 3 register operands
5367 plus 1 memory operand, VexXDS, and VexImmExt */
5368 gas_assert ((i
.reg_operands
== 4
5369 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5370 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5371 && (i
.tm
.opcode_modifier
.veximmext
5372 || (i
.imm_operands
== 1
5373 && i
.types
[0].bitfield
.vec_imm4
5374 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5375 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5376 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5377 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5379 if (i
.imm_operands
== 0)
5381 /* When there is no immediate operand, generate an 8bit
5382 immediate operand to encode the first operand. */
5383 exp
= &im_expressions
[i
.imm_operands
++];
5384 i
.op
[i
.operands
].imms
= exp
;
5385 i
.types
[i
.operands
] = imm8
;
5387 /* If VexW1 is set, the first operand is the source and
5388 the second operand is encoded in the immediate operand. */
5389 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5400 /* FMA swaps REG and NDS. */
5401 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5409 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5411 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5413 exp
->X_op
= O_constant
;
5414 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5418 unsigned int imm_slot
;
5420 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5422 /* If VexW0 is set, the third operand is the source and
5423 the second operand is encoded in the immediate
5430 /* VexW1 is set, the second operand is the source and
5431 the third operand is encoded in the immediate
5437 if (i
.tm
.opcode_modifier
.immext
)
5439 /* When ImmExt is set, the immdiate byte is the last
5441 imm_slot
= i
.operands
- 1;
5449 /* Turn on Imm8 so that output_imm will generate it. */
5450 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5453 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5455 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5457 i
.op
[imm_slot
].imms
->X_add_number
5458 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5461 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5462 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5464 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5469 /* i.reg_operands MUST be the number of real register operands;
5470 implicit registers do not count. If there are 3 register
5471 operands, it must be a instruction with VexNDS. For a
5472 instruction with VexNDD, the destination register is encoded
5473 in VEX prefix. If there are 4 register operands, it must be
5474 a instruction with VEX prefix and 3 sources. */
5475 if (i
.mem_operands
== 0
5476 && ((i
.reg_operands
== 2
5477 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5478 || (i
.reg_operands
== 3
5479 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5480 || (i
.reg_operands
== 4 && vex_3_sources
)))
5488 /* When there are 3 operands, one of them may be immediate,
5489 which may be the first or the last operand. Otherwise,
5490 the first operand must be shift count register (cl) or it
5491 is an instruction with VexNDS. */
5492 gas_assert (i
.imm_operands
== 1
5493 || (i
.imm_operands
== 0
5494 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5495 || i
.types
[0].bitfield
.shiftcount
)));
5496 if (operand_type_check (i
.types
[0], imm
)
5497 || i
.types
[0].bitfield
.shiftcount
)
5503 /* When there are 4 operands, the first two must be 8bit
5504 immediate operands. The source operand will be the 3rd
5507 For instructions with VexNDS, if the first operand
5508 an imm8, the source operand is the 2nd one. If the last
5509 operand is imm8, the source operand is the first one. */
5510 gas_assert ((i
.imm_operands
== 2
5511 && i
.types
[0].bitfield
.imm8
5512 && i
.types
[1].bitfield
.imm8
)
5513 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5514 && i
.imm_operands
== 1
5515 && (i
.types
[0].bitfield
.imm8
5516 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5517 if (i
.imm_operands
== 2)
5521 if (i
.types
[0].bitfield
.imm8
)
5537 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5539 /* For instructions with VexNDS, the register-only
5540 source operand must be 32/64bit integer, XMM or
5541 YMM register. It is encoded in VEX prefix. We
5542 need to clear RegMem bit before calling
5543 operand_type_equal. */
5545 i386_operand_type op
;
5548 /* Check register-only source operand when two source
5549 operands are swapped. */
5550 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5551 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5559 op
= i
.tm
.operand_types
[vvvv
];
5560 op
.bitfield
.regmem
= 0;
5561 if ((dest
+ 1) >= i
.operands
5562 || (op
.bitfield
.reg32
!= 1
5563 && !op
.bitfield
.reg64
!= 1
5564 && !operand_type_equal (&op
, ®xmm
)
5565 && !operand_type_equal (&op
, ®ymm
)))
5567 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5573 /* One of the register operands will be encoded in the i.tm.reg
5574 field, the other in the combined i.tm.mode and i.tm.regmem
5575 fields. If no form of this instruction supports a memory
5576 destination operand, then we assume the source operand may
5577 sometimes be a memory operand and so we need to store the
5578 destination in the i.rm.reg field. */
5579 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5580 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5582 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5583 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5584 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5586 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5591 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5592 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5593 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5595 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5598 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5600 if (!i
.types
[0].bitfield
.control
5601 && !i
.types
[1].bitfield
.control
)
5603 i
.rex
&= ~(REX_R
| REX_B
);
5604 add_prefix (LOCK_PREFIX_OPCODE
);
5608 { /* If it's not 2 reg operands... */
5613 unsigned int fake_zero_displacement
= 0;
5616 for (op
= 0; op
< i
.operands
; op
++)
5617 if (operand_type_check (i
.types
[op
], anymem
))
5619 gas_assert (op
< i
.operands
);
5621 if (i
.tm
.opcode_modifier
.vecsib
)
5623 if (i
.index_reg
->reg_num
== RegEiz
5624 || i
.index_reg
->reg_num
== RegRiz
)
5627 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5630 i
.sib
.base
= NO_BASE_REGISTER
;
5631 i
.sib
.scale
= i
.log2_scale_factor
;
5632 i
.types
[op
].bitfield
.disp8
= 0;
5633 i
.types
[op
].bitfield
.disp16
= 0;
5634 i
.types
[op
].bitfield
.disp64
= 0;
5635 if (flag_code
!= CODE_64BIT
)
5637 /* Must be 32 bit */
5638 i
.types
[op
].bitfield
.disp32
= 1;
5639 i
.types
[op
].bitfield
.disp32s
= 0;
5643 i
.types
[op
].bitfield
.disp32
= 0;
5644 i
.types
[op
].bitfield
.disp32s
= 1;
5647 i
.sib
.index
= i
.index_reg
->reg_num
;
5648 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5654 if (i
.base_reg
== 0)
5657 if (!i
.disp_operands
)
5659 fake_zero_displacement
= 1;
5660 /* Instructions with VSIB byte need 32bit displacement
5661 if there is no base register. */
5662 if (i
.tm
.opcode_modifier
.vecsib
)
5663 i
.types
[op
].bitfield
.disp32
= 1;
5665 if (i
.index_reg
== 0)
5667 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5668 /* Operand is just <disp> */
5669 if (flag_code
== CODE_64BIT
)
5671 /* 64bit mode overwrites the 32bit absolute
5672 addressing by RIP relative addressing and
5673 absolute addressing is encoded by one of the
5674 redundant SIB forms. */
5675 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5676 i
.sib
.base
= NO_BASE_REGISTER
;
5677 i
.sib
.index
= NO_INDEX_REGISTER
;
5678 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5679 ? disp32s
: disp32
);
5681 else if ((flag_code
== CODE_16BIT
)
5682 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5684 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5685 i
.types
[op
] = disp16
;
5689 i
.rm
.regmem
= NO_BASE_REGISTER
;
5690 i
.types
[op
] = disp32
;
5693 else if (!i
.tm
.opcode_modifier
.vecsib
)
5695 /* !i.base_reg && i.index_reg */
5696 if (i
.index_reg
->reg_num
== RegEiz
5697 || i
.index_reg
->reg_num
== RegRiz
)
5698 i
.sib
.index
= NO_INDEX_REGISTER
;
5700 i
.sib
.index
= i
.index_reg
->reg_num
;
5701 i
.sib
.base
= NO_BASE_REGISTER
;
5702 i
.sib
.scale
= i
.log2_scale_factor
;
5703 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5704 i
.types
[op
].bitfield
.disp8
= 0;
5705 i
.types
[op
].bitfield
.disp16
= 0;
5706 i
.types
[op
].bitfield
.disp64
= 0;
5707 if (flag_code
!= CODE_64BIT
)
5709 /* Must be 32 bit */
5710 i
.types
[op
].bitfield
.disp32
= 1;
5711 i
.types
[op
].bitfield
.disp32s
= 0;
5715 i
.types
[op
].bitfield
.disp32
= 0;
5716 i
.types
[op
].bitfield
.disp32s
= 1;
5718 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5722 /* RIP addressing for 64bit mode. */
5723 else if (i
.base_reg
->reg_num
== RegRip
||
5724 i
.base_reg
->reg_num
== RegEip
)
5726 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5727 i
.rm
.regmem
= NO_BASE_REGISTER
;
5728 i
.types
[op
].bitfield
.disp8
= 0;
5729 i
.types
[op
].bitfield
.disp16
= 0;
5730 i
.types
[op
].bitfield
.disp32
= 0;
5731 i
.types
[op
].bitfield
.disp32s
= 1;
5732 i
.types
[op
].bitfield
.disp64
= 0;
5733 i
.flags
[op
] |= Operand_PCrel
;
5734 if (! i
.disp_operands
)
5735 fake_zero_displacement
= 1;
5737 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5739 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5740 switch (i
.base_reg
->reg_num
)
5743 if (i
.index_reg
== 0)
5745 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5746 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5750 if (i
.index_reg
== 0)
5753 if (operand_type_check (i
.types
[op
], disp
) == 0)
5755 /* fake (%bp) into 0(%bp) */
5756 i
.types
[op
].bitfield
.disp8
= 1;
5757 fake_zero_displacement
= 1;
5760 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5761 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5763 default: /* (%si) -> 4 or (%di) -> 5 */
5764 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5766 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5768 else /* i.base_reg and 32/64 bit mode */
5770 if (flag_code
== CODE_64BIT
5771 && operand_type_check (i
.types
[op
], disp
))
5773 i386_operand_type temp
;
5774 operand_type_set (&temp
, 0);
5775 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5777 if (i
.prefix
[ADDR_PREFIX
] == 0)
5778 i
.types
[op
].bitfield
.disp32s
= 1;
5780 i
.types
[op
].bitfield
.disp32
= 1;
5783 if (!i
.tm
.opcode_modifier
.vecsib
)
5784 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5785 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5787 i
.sib
.base
= i
.base_reg
->reg_num
;
5788 /* x86-64 ignores REX prefix bit here to avoid decoder
5790 if (!(i
.base_reg
->reg_flags
& RegRex
)
5791 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5792 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5794 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5796 fake_zero_displacement
= 1;
5797 i
.types
[op
].bitfield
.disp8
= 1;
5799 i
.sib
.scale
= i
.log2_scale_factor
;
5800 if (i
.index_reg
== 0)
5802 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5803 /* <disp>(%esp) becomes two byte modrm with no index
5804 register. We've already stored the code for esp
5805 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5806 Any base register besides %esp will not use the
5807 extra modrm byte. */
5808 i
.sib
.index
= NO_INDEX_REGISTER
;
5810 else if (!i
.tm
.opcode_modifier
.vecsib
)
5812 if (i
.index_reg
->reg_num
== RegEiz
5813 || i
.index_reg
->reg_num
== RegRiz
)
5814 i
.sib
.index
= NO_INDEX_REGISTER
;
5816 i
.sib
.index
= i
.index_reg
->reg_num
;
5817 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5818 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5823 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5824 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5828 if (!fake_zero_displacement
5832 fake_zero_displacement
= 1;
5833 if (i
.disp_encoding
== disp_encoding_8bit
)
5834 i
.types
[op
].bitfield
.disp8
= 1;
5836 i
.types
[op
].bitfield
.disp32
= 1;
5838 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5842 if (fake_zero_displacement
)
5844 /* Fakes a zero displacement assuming that i.types[op]
5845 holds the correct displacement size. */
5848 gas_assert (i
.op
[op
].disps
== 0);
5849 exp
= &disp_expressions
[i
.disp_operands
++];
5850 i
.op
[op
].disps
= exp
;
5851 exp
->X_op
= O_constant
;
5852 exp
->X_add_number
= 0;
5853 exp
->X_add_symbol
= (symbolS
*) 0;
5854 exp
->X_op_symbol
= (symbolS
*) 0;
5862 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5864 if (operand_type_check (i
.types
[0], imm
))
5865 i
.vex
.register_specifier
= NULL
;
5868 /* VEX.vvvv encodes one of the sources when the first
5869 operand is not an immediate. */
5870 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5871 i
.vex
.register_specifier
= i
.op
[0].regs
;
5873 i
.vex
.register_specifier
= i
.op
[1].regs
;
5876 /* Destination is a XMM register encoded in the ModRM.reg
5878 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5879 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5882 /* ModRM.rm and VEX.B encodes the other source. */
5883 if (!i
.mem_operands
)
5887 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5888 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5890 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5892 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5896 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5898 i
.vex
.register_specifier
= i
.op
[2].regs
;
5899 if (!i
.mem_operands
)
5902 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5903 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5907 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5908 (if any) based on i.tm.extension_opcode. Again, we must be
5909 careful to make sure that segment/control/debug/test/MMX
5910 registers are coded into the i.rm.reg field. */
5911 else if (i
.reg_operands
)
5914 unsigned int vex_reg
= ~0;
5916 for (op
= 0; op
< i
.operands
; op
++)
5917 if (i
.types
[op
].bitfield
.reg8
5918 || i
.types
[op
].bitfield
.reg16
5919 || i
.types
[op
].bitfield
.reg32
5920 || i
.types
[op
].bitfield
.reg64
5921 || i
.types
[op
].bitfield
.regmmx
5922 || i
.types
[op
].bitfield
.regxmm
5923 || i
.types
[op
].bitfield
.regymm
5924 || i
.types
[op
].bitfield
.regbnd
5925 || i
.types
[op
].bitfield
.sreg2
5926 || i
.types
[op
].bitfield
.sreg3
5927 || i
.types
[op
].bitfield
.control
5928 || i
.types
[op
].bitfield
.debug
5929 || i
.types
[op
].bitfield
.test
)
5934 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5936 /* For instructions with VexNDS, the register-only
5937 source operand is encoded in VEX prefix. */
5938 gas_assert (mem
!= (unsigned int) ~0);
5943 gas_assert (op
< i
.operands
);
5947 /* Check register-only source operand when two source
5948 operands are swapped. */
5949 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5950 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5954 gas_assert (mem
== (vex_reg
+ 1)
5955 && op
< i
.operands
);
5960 gas_assert (vex_reg
< i
.operands
);
5964 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5966 /* For instructions with VexNDD, the register destination
5967 is encoded in VEX prefix. */
5968 if (i
.mem_operands
== 0)
5970 /* There is no memory operand. */
5971 gas_assert ((op
+ 2) == i
.operands
);
5976 /* There are only 2 operands. */
5977 gas_assert (op
< 2 && i
.operands
== 2);
5982 gas_assert (op
< i
.operands
);
5984 if (vex_reg
!= (unsigned int) ~0)
5986 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5988 if (type
->bitfield
.reg32
!= 1
5989 && type
->bitfield
.reg64
!= 1
5990 && !operand_type_equal (type
, ®xmm
)
5991 && !operand_type_equal (type
, ®ymm
))
5994 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5997 /* Don't set OP operand twice. */
6000 /* If there is an extension opcode to put here, the
6001 register number must be put into the regmem field. */
6002 if (i
.tm
.extension_opcode
!= None
)
6004 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6005 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6010 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6011 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6016 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6017 must set it to 3 to indicate this is a register operand
6018 in the regmem field. */
6019 if (!i
.mem_operands
)
6023 /* Fill in i.rm.reg field with extension opcode (if any). */
6024 if (i
.tm
.extension_opcode
!= None
)
6025 i
.rm
.reg
= i
.tm
.extension_opcode
;
6031 output_branch (void)
6037 relax_substateT subtype
;
6041 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6042 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6045 if (i
.prefix
[DATA_PREFIX
] != 0)
6051 /* Pentium4 branch hints. */
6052 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6053 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6058 if (i
.prefix
[REX_PREFIX
] != 0)
6064 /* BND prefixed jump. */
6065 if (i
.prefix
[BND_PREFIX
] != 0)
6067 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6071 if (i
.prefixes
!= 0 && !intel_syntax
)
6072 as_warn (_("skipping prefixes on this instruction"));
6074 /* It's always a symbol; End frag & setup for relax.
6075 Make sure there is enough room in this frag for the largest
6076 instruction we may generate in md_convert_frag. This is 2
6077 bytes for the opcode and room for the prefix and largest
6079 frag_grow (prefix
+ 2 + 4);
6080 /* Prefix and 1 opcode byte go in fr_fix. */
6081 p
= frag_more (prefix
+ 1);
6082 if (i
.prefix
[DATA_PREFIX
] != 0)
6083 *p
++ = DATA_PREFIX_OPCODE
;
6084 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6085 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6086 *p
++ = i
.prefix
[SEG_PREFIX
];
6087 if (i
.prefix
[REX_PREFIX
] != 0)
6088 *p
++ = i
.prefix
[REX_PREFIX
];
6089 *p
= i
.tm
.base_opcode
;
6091 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6092 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6093 else if (cpu_arch_flags
.bitfield
.cpui386
)
6094 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6096 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6099 sym
= i
.op
[0].disps
->X_add_symbol
;
6100 off
= i
.op
[0].disps
->X_add_number
;
6102 if (i
.op
[0].disps
->X_op
!= O_constant
6103 && i
.op
[0].disps
->X_op
!= O_symbol
)
6105 /* Handle complex expressions. */
6106 sym
= make_expr_symbol (i
.op
[0].disps
);
6110 /* 1 possible extra opcode + 4 byte displacement go in var part.
6111 Pass reloc in fr_var. */
6112 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6122 if (i
.tm
.opcode_modifier
.jumpbyte
)
6124 /* This is a loop or jecxz type instruction. */
6126 if (i
.prefix
[ADDR_PREFIX
] != 0)
6128 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6131 /* Pentium4 branch hints. */
6132 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6133 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6135 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6144 if (flag_code
== CODE_16BIT
)
6147 if (i
.prefix
[DATA_PREFIX
] != 0)
6149 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6159 if (i
.prefix
[REX_PREFIX
] != 0)
6161 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6165 /* BND prefixed jump. */
6166 if (i
.prefix
[BND_PREFIX
] != 0)
6168 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6172 if (i
.prefixes
!= 0 && !intel_syntax
)
6173 as_warn (_("skipping prefixes on this instruction"));
6175 p
= frag_more (i
.tm
.opcode_length
+ size
);
6176 switch (i
.tm
.opcode_length
)
6179 *p
++ = i
.tm
.base_opcode
>> 8;
6181 *p
++ = i
.tm
.base_opcode
;
6187 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6188 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6190 /* All jumps handled here are signed, but don't use a signed limit
6191 check for 32 and 16 bit jumps as we want to allow wrap around at
6192 4G and 64k respectively. */
6194 fixP
->fx_signed
= 1;
6198 output_interseg_jump (void)
6206 if (flag_code
== CODE_16BIT
)
6210 if (i
.prefix
[DATA_PREFIX
] != 0)
6216 if (i
.prefix
[REX_PREFIX
] != 0)
6226 if (i
.prefixes
!= 0 && !intel_syntax
)
6227 as_warn (_("skipping prefixes on this instruction"));
6229 /* 1 opcode; 2 segment; offset */
6230 p
= frag_more (prefix
+ 1 + 2 + size
);
6232 if (i
.prefix
[DATA_PREFIX
] != 0)
6233 *p
++ = DATA_PREFIX_OPCODE
;
6235 if (i
.prefix
[REX_PREFIX
] != 0)
6236 *p
++ = i
.prefix
[REX_PREFIX
];
6238 *p
++ = i
.tm
.base_opcode
;
6239 if (i
.op
[1].imms
->X_op
== O_constant
)
6241 offsetT n
= i
.op
[1].imms
->X_add_number
;
6244 && !fits_in_unsigned_word (n
)
6245 && !fits_in_signed_word (n
))
6247 as_bad (_("16-bit jump out of range"));
6250 md_number_to_chars (p
, n
, size
);
6253 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6254 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6255 if (i
.op
[0].imms
->X_op
!= O_constant
)
6256 as_bad (_("can't handle non absolute segment in `%s'"),
6258 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6264 fragS
*insn_start_frag
;
6265 offsetT insn_start_off
;
6267 /* Tie dwarf2 debug info to the address at the start of the insn.
6268 We can't do this after the insn has been output as the current
6269 frag may have been closed off. eg. by frag_var. */
6270 dwarf2_emit_insn (0);
6272 insn_start_frag
= frag_now
;
6273 insn_start_off
= frag_now_fix ();
6276 if (i
.tm
.opcode_modifier
.jump
)
6278 else if (i
.tm
.opcode_modifier
.jumpbyte
6279 || i
.tm
.opcode_modifier
.jumpdword
)
6281 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6282 output_interseg_jump ();
6285 /* Output normal instructions here. */
6289 unsigned int prefix
;
6291 /* Since the VEX prefix contains the implicit prefix, we don't
6292 need the explicit prefix. */
6293 if (!i
.tm
.opcode_modifier
.vex
)
6295 switch (i
.tm
.opcode_length
)
6298 if (i
.tm
.base_opcode
& 0xff000000)
6300 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6305 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6307 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6308 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6311 if (prefix
!= REPE_PREFIX_OPCODE
6312 || (i
.prefix
[REP_PREFIX
]
6313 != REPE_PREFIX_OPCODE
))
6314 add_prefix (prefix
);
6317 add_prefix (prefix
);
6326 /* The prefix bytes. */
6327 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6329 FRAG_APPEND_1_CHAR (*q
);
6333 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6338 /* REX byte is encoded in VEX prefix. */
6342 FRAG_APPEND_1_CHAR (*q
);
6345 /* There should be no other prefixes for instructions
6350 /* Now the VEX prefix. */
6351 p
= frag_more (i
.vex
.length
);
6352 for (j
= 0; j
< i
.vex
.length
; j
++)
6353 p
[j
] = i
.vex
.bytes
[j
];
6356 /* Now the opcode; be careful about word order here! */
6357 if (i
.tm
.opcode_length
== 1)
6359 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6363 switch (i
.tm
.opcode_length
)
6367 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6377 /* Put out high byte first: can't use md_number_to_chars! */
6378 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6379 *p
= i
.tm
.base_opcode
& 0xff;
6382 /* Now the modrm byte and sib byte (if present). */
6383 if (i
.tm
.opcode_modifier
.modrm
)
6385 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6388 /* If i.rm.regmem == ESP (4)
6389 && i.rm.mode != (Register mode)
6391 ==> need second modrm byte. */
6392 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6394 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6395 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6397 | i
.sib
.scale
<< 6));
6400 if (i
.disp_operands
)
6401 output_disp (insn_start_frag
, insn_start_off
);
6404 output_imm (insn_start_frag
, insn_start_off
);
6410 pi ("" /*line*/, &i
);
6412 #endif /* DEBUG386 */
6415 /* Return the size of the displacement operand N. */
6418 disp_size (unsigned int n
)
6421 if (i
.types
[n
].bitfield
.disp64
)
6423 else if (i
.types
[n
].bitfield
.disp8
)
6425 else if (i
.types
[n
].bitfield
.disp16
)
6430 /* Return the size of the immediate operand N. */
6433 imm_size (unsigned int n
)
6436 if (i
.types
[n
].bitfield
.imm64
)
6438 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6440 else if (i
.types
[n
].bitfield
.imm16
)
6446 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6451 for (n
= 0; n
< i
.operands
; n
++)
6453 if (operand_type_check (i
.types
[n
], disp
))
6455 if (i
.op
[n
].disps
->X_op
== O_constant
)
6457 int size
= disp_size (n
);
6460 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6462 p
= frag_more (size
);
6463 md_number_to_chars (p
, val
, size
);
6467 enum bfd_reloc_code_real reloc_type
;
6468 int size
= disp_size (n
);
6469 int sign
= i
.types
[n
].bitfield
.disp32s
;
6470 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6472 /* We can't have 8 bit displacement here. */
6473 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6475 /* The PC relative address is computed relative
6476 to the instruction boundary, so in case immediate
6477 fields follows, we need to adjust the value. */
6478 if (pcrel
&& i
.imm_operands
)
6483 for (n1
= 0; n1
< i
.operands
; n1
++)
6484 if (operand_type_check (i
.types
[n1
], imm
))
6486 /* Only one immediate is allowed for PC
6487 relative address. */
6488 gas_assert (sz
== 0);
6490 i
.op
[n
].disps
->X_add_number
-= sz
;
6492 /* We should find the immediate. */
6493 gas_assert (sz
!= 0);
6496 p
= frag_more (size
);
6497 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6499 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6500 && (((reloc_type
== BFD_RELOC_32
6501 || reloc_type
== BFD_RELOC_X86_64_32S
6502 || (reloc_type
== BFD_RELOC_64
6504 && (i
.op
[n
].disps
->X_op
== O_symbol
6505 || (i
.op
[n
].disps
->X_op
== O_add
6506 && ((symbol_get_value_expression
6507 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6509 || reloc_type
== BFD_RELOC_32_PCREL
))
6513 if (insn_start_frag
== frag_now
)
6514 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6519 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6520 for (fr
= insn_start_frag
->fr_next
;
6521 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6523 add
+= p
- frag_now
->fr_literal
;
6528 reloc_type
= BFD_RELOC_386_GOTPC
;
6529 i
.op
[n
].imms
->X_add_number
+= add
;
6531 else if (reloc_type
== BFD_RELOC_64
)
6532 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6534 /* Don't do the adjustment for x86-64, as there
6535 the pcrel addressing is relative to the _next_
6536 insn, and that is taken care of in other code. */
6537 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6539 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6540 i
.op
[n
].disps
, pcrel
, reloc_type
);
6547 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6552 for (n
= 0; n
< i
.operands
; n
++)
6554 if (operand_type_check (i
.types
[n
], imm
))
6556 if (i
.op
[n
].imms
->X_op
== O_constant
)
6558 int size
= imm_size (n
);
6561 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6563 p
= frag_more (size
);
6564 md_number_to_chars (p
, val
, size
);
6568 /* Not absolute_section.
6569 Need a 32-bit fixup (don't support 8bit
6570 non-absolute imms). Try to support other
6572 enum bfd_reloc_code_real reloc_type
;
6573 int size
= imm_size (n
);
6576 if (i
.types
[n
].bitfield
.imm32s
6577 && (i
.suffix
== QWORD_MNEM_SUFFIX
6578 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6583 p
= frag_more (size
);
6584 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6586 /* This is tough to explain. We end up with this one if we
6587 * have operands that look like
6588 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6589 * obtain the absolute address of the GOT, and it is strongly
6590 * preferable from a performance point of view to avoid using
6591 * a runtime relocation for this. The actual sequence of
6592 * instructions often look something like:
6597 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6599 * The call and pop essentially return the absolute address
6600 * of the label .L66 and store it in %ebx. The linker itself
6601 * will ultimately change the first operand of the addl so
6602 * that %ebx points to the GOT, but to keep things simple, the
6603 * .o file must have this operand set so that it generates not
6604 * the absolute address of .L66, but the absolute address of
6605 * itself. This allows the linker itself simply treat a GOTPC
6606 * relocation as asking for a pcrel offset to the GOT to be
6607 * added in, and the addend of the relocation is stored in the
6608 * operand field for the instruction itself.
6610 * Our job here is to fix the operand so that it would add
6611 * the correct offset so that %ebx would point to itself. The
6612 * thing that is tricky is that .-.L66 will point to the
6613 * beginning of the instruction, so we need to further modify
6614 * the operand so that it will point to itself. There are
6615 * other cases where you have something like:
6617 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6619 * and here no correction would be required. Internally in
6620 * the assembler we treat operands of this form as not being
6621 * pcrel since the '.' is explicitly mentioned, and I wonder
6622 * whether it would simplify matters to do it this way. Who
6623 * knows. In earlier versions of the PIC patches, the
6624 * pcrel_adjust field was used to store the correction, but
6625 * since the expression is not pcrel, I felt it would be
6626 * confusing to do it this way. */
6628 if ((reloc_type
== BFD_RELOC_32
6629 || reloc_type
== BFD_RELOC_X86_64_32S
6630 || reloc_type
== BFD_RELOC_64
)
6632 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6633 && (i
.op
[n
].imms
->X_op
== O_symbol
6634 || (i
.op
[n
].imms
->X_op
== O_add
6635 && ((symbol_get_value_expression
6636 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6641 if (insn_start_frag
== frag_now
)
6642 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6647 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6648 for (fr
= insn_start_frag
->fr_next
;
6649 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6651 add
+= p
- frag_now
->fr_literal
;
6655 reloc_type
= BFD_RELOC_386_GOTPC
;
6657 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6659 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6660 i
.op
[n
].imms
->X_add_number
+= add
;
6662 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6663 i
.op
[n
].imms
, 0, reloc_type
);
6669 /* x86_cons_fix_new is called via the expression parsing code when a
6670 reloc is needed. We use this hook to get the correct .got reloc. */
6671 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6672 static int cons_sign
= -1;
6675 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6678 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6680 got_reloc
= NO_RELOC
;
6683 if (exp
->X_op
== O_secrel
)
6685 exp
->X_op
= O_symbol
;
6686 r
= BFD_RELOC_32_SECREL
;
6690 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6693 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6694 purpose of the `.dc.a' internal pseudo-op. */
6697 x86_address_bytes (void)
6699 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6701 return stdoutput
->arch_info
->bits_per_address
/ 8;
6704 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6706 # define lex_got(reloc, adjust, types) NULL
6708 /* Parse operands of the form
6709 <symbol>@GOTOFF+<nnn>
6710 and similar .plt or .got references.
6712 If we find one, set up the correct relocation in RELOC and copy the
6713 input string, minus the `@GOTOFF' into a malloc'd buffer for
6714 parsing by the calling routine. Return this buffer, and if ADJUST
6715 is non-null set it to the length of the string we removed from the
6716 input line. Otherwise return NULL. */
6718 lex_got (enum bfd_reloc_code_real
*rel
,
6720 i386_operand_type
*types
)
6722 /* Some of the relocations depend on the size of what field is to
6723 be relocated. But in our callers i386_immediate and i386_displacement
6724 we don't yet know the operand size (this will be set by insn
6725 matching). Hence we record the word32 relocation here,
6726 and adjust the reloc according to the real size in reloc(). */
6727 static const struct {
6730 const enum bfd_reloc_code_real rel
[2];
6731 const i386_operand_type types64
;
6733 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6734 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6736 OPERAND_TYPE_IMM32_64
},
6738 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6739 BFD_RELOC_X86_64_PLTOFF64
},
6740 OPERAND_TYPE_IMM64
},
6741 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6742 BFD_RELOC_X86_64_PLT32
},
6743 OPERAND_TYPE_IMM32_32S_DISP32
},
6744 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6745 BFD_RELOC_X86_64_GOTPLT64
},
6746 OPERAND_TYPE_IMM64_DISP64
},
6747 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6748 BFD_RELOC_X86_64_GOTOFF64
},
6749 OPERAND_TYPE_IMM64_DISP64
},
6750 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6751 BFD_RELOC_X86_64_GOTPCREL
},
6752 OPERAND_TYPE_IMM32_32S_DISP32
},
6753 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6754 BFD_RELOC_X86_64_TLSGD
},
6755 OPERAND_TYPE_IMM32_32S_DISP32
},
6756 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6757 _dummy_first_bfd_reloc_code_real
},
6758 OPERAND_TYPE_NONE
},
6759 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6760 BFD_RELOC_X86_64_TLSLD
},
6761 OPERAND_TYPE_IMM32_32S_DISP32
},
6762 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6763 BFD_RELOC_X86_64_GOTTPOFF
},
6764 OPERAND_TYPE_IMM32_32S_DISP32
},
6765 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6766 BFD_RELOC_X86_64_TPOFF32
},
6767 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6768 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6769 _dummy_first_bfd_reloc_code_real
},
6770 OPERAND_TYPE_NONE
},
6771 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6772 BFD_RELOC_X86_64_DTPOFF32
},
6773 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6774 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6775 _dummy_first_bfd_reloc_code_real
},
6776 OPERAND_TYPE_NONE
},
6777 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6778 _dummy_first_bfd_reloc_code_real
},
6779 OPERAND_TYPE_NONE
},
6780 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6781 BFD_RELOC_X86_64_GOT32
},
6782 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6783 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6784 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6785 OPERAND_TYPE_IMM32_32S_DISP32
},
6786 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6787 BFD_RELOC_X86_64_TLSDESC_CALL
},
6788 OPERAND_TYPE_IMM32_32S_DISP32
},
6793 #if defined (OBJ_MAYBE_ELF)
6798 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6799 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6802 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6804 int len
= gotrel
[j
].len
;
6805 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6807 if (gotrel
[j
].rel
[object_64bit
] != 0)
6810 char *tmpbuf
, *past_reloc
;
6812 *rel
= gotrel
[j
].rel
[object_64bit
];
6816 if (flag_code
!= CODE_64BIT
)
6818 types
->bitfield
.imm32
= 1;
6819 types
->bitfield
.disp32
= 1;
6822 *types
= gotrel
[j
].types64
;
6825 if (j
!= 0 && GOT_symbol
== NULL
)
6826 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6828 /* The length of the first part of our input line. */
6829 first
= cp
- input_line_pointer
;
6831 /* The second part goes from after the reloc token until
6832 (and including) an end_of_line char or comma. */
6833 past_reloc
= cp
+ 1 + len
;
6835 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6837 second
= cp
+ 1 - past_reloc
;
6839 /* Allocate and copy string. The trailing NUL shouldn't
6840 be necessary, but be safe. */
6841 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6842 memcpy (tmpbuf
, input_line_pointer
, first
);
6843 if (second
!= 0 && *past_reloc
!= ' ')
6844 /* Replace the relocation token with ' ', so that
6845 errors like foo@GOTOFF1 will be detected. */
6846 tmpbuf
[first
++] = ' ';
6848 /* Increment length by 1 if the relocation token is
6853 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6854 tmpbuf
[first
+ second
] = '\0';
6858 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6859 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6864 /* Might be a symbol version string. Don't as_bad here. */
6873 /* Parse operands of the form
6874 <symbol>@SECREL32+<nnn>
6876 If we find one, set up the correct relocation in RELOC and copy the
6877 input string, minus the `@SECREL32' into a malloc'd buffer for
6878 parsing by the calling routine. Return this buffer, and if ADJUST
6879 is non-null set it to the length of the string we removed from the
6880 input line. Otherwise return NULL.
6882 This function is copied from the ELF version above adjusted for PE targets. */
6885 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6886 int *adjust ATTRIBUTE_UNUSED
,
6887 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6893 const enum bfd_reloc_code_real rel
[2];
6894 const i386_operand_type types64
;
6898 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6899 BFD_RELOC_32_SECREL
},
6900 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6906 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6907 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6910 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6912 int len
= gotrel
[j
].len
;
6914 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6916 if (gotrel
[j
].rel
[object_64bit
] != 0)
6919 char *tmpbuf
, *past_reloc
;
6921 *rel
= gotrel
[j
].rel
[object_64bit
];
6927 if (flag_code
!= CODE_64BIT
)
6929 types
->bitfield
.imm32
= 1;
6930 types
->bitfield
.disp32
= 1;
6933 *types
= gotrel
[j
].types64
;
6936 /* The length of the first part of our input line. */
6937 first
= cp
- input_line_pointer
;
6939 /* The second part goes from after the reloc token until
6940 (and including) an end_of_line char or comma. */
6941 past_reloc
= cp
+ 1 + len
;
6943 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6945 second
= cp
+ 1 - past_reloc
;
6947 /* Allocate and copy string. The trailing NUL shouldn't
6948 be necessary, but be safe. */
6949 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6950 memcpy (tmpbuf
, input_line_pointer
, first
);
6951 if (second
!= 0 && *past_reloc
!= ' ')
6952 /* Replace the relocation token with ' ', so that
6953 errors like foo@SECLREL321 will be detected. */
6954 tmpbuf
[first
++] = ' ';
6955 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6956 tmpbuf
[first
+ second
] = '\0';
6960 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6961 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6966 /* Might be a symbol version string. Don't as_bad here. */
6973 x86_cons (expressionS
*exp
, int size
)
6975 intel_syntax
= -intel_syntax
;
6978 if (size
== 4 || (object_64bit
&& size
== 8))
6980 /* Handle @GOTOFF and the like in an expression. */
6982 char *gotfree_input_line
;
6985 save
= input_line_pointer
;
6986 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6987 if (gotfree_input_line
)
6988 input_line_pointer
= gotfree_input_line
;
6992 if (gotfree_input_line
)
6994 /* expression () has merrily parsed up to the end of line,
6995 or a comma - in the wrong buffer. Transfer how far
6996 input_line_pointer has moved to the right buffer. */
6997 input_line_pointer
= (save
6998 + (input_line_pointer
- gotfree_input_line
)
7000 free (gotfree_input_line
);
7001 if (exp
->X_op
== O_constant
7002 || exp
->X_op
== O_absent
7003 || exp
->X_op
== O_illegal
7004 || exp
->X_op
== O_register
7005 || exp
->X_op
== O_big
)
7007 char c
= *input_line_pointer
;
7008 *input_line_pointer
= 0;
7009 as_bad (_("missing or invalid expression `%s'"), save
);
7010 *input_line_pointer
= c
;
7017 intel_syntax
= -intel_syntax
;
7020 i386_intel_simplify (exp
);
7024 signed_cons (int size
)
7026 if (flag_code
== CODE_64BIT
)
7034 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7041 if (exp
.X_op
== O_symbol
)
7042 exp
.X_op
= O_secrel
;
7044 emit_expr (&exp
, 4);
7046 while (*input_line_pointer
++ == ',');
7048 input_line_pointer
--;
7049 demand_empty_rest_of_line ();
7054 i386_immediate (char *imm_start
)
7056 char *save_input_line_pointer
;
7057 char *gotfree_input_line
;
7060 i386_operand_type types
;
7062 operand_type_set (&types
, ~0);
7064 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7066 as_bad (_("at most %d immediate operands are allowed"),
7067 MAX_IMMEDIATE_OPERANDS
);
7071 exp
= &im_expressions
[i
.imm_operands
++];
7072 i
.op
[this_operand
].imms
= exp
;
7074 if (is_space_char (*imm_start
))
7077 save_input_line_pointer
= input_line_pointer
;
7078 input_line_pointer
= imm_start
;
7080 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7081 if (gotfree_input_line
)
7082 input_line_pointer
= gotfree_input_line
;
7084 exp_seg
= expression (exp
);
7087 if (*input_line_pointer
)
7088 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7090 input_line_pointer
= save_input_line_pointer
;
7091 if (gotfree_input_line
)
7093 free (gotfree_input_line
);
7095 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7096 exp
->X_op
= O_illegal
;
7099 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7103 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7104 i386_operand_type types
, const char *imm_start
)
7106 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7109 as_bad (_("missing or invalid immediate expression `%s'"),
7113 else if (exp
->X_op
== O_constant
)
7115 /* Size it properly later. */
7116 i
.types
[this_operand
].bitfield
.imm64
= 1;
7117 /* If not 64bit, sign extend val. */
7118 if (flag_code
!= CODE_64BIT
7119 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7121 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7123 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7124 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7125 && exp_seg
!= absolute_section
7126 && exp_seg
!= text_section
7127 && exp_seg
!= data_section
7128 && exp_seg
!= bss_section
7129 && exp_seg
!= undefined_section
7130 && !bfd_is_com_section (exp_seg
))
7132 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7136 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7139 as_bad (_("illegal immediate register operand %s"), imm_start
);
7144 /* This is an address. The size of the address will be
7145 determined later, depending on destination register,
7146 suffix, or the default for the section. */
7147 i
.types
[this_operand
].bitfield
.imm8
= 1;
7148 i
.types
[this_operand
].bitfield
.imm16
= 1;
7149 i
.types
[this_operand
].bitfield
.imm32
= 1;
7150 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7151 i
.types
[this_operand
].bitfield
.imm64
= 1;
7152 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7160 i386_scale (char *scale
)
7163 char *save
= input_line_pointer
;
7165 input_line_pointer
= scale
;
7166 val
= get_absolute_expression ();
7171 i
.log2_scale_factor
= 0;
7174 i
.log2_scale_factor
= 1;
7177 i
.log2_scale_factor
= 2;
7180 i
.log2_scale_factor
= 3;
7184 char sep
= *input_line_pointer
;
7186 *input_line_pointer
= '\0';
7187 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7189 *input_line_pointer
= sep
;
7190 input_line_pointer
= save
;
7194 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7196 as_warn (_("scale factor of %d without an index register"),
7197 1 << i
.log2_scale_factor
);
7198 i
.log2_scale_factor
= 0;
7200 scale
= input_line_pointer
;
7201 input_line_pointer
= save
;
7206 i386_displacement (char *disp_start
, char *disp_end
)
7210 char *save_input_line_pointer
;
7211 char *gotfree_input_line
;
7213 i386_operand_type bigdisp
, types
= anydisp
;
7216 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7218 as_bad (_("at most %d displacement operands are allowed"),
7219 MAX_MEMORY_OPERANDS
);
7223 operand_type_set (&bigdisp
, 0);
7224 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7225 || (!current_templates
->start
->opcode_modifier
.jump
7226 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7228 bigdisp
.bitfield
.disp32
= 1;
7229 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7230 if (flag_code
== CODE_64BIT
)
7234 bigdisp
.bitfield
.disp32s
= 1;
7235 bigdisp
.bitfield
.disp64
= 1;
7238 else if ((flag_code
== CODE_16BIT
) ^ override
)
7240 bigdisp
.bitfield
.disp32
= 0;
7241 bigdisp
.bitfield
.disp16
= 1;
7246 /* For PC-relative branches, the width of the displacement
7247 is dependent upon data size, not address size. */
7248 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7249 if (flag_code
== CODE_64BIT
)
7251 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7252 bigdisp
.bitfield
.disp16
= 1;
7255 bigdisp
.bitfield
.disp32
= 1;
7256 bigdisp
.bitfield
.disp32s
= 1;
7262 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7264 : LONG_MNEM_SUFFIX
));
7265 bigdisp
.bitfield
.disp32
= 1;
7266 if ((flag_code
== CODE_16BIT
) ^ override
)
7268 bigdisp
.bitfield
.disp32
= 0;
7269 bigdisp
.bitfield
.disp16
= 1;
7273 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7276 exp
= &disp_expressions
[i
.disp_operands
];
7277 i
.op
[this_operand
].disps
= exp
;
7279 save_input_line_pointer
= input_line_pointer
;
7280 input_line_pointer
= disp_start
;
7281 END_STRING_AND_SAVE (disp_end
);
7283 #ifndef GCC_ASM_O_HACK
7284 #define GCC_ASM_O_HACK 0
7287 END_STRING_AND_SAVE (disp_end
+ 1);
7288 if (i
.types
[this_operand
].bitfield
.baseIndex
7289 && displacement_string_end
[-1] == '+')
7291 /* This hack is to avoid a warning when using the "o"
7292 constraint within gcc asm statements.
7295 #define _set_tssldt_desc(n,addr,limit,type) \
7296 __asm__ __volatile__ ( \
7298 "movw %w1,2+%0\n\t" \
7300 "movb %b1,4+%0\n\t" \
7301 "movb %4,5+%0\n\t" \
7302 "movb $0,6+%0\n\t" \
7303 "movb %h1,7+%0\n\t" \
7305 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7307 This works great except that the output assembler ends
7308 up looking a bit weird if it turns out that there is
7309 no offset. You end up producing code that looks like:
7322 So here we provide the missing zero. */
7324 *displacement_string_end
= '0';
7327 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7328 if (gotfree_input_line
)
7329 input_line_pointer
= gotfree_input_line
;
7331 exp_seg
= expression (exp
);
7334 if (*input_line_pointer
)
7335 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7337 RESTORE_END_STRING (disp_end
+ 1);
7339 input_line_pointer
= save_input_line_pointer
;
7340 if (gotfree_input_line
)
7342 free (gotfree_input_line
);
7344 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7345 exp
->X_op
= O_illegal
;
7348 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7350 RESTORE_END_STRING (disp_end
);
7356 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7357 i386_operand_type types
, const char *disp_start
)
7359 i386_operand_type bigdisp
;
7362 /* We do this to make sure that the section symbol is in
7363 the symbol table. We will ultimately change the relocation
7364 to be relative to the beginning of the section. */
7365 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7366 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7367 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7369 if (exp
->X_op
!= O_symbol
)
7372 if (S_IS_LOCAL (exp
->X_add_symbol
)
7373 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7374 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7375 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7376 exp
->X_op
= O_subtract
;
7377 exp
->X_op_symbol
= GOT_symbol
;
7378 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7379 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7380 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7381 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7383 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7386 else if (exp
->X_op
== O_absent
7387 || exp
->X_op
== O_illegal
7388 || exp
->X_op
== O_big
)
7391 as_bad (_("missing or invalid displacement expression `%s'"),
7396 else if (flag_code
== CODE_64BIT
7397 && !i
.prefix
[ADDR_PREFIX
]
7398 && exp
->X_op
== O_constant
)
7400 /* Since displacement is signed extended to 64bit, don't allow
7401 disp32 and turn off disp32s if they are out of range. */
7402 i
.types
[this_operand
].bitfield
.disp32
= 0;
7403 if (!fits_in_signed_long (exp
->X_add_number
))
7405 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7406 if (i
.types
[this_operand
].bitfield
.baseindex
)
7408 as_bad (_("0x%lx out range of signed 32bit displacement"),
7409 (long) exp
->X_add_number
);
7415 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7416 else if (exp
->X_op
!= O_constant
7417 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7418 && exp_seg
!= absolute_section
7419 && exp_seg
!= text_section
7420 && exp_seg
!= data_section
7421 && exp_seg
!= bss_section
7422 && exp_seg
!= undefined_section
7423 && !bfd_is_com_section (exp_seg
))
7425 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7430 /* Check if this is a displacement only operand. */
7431 bigdisp
= i
.types
[this_operand
];
7432 bigdisp
.bitfield
.disp8
= 0;
7433 bigdisp
.bitfield
.disp16
= 0;
7434 bigdisp
.bitfield
.disp32
= 0;
7435 bigdisp
.bitfield
.disp32s
= 0;
7436 bigdisp
.bitfield
.disp64
= 0;
7437 if (operand_type_all_zero (&bigdisp
))
7438 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7444 /* Make sure the memory operand we've been dealt is valid.
7445 Return 1 on success, 0 on a failure. */
7448 i386_index_check (const char *operand_string
)
7450 const char *kind
= "base/index";
7451 enum flag_code addr_mode
;
7453 if (i
.prefix
[ADDR_PREFIX
])
7454 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
7457 addr_mode
= flag_code
;
7459 #if INFER_ADDR_PREFIX
7460 if (i
.mem_operands
== 0)
7462 /* Infer address prefix from the first memory operand. */
7463 const reg_entry
*addr_reg
= i
.base_reg
;
7465 if (addr_reg
== NULL
)
7466 addr_reg
= i
.index_reg
;
7470 if (addr_reg
->reg_num
== RegEip
7471 || addr_reg
->reg_num
== RegEiz
7472 || addr_reg
->reg_type
.bitfield
.reg32
)
7473 addr_mode
= CODE_32BIT
;
7474 else if (flag_code
!= CODE_64BIT
7475 && addr_reg
->reg_type
.bitfield
.reg16
)
7476 addr_mode
= CODE_16BIT
;
7478 if (addr_mode
!= flag_code
)
7480 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7482 /* Change the size of any displacement too. At most one
7483 of Disp16 or Disp32 is set.
7484 FIXME. There doesn't seem to be any real need for
7485 separate Disp16 and Disp32 flags. The same goes for
7486 Imm16 and Imm32. Removing them would probably clean
7487 up the code quite a lot. */
7488 if (flag_code
!= CODE_64BIT
7489 && (i
.types
[this_operand
].bitfield
.disp16
7490 || i
.types
[this_operand
].bitfield
.disp32
))
7491 i
.types
[this_operand
]
7492 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7499 if (current_templates
->start
->opcode_modifier
.isstring
7500 && !current_templates
->start
->opcode_modifier
.immext
7501 && (current_templates
->end
[-1].opcode_modifier
.isstring
7504 /* Memory operands of string insns are special in that they only allow
7505 a single register (rDI, rSI, or rBX) as their memory address. */
7506 const reg_entry
*expected_reg
;
7507 static const char *di_si
[][2] =
7513 static const char *bx
[] = { "ebx", "bx", "rbx" };
7515 kind
= "string address";
7517 if (current_templates
->start
->opcode_modifier
.w
)
7519 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7521 if (!type
.bitfield
.baseindex
7522 || ((!i
.mem_operands
!= !intel_syntax
)
7523 && current_templates
->end
[-1].operand_types
[1]
7524 .bitfield
.baseindex
))
7525 type
= current_templates
->end
[-1].operand_types
[1];
7526 expected_reg
= hash_find (reg_hash
,
7527 di_si
[addr_mode
][type
.bitfield
.esseg
]);
7531 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
7533 if (i
.base_reg
!= expected_reg
7535 || operand_type_check (i
.types
[this_operand
], disp
))
7537 /* The second memory operand must have the same size as
7541 && !((addr_mode
== CODE_64BIT
7542 && i
.base_reg
->reg_type
.bitfield
.reg64
)
7543 || (addr_mode
== CODE_32BIT
7544 ? i
.base_reg
->reg_type
.bitfield
.reg32
7545 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
7548 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7550 intel_syntax
? '[' : '(',
7552 expected_reg
->reg_name
,
7553 intel_syntax
? ']' : ')');
7560 as_bad (_("`%s' is not a valid %s expression"),
7561 operand_string
, kind
);
7566 if (addr_mode
!= CODE_16BIT
)
7568 /* 32-bit/64-bit checks. */
7570 && (addr_mode
== CODE_64BIT
7571 ? !i
.base_reg
->reg_type
.bitfield
.reg64
7572 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
7574 || (i
.base_reg
->reg_num
7575 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
7577 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7578 && !i
.index_reg
->reg_type
.bitfield
.regymm
7579 && ((addr_mode
== CODE_64BIT
7580 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
7581 || i
.index_reg
->reg_num
== RegRiz
)
7582 : !(i
.index_reg
->reg_type
.bitfield
.reg32
7583 || i
.index_reg
->reg_num
== RegEiz
))
7584 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7589 /* 16-bit checks. */
7591 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7592 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7594 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7595 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7597 && i
.base_reg
->reg_num
< 6
7598 && i
.index_reg
->reg_num
>= 6
7599 && i
.log2_scale_factor
== 0))))
7606 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7610 i386_att_operand (char *operand_string
)
7614 char *op_string
= operand_string
;
7616 if (is_space_char (*op_string
))
7619 /* We check for an absolute prefix (differentiating,
7620 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7621 if (*op_string
== ABSOLUTE_PREFIX
)
7624 if (is_space_char (*op_string
))
7626 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7629 /* Check if operand is a register. */
7630 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7632 i386_operand_type temp
;
7634 /* Check for a segment override by searching for ':' after a
7635 segment register. */
7637 if (is_space_char (*op_string
))
7639 if (*op_string
== ':'
7640 && (r
->reg_type
.bitfield
.sreg2
7641 || r
->reg_type
.bitfield
.sreg3
))
7646 i
.seg
[i
.mem_operands
] = &es
;
7649 i
.seg
[i
.mem_operands
] = &cs
;
7652 i
.seg
[i
.mem_operands
] = &ss
;
7655 i
.seg
[i
.mem_operands
] = &ds
;
7658 i
.seg
[i
.mem_operands
] = &fs
;
7661 i
.seg
[i
.mem_operands
] = &gs
;
7665 /* Skip the ':' and whitespace. */
7667 if (is_space_char (*op_string
))
7670 if (!is_digit_char (*op_string
)
7671 && !is_identifier_char (*op_string
)
7672 && *op_string
!= '('
7673 && *op_string
!= ABSOLUTE_PREFIX
)
7675 as_bad (_("bad memory operand `%s'"), op_string
);
7678 /* Handle case of %es:*foo. */
7679 if (*op_string
== ABSOLUTE_PREFIX
)
7682 if (is_space_char (*op_string
))
7684 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7686 goto do_memory_reference
;
7690 as_bad (_("junk `%s' after register"), op_string
);
7694 temp
.bitfield
.baseindex
= 0;
7695 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7697 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7698 i
.op
[this_operand
].regs
= r
;
7701 else if (*op_string
== REGISTER_PREFIX
)
7703 as_bad (_("bad register name `%s'"), op_string
);
7706 else if (*op_string
== IMMEDIATE_PREFIX
)
7709 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7711 as_bad (_("immediate operand illegal with absolute jump"));
7714 if (!i386_immediate (op_string
))
7717 else if (is_digit_char (*op_string
)
7718 || is_identifier_char (*op_string
)
7719 || *op_string
== '(')
7721 /* This is a memory reference of some sort. */
7724 /* Start and end of displacement string expression (if found). */
7725 char *displacement_string_start
;
7726 char *displacement_string_end
;
7728 do_memory_reference
:
7729 if ((i
.mem_operands
== 1
7730 && !current_templates
->start
->opcode_modifier
.isstring
)
7731 || i
.mem_operands
== 2)
7733 as_bad (_("too many memory references for `%s'"),
7734 current_templates
->start
->name
);
7738 /* Check for base index form. We detect the base index form by
7739 looking for an ')' at the end of the operand, searching
7740 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7742 base_string
= op_string
+ strlen (op_string
);
7745 if (is_space_char (*base_string
))
7748 /* If we only have a displacement, set-up for it to be parsed later. */
7749 displacement_string_start
= op_string
;
7750 displacement_string_end
= base_string
+ 1;
7752 if (*base_string
== ')')
7755 unsigned int parens_balanced
= 1;
7756 /* We've already checked that the number of left & right ()'s are
7757 equal, so this loop will not be infinite. */
7761 if (*base_string
== ')')
7763 if (*base_string
== '(')
7766 while (parens_balanced
);
7768 temp_string
= base_string
;
7770 /* Skip past '(' and whitespace. */
7772 if (is_space_char (*base_string
))
7775 if (*base_string
== ','
7776 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7779 displacement_string_end
= temp_string
;
7781 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7785 base_string
= end_op
;
7786 if (is_space_char (*base_string
))
7790 /* There may be an index reg or scale factor here. */
7791 if (*base_string
== ',')
7794 if (is_space_char (*base_string
))
7797 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7800 base_string
= end_op
;
7801 if (is_space_char (*base_string
))
7803 if (*base_string
== ',')
7806 if (is_space_char (*base_string
))
7809 else if (*base_string
!= ')')
7811 as_bad (_("expecting `,' or `)' "
7812 "after index register in `%s'"),
7817 else if (*base_string
== REGISTER_PREFIX
)
7819 end_op
= strchr (base_string
, ',');
7822 as_bad (_("bad register name `%s'"), base_string
);
7826 /* Check for scale factor. */
7827 if (*base_string
!= ')')
7829 char *end_scale
= i386_scale (base_string
);
7834 base_string
= end_scale
;
7835 if (is_space_char (*base_string
))
7837 if (*base_string
!= ')')
7839 as_bad (_("expecting `)' "
7840 "after scale factor in `%s'"),
7845 else if (!i
.index_reg
)
7847 as_bad (_("expecting index register or scale factor "
7848 "after `,'; got '%c'"),
7853 else if (*base_string
!= ')')
7855 as_bad (_("expecting `,' or `)' "
7856 "after base register in `%s'"),
7861 else if (*base_string
== REGISTER_PREFIX
)
7863 end_op
= strchr (base_string
, ',');
7866 as_bad (_("bad register name `%s'"), base_string
);
7871 /* If there's an expression beginning the operand, parse it,
7872 assuming displacement_string_start and
7873 displacement_string_end are meaningful. */
7874 if (displacement_string_start
!= displacement_string_end
)
7876 if (!i386_displacement (displacement_string_start
,
7877 displacement_string_end
))
7881 /* Special case for (%dx) while doing input/output op. */
7883 && operand_type_equal (&i
.base_reg
->reg_type
,
7884 ®16_inoutportreg
)
7886 && i
.log2_scale_factor
== 0
7887 && i
.seg
[i
.mem_operands
] == 0
7888 && !operand_type_check (i
.types
[this_operand
], disp
))
7890 i
.types
[this_operand
] = inoutportreg
;
7894 if (i386_index_check (operand_string
) == 0)
7896 i
.types
[this_operand
].bitfield
.mem
= 1;
7901 /* It's not a memory operand; argh! */
7902 as_bad (_("invalid char %s beginning operand %d `%s'"),
7903 output_invalid (*op_string
),
7908 return 1; /* Normal return. */
7911 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7912 that an rs_machine_dependent frag may reach. */
7915 i386_frag_max_var (fragS
*frag
)
7917 /* The only relaxable frags are for jumps.
7918 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7919 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7920 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7923 /* md_estimate_size_before_relax()
7925 Called just before relax() for rs_machine_dependent frags. The x86
7926 assembler uses these frags to handle variable size jump
7929 Any symbol that is now undefined will not become defined.
7930 Return the correct fr_subtype in the frag.
7931 Return the initial "guess for variable size of frag" to caller.
7932 The guess is actually the growth beyond the fixed part. Whatever
7933 we do to grow the fixed or variable part contributes to our
7937 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7939 /* We've already got fragP->fr_subtype right; all we have to do is
7940 check for un-relaxable symbols. On an ELF system, we can't relax
7941 an externally visible symbol, because it may be overridden by a
7943 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7946 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7947 || S_IS_WEAK (fragP
->fr_symbol
)
7948 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7949 & BSF_GNU_INDIRECT_FUNCTION
))))
7951 #if defined (OBJ_COFF) && defined (TE_PE)
7952 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7953 && S_IS_WEAK (fragP
->fr_symbol
))
7957 /* Symbol is undefined in this segment, or we need to keep a
7958 reloc so that weak symbols can be overridden. */
7959 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7960 enum bfd_reloc_code_real reloc_type
;
7961 unsigned char *opcode
;
7964 if (fragP
->fr_var
!= NO_RELOC
)
7965 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7967 reloc_type
= BFD_RELOC_16_PCREL
;
7969 reloc_type
= BFD_RELOC_32_PCREL
;
7971 old_fr_fix
= fragP
->fr_fix
;
7972 opcode
= (unsigned char *) fragP
->fr_opcode
;
7974 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7977 /* Make jmp (0xeb) a (d)word displacement jump. */
7979 fragP
->fr_fix
+= size
;
7980 fix_new (fragP
, old_fr_fix
, size
,
7982 fragP
->fr_offset
, 1,
7988 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7990 /* Negate the condition, and branch past an
7991 unconditional jump. */
7994 /* Insert an unconditional jump. */
7996 /* We added two extra opcode bytes, and have a two byte
7998 fragP
->fr_fix
+= 2 + 2;
7999 fix_new (fragP
, old_fr_fix
+ 2, 2,
8001 fragP
->fr_offset
, 1,
8008 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8013 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8015 fragP
->fr_offset
, 1,
8017 fixP
->fx_signed
= 1;
8021 /* This changes the byte-displacement jump 0x7N
8022 to the (d)word-displacement jump 0x0f,0x8N. */
8023 opcode
[1] = opcode
[0] + 0x10;
8024 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8025 /* We've added an opcode byte. */
8026 fragP
->fr_fix
+= 1 + size
;
8027 fix_new (fragP
, old_fr_fix
+ 1, size
,
8029 fragP
->fr_offset
, 1,
8034 BAD_CASE (fragP
->fr_subtype
);
8038 return fragP
->fr_fix
- old_fr_fix
;
8041 /* Guess size depending on current relax state. Initially the relax
8042 state will correspond to a short jump and we return 1, because
8043 the variable part of the frag (the branch offset) is one byte
8044 long. However, we can relax a section more than once and in that
8045 case we must either set fr_subtype back to the unrelaxed state,
8046 or return the value for the appropriate branch. */
8047 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8050 /* Called after relax() is finished.
8052 In: Address of frag.
8053 fr_type == rs_machine_dependent.
8054 fr_subtype is what the address relaxed to.
8056 Out: Any fixSs and constants are set up.
8057 Caller will turn frag into a ".space 0". */
8060 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8063 unsigned char *opcode
;
8064 unsigned char *where_to_put_displacement
= NULL
;
8065 offsetT target_address
;
8066 offsetT opcode_address
;
8067 unsigned int extension
= 0;
8068 offsetT displacement_from_opcode_start
;
8070 opcode
= (unsigned char *) fragP
->fr_opcode
;
8072 /* Address we want to reach in file space. */
8073 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8075 /* Address opcode resides at in file space. */
8076 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8078 /* Displacement from opcode start to fill into instruction. */
8079 displacement_from_opcode_start
= target_address
- opcode_address
;
8081 if ((fragP
->fr_subtype
& BIG
) == 0)
8083 /* Don't have to change opcode. */
8084 extension
= 1; /* 1 opcode + 1 displacement */
8085 where_to_put_displacement
= &opcode
[1];
8089 if (no_cond_jump_promotion
8090 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8091 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8092 _("long jump required"));
8094 switch (fragP
->fr_subtype
)
8096 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8097 extension
= 4; /* 1 opcode + 4 displacement */
8099 where_to_put_displacement
= &opcode
[1];
8102 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8103 extension
= 2; /* 1 opcode + 2 displacement */
8105 where_to_put_displacement
= &opcode
[1];
8108 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8109 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8110 extension
= 5; /* 2 opcode + 4 displacement */
8111 opcode
[1] = opcode
[0] + 0x10;
8112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8113 where_to_put_displacement
= &opcode
[2];
8116 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8117 extension
= 3; /* 2 opcode + 2 displacement */
8118 opcode
[1] = opcode
[0] + 0x10;
8119 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8120 where_to_put_displacement
= &opcode
[2];
8123 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8128 where_to_put_displacement
= &opcode
[3];
8132 BAD_CASE (fragP
->fr_subtype
);
8137 /* If size if less then four we are sure that the operand fits,
8138 but if it's 4, then it could be that the displacement is larger
8140 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8142 && ((addressT
) (displacement_from_opcode_start
- extension
8143 + ((addressT
) 1 << 31))
8144 > (((addressT
) 2 << 31) - 1)))
8146 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8147 _("jump target out of range"));
8148 /* Make us emit 0. */
8149 displacement_from_opcode_start
= extension
;
8151 /* Now put displacement after opcode. */
8152 md_number_to_chars ((char *) where_to_put_displacement
,
8153 (valueT
) (displacement_from_opcode_start
- extension
),
8154 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8155 fragP
->fr_fix
+= extension
;
8158 /* Apply a fixup (fixP) to segment data, once it has been determined
8159 by our caller that we have all the info we need to fix it up.
8161 Parameter valP is the pointer to the value of the bits.
8163 On the 386, immediates, displacements, and data pointers are all in
8164 the same (little-endian) format, so we don't need to care about which
8168 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8170 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8171 valueT value
= *valP
;
8173 #if !defined (TE_Mach)
8176 switch (fixP
->fx_r_type
)
8182 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8185 case BFD_RELOC_X86_64_32S
:
8186 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8189 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8192 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8197 if (fixP
->fx_addsy
!= NULL
8198 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8199 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8200 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8201 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8202 && !use_rela_relocations
)
8204 /* This is a hack. There should be a better way to handle this.
8205 This covers for the fact that bfd_install_relocation will
8206 subtract the current location (for partial_inplace, PC relative
8207 relocations); see more below. */
8211 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8214 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8219 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8222 || (symbol_section_p (fixP
->fx_addsy
)
8223 && sym_seg
!= absolute_section
))
8224 && !generic_force_reloc (fixP
))
8226 /* Yes, we add the values in twice. This is because
8227 bfd_install_relocation subtracts them out again. I think
8228 bfd_install_relocation is broken, but I don't dare change
8230 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8234 #if defined (OBJ_COFF) && defined (TE_PE)
8235 /* For some reason, the PE format does not store a
8236 section address offset for a PC relative symbol. */
8237 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8238 || S_IS_WEAK (fixP
->fx_addsy
))
8239 value
+= md_pcrel_from (fixP
);
8242 #if defined (OBJ_COFF) && defined (TE_PE)
8243 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8245 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8249 /* Fix a few things - the dynamic linker expects certain values here,
8250 and we must not disappoint it. */
8251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8252 if (IS_ELF
&& fixP
->fx_addsy
)
8253 switch (fixP
->fx_r_type
)
8255 case BFD_RELOC_386_PLT32
:
8256 case BFD_RELOC_X86_64_PLT32
:
8257 /* Make the jump instruction point to the address of the operand. At
8258 runtime we merely add the offset to the actual PLT entry. */
8262 case BFD_RELOC_386_TLS_GD
:
8263 case BFD_RELOC_386_TLS_LDM
:
8264 case BFD_RELOC_386_TLS_IE_32
:
8265 case BFD_RELOC_386_TLS_IE
:
8266 case BFD_RELOC_386_TLS_GOTIE
:
8267 case BFD_RELOC_386_TLS_GOTDESC
:
8268 case BFD_RELOC_X86_64_TLSGD
:
8269 case BFD_RELOC_X86_64_TLSLD
:
8270 case BFD_RELOC_X86_64_GOTTPOFF
:
8271 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8272 value
= 0; /* Fully resolved at runtime. No addend. */
8274 case BFD_RELOC_386_TLS_LE
:
8275 case BFD_RELOC_386_TLS_LDO_32
:
8276 case BFD_RELOC_386_TLS_LE_32
:
8277 case BFD_RELOC_X86_64_DTPOFF32
:
8278 case BFD_RELOC_X86_64_DTPOFF64
:
8279 case BFD_RELOC_X86_64_TPOFF32
:
8280 case BFD_RELOC_X86_64_TPOFF64
:
8281 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8284 case BFD_RELOC_386_TLS_DESC_CALL
:
8285 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8286 value
= 0; /* Fully resolved at runtime. No addend. */
8287 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8291 case BFD_RELOC_386_GOT32
:
8292 case BFD_RELOC_X86_64_GOT32
:
8293 value
= 0; /* Fully resolved at runtime. No addend. */
8296 case BFD_RELOC_VTABLE_INHERIT
:
8297 case BFD_RELOC_VTABLE_ENTRY
:
8304 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8306 #endif /* !defined (TE_Mach) */
8308 /* Are we finished with this relocation now? */
8309 if (fixP
->fx_addsy
== NULL
)
8311 #if defined (OBJ_COFF) && defined (TE_PE)
8312 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8315 /* Remember value for tc_gen_reloc. */
8316 fixP
->fx_addnumber
= value
;
8317 /* Clear out the frag for now. */
8321 else if (use_rela_relocations
)
8323 fixP
->fx_no_overflow
= 1;
8324 /* Remember value for tc_gen_reloc. */
8325 fixP
->fx_addnumber
= value
;
8329 md_number_to_chars (p
, value
, fixP
->fx_size
);
8333 md_atof (int type
, char *litP
, int *sizeP
)
8335 /* This outputs the LITTLENUMs in REVERSE order;
8336 in accord with the bigendian 386. */
8337 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8340 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8343 output_invalid (int c
)
8346 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8349 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8350 "(0x%x)", (unsigned char) c
);
8351 return output_invalid_buf
;
8354 /* REG_STRING starts *before* REGISTER_PREFIX. */
8356 static const reg_entry
*
8357 parse_real_register (char *reg_string
, char **end_op
)
8359 char *s
= reg_string
;
8361 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8364 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8365 if (*s
== REGISTER_PREFIX
)
8368 if (is_space_char (*s
))
8372 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8374 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8375 return (const reg_entry
*) NULL
;
8379 /* For naked regs, make sure that we are not dealing with an identifier.
8380 This prevents confusing an identifier like `eax_var' with register
8382 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8383 return (const reg_entry
*) NULL
;
8387 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8389 /* Handle floating point regs, allowing spaces in the (i) part. */
8390 if (r
== i386_regtab
/* %st is first entry of table */)
8392 if (is_space_char (*s
))
8397 if (is_space_char (*s
))
8399 if (*s
>= '0' && *s
<= '7')
8403 if (is_space_char (*s
))
8408 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8413 /* We have "%st(" then garbage. */
8414 return (const reg_entry
*) NULL
;
8418 if (r
== NULL
|| allow_pseudo_reg
)
8421 if (operand_type_all_zero (&r
->reg_type
))
8422 return (const reg_entry
*) NULL
;
8424 if ((r
->reg_type
.bitfield
.reg32
8425 || r
->reg_type
.bitfield
.sreg3
8426 || r
->reg_type
.bitfield
.control
8427 || r
->reg_type
.bitfield
.debug
8428 || r
->reg_type
.bitfield
.test
)
8429 && !cpu_arch_flags
.bitfield
.cpui386
)
8430 return (const reg_entry
*) NULL
;
8432 if (r
->reg_type
.bitfield
.floatreg
8433 && !cpu_arch_flags
.bitfield
.cpu8087
8434 && !cpu_arch_flags
.bitfield
.cpu287
8435 && !cpu_arch_flags
.bitfield
.cpu387
)
8436 return (const reg_entry
*) NULL
;
8438 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8439 return (const reg_entry
*) NULL
;
8441 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8442 return (const reg_entry
*) NULL
;
8444 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8445 return (const reg_entry
*) NULL
;
8447 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8448 if (!allow_index_reg
8449 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8450 return (const reg_entry
*) NULL
;
8452 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8453 || r
->reg_type
.bitfield
.reg64
)
8454 && (!cpu_arch_flags
.bitfield
.cpulm
8455 || !operand_type_equal (&r
->reg_type
, &control
))
8456 && flag_code
!= CODE_64BIT
)
8457 return (const reg_entry
*) NULL
;
8459 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8460 return (const reg_entry
*) NULL
;
8465 /* REG_STRING starts *before* REGISTER_PREFIX. */
8467 static const reg_entry
*
8468 parse_register (char *reg_string
, char **end_op
)
8472 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8473 r
= parse_real_register (reg_string
, end_op
);
8478 char *save
= input_line_pointer
;
8482 input_line_pointer
= reg_string
;
8483 c
= get_symbol_end ();
8484 symbolP
= symbol_find (reg_string
);
8485 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8487 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8489 know (e
->X_op
== O_register
);
8490 know (e
->X_add_number
>= 0
8491 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8492 r
= i386_regtab
+ e
->X_add_number
;
8493 *end_op
= input_line_pointer
;
8495 *input_line_pointer
= c
;
8496 input_line_pointer
= save
;
8502 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8505 char *end
= input_line_pointer
;
8508 r
= parse_register (name
, &input_line_pointer
);
8509 if (r
&& end
<= input_line_pointer
)
8511 *nextcharP
= *input_line_pointer
;
8512 *input_line_pointer
= 0;
8513 e
->X_op
= O_register
;
8514 e
->X_add_number
= r
- i386_regtab
;
8517 input_line_pointer
= end
;
8519 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8523 md_operand (expressionS
*e
)
8528 switch (*input_line_pointer
)
8530 case REGISTER_PREFIX
:
8531 r
= parse_real_register (input_line_pointer
, &end
);
8534 e
->X_op
= O_register
;
8535 e
->X_add_number
= r
- i386_regtab
;
8536 input_line_pointer
= end
;
8541 gas_assert (intel_syntax
);
8542 end
= input_line_pointer
++;
8544 if (*input_line_pointer
== ']')
8546 ++input_line_pointer
;
8547 e
->X_op_symbol
= make_expr_symbol (e
);
8548 e
->X_add_symbol
= NULL
;
8549 e
->X_add_number
= 0;
8555 input_line_pointer
= end
;
8562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8563 const char *md_shortopts
= "kVQ:sqn";
8565 const char *md_shortopts
= "qn";
8568 #define OPTION_32 (OPTION_MD_BASE + 0)
8569 #define OPTION_64 (OPTION_MD_BASE + 1)
8570 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8571 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8572 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8573 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8574 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8575 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8576 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8577 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8578 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8579 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8580 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8581 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8582 #define OPTION_X32 (OPTION_MD_BASE + 14)
8583 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
8585 struct option md_longopts
[] =
8587 {"32", no_argument
, NULL
, OPTION_32
},
8588 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8589 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8590 {"64", no_argument
, NULL
, OPTION_64
},
8592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8593 {"x32", no_argument
, NULL
, OPTION_X32
},
8595 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8596 {"march", required_argument
, NULL
, OPTION_MARCH
},
8597 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8598 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8599 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8600 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8601 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8602 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8603 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8604 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8605 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8606 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8607 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
8608 {NULL
, no_argument
, NULL
, 0}
8610 size_t md_longopts_size
= sizeof (md_longopts
);
8613 md_parse_option (int c
, char *arg
)
8621 optimize_align_code
= 0;
8628 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8629 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8630 should be emitted or not. FIXME: Not implemented. */
8634 /* -V: SVR4 argument to print version ID. */
8636 print_version_id ();
8639 /* -k: Ignore for FreeBSD compatibility. */
8644 /* -s: On i386 Solaris, this tells the native assembler to use
8645 .stab instead of .stab.excl. We always use .stab anyhow. */
8648 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8649 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8652 const char **list
, **l
;
8654 list
= bfd_target_list ();
8655 for (l
= list
; *l
!= NULL
; l
++)
8656 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8657 || strcmp (*l
, "coff-x86-64") == 0
8658 || strcmp (*l
, "pe-x86-64") == 0
8659 || strcmp (*l
, "pei-x86-64") == 0
8660 || strcmp (*l
, "mach-o-x86-64") == 0)
8662 default_arch
= "x86_64";
8666 as_fatal (_("no compiled in support for x86_64"));
8672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8676 const char **list
, **l
;
8678 list
= bfd_target_list ();
8679 for (l
= list
; *l
!= NULL
; l
++)
8680 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8682 default_arch
= "x86_64:32";
8686 as_fatal (_("no compiled in support for 32bit x86_64"));
8690 as_fatal (_("32bit x86_64 is only supported for ELF"));
8695 default_arch
= "i386";
8699 #ifdef SVR4_COMMENT_CHARS
8704 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8706 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8710 i386_comment_chars
= n
;
8716 arch
= xstrdup (arg
);
8720 as_fatal (_("invalid -march= option: `%s'"), arg
);
8721 next
= strchr (arch
, '+');
8724 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8726 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8729 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8732 cpu_arch_name
= cpu_arch
[j
].name
;
8733 cpu_sub_arch_name
= NULL
;
8734 cpu_arch_flags
= cpu_arch
[j
].flags
;
8735 cpu_arch_isa
= cpu_arch
[j
].type
;
8736 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8737 if (!cpu_arch_tune_set
)
8739 cpu_arch_tune
= cpu_arch_isa
;
8740 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8744 else if (*cpu_arch
[j
].name
== '.'
8745 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8747 /* ISA entension. */
8748 i386_cpu_flags flags
;
8750 if (!cpu_arch
[j
].negated
)
8751 flags
= cpu_flags_or (cpu_arch_flags
,
8754 flags
= cpu_flags_and_not (cpu_arch_flags
,
8756 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8758 if (cpu_sub_arch_name
)
8760 char *name
= cpu_sub_arch_name
;
8761 cpu_sub_arch_name
= concat (name
,
8763 (const char *) NULL
);
8767 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8768 cpu_arch_flags
= flags
;
8769 cpu_arch_isa_flags
= flags
;
8775 if (j
>= ARRAY_SIZE (cpu_arch
))
8776 as_fatal (_("invalid -march= option: `%s'"), arg
);
8780 while (next
!= NULL
);
8785 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8786 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8788 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8790 cpu_arch_tune_set
= 1;
8791 cpu_arch_tune
= cpu_arch
[j
].type
;
8792 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8796 if (j
>= ARRAY_SIZE (cpu_arch
))
8797 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8800 case OPTION_MMNEMONIC
:
8801 if (strcasecmp (arg
, "att") == 0)
8803 else if (strcasecmp (arg
, "intel") == 0)
8806 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8809 case OPTION_MSYNTAX
:
8810 if (strcasecmp (arg
, "att") == 0)
8812 else if (strcasecmp (arg
, "intel") == 0)
8815 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8818 case OPTION_MINDEX_REG
:
8819 allow_index_reg
= 1;
8822 case OPTION_MNAKED_REG
:
8823 allow_naked_reg
= 1;
8826 case OPTION_MOLD_GCC
:
8830 case OPTION_MSSE2AVX
:
8834 case OPTION_MSSE_CHECK
:
8835 if (strcasecmp (arg
, "error") == 0)
8836 sse_check
= check_error
;
8837 else if (strcasecmp (arg
, "warning") == 0)
8838 sse_check
= check_warning
;
8839 else if (strcasecmp (arg
, "none") == 0)
8840 sse_check
= check_none
;
8842 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8845 case OPTION_MOPERAND_CHECK
:
8846 if (strcasecmp (arg
, "error") == 0)
8847 operand_check
= check_error
;
8848 else if (strcasecmp (arg
, "warning") == 0)
8849 operand_check
= check_warning
;
8850 else if (strcasecmp (arg
, "none") == 0)
8851 operand_check
= check_none
;
8853 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8856 case OPTION_MAVXSCALAR
:
8857 if (strcasecmp (arg
, "128") == 0)
8859 else if (strcasecmp (arg
, "256") == 0)
8862 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8865 case OPTION_MADD_BND_PREFIX
:
8875 #define MESSAGE_TEMPLATE \
8879 show_arch (FILE *stream
, int ext
, int check
)
8881 static char message
[] = MESSAGE_TEMPLATE
;
8882 char *start
= message
+ 27;
8884 int size
= sizeof (MESSAGE_TEMPLATE
);
8891 left
= size
- (start
- message
);
8892 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8894 /* Should it be skipped? */
8895 if (cpu_arch
[j
].skip
)
8898 name
= cpu_arch
[j
].name
;
8899 len
= cpu_arch
[j
].len
;
8902 /* It is an extension. Skip if we aren't asked to show it. */
8913 /* It is an processor. Skip if we show only extension. */
8916 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8918 /* It is an impossible processor - skip. */
8922 /* Reserve 2 spaces for ", " or ",\0" */
8925 /* Check if there is any room. */
8933 p
= mempcpy (p
, name
, len
);
8937 /* Output the current message now and start a new one. */
8940 fprintf (stream
, "%s\n", message
);
8942 left
= size
- (start
- message
) - len
- 2;
8944 gas_assert (left
>= 0);
8946 p
= mempcpy (p
, name
, len
);
8951 fprintf (stream
, "%s\n", message
);
8955 md_show_usage (FILE *stream
)
8957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8958 fprintf (stream
, _("\
8960 -V print assembler version number\n\
8963 fprintf (stream
, _("\
8964 -n Do not optimize code alignment\n\
8965 -q quieten some warnings\n"));
8966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8967 fprintf (stream
, _("\
8970 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8971 || defined (TE_PE) || defined (TE_PEP))
8972 fprintf (stream
, _("\
8973 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8975 #ifdef SVR4_COMMENT_CHARS
8976 fprintf (stream
, _("\
8977 --divide do not treat `/' as a comment character\n"));
8979 fprintf (stream
, _("\
8980 --divide ignored\n"));
8982 fprintf (stream
, _("\
8983 -march=CPU[,+EXTENSION...]\n\
8984 generate code for CPU and EXTENSION, CPU is one of:\n"));
8985 show_arch (stream
, 0, 1);
8986 fprintf (stream
, _("\
8987 EXTENSION is combination of:\n"));
8988 show_arch (stream
, 1, 0);
8989 fprintf (stream
, _("\
8990 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8991 show_arch (stream
, 0, 0);
8992 fprintf (stream
, _("\
8993 -msse2avx encode SSE instructions with VEX prefix\n"));
8994 fprintf (stream
, _("\
8995 -msse-check=[none|error|warning]\n\
8996 check SSE instructions\n"));
8997 fprintf (stream
, _("\
8998 -moperand-check=[none|error|warning]\n\
8999 check operand combinations for validity\n"));
9000 fprintf (stream
, _("\
9001 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9003 fprintf (stream
, _("\
9004 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9005 fprintf (stream
, _("\
9006 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9007 fprintf (stream
, _("\
9008 -mindex-reg support pseudo index registers\n"));
9009 fprintf (stream
, _("\
9010 -mnaked-reg don't require `%%' prefix for registers\n"));
9011 fprintf (stream
, _("\
9012 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9013 fprintf (stream
, _("\
9014 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9017 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9018 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9019 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9021 /* Pick the target format to use. */
9024 i386_target_format (void)
9026 if (!strncmp (default_arch
, "x86_64", 6))
9028 update_code_flag (CODE_64BIT
, 1);
9029 if (default_arch
[6] == '\0')
9030 x86_elf_abi
= X86_64_ABI
;
9032 x86_elf_abi
= X86_64_X32_ABI
;
9034 else if (!strcmp (default_arch
, "i386"))
9035 update_code_flag (CODE_32BIT
, 1);
9037 as_fatal (_("unknown architecture"));
9039 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9040 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9041 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9042 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9044 switch (OUTPUT_FLAVOR
)
9046 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9047 case bfd_target_aout_flavour
:
9048 return AOUT_TARGET_FORMAT
;
9050 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9051 # if defined (TE_PE) || defined (TE_PEP)
9052 case bfd_target_coff_flavour
:
9053 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9054 # elif defined (TE_GO32)
9055 case bfd_target_coff_flavour
:
9058 case bfd_target_coff_flavour
:
9062 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9063 case bfd_target_elf_flavour
:
9067 switch (x86_elf_abi
)
9070 format
= ELF_TARGET_FORMAT
;
9073 use_rela_relocations
= 1;
9075 format
= ELF_TARGET_FORMAT64
;
9077 case X86_64_X32_ABI
:
9078 use_rela_relocations
= 1;
9080 disallow_64bit_reloc
= 1;
9081 format
= ELF_TARGET_FORMAT32
;
9084 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9086 if (x86_elf_abi
!= X86_64_ABI
)
9087 as_fatal (_("Intel L1OM is 64bit only"));
9088 return ELF_TARGET_L1OM_FORMAT
;
9090 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9092 if (x86_elf_abi
!= X86_64_ABI
)
9093 as_fatal (_("Intel K1OM is 64bit only"));
9094 return ELF_TARGET_K1OM_FORMAT
;
9100 #if defined (OBJ_MACH_O)
9101 case bfd_target_mach_o_flavour
:
9102 if (flag_code
== CODE_64BIT
)
9104 use_rela_relocations
= 1;
9106 return "mach-o-x86-64";
9109 return "mach-o-i386";
9117 #endif /* OBJ_MAYBE_ more than one */
9119 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9121 i386_elf_emit_arch_note (void)
9123 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9126 asection
*seg
= now_seg
;
9127 subsegT subseg
= now_subseg
;
9128 Elf_Internal_Note i_note
;
9129 Elf_External_Note e_note
;
9130 asection
*note_secp
;
9133 /* Create the .note section. */
9134 note_secp
= subseg_new (".note", 0);
9135 bfd_set_section_flags (stdoutput
,
9137 SEC_HAS_CONTENTS
| SEC_READONLY
);
9139 /* Process the arch string. */
9140 len
= strlen (cpu_arch_name
);
9142 i_note
.namesz
= len
+ 1;
9144 i_note
.type
= NT_ARCH
;
9145 p
= frag_more (sizeof (e_note
.namesz
));
9146 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9147 p
= frag_more (sizeof (e_note
.descsz
));
9148 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9149 p
= frag_more (sizeof (e_note
.type
));
9150 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9151 p
= frag_more (len
+ 1);
9152 strcpy (p
, cpu_arch_name
);
9154 frag_align (2, 0, 0);
9156 subseg_set (seg
, subseg
);
9162 md_undefined_symbol (char *name
)
9164 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9165 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9166 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9167 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9171 if (symbol_find (name
))
9172 as_bad (_("GOT already in symbol table"));
9173 GOT_symbol
= symbol_new (name
, undefined_section
,
9174 (valueT
) 0, &zero_address_frag
);
9181 /* Round up a section size to the appropriate boundary. */
9184 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9186 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9187 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9189 /* For a.out, force the section size to be aligned. If we don't do
9190 this, BFD will align it for us, but it will not write out the
9191 final bytes of the section. This may be a bug in BFD, but it is
9192 easier to fix it here since that is how the other a.out targets
9196 align
= bfd_get_section_alignment (stdoutput
, segment
);
9197 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9204 /* On the i386, PC-relative offsets are relative to the start of the
9205 next instruction. That is, the address of the offset, plus its
9206 size, since the offset is always the last part of the insn. */
9209 md_pcrel_from (fixS
*fixP
)
9211 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9217 s_bss (int ignore ATTRIBUTE_UNUSED
)
9221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9223 obj_elf_section_change_hook ();
9225 temp
= get_absolute_expression ();
9226 subseg_set (bss_section
, (subsegT
) temp
);
9227 demand_empty_rest_of_line ();
9233 i386_validate_fix (fixS
*fixp
)
9235 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9237 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9241 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9246 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9248 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9255 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9258 bfd_reloc_code_real_type code
;
9260 switch (fixp
->fx_r_type
)
9262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9263 case BFD_RELOC_SIZE32
:
9264 case BFD_RELOC_SIZE64
:
9265 if (S_IS_DEFINED (fixp
->fx_addsy
)
9266 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9268 /* Resolve size relocation against local symbol to size of
9269 the symbol plus addend. */
9270 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9271 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9272 && !fits_in_unsigned_long (value
))
9273 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9274 _("symbol size computation overflow"));
9275 fixp
->fx_addsy
= NULL
;
9276 fixp
->fx_subsy
= NULL
;
9277 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9282 case BFD_RELOC_X86_64_PLT32
:
9283 case BFD_RELOC_X86_64_GOT32
:
9284 case BFD_RELOC_X86_64_GOTPCREL
:
9285 case BFD_RELOC_386_PLT32
:
9286 case BFD_RELOC_386_GOT32
:
9287 case BFD_RELOC_386_GOTOFF
:
9288 case BFD_RELOC_386_GOTPC
:
9289 case BFD_RELOC_386_TLS_GD
:
9290 case BFD_RELOC_386_TLS_LDM
:
9291 case BFD_RELOC_386_TLS_LDO_32
:
9292 case BFD_RELOC_386_TLS_IE_32
:
9293 case BFD_RELOC_386_TLS_IE
:
9294 case BFD_RELOC_386_TLS_GOTIE
:
9295 case BFD_RELOC_386_TLS_LE_32
:
9296 case BFD_RELOC_386_TLS_LE
:
9297 case BFD_RELOC_386_TLS_GOTDESC
:
9298 case BFD_RELOC_386_TLS_DESC_CALL
:
9299 case BFD_RELOC_X86_64_TLSGD
:
9300 case BFD_RELOC_X86_64_TLSLD
:
9301 case BFD_RELOC_X86_64_DTPOFF32
:
9302 case BFD_RELOC_X86_64_DTPOFF64
:
9303 case BFD_RELOC_X86_64_GOTTPOFF
:
9304 case BFD_RELOC_X86_64_TPOFF32
:
9305 case BFD_RELOC_X86_64_TPOFF64
:
9306 case BFD_RELOC_X86_64_GOTOFF64
:
9307 case BFD_RELOC_X86_64_GOTPC32
:
9308 case BFD_RELOC_X86_64_GOT64
:
9309 case BFD_RELOC_X86_64_GOTPCREL64
:
9310 case BFD_RELOC_X86_64_GOTPC64
:
9311 case BFD_RELOC_X86_64_GOTPLT64
:
9312 case BFD_RELOC_X86_64_PLTOFF64
:
9313 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9314 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9316 case BFD_RELOC_VTABLE_ENTRY
:
9317 case BFD_RELOC_VTABLE_INHERIT
:
9319 case BFD_RELOC_32_SECREL
:
9321 code
= fixp
->fx_r_type
;
9323 case BFD_RELOC_X86_64_32S
:
9324 if (!fixp
->fx_pcrel
)
9326 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9327 code
= fixp
->fx_r_type
;
9333 switch (fixp
->fx_size
)
9336 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9337 _("can not do %d byte pc-relative relocation"),
9339 code
= BFD_RELOC_32_PCREL
;
9341 case 1: code
= BFD_RELOC_8_PCREL
; break;
9342 case 2: code
= BFD_RELOC_16_PCREL
; break;
9343 case 4: code
= BFD_RELOC_32_PCREL
; break;
9345 case 8: code
= BFD_RELOC_64_PCREL
; break;
9351 switch (fixp
->fx_size
)
9354 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9355 _("can not do %d byte relocation"),
9357 code
= BFD_RELOC_32
;
9359 case 1: code
= BFD_RELOC_8
; break;
9360 case 2: code
= BFD_RELOC_16
; break;
9361 case 4: code
= BFD_RELOC_32
; break;
9363 case 8: code
= BFD_RELOC_64
; break;
9370 if ((code
== BFD_RELOC_32
9371 || code
== BFD_RELOC_32_PCREL
9372 || code
== BFD_RELOC_X86_64_32S
)
9374 && fixp
->fx_addsy
== GOT_symbol
)
9377 code
= BFD_RELOC_386_GOTPC
;
9379 code
= BFD_RELOC_X86_64_GOTPC32
;
9381 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9383 && fixp
->fx_addsy
== GOT_symbol
)
9385 code
= BFD_RELOC_X86_64_GOTPC64
;
9388 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9389 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9390 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9392 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9394 if (!use_rela_relocations
)
9396 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9397 vtable entry to be used in the relocation's section offset. */
9398 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9399 rel
->address
= fixp
->fx_offset
;
9400 #if defined (OBJ_COFF) && defined (TE_PE)
9401 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9402 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9407 /* Use the rela in 64bit mode. */
9410 if (disallow_64bit_reloc
)
9413 case BFD_RELOC_X86_64_DTPOFF64
:
9414 case BFD_RELOC_X86_64_TPOFF64
:
9415 case BFD_RELOC_64_PCREL
:
9416 case BFD_RELOC_X86_64_GOTOFF64
:
9417 case BFD_RELOC_X86_64_GOT64
:
9418 case BFD_RELOC_X86_64_GOTPCREL64
:
9419 case BFD_RELOC_X86_64_GOTPC64
:
9420 case BFD_RELOC_X86_64_GOTPLT64
:
9421 case BFD_RELOC_X86_64_PLTOFF64
:
9422 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9423 _("cannot represent relocation type %s in x32 mode"),
9424 bfd_get_reloc_code_name (code
));
9430 if (!fixp
->fx_pcrel
)
9431 rel
->addend
= fixp
->fx_offset
;
9435 case BFD_RELOC_X86_64_PLT32
:
9436 case BFD_RELOC_X86_64_GOT32
:
9437 case BFD_RELOC_X86_64_GOTPCREL
:
9438 case BFD_RELOC_X86_64_TLSGD
:
9439 case BFD_RELOC_X86_64_TLSLD
:
9440 case BFD_RELOC_X86_64_GOTTPOFF
:
9441 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9442 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9443 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9446 rel
->addend
= (section
->vma
9448 + fixp
->fx_addnumber
9449 + md_pcrel_from (fixp
));
9454 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9455 if (rel
->howto
== NULL
)
9457 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9458 _("cannot represent relocation type %s"),
9459 bfd_get_reloc_code_name (code
));
9460 /* Set howto to a garbage value so that we can keep going. */
9461 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9462 gas_assert (rel
->howto
!= NULL
);
9468 #include "tc-i386-intel.c"
9471 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9473 int saved_naked_reg
;
9474 char saved_register_dot
;
9476 saved_naked_reg
= allow_naked_reg
;
9477 allow_naked_reg
= 1;
9478 saved_register_dot
= register_chars
['.'];
9479 register_chars
['.'] = '.';
9480 allow_pseudo_reg
= 1;
9481 expression_and_evaluate (exp
);
9482 allow_pseudo_reg
= 0;
9483 register_chars
['.'] = saved_register_dot
;
9484 allow_naked_reg
= saved_naked_reg
;
9486 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9488 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9490 exp
->X_op
= O_constant
;
9491 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9492 .dw2_regnum
[flag_code
>> 1];
9495 exp
->X_op
= O_illegal
;
9500 tc_x86_frame_initial_instructions (void)
9502 static unsigned int sp_regno
[2];
9504 if (!sp_regno
[flag_code
>> 1])
9506 char *saved_input
= input_line_pointer
;
9507 char sp
[][4] = {"esp", "rsp"};
9510 input_line_pointer
= sp
[flag_code
>> 1];
9511 tc_x86_parse_to_dw2regnum (&exp
);
9512 gas_assert (exp
.X_op
== O_constant
);
9513 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9514 input_line_pointer
= saved_input
;
9517 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9518 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9522 x86_dwarf2_addr_size (void)
9524 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9525 if (x86_elf_abi
== X86_64_X32_ABI
)
9528 return bfd_arch_bits_per_address (stdoutput
) / 8;
9532 i386_elf_section_type (const char *str
, size_t len
)
9534 if (flag_code
== CODE_64BIT
9535 && len
== sizeof ("unwind") - 1
9536 && strncmp (str
, "unwind", 6) == 0)
9537 return SHT_X86_64_UNWIND
;
9544 i386_solaris_fix_up_eh_frame (segT sec
)
9546 if (flag_code
== CODE_64BIT
)
9547 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9553 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9557 exp
.X_op
= O_secrel
;
9558 exp
.X_add_symbol
= symbol
;
9559 exp
.X_add_number
= 0;
9560 emit_expr (&exp
, size
);
9564 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9565 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9568 x86_64_section_letter (int letter
, char **ptr_msg
)
9570 if (flag_code
== CODE_64BIT
)
9573 return SHF_X86_64_LARGE
;
9575 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9578 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9583 x86_64_section_word (char *str
, size_t len
)
9585 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9586 return SHF_X86_64_LARGE
;
9592 handle_large_common (int small ATTRIBUTE_UNUSED
)
9594 if (flag_code
!= CODE_64BIT
)
9596 s_comm_internal (0, elf_common_parse
);
9597 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9601 static segT lbss_section
;
9602 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9603 asection
*saved_bss_section
= bss_section
;
9605 if (lbss_section
== NULL
)
9607 flagword applicable
;
9609 subsegT subseg
= now_subseg
;
9611 /* The .lbss section is for local .largecomm symbols. */
9612 lbss_section
= subseg_new (".lbss", 0);
9613 applicable
= bfd_applicable_section_flags (stdoutput
);
9614 bfd_set_section_flags (stdoutput
, lbss_section
,
9615 applicable
& SEC_ALLOC
);
9616 seg_info (lbss_section
)->bss
= 1;
9618 subseg_set (seg
, subseg
);
9621 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9622 bss_section
= lbss_section
;
9624 s_comm_internal (0, elf_common_parse
);
9626 elf_com_section_ptr
= saved_com_section_ptr
;
9627 bss_section
= saved_bss_section
;
9630 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */