1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template
*start
;
106 const insn_template
*end
;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem
; /* codes register or memory operand */
114 unsigned int reg
; /* codes register operand (or extended opcode) */
115 unsigned int mode
; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte
;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name
; /* arch name */
135 unsigned int len
; /* arch string length */
136 enum processor_type type
; /* arch type */
137 i386_cpu_flags flags
; /* cpu feature flags */
138 unsigned int skip
; /* show_arch should skip this. */
139 unsigned int negated
; /* turn off indicated flags. */
143 static void update_code_flag (int, int);
144 static void set_code_flag (int);
145 static void set_16bit_gcc_code_flag (int);
146 static void set_intel_syntax (int);
147 static void set_intel_mnemonic (int);
148 static void set_allow_index_reg (int);
149 static void set_check (int);
150 static void set_cpu_arch (int);
152 static void pe_directive_secrel (int);
154 static void signed_cons (int);
155 static char *output_invalid (int c
);
156 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
158 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
160 static int i386_att_operand (char *);
161 static int i386_intel_operand (char *, int);
162 static int i386_intel_simplify (expressionS
*);
163 static int i386_intel_parse_name (const char *, expressionS
*);
164 static const reg_entry
*parse_register (char *, char **);
165 static char *parse_insn (char *, char *);
166 static char *parse_operands (char *, const char *);
167 static void swap_operands (void);
168 static void swap_2_operands (int, int);
169 static void optimize_imm (void);
170 static void optimize_disp (void);
171 static const insn_template
*match_template (void);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const seg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
191 static const char *default_arch
= DEFAULT_ARCH
;
193 /* This struct describes rounding control and SAE in the instruction. */
207 static struct RC_Operation rc_op
;
209 /* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212 struct Mask_Operation
214 const reg_entry
*mask
;
215 unsigned int zeroing
;
216 /* The operand where this operation is associated. */
220 static struct Mask_Operation mask_op
;
222 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
224 struct Broadcast_Operation
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 /* Index of broadcasted operand. */
233 static struct Broadcast_Operation broadcast_op
;
238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes
[4];
241 /* Destination or source register specifier. */
242 const reg_entry
*register_specifier
;
245 /* 'md_assemble ()' gathers together information and puts it into a
252 const reg_entry
*regs
;
257 operand_size_mismatch
,
258 operand_type_mismatch
,
259 register_type_mismatch
,
260 number_of_operands_mismatch
,
261 invalid_instruction_suffix
,
264 unsupported_with_intel_mnemonic
,
267 invalid_vsib_address
,
268 invalid_vector_register_set
,
269 unsupported_vector_index_register
,
270 unsupported_broadcast
,
271 broadcast_not_on_src_operand
,
274 mask_not_on_destination
,
277 rc_sae_operand_not_last_imm
,
278 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes
;
327 unsigned char prefix
[MAX_PREFIXES
];
329 /* RM and SIB are the modrm byte and the sib byte where the
330 addressing modes of this insn are encoded. */
337 /* Masking attributes. */
338 struct Mask_Operation
*mask
;
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation
*rounding
;
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation
*broadcast
;
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift
;
349 /* Swap operand in encoding. */
350 unsigned int swap_operand
;
352 /* Prefer 8bit or 32bit displacement in encoding. */
355 disp_encoding_default
= 0,
361 const char *rep_prefix
;
364 const char *hle_prefix
;
366 /* Have BND prefix. */
367 const char *bnd_prefix
;
369 /* Need VREX to support upper 16 registers. */
373 enum i386_error error
;
376 typedef struct _i386_insn i386_insn
;
378 /* Link RC type with corresponding string, that'll be looked for in
387 static const struct RC_name RC_NamesTable
[] =
389 { rne
, STRING_COMMA_LEN ("rn-sae") },
390 { rd
, STRING_COMMA_LEN ("rd-sae") },
391 { ru
, STRING_COMMA_LEN ("ru-sae") },
392 { rz
, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly
, STRING_COMMA_LEN ("sae") },
396 /* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
398 const char extra_symbol_chars
[] = "*%-([{"
407 #if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
409 && !defined (TE_GNU) \
410 && !defined (TE_LINUX) \
411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
413 && !defined (TE_FreeBSD) \
414 && !defined (TE_DragonFly) \
415 && !defined (TE_NetBSD)))
416 /* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419 const char *i386_comment_chars
= "#/";
420 #define SVR4_COMMENT_CHARS 1
421 #define PREFIX_SEPARATOR '\\'
424 const char *i386_comment_chars
= "#";
425 #define PREFIX_SEPARATOR '/'
428 /* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
432 first line of the input file. This is because the compiler outputs
433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
435 '/' isn't otherwise defined. */
436 const char line_comment_chars
[] = "#/";
438 const char line_separator_chars
[] = ";";
440 /* Chars that can be used to separate mant from exp in floating point
442 const char EXP_CHARS
[] = "eE";
444 /* Chars that mean this number is a floating point constant
447 const char FLT_CHARS
[] = "fFdDxX";
449 /* Tables for lexical analysis. */
450 static char mnemonic_chars
[256];
451 static char register_chars
[256];
452 static char operand_chars
[256];
453 static char identifier_chars
[256];
454 static char digit_chars
[256];
456 /* Lexical macros. */
457 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458 #define is_operand_char(x) (operand_chars[(unsigned char) x])
459 #define is_register_char(x) (register_chars[(unsigned char) x])
460 #define is_space_char(x) ((x) == ' ')
461 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462 #define is_digit_char(x) (digit_chars[(unsigned char) x])
464 /* All non-digit non-letter characters that may occur in an operand. */
465 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
467 /* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
470 assembler instruction). */
471 static char save_stack
[32];
472 static char *save_stack_p
;
473 #define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475 #define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
478 /* The instruction we're assembling. */
481 /* Possible templates for current insn. */
482 static const templates
*current_templates
;
484 /* Per instruction expressionS buffers: max displacements & immediates. */
485 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
486 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
488 /* Current operand we are working on. */
489 static int this_operand
= -1;
491 /* We support four different modes. FLAG_CODE variable is used to distinguish
499 static enum flag_code flag_code
;
500 static unsigned int object_64bit
;
501 static unsigned int disallow_64bit_reloc
;
502 static int use_rela_relocations
= 0;
504 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
508 /* The ELF ABI to use. */
516 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
519 /* 1 for intel syntax,
521 static int intel_syntax
= 0;
523 /* 1 for intel mnemonic,
524 0 if att mnemonic. */
525 static int intel_mnemonic
= !SYSV386_COMPAT
;
527 /* 1 if support old (<= 2.8.1) versions of gcc. */
528 static int old_gcc
= OLDGCC_COMPAT
;
530 /* 1 if pseudo registers are permitted. */
531 static int allow_pseudo_reg
= 0;
533 /* 1 if register prefix % not required. */
534 static int allow_naked_reg
= 0;
536 /* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
539 static int add_bnd_prefix
= 0;
541 /* 1 if pseudo index register, eiz/riz, is allowed . */
542 static int allow_index_reg
= 0;
544 static enum check_kind
550 sse_check
, operand_check
= check_warning
;
552 /* Register prefix used for error message. */
553 static const char *register_prefix
= "%";
555 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558 static char stackop_size
= '\0';
560 /* Non-zero to optimize code alignment. */
561 int optimize_align_code
= 1;
563 /* Non-zero to quieten some warnings. */
564 static int quiet_warnings
= 0;
567 static const char *cpu_arch_name
= NULL
;
568 static char *cpu_sub_arch_name
= NULL
;
570 /* CPU feature flags. */
571 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
573 /* If we have selected a cpu we are generating instructions for. */
574 static int cpu_arch_tune_set
= 0;
576 /* Cpu we are generating instructions for. */
577 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
579 /* CPU feature flags of cpu we are generating instructions for. */
580 static i386_cpu_flags cpu_arch_tune_flags
;
582 /* CPU instruction set architecture used. */
583 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of instruction set architecture used. */
586 i386_cpu_flags cpu_arch_isa_flags
;
588 /* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590 static unsigned int no_cond_jump_promotion
= 0;
592 /* Encode SSE instructions with VEX prefix. */
593 static unsigned int sse2avx
;
595 /* Encode scalar AVX instructions with specific vector length. */
602 /* Encode scalar EVEX LIG instructions with specific vector length. */
610 /* Encode EVEX WIG instructions with specific evex.w. */
617 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
618 static symbolS
*GOT_symbol
;
620 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
621 unsigned int x86_dwarf2_return_column
;
623 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624 int x86_cie_data_alignment
;
626 /* Interface to relax_segment.
627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
632 #define UNCOND_JUMP 0
634 #define COND_JUMP86 2
639 #define SMALL16 (SMALL | CODE16)
641 #define BIG16 (BIG | CODE16)
645 #define INLINE __inline__
651 #define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653 #define TYPE_FROM_RELAX_STATE(s) \
655 #define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
658 /* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
666 const relax_typeS md_relax_table
[] =
669 1) most positive reach of this state,
670 2) most negative reach of this state,
671 3) how many bytes this mode will have in the variable part of the frag
672 4) which index into the table to try if we can't fit into this one. */
674 /* UNCOND_JUMP states. */
675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
690 /* word conditionals add 3 bytes to frag:
691 1 extra opcode byte, 2 displacement bytes. */
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
705 static const arch_entry cpu_arch
[] =
707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
710 CPU_GENERIC32_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
712 CPU_GENERIC64_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
714 CPU_NONE_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
716 CPU_I186_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
718 CPU_I286_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
720 CPU_I386_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
722 CPU_I486_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
724 CPU_I586_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
726 CPU_I686_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
728 CPU_I586_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
730 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
732 CPU_P2_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
734 CPU_P3_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
736 CPU_P4_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
738 CPU_CORE_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
740 CPU_NOCONA_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
742 CPU_CORE_FLAGS
, 1, 0 },
743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
746 CPU_CORE2_FLAGS
, 1, 0 },
747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
750 CPU_COREI7_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
752 CPU_L1OM_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
754 CPU_K1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
756 CPU_K6_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
758 CPU_K6_2_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
760 CPU_ATHLON_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
762 CPU_K8_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
768 CPU_AMDFAM10_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
770 CPU_BDVER1_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
772 CPU_BDVER2_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
774 CPU_BDVER3_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
776 CPU_BDVER4_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
778 CPU_BTVER1_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
780 CPU_BTVER2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
782 CPU_8087_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
784 CPU_287_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
786 CPU_387_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
788 CPU_ANY87_FLAGS
, 0, 1 },
789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
790 CPU_MMX_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
792 CPU_3DNOWA_FLAGS
, 0, 1 },
793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
794 CPU_SSE_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
796 CPU_SSE2_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
798 CPU_SSE3_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
802 CPU_SSE4_1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
808 CPU_ANY_SSE_FLAGS
, 0, 1 },
809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
810 CPU_AVX_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
812 CPU_AVX2_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
814 CPU_AVX512F_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512CD_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512ER_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512PF_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
822 CPU_ANY_AVX_FLAGS
, 0, 1 },
823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
824 CPU_VMX_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
826 CPU_VMFUNC_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
828 CPU_SMX_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
830 CPU_XSAVE_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVEOPT_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
834 CPU_AES_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
836 CPU_PCLMUL_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 1, 0 },
839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
840 CPU_FSGSBASE_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
842 CPU_RDRND_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
844 CPU_F16C_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
846 CPU_BMI2_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
848 CPU_FMA_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
850 CPU_FMA4_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
852 CPU_XOP_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
854 CPU_LWP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
856 CPU_MOVBE_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
858 CPU_CX16_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
860 CPU_EPT_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
862 CPU_LZCNT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
864 CPU_HLE_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
866 CPU_RTM_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
868 CPU_INVPCID_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
870 CPU_CLFLUSH_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
872 CPU_NOP_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
874 CPU_SYSCALL_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
876 CPU_RDTSCP_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
878 CPU_3DNOW_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOWA_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
882 CPU_PADLOCK_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
884 CPU_SVME_FLAGS
, 1, 0 },
885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
888 CPU_SSE4A_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
890 CPU_ABM_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
892 CPU_BMI_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
894 CPU_TBM_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
896 CPU_ADX_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
898 CPU_RDSEED_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
900 CPU_PRFCHW_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
902 CPU_SMAP_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
904 CPU_MPX_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
906 CPU_SHA_FLAGS
, 0, 0 },
910 /* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
914 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
921 && *input_line_pointer
== ',')
923 align
= parse_align (needs_align
- 1);
925 if (align
== (addressT
) -1)
940 bss_alloc (symbolP
, size
, align
);
945 pe_lcomm (int needs_align
)
947 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
951 const pseudo_typeS md_pseudo_table
[] =
953 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes
, 0},
956 {"align", s_align_ptwo
, 0},
958 {"arch", set_cpu_arch
, 0},
962 {"lcomm", pe_lcomm
, 1},
964 {"ffloat", float_cons
, 'f'},
965 {"dfloat", float_cons
, 'd'},
966 {"tfloat", float_cons
, 'x'},
968 {"slong", signed_cons
, 4},
969 {"noopt", s_ignore
, 0},
970 {"optim", s_ignore
, 0},
971 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
972 {"code16", set_code_flag
, CODE_16BIT
},
973 {"code32", set_code_flag
, CODE_32BIT
},
974 {"code64", set_code_flag
, CODE_64BIT
},
975 {"intel_syntax", set_intel_syntax
, 1},
976 {"att_syntax", set_intel_syntax
, 0},
977 {"intel_mnemonic", set_intel_mnemonic
, 1},
978 {"att_mnemonic", set_intel_mnemonic
, 0},
979 {"allow_index_reg", set_allow_index_reg
, 1},
980 {"disallow_index_reg", set_allow_index_reg
, 0},
981 {"sse_check", set_check
, 0},
982 {"operand_check", set_check
, 1},
983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common
, 0},
986 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
987 {"loc", dwarf2_directive_loc
, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
991 {"secrel32", pe_directive_secrel
, 0},
996 /* For interface with expression (). */
997 extern char *input_line_pointer
;
999 /* Hash table for instruction mnemonic lookup. */
1000 static struct hash_control
*op_hash
;
1002 /* Hash table for register lookup. */
1003 static struct hash_control
*reg_hash
;
1006 i386_align_code (fragS
*fragP
, int count
)
1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
1011 static const char f32_1
[] =
1013 static const char f32_2
[] =
1014 {0x66,0x90}; /* xchg %ax,%ax */
1015 static const char f32_3
[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4
[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5
[] =
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6
[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7
[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8
[] =
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9
[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10
[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11
[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12
[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13
[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14
[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f16_3
[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1049 static const char f16_4
[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5
[] =
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6
[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7
[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8
[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1063 static const char jump_31
[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1068 static const char *const f32_patt
[] = {
1069 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1070 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1072 static const char *const f16_patt
[] = {
1073 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1075 /* nopl (%[re]ax) */
1076 static const char alt_3
[] =
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4
[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5
[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6
[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7
[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8
[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9
[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10
[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11
[] =
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12
[] =
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13
[] =
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14
[] =
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15
[] =
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11
[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12
[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1156 static const char alt_short_13
[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1161 static const char alt_short_14
[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15
[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt
[] = {
1170 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1171 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1172 alt_short_14
, alt_short_15
1174 static const char *const alt_long_patt
[] = {
1175 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1176 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1177 alt_long_14
, alt_long_15
1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1196 When -mtune= isn't used, alt_long_patt will be used if
1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1203 if (flag_code
== CODE_16BIT
)
1207 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1209 /* Adjust jump offset. */
1210 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1213 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1214 f16_patt
[count
- 1], count
);
1218 const char *const *patt
= NULL
;
1220 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune
)
1225 case PROCESSOR_UNKNOWN
:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
1227 optimize with nops. */
1228 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1229 patt
= alt_long_patt
;
1233 case PROCESSOR_PENTIUM4
:
1234 case PROCESSOR_NOCONA
:
1235 case PROCESSOR_CORE
:
1236 case PROCESSOR_CORE2
:
1237 case PROCESSOR_COREI7
:
1238 case PROCESSOR_L1OM
:
1239 case PROCESSOR_K1OM
:
1240 case PROCESSOR_GENERIC64
:
1241 patt
= alt_long_patt
;
1244 case PROCESSOR_ATHLON
:
1246 case PROCESSOR_AMDFAM10
:
1249 patt
= alt_short_patt
;
1251 case PROCESSOR_I386
:
1252 case PROCESSOR_I486
:
1253 case PROCESSOR_PENTIUM
:
1254 case PROCESSOR_PENTIUMPRO
:
1255 case PROCESSOR_GENERIC32
:
1262 switch (fragP
->tc_frag_data
.tune
)
1264 case PROCESSOR_UNKNOWN
:
1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1266 PROCESSOR_UNKNOWN. */
1270 case PROCESSOR_I386
:
1271 case PROCESSOR_I486
:
1272 case PROCESSOR_PENTIUM
:
1274 case PROCESSOR_ATHLON
:
1276 case PROCESSOR_AMDFAM10
:
1279 case PROCESSOR_GENERIC32
:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
1282 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1283 patt
= alt_short_patt
;
1287 case PROCESSOR_PENTIUMPRO
:
1288 case PROCESSOR_PENTIUM4
:
1289 case PROCESSOR_NOCONA
:
1290 case PROCESSOR_CORE
:
1291 case PROCESSOR_CORE2
:
1292 case PROCESSOR_COREI7
:
1293 case PROCESSOR_L1OM
:
1294 case PROCESSOR_K1OM
:
1295 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1296 patt
= alt_long_patt
;
1300 case PROCESSOR_GENERIC64
:
1301 patt
= alt_long_patt
;
1306 if (patt
== f32_patt
)
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code
== CODE_64BIT
1315 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1320 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1321 patt
[count
- 1], count
);
1324 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1326 /* Adjust jump offset. */
1327 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding
= count
;
1336 while (padding
> 15)
1339 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1344 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1345 patt
[padding
- 1], padding
);
1348 fragP
->fr_var
= count
;
1352 operand_type_all_zero (const union i386_operand_type
*x
)
1354 switch (ARRAY_SIZE(x
->array
))
1363 return !x
->array
[0];
1370 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1372 switch (ARRAY_SIZE(x
->array
))
1387 operand_type_equal (const union i386_operand_type
*x
,
1388 const union i386_operand_type
*y
)
1390 switch (ARRAY_SIZE(x
->array
))
1393 if (x
->array
[2] != y
->array
[2])
1396 if (x
->array
[1] != y
->array
[1])
1399 return x
->array
[0] == y
->array
[0];
1407 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1409 switch (ARRAY_SIZE(x
->array
))
1418 return !x
->array
[0];
1425 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1427 switch (ARRAY_SIZE(x
->array
))
1442 cpu_flags_equal (const union i386_cpu_flags
*x
,
1443 const union i386_cpu_flags
*y
)
1445 switch (ARRAY_SIZE(x
->array
))
1448 if (x
->array
[2] != y
->array
[2])
1451 if (x
->array
[1] != y
->array
[1])
1454 return x
->array
[0] == y
->array
[0];
1462 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1464 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1465 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1468 static INLINE i386_cpu_flags
1469 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1471 switch (ARRAY_SIZE (x
.array
))
1474 x
.array
[2] &= y
.array
[2];
1476 x
.array
[1] &= y
.array
[1];
1478 x
.array
[0] &= y
.array
[0];
1486 static INLINE i386_cpu_flags
1487 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1489 switch (ARRAY_SIZE (x
.array
))
1492 x
.array
[2] |= y
.array
[2];
1494 x
.array
[1] |= y
.array
[1];
1496 x
.array
[0] |= y
.array
[0];
1504 static INLINE i386_cpu_flags
1505 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1507 switch (ARRAY_SIZE (x
.array
))
1510 x
.array
[2] &= ~y
.array
[2];
1512 x
.array
[1] &= ~y
.array
[1];
1514 x
.array
[0] &= ~y
.array
[0];
1522 #define CPU_FLAGS_ARCH_MATCH 0x1
1523 #define CPU_FLAGS_64BIT_MATCH 0x2
1524 #define CPU_FLAGS_AES_MATCH 0x4
1525 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1526 #define CPU_FLAGS_AVX_MATCH 0x10
1528 #define CPU_FLAGS_32BIT_MATCH \
1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1531 #define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1534 /* Return CPU flags match bits. */
1537 cpu_flags_match (const insn_template
*t
)
1539 i386_cpu_flags x
= t
->cpu_flags
;
1540 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1542 x
.bitfield
.cpu64
= 0;
1543 x
.bitfield
.cpuno64
= 0;
1545 if (cpu_flags_all_zero (&x
))
1547 /* This instruction is available on all archs. */
1548 match
|= CPU_FLAGS_32BIT_MATCH
;
1552 /* This instruction is available only on some archs. */
1553 i386_cpu_flags cpu
= cpu_arch_flags
;
1555 cpu
.bitfield
.cpu64
= 0;
1556 cpu
.bitfield
.cpuno64
= 0;
1557 cpu
= cpu_flags_and (x
, cpu
);
1558 if (!cpu_flags_all_zero (&cpu
))
1560 if (x
.bitfield
.cpuavx
)
1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1563 if (cpu
.bitfield
.cpuavx
)
1565 /* Check SSE2AVX. */
1566 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1568 match
|= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH
);
1571 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1572 match
|= CPU_FLAGS_AES_MATCH
;
1574 if (!x
.bitfield
.cpupclmul
1575 || cpu
.bitfield
.cpupclmul
)
1576 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1580 match
|= CPU_FLAGS_ARCH_MATCH
;
1583 match
|= CPU_FLAGS_32BIT_MATCH
;
1589 static INLINE i386_operand_type
1590 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1592 switch (ARRAY_SIZE (x
.array
))
1595 x
.array
[2] &= y
.array
[2];
1597 x
.array
[1] &= y
.array
[1];
1599 x
.array
[0] &= y
.array
[0];
1607 static INLINE i386_operand_type
1608 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1610 switch (ARRAY_SIZE (x
.array
))
1613 x
.array
[2] |= y
.array
[2];
1615 x
.array
[1] |= y
.array
[1];
1617 x
.array
[0] |= y
.array
[0];
1625 static INLINE i386_operand_type
1626 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1628 switch (ARRAY_SIZE (x
.array
))
1631 x
.array
[2] ^= y
.array
[2];
1633 x
.array
[1] ^= y
.array
[1];
1635 x
.array
[0] ^= y
.array
[0];
1643 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1644 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1645 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1646 static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG
;
1648 static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1650 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1651 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1652 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1653 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1654 static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP
;
1656 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1657 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1658 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1659 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1660 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1661 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1662 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1663 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1664 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1665 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1666 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1667 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1668 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1669 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1680 operand_type_check (i386_operand_type t
, enum operand_type c
)
1685 return (t
.bitfield
.reg8
1688 || t
.bitfield
.reg64
);
1691 return (t
.bitfield
.imm8
1695 || t
.bitfield
.imm32s
1696 || t
.bitfield
.imm64
);
1699 return (t
.bitfield
.disp8
1700 || t
.bitfield
.disp16
1701 || t
.bitfield
.disp32
1702 || t
.bitfield
.disp32s
1703 || t
.bitfield
.disp64
);
1706 return (t
.bitfield
.disp8
1707 || t
.bitfield
.disp16
1708 || t
.bitfield
.disp32
1709 || t
.bitfield
.disp32s
1710 || t
.bitfield
.disp64
1711 || t
.bitfield
.baseindex
);
1720 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1721 operand J for instruction template T. */
1724 match_reg_size (const insn_template
*t
, unsigned int j
)
1726 return !((i
.types
[j
].bitfield
.byte
1727 && !t
->operand_types
[j
].bitfield
.byte
)
1728 || (i
.types
[j
].bitfield
.word
1729 && !t
->operand_types
[j
].bitfield
.word
)
1730 || (i
.types
[j
].bitfield
.dword
1731 && !t
->operand_types
[j
].bitfield
.dword
)
1732 || (i
.types
[j
].bitfield
.qword
1733 && !t
->operand_types
[j
].bitfield
.qword
));
1736 /* Return 1 if there is no conflict in any size on operand J for
1737 instruction template T. */
1740 match_mem_size (const insn_template
*t
, unsigned int j
)
1742 return (match_reg_size (t
, j
)
1743 && !((i
.types
[j
].bitfield
.unspecified
1744 && !t
->operand_types
[j
].bitfield
.unspecified
)
1745 || (i
.types
[j
].bitfield
.fword
1746 && !t
->operand_types
[j
].bitfield
.fword
)
1747 || (i
.types
[j
].bitfield
.tbyte
1748 && !t
->operand_types
[j
].bitfield
.tbyte
)
1749 || (i
.types
[j
].bitfield
.xmmword
1750 && !t
->operand_types
[j
].bitfield
.xmmword
)
1751 || (i
.types
[j
].bitfield
.ymmword
1752 && !t
->operand_types
[j
].bitfield
.ymmword
)
1753 || (i
.types
[j
].bitfield
.zmmword
1754 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1757 /* Return 1 if there is no size conflict on any operands for
1758 instruction template T. */
1761 operand_size_match (const insn_template
*t
)
1766 /* Don't check jump instructions. */
1767 if (t
->opcode_modifier
.jump
1768 || t
->opcode_modifier
.jumpbyte
1769 || t
->opcode_modifier
.jumpdword
1770 || t
->opcode_modifier
.jumpintersegment
)
1773 /* Check memory and accumulator operand size. */
1774 for (j
= 0; j
< i
.operands
; j
++)
1776 if (t
->operand_types
[j
].bitfield
.anysize
)
1779 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1785 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1794 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1797 i
.error
= operand_size_mismatch
;
1801 /* Check reverse. */
1802 gas_assert (i
.operands
== 2);
1805 for (j
= 0; j
< 2; j
++)
1807 if (t
->operand_types
[j
].bitfield
.acc
1808 && !match_reg_size (t
, j
? 0 : 1))
1811 if (i
.types
[j
].bitfield
.mem
1812 && !match_mem_size (t
, j
? 0 : 1))
1820 operand_type_match (i386_operand_type overlap
,
1821 i386_operand_type given
)
1823 i386_operand_type temp
= overlap
;
1825 temp
.bitfield
.jumpabsolute
= 0;
1826 temp
.bitfield
.unspecified
= 0;
1827 temp
.bitfield
.byte
= 0;
1828 temp
.bitfield
.word
= 0;
1829 temp
.bitfield
.dword
= 0;
1830 temp
.bitfield
.fword
= 0;
1831 temp
.bitfield
.qword
= 0;
1832 temp
.bitfield
.tbyte
= 0;
1833 temp
.bitfield
.xmmword
= 0;
1834 temp
.bitfield
.ymmword
= 0;
1835 temp
.bitfield
.zmmword
= 0;
1836 if (operand_type_all_zero (&temp
))
1839 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1840 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1844 i
.error
= operand_type_mismatch
;
1848 /* If given types g0 and g1 are registers they must be of the same type
1849 unless the expected operand type register overlap is null.
1850 Note that Acc in a template matches every size of reg. */
1853 operand_type_register_match (i386_operand_type m0
,
1854 i386_operand_type g0
,
1855 i386_operand_type t0
,
1856 i386_operand_type m1
,
1857 i386_operand_type g1
,
1858 i386_operand_type t1
)
1860 if (!operand_type_check (g0
, reg
))
1863 if (!operand_type_check (g1
, reg
))
1866 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1867 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1868 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1869 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1872 if (m0
.bitfield
.acc
)
1874 t0
.bitfield
.reg8
= 1;
1875 t0
.bitfield
.reg16
= 1;
1876 t0
.bitfield
.reg32
= 1;
1877 t0
.bitfield
.reg64
= 1;
1880 if (m1
.bitfield
.acc
)
1882 t1
.bitfield
.reg8
= 1;
1883 t1
.bitfield
.reg16
= 1;
1884 t1
.bitfield
.reg32
= 1;
1885 t1
.bitfield
.reg64
= 1;
1888 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1889 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1890 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1891 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1894 i
.error
= register_type_mismatch
;
1899 static INLINE
unsigned int
1900 register_number (const reg_entry
*r
)
1902 unsigned int nr
= r
->reg_num
;
1904 if (r
->reg_flags
& RegRex
)
1910 static INLINE
unsigned int
1911 mode_from_disp_size (i386_operand_type t
)
1913 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1915 else if (t
.bitfield
.disp16
1916 || t
.bitfield
.disp32
1917 || t
.bitfield
.disp32s
)
1924 fits_in_signed_byte (offsetT num
)
1926 return (num
>= -128) && (num
<= 127);
1930 fits_in_unsigned_byte (offsetT num
)
1932 return (num
& 0xff) == num
;
1936 fits_in_unsigned_word (offsetT num
)
1938 return (num
& 0xffff) == num
;
1942 fits_in_signed_word (offsetT num
)
1944 return (-32768 <= num
) && (num
<= 32767);
1948 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1953 return (!(((offsetT
) -1 << 31) & num
)
1954 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1956 } /* fits_in_signed_long() */
1959 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1964 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1966 } /* fits_in_unsigned_long() */
1969 fits_in_vec_disp8 (offsetT num
)
1971 int shift
= i
.memshift
;
1977 mask
= (1 << shift
) - 1;
1979 /* Return 0 if NUM isn't properly aligned. */
1983 /* Check if NUM will fit in 8bit after shift. */
1984 return fits_in_signed_byte (num
>> shift
);
1988 fits_in_imm4 (offsetT num
)
1990 return (num
& 0xf) == num
;
1993 static i386_operand_type
1994 smallest_imm_type (offsetT num
)
1996 i386_operand_type t
;
1998 operand_type_set (&t
, 0);
1999 t
.bitfield
.imm64
= 1;
2001 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2003 /* This code is disabled on the 486 because all the Imm1 forms
2004 in the opcode table are slower on the i486. They're the
2005 versions with the implicitly specified single-position
2006 displacement, which has another syntax if you really want to
2008 t
.bitfield
.imm1
= 1;
2009 t
.bitfield
.imm8
= 1;
2010 t
.bitfield
.imm8s
= 1;
2011 t
.bitfield
.imm16
= 1;
2012 t
.bitfield
.imm32
= 1;
2013 t
.bitfield
.imm32s
= 1;
2015 else if (fits_in_signed_byte (num
))
2017 t
.bitfield
.imm8
= 1;
2018 t
.bitfield
.imm8s
= 1;
2019 t
.bitfield
.imm16
= 1;
2020 t
.bitfield
.imm32
= 1;
2021 t
.bitfield
.imm32s
= 1;
2023 else if (fits_in_unsigned_byte (num
))
2025 t
.bitfield
.imm8
= 1;
2026 t
.bitfield
.imm16
= 1;
2027 t
.bitfield
.imm32
= 1;
2028 t
.bitfield
.imm32s
= 1;
2030 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2032 t
.bitfield
.imm16
= 1;
2033 t
.bitfield
.imm32
= 1;
2034 t
.bitfield
.imm32s
= 1;
2036 else if (fits_in_signed_long (num
))
2038 t
.bitfield
.imm32
= 1;
2039 t
.bitfield
.imm32s
= 1;
2041 else if (fits_in_unsigned_long (num
))
2042 t
.bitfield
.imm32
= 1;
2048 offset_in_range (offsetT val
, int size
)
2054 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2055 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2056 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2058 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2064 /* If BFD64, sign extend val for 32bit address mode. */
2065 if (flag_code
!= CODE_64BIT
2066 || i
.prefix
[ADDR_PREFIX
])
2067 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2068 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2071 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2073 char buf1
[40], buf2
[40];
2075 sprint_value (buf1
, val
);
2076 sprint_value (buf2
, val
& mask
);
2077 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2091 a. PREFIX_EXIST if attempting to add a prefix where one from the
2092 same class already exists.
2093 b. PREFIX_LOCK if lock prefix is added.
2094 c. PREFIX_REP if rep/repne prefix is added.
2095 d. PREFIX_OTHER if other prefix is added.
2098 static enum PREFIX_GROUP
2099 add_prefix (unsigned int prefix
)
2101 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2104 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2105 && flag_code
== CODE_64BIT
)
2107 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2108 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2109 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2120 case CS_PREFIX_OPCODE
:
2121 case DS_PREFIX_OPCODE
:
2122 case ES_PREFIX_OPCODE
:
2123 case FS_PREFIX_OPCODE
:
2124 case GS_PREFIX_OPCODE
:
2125 case SS_PREFIX_OPCODE
:
2129 case REPNE_PREFIX_OPCODE
:
2130 case REPE_PREFIX_OPCODE
:
2135 case LOCK_PREFIX_OPCODE
:
2144 case ADDR_PREFIX_OPCODE
:
2148 case DATA_PREFIX_OPCODE
:
2152 if (i
.prefix
[q
] != 0)
2160 i
.prefix
[q
] |= prefix
;
2163 as_bad (_("same type of prefix used twice"));
2169 update_code_flag (int value
, int check
)
2171 PRINTF_LIKE ((*as_error
));
2173 flag_code
= (enum flag_code
) value
;
2174 if (flag_code
== CODE_64BIT
)
2176 cpu_arch_flags
.bitfield
.cpu64
= 1;
2177 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2181 cpu_arch_flags
.bitfield
.cpu64
= 0;
2182 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2184 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2187 as_error
= as_fatal
;
2190 (*as_error
) (_("64bit mode not supported on `%s'."),
2191 cpu_arch_name
? cpu_arch_name
: default_arch
);
2193 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2196 as_error
= as_fatal
;
2199 (*as_error
) (_("32bit mode not supported on `%s'."),
2200 cpu_arch_name
? cpu_arch_name
: default_arch
);
2202 stackop_size
= '\0';
2206 set_code_flag (int value
)
2208 update_code_flag (value
, 0);
2212 set_16bit_gcc_code_flag (int new_code_flag
)
2214 flag_code
= (enum flag_code
) new_code_flag
;
2215 if (flag_code
!= CODE_16BIT
)
2217 cpu_arch_flags
.bitfield
.cpu64
= 0;
2218 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2219 stackop_size
= LONG_MNEM_SUFFIX
;
2223 set_intel_syntax (int syntax_flag
)
2225 /* Find out if register prefixing is specified. */
2226 int ask_naked_reg
= 0;
2229 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2231 char *string
= input_line_pointer
;
2232 int e
= get_symbol_end ();
2234 if (strcmp (string
, "prefix") == 0)
2236 else if (strcmp (string
, "noprefix") == 0)
2239 as_bad (_("bad argument to syntax directive."));
2240 *input_line_pointer
= e
;
2242 demand_empty_rest_of_line ();
2244 intel_syntax
= syntax_flag
;
2246 if (ask_naked_reg
== 0)
2247 allow_naked_reg
= (intel_syntax
2248 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2250 allow_naked_reg
= (ask_naked_reg
< 0);
2252 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2254 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2255 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2256 register_prefix
= allow_naked_reg
? "" : "%";
2260 set_intel_mnemonic (int mnemonic_flag
)
2262 intel_mnemonic
= mnemonic_flag
;
2266 set_allow_index_reg (int flag
)
2268 allow_index_reg
= flag
;
2272 set_check (int what
)
2274 enum check_kind
*kind
;
2279 kind
= &operand_check
;
2290 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2292 char *string
= input_line_pointer
;
2293 int e
= get_symbol_end ();
2295 if (strcmp (string
, "none") == 0)
2297 else if (strcmp (string
, "warning") == 0)
2298 *kind
= check_warning
;
2299 else if (strcmp (string
, "error") == 0)
2300 *kind
= check_error
;
2302 as_bad (_("bad argument to %s_check directive."), str
);
2303 *input_line_pointer
= e
;
2306 as_bad (_("missing argument for %s_check directive"), str
);
2308 demand_empty_rest_of_line ();
2312 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2313 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2316 static const char *arch
;
2318 /* Intel LIOM is only supported on ELF. */
2324 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2325 use default_arch. */
2326 arch
= cpu_arch_name
;
2328 arch
= default_arch
;
2331 /* If we are targeting Intel L1OM, we must enable it. */
2332 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2333 || new_flag
.bitfield
.cpul1om
)
2336 /* If we are targeting Intel K1OM, we must enable it. */
2337 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2338 || new_flag
.bitfield
.cpuk1om
)
2341 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2346 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2350 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2352 char *string
= input_line_pointer
;
2353 int e
= get_symbol_end ();
2355 i386_cpu_flags flags
;
2357 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2359 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2361 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2365 cpu_arch_name
= cpu_arch
[j
].name
;
2366 cpu_sub_arch_name
= NULL
;
2367 cpu_arch_flags
= cpu_arch
[j
].flags
;
2368 if (flag_code
== CODE_64BIT
)
2370 cpu_arch_flags
.bitfield
.cpu64
= 1;
2371 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2375 cpu_arch_flags
.bitfield
.cpu64
= 0;
2376 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2378 cpu_arch_isa
= cpu_arch
[j
].type
;
2379 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2380 if (!cpu_arch_tune_set
)
2382 cpu_arch_tune
= cpu_arch_isa
;
2383 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2388 if (!cpu_arch
[j
].negated
)
2389 flags
= cpu_flags_or (cpu_arch_flags
,
2392 flags
= cpu_flags_and_not (cpu_arch_flags
,
2394 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2396 if (cpu_sub_arch_name
)
2398 char *name
= cpu_sub_arch_name
;
2399 cpu_sub_arch_name
= concat (name
,
2401 (const char *) NULL
);
2405 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2406 cpu_arch_flags
= flags
;
2407 cpu_arch_isa_flags
= flags
;
2409 *input_line_pointer
= e
;
2410 demand_empty_rest_of_line ();
2414 if (j
>= ARRAY_SIZE (cpu_arch
))
2415 as_bad (_("no such architecture: `%s'"), string
);
2417 *input_line_pointer
= e
;
2420 as_bad (_("missing cpu architecture"));
2422 no_cond_jump_promotion
= 0;
2423 if (*input_line_pointer
== ','
2424 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2426 char *string
= ++input_line_pointer
;
2427 int e
= get_symbol_end ();
2429 if (strcmp (string
, "nojumps") == 0)
2430 no_cond_jump_promotion
= 1;
2431 else if (strcmp (string
, "jumps") == 0)
2434 as_bad (_("no such architecture modifier: `%s'"), string
);
2436 *input_line_pointer
= e
;
2439 demand_empty_rest_of_line ();
2442 enum bfd_architecture
2445 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2447 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2448 || flag_code
!= CODE_64BIT
)
2449 as_fatal (_("Intel L1OM is 64bit ELF only"));
2450 return bfd_arch_l1om
;
2452 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2455 || flag_code
!= CODE_64BIT
)
2456 as_fatal (_("Intel K1OM is 64bit ELF only"));
2457 return bfd_arch_k1om
;
2460 return bfd_arch_i386
;
2466 if (!strncmp (default_arch
, "x86_64", 6))
2468 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2470 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2471 || default_arch
[6] != '\0')
2472 as_fatal (_("Intel L1OM is 64bit ELF only"));
2473 return bfd_mach_l1om
;
2475 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2477 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2478 || default_arch
[6] != '\0')
2479 as_fatal (_("Intel K1OM is 64bit ELF only"));
2480 return bfd_mach_k1om
;
2482 else if (default_arch
[6] == '\0')
2483 return bfd_mach_x86_64
;
2485 return bfd_mach_x64_32
;
2487 else if (!strcmp (default_arch
, "i386"))
2488 return bfd_mach_i386_i386
;
2490 as_fatal (_("unknown architecture"));
2496 const char *hash_err
;
2498 /* Initialize op_hash hash table. */
2499 op_hash
= hash_new ();
2502 const insn_template
*optab
;
2503 templates
*core_optab
;
2505 /* Setup for loop. */
2507 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2508 core_optab
->start
= optab
;
2513 if (optab
->name
== NULL
2514 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2516 /* different name --> ship out current template list;
2517 add to hash table; & begin anew. */
2518 core_optab
->end
= optab
;
2519 hash_err
= hash_insert (op_hash
,
2521 (void *) core_optab
);
2524 as_fatal (_("can't hash %s: %s"),
2528 if (optab
->name
== NULL
)
2530 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2531 core_optab
->start
= optab
;
2536 /* Initialize reg_hash hash table. */
2537 reg_hash
= hash_new ();
2539 const reg_entry
*regtab
;
2540 unsigned int regtab_size
= i386_regtab_size
;
2542 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2544 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2546 as_fatal (_("can't hash %s: %s"),
2552 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2557 for (c
= 0; c
< 256; c
++)
2562 mnemonic_chars
[c
] = c
;
2563 register_chars
[c
] = c
;
2564 operand_chars
[c
] = c
;
2566 else if (ISLOWER (c
))
2568 mnemonic_chars
[c
] = c
;
2569 register_chars
[c
] = c
;
2570 operand_chars
[c
] = c
;
2572 else if (ISUPPER (c
))
2574 mnemonic_chars
[c
] = TOLOWER (c
);
2575 register_chars
[c
] = mnemonic_chars
[c
];
2576 operand_chars
[c
] = c
;
2578 else if (c
== '{' || c
== '}')
2579 operand_chars
[c
] = c
;
2581 if (ISALPHA (c
) || ISDIGIT (c
))
2582 identifier_chars
[c
] = c
;
2585 identifier_chars
[c
] = c
;
2586 operand_chars
[c
] = c
;
2591 identifier_chars
['@'] = '@';
2594 identifier_chars
['?'] = '?';
2595 operand_chars
['?'] = '?';
2597 digit_chars
['-'] = '-';
2598 mnemonic_chars
['_'] = '_';
2599 mnemonic_chars
['-'] = '-';
2600 mnemonic_chars
['.'] = '.';
2601 identifier_chars
['_'] = '_';
2602 identifier_chars
['.'] = '.';
2604 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2605 operand_chars
[(unsigned char) *p
] = *p
;
2608 if (flag_code
== CODE_64BIT
)
2610 #if defined (OBJ_COFF) && defined (TE_PE)
2611 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2614 x86_dwarf2_return_column
= 16;
2616 x86_cie_data_alignment
= -8;
2620 x86_dwarf2_return_column
= 8;
2621 x86_cie_data_alignment
= -4;
2626 i386_print_statistics (FILE *file
)
2628 hash_print_statistics (file
, "i386 opcode", op_hash
);
2629 hash_print_statistics (file
, "i386 register", reg_hash
);
2634 /* Debugging routines for md_assemble. */
2635 static void pte (insn_template
*);
2636 static void pt (i386_operand_type
);
2637 static void pe (expressionS
*);
2638 static void ps (symbolS
*);
2641 pi (char *line
, i386_insn
*x
)
2645 fprintf (stdout
, "%s: template ", line
);
2647 fprintf (stdout
, " address: base %s index %s scale %x\n",
2648 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2649 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2650 x
->log2_scale_factor
);
2651 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2652 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2653 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2654 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2655 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2656 (x
->rex
& REX_W
) != 0,
2657 (x
->rex
& REX_R
) != 0,
2658 (x
->rex
& REX_X
) != 0,
2659 (x
->rex
& REX_B
) != 0);
2660 for (j
= 0; j
< x
->operands
; j
++)
2662 fprintf (stdout
, " #%d: ", j
+ 1);
2664 fprintf (stdout
, "\n");
2665 if (x
->types
[j
].bitfield
.reg8
2666 || x
->types
[j
].bitfield
.reg16
2667 || x
->types
[j
].bitfield
.reg32
2668 || x
->types
[j
].bitfield
.reg64
2669 || x
->types
[j
].bitfield
.regmmx
2670 || x
->types
[j
].bitfield
.regxmm
2671 || x
->types
[j
].bitfield
.regymm
2672 || x
->types
[j
].bitfield
.regzmm
2673 || x
->types
[j
].bitfield
.sreg2
2674 || x
->types
[j
].bitfield
.sreg3
2675 || x
->types
[j
].bitfield
.control
2676 || x
->types
[j
].bitfield
.debug
2677 || x
->types
[j
].bitfield
.test
)
2678 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2679 if (operand_type_check (x
->types
[j
], imm
))
2681 if (operand_type_check (x
->types
[j
], disp
))
2682 pe (x
->op
[j
].disps
);
2687 pte (insn_template
*t
)
2690 fprintf (stdout
, " %d operands ", t
->operands
);
2691 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2692 if (t
->extension_opcode
!= None
)
2693 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2694 if (t
->opcode_modifier
.d
)
2695 fprintf (stdout
, "D");
2696 if (t
->opcode_modifier
.w
)
2697 fprintf (stdout
, "W");
2698 fprintf (stdout
, "\n");
2699 for (j
= 0; j
< t
->operands
; j
++)
2701 fprintf (stdout
, " #%d type ", j
+ 1);
2702 pt (t
->operand_types
[j
]);
2703 fprintf (stdout
, "\n");
2710 fprintf (stdout
, " operation %d\n", e
->X_op
);
2711 fprintf (stdout
, " add_number %ld (%lx)\n",
2712 (long) e
->X_add_number
, (long) e
->X_add_number
);
2713 if (e
->X_add_symbol
)
2715 fprintf (stdout
, " add_symbol ");
2716 ps (e
->X_add_symbol
);
2717 fprintf (stdout
, "\n");
2721 fprintf (stdout
, " op_symbol ");
2722 ps (e
->X_op_symbol
);
2723 fprintf (stdout
, "\n");
2730 fprintf (stdout
, "%s type %s%s",
2732 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2733 segment_name (S_GET_SEGMENT (s
)));
2736 static struct type_name
2738 i386_operand_type mask
;
2741 const type_names
[] =
2743 { OPERAND_TYPE_REG8
, "r8" },
2744 { OPERAND_TYPE_REG16
, "r16" },
2745 { OPERAND_TYPE_REG32
, "r32" },
2746 { OPERAND_TYPE_REG64
, "r64" },
2747 { OPERAND_TYPE_IMM8
, "i8" },
2748 { OPERAND_TYPE_IMM8
, "i8s" },
2749 { OPERAND_TYPE_IMM16
, "i16" },
2750 { OPERAND_TYPE_IMM32
, "i32" },
2751 { OPERAND_TYPE_IMM32S
, "i32s" },
2752 { OPERAND_TYPE_IMM64
, "i64" },
2753 { OPERAND_TYPE_IMM1
, "i1" },
2754 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2755 { OPERAND_TYPE_DISP8
, "d8" },
2756 { OPERAND_TYPE_DISP16
, "d16" },
2757 { OPERAND_TYPE_DISP32
, "d32" },
2758 { OPERAND_TYPE_DISP32S
, "d32s" },
2759 { OPERAND_TYPE_DISP64
, "d64" },
2760 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2761 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2762 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2763 { OPERAND_TYPE_CONTROL
, "control reg" },
2764 { OPERAND_TYPE_TEST
, "test reg" },
2765 { OPERAND_TYPE_DEBUG
, "debug reg" },
2766 { OPERAND_TYPE_FLOATREG
, "FReg" },
2767 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2768 { OPERAND_TYPE_SREG2
, "SReg2" },
2769 { OPERAND_TYPE_SREG3
, "SReg3" },
2770 { OPERAND_TYPE_ACC
, "Acc" },
2771 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2772 { OPERAND_TYPE_REGMMX
, "rMMX" },
2773 { OPERAND_TYPE_REGXMM
, "rXMM" },
2774 { OPERAND_TYPE_REGYMM
, "rYMM" },
2775 { OPERAND_TYPE_REGZMM
, "rZMM" },
2776 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2777 { OPERAND_TYPE_ESSEG
, "es" },
2781 pt (i386_operand_type t
)
2784 i386_operand_type a
;
2786 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2788 a
= operand_type_and (t
, type_names
[j
].mask
);
2789 if (!operand_type_all_zero (&a
))
2790 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2795 #endif /* DEBUG386 */
2797 static bfd_reloc_code_real_type
2798 reloc (unsigned int size
,
2802 bfd_reloc_code_real_type other
)
2804 if (other
!= NO_RELOC
)
2806 reloc_howto_type
*rel
;
2811 case BFD_RELOC_X86_64_GOT32
:
2812 return BFD_RELOC_X86_64_GOT64
;
2814 case BFD_RELOC_X86_64_PLTOFF64
:
2815 return BFD_RELOC_X86_64_PLTOFF64
;
2817 case BFD_RELOC_X86_64_GOTPC32
:
2818 other
= BFD_RELOC_X86_64_GOTPC64
;
2820 case BFD_RELOC_X86_64_GOTPCREL
:
2821 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2823 case BFD_RELOC_X86_64_TPOFF32
:
2824 other
= BFD_RELOC_X86_64_TPOFF64
;
2826 case BFD_RELOC_X86_64_DTPOFF32
:
2827 other
= BFD_RELOC_X86_64_DTPOFF64
;
2833 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2834 if (other
== BFD_RELOC_SIZE32
)
2837 return BFD_RELOC_SIZE64
;
2839 as_bad (_("there are no pc-relative size relocations"));
2843 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2844 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2847 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2849 as_bad (_("unknown relocation (%u)"), other
);
2850 else if (size
!= bfd_get_reloc_size (rel
))
2851 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2852 bfd_get_reloc_size (rel
),
2854 else if (pcrel
&& !rel
->pc_relative
)
2855 as_bad (_("non-pc-relative relocation for pc-relative field"));
2856 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2858 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2860 as_bad (_("relocated field and relocation type differ in signedness"));
2869 as_bad (_("there are no unsigned pc-relative relocations"));
2872 case 1: return BFD_RELOC_8_PCREL
;
2873 case 2: return BFD_RELOC_16_PCREL
;
2874 case 4: return (bnd_prefix
&& object_64bit
2875 ? BFD_RELOC_X86_64_PC32_BND
2876 : BFD_RELOC_32_PCREL
);
2877 case 8: return BFD_RELOC_64_PCREL
;
2879 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2886 case 4: return BFD_RELOC_X86_64_32S
;
2891 case 1: return BFD_RELOC_8
;
2892 case 2: return BFD_RELOC_16
;
2893 case 4: return BFD_RELOC_32
;
2894 case 8: return BFD_RELOC_64
;
2896 as_bad (_("cannot do %s %u byte relocation"),
2897 sign
> 0 ? "signed" : "unsigned", size
);
2903 /* Here we decide which fixups can be adjusted to make them relative to
2904 the beginning of the section instead of the symbol. Basically we need
2905 to make sure that the dynamic relocations are done correctly, so in
2906 some cases we force the original symbol to be used. */
2909 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2915 /* Don't adjust pc-relative references to merge sections in 64-bit
2917 if (use_rela_relocations
2918 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2922 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2923 and changed later by validate_fix. */
2924 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2925 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2928 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2929 for size relocations. */
2930 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2931 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2932 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2933 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2934 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2958 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2959 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2966 intel_float_operand (const char *mnemonic
)
2968 /* Note that the value returned is meaningful only for opcodes with (memory)
2969 operands, hence the code here is free to improperly handle opcodes that
2970 have no operands (for better performance and smaller code). */
2972 if (mnemonic
[0] != 'f')
2973 return 0; /* non-math */
2975 switch (mnemonic
[1])
2977 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2978 the fs segment override prefix not currently handled because no
2979 call path can make opcodes without operands get here */
2981 return 2 /* integer op */;
2983 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2984 return 3; /* fldcw/fldenv */
2987 if (mnemonic
[2] != 'o' /* fnop */)
2988 return 3; /* non-waiting control op */
2991 if (mnemonic
[2] == 's')
2992 return 3; /* frstor/frstpm */
2995 if (mnemonic
[2] == 'a')
2996 return 3; /* fsave */
2997 if (mnemonic
[2] == 't')
2999 switch (mnemonic
[3])
3001 case 'c': /* fstcw */
3002 case 'd': /* fstdw */
3003 case 'e': /* fstenv */
3004 case 's': /* fsts[gw] */
3010 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3011 return 0; /* fxsave/fxrstor are not really math ops */
3018 /* Build the VEX prefix. */
3021 build_vex_prefix (const insn_template
*t
)
3023 unsigned int register_specifier
;
3024 unsigned int implied_prefix
;
3025 unsigned int vector_length
;
3027 /* Check register specifier. */
3028 if (i
.vex
.register_specifier
)
3030 register_specifier
=
3031 ~register_number (i
.vex
.register_specifier
) & 0xf;
3032 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3035 register_specifier
= 0xf;
3037 /* Use 2-byte VEX prefix by swappping destination and source
3040 && i
.operands
== i
.reg_operands
3041 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3042 && i
.tm
.opcode_modifier
.s
3045 unsigned int xchg
= i
.operands
- 1;
3046 union i386_op temp_op
;
3047 i386_operand_type temp_type
;
3049 temp_type
= i
.types
[xchg
];
3050 i
.types
[xchg
] = i
.types
[0];
3051 i
.types
[0] = temp_type
;
3052 temp_op
= i
.op
[xchg
];
3053 i
.op
[xchg
] = i
.op
[0];
3056 gas_assert (i
.rm
.mode
== 3);
3060 i
.rm
.regmem
= i
.rm
.reg
;
3063 /* Use the next insn. */
3067 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3068 vector_length
= avxscalar
;
3070 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3072 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3077 case DATA_PREFIX_OPCODE
:
3080 case REPE_PREFIX_OPCODE
:
3083 case REPNE_PREFIX_OPCODE
:
3090 /* Use 2-byte VEX prefix if possible. */
3091 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3092 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3093 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3095 /* 2-byte VEX prefix. */
3099 i
.vex
.bytes
[0] = 0xc5;
3101 /* Check the REX.R bit. */
3102 r
= (i
.rex
& REX_R
) ? 0 : 1;
3103 i
.vex
.bytes
[1] = (r
<< 7
3104 | register_specifier
<< 3
3105 | vector_length
<< 2
3110 /* 3-byte VEX prefix. */
3115 switch (i
.tm
.opcode_modifier
.vexopcode
)
3119 i
.vex
.bytes
[0] = 0xc4;
3123 i
.vex
.bytes
[0] = 0xc4;
3127 i
.vex
.bytes
[0] = 0xc4;
3131 i
.vex
.bytes
[0] = 0x8f;
3135 i
.vex
.bytes
[0] = 0x8f;
3139 i
.vex
.bytes
[0] = 0x8f;
3145 /* The high 3 bits of the second VEX byte are 1's compliment
3146 of RXB bits from REX. */
3147 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3149 /* Check the REX.W bit. */
3150 w
= (i
.rex
& REX_W
) ? 1 : 0;
3151 if (i
.tm
.opcode_modifier
.vexw
)
3156 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3160 i
.vex
.bytes
[2] = (w
<< 7
3161 | register_specifier
<< 3
3162 | vector_length
<< 2
3167 /* Build the EVEX prefix. */
3170 build_evex_prefix (void)
3172 unsigned int register_specifier
;
3173 unsigned int implied_prefix
;
3175 rex_byte vrex_used
= 0;
3177 /* Check register specifier. */
3178 if (i
.vex
.register_specifier
)
3180 gas_assert ((i
.vrex
& REX_X
) == 0);
3182 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3183 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3184 register_specifier
+= 8;
3185 /* The upper 16 registers are encoded in the fourth byte of the
3187 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3188 i
.vex
.bytes
[3] = 0x8;
3189 register_specifier
= ~register_specifier
& 0xf;
3193 register_specifier
= 0xf;
3195 /* Encode upper 16 vector index register in the fourth byte of
3197 if (!(i
.vrex
& REX_X
))
3198 i
.vex
.bytes
[3] = 0x8;
3203 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3208 case DATA_PREFIX_OPCODE
:
3211 case REPE_PREFIX_OPCODE
:
3214 case REPNE_PREFIX_OPCODE
:
3221 /* 4 byte EVEX prefix. */
3223 i
.vex
.bytes
[0] = 0x62;
3226 switch (i
.tm
.opcode_modifier
.vexopcode
)
3242 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3244 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3246 /* The fifth bit of the second EVEX byte is 1's compliment of the
3247 REX_R bit in VREX. */
3248 if (!(i
.vrex
& REX_R
))
3249 i
.vex
.bytes
[1] |= 0x10;
3253 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3255 /* When all operands are registers, the REX_X bit in REX is not
3256 used. We reuse it to encode the upper 16 registers, which is
3257 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3258 as 1's compliment. */
3259 if ((i
.vrex
& REX_B
))
3262 i
.vex
.bytes
[1] &= ~0x40;
3266 /* EVEX instructions shouldn't need the REX prefix. */
3267 i
.vrex
&= ~vrex_used
;
3268 gas_assert (i
.vrex
== 0);
3270 /* Check the REX.W bit. */
3271 w
= (i
.rex
& REX_W
) ? 1 : 0;
3272 if (i
.tm
.opcode_modifier
.vexw
)
3274 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3277 /* If w is not set it means we are dealing with WIG instruction. */
3280 if (evexwig
== evexw1
)
3284 /* Encode the U bit. */
3285 implied_prefix
|= 0x4;
3287 /* The third byte of the EVEX prefix. */
3288 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3290 /* The fourth byte of the EVEX prefix. */
3291 /* The zeroing-masking bit. */
3292 if (i
.mask
&& i
.mask
->zeroing
)
3293 i
.vex
.bytes
[3] |= 0x80;
3295 /* Don't always set the broadcast bit if there is no RC. */
3298 /* Encode the vector length. */
3299 unsigned int vec_length
;
3301 switch (i
.tm
.opcode_modifier
.evex
)
3303 case EVEXLIG
: /* LL' is ignored */
3304 vec_length
= evexlig
<< 5;
3307 vec_length
= 0 << 5;
3310 vec_length
= 1 << 5;
3313 vec_length
= 2 << 5;
3319 i
.vex
.bytes
[3] |= vec_length
;
3320 /* Encode the broadcast bit. */
3322 i
.vex
.bytes
[3] |= 0x10;
3326 if (i
.rounding
->type
!= saeonly
)
3327 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3329 i
.vex
.bytes
[3] |= 0x10;
3332 if (i
.mask
&& i
.mask
->mask
)
3333 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3337 process_immext (void)
3341 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3344 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3345 with an opcode suffix which is coded in the same place as an
3346 8-bit immediate field would be.
3347 Here we check those operands and remove them afterwards. */
3350 for (x
= 0; x
< i
.operands
; x
++)
3351 if (register_number (i
.op
[x
].regs
) != x
)
3352 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3353 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3359 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3360 which is coded in the same place as an 8-bit immediate field
3361 would be. Here we fake an 8-bit immediate operand from the
3362 opcode suffix stored in tm.extension_opcode.
3364 AVX instructions also use this encoding, for some of
3365 3 argument instructions. */
3367 gas_assert (i
.imm_operands
<= 1
3369 || ((i
.tm
.opcode_modifier
.vex
3370 || i
.tm
.opcode_modifier
.evex
)
3371 && i
.operands
<= 4)));
3373 exp
= &im_expressions
[i
.imm_operands
++];
3374 i
.op
[i
.operands
].imms
= exp
;
3375 i
.types
[i
.operands
] = imm8
;
3377 exp
->X_op
= O_constant
;
3378 exp
->X_add_number
= i
.tm
.extension_opcode
;
3379 i
.tm
.extension_opcode
= None
;
3386 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3391 as_bad (_("invalid instruction `%s' after `%s'"),
3392 i
.tm
.name
, i
.hle_prefix
);
3395 if (i
.prefix
[LOCK_PREFIX
])
3397 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3401 case HLEPrefixRelease
:
3402 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3404 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3408 if (i
.mem_operands
== 0
3409 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3411 as_bad (_("memory destination needed for instruction `%s'"
3412 " after `xrelease'"), i
.tm
.name
);
3419 /* This is the guts of the machine-dependent assembler. LINE points to a
3420 machine dependent instruction. This function is supposed to emit
3421 the frags/bytes it assembles to. */
3424 md_assemble (char *line
)
3427 char mnemonic
[MAX_MNEM_SIZE
];
3428 const insn_template
*t
;
3430 /* Initialize globals. */
3431 memset (&i
, '\0', sizeof (i
));
3432 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3433 i
.reloc
[j
] = NO_RELOC
;
3434 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3435 memset (im_expressions
, '\0', sizeof (im_expressions
));
3436 save_stack_p
= save_stack
;
3438 /* First parse an instruction mnemonic & call i386_operand for the operands.
3439 We assume that the scrubber has arranged it so that line[0] is the valid
3440 start of a (possibly prefixed) mnemonic. */
3442 line
= parse_insn (line
, mnemonic
);
3446 line
= parse_operands (line
, mnemonic
);
3451 /* Now we've parsed the mnemonic into a set of templates, and have the
3452 operands at hand. */
3454 /* All intel opcodes have reversed operands except for "bound" and
3455 "enter". We also don't reverse intersegment "jmp" and "call"
3456 instructions with 2 immediate operands so that the immediate segment
3457 precedes the offset, as it does when in AT&T mode. */
3460 && (strcmp (mnemonic
, "bound") != 0)
3461 && (strcmp (mnemonic
, "invlpga") != 0)
3462 && !(operand_type_check (i
.types
[0], imm
)
3463 && operand_type_check (i
.types
[1], imm
)))
3466 /* The order of the immediates should be reversed
3467 for 2 immediates extrq and insertq instructions */
3468 if (i
.imm_operands
== 2
3469 && (strcmp (mnemonic
, "extrq") == 0
3470 || strcmp (mnemonic
, "insertq") == 0))
3471 swap_2_operands (0, 1);
3476 /* Don't optimize displacement for movabs since it only takes 64bit
3479 && i
.disp_encoding
!= disp_encoding_32bit
3480 && (flag_code
!= CODE_64BIT
3481 || strcmp (mnemonic
, "movabs") != 0))
3484 /* Next, we find a template that matches the given insn,
3485 making sure the overlap of the given operands types is consistent
3486 with the template operand types. */
3488 if (!(t
= match_template ()))
3491 if (sse_check
!= check_none
3492 && !i
.tm
.opcode_modifier
.noavx
3493 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3494 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3495 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3496 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3497 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3498 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3500 (sse_check
== check_warning
3502 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3505 /* Zap movzx and movsx suffix. The suffix has been set from
3506 "word ptr" or "byte ptr" on the source operand in Intel syntax
3507 or extracted from mnemonic in AT&T syntax. But we'll use
3508 the destination register to choose the suffix for encoding. */
3509 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3511 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3512 there is no suffix, the default will be byte extension. */
3513 if (i
.reg_operands
!= 2
3516 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3521 if (i
.tm
.opcode_modifier
.fwait
)
3522 if (!add_prefix (FWAIT_OPCODE
))
3525 /* Check if REP prefix is OK. */
3526 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3528 as_bad (_("invalid instruction `%s' after `%s'"),
3529 i
.tm
.name
, i
.rep_prefix
);
3533 /* Check for lock without a lockable instruction. Destination operand
3534 must be memory unless it is xchg (0x86). */
3535 if (i
.prefix
[LOCK_PREFIX
]
3536 && (!i
.tm
.opcode_modifier
.islockable
3537 || i
.mem_operands
== 0
3538 || (i
.tm
.base_opcode
!= 0x86
3539 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3541 as_bad (_("expecting lockable instruction after `lock'"));
3545 /* Check if HLE prefix is OK. */
3546 if (i
.hle_prefix
&& !check_hle ())
3549 /* Check BND prefix. */
3550 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3551 as_bad (_("expecting valid branch instruction after `bnd'"));
3553 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3554 && flag_code
== CODE_64BIT
3555 && i
.prefix
[ADDR_PREFIX
])
3556 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3558 /* Insert BND prefix. */
3560 && i
.tm
.opcode_modifier
.bndprefixok
3561 && !i
.prefix
[BND_PREFIX
])
3562 add_prefix (BND_PREFIX_OPCODE
);
3564 /* Check string instruction segment overrides. */
3565 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3567 if (!check_string ())
3569 i
.disp_operands
= 0;
3572 if (!process_suffix ())
3575 /* Update operand types. */
3576 for (j
= 0; j
< i
.operands
; j
++)
3577 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3579 /* Make still unresolved immediate matches conform to size of immediate
3580 given in i.suffix. */
3581 if (!finalize_imm ())
3584 if (i
.types
[0].bitfield
.imm1
)
3585 i
.imm_operands
= 0; /* kludge for shift insns. */
3587 /* We only need to check those implicit registers for instructions
3588 with 3 operands or less. */
3589 if (i
.operands
<= 3)
3590 for (j
= 0; j
< i
.operands
; j
++)
3591 if (i
.types
[j
].bitfield
.inoutportreg
3592 || i
.types
[j
].bitfield
.shiftcount
3593 || i
.types
[j
].bitfield
.acc
3594 || i
.types
[j
].bitfield
.floatacc
)
3597 /* ImmExt should be processed after SSE2AVX. */
3598 if (!i
.tm
.opcode_modifier
.sse2avx
3599 && i
.tm
.opcode_modifier
.immext
)
3602 /* For insns with operands there are more diddles to do to the opcode. */
3605 if (!process_operands ())
3608 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3610 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3611 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3614 if (i
.tm
.opcode_modifier
.vex
)
3615 build_vex_prefix (t
);
3617 if (i
.tm
.opcode_modifier
.evex
)
3618 build_evex_prefix ();
3620 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3621 instructions may define INT_OPCODE as well, so avoid this corner
3622 case for those instructions that use MODRM. */
3623 if (i
.tm
.base_opcode
== INT_OPCODE
3624 && !i
.tm
.opcode_modifier
.modrm
3625 && i
.op
[0].imms
->X_add_number
== 3)
3627 i
.tm
.base_opcode
= INT3_OPCODE
;
3631 if ((i
.tm
.opcode_modifier
.jump
3632 || i
.tm
.opcode_modifier
.jumpbyte
3633 || i
.tm
.opcode_modifier
.jumpdword
)
3634 && i
.op
[0].disps
->X_op
== O_constant
)
3636 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3637 the absolute address given by the constant. Since ix86 jumps and
3638 calls are pc relative, we need to generate a reloc. */
3639 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3640 i
.op
[0].disps
->X_op
= O_symbol
;
3643 if (i
.tm
.opcode_modifier
.rex64
)
3646 /* For 8 bit registers we need an empty rex prefix. Also if the
3647 instruction already has a prefix, we need to convert old
3648 registers to new ones. */
3650 if ((i
.types
[0].bitfield
.reg8
3651 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3652 || (i
.types
[1].bitfield
.reg8
3653 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3654 || ((i
.types
[0].bitfield
.reg8
3655 || i
.types
[1].bitfield
.reg8
)
3660 i
.rex
|= REX_OPCODE
;
3661 for (x
= 0; x
< 2; x
++)
3663 /* Look for 8 bit operand that uses old registers. */
3664 if (i
.types
[x
].bitfield
.reg8
3665 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3667 /* In case it is "hi" register, give up. */
3668 if (i
.op
[x
].regs
->reg_num
> 3)
3669 as_bad (_("can't encode register '%s%s' in an "
3670 "instruction requiring REX prefix."),
3671 register_prefix
, i
.op
[x
].regs
->reg_name
);
3673 /* Otherwise it is equivalent to the extended register.
3674 Since the encoding doesn't change this is merely
3675 cosmetic cleanup for debug output. */
3677 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3683 add_prefix (REX_OPCODE
| i
.rex
);
3685 /* We are ready to output the insn. */
3690 parse_insn (char *line
, char *mnemonic
)
3693 char *token_start
= l
;
3696 const insn_template
*t
;
3702 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3707 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3709 as_bad (_("no such instruction: `%s'"), token_start
);
3714 if (!is_space_char (*l
)
3715 && *l
!= END_OF_INSN
3717 || (*l
!= PREFIX_SEPARATOR
3720 as_bad (_("invalid character %s in mnemonic"),
3721 output_invalid (*l
));
3724 if (token_start
== l
)
3726 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3727 as_bad (_("expecting prefix; got nothing"));
3729 as_bad (_("expecting mnemonic; got nothing"));
3733 /* Look up instruction (or prefix) via hash table. */
3734 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3736 if (*l
!= END_OF_INSN
3737 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3738 && current_templates
3739 && current_templates
->start
->opcode_modifier
.isprefix
)
3741 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3743 as_bad ((flag_code
!= CODE_64BIT
3744 ? _("`%s' is only supported in 64-bit mode")
3745 : _("`%s' is not supported in 64-bit mode")),
3746 current_templates
->start
->name
);
3749 /* If we are in 16-bit mode, do not allow addr16 or data16.
3750 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3751 if ((current_templates
->start
->opcode_modifier
.size16
3752 || current_templates
->start
->opcode_modifier
.size32
)
3753 && flag_code
!= CODE_64BIT
3754 && (current_templates
->start
->opcode_modifier
.size32
3755 ^ (flag_code
== CODE_16BIT
)))
3757 as_bad (_("redundant %s prefix"),
3758 current_templates
->start
->name
);
3761 /* Add prefix, checking for repeated prefixes. */
3762 switch (add_prefix (current_templates
->start
->base_opcode
))
3767 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3768 i
.hle_prefix
= current_templates
->start
->name
;
3769 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3770 i
.bnd_prefix
= current_templates
->start
->name
;
3772 i
.rep_prefix
= current_templates
->start
->name
;
3777 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3784 if (!current_templates
)
3786 /* Check if we should swap operand or force 32bit displacement in
3788 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3790 else if (mnem_p
- 3 == dot_p
3793 i
.disp_encoding
= disp_encoding_8bit
;
3794 else if (mnem_p
- 4 == dot_p
3798 i
.disp_encoding
= disp_encoding_32bit
;
3803 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3806 if (!current_templates
)
3809 /* See if we can get a match by trimming off a suffix. */
3812 case WORD_MNEM_SUFFIX
:
3813 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3814 i
.suffix
= SHORT_MNEM_SUFFIX
;
3816 case BYTE_MNEM_SUFFIX
:
3817 case QWORD_MNEM_SUFFIX
:
3818 i
.suffix
= mnem_p
[-1];
3820 current_templates
= (const templates
*) hash_find (op_hash
,
3823 case SHORT_MNEM_SUFFIX
:
3824 case LONG_MNEM_SUFFIX
:
3827 i
.suffix
= mnem_p
[-1];
3829 current_templates
= (const templates
*) hash_find (op_hash
,
3838 if (intel_float_operand (mnemonic
) == 1)
3839 i
.suffix
= SHORT_MNEM_SUFFIX
;
3841 i
.suffix
= LONG_MNEM_SUFFIX
;
3843 current_templates
= (const templates
*) hash_find (op_hash
,
3848 if (!current_templates
)
3850 as_bad (_("no such instruction: `%s'"), token_start
);
3855 if (current_templates
->start
->opcode_modifier
.jump
3856 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3858 /* Check for a branch hint. We allow ",pt" and ",pn" for
3859 predict taken and predict not taken respectively.
3860 I'm not sure that branch hints actually do anything on loop
3861 and jcxz insns (JumpByte) for current Pentium4 chips. They
3862 may work in the future and it doesn't hurt to accept them
3864 if (l
[0] == ',' && l
[1] == 'p')
3868 if (!add_prefix (DS_PREFIX_OPCODE
))
3872 else if (l
[2] == 'n')
3874 if (!add_prefix (CS_PREFIX_OPCODE
))
3880 /* Any other comma loses. */
3883 as_bad (_("invalid character %s in mnemonic"),
3884 output_invalid (*l
));
3888 /* Check if instruction is supported on specified architecture. */
3890 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3892 supported
|= cpu_flags_match (t
);
3893 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3897 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3899 as_bad (flag_code
== CODE_64BIT
3900 ? _("`%s' is not supported in 64-bit mode")
3901 : _("`%s' is only supported in 64-bit mode"),
3902 current_templates
->start
->name
);
3905 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3907 as_bad (_("`%s' is not supported on `%s%s'"),
3908 current_templates
->start
->name
,
3909 cpu_arch_name
? cpu_arch_name
: default_arch
,
3910 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3915 if (!cpu_arch_flags
.bitfield
.cpui386
3916 && (flag_code
!= CODE_16BIT
))
3918 as_warn (_("use .code16 to ensure correct addressing mode"));
3925 parse_operands (char *l
, const char *mnemonic
)
3929 /* 1 if operand is pending after ','. */
3930 unsigned int expecting_operand
= 0;
3932 /* Non-zero if operand parens not balanced. */
3933 unsigned int paren_not_balanced
;
3935 while (*l
!= END_OF_INSN
)
3937 /* Skip optional white space before operand. */
3938 if (is_space_char (*l
))
3940 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3942 as_bad (_("invalid character %s before operand %d"),
3943 output_invalid (*l
),
3947 token_start
= l
; /* after white space */
3948 paren_not_balanced
= 0;
3949 while (paren_not_balanced
|| *l
!= ',')
3951 if (*l
== END_OF_INSN
)
3953 if (paren_not_balanced
)
3956 as_bad (_("unbalanced parenthesis in operand %d."),
3959 as_bad (_("unbalanced brackets in operand %d."),
3964 break; /* we are done */
3966 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3968 as_bad (_("invalid character %s in operand %d"),
3969 output_invalid (*l
),
3976 ++paren_not_balanced
;
3978 --paren_not_balanced
;
3983 ++paren_not_balanced
;
3985 --paren_not_balanced
;
3989 if (l
!= token_start
)
3990 { /* Yes, we've read in another operand. */
3991 unsigned int operand_ok
;
3992 this_operand
= i
.operands
++;
3993 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3994 if (i
.operands
> MAX_OPERANDS
)
3996 as_bad (_("spurious operands; (%d operands/instruction max)"),
4000 /* Now parse operand adding info to 'i' as we go along. */
4001 END_STRING_AND_SAVE (l
);
4005 i386_intel_operand (token_start
,
4006 intel_float_operand (mnemonic
));
4008 operand_ok
= i386_att_operand (token_start
);
4010 RESTORE_END_STRING (l
);
4016 if (expecting_operand
)
4018 expecting_operand_after_comma
:
4019 as_bad (_("expecting operand after ','; got nothing"));
4024 as_bad (_("expecting operand before ','; got nothing"));
4029 /* Now *l must be either ',' or END_OF_INSN. */
4032 if (*++l
== END_OF_INSN
)
4034 /* Just skip it, if it's \n complain. */
4035 goto expecting_operand_after_comma
;
4037 expecting_operand
= 1;
4044 swap_2_operands (int xchg1
, int xchg2
)
4046 union i386_op temp_op
;
4047 i386_operand_type temp_type
;
4048 enum bfd_reloc_code_real temp_reloc
;
4050 temp_type
= i
.types
[xchg2
];
4051 i
.types
[xchg2
] = i
.types
[xchg1
];
4052 i
.types
[xchg1
] = temp_type
;
4053 temp_op
= i
.op
[xchg2
];
4054 i
.op
[xchg2
] = i
.op
[xchg1
];
4055 i
.op
[xchg1
] = temp_op
;
4056 temp_reloc
= i
.reloc
[xchg2
];
4057 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4058 i
.reloc
[xchg1
] = temp_reloc
;
4062 if (i
.mask
->operand
== xchg1
)
4063 i
.mask
->operand
= xchg2
;
4064 else if (i
.mask
->operand
== xchg2
)
4065 i
.mask
->operand
= xchg1
;
4069 if (i
.broadcast
->operand
== xchg1
)
4070 i
.broadcast
->operand
= xchg2
;
4071 else if (i
.broadcast
->operand
== xchg2
)
4072 i
.broadcast
->operand
= xchg1
;
4076 if (i
.rounding
->operand
== xchg1
)
4077 i
.rounding
->operand
= xchg2
;
4078 else if (i
.rounding
->operand
== xchg2
)
4079 i
.rounding
->operand
= xchg1
;
4084 swap_operands (void)
4090 swap_2_operands (1, i
.operands
- 2);
4093 swap_2_operands (0, i
.operands
- 1);
4099 if (i
.mem_operands
== 2)
4101 const seg_entry
*temp_seg
;
4102 temp_seg
= i
.seg
[0];
4103 i
.seg
[0] = i
.seg
[1];
4104 i
.seg
[1] = temp_seg
;
4108 /* Try to ensure constant immediates are represented in the smallest
4113 char guess_suffix
= 0;
4117 guess_suffix
= i
.suffix
;
4118 else if (i
.reg_operands
)
4120 /* Figure out a suffix from the last register operand specified.
4121 We can't do this properly yet, ie. excluding InOutPortReg,
4122 but the following works for instructions with immediates.
4123 In any case, we can't set i.suffix yet. */
4124 for (op
= i
.operands
; --op
>= 0;)
4125 if (i
.types
[op
].bitfield
.reg8
)
4127 guess_suffix
= BYTE_MNEM_SUFFIX
;
4130 else if (i
.types
[op
].bitfield
.reg16
)
4132 guess_suffix
= WORD_MNEM_SUFFIX
;
4135 else if (i
.types
[op
].bitfield
.reg32
)
4137 guess_suffix
= LONG_MNEM_SUFFIX
;
4140 else if (i
.types
[op
].bitfield
.reg64
)
4142 guess_suffix
= QWORD_MNEM_SUFFIX
;
4146 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4147 guess_suffix
= WORD_MNEM_SUFFIX
;
4149 for (op
= i
.operands
; --op
>= 0;)
4150 if (operand_type_check (i
.types
[op
], imm
))
4152 switch (i
.op
[op
].imms
->X_op
)
4155 /* If a suffix is given, this operand may be shortened. */
4156 switch (guess_suffix
)
4158 case LONG_MNEM_SUFFIX
:
4159 i
.types
[op
].bitfield
.imm32
= 1;
4160 i
.types
[op
].bitfield
.imm64
= 1;
4162 case WORD_MNEM_SUFFIX
:
4163 i
.types
[op
].bitfield
.imm16
= 1;
4164 i
.types
[op
].bitfield
.imm32
= 1;
4165 i
.types
[op
].bitfield
.imm32s
= 1;
4166 i
.types
[op
].bitfield
.imm64
= 1;
4168 case BYTE_MNEM_SUFFIX
:
4169 i
.types
[op
].bitfield
.imm8
= 1;
4170 i
.types
[op
].bitfield
.imm8s
= 1;
4171 i
.types
[op
].bitfield
.imm16
= 1;
4172 i
.types
[op
].bitfield
.imm32
= 1;
4173 i
.types
[op
].bitfield
.imm32s
= 1;
4174 i
.types
[op
].bitfield
.imm64
= 1;
4178 /* If this operand is at most 16 bits, convert it
4179 to a signed 16 bit number before trying to see
4180 whether it will fit in an even smaller size.
4181 This allows a 16-bit operand such as $0xffe0 to
4182 be recognised as within Imm8S range. */
4183 if ((i
.types
[op
].bitfield
.imm16
)
4184 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4186 i
.op
[op
].imms
->X_add_number
=
4187 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4189 if ((i
.types
[op
].bitfield
.imm32
)
4190 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4193 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4194 ^ ((offsetT
) 1 << 31))
4195 - ((offsetT
) 1 << 31));
4198 = operand_type_or (i
.types
[op
],
4199 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4201 /* We must avoid matching of Imm32 templates when 64bit
4202 only immediate is available. */
4203 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4204 i
.types
[op
].bitfield
.imm32
= 0;
4211 /* Symbols and expressions. */
4213 /* Convert symbolic operand to proper sizes for matching, but don't
4214 prevent matching a set of insns that only supports sizes other
4215 than those matching the insn suffix. */
4217 i386_operand_type mask
, allowed
;
4218 const insn_template
*t
;
4220 operand_type_set (&mask
, 0);
4221 operand_type_set (&allowed
, 0);
4223 for (t
= current_templates
->start
;
4224 t
< current_templates
->end
;
4226 allowed
= operand_type_or (allowed
,
4227 t
->operand_types
[op
]);
4228 switch (guess_suffix
)
4230 case QWORD_MNEM_SUFFIX
:
4231 mask
.bitfield
.imm64
= 1;
4232 mask
.bitfield
.imm32s
= 1;
4234 case LONG_MNEM_SUFFIX
:
4235 mask
.bitfield
.imm32
= 1;
4237 case WORD_MNEM_SUFFIX
:
4238 mask
.bitfield
.imm16
= 1;
4240 case BYTE_MNEM_SUFFIX
:
4241 mask
.bitfield
.imm8
= 1;
4246 allowed
= operand_type_and (mask
, allowed
);
4247 if (!operand_type_all_zero (&allowed
))
4248 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4255 /* Try to use the smallest displacement type too. */
4257 optimize_disp (void)
4261 for (op
= i
.operands
; --op
>= 0;)
4262 if (operand_type_check (i
.types
[op
], disp
))
4264 if (i
.op
[op
].disps
->X_op
== O_constant
)
4266 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4268 if (i
.types
[op
].bitfield
.disp16
4269 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4271 /* If this operand is at most 16 bits, convert
4272 to a signed 16 bit number and don't use 64bit
4274 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4275 i
.types
[op
].bitfield
.disp64
= 0;
4277 if (i
.types
[op
].bitfield
.disp32
4278 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4280 /* If this operand is at most 32 bits, convert
4281 to a signed 32 bit number and don't use 64bit
4283 op_disp
&= (((offsetT
) 2 << 31) - 1);
4284 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4285 i
.types
[op
].bitfield
.disp64
= 0;
4287 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4289 i
.types
[op
].bitfield
.disp8
= 0;
4290 i
.types
[op
].bitfield
.disp16
= 0;
4291 i
.types
[op
].bitfield
.disp32
= 0;
4292 i
.types
[op
].bitfield
.disp32s
= 0;
4293 i
.types
[op
].bitfield
.disp64
= 0;
4297 else if (flag_code
== CODE_64BIT
)
4299 if (fits_in_signed_long (op_disp
))
4301 i
.types
[op
].bitfield
.disp64
= 0;
4302 i
.types
[op
].bitfield
.disp32s
= 1;
4304 if (i
.prefix
[ADDR_PREFIX
]
4305 && fits_in_unsigned_long (op_disp
))
4306 i
.types
[op
].bitfield
.disp32
= 1;
4308 if ((i
.types
[op
].bitfield
.disp32
4309 || i
.types
[op
].bitfield
.disp32s
4310 || i
.types
[op
].bitfield
.disp16
)
4311 && fits_in_signed_byte (op_disp
))
4312 i
.types
[op
].bitfield
.disp8
= 1;
4314 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4315 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4317 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4318 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4319 i
.types
[op
].bitfield
.disp8
= 0;
4320 i
.types
[op
].bitfield
.disp16
= 0;
4321 i
.types
[op
].bitfield
.disp32
= 0;
4322 i
.types
[op
].bitfield
.disp32s
= 0;
4323 i
.types
[op
].bitfield
.disp64
= 0;
4326 /* We only support 64bit displacement on constants. */
4327 i
.types
[op
].bitfield
.disp64
= 0;
4331 /* Check if operands are valid for the instruction. */
4334 check_VecOperands (const insn_template
*t
)
4338 /* Without VSIB byte, we can't have a vector register for index. */
4339 if (!t
->opcode_modifier
.vecsib
4341 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4342 || i
.index_reg
->reg_type
.bitfield
.regymm
4343 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4345 i
.error
= unsupported_vector_index_register
;
4349 /* Check if default mask is allowed. */
4350 if (t
->opcode_modifier
.nodefmask
4351 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4353 i
.error
= no_default_mask
;
4357 /* For VSIB byte, we need a vector register for index, and all vector
4358 registers must be distinct. */
4359 if (t
->opcode_modifier
.vecsib
)
4362 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4363 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4364 || (t
->opcode_modifier
.vecsib
== VecSIB256
4365 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4366 || (t
->opcode_modifier
.vecsib
== VecSIB512
4367 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4369 i
.error
= invalid_vsib_address
;
4373 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4374 if (i
.reg_operands
== 2 && !i
.mask
)
4376 gas_assert (i
.types
[0].bitfield
.regxmm
4377 || i
.types
[0].bitfield
.regymm
4378 || i
.types
[0].bitfield
.regzmm
);
4379 gas_assert (i
.types
[2].bitfield
.regxmm
4380 || i
.types
[2].bitfield
.regymm
4381 || i
.types
[2].bitfield
.regzmm
);
4382 if (operand_check
== check_none
)
4384 if (register_number (i
.op
[0].regs
)
4385 != register_number (i
.index_reg
)
4386 && register_number (i
.op
[2].regs
)
4387 != register_number (i
.index_reg
)
4388 && register_number (i
.op
[0].regs
)
4389 != register_number (i
.op
[2].regs
))
4391 if (operand_check
== check_error
)
4393 i
.error
= invalid_vector_register_set
;
4396 as_warn (_("mask, index, and destination registers should be distinct"));
4398 else if (i
.reg_operands
== 1 && i
.mask
)
4400 if ((i
.types
[1].bitfield
.regymm
4401 || i
.types
[1].bitfield
.regzmm
)
4402 && (register_number (i
.op
[1].regs
)
4403 == register_number (i
.index_reg
)))
4405 if (operand_check
== check_error
)
4407 i
.error
= invalid_vector_register_set
;
4410 if (operand_check
!= check_none
)
4411 as_warn (_("index and destination registers should be distinct"));
4416 /* Check if broadcast is supported by the instruction and is applied
4417 to the memory operand. */
4420 int broadcasted_opnd_size
;
4422 /* Check if specified broadcast is supported in this instruction,
4423 and it's applied to memory operand of DWORD or QWORD type,
4424 depending on VecESize. */
4425 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4426 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4427 || (t
->opcode_modifier
.vecesize
== 0
4428 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4429 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4430 || (t
->opcode_modifier
.vecesize
== 1
4431 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4432 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4435 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4436 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4437 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4438 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4439 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4443 if ((broadcasted_opnd_size
== 256
4444 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4445 || (broadcasted_opnd_size
== 512
4446 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4449 i
.error
= unsupported_broadcast
;
4453 /* If broadcast is supported in this instruction, we need to check if
4454 operand of one-element size isn't specified without broadcast. */
4455 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4457 /* Find memory operand. */
4458 for (op
= 0; op
< i
.operands
; op
++)
4459 if (operand_type_check (i
.types
[op
], anymem
))
4461 gas_assert (op
< i
.operands
);
4462 /* Check size of the memory operand. */
4463 if ((t
->opcode_modifier
.vecesize
== 0
4464 && i
.types
[op
].bitfield
.dword
)
4465 || (t
->opcode_modifier
.vecesize
== 1
4466 && i
.types
[op
].bitfield
.qword
))
4468 i
.error
= broadcast_needed
;
4473 /* Check if requested masking is supported. */
4475 && (!t
->opcode_modifier
.masking
4477 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4479 i
.error
= unsupported_masking
;
4483 /* Check if masking is applied to dest operand. */
4484 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4486 i
.error
= mask_not_on_destination
;
4493 if ((i
.rounding
->type
!= saeonly
4494 && !t
->opcode_modifier
.staticrounding
)
4495 || (i
.rounding
->type
== saeonly
4496 && (t
->opcode_modifier
.staticrounding
4497 || !t
->opcode_modifier
.sae
)))
4499 i
.error
= unsupported_rc_sae
;
4502 /* If the instruction has several immediate operands and one of
4503 them is rounding, the rounding operand should be the last
4504 immediate operand. */
4505 if (i
.imm_operands
> 1
4506 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4508 i
.error
= rc_sae_operand_not_last_imm
;
4513 /* Check vector Disp8 operand. */
4514 if (t
->opcode_modifier
.disp8memshift
)
4517 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4519 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4521 for (op
= 0; op
< i
.operands
; op
++)
4522 if (operand_type_check (i
.types
[op
], disp
)
4523 && i
.op
[op
].disps
->X_op
== O_constant
)
4525 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4526 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4527 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4530 i
.types
[op
].bitfield
.vec_disp8
= 1;
4533 /* Vector insn can only have Vec_Disp8/Disp32 in
4534 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4536 i
.types
[op
].bitfield
.disp8
= 0;
4537 if (flag_code
!= CODE_16BIT
)
4538 i
.types
[op
].bitfield
.disp16
= 0;
4541 else if (flag_code
!= CODE_16BIT
)
4543 /* One form of this instruction supports vector Disp8.
4544 Try vector Disp8 if we need to use Disp32. */
4545 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4547 i
.error
= try_vector_disp8
;
4559 /* Check if operands are valid for the instruction. Update VEX
4563 VEX_check_operands (const insn_template
*t
)
4565 /* VREX is only valid with EVEX prefix. */
4566 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4568 i
.error
= invalid_register_operand
;
4572 if (!t
->opcode_modifier
.vex
)
4575 /* Only check VEX_Imm4, which must be the first operand. */
4576 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4578 if (i
.op
[0].imms
->X_op
!= O_constant
4579 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4585 /* Turn off Imm8 so that update_imm won't complain. */
4586 i
.types
[0] = vec_imm4
;
4592 static const insn_template
*
4593 match_template (void)
4595 /* Points to template once we've found it. */
4596 const insn_template
*t
;
4597 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4598 i386_operand_type overlap4
;
4599 unsigned int found_reverse_match
;
4600 i386_opcode_modifier suffix_check
;
4601 i386_operand_type operand_types
[MAX_OPERANDS
];
4602 int addr_prefix_disp
;
4604 unsigned int found_cpu_match
;
4605 unsigned int check_register
;
4606 enum i386_error specific_error
= 0;
4608 #if MAX_OPERANDS != 5
4609 # error "MAX_OPERANDS must be 5."
4612 found_reverse_match
= 0;
4613 addr_prefix_disp
= -1;
4615 memset (&suffix_check
, 0, sizeof (suffix_check
));
4616 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4617 suffix_check
.no_bsuf
= 1;
4618 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4619 suffix_check
.no_wsuf
= 1;
4620 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4621 suffix_check
.no_ssuf
= 1;
4622 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4623 suffix_check
.no_lsuf
= 1;
4624 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4625 suffix_check
.no_qsuf
= 1;
4626 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4627 suffix_check
.no_ldsuf
= 1;
4629 /* Must have right number of operands. */
4630 i
.error
= number_of_operands_mismatch
;
4632 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4634 addr_prefix_disp
= -1;
4636 if (i
.operands
!= t
->operands
)
4639 /* Check processor support. */
4640 i
.error
= unsupported
;
4641 found_cpu_match
= (cpu_flags_match (t
)
4642 == CPU_FLAGS_PERFECT_MATCH
);
4643 if (!found_cpu_match
)
4646 /* Check old gcc support. */
4647 i
.error
= old_gcc_only
;
4648 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4651 /* Check AT&T mnemonic. */
4652 i
.error
= unsupported_with_intel_mnemonic
;
4653 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4656 /* Check AT&T/Intel syntax. */
4657 i
.error
= unsupported_syntax
;
4658 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4659 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4662 /* Check the suffix, except for some instructions in intel mode. */
4663 i
.error
= invalid_instruction_suffix
;
4664 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4665 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4666 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4667 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4668 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4669 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4670 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4673 if (!operand_size_match (t
))
4676 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4677 operand_types
[j
] = t
->operand_types
[j
];
4679 /* In general, don't allow 64-bit operands in 32-bit mode. */
4680 if (i
.suffix
== QWORD_MNEM_SUFFIX
4681 && flag_code
!= CODE_64BIT
4683 ? (!t
->opcode_modifier
.ignoresize
4684 && !intel_float_operand (t
->name
))
4685 : intel_float_operand (t
->name
) != 2)
4686 && ((!operand_types
[0].bitfield
.regmmx
4687 && !operand_types
[0].bitfield
.regxmm
4688 && !operand_types
[0].bitfield
.regymm
4689 && !operand_types
[0].bitfield
.regzmm
)
4690 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4691 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4692 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4693 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4694 && (t
->base_opcode
!= 0x0fc7
4695 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4698 /* In general, don't allow 32-bit operands on pre-386. */
4699 else if (i
.suffix
== LONG_MNEM_SUFFIX
4700 && !cpu_arch_flags
.bitfield
.cpui386
4702 ? (!t
->opcode_modifier
.ignoresize
4703 && !intel_float_operand (t
->name
))
4704 : intel_float_operand (t
->name
) != 2)
4705 && ((!operand_types
[0].bitfield
.regmmx
4706 && !operand_types
[0].bitfield
.regxmm
)
4707 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4708 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4711 /* Do not verify operands when there are none. */
4715 /* We've found a match; break out of loop. */
4719 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4720 into Disp32/Disp16/Disp32 operand. */
4721 if (i
.prefix
[ADDR_PREFIX
] != 0)
4723 /* There should be only one Disp operand. */
4727 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4729 if (operand_types
[j
].bitfield
.disp16
)
4731 addr_prefix_disp
= j
;
4732 operand_types
[j
].bitfield
.disp32
= 1;
4733 operand_types
[j
].bitfield
.disp16
= 0;
4739 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4741 if (operand_types
[j
].bitfield
.disp32
)
4743 addr_prefix_disp
= j
;
4744 operand_types
[j
].bitfield
.disp32
= 0;
4745 operand_types
[j
].bitfield
.disp16
= 1;
4751 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4753 if (operand_types
[j
].bitfield
.disp64
)
4755 addr_prefix_disp
= j
;
4756 operand_types
[j
].bitfield
.disp64
= 0;
4757 operand_types
[j
].bitfield
.disp32
= 1;
4765 /* We check register size if needed. */
4766 check_register
= t
->opcode_modifier
.checkregsize
;
4767 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4768 switch (t
->operands
)
4771 if (!operand_type_match (overlap0
, i
.types
[0]))
4775 /* xchg %eax, %eax is a special case. It is an aliase for nop
4776 only in 32bit mode and we can use opcode 0x90. In 64bit
4777 mode, we can't use 0x90 for xchg %eax, %eax since it should
4778 zero-extend %eax to %rax. */
4779 if (flag_code
== CODE_64BIT
4780 && t
->base_opcode
== 0x90
4781 && operand_type_equal (&i
.types
[0], &acc32
)
4782 && operand_type_equal (&i
.types
[1], &acc32
))
4786 /* If we swap operand in encoding, we either match
4787 the next one or reverse direction of operands. */
4788 if (t
->opcode_modifier
.s
)
4790 else if (t
->opcode_modifier
.d
)
4795 /* If we swap operand in encoding, we match the next one. */
4796 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4800 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4801 if (!operand_type_match (overlap0
, i
.types
[0])
4802 || !operand_type_match (overlap1
, i
.types
[1])
4804 && !operand_type_register_match (overlap0
, i
.types
[0],
4806 overlap1
, i
.types
[1],
4809 /* Check if other direction is valid ... */
4810 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4814 /* Try reversing direction of operands. */
4815 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4816 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4817 if (!operand_type_match (overlap0
, i
.types
[0])
4818 || !operand_type_match (overlap1
, i
.types
[1])
4820 && !operand_type_register_match (overlap0
,
4827 /* Does not match either direction. */
4830 /* found_reverse_match holds which of D or FloatDR
4832 if (t
->opcode_modifier
.d
)
4833 found_reverse_match
= Opcode_D
;
4834 else if (t
->opcode_modifier
.floatd
)
4835 found_reverse_match
= Opcode_FloatD
;
4837 found_reverse_match
= 0;
4838 if (t
->opcode_modifier
.floatr
)
4839 found_reverse_match
|= Opcode_FloatR
;
4843 /* Found a forward 2 operand match here. */
4844 switch (t
->operands
)
4847 overlap4
= operand_type_and (i
.types
[4],
4850 overlap3
= operand_type_and (i
.types
[3],
4853 overlap2
= operand_type_and (i
.types
[2],
4858 switch (t
->operands
)
4861 if (!operand_type_match (overlap4
, i
.types
[4])
4862 || !operand_type_register_match (overlap3
,
4870 if (!operand_type_match (overlap3
, i
.types
[3])
4872 && !operand_type_register_match (overlap2
,
4880 /* Here we make use of the fact that there are no
4881 reverse match 3 operand instructions, and all 3
4882 operand instructions only need to be checked for
4883 register consistency between operands 2 and 3. */
4884 if (!operand_type_match (overlap2
, i
.types
[2])
4886 && !operand_type_register_match (overlap1
,
4896 /* Found either forward/reverse 2, 3 or 4 operand match here:
4897 slip through to break. */
4899 if (!found_cpu_match
)
4901 found_reverse_match
= 0;
4905 /* Check if vector and VEX operands are valid. */
4906 if (check_VecOperands (t
) || VEX_check_operands (t
))
4908 specific_error
= i
.error
;
4912 /* We've found a match; break out of loop. */
4916 if (t
== current_templates
->end
)
4918 /* We found no match. */
4919 const char *err_msg
;
4920 switch (specific_error
? specific_error
: i
.error
)
4924 case operand_size_mismatch
:
4925 err_msg
= _("operand size mismatch");
4927 case operand_type_mismatch
:
4928 err_msg
= _("operand type mismatch");
4930 case register_type_mismatch
:
4931 err_msg
= _("register type mismatch");
4933 case number_of_operands_mismatch
:
4934 err_msg
= _("number of operands mismatch");
4936 case invalid_instruction_suffix
:
4937 err_msg
= _("invalid instruction suffix");
4940 err_msg
= _("constant doesn't fit in 4 bits");
4943 err_msg
= _("only supported with old gcc");
4945 case unsupported_with_intel_mnemonic
:
4946 err_msg
= _("unsupported with Intel mnemonic");
4948 case unsupported_syntax
:
4949 err_msg
= _("unsupported syntax");
4952 as_bad (_("unsupported instruction `%s'"),
4953 current_templates
->start
->name
);
4955 case invalid_vsib_address
:
4956 err_msg
= _("invalid VSIB address");
4958 case invalid_vector_register_set
:
4959 err_msg
= _("mask, index, and destination registers must be distinct");
4961 case unsupported_vector_index_register
:
4962 err_msg
= _("unsupported vector index register");
4964 case unsupported_broadcast
:
4965 err_msg
= _("unsupported broadcast");
4967 case broadcast_not_on_src_operand
:
4968 err_msg
= _("broadcast not on source memory operand");
4970 case broadcast_needed
:
4971 err_msg
= _("broadcast is needed for operand of such type");
4973 case unsupported_masking
:
4974 err_msg
= _("unsupported masking");
4976 case mask_not_on_destination
:
4977 err_msg
= _("mask not on destination operand");
4979 case no_default_mask
:
4980 err_msg
= _("default mask isn't allowed");
4982 case unsupported_rc_sae
:
4983 err_msg
= _("unsupported static rounding/sae");
4985 case rc_sae_operand_not_last_imm
:
4987 err_msg
= _("RC/SAE operand must precede immediate operands");
4989 err_msg
= _("RC/SAE operand must follow immediate operands");
4991 case invalid_register_operand
:
4992 err_msg
= _("invalid register operand");
4995 as_bad (_("%s for `%s'"), err_msg
,
4996 current_templates
->start
->name
);
5000 if (!quiet_warnings
)
5003 && (i
.types
[0].bitfield
.jumpabsolute
5004 != operand_types
[0].bitfield
.jumpabsolute
))
5006 as_warn (_("indirect %s without `*'"), t
->name
);
5009 if (t
->opcode_modifier
.isprefix
5010 && t
->opcode_modifier
.ignoresize
)
5012 /* Warn them that a data or address size prefix doesn't
5013 affect assembly of the next line of code. */
5014 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5018 /* Copy the template we found. */
5021 if (addr_prefix_disp
!= -1)
5022 i
.tm
.operand_types
[addr_prefix_disp
]
5023 = operand_types
[addr_prefix_disp
];
5025 if (found_reverse_match
)
5027 /* If we found a reverse match we must alter the opcode
5028 direction bit. found_reverse_match holds bits to change
5029 (different for int & float insns). */
5031 i
.tm
.base_opcode
^= found_reverse_match
;
5033 i
.tm
.operand_types
[0] = operand_types
[1];
5034 i
.tm
.operand_types
[1] = operand_types
[0];
5043 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5044 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5046 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5048 as_bad (_("`%s' operand %d must use `%ses' segment"),
5054 /* There's only ever one segment override allowed per instruction.
5055 This instruction possibly has a legal segment override on the
5056 second operand, so copy the segment to where non-string
5057 instructions store it, allowing common code. */
5058 i
.seg
[0] = i
.seg
[1];
5060 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5062 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5064 as_bad (_("`%s' operand %d must use `%ses' segment"),
5075 process_suffix (void)
5077 /* If matched instruction specifies an explicit instruction mnemonic
5079 if (i
.tm
.opcode_modifier
.size16
)
5080 i
.suffix
= WORD_MNEM_SUFFIX
;
5081 else if (i
.tm
.opcode_modifier
.size32
)
5082 i
.suffix
= LONG_MNEM_SUFFIX
;
5083 else if (i
.tm
.opcode_modifier
.size64
)
5084 i
.suffix
= QWORD_MNEM_SUFFIX
;
5085 else if (i
.reg_operands
)
5087 /* If there's no instruction mnemonic suffix we try to invent one
5088 based on register operands. */
5091 /* We take i.suffix from the last register operand specified,
5092 Destination register type is more significant than source
5093 register type. crc32 in SSE4.2 prefers source register
5095 if (i
.tm
.base_opcode
== 0xf20f38f1)
5097 if (i
.types
[0].bitfield
.reg16
)
5098 i
.suffix
= WORD_MNEM_SUFFIX
;
5099 else if (i
.types
[0].bitfield
.reg32
)
5100 i
.suffix
= LONG_MNEM_SUFFIX
;
5101 else if (i
.types
[0].bitfield
.reg64
)
5102 i
.suffix
= QWORD_MNEM_SUFFIX
;
5104 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5106 if (i
.types
[0].bitfield
.reg8
)
5107 i
.suffix
= BYTE_MNEM_SUFFIX
;
5114 if (i
.tm
.base_opcode
== 0xf20f38f1
5115 || i
.tm
.base_opcode
== 0xf20f38f0)
5117 /* We have to know the operand size for crc32. */
5118 as_bad (_("ambiguous memory operand size for `%s`"),
5123 for (op
= i
.operands
; --op
>= 0;)
5124 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5126 if (i
.types
[op
].bitfield
.reg8
)
5128 i
.suffix
= BYTE_MNEM_SUFFIX
;
5131 else if (i
.types
[op
].bitfield
.reg16
)
5133 i
.suffix
= WORD_MNEM_SUFFIX
;
5136 else if (i
.types
[op
].bitfield
.reg32
)
5138 i
.suffix
= LONG_MNEM_SUFFIX
;
5141 else if (i
.types
[op
].bitfield
.reg64
)
5143 i
.suffix
= QWORD_MNEM_SUFFIX
;
5149 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5152 && i
.tm
.opcode_modifier
.ignoresize
5153 && i
.tm
.opcode_modifier
.no_bsuf
)
5155 else if (!check_byte_reg ())
5158 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5161 && i
.tm
.opcode_modifier
.ignoresize
5162 && i
.tm
.opcode_modifier
.no_lsuf
)
5164 else if (!check_long_reg ())
5167 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5170 && i
.tm
.opcode_modifier
.ignoresize
5171 && i
.tm
.opcode_modifier
.no_qsuf
)
5173 else if (!check_qword_reg ())
5176 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5179 && i
.tm
.opcode_modifier
.ignoresize
5180 && i
.tm
.opcode_modifier
.no_wsuf
)
5182 else if (!check_word_reg ())
5185 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5186 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5187 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5189 /* Skip if the instruction has x/y/z suffix. match_template
5190 should check if it is a valid suffix. */
5192 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5193 /* Do nothing if the instruction is going to ignore the prefix. */
5198 else if (i
.tm
.opcode_modifier
.defaultsize
5200 /* exclude fldenv/frstor/fsave/fstenv */
5201 && i
.tm
.opcode_modifier
.no_ssuf
)
5203 i
.suffix
= stackop_size
;
5205 else if (intel_syntax
5207 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5208 || i
.tm
.opcode_modifier
.jumpbyte
5209 || i
.tm
.opcode_modifier
.jumpintersegment
5210 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5211 && i
.tm
.extension_opcode
<= 3)))
5216 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5218 i
.suffix
= QWORD_MNEM_SUFFIX
;
5222 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5223 i
.suffix
= LONG_MNEM_SUFFIX
;
5226 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5227 i
.suffix
= WORD_MNEM_SUFFIX
;
5236 if (i
.tm
.opcode_modifier
.w
)
5238 as_bad (_("no instruction mnemonic suffix given and "
5239 "no register operands; can't size instruction"));
5245 unsigned int suffixes
;
5247 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5248 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5250 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5252 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5254 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5256 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5259 /* There are more than suffix matches. */
5260 if (i
.tm
.opcode_modifier
.w
5261 || ((suffixes
& (suffixes
- 1))
5262 && !i
.tm
.opcode_modifier
.defaultsize
5263 && !i
.tm
.opcode_modifier
.ignoresize
))
5265 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5271 /* Change the opcode based on the operand size given by i.suffix;
5272 We don't need to change things for byte insns. */
5275 && i
.suffix
!= BYTE_MNEM_SUFFIX
5276 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5277 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5278 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5280 /* It's not a byte, select word/dword operation. */
5281 if (i
.tm
.opcode_modifier
.w
)
5283 if (i
.tm
.opcode_modifier
.shortform
)
5284 i
.tm
.base_opcode
|= 8;
5286 i
.tm
.base_opcode
|= 1;
5289 /* Now select between word & dword operations via the operand
5290 size prefix, except for instructions that will ignore this
5292 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5294 /* The address size override prefix changes the size of the
5296 if ((flag_code
== CODE_32BIT
5297 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5298 || (flag_code
!= CODE_32BIT
5299 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5300 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5303 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5304 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5305 && !i
.tm
.opcode_modifier
.ignoresize
5306 && !i
.tm
.opcode_modifier
.floatmf
5307 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5308 || (flag_code
== CODE_64BIT
5309 && i
.tm
.opcode_modifier
.jumpbyte
)))
5311 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5313 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5314 prefix
= ADDR_PREFIX_OPCODE
;
5316 if (!add_prefix (prefix
))
5320 /* Set mode64 for an operand. */
5321 if (i
.suffix
== QWORD_MNEM_SUFFIX
5322 && flag_code
== CODE_64BIT
5323 && !i
.tm
.opcode_modifier
.norex64
)
5325 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5326 need rex64. cmpxchg8b is also a special case. */
5327 if (! (i
.operands
== 2
5328 && i
.tm
.base_opcode
== 0x90
5329 && i
.tm
.extension_opcode
== None
5330 && operand_type_equal (&i
.types
[0], &acc64
)
5331 && operand_type_equal (&i
.types
[1], &acc64
))
5332 && ! (i
.operands
== 1
5333 && i
.tm
.base_opcode
== 0xfc7
5334 && i
.tm
.extension_opcode
== 1
5335 && !operand_type_check (i
.types
[0], reg
)
5336 && operand_type_check (i
.types
[0], anymem
)))
5340 /* Size floating point instruction. */
5341 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5342 if (i
.tm
.opcode_modifier
.floatmf
)
5343 i
.tm
.base_opcode
^= 4;
5350 check_byte_reg (void)
5354 for (op
= i
.operands
; --op
>= 0;)
5356 /* If this is an eight bit register, it's OK. If it's the 16 or
5357 32 bit version of an eight bit register, we will just use the
5358 low portion, and that's OK too. */
5359 if (i
.types
[op
].bitfield
.reg8
)
5362 /* I/O port address operands are OK too. */
5363 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5366 /* crc32 doesn't generate this warning. */
5367 if (i
.tm
.base_opcode
== 0xf20f38f0)
5370 if ((i
.types
[op
].bitfield
.reg16
5371 || i
.types
[op
].bitfield
.reg32
5372 || i
.types
[op
].bitfield
.reg64
)
5373 && i
.op
[op
].regs
->reg_num
< 4
5374 /* Prohibit these changes in 64bit mode, since the lowering
5375 would be more complicated. */
5376 && flag_code
!= CODE_64BIT
)
5378 #if REGISTER_WARNINGS
5379 if (!quiet_warnings
)
5380 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5382 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5383 ? REGNAM_AL
- REGNAM_AX
5384 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5386 i
.op
[op
].regs
->reg_name
,
5391 /* Any other register is bad. */
5392 if (i
.types
[op
].bitfield
.reg16
5393 || i
.types
[op
].bitfield
.reg32
5394 || i
.types
[op
].bitfield
.reg64
5395 || i
.types
[op
].bitfield
.regmmx
5396 || i
.types
[op
].bitfield
.regxmm
5397 || i
.types
[op
].bitfield
.regymm
5398 || i
.types
[op
].bitfield
.regzmm
5399 || i
.types
[op
].bitfield
.sreg2
5400 || i
.types
[op
].bitfield
.sreg3
5401 || i
.types
[op
].bitfield
.control
5402 || i
.types
[op
].bitfield
.debug
5403 || i
.types
[op
].bitfield
.test
5404 || i
.types
[op
].bitfield
.floatreg
5405 || i
.types
[op
].bitfield
.floatacc
)
5407 as_bad (_("`%s%s' not allowed with `%s%c'"),
5409 i
.op
[op
].regs
->reg_name
,
5419 check_long_reg (void)
5423 for (op
= i
.operands
; --op
>= 0;)
5424 /* Reject eight bit registers, except where the template requires
5425 them. (eg. movzb) */
5426 if (i
.types
[op
].bitfield
.reg8
5427 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5428 || i
.tm
.operand_types
[op
].bitfield
.reg32
5429 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5431 as_bad (_("`%s%s' not allowed with `%s%c'"),
5433 i
.op
[op
].regs
->reg_name
,
5438 /* Warn if the e prefix on a general reg is missing. */
5439 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5440 && i
.types
[op
].bitfield
.reg16
5441 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5442 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5444 /* Prohibit these changes in the 64bit mode, since the
5445 lowering is more complicated. */
5446 if (flag_code
== CODE_64BIT
)
5448 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5449 register_prefix
, i
.op
[op
].regs
->reg_name
,
5453 #if REGISTER_WARNINGS
5454 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5456 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5457 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5460 /* Warn if the r prefix on a general reg is present. */
5461 else if (i
.types
[op
].bitfield
.reg64
5462 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5463 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5466 && i
.tm
.opcode_modifier
.toqword
5467 && !i
.types
[0].bitfield
.regxmm
)
5469 /* Convert to QWORD. We want REX byte. */
5470 i
.suffix
= QWORD_MNEM_SUFFIX
;
5474 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5475 register_prefix
, i
.op
[op
].regs
->reg_name
,
5484 check_qword_reg (void)
5488 for (op
= i
.operands
; --op
>= 0; )
5489 /* Reject eight bit registers, except where the template requires
5490 them. (eg. movzb) */
5491 if (i
.types
[op
].bitfield
.reg8
5492 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5493 || i
.tm
.operand_types
[op
].bitfield
.reg32
5494 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5496 as_bad (_("`%s%s' not allowed with `%s%c'"),
5498 i
.op
[op
].regs
->reg_name
,
5503 /* Warn if the r prefix on a general reg is missing. */
5504 else if ((i
.types
[op
].bitfield
.reg16
5505 || i
.types
[op
].bitfield
.reg32
)
5506 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5507 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5509 /* Prohibit these changes in the 64bit mode, since the
5510 lowering is more complicated. */
5512 && i
.tm
.opcode_modifier
.todword
5513 && !i
.types
[0].bitfield
.regxmm
)
5515 /* Convert to DWORD. We don't want REX byte. */
5516 i
.suffix
= LONG_MNEM_SUFFIX
;
5520 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5521 register_prefix
, i
.op
[op
].regs
->reg_name
,
5530 check_word_reg (void)
5533 for (op
= i
.operands
; --op
>= 0;)
5534 /* Reject eight bit registers, except where the template requires
5535 them. (eg. movzb) */
5536 if (i
.types
[op
].bitfield
.reg8
5537 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5538 || i
.tm
.operand_types
[op
].bitfield
.reg32
5539 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5541 as_bad (_("`%s%s' not allowed with `%s%c'"),
5543 i
.op
[op
].regs
->reg_name
,
5548 /* Warn if the e or r prefix on a general reg is present. */
5549 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5550 && (i
.types
[op
].bitfield
.reg32
5551 || i
.types
[op
].bitfield
.reg64
)
5552 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5553 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5555 /* Prohibit these changes in the 64bit mode, since the
5556 lowering is more complicated. */
5557 if (flag_code
== CODE_64BIT
)
5559 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5560 register_prefix
, i
.op
[op
].regs
->reg_name
,
5564 #if REGISTER_WARNINGS
5565 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5567 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5568 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5575 update_imm (unsigned int j
)
5577 i386_operand_type overlap
= i
.types
[j
];
5578 if ((overlap
.bitfield
.imm8
5579 || overlap
.bitfield
.imm8s
5580 || overlap
.bitfield
.imm16
5581 || overlap
.bitfield
.imm32
5582 || overlap
.bitfield
.imm32s
5583 || overlap
.bitfield
.imm64
)
5584 && !operand_type_equal (&overlap
, &imm8
)
5585 && !operand_type_equal (&overlap
, &imm8s
)
5586 && !operand_type_equal (&overlap
, &imm16
)
5587 && !operand_type_equal (&overlap
, &imm32
)
5588 && !operand_type_equal (&overlap
, &imm32s
)
5589 && !operand_type_equal (&overlap
, &imm64
))
5593 i386_operand_type temp
;
5595 operand_type_set (&temp
, 0);
5596 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5598 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5599 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5601 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5602 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5603 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5605 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5606 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5609 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5612 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5613 || operand_type_equal (&overlap
, &imm16_32
)
5614 || operand_type_equal (&overlap
, &imm16_32s
))
5616 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5621 if (!operand_type_equal (&overlap
, &imm8
)
5622 && !operand_type_equal (&overlap
, &imm8s
)
5623 && !operand_type_equal (&overlap
, &imm16
)
5624 && !operand_type_equal (&overlap
, &imm32
)
5625 && !operand_type_equal (&overlap
, &imm32s
)
5626 && !operand_type_equal (&overlap
, &imm64
))
5628 as_bad (_("no instruction mnemonic suffix given; "
5629 "can't determine immediate size"));
5633 i
.types
[j
] = overlap
;
5643 /* Update the first 2 immediate operands. */
5644 n
= i
.operands
> 2 ? 2 : i
.operands
;
5647 for (j
= 0; j
< n
; j
++)
5648 if (update_imm (j
) == 0)
5651 /* The 3rd operand can't be immediate operand. */
5652 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5659 bad_implicit_operand (int xmm
)
5661 const char *ireg
= xmm
? "xmm0" : "ymm0";
5664 as_bad (_("the last operand of `%s' must be `%s%s'"),
5665 i
.tm
.name
, register_prefix
, ireg
);
5667 as_bad (_("the first operand of `%s' must be `%s%s'"),
5668 i
.tm
.name
, register_prefix
, ireg
);
5673 process_operands (void)
5675 /* Default segment register this instruction will use for memory
5676 accesses. 0 means unknown. This is only for optimizing out
5677 unnecessary segment overrides. */
5678 const seg_entry
*default_seg
= 0;
5680 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5682 unsigned int dupl
= i
.operands
;
5683 unsigned int dest
= dupl
- 1;
5686 /* The destination must be an xmm register. */
5687 gas_assert (i
.reg_operands
5688 && MAX_OPERANDS
> dupl
5689 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5691 if (i
.tm
.opcode_modifier
.firstxmm0
)
5693 /* The first operand is implicit and must be xmm0. */
5694 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5695 if (register_number (i
.op
[0].regs
) != 0)
5696 return bad_implicit_operand (1);
5698 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5700 /* Keep xmm0 for instructions with VEX prefix and 3
5706 /* We remove the first xmm0 and keep the number of
5707 operands unchanged, which in fact duplicates the
5709 for (j
= 1; j
< i
.operands
; j
++)
5711 i
.op
[j
- 1] = i
.op
[j
];
5712 i
.types
[j
- 1] = i
.types
[j
];
5713 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5717 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5719 gas_assert ((MAX_OPERANDS
- 1) > dupl
5720 && (i
.tm
.opcode_modifier
.vexsources
5723 /* Add the implicit xmm0 for instructions with VEX prefix
5725 for (j
= i
.operands
; j
> 0; j
--)
5727 i
.op
[j
] = i
.op
[j
- 1];
5728 i
.types
[j
] = i
.types
[j
- 1];
5729 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5732 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5733 i
.types
[0] = regxmm
;
5734 i
.tm
.operand_types
[0] = regxmm
;
5737 i
.reg_operands
+= 2;
5742 i
.op
[dupl
] = i
.op
[dest
];
5743 i
.types
[dupl
] = i
.types
[dest
];
5744 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5753 i
.op
[dupl
] = i
.op
[dest
];
5754 i
.types
[dupl
] = i
.types
[dest
];
5755 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5758 if (i
.tm
.opcode_modifier
.immext
)
5761 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5765 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5766 gas_assert (i
.reg_operands
5767 && (operand_type_equal (&i
.types
[0], ®xmm
)
5768 || operand_type_equal (&i
.types
[0], ®ymm
)
5769 || operand_type_equal (&i
.types
[0], ®zmm
)));
5770 if (register_number (i
.op
[0].regs
) != 0)
5771 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5773 for (j
= 1; j
< i
.operands
; j
++)
5775 i
.op
[j
- 1] = i
.op
[j
];
5776 i
.types
[j
- 1] = i
.types
[j
];
5778 /* We need to adjust fields in i.tm since they are used by
5779 build_modrm_byte. */
5780 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5787 else if (i
.tm
.opcode_modifier
.regkludge
)
5789 /* The imul $imm, %reg instruction is converted into
5790 imul $imm, %reg, %reg, and the clr %reg instruction
5791 is converted into xor %reg, %reg. */
5793 unsigned int first_reg_op
;
5795 if (operand_type_check (i
.types
[0], reg
))
5799 /* Pretend we saw the extra register operand. */
5800 gas_assert (i
.reg_operands
== 1
5801 && i
.op
[first_reg_op
+ 1].regs
== 0);
5802 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5803 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5808 if (i
.tm
.opcode_modifier
.shortform
)
5810 if (i
.types
[0].bitfield
.sreg2
5811 || i
.types
[0].bitfield
.sreg3
)
5813 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5814 && i
.op
[0].regs
->reg_num
== 1)
5816 as_bad (_("you can't `pop %scs'"), register_prefix
);
5819 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5820 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5825 /* The register or float register operand is in operand
5829 if (i
.types
[0].bitfield
.floatreg
5830 || operand_type_check (i
.types
[0], reg
))
5834 /* Register goes in low 3 bits of opcode. */
5835 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5836 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5838 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5840 /* Warn about some common errors, but press on regardless.
5841 The first case can be generated by gcc (<= 2.8.1). */
5842 if (i
.operands
== 2)
5844 /* Reversed arguments on faddp, fsubp, etc. */
5845 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5846 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5847 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5851 /* Extraneous `l' suffix on fp insn. */
5852 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5853 register_prefix
, i
.op
[0].regs
->reg_name
);
5858 else if (i
.tm
.opcode_modifier
.modrm
)
5860 /* The opcode is completed (modulo i.tm.extension_opcode which
5861 must be put into the modrm byte). Now, we make the modrm and
5862 index base bytes based on all the info we've collected. */
5864 default_seg
= build_modrm_byte ();
5866 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5870 else if (i
.tm
.opcode_modifier
.isstring
)
5872 /* For the string instructions that allow a segment override
5873 on one of their operands, the default segment is ds. */
5877 if (i
.tm
.base_opcode
== 0x8d /* lea */
5880 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5882 /* If a segment was explicitly specified, and the specified segment
5883 is not the default, use an opcode prefix to select it. If we
5884 never figured out what the default segment is, then default_seg
5885 will be zero at this point, and the specified segment prefix will
5887 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5889 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5895 static const seg_entry
*
5896 build_modrm_byte (void)
5898 const seg_entry
*default_seg
= 0;
5899 unsigned int source
, dest
;
5902 /* The first operand of instructions with VEX prefix and 3 sources
5903 must be VEX_Imm4. */
5904 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5907 unsigned int nds
, reg_slot
;
5910 if (i
.tm
.opcode_modifier
.veximmext
5911 && i
.tm
.opcode_modifier
.immext
)
5913 dest
= i
.operands
- 2;
5914 gas_assert (dest
== 3);
5917 dest
= i
.operands
- 1;
5920 /* There are 2 kinds of instructions:
5921 1. 5 operands: 4 register operands or 3 register operands
5922 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5923 VexW0 or VexW1. The destination must be either XMM, YMM or
5925 2. 4 operands: 4 register operands or 3 register operands
5926 plus 1 memory operand, VexXDS, and VexImmExt */
5927 gas_assert ((i
.reg_operands
== 4
5928 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5929 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5930 && (i
.tm
.opcode_modifier
.veximmext
5931 || (i
.imm_operands
== 1
5932 && i
.types
[0].bitfield
.vec_imm4
5933 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5934 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5935 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5936 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5937 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5939 if (i
.imm_operands
== 0)
5941 /* When there is no immediate operand, generate an 8bit
5942 immediate operand to encode the first operand. */
5943 exp
= &im_expressions
[i
.imm_operands
++];
5944 i
.op
[i
.operands
].imms
= exp
;
5945 i
.types
[i
.operands
] = imm8
;
5947 /* If VexW1 is set, the first operand is the source and
5948 the second operand is encoded in the immediate operand. */
5949 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5960 /* FMA swaps REG and NDS. */
5961 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5969 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5971 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5973 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5975 exp
->X_op
= O_constant
;
5976 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5977 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5981 unsigned int imm_slot
;
5983 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5985 /* If VexW0 is set, the third operand is the source and
5986 the second operand is encoded in the immediate
5993 /* VexW1 is set, the second operand is the source and
5994 the third operand is encoded in the immediate
6000 if (i
.tm
.opcode_modifier
.immext
)
6002 /* When ImmExt is set, the immdiate byte is the last
6004 imm_slot
= i
.operands
- 1;
6012 /* Turn on Imm8 so that output_imm will generate it. */
6013 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6016 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6018 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6020 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6022 i
.op
[imm_slot
].imms
->X_add_number
6023 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6024 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6027 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6028 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6030 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6032 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6037 /* i.reg_operands MUST be the number of real register operands;
6038 implicit registers do not count. If there are 3 register
6039 operands, it must be a instruction with VexNDS. For a
6040 instruction with VexNDD, the destination register is encoded
6041 in VEX prefix. If there are 4 register operands, it must be
6042 a instruction with VEX prefix and 3 sources. */
6043 if (i
.mem_operands
== 0
6044 && ((i
.reg_operands
== 2
6045 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6046 || (i
.reg_operands
== 3
6047 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6048 || (i
.reg_operands
== 4 && vex_3_sources
)))
6056 /* When there are 3 operands, one of them may be immediate,
6057 which may be the first or the last operand. Otherwise,
6058 the first operand must be shift count register (cl) or it
6059 is an instruction with VexNDS. */
6060 gas_assert (i
.imm_operands
== 1
6061 || (i
.imm_operands
== 0
6062 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6063 || i
.types
[0].bitfield
.shiftcount
)));
6064 if (operand_type_check (i
.types
[0], imm
)
6065 || i
.types
[0].bitfield
.shiftcount
)
6071 /* When there are 4 operands, the first two must be 8bit
6072 immediate operands. The source operand will be the 3rd
6075 For instructions with VexNDS, if the first operand
6076 an imm8, the source operand is the 2nd one. If the last
6077 operand is imm8, the source operand is the first one. */
6078 gas_assert ((i
.imm_operands
== 2
6079 && i
.types
[0].bitfield
.imm8
6080 && i
.types
[1].bitfield
.imm8
)
6081 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6082 && i
.imm_operands
== 1
6083 && (i
.types
[0].bitfield
.imm8
6084 || i
.types
[i
.operands
- 1].bitfield
.imm8
6086 if (i
.imm_operands
== 2)
6090 if (i
.types
[0].bitfield
.imm8
)
6097 if (i
.tm
.opcode_modifier
.evex
)
6099 /* For EVEX instructions, when there are 5 operands, the
6100 first one must be immediate operand. If the second one
6101 is immediate operand, the source operand is the 3th
6102 one. If the last one is immediate operand, the source
6103 operand is the 2nd one. */
6104 gas_assert (i
.imm_operands
== 2
6105 && i
.tm
.opcode_modifier
.sae
6106 && operand_type_check (i
.types
[0], imm
));
6107 if (operand_type_check (i
.types
[1], imm
))
6109 else if (operand_type_check (i
.types
[4], imm
))
6123 /* RC/SAE operand could be between DEST and SRC. That happens
6124 when one operand is GPR and the other one is XMM/YMM/ZMM
6126 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6129 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6131 /* For instructions with VexNDS, the register-only source
6132 operand must be 32/64bit integer, XMM, YMM or ZMM
6133 register. It is encoded in VEX prefix. We need to
6134 clear RegMem bit before calling operand_type_equal. */
6136 i386_operand_type op
;
6139 /* Check register-only source operand when two source
6140 operands are swapped. */
6141 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6142 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6150 op
= i
.tm
.operand_types
[vvvv
];
6151 op
.bitfield
.regmem
= 0;
6152 if ((dest
+ 1) >= i
.operands
6153 || (op
.bitfield
.reg32
!= 1
6154 && !op
.bitfield
.reg64
!= 1
6155 && !operand_type_equal (&op
, ®xmm
)
6156 && !operand_type_equal (&op
, ®ymm
)
6157 && !operand_type_equal (&op
, ®zmm
)
6158 && !operand_type_equal (&op
, ®mask
)))
6160 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6166 /* One of the register operands will be encoded in the i.tm.reg
6167 field, the other in the combined i.tm.mode and i.tm.regmem
6168 fields. If no form of this instruction supports a memory
6169 destination operand, then we assume the source operand may
6170 sometimes be a memory operand and so we need to store the
6171 destination in the i.rm.reg field. */
6172 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6173 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6175 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6176 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6177 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6179 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6181 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6183 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6188 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6189 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6190 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6192 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6194 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6196 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6199 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6201 if (!i
.types
[0].bitfield
.control
6202 && !i
.types
[1].bitfield
.control
)
6204 i
.rex
&= ~(REX_R
| REX_B
);
6205 add_prefix (LOCK_PREFIX_OPCODE
);
6209 { /* If it's not 2 reg operands... */
6214 unsigned int fake_zero_displacement
= 0;
6217 for (op
= 0; op
< i
.operands
; op
++)
6218 if (operand_type_check (i
.types
[op
], anymem
))
6220 gas_assert (op
< i
.operands
);
6222 if (i
.tm
.opcode_modifier
.vecsib
)
6224 if (i
.index_reg
->reg_num
== RegEiz
6225 || i
.index_reg
->reg_num
== RegRiz
)
6228 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6231 i
.sib
.base
= NO_BASE_REGISTER
;
6232 i
.sib
.scale
= i
.log2_scale_factor
;
6233 /* No Vec_Disp8 if there is no base. */
6234 i
.types
[op
].bitfield
.vec_disp8
= 0;
6235 i
.types
[op
].bitfield
.disp8
= 0;
6236 i
.types
[op
].bitfield
.disp16
= 0;
6237 i
.types
[op
].bitfield
.disp64
= 0;
6238 if (flag_code
!= CODE_64BIT
)
6240 /* Must be 32 bit */
6241 i
.types
[op
].bitfield
.disp32
= 1;
6242 i
.types
[op
].bitfield
.disp32s
= 0;
6246 i
.types
[op
].bitfield
.disp32
= 0;
6247 i
.types
[op
].bitfield
.disp32s
= 1;
6250 i
.sib
.index
= i
.index_reg
->reg_num
;
6251 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6253 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6259 if (i
.base_reg
== 0)
6262 if (!i
.disp_operands
)
6264 fake_zero_displacement
= 1;
6265 /* Instructions with VSIB byte need 32bit displacement
6266 if there is no base register. */
6267 if (i
.tm
.opcode_modifier
.vecsib
)
6268 i
.types
[op
].bitfield
.disp32
= 1;
6270 if (i
.index_reg
== 0)
6272 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6273 /* Operand is just <disp> */
6274 if (flag_code
== CODE_64BIT
)
6276 /* 64bit mode overwrites the 32bit absolute
6277 addressing by RIP relative addressing and
6278 absolute addressing is encoded by one of the
6279 redundant SIB forms. */
6280 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6281 i
.sib
.base
= NO_BASE_REGISTER
;
6282 i
.sib
.index
= NO_INDEX_REGISTER
;
6283 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6284 ? disp32s
: disp32
);
6286 else if ((flag_code
== CODE_16BIT
)
6287 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6289 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6290 i
.types
[op
] = disp16
;
6294 i
.rm
.regmem
= NO_BASE_REGISTER
;
6295 i
.types
[op
] = disp32
;
6298 else if (!i
.tm
.opcode_modifier
.vecsib
)
6300 /* !i.base_reg && i.index_reg */
6301 if (i
.index_reg
->reg_num
== RegEiz
6302 || i
.index_reg
->reg_num
== RegRiz
)
6303 i
.sib
.index
= NO_INDEX_REGISTER
;
6305 i
.sib
.index
= i
.index_reg
->reg_num
;
6306 i
.sib
.base
= NO_BASE_REGISTER
;
6307 i
.sib
.scale
= i
.log2_scale_factor
;
6308 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6309 /* No Vec_Disp8 if there is no base. */
6310 i
.types
[op
].bitfield
.vec_disp8
= 0;
6311 i
.types
[op
].bitfield
.disp8
= 0;
6312 i
.types
[op
].bitfield
.disp16
= 0;
6313 i
.types
[op
].bitfield
.disp64
= 0;
6314 if (flag_code
!= CODE_64BIT
)
6316 /* Must be 32 bit */
6317 i
.types
[op
].bitfield
.disp32
= 1;
6318 i
.types
[op
].bitfield
.disp32s
= 0;
6322 i
.types
[op
].bitfield
.disp32
= 0;
6323 i
.types
[op
].bitfield
.disp32s
= 1;
6325 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6329 /* RIP addressing for 64bit mode. */
6330 else if (i
.base_reg
->reg_num
== RegRip
||
6331 i
.base_reg
->reg_num
== RegEip
)
6333 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6334 i
.rm
.regmem
= NO_BASE_REGISTER
;
6335 i
.types
[op
].bitfield
.disp8
= 0;
6336 i
.types
[op
].bitfield
.disp16
= 0;
6337 i
.types
[op
].bitfield
.disp32
= 0;
6338 i
.types
[op
].bitfield
.disp32s
= 1;
6339 i
.types
[op
].bitfield
.disp64
= 0;
6340 i
.types
[op
].bitfield
.vec_disp8
= 0;
6341 i
.flags
[op
] |= Operand_PCrel
;
6342 if (! i
.disp_operands
)
6343 fake_zero_displacement
= 1;
6345 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6347 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6348 switch (i
.base_reg
->reg_num
)
6351 if (i
.index_reg
== 0)
6353 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6354 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6358 if (i
.index_reg
== 0)
6361 if (operand_type_check (i
.types
[op
], disp
) == 0)
6363 /* fake (%bp) into 0(%bp) */
6364 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6365 i
.types
[op
].bitfield
.vec_disp8
= 1;
6367 i
.types
[op
].bitfield
.disp8
= 1;
6368 fake_zero_displacement
= 1;
6371 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6372 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6374 default: /* (%si) -> 4 or (%di) -> 5 */
6375 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6377 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6379 else /* i.base_reg and 32/64 bit mode */
6381 if (flag_code
== CODE_64BIT
6382 && operand_type_check (i
.types
[op
], disp
))
6384 i386_operand_type temp
;
6385 operand_type_set (&temp
, 0);
6386 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6387 temp
.bitfield
.vec_disp8
6388 = i
.types
[op
].bitfield
.vec_disp8
;
6390 if (i
.prefix
[ADDR_PREFIX
] == 0)
6391 i
.types
[op
].bitfield
.disp32s
= 1;
6393 i
.types
[op
].bitfield
.disp32
= 1;
6396 if (!i
.tm
.opcode_modifier
.vecsib
)
6397 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6398 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6400 i
.sib
.base
= i
.base_reg
->reg_num
;
6401 /* x86-64 ignores REX prefix bit here to avoid decoder
6403 if (!(i
.base_reg
->reg_flags
& RegRex
)
6404 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6405 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6407 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6409 fake_zero_displacement
= 1;
6410 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6411 i
.types
[op
].bitfield
.vec_disp8
= 1;
6413 i
.types
[op
].bitfield
.disp8
= 1;
6415 i
.sib
.scale
= i
.log2_scale_factor
;
6416 if (i
.index_reg
== 0)
6418 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6419 /* <disp>(%esp) becomes two byte modrm with no index
6420 register. We've already stored the code for esp
6421 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6422 Any base register besides %esp will not use the
6423 extra modrm byte. */
6424 i
.sib
.index
= NO_INDEX_REGISTER
;
6426 else if (!i
.tm
.opcode_modifier
.vecsib
)
6428 if (i
.index_reg
->reg_num
== RegEiz
6429 || i
.index_reg
->reg_num
== RegRiz
)
6430 i
.sib
.index
= NO_INDEX_REGISTER
;
6432 i
.sib
.index
= i
.index_reg
->reg_num
;
6433 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6434 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6439 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6440 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6444 if (!fake_zero_displacement
6448 fake_zero_displacement
= 1;
6449 if (i
.disp_encoding
== disp_encoding_8bit
)
6450 i
.types
[op
].bitfield
.disp8
= 1;
6452 i
.types
[op
].bitfield
.disp32
= 1;
6454 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6458 if (fake_zero_displacement
)
6460 /* Fakes a zero displacement assuming that i.types[op]
6461 holds the correct displacement size. */
6464 gas_assert (i
.op
[op
].disps
== 0);
6465 exp
= &disp_expressions
[i
.disp_operands
++];
6466 i
.op
[op
].disps
= exp
;
6467 exp
->X_op
= O_constant
;
6468 exp
->X_add_number
= 0;
6469 exp
->X_add_symbol
= (symbolS
*) 0;
6470 exp
->X_op_symbol
= (symbolS
*) 0;
6478 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6480 if (operand_type_check (i
.types
[0], imm
))
6481 i
.vex
.register_specifier
= NULL
;
6484 /* VEX.vvvv encodes one of the sources when the first
6485 operand is not an immediate. */
6486 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6487 i
.vex
.register_specifier
= i
.op
[0].regs
;
6489 i
.vex
.register_specifier
= i
.op
[1].regs
;
6492 /* Destination is a XMM register encoded in the ModRM.reg
6494 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6495 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6498 /* ModRM.rm and VEX.B encodes the other source. */
6499 if (!i
.mem_operands
)
6503 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6504 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6506 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6508 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6512 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6514 i
.vex
.register_specifier
= i
.op
[2].regs
;
6515 if (!i
.mem_operands
)
6518 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6519 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6523 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6524 (if any) based on i.tm.extension_opcode. Again, we must be
6525 careful to make sure that segment/control/debug/test/MMX
6526 registers are coded into the i.rm.reg field. */
6527 else if (i
.reg_operands
)
6530 unsigned int vex_reg
= ~0;
6532 for (op
= 0; op
< i
.operands
; op
++)
6533 if (i
.types
[op
].bitfield
.reg8
6534 || i
.types
[op
].bitfield
.reg16
6535 || i
.types
[op
].bitfield
.reg32
6536 || i
.types
[op
].bitfield
.reg64
6537 || i
.types
[op
].bitfield
.regmmx
6538 || i
.types
[op
].bitfield
.regxmm
6539 || i
.types
[op
].bitfield
.regymm
6540 || i
.types
[op
].bitfield
.regbnd
6541 || i
.types
[op
].bitfield
.regzmm
6542 || i
.types
[op
].bitfield
.regmask
6543 || i
.types
[op
].bitfield
.sreg2
6544 || i
.types
[op
].bitfield
.sreg3
6545 || i
.types
[op
].bitfield
.control
6546 || i
.types
[op
].bitfield
.debug
6547 || i
.types
[op
].bitfield
.test
)
6552 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6554 /* For instructions with VexNDS, the register-only
6555 source operand is encoded in VEX prefix. */
6556 gas_assert (mem
!= (unsigned int) ~0);
6561 gas_assert (op
< i
.operands
);
6565 /* Check register-only source operand when two source
6566 operands are swapped. */
6567 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6568 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6572 gas_assert (mem
== (vex_reg
+ 1)
6573 && op
< i
.operands
);
6578 gas_assert (vex_reg
< i
.operands
);
6582 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6584 /* For instructions with VexNDD, the register destination
6585 is encoded in VEX prefix. */
6586 if (i
.mem_operands
== 0)
6588 /* There is no memory operand. */
6589 gas_assert ((op
+ 2) == i
.operands
);
6594 /* There are only 2 operands. */
6595 gas_assert (op
< 2 && i
.operands
== 2);
6600 gas_assert (op
< i
.operands
);
6602 if (vex_reg
!= (unsigned int) ~0)
6604 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6606 if (type
->bitfield
.reg32
!= 1
6607 && type
->bitfield
.reg64
!= 1
6608 && !operand_type_equal (type
, ®xmm
)
6609 && !operand_type_equal (type
, ®ymm
)
6610 && !operand_type_equal (type
, ®zmm
)
6611 && !operand_type_equal (type
, ®mask
))
6614 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6617 /* Don't set OP operand twice. */
6620 /* If there is an extension opcode to put here, the
6621 register number must be put into the regmem field. */
6622 if (i
.tm
.extension_opcode
!= None
)
6624 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6625 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6627 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6632 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6633 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6635 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6640 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6641 must set it to 3 to indicate this is a register operand
6642 in the regmem field. */
6643 if (!i
.mem_operands
)
6647 /* Fill in i.rm.reg field with extension opcode (if any). */
6648 if (i
.tm
.extension_opcode
!= None
)
6649 i
.rm
.reg
= i
.tm
.extension_opcode
;
6655 output_branch (void)
6661 relax_substateT subtype
;
6665 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6666 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6669 if (i
.prefix
[DATA_PREFIX
] != 0)
6675 /* Pentium4 branch hints. */
6676 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6677 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6682 if (i
.prefix
[REX_PREFIX
] != 0)
6688 /* BND prefixed jump. */
6689 if (i
.prefix
[BND_PREFIX
] != 0)
6691 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6695 if (i
.prefixes
!= 0 && !intel_syntax
)
6696 as_warn (_("skipping prefixes on this instruction"));
6698 /* It's always a symbol; End frag & setup for relax.
6699 Make sure there is enough room in this frag for the largest
6700 instruction we may generate in md_convert_frag. This is 2
6701 bytes for the opcode and room for the prefix and largest
6703 frag_grow (prefix
+ 2 + 4);
6704 /* Prefix and 1 opcode byte go in fr_fix. */
6705 p
= frag_more (prefix
+ 1);
6706 if (i
.prefix
[DATA_PREFIX
] != 0)
6707 *p
++ = DATA_PREFIX_OPCODE
;
6708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6710 *p
++ = i
.prefix
[SEG_PREFIX
];
6711 if (i
.prefix
[REX_PREFIX
] != 0)
6712 *p
++ = i
.prefix
[REX_PREFIX
];
6713 *p
= i
.tm
.base_opcode
;
6715 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6716 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6717 else if (cpu_arch_flags
.bitfield
.cpui386
)
6718 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6720 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6723 sym
= i
.op
[0].disps
->X_add_symbol
;
6724 off
= i
.op
[0].disps
->X_add_number
;
6726 if (i
.op
[0].disps
->X_op
!= O_constant
6727 && i
.op
[0].disps
->X_op
!= O_symbol
)
6729 /* Handle complex expressions. */
6730 sym
= make_expr_symbol (i
.op
[0].disps
);
6734 /* 1 possible extra opcode + 4 byte displacement go in var part.
6735 Pass reloc in fr_var. */
6736 frag_var (rs_machine_dependent
, 5,
6738 || i
.reloc
[0] != NO_RELOC
6739 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6741 : BFD_RELOC_X86_64_PC32_BND
),
6742 subtype
, sym
, off
, p
);
6752 if (i
.tm
.opcode_modifier
.jumpbyte
)
6754 /* This is a loop or jecxz type instruction. */
6756 if (i
.prefix
[ADDR_PREFIX
] != 0)
6758 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6761 /* Pentium4 branch hints. */
6762 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6763 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6765 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6774 if (flag_code
== CODE_16BIT
)
6777 if (i
.prefix
[DATA_PREFIX
] != 0)
6779 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6789 if (i
.prefix
[REX_PREFIX
] != 0)
6791 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6795 /* BND prefixed jump. */
6796 if (i
.prefix
[BND_PREFIX
] != 0)
6798 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6802 if (i
.prefixes
!= 0 && !intel_syntax
)
6803 as_warn (_("skipping prefixes on this instruction"));
6805 p
= frag_more (i
.tm
.opcode_length
+ size
);
6806 switch (i
.tm
.opcode_length
)
6809 *p
++ = i
.tm
.base_opcode
>> 8;
6811 *p
++ = i
.tm
.base_opcode
;
6817 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6818 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6819 (i
.bnd_prefix
!= NULL
6823 /* All jumps handled here are signed, but don't use a signed limit
6824 check for 32 and 16 bit jumps as we want to allow wrap around at
6825 4G and 64k respectively. */
6827 fixP
->fx_signed
= 1;
6831 output_interseg_jump (void)
6839 if (flag_code
== CODE_16BIT
)
6843 if (i
.prefix
[DATA_PREFIX
] != 0)
6849 if (i
.prefix
[REX_PREFIX
] != 0)
6859 if (i
.prefixes
!= 0 && !intel_syntax
)
6860 as_warn (_("skipping prefixes on this instruction"));
6862 /* 1 opcode; 2 segment; offset */
6863 p
= frag_more (prefix
+ 1 + 2 + size
);
6865 if (i
.prefix
[DATA_PREFIX
] != 0)
6866 *p
++ = DATA_PREFIX_OPCODE
;
6868 if (i
.prefix
[REX_PREFIX
] != 0)
6869 *p
++ = i
.prefix
[REX_PREFIX
];
6871 *p
++ = i
.tm
.base_opcode
;
6872 if (i
.op
[1].imms
->X_op
== O_constant
)
6874 offsetT n
= i
.op
[1].imms
->X_add_number
;
6877 && !fits_in_unsigned_word (n
)
6878 && !fits_in_signed_word (n
))
6880 as_bad (_("16-bit jump out of range"));
6883 md_number_to_chars (p
, n
, size
);
6886 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6887 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6888 if (i
.op
[0].imms
->X_op
!= O_constant
)
6889 as_bad (_("can't handle non absolute segment in `%s'"),
6891 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6897 fragS
*insn_start_frag
;
6898 offsetT insn_start_off
;
6900 /* Tie dwarf2 debug info to the address at the start of the insn.
6901 We can't do this after the insn has been output as the current
6902 frag may have been closed off. eg. by frag_var. */
6903 dwarf2_emit_insn (0);
6905 insn_start_frag
= frag_now
;
6906 insn_start_off
= frag_now_fix ();
6909 if (i
.tm
.opcode_modifier
.jump
)
6911 else if (i
.tm
.opcode_modifier
.jumpbyte
6912 || i
.tm
.opcode_modifier
.jumpdword
)
6914 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6915 output_interseg_jump ();
6918 /* Output normal instructions here. */
6922 unsigned int prefix
;
6924 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6925 don't need the explicit prefix. */
6926 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6928 switch (i
.tm
.opcode_length
)
6931 if (i
.tm
.base_opcode
& 0xff000000)
6933 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6938 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6940 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6941 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6944 if (prefix
!= REPE_PREFIX_OPCODE
6945 || (i
.prefix
[REP_PREFIX
]
6946 != REPE_PREFIX_OPCODE
))
6947 add_prefix (prefix
);
6950 add_prefix (prefix
);
6959 /* The prefix bytes. */
6960 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6962 FRAG_APPEND_1_CHAR (*q
);
6966 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6971 /* REX byte is encoded in VEX prefix. */
6975 FRAG_APPEND_1_CHAR (*q
);
6978 /* There should be no other prefixes for instructions
6983 /* For EVEX instructions i.vrex should become 0 after
6984 build_evex_prefix. For VEX instructions upper 16 registers
6985 aren't available, so VREX should be 0. */
6988 /* Now the VEX prefix. */
6989 p
= frag_more (i
.vex
.length
);
6990 for (j
= 0; j
< i
.vex
.length
; j
++)
6991 p
[j
] = i
.vex
.bytes
[j
];
6994 /* Now the opcode; be careful about word order here! */
6995 if (i
.tm
.opcode_length
== 1)
6997 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7001 switch (i
.tm
.opcode_length
)
7005 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7006 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7010 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7020 /* Put out high byte first: can't use md_number_to_chars! */
7021 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7022 *p
= i
.tm
.base_opcode
& 0xff;
7025 /* Now the modrm byte and sib byte (if present). */
7026 if (i
.tm
.opcode_modifier
.modrm
)
7028 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7031 /* If i.rm.regmem == ESP (4)
7032 && i.rm.mode != (Register mode)
7034 ==> need second modrm byte. */
7035 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7037 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7038 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7040 | i
.sib
.scale
<< 6));
7043 if (i
.disp_operands
)
7044 output_disp (insn_start_frag
, insn_start_off
);
7047 output_imm (insn_start_frag
, insn_start_off
);
7053 pi ("" /*line*/, &i
);
7055 #endif /* DEBUG386 */
7058 /* Return the size of the displacement operand N. */
7061 disp_size (unsigned int n
)
7065 /* Vec_Disp8 has to be 8bit. */
7066 if (i
.types
[n
].bitfield
.vec_disp8
)
7068 else if (i
.types
[n
].bitfield
.disp64
)
7070 else if (i
.types
[n
].bitfield
.disp8
)
7072 else if (i
.types
[n
].bitfield
.disp16
)
7077 /* Return the size of the immediate operand N. */
7080 imm_size (unsigned int n
)
7083 if (i
.types
[n
].bitfield
.imm64
)
7085 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7087 else if (i
.types
[n
].bitfield
.imm16
)
7093 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7098 for (n
= 0; n
< i
.operands
; n
++)
7100 if (i
.types
[n
].bitfield
.vec_disp8
7101 || operand_type_check (i
.types
[n
], disp
))
7103 if (i
.op
[n
].disps
->X_op
== O_constant
)
7105 int size
= disp_size (n
);
7106 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7108 if (i
.types
[n
].bitfield
.vec_disp8
)
7110 val
= offset_in_range (val
, size
);
7111 p
= frag_more (size
);
7112 md_number_to_chars (p
, val
, size
);
7116 enum bfd_reloc_code_real reloc_type
;
7117 int size
= disp_size (n
);
7118 int sign
= i
.types
[n
].bitfield
.disp32s
;
7119 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7121 /* We can't have 8 bit displacement here. */
7122 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7124 /* The PC relative address is computed relative
7125 to the instruction boundary, so in case immediate
7126 fields follows, we need to adjust the value. */
7127 if (pcrel
&& i
.imm_operands
)
7132 for (n1
= 0; n1
< i
.operands
; n1
++)
7133 if (operand_type_check (i
.types
[n1
], imm
))
7135 /* Only one immediate is allowed for PC
7136 relative address. */
7137 gas_assert (sz
== 0);
7139 i
.op
[n
].disps
->X_add_number
-= sz
;
7141 /* We should find the immediate. */
7142 gas_assert (sz
!= 0);
7145 p
= frag_more (size
);
7146 reloc_type
= reloc (size
, pcrel
, sign
,
7147 (i
.bnd_prefix
!= NULL
7151 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7152 && (((reloc_type
== BFD_RELOC_32
7153 || reloc_type
== BFD_RELOC_X86_64_32S
7154 || (reloc_type
== BFD_RELOC_64
7156 && (i
.op
[n
].disps
->X_op
== O_symbol
7157 || (i
.op
[n
].disps
->X_op
== O_add
7158 && ((symbol_get_value_expression
7159 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7161 || reloc_type
== BFD_RELOC_32_PCREL
))
7165 if (insn_start_frag
== frag_now
)
7166 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7171 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7172 for (fr
= insn_start_frag
->fr_next
;
7173 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7175 add
+= p
- frag_now
->fr_literal
;
7180 reloc_type
= BFD_RELOC_386_GOTPC
;
7181 i
.op
[n
].imms
->X_add_number
+= add
;
7183 else if (reloc_type
== BFD_RELOC_64
)
7184 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7186 /* Don't do the adjustment for x86-64, as there
7187 the pcrel addressing is relative to the _next_
7188 insn, and that is taken care of in other code. */
7189 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7191 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7192 i
.op
[n
].disps
, pcrel
, reloc_type
);
7199 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7204 for (n
= 0; n
< i
.operands
; n
++)
7206 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7207 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7210 if (operand_type_check (i
.types
[n
], imm
))
7212 if (i
.op
[n
].imms
->X_op
== O_constant
)
7214 int size
= imm_size (n
);
7217 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7219 p
= frag_more (size
);
7220 md_number_to_chars (p
, val
, size
);
7224 /* Not absolute_section.
7225 Need a 32-bit fixup (don't support 8bit
7226 non-absolute imms). Try to support other
7228 enum bfd_reloc_code_real reloc_type
;
7229 int size
= imm_size (n
);
7232 if (i
.types
[n
].bitfield
.imm32s
7233 && (i
.suffix
== QWORD_MNEM_SUFFIX
7234 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7239 p
= frag_more (size
);
7240 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7242 /* This is tough to explain. We end up with this one if we
7243 * have operands that look like
7244 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7245 * obtain the absolute address of the GOT, and it is strongly
7246 * preferable from a performance point of view to avoid using
7247 * a runtime relocation for this. The actual sequence of
7248 * instructions often look something like:
7253 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7255 * The call and pop essentially return the absolute address
7256 * of the label .L66 and store it in %ebx. The linker itself
7257 * will ultimately change the first operand of the addl so
7258 * that %ebx points to the GOT, but to keep things simple, the
7259 * .o file must have this operand set so that it generates not
7260 * the absolute address of .L66, but the absolute address of
7261 * itself. This allows the linker itself simply treat a GOTPC
7262 * relocation as asking for a pcrel offset to the GOT to be
7263 * added in, and the addend of the relocation is stored in the
7264 * operand field for the instruction itself.
7266 * Our job here is to fix the operand so that it would add
7267 * the correct offset so that %ebx would point to itself. The
7268 * thing that is tricky is that .-.L66 will point to the
7269 * beginning of the instruction, so we need to further modify
7270 * the operand so that it will point to itself. There are
7271 * other cases where you have something like:
7273 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7275 * and here no correction would be required. Internally in
7276 * the assembler we treat operands of this form as not being
7277 * pcrel since the '.' is explicitly mentioned, and I wonder
7278 * whether it would simplify matters to do it this way. Who
7279 * knows. In earlier versions of the PIC patches, the
7280 * pcrel_adjust field was used to store the correction, but
7281 * since the expression is not pcrel, I felt it would be
7282 * confusing to do it this way. */
7284 if ((reloc_type
== BFD_RELOC_32
7285 || reloc_type
== BFD_RELOC_X86_64_32S
7286 || reloc_type
== BFD_RELOC_64
)
7288 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7289 && (i
.op
[n
].imms
->X_op
== O_symbol
7290 || (i
.op
[n
].imms
->X_op
== O_add
7291 && ((symbol_get_value_expression
7292 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7297 if (insn_start_frag
== frag_now
)
7298 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7303 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7304 for (fr
= insn_start_frag
->fr_next
;
7305 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7307 add
+= p
- frag_now
->fr_literal
;
7311 reloc_type
= BFD_RELOC_386_GOTPC
;
7313 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7315 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7316 i
.op
[n
].imms
->X_add_number
+= add
;
7318 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7319 i
.op
[n
].imms
, 0, reloc_type
);
7325 /* x86_cons_fix_new is called via the expression parsing code when a
7326 reloc is needed. We use this hook to get the correct .got reloc. */
7327 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
7328 static int cons_sign
= -1;
7331 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7334 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, 0, got_reloc
);
7336 got_reloc
= NO_RELOC
;
7339 if (exp
->X_op
== O_secrel
)
7341 exp
->X_op
= O_symbol
;
7342 r
= BFD_RELOC_32_SECREL
;
7346 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7349 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7350 purpose of the `.dc.a' internal pseudo-op. */
7353 x86_address_bytes (void)
7355 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7357 return stdoutput
->arch_info
->bits_per_address
/ 8;
7360 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7362 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7364 /* Parse operands of the form
7365 <symbol>@GOTOFF+<nnn>
7366 and similar .plt or .got references.
7368 If we find one, set up the correct relocation in RELOC and copy the
7369 input string, minus the `@GOTOFF' into a malloc'd buffer for
7370 parsing by the calling routine. Return this buffer, and if ADJUST
7371 is non-null set it to the length of the string we removed from the
7372 input line. Otherwise return NULL. */
7374 lex_got (enum bfd_reloc_code_real
*rel
,
7376 i386_operand_type
*types
,
7379 /* Some of the relocations depend on the size of what field is to
7380 be relocated. But in our callers i386_immediate and i386_displacement
7381 we don't yet know the operand size (this will be set by insn
7382 matching). Hence we record the word32 relocation here,
7383 and adjust the reloc according to the real size in reloc(). */
7384 static const struct {
7387 const enum bfd_reloc_code_real rel
[2];
7388 const i386_operand_type types64
;
7390 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7391 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7393 OPERAND_TYPE_IMM32_64
},
7395 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7396 BFD_RELOC_X86_64_PLTOFF64
},
7397 OPERAND_TYPE_IMM64
},
7398 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7399 BFD_RELOC_X86_64_PLT32
},
7400 OPERAND_TYPE_IMM32_32S_DISP32
},
7401 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7402 BFD_RELOC_X86_64_GOTPLT64
},
7403 OPERAND_TYPE_IMM64_DISP64
},
7404 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7405 BFD_RELOC_X86_64_GOTOFF64
},
7406 OPERAND_TYPE_IMM64_DISP64
},
7407 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7408 BFD_RELOC_X86_64_GOTPCREL
},
7409 OPERAND_TYPE_IMM32_32S_DISP32
},
7410 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7411 BFD_RELOC_X86_64_TLSGD
},
7412 OPERAND_TYPE_IMM32_32S_DISP32
},
7413 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7414 _dummy_first_bfd_reloc_code_real
},
7415 OPERAND_TYPE_NONE
},
7416 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7417 BFD_RELOC_X86_64_TLSLD
},
7418 OPERAND_TYPE_IMM32_32S_DISP32
},
7419 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7420 BFD_RELOC_X86_64_GOTTPOFF
},
7421 OPERAND_TYPE_IMM32_32S_DISP32
},
7422 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7423 BFD_RELOC_X86_64_TPOFF32
},
7424 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7425 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7426 _dummy_first_bfd_reloc_code_real
},
7427 OPERAND_TYPE_NONE
},
7428 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7429 BFD_RELOC_X86_64_DTPOFF32
},
7430 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7431 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7432 _dummy_first_bfd_reloc_code_real
},
7433 OPERAND_TYPE_NONE
},
7434 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7435 _dummy_first_bfd_reloc_code_real
},
7436 OPERAND_TYPE_NONE
},
7437 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7438 BFD_RELOC_X86_64_GOT32
},
7439 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7440 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7441 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7442 OPERAND_TYPE_IMM32_32S_DISP32
},
7443 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7444 BFD_RELOC_X86_64_TLSDESC_CALL
},
7445 OPERAND_TYPE_IMM32_32S_DISP32
},
7450 #if defined (OBJ_MAYBE_ELF)
7455 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7456 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7459 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7461 int len
= gotrel
[j
].len
;
7462 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7464 if (gotrel
[j
].rel
[object_64bit
] != 0)
7467 char *tmpbuf
, *past_reloc
;
7469 *rel
= gotrel
[j
].rel
[object_64bit
];
7473 if (flag_code
!= CODE_64BIT
)
7475 types
->bitfield
.imm32
= 1;
7476 types
->bitfield
.disp32
= 1;
7479 *types
= gotrel
[j
].types64
;
7482 if (j
!= 0 && GOT_symbol
== NULL
)
7483 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7485 /* The length of the first part of our input line. */
7486 first
= cp
- input_line_pointer
;
7488 /* The second part goes from after the reloc token until
7489 (and including) an end_of_line char or comma. */
7490 past_reloc
= cp
+ 1 + len
;
7492 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7494 second
= cp
+ 1 - past_reloc
;
7496 /* Allocate and copy string. The trailing NUL shouldn't
7497 be necessary, but be safe. */
7498 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7499 memcpy (tmpbuf
, input_line_pointer
, first
);
7500 if (second
!= 0 && *past_reloc
!= ' ')
7501 /* Replace the relocation token with ' ', so that
7502 errors like foo@GOTOFF1 will be detected. */
7503 tmpbuf
[first
++] = ' ';
7505 /* Increment length by 1 if the relocation token is
7510 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7511 tmpbuf
[first
+ second
] = '\0';
7512 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7513 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7517 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7518 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7523 /* Might be a symbol version string. Don't as_bad here. */
7532 /* Parse operands of the form
7533 <symbol>@SECREL32+<nnn>
7535 If we find one, set up the correct relocation in RELOC and copy the
7536 input string, minus the `@SECREL32' into a malloc'd buffer for
7537 parsing by the calling routine. Return this buffer, and if ADJUST
7538 is non-null set it to the length of the string we removed from the
7539 input line. Otherwise return NULL.
7541 This function is copied from the ELF version above adjusted for PE targets. */
7544 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7545 int *adjust ATTRIBUTE_UNUSED
,
7546 i386_operand_type
*types
,
7547 int bnd_prefix ATTRIBUTE_UNUSED
)
7553 const enum bfd_reloc_code_real rel
[2];
7554 const i386_operand_type types64
;
7558 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7559 BFD_RELOC_32_SECREL
},
7560 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7566 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7567 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7570 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7572 int len
= gotrel
[j
].len
;
7574 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7576 if (gotrel
[j
].rel
[object_64bit
] != 0)
7579 char *tmpbuf
, *past_reloc
;
7581 *rel
= gotrel
[j
].rel
[object_64bit
];
7587 if (flag_code
!= CODE_64BIT
)
7589 types
->bitfield
.imm32
= 1;
7590 types
->bitfield
.disp32
= 1;
7593 *types
= gotrel
[j
].types64
;
7596 /* The length of the first part of our input line. */
7597 first
= cp
- input_line_pointer
;
7599 /* The second part goes from after the reloc token until
7600 (and including) an end_of_line char or comma. */
7601 past_reloc
= cp
+ 1 + len
;
7603 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7605 second
= cp
+ 1 - past_reloc
;
7607 /* Allocate and copy string. The trailing NUL shouldn't
7608 be necessary, but be safe. */
7609 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7610 memcpy (tmpbuf
, input_line_pointer
, first
);
7611 if (second
!= 0 && *past_reloc
!= ' ')
7612 /* Replace the relocation token with ' ', so that
7613 errors like foo@SECLREL321 will be detected. */
7614 tmpbuf
[first
++] = ' ';
7615 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7616 tmpbuf
[first
+ second
] = '\0';
7620 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7621 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7626 /* Might be a symbol version string. Don't as_bad here. */
7633 x86_cons (expressionS
*exp
, int size
)
7635 intel_syntax
= -intel_syntax
;
7638 if (size
== 4 || (object_64bit
&& size
== 8))
7640 /* Handle @GOTOFF and the like in an expression. */
7642 char *gotfree_input_line
;
7645 save
= input_line_pointer
;
7646 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7647 if (gotfree_input_line
)
7648 input_line_pointer
= gotfree_input_line
;
7652 if (gotfree_input_line
)
7654 /* expression () has merrily parsed up to the end of line,
7655 or a comma - in the wrong buffer. Transfer how far
7656 input_line_pointer has moved to the right buffer. */
7657 input_line_pointer
= (save
7658 + (input_line_pointer
- gotfree_input_line
)
7660 free (gotfree_input_line
);
7661 if (exp
->X_op
== O_constant
7662 || exp
->X_op
== O_absent
7663 || exp
->X_op
== O_illegal
7664 || exp
->X_op
== O_register
7665 || exp
->X_op
== O_big
)
7667 char c
= *input_line_pointer
;
7668 *input_line_pointer
= 0;
7669 as_bad (_("missing or invalid expression `%s'"), save
);
7670 *input_line_pointer
= c
;
7677 intel_syntax
= -intel_syntax
;
7680 i386_intel_simplify (exp
);
7684 signed_cons (int size
)
7686 if (flag_code
== CODE_64BIT
)
7694 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7701 if (exp
.X_op
== O_symbol
)
7702 exp
.X_op
= O_secrel
;
7704 emit_expr (&exp
, 4);
7706 while (*input_line_pointer
++ == ',');
7708 input_line_pointer
--;
7709 demand_empty_rest_of_line ();
7713 /* Handle Vector operations. */
7716 check_VecOperations (char *op_string
, char *op_end
)
7718 const reg_entry
*mask
;
7723 && (op_end
== NULL
|| op_string
< op_end
))
7726 if (*op_string
== '{')
7730 /* Check broadcasts. */
7731 if (strncmp (op_string
, "1to", 3) == 0)
7736 goto duplicated_vec_op
;
7739 if (*op_string
== '8')
7740 bcst_type
= BROADCAST_1TO8
;
7741 else if (*op_string
== '1'
7742 && *(op_string
+1) == '6')
7744 bcst_type
= BROADCAST_1TO16
;
7749 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7754 broadcast_op
.type
= bcst_type
;
7755 broadcast_op
.operand
= this_operand
;
7756 i
.broadcast
= &broadcast_op
;
7758 /* Check masking operation. */
7759 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7761 /* k0 can't be used for write mask. */
7762 if (mask
->reg_num
== 0)
7764 as_bad (_("`%s' can't be used for write mask"),
7771 mask_op
.mask
= mask
;
7772 mask_op
.zeroing
= 0;
7773 mask_op
.operand
= this_operand
;
7779 goto duplicated_vec_op
;
7781 i
.mask
->mask
= mask
;
7783 /* Only "{z}" is allowed here. No need to check
7784 zeroing mask explicitly. */
7785 if (i
.mask
->operand
!= this_operand
)
7787 as_bad (_("invalid write mask `%s'"), saved
);
7794 /* Check zeroing-flag for masking operation. */
7795 else if (*op_string
== 'z')
7799 mask_op
.mask
= NULL
;
7800 mask_op
.zeroing
= 1;
7801 mask_op
.operand
= this_operand
;
7806 if (i
.mask
->zeroing
)
7809 as_bad (_("duplicated `%s'"), saved
);
7813 i
.mask
->zeroing
= 1;
7815 /* Only "{%k}" is allowed here. No need to check mask
7816 register explicitly. */
7817 if (i
.mask
->operand
!= this_operand
)
7819 as_bad (_("invalid zeroing-masking `%s'"),
7828 goto unknown_vec_op
;
7830 if (*op_string
!= '}')
7832 as_bad (_("missing `}' in `%s'"), saved
);
7839 /* We don't know this one. */
7840 as_bad (_("unknown vector operation: `%s'"), saved
);
7848 i386_immediate (char *imm_start
)
7850 char *save_input_line_pointer
;
7851 char *gotfree_input_line
;
7854 i386_operand_type types
;
7856 operand_type_set (&types
, ~0);
7858 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7860 as_bad (_("at most %d immediate operands are allowed"),
7861 MAX_IMMEDIATE_OPERANDS
);
7865 exp
= &im_expressions
[i
.imm_operands
++];
7866 i
.op
[this_operand
].imms
= exp
;
7868 if (is_space_char (*imm_start
))
7871 save_input_line_pointer
= input_line_pointer
;
7872 input_line_pointer
= imm_start
;
7874 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7875 (i
.bnd_prefix
!= NULL
7876 || add_bnd_prefix
));
7877 if (gotfree_input_line
)
7878 input_line_pointer
= gotfree_input_line
;
7880 exp_seg
= expression (exp
);
7884 /* Handle vector operations. */
7885 if (*input_line_pointer
== '{')
7887 input_line_pointer
= check_VecOperations (input_line_pointer
,
7889 if (input_line_pointer
== NULL
)
7893 if (*input_line_pointer
)
7894 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7896 input_line_pointer
= save_input_line_pointer
;
7897 if (gotfree_input_line
)
7899 free (gotfree_input_line
);
7901 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7902 exp
->X_op
= O_illegal
;
7905 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7909 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7910 i386_operand_type types
, const char *imm_start
)
7912 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7915 as_bad (_("missing or invalid immediate expression `%s'"),
7919 else if (exp
->X_op
== O_constant
)
7921 /* Size it properly later. */
7922 i
.types
[this_operand
].bitfield
.imm64
= 1;
7923 /* If not 64bit, sign extend val. */
7924 if (flag_code
!= CODE_64BIT
7925 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7927 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7929 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7930 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7931 && exp_seg
!= absolute_section
7932 && exp_seg
!= text_section
7933 && exp_seg
!= data_section
7934 && exp_seg
!= bss_section
7935 && exp_seg
!= undefined_section
7936 && !bfd_is_com_section (exp_seg
))
7938 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7942 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7945 as_bad (_("illegal immediate register operand %s"), imm_start
);
7950 /* This is an address. The size of the address will be
7951 determined later, depending on destination register,
7952 suffix, or the default for the section. */
7953 i
.types
[this_operand
].bitfield
.imm8
= 1;
7954 i
.types
[this_operand
].bitfield
.imm16
= 1;
7955 i
.types
[this_operand
].bitfield
.imm32
= 1;
7956 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7957 i
.types
[this_operand
].bitfield
.imm64
= 1;
7958 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7966 i386_scale (char *scale
)
7969 char *save
= input_line_pointer
;
7971 input_line_pointer
= scale
;
7972 val
= get_absolute_expression ();
7977 i
.log2_scale_factor
= 0;
7980 i
.log2_scale_factor
= 1;
7983 i
.log2_scale_factor
= 2;
7986 i
.log2_scale_factor
= 3;
7990 char sep
= *input_line_pointer
;
7992 *input_line_pointer
= '\0';
7993 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7995 *input_line_pointer
= sep
;
7996 input_line_pointer
= save
;
8000 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8002 as_warn (_("scale factor of %d without an index register"),
8003 1 << i
.log2_scale_factor
);
8004 i
.log2_scale_factor
= 0;
8006 scale
= input_line_pointer
;
8007 input_line_pointer
= save
;
8012 i386_displacement (char *disp_start
, char *disp_end
)
8016 char *save_input_line_pointer
;
8017 char *gotfree_input_line
;
8019 i386_operand_type bigdisp
, types
= anydisp
;
8022 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8024 as_bad (_("at most %d displacement operands are allowed"),
8025 MAX_MEMORY_OPERANDS
);
8029 operand_type_set (&bigdisp
, 0);
8030 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8031 || (!current_templates
->start
->opcode_modifier
.jump
8032 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8034 bigdisp
.bitfield
.disp32
= 1;
8035 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8036 if (flag_code
== CODE_64BIT
)
8040 bigdisp
.bitfield
.disp32s
= 1;
8041 bigdisp
.bitfield
.disp64
= 1;
8044 else if ((flag_code
== CODE_16BIT
) ^ override
)
8046 bigdisp
.bitfield
.disp32
= 0;
8047 bigdisp
.bitfield
.disp16
= 1;
8052 /* For PC-relative branches, the width of the displacement
8053 is dependent upon data size, not address size. */
8054 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8055 if (flag_code
== CODE_64BIT
)
8057 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8058 bigdisp
.bitfield
.disp16
= 1;
8061 bigdisp
.bitfield
.disp32
= 1;
8062 bigdisp
.bitfield
.disp32s
= 1;
8068 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8070 : LONG_MNEM_SUFFIX
));
8071 bigdisp
.bitfield
.disp32
= 1;
8072 if ((flag_code
== CODE_16BIT
) ^ override
)
8074 bigdisp
.bitfield
.disp32
= 0;
8075 bigdisp
.bitfield
.disp16
= 1;
8079 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8082 exp
= &disp_expressions
[i
.disp_operands
];
8083 i
.op
[this_operand
].disps
= exp
;
8085 save_input_line_pointer
= input_line_pointer
;
8086 input_line_pointer
= disp_start
;
8087 END_STRING_AND_SAVE (disp_end
);
8089 #ifndef GCC_ASM_O_HACK
8090 #define GCC_ASM_O_HACK 0
8093 END_STRING_AND_SAVE (disp_end
+ 1);
8094 if (i
.types
[this_operand
].bitfield
.baseIndex
8095 && displacement_string_end
[-1] == '+')
8097 /* This hack is to avoid a warning when using the "o"
8098 constraint within gcc asm statements.
8101 #define _set_tssldt_desc(n,addr,limit,type) \
8102 __asm__ __volatile__ ( \
8104 "movw %w1,2+%0\n\t" \
8106 "movb %b1,4+%0\n\t" \
8107 "movb %4,5+%0\n\t" \
8108 "movb $0,6+%0\n\t" \
8109 "movb %h1,7+%0\n\t" \
8111 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8113 This works great except that the output assembler ends
8114 up looking a bit weird if it turns out that there is
8115 no offset. You end up producing code that looks like:
8128 So here we provide the missing zero. */
8130 *displacement_string_end
= '0';
8133 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8134 (i
.bnd_prefix
!= NULL
8135 || add_bnd_prefix
));
8136 if (gotfree_input_line
)
8137 input_line_pointer
= gotfree_input_line
;
8139 exp_seg
= expression (exp
);
8142 if (*input_line_pointer
)
8143 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8145 RESTORE_END_STRING (disp_end
+ 1);
8147 input_line_pointer
= save_input_line_pointer
;
8148 if (gotfree_input_line
)
8150 free (gotfree_input_line
);
8152 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8153 exp
->X_op
= O_illegal
;
8156 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8158 RESTORE_END_STRING (disp_end
);
8164 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8165 i386_operand_type types
, const char *disp_start
)
8167 i386_operand_type bigdisp
;
8170 /* We do this to make sure that the section symbol is in
8171 the symbol table. We will ultimately change the relocation
8172 to be relative to the beginning of the section. */
8173 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8174 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8175 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8177 if (exp
->X_op
!= O_symbol
)
8180 if (S_IS_LOCAL (exp
->X_add_symbol
)
8181 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8182 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8183 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8184 exp
->X_op
= O_subtract
;
8185 exp
->X_op_symbol
= GOT_symbol
;
8186 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8187 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8188 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8189 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8191 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8194 else if (exp
->X_op
== O_absent
8195 || exp
->X_op
== O_illegal
8196 || exp
->X_op
== O_big
)
8199 as_bad (_("missing or invalid displacement expression `%s'"),
8204 else if (flag_code
== CODE_64BIT
8205 && !i
.prefix
[ADDR_PREFIX
]
8206 && exp
->X_op
== O_constant
)
8208 /* Since displacement is signed extended to 64bit, don't allow
8209 disp32 and turn off disp32s if they are out of range. */
8210 i
.types
[this_operand
].bitfield
.disp32
= 0;
8211 if (!fits_in_signed_long (exp
->X_add_number
))
8213 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8214 if (i
.types
[this_operand
].bitfield
.baseindex
)
8216 as_bad (_("0x%lx out range of signed 32bit displacement"),
8217 (long) exp
->X_add_number
);
8223 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8224 else if (exp
->X_op
!= O_constant
8225 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8226 && exp_seg
!= absolute_section
8227 && exp_seg
!= text_section
8228 && exp_seg
!= data_section
8229 && exp_seg
!= bss_section
8230 && exp_seg
!= undefined_section
8231 && !bfd_is_com_section (exp_seg
))
8233 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8238 /* Check if this is a displacement only operand. */
8239 bigdisp
= i
.types
[this_operand
];
8240 bigdisp
.bitfield
.disp8
= 0;
8241 bigdisp
.bitfield
.disp16
= 0;
8242 bigdisp
.bitfield
.disp32
= 0;
8243 bigdisp
.bitfield
.disp32s
= 0;
8244 bigdisp
.bitfield
.disp64
= 0;
8245 if (operand_type_all_zero (&bigdisp
))
8246 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8252 /* Make sure the memory operand we've been dealt is valid.
8253 Return 1 on success, 0 on a failure. */
8256 i386_index_check (const char *operand_string
)
8258 const char *kind
= "base/index";
8259 enum flag_code addr_mode
;
8261 if (i
.prefix
[ADDR_PREFIX
])
8262 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8265 addr_mode
= flag_code
;
8267 #if INFER_ADDR_PREFIX
8268 if (i
.mem_operands
== 0)
8270 /* Infer address prefix from the first memory operand. */
8271 const reg_entry
*addr_reg
= i
.base_reg
;
8273 if (addr_reg
== NULL
)
8274 addr_reg
= i
.index_reg
;
8278 if (addr_reg
->reg_num
== RegEip
8279 || addr_reg
->reg_num
== RegEiz
8280 || addr_reg
->reg_type
.bitfield
.reg32
)
8281 addr_mode
= CODE_32BIT
;
8282 else if (flag_code
!= CODE_64BIT
8283 && addr_reg
->reg_type
.bitfield
.reg16
)
8284 addr_mode
= CODE_16BIT
;
8286 if (addr_mode
!= flag_code
)
8288 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8290 /* Change the size of any displacement too. At most one
8291 of Disp16 or Disp32 is set.
8292 FIXME. There doesn't seem to be any real need for
8293 separate Disp16 and Disp32 flags. The same goes for
8294 Imm16 and Imm32. Removing them would probably clean
8295 up the code quite a lot. */
8296 if (flag_code
!= CODE_64BIT
8297 && (i
.types
[this_operand
].bitfield
.disp16
8298 || i
.types
[this_operand
].bitfield
.disp32
))
8299 i
.types
[this_operand
]
8300 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8307 if (current_templates
->start
->opcode_modifier
.isstring
8308 && !current_templates
->start
->opcode_modifier
.immext
8309 && (current_templates
->end
[-1].opcode_modifier
.isstring
8312 /* Memory operands of string insns are special in that they only allow
8313 a single register (rDI, rSI, or rBX) as their memory address. */
8314 const reg_entry
*expected_reg
;
8315 static const char *di_si
[][2] =
8321 static const char *bx
[] = { "ebx", "bx", "rbx" };
8323 kind
= "string address";
8325 if (current_templates
->start
->opcode_modifier
.w
)
8327 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8329 if (!type
.bitfield
.baseindex
8330 || ((!i
.mem_operands
!= !intel_syntax
)
8331 && current_templates
->end
[-1].operand_types
[1]
8332 .bitfield
.baseindex
))
8333 type
= current_templates
->end
[-1].operand_types
[1];
8334 expected_reg
= hash_find (reg_hash
,
8335 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8339 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8341 if (i
.base_reg
!= expected_reg
8343 || operand_type_check (i
.types
[this_operand
], disp
))
8345 /* The second memory operand must have the same size as
8349 && !((addr_mode
== CODE_64BIT
8350 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8351 || (addr_mode
== CODE_32BIT
8352 ? i
.base_reg
->reg_type
.bitfield
.reg32
8353 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8356 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8358 intel_syntax
? '[' : '(',
8360 expected_reg
->reg_name
,
8361 intel_syntax
? ']' : ')');
8368 as_bad (_("`%s' is not a valid %s expression"),
8369 operand_string
, kind
);
8374 if (addr_mode
!= CODE_16BIT
)
8376 /* 32-bit/64-bit checks. */
8378 && (addr_mode
== CODE_64BIT
8379 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8380 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8382 || (i
.base_reg
->reg_num
8383 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8385 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8386 && !i
.index_reg
->reg_type
.bitfield
.regymm
8387 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8388 && ((addr_mode
== CODE_64BIT
8389 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8390 || i
.index_reg
->reg_num
== RegRiz
)
8391 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8392 || i
.index_reg
->reg_num
== RegEiz
))
8393 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8398 /* 16-bit checks. */
8400 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8401 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8403 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8404 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8406 && i
.base_reg
->reg_num
< 6
8407 && i
.index_reg
->reg_num
>= 6
8408 && i
.log2_scale_factor
== 0))))
8415 /* Handle vector immediates. */
8418 RC_SAE_immediate (const char *imm_start
)
8420 unsigned int match_found
, j
;
8421 const char *pstr
= imm_start
;
8429 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8431 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8435 rc_op
.type
= RC_NamesTable
[j
].type
;
8436 rc_op
.operand
= this_operand
;
8437 i
.rounding
= &rc_op
;
8441 as_bad (_("duplicated `%s'"), imm_start
);
8444 pstr
+= RC_NamesTable
[j
].len
;
8454 as_bad (_("Missing '}': '%s'"), imm_start
);
8457 /* RC/SAE immediate string should contain nothing more. */;
8460 as_bad (_("Junk after '}': '%s'"), imm_start
);
8464 exp
= &im_expressions
[i
.imm_operands
++];
8465 i
.op
[this_operand
].imms
= exp
;
8467 exp
->X_op
= O_constant
;
8468 exp
->X_add_number
= 0;
8469 exp
->X_add_symbol
= (symbolS
*) 0;
8470 exp
->X_op_symbol
= (symbolS
*) 0;
8472 i
.types
[this_operand
].bitfield
.imm8
= 1;
8476 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8480 i386_att_operand (char *operand_string
)
8484 char *op_string
= operand_string
;
8486 if (is_space_char (*op_string
))
8489 /* We check for an absolute prefix (differentiating,
8490 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8491 if (*op_string
== ABSOLUTE_PREFIX
)
8494 if (is_space_char (*op_string
))
8496 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8499 /* Check if operand is a register. */
8500 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8502 i386_operand_type temp
;
8504 /* Check for a segment override by searching for ':' after a
8505 segment register. */
8507 if (is_space_char (*op_string
))
8509 if (*op_string
== ':'
8510 && (r
->reg_type
.bitfield
.sreg2
8511 || r
->reg_type
.bitfield
.sreg3
))
8516 i
.seg
[i
.mem_operands
] = &es
;
8519 i
.seg
[i
.mem_operands
] = &cs
;
8522 i
.seg
[i
.mem_operands
] = &ss
;
8525 i
.seg
[i
.mem_operands
] = &ds
;
8528 i
.seg
[i
.mem_operands
] = &fs
;
8531 i
.seg
[i
.mem_operands
] = &gs
;
8535 /* Skip the ':' and whitespace. */
8537 if (is_space_char (*op_string
))
8540 if (!is_digit_char (*op_string
)
8541 && !is_identifier_char (*op_string
)
8542 && *op_string
!= '('
8543 && *op_string
!= ABSOLUTE_PREFIX
)
8545 as_bad (_("bad memory operand `%s'"), op_string
);
8548 /* Handle case of %es:*foo. */
8549 if (*op_string
== ABSOLUTE_PREFIX
)
8552 if (is_space_char (*op_string
))
8554 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8556 goto do_memory_reference
;
8559 /* Handle vector operations. */
8560 if (*op_string
== '{')
8562 op_string
= check_VecOperations (op_string
, NULL
);
8563 if (op_string
== NULL
)
8569 as_bad (_("junk `%s' after register"), op_string
);
8573 temp
.bitfield
.baseindex
= 0;
8574 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8576 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8577 i
.op
[this_operand
].regs
= r
;
8580 else if (*op_string
== REGISTER_PREFIX
)
8582 as_bad (_("bad register name `%s'"), op_string
);
8585 else if (*op_string
== IMMEDIATE_PREFIX
)
8588 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8590 as_bad (_("immediate operand illegal with absolute jump"));
8593 if (!i386_immediate (op_string
))
8596 else if (RC_SAE_immediate (operand_string
))
8598 /* If it is a RC or SAE immediate, do nothing. */
8601 else if (is_digit_char (*op_string
)
8602 || is_identifier_char (*op_string
)
8603 || *op_string
== '(')
8605 /* This is a memory reference of some sort. */
8608 /* Start and end of displacement string expression (if found). */
8609 char *displacement_string_start
;
8610 char *displacement_string_end
;
8613 do_memory_reference
:
8614 if ((i
.mem_operands
== 1
8615 && !current_templates
->start
->opcode_modifier
.isstring
)
8616 || i
.mem_operands
== 2)
8618 as_bad (_("too many memory references for `%s'"),
8619 current_templates
->start
->name
);
8623 /* Check for base index form. We detect the base index form by
8624 looking for an ')' at the end of the operand, searching
8625 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8627 base_string
= op_string
+ strlen (op_string
);
8629 /* Handle vector operations. */
8630 vop_start
= strchr (op_string
, '{');
8631 if (vop_start
&& vop_start
< base_string
)
8633 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8635 base_string
= vop_start
;
8639 if (is_space_char (*base_string
))
8642 /* If we only have a displacement, set-up for it to be parsed later. */
8643 displacement_string_start
= op_string
;
8644 displacement_string_end
= base_string
+ 1;
8646 if (*base_string
== ')')
8649 unsigned int parens_balanced
= 1;
8650 /* We've already checked that the number of left & right ()'s are
8651 equal, so this loop will not be infinite. */
8655 if (*base_string
== ')')
8657 if (*base_string
== '(')
8660 while (parens_balanced
);
8662 temp_string
= base_string
;
8664 /* Skip past '(' and whitespace. */
8666 if (is_space_char (*base_string
))
8669 if (*base_string
== ','
8670 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8673 displacement_string_end
= temp_string
;
8675 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8679 base_string
= end_op
;
8680 if (is_space_char (*base_string
))
8684 /* There may be an index reg or scale factor here. */
8685 if (*base_string
== ',')
8688 if (is_space_char (*base_string
))
8691 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8694 base_string
= end_op
;
8695 if (is_space_char (*base_string
))
8697 if (*base_string
== ',')
8700 if (is_space_char (*base_string
))
8703 else if (*base_string
!= ')')
8705 as_bad (_("expecting `,' or `)' "
8706 "after index register in `%s'"),
8711 else if (*base_string
== REGISTER_PREFIX
)
8713 end_op
= strchr (base_string
, ',');
8716 as_bad (_("bad register name `%s'"), base_string
);
8720 /* Check for scale factor. */
8721 if (*base_string
!= ')')
8723 char *end_scale
= i386_scale (base_string
);
8728 base_string
= end_scale
;
8729 if (is_space_char (*base_string
))
8731 if (*base_string
!= ')')
8733 as_bad (_("expecting `)' "
8734 "after scale factor in `%s'"),
8739 else if (!i
.index_reg
)
8741 as_bad (_("expecting index register or scale factor "
8742 "after `,'; got '%c'"),
8747 else if (*base_string
!= ')')
8749 as_bad (_("expecting `,' or `)' "
8750 "after base register in `%s'"),
8755 else if (*base_string
== REGISTER_PREFIX
)
8757 end_op
= strchr (base_string
, ',');
8760 as_bad (_("bad register name `%s'"), base_string
);
8765 /* If there's an expression beginning the operand, parse it,
8766 assuming displacement_string_start and
8767 displacement_string_end are meaningful. */
8768 if (displacement_string_start
!= displacement_string_end
)
8770 if (!i386_displacement (displacement_string_start
,
8771 displacement_string_end
))
8775 /* Special case for (%dx) while doing input/output op. */
8777 && operand_type_equal (&i
.base_reg
->reg_type
,
8778 ®16_inoutportreg
)
8780 && i
.log2_scale_factor
== 0
8781 && i
.seg
[i
.mem_operands
] == 0
8782 && !operand_type_check (i
.types
[this_operand
], disp
))
8784 i
.types
[this_operand
] = inoutportreg
;
8788 if (i386_index_check (operand_string
) == 0)
8790 i
.types
[this_operand
].bitfield
.mem
= 1;
8795 /* It's not a memory operand; argh! */
8796 as_bad (_("invalid char %s beginning operand %d `%s'"),
8797 output_invalid (*op_string
),
8802 return 1; /* Normal return. */
8805 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8806 that an rs_machine_dependent frag may reach. */
8809 i386_frag_max_var (fragS
*frag
)
8811 /* The only relaxable frags are for jumps.
8812 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8813 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8814 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8817 /* md_estimate_size_before_relax()
8819 Called just before relax() for rs_machine_dependent frags. The x86
8820 assembler uses these frags to handle variable size jump
8823 Any symbol that is now undefined will not become defined.
8824 Return the correct fr_subtype in the frag.
8825 Return the initial "guess for variable size of frag" to caller.
8826 The guess is actually the growth beyond the fixed part. Whatever
8827 we do to grow the fixed or variable part contributes to our
8831 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8833 /* We've already got fragP->fr_subtype right; all we have to do is
8834 check for un-relaxable symbols. On an ELF system, we can't relax
8835 an externally visible symbol, because it may be overridden by a
8837 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8840 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8841 || S_IS_WEAK (fragP
->fr_symbol
)
8842 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8843 & BSF_GNU_INDIRECT_FUNCTION
))))
8845 #if defined (OBJ_COFF) && defined (TE_PE)
8846 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8847 && S_IS_WEAK (fragP
->fr_symbol
))
8851 /* Symbol is undefined in this segment, or we need to keep a
8852 reloc so that weak symbols can be overridden. */
8853 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8854 enum bfd_reloc_code_real reloc_type
;
8855 unsigned char *opcode
;
8858 if (fragP
->fr_var
!= NO_RELOC
)
8859 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8861 reloc_type
= BFD_RELOC_16_PCREL
;
8863 reloc_type
= BFD_RELOC_32_PCREL
;
8865 old_fr_fix
= fragP
->fr_fix
;
8866 opcode
= (unsigned char *) fragP
->fr_opcode
;
8868 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8871 /* Make jmp (0xeb) a (d)word displacement jump. */
8873 fragP
->fr_fix
+= size
;
8874 fix_new (fragP
, old_fr_fix
, size
,
8876 fragP
->fr_offset
, 1,
8882 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8884 /* Negate the condition, and branch past an
8885 unconditional jump. */
8888 /* Insert an unconditional jump. */
8890 /* We added two extra opcode bytes, and have a two byte
8892 fragP
->fr_fix
+= 2 + 2;
8893 fix_new (fragP
, old_fr_fix
+ 2, 2,
8895 fragP
->fr_offset
, 1,
8902 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8907 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8909 fragP
->fr_offset
, 1,
8911 fixP
->fx_signed
= 1;
8915 /* This changes the byte-displacement jump 0x7N
8916 to the (d)word-displacement jump 0x0f,0x8N. */
8917 opcode
[1] = opcode
[0] + 0x10;
8918 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8919 /* We've added an opcode byte. */
8920 fragP
->fr_fix
+= 1 + size
;
8921 fix_new (fragP
, old_fr_fix
+ 1, size
,
8923 fragP
->fr_offset
, 1,
8928 BAD_CASE (fragP
->fr_subtype
);
8932 return fragP
->fr_fix
- old_fr_fix
;
8935 /* Guess size depending on current relax state. Initially the relax
8936 state will correspond to a short jump and we return 1, because
8937 the variable part of the frag (the branch offset) is one byte
8938 long. However, we can relax a section more than once and in that
8939 case we must either set fr_subtype back to the unrelaxed state,
8940 or return the value for the appropriate branch. */
8941 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8944 /* Called after relax() is finished.
8946 In: Address of frag.
8947 fr_type == rs_machine_dependent.
8948 fr_subtype is what the address relaxed to.
8950 Out: Any fixSs and constants are set up.
8951 Caller will turn frag into a ".space 0". */
8954 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8957 unsigned char *opcode
;
8958 unsigned char *where_to_put_displacement
= NULL
;
8959 offsetT target_address
;
8960 offsetT opcode_address
;
8961 unsigned int extension
= 0;
8962 offsetT displacement_from_opcode_start
;
8964 opcode
= (unsigned char *) fragP
->fr_opcode
;
8966 /* Address we want to reach in file space. */
8967 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8969 /* Address opcode resides at in file space. */
8970 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8972 /* Displacement from opcode start to fill into instruction. */
8973 displacement_from_opcode_start
= target_address
- opcode_address
;
8975 if ((fragP
->fr_subtype
& BIG
) == 0)
8977 /* Don't have to change opcode. */
8978 extension
= 1; /* 1 opcode + 1 displacement */
8979 where_to_put_displacement
= &opcode
[1];
8983 if (no_cond_jump_promotion
8984 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8985 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8986 _("long jump required"));
8988 switch (fragP
->fr_subtype
)
8990 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8991 extension
= 4; /* 1 opcode + 4 displacement */
8993 where_to_put_displacement
= &opcode
[1];
8996 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8997 extension
= 2; /* 1 opcode + 2 displacement */
8999 where_to_put_displacement
= &opcode
[1];
9002 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9003 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9004 extension
= 5; /* 2 opcode + 4 displacement */
9005 opcode
[1] = opcode
[0] + 0x10;
9006 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9007 where_to_put_displacement
= &opcode
[2];
9010 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9011 extension
= 3; /* 2 opcode + 2 displacement */
9012 opcode
[1] = opcode
[0] + 0x10;
9013 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9014 where_to_put_displacement
= &opcode
[2];
9017 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9022 where_to_put_displacement
= &opcode
[3];
9026 BAD_CASE (fragP
->fr_subtype
);
9031 /* If size if less then four we are sure that the operand fits,
9032 but if it's 4, then it could be that the displacement is larger
9034 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9036 && ((addressT
) (displacement_from_opcode_start
- extension
9037 + ((addressT
) 1 << 31))
9038 > (((addressT
) 2 << 31) - 1)))
9040 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9041 _("jump target out of range"));
9042 /* Make us emit 0. */
9043 displacement_from_opcode_start
= extension
;
9045 /* Now put displacement after opcode. */
9046 md_number_to_chars ((char *) where_to_put_displacement
,
9047 (valueT
) (displacement_from_opcode_start
- extension
),
9048 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9049 fragP
->fr_fix
+= extension
;
9052 /* Apply a fixup (fixP) to segment data, once it has been determined
9053 by our caller that we have all the info we need to fix it up.
9055 Parameter valP is the pointer to the value of the bits.
9057 On the 386, immediates, displacements, and data pointers are all in
9058 the same (little-endian) format, so we don't need to care about which
9062 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9064 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9065 valueT value
= *valP
;
9067 #if !defined (TE_Mach)
9070 switch (fixP
->fx_r_type
)
9076 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9079 case BFD_RELOC_X86_64_32S
:
9080 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9083 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9086 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9091 if (fixP
->fx_addsy
!= NULL
9092 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9093 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9094 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9095 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9096 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9097 && !use_rela_relocations
)
9099 /* This is a hack. There should be a better way to handle this.
9100 This covers for the fact that bfd_install_relocation will
9101 subtract the current location (for partial_inplace, PC relative
9102 relocations); see more below. */
9106 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9109 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9114 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9117 || (symbol_section_p (fixP
->fx_addsy
)
9118 && sym_seg
!= absolute_section
))
9119 && !generic_force_reloc (fixP
))
9121 /* Yes, we add the values in twice. This is because
9122 bfd_install_relocation subtracts them out again. I think
9123 bfd_install_relocation is broken, but I don't dare change
9125 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9129 #if defined (OBJ_COFF) && defined (TE_PE)
9130 /* For some reason, the PE format does not store a
9131 section address offset for a PC relative symbol. */
9132 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9133 || S_IS_WEAK (fixP
->fx_addsy
))
9134 value
+= md_pcrel_from (fixP
);
9137 #if defined (OBJ_COFF) && defined (TE_PE)
9138 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9140 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9144 /* Fix a few things - the dynamic linker expects certain values here,
9145 and we must not disappoint it. */
9146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9147 if (IS_ELF
&& fixP
->fx_addsy
)
9148 switch (fixP
->fx_r_type
)
9150 case BFD_RELOC_386_PLT32
:
9151 case BFD_RELOC_X86_64_PLT32
:
9152 case BFD_RELOC_X86_64_PLT32_BND
:
9153 /* Make the jump instruction point to the address of the operand. At
9154 runtime we merely add the offset to the actual PLT entry. */
9158 case BFD_RELOC_386_TLS_GD
:
9159 case BFD_RELOC_386_TLS_LDM
:
9160 case BFD_RELOC_386_TLS_IE_32
:
9161 case BFD_RELOC_386_TLS_IE
:
9162 case BFD_RELOC_386_TLS_GOTIE
:
9163 case BFD_RELOC_386_TLS_GOTDESC
:
9164 case BFD_RELOC_X86_64_TLSGD
:
9165 case BFD_RELOC_X86_64_TLSLD
:
9166 case BFD_RELOC_X86_64_GOTTPOFF
:
9167 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9168 value
= 0; /* Fully resolved at runtime. No addend. */
9170 case BFD_RELOC_386_TLS_LE
:
9171 case BFD_RELOC_386_TLS_LDO_32
:
9172 case BFD_RELOC_386_TLS_LE_32
:
9173 case BFD_RELOC_X86_64_DTPOFF32
:
9174 case BFD_RELOC_X86_64_DTPOFF64
:
9175 case BFD_RELOC_X86_64_TPOFF32
:
9176 case BFD_RELOC_X86_64_TPOFF64
:
9177 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9180 case BFD_RELOC_386_TLS_DESC_CALL
:
9181 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9182 value
= 0; /* Fully resolved at runtime. No addend. */
9183 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9187 case BFD_RELOC_386_GOT32
:
9188 case BFD_RELOC_X86_64_GOT32
:
9189 value
= 0; /* Fully resolved at runtime. No addend. */
9192 case BFD_RELOC_VTABLE_INHERIT
:
9193 case BFD_RELOC_VTABLE_ENTRY
:
9200 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9202 #endif /* !defined (TE_Mach) */
9204 /* Are we finished with this relocation now? */
9205 if (fixP
->fx_addsy
== NULL
)
9207 #if defined (OBJ_COFF) && defined (TE_PE)
9208 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9211 /* Remember value for tc_gen_reloc. */
9212 fixP
->fx_addnumber
= value
;
9213 /* Clear out the frag for now. */
9217 else if (use_rela_relocations
)
9219 fixP
->fx_no_overflow
= 1;
9220 /* Remember value for tc_gen_reloc. */
9221 fixP
->fx_addnumber
= value
;
9225 md_number_to_chars (p
, value
, fixP
->fx_size
);
9229 md_atof (int type
, char *litP
, int *sizeP
)
9231 /* This outputs the LITTLENUMs in REVERSE order;
9232 in accord with the bigendian 386. */
9233 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9236 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9239 output_invalid (int c
)
9242 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9245 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9246 "(0x%x)", (unsigned char) c
);
9247 return output_invalid_buf
;
9250 /* REG_STRING starts *before* REGISTER_PREFIX. */
9252 static const reg_entry
*
9253 parse_real_register (char *reg_string
, char **end_op
)
9255 char *s
= reg_string
;
9257 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9260 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9261 if (*s
== REGISTER_PREFIX
)
9264 if (is_space_char (*s
))
9268 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9270 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9271 return (const reg_entry
*) NULL
;
9275 /* For naked regs, make sure that we are not dealing with an identifier.
9276 This prevents confusing an identifier like `eax_var' with register
9278 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9279 return (const reg_entry
*) NULL
;
9283 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9285 /* Handle floating point regs, allowing spaces in the (i) part. */
9286 if (r
== i386_regtab
/* %st is first entry of table */)
9288 if (is_space_char (*s
))
9293 if (is_space_char (*s
))
9295 if (*s
>= '0' && *s
<= '7')
9299 if (is_space_char (*s
))
9304 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9309 /* We have "%st(" then garbage. */
9310 return (const reg_entry
*) NULL
;
9314 if (r
== NULL
|| allow_pseudo_reg
)
9317 if (operand_type_all_zero (&r
->reg_type
))
9318 return (const reg_entry
*) NULL
;
9320 if ((r
->reg_type
.bitfield
.reg32
9321 || r
->reg_type
.bitfield
.sreg3
9322 || r
->reg_type
.bitfield
.control
9323 || r
->reg_type
.bitfield
.debug
9324 || r
->reg_type
.bitfield
.test
)
9325 && !cpu_arch_flags
.bitfield
.cpui386
)
9326 return (const reg_entry
*) NULL
;
9328 if (r
->reg_type
.bitfield
.floatreg
9329 && !cpu_arch_flags
.bitfield
.cpu8087
9330 && !cpu_arch_flags
.bitfield
.cpu287
9331 && !cpu_arch_flags
.bitfield
.cpu387
)
9332 return (const reg_entry
*) NULL
;
9334 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9335 return (const reg_entry
*) NULL
;
9337 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9338 return (const reg_entry
*) NULL
;
9340 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9341 return (const reg_entry
*) NULL
;
9343 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9344 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9345 return (const reg_entry
*) NULL
;
9347 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9348 if (!allow_index_reg
9349 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9350 return (const reg_entry
*) NULL
;
9352 /* Upper 16 vector register is only available with VREX in 64bit
9354 if ((r
->reg_flags
& RegVRex
))
9356 if (!cpu_arch_flags
.bitfield
.cpuvrex
9357 || flag_code
!= CODE_64BIT
)
9358 return (const reg_entry
*) NULL
;
9363 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9364 || r
->reg_type
.bitfield
.reg64
)
9365 && (!cpu_arch_flags
.bitfield
.cpulm
9366 || !operand_type_equal (&r
->reg_type
, &control
))
9367 && flag_code
!= CODE_64BIT
)
9368 return (const reg_entry
*) NULL
;
9370 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9371 return (const reg_entry
*) NULL
;
9376 /* REG_STRING starts *before* REGISTER_PREFIX. */
9378 static const reg_entry
*
9379 parse_register (char *reg_string
, char **end_op
)
9383 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9384 r
= parse_real_register (reg_string
, end_op
);
9389 char *save
= input_line_pointer
;
9393 input_line_pointer
= reg_string
;
9394 c
= get_symbol_end ();
9395 symbolP
= symbol_find (reg_string
);
9396 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9398 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9400 know (e
->X_op
== O_register
);
9401 know (e
->X_add_number
>= 0
9402 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9403 r
= i386_regtab
+ e
->X_add_number
;
9404 *end_op
= input_line_pointer
;
9406 *input_line_pointer
= c
;
9407 input_line_pointer
= save
;
9413 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9416 char *end
= input_line_pointer
;
9419 r
= parse_register (name
, &input_line_pointer
);
9420 if (r
&& end
<= input_line_pointer
)
9422 *nextcharP
= *input_line_pointer
;
9423 *input_line_pointer
= 0;
9424 e
->X_op
= O_register
;
9425 e
->X_add_number
= r
- i386_regtab
;
9428 input_line_pointer
= end
;
9430 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9434 md_operand (expressionS
*e
)
9439 switch (*input_line_pointer
)
9441 case REGISTER_PREFIX
:
9442 r
= parse_real_register (input_line_pointer
, &end
);
9445 e
->X_op
= O_register
;
9446 e
->X_add_number
= r
- i386_regtab
;
9447 input_line_pointer
= end
;
9452 gas_assert (intel_syntax
);
9453 end
= input_line_pointer
++;
9455 if (*input_line_pointer
== ']')
9457 ++input_line_pointer
;
9458 e
->X_op_symbol
= make_expr_symbol (e
);
9459 e
->X_add_symbol
= NULL
;
9460 e
->X_add_number
= 0;
9466 input_line_pointer
= end
;
9473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9474 const char *md_shortopts
= "kVQ:sqn";
9476 const char *md_shortopts
= "qn";
9479 #define OPTION_32 (OPTION_MD_BASE + 0)
9480 #define OPTION_64 (OPTION_MD_BASE + 1)
9481 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9482 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9483 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9484 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9485 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9486 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9487 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9488 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9489 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9490 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9491 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9492 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9493 #define OPTION_X32 (OPTION_MD_BASE + 14)
9494 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9495 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9496 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9498 struct option md_longopts
[] =
9500 {"32", no_argument
, NULL
, OPTION_32
},
9501 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9502 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9503 {"64", no_argument
, NULL
, OPTION_64
},
9505 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9506 {"x32", no_argument
, NULL
, OPTION_X32
},
9508 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9509 {"march", required_argument
, NULL
, OPTION_MARCH
},
9510 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9511 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9512 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9513 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9514 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9515 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9516 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9517 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9518 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9519 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9520 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9521 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9522 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9523 {NULL
, no_argument
, NULL
, 0}
9525 size_t md_longopts_size
= sizeof (md_longopts
);
9528 md_parse_option (int c
, char *arg
)
9536 optimize_align_code
= 0;
9543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9544 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9545 should be emitted or not. FIXME: Not implemented. */
9549 /* -V: SVR4 argument to print version ID. */
9551 print_version_id ();
9554 /* -k: Ignore for FreeBSD compatibility. */
9559 /* -s: On i386 Solaris, this tells the native assembler to use
9560 .stab instead of .stab.excl. We always use .stab anyhow. */
9563 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9564 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9567 const char **list
, **l
;
9569 list
= bfd_target_list ();
9570 for (l
= list
; *l
!= NULL
; l
++)
9571 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9572 || strcmp (*l
, "coff-x86-64") == 0
9573 || strcmp (*l
, "pe-x86-64") == 0
9574 || strcmp (*l
, "pei-x86-64") == 0
9575 || strcmp (*l
, "mach-o-x86-64") == 0)
9577 default_arch
= "x86_64";
9581 as_fatal (_("no compiled in support for x86_64"));
9587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9591 const char **list
, **l
;
9593 list
= bfd_target_list ();
9594 for (l
= list
; *l
!= NULL
; l
++)
9595 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9597 default_arch
= "x86_64:32";
9601 as_fatal (_("no compiled in support for 32bit x86_64"));
9605 as_fatal (_("32bit x86_64 is only supported for ELF"));
9610 default_arch
= "i386";
9614 #ifdef SVR4_COMMENT_CHARS
9619 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9621 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9625 i386_comment_chars
= n
;
9631 arch
= xstrdup (arg
);
9635 as_fatal (_("invalid -march= option: `%s'"), arg
);
9636 next
= strchr (arch
, '+');
9639 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9641 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9644 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9647 cpu_arch_name
= cpu_arch
[j
].name
;
9648 cpu_sub_arch_name
= NULL
;
9649 cpu_arch_flags
= cpu_arch
[j
].flags
;
9650 cpu_arch_isa
= cpu_arch
[j
].type
;
9651 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9652 if (!cpu_arch_tune_set
)
9654 cpu_arch_tune
= cpu_arch_isa
;
9655 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9659 else if (*cpu_arch
[j
].name
== '.'
9660 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9662 /* ISA entension. */
9663 i386_cpu_flags flags
;
9665 if (!cpu_arch
[j
].negated
)
9666 flags
= cpu_flags_or (cpu_arch_flags
,
9669 flags
= cpu_flags_and_not (cpu_arch_flags
,
9671 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9673 if (cpu_sub_arch_name
)
9675 char *name
= cpu_sub_arch_name
;
9676 cpu_sub_arch_name
= concat (name
,
9678 (const char *) NULL
);
9682 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9683 cpu_arch_flags
= flags
;
9684 cpu_arch_isa_flags
= flags
;
9690 if (j
>= ARRAY_SIZE (cpu_arch
))
9691 as_fatal (_("invalid -march= option: `%s'"), arg
);
9695 while (next
!= NULL
);
9700 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9701 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9703 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9705 cpu_arch_tune_set
= 1;
9706 cpu_arch_tune
= cpu_arch
[j
].type
;
9707 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9711 if (j
>= ARRAY_SIZE (cpu_arch
))
9712 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9715 case OPTION_MMNEMONIC
:
9716 if (strcasecmp (arg
, "att") == 0)
9718 else if (strcasecmp (arg
, "intel") == 0)
9721 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9724 case OPTION_MSYNTAX
:
9725 if (strcasecmp (arg
, "att") == 0)
9727 else if (strcasecmp (arg
, "intel") == 0)
9730 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9733 case OPTION_MINDEX_REG
:
9734 allow_index_reg
= 1;
9737 case OPTION_MNAKED_REG
:
9738 allow_naked_reg
= 1;
9741 case OPTION_MOLD_GCC
:
9745 case OPTION_MSSE2AVX
:
9749 case OPTION_MSSE_CHECK
:
9750 if (strcasecmp (arg
, "error") == 0)
9751 sse_check
= check_error
;
9752 else if (strcasecmp (arg
, "warning") == 0)
9753 sse_check
= check_warning
;
9754 else if (strcasecmp (arg
, "none") == 0)
9755 sse_check
= check_none
;
9757 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9760 case OPTION_MOPERAND_CHECK
:
9761 if (strcasecmp (arg
, "error") == 0)
9762 operand_check
= check_error
;
9763 else if (strcasecmp (arg
, "warning") == 0)
9764 operand_check
= check_warning
;
9765 else if (strcasecmp (arg
, "none") == 0)
9766 operand_check
= check_none
;
9768 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9771 case OPTION_MAVXSCALAR
:
9772 if (strcasecmp (arg
, "128") == 0)
9774 else if (strcasecmp (arg
, "256") == 0)
9777 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9780 case OPTION_MADD_BND_PREFIX
:
9784 case OPTION_MEVEXLIG
:
9785 if (strcmp (arg
, "128") == 0)
9787 else if (strcmp (arg
, "256") == 0)
9789 else if (strcmp (arg
, "512") == 0)
9792 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9795 case OPTION_MEVEXWIG
:
9796 if (strcmp (arg
, "0") == 0)
9798 else if (strcmp (arg
, "1") == 0)
9801 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9810 #define MESSAGE_TEMPLATE \
9814 show_arch (FILE *stream
, int ext
, int check
)
9816 static char message
[] = MESSAGE_TEMPLATE
;
9817 char *start
= message
+ 27;
9819 int size
= sizeof (MESSAGE_TEMPLATE
);
9826 left
= size
- (start
- message
);
9827 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9829 /* Should it be skipped? */
9830 if (cpu_arch
[j
].skip
)
9833 name
= cpu_arch
[j
].name
;
9834 len
= cpu_arch
[j
].len
;
9837 /* It is an extension. Skip if we aren't asked to show it. */
9848 /* It is an processor. Skip if we show only extension. */
9851 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9853 /* It is an impossible processor - skip. */
9857 /* Reserve 2 spaces for ", " or ",\0" */
9860 /* Check if there is any room. */
9868 p
= mempcpy (p
, name
, len
);
9872 /* Output the current message now and start a new one. */
9875 fprintf (stream
, "%s\n", message
);
9877 left
= size
- (start
- message
) - len
- 2;
9879 gas_assert (left
>= 0);
9881 p
= mempcpy (p
, name
, len
);
9886 fprintf (stream
, "%s\n", message
);
9890 md_show_usage (FILE *stream
)
9892 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9893 fprintf (stream
, _("\
9895 -V print assembler version number\n\
9898 fprintf (stream
, _("\
9899 -n Do not optimize code alignment\n\
9900 -q quieten some warnings\n"));
9901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9902 fprintf (stream
, _("\
9905 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9906 || defined (TE_PE) || defined (TE_PEP))
9907 fprintf (stream
, _("\
9908 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9910 #ifdef SVR4_COMMENT_CHARS
9911 fprintf (stream
, _("\
9912 --divide do not treat `/' as a comment character\n"));
9914 fprintf (stream
, _("\
9915 --divide ignored\n"));
9917 fprintf (stream
, _("\
9918 -march=CPU[,+EXTENSION...]\n\
9919 generate code for CPU and EXTENSION, CPU is one of:\n"));
9920 show_arch (stream
, 0, 1);
9921 fprintf (stream
, _("\
9922 EXTENSION is combination of:\n"));
9923 show_arch (stream
, 1, 0);
9924 fprintf (stream
, _("\
9925 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9926 show_arch (stream
, 0, 0);
9927 fprintf (stream
, _("\
9928 -msse2avx encode SSE instructions with VEX prefix\n"));
9929 fprintf (stream
, _("\
9930 -msse-check=[none|error|warning]\n\
9931 check SSE instructions\n"));
9932 fprintf (stream
, _("\
9933 -moperand-check=[none|error|warning]\n\
9934 check operand combinations for validity\n"));
9935 fprintf (stream
, _("\
9936 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9938 fprintf (stream
, _("\
9939 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9941 fprintf (stream
, _("\
9942 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9943 for EVEX.W bit ignored instructions\n"));
9944 fprintf (stream
, _("\
9945 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9946 fprintf (stream
, _("\
9947 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9948 fprintf (stream
, _("\
9949 -mindex-reg support pseudo index registers\n"));
9950 fprintf (stream
, _("\
9951 -mnaked-reg don't require `%%' prefix for registers\n"));
9952 fprintf (stream
, _("\
9953 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9954 fprintf (stream
, _("\
9955 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9958 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9959 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9960 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9962 /* Pick the target format to use. */
9965 i386_target_format (void)
9967 if (!strncmp (default_arch
, "x86_64", 6))
9969 update_code_flag (CODE_64BIT
, 1);
9970 if (default_arch
[6] == '\0')
9971 x86_elf_abi
= X86_64_ABI
;
9973 x86_elf_abi
= X86_64_X32_ABI
;
9975 else if (!strcmp (default_arch
, "i386"))
9976 update_code_flag (CODE_32BIT
, 1);
9978 as_fatal (_("unknown architecture"));
9980 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9981 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9982 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9983 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9985 switch (OUTPUT_FLAVOR
)
9987 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9988 case bfd_target_aout_flavour
:
9989 return AOUT_TARGET_FORMAT
;
9991 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9992 # if defined (TE_PE) || defined (TE_PEP)
9993 case bfd_target_coff_flavour
:
9994 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9995 # elif defined (TE_GO32)
9996 case bfd_target_coff_flavour
:
9999 case bfd_target_coff_flavour
:
10000 return "coff-i386";
10003 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10004 case bfd_target_elf_flavour
:
10006 const char *format
;
10008 switch (x86_elf_abi
)
10011 format
= ELF_TARGET_FORMAT
;
10014 use_rela_relocations
= 1;
10016 format
= ELF_TARGET_FORMAT64
;
10018 case X86_64_X32_ABI
:
10019 use_rela_relocations
= 1;
10021 disallow_64bit_reloc
= 1;
10022 format
= ELF_TARGET_FORMAT32
;
10025 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10027 if (x86_elf_abi
!= X86_64_ABI
)
10028 as_fatal (_("Intel L1OM is 64bit only"));
10029 return ELF_TARGET_L1OM_FORMAT
;
10031 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10033 if (x86_elf_abi
!= X86_64_ABI
)
10034 as_fatal (_("Intel K1OM is 64bit only"));
10035 return ELF_TARGET_K1OM_FORMAT
;
10041 #if defined (OBJ_MACH_O)
10042 case bfd_target_mach_o_flavour
:
10043 if (flag_code
== CODE_64BIT
)
10045 use_rela_relocations
= 1;
10047 return "mach-o-x86-64";
10050 return "mach-o-i386";
10058 #endif /* OBJ_MAYBE_ more than one */
10060 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10062 i386_elf_emit_arch_note (void)
10064 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10067 asection
*seg
= now_seg
;
10068 subsegT subseg
= now_subseg
;
10069 Elf_Internal_Note i_note
;
10070 Elf_External_Note e_note
;
10071 asection
*note_secp
;
10074 /* Create the .note section. */
10075 note_secp
= subseg_new (".note", 0);
10076 bfd_set_section_flags (stdoutput
,
10078 SEC_HAS_CONTENTS
| SEC_READONLY
);
10080 /* Process the arch string. */
10081 len
= strlen (cpu_arch_name
);
10083 i_note
.namesz
= len
+ 1;
10085 i_note
.type
= NT_ARCH
;
10086 p
= frag_more (sizeof (e_note
.namesz
));
10087 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10088 p
= frag_more (sizeof (e_note
.descsz
));
10089 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10090 p
= frag_more (sizeof (e_note
.type
));
10091 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10092 p
= frag_more (len
+ 1);
10093 strcpy (p
, cpu_arch_name
);
10095 frag_align (2, 0, 0);
10097 subseg_set (seg
, subseg
);
10103 md_undefined_symbol (char *name
)
10105 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10106 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10107 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10108 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10112 if (symbol_find (name
))
10113 as_bad (_("GOT already in symbol table"));
10114 GOT_symbol
= symbol_new (name
, undefined_section
,
10115 (valueT
) 0, &zero_address_frag
);
10122 /* Round up a section size to the appropriate boundary. */
10125 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10127 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10128 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10130 /* For a.out, force the section size to be aligned. If we don't do
10131 this, BFD will align it for us, but it will not write out the
10132 final bytes of the section. This may be a bug in BFD, but it is
10133 easier to fix it here since that is how the other a.out targets
10137 align
= bfd_get_section_alignment (stdoutput
, segment
);
10138 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10145 /* On the i386, PC-relative offsets are relative to the start of the
10146 next instruction. That is, the address of the offset, plus its
10147 size, since the offset is always the last part of the insn. */
10150 md_pcrel_from (fixS
*fixP
)
10152 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10158 s_bss (int ignore ATTRIBUTE_UNUSED
)
10162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10164 obj_elf_section_change_hook ();
10166 temp
= get_absolute_expression ();
10167 subseg_set (bss_section
, (subsegT
) temp
);
10168 demand_empty_rest_of_line ();
10174 i386_validate_fix (fixS
*fixp
)
10176 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10178 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10182 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10187 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10189 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10191 fixp
->fx_subsy
= 0;
10196 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10199 bfd_reloc_code_real_type code
;
10201 switch (fixp
->fx_r_type
)
10203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10204 case BFD_RELOC_SIZE32
:
10205 case BFD_RELOC_SIZE64
:
10206 if (S_IS_DEFINED (fixp
->fx_addsy
)
10207 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10209 /* Resolve size relocation against local symbol to size of
10210 the symbol plus addend. */
10211 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10212 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10213 && !fits_in_unsigned_long (value
))
10214 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10215 _("symbol size computation overflow"));
10216 fixp
->fx_addsy
= NULL
;
10217 fixp
->fx_subsy
= NULL
;
10218 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10223 case BFD_RELOC_X86_64_PLT32
:
10224 case BFD_RELOC_X86_64_PLT32_BND
:
10225 case BFD_RELOC_X86_64_GOT32
:
10226 case BFD_RELOC_X86_64_GOTPCREL
:
10227 case BFD_RELOC_386_PLT32
:
10228 case BFD_RELOC_386_GOT32
:
10229 case BFD_RELOC_386_GOTOFF
:
10230 case BFD_RELOC_386_GOTPC
:
10231 case BFD_RELOC_386_TLS_GD
:
10232 case BFD_RELOC_386_TLS_LDM
:
10233 case BFD_RELOC_386_TLS_LDO_32
:
10234 case BFD_RELOC_386_TLS_IE_32
:
10235 case BFD_RELOC_386_TLS_IE
:
10236 case BFD_RELOC_386_TLS_GOTIE
:
10237 case BFD_RELOC_386_TLS_LE_32
:
10238 case BFD_RELOC_386_TLS_LE
:
10239 case BFD_RELOC_386_TLS_GOTDESC
:
10240 case BFD_RELOC_386_TLS_DESC_CALL
:
10241 case BFD_RELOC_X86_64_TLSGD
:
10242 case BFD_RELOC_X86_64_TLSLD
:
10243 case BFD_RELOC_X86_64_DTPOFF32
:
10244 case BFD_RELOC_X86_64_DTPOFF64
:
10245 case BFD_RELOC_X86_64_GOTTPOFF
:
10246 case BFD_RELOC_X86_64_TPOFF32
:
10247 case BFD_RELOC_X86_64_TPOFF64
:
10248 case BFD_RELOC_X86_64_GOTOFF64
:
10249 case BFD_RELOC_X86_64_GOTPC32
:
10250 case BFD_RELOC_X86_64_GOT64
:
10251 case BFD_RELOC_X86_64_GOTPCREL64
:
10252 case BFD_RELOC_X86_64_GOTPC64
:
10253 case BFD_RELOC_X86_64_GOTPLT64
:
10254 case BFD_RELOC_X86_64_PLTOFF64
:
10255 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10256 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10257 case BFD_RELOC_RVA
:
10258 case BFD_RELOC_VTABLE_ENTRY
:
10259 case BFD_RELOC_VTABLE_INHERIT
:
10261 case BFD_RELOC_32_SECREL
:
10263 code
= fixp
->fx_r_type
;
10265 case BFD_RELOC_X86_64_32S
:
10266 if (!fixp
->fx_pcrel
)
10268 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10269 code
= fixp
->fx_r_type
;
10273 if (fixp
->fx_pcrel
)
10275 switch (fixp
->fx_size
)
10278 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10279 _("can not do %d byte pc-relative relocation"),
10281 code
= BFD_RELOC_32_PCREL
;
10283 case 1: code
= BFD_RELOC_8_PCREL
; break;
10284 case 2: code
= BFD_RELOC_16_PCREL
; break;
10286 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10287 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10290 case 8: code
= BFD_RELOC_64_PCREL
; break;
10296 switch (fixp
->fx_size
)
10299 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10300 _("can not do %d byte relocation"),
10302 code
= BFD_RELOC_32
;
10304 case 1: code
= BFD_RELOC_8
; break;
10305 case 2: code
= BFD_RELOC_16
; break;
10306 case 4: code
= BFD_RELOC_32
; break;
10308 case 8: code
= BFD_RELOC_64
; break;
10315 if ((code
== BFD_RELOC_32
10316 || code
== BFD_RELOC_32_PCREL
10317 || code
== BFD_RELOC_X86_64_32S
)
10319 && fixp
->fx_addsy
== GOT_symbol
)
10322 code
= BFD_RELOC_386_GOTPC
;
10324 code
= BFD_RELOC_X86_64_GOTPC32
;
10326 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10328 && fixp
->fx_addsy
== GOT_symbol
)
10330 code
= BFD_RELOC_X86_64_GOTPC64
;
10333 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10334 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10335 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10337 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10339 if (!use_rela_relocations
)
10341 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10342 vtable entry to be used in the relocation's section offset. */
10343 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10344 rel
->address
= fixp
->fx_offset
;
10345 #if defined (OBJ_COFF) && defined (TE_PE)
10346 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10347 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10352 /* Use the rela in 64bit mode. */
10355 if (disallow_64bit_reloc
)
10358 case BFD_RELOC_X86_64_DTPOFF64
:
10359 case BFD_RELOC_X86_64_TPOFF64
:
10360 case BFD_RELOC_64_PCREL
:
10361 case BFD_RELOC_X86_64_GOTOFF64
:
10362 case BFD_RELOC_X86_64_GOT64
:
10363 case BFD_RELOC_X86_64_GOTPCREL64
:
10364 case BFD_RELOC_X86_64_GOTPC64
:
10365 case BFD_RELOC_X86_64_GOTPLT64
:
10366 case BFD_RELOC_X86_64_PLTOFF64
:
10367 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10368 _("cannot represent relocation type %s in x32 mode"),
10369 bfd_get_reloc_code_name (code
));
10375 if (!fixp
->fx_pcrel
)
10376 rel
->addend
= fixp
->fx_offset
;
10380 case BFD_RELOC_X86_64_PLT32
:
10381 case BFD_RELOC_X86_64_PLT32_BND
:
10382 case BFD_RELOC_X86_64_GOT32
:
10383 case BFD_RELOC_X86_64_GOTPCREL
:
10384 case BFD_RELOC_X86_64_TLSGD
:
10385 case BFD_RELOC_X86_64_TLSLD
:
10386 case BFD_RELOC_X86_64_GOTTPOFF
:
10387 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10388 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10389 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10392 rel
->addend
= (section
->vma
10394 + fixp
->fx_addnumber
10395 + md_pcrel_from (fixp
));
10400 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10401 if (rel
->howto
== NULL
)
10403 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10404 _("cannot represent relocation type %s"),
10405 bfd_get_reloc_code_name (code
));
10406 /* Set howto to a garbage value so that we can keep going. */
10407 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10408 gas_assert (rel
->howto
!= NULL
);
10414 #include "tc-i386-intel.c"
10417 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10419 int saved_naked_reg
;
10420 char saved_register_dot
;
10422 saved_naked_reg
= allow_naked_reg
;
10423 allow_naked_reg
= 1;
10424 saved_register_dot
= register_chars
['.'];
10425 register_chars
['.'] = '.';
10426 allow_pseudo_reg
= 1;
10427 expression_and_evaluate (exp
);
10428 allow_pseudo_reg
= 0;
10429 register_chars
['.'] = saved_register_dot
;
10430 allow_naked_reg
= saved_naked_reg
;
10432 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10434 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10436 exp
->X_op
= O_constant
;
10437 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10438 .dw2_regnum
[flag_code
>> 1];
10441 exp
->X_op
= O_illegal
;
10446 tc_x86_frame_initial_instructions (void)
10448 static unsigned int sp_regno
[2];
10450 if (!sp_regno
[flag_code
>> 1])
10452 char *saved_input
= input_line_pointer
;
10453 char sp
[][4] = {"esp", "rsp"};
10456 input_line_pointer
= sp
[flag_code
>> 1];
10457 tc_x86_parse_to_dw2regnum (&exp
);
10458 gas_assert (exp
.X_op
== O_constant
);
10459 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10460 input_line_pointer
= saved_input
;
10463 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10464 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10468 x86_dwarf2_addr_size (void)
10470 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10471 if (x86_elf_abi
== X86_64_X32_ABI
)
10474 return bfd_arch_bits_per_address (stdoutput
) / 8;
10478 i386_elf_section_type (const char *str
, size_t len
)
10480 if (flag_code
== CODE_64BIT
10481 && len
== sizeof ("unwind") - 1
10482 && strncmp (str
, "unwind", 6) == 0)
10483 return SHT_X86_64_UNWIND
;
10490 i386_solaris_fix_up_eh_frame (segT sec
)
10492 if (flag_code
== CODE_64BIT
)
10493 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10499 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10503 exp
.X_op
= O_secrel
;
10504 exp
.X_add_symbol
= symbol
;
10505 exp
.X_add_number
= 0;
10506 emit_expr (&exp
, size
);
10510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10511 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10514 x86_64_section_letter (int letter
, char **ptr_msg
)
10516 if (flag_code
== CODE_64BIT
)
10519 return SHF_X86_64_LARGE
;
10521 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10524 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10529 x86_64_section_word (char *str
, size_t len
)
10531 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10532 return SHF_X86_64_LARGE
;
10538 handle_large_common (int small ATTRIBUTE_UNUSED
)
10540 if (flag_code
!= CODE_64BIT
)
10542 s_comm_internal (0, elf_common_parse
);
10543 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10547 static segT lbss_section
;
10548 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10549 asection
*saved_bss_section
= bss_section
;
10551 if (lbss_section
== NULL
)
10553 flagword applicable
;
10554 segT seg
= now_seg
;
10555 subsegT subseg
= now_subseg
;
10557 /* The .lbss section is for local .largecomm symbols. */
10558 lbss_section
= subseg_new (".lbss", 0);
10559 applicable
= bfd_applicable_section_flags (stdoutput
);
10560 bfd_set_section_flags (stdoutput
, lbss_section
,
10561 applicable
& SEC_ALLOC
);
10562 seg_info (lbss_section
)->bss
= 1;
10564 subseg_set (seg
, subseg
);
10567 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10568 bss_section
= lbss_section
;
10570 s_comm_internal (0, elf_common_parse
);
10572 elf_com_section_ptr
= saved_com_section_ptr
;
10573 bss_section
= saved_bss_section
;
10576 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */