1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 int flag_compress_debug
= 1;
41 #ifndef REGISTER_WARNINGS
42 #define REGISTER_WARNINGS 1
45 #ifndef INFER_ADDR_PREFIX
46 #define INFER_ADDR_PREFIX 1
50 #define DEFAULT_ARCH "i386"
55 #define INLINE __inline__
61 /* Prefixes will be emitted in the order defined below.
62 WAIT_PREFIX must be the first prefix since FWAIT is really is an
63 instruction, and so must come before any prefixes.
64 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
65 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
71 #define HLE_PREFIX REP_PREFIX
72 #define BND_PREFIX REP_PREFIX
74 #define REX_PREFIX 6 /* must come last. */
75 #define MAX_PREFIXES 7 /* max prefixes per opcode */
77 /* we define the syntax here (modulo base,index,scale syntax) */
78 #define REGISTER_PREFIX '%'
79 #define IMMEDIATE_PREFIX '$'
80 #define ABSOLUTE_PREFIX '*'
82 /* these are the instruction mnemonic suffixes in AT&T syntax or
83 memory operand size in Intel syntax. */
84 #define WORD_MNEM_SUFFIX 'w'
85 #define BYTE_MNEM_SUFFIX 'b'
86 #define SHORT_MNEM_SUFFIX 's'
87 #define LONG_MNEM_SUFFIX 'l'
88 #define QWORD_MNEM_SUFFIX 'q'
89 #define XMMWORD_MNEM_SUFFIX 'x'
90 #define YMMWORD_MNEM_SUFFIX 'y'
91 #define ZMMWORD_MNEM_SUFFIX 'z'
92 /* Intel Syntax. Use a non-ascii letter since since it never appears
94 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
96 #define END_OF_INSN '\0'
99 'templates' is for grouping together 'template' structures for opcodes
100 of the same name. This is only used for storing the insns in the grand
101 ole hash table of insns.
102 The templates themselves start at START and range up to (but not including)
107 const insn_template
*start
;
108 const insn_template
*end
;
112 /* 386 operand encoding bytes: see 386 book for details of this. */
115 unsigned int regmem
; /* codes register or memory operand */
116 unsigned int reg
; /* codes register operand (or extended opcode) */
117 unsigned int mode
; /* how to interpret regmem & reg */
121 /* x86-64 extension prefix. */
122 typedef int rex_byte
;
124 /* 386 opcode byte to code indirect addressing. */
133 /* x86 arch names, types and features */
136 const char *name
; /* arch name */
137 unsigned int len
; /* arch string length */
138 enum processor_type type
; /* arch type */
139 i386_cpu_flags flags
; /* cpu feature flags */
140 unsigned int skip
; /* show_arch should skip this. */
141 unsigned int negated
; /* turn off indicated flags. */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (void);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
266 unsupported_with_intel_mnemonic
,
269 invalid_vsib_address
,
270 invalid_vector_register_set
,
271 unsupported_vector_index_register
,
272 unsupported_broadcast
,
273 broadcast_not_on_src_operand
,
276 mask_not_on_destination
,
279 rc_sae_operand_not_last_imm
,
280 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry
*base_reg
;
319 const reg_entry
*index_reg
;
320 unsigned int log2_scale_factor
;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry
*seg
[2];
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes
;
329 unsigned char prefix
[MAX_PREFIXES
];
331 /* RM and SIB are the modrm byte and the sib byte where the
332 addressing modes of this insn are encoded. */
339 /* Masking attributes. */
340 struct Mask_Operation
*mask
;
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation
*rounding
;
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation
*broadcast
;
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift
;
351 /* Swap operand in encoding. */
352 unsigned int swap_operand
;
354 /* Prefer 8bit or 32bit displacement in encoding. */
357 disp_encoding_default
= 0,
363 const char *rep_prefix
;
366 const char *hle_prefix
;
368 /* Have BND prefix. */
369 const char *bnd_prefix
;
371 /* Need VREX to support upper 16 registers. */
375 enum i386_error error
;
378 typedef struct _i386_insn i386_insn
;
380 /* Link RC type with corresponding string, that'll be looked for in
389 static const struct RC_name RC_NamesTable
[] =
391 { rne
, STRING_COMMA_LEN ("rn-sae") },
392 { rd
, STRING_COMMA_LEN ("rd-sae") },
393 { ru
, STRING_COMMA_LEN ("ru-sae") },
394 { rz
, STRING_COMMA_LEN ("rz-sae") },
395 { saeonly
, STRING_COMMA_LEN ("sae") },
398 /* List of chars besides those in app.c:symbol_chars that can start an
399 operand. Used to prevent the scrubber eating vital white-space. */
400 const char extra_symbol_chars
[] = "*%-([{"
409 #if (defined (TE_I386AIX) \
410 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
411 && !defined (TE_GNU) \
412 && !defined (TE_LINUX) \
413 && !defined (TE_NACL) \
414 && !defined (TE_NETWARE) \
415 && !defined (TE_FreeBSD) \
416 && !defined (TE_DragonFly) \
417 && !defined (TE_NetBSD)))
418 /* This array holds the chars that always start a comment. If the
419 pre-processor is disabled, these aren't very useful. The option
420 --divide will remove '/' from this list. */
421 const char *i386_comment_chars
= "#/";
422 #define SVR4_COMMENT_CHARS 1
423 #define PREFIX_SEPARATOR '\\'
426 const char *i386_comment_chars
= "#";
427 #define PREFIX_SEPARATOR '/'
430 /* This array holds the chars that only start a comment at the beginning of
431 a line. If the line seems to have the form '# 123 filename'
432 .line and .file directives will appear in the pre-processed output.
433 Note that input_file.c hand checks for '#' at the beginning of the
434 first line of the input file. This is because the compiler outputs
435 #NO_APP at the beginning of its output.
436 Also note that comments started like this one will always work if
437 '/' isn't otherwise defined. */
438 const char line_comment_chars
[] = "#/";
440 const char line_separator_chars
[] = ";";
442 /* Chars that can be used to separate mant from exp in floating point
444 const char EXP_CHARS
[] = "eE";
446 /* Chars that mean this number is a floating point constant
449 const char FLT_CHARS
[] = "fFdDxX";
451 /* Tables for lexical analysis. */
452 static char mnemonic_chars
[256];
453 static char register_chars
[256];
454 static char operand_chars
[256];
455 static char identifier_chars
[256];
456 static char digit_chars
[256];
458 /* Lexical macros. */
459 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
460 #define is_operand_char(x) (operand_chars[(unsigned char) x])
461 #define is_register_char(x) (register_chars[(unsigned char) x])
462 #define is_space_char(x) ((x) == ' ')
463 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
464 #define is_digit_char(x) (digit_chars[(unsigned char) x])
466 /* All non-digit non-letter characters that may occur in an operand. */
467 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
469 /* md_assemble() always leaves the strings it's passed unaltered. To
470 effect this we maintain a stack of saved characters that we've smashed
471 with '\0's (indicating end of strings for various sub-fields of the
472 assembler instruction). */
473 static char save_stack
[32];
474 static char *save_stack_p
;
475 #define END_STRING_AND_SAVE(s) \
476 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
477 #define RESTORE_END_STRING(s) \
478 do { *(s) = *--save_stack_p; } while (0)
480 /* The instruction we're assembling. */
483 /* Possible templates for current insn. */
484 static const templates
*current_templates
;
486 /* Per instruction expressionS buffers: max displacements & immediates. */
487 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
488 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
490 /* Current operand we are working on. */
491 static int this_operand
= -1;
493 /* We support four different modes. FLAG_CODE variable is used to distinguish
501 static enum flag_code flag_code
;
502 static unsigned int object_64bit
;
503 static unsigned int disallow_64bit_reloc
;
504 static int use_rela_relocations
= 0;
506 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510 /* The ELF ABI to use. */
518 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
521 #if defined (TE_PE) || defined (TE_PEP)
522 /* Use big object file format. */
523 static int use_big_obj
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 static enum check_kind
561 sse_check
, operand_check
= check_warning
;
563 /* Register prefix used for error message. */
564 static const char *register_prefix
= "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size
= '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code
= 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings
= 0;
578 static const char *cpu_arch_name
= NULL
;
579 static char *cpu_sub_arch_name
= NULL
;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set
= 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags
;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags
;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion
= 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx
;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig
= rne
;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS
*GOT_symbol
;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column
;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment
;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table
[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch
[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
724 CPU_GENERIC32_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
726 CPU_GENERIC64_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
728 CPU_NONE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
730 CPU_I186_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
732 CPU_I286_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
734 CPU_I386_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
736 CPU_I486_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
738 CPU_I586_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
740 CPU_I686_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
744 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
746 CPU_P2_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
748 CPU_P3_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
750 CPU_P4_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
752 CPU_CORE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
754 CPU_NOCONA_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
756 CPU_CORE_FLAGS
, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
760 CPU_CORE2_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
762 CPU_CORE2_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
764 CPU_COREI7_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
766 CPU_L1OM_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
768 CPU_K1OM_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
770 CPU_K6_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
772 CPU_K6_2_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
774 CPU_ATHLON_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
776 CPU_K8_FLAGS
, 1, 0 },
777 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
778 CPU_K8_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
780 CPU_K8_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
782 CPU_AMDFAM10_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
784 CPU_BDVER1_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
786 CPU_BDVER2_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
788 CPU_BDVER3_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
790 CPU_BDVER4_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
792 CPU_BTVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
794 CPU_BTVER2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
796 CPU_8087_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
798 CPU_287_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
800 CPU_387_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
802 CPU_ANY87_FLAGS
, 0, 1 },
803 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
804 CPU_MMX_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
806 CPU_3DNOWA_FLAGS
, 0, 1 },
807 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
808 CPU_SSE_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
810 CPU_SSE2_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
812 CPU_SSE3_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
814 CPU_SSSE3_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
816 CPU_SSE4_1_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
818 CPU_SSE4_2_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
820 CPU_SSE4_2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
822 CPU_ANY_SSE_FLAGS
, 0, 1 },
823 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
824 CPU_AVX_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
826 CPU_AVX2_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
828 CPU_AVX512F_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
830 CPU_AVX512CD_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
832 CPU_AVX512ER_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
834 CPU_AVX512PF_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512DQ_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512BW_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512VL_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
842 CPU_ANY_AVX_FLAGS
, 0, 1 },
843 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
844 CPU_VMX_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
846 CPU_VMFUNC_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
848 CPU_SMX_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
850 CPU_XSAVE_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
852 CPU_XSAVEOPT_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
854 CPU_XSAVEC_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
856 CPU_XSAVES_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
858 CPU_AES_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
860 CPU_PCLMUL_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
862 CPU_PCLMUL_FLAGS
, 1, 0 },
863 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
864 CPU_FSGSBASE_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
866 CPU_RDRND_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
868 CPU_F16C_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
870 CPU_BMI2_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
872 CPU_FMA_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
874 CPU_FMA4_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
876 CPU_XOP_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
878 CPU_LWP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
880 CPU_MOVBE_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
882 CPU_CX16_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
884 CPU_EPT_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
886 CPU_LZCNT_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
888 CPU_HLE_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
890 CPU_RTM_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
892 CPU_INVPCID_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
894 CPU_CLFLUSH_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
896 CPU_NOP_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
898 CPU_SYSCALL_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
900 CPU_RDTSCP_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
902 CPU_3DNOW_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
904 CPU_3DNOWA_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
906 CPU_PADLOCK_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
908 CPU_SVME_FLAGS
, 1, 0 },
909 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
910 CPU_SVME_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
912 CPU_SSE4A_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
914 CPU_ABM_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
916 CPU_BMI_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
918 CPU_TBM_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
920 CPU_ADX_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
922 CPU_RDSEED_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
924 CPU_PRFCHW_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
926 CPU_SMAP_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
928 CPU_MPX_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
930 CPU_SHA_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
932 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
934 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
936 CPU_SE1_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
938 CPU_CLWB_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
940 CPU_PCOMMIT_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
942 CPU_AVX512IFMA_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
944 CPU_AVX512VBMI_FLAGS
, 0, 0 },
948 /* Like s_lcomm_internal in gas/read.c but the alignment string
949 is allowed to be optional. */
952 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
959 && *input_line_pointer
== ',')
961 align
= parse_align (needs_align
- 1);
963 if (align
== (addressT
) -1)
978 bss_alloc (symbolP
, size
, align
);
983 pe_lcomm (int needs_align
)
985 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
989 const pseudo_typeS md_pseudo_table
[] =
991 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
992 {"align", s_align_bytes
, 0},
994 {"align", s_align_ptwo
, 0},
996 {"arch", set_cpu_arch
, 0},
1000 {"lcomm", pe_lcomm
, 1},
1002 {"ffloat", float_cons
, 'f'},
1003 {"dfloat", float_cons
, 'd'},
1004 {"tfloat", float_cons
, 'x'},
1006 {"slong", signed_cons
, 4},
1007 {"noopt", s_ignore
, 0},
1008 {"optim", s_ignore
, 0},
1009 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1010 {"code16", set_code_flag
, CODE_16BIT
},
1011 {"code32", set_code_flag
, CODE_32BIT
},
1012 {"code64", set_code_flag
, CODE_64BIT
},
1013 {"intel_syntax", set_intel_syntax
, 1},
1014 {"att_syntax", set_intel_syntax
, 0},
1015 {"intel_mnemonic", set_intel_mnemonic
, 1},
1016 {"att_mnemonic", set_intel_mnemonic
, 0},
1017 {"allow_index_reg", set_allow_index_reg
, 1},
1018 {"disallow_index_reg", set_allow_index_reg
, 0},
1019 {"sse_check", set_check
, 0},
1020 {"operand_check", set_check
, 1},
1021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1022 {"largecomm", handle_large_common
, 0},
1024 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1025 {"loc", dwarf2_directive_loc
, 0},
1026 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1029 {"secrel32", pe_directive_secrel
, 0},
1034 /* For interface with expression (). */
1035 extern char *input_line_pointer
;
1037 /* Hash table for instruction mnemonic lookup. */
1038 static struct hash_control
*op_hash
;
1040 /* Hash table for register lookup. */
1041 static struct hash_control
*reg_hash
;
1044 i386_align_code (fragS
*fragP
, int count
)
1046 /* Various efficient no-op patterns for aligning code labels.
1047 Note: Don't try to assemble the instructions in the comments.
1048 0L and 0w are not legal. */
1049 static const char f32_1
[] =
1051 static const char f32_2
[] =
1052 {0x66,0x90}; /* xchg %ax,%ax */
1053 static const char f32_3
[] =
1054 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1055 static const char f32_4
[] =
1056 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1057 static const char f32_5
[] =
1059 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1060 static const char f32_6
[] =
1061 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1062 static const char f32_7
[] =
1063 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1064 static const char f32_8
[] =
1066 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1067 static const char f32_9
[] =
1068 {0x89,0xf6, /* movl %esi,%esi */
1069 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1070 static const char f32_10
[] =
1071 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1072 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1073 static const char f32_11
[] =
1074 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1075 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1076 static const char f32_12
[] =
1077 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1078 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1079 static const char f32_13
[] =
1080 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1081 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1082 static const char f32_14
[] =
1083 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1084 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1085 static const char f16_3
[] =
1086 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1087 static const char f16_4
[] =
1088 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1089 static const char f16_5
[] =
1091 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1092 static const char f16_6
[] =
1093 {0x89,0xf6, /* mov %si,%si */
1094 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1095 static const char f16_7
[] =
1096 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1097 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1098 static const char f16_8
[] =
1099 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1100 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1101 static const char jump_31
[] =
1102 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1103 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1104 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1105 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1106 static const char *const f32_patt
[] = {
1107 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1108 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1110 static const char *const f16_patt
[] = {
1111 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1113 /* nopl (%[re]ax) */
1114 static const char alt_3
[] =
1116 /* nopl 0(%[re]ax) */
1117 static const char alt_4
[] =
1118 {0x0f,0x1f,0x40,0x00};
1119 /* nopl 0(%[re]ax,%[re]ax,1) */
1120 static const char alt_5
[] =
1121 {0x0f,0x1f,0x44,0x00,0x00};
1122 /* nopw 0(%[re]ax,%[re]ax,1) */
1123 static const char alt_6
[] =
1124 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1125 /* nopl 0L(%[re]ax) */
1126 static const char alt_7
[] =
1127 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1128 /* nopl 0L(%[re]ax,%[re]ax,1) */
1129 static const char alt_8
[] =
1130 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* nopw 0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_9
[] =
1133 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1134 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1135 static const char alt_10
[] =
1136 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1138 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_long_11
[] =
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1145 static const char alt_long_12
[] =
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1152 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1153 static const char alt_long_13
[] =
1157 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1162 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1163 static const char alt_long_14
[] =
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1174 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1175 static const char alt_long_15
[] =
1181 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1182 /* nopl 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_11
[] =
1185 {0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1188 nopw 0(%[re]ax,%[re]ax,1) */
1189 static const char alt_short_12
[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x66,0x0f,0x1f,0x44,0x00,0x00};
1192 /* nopw 0(%[re]ax,%[re]ax,1)
1194 static const char alt_short_13
[] =
1195 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1199 static const char alt_short_14
[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1203 nopl 0L(%[re]ax,%[re]ax,1) */
1204 static const char alt_short_15
[] =
1205 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1206 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1207 static const char *const alt_short_patt
[] = {
1208 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1209 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1210 alt_short_14
, alt_short_15
1212 static const char *const alt_long_patt
[] = {
1213 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1214 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1215 alt_long_14
, alt_long_15
1218 /* Only align for at least a positive non-zero boundary. */
1219 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1222 /* We need to decide which NOP sequence to use for 32bit and
1223 64bit. When -mtune= is used:
1225 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1226 PROCESSOR_GENERIC32, f32_patt will be used.
1227 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1228 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1229 PROCESSOR_GENERIC64, alt_long_patt will be used.
1230 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1231 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1234 When -mtune= isn't used, alt_long_patt will be used if
1235 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1238 When -march= or .arch is used, we can't use anything beyond
1239 cpu_arch_isa_flags. */
1241 if (flag_code
== CODE_16BIT
)
1245 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1247 /* Adjust jump offset. */
1248 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1251 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1252 f16_patt
[count
- 1], count
);
1256 const char *const *patt
= NULL
;
1258 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1260 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1261 switch (cpu_arch_tune
)
1263 case PROCESSOR_UNKNOWN
:
1264 /* We use cpu_arch_isa_flags to check if we SHOULD
1265 optimize with nops. */
1266 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1267 patt
= alt_long_patt
;
1271 case PROCESSOR_PENTIUM4
:
1272 case PROCESSOR_NOCONA
:
1273 case PROCESSOR_CORE
:
1274 case PROCESSOR_CORE2
:
1275 case PROCESSOR_COREI7
:
1276 case PROCESSOR_L1OM
:
1277 case PROCESSOR_K1OM
:
1278 case PROCESSOR_GENERIC64
:
1279 patt
= alt_long_patt
;
1282 case PROCESSOR_ATHLON
:
1284 case PROCESSOR_AMDFAM10
:
1287 patt
= alt_short_patt
;
1289 case PROCESSOR_I386
:
1290 case PROCESSOR_I486
:
1291 case PROCESSOR_PENTIUM
:
1292 case PROCESSOR_PENTIUMPRO
:
1293 case PROCESSOR_GENERIC32
:
1300 switch (fragP
->tc_frag_data
.tune
)
1302 case PROCESSOR_UNKNOWN
:
1303 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1304 PROCESSOR_UNKNOWN. */
1308 case PROCESSOR_I386
:
1309 case PROCESSOR_I486
:
1310 case PROCESSOR_PENTIUM
:
1312 case PROCESSOR_ATHLON
:
1314 case PROCESSOR_AMDFAM10
:
1317 case PROCESSOR_GENERIC32
:
1318 /* We use cpu_arch_isa_flags to check if we CAN optimize
1320 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1321 patt
= alt_short_patt
;
1325 case PROCESSOR_PENTIUMPRO
:
1326 case PROCESSOR_PENTIUM4
:
1327 case PROCESSOR_NOCONA
:
1328 case PROCESSOR_CORE
:
1329 case PROCESSOR_CORE2
:
1330 case PROCESSOR_COREI7
:
1331 case PROCESSOR_L1OM
:
1332 case PROCESSOR_K1OM
:
1333 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1334 patt
= alt_long_patt
;
1338 case PROCESSOR_GENERIC64
:
1339 patt
= alt_long_patt
;
1344 if (patt
== f32_patt
)
1346 /* If the padding is less than 15 bytes, we use the normal
1347 ones. Otherwise, we use a jump instruction and adjust
1351 /* For 64bit, the limit is 3 bytes. */
1352 if (flag_code
== CODE_64BIT
1353 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1358 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1359 patt
[count
- 1], count
);
1362 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1364 /* Adjust jump offset. */
1365 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1370 /* Maximum length of an instruction is 15 byte. If the
1371 padding is greater than 15 bytes and we don't use jump,
1372 we have to break it into smaller pieces. */
1373 int padding
= count
;
1374 while (padding
> 15)
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1382 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1383 patt
[padding
- 1], padding
);
1386 fragP
->fr_var
= count
;
1390 operand_type_all_zero (const union i386_operand_type
*x
)
1392 switch (ARRAY_SIZE(x
->array
))
1401 return !x
->array
[0];
1408 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1410 switch (ARRAY_SIZE(x
->array
))
1425 operand_type_equal (const union i386_operand_type
*x
,
1426 const union i386_operand_type
*y
)
1428 switch (ARRAY_SIZE(x
->array
))
1431 if (x
->array
[2] != y
->array
[2])
1434 if (x
->array
[1] != y
->array
[1])
1437 return x
->array
[0] == y
->array
[0];
1445 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1447 switch (ARRAY_SIZE(x
->array
))
1456 return !x
->array
[0];
1463 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1465 switch (ARRAY_SIZE(x
->array
))
1480 cpu_flags_equal (const union i386_cpu_flags
*x
,
1481 const union i386_cpu_flags
*y
)
1483 switch (ARRAY_SIZE(x
->array
))
1486 if (x
->array
[2] != y
->array
[2])
1489 if (x
->array
[1] != y
->array
[1])
1492 return x
->array
[0] == y
->array
[0];
1500 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1502 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1503 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1506 static INLINE i386_cpu_flags
1507 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1509 switch (ARRAY_SIZE (x
.array
))
1512 x
.array
[2] &= y
.array
[2];
1514 x
.array
[1] &= y
.array
[1];
1516 x
.array
[0] &= y
.array
[0];
1524 static INLINE i386_cpu_flags
1525 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1527 switch (ARRAY_SIZE (x
.array
))
1530 x
.array
[2] |= y
.array
[2];
1532 x
.array
[1] |= y
.array
[1];
1534 x
.array
[0] |= y
.array
[0];
1542 static INLINE i386_cpu_flags
1543 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1545 switch (ARRAY_SIZE (x
.array
))
1548 x
.array
[2] &= ~y
.array
[2];
1550 x
.array
[1] &= ~y
.array
[1];
1552 x
.array
[0] &= ~y
.array
[0];
1560 #define CPU_FLAGS_ARCH_MATCH 0x1
1561 #define CPU_FLAGS_64BIT_MATCH 0x2
1562 #define CPU_FLAGS_AES_MATCH 0x4
1563 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1564 #define CPU_FLAGS_AVX_MATCH 0x10
1566 #define CPU_FLAGS_32BIT_MATCH \
1567 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1568 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1569 #define CPU_FLAGS_PERFECT_MATCH \
1570 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1572 /* Return CPU flags match bits. */
1575 cpu_flags_match (const insn_template
*t
)
1577 i386_cpu_flags x
= t
->cpu_flags
;
1578 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1580 x
.bitfield
.cpu64
= 0;
1581 x
.bitfield
.cpuno64
= 0;
1583 if (cpu_flags_all_zero (&x
))
1585 /* This instruction is available on all archs. */
1586 match
|= CPU_FLAGS_32BIT_MATCH
;
1590 /* This instruction is available only on some archs. */
1591 i386_cpu_flags cpu
= cpu_arch_flags
;
1593 cpu
.bitfield
.cpu64
= 0;
1594 cpu
.bitfield
.cpuno64
= 0;
1595 cpu
= cpu_flags_and (x
, cpu
);
1596 if (!cpu_flags_all_zero (&cpu
))
1598 if (x
.bitfield
.cpuavx
)
1600 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1601 if (cpu
.bitfield
.cpuavx
)
1603 /* Check SSE2AVX. */
1604 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1606 match
|= (CPU_FLAGS_ARCH_MATCH
1607 | CPU_FLAGS_AVX_MATCH
);
1609 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1610 match
|= CPU_FLAGS_AES_MATCH
;
1612 if (!x
.bitfield
.cpupclmul
1613 || cpu
.bitfield
.cpupclmul
)
1614 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1618 match
|= CPU_FLAGS_ARCH_MATCH
;
1621 match
|= CPU_FLAGS_32BIT_MATCH
;
1627 static INLINE i386_operand_type
1628 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1630 switch (ARRAY_SIZE (x
.array
))
1633 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1637 x
.array
[0] &= y
.array
[0];
1645 static INLINE i386_operand_type
1646 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1648 switch (ARRAY_SIZE (x
.array
))
1651 x
.array
[2] |= y
.array
[2];
1653 x
.array
[1] |= y
.array
[1];
1655 x
.array
[0] |= y
.array
[0];
1663 static INLINE i386_operand_type
1664 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1666 switch (ARRAY_SIZE (x
.array
))
1669 x
.array
[2] ^= y
.array
[2];
1671 x
.array
[1] ^= y
.array
[1];
1673 x
.array
[0] ^= y
.array
[0];
1681 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1682 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1683 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1684 static const i386_operand_type inoutportreg
1685 = OPERAND_TYPE_INOUTPORTREG
;
1686 static const i386_operand_type reg16_inoutportreg
1687 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1688 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1689 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1690 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1691 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1692 static const i386_operand_type anydisp
1693 = OPERAND_TYPE_ANYDISP
;
1694 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1695 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1696 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1697 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1698 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1699 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1700 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1701 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1702 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1703 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1704 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1705 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1706 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1707 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1718 operand_type_check (i386_operand_type t
, enum operand_type c
)
1723 return (t
.bitfield
.reg8
1726 || t
.bitfield
.reg64
);
1729 return (t
.bitfield
.imm8
1733 || t
.bitfield
.imm32s
1734 || t
.bitfield
.imm64
);
1737 return (t
.bitfield
.disp8
1738 || t
.bitfield
.disp16
1739 || t
.bitfield
.disp32
1740 || t
.bitfield
.disp32s
1741 || t
.bitfield
.disp64
);
1744 return (t
.bitfield
.disp8
1745 || t
.bitfield
.disp16
1746 || t
.bitfield
.disp32
1747 || t
.bitfield
.disp32s
1748 || t
.bitfield
.disp64
1749 || t
.bitfield
.baseindex
);
1758 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1759 operand J for instruction template T. */
1762 match_reg_size (const insn_template
*t
, unsigned int j
)
1764 return !((i
.types
[j
].bitfield
.byte
1765 && !t
->operand_types
[j
].bitfield
.byte
)
1766 || (i
.types
[j
].bitfield
.word
1767 && !t
->operand_types
[j
].bitfield
.word
)
1768 || (i
.types
[j
].bitfield
.dword
1769 && !t
->operand_types
[j
].bitfield
.dword
)
1770 || (i
.types
[j
].bitfield
.qword
1771 && !t
->operand_types
[j
].bitfield
.qword
));
1774 /* Return 1 if there is no conflict in any size on operand J for
1775 instruction template T. */
1778 match_mem_size (const insn_template
*t
, unsigned int j
)
1780 return (match_reg_size (t
, j
)
1781 && !((i
.types
[j
].bitfield
.unspecified
1782 && !t
->operand_types
[j
].bitfield
.unspecified
)
1783 || (i
.types
[j
].bitfield
.fword
1784 && !t
->operand_types
[j
].bitfield
.fword
)
1785 || (i
.types
[j
].bitfield
.tbyte
1786 && !t
->operand_types
[j
].bitfield
.tbyte
)
1787 || (i
.types
[j
].bitfield
.xmmword
1788 && !t
->operand_types
[j
].bitfield
.xmmword
)
1789 || (i
.types
[j
].bitfield
.ymmword
1790 && !t
->operand_types
[j
].bitfield
.ymmword
)
1791 || (i
.types
[j
].bitfield
.zmmword
1792 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1795 /* Return 1 if there is no size conflict on any operands for
1796 instruction template T. */
1799 operand_size_match (const insn_template
*t
)
1804 /* Don't check jump instructions. */
1805 if (t
->opcode_modifier
.jump
1806 || t
->opcode_modifier
.jumpbyte
1807 || t
->opcode_modifier
.jumpdword
1808 || t
->opcode_modifier
.jumpintersegment
)
1811 /* Check memory and accumulator operand size. */
1812 for (j
= 0; j
< i
.operands
; j
++)
1814 if (t
->operand_types
[j
].bitfield
.anysize
)
1817 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1823 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1832 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1835 i
.error
= operand_size_mismatch
;
1839 /* Check reverse. */
1840 gas_assert (i
.operands
== 2);
1843 for (j
= 0; j
< 2; j
++)
1845 if (t
->operand_types
[j
].bitfield
.acc
1846 && !match_reg_size (t
, j
? 0 : 1))
1849 if (i
.types
[j
].bitfield
.mem
1850 && !match_mem_size (t
, j
? 0 : 1))
1858 operand_type_match (i386_operand_type overlap
,
1859 i386_operand_type given
)
1861 i386_operand_type temp
= overlap
;
1863 temp
.bitfield
.jumpabsolute
= 0;
1864 temp
.bitfield
.unspecified
= 0;
1865 temp
.bitfield
.byte
= 0;
1866 temp
.bitfield
.word
= 0;
1867 temp
.bitfield
.dword
= 0;
1868 temp
.bitfield
.fword
= 0;
1869 temp
.bitfield
.qword
= 0;
1870 temp
.bitfield
.tbyte
= 0;
1871 temp
.bitfield
.xmmword
= 0;
1872 temp
.bitfield
.ymmword
= 0;
1873 temp
.bitfield
.zmmword
= 0;
1874 if (operand_type_all_zero (&temp
))
1877 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1878 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1882 i
.error
= operand_type_mismatch
;
1886 /* If given types g0 and g1 are registers they must be of the same type
1887 unless the expected operand type register overlap is null.
1888 Note that Acc in a template matches every size of reg. */
1891 operand_type_register_match (i386_operand_type m0
,
1892 i386_operand_type g0
,
1893 i386_operand_type t0
,
1894 i386_operand_type m1
,
1895 i386_operand_type g1
,
1896 i386_operand_type t1
)
1898 if (!operand_type_check (g0
, reg
))
1901 if (!operand_type_check (g1
, reg
))
1904 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1905 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1906 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1907 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1910 if (m0
.bitfield
.acc
)
1912 t0
.bitfield
.reg8
= 1;
1913 t0
.bitfield
.reg16
= 1;
1914 t0
.bitfield
.reg32
= 1;
1915 t0
.bitfield
.reg64
= 1;
1918 if (m1
.bitfield
.acc
)
1920 t1
.bitfield
.reg8
= 1;
1921 t1
.bitfield
.reg16
= 1;
1922 t1
.bitfield
.reg32
= 1;
1923 t1
.bitfield
.reg64
= 1;
1926 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1927 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1928 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1929 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1932 i
.error
= register_type_mismatch
;
1937 static INLINE
unsigned int
1938 register_number (const reg_entry
*r
)
1940 unsigned int nr
= r
->reg_num
;
1942 if (r
->reg_flags
& RegRex
)
1948 static INLINE
unsigned int
1949 mode_from_disp_size (i386_operand_type t
)
1951 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1953 else if (t
.bitfield
.disp16
1954 || t
.bitfield
.disp32
1955 || t
.bitfield
.disp32s
)
1962 fits_in_signed_byte (addressT num
)
1964 return num
+ 0x80 <= 0xff;
1968 fits_in_unsigned_byte (addressT num
)
1974 fits_in_unsigned_word (addressT num
)
1976 return num
<= 0xffff;
1980 fits_in_signed_word (addressT num
)
1982 return num
+ 0x8000 <= 0xffff;
1986 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1991 return num
+ 0x80000000 <= 0xffffffff;
1993 } /* fits_in_signed_long() */
1996 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2001 return num
<= 0xffffffff;
2003 } /* fits_in_unsigned_long() */
2006 fits_in_vec_disp8 (offsetT num
)
2008 int shift
= i
.memshift
;
2014 mask
= (1 << shift
) - 1;
2016 /* Return 0 if NUM isn't properly aligned. */
2020 /* Check if NUM will fit in 8bit after shift. */
2021 return fits_in_signed_byte (num
>> shift
);
2025 fits_in_imm4 (offsetT num
)
2027 return (num
& 0xf) == num
;
2030 static i386_operand_type
2031 smallest_imm_type (offsetT num
)
2033 i386_operand_type t
;
2035 operand_type_set (&t
, 0);
2036 t
.bitfield
.imm64
= 1;
2038 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2040 /* This code is disabled on the 486 because all the Imm1 forms
2041 in the opcode table are slower on the i486. They're the
2042 versions with the implicitly specified single-position
2043 displacement, which has another syntax if you really want to
2045 t
.bitfield
.imm1
= 1;
2046 t
.bitfield
.imm8
= 1;
2047 t
.bitfield
.imm8s
= 1;
2048 t
.bitfield
.imm16
= 1;
2049 t
.bitfield
.imm32
= 1;
2050 t
.bitfield
.imm32s
= 1;
2052 else if (fits_in_signed_byte (num
))
2054 t
.bitfield
.imm8
= 1;
2055 t
.bitfield
.imm8s
= 1;
2056 t
.bitfield
.imm16
= 1;
2057 t
.bitfield
.imm32
= 1;
2058 t
.bitfield
.imm32s
= 1;
2060 else if (fits_in_unsigned_byte (num
))
2062 t
.bitfield
.imm8
= 1;
2063 t
.bitfield
.imm16
= 1;
2064 t
.bitfield
.imm32
= 1;
2065 t
.bitfield
.imm32s
= 1;
2067 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2069 t
.bitfield
.imm16
= 1;
2070 t
.bitfield
.imm32
= 1;
2071 t
.bitfield
.imm32s
= 1;
2073 else if (fits_in_signed_long (num
))
2075 t
.bitfield
.imm32
= 1;
2076 t
.bitfield
.imm32s
= 1;
2078 else if (fits_in_unsigned_long (num
))
2079 t
.bitfield
.imm32
= 1;
2085 offset_in_range (offsetT val
, int size
)
2091 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2092 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2093 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2095 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2101 /* If BFD64, sign extend val for 32bit address mode. */
2102 if (flag_code
!= CODE_64BIT
2103 || i
.prefix
[ADDR_PREFIX
])
2104 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2105 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2108 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2110 char buf1
[40], buf2
[40];
2112 sprint_value (buf1
, val
);
2113 sprint_value (buf2
, val
& mask
);
2114 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2128 a. PREFIX_EXIST if attempting to add a prefix where one from the
2129 same class already exists.
2130 b. PREFIX_LOCK if lock prefix is added.
2131 c. PREFIX_REP if rep/repne prefix is added.
2132 d. PREFIX_OTHER if other prefix is added.
2135 static enum PREFIX_GROUP
2136 add_prefix (unsigned int prefix
)
2138 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2141 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2142 && flag_code
== CODE_64BIT
)
2144 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2145 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2146 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2157 case CS_PREFIX_OPCODE
:
2158 case DS_PREFIX_OPCODE
:
2159 case ES_PREFIX_OPCODE
:
2160 case FS_PREFIX_OPCODE
:
2161 case GS_PREFIX_OPCODE
:
2162 case SS_PREFIX_OPCODE
:
2166 case REPNE_PREFIX_OPCODE
:
2167 case REPE_PREFIX_OPCODE
:
2172 case LOCK_PREFIX_OPCODE
:
2181 case ADDR_PREFIX_OPCODE
:
2185 case DATA_PREFIX_OPCODE
:
2189 if (i
.prefix
[q
] != 0)
2197 i
.prefix
[q
] |= prefix
;
2200 as_bad (_("same type of prefix used twice"));
2206 update_code_flag (int value
, int check
)
2208 PRINTF_LIKE ((*as_error
));
2210 flag_code
= (enum flag_code
) value
;
2211 if (flag_code
== CODE_64BIT
)
2213 cpu_arch_flags
.bitfield
.cpu64
= 1;
2214 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2218 cpu_arch_flags
.bitfield
.cpu64
= 0;
2219 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2221 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2224 as_error
= as_fatal
;
2227 (*as_error
) (_("64bit mode not supported on `%s'."),
2228 cpu_arch_name
? cpu_arch_name
: default_arch
);
2230 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2233 as_error
= as_fatal
;
2236 (*as_error
) (_("32bit mode not supported on `%s'."),
2237 cpu_arch_name
? cpu_arch_name
: default_arch
);
2239 stackop_size
= '\0';
2243 set_code_flag (int value
)
2245 update_code_flag (value
, 0);
2249 set_16bit_gcc_code_flag (int new_code_flag
)
2251 flag_code
= (enum flag_code
) new_code_flag
;
2252 if (flag_code
!= CODE_16BIT
)
2254 cpu_arch_flags
.bitfield
.cpu64
= 0;
2255 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2256 stackop_size
= LONG_MNEM_SUFFIX
;
2260 set_intel_syntax (int syntax_flag
)
2262 /* Find out if register prefixing is specified. */
2263 int ask_naked_reg
= 0;
2266 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2268 char *string
= input_line_pointer
;
2269 int e
= get_symbol_end ();
2271 if (strcmp (string
, "prefix") == 0)
2273 else if (strcmp (string
, "noprefix") == 0)
2276 as_bad (_("bad argument to syntax directive."));
2277 *input_line_pointer
= e
;
2279 demand_empty_rest_of_line ();
2281 intel_syntax
= syntax_flag
;
2283 if (ask_naked_reg
== 0)
2284 allow_naked_reg
= (intel_syntax
2285 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2287 allow_naked_reg
= (ask_naked_reg
< 0);
2289 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2291 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2292 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2293 register_prefix
= allow_naked_reg
? "" : "%";
2297 set_intel_mnemonic (int mnemonic_flag
)
2299 intel_mnemonic
= mnemonic_flag
;
2303 set_allow_index_reg (int flag
)
2305 allow_index_reg
= flag
;
2309 set_check (int what
)
2311 enum check_kind
*kind
;
2316 kind
= &operand_check
;
2327 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2329 char *string
= input_line_pointer
;
2330 int e
= get_symbol_end ();
2332 if (strcmp (string
, "none") == 0)
2334 else if (strcmp (string
, "warning") == 0)
2335 *kind
= check_warning
;
2336 else if (strcmp (string
, "error") == 0)
2337 *kind
= check_error
;
2339 as_bad (_("bad argument to %s_check directive."), str
);
2340 *input_line_pointer
= e
;
2343 as_bad (_("missing argument for %s_check directive"), str
);
2345 demand_empty_rest_of_line ();
2349 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2350 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2353 static const char *arch
;
2355 /* Intel LIOM is only supported on ELF. */
2361 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2362 use default_arch. */
2363 arch
= cpu_arch_name
;
2365 arch
= default_arch
;
2368 /* If we are targeting Intel L1OM, we must enable it. */
2369 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2370 || new_flag
.bitfield
.cpul1om
)
2373 /* If we are targeting Intel K1OM, we must enable it. */
2374 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2375 || new_flag
.bitfield
.cpuk1om
)
2378 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2383 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2387 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2389 char *string
= input_line_pointer
;
2390 int e
= get_symbol_end ();
2392 i386_cpu_flags flags
;
2394 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2396 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2398 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2402 cpu_arch_name
= cpu_arch
[j
].name
;
2403 cpu_sub_arch_name
= NULL
;
2404 cpu_arch_flags
= cpu_arch
[j
].flags
;
2405 if (flag_code
== CODE_64BIT
)
2407 cpu_arch_flags
.bitfield
.cpu64
= 1;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2412 cpu_arch_flags
.bitfield
.cpu64
= 0;
2413 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2415 cpu_arch_isa
= cpu_arch
[j
].type
;
2416 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2417 if (!cpu_arch_tune_set
)
2419 cpu_arch_tune
= cpu_arch_isa
;
2420 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2425 if (!cpu_arch
[j
].negated
)
2426 flags
= cpu_flags_or (cpu_arch_flags
,
2429 flags
= cpu_flags_and_not (cpu_arch_flags
,
2431 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2433 if (cpu_sub_arch_name
)
2435 char *name
= cpu_sub_arch_name
;
2436 cpu_sub_arch_name
= concat (name
,
2438 (const char *) NULL
);
2442 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2443 cpu_arch_flags
= flags
;
2444 cpu_arch_isa_flags
= flags
;
2446 *input_line_pointer
= e
;
2447 demand_empty_rest_of_line ();
2451 if (j
>= ARRAY_SIZE (cpu_arch
))
2452 as_bad (_("no such architecture: `%s'"), string
);
2454 *input_line_pointer
= e
;
2457 as_bad (_("missing cpu architecture"));
2459 no_cond_jump_promotion
= 0;
2460 if (*input_line_pointer
== ','
2461 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2463 char *string
= ++input_line_pointer
;
2464 int e
= get_symbol_end ();
2466 if (strcmp (string
, "nojumps") == 0)
2467 no_cond_jump_promotion
= 1;
2468 else if (strcmp (string
, "jumps") == 0)
2471 as_bad (_("no such architecture modifier: `%s'"), string
);
2473 *input_line_pointer
= e
;
2476 demand_empty_rest_of_line ();
2479 enum bfd_architecture
2482 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2484 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2485 || flag_code
!= CODE_64BIT
)
2486 as_fatal (_("Intel L1OM is 64bit ELF only"));
2487 return bfd_arch_l1om
;
2489 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2491 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2492 || flag_code
!= CODE_64BIT
)
2493 as_fatal (_("Intel K1OM is 64bit ELF only"));
2494 return bfd_arch_k1om
;
2497 return bfd_arch_i386
;
2503 if (!strncmp (default_arch
, "x86_64", 6))
2505 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2507 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2508 || default_arch
[6] != '\0')
2509 as_fatal (_("Intel L1OM is 64bit ELF only"));
2510 return bfd_mach_l1om
;
2512 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2514 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2515 || default_arch
[6] != '\0')
2516 as_fatal (_("Intel K1OM is 64bit ELF only"));
2517 return bfd_mach_k1om
;
2519 else if (default_arch
[6] == '\0')
2520 return bfd_mach_x86_64
;
2522 return bfd_mach_x64_32
;
2524 else if (!strcmp (default_arch
, "i386"))
2525 return bfd_mach_i386_i386
;
2527 as_fatal (_("unknown architecture"));
2533 const char *hash_err
;
2535 /* Initialize op_hash hash table. */
2536 op_hash
= hash_new ();
2539 const insn_template
*optab
;
2540 templates
*core_optab
;
2542 /* Setup for loop. */
2544 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2545 core_optab
->start
= optab
;
2550 if (optab
->name
== NULL
2551 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2553 /* different name --> ship out current template list;
2554 add to hash table; & begin anew. */
2555 core_optab
->end
= optab
;
2556 hash_err
= hash_insert (op_hash
,
2558 (void *) core_optab
);
2561 as_fatal (_("can't hash %s: %s"),
2565 if (optab
->name
== NULL
)
2567 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2568 core_optab
->start
= optab
;
2573 /* Initialize reg_hash hash table. */
2574 reg_hash
= hash_new ();
2576 const reg_entry
*regtab
;
2577 unsigned int regtab_size
= i386_regtab_size
;
2579 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2581 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2583 as_fatal (_("can't hash %s: %s"),
2589 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2594 for (c
= 0; c
< 256; c
++)
2599 mnemonic_chars
[c
] = c
;
2600 register_chars
[c
] = c
;
2601 operand_chars
[c
] = c
;
2603 else if (ISLOWER (c
))
2605 mnemonic_chars
[c
] = c
;
2606 register_chars
[c
] = c
;
2607 operand_chars
[c
] = c
;
2609 else if (ISUPPER (c
))
2611 mnemonic_chars
[c
] = TOLOWER (c
);
2612 register_chars
[c
] = mnemonic_chars
[c
];
2613 operand_chars
[c
] = c
;
2615 else if (c
== '{' || c
== '}')
2616 operand_chars
[c
] = c
;
2618 if (ISALPHA (c
) || ISDIGIT (c
))
2619 identifier_chars
[c
] = c
;
2622 identifier_chars
[c
] = c
;
2623 operand_chars
[c
] = c
;
2628 identifier_chars
['@'] = '@';
2631 identifier_chars
['?'] = '?';
2632 operand_chars
['?'] = '?';
2634 digit_chars
['-'] = '-';
2635 mnemonic_chars
['_'] = '_';
2636 mnemonic_chars
['-'] = '-';
2637 mnemonic_chars
['.'] = '.';
2638 identifier_chars
['_'] = '_';
2639 identifier_chars
['.'] = '.';
2641 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2642 operand_chars
[(unsigned char) *p
] = *p
;
2645 if (flag_code
== CODE_64BIT
)
2647 #if defined (OBJ_COFF) && defined (TE_PE)
2648 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2651 x86_dwarf2_return_column
= 16;
2653 x86_cie_data_alignment
= -8;
2657 x86_dwarf2_return_column
= 8;
2658 x86_cie_data_alignment
= -4;
2663 i386_print_statistics (FILE *file
)
2665 hash_print_statistics (file
, "i386 opcode", op_hash
);
2666 hash_print_statistics (file
, "i386 register", reg_hash
);
2671 /* Debugging routines for md_assemble. */
2672 static void pte (insn_template
*);
2673 static void pt (i386_operand_type
);
2674 static void pe (expressionS
*);
2675 static void ps (symbolS
*);
2678 pi (char *line
, i386_insn
*x
)
2682 fprintf (stdout
, "%s: template ", line
);
2684 fprintf (stdout
, " address: base %s index %s scale %x\n",
2685 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2686 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2687 x
->log2_scale_factor
);
2688 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2689 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2690 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2691 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2692 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2693 (x
->rex
& REX_W
) != 0,
2694 (x
->rex
& REX_R
) != 0,
2695 (x
->rex
& REX_X
) != 0,
2696 (x
->rex
& REX_B
) != 0);
2697 for (j
= 0; j
< x
->operands
; j
++)
2699 fprintf (stdout
, " #%d: ", j
+ 1);
2701 fprintf (stdout
, "\n");
2702 if (x
->types
[j
].bitfield
.reg8
2703 || x
->types
[j
].bitfield
.reg16
2704 || x
->types
[j
].bitfield
.reg32
2705 || x
->types
[j
].bitfield
.reg64
2706 || x
->types
[j
].bitfield
.regmmx
2707 || x
->types
[j
].bitfield
.regxmm
2708 || x
->types
[j
].bitfield
.regymm
2709 || x
->types
[j
].bitfield
.regzmm
2710 || x
->types
[j
].bitfield
.sreg2
2711 || x
->types
[j
].bitfield
.sreg3
2712 || x
->types
[j
].bitfield
.control
2713 || x
->types
[j
].bitfield
.debug
2714 || x
->types
[j
].bitfield
.test
)
2715 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2716 if (operand_type_check (x
->types
[j
], imm
))
2718 if (operand_type_check (x
->types
[j
], disp
))
2719 pe (x
->op
[j
].disps
);
2724 pte (insn_template
*t
)
2727 fprintf (stdout
, " %d operands ", t
->operands
);
2728 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2729 if (t
->extension_opcode
!= None
)
2730 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2731 if (t
->opcode_modifier
.d
)
2732 fprintf (stdout
, "D");
2733 if (t
->opcode_modifier
.w
)
2734 fprintf (stdout
, "W");
2735 fprintf (stdout
, "\n");
2736 for (j
= 0; j
< t
->operands
; j
++)
2738 fprintf (stdout
, " #%d type ", j
+ 1);
2739 pt (t
->operand_types
[j
]);
2740 fprintf (stdout
, "\n");
2747 fprintf (stdout
, " operation %d\n", e
->X_op
);
2748 fprintf (stdout
, " add_number %ld (%lx)\n",
2749 (long) e
->X_add_number
, (long) e
->X_add_number
);
2750 if (e
->X_add_symbol
)
2752 fprintf (stdout
, " add_symbol ");
2753 ps (e
->X_add_symbol
);
2754 fprintf (stdout
, "\n");
2758 fprintf (stdout
, " op_symbol ");
2759 ps (e
->X_op_symbol
);
2760 fprintf (stdout
, "\n");
2767 fprintf (stdout
, "%s type %s%s",
2769 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2770 segment_name (S_GET_SEGMENT (s
)));
2773 static struct type_name
2775 i386_operand_type mask
;
2778 const type_names
[] =
2780 { OPERAND_TYPE_REG8
, "r8" },
2781 { OPERAND_TYPE_REG16
, "r16" },
2782 { OPERAND_TYPE_REG32
, "r32" },
2783 { OPERAND_TYPE_REG64
, "r64" },
2784 { OPERAND_TYPE_IMM8
, "i8" },
2785 { OPERAND_TYPE_IMM8
, "i8s" },
2786 { OPERAND_TYPE_IMM16
, "i16" },
2787 { OPERAND_TYPE_IMM32
, "i32" },
2788 { OPERAND_TYPE_IMM32S
, "i32s" },
2789 { OPERAND_TYPE_IMM64
, "i64" },
2790 { OPERAND_TYPE_IMM1
, "i1" },
2791 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2792 { OPERAND_TYPE_DISP8
, "d8" },
2793 { OPERAND_TYPE_DISP16
, "d16" },
2794 { OPERAND_TYPE_DISP32
, "d32" },
2795 { OPERAND_TYPE_DISP32S
, "d32s" },
2796 { OPERAND_TYPE_DISP64
, "d64" },
2797 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2798 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2799 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2800 { OPERAND_TYPE_CONTROL
, "control reg" },
2801 { OPERAND_TYPE_TEST
, "test reg" },
2802 { OPERAND_TYPE_DEBUG
, "debug reg" },
2803 { OPERAND_TYPE_FLOATREG
, "FReg" },
2804 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2805 { OPERAND_TYPE_SREG2
, "SReg2" },
2806 { OPERAND_TYPE_SREG3
, "SReg3" },
2807 { OPERAND_TYPE_ACC
, "Acc" },
2808 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2809 { OPERAND_TYPE_REGMMX
, "rMMX" },
2810 { OPERAND_TYPE_REGXMM
, "rXMM" },
2811 { OPERAND_TYPE_REGYMM
, "rYMM" },
2812 { OPERAND_TYPE_REGZMM
, "rZMM" },
2813 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2814 { OPERAND_TYPE_ESSEG
, "es" },
2818 pt (i386_operand_type t
)
2821 i386_operand_type a
;
2823 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2825 a
= operand_type_and (t
, type_names
[j
].mask
);
2826 if (!operand_type_all_zero (&a
))
2827 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2832 #endif /* DEBUG386 */
2834 static bfd_reloc_code_real_type
2835 reloc (unsigned int size
,
2838 bfd_reloc_code_real_type other
)
2840 if (other
!= NO_RELOC
)
2842 reloc_howto_type
*rel
;
2847 case BFD_RELOC_X86_64_GOT32
:
2848 return BFD_RELOC_X86_64_GOT64
;
2850 case BFD_RELOC_X86_64_GOTPLT64
:
2851 return BFD_RELOC_X86_64_GOTPLT64
;
2853 case BFD_RELOC_X86_64_PLTOFF64
:
2854 return BFD_RELOC_X86_64_PLTOFF64
;
2856 case BFD_RELOC_X86_64_GOTPC32
:
2857 other
= BFD_RELOC_X86_64_GOTPC64
;
2859 case BFD_RELOC_X86_64_GOTPCREL
:
2860 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2862 case BFD_RELOC_X86_64_TPOFF32
:
2863 other
= BFD_RELOC_X86_64_TPOFF64
;
2865 case BFD_RELOC_X86_64_DTPOFF32
:
2866 other
= BFD_RELOC_X86_64_DTPOFF64
;
2872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2873 if (other
== BFD_RELOC_SIZE32
)
2876 other
= BFD_RELOC_SIZE64
;
2879 as_bad (_("there are no pc-relative size relocations"));
2885 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2886 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2889 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2891 as_bad (_("unknown relocation (%u)"), other
);
2892 else if (size
!= bfd_get_reloc_size (rel
))
2893 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2894 bfd_get_reloc_size (rel
),
2896 else if (pcrel
&& !rel
->pc_relative
)
2897 as_bad (_("non-pc-relative relocation for pc-relative field"));
2898 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2900 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2902 as_bad (_("relocated field and relocation type differ in signedness"));
2911 as_bad (_("there are no unsigned pc-relative relocations"));
2914 case 1: return BFD_RELOC_8_PCREL
;
2915 case 2: return BFD_RELOC_16_PCREL
;
2916 case 4: return BFD_RELOC_32_PCREL
;
2917 case 8: return BFD_RELOC_64_PCREL
;
2919 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2926 case 4: return BFD_RELOC_X86_64_32S
;
2931 case 1: return BFD_RELOC_8
;
2932 case 2: return BFD_RELOC_16
;
2933 case 4: return BFD_RELOC_32
;
2934 case 8: return BFD_RELOC_64
;
2936 as_bad (_("cannot do %s %u byte relocation"),
2937 sign
> 0 ? "signed" : "unsigned", size
);
2943 /* Here we decide which fixups can be adjusted to make them relative to
2944 the beginning of the section instead of the symbol. Basically we need
2945 to make sure that the dynamic relocations are done correctly, so in
2946 some cases we force the original symbol to be used. */
2949 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2955 /* Don't adjust pc-relative references to merge sections in 64-bit
2957 if (use_rela_relocations
2958 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2962 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2963 and changed later by validate_fix. */
2964 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2965 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2968 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2969 for size relocations. */
2970 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2971 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2972 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2973 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2974 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2975 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2976 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2977 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2978 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2979 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2980 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2981 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2982 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2983 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2984 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2986 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2987 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2988 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2989 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2990 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2992 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2993 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2994 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2995 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2996 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2997 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2998 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2999 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3006 intel_float_operand (const char *mnemonic
)
3008 /* Note that the value returned is meaningful only for opcodes with (memory)
3009 operands, hence the code here is free to improperly handle opcodes that
3010 have no operands (for better performance and smaller code). */
3012 if (mnemonic
[0] != 'f')
3013 return 0; /* non-math */
3015 switch (mnemonic
[1])
3017 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3018 the fs segment override prefix not currently handled because no
3019 call path can make opcodes without operands get here */
3021 return 2 /* integer op */;
3023 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3024 return 3; /* fldcw/fldenv */
3027 if (mnemonic
[2] != 'o' /* fnop */)
3028 return 3; /* non-waiting control op */
3031 if (mnemonic
[2] == 's')
3032 return 3; /* frstor/frstpm */
3035 if (mnemonic
[2] == 'a')
3036 return 3; /* fsave */
3037 if (mnemonic
[2] == 't')
3039 switch (mnemonic
[3])
3041 case 'c': /* fstcw */
3042 case 'd': /* fstdw */
3043 case 'e': /* fstenv */
3044 case 's': /* fsts[gw] */
3050 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3051 return 0; /* fxsave/fxrstor are not really math ops */
3058 /* Build the VEX prefix. */
3061 build_vex_prefix (const insn_template
*t
)
3063 unsigned int register_specifier
;
3064 unsigned int implied_prefix
;
3065 unsigned int vector_length
;
3067 /* Check register specifier. */
3068 if (i
.vex
.register_specifier
)
3070 register_specifier
=
3071 ~register_number (i
.vex
.register_specifier
) & 0xf;
3072 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3075 register_specifier
= 0xf;
3077 /* Use 2-byte VEX prefix by swappping destination and source
3080 && i
.operands
== i
.reg_operands
3081 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3082 && i
.tm
.opcode_modifier
.s
3085 unsigned int xchg
= i
.operands
- 1;
3086 union i386_op temp_op
;
3087 i386_operand_type temp_type
;
3089 temp_type
= i
.types
[xchg
];
3090 i
.types
[xchg
] = i
.types
[0];
3091 i
.types
[0] = temp_type
;
3092 temp_op
= i
.op
[xchg
];
3093 i
.op
[xchg
] = i
.op
[0];
3096 gas_assert (i
.rm
.mode
== 3);
3100 i
.rm
.regmem
= i
.rm
.reg
;
3103 /* Use the next insn. */
3107 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3108 vector_length
= avxscalar
;
3110 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3112 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3117 case DATA_PREFIX_OPCODE
:
3120 case REPE_PREFIX_OPCODE
:
3123 case REPNE_PREFIX_OPCODE
:
3130 /* Use 2-byte VEX prefix if possible. */
3131 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3132 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3133 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3135 /* 2-byte VEX prefix. */
3139 i
.vex
.bytes
[0] = 0xc5;
3141 /* Check the REX.R bit. */
3142 r
= (i
.rex
& REX_R
) ? 0 : 1;
3143 i
.vex
.bytes
[1] = (r
<< 7
3144 | register_specifier
<< 3
3145 | vector_length
<< 2
3150 /* 3-byte VEX prefix. */
3155 switch (i
.tm
.opcode_modifier
.vexopcode
)
3159 i
.vex
.bytes
[0] = 0xc4;
3163 i
.vex
.bytes
[0] = 0xc4;
3167 i
.vex
.bytes
[0] = 0xc4;
3171 i
.vex
.bytes
[0] = 0x8f;
3175 i
.vex
.bytes
[0] = 0x8f;
3179 i
.vex
.bytes
[0] = 0x8f;
3185 /* The high 3 bits of the second VEX byte are 1's compliment
3186 of RXB bits from REX. */
3187 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3189 /* Check the REX.W bit. */
3190 w
= (i
.rex
& REX_W
) ? 1 : 0;
3191 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3194 i
.vex
.bytes
[2] = (w
<< 7
3195 | register_specifier
<< 3
3196 | vector_length
<< 2
3201 /* Build the EVEX prefix. */
3204 build_evex_prefix (void)
3206 unsigned int register_specifier
;
3207 unsigned int implied_prefix
;
3209 rex_byte vrex_used
= 0;
3211 /* Check register specifier. */
3212 if (i
.vex
.register_specifier
)
3214 gas_assert ((i
.vrex
& REX_X
) == 0);
3216 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3217 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3218 register_specifier
+= 8;
3219 /* The upper 16 registers are encoded in the fourth byte of the
3221 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3222 i
.vex
.bytes
[3] = 0x8;
3223 register_specifier
= ~register_specifier
& 0xf;
3227 register_specifier
= 0xf;
3229 /* Encode upper 16 vector index register in the fourth byte of
3231 if (!(i
.vrex
& REX_X
))
3232 i
.vex
.bytes
[3] = 0x8;
3237 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3242 case DATA_PREFIX_OPCODE
:
3245 case REPE_PREFIX_OPCODE
:
3248 case REPNE_PREFIX_OPCODE
:
3255 /* 4 byte EVEX prefix. */
3257 i
.vex
.bytes
[0] = 0x62;
3260 switch (i
.tm
.opcode_modifier
.vexopcode
)
3276 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3278 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3280 /* The fifth bit of the second EVEX byte is 1's compliment of the
3281 REX_R bit in VREX. */
3282 if (!(i
.vrex
& REX_R
))
3283 i
.vex
.bytes
[1] |= 0x10;
3287 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3289 /* When all operands are registers, the REX_X bit in REX is not
3290 used. We reuse it to encode the upper 16 registers, which is
3291 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3292 as 1's compliment. */
3293 if ((i
.vrex
& REX_B
))
3296 i
.vex
.bytes
[1] &= ~0x40;
3300 /* EVEX instructions shouldn't need the REX prefix. */
3301 i
.vrex
&= ~vrex_used
;
3302 gas_assert (i
.vrex
== 0);
3304 /* Check the REX.W bit. */
3305 w
= (i
.rex
& REX_W
) ? 1 : 0;
3306 if (i
.tm
.opcode_modifier
.vexw
)
3308 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3311 /* If w is not set it means we are dealing with WIG instruction. */
3314 if (evexwig
== evexw1
)
3318 /* Encode the U bit. */
3319 implied_prefix
|= 0x4;
3321 /* The third byte of the EVEX prefix. */
3322 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3324 /* The fourth byte of the EVEX prefix. */
3325 /* The zeroing-masking bit. */
3326 if (i
.mask
&& i
.mask
->zeroing
)
3327 i
.vex
.bytes
[3] |= 0x80;
3329 /* Don't always set the broadcast bit if there is no RC. */
3332 /* Encode the vector length. */
3333 unsigned int vec_length
;
3335 switch (i
.tm
.opcode_modifier
.evex
)
3337 case EVEXLIG
: /* LL' is ignored */
3338 vec_length
= evexlig
<< 5;
3341 vec_length
= 0 << 5;
3344 vec_length
= 1 << 5;
3347 vec_length
= 2 << 5;
3353 i
.vex
.bytes
[3] |= vec_length
;
3354 /* Encode the broadcast bit. */
3356 i
.vex
.bytes
[3] |= 0x10;
3360 if (i
.rounding
->type
!= saeonly
)
3361 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3363 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3366 if (i
.mask
&& i
.mask
->mask
)
3367 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3371 process_immext (void)
3375 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3378 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3379 with an opcode suffix which is coded in the same place as an
3380 8-bit immediate field would be.
3381 Here we check those operands and remove them afterwards. */
3384 for (x
= 0; x
< i
.operands
; x
++)
3385 if (register_number (i
.op
[x
].regs
) != x
)
3386 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3387 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3393 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3394 which is coded in the same place as an 8-bit immediate field
3395 would be. Here we fake an 8-bit immediate operand from the
3396 opcode suffix stored in tm.extension_opcode.
3398 AVX instructions also use this encoding, for some of
3399 3 argument instructions. */
3401 gas_assert (i
.imm_operands
<= 1
3403 || ((i
.tm
.opcode_modifier
.vex
3404 || i
.tm
.opcode_modifier
.evex
)
3405 && i
.operands
<= 4)));
3407 exp
= &im_expressions
[i
.imm_operands
++];
3408 i
.op
[i
.operands
].imms
= exp
;
3409 i
.types
[i
.operands
] = imm8
;
3411 exp
->X_op
= O_constant
;
3412 exp
->X_add_number
= i
.tm
.extension_opcode
;
3413 i
.tm
.extension_opcode
= None
;
3420 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3425 as_bad (_("invalid instruction `%s' after `%s'"),
3426 i
.tm
.name
, i
.hle_prefix
);
3429 if (i
.prefix
[LOCK_PREFIX
])
3431 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3435 case HLEPrefixRelease
:
3436 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3438 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3442 if (i
.mem_operands
== 0
3443 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3445 as_bad (_("memory destination needed for instruction `%s'"
3446 " after `xrelease'"), i
.tm
.name
);
3453 /* This is the guts of the machine-dependent assembler. LINE points to a
3454 machine dependent instruction. This function is supposed to emit
3455 the frags/bytes it assembles to. */
3458 md_assemble (char *line
)
3461 char mnemonic
[MAX_MNEM_SIZE
];
3462 const insn_template
*t
;
3464 /* Initialize globals. */
3465 memset (&i
, '\0', sizeof (i
));
3466 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3467 i
.reloc
[j
] = NO_RELOC
;
3468 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3469 memset (im_expressions
, '\0', sizeof (im_expressions
));
3470 save_stack_p
= save_stack
;
3472 /* First parse an instruction mnemonic & call i386_operand for the operands.
3473 We assume that the scrubber has arranged it so that line[0] is the valid
3474 start of a (possibly prefixed) mnemonic. */
3476 line
= parse_insn (line
, mnemonic
);
3480 line
= parse_operands (line
, mnemonic
);
3485 /* Now we've parsed the mnemonic into a set of templates, and have the
3486 operands at hand. */
3488 /* All intel opcodes have reversed operands except for "bound" and
3489 "enter". We also don't reverse intersegment "jmp" and "call"
3490 instructions with 2 immediate operands so that the immediate segment
3491 precedes the offset, as it does when in AT&T mode. */
3494 && (strcmp (mnemonic
, "bound") != 0)
3495 && (strcmp (mnemonic
, "invlpga") != 0)
3496 && !(operand_type_check (i
.types
[0], imm
)
3497 && operand_type_check (i
.types
[1], imm
)))
3500 /* The order of the immediates should be reversed
3501 for 2 immediates extrq and insertq instructions */
3502 if (i
.imm_operands
== 2
3503 && (strcmp (mnemonic
, "extrq") == 0
3504 || strcmp (mnemonic
, "insertq") == 0))
3505 swap_2_operands (0, 1);
3510 /* Don't optimize displacement for movabs since it only takes 64bit
3513 && i
.disp_encoding
!= disp_encoding_32bit
3514 && (flag_code
!= CODE_64BIT
3515 || strcmp (mnemonic
, "movabs") != 0))
3518 /* Next, we find a template that matches the given insn,
3519 making sure the overlap of the given operands types is consistent
3520 with the template operand types. */
3522 if (!(t
= match_template ()))
3525 if (sse_check
!= check_none
3526 && !i
.tm
.opcode_modifier
.noavx
3527 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3528 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3529 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3530 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3531 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3532 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3534 (sse_check
== check_warning
3536 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3539 /* Zap movzx and movsx suffix. The suffix has been set from
3540 "word ptr" or "byte ptr" on the source operand in Intel syntax
3541 or extracted from mnemonic in AT&T syntax. But we'll use
3542 the destination register to choose the suffix for encoding. */
3543 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3545 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3546 there is no suffix, the default will be byte extension. */
3547 if (i
.reg_operands
!= 2
3550 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3555 if (i
.tm
.opcode_modifier
.fwait
)
3556 if (!add_prefix (FWAIT_OPCODE
))
3559 /* Check if REP prefix is OK. */
3560 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3562 as_bad (_("invalid instruction `%s' after `%s'"),
3563 i
.tm
.name
, i
.rep_prefix
);
3567 /* Check for lock without a lockable instruction. Destination operand
3568 must be memory unless it is xchg (0x86). */
3569 if (i
.prefix
[LOCK_PREFIX
]
3570 && (!i
.tm
.opcode_modifier
.islockable
3571 || i
.mem_operands
== 0
3572 || (i
.tm
.base_opcode
!= 0x86
3573 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3575 as_bad (_("expecting lockable instruction after `lock'"));
3579 /* Check if HLE prefix is OK. */
3580 if (i
.hle_prefix
&& !check_hle ())
3583 /* Check BND prefix. */
3584 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3585 as_bad (_("expecting valid branch instruction after `bnd'"));
3587 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3588 && flag_code
== CODE_64BIT
3589 && i
.prefix
[ADDR_PREFIX
])
3590 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3592 /* Insert BND prefix. */
3594 && i
.tm
.opcode_modifier
.bndprefixok
3595 && !i
.prefix
[BND_PREFIX
])
3596 add_prefix (BND_PREFIX_OPCODE
);
3598 /* Check string instruction segment overrides. */
3599 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3601 if (!check_string ())
3603 i
.disp_operands
= 0;
3606 if (!process_suffix ())
3609 /* Update operand types. */
3610 for (j
= 0; j
< i
.operands
; j
++)
3611 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3613 /* Make still unresolved immediate matches conform to size of immediate
3614 given in i.suffix. */
3615 if (!finalize_imm ())
3618 if (i
.types
[0].bitfield
.imm1
)
3619 i
.imm_operands
= 0; /* kludge for shift insns. */
3621 /* We only need to check those implicit registers for instructions
3622 with 3 operands or less. */
3623 if (i
.operands
<= 3)
3624 for (j
= 0; j
< i
.operands
; j
++)
3625 if (i
.types
[j
].bitfield
.inoutportreg
3626 || i
.types
[j
].bitfield
.shiftcount
3627 || i
.types
[j
].bitfield
.acc
3628 || i
.types
[j
].bitfield
.floatacc
)
3631 /* ImmExt should be processed after SSE2AVX. */
3632 if (!i
.tm
.opcode_modifier
.sse2avx
3633 && i
.tm
.opcode_modifier
.immext
)
3636 /* For insns with operands there are more diddles to do to the opcode. */
3639 if (!process_operands ())
3642 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3644 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3645 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3648 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3650 if (flag_code
== CODE_16BIT
)
3652 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3657 if (i
.tm
.opcode_modifier
.vex
)
3658 build_vex_prefix (t
);
3660 build_evex_prefix ();
3663 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3664 instructions may define INT_OPCODE as well, so avoid this corner
3665 case for those instructions that use MODRM. */
3666 if (i
.tm
.base_opcode
== INT_OPCODE
3667 && !i
.tm
.opcode_modifier
.modrm
3668 && i
.op
[0].imms
->X_add_number
== 3)
3670 i
.tm
.base_opcode
= INT3_OPCODE
;
3674 if ((i
.tm
.opcode_modifier
.jump
3675 || i
.tm
.opcode_modifier
.jumpbyte
3676 || i
.tm
.opcode_modifier
.jumpdword
)
3677 && i
.op
[0].disps
->X_op
== O_constant
)
3679 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3680 the absolute address given by the constant. Since ix86 jumps and
3681 calls are pc relative, we need to generate a reloc. */
3682 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3683 i
.op
[0].disps
->X_op
= O_symbol
;
3686 if (i
.tm
.opcode_modifier
.rex64
)
3689 /* For 8 bit registers we need an empty rex prefix. Also if the
3690 instruction already has a prefix, we need to convert old
3691 registers to new ones. */
3693 if ((i
.types
[0].bitfield
.reg8
3694 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3695 || (i
.types
[1].bitfield
.reg8
3696 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3697 || ((i
.types
[0].bitfield
.reg8
3698 || i
.types
[1].bitfield
.reg8
)
3703 i
.rex
|= REX_OPCODE
;
3704 for (x
= 0; x
< 2; x
++)
3706 /* Look for 8 bit operand that uses old registers. */
3707 if (i
.types
[x
].bitfield
.reg8
3708 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3710 /* In case it is "hi" register, give up. */
3711 if (i
.op
[x
].regs
->reg_num
> 3)
3712 as_bad (_("can't encode register '%s%s' in an "
3713 "instruction requiring REX prefix."),
3714 register_prefix
, i
.op
[x
].regs
->reg_name
);
3716 /* Otherwise it is equivalent to the extended register.
3717 Since the encoding doesn't change this is merely
3718 cosmetic cleanup for debug output. */
3720 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3726 add_prefix (REX_OPCODE
| i
.rex
);
3728 /* We are ready to output the insn. */
3733 parse_insn (char *line
, char *mnemonic
)
3736 char *token_start
= l
;
3739 const insn_template
*t
;
3745 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3750 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3752 as_bad (_("no such instruction: `%s'"), token_start
);
3757 if (!is_space_char (*l
)
3758 && *l
!= END_OF_INSN
3760 || (*l
!= PREFIX_SEPARATOR
3763 as_bad (_("invalid character %s in mnemonic"),
3764 output_invalid (*l
));
3767 if (token_start
== l
)
3769 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3770 as_bad (_("expecting prefix; got nothing"));
3772 as_bad (_("expecting mnemonic; got nothing"));
3776 /* Look up instruction (or prefix) via hash table. */
3777 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3779 if (*l
!= END_OF_INSN
3780 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3781 && current_templates
3782 && current_templates
->start
->opcode_modifier
.isprefix
)
3784 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3786 as_bad ((flag_code
!= CODE_64BIT
3787 ? _("`%s' is only supported in 64-bit mode")
3788 : _("`%s' is not supported in 64-bit mode")),
3789 current_templates
->start
->name
);
3792 /* If we are in 16-bit mode, do not allow addr16 or data16.
3793 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3794 if ((current_templates
->start
->opcode_modifier
.size16
3795 || current_templates
->start
->opcode_modifier
.size32
)
3796 && flag_code
!= CODE_64BIT
3797 && (current_templates
->start
->opcode_modifier
.size32
3798 ^ (flag_code
== CODE_16BIT
)))
3800 as_bad (_("redundant %s prefix"),
3801 current_templates
->start
->name
);
3804 /* Add prefix, checking for repeated prefixes. */
3805 switch (add_prefix (current_templates
->start
->base_opcode
))
3810 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3811 i
.hle_prefix
= current_templates
->start
->name
;
3812 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3813 i
.bnd_prefix
= current_templates
->start
->name
;
3815 i
.rep_prefix
= current_templates
->start
->name
;
3820 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3827 if (!current_templates
)
3829 /* Check if we should swap operand or force 32bit displacement in
3831 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3833 else if (mnem_p
- 3 == dot_p
3836 i
.disp_encoding
= disp_encoding_8bit
;
3837 else if (mnem_p
- 4 == dot_p
3841 i
.disp_encoding
= disp_encoding_32bit
;
3846 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3849 if (!current_templates
)
3852 /* See if we can get a match by trimming off a suffix. */
3855 case WORD_MNEM_SUFFIX
:
3856 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3857 i
.suffix
= SHORT_MNEM_SUFFIX
;
3859 case BYTE_MNEM_SUFFIX
:
3860 case QWORD_MNEM_SUFFIX
:
3861 i
.suffix
= mnem_p
[-1];
3863 current_templates
= (const templates
*) hash_find (op_hash
,
3866 case SHORT_MNEM_SUFFIX
:
3867 case LONG_MNEM_SUFFIX
:
3870 i
.suffix
= mnem_p
[-1];
3872 current_templates
= (const templates
*) hash_find (op_hash
,
3881 if (intel_float_operand (mnemonic
) == 1)
3882 i
.suffix
= SHORT_MNEM_SUFFIX
;
3884 i
.suffix
= LONG_MNEM_SUFFIX
;
3886 current_templates
= (const templates
*) hash_find (op_hash
,
3891 if (!current_templates
)
3893 as_bad (_("no such instruction: `%s'"), token_start
);
3898 if (current_templates
->start
->opcode_modifier
.jump
3899 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3901 /* Check for a branch hint. We allow ",pt" and ",pn" for
3902 predict taken and predict not taken respectively.
3903 I'm not sure that branch hints actually do anything on loop
3904 and jcxz insns (JumpByte) for current Pentium4 chips. They
3905 may work in the future and it doesn't hurt to accept them
3907 if (l
[0] == ',' && l
[1] == 'p')
3911 if (!add_prefix (DS_PREFIX_OPCODE
))
3915 else if (l
[2] == 'n')
3917 if (!add_prefix (CS_PREFIX_OPCODE
))
3923 /* Any other comma loses. */
3926 as_bad (_("invalid character %s in mnemonic"),
3927 output_invalid (*l
));
3931 /* Check if instruction is supported on specified architecture. */
3933 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3935 supported
|= cpu_flags_match (t
);
3936 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3940 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3942 as_bad (flag_code
== CODE_64BIT
3943 ? _("`%s' is not supported in 64-bit mode")
3944 : _("`%s' is only supported in 64-bit mode"),
3945 current_templates
->start
->name
);
3948 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3950 as_bad (_("`%s' is not supported on `%s%s'"),
3951 current_templates
->start
->name
,
3952 cpu_arch_name
? cpu_arch_name
: default_arch
,
3953 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3958 if (!cpu_arch_flags
.bitfield
.cpui386
3959 && (flag_code
!= CODE_16BIT
))
3961 as_warn (_("use .code16 to ensure correct addressing mode"));
3968 parse_operands (char *l
, const char *mnemonic
)
3972 /* 1 if operand is pending after ','. */
3973 unsigned int expecting_operand
= 0;
3975 /* Non-zero if operand parens not balanced. */
3976 unsigned int paren_not_balanced
;
3978 while (*l
!= END_OF_INSN
)
3980 /* Skip optional white space before operand. */
3981 if (is_space_char (*l
))
3983 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3985 as_bad (_("invalid character %s before operand %d"),
3986 output_invalid (*l
),
3990 token_start
= l
; /* after white space */
3991 paren_not_balanced
= 0;
3992 while (paren_not_balanced
|| *l
!= ',')
3994 if (*l
== END_OF_INSN
)
3996 if (paren_not_balanced
)
3999 as_bad (_("unbalanced parenthesis in operand %d."),
4002 as_bad (_("unbalanced brackets in operand %d."),
4007 break; /* we are done */
4009 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4011 as_bad (_("invalid character %s in operand %d"),
4012 output_invalid (*l
),
4019 ++paren_not_balanced
;
4021 --paren_not_balanced
;
4026 ++paren_not_balanced
;
4028 --paren_not_balanced
;
4032 if (l
!= token_start
)
4033 { /* Yes, we've read in another operand. */
4034 unsigned int operand_ok
;
4035 this_operand
= i
.operands
++;
4036 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4037 if (i
.operands
> MAX_OPERANDS
)
4039 as_bad (_("spurious operands; (%d operands/instruction max)"),
4043 /* Now parse operand adding info to 'i' as we go along. */
4044 END_STRING_AND_SAVE (l
);
4048 i386_intel_operand (token_start
,
4049 intel_float_operand (mnemonic
));
4051 operand_ok
= i386_att_operand (token_start
);
4053 RESTORE_END_STRING (l
);
4059 if (expecting_operand
)
4061 expecting_operand_after_comma
:
4062 as_bad (_("expecting operand after ','; got nothing"));
4067 as_bad (_("expecting operand before ','; got nothing"));
4072 /* Now *l must be either ',' or END_OF_INSN. */
4075 if (*++l
== END_OF_INSN
)
4077 /* Just skip it, if it's \n complain. */
4078 goto expecting_operand_after_comma
;
4080 expecting_operand
= 1;
4087 swap_2_operands (int xchg1
, int xchg2
)
4089 union i386_op temp_op
;
4090 i386_operand_type temp_type
;
4091 enum bfd_reloc_code_real temp_reloc
;
4093 temp_type
= i
.types
[xchg2
];
4094 i
.types
[xchg2
] = i
.types
[xchg1
];
4095 i
.types
[xchg1
] = temp_type
;
4096 temp_op
= i
.op
[xchg2
];
4097 i
.op
[xchg2
] = i
.op
[xchg1
];
4098 i
.op
[xchg1
] = temp_op
;
4099 temp_reloc
= i
.reloc
[xchg2
];
4100 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4101 i
.reloc
[xchg1
] = temp_reloc
;
4105 if (i
.mask
->operand
== xchg1
)
4106 i
.mask
->operand
= xchg2
;
4107 else if (i
.mask
->operand
== xchg2
)
4108 i
.mask
->operand
= xchg1
;
4112 if (i
.broadcast
->operand
== xchg1
)
4113 i
.broadcast
->operand
= xchg2
;
4114 else if (i
.broadcast
->operand
== xchg2
)
4115 i
.broadcast
->operand
= xchg1
;
4119 if (i
.rounding
->operand
== xchg1
)
4120 i
.rounding
->operand
= xchg2
;
4121 else if (i
.rounding
->operand
== xchg2
)
4122 i
.rounding
->operand
= xchg1
;
4127 swap_operands (void)
4133 swap_2_operands (1, i
.operands
- 2);
4136 swap_2_operands (0, i
.operands
- 1);
4142 if (i
.mem_operands
== 2)
4144 const seg_entry
*temp_seg
;
4145 temp_seg
= i
.seg
[0];
4146 i
.seg
[0] = i
.seg
[1];
4147 i
.seg
[1] = temp_seg
;
4151 /* Try to ensure constant immediates are represented in the smallest
4156 char guess_suffix
= 0;
4160 guess_suffix
= i
.suffix
;
4161 else if (i
.reg_operands
)
4163 /* Figure out a suffix from the last register operand specified.
4164 We can't do this properly yet, ie. excluding InOutPortReg,
4165 but the following works for instructions with immediates.
4166 In any case, we can't set i.suffix yet. */
4167 for (op
= i
.operands
; --op
>= 0;)
4168 if (i
.types
[op
].bitfield
.reg8
)
4170 guess_suffix
= BYTE_MNEM_SUFFIX
;
4173 else if (i
.types
[op
].bitfield
.reg16
)
4175 guess_suffix
= WORD_MNEM_SUFFIX
;
4178 else if (i
.types
[op
].bitfield
.reg32
)
4180 guess_suffix
= LONG_MNEM_SUFFIX
;
4183 else if (i
.types
[op
].bitfield
.reg64
)
4185 guess_suffix
= QWORD_MNEM_SUFFIX
;
4189 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4190 guess_suffix
= WORD_MNEM_SUFFIX
;
4192 for (op
= i
.operands
; --op
>= 0;)
4193 if (operand_type_check (i
.types
[op
], imm
))
4195 switch (i
.op
[op
].imms
->X_op
)
4198 /* If a suffix is given, this operand may be shortened. */
4199 switch (guess_suffix
)
4201 case LONG_MNEM_SUFFIX
:
4202 i
.types
[op
].bitfield
.imm32
= 1;
4203 i
.types
[op
].bitfield
.imm64
= 1;
4205 case WORD_MNEM_SUFFIX
:
4206 i
.types
[op
].bitfield
.imm16
= 1;
4207 i
.types
[op
].bitfield
.imm32
= 1;
4208 i
.types
[op
].bitfield
.imm32s
= 1;
4209 i
.types
[op
].bitfield
.imm64
= 1;
4211 case BYTE_MNEM_SUFFIX
:
4212 i
.types
[op
].bitfield
.imm8
= 1;
4213 i
.types
[op
].bitfield
.imm8s
= 1;
4214 i
.types
[op
].bitfield
.imm16
= 1;
4215 i
.types
[op
].bitfield
.imm32
= 1;
4216 i
.types
[op
].bitfield
.imm32s
= 1;
4217 i
.types
[op
].bitfield
.imm64
= 1;
4221 /* If this operand is at most 16 bits, convert it
4222 to a signed 16 bit number before trying to see
4223 whether it will fit in an even smaller size.
4224 This allows a 16-bit operand such as $0xffe0 to
4225 be recognised as within Imm8S range. */
4226 if ((i
.types
[op
].bitfield
.imm16
)
4227 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4229 i
.op
[op
].imms
->X_add_number
=
4230 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4232 if ((i
.types
[op
].bitfield
.imm32
)
4233 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4236 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4237 ^ ((offsetT
) 1 << 31))
4238 - ((offsetT
) 1 << 31));
4241 = operand_type_or (i
.types
[op
],
4242 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4244 /* We must avoid matching of Imm32 templates when 64bit
4245 only immediate is available. */
4246 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4247 i
.types
[op
].bitfield
.imm32
= 0;
4254 /* Symbols and expressions. */
4256 /* Convert symbolic operand to proper sizes for matching, but don't
4257 prevent matching a set of insns that only supports sizes other
4258 than those matching the insn suffix. */
4260 i386_operand_type mask
, allowed
;
4261 const insn_template
*t
;
4263 operand_type_set (&mask
, 0);
4264 operand_type_set (&allowed
, 0);
4266 for (t
= current_templates
->start
;
4267 t
< current_templates
->end
;
4269 allowed
= operand_type_or (allowed
,
4270 t
->operand_types
[op
]);
4271 switch (guess_suffix
)
4273 case QWORD_MNEM_SUFFIX
:
4274 mask
.bitfield
.imm64
= 1;
4275 mask
.bitfield
.imm32s
= 1;
4277 case LONG_MNEM_SUFFIX
:
4278 mask
.bitfield
.imm32
= 1;
4280 case WORD_MNEM_SUFFIX
:
4281 mask
.bitfield
.imm16
= 1;
4283 case BYTE_MNEM_SUFFIX
:
4284 mask
.bitfield
.imm8
= 1;
4289 allowed
= operand_type_and (mask
, allowed
);
4290 if (!operand_type_all_zero (&allowed
))
4291 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4298 /* Try to use the smallest displacement type too. */
4300 optimize_disp (void)
4304 for (op
= i
.operands
; --op
>= 0;)
4305 if (operand_type_check (i
.types
[op
], disp
))
4307 if (i
.op
[op
].disps
->X_op
== O_constant
)
4309 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4311 if (i
.types
[op
].bitfield
.disp16
4312 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4314 /* If this operand is at most 16 bits, convert
4315 to a signed 16 bit number and don't use 64bit
4317 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4318 i
.types
[op
].bitfield
.disp64
= 0;
4320 if (i
.types
[op
].bitfield
.disp32
4321 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4323 /* If this operand is at most 32 bits, convert
4324 to a signed 32 bit number and don't use 64bit
4326 op_disp
&= (((offsetT
) 2 << 31) - 1);
4327 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4328 i
.types
[op
].bitfield
.disp64
= 0;
4330 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4332 i
.types
[op
].bitfield
.disp8
= 0;
4333 i
.types
[op
].bitfield
.disp16
= 0;
4334 i
.types
[op
].bitfield
.disp32
= 0;
4335 i
.types
[op
].bitfield
.disp32s
= 0;
4336 i
.types
[op
].bitfield
.disp64
= 0;
4340 else if (flag_code
== CODE_64BIT
)
4342 if (fits_in_signed_long (op_disp
))
4344 i
.types
[op
].bitfield
.disp64
= 0;
4345 i
.types
[op
].bitfield
.disp32s
= 1;
4347 if (i
.prefix
[ADDR_PREFIX
]
4348 && fits_in_unsigned_long (op_disp
))
4349 i
.types
[op
].bitfield
.disp32
= 1;
4351 if ((i
.types
[op
].bitfield
.disp32
4352 || i
.types
[op
].bitfield
.disp32s
4353 || i
.types
[op
].bitfield
.disp16
)
4354 && fits_in_signed_byte (op_disp
))
4355 i
.types
[op
].bitfield
.disp8
= 1;
4357 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4358 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4360 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4361 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4362 i
.types
[op
].bitfield
.disp8
= 0;
4363 i
.types
[op
].bitfield
.disp16
= 0;
4364 i
.types
[op
].bitfield
.disp32
= 0;
4365 i
.types
[op
].bitfield
.disp32s
= 0;
4366 i
.types
[op
].bitfield
.disp64
= 0;
4369 /* We only support 64bit displacement on constants. */
4370 i
.types
[op
].bitfield
.disp64
= 0;
4374 /* Check if operands are valid for the instruction. */
4377 check_VecOperands (const insn_template
*t
)
4381 /* Without VSIB byte, we can't have a vector register for index. */
4382 if (!t
->opcode_modifier
.vecsib
4384 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4385 || i
.index_reg
->reg_type
.bitfield
.regymm
4386 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4388 i
.error
= unsupported_vector_index_register
;
4392 /* Check if default mask is allowed. */
4393 if (t
->opcode_modifier
.nodefmask
4394 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4396 i
.error
= no_default_mask
;
4400 /* For VSIB byte, we need a vector register for index, and all vector
4401 registers must be distinct. */
4402 if (t
->opcode_modifier
.vecsib
)
4405 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4406 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4407 || (t
->opcode_modifier
.vecsib
== VecSIB256
4408 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4409 || (t
->opcode_modifier
.vecsib
== VecSIB512
4410 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4412 i
.error
= invalid_vsib_address
;
4416 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4417 if (i
.reg_operands
== 2 && !i
.mask
)
4419 gas_assert (i
.types
[0].bitfield
.regxmm
4420 || i
.types
[0].bitfield
.regymm
);
4421 gas_assert (i
.types
[2].bitfield
.regxmm
4422 || i
.types
[2].bitfield
.regymm
);
4423 if (operand_check
== check_none
)
4425 if (register_number (i
.op
[0].regs
)
4426 != register_number (i
.index_reg
)
4427 && register_number (i
.op
[2].regs
)
4428 != register_number (i
.index_reg
)
4429 && register_number (i
.op
[0].regs
)
4430 != register_number (i
.op
[2].regs
))
4432 if (operand_check
== check_error
)
4434 i
.error
= invalid_vector_register_set
;
4437 as_warn (_("mask, index, and destination registers should be distinct"));
4439 else if (i
.reg_operands
== 1 && i
.mask
)
4441 if ((i
.types
[1].bitfield
.regymm
4442 || i
.types
[1].bitfield
.regzmm
)
4443 && (register_number (i
.op
[1].regs
)
4444 == register_number (i
.index_reg
)))
4446 if (operand_check
== check_error
)
4448 i
.error
= invalid_vector_register_set
;
4451 if (operand_check
!= check_none
)
4452 as_warn (_("index and destination registers should be distinct"));
4457 /* Check if broadcast is supported by the instruction and is applied
4458 to the memory operand. */
4461 int broadcasted_opnd_size
;
4463 /* Check if specified broadcast is supported in this instruction,
4464 and it's applied to memory operand of DWORD or QWORD type,
4465 depending on VecESize. */
4466 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4467 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4468 || (t
->opcode_modifier
.vecesize
== 0
4469 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4470 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4471 || (t
->opcode_modifier
.vecesize
== 1
4472 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4473 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4476 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4477 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4478 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4479 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4480 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4481 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4482 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4483 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4484 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4488 if ((broadcasted_opnd_size
== 256
4489 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4490 || (broadcasted_opnd_size
== 512
4491 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4494 i
.error
= unsupported_broadcast
;
4498 /* If broadcast is supported in this instruction, we need to check if
4499 operand of one-element size isn't specified without broadcast. */
4500 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4502 /* Find memory operand. */
4503 for (op
= 0; op
< i
.operands
; op
++)
4504 if (operand_type_check (i
.types
[op
], anymem
))
4506 gas_assert (op
< i
.operands
);
4507 /* Check size of the memory operand. */
4508 if ((t
->opcode_modifier
.vecesize
== 0
4509 && i
.types
[op
].bitfield
.dword
)
4510 || (t
->opcode_modifier
.vecesize
== 1
4511 && i
.types
[op
].bitfield
.qword
))
4513 i
.error
= broadcast_needed
;
4518 /* Check if requested masking is supported. */
4520 && (!t
->opcode_modifier
.masking
4522 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4524 i
.error
= unsupported_masking
;
4528 /* Check if masking is applied to dest operand. */
4529 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4531 i
.error
= mask_not_on_destination
;
4538 if ((i
.rounding
->type
!= saeonly
4539 && !t
->opcode_modifier
.staticrounding
)
4540 || (i
.rounding
->type
== saeonly
4541 && (t
->opcode_modifier
.staticrounding
4542 || !t
->opcode_modifier
.sae
)))
4544 i
.error
= unsupported_rc_sae
;
4547 /* If the instruction has several immediate operands and one of
4548 them is rounding, the rounding operand should be the last
4549 immediate operand. */
4550 if (i
.imm_operands
> 1
4551 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4553 i
.error
= rc_sae_operand_not_last_imm
;
4558 /* Check vector Disp8 operand. */
4559 if (t
->opcode_modifier
.disp8memshift
)
4562 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4564 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4566 for (op
= 0; op
< i
.operands
; op
++)
4567 if (operand_type_check (i
.types
[op
], disp
)
4568 && i
.op
[op
].disps
->X_op
== O_constant
)
4570 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4571 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4572 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4575 i
.types
[op
].bitfield
.vec_disp8
= 1;
4578 /* Vector insn can only have Vec_Disp8/Disp32 in
4579 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4581 i
.types
[op
].bitfield
.disp8
= 0;
4582 if (flag_code
!= CODE_16BIT
)
4583 i
.types
[op
].bitfield
.disp16
= 0;
4586 else if (flag_code
!= CODE_16BIT
)
4588 /* One form of this instruction supports vector Disp8.
4589 Try vector Disp8 if we need to use Disp32. */
4590 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4592 i
.error
= try_vector_disp8
;
4604 /* Check if operands are valid for the instruction. Update VEX
4608 VEX_check_operands (const insn_template
*t
)
4610 /* VREX is only valid with EVEX prefix. */
4611 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4613 i
.error
= invalid_register_operand
;
4617 if (!t
->opcode_modifier
.vex
)
4620 /* Only check VEX_Imm4, which must be the first operand. */
4621 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4623 if (i
.op
[0].imms
->X_op
!= O_constant
4624 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4630 /* Turn off Imm8 so that update_imm won't complain. */
4631 i
.types
[0] = vec_imm4
;
4637 static const insn_template
*
4638 match_template (void)
4640 /* Points to template once we've found it. */
4641 const insn_template
*t
;
4642 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4643 i386_operand_type overlap4
;
4644 unsigned int found_reverse_match
;
4645 i386_opcode_modifier suffix_check
;
4646 i386_operand_type operand_types
[MAX_OPERANDS
];
4647 int addr_prefix_disp
;
4649 unsigned int found_cpu_match
;
4650 unsigned int check_register
;
4651 enum i386_error specific_error
= 0;
4653 #if MAX_OPERANDS != 5
4654 # error "MAX_OPERANDS must be 5."
4657 found_reverse_match
= 0;
4658 addr_prefix_disp
= -1;
4660 memset (&suffix_check
, 0, sizeof (suffix_check
));
4661 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4662 suffix_check
.no_bsuf
= 1;
4663 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4664 suffix_check
.no_wsuf
= 1;
4665 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4666 suffix_check
.no_ssuf
= 1;
4667 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4668 suffix_check
.no_lsuf
= 1;
4669 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4670 suffix_check
.no_qsuf
= 1;
4671 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4672 suffix_check
.no_ldsuf
= 1;
4674 /* Must have right number of operands. */
4675 i
.error
= number_of_operands_mismatch
;
4677 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4679 addr_prefix_disp
= -1;
4681 if (i
.operands
!= t
->operands
)
4684 /* Check processor support. */
4685 i
.error
= unsupported
;
4686 found_cpu_match
= (cpu_flags_match (t
)
4687 == CPU_FLAGS_PERFECT_MATCH
);
4688 if (!found_cpu_match
)
4691 /* Check old gcc support. */
4692 i
.error
= old_gcc_only
;
4693 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4696 /* Check AT&T mnemonic. */
4697 i
.error
= unsupported_with_intel_mnemonic
;
4698 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4701 /* Check AT&T/Intel syntax. */
4702 i
.error
= unsupported_syntax
;
4703 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4704 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4707 /* Check the suffix, except for some instructions in intel mode. */
4708 i
.error
= invalid_instruction_suffix
;
4709 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4710 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4711 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4712 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4713 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4714 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4715 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4718 if (!operand_size_match (t
))
4721 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4722 operand_types
[j
] = t
->operand_types
[j
];
4724 /* In general, don't allow 64-bit operands in 32-bit mode. */
4725 if (i
.suffix
== QWORD_MNEM_SUFFIX
4726 && flag_code
!= CODE_64BIT
4728 ? (!t
->opcode_modifier
.ignoresize
4729 && !intel_float_operand (t
->name
))
4730 : intel_float_operand (t
->name
) != 2)
4731 && ((!operand_types
[0].bitfield
.regmmx
4732 && !operand_types
[0].bitfield
.regxmm
4733 && !operand_types
[0].bitfield
.regymm
4734 && !operand_types
[0].bitfield
.regzmm
)
4735 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4736 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4737 && operand_types
[t
->operands
> 1].bitfield
.regymm
4738 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4739 && (t
->base_opcode
!= 0x0fc7
4740 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4743 /* In general, don't allow 32-bit operands on pre-386. */
4744 else if (i
.suffix
== LONG_MNEM_SUFFIX
4745 && !cpu_arch_flags
.bitfield
.cpui386
4747 ? (!t
->opcode_modifier
.ignoresize
4748 && !intel_float_operand (t
->name
))
4749 : intel_float_operand (t
->name
) != 2)
4750 && ((!operand_types
[0].bitfield
.regmmx
4751 && !operand_types
[0].bitfield
.regxmm
)
4752 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4753 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4756 /* Do not verify operands when there are none. */
4760 /* We've found a match; break out of loop. */
4764 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4765 into Disp32/Disp16/Disp32 operand. */
4766 if (i
.prefix
[ADDR_PREFIX
] != 0)
4768 /* There should be only one Disp operand. */
4772 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4774 if (operand_types
[j
].bitfield
.disp16
)
4776 addr_prefix_disp
= j
;
4777 operand_types
[j
].bitfield
.disp32
= 1;
4778 operand_types
[j
].bitfield
.disp16
= 0;
4784 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4786 if (operand_types
[j
].bitfield
.disp32
)
4788 addr_prefix_disp
= j
;
4789 operand_types
[j
].bitfield
.disp32
= 0;
4790 operand_types
[j
].bitfield
.disp16
= 1;
4796 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4798 if (operand_types
[j
].bitfield
.disp64
)
4800 addr_prefix_disp
= j
;
4801 operand_types
[j
].bitfield
.disp64
= 0;
4802 operand_types
[j
].bitfield
.disp32
= 1;
4810 /* We check register size if needed. */
4811 check_register
= t
->opcode_modifier
.checkregsize
;
4812 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4813 switch (t
->operands
)
4816 if (!operand_type_match (overlap0
, i
.types
[0]))
4820 /* xchg %eax, %eax is a special case. It is an aliase for nop
4821 only in 32bit mode and we can use opcode 0x90. In 64bit
4822 mode, we can't use 0x90 for xchg %eax, %eax since it should
4823 zero-extend %eax to %rax. */
4824 if (flag_code
== CODE_64BIT
4825 && t
->base_opcode
== 0x90
4826 && operand_type_equal (&i
.types
[0], &acc32
)
4827 && operand_type_equal (&i
.types
[1], &acc32
))
4831 /* If we swap operand in encoding, we either match
4832 the next one or reverse direction of operands. */
4833 if (t
->opcode_modifier
.s
)
4835 else if (t
->opcode_modifier
.d
)
4840 /* If we swap operand in encoding, we match the next one. */
4841 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4845 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4846 if (!operand_type_match (overlap0
, i
.types
[0])
4847 || !operand_type_match (overlap1
, i
.types
[1])
4849 && !operand_type_register_match (overlap0
, i
.types
[0],
4851 overlap1
, i
.types
[1],
4854 /* Check if other direction is valid ... */
4855 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4859 /* Try reversing direction of operands. */
4860 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4861 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4862 if (!operand_type_match (overlap0
, i
.types
[0])
4863 || !operand_type_match (overlap1
, i
.types
[1])
4865 && !operand_type_register_match (overlap0
,
4872 /* Does not match either direction. */
4875 /* found_reverse_match holds which of D or FloatDR
4877 if (t
->opcode_modifier
.d
)
4878 found_reverse_match
= Opcode_D
;
4879 else if (t
->opcode_modifier
.floatd
)
4880 found_reverse_match
= Opcode_FloatD
;
4882 found_reverse_match
= 0;
4883 if (t
->opcode_modifier
.floatr
)
4884 found_reverse_match
|= Opcode_FloatR
;
4888 /* Found a forward 2 operand match here. */
4889 switch (t
->operands
)
4892 overlap4
= operand_type_and (i
.types
[4],
4895 overlap3
= operand_type_and (i
.types
[3],
4898 overlap2
= operand_type_and (i
.types
[2],
4903 switch (t
->operands
)
4906 if (!operand_type_match (overlap4
, i
.types
[4])
4907 || !operand_type_register_match (overlap3
,
4915 if (!operand_type_match (overlap3
, i
.types
[3])
4917 && !operand_type_register_match (overlap2
,
4925 /* Here we make use of the fact that there are no
4926 reverse match 3 operand instructions, and all 3
4927 operand instructions only need to be checked for
4928 register consistency between operands 2 and 3. */
4929 if (!operand_type_match (overlap2
, i
.types
[2])
4931 && !operand_type_register_match (overlap1
,
4941 /* Found either forward/reverse 2, 3 or 4 operand match here:
4942 slip through to break. */
4944 if (!found_cpu_match
)
4946 found_reverse_match
= 0;
4950 /* Check if vector and VEX operands are valid. */
4951 if (check_VecOperands (t
) || VEX_check_operands (t
))
4953 specific_error
= i
.error
;
4957 /* We've found a match; break out of loop. */
4961 if (t
== current_templates
->end
)
4963 /* We found no match. */
4964 const char *err_msg
;
4965 switch (specific_error
? specific_error
: i
.error
)
4969 case operand_size_mismatch
:
4970 err_msg
= _("operand size mismatch");
4972 case operand_type_mismatch
:
4973 err_msg
= _("operand type mismatch");
4975 case register_type_mismatch
:
4976 err_msg
= _("register type mismatch");
4978 case number_of_operands_mismatch
:
4979 err_msg
= _("number of operands mismatch");
4981 case invalid_instruction_suffix
:
4982 err_msg
= _("invalid instruction suffix");
4985 err_msg
= _("constant doesn't fit in 4 bits");
4988 err_msg
= _("only supported with old gcc");
4990 case unsupported_with_intel_mnemonic
:
4991 err_msg
= _("unsupported with Intel mnemonic");
4993 case unsupported_syntax
:
4994 err_msg
= _("unsupported syntax");
4997 as_bad (_("unsupported instruction `%s'"),
4998 current_templates
->start
->name
);
5000 case invalid_vsib_address
:
5001 err_msg
= _("invalid VSIB address");
5003 case invalid_vector_register_set
:
5004 err_msg
= _("mask, index, and destination registers must be distinct");
5006 case unsupported_vector_index_register
:
5007 err_msg
= _("unsupported vector index register");
5009 case unsupported_broadcast
:
5010 err_msg
= _("unsupported broadcast");
5012 case broadcast_not_on_src_operand
:
5013 err_msg
= _("broadcast not on source memory operand");
5015 case broadcast_needed
:
5016 err_msg
= _("broadcast is needed for operand of such type");
5018 case unsupported_masking
:
5019 err_msg
= _("unsupported masking");
5021 case mask_not_on_destination
:
5022 err_msg
= _("mask not on destination operand");
5024 case no_default_mask
:
5025 err_msg
= _("default mask isn't allowed");
5027 case unsupported_rc_sae
:
5028 err_msg
= _("unsupported static rounding/sae");
5030 case rc_sae_operand_not_last_imm
:
5032 err_msg
= _("RC/SAE operand must precede immediate operands");
5034 err_msg
= _("RC/SAE operand must follow immediate operands");
5036 case invalid_register_operand
:
5037 err_msg
= _("invalid register operand");
5040 as_bad (_("%s for `%s'"), err_msg
,
5041 current_templates
->start
->name
);
5045 if (!quiet_warnings
)
5048 && (i
.types
[0].bitfield
.jumpabsolute
5049 != operand_types
[0].bitfield
.jumpabsolute
))
5051 as_warn (_("indirect %s without `*'"), t
->name
);
5054 if (t
->opcode_modifier
.isprefix
5055 && t
->opcode_modifier
.ignoresize
)
5057 /* Warn them that a data or address size prefix doesn't
5058 affect assembly of the next line of code. */
5059 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5063 /* Copy the template we found. */
5066 if (addr_prefix_disp
!= -1)
5067 i
.tm
.operand_types
[addr_prefix_disp
]
5068 = operand_types
[addr_prefix_disp
];
5070 if (found_reverse_match
)
5072 /* If we found a reverse match we must alter the opcode
5073 direction bit. found_reverse_match holds bits to change
5074 (different for int & float insns). */
5076 i
.tm
.base_opcode
^= found_reverse_match
;
5078 i
.tm
.operand_types
[0] = operand_types
[1];
5079 i
.tm
.operand_types
[1] = operand_types
[0];
5088 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5089 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5091 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5093 as_bad (_("`%s' operand %d must use `%ses' segment"),
5099 /* There's only ever one segment override allowed per instruction.
5100 This instruction possibly has a legal segment override on the
5101 second operand, so copy the segment to where non-string
5102 instructions store it, allowing common code. */
5103 i
.seg
[0] = i
.seg
[1];
5105 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5107 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5109 as_bad (_("`%s' operand %d must use `%ses' segment"),
5120 process_suffix (void)
5122 /* If matched instruction specifies an explicit instruction mnemonic
5124 if (i
.tm
.opcode_modifier
.size16
)
5125 i
.suffix
= WORD_MNEM_SUFFIX
;
5126 else if (i
.tm
.opcode_modifier
.size32
)
5127 i
.suffix
= LONG_MNEM_SUFFIX
;
5128 else if (i
.tm
.opcode_modifier
.size64
)
5129 i
.suffix
= QWORD_MNEM_SUFFIX
;
5130 else if (i
.reg_operands
)
5132 /* If there's no instruction mnemonic suffix we try to invent one
5133 based on register operands. */
5136 /* We take i.suffix from the last register operand specified,
5137 Destination register type is more significant than source
5138 register type. crc32 in SSE4.2 prefers source register
5140 if (i
.tm
.base_opcode
== 0xf20f38f1)
5142 if (i
.types
[0].bitfield
.reg16
)
5143 i
.suffix
= WORD_MNEM_SUFFIX
;
5144 else if (i
.types
[0].bitfield
.reg32
)
5145 i
.suffix
= LONG_MNEM_SUFFIX
;
5146 else if (i
.types
[0].bitfield
.reg64
)
5147 i
.suffix
= QWORD_MNEM_SUFFIX
;
5149 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5151 if (i
.types
[0].bitfield
.reg8
)
5152 i
.suffix
= BYTE_MNEM_SUFFIX
;
5159 if (i
.tm
.base_opcode
== 0xf20f38f1
5160 || i
.tm
.base_opcode
== 0xf20f38f0)
5162 /* We have to know the operand size for crc32. */
5163 as_bad (_("ambiguous memory operand size for `%s`"),
5168 for (op
= i
.operands
; --op
>= 0;)
5169 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5171 if (i
.types
[op
].bitfield
.reg8
)
5173 i
.suffix
= BYTE_MNEM_SUFFIX
;
5176 else if (i
.types
[op
].bitfield
.reg16
)
5178 i
.suffix
= WORD_MNEM_SUFFIX
;
5181 else if (i
.types
[op
].bitfield
.reg32
)
5183 i
.suffix
= LONG_MNEM_SUFFIX
;
5186 else if (i
.types
[op
].bitfield
.reg64
)
5188 i
.suffix
= QWORD_MNEM_SUFFIX
;
5194 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5197 && i
.tm
.opcode_modifier
.ignoresize
5198 && i
.tm
.opcode_modifier
.no_bsuf
)
5200 else if (!check_byte_reg ())
5203 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5206 && i
.tm
.opcode_modifier
.ignoresize
5207 && i
.tm
.opcode_modifier
.no_lsuf
)
5209 else if (!check_long_reg ())
5212 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5215 && i
.tm
.opcode_modifier
.ignoresize
5216 && i
.tm
.opcode_modifier
.no_qsuf
)
5218 else if (!check_qword_reg ())
5221 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5224 && i
.tm
.opcode_modifier
.ignoresize
5225 && i
.tm
.opcode_modifier
.no_wsuf
)
5227 else if (!check_word_reg ())
5230 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5231 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5232 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5234 /* Skip if the instruction has x/y/z suffix. match_template
5235 should check if it is a valid suffix. */
5237 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5238 /* Do nothing if the instruction is going to ignore the prefix. */
5243 else if (i
.tm
.opcode_modifier
.defaultsize
5245 /* exclude fldenv/frstor/fsave/fstenv */
5246 && i
.tm
.opcode_modifier
.no_ssuf
)
5248 i
.suffix
= stackop_size
;
5250 else if (intel_syntax
5252 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5253 || i
.tm
.opcode_modifier
.jumpbyte
5254 || i
.tm
.opcode_modifier
.jumpintersegment
5255 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5256 && i
.tm
.extension_opcode
<= 3)))
5261 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5263 i
.suffix
= QWORD_MNEM_SUFFIX
;
5267 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5268 i
.suffix
= LONG_MNEM_SUFFIX
;
5271 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5272 i
.suffix
= WORD_MNEM_SUFFIX
;
5281 if (i
.tm
.opcode_modifier
.w
)
5283 as_bad (_("no instruction mnemonic suffix given and "
5284 "no register operands; can't size instruction"));
5290 unsigned int suffixes
;
5292 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5293 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5295 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5297 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5299 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5301 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5304 /* There are more than suffix matches. */
5305 if (i
.tm
.opcode_modifier
.w
5306 || ((suffixes
& (suffixes
- 1))
5307 && !i
.tm
.opcode_modifier
.defaultsize
5308 && !i
.tm
.opcode_modifier
.ignoresize
))
5310 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5316 /* Change the opcode based on the operand size given by i.suffix;
5317 We don't need to change things for byte insns. */
5320 && i
.suffix
!= BYTE_MNEM_SUFFIX
5321 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5322 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5323 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5325 /* It's not a byte, select word/dword operation. */
5326 if (i
.tm
.opcode_modifier
.w
)
5328 if (i
.tm
.opcode_modifier
.shortform
)
5329 i
.tm
.base_opcode
|= 8;
5331 i
.tm
.base_opcode
|= 1;
5334 /* Now select between word & dword operations via the operand
5335 size prefix, except for instructions that will ignore this
5337 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5339 /* The address size override prefix changes the size of the
5341 if ((flag_code
== CODE_32BIT
5342 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5343 || (flag_code
!= CODE_32BIT
5344 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5345 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5348 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5349 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5350 && !i
.tm
.opcode_modifier
.ignoresize
5351 && !i
.tm
.opcode_modifier
.floatmf
5352 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5353 || (flag_code
== CODE_64BIT
5354 && i
.tm
.opcode_modifier
.jumpbyte
)))
5356 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5358 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5359 prefix
= ADDR_PREFIX_OPCODE
;
5361 if (!add_prefix (prefix
))
5365 /* Set mode64 for an operand. */
5366 if (i
.suffix
== QWORD_MNEM_SUFFIX
5367 && flag_code
== CODE_64BIT
5368 && !i
.tm
.opcode_modifier
.norex64
)
5370 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5371 need rex64. cmpxchg8b is also a special case. */
5372 if (! (i
.operands
== 2
5373 && i
.tm
.base_opcode
== 0x90
5374 && i
.tm
.extension_opcode
== None
5375 && operand_type_equal (&i
.types
[0], &acc64
)
5376 && operand_type_equal (&i
.types
[1], &acc64
))
5377 && ! (i
.operands
== 1
5378 && i
.tm
.base_opcode
== 0xfc7
5379 && i
.tm
.extension_opcode
== 1
5380 && !operand_type_check (i
.types
[0], reg
)
5381 && operand_type_check (i
.types
[0], anymem
)))
5385 /* Size floating point instruction. */
5386 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5387 if (i
.tm
.opcode_modifier
.floatmf
)
5388 i
.tm
.base_opcode
^= 4;
5395 check_byte_reg (void)
5399 for (op
= i
.operands
; --op
>= 0;)
5401 /* If this is an eight bit register, it's OK. If it's the 16 or
5402 32 bit version of an eight bit register, we will just use the
5403 low portion, and that's OK too. */
5404 if (i
.types
[op
].bitfield
.reg8
)
5407 /* I/O port address operands are OK too. */
5408 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5411 /* crc32 doesn't generate this warning. */
5412 if (i
.tm
.base_opcode
== 0xf20f38f0)
5415 if ((i
.types
[op
].bitfield
.reg16
5416 || i
.types
[op
].bitfield
.reg32
5417 || i
.types
[op
].bitfield
.reg64
)
5418 && i
.op
[op
].regs
->reg_num
< 4
5419 /* Prohibit these changes in 64bit mode, since the lowering
5420 would be more complicated. */
5421 && flag_code
!= CODE_64BIT
)
5423 #if REGISTER_WARNINGS
5424 if (!quiet_warnings
)
5425 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5427 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5428 ? REGNAM_AL
- REGNAM_AX
5429 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5431 i
.op
[op
].regs
->reg_name
,
5436 /* Any other register is bad. */
5437 if (i
.types
[op
].bitfield
.reg16
5438 || i
.types
[op
].bitfield
.reg32
5439 || i
.types
[op
].bitfield
.reg64
5440 || i
.types
[op
].bitfield
.regmmx
5441 || i
.types
[op
].bitfield
.regxmm
5442 || i
.types
[op
].bitfield
.regymm
5443 || i
.types
[op
].bitfield
.regzmm
5444 || i
.types
[op
].bitfield
.sreg2
5445 || i
.types
[op
].bitfield
.sreg3
5446 || i
.types
[op
].bitfield
.control
5447 || i
.types
[op
].bitfield
.debug
5448 || i
.types
[op
].bitfield
.test
5449 || i
.types
[op
].bitfield
.floatreg
5450 || i
.types
[op
].bitfield
.floatacc
)
5452 as_bad (_("`%s%s' not allowed with `%s%c'"),
5454 i
.op
[op
].regs
->reg_name
,
5464 check_long_reg (void)
5468 for (op
= i
.operands
; --op
>= 0;)
5469 /* Reject eight bit registers, except where the template requires
5470 them. (eg. movzb) */
5471 if (i
.types
[op
].bitfield
.reg8
5472 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5473 || i
.tm
.operand_types
[op
].bitfield
.reg32
5474 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5476 as_bad (_("`%s%s' not allowed with `%s%c'"),
5478 i
.op
[op
].regs
->reg_name
,
5483 /* Warn if the e prefix on a general reg is missing. */
5484 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5485 && i
.types
[op
].bitfield
.reg16
5486 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5487 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5489 /* Prohibit these changes in the 64bit mode, since the
5490 lowering is more complicated. */
5491 if (flag_code
== CODE_64BIT
)
5493 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5494 register_prefix
, i
.op
[op
].regs
->reg_name
,
5498 #if REGISTER_WARNINGS
5499 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5501 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5502 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5505 /* Warn if the r prefix on a general reg is present. */
5506 else if (i
.types
[op
].bitfield
.reg64
5507 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5508 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5511 && i
.tm
.opcode_modifier
.toqword
5512 && !i
.types
[0].bitfield
.regxmm
)
5514 /* Convert to QWORD. We want REX byte. */
5515 i
.suffix
= QWORD_MNEM_SUFFIX
;
5519 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5520 register_prefix
, i
.op
[op
].regs
->reg_name
,
5529 check_qword_reg (void)
5533 for (op
= i
.operands
; --op
>= 0; )
5534 /* Reject eight bit registers, except where the template requires
5535 them. (eg. movzb) */
5536 if (i
.types
[op
].bitfield
.reg8
5537 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5538 || i
.tm
.operand_types
[op
].bitfield
.reg32
5539 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5541 as_bad (_("`%s%s' not allowed with `%s%c'"),
5543 i
.op
[op
].regs
->reg_name
,
5548 /* Warn if the r prefix on a general reg is missing. */
5549 else if ((i
.types
[op
].bitfield
.reg16
5550 || i
.types
[op
].bitfield
.reg32
)
5551 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5552 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5554 /* Prohibit these changes in the 64bit mode, since the
5555 lowering is more complicated. */
5557 && i
.tm
.opcode_modifier
.todword
5558 && !i
.types
[0].bitfield
.regxmm
)
5560 /* Convert to DWORD. We don't want REX byte. */
5561 i
.suffix
= LONG_MNEM_SUFFIX
;
5565 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5566 register_prefix
, i
.op
[op
].regs
->reg_name
,
5575 check_word_reg (void)
5578 for (op
= i
.operands
; --op
>= 0;)
5579 /* Reject eight bit registers, except where the template requires
5580 them. (eg. movzb) */
5581 if (i
.types
[op
].bitfield
.reg8
5582 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5583 || i
.tm
.operand_types
[op
].bitfield
.reg32
5584 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5586 as_bad (_("`%s%s' not allowed with `%s%c'"),
5588 i
.op
[op
].regs
->reg_name
,
5593 /* Warn if the e or r prefix on a general reg is present. */
5594 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5595 && (i
.types
[op
].bitfield
.reg32
5596 || i
.types
[op
].bitfield
.reg64
)
5597 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5598 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5600 /* Prohibit these changes in the 64bit mode, since the
5601 lowering is more complicated. */
5602 if (flag_code
== CODE_64BIT
)
5604 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5605 register_prefix
, i
.op
[op
].regs
->reg_name
,
5609 #if REGISTER_WARNINGS
5610 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5612 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5613 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5620 update_imm (unsigned int j
)
5622 i386_operand_type overlap
= i
.types
[j
];
5623 if ((overlap
.bitfield
.imm8
5624 || overlap
.bitfield
.imm8s
5625 || overlap
.bitfield
.imm16
5626 || overlap
.bitfield
.imm32
5627 || overlap
.bitfield
.imm32s
5628 || overlap
.bitfield
.imm64
)
5629 && !operand_type_equal (&overlap
, &imm8
)
5630 && !operand_type_equal (&overlap
, &imm8s
)
5631 && !operand_type_equal (&overlap
, &imm16
)
5632 && !operand_type_equal (&overlap
, &imm32
)
5633 && !operand_type_equal (&overlap
, &imm32s
)
5634 && !operand_type_equal (&overlap
, &imm64
))
5638 i386_operand_type temp
;
5640 operand_type_set (&temp
, 0);
5641 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5643 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5644 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5646 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5647 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5648 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5650 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5651 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5654 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5657 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5658 || operand_type_equal (&overlap
, &imm16_32
)
5659 || operand_type_equal (&overlap
, &imm16_32s
))
5661 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5666 if (!operand_type_equal (&overlap
, &imm8
)
5667 && !operand_type_equal (&overlap
, &imm8s
)
5668 && !operand_type_equal (&overlap
, &imm16
)
5669 && !operand_type_equal (&overlap
, &imm32
)
5670 && !operand_type_equal (&overlap
, &imm32s
)
5671 && !operand_type_equal (&overlap
, &imm64
))
5673 as_bad (_("no instruction mnemonic suffix given; "
5674 "can't determine immediate size"));
5678 i
.types
[j
] = overlap
;
5688 /* Update the first 2 immediate operands. */
5689 n
= i
.operands
> 2 ? 2 : i
.operands
;
5692 for (j
= 0; j
< n
; j
++)
5693 if (update_imm (j
) == 0)
5696 /* The 3rd operand can't be immediate operand. */
5697 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5704 bad_implicit_operand (int xmm
)
5706 const char *ireg
= xmm
? "xmm0" : "ymm0";
5709 as_bad (_("the last operand of `%s' must be `%s%s'"),
5710 i
.tm
.name
, register_prefix
, ireg
);
5712 as_bad (_("the first operand of `%s' must be `%s%s'"),
5713 i
.tm
.name
, register_prefix
, ireg
);
5718 process_operands (void)
5720 /* Default segment register this instruction will use for memory
5721 accesses. 0 means unknown. This is only for optimizing out
5722 unnecessary segment overrides. */
5723 const seg_entry
*default_seg
= 0;
5725 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5727 unsigned int dupl
= i
.operands
;
5728 unsigned int dest
= dupl
- 1;
5731 /* The destination must be an xmm register. */
5732 gas_assert (i
.reg_operands
5733 && MAX_OPERANDS
> dupl
5734 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5736 if (i
.tm
.opcode_modifier
.firstxmm0
)
5738 /* The first operand is implicit and must be xmm0. */
5739 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5740 if (register_number (i
.op
[0].regs
) != 0)
5741 return bad_implicit_operand (1);
5743 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5745 /* Keep xmm0 for instructions with VEX prefix and 3
5751 /* We remove the first xmm0 and keep the number of
5752 operands unchanged, which in fact duplicates the
5754 for (j
= 1; j
< i
.operands
; j
++)
5756 i
.op
[j
- 1] = i
.op
[j
];
5757 i
.types
[j
- 1] = i
.types
[j
];
5758 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5762 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5764 gas_assert ((MAX_OPERANDS
- 1) > dupl
5765 && (i
.tm
.opcode_modifier
.vexsources
5768 /* Add the implicit xmm0 for instructions with VEX prefix
5770 for (j
= i
.operands
; j
> 0; j
--)
5772 i
.op
[j
] = i
.op
[j
- 1];
5773 i
.types
[j
] = i
.types
[j
- 1];
5774 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5777 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5778 i
.types
[0] = regxmm
;
5779 i
.tm
.operand_types
[0] = regxmm
;
5782 i
.reg_operands
+= 2;
5787 i
.op
[dupl
] = i
.op
[dest
];
5788 i
.types
[dupl
] = i
.types
[dest
];
5789 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5798 i
.op
[dupl
] = i
.op
[dest
];
5799 i
.types
[dupl
] = i
.types
[dest
];
5800 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5803 if (i
.tm
.opcode_modifier
.immext
)
5806 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5810 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5811 gas_assert (i
.reg_operands
5812 && (operand_type_equal (&i
.types
[0], ®xmm
)
5813 || operand_type_equal (&i
.types
[0], ®ymm
)
5814 || operand_type_equal (&i
.types
[0], ®zmm
)));
5815 if (register_number (i
.op
[0].regs
) != 0)
5816 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5818 for (j
= 1; j
< i
.operands
; j
++)
5820 i
.op
[j
- 1] = i
.op
[j
];
5821 i
.types
[j
- 1] = i
.types
[j
];
5823 /* We need to adjust fields in i.tm since they are used by
5824 build_modrm_byte. */
5825 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5832 else if (i
.tm
.opcode_modifier
.regkludge
)
5834 /* The imul $imm, %reg instruction is converted into
5835 imul $imm, %reg, %reg, and the clr %reg instruction
5836 is converted into xor %reg, %reg. */
5838 unsigned int first_reg_op
;
5840 if (operand_type_check (i
.types
[0], reg
))
5844 /* Pretend we saw the extra register operand. */
5845 gas_assert (i
.reg_operands
== 1
5846 && i
.op
[first_reg_op
+ 1].regs
== 0);
5847 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5848 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5853 if (i
.tm
.opcode_modifier
.shortform
)
5855 if (i
.types
[0].bitfield
.sreg2
5856 || i
.types
[0].bitfield
.sreg3
)
5858 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5859 && i
.op
[0].regs
->reg_num
== 1)
5861 as_bad (_("you can't `pop %scs'"), register_prefix
);
5864 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5865 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5870 /* The register or float register operand is in operand
5874 if (i
.types
[0].bitfield
.floatreg
5875 || operand_type_check (i
.types
[0], reg
))
5879 /* Register goes in low 3 bits of opcode. */
5880 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5881 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5883 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5885 /* Warn about some common errors, but press on regardless.
5886 The first case can be generated by gcc (<= 2.8.1). */
5887 if (i
.operands
== 2)
5889 /* Reversed arguments on faddp, fsubp, etc. */
5890 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5891 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5892 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5896 /* Extraneous `l' suffix on fp insn. */
5897 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5898 register_prefix
, i
.op
[0].regs
->reg_name
);
5903 else if (i
.tm
.opcode_modifier
.modrm
)
5905 /* The opcode is completed (modulo i.tm.extension_opcode which
5906 must be put into the modrm byte). Now, we make the modrm and
5907 index base bytes based on all the info we've collected. */
5909 default_seg
= build_modrm_byte ();
5911 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5915 else if (i
.tm
.opcode_modifier
.isstring
)
5917 /* For the string instructions that allow a segment override
5918 on one of their operands, the default segment is ds. */
5922 if (i
.tm
.base_opcode
== 0x8d /* lea */
5925 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5927 /* If a segment was explicitly specified, and the specified segment
5928 is not the default, use an opcode prefix to select it. If we
5929 never figured out what the default segment is, then default_seg
5930 will be zero at this point, and the specified segment prefix will
5932 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5934 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5940 static const seg_entry
*
5941 build_modrm_byte (void)
5943 const seg_entry
*default_seg
= 0;
5944 unsigned int source
, dest
;
5947 /* The first operand of instructions with VEX prefix and 3 sources
5948 must be VEX_Imm4. */
5949 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5952 unsigned int nds
, reg_slot
;
5955 if (i
.tm
.opcode_modifier
.veximmext
5956 && i
.tm
.opcode_modifier
.immext
)
5958 dest
= i
.operands
- 2;
5959 gas_assert (dest
== 3);
5962 dest
= i
.operands
- 1;
5965 /* There are 2 kinds of instructions:
5966 1. 5 operands: 4 register operands or 3 register operands
5967 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5968 VexW0 or VexW1. The destination must be either XMM, YMM or
5970 2. 4 operands: 4 register operands or 3 register operands
5971 plus 1 memory operand, VexXDS, and VexImmExt */
5972 gas_assert ((i
.reg_operands
== 4
5973 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5974 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5975 && (i
.tm
.opcode_modifier
.veximmext
5976 || (i
.imm_operands
== 1
5977 && i
.types
[0].bitfield
.vec_imm4
5978 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5979 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5980 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5981 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5982 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5984 if (i
.imm_operands
== 0)
5986 /* When there is no immediate operand, generate an 8bit
5987 immediate operand to encode the first operand. */
5988 exp
= &im_expressions
[i
.imm_operands
++];
5989 i
.op
[i
.operands
].imms
= exp
;
5990 i
.types
[i
.operands
] = imm8
;
5992 /* If VexW1 is set, the first operand is the source and
5993 the second operand is encoded in the immediate operand. */
5994 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6005 /* FMA swaps REG and NDS. */
6006 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6014 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6016 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6018 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6020 exp
->X_op
= O_constant
;
6021 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6022 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6026 unsigned int imm_slot
;
6028 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6030 /* If VexW0 is set, the third operand is the source and
6031 the second operand is encoded in the immediate
6038 /* VexW1 is set, the second operand is the source and
6039 the third operand is encoded in the immediate
6045 if (i
.tm
.opcode_modifier
.immext
)
6047 /* When ImmExt is set, the immdiate byte is the last
6049 imm_slot
= i
.operands
- 1;
6057 /* Turn on Imm8 so that output_imm will generate it. */
6058 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6061 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6063 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6065 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6067 i
.op
[imm_slot
].imms
->X_add_number
6068 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6069 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6072 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6073 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6075 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6077 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6082 /* i.reg_operands MUST be the number of real register operands;
6083 implicit registers do not count. If there are 3 register
6084 operands, it must be a instruction with VexNDS. For a
6085 instruction with VexNDD, the destination register is encoded
6086 in VEX prefix. If there are 4 register operands, it must be
6087 a instruction with VEX prefix and 3 sources. */
6088 if (i
.mem_operands
== 0
6089 && ((i
.reg_operands
== 2
6090 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6091 || (i
.reg_operands
== 3
6092 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6093 || (i
.reg_operands
== 4 && vex_3_sources
)))
6101 /* When there are 3 operands, one of them may be immediate,
6102 which may be the first or the last operand. Otherwise,
6103 the first operand must be shift count register (cl) or it
6104 is an instruction with VexNDS. */
6105 gas_assert (i
.imm_operands
== 1
6106 || (i
.imm_operands
== 0
6107 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6108 || i
.types
[0].bitfield
.shiftcount
)));
6109 if (operand_type_check (i
.types
[0], imm
)
6110 || i
.types
[0].bitfield
.shiftcount
)
6116 /* When there are 4 operands, the first two must be 8bit
6117 immediate operands. The source operand will be the 3rd
6120 For instructions with VexNDS, if the first operand
6121 an imm8, the source operand is the 2nd one. If the last
6122 operand is imm8, the source operand is the first one. */
6123 gas_assert ((i
.imm_operands
== 2
6124 && i
.types
[0].bitfield
.imm8
6125 && i
.types
[1].bitfield
.imm8
)
6126 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6127 && i
.imm_operands
== 1
6128 && (i
.types
[0].bitfield
.imm8
6129 || i
.types
[i
.operands
- 1].bitfield
.imm8
6131 if (i
.imm_operands
== 2)
6135 if (i
.types
[0].bitfield
.imm8
)
6142 if (i
.tm
.opcode_modifier
.evex
)
6144 /* For EVEX instructions, when there are 5 operands, the
6145 first one must be immediate operand. If the second one
6146 is immediate operand, the source operand is the 3th
6147 one. If the last one is immediate operand, the source
6148 operand is the 2nd one. */
6149 gas_assert (i
.imm_operands
== 2
6150 && i
.tm
.opcode_modifier
.sae
6151 && operand_type_check (i
.types
[0], imm
));
6152 if (operand_type_check (i
.types
[1], imm
))
6154 else if (operand_type_check (i
.types
[4], imm
))
6168 /* RC/SAE operand could be between DEST and SRC. That happens
6169 when one operand is GPR and the other one is XMM/YMM/ZMM
6171 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6174 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6176 /* For instructions with VexNDS, the register-only source
6177 operand must be 32/64bit integer, XMM, YMM or ZMM
6178 register. It is encoded in VEX prefix. We need to
6179 clear RegMem bit before calling operand_type_equal. */
6181 i386_operand_type op
;
6184 /* Check register-only source operand when two source
6185 operands are swapped. */
6186 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6187 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6195 op
= i
.tm
.operand_types
[vvvv
];
6196 op
.bitfield
.regmem
= 0;
6197 if ((dest
+ 1) >= i
.operands
6198 || (!op
.bitfield
.reg32
6199 && op
.bitfield
.reg64
6200 && !operand_type_equal (&op
, ®xmm
)
6201 && !operand_type_equal (&op
, ®ymm
)
6202 && !operand_type_equal (&op
, ®zmm
)
6203 && !operand_type_equal (&op
, ®mask
)))
6205 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6211 /* One of the register operands will be encoded in the i.tm.reg
6212 field, the other in the combined i.tm.mode and i.tm.regmem
6213 fields. If no form of this instruction supports a memory
6214 destination operand, then we assume the source operand may
6215 sometimes be a memory operand and so we need to store the
6216 destination in the i.rm.reg field. */
6217 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6218 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6220 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6221 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6222 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6224 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6226 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6228 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6233 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6234 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6235 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6237 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6239 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6241 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6244 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6246 if (!i
.types
[0].bitfield
.control
6247 && !i
.types
[1].bitfield
.control
)
6249 i
.rex
&= ~(REX_R
| REX_B
);
6250 add_prefix (LOCK_PREFIX_OPCODE
);
6254 { /* If it's not 2 reg operands... */
6259 unsigned int fake_zero_displacement
= 0;
6262 for (op
= 0; op
< i
.operands
; op
++)
6263 if (operand_type_check (i
.types
[op
], anymem
))
6265 gas_assert (op
< i
.operands
);
6267 if (i
.tm
.opcode_modifier
.vecsib
)
6269 if (i
.index_reg
->reg_num
== RegEiz
6270 || i
.index_reg
->reg_num
== RegRiz
)
6273 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6276 i
.sib
.base
= NO_BASE_REGISTER
;
6277 i
.sib
.scale
= i
.log2_scale_factor
;
6278 /* No Vec_Disp8 if there is no base. */
6279 i
.types
[op
].bitfield
.vec_disp8
= 0;
6280 i
.types
[op
].bitfield
.disp8
= 0;
6281 i
.types
[op
].bitfield
.disp16
= 0;
6282 i
.types
[op
].bitfield
.disp64
= 0;
6283 if (flag_code
!= CODE_64BIT
)
6285 /* Must be 32 bit */
6286 i
.types
[op
].bitfield
.disp32
= 1;
6287 i
.types
[op
].bitfield
.disp32s
= 0;
6291 i
.types
[op
].bitfield
.disp32
= 0;
6292 i
.types
[op
].bitfield
.disp32s
= 1;
6295 i
.sib
.index
= i
.index_reg
->reg_num
;
6296 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6298 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6304 if (i
.base_reg
== 0)
6307 if (!i
.disp_operands
)
6309 fake_zero_displacement
= 1;
6310 /* Instructions with VSIB byte need 32bit displacement
6311 if there is no base register. */
6312 if (i
.tm
.opcode_modifier
.vecsib
)
6313 i
.types
[op
].bitfield
.disp32
= 1;
6315 if (i
.index_reg
== 0)
6317 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6318 /* Operand is just <disp> */
6319 if (flag_code
== CODE_64BIT
)
6321 /* 64bit mode overwrites the 32bit absolute
6322 addressing by RIP relative addressing and
6323 absolute addressing is encoded by one of the
6324 redundant SIB forms. */
6325 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6326 i
.sib
.base
= NO_BASE_REGISTER
;
6327 i
.sib
.index
= NO_INDEX_REGISTER
;
6328 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6329 ? disp32s
: disp32
);
6331 else if ((flag_code
== CODE_16BIT
)
6332 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6334 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6335 i
.types
[op
] = disp16
;
6339 i
.rm
.regmem
= NO_BASE_REGISTER
;
6340 i
.types
[op
] = disp32
;
6343 else if (!i
.tm
.opcode_modifier
.vecsib
)
6345 /* !i.base_reg && i.index_reg */
6346 if (i
.index_reg
->reg_num
== RegEiz
6347 || i
.index_reg
->reg_num
== RegRiz
)
6348 i
.sib
.index
= NO_INDEX_REGISTER
;
6350 i
.sib
.index
= i
.index_reg
->reg_num
;
6351 i
.sib
.base
= NO_BASE_REGISTER
;
6352 i
.sib
.scale
= i
.log2_scale_factor
;
6353 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6354 /* No Vec_Disp8 if there is no base. */
6355 i
.types
[op
].bitfield
.vec_disp8
= 0;
6356 i
.types
[op
].bitfield
.disp8
= 0;
6357 i
.types
[op
].bitfield
.disp16
= 0;
6358 i
.types
[op
].bitfield
.disp64
= 0;
6359 if (flag_code
!= CODE_64BIT
)
6361 /* Must be 32 bit */
6362 i
.types
[op
].bitfield
.disp32
= 1;
6363 i
.types
[op
].bitfield
.disp32s
= 0;
6367 i
.types
[op
].bitfield
.disp32
= 0;
6368 i
.types
[op
].bitfield
.disp32s
= 1;
6370 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6374 /* RIP addressing for 64bit mode. */
6375 else if (i
.base_reg
->reg_num
== RegRip
||
6376 i
.base_reg
->reg_num
== RegEip
)
6378 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6379 i
.rm
.regmem
= NO_BASE_REGISTER
;
6380 i
.types
[op
].bitfield
.disp8
= 0;
6381 i
.types
[op
].bitfield
.disp16
= 0;
6382 i
.types
[op
].bitfield
.disp32
= 0;
6383 i
.types
[op
].bitfield
.disp32s
= 1;
6384 i
.types
[op
].bitfield
.disp64
= 0;
6385 i
.types
[op
].bitfield
.vec_disp8
= 0;
6386 i
.flags
[op
] |= Operand_PCrel
;
6387 if (! i
.disp_operands
)
6388 fake_zero_displacement
= 1;
6390 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6392 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6393 switch (i
.base_reg
->reg_num
)
6396 if (i
.index_reg
== 0)
6398 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6399 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6403 if (i
.index_reg
== 0)
6406 if (operand_type_check (i
.types
[op
], disp
) == 0)
6408 /* fake (%bp) into 0(%bp) */
6409 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6410 i
.types
[op
].bitfield
.vec_disp8
= 1;
6412 i
.types
[op
].bitfield
.disp8
= 1;
6413 fake_zero_displacement
= 1;
6416 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6417 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6419 default: /* (%si) -> 4 or (%di) -> 5 */
6420 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6422 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6424 else /* i.base_reg and 32/64 bit mode */
6426 if (flag_code
== CODE_64BIT
6427 && operand_type_check (i
.types
[op
], disp
))
6429 i386_operand_type temp
;
6430 operand_type_set (&temp
, 0);
6431 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6432 temp
.bitfield
.vec_disp8
6433 = i
.types
[op
].bitfield
.vec_disp8
;
6435 if (i
.prefix
[ADDR_PREFIX
] == 0)
6436 i
.types
[op
].bitfield
.disp32s
= 1;
6438 i
.types
[op
].bitfield
.disp32
= 1;
6441 if (!i
.tm
.opcode_modifier
.vecsib
)
6442 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6443 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6445 i
.sib
.base
= i
.base_reg
->reg_num
;
6446 /* x86-64 ignores REX prefix bit here to avoid decoder
6448 if (!(i
.base_reg
->reg_flags
& RegRex
)
6449 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6450 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6452 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6454 fake_zero_displacement
= 1;
6455 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6456 i
.types
[op
].bitfield
.vec_disp8
= 1;
6458 i
.types
[op
].bitfield
.disp8
= 1;
6460 i
.sib
.scale
= i
.log2_scale_factor
;
6461 if (i
.index_reg
== 0)
6463 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6464 /* <disp>(%esp) becomes two byte modrm with no index
6465 register. We've already stored the code for esp
6466 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6467 Any base register besides %esp will not use the
6468 extra modrm byte. */
6469 i
.sib
.index
= NO_INDEX_REGISTER
;
6471 else if (!i
.tm
.opcode_modifier
.vecsib
)
6473 if (i
.index_reg
->reg_num
== RegEiz
6474 || i
.index_reg
->reg_num
== RegRiz
)
6475 i
.sib
.index
= NO_INDEX_REGISTER
;
6477 i
.sib
.index
= i
.index_reg
->reg_num
;
6478 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6479 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6484 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6485 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6489 if (!fake_zero_displacement
6493 fake_zero_displacement
= 1;
6494 if (i
.disp_encoding
== disp_encoding_8bit
)
6495 i
.types
[op
].bitfield
.disp8
= 1;
6497 i
.types
[op
].bitfield
.disp32
= 1;
6499 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6503 if (fake_zero_displacement
)
6505 /* Fakes a zero displacement assuming that i.types[op]
6506 holds the correct displacement size. */
6509 gas_assert (i
.op
[op
].disps
== 0);
6510 exp
= &disp_expressions
[i
.disp_operands
++];
6511 i
.op
[op
].disps
= exp
;
6512 exp
->X_op
= O_constant
;
6513 exp
->X_add_number
= 0;
6514 exp
->X_add_symbol
= (symbolS
*) 0;
6515 exp
->X_op_symbol
= (symbolS
*) 0;
6523 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6525 if (operand_type_check (i
.types
[0], imm
))
6526 i
.vex
.register_specifier
= NULL
;
6529 /* VEX.vvvv encodes one of the sources when the first
6530 operand is not an immediate. */
6531 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6532 i
.vex
.register_specifier
= i
.op
[0].regs
;
6534 i
.vex
.register_specifier
= i
.op
[1].regs
;
6537 /* Destination is a XMM register encoded in the ModRM.reg
6539 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6540 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6543 /* ModRM.rm and VEX.B encodes the other source. */
6544 if (!i
.mem_operands
)
6548 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6549 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6551 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6553 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6557 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6559 i
.vex
.register_specifier
= i
.op
[2].regs
;
6560 if (!i
.mem_operands
)
6563 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6564 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6568 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6569 (if any) based on i.tm.extension_opcode. Again, we must be
6570 careful to make sure that segment/control/debug/test/MMX
6571 registers are coded into the i.rm.reg field. */
6572 else if (i
.reg_operands
)
6575 unsigned int vex_reg
= ~0;
6577 for (op
= 0; op
< i
.operands
; op
++)
6578 if (i
.types
[op
].bitfield
.reg8
6579 || i
.types
[op
].bitfield
.reg16
6580 || i
.types
[op
].bitfield
.reg32
6581 || i
.types
[op
].bitfield
.reg64
6582 || i
.types
[op
].bitfield
.regmmx
6583 || i
.types
[op
].bitfield
.regxmm
6584 || i
.types
[op
].bitfield
.regymm
6585 || i
.types
[op
].bitfield
.regbnd
6586 || i
.types
[op
].bitfield
.regzmm
6587 || i
.types
[op
].bitfield
.regmask
6588 || i
.types
[op
].bitfield
.sreg2
6589 || i
.types
[op
].bitfield
.sreg3
6590 || i
.types
[op
].bitfield
.control
6591 || i
.types
[op
].bitfield
.debug
6592 || i
.types
[op
].bitfield
.test
)
6597 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6599 /* For instructions with VexNDS, the register-only
6600 source operand is encoded in VEX prefix. */
6601 gas_assert (mem
!= (unsigned int) ~0);
6606 gas_assert (op
< i
.operands
);
6610 /* Check register-only source operand when two source
6611 operands are swapped. */
6612 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6613 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6617 gas_assert (mem
== (vex_reg
+ 1)
6618 && op
< i
.operands
);
6623 gas_assert (vex_reg
< i
.operands
);
6627 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6629 /* For instructions with VexNDD, the register destination
6630 is encoded in VEX prefix. */
6631 if (i
.mem_operands
== 0)
6633 /* There is no memory operand. */
6634 gas_assert ((op
+ 2) == i
.operands
);
6639 /* There are only 2 operands. */
6640 gas_assert (op
< 2 && i
.operands
== 2);
6645 gas_assert (op
< i
.operands
);
6647 if (vex_reg
!= (unsigned int) ~0)
6649 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6651 if (type
->bitfield
.reg32
!= 1
6652 && type
->bitfield
.reg64
!= 1
6653 && !operand_type_equal (type
, ®xmm
)
6654 && !operand_type_equal (type
, ®ymm
)
6655 && !operand_type_equal (type
, ®zmm
)
6656 && !operand_type_equal (type
, ®mask
))
6659 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6662 /* Don't set OP operand twice. */
6665 /* If there is an extension opcode to put here, the
6666 register number must be put into the regmem field. */
6667 if (i
.tm
.extension_opcode
!= None
)
6669 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6670 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6672 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6677 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6678 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6680 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6685 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6686 must set it to 3 to indicate this is a register operand
6687 in the regmem field. */
6688 if (!i
.mem_operands
)
6692 /* Fill in i.rm.reg field with extension opcode (if any). */
6693 if (i
.tm
.extension_opcode
!= None
)
6694 i
.rm
.reg
= i
.tm
.extension_opcode
;
6700 output_branch (void)
6706 relax_substateT subtype
;
6710 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6711 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6714 if (i
.prefix
[DATA_PREFIX
] != 0)
6720 /* Pentium4 branch hints. */
6721 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6722 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6727 if (i
.prefix
[REX_PREFIX
] != 0)
6733 /* BND prefixed jump. */
6734 if (i
.prefix
[BND_PREFIX
] != 0)
6736 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6740 if (i
.prefixes
!= 0 && !intel_syntax
)
6741 as_warn (_("skipping prefixes on this instruction"));
6743 /* It's always a symbol; End frag & setup for relax.
6744 Make sure there is enough room in this frag for the largest
6745 instruction we may generate in md_convert_frag. This is 2
6746 bytes for the opcode and room for the prefix and largest
6748 frag_grow (prefix
+ 2 + 4);
6749 /* Prefix and 1 opcode byte go in fr_fix. */
6750 p
= frag_more (prefix
+ 1);
6751 if (i
.prefix
[DATA_PREFIX
] != 0)
6752 *p
++ = DATA_PREFIX_OPCODE
;
6753 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6754 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6755 *p
++ = i
.prefix
[SEG_PREFIX
];
6756 if (i
.prefix
[REX_PREFIX
] != 0)
6757 *p
++ = i
.prefix
[REX_PREFIX
];
6758 *p
= i
.tm
.base_opcode
;
6760 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6761 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6762 else if (cpu_arch_flags
.bitfield
.cpui386
)
6763 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6765 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6768 sym
= i
.op
[0].disps
->X_add_symbol
;
6769 off
= i
.op
[0].disps
->X_add_number
;
6771 if (i
.op
[0].disps
->X_op
!= O_constant
6772 && i
.op
[0].disps
->X_op
!= O_symbol
)
6774 /* Handle complex expressions. */
6775 sym
= make_expr_symbol (i
.op
[0].disps
);
6779 /* 1 possible extra opcode + 4 byte displacement go in var part.
6780 Pass reloc in fr_var. */
6781 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6791 if (i
.tm
.opcode_modifier
.jumpbyte
)
6793 /* This is a loop or jecxz type instruction. */
6795 if (i
.prefix
[ADDR_PREFIX
] != 0)
6797 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6800 /* Pentium4 branch hints. */
6801 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6802 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6804 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6813 if (flag_code
== CODE_16BIT
)
6816 if (i
.prefix
[DATA_PREFIX
] != 0)
6818 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6828 if (i
.prefix
[REX_PREFIX
] != 0)
6830 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6834 /* BND prefixed jump. */
6835 if (i
.prefix
[BND_PREFIX
] != 0)
6837 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6841 if (i
.prefixes
!= 0 && !intel_syntax
)
6842 as_warn (_("skipping prefixes on this instruction"));
6844 p
= frag_more (i
.tm
.opcode_length
+ size
);
6845 switch (i
.tm
.opcode_length
)
6848 *p
++ = i
.tm
.base_opcode
>> 8;
6850 *p
++ = i
.tm
.base_opcode
;
6856 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6857 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6859 /* All jumps handled here are signed, but don't use a signed limit
6860 check for 32 and 16 bit jumps as we want to allow wrap around at
6861 4G and 64k respectively. */
6863 fixP
->fx_signed
= 1;
6867 output_interseg_jump (void)
6875 if (flag_code
== CODE_16BIT
)
6879 if (i
.prefix
[DATA_PREFIX
] != 0)
6885 if (i
.prefix
[REX_PREFIX
] != 0)
6895 if (i
.prefixes
!= 0 && !intel_syntax
)
6896 as_warn (_("skipping prefixes on this instruction"));
6898 /* 1 opcode; 2 segment; offset */
6899 p
= frag_more (prefix
+ 1 + 2 + size
);
6901 if (i
.prefix
[DATA_PREFIX
] != 0)
6902 *p
++ = DATA_PREFIX_OPCODE
;
6904 if (i
.prefix
[REX_PREFIX
] != 0)
6905 *p
++ = i
.prefix
[REX_PREFIX
];
6907 *p
++ = i
.tm
.base_opcode
;
6908 if (i
.op
[1].imms
->X_op
== O_constant
)
6910 offsetT n
= i
.op
[1].imms
->X_add_number
;
6913 && !fits_in_unsigned_word (n
)
6914 && !fits_in_signed_word (n
))
6916 as_bad (_("16-bit jump out of range"));
6919 md_number_to_chars (p
, n
, size
);
6922 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6923 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6924 if (i
.op
[0].imms
->X_op
!= O_constant
)
6925 as_bad (_("can't handle non absolute segment in `%s'"),
6927 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6933 fragS
*insn_start_frag
;
6934 offsetT insn_start_off
;
6936 /* Tie dwarf2 debug info to the address at the start of the insn.
6937 We can't do this after the insn has been output as the current
6938 frag may have been closed off. eg. by frag_var. */
6939 dwarf2_emit_insn (0);
6941 insn_start_frag
= frag_now
;
6942 insn_start_off
= frag_now_fix ();
6945 if (i
.tm
.opcode_modifier
.jump
)
6947 else if (i
.tm
.opcode_modifier
.jumpbyte
6948 || i
.tm
.opcode_modifier
.jumpdword
)
6950 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6951 output_interseg_jump ();
6954 /* Output normal instructions here. */
6958 unsigned int prefix
;
6960 /* Some processors fail on LOCK prefix. This options makes
6961 assembler ignore LOCK prefix and serves as a workaround. */
6962 if (omit_lock_prefix
)
6964 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6966 i
.prefix
[LOCK_PREFIX
] = 0;
6969 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6970 don't need the explicit prefix. */
6971 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6973 switch (i
.tm
.opcode_length
)
6976 if (i
.tm
.base_opcode
& 0xff000000)
6978 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6983 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6985 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6986 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6989 if (prefix
!= REPE_PREFIX_OPCODE
6990 || (i
.prefix
[REP_PREFIX
]
6991 != REPE_PREFIX_OPCODE
))
6992 add_prefix (prefix
);
6995 add_prefix (prefix
);
7004 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7005 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7006 R_X86_64_GOTTPOFF relocation so that linker can safely
7007 perform IE->LE optimization. */
7008 if (x86_elf_abi
== X86_64_X32_ABI
7010 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7011 && i
.prefix
[REX_PREFIX
] == 0)
7012 add_prefix (REX_OPCODE
);
7015 /* The prefix bytes. */
7016 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7018 FRAG_APPEND_1_CHAR (*q
);
7022 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7027 /* REX byte is encoded in VEX prefix. */
7031 FRAG_APPEND_1_CHAR (*q
);
7034 /* There should be no other prefixes for instructions
7039 /* For EVEX instructions i.vrex should become 0 after
7040 build_evex_prefix. For VEX instructions upper 16 registers
7041 aren't available, so VREX should be 0. */
7044 /* Now the VEX prefix. */
7045 p
= frag_more (i
.vex
.length
);
7046 for (j
= 0; j
< i
.vex
.length
; j
++)
7047 p
[j
] = i
.vex
.bytes
[j
];
7050 /* Now the opcode; be careful about word order here! */
7051 if (i
.tm
.opcode_length
== 1)
7053 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7057 switch (i
.tm
.opcode_length
)
7061 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7062 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7066 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7076 /* Put out high byte first: can't use md_number_to_chars! */
7077 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7078 *p
= i
.tm
.base_opcode
& 0xff;
7081 /* Now the modrm byte and sib byte (if present). */
7082 if (i
.tm
.opcode_modifier
.modrm
)
7084 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7087 /* If i.rm.regmem == ESP (4)
7088 && i.rm.mode != (Register mode)
7090 ==> need second modrm byte. */
7091 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7093 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7094 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7096 | i
.sib
.scale
<< 6));
7099 if (i
.disp_operands
)
7100 output_disp (insn_start_frag
, insn_start_off
);
7103 output_imm (insn_start_frag
, insn_start_off
);
7109 pi ("" /*line*/, &i
);
7111 #endif /* DEBUG386 */
7114 /* Return the size of the displacement operand N. */
7117 disp_size (unsigned int n
)
7121 /* Vec_Disp8 has to be 8bit. */
7122 if (i
.types
[n
].bitfield
.vec_disp8
)
7124 else if (i
.types
[n
].bitfield
.disp64
)
7126 else if (i
.types
[n
].bitfield
.disp8
)
7128 else if (i
.types
[n
].bitfield
.disp16
)
7133 /* Return the size of the immediate operand N. */
7136 imm_size (unsigned int n
)
7139 if (i
.types
[n
].bitfield
.imm64
)
7141 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7143 else if (i
.types
[n
].bitfield
.imm16
)
7149 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7154 for (n
= 0; n
< i
.operands
; n
++)
7156 if (i
.types
[n
].bitfield
.vec_disp8
7157 || operand_type_check (i
.types
[n
], disp
))
7159 if (i
.op
[n
].disps
->X_op
== O_constant
)
7161 int size
= disp_size (n
);
7162 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7164 if (i
.types
[n
].bitfield
.vec_disp8
)
7166 val
= offset_in_range (val
, size
);
7167 p
= frag_more (size
);
7168 md_number_to_chars (p
, val
, size
);
7172 enum bfd_reloc_code_real reloc_type
;
7173 int size
= disp_size (n
);
7174 int sign
= i
.types
[n
].bitfield
.disp32s
;
7175 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7177 /* We can't have 8 bit displacement here. */
7178 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7180 /* The PC relative address is computed relative
7181 to the instruction boundary, so in case immediate
7182 fields follows, we need to adjust the value. */
7183 if (pcrel
&& i
.imm_operands
)
7188 for (n1
= 0; n1
< i
.operands
; n1
++)
7189 if (operand_type_check (i
.types
[n1
], imm
))
7191 /* Only one immediate is allowed for PC
7192 relative address. */
7193 gas_assert (sz
== 0);
7195 i
.op
[n
].disps
->X_add_number
-= sz
;
7197 /* We should find the immediate. */
7198 gas_assert (sz
!= 0);
7201 p
= frag_more (size
);
7202 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7204 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7205 && (((reloc_type
== BFD_RELOC_32
7206 || reloc_type
== BFD_RELOC_X86_64_32S
7207 || (reloc_type
== BFD_RELOC_64
7209 && (i
.op
[n
].disps
->X_op
== O_symbol
7210 || (i
.op
[n
].disps
->X_op
== O_add
7211 && ((symbol_get_value_expression
7212 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7214 || reloc_type
== BFD_RELOC_32_PCREL
))
7218 if (insn_start_frag
== frag_now
)
7219 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7224 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7225 for (fr
= insn_start_frag
->fr_next
;
7226 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7228 add
+= p
- frag_now
->fr_literal
;
7233 reloc_type
= BFD_RELOC_386_GOTPC
;
7234 i
.op
[n
].imms
->X_add_number
+= add
;
7236 else if (reloc_type
== BFD_RELOC_64
)
7237 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7239 /* Don't do the adjustment for x86-64, as there
7240 the pcrel addressing is relative to the _next_
7241 insn, and that is taken care of in other code. */
7242 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7244 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7245 i
.op
[n
].disps
, pcrel
, reloc_type
);
7252 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7257 for (n
= 0; n
< i
.operands
; n
++)
7259 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7260 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7263 if (operand_type_check (i
.types
[n
], imm
))
7265 if (i
.op
[n
].imms
->X_op
== O_constant
)
7267 int size
= imm_size (n
);
7270 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7272 p
= frag_more (size
);
7273 md_number_to_chars (p
, val
, size
);
7277 /* Not absolute_section.
7278 Need a 32-bit fixup (don't support 8bit
7279 non-absolute imms). Try to support other
7281 enum bfd_reloc_code_real reloc_type
;
7282 int size
= imm_size (n
);
7285 if (i
.types
[n
].bitfield
.imm32s
7286 && (i
.suffix
== QWORD_MNEM_SUFFIX
7287 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7292 p
= frag_more (size
);
7293 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7295 /* This is tough to explain. We end up with this one if we
7296 * have operands that look like
7297 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7298 * obtain the absolute address of the GOT, and it is strongly
7299 * preferable from a performance point of view to avoid using
7300 * a runtime relocation for this. The actual sequence of
7301 * instructions often look something like:
7306 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7308 * The call and pop essentially return the absolute address
7309 * of the label .L66 and store it in %ebx. The linker itself
7310 * will ultimately change the first operand of the addl so
7311 * that %ebx points to the GOT, but to keep things simple, the
7312 * .o file must have this operand set so that it generates not
7313 * the absolute address of .L66, but the absolute address of
7314 * itself. This allows the linker itself simply treat a GOTPC
7315 * relocation as asking for a pcrel offset to the GOT to be
7316 * added in, and the addend of the relocation is stored in the
7317 * operand field for the instruction itself.
7319 * Our job here is to fix the operand so that it would add
7320 * the correct offset so that %ebx would point to itself. The
7321 * thing that is tricky is that .-.L66 will point to the
7322 * beginning of the instruction, so we need to further modify
7323 * the operand so that it will point to itself. There are
7324 * other cases where you have something like:
7326 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7328 * and here no correction would be required. Internally in
7329 * the assembler we treat operands of this form as not being
7330 * pcrel since the '.' is explicitly mentioned, and I wonder
7331 * whether it would simplify matters to do it this way. Who
7332 * knows. In earlier versions of the PIC patches, the
7333 * pcrel_adjust field was used to store the correction, but
7334 * since the expression is not pcrel, I felt it would be
7335 * confusing to do it this way. */
7337 if ((reloc_type
== BFD_RELOC_32
7338 || reloc_type
== BFD_RELOC_X86_64_32S
7339 || reloc_type
== BFD_RELOC_64
)
7341 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7342 && (i
.op
[n
].imms
->X_op
== O_symbol
7343 || (i
.op
[n
].imms
->X_op
== O_add
7344 && ((symbol_get_value_expression
7345 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7350 if (insn_start_frag
== frag_now
)
7351 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7356 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7357 for (fr
= insn_start_frag
->fr_next
;
7358 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7360 add
+= p
- frag_now
->fr_literal
;
7364 reloc_type
= BFD_RELOC_386_GOTPC
;
7366 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7368 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7369 i
.op
[n
].imms
->X_add_number
+= add
;
7371 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7372 i
.op
[n
].imms
, 0, reloc_type
);
7378 /* x86_cons_fix_new is called via the expression parsing code when a
7379 reloc is needed. We use this hook to get the correct .got reloc. */
7380 static int cons_sign
= -1;
7383 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7384 expressionS
*exp
, bfd_reloc_code_real_type r
)
7386 r
= reloc (len
, 0, cons_sign
, r
);
7389 if (exp
->X_op
== O_secrel
)
7391 exp
->X_op
= O_symbol
;
7392 r
= BFD_RELOC_32_SECREL
;
7396 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7399 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7400 purpose of the `.dc.a' internal pseudo-op. */
7403 x86_address_bytes (void)
7405 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7407 return stdoutput
->arch_info
->bits_per_address
/ 8;
7410 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7412 # define lex_got(reloc, adjust, types) NULL
7414 /* Parse operands of the form
7415 <symbol>@GOTOFF+<nnn>
7416 and similar .plt or .got references.
7418 If we find one, set up the correct relocation in RELOC and copy the
7419 input string, minus the `@GOTOFF' into a malloc'd buffer for
7420 parsing by the calling routine. Return this buffer, and if ADJUST
7421 is non-null set it to the length of the string we removed from the
7422 input line. Otherwise return NULL. */
7424 lex_got (enum bfd_reloc_code_real
*rel
,
7426 i386_operand_type
*types
)
7428 /* Some of the relocations depend on the size of what field is to
7429 be relocated. But in our callers i386_immediate and i386_displacement
7430 we don't yet know the operand size (this will be set by insn
7431 matching). Hence we record the word32 relocation here,
7432 and adjust the reloc according to the real size in reloc(). */
7433 static const struct {
7436 const enum bfd_reloc_code_real rel
[2];
7437 const i386_operand_type types64
;
7439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7440 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7442 OPERAND_TYPE_IMM32_64
},
7444 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7445 BFD_RELOC_X86_64_PLTOFF64
},
7446 OPERAND_TYPE_IMM64
},
7447 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7448 BFD_RELOC_X86_64_PLT32
},
7449 OPERAND_TYPE_IMM32_32S_DISP32
},
7450 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7451 BFD_RELOC_X86_64_GOTPLT64
},
7452 OPERAND_TYPE_IMM64_DISP64
},
7453 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7454 BFD_RELOC_X86_64_GOTOFF64
},
7455 OPERAND_TYPE_IMM64_DISP64
},
7456 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7457 BFD_RELOC_X86_64_GOTPCREL
},
7458 OPERAND_TYPE_IMM32_32S_DISP32
},
7459 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7460 BFD_RELOC_X86_64_TLSGD
},
7461 OPERAND_TYPE_IMM32_32S_DISP32
},
7462 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7463 _dummy_first_bfd_reloc_code_real
},
7464 OPERAND_TYPE_NONE
},
7465 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7466 BFD_RELOC_X86_64_TLSLD
},
7467 OPERAND_TYPE_IMM32_32S_DISP32
},
7468 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7469 BFD_RELOC_X86_64_GOTTPOFF
},
7470 OPERAND_TYPE_IMM32_32S_DISP32
},
7471 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7472 BFD_RELOC_X86_64_TPOFF32
},
7473 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7474 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7475 _dummy_first_bfd_reloc_code_real
},
7476 OPERAND_TYPE_NONE
},
7477 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7478 BFD_RELOC_X86_64_DTPOFF32
},
7479 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7480 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7481 _dummy_first_bfd_reloc_code_real
},
7482 OPERAND_TYPE_NONE
},
7483 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7484 _dummy_first_bfd_reloc_code_real
},
7485 OPERAND_TYPE_NONE
},
7486 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7487 BFD_RELOC_X86_64_GOT32
},
7488 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7489 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7490 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7491 OPERAND_TYPE_IMM32_32S_DISP32
},
7492 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7493 BFD_RELOC_X86_64_TLSDESC_CALL
},
7494 OPERAND_TYPE_IMM32_32S_DISP32
},
7499 #if defined (OBJ_MAYBE_ELF)
7504 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7505 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7508 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7510 int len
= gotrel
[j
].len
;
7511 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7513 if (gotrel
[j
].rel
[object_64bit
] != 0)
7516 char *tmpbuf
, *past_reloc
;
7518 *rel
= gotrel
[j
].rel
[object_64bit
];
7522 if (flag_code
!= CODE_64BIT
)
7524 types
->bitfield
.imm32
= 1;
7525 types
->bitfield
.disp32
= 1;
7528 *types
= gotrel
[j
].types64
;
7531 if (j
!= 0 && GOT_symbol
== NULL
)
7532 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7534 /* The length of the first part of our input line. */
7535 first
= cp
- input_line_pointer
;
7537 /* The second part goes from after the reloc token until
7538 (and including) an end_of_line char or comma. */
7539 past_reloc
= cp
+ 1 + len
;
7541 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7543 second
= cp
+ 1 - past_reloc
;
7545 /* Allocate and copy string. The trailing NUL shouldn't
7546 be necessary, but be safe. */
7547 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7548 memcpy (tmpbuf
, input_line_pointer
, first
);
7549 if (second
!= 0 && *past_reloc
!= ' ')
7550 /* Replace the relocation token with ' ', so that
7551 errors like foo@GOTOFF1 will be detected. */
7552 tmpbuf
[first
++] = ' ';
7554 /* Increment length by 1 if the relocation token is
7559 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7560 tmpbuf
[first
+ second
] = '\0';
7564 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7565 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7570 /* Might be a symbol version string. Don't as_bad here. */
7579 /* Parse operands of the form
7580 <symbol>@SECREL32+<nnn>
7582 If we find one, set up the correct relocation in RELOC and copy the
7583 input string, minus the `@SECREL32' into a malloc'd buffer for
7584 parsing by the calling routine. Return this buffer, and if ADJUST
7585 is non-null set it to the length of the string we removed from the
7586 input line. Otherwise return NULL.
7588 This function is copied from the ELF version above adjusted for PE targets. */
7591 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7592 int *adjust ATTRIBUTE_UNUSED
,
7593 i386_operand_type
*types
)
7599 const enum bfd_reloc_code_real rel
[2];
7600 const i386_operand_type types64
;
7604 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7605 BFD_RELOC_32_SECREL
},
7606 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7612 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7613 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7616 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7618 int len
= gotrel
[j
].len
;
7620 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7622 if (gotrel
[j
].rel
[object_64bit
] != 0)
7625 char *tmpbuf
, *past_reloc
;
7627 *rel
= gotrel
[j
].rel
[object_64bit
];
7633 if (flag_code
!= CODE_64BIT
)
7635 types
->bitfield
.imm32
= 1;
7636 types
->bitfield
.disp32
= 1;
7639 *types
= gotrel
[j
].types64
;
7642 /* The length of the first part of our input line. */
7643 first
= cp
- input_line_pointer
;
7645 /* The second part goes from after the reloc token until
7646 (and including) an end_of_line char or comma. */
7647 past_reloc
= cp
+ 1 + len
;
7649 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7651 second
= cp
+ 1 - past_reloc
;
7653 /* Allocate and copy string. The trailing NUL shouldn't
7654 be necessary, but be safe. */
7655 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7656 memcpy (tmpbuf
, input_line_pointer
, first
);
7657 if (second
!= 0 && *past_reloc
!= ' ')
7658 /* Replace the relocation token with ' ', so that
7659 errors like foo@SECLREL321 will be detected. */
7660 tmpbuf
[first
++] = ' ';
7661 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7662 tmpbuf
[first
+ second
] = '\0';
7666 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7667 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7672 /* Might be a symbol version string. Don't as_bad here. */
7678 bfd_reloc_code_real_type
7679 x86_cons (expressionS
*exp
, int size
)
7681 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7683 intel_syntax
= -intel_syntax
;
7686 if (size
== 4 || (object_64bit
&& size
== 8))
7688 /* Handle @GOTOFF and the like in an expression. */
7690 char *gotfree_input_line
;
7693 save
= input_line_pointer
;
7694 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7695 if (gotfree_input_line
)
7696 input_line_pointer
= gotfree_input_line
;
7700 if (gotfree_input_line
)
7702 /* expression () has merrily parsed up to the end of line,
7703 or a comma - in the wrong buffer. Transfer how far
7704 input_line_pointer has moved to the right buffer. */
7705 input_line_pointer
= (save
7706 + (input_line_pointer
- gotfree_input_line
)
7708 free (gotfree_input_line
);
7709 if (exp
->X_op
== O_constant
7710 || exp
->X_op
== O_absent
7711 || exp
->X_op
== O_illegal
7712 || exp
->X_op
== O_register
7713 || exp
->X_op
== O_big
)
7715 char c
= *input_line_pointer
;
7716 *input_line_pointer
= 0;
7717 as_bad (_("missing or invalid expression `%s'"), save
);
7718 *input_line_pointer
= c
;
7725 intel_syntax
= -intel_syntax
;
7728 i386_intel_simplify (exp
);
7734 signed_cons (int size
)
7736 if (flag_code
== CODE_64BIT
)
7744 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7751 if (exp
.X_op
== O_symbol
)
7752 exp
.X_op
= O_secrel
;
7754 emit_expr (&exp
, 4);
7756 while (*input_line_pointer
++ == ',');
7758 input_line_pointer
--;
7759 demand_empty_rest_of_line ();
7763 /* Handle Vector operations. */
7766 check_VecOperations (char *op_string
, char *op_end
)
7768 const reg_entry
*mask
;
7773 && (op_end
== NULL
|| op_string
< op_end
))
7776 if (*op_string
== '{')
7780 /* Check broadcasts. */
7781 if (strncmp (op_string
, "1to", 3) == 0)
7786 goto duplicated_vec_op
;
7789 if (*op_string
== '8')
7790 bcst_type
= BROADCAST_1TO8
;
7791 else if (*op_string
== '4')
7792 bcst_type
= BROADCAST_1TO4
;
7793 else if (*op_string
== '2')
7794 bcst_type
= BROADCAST_1TO2
;
7795 else if (*op_string
== '1'
7796 && *(op_string
+1) == '6')
7798 bcst_type
= BROADCAST_1TO16
;
7803 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7808 broadcast_op
.type
= bcst_type
;
7809 broadcast_op
.operand
= this_operand
;
7810 i
.broadcast
= &broadcast_op
;
7812 /* Check masking operation. */
7813 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7815 /* k0 can't be used for write mask. */
7816 if (mask
->reg_num
== 0)
7818 as_bad (_("`%s' can't be used for write mask"),
7825 mask_op
.mask
= mask
;
7826 mask_op
.zeroing
= 0;
7827 mask_op
.operand
= this_operand
;
7833 goto duplicated_vec_op
;
7835 i
.mask
->mask
= mask
;
7837 /* Only "{z}" is allowed here. No need to check
7838 zeroing mask explicitly. */
7839 if (i
.mask
->operand
!= this_operand
)
7841 as_bad (_("invalid write mask `%s'"), saved
);
7848 /* Check zeroing-flag for masking operation. */
7849 else if (*op_string
== 'z')
7853 mask_op
.mask
= NULL
;
7854 mask_op
.zeroing
= 1;
7855 mask_op
.operand
= this_operand
;
7860 if (i
.mask
->zeroing
)
7863 as_bad (_("duplicated `%s'"), saved
);
7867 i
.mask
->zeroing
= 1;
7869 /* Only "{%k}" is allowed here. No need to check mask
7870 register explicitly. */
7871 if (i
.mask
->operand
!= this_operand
)
7873 as_bad (_("invalid zeroing-masking `%s'"),
7882 goto unknown_vec_op
;
7884 if (*op_string
!= '}')
7886 as_bad (_("missing `}' in `%s'"), saved
);
7893 /* We don't know this one. */
7894 as_bad (_("unknown vector operation: `%s'"), saved
);
7902 i386_immediate (char *imm_start
)
7904 char *save_input_line_pointer
;
7905 char *gotfree_input_line
;
7908 i386_operand_type types
;
7910 operand_type_set (&types
, ~0);
7912 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7914 as_bad (_("at most %d immediate operands are allowed"),
7915 MAX_IMMEDIATE_OPERANDS
);
7919 exp
= &im_expressions
[i
.imm_operands
++];
7920 i
.op
[this_operand
].imms
= exp
;
7922 if (is_space_char (*imm_start
))
7925 save_input_line_pointer
= input_line_pointer
;
7926 input_line_pointer
= imm_start
;
7928 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7929 if (gotfree_input_line
)
7930 input_line_pointer
= gotfree_input_line
;
7932 exp_seg
= expression (exp
);
7936 /* Handle vector operations. */
7937 if (*input_line_pointer
== '{')
7939 input_line_pointer
= check_VecOperations (input_line_pointer
,
7941 if (input_line_pointer
== NULL
)
7945 if (*input_line_pointer
)
7946 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7948 input_line_pointer
= save_input_line_pointer
;
7949 if (gotfree_input_line
)
7951 free (gotfree_input_line
);
7953 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7954 exp
->X_op
= O_illegal
;
7957 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7961 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7962 i386_operand_type types
, const char *imm_start
)
7964 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7967 as_bad (_("missing or invalid immediate expression `%s'"),
7971 else if (exp
->X_op
== O_constant
)
7973 /* Size it properly later. */
7974 i
.types
[this_operand
].bitfield
.imm64
= 1;
7975 /* If not 64bit, sign extend val. */
7976 if (flag_code
!= CODE_64BIT
7977 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7979 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7981 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7982 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7983 && exp_seg
!= absolute_section
7984 && exp_seg
!= text_section
7985 && exp_seg
!= data_section
7986 && exp_seg
!= bss_section
7987 && exp_seg
!= undefined_section
7988 && !bfd_is_com_section (exp_seg
))
7990 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7994 else if (!intel_syntax
&& exp_seg
== reg_section
)
7997 as_bad (_("illegal immediate register operand %s"), imm_start
);
8002 /* This is an address. The size of the address will be
8003 determined later, depending on destination register,
8004 suffix, or the default for the section. */
8005 i
.types
[this_operand
].bitfield
.imm8
= 1;
8006 i
.types
[this_operand
].bitfield
.imm16
= 1;
8007 i
.types
[this_operand
].bitfield
.imm32
= 1;
8008 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8009 i
.types
[this_operand
].bitfield
.imm64
= 1;
8010 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8018 i386_scale (char *scale
)
8021 char *save
= input_line_pointer
;
8023 input_line_pointer
= scale
;
8024 val
= get_absolute_expression ();
8029 i
.log2_scale_factor
= 0;
8032 i
.log2_scale_factor
= 1;
8035 i
.log2_scale_factor
= 2;
8038 i
.log2_scale_factor
= 3;
8042 char sep
= *input_line_pointer
;
8044 *input_line_pointer
= '\0';
8045 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8047 *input_line_pointer
= sep
;
8048 input_line_pointer
= save
;
8052 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8054 as_warn (_("scale factor of %d without an index register"),
8055 1 << i
.log2_scale_factor
);
8056 i
.log2_scale_factor
= 0;
8058 scale
= input_line_pointer
;
8059 input_line_pointer
= save
;
8064 i386_displacement (char *disp_start
, char *disp_end
)
8068 char *save_input_line_pointer
;
8069 char *gotfree_input_line
;
8071 i386_operand_type bigdisp
, types
= anydisp
;
8074 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8076 as_bad (_("at most %d displacement operands are allowed"),
8077 MAX_MEMORY_OPERANDS
);
8081 operand_type_set (&bigdisp
, 0);
8082 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8083 || (!current_templates
->start
->opcode_modifier
.jump
8084 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8086 bigdisp
.bitfield
.disp32
= 1;
8087 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8088 if (flag_code
== CODE_64BIT
)
8092 bigdisp
.bitfield
.disp32s
= 1;
8093 bigdisp
.bitfield
.disp64
= 1;
8096 else if ((flag_code
== CODE_16BIT
) ^ override
)
8098 bigdisp
.bitfield
.disp32
= 0;
8099 bigdisp
.bitfield
.disp16
= 1;
8104 /* For PC-relative branches, the width of the displacement
8105 is dependent upon data size, not address size. */
8106 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8107 if (flag_code
== CODE_64BIT
)
8109 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8110 bigdisp
.bitfield
.disp16
= 1;
8113 bigdisp
.bitfield
.disp32
= 1;
8114 bigdisp
.bitfield
.disp32s
= 1;
8120 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8122 : LONG_MNEM_SUFFIX
));
8123 bigdisp
.bitfield
.disp32
= 1;
8124 if ((flag_code
== CODE_16BIT
) ^ override
)
8126 bigdisp
.bitfield
.disp32
= 0;
8127 bigdisp
.bitfield
.disp16
= 1;
8131 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8134 exp
= &disp_expressions
[i
.disp_operands
];
8135 i
.op
[this_operand
].disps
= exp
;
8137 save_input_line_pointer
= input_line_pointer
;
8138 input_line_pointer
= disp_start
;
8139 END_STRING_AND_SAVE (disp_end
);
8141 #ifndef GCC_ASM_O_HACK
8142 #define GCC_ASM_O_HACK 0
8145 END_STRING_AND_SAVE (disp_end
+ 1);
8146 if (i
.types
[this_operand
].bitfield
.baseIndex
8147 && displacement_string_end
[-1] == '+')
8149 /* This hack is to avoid a warning when using the "o"
8150 constraint within gcc asm statements.
8153 #define _set_tssldt_desc(n,addr,limit,type) \
8154 __asm__ __volatile__ ( \
8156 "movw %w1,2+%0\n\t" \
8158 "movb %b1,4+%0\n\t" \
8159 "movb %4,5+%0\n\t" \
8160 "movb $0,6+%0\n\t" \
8161 "movb %h1,7+%0\n\t" \
8163 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8165 This works great except that the output assembler ends
8166 up looking a bit weird if it turns out that there is
8167 no offset. You end up producing code that looks like:
8180 So here we provide the missing zero. */
8182 *displacement_string_end
= '0';
8185 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8186 if (gotfree_input_line
)
8187 input_line_pointer
= gotfree_input_line
;
8189 exp_seg
= expression (exp
);
8192 if (*input_line_pointer
)
8193 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8195 RESTORE_END_STRING (disp_end
+ 1);
8197 input_line_pointer
= save_input_line_pointer
;
8198 if (gotfree_input_line
)
8200 free (gotfree_input_line
);
8202 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8203 exp
->X_op
= O_illegal
;
8206 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8208 RESTORE_END_STRING (disp_end
);
8214 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8215 i386_operand_type types
, const char *disp_start
)
8217 i386_operand_type bigdisp
;
8220 /* We do this to make sure that the section symbol is in
8221 the symbol table. We will ultimately change the relocation
8222 to be relative to the beginning of the section. */
8223 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8224 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8225 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8227 if (exp
->X_op
!= O_symbol
)
8230 if (S_IS_LOCAL (exp
->X_add_symbol
)
8231 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8232 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8233 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8234 exp
->X_op
= O_subtract
;
8235 exp
->X_op_symbol
= GOT_symbol
;
8236 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8237 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8238 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8239 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8241 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8244 else if (exp
->X_op
== O_absent
8245 || exp
->X_op
== O_illegal
8246 || exp
->X_op
== O_big
)
8249 as_bad (_("missing or invalid displacement expression `%s'"),
8254 else if (flag_code
== CODE_64BIT
8255 && !i
.prefix
[ADDR_PREFIX
]
8256 && exp
->X_op
== O_constant
)
8258 /* Since displacement is signed extended to 64bit, don't allow
8259 disp32 and turn off disp32s if they are out of range. */
8260 i
.types
[this_operand
].bitfield
.disp32
= 0;
8261 if (!fits_in_signed_long (exp
->X_add_number
))
8263 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8264 if (i
.types
[this_operand
].bitfield
.baseindex
)
8266 as_bad (_("0x%lx out range of signed 32bit displacement"),
8267 (long) exp
->X_add_number
);
8273 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8274 else if (exp
->X_op
!= O_constant
8275 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8276 && exp_seg
!= absolute_section
8277 && exp_seg
!= text_section
8278 && exp_seg
!= data_section
8279 && exp_seg
!= bss_section
8280 && exp_seg
!= undefined_section
8281 && !bfd_is_com_section (exp_seg
))
8283 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8288 /* Check if this is a displacement only operand. */
8289 bigdisp
= i
.types
[this_operand
];
8290 bigdisp
.bitfield
.disp8
= 0;
8291 bigdisp
.bitfield
.disp16
= 0;
8292 bigdisp
.bitfield
.disp32
= 0;
8293 bigdisp
.bitfield
.disp32s
= 0;
8294 bigdisp
.bitfield
.disp64
= 0;
8295 if (operand_type_all_zero (&bigdisp
))
8296 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8302 /* Make sure the memory operand we've been dealt is valid.
8303 Return 1 on success, 0 on a failure. */
8306 i386_index_check (const char *operand_string
)
8308 const char *kind
= "base/index";
8309 enum flag_code addr_mode
;
8311 if (i
.prefix
[ADDR_PREFIX
])
8312 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8315 addr_mode
= flag_code
;
8317 #if INFER_ADDR_PREFIX
8318 if (i
.mem_operands
== 0)
8320 /* Infer address prefix from the first memory operand. */
8321 const reg_entry
*addr_reg
= i
.base_reg
;
8323 if (addr_reg
== NULL
)
8324 addr_reg
= i
.index_reg
;
8328 if (addr_reg
->reg_num
== RegEip
8329 || addr_reg
->reg_num
== RegEiz
8330 || addr_reg
->reg_type
.bitfield
.reg32
)
8331 addr_mode
= CODE_32BIT
;
8332 else if (flag_code
!= CODE_64BIT
8333 && addr_reg
->reg_type
.bitfield
.reg16
)
8334 addr_mode
= CODE_16BIT
;
8336 if (addr_mode
!= flag_code
)
8338 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8340 /* Change the size of any displacement too. At most one
8341 of Disp16 or Disp32 is set.
8342 FIXME. There doesn't seem to be any real need for
8343 separate Disp16 and Disp32 flags. The same goes for
8344 Imm16 and Imm32. Removing them would probably clean
8345 up the code quite a lot. */
8346 if (flag_code
!= CODE_64BIT
8347 && (i
.types
[this_operand
].bitfield
.disp16
8348 || i
.types
[this_operand
].bitfield
.disp32
))
8349 i
.types
[this_operand
]
8350 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8357 if (current_templates
->start
->opcode_modifier
.isstring
8358 && !current_templates
->start
->opcode_modifier
.immext
8359 && (current_templates
->end
[-1].opcode_modifier
.isstring
8362 /* Memory operands of string insns are special in that they only allow
8363 a single register (rDI, rSI, or rBX) as their memory address. */
8364 const reg_entry
*expected_reg
;
8365 static const char *di_si
[][2] =
8371 static const char *bx
[] = { "ebx", "bx", "rbx" };
8373 kind
= "string address";
8375 if (current_templates
->start
->opcode_modifier
.w
)
8377 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8379 if (!type
.bitfield
.baseindex
8380 || ((!i
.mem_operands
!= !intel_syntax
)
8381 && current_templates
->end
[-1].operand_types
[1]
8382 .bitfield
.baseindex
))
8383 type
= current_templates
->end
[-1].operand_types
[1];
8384 expected_reg
= hash_find (reg_hash
,
8385 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8389 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8391 if (i
.base_reg
!= expected_reg
8393 || operand_type_check (i
.types
[this_operand
], disp
))
8395 /* The second memory operand must have the same size as
8399 && !((addr_mode
== CODE_64BIT
8400 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8401 || (addr_mode
== CODE_32BIT
8402 ? i
.base_reg
->reg_type
.bitfield
.reg32
8403 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8406 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8408 intel_syntax
? '[' : '(',
8410 expected_reg
->reg_name
,
8411 intel_syntax
? ']' : ')');
8418 as_bad (_("`%s' is not a valid %s expression"),
8419 operand_string
, kind
);
8424 if (addr_mode
!= CODE_16BIT
)
8426 /* 32-bit/64-bit checks. */
8428 && (addr_mode
== CODE_64BIT
8429 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8430 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8432 || (i
.base_reg
->reg_num
8433 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8435 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8436 && !i
.index_reg
->reg_type
.bitfield
.regymm
8437 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8438 && ((addr_mode
== CODE_64BIT
8439 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8440 || i
.index_reg
->reg_num
== RegRiz
)
8441 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8442 || i
.index_reg
->reg_num
== RegEiz
))
8443 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8448 /* 16-bit checks. */
8450 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8451 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8453 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8454 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8456 && i
.base_reg
->reg_num
< 6
8457 && i
.index_reg
->reg_num
>= 6
8458 && i
.log2_scale_factor
== 0))))
8465 /* Handle vector immediates. */
8468 RC_SAE_immediate (const char *imm_start
)
8470 unsigned int match_found
, j
;
8471 const char *pstr
= imm_start
;
8479 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8481 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8485 rc_op
.type
= RC_NamesTable
[j
].type
;
8486 rc_op
.operand
= this_operand
;
8487 i
.rounding
= &rc_op
;
8491 as_bad (_("duplicated `%s'"), imm_start
);
8494 pstr
+= RC_NamesTable
[j
].len
;
8504 as_bad (_("Missing '}': '%s'"), imm_start
);
8507 /* RC/SAE immediate string should contain nothing more. */;
8510 as_bad (_("Junk after '}': '%s'"), imm_start
);
8514 exp
= &im_expressions
[i
.imm_operands
++];
8515 i
.op
[this_operand
].imms
= exp
;
8517 exp
->X_op
= O_constant
;
8518 exp
->X_add_number
= 0;
8519 exp
->X_add_symbol
= (symbolS
*) 0;
8520 exp
->X_op_symbol
= (symbolS
*) 0;
8522 i
.types
[this_operand
].bitfield
.imm8
= 1;
8526 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8530 i386_att_operand (char *operand_string
)
8534 char *op_string
= operand_string
;
8536 if (is_space_char (*op_string
))
8539 /* We check for an absolute prefix (differentiating,
8540 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8541 if (*op_string
== ABSOLUTE_PREFIX
)
8544 if (is_space_char (*op_string
))
8546 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8549 /* Check if operand is a register. */
8550 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8552 i386_operand_type temp
;
8554 /* Check for a segment override by searching for ':' after a
8555 segment register. */
8557 if (is_space_char (*op_string
))
8559 if (*op_string
== ':'
8560 && (r
->reg_type
.bitfield
.sreg2
8561 || r
->reg_type
.bitfield
.sreg3
))
8566 i
.seg
[i
.mem_operands
] = &es
;
8569 i
.seg
[i
.mem_operands
] = &cs
;
8572 i
.seg
[i
.mem_operands
] = &ss
;
8575 i
.seg
[i
.mem_operands
] = &ds
;
8578 i
.seg
[i
.mem_operands
] = &fs
;
8581 i
.seg
[i
.mem_operands
] = &gs
;
8585 /* Skip the ':' and whitespace. */
8587 if (is_space_char (*op_string
))
8590 if (!is_digit_char (*op_string
)
8591 && !is_identifier_char (*op_string
)
8592 && *op_string
!= '('
8593 && *op_string
!= ABSOLUTE_PREFIX
)
8595 as_bad (_("bad memory operand `%s'"), op_string
);
8598 /* Handle case of %es:*foo. */
8599 if (*op_string
== ABSOLUTE_PREFIX
)
8602 if (is_space_char (*op_string
))
8604 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8606 goto do_memory_reference
;
8609 /* Handle vector operations. */
8610 if (*op_string
== '{')
8612 op_string
= check_VecOperations (op_string
, NULL
);
8613 if (op_string
== NULL
)
8619 as_bad (_("junk `%s' after register"), op_string
);
8623 temp
.bitfield
.baseindex
= 0;
8624 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8626 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8627 i
.op
[this_operand
].regs
= r
;
8630 else if (*op_string
== REGISTER_PREFIX
)
8632 as_bad (_("bad register name `%s'"), op_string
);
8635 else if (*op_string
== IMMEDIATE_PREFIX
)
8638 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8640 as_bad (_("immediate operand illegal with absolute jump"));
8643 if (!i386_immediate (op_string
))
8646 else if (RC_SAE_immediate (operand_string
))
8648 /* If it is a RC or SAE immediate, do nothing. */
8651 else if (is_digit_char (*op_string
)
8652 || is_identifier_char (*op_string
)
8653 || *op_string
== '(')
8655 /* This is a memory reference of some sort. */
8658 /* Start and end of displacement string expression (if found). */
8659 char *displacement_string_start
;
8660 char *displacement_string_end
;
8663 do_memory_reference
:
8664 if ((i
.mem_operands
== 1
8665 && !current_templates
->start
->opcode_modifier
.isstring
)
8666 || i
.mem_operands
== 2)
8668 as_bad (_("too many memory references for `%s'"),
8669 current_templates
->start
->name
);
8673 /* Check for base index form. We detect the base index form by
8674 looking for an ')' at the end of the operand, searching
8675 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8677 base_string
= op_string
+ strlen (op_string
);
8679 /* Handle vector operations. */
8680 vop_start
= strchr (op_string
, '{');
8681 if (vop_start
&& vop_start
< base_string
)
8683 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8685 base_string
= vop_start
;
8689 if (is_space_char (*base_string
))
8692 /* If we only have a displacement, set-up for it to be parsed later. */
8693 displacement_string_start
= op_string
;
8694 displacement_string_end
= base_string
+ 1;
8696 if (*base_string
== ')')
8699 unsigned int parens_balanced
= 1;
8700 /* We've already checked that the number of left & right ()'s are
8701 equal, so this loop will not be infinite. */
8705 if (*base_string
== ')')
8707 if (*base_string
== '(')
8710 while (parens_balanced
);
8712 temp_string
= base_string
;
8714 /* Skip past '(' and whitespace. */
8716 if (is_space_char (*base_string
))
8719 if (*base_string
== ','
8720 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8723 displacement_string_end
= temp_string
;
8725 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8729 base_string
= end_op
;
8730 if (is_space_char (*base_string
))
8734 /* There may be an index reg or scale factor here. */
8735 if (*base_string
== ',')
8738 if (is_space_char (*base_string
))
8741 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8744 base_string
= end_op
;
8745 if (is_space_char (*base_string
))
8747 if (*base_string
== ',')
8750 if (is_space_char (*base_string
))
8753 else if (*base_string
!= ')')
8755 as_bad (_("expecting `,' or `)' "
8756 "after index register in `%s'"),
8761 else if (*base_string
== REGISTER_PREFIX
)
8763 end_op
= strchr (base_string
, ',');
8766 as_bad (_("bad register name `%s'"), base_string
);
8770 /* Check for scale factor. */
8771 if (*base_string
!= ')')
8773 char *end_scale
= i386_scale (base_string
);
8778 base_string
= end_scale
;
8779 if (is_space_char (*base_string
))
8781 if (*base_string
!= ')')
8783 as_bad (_("expecting `)' "
8784 "after scale factor in `%s'"),
8789 else if (!i
.index_reg
)
8791 as_bad (_("expecting index register or scale factor "
8792 "after `,'; got '%c'"),
8797 else if (*base_string
!= ')')
8799 as_bad (_("expecting `,' or `)' "
8800 "after base register in `%s'"),
8805 else if (*base_string
== REGISTER_PREFIX
)
8807 end_op
= strchr (base_string
, ',');
8810 as_bad (_("bad register name `%s'"), base_string
);
8815 /* If there's an expression beginning the operand, parse it,
8816 assuming displacement_string_start and
8817 displacement_string_end are meaningful. */
8818 if (displacement_string_start
!= displacement_string_end
)
8820 if (!i386_displacement (displacement_string_start
,
8821 displacement_string_end
))
8825 /* Special case for (%dx) while doing input/output op. */
8827 && operand_type_equal (&i
.base_reg
->reg_type
,
8828 ®16_inoutportreg
)
8830 && i
.log2_scale_factor
== 0
8831 && i
.seg
[i
.mem_operands
] == 0
8832 && !operand_type_check (i
.types
[this_operand
], disp
))
8834 i
.types
[this_operand
] = inoutportreg
;
8838 if (i386_index_check (operand_string
) == 0)
8840 i
.types
[this_operand
].bitfield
.mem
= 1;
8845 /* It's not a memory operand; argh! */
8846 as_bad (_("invalid char %s beginning operand %d `%s'"),
8847 output_invalid (*op_string
),
8852 return 1; /* Normal return. */
8855 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8856 that an rs_machine_dependent frag may reach. */
8859 i386_frag_max_var (fragS
*frag
)
8861 /* The only relaxable frags are for jumps.
8862 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8863 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8864 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8867 /* md_estimate_size_before_relax()
8869 Called just before relax() for rs_machine_dependent frags. The x86
8870 assembler uses these frags to handle variable size jump
8873 Any symbol that is now undefined will not become defined.
8874 Return the correct fr_subtype in the frag.
8875 Return the initial "guess for variable size of frag" to caller.
8876 The guess is actually the growth beyond the fixed part. Whatever
8877 we do to grow the fixed or variable part contributes to our
8881 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8883 /* We've already got fragP->fr_subtype right; all we have to do is
8884 check for un-relaxable symbols. On an ELF system, we can't relax
8885 an externally visible symbol, because it may be overridden by a
8887 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8890 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8891 || S_IS_WEAK (fragP
->fr_symbol
)
8892 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8893 & BSF_GNU_INDIRECT_FUNCTION
))))
8895 #if defined (OBJ_COFF) && defined (TE_PE)
8896 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8897 && S_IS_WEAK (fragP
->fr_symbol
))
8901 /* Symbol is undefined in this segment, or we need to keep a
8902 reloc so that weak symbols can be overridden. */
8903 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8904 enum bfd_reloc_code_real reloc_type
;
8905 unsigned char *opcode
;
8908 if (fragP
->fr_var
!= NO_RELOC
)
8909 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8911 reloc_type
= BFD_RELOC_16_PCREL
;
8913 reloc_type
= BFD_RELOC_32_PCREL
;
8915 old_fr_fix
= fragP
->fr_fix
;
8916 opcode
= (unsigned char *) fragP
->fr_opcode
;
8918 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8921 /* Make jmp (0xeb) a (d)word displacement jump. */
8923 fragP
->fr_fix
+= size
;
8924 fix_new (fragP
, old_fr_fix
, size
,
8926 fragP
->fr_offset
, 1,
8932 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8934 /* Negate the condition, and branch past an
8935 unconditional jump. */
8938 /* Insert an unconditional jump. */
8940 /* We added two extra opcode bytes, and have a two byte
8942 fragP
->fr_fix
+= 2 + 2;
8943 fix_new (fragP
, old_fr_fix
+ 2, 2,
8945 fragP
->fr_offset
, 1,
8952 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8957 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8959 fragP
->fr_offset
, 1,
8961 fixP
->fx_signed
= 1;
8965 /* This changes the byte-displacement jump 0x7N
8966 to the (d)word-displacement jump 0x0f,0x8N. */
8967 opcode
[1] = opcode
[0] + 0x10;
8968 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8969 /* We've added an opcode byte. */
8970 fragP
->fr_fix
+= 1 + size
;
8971 fix_new (fragP
, old_fr_fix
+ 1, size
,
8973 fragP
->fr_offset
, 1,
8978 BAD_CASE (fragP
->fr_subtype
);
8982 return fragP
->fr_fix
- old_fr_fix
;
8985 /* Guess size depending on current relax state. Initially the relax
8986 state will correspond to a short jump and we return 1, because
8987 the variable part of the frag (the branch offset) is one byte
8988 long. However, we can relax a section more than once and in that
8989 case we must either set fr_subtype back to the unrelaxed state,
8990 or return the value for the appropriate branch. */
8991 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8994 /* Called after relax() is finished.
8996 In: Address of frag.
8997 fr_type == rs_machine_dependent.
8998 fr_subtype is what the address relaxed to.
9000 Out: Any fixSs and constants are set up.
9001 Caller will turn frag into a ".space 0". */
9004 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9007 unsigned char *opcode
;
9008 unsigned char *where_to_put_displacement
= NULL
;
9009 offsetT target_address
;
9010 offsetT opcode_address
;
9011 unsigned int extension
= 0;
9012 offsetT displacement_from_opcode_start
;
9014 opcode
= (unsigned char *) fragP
->fr_opcode
;
9016 /* Address we want to reach in file space. */
9017 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9019 /* Address opcode resides at in file space. */
9020 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9022 /* Displacement from opcode start to fill into instruction. */
9023 displacement_from_opcode_start
= target_address
- opcode_address
;
9025 if ((fragP
->fr_subtype
& BIG
) == 0)
9027 /* Don't have to change opcode. */
9028 extension
= 1; /* 1 opcode + 1 displacement */
9029 where_to_put_displacement
= &opcode
[1];
9033 if (no_cond_jump_promotion
9034 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9035 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9036 _("long jump required"));
9038 switch (fragP
->fr_subtype
)
9040 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9041 extension
= 4; /* 1 opcode + 4 displacement */
9043 where_to_put_displacement
= &opcode
[1];
9046 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9047 extension
= 2; /* 1 opcode + 2 displacement */
9049 where_to_put_displacement
= &opcode
[1];
9052 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9053 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9054 extension
= 5; /* 2 opcode + 4 displacement */
9055 opcode
[1] = opcode
[0] + 0x10;
9056 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9057 where_to_put_displacement
= &opcode
[2];
9060 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9061 extension
= 3; /* 2 opcode + 2 displacement */
9062 opcode
[1] = opcode
[0] + 0x10;
9063 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9064 where_to_put_displacement
= &opcode
[2];
9067 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9072 where_to_put_displacement
= &opcode
[3];
9076 BAD_CASE (fragP
->fr_subtype
);
9081 /* If size if less then four we are sure that the operand fits,
9082 but if it's 4, then it could be that the displacement is larger
9084 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9086 && ((addressT
) (displacement_from_opcode_start
- extension
9087 + ((addressT
) 1 << 31))
9088 > (((addressT
) 2 << 31) - 1)))
9090 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9091 _("jump target out of range"));
9092 /* Make us emit 0. */
9093 displacement_from_opcode_start
= extension
;
9095 /* Now put displacement after opcode. */
9096 md_number_to_chars ((char *) where_to_put_displacement
,
9097 (valueT
) (displacement_from_opcode_start
- extension
),
9098 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9099 fragP
->fr_fix
+= extension
;
9102 /* Apply a fixup (fixP) to segment data, once it has been determined
9103 by our caller that we have all the info we need to fix it up.
9105 Parameter valP is the pointer to the value of the bits.
9107 On the 386, immediates, displacements, and data pointers are all in
9108 the same (little-endian) format, so we don't need to care about which
9112 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9114 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9115 valueT value
= *valP
;
9117 #if !defined (TE_Mach)
9120 switch (fixP
->fx_r_type
)
9126 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9129 case BFD_RELOC_X86_64_32S
:
9130 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9133 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9136 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9141 if (fixP
->fx_addsy
!= NULL
9142 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9143 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9144 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9145 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9146 && !use_rela_relocations
)
9148 /* This is a hack. There should be a better way to handle this.
9149 This covers for the fact that bfd_install_relocation will
9150 subtract the current location (for partial_inplace, PC relative
9151 relocations); see more below. */
9155 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9158 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9163 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9166 || (symbol_section_p (fixP
->fx_addsy
)
9167 && sym_seg
!= absolute_section
))
9168 && !generic_force_reloc (fixP
))
9170 /* Yes, we add the values in twice. This is because
9171 bfd_install_relocation subtracts them out again. I think
9172 bfd_install_relocation is broken, but I don't dare change
9174 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9178 #if defined (OBJ_COFF) && defined (TE_PE)
9179 /* For some reason, the PE format does not store a
9180 section address offset for a PC relative symbol. */
9181 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9182 || S_IS_WEAK (fixP
->fx_addsy
))
9183 value
+= md_pcrel_from (fixP
);
9186 #if defined (OBJ_COFF) && defined (TE_PE)
9187 if (fixP
->fx_addsy
!= NULL
9188 && S_IS_WEAK (fixP
->fx_addsy
)
9189 /* PR 16858: Do not modify weak function references. */
9190 && ! fixP
->fx_pcrel
)
9192 #if !defined (TE_PEP)
9193 /* For x86 PE weak function symbols are neither PC-relative
9194 nor do they set S_IS_FUNCTION. So the only reliable way
9195 to detect them is to check the flags of their containing
9197 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9198 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9202 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9206 /* Fix a few things - the dynamic linker expects certain values here,
9207 and we must not disappoint it. */
9208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9209 if (IS_ELF
&& fixP
->fx_addsy
)
9210 switch (fixP
->fx_r_type
)
9212 case BFD_RELOC_386_PLT32
:
9213 case BFD_RELOC_X86_64_PLT32
:
9214 /* Make the jump instruction point to the address of the operand. At
9215 runtime we merely add the offset to the actual PLT entry. */
9219 case BFD_RELOC_386_TLS_GD
:
9220 case BFD_RELOC_386_TLS_LDM
:
9221 case BFD_RELOC_386_TLS_IE_32
:
9222 case BFD_RELOC_386_TLS_IE
:
9223 case BFD_RELOC_386_TLS_GOTIE
:
9224 case BFD_RELOC_386_TLS_GOTDESC
:
9225 case BFD_RELOC_X86_64_TLSGD
:
9226 case BFD_RELOC_X86_64_TLSLD
:
9227 case BFD_RELOC_X86_64_GOTTPOFF
:
9228 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9229 value
= 0; /* Fully resolved at runtime. No addend. */
9231 case BFD_RELOC_386_TLS_LE
:
9232 case BFD_RELOC_386_TLS_LDO_32
:
9233 case BFD_RELOC_386_TLS_LE_32
:
9234 case BFD_RELOC_X86_64_DTPOFF32
:
9235 case BFD_RELOC_X86_64_DTPOFF64
:
9236 case BFD_RELOC_X86_64_TPOFF32
:
9237 case BFD_RELOC_X86_64_TPOFF64
:
9238 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9241 case BFD_RELOC_386_TLS_DESC_CALL
:
9242 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9243 value
= 0; /* Fully resolved at runtime. No addend. */
9244 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9248 case BFD_RELOC_386_GOT32
:
9249 case BFD_RELOC_X86_64_GOT32
:
9250 value
= 0; /* Fully resolved at runtime. No addend. */
9253 case BFD_RELOC_VTABLE_INHERIT
:
9254 case BFD_RELOC_VTABLE_ENTRY
:
9261 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9263 #endif /* !defined (TE_Mach) */
9265 /* Are we finished with this relocation now? */
9266 if (fixP
->fx_addsy
== NULL
)
9268 #if defined (OBJ_COFF) && defined (TE_PE)
9269 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9272 /* Remember value for tc_gen_reloc. */
9273 fixP
->fx_addnumber
= value
;
9274 /* Clear out the frag for now. */
9278 else if (use_rela_relocations
)
9280 fixP
->fx_no_overflow
= 1;
9281 /* Remember value for tc_gen_reloc. */
9282 fixP
->fx_addnumber
= value
;
9286 md_number_to_chars (p
, value
, fixP
->fx_size
);
9290 md_atof (int type
, char *litP
, int *sizeP
)
9292 /* This outputs the LITTLENUMs in REVERSE order;
9293 in accord with the bigendian 386. */
9294 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9297 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9300 output_invalid (int c
)
9303 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9306 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9307 "(0x%x)", (unsigned char) c
);
9308 return output_invalid_buf
;
9311 /* REG_STRING starts *before* REGISTER_PREFIX. */
9313 static const reg_entry
*
9314 parse_real_register (char *reg_string
, char **end_op
)
9316 char *s
= reg_string
;
9318 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9321 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9322 if (*s
== REGISTER_PREFIX
)
9325 if (is_space_char (*s
))
9329 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9331 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9332 return (const reg_entry
*) NULL
;
9336 /* For naked regs, make sure that we are not dealing with an identifier.
9337 This prevents confusing an identifier like `eax_var' with register
9339 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9340 return (const reg_entry
*) NULL
;
9344 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9346 /* Handle floating point regs, allowing spaces in the (i) part. */
9347 if (r
== i386_regtab
/* %st is first entry of table */)
9349 if (is_space_char (*s
))
9354 if (is_space_char (*s
))
9356 if (*s
>= '0' && *s
<= '7')
9360 if (is_space_char (*s
))
9365 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9370 /* We have "%st(" then garbage. */
9371 return (const reg_entry
*) NULL
;
9375 if (r
== NULL
|| allow_pseudo_reg
)
9378 if (operand_type_all_zero (&r
->reg_type
))
9379 return (const reg_entry
*) NULL
;
9381 if ((r
->reg_type
.bitfield
.reg32
9382 || r
->reg_type
.bitfield
.sreg3
9383 || r
->reg_type
.bitfield
.control
9384 || r
->reg_type
.bitfield
.debug
9385 || r
->reg_type
.bitfield
.test
)
9386 && !cpu_arch_flags
.bitfield
.cpui386
)
9387 return (const reg_entry
*) NULL
;
9389 if (r
->reg_type
.bitfield
.floatreg
9390 && !cpu_arch_flags
.bitfield
.cpu8087
9391 && !cpu_arch_flags
.bitfield
.cpu287
9392 && !cpu_arch_flags
.bitfield
.cpu387
)
9393 return (const reg_entry
*) NULL
;
9395 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9396 return (const reg_entry
*) NULL
;
9398 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9399 return (const reg_entry
*) NULL
;
9401 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9402 return (const reg_entry
*) NULL
;
9404 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9405 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9406 return (const reg_entry
*) NULL
;
9408 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9409 if (!allow_index_reg
9410 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9411 return (const reg_entry
*) NULL
;
9413 /* Upper 16 vector register is only available with VREX in 64bit
9415 if ((r
->reg_flags
& RegVRex
))
9417 if (!cpu_arch_flags
.bitfield
.cpuvrex
9418 || flag_code
!= CODE_64BIT
)
9419 return (const reg_entry
*) NULL
;
9424 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9425 || r
->reg_type
.bitfield
.reg64
)
9426 && (!cpu_arch_flags
.bitfield
.cpulm
9427 || !operand_type_equal (&r
->reg_type
, &control
))
9428 && flag_code
!= CODE_64BIT
)
9429 return (const reg_entry
*) NULL
;
9431 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9432 return (const reg_entry
*) NULL
;
9437 /* REG_STRING starts *before* REGISTER_PREFIX. */
9439 static const reg_entry
*
9440 parse_register (char *reg_string
, char **end_op
)
9444 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9445 r
= parse_real_register (reg_string
, end_op
);
9450 char *save
= input_line_pointer
;
9454 input_line_pointer
= reg_string
;
9455 c
= get_symbol_end ();
9456 symbolP
= symbol_find (reg_string
);
9457 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9459 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9461 know (e
->X_op
== O_register
);
9462 know (e
->X_add_number
>= 0
9463 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9464 r
= i386_regtab
+ e
->X_add_number
;
9465 if ((r
->reg_flags
& RegVRex
))
9467 *end_op
= input_line_pointer
;
9469 *input_line_pointer
= c
;
9470 input_line_pointer
= save
;
9476 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9479 char *end
= input_line_pointer
;
9482 r
= parse_register (name
, &input_line_pointer
);
9483 if (r
&& end
<= input_line_pointer
)
9485 *nextcharP
= *input_line_pointer
;
9486 *input_line_pointer
= 0;
9487 e
->X_op
= O_register
;
9488 e
->X_add_number
= r
- i386_regtab
;
9491 input_line_pointer
= end
;
9493 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9497 md_operand (expressionS
*e
)
9502 switch (*input_line_pointer
)
9504 case REGISTER_PREFIX
:
9505 r
= parse_real_register (input_line_pointer
, &end
);
9508 e
->X_op
= O_register
;
9509 e
->X_add_number
= r
- i386_regtab
;
9510 input_line_pointer
= end
;
9515 gas_assert (intel_syntax
);
9516 end
= input_line_pointer
++;
9518 if (*input_line_pointer
== ']')
9520 ++input_line_pointer
;
9521 e
->X_op_symbol
= make_expr_symbol (e
);
9522 e
->X_add_symbol
= NULL
;
9523 e
->X_add_number
= 0;
9529 input_line_pointer
= end
;
9536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9537 const char *md_shortopts
= "kVQ:sqn";
9539 const char *md_shortopts
= "qn";
9542 #define OPTION_32 (OPTION_MD_BASE + 0)
9543 #define OPTION_64 (OPTION_MD_BASE + 1)
9544 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9545 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9546 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9547 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9548 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9549 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9550 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9551 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9552 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9553 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9554 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9555 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9556 #define OPTION_X32 (OPTION_MD_BASE + 14)
9557 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9558 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9559 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9560 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9561 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9562 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9564 struct option md_longopts
[] =
9566 {"32", no_argument
, NULL
, OPTION_32
},
9567 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9569 {"64", no_argument
, NULL
, OPTION_64
},
9571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9572 {"x32", no_argument
, NULL
, OPTION_X32
},
9574 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9575 {"march", required_argument
, NULL
, OPTION_MARCH
},
9576 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9577 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9578 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9579 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9580 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9581 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9582 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9583 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9584 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9585 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9586 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9587 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9588 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9589 # if defined (TE_PE) || defined (TE_PEP)
9590 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9592 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9593 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9594 {NULL
, no_argument
, NULL
, 0}
9596 size_t md_longopts_size
= sizeof (md_longopts
);
9599 md_parse_option (int c
, char *arg
)
9607 optimize_align_code
= 0;
9614 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9615 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9616 should be emitted or not. FIXME: Not implemented. */
9620 /* -V: SVR4 argument to print version ID. */
9622 print_version_id ();
9625 /* -k: Ignore for FreeBSD compatibility. */
9630 /* -s: On i386 Solaris, this tells the native assembler to use
9631 .stab instead of .stab.excl. We always use .stab anyhow. */
9634 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9635 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9638 const char **list
, **l
;
9640 list
= bfd_target_list ();
9641 for (l
= list
; *l
!= NULL
; l
++)
9642 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9643 || strcmp (*l
, "coff-x86-64") == 0
9644 || strcmp (*l
, "pe-x86-64") == 0
9645 || strcmp (*l
, "pei-x86-64") == 0
9646 || strcmp (*l
, "mach-o-x86-64") == 0)
9648 default_arch
= "x86_64";
9652 as_fatal (_("no compiled in support for x86_64"));
9658 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9662 const char **list
, **l
;
9664 list
= bfd_target_list ();
9665 for (l
= list
; *l
!= NULL
; l
++)
9666 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9668 default_arch
= "x86_64:32";
9672 as_fatal (_("no compiled in support for 32bit x86_64"));
9676 as_fatal (_("32bit x86_64 is only supported for ELF"));
9681 default_arch
= "i386";
9685 #ifdef SVR4_COMMENT_CHARS
9690 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9692 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9696 i386_comment_chars
= n
;
9702 arch
= xstrdup (arg
);
9706 as_fatal (_("invalid -march= option: `%s'"), arg
);
9707 next
= strchr (arch
, '+');
9710 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9712 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9715 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9718 cpu_arch_name
= cpu_arch
[j
].name
;
9719 cpu_sub_arch_name
= NULL
;
9720 cpu_arch_flags
= cpu_arch
[j
].flags
;
9721 cpu_arch_isa
= cpu_arch
[j
].type
;
9722 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9723 if (!cpu_arch_tune_set
)
9725 cpu_arch_tune
= cpu_arch_isa
;
9726 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9730 else if (*cpu_arch
[j
].name
== '.'
9731 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9733 /* ISA entension. */
9734 i386_cpu_flags flags
;
9736 if (!cpu_arch
[j
].negated
)
9737 flags
= cpu_flags_or (cpu_arch_flags
,
9740 flags
= cpu_flags_and_not (cpu_arch_flags
,
9742 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9744 if (cpu_sub_arch_name
)
9746 char *name
= cpu_sub_arch_name
;
9747 cpu_sub_arch_name
= concat (name
,
9749 (const char *) NULL
);
9753 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9754 cpu_arch_flags
= flags
;
9755 cpu_arch_isa_flags
= flags
;
9761 if (j
>= ARRAY_SIZE (cpu_arch
))
9762 as_fatal (_("invalid -march= option: `%s'"), arg
);
9766 while (next
!= NULL
);
9771 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9772 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9774 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9776 cpu_arch_tune_set
= 1;
9777 cpu_arch_tune
= cpu_arch
[j
].type
;
9778 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9782 if (j
>= ARRAY_SIZE (cpu_arch
))
9783 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9786 case OPTION_MMNEMONIC
:
9787 if (strcasecmp (arg
, "att") == 0)
9789 else if (strcasecmp (arg
, "intel") == 0)
9792 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9795 case OPTION_MSYNTAX
:
9796 if (strcasecmp (arg
, "att") == 0)
9798 else if (strcasecmp (arg
, "intel") == 0)
9801 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9804 case OPTION_MINDEX_REG
:
9805 allow_index_reg
= 1;
9808 case OPTION_MNAKED_REG
:
9809 allow_naked_reg
= 1;
9812 case OPTION_MOLD_GCC
:
9816 case OPTION_MSSE2AVX
:
9820 case OPTION_MSSE_CHECK
:
9821 if (strcasecmp (arg
, "error") == 0)
9822 sse_check
= check_error
;
9823 else if (strcasecmp (arg
, "warning") == 0)
9824 sse_check
= check_warning
;
9825 else if (strcasecmp (arg
, "none") == 0)
9826 sse_check
= check_none
;
9828 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9831 case OPTION_MOPERAND_CHECK
:
9832 if (strcasecmp (arg
, "error") == 0)
9833 operand_check
= check_error
;
9834 else if (strcasecmp (arg
, "warning") == 0)
9835 operand_check
= check_warning
;
9836 else if (strcasecmp (arg
, "none") == 0)
9837 operand_check
= check_none
;
9839 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9842 case OPTION_MAVXSCALAR
:
9843 if (strcasecmp (arg
, "128") == 0)
9845 else if (strcasecmp (arg
, "256") == 0)
9848 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9851 case OPTION_MADD_BND_PREFIX
:
9855 case OPTION_MEVEXLIG
:
9856 if (strcmp (arg
, "128") == 0)
9858 else if (strcmp (arg
, "256") == 0)
9860 else if (strcmp (arg
, "512") == 0)
9863 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9866 case OPTION_MEVEXRCIG
:
9867 if (strcmp (arg
, "rne") == 0)
9869 else if (strcmp (arg
, "rd") == 0)
9871 else if (strcmp (arg
, "ru") == 0)
9873 else if (strcmp (arg
, "rz") == 0)
9876 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9879 case OPTION_MEVEXWIG
:
9880 if (strcmp (arg
, "0") == 0)
9882 else if (strcmp (arg
, "1") == 0)
9885 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9888 # if defined (TE_PE) || defined (TE_PEP)
9889 case OPTION_MBIG_OBJ
:
9894 case OPTION_OMIT_LOCK_PREFIX
:
9895 if (strcasecmp (arg
, "yes") == 0)
9896 omit_lock_prefix
= 1;
9897 else if (strcasecmp (arg
, "no") == 0)
9898 omit_lock_prefix
= 0;
9900 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9909 #define MESSAGE_TEMPLATE \
9913 show_arch (FILE *stream
, int ext
, int check
)
9915 static char message
[] = MESSAGE_TEMPLATE
;
9916 char *start
= message
+ 27;
9918 int size
= sizeof (MESSAGE_TEMPLATE
);
9925 left
= size
- (start
- message
);
9926 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9928 /* Should it be skipped? */
9929 if (cpu_arch
[j
].skip
)
9932 name
= cpu_arch
[j
].name
;
9933 len
= cpu_arch
[j
].len
;
9936 /* It is an extension. Skip if we aren't asked to show it. */
9947 /* It is an processor. Skip if we show only extension. */
9950 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9952 /* It is an impossible processor - skip. */
9956 /* Reserve 2 spaces for ", " or ",\0" */
9959 /* Check if there is any room. */
9967 p
= mempcpy (p
, name
, len
);
9971 /* Output the current message now and start a new one. */
9974 fprintf (stream
, "%s\n", message
);
9976 left
= size
- (start
- message
) - len
- 2;
9978 gas_assert (left
>= 0);
9980 p
= mempcpy (p
, name
, len
);
9985 fprintf (stream
, "%s\n", message
);
9989 md_show_usage (FILE *stream
)
9991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9992 fprintf (stream
, _("\
9994 -V print assembler version number\n\
9997 fprintf (stream
, _("\
9998 -n Do not optimize code alignment\n\
9999 -q quieten some warnings\n"));
10000 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10001 fprintf (stream
, _("\
10004 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10005 || defined (TE_PE) || defined (TE_PEP))
10006 fprintf (stream
, _("\
10007 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10009 #ifdef SVR4_COMMENT_CHARS
10010 fprintf (stream
, _("\
10011 --divide do not treat `/' as a comment character\n"));
10013 fprintf (stream
, _("\
10014 --divide ignored\n"));
10016 fprintf (stream
, _("\
10017 -march=CPU[,+EXTENSION...]\n\
10018 generate code for CPU and EXTENSION, CPU is one of:\n"));
10019 show_arch (stream
, 0, 1);
10020 fprintf (stream
, _("\
10021 EXTENSION is combination of:\n"));
10022 show_arch (stream
, 1, 0);
10023 fprintf (stream
, _("\
10024 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10025 show_arch (stream
, 0, 0);
10026 fprintf (stream
, _("\
10027 -msse2avx encode SSE instructions with VEX prefix\n"));
10028 fprintf (stream
, _("\
10029 -msse-check=[none|error|warning]\n\
10030 check SSE instructions\n"));
10031 fprintf (stream
, _("\
10032 -moperand-check=[none|error|warning]\n\
10033 check operand combinations for validity\n"));
10034 fprintf (stream
, _("\
10035 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10037 fprintf (stream
, _("\
10038 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10040 fprintf (stream
, _("\
10041 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10042 for EVEX.W bit ignored instructions\n"));
10043 fprintf (stream
, _("\
10044 -mevexrcig=[rne|rd|ru|rz]\n\
10045 encode EVEX instructions with specific EVEX.RC value\n\
10046 for SAE-only ignored instructions\n"));
10047 fprintf (stream
, _("\
10048 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10049 fprintf (stream
, _("\
10050 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10051 fprintf (stream
, _("\
10052 -mindex-reg support pseudo index registers\n"));
10053 fprintf (stream
, _("\
10054 -mnaked-reg don't require `%%' prefix for registers\n"));
10055 fprintf (stream
, _("\
10056 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10057 fprintf (stream
, _("\
10058 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10059 # if defined (TE_PE) || defined (TE_PEP)
10060 fprintf (stream
, _("\
10061 -mbig-obj generate big object files\n"));
10063 fprintf (stream
, _("\
10064 -momit-lock-prefix=[no|yes]\n\
10065 strip all lock prefixes\n"));
10068 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10069 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10070 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10072 /* Pick the target format to use. */
10075 i386_target_format (void)
10077 if (!strncmp (default_arch
, "x86_64", 6))
10079 update_code_flag (CODE_64BIT
, 1);
10080 if (default_arch
[6] == '\0')
10081 x86_elf_abi
= X86_64_ABI
;
10083 x86_elf_abi
= X86_64_X32_ABI
;
10085 else if (!strcmp (default_arch
, "i386"))
10086 update_code_flag (CODE_32BIT
, 1);
10088 as_fatal (_("unknown architecture"));
10090 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10091 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10092 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10093 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10095 switch (OUTPUT_FLAVOR
)
10097 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10098 case bfd_target_aout_flavour
:
10099 return AOUT_TARGET_FORMAT
;
10101 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10102 # if defined (TE_PE) || defined (TE_PEP)
10103 case bfd_target_coff_flavour
:
10104 if (flag_code
== CODE_64BIT
)
10105 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10108 # elif defined (TE_GO32)
10109 case bfd_target_coff_flavour
:
10110 return "coff-go32";
10112 case bfd_target_coff_flavour
:
10113 return "coff-i386";
10116 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10117 case bfd_target_elf_flavour
:
10119 const char *format
;
10121 switch (x86_elf_abi
)
10124 format
= ELF_TARGET_FORMAT
;
10127 use_rela_relocations
= 1;
10129 format
= ELF_TARGET_FORMAT64
;
10131 case X86_64_X32_ABI
:
10132 use_rela_relocations
= 1;
10134 disallow_64bit_reloc
= 1;
10135 format
= ELF_TARGET_FORMAT32
;
10138 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10140 if (x86_elf_abi
!= X86_64_ABI
)
10141 as_fatal (_("Intel L1OM is 64bit only"));
10142 return ELF_TARGET_L1OM_FORMAT
;
10144 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10146 if (x86_elf_abi
!= X86_64_ABI
)
10147 as_fatal (_("Intel K1OM is 64bit only"));
10148 return ELF_TARGET_K1OM_FORMAT
;
10154 #if defined (OBJ_MACH_O)
10155 case bfd_target_mach_o_flavour
:
10156 if (flag_code
== CODE_64BIT
)
10158 use_rela_relocations
= 1;
10160 return "mach-o-x86-64";
10163 return "mach-o-i386";
10171 #endif /* OBJ_MAYBE_ more than one */
10173 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10175 i386_elf_emit_arch_note (void)
10177 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10180 asection
*seg
= now_seg
;
10181 subsegT subseg
= now_subseg
;
10182 Elf_Internal_Note i_note
;
10183 Elf_External_Note e_note
;
10184 asection
*note_secp
;
10187 /* Create the .note section. */
10188 note_secp
= subseg_new (".note", 0);
10189 bfd_set_section_flags (stdoutput
,
10191 SEC_HAS_CONTENTS
| SEC_READONLY
);
10193 /* Process the arch string. */
10194 len
= strlen (cpu_arch_name
);
10196 i_note
.namesz
= len
+ 1;
10198 i_note
.type
= NT_ARCH
;
10199 p
= frag_more (sizeof (e_note
.namesz
));
10200 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10201 p
= frag_more (sizeof (e_note
.descsz
));
10202 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10203 p
= frag_more (sizeof (e_note
.type
));
10204 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10205 p
= frag_more (len
+ 1);
10206 strcpy (p
, cpu_arch_name
);
10208 frag_align (2, 0, 0);
10210 subseg_set (seg
, subseg
);
10216 md_undefined_symbol (char *name
)
10218 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10219 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10220 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10221 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10225 if (symbol_find (name
))
10226 as_bad (_("GOT already in symbol table"));
10227 GOT_symbol
= symbol_new (name
, undefined_section
,
10228 (valueT
) 0, &zero_address_frag
);
10235 /* Round up a section size to the appropriate boundary. */
10238 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10240 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10241 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10243 /* For a.out, force the section size to be aligned. If we don't do
10244 this, BFD will align it for us, but it will not write out the
10245 final bytes of the section. This may be a bug in BFD, but it is
10246 easier to fix it here since that is how the other a.out targets
10250 align
= bfd_get_section_alignment (stdoutput
, segment
);
10251 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10258 /* On the i386, PC-relative offsets are relative to the start of the
10259 next instruction. That is, the address of the offset, plus its
10260 size, since the offset is always the last part of the insn. */
10263 md_pcrel_from (fixS
*fixP
)
10265 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10271 s_bss (int ignore ATTRIBUTE_UNUSED
)
10275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10277 obj_elf_section_change_hook ();
10279 temp
= get_absolute_expression ();
10280 subseg_set (bss_section
, (subsegT
) temp
);
10281 demand_empty_rest_of_line ();
10287 i386_validate_fix (fixS
*fixp
)
10289 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10291 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10295 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10300 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10302 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10304 fixp
->fx_subsy
= 0;
10309 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10312 bfd_reloc_code_real_type code
;
10314 switch (fixp
->fx_r_type
)
10316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10317 case BFD_RELOC_SIZE32
:
10318 case BFD_RELOC_SIZE64
:
10319 if (S_IS_DEFINED (fixp
->fx_addsy
)
10320 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10322 /* Resolve size relocation against local symbol to size of
10323 the symbol plus addend. */
10324 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10325 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10326 && !fits_in_unsigned_long (value
))
10327 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10328 _("symbol size computation overflow"));
10329 fixp
->fx_addsy
= NULL
;
10330 fixp
->fx_subsy
= NULL
;
10331 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10336 case BFD_RELOC_X86_64_PLT32
:
10337 case BFD_RELOC_X86_64_GOT32
:
10338 case BFD_RELOC_X86_64_GOTPCREL
:
10339 case BFD_RELOC_386_PLT32
:
10340 case BFD_RELOC_386_GOT32
:
10341 case BFD_RELOC_386_GOTOFF
:
10342 case BFD_RELOC_386_GOTPC
:
10343 case BFD_RELOC_386_TLS_GD
:
10344 case BFD_RELOC_386_TLS_LDM
:
10345 case BFD_RELOC_386_TLS_LDO_32
:
10346 case BFD_RELOC_386_TLS_IE_32
:
10347 case BFD_RELOC_386_TLS_IE
:
10348 case BFD_RELOC_386_TLS_GOTIE
:
10349 case BFD_RELOC_386_TLS_LE_32
:
10350 case BFD_RELOC_386_TLS_LE
:
10351 case BFD_RELOC_386_TLS_GOTDESC
:
10352 case BFD_RELOC_386_TLS_DESC_CALL
:
10353 case BFD_RELOC_X86_64_TLSGD
:
10354 case BFD_RELOC_X86_64_TLSLD
:
10355 case BFD_RELOC_X86_64_DTPOFF32
:
10356 case BFD_RELOC_X86_64_DTPOFF64
:
10357 case BFD_RELOC_X86_64_GOTTPOFF
:
10358 case BFD_RELOC_X86_64_TPOFF32
:
10359 case BFD_RELOC_X86_64_TPOFF64
:
10360 case BFD_RELOC_X86_64_GOTOFF64
:
10361 case BFD_RELOC_X86_64_GOTPC32
:
10362 case BFD_RELOC_X86_64_GOT64
:
10363 case BFD_RELOC_X86_64_GOTPCREL64
:
10364 case BFD_RELOC_X86_64_GOTPC64
:
10365 case BFD_RELOC_X86_64_GOTPLT64
:
10366 case BFD_RELOC_X86_64_PLTOFF64
:
10367 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10368 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10369 case BFD_RELOC_RVA
:
10370 case BFD_RELOC_VTABLE_ENTRY
:
10371 case BFD_RELOC_VTABLE_INHERIT
:
10373 case BFD_RELOC_32_SECREL
:
10375 code
= fixp
->fx_r_type
;
10377 case BFD_RELOC_X86_64_32S
:
10378 if (!fixp
->fx_pcrel
)
10380 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10381 code
= fixp
->fx_r_type
;
10385 if (fixp
->fx_pcrel
)
10387 switch (fixp
->fx_size
)
10390 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10391 _("can not do %d byte pc-relative relocation"),
10393 code
= BFD_RELOC_32_PCREL
;
10395 case 1: code
= BFD_RELOC_8_PCREL
; break;
10396 case 2: code
= BFD_RELOC_16_PCREL
; break;
10397 case 4: code
= BFD_RELOC_32_PCREL
; break;
10399 case 8: code
= BFD_RELOC_64_PCREL
; break;
10405 switch (fixp
->fx_size
)
10408 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10409 _("can not do %d byte relocation"),
10411 code
= BFD_RELOC_32
;
10413 case 1: code
= BFD_RELOC_8
; break;
10414 case 2: code
= BFD_RELOC_16
; break;
10415 case 4: code
= BFD_RELOC_32
; break;
10417 case 8: code
= BFD_RELOC_64
; break;
10424 if ((code
== BFD_RELOC_32
10425 || code
== BFD_RELOC_32_PCREL
10426 || code
== BFD_RELOC_X86_64_32S
)
10428 && fixp
->fx_addsy
== GOT_symbol
)
10431 code
= BFD_RELOC_386_GOTPC
;
10433 code
= BFD_RELOC_X86_64_GOTPC32
;
10435 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10437 && fixp
->fx_addsy
== GOT_symbol
)
10439 code
= BFD_RELOC_X86_64_GOTPC64
;
10442 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10443 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10444 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10446 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10448 if (!use_rela_relocations
)
10450 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10451 vtable entry to be used in the relocation's section offset. */
10452 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10453 rel
->address
= fixp
->fx_offset
;
10454 #if defined (OBJ_COFF) && defined (TE_PE)
10455 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10456 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10461 /* Use the rela in 64bit mode. */
10464 if (disallow_64bit_reloc
)
10467 case BFD_RELOC_X86_64_DTPOFF64
:
10468 case BFD_RELOC_X86_64_TPOFF64
:
10469 case BFD_RELOC_64_PCREL
:
10470 case BFD_RELOC_X86_64_GOTOFF64
:
10471 case BFD_RELOC_X86_64_GOT64
:
10472 case BFD_RELOC_X86_64_GOTPCREL64
:
10473 case BFD_RELOC_X86_64_GOTPC64
:
10474 case BFD_RELOC_X86_64_GOTPLT64
:
10475 case BFD_RELOC_X86_64_PLTOFF64
:
10476 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10477 _("cannot represent relocation type %s in x32 mode"),
10478 bfd_get_reloc_code_name (code
));
10484 if (!fixp
->fx_pcrel
)
10485 rel
->addend
= fixp
->fx_offset
;
10489 case BFD_RELOC_X86_64_PLT32
:
10490 case BFD_RELOC_X86_64_GOT32
:
10491 case BFD_RELOC_X86_64_GOTPCREL
:
10492 case BFD_RELOC_X86_64_TLSGD
:
10493 case BFD_RELOC_X86_64_TLSLD
:
10494 case BFD_RELOC_X86_64_GOTTPOFF
:
10495 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10496 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10497 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10500 rel
->addend
= (section
->vma
10502 + fixp
->fx_addnumber
10503 + md_pcrel_from (fixp
));
10508 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10509 if (rel
->howto
== NULL
)
10511 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10512 _("cannot represent relocation type %s"),
10513 bfd_get_reloc_code_name (code
));
10514 /* Set howto to a garbage value so that we can keep going. */
10515 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10516 gas_assert (rel
->howto
!= NULL
);
10522 #include "tc-i386-intel.c"
10525 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10527 int saved_naked_reg
;
10528 char saved_register_dot
;
10530 saved_naked_reg
= allow_naked_reg
;
10531 allow_naked_reg
= 1;
10532 saved_register_dot
= register_chars
['.'];
10533 register_chars
['.'] = '.';
10534 allow_pseudo_reg
= 1;
10535 expression_and_evaluate (exp
);
10536 allow_pseudo_reg
= 0;
10537 register_chars
['.'] = saved_register_dot
;
10538 allow_naked_reg
= saved_naked_reg
;
10540 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10542 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10544 exp
->X_op
= O_constant
;
10545 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10546 .dw2_regnum
[flag_code
>> 1];
10549 exp
->X_op
= O_illegal
;
10554 tc_x86_frame_initial_instructions (void)
10556 static unsigned int sp_regno
[2];
10558 if (!sp_regno
[flag_code
>> 1])
10560 char *saved_input
= input_line_pointer
;
10561 char sp
[][4] = {"esp", "rsp"};
10564 input_line_pointer
= sp
[flag_code
>> 1];
10565 tc_x86_parse_to_dw2regnum (&exp
);
10566 gas_assert (exp
.X_op
== O_constant
);
10567 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10568 input_line_pointer
= saved_input
;
10571 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10572 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10576 x86_dwarf2_addr_size (void)
10578 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10579 if (x86_elf_abi
== X86_64_X32_ABI
)
10582 return bfd_arch_bits_per_address (stdoutput
) / 8;
10586 i386_elf_section_type (const char *str
, size_t len
)
10588 if (flag_code
== CODE_64BIT
10589 && len
== sizeof ("unwind") - 1
10590 && strncmp (str
, "unwind", 6) == 0)
10591 return SHT_X86_64_UNWIND
;
10598 i386_solaris_fix_up_eh_frame (segT sec
)
10600 if (flag_code
== CODE_64BIT
)
10601 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10607 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10611 exp
.X_op
= O_secrel
;
10612 exp
.X_add_symbol
= symbol
;
10613 exp
.X_add_number
= 0;
10614 emit_expr (&exp
, size
);
10618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10619 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10622 x86_64_section_letter (int letter
, char **ptr_msg
)
10624 if (flag_code
== CODE_64BIT
)
10627 return SHF_X86_64_LARGE
;
10629 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10632 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10637 x86_64_section_word (char *str
, size_t len
)
10639 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10640 return SHF_X86_64_LARGE
;
10646 handle_large_common (int small ATTRIBUTE_UNUSED
)
10648 if (flag_code
!= CODE_64BIT
)
10650 s_comm_internal (0, elf_common_parse
);
10651 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10655 static segT lbss_section
;
10656 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10657 asection
*saved_bss_section
= bss_section
;
10659 if (lbss_section
== NULL
)
10661 flagword applicable
;
10662 segT seg
= now_seg
;
10663 subsegT subseg
= now_subseg
;
10665 /* The .lbss section is for local .largecomm symbols. */
10666 lbss_section
= subseg_new (".lbss", 0);
10667 applicable
= bfd_applicable_section_flags (stdoutput
);
10668 bfd_set_section_flags (stdoutput
, lbss_section
,
10669 applicable
& SEC_ALLOC
);
10670 seg_info (lbss_section
)->bss
= 1;
10672 subseg_set (seg
, subseg
);
10675 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10676 bss_section
= lbss_section
;
10678 s_comm_internal (0, elf_common_parse
);
10680 elf_com_section_ptr
= saved_com_section_ptr
;
10681 bss_section
= saved_bss_section
;
10684 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */