1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c
);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry
*parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry
*build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS
*, offsetT
);
96 static void output_disp (fragS
*, offsetT
);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
104 static const char *default_arch
= DEFAULT_ARCH
;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry
*regs
;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands
;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 unsigned int types
[MAX_OPERANDS
];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op
[MAX_OPERANDS
];
141 /* Flags for operands. */
142 unsigned int flags
[MAX_OPERANDS
];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry
*base_reg
;
151 const reg_entry
*index_reg
;
152 unsigned int log2_scale_factor
;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry
*seg
[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes
;
161 unsigned char prefix
[MAX_PREFIXES
];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn
;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars
[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars
= "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars
= "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars
[] = "#/";
213 const char line_separator_chars
[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS
[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS
[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars
[256];
226 static char register_chars
[256];
227 static char operand_chars
[256];
228 static char identifier_chars
[256];
229 static char digit_chars
[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack
[32];
247 static char *save_stack_p
;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates
*current_templates
;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
261 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
263 /* Current operand we are working on. */
264 static int this_operand
;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code
;
276 static unsigned int object_64bit
;
277 static int use_rela_relocations
= 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names
[] =
287 /* 1 for intel syntax,
289 static int intel_syntax
= 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg
= 0;
294 /* Register prefix used for error message. */
295 static const char *register_prefix
= "%";
297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300 static char stackop_size
= '\0';
302 /* Non-zero to optimize code alignment. */
303 int optimize_align_code
= 1;
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings
= 0;
309 static const char *cpu_arch_name
= NULL
;
310 static const char *cpu_sub_arch_name
= NULL
;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
315 /* If we have selected a cpu we are generating instructions for. */
316 static int cpu_arch_tune_set
= 0;
318 /* Cpu we are generating instructions for. */
319 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
321 /* CPU feature flags of cpu we are generating instructions for. */
322 static unsigned int cpu_arch_tune_flags
= 0;
324 /* CPU instruction set architecture used. */
325 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
327 /* CPU feature flags of instruction set architecture used. */
328 static unsigned int cpu_arch_isa_flags
= 0;
330 /* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332 static unsigned int no_cond_jump_promotion
= 0;
334 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
335 static symbolS
*GOT_symbol
;
337 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
338 unsigned int x86_dwarf2_return_column
;
340 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341 int x86_cie_data_alignment
;
343 /* Interface to relax_segment.
344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
349 #define UNCOND_JUMP 0
351 #define COND_JUMP86 2
356 #define SMALL16 (SMALL | CODE16)
358 #define BIG16 (BIG | CODE16)
362 #define INLINE __inline__
368 #define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370 #define TYPE_FROM_RELAX_STATE(s) \
372 #define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
375 /* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
383 const relax_typeS md_relax_table
[] =
386 1) most positive reach of this state,
387 2) most negative reach of this state,
388 3) how many bytes this mode will have in the variable part of the frag
389 4) which index into the table to try if we can't fit into this one. */
391 /* UNCOND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 3 bytes to frag:
408 1 extra opcode byte, 2 displacement bytes. */
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
422 static const arch_entry cpu_arch
[] =
424 {"generic32", PROCESSOR_GENERIC32
,
425 Cpu186
|Cpu286
|Cpu386
},
426 {"generic64", PROCESSOR_GENERIC64
,
427 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
428 |CpuMMX2
|CpuSSE
|CpuSSE2
},
429 {"i8086", PROCESSOR_UNKNOWN
,
431 {"i186", PROCESSOR_UNKNOWN
,
433 {"i286", PROCESSOR_UNKNOWN
,
435 {"i386", PROCESSOR_GENERIC32
,
436 Cpu186
|Cpu286
|Cpu386
},
437 {"i486", PROCESSOR_I486
,
438 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
439 {"i586", PROCESSOR_PENTIUM
,
440 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
441 {"i686", PROCESSOR_PENTIUMPRO
,
442 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
443 {"pentium", PROCESSOR_PENTIUM
,
444 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
445 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
446 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
447 {"pentiumii", PROCESSOR_PENTIUMPRO
,
448 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
449 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
450 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
451 {"pentium4", PROCESSOR_PENTIUM4
,
452 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
453 |CpuMMX2
|CpuSSE
|CpuSSE2
},
454 {"prescott", PROCESSOR_NOCONA
,
455 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
456 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
457 {"nocona", PROCESSOR_NOCONA
,
458 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
459 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
460 {"yonah", PROCESSOR_CORE
,
461 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
462 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
463 {"core", PROCESSOR_CORE
,
464 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
465 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
466 {"merom", PROCESSOR_CORE2
,
467 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
468 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
469 {"core2", PROCESSOR_CORE2
,
470 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
471 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
473 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
474 {"k6_2", PROCESSOR_K6
,
475 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
476 {"athlon", PROCESSOR_ATHLON
,
477 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
478 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
479 {"sledgehammer", PROCESSOR_K8
,
480 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
481 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
482 {"opteron", PROCESSOR_K8
,
483 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
484 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
486 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
487 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
488 {"amdfam10", PROCESSOR_AMDFAM10
,
489 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
490 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
492 {".mmx", PROCESSOR_UNKNOWN
,
494 {".sse", PROCESSOR_UNKNOWN
,
495 CpuMMX
|CpuMMX2
|CpuSSE
},
496 {".sse2", PROCESSOR_UNKNOWN
,
497 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
498 {".sse3", PROCESSOR_UNKNOWN
,
499 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
500 {".ssse3", PROCESSOR_UNKNOWN
,
501 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
502 {".3dnow", PROCESSOR_UNKNOWN
,
504 {".3dnowa", PROCESSOR_UNKNOWN
,
505 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
506 {".padlock", PROCESSOR_UNKNOWN
,
508 {".pacifica", PROCESSOR_UNKNOWN
,
510 {".svme", PROCESSOR_UNKNOWN
,
512 {".sse4a", PROCESSOR_UNKNOWN
,
513 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
514 {".abm", PROCESSOR_UNKNOWN
,
518 const pseudo_typeS md_pseudo_table
[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes
, 0},
523 {"align", s_align_ptwo
, 0},
525 {"arch", set_cpu_arch
, 0},
529 {"ffloat", float_cons
, 'f'},
530 {"dfloat", float_cons
, 'd'},
531 {"tfloat", float_cons
, 'x'},
533 {"slong", signed_cons
, 4},
534 {"noopt", s_ignore
, 0},
535 {"optim", s_ignore
, 0},
536 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
537 {"code16", set_code_flag
, CODE_16BIT
},
538 {"code32", set_code_flag
, CODE_32BIT
},
539 {"code64", set_code_flag
, CODE_64BIT
},
540 {"intel_syntax", set_intel_syntax
, 1},
541 {"att_syntax", set_intel_syntax
, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common
, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
546 {"loc", dwarf2_directive_loc
, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
550 {"secrel32", pe_directive_secrel
, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer
;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control
*op_hash
;
561 /* Hash table for register lookup. */
562 static struct hash_control
*reg_hash
;
565 i386_align_code (fragS
*fragP
, int count
)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1
[] =
572 static const char f32_2
[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3
[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4
[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5
[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6
[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7
[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8
[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9
[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10
[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11
[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12
[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13
[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14
[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15
[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
609 static const char f16_3
[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
611 static const char f16_4
[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5
[] =
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6
[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7
[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8
[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt
[] = {
626 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
627 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
629 static const char *const f16_patt
[] = {
630 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
631 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
634 static const char alt_3
[] =
636 /* nopl 0(%[re]ax) */
637 static const char alt_4
[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5
[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6
[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7
[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8
[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9
[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10
[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11
[] =
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12
[] =
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13
[] =
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14
[] =
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15
[] =
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11
[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12
[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
714 static const char alt_short_13
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 static const char alt_short_14
[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt
[] = {
728 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
729 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
730 alt_short_14
, alt_short_15
732 static const char *const alt_long_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
735 alt_long_14
, alt_long_15
738 if (count
<= 0 || count
> 15)
741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
747 0x66 prefix will be used.
748 3. For PROCESSOR_CORE2, alt_long_patt will be used.
749 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
750 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
751 and PROCESSOR_GENERIC64, alt_short_patt will be used.
753 When -mtune= isn't used, alt_short_patt will be used if
754 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
759 if (flag_code
== CODE_16BIT
)
761 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
762 f16_patt
[count
- 1], count
);
764 /* Adjust jump offset. */
765 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
767 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
770 int nnops
= (count
+ 3) / 4;
771 int len
= count
/ nnops
;
772 int remains
= count
- nnops
* len
;
775 /* The recommended way to pad 64bit code is to use NOPs preceded
776 by maximally four 0x66 prefixes. Balance the size of nops. */
777 for (i
= 0; i
< remains
; i
++)
779 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
780 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
783 for (; i
< nnops
; i
++)
785 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
786 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
792 const char *const *patt
= NULL
;
794 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
796 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
797 switch (cpu_arch_tune
)
799 case PROCESSOR_UNKNOWN
:
800 /* We use cpu_arch_isa_flags to check if we SHOULD
801 optimize for Cpu686. */
802 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
803 patt
= alt_short_patt
;
807 case PROCESSOR_CORE2
:
808 patt
= alt_long_patt
;
810 case PROCESSOR_PENTIUMPRO
:
811 case PROCESSOR_PENTIUM4
:
812 case PROCESSOR_NOCONA
:
815 case PROCESSOR_ATHLON
:
817 case PROCESSOR_GENERIC64
:
818 case PROCESSOR_AMDFAM10
:
819 patt
= alt_short_patt
;
822 case PROCESSOR_PENTIUM
:
823 case PROCESSOR_GENERIC32
:
830 switch (cpu_arch_tune
)
832 case PROCESSOR_UNKNOWN
:
833 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
834 PROCESSOR_UNKNOWN. */
839 case PROCESSOR_PENTIUM
:
840 case PROCESSOR_PENTIUMPRO
:
841 case PROCESSOR_PENTIUM4
:
842 case PROCESSOR_NOCONA
:
845 case PROCESSOR_ATHLON
:
847 case PROCESSOR_AMDFAM10
:
848 case PROCESSOR_GENERIC32
:
849 /* We use cpu_arch_isa_flags to check if we CAN optimize
851 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
852 patt
= alt_short_patt
;
856 case PROCESSOR_CORE2
:
857 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
858 patt
= alt_long_patt
;
862 case PROCESSOR_GENERIC64
:
863 patt
= alt_short_patt
;
868 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
869 patt
[count
- 1], count
);
871 fragP
->fr_var
= count
;
874 static INLINE
unsigned int
875 mode_from_disp_size (unsigned int t
)
877 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
881 fits_in_signed_byte (offsetT num
)
883 return (num
>= -128) && (num
<= 127);
887 fits_in_unsigned_byte (offsetT num
)
889 return (num
& 0xff) == num
;
893 fits_in_unsigned_word (offsetT num
)
895 return (num
& 0xffff) == num
;
899 fits_in_signed_word (offsetT num
)
901 return (-32768 <= num
) && (num
<= 32767);
905 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
910 return (!(((offsetT
) -1 << 31) & num
)
911 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
913 } /* fits_in_signed_long() */
916 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
921 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
923 } /* fits_in_unsigned_long() */
926 smallest_imm_type (offsetT num
)
928 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
930 /* This code is disabled on the 486 because all the Imm1 forms
931 in the opcode table are slower on the i486. They're the
932 versions with the implicitly specified single-position
933 displacement, which has another syntax if you really want to
936 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
938 return (fits_in_signed_byte (num
)
939 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
940 : fits_in_unsigned_byte (num
)
941 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
942 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
943 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
944 : fits_in_signed_long (num
)
945 ? (Imm32
| Imm32S
| Imm64
)
946 : fits_in_unsigned_long (num
)
952 offset_in_range (offsetT val
, int size
)
958 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
959 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
960 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
962 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
967 /* If BFD64, sign extend val. */
968 if (!use_rela_relocations
)
969 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
970 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
972 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
974 char buf1
[40], buf2
[40];
976 sprint_value (buf1
, val
);
977 sprint_value (buf2
, val
& mask
);
978 as_warn (_("%s shortened to %s"), buf1
, buf2
);
983 /* Returns 0 if attempting to add a prefix where one from the same
984 class already exists, 1 if non rep/repne added, 2 if rep/repne
987 add_prefix (unsigned int prefix
)
992 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
993 && flag_code
== CODE_64BIT
)
995 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
996 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
997 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
1008 case CS_PREFIX_OPCODE
:
1009 case DS_PREFIX_OPCODE
:
1010 case ES_PREFIX_OPCODE
:
1011 case FS_PREFIX_OPCODE
:
1012 case GS_PREFIX_OPCODE
:
1013 case SS_PREFIX_OPCODE
:
1017 case REPNE_PREFIX_OPCODE
:
1018 case REPE_PREFIX_OPCODE
:
1021 case LOCK_PREFIX_OPCODE
:
1029 case ADDR_PREFIX_OPCODE
:
1033 case DATA_PREFIX_OPCODE
:
1037 if (i
.prefix
[q
] != 0)
1045 i
.prefix
[q
] |= prefix
;
1048 as_bad (_("same type of prefix used twice"));
1054 set_code_flag (int value
)
1057 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1058 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1059 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1061 as_bad (_("64bit mode not supported on this CPU."));
1063 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1065 as_bad (_("32bit mode not supported on this CPU."));
1067 stackop_size
= '\0';
1071 set_16bit_gcc_code_flag (int new_code_flag
)
1073 flag_code
= new_code_flag
;
1074 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1075 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1076 stackop_size
= LONG_MNEM_SUFFIX
;
1080 set_intel_syntax (int syntax_flag
)
1082 /* Find out if register prefixing is specified. */
1083 int ask_naked_reg
= 0;
1086 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1088 char *string
= input_line_pointer
;
1089 int e
= get_symbol_end ();
1091 if (strcmp (string
, "prefix") == 0)
1093 else if (strcmp (string
, "noprefix") == 0)
1096 as_bad (_("bad argument to syntax directive."));
1097 *input_line_pointer
= e
;
1099 demand_empty_rest_of_line ();
1101 intel_syntax
= syntax_flag
;
1103 if (ask_naked_reg
== 0)
1104 allow_naked_reg
= (intel_syntax
1105 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1107 allow_naked_reg
= (ask_naked_reg
< 0);
1109 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1110 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1111 register_prefix
= allow_naked_reg
? "" : "%";
1115 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1119 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1121 char *string
= input_line_pointer
;
1122 int e
= get_symbol_end ();
1125 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1127 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1131 cpu_arch_name
= cpu_arch
[i
].name
;
1132 cpu_sub_arch_name
= NULL
;
1133 cpu_arch_flags
= (cpu_arch
[i
].flags
1134 | (flag_code
== CODE_64BIT
1135 ? Cpu64
: CpuNo64
));
1136 cpu_arch_isa
= cpu_arch
[i
].type
;
1137 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1138 if (!cpu_arch_tune_set
)
1140 cpu_arch_tune
= cpu_arch_isa
;
1141 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1145 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1147 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1148 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1150 *input_line_pointer
= e
;
1151 demand_empty_rest_of_line ();
1155 if (i
>= ARRAY_SIZE (cpu_arch
))
1156 as_bad (_("no such architecture: `%s'"), string
);
1158 *input_line_pointer
= e
;
1161 as_bad (_("missing cpu architecture"));
1163 no_cond_jump_promotion
= 0;
1164 if (*input_line_pointer
== ','
1165 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1167 char *string
= ++input_line_pointer
;
1168 int e
= get_symbol_end ();
1170 if (strcmp (string
, "nojumps") == 0)
1171 no_cond_jump_promotion
= 1;
1172 else if (strcmp (string
, "jumps") == 0)
1175 as_bad (_("no such architecture modifier: `%s'"), string
);
1177 *input_line_pointer
= e
;
1180 demand_empty_rest_of_line ();
1186 if (!strcmp (default_arch
, "x86_64"))
1187 return bfd_mach_x86_64
;
1188 else if (!strcmp (default_arch
, "i386"))
1189 return bfd_mach_i386_i386
;
1191 as_fatal (_("Unknown architecture"));
1197 const char *hash_err
;
1199 /* Initialize op_hash hash table. */
1200 op_hash
= hash_new ();
1203 const template *optab
;
1204 templates
*core_optab
;
1206 /* Setup for loop. */
1208 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1209 core_optab
->start
= optab
;
1214 if (optab
->name
== NULL
1215 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1217 /* different name --> ship out current template list;
1218 add to hash table; & begin anew. */
1219 core_optab
->end
= optab
;
1220 hash_err
= hash_insert (op_hash
,
1225 as_fatal (_("Internal Error: Can't hash %s: %s"),
1229 if (optab
->name
== NULL
)
1231 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1232 core_optab
->start
= optab
;
1237 /* Initialize reg_hash hash table. */
1238 reg_hash
= hash_new ();
1240 const reg_entry
*regtab
;
1242 for (regtab
= i386_regtab
;
1243 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
1246 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1248 as_fatal (_("Internal Error: Can't hash %s: %s"),
1254 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1259 for (c
= 0; c
< 256; c
++)
1264 mnemonic_chars
[c
] = c
;
1265 register_chars
[c
] = c
;
1266 operand_chars
[c
] = c
;
1268 else if (ISLOWER (c
))
1270 mnemonic_chars
[c
] = c
;
1271 register_chars
[c
] = c
;
1272 operand_chars
[c
] = c
;
1274 else if (ISUPPER (c
))
1276 mnemonic_chars
[c
] = TOLOWER (c
);
1277 register_chars
[c
] = mnemonic_chars
[c
];
1278 operand_chars
[c
] = c
;
1281 if (ISALPHA (c
) || ISDIGIT (c
))
1282 identifier_chars
[c
] = c
;
1285 identifier_chars
[c
] = c
;
1286 operand_chars
[c
] = c
;
1291 identifier_chars
['@'] = '@';
1294 identifier_chars
['?'] = '?';
1295 operand_chars
['?'] = '?';
1297 digit_chars
['-'] = '-';
1298 mnemonic_chars
['-'] = '-';
1299 identifier_chars
['_'] = '_';
1300 identifier_chars
['.'] = '.';
1302 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1303 operand_chars
[(unsigned char) *p
] = *p
;
1306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1309 record_alignment (text_section
, 2);
1310 record_alignment (data_section
, 2);
1311 record_alignment (bss_section
, 2);
1315 if (flag_code
== CODE_64BIT
)
1317 x86_dwarf2_return_column
= 16;
1318 x86_cie_data_alignment
= -8;
1322 x86_dwarf2_return_column
= 8;
1323 x86_cie_data_alignment
= -4;
1328 i386_print_statistics (FILE *file
)
1330 hash_print_statistics (file
, "i386 opcode", op_hash
);
1331 hash_print_statistics (file
, "i386 register", reg_hash
);
1336 /* Debugging routines for md_assemble. */
1337 static void pte (template *);
1338 static void pt (unsigned int);
1339 static void pe (expressionS
*);
1340 static void ps (symbolS
*);
1343 pi (char *line
, i386_insn
*x
)
1347 fprintf (stdout
, "%s: template ", line
);
1349 fprintf (stdout
, " address: base %s index %s scale %x\n",
1350 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1351 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1352 x
->log2_scale_factor
);
1353 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1354 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1355 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1356 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1357 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1358 (x
->rex
& REX_MODE64
) != 0,
1359 (x
->rex
& REX_EXTX
) != 0,
1360 (x
->rex
& REX_EXTY
) != 0,
1361 (x
->rex
& REX_EXTZ
) != 0);
1362 for (i
= 0; i
< x
->operands
; i
++)
1364 fprintf (stdout
, " #%d: ", i
+ 1);
1366 fprintf (stdout
, "\n");
1368 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1369 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1370 if (x
->types
[i
] & Imm
)
1372 if (x
->types
[i
] & Disp
)
1373 pe (x
->op
[i
].disps
);
1381 fprintf (stdout
, " %d operands ", t
->operands
);
1382 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1383 if (t
->extension_opcode
!= None
)
1384 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1385 if (t
->opcode_modifier
& D
)
1386 fprintf (stdout
, "D");
1387 if (t
->opcode_modifier
& W
)
1388 fprintf (stdout
, "W");
1389 fprintf (stdout
, "\n");
1390 for (i
= 0; i
< t
->operands
; i
++)
1392 fprintf (stdout
, " #%d type ", i
+ 1);
1393 pt (t
->operand_types
[i
]);
1394 fprintf (stdout
, "\n");
1401 fprintf (stdout
, " operation %d\n", e
->X_op
);
1402 fprintf (stdout
, " add_number %ld (%lx)\n",
1403 (long) e
->X_add_number
, (long) e
->X_add_number
);
1404 if (e
->X_add_symbol
)
1406 fprintf (stdout
, " add_symbol ");
1407 ps (e
->X_add_symbol
);
1408 fprintf (stdout
, "\n");
1412 fprintf (stdout
, " op_symbol ");
1413 ps (e
->X_op_symbol
);
1414 fprintf (stdout
, "\n");
1421 fprintf (stdout
, "%s type %s%s",
1423 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1424 segment_name (S_GET_SEGMENT (s
)));
1427 static struct type_name
1432 const type_names
[] =
1445 { BaseIndex
, "BaseIndex" },
1449 { Disp32S
, "d32s" },
1451 { InOutPortReg
, "InOutPortReg" },
1452 { ShiftCount
, "ShiftCount" },
1453 { Control
, "control reg" },
1454 { Test
, "test reg" },
1455 { Debug
, "debug reg" },
1456 { FloatReg
, "FReg" },
1457 { FloatAcc
, "FAcc" },
1461 { JumpAbsolute
, "Jump Absolute" },
1472 const struct type_name
*ty
;
1474 for (ty
= type_names
; ty
->mask
; ty
++)
1476 fprintf (stdout
, "%s, ", ty
->tname
);
1480 #endif /* DEBUG386 */
1482 static bfd_reloc_code_real_type
1483 reloc (unsigned int size
,
1486 bfd_reloc_code_real_type other
)
1488 if (other
!= NO_RELOC
)
1490 reloc_howto_type
*reloc
;
1495 case BFD_RELOC_X86_64_GOT32
:
1496 return BFD_RELOC_X86_64_GOT64
;
1498 case BFD_RELOC_X86_64_PLTOFF64
:
1499 return BFD_RELOC_X86_64_PLTOFF64
;
1501 case BFD_RELOC_X86_64_GOTPC32
:
1502 other
= BFD_RELOC_X86_64_GOTPC64
;
1504 case BFD_RELOC_X86_64_GOTPCREL
:
1505 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1507 case BFD_RELOC_X86_64_TPOFF32
:
1508 other
= BFD_RELOC_X86_64_TPOFF64
;
1510 case BFD_RELOC_X86_64_DTPOFF32
:
1511 other
= BFD_RELOC_X86_64_DTPOFF64
;
1517 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1518 if (size
== 4 && flag_code
!= CODE_64BIT
)
1521 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1523 as_bad (_("unknown relocation (%u)"), other
);
1524 else if (size
!= bfd_get_reloc_size (reloc
))
1525 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1526 bfd_get_reloc_size (reloc
),
1528 else if (pcrel
&& !reloc
->pc_relative
)
1529 as_bad (_("non-pc-relative relocation for pc-relative field"));
1530 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1532 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1534 as_bad (_("relocated field and relocation type differ in signedness"));
1543 as_bad (_("there are no unsigned pc-relative relocations"));
1546 case 1: return BFD_RELOC_8_PCREL
;
1547 case 2: return BFD_RELOC_16_PCREL
;
1548 case 4: return BFD_RELOC_32_PCREL
;
1549 case 8: return BFD_RELOC_64_PCREL
;
1551 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1558 case 4: return BFD_RELOC_X86_64_32S
;
1563 case 1: return BFD_RELOC_8
;
1564 case 2: return BFD_RELOC_16
;
1565 case 4: return BFD_RELOC_32
;
1566 case 8: return BFD_RELOC_64
;
1568 as_bad (_("cannot do %s %u byte relocation"),
1569 sign
> 0 ? "signed" : "unsigned", size
);
1573 return BFD_RELOC_NONE
;
1576 /* Here we decide which fixups can be adjusted to make them relative to
1577 the beginning of the section instead of the symbol. Basically we need
1578 to make sure that the dynamic relocations are done correctly, so in
1579 some cases we force the original symbol to be used. */
1582 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1584 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1588 /* Don't adjust pc-relative references to merge sections in 64-bit
1590 if (use_rela_relocations
1591 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1595 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1596 and changed later by validate_fix. */
1597 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1598 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1601 /* adjust_reloc_syms doesn't know about the GOT. */
1602 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1603 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1604 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1606 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1607 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1608 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1609 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1612 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1613 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1614 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1625 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1626 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1627 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1628 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1629 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1636 intel_float_operand (const char *mnemonic
)
1638 /* Note that the value returned is meaningful only for opcodes with (memory)
1639 operands, hence the code here is free to improperly handle opcodes that
1640 have no operands (for better performance and smaller code). */
1642 if (mnemonic
[0] != 'f')
1643 return 0; /* non-math */
1645 switch (mnemonic
[1])
1647 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1648 the fs segment override prefix not currently handled because no
1649 call path can make opcodes without operands get here */
1651 return 2 /* integer op */;
1653 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1654 return 3; /* fldcw/fldenv */
1657 if (mnemonic
[2] != 'o' /* fnop */)
1658 return 3; /* non-waiting control op */
1661 if (mnemonic
[2] == 's')
1662 return 3; /* frstor/frstpm */
1665 if (mnemonic
[2] == 'a')
1666 return 3; /* fsave */
1667 if (mnemonic
[2] == 't')
1669 switch (mnemonic
[3])
1671 case 'c': /* fstcw */
1672 case 'd': /* fstdw */
1673 case 'e': /* fstenv */
1674 case 's': /* fsts[gw] */
1680 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1681 return 0; /* fxsave/fxrstor are not really math ops */
1688 /* This is the guts of the machine-dependent assembler. LINE points to a
1689 machine dependent instruction. This function is supposed to emit
1690 the frags/bytes it assembles to. */
1697 char mnemonic
[MAX_MNEM_SIZE
];
1699 /* Initialize globals. */
1700 memset (&i
, '\0', sizeof (i
));
1701 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1702 i
.reloc
[j
] = NO_RELOC
;
1703 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1704 memset (im_expressions
, '\0', sizeof (im_expressions
));
1705 save_stack_p
= save_stack
;
1707 /* First parse an instruction mnemonic & call i386_operand for the operands.
1708 We assume that the scrubber has arranged it so that line[0] is the valid
1709 start of a (possibly prefixed) mnemonic. */
1711 line
= parse_insn (line
, mnemonic
);
1715 line
= parse_operands (line
, mnemonic
);
1719 /* The order of the immediates should be reversed
1720 for 2 immediates extrq and insertq instructions */
1721 if ((i
.imm_operands
== 2)
1722 && ((strcmp (mnemonic
, "extrq") == 0)
1723 || (strcmp (mnemonic
, "insertq") == 0)))
1725 swap_2_operands (0, 1);
1726 /* "extrq" and insertq" are the only two instructions whose operands
1727 have to be reversed even though they have two immediate operands.
1733 /* Now we've parsed the mnemonic into a set of templates, and have the
1734 operands at hand. */
1736 /* All intel opcodes have reversed operands except for "bound" and
1737 "enter". We also don't reverse intersegment "jmp" and "call"
1738 instructions with 2 immediate operands so that the immediate segment
1739 precedes the offset, as it does when in AT&T mode. */
1742 && (strcmp (mnemonic
, "bound") != 0)
1743 && (strcmp (mnemonic
, "invlpga") != 0)
1744 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1750 /* Don't optimize displacement for movabs since it only takes 64bit
1753 && (flag_code
!= CODE_64BIT
1754 || strcmp (mnemonic
, "movabs") != 0))
1757 /* Next, we find a template that matches the given insn,
1758 making sure the overlap of the given operands types is consistent
1759 with the template operand types. */
1761 if (!match_template ())
1766 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1768 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1769 i
.tm
.base_opcode
^= Opcode_FloatR
;
1771 /* Zap movzx and movsx suffix. The suffix may have been set from
1772 "word ptr" or "byte ptr" on the source operand, but we'll use
1773 the suffix later to choose the destination register. */
1774 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1776 if (i
.reg_operands
< 2
1778 && (~i
.tm
.opcode_modifier
1785 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1791 if (i
.tm
.opcode_modifier
& FWait
)
1792 if (!add_prefix (FWAIT_OPCODE
))
1795 /* Check string instruction segment overrides. */
1796 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1798 if (!check_string ())
1802 if (!process_suffix ())
1805 /* Make still unresolved immediate matches conform to size of immediate
1806 given in i.suffix. */
1807 if (!finalize_imm ())
1810 if (i
.types
[0] & Imm1
)
1811 i
.imm_operands
= 0; /* kludge for shift insns. */
1812 if (i
.types
[0] & ImplicitRegister
)
1814 if (i
.types
[1] & ImplicitRegister
)
1816 if (i
.types
[2] & ImplicitRegister
)
1819 if (i
.tm
.opcode_modifier
& ImmExt
)
1823 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1825 /* Streaming SIMD extensions 3 Instructions have the fixed
1826 operands with an opcode suffix which is coded in the same
1827 place as an 8-bit immediate field would be. Here we check
1828 those operands and remove them afterwards. */
1831 for (x
= 0; x
< i
.operands
; x
++)
1832 if (i
.op
[x
].regs
->reg_num
!= x
)
1833 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1834 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1838 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1839 opcode suffix which is coded in the same place as an 8-bit
1840 immediate field would be. Here we fake an 8-bit immediate
1841 operand from the opcode suffix stored in tm.extension_opcode. */
1843 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1845 exp
= &im_expressions
[i
.imm_operands
++];
1846 i
.op
[i
.operands
].imms
= exp
;
1847 i
.types
[i
.operands
++] = Imm8
;
1848 exp
->X_op
= O_constant
;
1849 exp
->X_add_number
= i
.tm
.extension_opcode
;
1850 i
.tm
.extension_opcode
= None
;
1853 /* For insns with operands there are more diddles to do to the opcode. */
1856 if (!process_operands ())
1859 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1861 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1862 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1865 /* Handle conversion of 'int $3' --> special int3 insn. */
1866 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1868 i
.tm
.base_opcode
= INT3_OPCODE
;
1872 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1873 && i
.op
[0].disps
->X_op
== O_constant
)
1875 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1876 the absolute address given by the constant. Since ix86 jumps and
1877 calls are pc relative, we need to generate a reloc. */
1878 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1879 i
.op
[0].disps
->X_op
= O_symbol
;
1882 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1883 i
.rex
|= REX_MODE64
;
1885 /* For 8 bit registers we need an empty rex prefix. Also if the
1886 instruction already has a prefix, we need to convert old
1887 registers to new ones. */
1889 if (((i
.types
[0] & Reg8
) != 0
1890 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1891 || ((i
.types
[1] & Reg8
) != 0
1892 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1893 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1898 i
.rex
|= REX_OPCODE
;
1899 for (x
= 0; x
< 2; x
++)
1901 /* Look for 8 bit operand that uses old registers. */
1902 if ((i
.types
[x
] & Reg8
) != 0
1903 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1905 /* In case it is "hi" register, give up. */
1906 if (i
.op
[x
].regs
->reg_num
> 3)
1907 as_bad (_("can't encode register '%%%s' in an "
1908 "instruction requiring REX prefix."),
1909 i
.op
[x
].regs
->reg_name
);
1911 /* Otherwise it is equivalent to the extended register.
1912 Since the encoding doesn't change this is merely
1913 cosmetic cleanup for debug output. */
1915 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1921 add_prefix (REX_OPCODE
| i
.rex
);
1923 /* We are ready to output the insn. */
1928 parse_insn (char *line
, char *mnemonic
)
1931 char *token_start
= l
;
1936 /* Non-zero if we found a prefix only acceptable with string insns. */
1937 const char *expecting_string_instruction
= NULL
;
1942 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1945 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1947 as_bad (_("no such instruction: `%s'"), token_start
);
1952 if (!is_space_char (*l
)
1953 && *l
!= END_OF_INSN
1955 || (*l
!= PREFIX_SEPARATOR
1958 as_bad (_("invalid character %s in mnemonic"),
1959 output_invalid (*l
));
1962 if (token_start
== l
)
1964 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1965 as_bad (_("expecting prefix; got nothing"));
1967 as_bad (_("expecting mnemonic; got nothing"));
1971 /* Look up instruction (or prefix) via hash table. */
1972 current_templates
= hash_find (op_hash
, mnemonic
);
1974 if (*l
!= END_OF_INSN
1975 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1976 && current_templates
1977 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1979 if (current_templates
->start
->cpu_flags
1980 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1982 as_bad ((flag_code
!= CODE_64BIT
1983 ? _("`%s' is only supported in 64-bit mode")
1984 : _("`%s' is not supported in 64-bit mode")),
1985 current_templates
->start
->name
);
1988 /* If we are in 16-bit mode, do not allow addr16 or data16.
1989 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1990 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1991 && flag_code
!= CODE_64BIT
1992 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1993 ^ (flag_code
== CODE_16BIT
)))
1995 as_bad (_("redundant %s prefix"),
1996 current_templates
->start
->name
);
1999 /* Add prefix, checking for repeated prefixes. */
2000 switch (add_prefix (current_templates
->start
->base_opcode
))
2005 expecting_string_instruction
= current_templates
->start
->name
;
2008 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2015 if (!current_templates
)
2017 /* See if we can get a match by trimming off a suffix. */
2020 case WORD_MNEM_SUFFIX
:
2021 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2022 i
.suffix
= SHORT_MNEM_SUFFIX
;
2024 case BYTE_MNEM_SUFFIX
:
2025 case QWORD_MNEM_SUFFIX
:
2026 i
.suffix
= mnem_p
[-1];
2028 current_templates
= hash_find (op_hash
, mnemonic
);
2030 case SHORT_MNEM_SUFFIX
:
2031 case LONG_MNEM_SUFFIX
:
2034 i
.suffix
= mnem_p
[-1];
2036 current_templates
= hash_find (op_hash
, mnemonic
);
2044 if (intel_float_operand (mnemonic
) == 1)
2045 i
.suffix
= SHORT_MNEM_SUFFIX
;
2047 i
.suffix
= LONG_MNEM_SUFFIX
;
2049 current_templates
= hash_find (op_hash
, mnemonic
);
2053 if (!current_templates
)
2055 as_bad (_("no such instruction: `%s'"), token_start
);
2060 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2062 /* Check for a branch hint. We allow ",pt" and ",pn" for
2063 predict taken and predict not taken respectively.
2064 I'm not sure that branch hints actually do anything on loop
2065 and jcxz insns (JumpByte) for current Pentium4 chips. They
2066 may work in the future and it doesn't hurt to accept them
2068 if (l
[0] == ',' && l
[1] == 'p')
2072 if (!add_prefix (DS_PREFIX_OPCODE
))
2076 else if (l
[2] == 'n')
2078 if (!add_prefix (CS_PREFIX_OPCODE
))
2084 /* Any other comma loses. */
2087 as_bad (_("invalid character %s in mnemonic"),
2088 output_invalid (*l
));
2092 /* Check if instruction is supported on specified architecture. */
2094 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2096 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2097 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2099 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2102 if (!(supported
& 2))
2104 as_bad (flag_code
== CODE_64BIT
2105 ? _("`%s' is not supported in 64-bit mode")
2106 : _("`%s' is only supported in 64-bit mode"),
2107 current_templates
->start
->name
);
2110 if (!(supported
& 1))
2112 as_warn (_("`%s' is not supported on `%s%s'"),
2113 current_templates
->start
->name
,
2115 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2117 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2119 as_warn (_("use .code16 to ensure correct addressing mode"));
2122 /* Check for rep/repne without a string instruction. */
2123 if (expecting_string_instruction
)
2125 static templates override
;
2127 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2128 if (t
->opcode_modifier
& IsString
)
2130 if (t
>= current_templates
->end
)
2132 as_bad (_("expecting string instruction after `%s'"),
2133 expecting_string_instruction
);
2136 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2137 if (!(t
->opcode_modifier
& IsString
))
2140 current_templates
= &override
;
2147 parse_operands (char *l
, const char *mnemonic
)
2151 /* 1 if operand is pending after ','. */
2152 unsigned int expecting_operand
= 0;
2154 /* Non-zero if operand parens not balanced. */
2155 unsigned int paren_not_balanced
;
2157 while (*l
!= END_OF_INSN
)
2159 /* Skip optional white space before operand. */
2160 if (is_space_char (*l
))
2162 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2164 as_bad (_("invalid character %s before operand %d"),
2165 output_invalid (*l
),
2169 token_start
= l
; /* after white space */
2170 paren_not_balanced
= 0;
2171 while (paren_not_balanced
|| *l
!= ',')
2173 if (*l
== END_OF_INSN
)
2175 if (paren_not_balanced
)
2178 as_bad (_("unbalanced parenthesis in operand %d."),
2181 as_bad (_("unbalanced brackets in operand %d."),
2186 break; /* we are done */
2188 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2190 as_bad (_("invalid character %s in operand %d"),
2191 output_invalid (*l
),
2198 ++paren_not_balanced
;
2200 --paren_not_balanced
;
2205 ++paren_not_balanced
;
2207 --paren_not_balanced
;
2211 if (l
!= token_start
)
2212 { /* Yes, we've read in another operand. */
2213 unsigned int operand_ok
;
2214 this_operand
= i
.operands
++;
2215 if (i
.operands
> MAX_OPERANDS
)
2217 as_bad (_("spurious operands; (%d operands/instruction max)"),
2221 /* Now parse operand adding info to 'i' as we go along. */
2222 END_STRING_AND_SAVE (l
);
2226 i386_intel_operand (token_start
,
2227 intel_float_operand (mnemonic
));
2229 operand_ok
= i386_operand (token_start
);
2231 RESTORE_END_STRING (l
);
2237 if (expecting_operand
)
2239 expecting_operand_after_comma
:
2240 as_bad (_("expecting operand after ','; got nothing"));
2245 as_bad (_("expecting operand before ','; got nothing"));
2250 /* Now *l must be either ',' or END_OF_INSN. */
2253 if (*++l
== END_OF_INSN
)
2255 /* Just skip it, if it's \n complain. */
2256 goto expecting_operand_after_comma
;
2258 expecting_operand
= 1;
2265 swap_2_operands (int xchg1
, int xchg2
)
2267 union i386_op temp_op
;
2268 unsigned int temp_type
;
2269 enum bfd_reloc_code_real temp_reloc
;
2271 temp_type
= i
.types
[xchg2
];
2272 i
.types
[xchg2
] = i
.types
[xchg1
];
2273 i
.types
[xchg1
] = temp_type
;
2274 temp_op
= i
.op
[xchg2
];
2275 i
.op
[xchg2
] = i
.op
[xchg1
];
2276 i
.op
[xchg1
] = temp_op
;
2277 temp_reloc
= i
.reloc
[xchg2
];
2278 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2279 i
.reloc
[xchg1
] = temp_reloc
;
2283 swap_operands (void)
2288 swap_2_operands (1, i
.operands
- 2);
2291 swap_2_operands (0, i
.operands
- 1);
2297 if (i
.mem_operands
== 2)
2299 const seg_entry
*temp_seg
;
2300 temp_seg
= i
.seg
[0];
2301 i
.seg
[0] = i
.seg
[1];
2302 i
.seg
[1] = temp_seg
;
2306 /* Try to ensure constant immediates are represented in the smallest
2311 char guess_suffix
= 0;
2315 guess_suffix
= i
.suffix
;
2316 else if (i
.reg_operands
)
2318 /* Figure out a suffix from the last register operand specified.
2319 We can't do this properly yet, ie. excluding InOutPortReg,
2320 but the following works for instructions with immediates.
2321 In any case, we can't set i.suffix yet. */
2322 for (op
= i
.operands
; --op
>= 0;)
2323 if (i
.types
[op
] & Reg
)
2325 if (i
.types
[op
] & Reg8
)
2326 guess_suffix
= BYTE_MNEM_SUFFIX
;
2327 else if (i
.types
[op
] & Reg16
)
2328 guess_suffix
= WORD_MNEM_SUFFIX
;
2329 else if (i
.types
[op
] & Reg32
)
2330 guess_suffix
= LONG_MNEM_SUFFIX
;
2331 else if (i
.types
[op
] & Reg64
)
2332 guess_suffix
= QWORD_MNEM_SUFFIX
;
2336 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2337 guess_suffix
= WORD_MNEM_SUFFIX
;
2339 for (op
= i
.operands
; --op
>= 0;)
2340 if (i
.types
[op
] & Imm
)
2342 switch (i
.op
[op
].imms
->X_op
)
2345 /* If a suffix is given, this operand may be shortened. */
2346 switch (guess_suffix
)
2348 case LONG_MNEM_SUFFIX
:
2349 i
.types
[op
] |= Imm32
| Imm64
;
2351 case WORD_MNEM_SUFFIX
:
2352 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2354 case BYTE_MNEM_SUFFIX
:
2355 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2359 /* If this operand is at most 16 bits, convert it
2360 to a signed 16 bit number before trying to see
2361 whether it will fit in an even smaller size.
2362 This allows a 16-bit operand such as $0xffe0 to
2363 be recognised as within Imm8S range. */
2364 if ((i
.types
[op
] & Imm16
)
2365 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2367 i
.op
[op
].imms
->X_add_number
=
2368 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2370 if ((i
.types
[op
] & Imm32
)
2371 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2374 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2375 ^ ((offsetT
) 1 << 31))
2376 - ((offsetT
) 1 << 31));
2378 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2380 /* We must avoid matching of Imm32 templates when 64bit
2381 only immediate is available. */
2382 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2383 i
.types
[op
] &= ~Imm32
;
2390 /* Symbols and expressions. */
2392 /* Convert symbolic operand to proper sizes for matching, but don't
2393 prevent matching a set of insns that only supports sizes other
2394 than those matching the insn suffix. */
2396 unsigned int mask
, allowed
= 0;
2399 for (t
= current_templates
->start
;
2400 t
< current_templates
->end
;
2402 allowed
|= t
->operand_types
[op
];
2403 switch (guess_suffix
)
2405 case QWORD_MNEM_SUFFIX
:
2406 mask
= Imm64
| Imm32S
;
2408 case LONG_MNEM_SUFFIX
:
2411 case WORD_MNEM_SUFFIX
:
2414 case BYTE_MNEM_SUFFIX
:
2422 i
.types
[op
] &= mask
;
2429 /* Try to use the smallest displacement type too. */
2431 optimize_disp (void)
2435 for (op
= i
.operands
; --op
>= 0;)
2436 if (i
.types
[op
] & Disp
)
2438 if (i
.op
[op
].disps
->X_op
== O_constant
)
2440 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2442 if ((i
.types
[op
] & Disp16
)
2443 && (disp
& ~(offsetT
) 0xffff) == 0)
2445 /* If this operand is at most 16 bits, convert
2446 to a signed 16 bit number and don't use 64bit
2448 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2449 i
.types
[op
] &= ~Disp64
;
2451 if ((i
.types
[op
] & Disp32
)
2452 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2454 /* If this operand is at most 32 bits, convert
2455 to a signed 32 bit number and don't use 64bit
2457 disp
&= (((offsetT
) 2 << 31) - 1);
2458 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2459 i
.types
[op
] &= ~Disp64
;
2461 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2463 i
.types
[op
] &= ~Disp
;
2467 else if (flag_code
== CODE_64BIT
)
2469 if (fits_in_signed_long (disp
))
2471 i
.types
[op
] &= ~Disp64
;
2472 i
.types
[op
] |= Disp32S
;
2474 if (fits_in_unsigned_long (disp
))
2475 i
.types
[op
] |= Disp32
;
2477 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2478 && fits_in_signed_byte (disp
))
2479 i
.types
[op
] |= Disp8
;
2481 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2482 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2484 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2485 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2486 i
.types
[op
] &= ~Disp
;
2489 /* We only support 64bit displacement on constants. */
2490 i
.types
[op
] &= ~Disp64
;
2495 match_template (void)
2497 /* Points to template once we've found it. */
2499 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2500 unsigned int found_reverse_match
;
2502 unsigned int operand_types
[MAX_OPERANDS
];
2503 int addr_prefix_disp
;
2506 #if MAX_OPERANDS != 4
2507 # error "MAX_OPERANDS must be 4."
2510 #define MATCH(overlap, given, template) \
2511 ((overlap & ~JumpAbsolute) \
2512 && (((given) & (BaseIndex | JumpAbsolute)) \
2513 == ((overlap) & (BaseIndex | JumpAbsolute))))
2515 /* If given types r0 and r1 are registers they must be of the same type
2516 unless the expected operand type register overlap is null.
2517 Note that Acc in a template matches every size of reg. */
2518 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2519 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2520 || ((g0) & Reg) == ((g1) & Reg) \
2521 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2527 found_reverse_match
= 0;
2528 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2529 operand_types
[j
] = 0;
2530 addr_prefix_disp
= -1;
2531 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2533 : (i
.suffix
== WORD_MNEM_SUFFIX
2535 : (i
.suffix
== SHORT_MNEM_SUFFIX
2537 : (i
.suffix
== LONG_MNEM_SUFFIX
2539 : (i
.suffix
== QWORD_MNEM_SUFFIX
2541 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2542 ? No_xSuf
: 0))))));
2544 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2546 addr_prefix_disp
= -1;
2548 /* Must have right number of operands. */
2549 if (i
.operands
!= t
->operands
)
2552 /* Check the suffix, except for some instructions in intel mode. */
2553 if ((t
->opcode_modifier
& suffix_check
)
2555 && (t
->opcode_modifier
& IgnoreSize
)))
2558 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2559 operand_types
[j
] = t
->operand_types
[j
];
2561 /* In general, don't allow 64-bit operands in 32-bit mode. */
2562 if (i
.suffix
== QWORD_MNEM_SUFFIX
2563 && flag_code
!= CODE_64BIT
2565 ? (!(t
->opcode_modifier
& IgnoreSize
)
2566 && !intel_float_operand (t
->name
))
2567 : intel_float_operand (t
->name
) != 2)
2568 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2569 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2570 && (t
->base_opcode
!= 0x0fc7
2571 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2574 /* Do not verify operands when there are none. */
2575 else if (!t
->operands
)
2577 if (t
->cpu_flags
& ~cpu_arch_flags
)
2579 /* We've found a match; break out of loop. */
2583 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2584 into Disp32/Disp16/Disp32 operand. */
2585 if (i
.prefix
[ADDR_PREFIX
] != 0)
2587 unsigned int DispOn
= 0, DispOff
= 0;
2605 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2607 /* There should be only one Disp operand. */
2608 if ((operand_types
[j
] & DispOff
))
2610 addr_prefix_disp
= j
;
2611 operand_types
[j
] |= DispOn
;
2612 operand_types
[j
] &= ~DispOff
;
2618 overlap0
= i
.types
[0] & operand_types
[0];
2619 switch (t
->operands
)
2622 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2628 overlap1
= i
.types
[1] & operand_types
[1];
2629 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2630 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2631 /* monitor in SSE3 is a very special case. The first
2632 register and the second register may have different
2634 || !((t
->base_opcode
== 0x0f01
2635 && t
->extension_opcode
== 0xc8)
2636 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2638 overlap1
, i
.types
[1],
2641 /* Check if other direction is valid ... */
2642 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2645 /* Try reversing direction of operands. */
2646 overlap0
= i
.types
[0] & operand_types
[1];
2647 overlap1
= i
.types
[1] & operand_types
[0];
2648 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2649 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2650 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2652 overlap1
, i
.types
[1],
2655 /* Does not match either direction. */
2658 /* found_reverse_match holds which of D or FloatDR
2660 if ((t
->opcode_modifier
& D
))
2661 found_reverse_match
= Opcode_D
;
2662 else if ((t
->opcode_modifier
& FloatD
))
2663 found_reverse_match
= Opcode_FloatD
;
2665 found_reverse_match
= 0;
2666 if ((t
->opcode_modifier
& FloatR
))
2667 found_reverse_match
|= Opcode_FloatR
;
2671 /* Found a forward 2 operand match here. */
2672 switch (t
->operands
)
2675 overlap3
= i
.types
[3] & operand_types
[3];
2677 overlap2
= i
.types
[2] & operand_types
[2];
2681 switch (t
->operands
)
2684 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2685 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2693 /* Here we make use of the fact that there are no
2694 reverse match 3 operand instructions, and all 3
2695 operand instructions only need to be checked for
2696 register consistency between operands 2 and 3. */
2697 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2698 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2708 /* Found either forward/reverse 2, 3 or 4 operand match here:
2709 slip through to break. */
2711 if (t
->cpu_flags
& ~cpu_arch_flags
)
2713 found_reverse_match
= 0;
2716 /* We've found a match; break out of loop. */
2720 if (t
== current_templates
->end
)
2722 /* We found no match. */
2723 as_bad (_("suffix or operands invalid for `%s'"),
2724 current_templates
->start
->name
);
2728 if (!quiet_warnings
)
2731 && ((i
.types
[0] & JumpAbsolute
)
2732 != (operand_types
[0] & JumpAbsolute
)))
2734 as_warn (_("indirect %s without `*'"), t
->name
);
2737 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2738 == (IsPrefix
| IgnoreSize
))
2740 /* Warn them that a data or address size prefix doesn't
2741 affect assembly of the next line of code. */
2742 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2746 /* Copy the template we found. */
2749 if (addr_prefix_disp
!= -1)
2750 i
.tm
.operand_types
[addr_prefix_disp
]
2751 = operand_types
[addr_prefix_disp
];
2753 if (found_reverse_match
)
2755 /* If we found a reverse match we must alter the opcode
2756 direction bit. found_reverse_match holds bits to change
2757 (different for int & float insns). */
2759 i
.tm
.base_opcode
^= found_reverse_match
;
2761 i
.tm
.operand_types
[0] = operand_types
[1];
2762 i
.tm
.operand_types
[1] = operand_types
[0];
2771 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2772 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2774 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2776 as_bad (_("`%s' operand %d must use `%%es' segment"),
2781 /* There's only ever one segment override allowed per instruction.
2782 This instruction possibly has a legal segment override on the
2783 second operand, so copy the segment to where non-string
2784 instructions store it, allowing common code. */
2785 i
.seg
[0] = i
.seg
[1];
2787 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2789 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2791 as_bad (_("`%s' operand %d must use `%%es' segment"),
2801 process_suffix (void)
2803 /* If matched instruction specifies an explicit instruction mnemonic
2805 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2807 if (i
.tm
.opcode_modifier
& Size16
)
2808 i
.suffix
= WORD_MNEM_SUFFIX
;
2809 else if (i
.tm
.opcode_modifier
& Size64
)
2810 i
.suffix
= QWORD_MNEM_SUFFIX
;
2812 i
.suffix
= LONG_MNEM_SUFFIX
;
2814 else if (i
.reg_operands
)
2816 /* If there's no instruction mnemonic suffix we try to invent one
2817 based on register operands. */
2820 /* We take i.suffix from the last register operand specified,
2821 Destination register type is more significant than source
2825 for (op
= i
.operands
; --op
>= 0;)
2826 if ((i
.types
[op
] & Reg
)
2827 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2829 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2830 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2831 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2836 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2838 if (!check_byte_reg ())
2841 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2843 if (!check_long_reg ())
2846 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2848 if (!check_qword_reg ())
2851 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2853 if (!check_word_reg ())
2856 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2857 /* Do nothing if the instruction is going to ignore the prefix. */
2862 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2864 /* exclude fldenv/frstor/fsave/fstenv */
2865 && (i
.tm
.opcode_modifier
& No_sSuf
))
2867 i
.suffix
= stackop_size
;
2869 else if (intel_syntax
2871 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2872 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2873 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2874 && i
.tm
.extension_opcode
<= 3)))
2879 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2881 i
.suffix
= QWORD_MNEM_SUFFIX
;
2885 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2886 i
.suffix
= LONG_MNEM_SUFFIX
;
2889 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2890 i
.suffix
= WORD_MNEM_SUFFIX
;
2899 if (i
.tm
.opcode_modifier
& W
)
2901 as_bad (_("no instruction mnemonic suffix given and "
2902 "no register operands; can't size instruction"));
2908 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2916 if ((i
.tm
.opcode_modifier
& W
)
2917 || ((suffixes
& (suffixes
- 1))
2918 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2920 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2926 /* Change the opcode based on the operand size given by i.suffix;
2927 We don't need to change things for byte insns. */
2929 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2931 /* It's not a byte, select word/dword operation. */
2932 if (i
.tm
.opcode_modifier
& W
)
2934 if (i
.tm
.opcode_modifier
& ShortForm
)
2935 i
.tm
.base_opcode
|= 8;
2937 i
.tm
.base_opcode
|= 1;
2940 /* Now select between word & dword operations via the operand
2941 size prefix, except for instructions that will ignore this
2943 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2945 /* monitor in SSE3 is a very special case. The default size
2946 of AX is the size of mode. The address size override
2947 prefix will change the size of AX. */
2948 if (i
.op
->regs
[0].reg_type
&
2949 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2950 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2953 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2954 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2955 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2956 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2957 || (flag_code
== CODE_64BIT
2958 && (i
.tm
.opcode_modifier
& JumpByte
))))
2960 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2962 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2963 prefix
= ADDR_PREFIX_OPCODE
;
2965 if (!add_prefix (prefix
))
2969 /* Set mode64 for an operand. */
2970 if (i
.suffix
== QWORD_MNEM_SUFFIX
2971 && flag_code
== CODE_64BIT
2972 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2974 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2977 || i
.types
[0] != (Acc
| Reg64
)
2978 || i
.types
[1] != (Acc
| Reg64
)
2979 || strcmp (i
.tm
.name
, "xchg") != 0)
2980 i
.rex
|= REX_MODE64
;
2983 /* Size floating point instruction. */
2984 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2985 if (i
.tm
.opcode_modifier
& FloatMF
)
2986 i
.tm
.base_opcode
^= 4;
2993 check_byte_reg (void)
2997 for (op
= i
.operands
; --op
>= 0;)
2999 /* If this is an eight bit register, it's OK. If it's the 16 or
3000 32 bit version of an eight bit register, we will just use the
3001 low portion, and that's OK too. */
3002 if (i
.types
[op
] & Reg8
)
3005 /* movzx and movsx should not generate this warning. */
3007 && (i
.tm
.base_opcode
== 0xfb7
3008 || i
.tm
.base_opcode
== 0xfb6
3009 || i
.tm
.base_opcode
== 0x63
3010 || i
.tm
.base_opcode
== 0xfbe
3011 || i
.tm
.base_opcode
== 0xfbf))
3014 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3016 /* Prohibit these changes in the 64bit mode, since the
3017 lowering is more complicated. */
3018 if (flag_code
== CODE_64BIT
3019 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3021 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3022 register_prefix
, i
.op
[op
].regs
->reg_name
,
3026 #if REGISTER_WARNINGS
3028 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3029 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3030 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3031 ? REGNAM_AL
- REGNAM_AX
3032 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3033 i
.op
[op
].regs
->reg_name
,
3038 /* Any other register is bad. */
3039 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3041 | Control
| Debug
| Test
3042 | FloatReg
| FloatAcc
))
3044 as_bad (_("`%%%s' not allowed with `%s%c'"),
3045 i
.op
[op
].regs
->reg_name
,
3055 check_long_reg (void)
3059 for (op
= i
.operands
; --op
>= 0;)
3060 /* Reject eight bit registers, except where the template requires
3061 them. (eg. movzb) */
3062 if ((i
.types
[op
] & Reg8
) != 0
3063 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3065 as_bad (_("`%%%s' not allowed with `%s%c'"),
3066 i
.op
[op
].regs
->reg_name
,
3071 /* Warn if the e prefix on a general reg is missing. */
3072 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3073 && (i
.types
[op
] & Reg16
) != 0
3074 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3076 /* Prohibit these changes in the 64bit mode, since the
3077 lowering is more complicated. */
3078 if (flag_code
== CODE_64BIT
)
3080 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3081 register_prefix
, i
.op
[op
].regs
->reg_name
,
3085 #if REGISTER_WARNINGS
3087 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3088 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3089 i
.op
[op
].regs
->reg_name
,
3093 /* Warn if the r prefix on a general reg is missing. */
3094 else if ((i
.types
[op
] & Reg64
) != 0
3095 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3097 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3098 register_prefix
, i
.op
[op
].regs
->reg_name
,
3106 check_qword_reg (void)
3110 for (op
= i
.operands
; --op
>= 0; )
3111 /* Reject eight bit registers, except where the template requires
3112 them. (eg. movzb) */
3113 if ((i
.types
[op
] & Reg8
) != 0
3114 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3116 as_bad (_("`%%%s' not allowed with `%s%c'"),
3117 i
.op
[op
].regs
->reg_name
,
3122 /* Warn if the e prefix on a general reg is missing. */
3123 else if (((i
.types
[op
] & Reg16
) != 0
3124 || (i
.types
[op
] & Reg32
) != 0)
3125 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3127 /* Prohibit these changes in the 64bit mode, since the
3128 lowering is more complicated. */
3129 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3130 register_prefix
, i
.op
[op
].regs
->reg_name
,
3138 check_word_reg (void)
3141 for (op
= i
.operands
; --op
>= 0;)
3142 /* Reject eight bit registers, except where the template requires
3143 them. (eg. movzb) */
3144 if ((i
.types
[op
] & Reg8
) != 0
3145 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3147 as_bad (_("`%%%s' not allowed with `%s%c'"),
3148 i
.op
[op
].regs
->reg_name
,
3153 /* Warn if the e prefix on a general reg is present. */
3154 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3155 && (i
.types
[op
] & Reg32
) != 0
3156 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3158 /* Prohibit these changes in the 64bit mode, since the
3159 lowering is more complicated. */
3160 if (flag_code
== CODE_64BIT
)
3162 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3163 register_prefix
, i
.op
[op
].regs
->reg_name
,
3168 #if REGISTER_WARNINGS
3169 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3170 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3171 i
.op
[op
].regs
->reg_name
,
3181 unsigned int overlap0
, overlap1
, overlap2
;
3183 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3184 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3185 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3186 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3187 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3191 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3193 : (i
.suffix
== WORD_MNEM_SUFFIX
3195 : (i
.suffix
== QWORD_MNEM_SUFFIX
3199 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3200 || overlap0
== (Imm16
| Imm32
)
3201 || overlap0
== (Imm16
| Imm32S
))
3203 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3206 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3207 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3208 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3210 as_bad (_("no instruction mnemonic suffix given; "
3211 "can't determine immediate size"));
3215 i
.types
[0] = overlap0
;
3217 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3218 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3219 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3220 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3221 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3225 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3227 : (i
.suffix
== WORD_MNEM_SUFFIX
3229 : (i
.suffix
== QWORD_MNEM_SUFFIX
3233 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3234 || overlap1
== (Imm16
| Imm32
)
3235 || overlap1
== (Imm16
| Imm32S
))
3237 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3240 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3241 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3242 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3244 as_bad (_("no instruction mnemonic suffix given; "
3245 "can't determine immediate size %x %c"),
3246 overlap1
, i
.suffix
);
3250 i
.types
[1] = overlap1
;
3252 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3253 assert ((overlap2
& Imm
) == 0);
3254 i
.types
[2] = overlap2
;
3260 process_operands (void)
3262 /* Default segment register this instruction will use for memory
3263 accesses. 0 means unknown. This is only for optimizing out
3264 unnecessary segment overrides. */
3265 const seg_entry
*default_seg
= 0;
3267 /* The imul $imm, %reg instruction is converted into
3268 imul $imm, %reg, %reg, and the clr %reg instruction
3269 is converted into xor %reg, %reg. */
3270 if (i
.tm
.opcode_modifier
& regKludge
)
3272 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3273 /* Pretend we saw the extra register operand. */
3274 assert (i
.reg_operands
== 1
3275 && i
.op
[first_reg_op
+ 1].regs
== 0);
3276 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3277 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3282 if (i
.tm
.opcode_modifier
& ShortForm
)
3284 if (i
.types
[0] & (SReg2
| SReg3
))
3286 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3287 && i
.op
[0].regs
->reg_num
== 1)
3289 as_bad (_("you can't `pop %%cs'"));
3292 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3293 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3298 /* The register or float register operand is in operand 0 or 1. */
3299 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3300 /* Register goes in low 3 bits of opcode. */
3301 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3302 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3304 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3306 /* Warn about some common errors, but press on regardless.
3307 The first case can be generated by gcc (<= 2.8.1). */
3308 if (i
.operands
== 2)
3310 /* Reversed arguments on faddp, fsubp, etc. */
3311 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3312 i
.op
[1].regs
->reg_name
,
3313 i
.op
[0].regs
->reg_name
);
3317 /* Extraneous `l' suffix on fp insn. */
3318 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3319 i
.op
[0].regs
->reg_name
);
3324 else if (i
.tm
.opcode_modifier
& Modrm
)
3326 /* The opcode is completed (modulo i.tm.extension_opcode which
3327 must be put into the modrm byte). Now, we make the modrm and
3328 index base bytes based on all the info we've collected. */
3330 default_seg
= build_modrm_byte ();
3332 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3336 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3338 /* For the string instructions that allow a segment override
3339 on one of their operands, the default segment is ds. */
3343 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3344 || (i
.tm
.cpu_flags
& CpuSVME
))
3345 && i
.seg
[0] && !quiet_warnings
)
3346 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3348 /* If a segment was explicitly specified, and the specified segment
3349 is not the default, use an opcode prefix to select it. If we
3350 never figured out what the default segment is, then default_seg
3351 will be zero at this point, and the specified segment prefix will
3353 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3355 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3361 static const seg_entry
*
3362 build_modrm_byte (void)
3364 const seg_entry
*default_seg
= 0;
3366 /* i.reg_operands MUST be the number of real register operands;
3367 implicit registers do not count. */
3368 if (i
.reg_operands
== 2)
3370 unsigned int source
, dest
;
3378 /* When there are 3 operands, one of them may be immediate,
3379 which may be the first or the last operand. Otherwise,
3380 the first operand must be shift count register (cl). */
3381 assert (i
.imm_operands
== 1
3382 || (i
.imm_operands
== 0
3383 && (i
.types
[0] & ShiftCount
)));
3384 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3387 /* When there are 4 operands, the first two must be immediate
3388 operands. The source operand will be the 3rd one. */
3389 assert (i
.imm_operands
== 2
3390 && (i
.types
[0] & Imm
)
3391 && (i
.types
[1] & Imm
));
3401 /* One of the register operands will be encoded in the i.tm.reg
3402 field, the other in the combined i.tm.mode and i.tm.regmem
3403 fields. If no form of this instruction supports a memory
3404 destination operand, then we assume the source operand may
3405 sometimes be a memory operand and so we need to store the
3406 destination in the i.rm.reg field. */
3407 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3409 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3410 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3411 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3413 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3418 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3419 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3420 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3422 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3425 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3427 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3429 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3430 add_prefix (LOCK_PREFIX_OPCODE
);
3434 { /* If it's not 2 reg operands... */
3437 unsigned int fake_zero_displacement
= 0;
3440 for (op
= 0; op
< i
.operands
; op
++)
3441 if ((i
.types
[op
] & AnyMem
))
3443 assert (op
< i
.operands
);
3447 if (i
.base_reg
== 0)
3450 if (!i
.disp_operands
)
3451 fake_zero_displacement
= 1;
3452 if (i
.index_reg
== 0)
3454 /* Operand is just <disp> */
3455 if (flag_code
== CODE_64BIT
)
3457 /* 64bit mode overwrites the 32bit absolute
3458 addressing by RIP relative addressing and
3459 absolute addressing is encoded by one of the
3460 redundant SIB forms. */
3461 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3462 i
.sib
.base
= NO_BASE_REGISTER
;
3463 i
.sib
.index
= NO_INDEX_REGISTER
;
3464 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3465 ? Disp32S
: Disp32
);
3467 else if ((flag_code
== CODE_16BIT
)
3468 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3470 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3471 i
.types
[op
] = Disp16
;
3475 i
.rm
.regmem
= NO_BASE_REGISTER
;
3476 i
.types
[op
] = Disp32
;
3479 else /* !i.base_reg && i.index_reg */
3481 i
.sib
.index
= i
.index_reg
->reg_num
;
3482 i
.sib
.base
= NO_BASE_REGISTER
;
3483 i
.sib
.scale
= i
.log2_scale_factor
;
3484 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3485 i
.types
[op
] &= ~Disp
;
3486 if (flag_code
!= CODE_64BIT
)
3487 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3489 i
.types
[op
] |= Disp32S
;
3490 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3494 /* RIP addressing for 64bit mode. */
3495 else if (i
.base_reg
->reg_type
== BaseIndex
)
3497 i
.rm
.regmem
= NO_BASE_REGISTER
;
3498 i
.types
[op
] &= ~ Disp
;
3499 i
.types
[op
] |= Disp32S
;
3500 i
.flags
[op
] |= Operand_PCrel
;
3501 if (! i
.disp_operands
)
3502 fake_zero_displacement
= 1;
3504 else if (i
.base_reg
->reg_type
& Reg16
)
3506 switch (i
.base_reg
->reg_num
)
3509 if (i
.index_reg
== 0)
3511 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3512 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3516 if (i
.index_reg
== 0)
3519 if ((i
.types
[op
] & Disp
) == 0)
3521 /* fake (%bp) into 0(%bp) */
3522 i
.types
[op
] |= Disp8
;
3523 fake_zero_displacement
= 1;
3526 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3527 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3529 default: /* (%si) -> 4 or (%di) -> 5 */
3530 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3532 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3534 else /* i.base_reg and 32/64 bit mode */
3536 if (flag_code
== CODE_64BIT
3537 && (i
.types
[op
] & Disp
))
3538 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3539 | (i
.prefix
[ADDR_PREFIX
] == 0
3540 ? Disp32S
: Disp32
));
3542 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3543 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3545 i
.sib
.base
= i
.base_reg
->reg_num
;
3546 /* x86-64 ignores REX prefix bit here to avoid decoder
3548 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3551 if (i
.disp_operands
== 0)
3553 fake_zero_displacement
= 1;
3554 i
.types
[op
] |= Disp8
;
3557 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3561 i
.sib
.scale
= i
.log2_scale_factor
;
3562 if (i
.index_reg
== 0)
3564 /* <disp>(%esp) becomes two byte modrm with no index
3565 register. We've already stored the code for esp
3566 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3567 Any base register besides %esp will not use the
3568 extra modrm byte. */
3569 i
.sib
.index
= NO_INDEX_REGISTER
;
3570 #if !SCALE1_WHEN_NO_INDEX
3571 /* Another case where we force the second modrm byte. */
3572 if (i
.log2_scale_factor
)
3573 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3578 i
.sib
.index
= i
.index_reg
->reg_num
;
3579 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3580 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3585 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3586 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3589 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3592 if (fake_zero_displacement
)
3594 /* Fakes a zero displacement assuming that i.types[op]
3595 holds the correct displacement size. */
3598 assert (i
.op
[op
].disps
== 0);
3599 exp
= &disp_expressions
[i
.disp_operands
++];
3600 i
.op
[op
].disps
= exp
;
3601 exp
->X_op
= O_constant
;
3602 exp
->X_add_number
= 0;
3603 exp
->X_add_symbol
= (symbolS
*) 0;
3604 exp
->X_op_symbol
= (symbolS
*) 0;
3608 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3609 (if any) based on i.tm.extension_opcode. Again, we must be
3610 careful to make sure that segment/control/debug/test/MMX
3611 registers are coded into the i.rm.reg field. */
3616 for (op
= 0; op
< i
.operands
; op
++)
3617 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3619 | Control
| Debug
| Test
)))
3621 assert (op
< i
.operands
);
3623 /* If there is an extension opcode to put here, the register
3624 number must be put into the regmem field. */
3625 if (i
.tm
.extension_opcode
!= None
)
3627 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3628 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3633 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3634 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3638 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3639 must set it to 3 to indicate this is a register operand
3640 in the regmem field. */
3641 if (!i
.mem_operands
)
3645 /* Fill in i.rm.reg field with extension opcode (if any). */
3646 if (i
.tm
.extension_opcode
!= None
)
3647 i
.rm
.reg
= i
.tm
.extension_opcode
;
3653 output_branch (void)
3658 relax_substateT subtype
;
3663 if (flag_code
== CODE_16BIT
)
3667 if (i
.prefix
[DATA_PREFIX
] != 0)
3673 /* Pentium4 branch hints. */
3674 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3675 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3680 if (i
.prefix
[REX_PREFIX
] != 0)
3686 if (i
.prefixes
!= 0 && !intel_syntax
)
3687 as_warn (_("skipping prefixes on this instruction"));
3689 /* It's always a symbol; End frag & setup for relax.
3690 Make sure there is enough room in this frag for the largest
3691 instruction we may generate in md_convert_frag. This is 2
3692 bytes for the opcode and room for the prefix and largest
3694 frag_grow (prefix
+ 2 + 4);
3695 /* Prefix and 1 opcode byte go in fr_fix. */
3696 p
= frag_more (prefix
+ 1);
3697 if (i
.prefix
[DATA_PREFIX
] != 0)
3698 *p
++ = DATA_PREFIX_OPCODE
;
3699 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3700 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3701 *p
++ = i
.prefix
[SEG_PREFIX
];
3702 if (i
.prefix
[REX_PREFIX
] != 0)
3703 *p
++ = i
.prefix
[REX_PREFIX
];
3704 *p
= i
.tm
.base_opcode
;
3706 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3707 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3708 else if ((cpu_arch_flags
& Cpu386
) != 0)
3709 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3711 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3714 sym
= i
.op
[0].disps
->X_add_symbol
;
3715 off
= i
.op
[0].disps
->X_add_number
;
3717 if (i
.op
[0].disps
->X_op
!= O_constant
3718 && i
.op
[0].disps
->X_op
!= O_symbol
)
3720 /* Handle complex expressions. */
3721 sym
= make_expr_symbol (i
.op
[0].disps
);
3725 /* 1 possible extra opcode + 4 byte displacement go in var part.
3726 Pass reloc in fr_var. */
3727 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3737 if (i
.tm
.opcode_modifier
& JumpByte
)
3739 /* This is a loop or jecxz type instruction. */
3741 if (i
.prefix
[ADDR_PREFIX
] != 0)
3743 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3746 /* Pentium4 branch hints. */
3747 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3748 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3750 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3759 if (flag_code
== CODE_16BIT
)
3762 if (i
.prefix
[DATA_PREFIX
] != 0)
3764 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3774 if (i
.prefix
[REX_PREFIX
] != 0)
3776 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3780 if (i
.prefixes
!= 0 && !intel_syntax
)
3781 as_warn (_("skipping prefixes on this instruction"));
3783 p
= frag_more (1 + size
);
3784 *p
++ = i
.tm
.base_opcode
;
3786 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3787 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3789 /* All jumps handled here are signed, but don't use a signed limit
3790 check for 32 and 16 bit jumps as we want to allow wrap around at
3791 4G and 64k respectively. */
3793 fixP
->fx_signed
= 1;
3797 output_interseg_jump (void)
3805 if (flag_code
== CODE_16BIT
)
3809 if (i
.prefix
[DATA_PREFIX
] != 0)
3815 if (i
.prefix
[REX_PREFIX
] != 0)
3825 if (i
.prefixes
!= 0 && !intel_syntax
)
3826 as_warn (_("skipping prefixes on this instruction"));
3828 /* 1 opcode; 2 segment; offset */
3829 p
= frag_more (prefix
+ 1 + 2 + size
);
3831 if (i
.prefix
[DATA_PREFIX
] != 0)
3832 *p
++ = DATA_PREFIX_OPCODE
;
3834 if (i
.prefix
[REX_PREFIX
] != 0)
3835 *p
++ = i
.prefix
[REX_PREFIX
];
3837 *p
++ = i
.tm
.base_opcode
;
3838 if (i
.op
[1].imms
->X_op
== O_constant
)
3840 offsetT n
= i
.op
[1].imms
->X_add_number
;
3843 && !fits_in_unsigned_word (n
)
3844 && !fits_in_signed_word (n
))
3846 as_bad (_("16-bit jump out of range"));
3849 md_number_to_chars (p
, n
, size
);
3852 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3853 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3854 if (i
.op
[0].imms
->X_op
!= O_constant
)
3855 as_bad (_("can't handle non absolute segment in `%s'"),
3857 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3863 fragS
*insn_start_frag
;
3864 offsetT insn_start_off
;
3866 /* Tie dwarf2 debug info to the address at the start of the insn.
3867 We can't do this after the insn has been output as the current
3868 frag may have been closed off. eg. by frag_var. */
3869 dwarf2_emit_insn (0);
3871 insn_start_frag
= frag_now
;
3872 insn_start_off
= frag_now_fix ();
3875 if (i
.tm
.opcode_modifier
& Jump
)
3877 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3879 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3880 output_interseg_jump ();
3883 /* Output normal instructions here. */
3886 unsigned int prefix
;
3888 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3889 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3890 use one more higher byte to specify a prefix the instruction
3892 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3894 if (i
.tm
.base_opcode
& 0xff000000)
3896 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3900 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3902 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3903 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3906 if (prefix
!= REPE_PREFIX_OPCODE
3907 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3908 add_prefix (prefix
);
3911 add_prefix (prefix
);
3914 /* The prefix bytes. */
3916 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3922 md_number_to_chars (p
, (valueT
) *q
, 1);
3926 /* Now the opcode; be careful about word order here! */
3927 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3929 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3933 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3936 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3941 /* Put out high byte first: can't use md_number_to_chars! */
3942 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3943 *p
= i
.tm
.base_opcode
& 0xff;
3946 /* Now the modrm byte and sib byte (if present). */
3947 if (i
.tm
.opcode_modifier
& Modrm
)
3950 md_number_to_chars (p
,
3951 (valueT
) (i
.rm
.regmem
<< 0
3955 /* If i.rm.regmem == ESP (4)
3956 && i.rm.mode != (Register mode)
3958 ==> need second modrm byte. */
3959 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3961 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3964 md_number_to_chars (p
,
3965 (valueT
) (i
.sib
.base
<< 0
3967 | i
.sib
.scale
<< 6),
3972 if (i
.disp_operands
)
3973 output_disp (insn_start_frag
, insn_start_off
);
3976 output_imm (insn_start_frag
, insn_start_off
);
3982 pi ("" /*line*/, &i
);
3984 #endif /* DEBUG386 */
3988 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
3993 for (n
= 0; n
< i
.operands
; n
++)
3995 if (i
.types
[n
] & Disp
)
3997 if (i
.op
[n
].disps
->X_op
== O_constant
)
4003 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4006 if (i
.types
[n
] & Disp8
)
4008 if (i
.types
[n
] & Disp64
)
4011 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4013 p
= frag_more (size
);
4014 md_number_to_chars (p
, val
, size
);
4018 enum bfd_reloc_code_real reloc_type
;
4021 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4023 /* The PC relative address is computed relative
4024 to the instruction boundary, so in case immediate
4025 fields follows, we need to adjust the value. */
4026 if (pcrel
&& i
.imm_operands
)
4031 for (n1
= 0; n1
< i
.operands
; n1
++)
4032 if (i
.types
[n1
] & Imm
)
4034 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4037 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4039 if (i
.types
[n1
] & Imm64
)
4044 /* We should find the immediate. */
4045 if (n1
== i
.operands
)
4047 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4050 if (i
.types
[n
] & Disp32S
)
4053 if (i
.types
[n
] & (Disp16
| Disp64
))
4056 if (i
.types
[n
] & Disp64
)
4060 p
= frag_more (size
);
4061 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4063 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4064 && (((reloc_type
== BFD_RELOC_32
4065 || reloc_type
== BFD_RELOC_X86_64_32S
4066 || (reloc_type
== BFD_RELOC_64
4068 && (i
.op
[n
].disps
->X_op
== O_symbol
4069 || (i
.op
[n
].disps
->X_op
== O_add
4070 && ((symbol_get_value_expression
4071 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4073 || reloc_type
== BFD_RELOC_32_PCREL
))
4077 if (insn_start_frag
== frag_now
)
4078 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4083 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4084 for (fr
= insn_start_frag
->fr_next
;
4085 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4087 add
+= p
- frag_now
->fr_literal
;
4092 reloc_type
= BFD_RELOC_386_GOTPC
;
4093 i
.op
[n
].imms
->X_add_number
+= add
;
4095 else if (reloc_type
== BFD_RELOC_64
)
4096 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4098 /* Don't do the adjustment for x86-64, as there
4099 the pcrel addressing is relative to the _next_
4100 insn, and that is taken care of in other code. */
4101 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4103 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4104 i
.op
[n
].disps
, pcrel
, reloc_type
);
4111 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4116 for (n
= 0; n
< i
.operands
; n
++)
4118 if (i
.types
[n
] & Imm
)
4120 if (i
.op
[n
].imms
->X_op
== O_constant
)
4126 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4129 if (i
.types
[n
] & (Imm8
| Imm8S
))
4131 else if (i
.types
[n
] & Imm64
)
4134 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4136 p
= frag_more (size
);
4137 md_number_to_chars (p
, val
, size
);
4141 /* Not absolute_section.
4142 Need a 32-bit fixup (don't support 8bit
4143 non-absolute imms). Try to support other
4145 enum bfd_reloc_code_real reloc_type
;
4149 if ((i
.types
[n
] & (Imm32S
))
4150 && (i
.suffix
== QWORD_MNEM_SUFFIX
4151 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4153 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4156 if (i
.types
[n
] & (Imm8
| Imm8S
))
4158 if (i
.types
[n
] & Imm64
)
4162 p
= frag_more (size
);
4163 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4165 /* This is tough to explain. We end up with this one if we
4166 * have operands that look like
4167 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4168 * obtain the absolute address of the GOT, and it is strongly
4169 * preferable from a performance point of view to avoid using
4170 * a runtime relocation for this. The actual sequence of
4171 * instructions often look something like:
4176 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4178 * The call and pop essentially return the absolute address
4179 * of the label .L66 and store it in %ebx. The linker itself
4180 * will ultimately change the first operand of the addl so
4181 * that %ebx points to the GOT, but to keep things simple, the
4182 * .o file must have this operand set so that it generates not
4183 * the absolute address of .L66, but the absolute address of
4184 * itself. This allows the linker itself simply treat a GOTPC
4185 * relocation as asking for a pcrel offset to the GOT to be
4186 * added in, and the addend of the relocation is stored in the
4187 * operand field for the instruction itself.
4189 * Our job here is to fix the operand so that it would add
4190 * the correct offset so that %ebx would point to itself. The
4191 * thing that is tricky is that .-.L66 will point to the
4192 * beginning of the instruction, so we need to further modify
4193 * the operand so that it will point to itself. There are
4194 * other cases where you have something like:
4196 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4198 * and here no correction would be required. Internally in
4199 * the assembler we treat operands of this form as not being
4200 * pcrel since the '.' is explicitly mentioned, and I wonder
4201 * whether it would simplify matters to do it this way. Who
4202 * knows. In earlier versions of the PIC patches, the
4203 * pcrel_adjust field was used to store the correction, but
4204 * since the expression is not pcrel, I felt it would be
4205 * confusing to do it this way. */
4207 if ((reloc_type
== BFD_RELOC_32
4208 || reloc_type
== BFD_RELOC_X86_64_32S
4209 || reloc_type
== BFD_RELOC_64
)
4211 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4212 && (i
.op
[n
].imms
->X_op
== O_symbol
4213 || (i
.op
[n
].imms
->X_op
== O_add
4214 && ((symbol_get_value_expression
4215 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4220 if (insn_start_frag
== frag_now
)
4221 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4226 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4227 for (fr
= insn_start_frag
->fr_next
;
4228 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4230 add
+= p
- frag_now
->fr_literal
;
4234 reloc_type
= BFD_RELOC_386_GOTPC
;
4236 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4238 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4239 i
.op
[n
].imms
->X_add_number
+= add
;
4241 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4242 i
.op
[n
].imms
, 0, reloc_type
);
4248 /* x86_cons_fix_new is called via the expression parsing code when a
4249 reloc is needed. We use this hook to get the correct .got reloc. */
4250 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4251 static int cons_sign
= -1;
4254 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4257 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4259 got_reloc
= NO_RELOC
;
4262 if (exp
->X_op
== O_secrel
)
4264 exp
->X_op
= O_symbol
;
4265 r
= BFD_RELOC_32_SECREL
;
4269 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4272 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4273 # define lex_got(reloc, adjust, types) NULL
4275 /* Parse operands of the form
4276 <symbol>@GOTOFF+<nnn>
4277 and similar .plt or .got references.
4279 If we find one, set up the correct relocation in RELOC and copy the
4280 input string, minus the `@GOTOFF' into a malloc'd buffer for
4281 parsing by the calling routine. Return this buffer, and if ADJUST
4282 is non-null set it to the length of the string we removed from the
4283 input line. Otherwise return NULL. */
4285 lex_got (enum bfd_reloc_code_real
*reloc
,
4287 unsigned int *types
)
4289 /* Some of the relocations depend on the size of what field is to
4290 be relocated. But in our callers i386_immediate and i386_displacement
4291 we don't yet know the operand size (this will be set by insn
4292 matching). Hence we record the word32 relocation here,
4293 and adjust the reloc according to the real size in reloc(). */
4294 static const struct {
4296 const enum bfd_reloc_code_real rel
[2];
4297 const unsigned int types64
;
4300 BFD_RELOC_X86_64_PLTOFF64
},
4302 { "PLT", { BFD_RELOC_386_PLT32
,
4303 BFD_RELOC_X86_64_PLT32
},
4304 Imm32
| Imm32S
| Disp32
},
4306 BFD_RELOC_X86_64_GOTPLT64
},
4308 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4309 BFD_RELOC_X86_64_GOTOFF64
},
4312 BFD_RELOC_X86_64_GOTPCREL
},
4313 Imm32
| Imm32S
| Disp32
},
4314 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4315 BFD_RELOC_X86_64_TLSGD
},
4316 Imm32
| Imm32S
| Disp32
},
4317 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4321 BFD_RELOC_X86_64_TLSLD
},
4322 Imm32
| Imm32S
| Disp32
},
4323 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4324 BFD_RELOC_X86_64_GOTTPOFF
},
4325 Imm32
| Imm32S
| Disp32
},
4326 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4327 BFD_RELOC_X86_64_TPOFF32
},
4328 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4329 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4332 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4333 BFD_RELOC_X86_64_DTPOFF32
},
4334 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4335 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4338 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4341 { "GOT", { BFD_RELOC_386_GOT32
,
4342 BFD_RELOC_X86_64_GOT32
},
4343 Imm32
| Imm32S
| Disp32
| Imm64
},
4344 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4345 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4346 Imm32
| Imm32S
| Disp32
},
4347 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4348 BFD_RELOC_X86_64_TLSDESC_CALL
},
4349 Imm32
| Imm32S
| Disp32
}
4357 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4358 if (is_end_of_line
[(unsigned char) *cp
])
4361 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4365 len
= strlen (gotrel
[j
].str
);
4366 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4368 if (gotrel
[j
].rel
[object_64bit
] != 0)
4371 char *tmpbuf
, *past_reloc
;
4373 *reloc
= gotrel
[j
].rel
[object_64bit
];
4379 if (flag_code
!= CODE_64BIT
)
4380 *types
= Imm32
| Disp32
;
4382 *types
= gotrel
[j
].types64
;
4385 if (GOT_symbol
== NULL
)
4386 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4388 /* Replace the relocation token with ' ', so that
4389 errors like foo@GOTOFF1 will be detected. */
4391 /* The length of the first part of our input line. */
4392 first
= cp
- input_line_pointer
;
4394 /* The second part goes from after the reloc token until
4395 (and including) an end_of_line char. Don't use strlen
4396 here as the end_of_line char may not be a NUL. */
4397 past_reloc
= cp
+ 1 + len
;
4398 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4400 second
= cp
- past_reloc
;
4402 /* Allocate and copy string. The trailing NUL shouldn't
4403 be necessary, but be safe. */
4404 tmpbuf
= xmalloc (first
+ second
+ 2);
4405 memcpy (tmpbuf
, input_line_pointer
, first
);
4406 tmpbuf
[first
] = ' ';
4407 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4408 tmpbuf
[first
+ second
+ 1] = '\0';
4412 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4413 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4418 /* Might be a symbol version string. Don't as_bad here. */
4423 x86_cons (expressionS
*exp
, int size
)
4425 if (size
== 4 || (object_64bit
&& size
== 8))
4427 /* Handle @GOTOFF and the like in an expression. */
4429 char *gotfree_input_line
;
4432 save
= input_line_pointer
;
4433 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4434 if (gotfree_input_line
)
4435 input_line_pointer
= gotfree_input_line
;
4439 if (gotfree_input_line
)
4441 /* expression () has merrily parsed up to the end of line,
4442 or a comma - in the wrong buffer. Transfer how far
4443 input_line_pointer has moved to the right buffer. */
4444 input_line_pointer
= (save
4445 + (input_line_pointer
- gotfree_input_line
)
4447 free (gotfree_input_line
);
4455 static void signed_cons (int size
)
4457 if (flag_code
== CODE_64BIT
)
4465 pe_directive_secrel (dummy
)
4466 int dummy ATTRIBUTE_UNUSED
;
4473 if (exp
.X_op
== O_symbol
)
4474 exp
.X_op
= O_secrel
;
4476 emit_expr (&exp
, 4);
4478 while (*input_line_pointer
++ == ',');
4480 input_line_pointer
--;
4481 demand_empty_rest_of_line ();
4486 i386_immediate (char *imm_start
)
4488 char *save_input_line_pointer
;
4489 char *gotfree_input_line
;
4492 unsigned int types
= ~0U;
4494 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4496 as_bad (_("at most %d immediate operands are allowed"),
4497 MAX_IMMEDIATE_OPERANDS
);
4501 exp
= &im_expressions
[i
.imm_operands
++];
4502 i
.op
[this_operand
].imms
= exp
;
4504 if (is_space_char (*imm_start
))
4507 save_input_line_pointer
= input_line_pointer
;
4508 input_line_pointer
= imm_start
;
4510 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4511 if (gotfree_input_line
)
4512 input_line_pointer
= gotfree_input_line
;
4514 exp_seg
= expression (exp
);
4517 if (*input_line_pointer
)
4518 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4520 input_line_pointer
= save_input_line_pointer
;
4521 if (gotfree_input_line
)
4522 free (gotfree_input_line
);
4524 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4526 /* Missing or bad expr becomes absolute 0. */
4527 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4529 exp
->X_op
= O_constant
;
4530 exp
->X_add_number
= 0;
4531 exp
->X_add_symbol
= (symbolS
*) 0;
4532 exp
->X_op_symbol
= (symbolS
*) 0;
4534 else if (exp
->X_op
== O_constant
)
4536 /* Size it properly later. */
4537 i
.types
[this_operand
] |= Imm64
;
4538 /* If BFD64, sign extend val. */
4539 if (!use_rela_relocations
4540 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4542 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4544 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4545 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4546 && exp_seg
!= absolute_section
4547 && exp_seg
!= text_section
4548 && exp_seg
!= data_section
4549 && exp_seg
!= bss_section
4550 && exp_seg
!= undefined_section
4551 && !bfd_is_com_section (exp_seg
))
4553 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4557 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4559 as_bad (_("illegal immediate register operand %s"), imm_start
);
4564 /* This is an address. The size of the address will be
4565 determined later, depending on destination register,
4566 suffix, or the default for the section. */
4567 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4568 i
.types
[this_operand
] &= types
;
4575 i386_scale (char *scale
)
4578 char *save
= input_line_pointer
;
4580 input_line_pointer
= scale
;
4581 val
= get_absolute_expression ();
4586 i
.log2_scale_factor
= 0;
4589 i
.log2_scale_factor
= 1;
4592 i
.log2_scale_factor
= 2;
4595 i
.log2_scale_factor
= 3;
4599 char sep
= *input_line_pointer
;
4601 *input_line_pointer
= '\0';
4602 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4604 *input_line_pointer
= sep
;
4605 input_line_pointer
= save
;
4609 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4611 as_warn (_("scale factor of %d without an index register"),
4612 1 << i
.log2_scale_factor
);
4613 #if SCALE1_WHEN_NO_INDEX
4614 i
.log2_scale_factor
= 0;
4617 scale
= input_line_pointer
;
4618 input_line_pointer
= save
;
4623 i386_displacement (char *disp_start
, char *disp_end
)
4627 char *save_input_line_pointer
;
4628 char *gotfree_input_line
;
4629 int bigdisp
, override
;
4630 unsigned int types
= Disp
;
4632 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4634 as_bad (_("at most %d displacement operands are allowed"),
4635 MAX_MEMORY_OPERANDS
);
4639 if ((i
.types
[this_operand
] & JumpAbsolute
)
4640 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4643 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4647 /* For PC-relative branches, the width of the displacement
4648 is dependent upon data size, not address size. */
4650 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4652 if (flag_code
== CODE_64BIT
)
4655 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4657 : Disp32S
| Disp32
);
4659 bigdisp
= Disp64
| Disp32S
| Disp32
;
4666 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4668 : LONG_MNEM_SUFFIX
));
4671 if ((flag_code
== CODE_16BIT
) ^ override
)
4674 i
.types
[this_operand
] |= bigdisp
;
4676 exp
= &disp_expressions
[i
.disp_operands
];
4677 i
.op
[this_operand
].disps
= exp
;
4679 save_input_line_pointer
= input_line_pointer
;
4680 input_line_pointer
= disp_start
;
4681 END_STRING_AND_SAVE (disp_end
);
4683 #ifndef GCC_ASM_O_HACK
4684 #define GCC_ASM_O_HACK 0
4687 END_STRING_AND_SAVE (disp_end
+ 1);
4688 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4689 && displacement_string_end
[-1] == '+')
4691 /* This hack is to avoid a warning when using the "o"
4692 constraint within gcc asm statements.
4695 #define _set_tssldt_desc(n,addr,limit,type) \
4696 __asm__ __volatile__ ( \
4698 "movw %w1,2+%0\n\t" \
4700 "movb %b1,4+%0\n\t" \
4701 "movb %4,5+%0\n\t" \
4702 "movb $0,6+%0\n\t" \
4703 "movb %h1,7+%0\n\t" \
4705 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4707 This works great except that the output assembler ends
4708 up looking a bit weird if it turns out that there is
4709 no offset. You end up producing code that looks like:
4722 So here we provide the missing zero. */
4724 *displacement_string_end
= '0';
4727 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4728 if (gotfree_input_line
)
4729 input_line_pointer
= gotfree_input_line
;
4731 exp_seg
= expression (exp
);
4734 if (*input_line_pointer
)
4735 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4737 RESTORE_END_STRING (disp_end
+ 1);
4739 RESTORE_END_STRING (disp_end
);
4740 input_line_pointer
= save_input_line_pointer
;
4741 if (gotfree_input_line
)
4742 free (gotfree_input_line
);
4744 /* We do this to make sure that the section symbol is in
4745 the symbol table. We will ultimately change the relocation
4746 to be relative to the beginning of the section. */
4747 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4748 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4749 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4751 if (exp
->X_op
!= O_symbol
)
4753 as_bad (_("bad expression used with @%s"),
4754 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4760 if (S_IS_LOCAL (exp
->X_add_symbol
)
4761 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4762 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4763 exp
->X_op
= O_subtract
;
4764 exp
->X_op_symbol
= GOT_symbol
;
4765 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4766 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4767 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4768 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4770 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4773 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4775 /* Missing or bad expr becomes absolute 0. */
4776 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4778 exp
->X_op
= O_constant
;
4779 exp
->X_add_number
= 0;
4780 exp
->X_add_symbol
= (symbolS
*) 0;
4781 exp
->X_op_symbol
= (symbolS
*) 0;
4784 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4785 if (exp
->X_op
!= O_constant
4786 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4787 && exp_seg
!= absolute_section
4788 && exp_seg
!= text_section
4789 && exp_seg
!= data_section
4790 && exp_seg
!= bss_section
4791 && exp_seg
!= undefined_section
4792 && !bfd_is_com_section (exp_seg
))
4794 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4799 if (!(i
.types
[this_operand
] & ~Disp
))
4800 i
.types
[this_operand
] &= types
;
4805 /* Make sure the memory operand we've been dealt is valid.
4806 Return 1 on success, 0 on a failure. */
4809 i386_index_check (const char *operand_string
)
4812 #if INFER_ADDR_PREFIX
4818 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4819 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4821 /* Memory operands of SVME insns are special in that they only allow
4822 rAX as their memory address and ignore any segment override. */
4825 /* SKINIT is even more restrictive: it always requires EAX. */
4826 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4828 else if (flag_code
== CODE_64BIT
)
4829 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4831 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4835 || !(i
.base_reg
->reg_type
& Acc
)
4836 || !(i
.base_reg
->reg_type
& RegXX
)
4838 || (i
.types
[0] & Disp
))
4841 else if (flag_code
== CODE_64BIT
)
4843 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4846 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4847 && (i
.base_reg
->reg_type
!= BaseIndex
4850 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4851 != (RegXX
| BaseIndex
))))
4856 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4860 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4861 != (Reg16
| BaseIndex
)))
4863 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4864 != (Reg16
| BaseIndex
))
4866 && i
.base_reg
->reg_num
< 6
4867 && i
.index_reg
->reg_num
>= 6
4868 && i
.log2_scale_factor
== 0))))
4875 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4877 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4878 != (Reg32
| BaseIndex
))))
4884 #if INFER_ADDR_PREFIX
4885 if (i
.prefix
[ADDR_PREFIX
] == 0)
4887 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4889 /* Change the size of any displacement too. At most one of
4890 Disp16 or Disp32 is set.
4891 FIXME. There doesn't seem to be any real need for separate
4892 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4893 Removing them would probably clean up the code quite a lot. */
4894 if (flag_code
!= CODE_64BIT
4895 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4896 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4901 as_bad (_("`%s' is not a valid base/index expression"),
4905 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4907 flag_code_names
[flag_code
]);
4912 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4916 i386_operand (char *operand_string
)
4920 char *op_string
= operand_string
;
4922 if (is_space_char (*op_string
))
4925 /* We check for an absolute prefix (differentiating,
4926 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4927 if (*op_string
== ABSOLUTE_PREFIX
)
4930 if (is_space_char (*op_string
))
4932 i
.types
[this_operand
] |= JumpAbsolute
;
4935 /* Check if operand is a register. */
4936 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4938 /* Check for a segment override by searching for ':' after a
4939 segment register. */
4941 if (is_space_char (*op_string
))
4943 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4948 i
.seg
[i
.mem_operands
] = &es
;
4951 i
.seg
[i
.mem_operands
] = &cs
;
4954 i
.seg
[i
.mem_operands
] = &ss
;
4957 i
.seg
[i
.mem_operands
] = &ds
;
4960 i
.seg
[i
.mem_operands
] = &fs
;
4963 i
.seg
[i
.mem_operands
] = &gs
;
4967 /* Skip the ':' and whitespace. */
4969 if (is_space_char (*op_string
))
4972 if (!is_digit_char (*op_string
)
4973 && !is_identifier_char (*op_string
)
4974 && *op_string
!= '('
4975 && *op_string
!= ABSOLUTE_PREFIX
)
4977 as_bad (_("bad memory operand `%s'"), op_string
);
4980 /* Handle case of %es:*foo. */
4981 if (*op_string
== ABSOLUTE_PREFIX
)
4984 if (is_space_char (*op_string
))
4986 i
.types
[this_operand
] |= JumpAbsolute
;
4988 goto do_memory_reference
;
4992 as_bad (_("junk `%s' after register"), op_string
);
4995 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4996 i
.op
[this_operand
].regs
= r
;
4999 else if (*op_string
== REGISTER_PREFIX
)
5001 as_bad (_("bad register name `%s'"), op_string
);
5004 else if (*op_string
== IMMEDIATE_PREFIX
)
5007 if (i
.types
[this_operand
] & JumpAbsolute
)
5009 as_bad (_("immediate operand illegal with absolute jump"));
5012 if (!i386_immediate (op_string
))
5015 else if (is_digit_char (*op_string
)
5016 || is_identifier_char (*op_string
)
5017 || *op_string
== '(')
5019 /* This is a memory reference of some sort. */
5022 /* Start and end of displacement string expression (if found). */
5023 char *displacement_string_start
;
5024 char *displacement_string_end
;
5026 do_memory_reference
:
5027 if ((i
.mem_operands
== 1
5028 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5029 || i
.mem_operands
== 2)
5031 as_bad (_("too many memory references for `%s'"),
5032 current_templates
->start
->name
);
5036 /* Check for base index form. We detect the base index form by
5037 looking for an ')' at the end of the operand, searching
5038 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5040 base_string
= op_string
+ strlen (op_string
);
5043 if (is_space_char (*base_string
))
5046 /* If we only have a displacement, set-up for it to be parsed later. */
5047 displacement_string_start
= op_string
;
5048 displacement_string_end
= base_string
+ 1;
5050 if (*base_string
== ')')
5053 unsigned int parens_balanced
= 1;
5054 /* We've already checked that the number of left & right ()'s are
5055 equal, so this loop will not be infinite. */
5059 if (*base_string
== ')')
5061 if (*base_string
== '(')
5064 while (parens_balanced
);
5066 temp_string
= base_string
;
5068 /* Skip past '(' and whitespace. */
5070 if (is_space_char (*base_string
))
5073 if (*base_string
== ','
5074 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5077 displacement_string_end
= temp_string
;
5079 i
.types
[this_operand
] |= BaseIndex
;
5083 base_string
= end_op
;
5084 if (is_space_char (*base_string
))
5088 /* There may be an index reg or scale factor here. */
5089 if (*base_string
== ',')
5092 if (is_space_char (*base_string
))
5095 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5098 base_string
= end_op
;
5099 if (is_space_char (*base_string
))
5101 if (*base_string
== ',')
5104 if (is_space_char (*base_string
))
5107 else if (*base_string
!= ')')
5109 as_bad (_("expecting `,' or `)' "
5110 "after index register in `%s'"),
5115 else if (*base_string
== REGISTER_PREFIX
)
5117 as_bad (_("bad register name `%s'"), base_string
);
5121 /* Check for scale factor. */
5122 if (*base_string
!= ')')
5124 char *end_scale
= i386_scale (base_string
);
5129 base_string
= end_scale
;
5130 if (is_space_char (*base_string
))
5132 if (*base_string
!= ')')
5134 as_bad (_("expecting `)' "
5135 "after scale factor in `%s'"),
5140 else if (!i
.index_reg
)
5142 as_bad (_("expecting index register or scale factor "
5143 "after `,'; got '%c'"),
5148 else if (*base_string
!= ')')
5150 as_bad (_("expecting `,' or `)' "
5151 "after base register in `%s'"),
5156 else if (*base_string
== REGISTER_PREFIX
)
5158 as_bad (_("bad register name `%s'"), base_string
);
5163 /* If there's an expression beginning the operand, parse it,
5164 assuming displacement_string_start and
5165 displacement_string_end are meaningful. */
5166 if (displacement_string_start
!= displacement_string_end
)
5168 if (!i386_displacement (displacement_string_start
,
5169 displacement_string_end
))
5173 /* Special case for (%dx) while doing input/output op. */
5175 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5177 && i
.log2_scale_factor
== 0
5178 && i
.seg
[i
.mem_operands
] == 0
5179 && (i
.types
[this_operand
] & Disp
) == 0)
5181 i
.types
[this_operand
] = InOutPortReg
;
5185 if (i386_index_check (operand_string
) == 0)
5191 /* It's not a memory operand; argh! */
5192 as_bad (_("invalid char %s beginning operand %d `%s'"),
5193 output_invalid (*op_string
),
5198 return 1; /* Normal return. */
5201 /* md_estimate_size_before_relax()
5203 Called just before relax() for rs_machine_dependent frags. The x86
5204 assembler uses these frags to handle variable size jump
5207 Any symbol that is now undefined will not become defined.
5208 Return the correct fr_subtype in the frag.
5209 Return the initial "guess for variable size of frag" to caller.
5210 The guess is actually the growth beyond the fixed part. Whatever
5211 we do to grow the fixed or variable part contributes to our
5215 md_estimate_size_before_relax (fragP
, segment
)
5219 /* We've already got fragP->fr_subtype right; all we have to do is
5220 check for un-relaxable symbols. On an ELF system, we can't relax
5221 an externally visible symbol, because it may be overridden by a
5223 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5224 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5226 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5227 || S_IS_WEAK (fragP
->fr_symbol
)))
5231 /* Symbol is undefined in this segment, or we need to keep a
5232 reloc so that weak symbols can be overridden. */
5233 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5234 enum bfd_reloc_code_real reloc_type
;
5235 unsigned char *opcode
;
5238 if (fragP
->fr_var
!= NO_RELOC
)
5239 reloc_type
= fragP
->fr_var
;
5241 reloc_type
= BFD_RELOC_16_PCREL
;
5243 reloc_type
= BFD_RELOC_32_PCREL
;
5245 old_fr_fix
= fragP
->fr_fix
;
5246 opcode
= (unsigned char *) fragP
->fr_opcode
;
5248 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5251 /* Make jmp (0xeb) a (d)word displacement jump. */
5253 fragP
->fr_fix
+= size
;
5254 fix_new (fragP
, old_fr_fix
, size
,
5256 fragP
->fr_offset
, 1,
5262 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5264 /* Negate the condition, and branch past an
5265 unconditional jump. */
5268 /* Insert an unconditional jump. */
5270 /* We added two extra opcode bytes, and have a two byte
5272 fragP
->fr_fix
+= 2 + 2;
5273 fix_new (fragP
, old_fr_fix
+ 2, 2,
5275 fragP
->fr_offset
, 1,
5282 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5287 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5289 fragP
->fr_offset
, 1,
5291 fixP
->fx_signed
= 1;
5295 /* This changes the byte-displacement jump 0x7N
5296 to the (d)word-displacement jump 0x0f,0x8N. */
5297 opcode
[1] = opcode
[0] + 0x10;
5298 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5299 /* We've added an opcode byte. */
5300 fragP
->fr_fix
+= 1 + size
;
5301 fix_new (fragP
, old_fr_fix
+ 1, size
,
5303 fragP
->fr_offset
, 1,
5308 BAD_CASE (fragP
->fr_subtype
);
5312 return fragP
->fr_fix
- old_fr_fix
;
5315 /* Guess size depending on current relax state. Initially the relax
5316 state will correspond to a short jump and we return 1, because
5317 the variable part of the frag (the branch offset) is one byte
5318 long. However, we can relax a section more than once and in that
5319 case we must either set fr_subtype back to the unrelaxed state,
5320 or return the value for the appropriate branch. */
5321 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5324 /* Called after relax() is finished.
5326 In: Address of frag.
5327 fr_type == rs_machine_dependent.
5328 fr_subtype is what the address relaxed to.
5330 Out: Any fixSs and constants are set up.
5331 Caller will turn frag into a ".space 0". */
5334 md_convert_frag (abfd
, sec
, fragP
)
5335 bfd
*abfd ATTRIBUTE_UNUSED
;
5336 segT sec ATTRIBUTE_UNUSED
;
5339 unsigned char *opcode
;
5340 unsigned char *where_to_put_displacement
= NULL
;
5341 offsetT target_address
;
5342 offsetT opcode_address
;
5343 unsigned int extension
= 0;
5344 offsetT displacement_from_opcode_start
;
5346 opcode
= (unsigned char *) fragP
->fr_opcode
;
5348 /* Address we want to reach in file space. */
5349 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5351 /* Address opcode resides at in file space. */
5352 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5354 /* Displacement from opcode start to fill into instruction. */
5355 displacement_from_opcode_start
= target_address
- opcode_address
;
5357 if ((fragP
->fr_subtype
& BIG
) == 0)
5359 /* Don't have to change opcode. */
5360 extension
= 1; /* 1 opcode + 1 displacement */
5361 where_to_put_displacement
= &opcode
[1];
5365 if (no_cond_jump_promotion
5366 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5367 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5368 _("long jump required"));
5370 switch (fragP
->fr_subtype
)
5372 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5373 extension
= 4; /* 1 opcode + 4 displacement */
5375 where_to_put_displacement
= &opcode
[1];
5378 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5379 extension
= 2; /* 1 opcode + 2 displacement */
5381 where_to_put_displacement
= &opcode
[1];
5384 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5385 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5386 extension
= 5; /* 2 opcode + 4 displacement */
5387 opcode
[1] = opcode
[0] + 0x10;
5388 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5389 where_to_put_displacement
= &opcode
[2];
5392 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5393 extension
= 3; /* 2 opcode + 2 displacement */
5394 opcode
[1] = opcode
[0] + 0x10;
5395 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5396 where_to_put_displacement
= &opcode
[2];
5399 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5404 where_to_put_displacement
= &opcode
[3];
5408 BAD_CASE (fragP
->fr_subtype
);
5413 /* If size if less then four we are sure that the operand fits,
5414 but if it's 4, then it could be that the displacement is larger
5416 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5418 && ((addressT
) (displacement_from_opcode_start
- extension
5419 + ((addressT
) 1 << 31))
5420 > (((addressT
) 2 << 31) - 1)))
5422 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5423 _("jump target out of range"));
5424 /* Make us emit 0. */
5425 displacement_from_opcode_start
= extension
;
5427 /* Now put displacement after opcode. */
5428 md_number_to_chars ((char *) where_to_put_displacement
,
5429 (valueT
) (displacement_from_opcode_start
- extension
),
5430 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5431 fragP
->fr_fix
+= extension
;
5434 /* Size of byte displacement jmp. */
5435 int md_short_jump_size
= 2;
5437 /* Size of dword displacement jmp. */
5438 int md_long_jump_size
= 5;
5441 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5443 addressT from_addr
, to_addr
;
5444 fragS
*frag ATTRIBUTE_UNUSED
;
5445 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5449 offset
= to_addr
- (from_addr
+ 2);
5450 /* Opcode for byte-disp jump. */
5451 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5452 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5456 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5458 addressT from_addr
, to_addr
;
5459 fragS
*frag ATTRIBUTE_UNUSED
;
5460 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5464 offset
= to_addr
- (from_addr
+ 5);
5465 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5466 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5469 /* Apply a fixup (fixS) to segment data, once it has been determined
5470 by our caller that we have all the info we need to fix it up.
5472 On the 386, immediates, displacements, and data pointers are all in
5473 the same (little-endian) format, so we don't need to care about which
5477 md_apply_fix (fixP
, valP
, seg
)
5478 /* The fix we're to put in. */
5480 /* Pointer to the value of the bits. */
5482 /* Segment fix is from. */
5483 segT seg ATTRIBUTE_UNUSED
;
5485 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5486 valueT value
= *valP
;
5488 #if !defined (TE_Mach)
5491 switch (fixP
->fx_r_type
)
5497 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5500 case BFD_RELOC_X86_64_32S
:
5501 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5504 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5507 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5512 if (fixP
->fx_addsy
!= NULL
5513 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5514 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5515 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5516 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5517 && !use_rela_relocations
)
5519 /* This is a hack. There should be a better way to handle this.
5520 This covers for the fact that bfd_install_relocation will
5521 subtract the current location (for partial_inplace, PC relative
5522 relocations); see more below. */
5526 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5529 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5534 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5537 || (symbol_section_p (fixP
->fx_addsy
)
5538 && sym_seg
!= absolute_section
))
5539 && !generic_force_reloc (fixP
))
5541 /* Yes, we add the values in twice. This is because
5542 bfd_install_relocation subtracts them out again. I think
5543 bfd_install_relocation is broken, but I don't dare change
5545 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5549 #if defined (OBJ_COFF) && defined (TE_PE)
5550 /* For some reason, the PE format does not store a
5551 section address offset for a PC relative symbol. */
5552 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5553 || S_IS_WEAK (fixP
->fx_addsy
))
5554 value
+= md_pcrel_from (fixP
);
5558 /* Fix a few things - the dynamic linker expects certain values here,
5559 and we must not disappoint it. */
5560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5561 if (IS_ELF
&& fixP
->fx_addsy
)
5562 switch (fixP
->fx_r_type
)
5564 case BFD_RELOC_386_PLT32
:
5565 case BFD_RELOC_X86_64_PLT32
:
5566 /* Make the jump instruction point to the address of the operand. At
5567 runtime we merely add the offset to the actual PLT entry. */
5571 case BFD_RELOC_386_TLS_GD
:
5572 case BFD_RELOC_386_TLS_LDM
:
5573 case BFD_RELOC_386_TLS_IE_32
:
5574 case BFD_RELOC_386_TLS_IE
:
5575 case BFD_RELOC_386_TLS_GOTIE
:
5576 case BFD_RELOC_386_TLS_GOTDESC
:
5577 case BFD_RELOC_X86_64_TLSGD
:
5578 case BFD_RELOC_X86_64_TLSLD
:
5579 case BFD_RELOC_X86_64_GOTTPOFF
:
5580 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5581 value
= 0; /* Fully resolved at runtime. No addend. */
5583 case BFD_RELOC_386_TLS_LE
:
5584 case BFD_RELOC_386_TLS_LDO_32
:
5585 case BFD_RELOC_386_TLS_LE_32
:
5586 case BFD_RELOC_X86_64_DTPOFF32
:
5587 case BFD_RELOC_X86_64_DTPOFF64
:
5588 case BFD_RELOC_X86_64_TPOFF32
:
5589 case BFD_RELOC_X86_64_TPOFF64
:
5590 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5593 case BFD_RELOC_386_TLS_DESC_CALL
:
5594 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5595 value
= 0; /* Fully resolved at runtime. No addend. */
5596 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5600 case BFD_RELOC_386_GOT32
:
5601 case BFD_RELOC_X86_64_GOT32
:
5602 value
= 0; /* Fully resolved at runtime. No addend. */
5605 case BFD_RELOC_VTABLE_INHERIT
:
5606 case BFD_RELOC_VTABLE_ENTRY
:
5613 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5615 #endif /* !defined (TE_Mach) */
5617 /* Are we finished with this relocation now? */
5618 if (fixP
->fx_addsy
== NULL
)
5620 else if (use_rela_relocations
)
5622 fixP
->fx_no_overflow
= 1;
5623 /* Remember value for tc_gen_reloc. */
5624 fixP
->fx_addnumber
= value
;
5628 md_number_to_chars (p
, value
, fixP
->fx_size
);
5631 #define MAX_LITTLENUMS 6
5633 /* Turn the string pointed to by litP into a floating point constant
5634 of type TYPE, and emit the appropriate bytes. The number of
5635 LITTLENUMS emitted is stored in *SIZEP. An error message is
5636 returned, or NULL on OK. */
5639 md_atof (type
, litP
, sizeP
)
5645 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5646 LITTLENUM_TYPE
*wordP
;
5668 return _("Bad call to md_atof ()");
5670 t
= atof_ieee (input_line_pointer
, type
, words
);
5672 input_line_pointer
= t
;
5674 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5675 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5676 the bigendian 386. */
5677 for (wordP
= words
+ prec
- 1; prec
--;)
5679 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5680 litP
+= sizeof (LITTLENUM_TYPE
);
5685 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5688 output_invalid (int c
)
5691 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5694 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5695 "(0x%x)", (unsigned char) c
);
5696 return output_invalid_buf
;
5699 /* REG_STRING starts *before* REGISTER_PREFIX. */
5701 static const reg_entry
*
5702 parse_real_register (char *reg_string
, char **end_op
)
5704 char *s
= reg_string
;
5706 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5709 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5710 if (*s
== REGISTER_PREFIX
)
5713 if (is_space_char (*s
))
5717 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5719 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5720 return (const reg_entry
*) NULL
;
5724 /* For naked regs, make sure that we are not dealing with an identifier.
5725 This prevents confusing an identifier like `eax_var' with register
5727 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5728 return (const reg_entry
*) NULL
;
5732 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5734 /* Handle floating point regs, allowing spaces in the (i) part. */
5735 if (r
== i386_regtab
/* %st is first entry of table */)
5737 if (is_space_char (*s
))
5742 if (is_space_char (*s
))
5744 if (*s
>= '0' && *s
<= '7')
5746 r
= &i386_float_regtab
[*s
- '0'];
5748 if (is_space_char (*s
))
5756 /* We have "%st(" then garbage. */
5757 return (const reg_entry
*) NULL
;
5762 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5763 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5764 && flag_code
!= CODE_64BIT
)
5765 return (const reg_entry
*) NULL
;
5770 /* REG_STRING starts *before* REGISTER_PREFIX. */
5772 static const reg_entry
*
5773 parse_register (char *reg_string
, char **end_op
)
5777 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5778 r
= parse_real_register (reg_string
, end_op
);
5783 char *save
= input_line_pointer
;
5787 input_line_pointer
= reg_string
;
5788 c
= get_symbol_end ();
5789 symbolP
= symbol_find (reg_string
);
5790 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5792 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5794 know (e
->X_op
== O_register
);
5795 know (e
->X_add_number
>= 0
5796 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5797 r
= i386_regtab
+ e
->X_add_number
;
5798 *end_op
= input_line_pointer
;
5800 *input_line_pointer
= c
;
5801 input_line_pointer
= save
;
5807 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5810 char *end
= input_line_pointer
;
5813 r
= parse_register (name
, &input_line_pointer
);
5814 if (r
&& end
<= input_line_pointer
)
5816 *nextcharP
= *input_line_pointer
;
5817 *input_line_pointer
= 0;
5818 e
->X_op
= O_register
;
5819 e
->X_add_number
= r
- i386_regtab
;
5822 input_line_pointer
= end
;
5828 md_operand (expressionS
*e
)
5830 if (*input_line_pointer
== REGISTER_PREFIX
)
5833 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5837 e
->X_op
= O_register
;
5838 e
->X_add_number
= r
- i386_regtab
;
5839 input_line_pointer
= end
;
5845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5846 const char *md_shortopts
= "kVQ:sqn";
5848 const char *md_shortopts
= "qn";
5851 #define OPTION_32 (OPTION_MD_BASE + 0)
5852 #define OPTION_64 (OPTION_MD_BASE + 1)
5853 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5854 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5855 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5857 struct option md_longopts
[] =
5859 {"32", no_argument
, NULL
, OPTION_32
},
5860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5861 {"64", no_argument
, NULL
, OPTION_64
},
5863 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5864 {"march", required_argument
, NULL
, OPTION_MARCH
},
5865 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5866 {NULL
, no_argument
, NULL
, 0}
5868 size_t md_longopts_size
= sizeof (md_longopts
);
5871 md_parse_option (int c
, char *arg
)
5878 optimize_align_code
= 0;
5885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5886 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5887 should be emitted or not. FIXME: Not implemented. */
5891 /* -V: SVR4 argument to print version ID. */
5893 print_version_id ();
5896 /* -k: Ignore for FreeBSD compatibility. */
5901 /* -s: On i386 Solaris, this tells the native assembler to use
5902 .stab instead of .stab.excl. We always use .stab anyhow. */
5905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5908 const char **list
, **l
;
5910 list
= bfd_target_list ();
5911 for (l
= list
; *l
!= NULL
; l
++)
5912 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5913 || strcmp (*l
, "coff-x86-64") == 0
5914 || strcmp (*l
, "pe-x86-64") == 0
5915 || strcmp (*l
, "pei-x86-64") == 0)
5917 default_arch
= "x86_64";
5921 as_fatal (_("No compiled in support for x86_64"));
5928 default_arch
= "i386";
5932 #ifdef SVR4_COMMENT_CHARS
5937 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5939 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5943 i386_comment_chars
= n
;
5950 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5951 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5953 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5955 cpu_arch_isa
= cpu_arch
[i
].type
;
5956 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5957 if (!cpu_arch_tune_set
)
5959 cpu_arch_tune
= cpu_arch_isa
;
5960 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5965 if (i
>= ARRAY_SIZE (cpu_arch
))
5966 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5971 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5972 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5974 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5976 cpu_arch_tune_set
= 1;
5977 cpu_arch_tune
= cpu_arch
[i
].type
;
5978 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5982 if (i
>= ARRAY_SIZE (cpu_arch
))
5983 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5993 md_show_usage (stream
)
5996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5997 fprintf (stream
, _("\
5999 -V print assembler version number\n\
6002 fprintf (stream
, _("\
6003 -n Do not optimize code alignment\n\
6004 -q quieten some warnings\n"));
6005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6006 fprintf (stream
, _("\
6009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6010 fprintf (stream
, _("\
6011 --32/--64 generate 32bit/64bit code\n"));
6013 #ifdef SVR4_COMMENT_CHARS
6014 fprintf (stream
, _("\
6015 --divide do not treat `/' as a comment character\n"));
6017 fprintf (stream
, _("\
6018 --divide ignored\n"));
6020 fprintf (stream
, _("\
6021 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6022 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6023 core, core2, k6, athlon, k8, generic32, generic64\n"));
6029 x86_64_target_format (void)
6031 if (strcmp (default_arch
, "x86_64") == 0)
6033 set_code_flag (CODE_64BIT
);
6034 return COFF_TARGET_FORMAT
;
6036 else if (strcmp (default_arch
, "i386") == 0)
6038 set_code_flag (CODE_32BIT
);
6042 as_fatal (_("Unknown architecture"));
6047 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6048 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6050 /* Pick the target format to use. */
6053 i386_target_format (void)
6055 if (!strcmp (default_arch
, "x86_64"))
6057 set_code_flag (CODE_64BIT
);
6058 if (cpu_arch_isa_flags
== 0)
6059 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6060 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6062 if (cpu_arch_tune_flags
== 0)
6063 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6064 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6067 else if (!strcmp (default_arch
, "i386"))
6069 set_code_flag (CODE_32BIT
);
6070 if (cpu_arch_isa_flags
== 0)
6071 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6072 if (cpu_arch_tune_flags
== 0)
6073 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6076 as_fatal (_("Unknown architecture"));
6077 switch (OUTPUT_FLAVOR
)
6079 #ifdef OBJ_MAYBE_AOUT
6080 case bfd_target_aout_flavour
:
6081 return AOUT_TARGET_FORMAT
;
6083 #ifdef OBJ_MAYBE_COFF
6084 case bfd_target_coff_flavour
:
6087 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6088 case bfd_target_elf_flavour
:
6090 if (flag_code
== CODE_64BIT
)
6093 use_rela_relocations
= 1;
6095 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6104 #endif /* OBJ_MAYBE_ more than one */
6106 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6108 i386_elf_emit_arch_note (void)
6110 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6113 asection
*seg
= now_seg
;
6114 subsegT subseg
= now_subseg
;
6115 Elf_Internal_Note i_note
;
6116 Elf_External_Note e_note
;
6117 asection
*note_secp
;
6120 /* Create the .note section. */
6121 note_secp
= subseg_new (".note", 0);
6122 bfd_set_section_flags (stdoutput
,
6124 SEC_HAS_CONTENTS
| SEC_READONLY
);
6126 /* Process the arch string. */
6127 len
= strlen (cpu_arch_name
);
6129 i_note
.namesz
= len
+ 1;
6131 i_note
.type
= NT_ARCH
;
6132 p
= frag_more (sizeof (e_note
.namesz
));
6133 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6134 p
= frag_more (sizeof (e_note
.descsz
));
6135 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6136 p
= frag_more (sizeof (e_note
.type
));
6137 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6138 p
= frag_more (len
+ 1);
6139 strcpy (p
, cpu_arch_name
);
6141 frag_align (2, 0, 0);
6143 subseg_set (seg
, subseg
);
6149 md_undefined_symbol (name
)
6152 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6153 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6154 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6155 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6159 if (symbol_find (name
))
6160 as_bad (_("GOT already in symbol table"));
6161 GOT_symbol
= symbol_new (name
, undefined_section
,
6162 (valueT
) 0, &zero_address_frag
);
6169 /* Round up a section size to the appropriate boundary. */
6172 md_section_align (segment
, size
)
6173 segT segment ATTRIBUTE_UNUSED
;
6176 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6177 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6179 /* For a.out, force the section size to be aligned. If we don't do
6180 this, BFD will align it for us, but it will not write out the
6181 final bytes of the section. This may be a bug in BFD, but it is
6182 easier to fix it here since that is how the other a.out targets
6186 align
= bfd_get_section_alignment (stdoutput
, segment
);
6187 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6194 /* On the i386, PC-relative offsets are relative to the start of the
6195 next instruction. That is, the address of the offset, plus its
6196 size, since the offset is always the last part of the insn. */
6199 md_pcrel_from (fixS
*fixP
)
6201 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6207 s_bss (int ignore ATTRIBUTE_UNUSED
)
6211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6213 obj_elf_section_change_hook ();
6215 temp
= get_absolute_expression ();
6216 subseg_set (bss_section
, (subsegT
) temp
);
6217 demand_empty_rest_of_line ();
6223 i386_validate_fix (fixS
*fixp
)
6225 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6227 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6231 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6236 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6238 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6245 tc_gen_reloc (section
, fixp
)
6246 asection
*section ATTRIBUTE_UNUSED
;
6250 bfd_reloc_code_real_type code
;
6252 switch (fixp
->fx_r_type
)
6254 case BFD_RELOC_X86_64_PLT32
:
6255 case BFD_RELOC_X86_64_GOT32
:
6256 case BFD_RELOC_X86_64_GOTPCREL
:
6257 case BFD_RELOC_386_PLT32
:
6258 case BFD_RELOC_386_GOT32
:
6259 case BFD_RELOC_386_GOTOFF
:
6260 case BFD_RELOC_386_GOTPC
:
6261 case BFD_RELOC_386_TLS_GD
:
6262 case BFD_RELOC_386_TLS_LDM
:
6263 case BFD_RELOC_386_TLS_LDO_32
:
6264 case BFD_RELOC_386_TLS_IE_32
:
6265 case BFD_RELOC_386_TLS_IE
:
6266 case BFD_RELOC_386_TLS_GOTIE
:
6267 case BFD_RELOC_386_TLS_LE_32
:
6268 case BFD_RELOC_386_TLS_LE
:
6269 case BFD_RELOC_386_TLS_GOTDESC
:
6270 case BFD_RELOC_386_TLS_DESC_CALL
:
6271 case BFD_RELOC_X86_64_TLSGD
:
6272 case BFD_RELOC_X86_64_TLSLD
:
6273 case BFD_RELOC_X86_64_DTPOFF32
:
6274 case BFD_RELOC_X86_64_DTPOFF64
:
6275 case BFD_RELOC_X86_64_GOTTPOFF
:
6276 case BFD_RELOC_X86_64_TPOFF32
:
6277 case BFD_RELOC_X86_64_TPOFF64
:
6278 case BFD_RELOC_X86_64_GOTOFF64
:
6279 case BFD_RELOC_X86_64_GOTPC32
:
6280 case BFD_RELOC_X86_64_GOT64
:
6281 case BFD_RELOC_X86_64_GOTPCREL64
:
6282 case BFD_RELOC_X86_64_GOTPC64
:
6283 case BFD_RELOC_X86_64_GOTPLT64
:
6284 case BFD_RELOC_X86_64_PLTOFF64
:
6285 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6286 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6288 case BFD_RELOC_VTABLE_ENTRY
:
6289 case BFD_RELOC_VTABLE_INHERIT
:
6291 case BFD_RELOC_32_SECREL
:
6293 code
= fixp
->fx_r_type
;
6295 case BFD_RELOC_X86_64_32S
:
6296 if (!fixp
->fx_pcrel
)
6298 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6299 code
= fixp
->fx_r_type
;
6305 switch (fixp
->fx_size
)
6308 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6309 _("can not do %d byte pc-relative relocation"),
6311 code
= BFD_RELOC_32_PCREL
;
6313 case 1: code
= BFD_RELOC_8_PCREL
; break;
6314 case 2: code
= BFD_RELOC_16_PCREL
; break;
6315 case 4: code
= BFD_RELOC_32_PCREL
; break;
6317 case 8: code
= BFD_RELOC_64_PCREL
; break;
6323 switch (fixp
->fx_size
)
6326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6327 _("can not do %d byte relocation"),
6329 code
= BFD_RELOC_32
;
6331 case 1: code
= BFD_RELOC_8
; break;
6332 case 2: code
= BFD_RELOC_16
; break;
6333 case 4: code
= BFD_RELOC_32
; break;
6335 case 8: code
= BFD_RELOC_64
; break;
6342 if ((code
== BFD_RELOC_32
6343 || code
== BFD_RELOC_32_PCREL
6344 || code
== BFD_RELOC_X86_64_32S
)
6346 && fixp
->fx_addsy
== GOT_symbol
)
6349 code
= BFD_RELOC_386_GOTPC
;
6351 code
= BFD_RELOC_X86_64_GOTPC32
;
6353 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6355 && fixp
->fx_addsy
== GOT_symbol
)
6357 code
= BFD_RELOC_X86_64_GOTPC64
;
6360 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6361 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6362 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6364 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6366 if (!use_rela_relocations
)
6368 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6369 vtable entry to be used in the relocation's section offset. */
6370 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6371 rel
->address
= fixp
->fx_offset
;
6375 /* Use the rela in 64bit mode. */
6378 if (!fixp
->fx_pcrel
)
6379 rel
->addend
= fixp
->fx_offset
;
6383 case BFD_RELOC_X86_64_PLT32
:
6384 case BFD_RELOC_X86_64_GOT32
:
6385 case BFD_RELOC_X86_64_GOTPCREL
:
6386 case BFD_RELOC_X86_64_TLSGD
:
6387 case BFD_RELOC_X86_64_TLSLD
:
6388 case BFD_RELOC_X86_64_GOTTPOFF
:
6389 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6390 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6391 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6394 rel
->addend
= (section
->vma
6396 + fixp
->fx_addnumber
6397 + md_pcrel_from (fixp
));
6402 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6403 if (rel
->howto
== NULL
)
6405 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6406 _("cannot represent relocation type %s"),
6407 bfd_get_reloc_code_name (code
));
6408 /* Set howto to a garbage value so that we can keep going. */
6409 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6410 assert (rel
->howto
!= NULL
);
6417 /* Parse operands using Intel syntax. This implements a recursive descent
6418 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6421 FIXME: We do not recognize the full operand grammar defined in the MASM
6422 documentation. In particular, all the structure/union and
6423 high-level macro operands are missing.
6425 Uppercase words are terminals, lower case words are non-terminals.
6426 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6427 bars '|' denote choices. Most grammar productions are implemented in
6428 functions called 'intel_<production>'.
6430 Initial production is 'expr'.
6436 binOp & | AND | \| | OR | ^ | XOR
6438 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6440 constant digits [[ radixOverride ]]
6442 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6480 => expr expr cmpOp e04
6483 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6484 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6486 hexdigit a | b | c | d | e | f
6487 | A | B | C | D | E | F
6493 mulOp * | / | % | MOD | << | SHL | >> | SHR
6497 register specialRegister
6501 segmentRegister CS | DS | ES | FS | GS | SS
6503 specialRegister CR0 | CR2 | CR3 | CR4
6504 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6505 | TR3 | TR4 | TR5 | TR6 | TR7
6507 We simplify the grammar in obvious places (e.g., register parsing is
6508 done by calling parse_register) and eliminate immediate left recursion
6509 to implement a recursive-descent parser.
6513 expr' cmpOp e04 expr'
6564 /* Parsing structure for the intel syntax parser. Used to implement the
6565 semantic actions for the operand grammar. */
6566 struct intel_parser_s
6568 char *op_string
; /* The string being parsed. */
6569 int got_a_float
; /* Whether the operand is a float. */
6570 int op_modifier
; /* Operand modifier. */
6571 int is_mem
; /* 1 if operand is memory reference. */
6572 int in_offset
; /* >=1 if parsing operand of offset. */
6573 int in_bracket
; /* >=1 if parsing operand in brackets. */
6574 const reg_entry
*reg
; /* Last register reference found. */
6575 char *disp
; /* Displacement string being built. */
6576 char *next_operand
; /* Resume point when splitting operands. */
6579 static struct intel_parser_s intel_parser
;
6581 /* Token structure for parsing intel syntax. */
6584 int code
; /* Token code. */
6585 const reg_entry
*reg
; /* Register entry for register tokens. */
6586 char *str
; /* String representation. */
6589 static struct intel_token cur_token
, prev_token
;
6591 /* Token codes for the intel parser. Since T_SHORT is already used
6592 by COFF, undefine it first to prevent a warning. */
6611 /* Prototypes for intel parser functions. */
6612 static int intel_match_token (int);
6613 static void intel_putback_token (void);
6614 static void intel_get_token (void);
6615 static int intel_expr (void);
6616 static int intel_e04 (void);
6617 static int intel_e05 (void);
6618 static int intel_e06 (void);
6619 static int intel_e09 (void);
6620 static int intel_e10 (void);
6621 static int intel_e11 (void);
6624 i386_intel_operand (char *operand_string
, int got_a_float
)
6629 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6630 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6634 /* Initialize token holders. */
6635 cur_token
.code
= prev_token
.code
= T_NIL
;
6636 cur_token
.reg
= prev_token
.reg
= NULL
;
6637 cur_token
.str
= prev_token
.str
= NULL
;
6639 /* Initialize parser structure. */
6640 intel_parser
.got_a_float
= got_a_float
;
6641 intel_parser
.op_modifier
= 0;
6642 intel_parser
.is_mem
= 0;
6643 intel_parser
.in_offset
= 0;
6644 intel_parser
.in_bracket
= 0;
6645 intel_parser
.reg
= NULL
;
6646 intel_parser
.disp
[0] = '\0';
6647 intel_parser
.next_operand
= NULL
;
6649 /* Read the first token and start the parser. */
6651 ret
= intel_expr ();
6656 if (cur_token
.code
!= T_NIL
)
6658 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6659 current_templates
->start
->name
, cur_token
.str
);
6662 /* If we found a memory reference, hand it over to i386_displacement
6663 to fill in the rest of the operand fields. */
6664 else if (intel_parser
.is_mem
)
6666 if ((i
.mem_operands
== 1
6667 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6668 || i
.mem_operands
== 2)
6670 as_bad (_("too many memory references for '%s'"),
6671 current_templates
->start
->name
);
6676 char *s
= intel_parser
.disp
;
6679 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6680 /* See the comments in intel_bracket_expr. */
6681 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6683 /* Add the displacement expression. */
6685 ret
= i386_displacement (s
, s
+ strlen (s
));
6688 /* Swap base and index in 16-bit memory operands like
6689 [si+bx]. Since i386_index_check is also used in AT&T
6690 mode we have to do that here. */
6693 && (i
.base_reg
->reg_type
& Reg16
)
6694 && (i
.index_reg
->reg_type
& Reg16
)
6695 && i
.base_reg
->reg_num
>= 6
6696 && i
.index_reg
->reg_num
< 6)
6698 const reg_entry
*base
= i
.index_reg
;
6700 i
.index_reg
= i
.base_reg
;
6703 ret
= i386_index_check (operand_string
);
6708 /* Constant and OFFSET expressions are handled by i386_immediate. */
6709 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6710 || intel_parser
.reg
== NULL
)
6711 ret
= i386_immediate (intel_parser
.disp
);
6713 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6715 if (!ret
|| !intel_parser
.next_operand
)
6717 intel_parser
.op_string
= intel_parser
.next_operand
;
6718 this_operand
= i
.operands
++;
6722 free (intel_parser
.disp
);
6727 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6731 expr' cmpOp e04 expr'
6736 /* XXX Implement the comparison operators. */
6737 return intel_e04 ();
6754 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6755 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6757 if (cur_token
.code
== '+')
6759 else if (cur_token
.code
== '-')
6760 nregs
= NUM_ADDRESS_REGS
;
6764 strcat (intel_parser
.disp
, cur_token
.str
);
6765 intel_match_token (cur_token
.code
);
6776 int nregs
= ~NUM_ADDRESS_REGS
;
6783 if (cur_token
.code
== '&'
6784 || cur_token
.code
== '|'
6785 || cur_token
.code
== '^')
6789 str
[0] = cur_token
.code
;
6791 strcat (intel_parser
.disp
, str
);
6796 intel_match_token (cur_token
.code
);
6801 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6802 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6813 int nregs
= ~NUM_ADDRESS_REGS
;
6820 if (cur_token
.code
== '*'
6821 || cur_token
.code
== '/'
6822 || cur_token
.code
== '%')
6826 str
[0] = cur_token
.code
;
6828 strcat (intel_parser
.disp
, str
);
6830 else if (cur_token
.code
== T_SHL
)
6831 strcat (intel_parser
.disp
, "<<");
6832 else if (cur_token
.code
== T_SHR
)
6833 strcat (intel_parser
.disp
, ">>");
6837 intel_match_token (cur_token
.code
);
6842 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6843 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6861 int nregs
= ~NUM_ADDRESS_REGS
;
6866 /* Don't consume constants here. */
6867 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6869 /* Need to look one token ahead - if the next token
6870 is a constant, the current token is its sign. */
6873 intel_match_token (cur_token
.code
);
6874 next_code
= cur_token
.code
;
6875 intel_putback_token ();
6876 if (next_code
== T_CONST
)
6880 /* e09 OFFSET e09 */
6881 if (cur_token
.code
== T_OFFSET
)
6884 ++intel_parser
.in_offset
;
6888 else if (cur_token
.code
== T_SHORT
)
6889 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6892 else if (cur_token
.code
== '+')
6893 strcat (intel_parser
.disp
, "+");
6898 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6904 str
[0] = cur_token
.code
;
6906 strcat (intel_parser
.disp
, str
);
6913 intel_match_token (cur_token
.code
);
6921 /* e09' PTR e10 e09' */
6922 if (cur_token
.code
== T_PTR
)
6926 if (prev_token
.code
== T_BYTE
)
6927 suffix
= BYTE_MNEM_SUFFIX
;
6929 else if (prev_token
.code
== T_WORD
)
6931 if (current_templates
->start
->name
[0] == 'l'
6932 && current_templates
->start
->name
[2] == 's'
6933 && current_templates
->start
->name
[3] == 0)
6934 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6935 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6936 suffix
= SHORT_MNEM_SUFFIX
;
6938 suffix
= WORD_MNEM_SUFFIX
;
6941 else if (prev_token
.code
== T_DWORD
)
6943 if (current_templates
->start
->name
[0] == 'l'
6944 && current_templates
->start
->name
[2] == 's'
6945 && current_templates
->start
->name
[3] == 0)
6946 suffix
= WORD_MNEM_SUFFIX
;
6947 else if (flag_code
== CODE_16BIT
6948 && (current_templates
->start
->opcode_modifier
6949 & (Jump
| JumpDword
)))
6950 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6951 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6952 suffix
= SHORT_MNEM_SUFFIX
;
6954 suffix
= LONG_MNEM_SUFFIX
;
6957 else if (prev_token
.code
== T_FWORD
)
6959 if (current_templates
->start
->name
[0] == 'l'
6960 && current_templates
->start
->name
[2] == 's'
6961 && current_templates
->start
->name
[3] == 0)
6962 suffix
= LONG_MNEM_SUFFIX
;
6963 else if (!intel_parser
.got_a_float
)
6965 if (flag_code
== CODE_16BIT
)
6966 add_prefix (DATA_PREFIX_OPCODE
);
6967 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6970 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6973 else if (prev_token
.code
== T_QWORD
)
6975 if (intel_parser
.got_a_float
== 1) /* "f..." */
6976 suffix
= LONG_MNEM_SUFFIX
;
6978 suffix
= QWORD_MNEM_SUFFIX
;
6981 else if (prev_token
.code
== T_TBYTE
)
6983 if (intel_parser
.got_a_float
== 1)
6984 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6986 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6989 else if (prev_token
.code
== T_XMMWORD
)
6991 /* XXX ignored for now, but accepted since gcc uses it */
6997 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7001 /* Operands for jump/call using 'ptr' notation denote absolute
7003 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7004 i
.types
[this_operand
] |= JumpAbsolute
;
7006 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7010 else if (i
.suffix
!= suffix
)
7012 as_bad (_("Conflicting operand modifiers"));
7018 /* e09' : e10 e09' */
7019 else if (cur_token
.code
== ':')
7021 if (prev_token
.code
!= T_REG
)
7023 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7024 segment/group identifier (which we don't have), using comma
7025 as the operand separator there is even less consistent, since
7026 there all branches only have a single operand. */
7027 if (this_operand
!= 0
7028 || intel_parser
.in_offset
7029 || intel_parser
.in_bracket
7030 || (!(current_templates
->start
->opcode_modifier
7031 & (Jump
|JumpDword
|JumpInterSegment
))
7032 && !(current_templates
->start
->operand_types
[0]
7034 return intel_match_token (T_NIL
);
7035 /* Remember the start of the 2nd operand and terminate 1st
7037 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7038 another expression), but it gets at least the simplest case
7039 (a plain number or symbol on the left side) right. */
7040 intel_parser
.next_operand
= intel_parser
.op_string
;
7041 *--intel_parser
.op_string
= '\0';
7042 return intel_match_token (':');
7050 intel_match_token (cur_token
.code
);
7056 --intel_parser
.in_offset
;
7059 if (NUM_ADDRESS_REGS
> nregs
)
7061 as_bad (_("Invalid operand to `OFFSET'"));
7064 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7067 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7068 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7073 intel_bracket_expr (void)
7075 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7076 const char *start
= intel_parser
.op_string
;
7079 if (i
.op
[this_operand
].regs
)
7080 return intel_match_token (T_NIL
);
7082 intel_match_token ('[');
7084 /* Mark as a memory operand only if it's not already known to be an
7085 offset expression. If it's an offset expression, we need to keep
7087 if (!intel_parser
.in_offset
)
7089 ++intel_parser
.in_bracket
;
7091 /* Operands for jump/call inside brackets denote absolute addresses. */
7092 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7093 i
.types
[this_operand
] |= JumpAbsolute
;
7095 /* Unfortunately gas always diverged from MASM in a respect that can't
7096 be easily fixed without risking to break code sequences likely to be
7097 encountered (the testsuite even check for this): MASM doesn't consider
7098 an expression inside brackets unconditionally as a memory reference.
7099 When that is e.g. a constant, an offset expression, or the sum of the
7100 two, this is still taken as a constant load. gas, however, always
7101 treated these as memory references. As a compromise, we'll try to make
7102 offset expressions inside brackets work the MASM way (since that's
7103 less likely to be found in real world code), but make constants alone
7104 continue to work the traditional gas way. In either case, issue a
7106 intel_parser
.op_modifier
&= ~was_offset
;
7109 strcat (intel_parser
.disp
, "[");
7111 /* Add a '+' to the displacement string if necessary. */
7112 if (*intel_parser
.disp
!= '\0'
7113 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7114 strcat (intel_parser
.disp
, "+");
7117 && (len
= intel_parser
.op_string
- start
- 1,
7118 intel_match_token (']')))
7120 /* Preserve brackets when the operand is an offset expression. */
7121 if (intel_parser
.in_offset
)
7122 strcat (intel_parser
.disp
, "]");
7125 --intel_parser
.in_bracket
;
7126 if (i
.base_reg
|| i
.index_reg
)
7127 intel_parser
.is_mem
= 1;
7128 if (!intel_parser
.is_mem
)
7130 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7131 /* Defer the warning until all of the operand was parsed. */
7132 intel_parser
.is_mem
= -1;
7133 else if (!quiet_warnings
)
7134 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7135 len
, start
, len
, start
);
7138 intel_parser
.op_modifier
|= was_offset
;
7155 while (cur_token
.code
== '[')
7157 if (!intel_bracket_expr ())
7182 switch (cur_token
.code
)
7186 intel_match_token ('(');
7187 strcat (intel_parser
.disp
, "(");
7189 if (intel_expr () && intel_match_token (')'))
7191 strcat (intel_parser
.disp
, ")");
7198 return intel_bracket_expr ();
7203 strcat (intel_parser
.disp
, cur_token
.str
);
7204 intel_match_token (cur_token
.code
);
7206 /* Mark as a memory operand only if it's not already known to be an
7207 offset expression. */
7208 if (!intel_parser
.in_offset
)
7209 intel_parser
.is_mem
= 1;
7216 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7218 intel_match_token (T_REG
);
7220 /* Check for segment change. */
7221 if (cur_token
.code
== ':')
7223 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7225 as_bad (_("`%s' is not a valid segment register"),
7229 else if (i
.seg
[i
.mem_operands
])
7230 as_warn (_("Extra segment override ignored"));
7233 if (!intel_parser
.in_offset
)
7234 intel_parser
.is_mem
= 1;
7235 switch (reg
->reg_num
)
7238 i
.seg
[i
.mem_operands
] = &es
;
7241 i
.seg
[i
.mem_operands
] = &cs
;
7244 i
.seg
[i
.mem_operands
] = &ss
;
7247 i
.seg
[i
.mem_operands
] = &ds
;
7250 i
.seg
[i
.mem_operands
] = &fs
;
7253 i
.seg
[i
.mem_operands
] = &gs
;
7259 /* Not a segment register. Check for register scaling. */
7260 else if (cur_token
.code
== '*')
7262 if (!intel_parser
.in_bracket
)
7264 as_bad (_("Register scaling only allowed in memory operands"));
7268 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7269 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7270 else if (i
.index_reg
)
7271 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7273 /* What follows must be a valid scale. */
7274 intel_match_token ('*');
7276 i
.types
[this_operand
] |= BaseIndex
;
7278 /* Set the scale after setting the register (otherwise,
7279 i386_scale will complain) */
7280 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7282 char *str
, sign
= cur_token
.code
;
7283 intel_match_token (cur_token
.code
);
7284 if (cur_token
.code
!= T_CONST
)
7286 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7290 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7291 strcpy (str
+ 1, cur_token
.str
);
7293 if (!i386_scale (str
))
7297 else if (!i386_scale (cur_token
.str
))
7299 intel_match_token (cur_token
.code
);
7302 /* No scaling. If this is a memory operand, the register is either a
7303 base register (first occurrence) or an index register (second
7305 else if (intel_parser
.in_bracket
)
7310 else if (!i
.index_reg
)
7314 as_bad (_("Too many register references in memory operand"));
7318 i
.types
[this_operand
] |= BaseIndex
;
7321 /* It's neither base nor index. */
7322 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7324 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7325 i
.op
[this_operand
].regs
= reg
;
7330 as_bad (_("Invalid use of register"));
7334 /* Since registers are not part of the displacement string (except
7335 when we're parsing offset operands), we may need to remove any
7336 preceding '+' from the displacement string. */
7337 if (*intel_parser
.disp
!= '\0'
7338 && !intel_parser
.in_offset
)
7340 char *s
= intel_parser
.disp
;
7341 s
+= strlen (s
) - 1;
7364 intel_match_token (cur_token
.code
);
7366 if (cur_token
.code
== T_PTR
)
7369 /* It must have been an identifier. */
7370 intel_putback_token ();
7371 cur_token
.code
= T_ID
;
7377 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7381 /* The identifier represents a memory reference only if it's not
7382 preceded by an offset modifier and if it's not an equate. */
7383 symbolP
= symbol_find(cur_token
.str
);
7384 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7385 intel_parser
.is_mem
= 1;
7393 char *save_str
, sign
= 0;
7395 /* Allow constants that start with `+' or `-'. */
7396 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7398 sign
= cur_token
.code
;
7399 intel_match_token (cur_token
.code
);
7400 if (cur_token
.code
!= T_CONST
)
7402 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7408 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7409 strcpy (save_str
+ !!sign
, cur_token
.str
);
7413 /* Get the next token to check for register scaling. */
7414 intel_match_token (cur_token
.code
);
7416 /* Check if this constant is a scaling factor for an
7418 if (cur_token
.code
== '*')
7420 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7422 const reg_entry
*reg
= cur_token
.reg
;
7424 if (!intel_parser
.in_bracket
)
7426 as_bad (_("Register scaling only allowed "
7427 "in memory operands"));
7431 /* Disallow things like [1*si].
7432 sp and esp are invalid as index. */
7433 if (reg
->reg_type
& Reg16
)
7434 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7435 else if (i
.index_reg
)
7436 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7438 /* The constant is followed by `* reg', so it must be
7441 i
.types
[this_operand
] |= BaseIndex
;
7443 /* Set the scale after setting the register (otherwise,
7444 i386_scale will complain) */
7445 if (!i386_scale (save_str
))
7447 intel_match_token (T_REG
);
7449 /* Since registers are not part of the displacement
7450 string, we may need to remove any preceding '+' from
7451 the displacement string. */
7452 if (*intel_parser
.disp
!= '\0')
7454 char *s
= intel_parser
.disp
;
7455 s
+= strlen (s
) - 1;
7465 /* The constant was not used for register scaling. Since we have
7466 already consumed the token following `*' we now need to put it
7467 back in the stream. */
7468 intel_putback_token ();
7471 /* Add the constant to the displacement string. */
7472 strcat (intel_parser
.disp
, save_str
);
7479 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7483 /* Match the given token against cur_token. If they match, read the next
7484 token from the operand string. */
7486 intel_match_token (int code
)
7488 if (cur_token
.code
== code
)
7495 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7500 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7502 intel_get_token (void)
7505 const reg_entry
*reg
;
7506 struct intel_token new_token
;
7508 new_token
.code
= T_NIL
;
7509 new_token
.reg
= NULL
;
7510 new_token
.str
= NULL
;
7512 /* Free the memory allocated to the previous token and move
7513 cur_token to prev_token. */
7515 free (prev_token
.str
);
7517 prev_token
= cur_token
;
7519 /* Skip whitespace. */
7520 while (is_space_char (*intel_parser
.op_string
))
7521 intel_parser
.op_string
++;
7523 /* Return an empty token if we find nothing else on the line. */
7524 if (*intel_parser
.op_string
== '\0')
7526 cur_token
= new_token
;
7530 /* The new token cannot be larger than the remainder of the operand
7532 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7533 new_token
.str
[0] = '\0';
7535 if (strchr ("0123456789", *intel_parser
.op_string
))
7537 char *p
= new_token
.str
;
7538 char *q
= intel_parser
.op_string
;
7539 new_token
.code
= T_CONST
;
7541 /* Allow any kind of identifier char to encompass floating point and
7542 hexadecimal numbers. */
7543 while (is_identifier_char (*q
))
7547 /* Recognize special symbol names [0-9][bf]. */
7548 if (strlen (intel_parser
.op_string
) == 2
7549 && (intel_parser
.op_string
[1] == 'b'
7550 || intel_parser
.op_string
[1] == 'f'))
7551 new_token
.code
= T_ID
;
7554 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7556 size_t len
= end_op
- intel_parser
.op_string
;
7558 new_token
.code
= T_REG
;
7559 new_token
.reg
= reg
;
7561 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7562 new_token
.str
[len
] = '\0';
7565 else if (is_identifier_char (*intel_parser
.op_string
))
7567 char *p
= new_token
.str
;
7568 char *q
= intel_parser
.op_string
;
7570 /* A '.' or '$' followed by an identifier char is an identifier.
7571 Otherwise, it's operator '.' followed by an expression. */
7572 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7574 new_token
.code
= '.';
7575 new_token
.str
[0] = '.';
7576 new_token
.str
[1] = '\0';
7580 while (is_identifier_char (*q
) || *q
== '@')
7584 if (strcasecmp (new_token
.str
, "NOT") == 0)
7585 new_token
.code
= '~';
7587 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7588 new_token
.code
= '%';
7590 else if (strcasecmp (new_token
.str
, "AND") == 0)
7591 new_token
.code
= '&';
7593 else if (strcasecmp (new_token
.str
, "OR") == 0)
7594 new_token
.code
= '|';
7596 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7597 new_token
.code
= '^';
7599 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7600 new_token
.code
= T_SHL
;
7602 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7603 new_token
.code
= T_SHR
;
7605 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7606 new_token
.code
= T_BYTE
;
7608 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7609 new_token
.code
= T_WORD
;
7611 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7612 new_token
.code
= T_DWORD
;
7614 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7615 new_token
.code
= T_FWORD
;
7617 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7618 new_token
.code
= T_QWORD
;
7620 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7621 /* XXX remove (gcc still uses it) */
7622 || strcasecmp (new_token
.str
, "XWORD") == 0)
7623 new_token
.code
= T_TBYTE
;
7625 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7626 || strcasecmp (new_token
.str
, "OWORD") == 0)
7627 new_token
.code
= T_XMMWORD
;
7629 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7630 new_token
.code
= T_PTR
;
7632 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7633 new_token
.code
= T_SHORT
;
7635 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7637 new_token
.code
= T_OFFSET
;
7639 /* ??? This is not mentioned in the MASM grammar but gcc
7640 makes use of it with -mintel-syntax. OFFSET may be
7641 followed by FLAT: */
7642 if (strncasecmp (q
, " FLAT:", 6) == 0)
7643 strcat (new_token
.str
, " FLAT:");
7646 /* ??? This is not mentioned in the MASM grammar. */
7647 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7649 new_token
.code
= T_OFFSET
;
7651 strcat (new_token
.str
, ":");
7653 as_bad (_("`:' expected"));
7657 new_token
.code
= T_ID
;
7661 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7663 new_token
.code
= *intel_parser
.op_string
;
7664 new_token
.str
[0] = *intel_parser
.op_string
;
7665 new_token
.str
[1] = '\0';
7668 else if (strchr ("<>", *intel_parser
.op_string
)
7669 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7671 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7672 new_token
.str
[0] = *intel_parser
.op_string
;
7673 new_token
.str
[1] = *intel_parser
.op_string
;
7674 new_token
.str
[2] = '\0';
7678 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7680 intel_parser
.op_string
+= strlen (new_token
.str
);
7681 cur_token
= new_token
;
7684 /* Put cur_token back into the token stream and make cur_token point to
7687 intel_putback_token (void)
7689 if (cur_token
.code
!= T_NIL
)
7691 intel_parser
.op_string
-= strlen (cur_token
.str
);
7692 free (cur_token
.str
);
7694 cur_token
= prev_token
;
7696 /* Forget prev_token. */
7697 prev_token
.code
= T_NIL
;
7698 prev_token
.reg
= NULL
;
7699 prev_token
.str
= NULL
;
7703 tc_x86_regname_to_dw2regnum (char *regname
)
7705 unsigned int regnum
;
7706 unsigned int regnames_count
;
7707 static const char *const regnames_32
[] =
7709 "eax", "ecx", "edx", "ebx",
7710 "esp", "ebp", "esi", "edi",
7711 "eip", "eflags", NULL
,
7712 "st0", "st1", "st2", "st3",
7713 "st4", "st5", "st6", "st7",
7715 "xmm0", "xmm1", "xmm2", "xmm3",
7716 "xmm4", "xmm5", "xmm6", "xmm7",
7717 "mm0", "mm1", "mm2", "mm3",
7718 "mm4", "mm5", "mm6", "mm7",
7719 "fcw", "fsw", "mxcsr",
7720 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7723 static const char *const regnames_64
[] =
7725 "rax", "rdx", "rcx", "rbx",
7726 "rsi", "rdi", "rbp", "rsp",
7727 "r8", "r9", "r10", "r11",
7728 "r12", "r13", "r14", "r15",
7730 "xmm0", "xmm1", "xmm2", "xmm3",
7731 "xmm4", "xmm5", "xmm6", "xmm7",
7732 "xmm8", "xmm9", "xmm10", "xmm11",
7733 "xmm12", "xmm13", "xmm14", "xmm15",
7734 "st0", "st1", "st2", "st3",
7735 "st4", "st5", "st6", "st7",
7736 "mm0", "mm1", "mm2", "mm3",
7737 "mm4", "mm5", "mm6", "mm7",
7739 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7740 "fs.base", "gs.base", NULL
, NULL
,
7742 "mxcsr", "fcw", "fsw"
7744 const char *const *regnames
;
7746 if (flag_code
== CODE_64BIT
)
7748 regnames
= regnames_64
;
7749 regnames_count
= ARRAY_SIZE (regnames_64
);
7753 regnames
= regnames_32
;
7754 regnames_count
= ARRAY_SIZE (regnames_32
);
7757 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7758 if (regnames
[regnum
] != NULL
7759 && strcmp (regname
, regnames
[regnum
]) == 0)
7766 tc_x86_frame_initial_instructions (void)
7768 static unsigned int sp_regno
;
7771 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7774 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7775 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7779 i386_elf_section_type (const char *str
, size_t len
)
7781 if (flag_code
== CODE_64BIT
7782 && len
== sizeof ("unwind") - 1
7783 && strncmp (str
, "unwind", 6) == 0)
7784 return SHT_X86_64_UNWIND
;
7791 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7795 expr
.X_op
= O_secrel
;
7796 expr
.X_add_symbol
= symbol
;
7797 expr
.X_add_number
= 0;
7798 emit_expr (&expr
, size
);
7802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7803 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7806 x86_64_section_letter (int letter
, char **ptr_msg
)
7808 if (flag_code
== CODE_64BIT
)
7811 return SHF_X86_64_LARGE
;
7813 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7816 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7821 x86_64_section_word (char *str
, size_t len
)
7823 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7824 return SHF_X86_64_LARGE
;
7830 handle_large_common (int small ATTRIBUTE_UNUSED
)
7832 if (flag_code
!= CODE_64BIT
)
7834 s_comm_internal (0, elf_common_parse
);
7835 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7839 static segT lbss_section
;
7840 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7841 asection
*saved_bss_section
= bss_section
;
7843 if (lbss_section
== NULL
)
7845 flagword applicable
;
7847 subsegT subseg
= now_subseg
;
7849 /* The .lbss section is for local .largecomm symbols. */
7850 lbss_section
= subseg_new (".lbss", 0);
7851 applicable
= bfd_applicable_section_flags (stdoutput
);
7852 bfd_set_section_flags (stdoutput
, lbss_section
,
7853 applicable
& SEC_ALLOC
);
7854 seg_info (lbss_section
)->bss
= 1;
7856 subseg_set (seg
, subseg
);
7859 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7860 bss_section
= lbss_section
;
7862 s_comm_internal (0, elf_common_parse
);
7864 elf_com_section_ptr
= saved_com_section_ptr
;
7865 bss_section
= saved_bss_section
;
7868 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */