1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1085 static const noarch_entry cpu_noarch
[] =
1087 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1088 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1089 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1090 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1091 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1092 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1093 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1094 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1095 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1096 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1097 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1099 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1118 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1119 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1120 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1121 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1125 /* Like s_lcomm_internal in gas/read.c but the alignment string
1126 is allowed to be optional. */
1129 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1136 && *input_line_pointer
== ',')
1138 align
= parse_align (needs_align
- 1);
1140 if (align
== (addressT
) -1)
1155 bss_alloc (symbolP
, size
, align
);
1160 pe_lcomm (int needs_align
)
1162 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1166 const pseudo_typeS md_pseudo_table
[] =
1168 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1169 {"align", s_align_bytes
, 0},
1171 {"align", s_align_ptwo
, 0},
1173 {"arch", set_cpu_arch
, 0},
1177 {"lcomm", pe_lcomm
, 1},
1179 {"ffloat", float_cons
, 'f'},
1180 {"dfloat", float_cons
, 'd'},
1181 {"tfloat", float_cons
, 'x'},
1183 {"slong", signed_cons
, 4},
1184 {"noopt", s_ignore
, 0},
1185 {"optim", s_ignore
, 0},
1186 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1187 {"code16", set_code_flag
, CODE_16BIT
},
1188 {"code32", set_code_flag
, CODE_32BIT
},
1190 {"code64", set_code_flag
, CODE_64BIT
},
1192 {"intel_syntax", set_intel_syntax
, 1},
1193 {"att_syntax", set_intel_syntax
, 0},
1194 {"intel_mnemonic", set_intel_mnemonic
, 1},
1195 {"att_mnemonic", set_intel_mnemonic
, 0},
1196 {"allow_index_reg", set_allow_index_reg
, 1},
1197 {"disallow_index_reg", set_allow_index_reg
, 0},
1198 {"sse_check", set_check
, 0},
1199 {"operand_check", set_check
, 1},
1200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1201 {"largecomm", handle_large_common
, 0},
1203 {"file", dwarf2_directive_file
, 0},
1204 {"loc", dwarf2_directive_loc
, 0},
1205 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1208 {"secrel32", pe_directive_secrel
, 0},
1213 /* For interface with expression (). */
1214 extern char *input_line_pointer
;
1216 /* Hash table for instruction mnemonic lookup. */
1217 static struct hash_control
*op_hash
;
1219 /* Hash table for register lookup. */
1220 static struct hash_control
*reg_hash
;
1222 /* Various efficient no-op patterns for aligning code labels.
1223 Note: Don't try to assemble the instructions in the comments.
1224 0L and 0w are not legal. */
1225 static const unsigned char f32_1
[] =
1227 static const unsigned char f32_2
[] =
1228 {0x66,0x90}; /* xchg %ax,%ax */
1229 static const unsigned char f32_3
[] =
1230 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1231 static const unsigned char f32_4
[] =
1232 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1233 static const unsigned char f32_6
[] =
1234 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1235 static const unsigned char f32_7
[] =
1236 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1237 static const unsigned char f16_3
[] =
1238 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1239 static const unsigned char f16_4
[] =
1240 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1241 static const unsigned char jump_disp8
[] =
1242 {0xeb}; /* jmp disp8 */
1243 static const unsigned char jump32_disp32
[] =
1244 {0xe9}; /* jmp disp32 */
1245 static const unsigned char jump16_disp32
[] =
1246 {0x66,0xe9}; /* jmp disp32 */
1247 /* 32-bit NOPs patterns. */
1248 static const unsigned char *const f32_patt
[] = {
1249 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1251 /* 16-bit NOPs patterns. */
1252 static const unsigned char *const f16_patt
[] = {
1253 f32_1
, f32_2
, f16_3
, f16_4
1255 /* nopl (%[re]ax) */
1256 static const unsigned char alt_3
[] =
1258 /* nopl 0(%[re]ax) */
1259 static const unsigned char alt_4
[] =
1260 {0x0f,0x1f,0x40,0x00};
1261 /* nopl 0(%[re]ax,%[re]ax,1) */
1262 static const unsigned char alt_5
[] =
1263 {0x0f,0x1f,0x44,0x00,0x00};
1264 /* nopw 0(%[re]ax,%[re]ax,1) */
1265 static const unsigned char alt_6
[] =
1266 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1267 /* nopl 0L(%[re]ax) */
1268 static const unsigned char alt_7
[] =
1269 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1270 /* nopl 0L(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_8
[] =
1272 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1273 /* nopw 0L(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_9
[] =
1275 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1276 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_10
[] =
1278 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* data16 nopw %cs:0L(%eax,%eax,1) */
1280 static const unsigned char alt_11
[] =
1281 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* 32-bit and 64-bit NOPs patterns. */
1283 static const unsigned char *const alt_patt
[] = {
1284 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1285 alt_9
, alt_10
, alt_11
1288 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1289 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1292 i386_output_nops (char *where
, const unsigned char *const *patt
,
1293 int count
, int max_single_nop_size
)
1296 /* Place the longer NOP first. */
1299 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1301 /* Use the smaller one if the requsted one isn't available. */
1304 max_single_nop_size
--;
1305 nops
= patt
[max_single_nop_size
- 1];
1308 last
= count
% max_single_nop_size
;
1311 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1312 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1316 nops
= patt
[last
- 1];
1319 /* Use the smaller one plus one-byte NOP if the needed one
1322 nops
= patt
[last
- 1];
1323 memcpy (where
+ offset
, nops
, last
);
1324 where
[offset
+ last
] = *patt
[0];
1327 memcpy (where
+ offset
, nops
, last
);
1332 fits_in_imm7 (offsetT num
)
1334 return (num
& 0x7f) == num
;
1338 fits_in_imm31 (offsetT num
)
1340 return (num
& 0x7fffffff) == num
;
1343 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1344 single NOP instruction LIMIT. */
1347 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1349 const unsigned char *const *patt
= NULL
;
1350 int max_single_nop_size
;
1351 /* Maximum number of NOPs before switching to jump over NOPs. */
1352 int max_number_of_nops
;
1354 switch (fragP
->fr_type
)
1363 /* We need to decide which NOP sequence to use for 32bit and
1364 64bit. When -mtune= is used:
1366 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1367 PROCESSOR_GENERIC32, f32_patt will be used.
1368 2. For the rest, alt_patt will be used.
1370 When -mtune= isn't used, alt_patt will be used if
1371 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1374 When -march= or .arch is used, we can't use anything beyond
1375 cpu_arch_isa_flags. */
1377 if (flag_code
== CODE_16BIT
)
1380 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1381 /* Limit number of NOPs to 2 in 16-bit mode. */
1382 max_number_of_nops
= 2;
1386 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1388 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1389 switch (cpu_arch_tune
)
1391 case PROCESSOR_UNKNOWN
:
1392 /* We use cpu_arch_isa_flags to check if we SHOULD
1393 optimize with nops. */
1394 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1399 case PROCESSOR_PENTIUM4
:
1400 case PROCESSOR_NOCONA
:
1401 case PROCESSOR_CORE
:
1402 case PROCESSOR_CORE2
:
1403 case PROCESSOR_COREI7
:
1404 case PROCESSOR_L1OM
:
1405 case PROCESSOR_K1OM
:
1406 case PROCESSOR_GENERIC64
:
1408 case PROCESSOR_ATHLON
:
1410 case PROCESSOR_AMDFAM10
:
1412 case PROCESSOR_ZNVER
:
1416 case PROCESSOR_I386
:
1417 case PROCESSOR_I486
:
1418 case PROCESSOR_PENTIUM
:
1419 case PROCESSOR_PENTIUMPRO
:
1420 case PROCESSOR_IAMCU
:
1421 case PROCESSOR_GENERIC32
:
1428 switch (fragP
->tc_frag_data
.tune
)
1430 case PROCESSOR_UNKNOWN
:
1431 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1432 PROCESSOR_UNKNOWN. */
1436 case PROCESSOR_I386
:
1437 case PROCESSOR_I486
:
1438 case PROCESSOR_PENTIUM
:
1439 case PROCESSOR_IAMCU
:
1441 case PROCESSOR_ATHLON
:
1443 case PROCESSOR_AMDFAM10
:
1445 case PROCESSOR_ZNVER
:
1447 case PROCESSOR_GENERIC32
:
1448 /* We use cpu_arch_isa_flags to check if we CAN optimize
1450 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1455 case PROCESSOR_PENTIUMPRO
:
1456 case PROCESSOR_PENTIUM4
:
1457 case PROCESSOR_NOCONA
:
1458 case PROCESSOR_CORE
:
1459 case PROCESSOR_CORE2
:
1460 case PROCESSOR_COREI7
:
1461 case PROCESSOR_L1OM
:
1462 case PROCESSOR_K1OM
:
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_GENERIC64
:
1474 if (patt
== f32_patt
)
1476 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1477 /* Limit number of NOPs to 2 for older processors. */
1478 max_number_of_nops
= 2;
1482 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1483 /* Limit number of NOPs to 7 for newer processors. */
1484 max_number_of_nops
= 7;
1489 limit
= max_single_nop_size
;
1491 if (fragP
->fr_type
== rs_fill_nop
)
1493 /* Output NOPs for .nop directive. */
1494 if (limit
> max_single_nop_size
)
1496 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1497 _("invalid single nop size: %d "
1498 "(expect within [0, %d])"),
1499 limit
, max_single_nop_size
);
1504 fragP
->fr_var
= count
;
1506 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1508 /* Generate jump over NOPs. */
1509 offsetT disp
= count
- 2;
1510 if (fits_in_imm7 (disp
))
1512 /* Use "jmp disp8" if possible. */
1514 where
[0] = jump_disp8
[0];
1520 unsigned int size_of_jump
;
1522 if (flag_code
== CODE_16BIT
)
1524 where
[0] = jump16_disp32
[0];
1525 where
[1] = jump16_disp32
[1];
1530 where
[0] = jump32_disp32
[0];
1534 count
-= size_of_jump
+ 4;
1535 if (!fits_in_imm31 (count
))
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("jump over nop padding out of range"));
1542 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1543 where
+= size_of_jump
+ 4;
1547 /* Generate multiple NOPs. */
1548 i386_output_nops (where
, patt
, count
, limit
);
1552 operand_type_all_zero (const union i386_operand_type
*x
)
1554 switch (ARRAY_SIZE(x
->array
))
1565 return !x
->array
[0];
1572 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1574 switch (ARRAY_SIZE(x
->array
))
1592 operand_type_equal (const union i386_operand_type
*x
,
1593 const union i386_operand_type
*y
)
1595 switch (ARRAY_SIZE(x
->array
))
1598 if (x
->array
[2] != y
->array
[2])
1602 if (x
->array
[1] != y
->array
[1])
1606 return x
->array
[0] == y
->array
[0];
1614 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1616 switch (ARRAY_SIZE(x
->array
))
1631 return !x
->array
[0];
1638 cpu_flags_equal (const union i386_cpu_flags
*x
,
1639 const union i386_cpu_flags
*y
)
1641 switch (ARRAY_SIZE(x
->array
))
1644 if (x
->array
[3] != y
->array
[3])
1648 if (x
->array
[2] != y
->array
[2])
1652 if (x
->array
[1] != y
->array
[1])
1656 return x
->array
[0] == y
->array
[0];
1664 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1666 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1667 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1670 static INLINE i386_cpu_flags
1671 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1673 switch (ARRAY_SIZE (x
.array
))
1676 x
.array
[3] &= y
.array
[3];
1679 x
.array
[2] &= y
.array
[2];
1682 x
.array
[1] &= y
.array
[1];
1685 x
.array
[0] &= y
.array
[0];
1693 static INLINE i386_cpu_flags
1694 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1696 switch (ARRAY_SIZE (x
.array
))
1699 x
.array
[3] |= y
.array
[3];
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_cpu_flags
1717 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[3] &= ~y
.array
[3];
1725 x
.array
[2] &= ~y
.array
[2];
1728 x
.array
[1] &= ~y
.array
[1];
1731 x
.array
[0] &= ~y
.array
[0];
1739 #define CPU_FLAGS_ARCH_MATCH 0x1
1740 #define CPU_FLAGS_64BIT_MATCH 0x2
1742 #define CPU_FLAGS_PERFECT_MATCH \
1743 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1745 /* Return CPU flags match bits. */
1748 cpu_flags_match (const insn_template
*t
)
1750 i386_cpu_flags x
= t
->cpu_flags
;
1751 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1753 x
.bitfield
.cpu64
= 0;
1754 x
.bitfield
.cpuno64
= 0;
1756 if (cpu_flags_all_zero (&x
))
1758 /* This instruction is available on all archs. */
1759 match
|= CPU_FLAGS_ARCH_MATCH
;
1763 /* This instruction is available only on some archs. */
1764 i386_cpu_flags cpu
= cpu_arch_flags
;
1766 /* AVX512VL is no standalone feature - match it and then strip it. */
1767 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1769 x
.bitfield
.cpuavx512vl
= 0;
1771 cpu
= cpu_flags_and (x
, cpu
);
1772 if (!cpu_flags_all_zero (&cpu
))
1774 if (x
.bitfield
.cpuavx
)
1776 /* We need to check a few extra flags with AVX. */
1777 if (cpu
.bitfield
.cpuavx
1778 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1779 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1780 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1781 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1782 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 else if (x
.bitfield
.cpuavx512f
)
1786 /* We need to check a few extra flags with AVX512F. */
1787 if (cpu
.bitfield
.cpuavx512f
1788 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1789 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1790 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1791 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 match
|= CPU_FLAGS_ARCH_MATCH
;
1800 static INLINE i386_operand_type
1801 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_operand_type
1821 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[2] &= ~y
.array
[2];
1829 x
.array
[1] &= ~y
.array
[1];
1832 x
.array
[0] &= ~y
.array
[0];
1840 static INLINE i386_operand_type
1841 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1843 switch (ARRAY_SIZE (x
.array
))
1846 x
.array
[2] |= y
.array
[2];
1849 x
.array
[1] |= y
.array
[1];
1852 x
.array
[0] |= y
.array
[0];
1860 static INLINE i386_operand_type
1861 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[2] ^= y
.array
[2];
1869 x
.array
[1] ^= y
.array
[1];
1872 x
.array
[0] ^= y
.array
[0];
1880 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1881 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1882 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1883 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1884 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1885 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1886 static const i386_operand_type anydisp
1887 = OPERAND_TYPE_ANYDISP
;
1888 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1889 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1890 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1891 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1892 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1893 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1894 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1895 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1896 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1897 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1898 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1899 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1910 operand_type_check (i386_operand_type t
, enum operand_type c
)
1915 return t
.bitfield
.reg
;
1918 return (t
.bitfield
.imm8
1922 || t
.bitfield
.imm32s
1923 || t
.bitfield
.imm64
);
1926 return (t
.bitfield
.disp8
1927 || t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
1930 || t
.bitfield
.disp64
);
1933 return (t
.bitfield
.disp8
1934 || t
.bitfield
.disp16
1935 || t
.bitfield
.disp32
1936 || t
.bitfield
.disp32s
1937 || t
.bitfield
.disp64
1938 || t
.bitfield
.baseindex
);
1947 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1948 between operand GIVEN and opeand WANTED for instruction template T. */
1951 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1954 return !((i
.types
[given
].bitfield
.byte
1955 && !t
->operand_types
[wanted
].bitfield
.byte
)
1956 || (i
.types
[given
].bitfield
.word
1957 && !t
->operand_types
[wanted
].bitfield
.word
)
1958 || (i
.types
[given
].bitfield
.dword
1959 && !t
->operand_types
[wanted
].bitfield
.dword
)
1960 || (i
.types
[given
].bitfield
.qword
1961 && !t
->operand_types
[wanted
].bitfield
.qword
)
1962 || (i
.types
[given
].bitfield
.tbyte
1963 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1966 /* Return 1 if there is no conflict in SIMD register between operand
1967 GIVEN and opeand WANTED for instruction template T. */
1970 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.xmmword
1974 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1975 || (i
.types
[given
].bitfield
.ymmword
1976 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1977 || (i
.types
[given
].bitfield
.zmmword
1978 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1981 /* Return 1 if there is no conflict in any size between operand GIVEN
1982 and opeand WANTED for instruction template T. */
1985 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1988 return (match_operand_size (t
, wanted
, given
)
1989 && !((i
.types
[given
].bitfield
.unspecified
1991 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1992 || (i
.types
[given
].bitfield
.fword
1993 && !t
->operand_types
[wanted
].bitfield
.fword
)
1994 /* For scalar opcode templates to allow register and memory
1995 operands at the same time, some special casing is needed
1996 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1997 down-conversion vpmov*. */
1998 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1999 && !t
->opcode_modifier
.broadcast
2000 && (t
->operand_types
[wanted
].bitfield
.byte
2001 || t
->operand_types
[wanted
].bitfield
.word
2002 || t
->operand_types
[wanted
].bitfield
.dword
2003 || t
->operand_types
[wanted
].bitfield
.qword
))
2004 ? (i
.types
[given
].bitfield
.xmmword
2005 || i
.types
[given
].bitfield
.ymmword
2006 || i
.types
[given
].bitfield
.zmmword
)
2007 : !match_simd_size(t
, wanted
, given
))));
2010 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2011 operands for instruction template T, and it has MATCH_REVERSE set if there
2012 is no size conflict on any operands for the template with operands reversed
2013 (and the template allows for reversing in the first place). */
2015 #define MATCH_STRAIGHT 1
2016 #define MATCH_REVERSE 2
2018 static INLINE
unsigned int
2019 operand_size_match (const insn_template
*t
)
2021 unsigned int j
, match
= MATCH_STRAIGHT
;
2023 /* Don't check jump instructions. */
2024 if (t
->opcode_modifier
.jump
2025 || t
->opcode_modifier
.jumpbyte
2026 || t
->opcode_modifier
.jumpdword
2027 || t
->opcode_modifier
.jumpintersegment
)
2030 /* Check memory and accumulator operand size. */
2031 for (j
= 0; j
< i
.operands
; j
++)
2033 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2034 && t
->operand_types
[j
].bitfield
.anysize
)
2037 if (t
->operand_types
[j
].bitfield
.reg
2038 && !match_operand_size (t
, j
, j
))
2044 if (t
->operand_types
[j
].bitfield
.regsimd
2045 && !match_simd_size (t
, j
, j
))
2051 if (t
->operand_types
[j
].bitfield
.acc
2052 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2058 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2065 if (!t
->opcode_modifier
.d
)
2069 i
.error
= operand_size_mismatch
;
2073 /* Check reverse. */
2074 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2076 for (j
= 0; j
< i
.operands
; j
++)
2078 unsigned int given
= i
.operands
- j
- 1;
2080 if (t
->operand_types
[j
].bitfield
.reg
2081 && !match_operand_size (t
, j
, given
))
2084 if (t
->operand_types
[j
].bitfield
.regsimd
2085 && !match_simd_size (t
, j
, given
))
2088 if (t
->operand_types
[j
].bitfield
.acc
2089 && (!match_operand_size (t
, j
, given
)
2090 || !match_simd_size (t
, j
, given
)))
2093 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2097 return match
| MATCH_REVERSE
;
2101 operand_type_match (i386_operand_type overlap
,
2102 i386_operand_type given
)
2104 i386_operand_type temp
= overlap
;
2106 temp
.bitfield
.jumpabsolute
= 0;
2107 temp
.bitfield
.unspecified
= 0;
2108 temp
.bitfield
.byte
= 0;
2109 temp
.bitfield
.word
= 0;
2110 temp
.bitfield
.dword
= 0;
2111 temp
.bitfield
.fword
= 0;
2112 temp
.bitfield
.qword
= 0;
2113 temp
.bitfield
.tbyte
= 0;
2114 temp
.bitfield
.xmmword
= 0;
2115 temp
.bitfield
.ymmword
= 0;
2116 temp
.bitfield
.zmmword
= 0;
2117 if (operand_type_all_zero (&temp
))
2120 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2121 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2125 i
.error
= operand_type_mismatch
;
2129 /* If given types g0 and g1 are registers they must be of the same type
2130 unless the expected operand type register overlap is null.
2131 Memory operand size of certain SIMD instructions is also being checked
2135 operand_type_register_match (i386_operand_type g0
,
2136 i386_operand_type t0
,
2137 i386_operand_type g1
,
2138 i386_operand_type t1
)
2140 if (!g0
.bitfield
.reg
2141 && !g0
.bitfield
.regsimd
2142 && (!operand_type_check (g0
, anymem
)
2143 || g0
.bitfield
.unspecified
2144 || !t0
.bitfield
.regsimd
))
2147 if (!g1
.bitfield
.reg
2148 && !g1
.bitfield
.regsimd
2149 && (!operand_type_check (g1
, anymem
)
2150 || g1
.bitfield
.unspecified
2151 || !t1
.bitfield
.regsimd
))
2154 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2155 && g0
.bitfield
.word
== g1
.bitfield
.word
2156 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2157 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2158 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2159 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2160 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2163 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2164 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2165 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2166 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2167 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2168 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2169 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2172 i
.error
= register_type_mismatch
;
2177 static INLINE
unsigned int
2178 register_number (const reg_entry
*r
)
2180 unsigned int nr
= r
->reg_num
;
2182 if (r
->reg_flags
& RegRex
)
2185 if (r
->reg_flags
& RegVRex
)
2191 static INLINE
unsigned int
2192 mode_from_disp_size (i386_operand_type t
)
2194 if (t
.bitfield
.disp8
)
2196 else if (t
.bitfield
.disp16
2197 || t
.bitfield
.disp32
2198 || t
.bitfield
.disp32s
)
2205 fits_in_signed_byte (addressT num
)
2207 return num
+ 0x80 <= 0xff;
2211 fits_in_unsigned_byte (addressT num
)
2217 fits_in_unsigned_word (addressT num
)
2219 return num
<= 0xffff;
2223 fits_in_signed_word (addressT num
)
2225 return num
+ 0x8000 <= 0xffff;
2229 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2234 return num
+ 0x80000000 <= 0xffffffff;
2236 } /* fits_in_signed_long() */
2239 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2244 return num
<= 0xffffffff;
2246 } /* fits_in_unsigned_long() */
2249 fits_in_disp8 (offsetT num
)
2251 int shift
= i
.memshift
;
2257 mask
= (1 << shift
) - 1;
2259 /* Return 0 if NUM isn't properly aligned. */
2263 /* Check if NUM will fit in 8bit after shift. */
2264 return fits_in_signed_byte (num
>> shift
);
2268 fits_in_imm4 (offsetT num
)
2270 return (num
& 0xf) == num
;
2273 static i386_operand_type
2274 smallest_imm_type (offsetT num
)
2276 i386_operand_type t
;
2278 operand_type_set (&t
, 0);
2279 t
.bitfield
.imm64
= 1;
2281 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2283 /* This code is disabled on the 486 because all the Imm1 forms
2284 in the opcode table are slower on the i486. They're the
2285 versions with the implicitly specified single-position
2286 displacement, which has another syntax if you really want to
2288 t
.bitfield
.imm1
= 1;
2289 t
.bitfield
.imm8
= 1;
2290 t
.bitfield
.imm8s
= 1;
2291 t
.bitfield
.imm16
= 1;
2292 t
.bitfield
.imm32
= 1;
2293 t
.bitfield
.imm32s
= 1;
2295 else if (fits_in_signed_byte (num
))
2297 t
.bitfield
.imm8
= 1;
2298 t
.bitfield
.imm8s
= 1;
2299 t
.bitfield
.imm16
= 1;
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_byte (num
))
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm16
= 1;
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2312 t
.bitfield
.imm16
= 1;
2313 t
.bitfield
.imm32
= 1;
2314 t
.bitfield
.imm32s
= 1;
2316 else if (fits_in_signed_long (num
))
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_long (num
))
2322 t
.bitfield
.imm32
= 1;
2328 offset_in_range (offsetT val
, int size
)
2334 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2335 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2336 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2338 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2344 /* If BFD64, sign extend val for 32bit address mode. */
2345 if (flag_code
!= CODE_64BIT
2346 || i
.prefix
[ADDR_PREFIX
])
2347 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2348 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2351 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2353 char buf1
[40], buf2
[40];
2355 sprint_value (buf1
, val
);
2356 sprint_value (buf2
, val
& mask
);
2357 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2372 a. PREFIX_EXIST if attempting to add a prefix where one from the
2373 same class already exists.
2374 b. PREFIX_LOCK if lock prefix is added.
2375 c. PREFIX_REP if rep/repne prefix is added.
2376 d. PREFIX_DS if ds prefix is added.
2377 e. PREFIX_OTHER if other prefix is added.
2380 static enum PREFIX_GROUP
2381 add_prefix (unsigned int prefix
)
2383 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2386 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2387 && flag_code
== CODE_64BIT
)
2389 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2390 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2391 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2392 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2403 case DS_PREFIX_OPCODE
:
2406 case CS_PREFIX_OPCODE
:
2407 case ES_PREFIX_OPCODE
:
2408 case FS_PREFIX_OPCODE
:
2409 case GS_PREFIX_OPCODE
:
2410 case SS_PREFIX_OPCODE
:
2414 case REPNE_PREFIX_OPCODE
:
2415 case REPE_PREFIX_OPCODE
:
2420 case LOCK_PREFIX_OPCODE
:
2429 case ADDR_PREFIX_OPCODE
:
2433 case DATA_PREFIX_OPCODE
:
2437 if (i
.prefix
[q
] != 0)
2445 i
.prefix
[q
] |= prefix
;
2448 as_bad (_("same type of prefix used twice"));
2454 update_code_flag (int value
, int check
)
2456 PRINTF_LIKE ((*as_error
));
2458 flag_code
= (enum flag_code
) value
;
2459 if (flag_code
== CODE_64BIT
)
2461 cpu_arch_flags
.bitfield
.cpu64
= 1;
2462 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2466 cpu_arch_flags
.bitfield
.cpu64
= 0;
2467 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2469 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2472 as_error
= as_fatal
;
2475 (*as_error
) (_("64bit mode not supported on `%s'."),
2476 cpu_arch_name
? cpu_arch_name
: default_arch
);
2478 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2481 as_error
= as_fatal
;
2484 (*as_error
) (_("32bit mode not supported on `%s'."),
2485 cpu_arch_name
? cpu_arch_name
: default_arch
);
2487 stackop_size
= '\0';
2491 set_code_flag (int value
)
2493 update_code_flag (value
, 0);
2497 set_16bit_gcc_code_flag (int new_code_flag
)
2499 flag_code
= (enum flag_code
) new_code_flag
;
2500 if (flag_code
!= CODE_16BIT
)
2502 cpu_arch_flags
.bitfield
.cpu64
= 0;
2503 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2504 stackop_size
= LONG_MNEM_SUFFIX
;
2508 set_intel_syntax (int syntax_flag
)
2510 /* Find out if register prefixing is specified. */
2511 int ask_naked_reg
= 0;
2514 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2517 int e
= get_symbol_name (&string
);
2519 if (strcmp (string
, "prefix") == 0)
2521 else if (strcmp (string
, "noprefix") == 0)
2524 as_bad (_("bad argument to syntax directive."));
2525 (void) restore_line_pointer (e
);
2527 demand_empty_rest_of_line ();
2529 intel_syntax
= syntax_flag
;
2531 if (ask_naked_reg
== 0)
2532 allow_naked_reg
= (intel_syntax
2533 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2535 allow_naked_reg
= (ask_naked_reg
< 0);
2537 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2539 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2540 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2541 register_prefix
= allow_naked_reg
? "" : "%";
2545 set_intel_mnemonic (int mnemonic_flag
)
2547 intel_mnemonic
= mnemonic_flag
;
2551 set_allow_index_reg (int flag
)
2553 allow_index_reg
= flag
;
2557 set_check (int what
)
2559 enum check_kind
*kind
;
2564 kind
= &operand_check
;
2575 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2578 int e
= get_symbol_name (&string
);
2580 if (strcmp (string
, "none") == 0)
2582 else if (strcmp (string
, "warning") == 0)
2583 *kind
= check_warning
;
2584 else if (strcmp (string
, "error") == 0)
2585 *kind
= check_error
;
2587 as_bad (_("bad argument to %s_check directive."), str
);
2588 (void) restore_line_pointer (e
);
2591 as_bad (_("missing argument for %s_check directive"), str
);
2593 demand_empty_rest_of_line ();
2597 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2598 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2601 static const char *arch
;
2603 /* Intel LIOM is only supported on ELF. */
2609 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2610 use default_arch. */
2611 arch
= cpu_arch_name
;
2613 arch
= default_arch
;
2616 /* If we are targeting Intel MCU, we must enable it. */
2617 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2618 || new_flag
.bitfield
.cpuiamcu
)
2621 /* If we are targeting Intel L1OM, we must enable it. */
2622 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2623 || new_flag
.bitfield
.cpul1om
)
2626 /* If we are targeting Intel K1OM, we must enable it. */
2627 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2628 || new_flag
.bitfield
.cpuk1om
)
2631 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2636 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2643 int e
= get_symbol_name (&string
);
2645 i386_cpu_flags flags
;
2647 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2649 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2651 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2655 cpu_arch_name
= cpu_arch
[j
].name
;
2656 cpu_sub_arch_name
= NULL
;
2657 cpu_arch_flags
= cpu_arch
[j
].flags
;
2658 if (flag_code
== CODE_64BIT
)
2660 cpu_arch_flags
.bitfield
.cpu64
= 1;
2661 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2665 cpu_arch_flags
.bitfield
.cpu64
= 0;
2666 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2668 cpu_arch_isa
= cpu_arch
[j
].type
;
2669 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2670 if (!cpu_arch_tune_set
)
2672 cpu_arch_tune
= cpu_arch_isa
;
2673 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2678 flags
= cpu_flags_or (cpu_arch_flags
,
2681 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2683 if (cpu_sub_arch_name
)
2685 char *name
= cpu_sub_arch_name
;
2686 cpu_sub_arch_name
= concat (name
,
2688 (const char *) NULL
);
2692 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2693 cpu_arch_flags
= flags
;
2694 cpu_arch_isa_flags
= flags
;
2698 = cpu_flags_or (cpu_arch_isa_flags
,
2700 (void) restore_line_pointer (e
);
2701 demand_empty_rest_of_line ();
2706 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2708 /* Disable an ISA extension. */
2709 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2710 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2712 flags
= cpu_flags_and_not (cpu_arch_flags
,
2713 cpu_noarch
[j
].flags
);
2714 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2716 if (cpu_sub_arch_name
)
2718 char *name
= cpu_sub_arch_name
;
2719 cpu_sub_arch_name
= concat (name
, string
,
2720 (const char *) NULL
);
2724 cpu_sub_arch_name
= xstrdup (string
);
2725 cpu_arch_flags
= flags
;
2726 cpu_arch_isa_flags
= flags
;
2728 (void) restore_line_pointer (e
);
2729 demand_empty_rest_of_line ();
2733 j
= ARRAY_SIZE (cpu_arch
);
2736 if (j
>= ARRAY_SIZE (cpu_arch
))
2737 as_bad (_("no such architecture: `%s'"), string
);
2739 *input_line_pointer
= e
;
2742 as_bad (_("missing cpu architecture"));
2744 no_cond_jump_promotion
= 0;
2745 if (*input_line_pointer
== ','
2746 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2751 ++input_line_pointer
;
2752 e
= get_symbol_name (&string
);
2754 if (strcmp (string
, "nojumps") == 0)
2755 no_cond_jump_promotion
= 1;
2756 else if (strcmp (string
, "jumps") == 0)
2759 as_bad (_("no such architecture modifier: `%s'"), string
);
2761 (void) restore_line_pointer (e
);
2764 demand_empty_rest_of_line ();
2767 enum bfd_architecture
2770 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2772 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2773 || flag_code
!= CODE_64BIT
)
2774 as_fatal (_("Intel L1OM is 64bit ELF only"));
2775 return bfd_arch_l1om
;
2777 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2779 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2780 || flag_code
!= CODE_64BIT
)
2781 as_fatal (_("Intel K1OM is 64bit ELF only"));
2782 return bfd_arch_k1om
;
2784 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2786 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2787 || flag_code
== CODE_64BIT
)
2788 as_fatal (_("Intel MCU is 32bit ELF only"));
2789 return bfd_arch_iamcu
;
2792 return bfd_arch_i386
;
2798 if (!strncmp (default_arch
, "x86_64", 6))
2800 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || default_arch
[6] != '\0')
2804 as_fatal (_("Intel L1OM is 64bit ELF only"));
2805 return bfd_mach_l1om
;
2807 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2809 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2810 || default_arch
[6] != '\0')
2811 as_fatal (_("Intel K1OM is 64bit ELF only"));
2812 return bfd_mach_k1om
;
2814 else if (default_arch
[6] == '\0')
2815 return bfd_mach_x86_64
;
2817 return bfd_mach_x64_32
;
2819 else if (!strcmp (default_arch
, "i386")
2820 || !strcmp (default_arch
, "iamcu"))
2822 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2825 as_fatal (_("Intel MCU is 32bit ELF only"));
2826 return bfd_mach_i386_iamcu
;
2829 return bfd_mach_i386_i386
;
2832 as_fatal (_("unknown architecture"));
2838 const char *hash_err
;
2840 /* Support pseudo prefixes like {disp32}. */
2841 lex_type
['{'] = LEX_BEGIN_NAME
;
2843 /* Initialize op_hash hash table. */
2844 op_hash
= hash_new ();
2847 const insn_template
*optab
;
2848 templates
*core_optab
;
2850 /* Setup for loop. */
2852 core_optab
= XNEW (templates
);
2853 core_optab
->start
= optab
;
2858 if (optab
->name
== NULL
2859 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2861 /* different name --> ship out current template list;
2862 add to hash table; & begin anew. */
2863 core_optab
->end
= optab
;
2864 hash_err
= hash_insert (op_hash
,
2866 (void *) core_optab
);
2869 as_fatal (_("can't hash %s: %s"),
2873 if (optab
->name
== NULL
)
2875 core_optab
= XNEW (templates
);
2876 core_optab
->start
= optab
;
2881 /* Initialize reg_hash hash table. */
2882 reg_hash
= hash_new ();
2884 const reg_entry
*regtab
;
2885 unsigned int regtab_size
= i386_regtab_size
;
2887 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2889 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2891 as_fatal (_("can't hash %s: %s"),
2897 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2902 for (c
= 0; c
< 256; c
++)
2907 mnemonic_chars
[c
] = c
;
2908 register_chars
[c
] = c
;
2909 operand_chars
[c
] = c
;
2911 else if (ISLOWER (c
))
2913 mnemonic_chars
[c
] = c
;
2914 register_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2917 else if (ISUPPER (c
))
2919 mnemonic_chars
[c
] = TOLOWER (c
);
2920 register_chars
[c
] = mnemonic_chars
[c
];
2921 operand_chars
[c
] = c
;
2923 else if (c
== '{' || c
== '}')
2925 mnemonic_chars
[c
] = c
;
2926 operand_chars
[c
] = c
;
2929 if (ISALPHA (c
) || ISDIGIT (c
))
2930 identifier_chars
[c
] = c
;
2933 identifier_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2939 identifier_chars
['@'] = '@';
2942 identifier_chars
['?'] = '?';
2943 operand_chars
['?'] = '?';
2945 digit_chars
['-'] = '-';
2946 mnemonic_chars
['_'] = '_';
2947 mnemonic_chars
['-'] = '-';
2948 mnemonic_chars
['.'] = '.';
2949 identifier_chars
['_'] = '_';
2950 identifier_chars
['.'] = '.';
2952 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2953 operand_chars
[(unsigned char) *p
] = *p
;
2956 if (flag_code
== CODE_64BIT
)
2958 #if defined (OBJ_COFF) && defined (TE_PE)
2959 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2962 x86_dwarf2_return_column
= 16;
2964 x86_cie_data_alignment
= -8;
2968 x86_dwarf2_return_column
= 8;
2969 x86_cie_data_alignment
= -4;
2974 i386_print_statistics (FILE *file
)
2976 hash_print_statistics (file
, "i386 opcode", op_hash
);
2977 hash_print_statistics (file
, "i386 register", reg_hash
);
2982 /* Debugging routines for md_assemble. */
2983 static void pte (insn_template
*);
2984 static void pt (i386_operand_type
);
2985 static void pe (expressionS
*);
2986 static void ps (symbolS
*);
2989 pi (char *line
, i386_insn
*x
)
2993 fprintf (stdout
, "%s: template ", line
);
2995 fprintf (stdout
, " address: base %s index %s scale %x\n",
2996 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2997 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2998 x
->log2_scale_factor
);
2999 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3000 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3001 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3002 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3003 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3004 (x
->rex
& REX_W
) != 0,
3005 (x
->rex
& REX_R
) != 0,
3006 (x
->rex
& REX_X
) != 0,
3007 (x
->rex
& REX_B
) != 0);
3008 for (j
= 0; j
< x
->operands
; j
++)
3010 fprintf (stdout
, " #%d: ", j
+ 1);
3012 fprintf (stdout
, "\n");
3013 if (x
->types
[j
].bitfield
.reg
3014 || x
->types
[j
].bitfield
.regmmx
3015 || x
->types
[j
].bitfield
.regsimd
3016 || x
->types
[j
].bitfield
.sreg2
3017 || x
->types
[j
].bitfield
.sreg3
3018 || x
->types
[j
].bitfield
.control
3019 || x
->types
[j
].bitfield
.debug
3020 || x
->types
[j
].bitfield
.test
)
3021 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3022 if (operand_type_check (x
->types
[j
], imm
))
3024 if (operand_type_check (x
->types
[j
], disp
))
3025 pe (x
->op
[j
].disps
);
3030 pte (insn_template
*t
)
3033 fprintf (stdout
, " %d operands ", t
->operands
);
3034 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3035 if (t
->extension_opcode
!= None
)
3036 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3037 if (t
->opcode_modifier
.d
)
3038 fprintf (stdout
, "D");
3039 if (t
->opcode_modifier
.w
)
3040 fprintf (stdout
, "W");
3041 fprintf (stdout
, "\n");
3042 for (j
= 0; j
< t
->operands
; j
++)
3044 fprintf (stdout
, " #%d type ", j
+ 1);
3045 pt (t
->operand_types
[j
]);
3046 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " operation %d\n", e
->X_op
);
3054 fprintf (stdout
, " add_number %ld (%lx)\n",
3055 (long) e
->X_add_number
, (long) e
->X_add_number
);
3056 if (e
->X_add_symbol
)
3058 fprintf (stdout
, " add_symbol ");
3059 ps (e
->X_add_symbol
);
3060 fprintf (stdout
, "\n");
3064 fprintf (stdout
, " op_symbol ");
3065 ps (e
->X_op_symbol
);
3066 fprintf (stdout
, "\n");
3073 fprintf (stdout
, "%s type %s%s",
3075 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3076 segment_name (S_GET_SEGMENT (s
)));
3079 static struct type_name
3081 i386_operand_type mask
;
3084 const type_names
[] =
3086 { OPERAND_TYPE_REG8
, "r8" },
3087 { OPERAND_TYPE_REG16
, "r16" },
3088 { OPERAND_TYPE_REG32
, "r32" },
3089 { OPERAND_TYPE_REG64
, "r64" },
3090 { OPERAND_TYPE_IMM8
, "i8" },
3091 { OPERAND_TYPE_IMM8
, "i8s" },
3092 { OPERAND_TYPE_IMM16
, "i16" },
3093 { OPERAND_TYPE_IMM32
, "i32" },
3094 { OPERAND_TYPE_IMM32S
, "i32s" },
3095 { OPERAND_TYPE_IMM64
, "i64" },
3096 { OPERAND_TYPE_IMM1
, "i1" },
3097 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3098 { OPERAND_TYPE_DISP8
, "d8" },
3099 { OPERAND_TYPE_DISP16
, "d16" },
3100 { OPERAND_TYPE_DISP32
, "d32" },
3101 { OPERAND_TYPE_DISP32S
, "d32s" },
3102 { OPERAND_TYPE_DISP64
, "d64" },
3103 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3104 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3105 { OPERAND_TYPE_CONTROL
, "control reg" },
3106 { OPERAND_TYPE_TEST
, "test reg" },
3107 { OPERAND_TYPE_DEBUG
, "debug reg" },
3108 { OPERAND_TYPE_FLOATREG
, "FReg" },
3109 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3110 { OPERAND_TYPE_SREG2
, "SReg2" },
3111 { OPERAND_TYPE_SREG3
, "SReg3" },
3112 { OPERAND_TYPE_ACC
, "Acc" },
3113 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3114 { OPERAND_TYPE_REGMMX
, "rMMX" },
3115 { OPERAND_TYPE_REGXMM
, "rXMM" },
3116 { OPERAND_TYPE_REGYMM
, "rYMM" },
3117 { OPERAND_TYPE_REGZMM
, "rZMM" },
3118 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3119 { OPERAND_TYPE_ESSEG
, "es" },
3123 pt (i386_operand_type t
)
3126 i386_operand_type a
;
3128 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3130 a
= operand_type_and (t
, type_names
[j
].mask
);
3131 if (!operand_type_all_zero (&a
))
3132 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3137 #endif /* DEBUG386 */
3139 static bfd_reloc_code_real_type
3140 reloc (unsigned int size
,
3143 bfd_reloc_code_real_type other
)
3145 if (other
!= NO_RELOC
)
3147 reloc_howto_type
*rel
;
3152 case BFD_RELOC_X86_64_GOT32
:
3153 return BFD_RELOC_X86_64_GOT64
;
3155 case BFD_RELOC_X86_64_GOTPLT64
:
3156 return BFD_RELOC_X86_64_GOTPLT64
;
3158 case BFD_RELOC_X86_64_PLTOFF64
:
3159 return BFD_RELOC_X86_64_PLTOFF64
;
3161 case BFD_RELOC_X86_64_GOTPC32
:
3162 other
= BFD_RELOC_X86_64_GOTPC64
;
3164 case BFD_RELOC_X86_64_GOTPCREL
:
3165 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3167 case BFD_RELOC_X86_64_TPOFF32
:
3168 other
= BFD_RELOC_X86_64_TPOFF64
;
3170 case BFD_RELOC_X86_64_DTPOFF32
:
3171 other
= BFD_RELOC_X86_64_DTPOFF64
;
3177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3178 if (other
== BFD_RELOC_SIZE32
)
3181 other
= BFD_RELOC_SIZE64
;
3184 as_bad (_("there are no pc-relative size relocations"));
3190 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3191 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3194 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3196 as_bad (_("unknown relocation (%u)"), other
);
3197 else if (size
!= bfd_get_reloc_size (rel
))
3198 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3199 bfd_get_reloc_size (rel
),
3201 else if (pcrel
&& !rel
->pc_relative
)
3202 as_bad (_("non-pc-relative relocation for pc-relative field"));
3203 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3205 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3207 as_bad (_("relocated field and relocation type differ in signedness"));
3216 as_bad (_("there are no unsigned pc-relative relocations"));
3219 case 1: return BFD_RELOC_8_PCREL
;
3220 case 2: return BFD_RELOC_16_PCREL
;
3221 case 4: return BFD_RELOC_32_PCREL
;
3222 case 8: return BFD_RELOC_64_PCREL
;
3224 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3231 case 4: return BFD_RELOC_X86_64_32S
;
3236 case 1: return BFD_RELOC_8
;
3237 case 2: return BFD_RELOC_16
;
3238 case 4: return BFD_RELOC_32
;
3239 case 8: return BFD_RELOC_64
;
3241 as_bad (_("cannot do %s %u byte relocation"),
3242 sign
> 0 ? "signed" : "unsigned", size
);
3248 /* Here we decide which fixups can be adjusted to make them relative to
3249 the beginning of the section instead of the symbol. Basically we need
3250 to make sure that the dynamic relocations are done correctly, so in
3251 some cases we force the original symbol to be used. */
3254 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3260 /* Don't adjust pc-relative references to merge sections in 64-bit
3262 if (use_rela_relocations
3263 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3267 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3268 and changed later by validate_fix. */
3269 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3270 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3273 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3274 for size relocations. */
3275 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3276 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3277 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3278 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3279 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3305 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3306 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3307 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3314 intel_float_operand (const char *mnemonic
)
3316 /* Note that the value returned is meaningful only for opcodes with (memory)
3317 operands, hence the code here is free to improperly handle opcodes that
3318 have no operands (for better performance and smaller code). */
3320 if (mnemonic
[0] != 'f')
3321 return 0; /* non-math */
3323 switch (mnemonic
[1])
3325 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3326 the fs segment override prefix not currently handled because no
3327 call path can make opcodes without operands get here */
3329 return 2 /* integer op */;
3331 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3332 return 3; /* fldcw/fldenv */
3335 if (mnemonic
[2] != 'o' /* fnop */)
3336 return 3; /* non-waiting control op */
3339 if (mnemonic
[2] == 's')
3340 return 3; /* frstor/frstpm */
3343 if (mnemonic
[2] == 'a')
3344 return 3; /* fsave */
3345 if (mnemonic
[2] == 't')
3347 switch (mnemonic
[3])
3349 case 'c': /* fstcw */
3350 case 'd': /* fstdw */
3351 case 'e': /* fstenv */
3352 case 's': /* fsts[gw] */
3358 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3359 return 0; /* fxsave/fxrstor are not really math ops */
3366 /* Build the VEX prefix. */
3369 build_vex_prefix (const insn_template
*t
)
3371 unsigned int register_specifier
;
3372 unsigned int implied_prefix
;
3373 unsigned int vector_length
;
3376 /* Check register specifier. */
3377 if (i
.vex
.register_specifier
)
3379 register_specifier
=
3380 ~register_number (i
.vex
.register_specifier
) & 0xf;
3381 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3384 register_specifier
= 0xf;
3386 /* Use 2-byte VEX prefix by swapping destination and source operand
3387 if there are more than 1 register operand. */
3388 if (i
.reg_operands
> 1
3389 && i
.vec_encoding
!= vex_encoding_vex3
3390 && i
.dir_encoding
== dir_encoding_default
3391 && i
.operands
== i
.reg_operands
3392 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3393 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3394 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3397 unsigned int xchg
= i
.operands
- 1;
3398 union i386_op temp_op
;
3399 i386_operand_type temp_type
;
3401 temp_type
= i
.types
[xchg
];
3402 i
.types
[xchg
] = i
.types
[0];
3403 i
.types
[0] = temp_type
;
3404 temp_op
= i
.op
[xchg
];
3405 i
.op
[xchg
] = i
.op
[0];
3408 gas_assert (i
.rm
.mode
== 3);
3412 i
.rm
.regmem
= i
.rm
.reg
;
3415 if (i
.tm
.opcode_modifier
.d
)
3416 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3417 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3418 else /* Use the next insn. */
3422 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3423 vector_length
= avxscalar
;
3424 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3430 /* Determine vector length from the last multi-length vector
3433 for (op
= t
->operands
; op
--;)
3434 if (t
->operand_types
[op
].bitfield
.xmmword
3435 && t
->operand_types
[op
].bitfield
.ymmword
3436 && i
.types
[op
].bitfield
.ymmword
)
3443 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3448 case DATA_PREFIX_OPCODE
:
3451 case REPE_PREFIX_OPCODE
:
3454 case REPNE_PREFIX_OPCODE
:
3461 /* Check the REX.W bit and VEXW. */
3462 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3463 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3464 else if (i
.tm
.opcode_modifier
.vexw
)
3465 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3467 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3469 /* Use 2-byte VEX prefix if possible. */
3471 && i
.vec_encoding
!= vex_encoding_vex3
3472 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3473 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3475 /* 2-byte VEX prefix. */
3479 i
.vex
.bytes
[0] = 0xc5;
3481 /* Check the REX.R bit. */
3482 r
= (i
.rex
& REX_R
) ? 0 : 1;
3483 i
.vex
.bytes
[1] = (r
<< 7
3484 | register_specifier
<< 3
3485 | vector_length
<< 2
3490 /* 3-byte VEX prefix. */
3495 switch (i
.tm
.opcode_modifier
.vexopcode
)
3499 i
.vex
.bytes
[0] = 0xc4;
3503 i
.vex
.bytes
[0] = 0xc4;
3507 i
.vex
.bytes
[0] = 0xc4;
3511 i
.vex
.bytes
[0] = 0x8f;
3515 i
.vex
.bytes
[0] = 0x8f;
3519 i
.vex
.bytes
[0] = 0x8f;
3525 /* The high 3 bits of the second VEX byte are 1's compliment
3526 of RXB bits from REX. */
3527 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3529 i
.vex
.bytes
[2] = (w
<< 7
3530 | register_specifier
<< 3
3531 | vector_length
<< 2
3536 static INLINE bfd_boolean
3537 is_evex_encoding (const insn_template
*t
)
3539 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3540 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3541 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3544 static INLINE bfd_boolean
3545 is_any_vex_encoding (const insn_template
*t
)
3547 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3548 || is_evex_encoding (t
);
3551 /* Build the EVEX prefix. */
3554 build_evex_prefix (void)
3556 unsigned int register_specifier
;
3557 unsigned int implied_prefix
;
3559 rex_byte vrex_used
= 0;
3561 /* Check register specifier. */
3562 if (i
.vex
.register_specifier
)
3564 gas_assert ((i
.vrex
& REX_X
) == 0);
3566 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3567 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3568 register_specifier
+= 8;
3569 /* The upper 16 registers are encoded in the fourth byte of the
3571 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3572 i
.vex
.bytes
[3] = 0x8;
3573 register_specifier
= ~register_specifier
& 0xf;
3577 register_specifier
= 0xf;
3579 /* Encode upper 16 vector index register in the fourth byte of
3581 if (!(i
.vrex
& REX_X
))
3582 i
.vex
.bytes
[3] = 0x8;
3587 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3592 case DATA_PREFIX_OPCODE
:
3595 case REPE_PREFIX_OPCODE
:
3598 case REPNE_PREFIX_OPCODE
:
3605 /* 4 byte EVEX prefix. */
3607 i
.vex
.bytes
[0] = 0x62;
3610 switch (i
.tm
.opcode_modifier
.vexopcode
)
3626 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3628 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3630 /* The fifth bit of the second EVEX byte is 1's compliment of the
3631 REX_R bit in VREX. */
3632 if (!(i
.vrex
& REX_R
))
3633 i
.vex
.bytes
[1] |= 0x10;
3637 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3639 /* When all operands are registers, the REX_X bit in REX is not
3640 used. We reuse it to encode the upper 16 registers, which is
3641 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3642 as 1's compliment. */
3643 if ((i
.vrex
& REX_B
))
3646 i
.vex
.bytes
[1] &= ~0x40;
3650 /* EVEX instructions shouldn't need the REX prefix. */
3651 i
.vrex
&= ~vrex_used
;
3652 gas_assert (i
.vrex
== 0);
3654 /* Check the REX.W bit and VEXW. */
3655 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3656 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3657 else if (i
.tm
.opcode_modifier
.vexw
)
3658 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3660 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3662 /* Encode the U bit. */
3663 implied_prefix
|= 0x4;
3665 /* The third byte of the EVEX prefix. */
3666 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3668 /* The fourth byte of the EVEX prefix. */
3669 /* The zeroing-masking bit. */
3670 if (i
.mask
&& i
.mask
->zeroing
)
3671 i
.vex
.bytes
[3] |= 0x80;
3673 /* Don't always set the broadcast bit if there is no RC. */
3676 /* Encode the vector length. */
3677 unsigned int vec_length
;
3679 if (!i
.tm
.opcode_modifier
.evex
3680 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3684 /* Determine vector length from the last multi-length vector
3687 for (op
= i
.operands
; op
--;)
3688 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3689 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3690 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3692 if (i
.types
[op
].bitfield
.zmmword
)
3694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3697 else if (i
.types
[op
].bitfield
.ymmword
)
3699 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3702 else if (i
.types
[op
].bitfield
.xmmword
)
3704 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3707 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3709 switch (i
.broadcast
->bytes
)
3712 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3715 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3718 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3727 if (op
>= MAX_OPERANDS
)
3731 switch (i
.tm
.opcode_modifier
.evex
)
3733 case EVEXLIG
: /* LL' is ignored */
3734 vec_length
= evexlig
<< 5;
3737 vec_length
= 0 << 5;
3740 vec_length
= 1 << 5;
3743 vec_length
= 2 << 5;
3749 i
.vex
.bytes
[3] |= vec_length
;
3750 /* Encode the broadcast bit. */
3752 i
.vex
.bytes
[3] |= 0x10;
3756 if (i
.rounding
->type
!= saeonly
)
3757 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3759 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3762 if (i
.mask
&& i
.mask
->mask
)
3763 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3767 process_immext (void)
3771 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3774 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3775 with an opcode suffix which is coded in the same place as an
3776 8-bit immediate field would be.
3777 Here we check those operands and remove them afterwards. */
3780 for (x
= 0; x
< i
.operands
; x
++)
3781 if (register_number (i
.op
[x
].regs
) != x
)
3782 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3783 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3789 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3791 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3792 suffix which is coded in the same place as an 8-bit immediate
3794 Here we check those operands and remove them afterwards. */
3797 if (i
.operands
!= 3)
3800 for (x
= 0; x
< 2; x
++)
3801 if (register_number (i
.op
[x
].regs
) != x
)
3802 goto bad_register_operand
;
3804 /* Check for third operand for mwaitx/monitorx insn. */
3805 if (register_number (i
.op
[x
].regs
)
3806 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3808 bad_register_operand
:
3809 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3810 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3818 which is coded in the same place as an 8-bit immediate field
3819 would be. Here we fake an 8-bit immediate operand from the
3820 opcode suffix stored in tm.extension_opcode.
3822 AVX instructions also use this encoding, for some of
3823 3 argument instructions. */
3825 gas_assert (i
.imm_operands
<= 1
3827 || (is_any_vex_encoding (&i
.tm
)
3828 && i
.operands
<= 4)));
3830 exp
= &im_expressions
[i
.imm_operands
++];
3831 i
.op
[i
.operands
].imms
= exp
;
3832 i
.types
[i
.operands
] = imm8
;
3834 exp
->X_op
= O_constant
;
3835 exp
->X_add_number
= i
.tm
.extension_opcode
;
3836 i
.tm
.extension_opcode
= None
;
3843 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3848 as_bad (_("invalid instruction `%s' after `%s'"),
3849 i
.tm
.name
, i
.hle_prefix
);
3852 if (i
.prefix
[LOCK_PREFIX
])
3854 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3858 case HLEPrefixRelease
:
3859 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3861 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3865 if (i
.mem_operands
== 0
3866 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3868 as_bad (_("memory destination needed for instruction `%s'"
3869 " after `xrelease'"), i
.tm
.name
);
3876 /* Try the shortest encoding by shortening operand size. */
3879 optimize_encoding (void)
3883 if (optimize_for_space
3884 && i
.reg_operands
== 1
3885 && i
.imm_operands
== 1
3886 && !i
.types
[1].bitfield
.byte
3887 && i
.op
[0].imms
->X_op
== O_constant
3888 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3889 && ((i
.tm
.base_opcode
== 0xa8
3890 && i
.tm
.extension_opcode
== None
)
3891 || (i
.tm
.base_opcode
== 0xf6
3892 && i
.tm
.extension_opcode
== 0x0)))
3895 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3897 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3898 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3900 i
.types
[1].bitfield
.byte
= 1;
3901 /* Ignore the suffix. */
3903 if (base_regnum
>= 4
3904 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3906 /* Handle SP, BP, SI and DI registers. */
3907 if (i
.types
[1].bitfield
.word
)
3909 else if (i
.types
[1].bitfield
.dword
)
3917 else if (flag_code
== CODE_64BIT
3918 && ((i
.types
[1].bitfield
.qword
3919 && i
.reg_operands
== 1
3920 && i
.imm_operands
== 1
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && ((i
.tm
.base_opcode
== 0xb0
3923 && i
.tm
.extension_opcode
== None
3924 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3925 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3926 && (((i
.tm
.base_opcode
== 0x24
3927 || i
.tm
.base_opcode
== 0xa8)
3928 && i
.tm
.extension_opcode
== None
)
3929 || (i
.tm
.base_opcode
== 0x80
3930 && i
.tm
.extension_opcode
== 0x4)
3931 || ((i
.tm
.base_opcode
== 0xf6
3932 || i
.tm
.base_opcode
== 0xc6)
3933 && i
.tm
.extension_opcode
== 0x0)))))
3934 || (i
.types
[0].bitfield
.qword
3935 && ((i
.reg_operands
== 2
3936 && i
.op
[0].regs
== i
.op
[1].regs
3937 && ((i
.tm
.base_opcode
== 0x30
3938 || i
.tm
.base_opcode
== 0x28)
3939 && i
.tm
.extension_opcode
== None
))
3940 || (i
.reg_operands
== 1
3942 && i
.tm
.base_opcode
== 0x30
3943 && i
.tm
.extension_opcode
== None
)))))
3946 andq $imm31, %r64 -> andl $imm31, %r32
3947 testq $imm31, %r64 -> testl $imm31, %r32
3948 xorq %r64, %r64 -> xorl %r32, %r32
3949 subq %r64, %r64 -> subl %r32, %r32
3950 movq $imm31, %r64 -> movl $imm31, %r32
3951 movq $imm32, %r64 -> movl $imm32, %r32
3953 i
.tm
.opcode_modifier
.norex64
= 1;
3954 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3957 movq $imm31, %r64 -> movl $imm31, %r32
3958 movq $imm32, %r64 -> movl $imm32, %r32
3960 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3961 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3962 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3963 i
.types
[0].bitfield
.imm32
= 1;
3964 i
.types
[0].bitfield
.imm32s
= 0;
3965 i
.types
[0].bitfield
.imm64
= 0;
3966 i
.types
[1].bitfield
.dword
= 1;
3967 i
.types
[1].bitfield
.qword
= 0;
3968 if (i
.tm
.base_opcode
== 0xc6)
3971 movq $imm31, %r64 -> movl $imm31, %r32
3973 i
.tm
.base_opcode
= 0xb0;
3974 i
.tm
.extension_opcode
= None
;
3975 i
.tm
.opcode_modifier
.shortform
= 1;
3976 i
.tm
.opcode_modifier
.modrm
= 0;
3980 else if (i
.reg_operands
== 3
3981 && i
.op
[0].regs
== i
.op
[1].regs
3982 && !i
.types
[2].bitfield
.xmmword
3983 && (i
.tm
.opcode_modifier
.vex
3984 || ((!i
.mask
|| i
.mask
->zeroing
)
3986 && is_evex_encoding (&i
.tm
)
3987 && (i
.vec_encoding
!= vex_encoding_evex
3988 || cpu_arch_flags
.bitfield
.cpuavx
3989 || cpu_arch_isa_flags
.bitfield
.cpuavx
3990 || cpu_arch_flags
.bitfield
.cpuavx512vl
3991 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
3992 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3993 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3994 && i
.types
[2].bitfield
.ymmword
))))
3995 && ((i
.tm
.base_opcode
== 0x55
3996 || i
.tm
.base_opcode
== 0x6655
3997 || i
.tm
.base_opcode
== 0x66df
3998 || i
.tm
.base_opcode
== 0x57
3999 || i
.tm
.base_opcode
== 0x6657
4000 || i
.tm
.base_opcode
== 0x66ef
4001 || i
.tm
.base_opcode
== 0x66f8
4002 || i
.tm
.base_opcode
== 0x66f9
4003 || i
.tm
.base_opcode
== 0x66fa
4004 || i
.tm
.base_opcode
== 0x66fb
4005 || i
.tm
.base_opcode
== 0x42
4006 || i
.tm
.base_opcode
== 0x6642
4007 || i
.tm
.base_opcode
== 0x47
4008 || i
.tm
.base_opcode
== 0x6647)
4009 && i
.tm
.extension_opcode
== None
))
4012 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4014 EVEX VOP %zmmM, %zmmM, %zmmN
4015 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4017 EVEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4019 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4020 VEX VOP %ymmM, %ymmM, %ymmN
4021 -> VEX VOP %xmmM, %xmmM, %xmmN
4022 VOP, one of vpandn and vpxor:
4023 VEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX VOP %xmmM, %xmmM, %xmmN
4025 VOP, one of vpandnd and vpandnq:
4026 EVEX VOP %zmmM, %zmmM, %zmmN
4027 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 EVEX VOP %ymmM, %ymmM, %ymmN
4030 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4031 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4032 VOP, one of vpxord and vpxorq:
4033 EVEX VOP %zmmM, %zmmM, %zmmN
4034 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 EVEX VOP %ymmM, %ymmM, %ymmN
4037 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4038 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4039 VOP, one of kxord and kxorq:
4040 VEX VOP %kM, %kM, %kN
4041 -> VEX kxorw %kM, %kM, %kN
4042 VOP, one of kandnd and kandnq:
4043 VEX VOP %kM, %kM, %kN
4044 -> VEX kandnw %kM, %kM, %kN
4046 if (is_evex_encoding (&i
.tm
))
4048 if (i
.vec_encoding
!= vex_encoding_evex
4049 && (cpu_arch_flags
.bitfield
.cpuavx
4050 || cpu_arch_isa_flags
.bitfield
.cpuavx
))
4052 i
.tm
.opcode_modifier
.vex
= VEX128
;
4053 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4054 i
.tm
.opcode_modifier
.evex
= 0;
4056 else if (optimize
> 1
4057 && (cpu_arch_flags
.bitfield
.cpuavx512vl
4058 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
))
4059 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4063 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4065 i
.tm
.base_opcode
&= 0xff;
4066 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4069 i
.tm
.opcode_modifier
.vex
= VEX128
;
4071 if (i
.tm
.opcode_modifier
.vex
)
4072 for (j
= 0; j
< 3; j
++)
4074 i
.types
[j
].bitfield
.xmmword
= 1;
4075 i
.types
[j
].bitfield
.ymmword
= 0;
4080 /* This is the guts of the machine-dependent assembler. LINE points to a
4081 machine dependent instruction. This function is supposed to emit
4082 the frags/bytes it assembles to. */
4085 md_assemble (char *line
)
4088 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4089 const insn_template
*t
;
4091 /* Initialize globals. */
4092 memset (&i
, '\0', sizeof (i
));
4093 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4094 i
.reloc
[j
] = NO_RELOC
;
4095 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4096 memset (im_expressions
, '\0', sizeof (im_expressions
));
4097 save_stack_p
= save_stack
;
4099 /* First parse an instruction mnemonic & call i386_operand for the operands.
4100 We assume that the scrubber has arranged it so that line[0] is the valid
4101 start of a (possibly prefixed) mnemonic. */
4103 line
= parse_insn (line
, mnemonic
);
4106 mnem_suffix
= i
.suffix
;
4108 line
= parse_operands (line
, mnemonic
);
4110 xfree (i
.memop1_string
);
4111 i
.memop1_string
= NULL
;
4115 /* Now we've parsed the mnemonic into a set of templates, and have the
4116 operands at hand. */
4118 /* All intel opcodes have reversed operands except for "bound" and
4119 "enter". We also don't reverse intersegment "jmp" and "call"
4120 instructions with 2 immediate operands so that the immediate segment
4121 precedes the offset, as it does when in AT&T mode. */
4124 && (strcmp (mnemonic
, "bound") != 0)
4125 && (strcmp (mnemonic
, "invlpga") != 0)
4126 && !(operand_type_check (i
.types
[0], imm
)
4127 && operand_type_check (i
.types
[1], imm
)))
4130 /* The order of the immediates should be reversed
4131 for 2 immediates extrq and insertq instructions */
4132 if (i
.imm_operands
== 2
4133 && (strcmp (mnemonic
, "extrq") == 0
4134 || strcmp (mnemonic
, "insertq") == 0))
4135 swap_2_operands (0, 1);
4140 /* Don't optimize displacement for movabs since it only takes 64bit
4143 && i
.disp_encoding
!= disp_encoding_32bit
4144 && (flag_code
!= CODE_64BIT
4145 || strcmp (mnemonic
, "movabs") != 0))
4148 /* Next, we find a template that matches the given insn,
4149 making sure the overlap of the given operands types is consistent
4150 with the template operand types. */
4152 if (!(t
= match_template (mnem_suffix
)))
4155 if (sse_check
!= check_none
4156 && !i
.tm
.opcode_modifier
.noavx
4157 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4158 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4159 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4160 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4161 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4162 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4163 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4164 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4165 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4166 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4168 (sse_check
== check_warning
4170 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4173 /* Zap movzx and movsx suffix. The suffix has been set from
4174 "word ptr" or "byte ptr" on the source operand in Intel syntax
4175 or extracted from mnemonic in AT&T syntax. But we'll use
4176 the destination register to choose the suffix for encoding. */
4177 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4179 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4180 there is no suffix, the default will be byte extension. */
4181 if (i
.reg_operands
!= 2
4184 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4189 if (i
.tm
.opcode_modifier
.fwait
)
4190 if (!add_prefix (FWAIT_OPCODE
))
4193 /* Check if REP prefix is OK. */
4194 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4196 as_bad (_("invalid instruction `%s' after `%s'"),
4197 i
.tm
.name
, i
.rep_prefix
);
4201 /* Check for lock without a lockable instruction. Destination operand
4202 must be memory unless it is xchg (0x86). */
4203 if (i
.prefix
[LOCK_PREFIX
]
4204 && (!i
.tm
.opcode_modifier
.islockable
4205 || i
.mem_operands
== 0
4206 || (i
.tm
.base_opcode
!= 0x86
4207 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4209 as_bad (_("expecting lockable instruction after `lock'"));
4213 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4214 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4216 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4220 /* Check if HLE prefix is OK. */
4221 if (i
.hle_prefix
&& !check_hle ())
4224 /* Check BND prefix. */
4225 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4226 as_bad (_("expecting valid branch instruction after `bnd'"));
4228 /* Check NOTRACK prefix. */
4229 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4230 as_bad (_("expecting indirect branch instruction after `notrack'"));
4232 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4234 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4235 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4236 else if (flag_code
!= CODE_16BIT
4237 ? i
.prefix
[ADDR_PREFIX
]
4238 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4239 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4242 /* Insert BND prefix. */
4243 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4245 if (!i
.prefix
[BND_PREFIX
])
4246 add_prefix (BND_PREFIX_OPCODE
);
4247 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4249 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4250 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4254 /* Check string instruction segment overrides. */
4255 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4257 if (!check_string ())
4259 i
.disp_operands
= 0;
4262 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4263 optimize_encoding ();
4265 if (!process_suffix ())
4268 /* Update operand types. */
4269 for (j
= 0; j
< i
.operands
; j
++)
4270 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4272 /* Make still unresolved immediate matches conform to size of immediate
4273 given in i.suffix. */
4274 if (!finalize_imm ())
4277 if (i
.types
[0].bitfield
.imm1
)
4278 i
.imm_operands
= 0; /* kludge for shift insns. */
4280 /* We only need to check those implicit registers for instructions
4281 with 3 operands or less. */
4282 if (i
.operands
<= 3)
4283 for (j
= 0; j
< i
.operands
; j
++)
4284 if (i
.types
[j
].bitfield
.inoutportreg
4285 || i
.types
[j
].bitfield
.shiftcount
4286 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4289 /* ImmExt should be processed after SSE2AVX. */
4290 if (!i
.tm
.opcode_modifier
.sse2avx
4291 && i
.tm
.opcode_modifier
.immext
)
4294 /* For insns with operands there are more diddles to do to the opcode. */
4297 if (!process_operands ())
4300 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4302 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4303 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4306 if (is_any_vex_encoding (&i
.tm
))
4308 if (flag_code
== CODE_16BIT
)
4310 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4315 if (i
.tm
.opcode_modifier
.vex
)
4316 build_vex_prefix (t
);
4318 build_evex_prefix ();
4321 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4322 instructions may define INT_OPCODE as well, so avoid this corner
4323 case for those instructions that use MODRM. */
4324 if (i
.tm
.base_opcode
== INT_OPCODE
4325 && !i
.tm
.opcode_modifier
.modrm
4326 && i
.op
[0].imms
->X_add_number
== 3)
4328 i
.tm
.base_opcode
= INT3_OPCODE
;
4332 if ((i
.tm
.opcode_modifier
.jump
4333 || i
.tm
.opcode_modifier
.jumpbyte
4334 || i
.tm
.opcode_modifier
.jumpdword
)
4335 && i
.op
[0].disps
->X_op
== O_constant
)
4337 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4338 the absolute address given by the constant. Since ix86 jumps and
4339 calls are pc relative, we need to generate a reloc. */
4340 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4341 i
.op
[0].disps
->X_op
= O_symbol
;
4344 if (i
.tm
.opcode_modifier
.rex64
)
4347 /* For 8 bit registers we need an empty rex prefix. Also if the
4348 instruction already has a prefix, we need to convert old
4349 registers to new ones. */
4351 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4352 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4353 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4354 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4355 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4356 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4361 i
.rex
|= REX_OPCODE
;
4362 for (x
= 0; x
< 2; x
++)
4364 /* Look for 8 bit operand that uses old registers. */
4365 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4366 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4368 /* In case it is "hi" register, give up. */
4369 if (i
.op
[x
].regs
->reg_num
> 3)
4370 as_bad (_("can't encode register '%s%s' in an "
4371 "instruction requiring REX prefix."),
4372 register_prefix
, i
.op
[x
].regs
->reg_name
);
4374 /* Otherwise it is equivalent to the extended register.
4375 Since the encoding doesn't change this is merely
4376 cosmetic cleanup for debug output. */
4378 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4383 if (i
.rex
== 0 && i
.rex_encoding
)
4385 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4386 that uses legacy register. If it is "hi" register, don't add
4387 the REX_OPCODE byte. */
4389 for (x
= 0; x
< 2; x
++)
4390 if (i
.types
[x
].bitfield
.reg
4391 && i
.types
[x
].bitfield
.byte
4392 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4393 && i
.op
[x
].regs
->reg_num
> 3)
4395 i
.rex_encoding
= FALSE
;
4404 add_prefix (REX_OPCODE
| i
.rex
);
4406 /* We are ready to output the insn. */
4411 parse_insn (char *line
, char *mnemonic
)
4414 char *token_start
= l
;
4417 const insn_template
*t
;
4423 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4428 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4430 as_bad (_("no such instruction: `%s'"), token_start
);
4435 if (!is_space_char (*l
)
4436 && *l
!= END_OF_INSN
4438 || (*l
!= PREFIX_SEPARATOR
4441 as_bad (_("invalid character %s in mnemonic"),
4442 output_invalid (*l
));
4445 if (token_start
== l
)
4447 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4448 as_bad (_("expecting prefix; got nothing"));
4450 as_bad (_("expecting mnemonic; got nothing"));
4454 /* Look up instruction (or prefix) via hash table. */
4455 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4457 if (*l
!= END_OF_INSN
4458 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4459 && current_templates
4460 && current_templates
->start
->opcode_modifier
.isprefix
)
4462 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4464 as_bad ((flag_code
!= CODE_64BIT
4465 ? _("`%s' is only supported in 64-bit mode")
4466 : _("`%s' is not supported in 64-bit mode")),
4467 current_templates
->start
->name
);
4470 /* If we are in 16-bit mode, do not allow addr16 or data16.
4471 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4472 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4473 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4474 && flag_code
!= CODE_64BIT
4475 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4476 ^ (flag_code
== CODE_16BIT
)))
4478 as_bad (_("redundant %s prefix"),
4479 current_templates
->start
->name
);
4482 if (current_templates
->start
->opcode_length
== 0)
4484 /* Handle pseudo prefixes. */
4485 switch (current_templates
->start
->base_opcode
)
4489 i
.disp_encoding
= disp_encoding_8bit
;
4493 i
.disp_encoding
= disp_encoding_32bit
;
4497 i
.dir_encoding
= dir_encoding_load
;
4501 i
.dir_encoding
= dir_encoding_store
;
4505 i
.vec_encoding
= vex_encoding_vex2
;
4509 i
.vec_encoding
= vex_encoding_vex3
;
4513 i
.vec_encoding
= vex_encoding_evex
;
4517 i
.rex_encoding
= TRUE
;
4521 i
.no_optimize
= TRUE
;
4529 /* Add prefix, checking for repeated prefixes. */
4530 switch (add_prefix (current_templates
->start
->base_opcode
))
4535 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4536 i
.notrack_prefix
= current_templates
->start
->name
;
4539 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4540 i
.hle_prefix
= current_templates
->start
->name
;
4541 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4542 i
.bnd_prefix
= current_templates
->start
->name
;
4544 i
.rep_prefix
= current_templates
->start
->name
;
4550 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4557 if (!current_templates
)
4559 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4560 Check if we should swap operand or force 32bit displacement in
4562 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4563 i
.dir_encoding
= dir_encoding_swap
;
4564 else if (mnem_p
- 3 == dot_p
4567 i
.disp_encoding
= disp_encoding_8bit
;
4568 else if (mnem_p
- 4 == dot_p
4572 i
.disp_encoding
= disp_encoding_32bit
;
4577 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4580 if (!current_templates
)
4583 if (mnem_p
> mnemonic
)
4585 /* See if we can get a match by trimming off a suffix. */
4588 case WORD_MNEM_SUFFIX
:
4589 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4590 i
.suffix
= SHORT_MNEM_SUFFIX
;
4593 case BYTE_MNEM_SUFFIX
:
4594 case QWORD_MNEM_SUFFIX
:
4595 i
.suffix
= mnem_p
[-1];
4597 current_templates
= (const templates
*) hash_find (op_hash
,
4600 case SHORT_MNEM_SUFFIX
:
4601 case LONG_MNEM_SUFFIX
:
4604 i
.suffix
= mnem_p
[-1];
4606 current_templates
= (const templates
*) hash_find (op_hash
,
4615 if (intel_float_operand (mnemonic
) == 1)
4616 i
.suffix
= SHORT_MNEM_SUFFIX
;
4618 i
.suffix
= LONG_MNEM_SUFFIX
;
4620 current_templates
= (const templates
*) hash_find (op_hash
,
4627 if (!current_templates
)
4629 as_bad (_("no such instruction: `%s'"), token_start
);
4634 if (current_templates
->start
->opcode_modifier
.jump
4635 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4637 /* Check for a branch hint. We allow ",pt" and ",pn" for
4638 predict taken and predict not taken respectively.
4639 I'm not sure that branch hints actually do anything on loop
4640 and jcxz insns (JumpByte) for current Pentium4 chips. They
4641 may work in the future and it doesn't hurt to accept them
4643 if (l
[0] == ',' && l
[1] == 'p')
4647 if (!add_prefix (DS_PREFIX_OPCODE
))
4651 else if (l
[2] == 'n')
4653 if (!add_prefix (CS_PREFIX_OPCODE
))
4659 /* Any other comma loses. */
4662 as_bad (_("invalid character %s in mnemonic"),
4663 output_invalid (*l
));
4667 /* Check if instruction is supported on specified architecture. */
4669 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4671 supported
|= cpu_flags_match (t
);
4672 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4674 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4675 as_warn (_("use .code16 to ensure correct addressing mode"));
4681 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4682 as_bad (flag_code
== CODE_64BIT
4683 ? _("`%s' is not supported in 64-bit mode")
4684 : _("`%s' is only supported in 64-bit mode"),
4685 current_templates
->start
->name
);
4687 as_bad (_("`%s' is not supported on `%s%s'"),
4688 current_templates
->start
->name
,
4689 cpu_arch_name
? cpu_arch_name
: default_arch
,
4690 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4696 parse_operands (char *l
, const char *mnemonic
)
4700 /* 1 if operand is pending after ','. */
4701 unsigned int expecting_operand
= 0;
4703 /* Non-zero if operand parens not balanced. */
4704 unsigned int paren_not_balanced
;
4706 while (*l
!= END_OF_INSN
)
4708 /* Skip optional white space before operand. */
4709 if (is_space_char (*l
))
4711 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4713 as_bad (_("invalid character %s before operand %d"),
4714 output_invalid (*l
),
4718 token_start
= l
; /* After white space. */
4719 paren_not_balanced
= 0;
4720 while (paren_not_balanced
|| *l
!= ',')
4722 if (*l
== END_OF_INSN
)
4724 if (paren_not_balanced
)
4727 as_bad (_("unbalanced parenthesis in operand %d."),
4730 as_bad (_("unbalanced brackets in operand %d."),
4735 break; /* we are done */
4737 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4739 as_bad (_("invalid character %s in operand %d"),
4740 output_invalid (*l
),
4747 ++paren_not_balanced
;
4749 --paren_not_balanced
;
4754 ++paren_not_balanced
;
4756 --paren_not_balanced
;
4760 if (l
!= token_start
)
4761 { /* Yes, we've read in another operand. */
4762 unsigned int operand_ok
;
4763 this_operand
= i
.operands
++;
4764 if (i
.operands
> MAX_OPERANDS
)
4766 as_bad (_("spurious operands; (%d operands/instruction max)"),
4770 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4771 /* Now parse operand adding info to 'i' as we go along. */
4772 END_STRING_AND_SAVE (l
);
4774 if (i
.mem_operands
> 1)
4776 as_bad (_("too many memory references for `%s'"),
4783 i386_intel_operand (token_start
,
4784 intel_float_operand (mnemonic
));
4786 operand_ok
= i386_att_operand (token_start
);
4788 RESTORE_END_STRING (l
);
4794 if (expecting_operand
)
4796 expecting_operand_after_comma
:
4797 as_bad (_("expecting operand after ','; got nothing"));
4802 as_bad (_("expecting operand before ','; got nothing"));
4807 /* Now *l must be either ',' or END_OF_INSN. */
4810 if (*++l
== END_OF_INSN
)
4812 /* Just skip it, if it's \n complain. */
4813 goto expecting_operand_after_comma
;
4815 expecting_operand
= 1;
4822 swap_2_operands (int xchg1
, int xchg2
)
4824 union i386_op temp_op
;
4825 i386_operand_type temp_type
;
4826 unsigned int temp_flags
;
4827 enum bfd_reloc_code_real temp_reloc
;
4829 temp_type
= i
.types
[xchg2
];
4830 i
.types
[xchg2
] = i
.types
[xchg1
];
4831 i
.types
[xchg1
] = temp_type
;
4833 temp_flags
= i
.flags
[xchg2
];
4834 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4835 i
.flags
[xchg1
] = temp_flags
;
4837 temp_op
= i
.op
[xchg2
];
4838 i
.op
[xchg2
] = i
.op
[xchg1
];
4839 i
.op
[xchg1
] = temp_op
;
4841 temp_reloc
= i
.reloc
[xchg2
];
4842 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4843 i
.reloc
[xchg1
] = temp_reloc
;
4847 if (i
.mask
->operand
== xchg1
)
4848 i
.mask
->operand
= xchg2
;
4849 else if (i
.mask
->operand
== xchg2
)
4850 i
.mask
->operand
= xchg1
;
4854 if (i
.broadcast
->operand
== xchg1
)
4855 i
.broadcast
->operand
= xchg2
;
4856 else if (i
.broadcast
->operand
== xchg2
)
4857 i
.broadcast
->operand
= xchg1
;
4861 if (i
.rounding
->operand
== xchg1
)
4862 i
.rounding
->operand
= xchg2
;
4863 else if (i
.rounding
->operand
== xchg2
)
4864 i
.rounding
->operand
= xchg1
;
4869 swap_operands (void)
4875 swap_2_operands (1, i
.operands
- 2);
4879 swap_2_operands (0, i
.operands
- 1);
4885 if (i
.mem_operands
== 2)
4887 const seg_entry
*temp_seg
;
4888 temp_seg
= i
.seg
[0];
4889 i
.seg
[0] = i
.seg
[1];
4890 i
.seg
[1] = temp_seg
;
4894 /* Try to ensure constant immediates are represented in the smallest
4899 char guess_suffix
= 0;
4903 guess_suffix
= i
.suffix
;
4904 else if (i
.reg_operands
)
4906 /* Figure out a suffix from the last register operand specified.
4907 We can't do this properly yet, ie. excluding InOutPortReg,
4908 but the following works for instructions with immediates.
4909 In any case, we can't set i.suffix yet. */
4910 for (op
= i
.operands
; --op
>= 0;)
4911 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4913 guess_suffix
= BYTE_MNEM_SUFFIX
;
4916 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4918 guess_suffix
= WORD_MNEM_SUFFIX
;
4921 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4923 guess_suffix
= LONG_MNEM_SUFFIX
;
4926 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4928 guess_suffix
= QWORD_MNEM_SUFFIX
;
4932 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4933 guess_suffix
= WORD_MNEM_SUFFIX
;
4935 for (op
= i
.operands
; --op
>= 0;)
4936 if (operand_type_check (i
.types
[op
], imm
))
4938 switch (i
.op
[op
].imms
->X_op
)
4941 /* If a suffix is given, this operand may be shortened. */
4942 switch (guess_suffix
)
4944 case LONG_MNEM_SUFFIX
:
4945 i
.types
[op
].bitfield
.imm32
= 1;
4946 i
.types
[op
].bitfield
.imm64
= 1;
4948 case WORD_MNEM_SUFFIX
:
4949 i
.types
[op
].bitfield
.imm16
= 1;
4950 i
.types
[op
].bitfield
.imm32
= 1;
4951 i
.types
[op
].bitfield
.imm32s
= 1;
4952 i
.types
[op
].bitfield
.imm64
= 1;
4954 case BYTE_MNEM_SUFFIX
:
4955 i
.types
[op
].bitfield
.imm8
= 1;
4956 i
.types
[op
].bitfield
.imm8s
= 1;
4957 i
.types
[op
].bitfield
.imm16
= 1;
4958 i
.types
[op
].bitfield
.imm32
= 1;
4959 i
.types
[op
].bitfield
.imm32s
= 1;
4960 i
.types
[op
].bitfield
.imm64
= 1;
4964 /* If this operand is at most 16 bits, convert it
4965 to a signed 16 bit number before trying to see
4966 whether it will fit in an even smaller size.
4967 This allows a 16-bit operand such as $0xffe0 to
4968 be recognised as within Imm8S range. */
4969 if ((i
.types
[op
].bitfield
.imm16
)
4970 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4972 i
.op
[op
].imms
->X_add_number
=
4973 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4976 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4977 if ((i
.types
[op
].bitfield
.imm32
)
4978 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4981 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4982 ^ ((offsetT
) 1 << 31))
4983 - ((offsetT
) 1 << 31));
4987 = operand_type_or (i
.types
[op
],
4988 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4990 /* We must avoid matching of Imm32 templates when 64bit
4991 only immediate is available. */
4992 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4993 i
.types
[op
].bitfield
.imm32
= 0;
5000 /* Symbols and expressions. */
5002 /* Convert symbolic operand to proper sizes for matching, but don't
5003 prevent matching a set of insns that only supports sizes other
5004 than those matching the insn suffix. */
5006 i386_operand_type mask
, allowed
;
5007 const insn_template
*t
;
5009 operand_type_set (&mask
, 0);
5010 operand_type_set (&allowed
, 0);
5012 for (t
= current_templates
->start
;
5013 t
< current_templates
->end
;
5015 allowed
= operand_type_or (allowed
,
5016 t
->operand_types
[op
]);
5017 switch (guess_suffix
)
5019 case QWORD_MNEM_SUFFIX
:
5020 mask
.bitfield
.imm64
= 1;
5021 mask
.bitfield
.imm32s
= 1;
5023 case LONG_MNEM_SUFFIX
:
5024 mask
.bitfield
.imm32
= 1;
5026 case WORD_MNEM_SUFFIX
:
5027 mask
.bitfield
.imm16
= 1;
5029 case BYTE_MNEM_SUFFIX
:
5030 mask
.bitfield
.imm8
= 1;
5035 allowed
= operand_type_and (mask
, allowed
);
5036 if (!operand_type_all_zero (&allowed
))
5037 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5044 /* Try to use the smallest displacement type too. */
5046 optimize_disp (void)
5050 for (op
= i
.operands
; --op
>= 0;)
5051 if (operand_type_check (i
.types
[op
], disp
))
5053 if (i
.op
[op
].disps
->X_op
== O_constant
)
5055 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5057 if (i
.types
[op
].bitfield
.disp16
5058 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5060 /* If this operand is at most 16 bits, convert
5061 to a signed 16 bit number and don't use 64bit
5063 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5064 i
.types
[op
].bitfield
.disp64
= 0;
5067 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5068 if (i
.types
[op
].bitfield
.disp32
5069 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5071 /* If this operand is at most 32 bits, convert
5072 to a signed 32 bit number and don't use 64bit
5074 op_disp
&= (((offsetT
) 2 << 31) - 1);
5075 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5076 i
.types
[op
].bitfield
.disp64
= 0;
5079 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5081 i
.types
[op
].bitfield
.disp8
= 0;
5082 i
.types
[op
].bitfield
.disp16
= 0;
5083 i
.types
[op
].bitfield
.disp32
= 0;
5084 i
.types
[op
].bitfield
.disp32s
= 0;
5085 i
.types
[op
].bitfield
.disp64
= 0;
5089 else if (flag_code
== CODE_64BIT
)
5091 if (fits_in_signed_long (op_disp
))
5093 i
.types
[op
].bitfield
.disp64
= 0;
5094 i
.types
[op
].bitfield
.disp32s
= 1;
5096 if (i
.prefix
[ADDR_PREFIX
]
5097 && fits_in_unsigned_long (op_disp
))
5098 i
.types
[op
].bitfield
.disp32
= 1;
5100 if ((i
.types
[op
].bitfield
.disp32
5101 || i
.types
[op
].bitfield
.disp32s
5102 || i
.types
[op
].bitfield
.disp16
)
5103 && fits_in_disp8 (op_disp
))
5104 i
.types
[op
].bitfield
.disp8
= 1;
5106 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5107 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5109 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5110 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5111 i
.types
[op
].bitfield
.disp8
= 0;
5112 i
.types
[op
].bitfield
.disp16
= 0;
5113 i
.types
[op
].bitfield
.disp32
= 0;
5114 i
.types
[op
].bitfield
.disp32s
= 0;
5115 i
.types
[op
].bitfield
.disp64
= 0;
5118 /* We only support 64bit displacement on constants. */
5119 i
.types
[op
].bitfield
.disp64
= 0;
5123 /* Return 1 if there is a match in broadcast bytes between operand
5124 GIVEN and instruction template T. */
5127 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5129 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5130 && i
.types
[given
].bitfield
.byte
)
5131 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5132 && i
.types
[given
].bitfield
.word
)
5133 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5134 && i
.types
[given
].bitfield
.dword
)
5135 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5136 && i
.types
[given
].bitfield
.qword
));
5139 /* Check if operands are valid for the instruction. */
5142 check_VecOperands (const insn_template
*t
)
5146 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5148 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5149 any one operand are implicity requiring AVX512VL support if the actual
5150 operand size is YMMword or XMMword. Since this function runs after
5151 template matching, there's no need to check for YMMword/XMMword in
5153 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5154 if (!cpu_flags_all_zero (&cpu
)
5155 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5156 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5158 for (op
= 0; op
< t
->operands
; ++op
)
5160 if (t
->operand_types
[op
].bitfield
.zmmword
5161 && (i
.types
[op
].bitfield
.ymmword
5162 || i
.types
[op
].bitfield
.xmmword
))
5164 i
.error
= unsupported
;
5170 /* Without VSIB byte, we can't have a vector register for index. */
5171 if (!t
->opcode_modifier
.vecsib
5173 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5174 || i
.index_reg
->reg_type
.bitfield
.ymmword
5175 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5177 i
.error
= unsupported_vector_index_register
;
5181 /* Check if default mask is allowed. */
5182 if (t
->opcode_modifier
.nodefmask
5183 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5185 i
.error
= no_default_mask
;
5189 /* For VSIB byte, we need a vector register for index, and all vector
5190 registers must be distinct. */
5191 if (t
->opcode_modifier
.vecsib
)
5194 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5195 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5196 || (t
->opcode_modifier
.vecsib
== VecSIB256
5197 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5198 || (t
->opcode_modifier
.vecsib
== VecSIB512
5199 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5201 i
.error
= invalid_vsib_address
;
5205 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5206 if (i
.reg_operands
== 2 && !i
.mask
)
5208 gas_assert (i
.types
[0].bitfield
.regsimd
);
5209 gas_assert (i
.types
[0].bitfield
.xmmword
5210 || i
.types
[0].bitfield
.ymmword
);
5211 gas_assert (i
.types
[2].bitfield
.regsimd
);
5212 gas_assert (i
.types
[2].bitfield
.xmmword
5213 || i
.types
[2].bitfield
.ymmword
);
5214 if (operand_check
== check_none
)
5216 if (register_number (i
.op
[0].regs
)
5217 != register_number (i
.index_reg
)
5218 && register_number (i
.op
[2].regs
)
5219 != register_number (i
.index_reg
)
5220 && register_number (i
.op
[0].regs
)
5221 != register_number (i
.op
[2].regs
))
5223 if (operand_check
== check_error
)
5225 i
.error
= invalid_vector_register_set
;
5228 as_warn (_("mask, index, and destination registers should be distinct"));
5230 else if (i
.reg_operands
== 1 && i
.mask
)
5232 if (i
.types
[1].bitfield
.regsimd
5233 && (i
.types
[1].bitfield
.xmmword
5234 || i
.types
[1].bitfield
.ymmword
5235 || i
.types
[1].bitfield
.zmmword
)
5236 && (register_number (i
.op
[1].regs
)
5237 == register_number (i
.index_reg
)))
5239 if (operand_check
== check_error
)
5241 i
.error
= invalid_vector_register_set
;
5244 if (operand_check
!= check_none
)
5245 as_warn (_("index and destination registers should be distinct"));
5250 /* Check if broadcast is supported by the instruction and is applied
5251 to the memory operand. */
5254 i386_operand_type type
, overlap
;
5256 /* Check if specified broadcast is supported in this instruction,
5257 and its broadcast bytes match the memory operand. */
5258 op
= i
.broadcast
->operand
;
5259 if (!t
->opcode_modifier
.broadcast
5260 || !(i
.flags
[op
] & Operand_Mem
)
5261 || (!i
.types
[op
].bitfield
.unspecified
5262 && !match_broadcast_size (t
, op
)))
5265 i
.error
= unsupported_broadcast
;
5269 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5270 * i
.broadcast
->type
);
5271 operand_type_set (&type
, 0);
5272 switch (i
.broadcast
->bytes
)
5275 type
.bitfield
.word
= 1;
5278 type
.bitfield
.dword
= 1;
5281 type
.bitfield
.qword
= 1;
5284 type
.bitfield
.xmmword
= 1;
5287 type
.bitfield
.ymmword
= 1;
5290 type
.bitfield
.zmmword
= 1;
5296 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5297 if (operand_type_all_zero (&overlap
))
5300 if (t
->opcode_modifier
.checkregsize
)
5304 type
.bitfield
.baseindex
= 1;
5305 for (j
= 0; j
< i
.operands
; ++j
)
5308 && !operand_type_register_match(i
.types
[j
],
5309 t
->operand_types
[j
],
5311 t
->operand_types
[op
]))
5316 /* If broadcast is supported in this instruction, we need to check if
5317 operand of one-element size isn't specified without broadcast. */
5318 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5320 /* Find memory operand. */
5321 for (op
= 0; op
< i
.operands
; op
++)
5322 if (operand_type_check (i
.types
[op
], anymem
))
5324 gas_assert (op
< i
.operands
);
5325 /* Check size of the memory operand. */
5326 if (match_broadcast_size (t
, op
))
5328 i
.error
= broadcast_needed
;
5333 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5335 /* Check if requested masking is supported. */
5338 switch (t
->opcode_modifier
.masking
)
5342 case MERGING_MASKING
:
5343 if (i
.mask
->zeroing
)
5346 i
.error
= unsupported_masking
;
5350 case DYNAMIC_MASKING
:
5351 /* Memory destinations allow only merging masking. */
5352 if (i
.mask
->zeroing
&& i
.mem_operands
)
5354 /* Find memory operand. */
5355 for (op
= 0; op
< i
.operands
; op
++)
5356 if (i
.flags
[op
] & Operand_Mem
)
5358 gas_assert (op
< i
.operands
);
5359 if (op
== i
.operands
- 1)
5361 i
.error
= unsupported_masking
;
5371 /* Check if masking is applied to dest operand. */
5372 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5374 i
.error
= mask_not_on_destination
;
5381 if ((i
.rounding
->type
!= saeonly
5382 && !t
->opcode_modifier
.staticrounding
)
5383 || (i
.rounding
->type
== saeonly
5384 && (t
->opcode_modifier
.staticrounding
5385 || !t
->opcode_modifier
.sae
)))
5387 i
.error
= unsupported_rc_sae
;
5390 /* If the instruction has several immediate operands and one of
5391 them is rounding, the rounding operand should be the last
5392 immediate operand. */
5393 if (i
.imm_operands
> 1
5394 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5396 i
.error
= rc_sae_operand_not_last_imm
;
5401 /* Check vector Disp8 operand. */
5402 if (t
->opcode_modifier
.disp8memshift
5403 && i
.disp_encoding
!= disp_encoding_32bit
)
5406 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5407 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5408 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5411 const i386_operand_type
*type
= NULL
;
5414 for (op
= 0; op
< i
.operands
; op
++)
5415 if (operand_type_check (i
.types
[op
], anymem
))
5417 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5418 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5419 else if (t
->operand_types
[op
].bitfield
.xmmword
5420 + t
->operand_types
[op
].bitfield
.ymmword
5421 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5422 type
= &t
->operand_types
[op
];
5423 else if (!i
.types
[op
].bitfield
.unspecified
)
5424 type
= &i
.types
[op
];
5426 else if (i
.types
[op
].bitfield
.regsimd
5427 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5429 if (i
.types
[op
].bitfield
.zmmword
)
5431 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5433 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5439 if (type
->bitfield
.zmmword
)
5441 else if (type
->bitfield
.ymmword
)
5443 else if (type
->bitfield
.xmmword
)
5447 /* For the check in fits_in_disp8(). */
5448 if (i
.memshift
== 0)
5452 for (op
= 0; op
< i
.operands
; op
++)
5453 if (operand_type_check (i
.types
[op
], disp
)
5454 && i
.op
[op
].disps
->X_op
== O_constant
)
5456 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5458 i
.types
[op
].bitfield
.disp8
= 1;
5461 i
.types
[op
].bitfield
.disp8
= 0;
5470 /* Check if operands are valid for the instruction. Update VEX
5474 VEX_check_operands (const insn_template
*t
)
5476 if (i
.vec_encoding
== vex_encoding_evex
)
5478 /* This instruction must be encoded with EVEX prefix. */
5479 if (!is_evex_encoding (t
))
5481 i
.error
= unsupported
;
5487 if (!t
->opcode_modifier
.vex
)
5489 /* This instruction template doesn't have VEX prefix. */
5490 if (i
.vec_encoding
!= vex_encoding_default
)
5492 i
.error
= unsupported
;
5498 /* Only check VEX_Imm4, which must be the first operand. */
5499 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5501 if (i
.op
[0].imms
->X_op
!= O_constant
5502 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5508 /* Turn off Imm8 so that update_imm won't complain. */
5509 i
.types
[0] = vec_imm4
;
5515 static const insn_template
*
5516 match_template (char mnem_suffix
)
5518 /* Points to template once we've found it. */
5519 const insn_template
*t
;
5520 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5521 i386_operand_type overlap4
;
5522 unsigned int found_reverse_match
;
5523 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5524 i386_operand_type operand_types
[MAX_OPERANDS
];
5525 int addr_prefix_disp
;
5527 unsigned int found_cpu_match
, size_match
;
5528 unsigned int check_register
;
5529 enum i386_error specific_error
= 0;
5531 #if MAX_OPERANDS != 5
5532 # error "MAX_OPERANDS must be 5."
5535 found_reverse_match
= 0;
5536 addr_prefix_disp
= -1;
5538 memset (&suffix_check
, 0, sizeof (suffix_check
));
5539 if (intel_syntax
&& i
.broadcast
)
5541 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5542 suffix_check
.no_bsuf
= 1;
5543 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5544 suffix_check
.no_wsuf
= 1;
5545 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5546 suffix_check
.no_ssuf
= 1;
5547 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5548 suffix_check
.no_lsuf
= 1;
5549 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5550 suffix_check
.no_qsuf
= 1;
5551 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5552 suffix_check
.no_ldsuf
= 1;
5554 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5557 switch (mnem_suffix
)
5559 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5560 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5561 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5562 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5563 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5567 /* Must have right number of operands. */
5568 i
.error
= number_of_operands_mismatch
;
5570 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5572 addr_prefix_disp
= -1;
5573 found_reverse_match
= 0;
5575 if (i
.operands
!= t
->operands
)
5578 /* Check processor support. */
5579 i
.error
= unsupported
;
5580 found_cpu_match
= (cpu_flags_match (t
)
5581 == CPU_FLAGS_PERFECT_MATCH
);
5582 if (!found_cpu_match
)
5585 /* Check AT&T mnemonic. */
5586 i
.error
= unsupported_with_intel_mnemonic
;
5587 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5590 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5591 i
.error
= unsupported_syntax
;
5592 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5593 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5594 || (intel64
&& t
->opcode_modifier
.amd64
)
5595 || (!intel64
&& t
->opcode_modifier
.intel64
))
5598 /* Check the suffix, except for some instructions in intel mode. */
5599 i
.error
= invalid_instruction_suffix
;
5600 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5601 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5602 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5603 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5604 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5605 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5606 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5608 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5609 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5610 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5611 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5612 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5613 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5614 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5617 size_match
= operand_size_match (t
);
5621 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5622 operand_types
[j
] = t
->operand_types
[j
];
5624 /* In general, don't allow 64-bit operands in 32-bit mode. */
5625 if (i
.suffix
== QWORD_MNEM_SUFFIX
5626 && flag_code
!= CODE_64BIT
5628 ? (!t
->opcode_modifier
.ignoresize
5629 && !t
->opcode_modifier
.broadcast
5630 && !intel_float_operand (t
->name
))
5631 : intel_float_operand (t
->name
) != 2)
5632 && ((!operand_types
[0].bitfield
.regmmx
5633 && !operand_types
[0].bitfield
.regsimd
)
5634 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5635 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5636 && (t
->base_opcode
!= 0x0fc7
5637 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5640 /* In general, don't allow 32-bit operands on pre-386. */
5641 else if (i
.suffix
== LONG_MNEM_SUFFIX
5642 && !cpu_arch_flags
.bitfield
.cpui386
5644 ? (!t
->opcode_modifier
.ignoresize
5645 && !intel_float_operand (t
->name
))
5646 : intel_float_operand (t
->name
) != 2)
5647 && ((!operand_types
[0].bitfield
.regmmx
5648 && !operand_types
[0].bitfield
.regsimd
)
5649 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5650 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5653 /* Do not verify operands when there are none. */
5657 /* We've found a match; break out of loop. */
5661 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5662 into Disp32/Disp16/Disp32 operand. */
5663 if (i
.prefix
[ADDR_PREFIX
] != 0)
5665 /* There should be only one Disp operand. */
5669 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5671 if (operand_types
[j
].bitfield
.disp16
)
5673 addr_prefix_disp
= j
;
5674 operand_types
[j
].bitfield
.disp32
= 1;
5675 operand_types
[j
].bitfield
.disp16
= 0;
5681 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5683 if (operand_types
[j
].bitfield
.disp32
)
5685 addr_prefix_disp
= j
;
5686 operand_types
[j
].bitfield
.disp32
= 0;
5687 operand_types
[j
].bitfield
.disp16
= 1;
5693 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5695 if (operand_types
[j
].bitfield
.disp64
)
5697 addr_prefix_disp
= j
;
5698 operand_types
[j
].bitfield
.disp64
= 0;
5699 operand_types
[j
].bitfield
.disp32
= 1;
5707 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5708 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5711 /* We check register size if needed. */
5712 if (t
->opcode_modifier
.checkregsize
)
5714 check_register
= (1 << t
->operands
) - 1;
5716 check_register
&= ~(1 << i
.broadcast
->operand
);
5721 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5722 switch (t
->operands
)
5725 if (!operand_type_match (overlap0
, i
.types
[0]))
5729 /* xchg %eax, %eax is a special case. It is an alias for nop
5730 only in 32bit mode and we can use opcode 0x90. In 64bit
5731 mode, we can't use 0x90 for xchg %eax, %eax since it should
5732 zero-extend %eax to %rax. */
5733 if (flag_code
== CODE_64BIT
5734 && t
->base_opcode
== 0x90
5735 && operand_type_equal (&i
.types
[0], &acc32
)
5736 && operand_type_equal (&i
.types
[1], &acc32
))
5738 /* xrelease mov %eax, <disp> is another special case. It must not
5739 match the accumulator-only encoding of mov. */
5740 if (flag_code
!= CODE_64BIT
5742 && t
->base_opcode
== 0xa0
5743 && i
.types
[0].bitfield
.acc
5744 && operand_type_check (i
.types
[1], anymem
))
5749 if (!(size_match
& MATCH_STRAIGHT
))
5751 /* Reverse direction of operands if swapping is possible in the first
5752 place (operands need to be symmetric) and
5753 - the load form is requested, and the template is a store form,
5754 - the store form is requested, and the template is a load form,
5755 - the non-default (swapped) form is requested. */
5756 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5757 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5758 && !operand_type_all_zero (&overlap1
))
5759 switch (i
.dir_encoding
)
5761 case dir_encoding_load
:
5762 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5763 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5767 case dir_encoding_store
:
5768 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5769 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5773 case dir_encoding_swap
:
5776 case dir_encoding_default
:
5779 /* If we want store form, we skip the current load. */
5780 if ((i
.dir_encoding
== dir_encoding_store
5781 || i
.dir_encoding
== dir_encoding_swap
)
5782 && i
.mem_operands
== 0
5783 && t
->opcode_modifier
.load
)
5788 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5789 if (!operand_type_match (overlap0
, i
.types
[0])
5790 || !operand_type_match (overlap1
, i
.types
[1])
5791 || ((check_register
& 3) == 3
5792 && !operand_type_register_match (i
.types
[0],
5797 /* Check if other direction is valid ... */
5798 if (!t
->opcode_modifier
.d
)
5802 if (!(size_match
& MATCH_REVERSE
))
5804 /* Try reversing direction of operands. */
5805 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5806 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5807 if (!operand_type_match (overlap0
, i
.types
[0])
5808 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5810 && !operand_type_register_match (i
.types
[0],
5811 operand_types
[i
.operands
- 1],
5812 i
.types
[i
.operands
- 1],
5815 /* Does not match either direction. */
5818 /* found_reverse_match holds which of D or FloatR
5820 if (!t
->opcode_modifier
.d
)
5821 found_reverse_match
= 0;
5822 else if (operand_types
[0].bitfield
.tbyte
)
5823 found_reverse_match
= Opcode_FloatD
;
5824 else if (operand_types
[0].bitfield
.xmmword
5825 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5826 || operand_types
[0].bitfield
.regmmx
5827 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5828 || is_any_vex_encoding(t
))
5829 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5830 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5832 found_reverse_match
= Opcode_D
;
5833 if (t
->opcode_modifier
.floatr
)
5834 found_reverse_match
|= Opcode_FloatR
;
5838 /* Found a forward 2 operand match here. */
5839 switch (t
->operands
)
5842 overlap4
= operand_type_and (i
.types
[4],
5846 overlap3
= operand_type_and (i
.types
[3],
5850 overlap2
= operand_type_and (i
.types
[2],
5855 switch (t
->operands
)
5858 if (!operand_type_match (overlap4
, i
.types
[4])
5859 || !operand_type_register_match (i
.types
[3],
5866 if (!operand_type_match (overlap3
, i
.types
[3])
5867 || ((check_register
& 0xa) == 0xa
5868 && !operand_type_register_match (i
.types
[1],
5872 || ((check_register
& 0xc) == 0xc
5873 && !operand_type_register_match (i
.types
[2],
5880 /* Here we make use of the fact that there are no
5881 reverse match 3 operand instructions. */
5882 if (!operand_type_match (overlap2
, i
.types
[2])
5883 || ((check_register
& 5) == 5
5884 && !operand_type_register_match (i
.types
[0],
5888 || ((check_register
& 6) == 6
5889 && !operand_type_register_match (i
.types
[1],
5897 /* Found either forward/reverse 2, 3 or 4 operand match here:
5898 slip through to break. */
5900 if (!found_cpu_match
)
5903 /* Check if vector and VEX operands are valid. */
5904 if (check_VecOperands (t
) || VEX_check_operands (t
))
5906 specific_error
= i
.error
;
5910 /* We've found a match; break out of loop. */
5914 if (t
== current_templates
->end
)
5916 /* We found no match. */
5917 const char *err_msg
;
5918 switch (specific_error
? specific_error
: i
.error
)
5922 case operand_size_mismatch
:
5923 err_msg
= _("operand size mismatch");
5925 case operand_type_mismatch
:
5926 err_msg
= _("operand type mismatch");
5928 case register_type_mismatch
:
5929 err_msg
= _("register type mismatch");
5931 case number_of_operands_mismatch
:
5932 err_msg
= _("number of operands mismatch");
5934 case invalid_instruction_suffix
:
5935 err_msg
= _("invalid instruction suffix");
5938 err_msg
= _("constant doesn't fit in 4 bits");
5940 case unsupported_with_intel_mnemonic
:
5941 err_msg
= _("unsupported with Intel mnemonic");
5943 case unsupported_syntax
:
5944 err_msg
= _("unsupported syntax");
5947 as_bad (_("unsupported instruction `%s'"),
5948 current_templates
->start
->name
);
5950 case invalid_vsib_address
:
5951 err_msg
= _("invalid VSIB address");
5953 case invalid_vector_register_set
:
5954 err_msg
= _("mask, index, and destination registers must be distinct");
5956 case unsupported_vector_index_register
:
5957 err_msg
= _("unsupported vector index register");
5959 case unsupported_broadcast
:
5960 err_msg
= _("unsupported broadcast");
5962 case broadcast_needed
:
5963 err_msg
= _("broadcast is needed for operand of such type");
5965 case unsupported_masking
:
5966 err_msg
= _("unsupported masking");
5968 case mask_not_on_destination
:
5969 err_msg
= _("mask not on destination operand");
5971 case no_default_mask
:
5972 err_msg
= _("default mask isn't allowed");
5974 case unsupported_rc_sae
:
5975 err_msg
= _("unsupported static rounding/sae");
5977 case rc_sae_operand_not_last_imm
:
5979 err_msg
= _("RC/SAE operand must precede immediate operands");
5981 err_msg
= _("RC/SAE operand must follow immediate operands");
5983 case invalid_register_operand
:
5984 err_msg
= _("invalid register operand");
5987 as_bad (_("%s for `%s'"), err_msg
,
5988 current_templates
->start
->name
);
5992 if (!quiet_warnings
)
5995 && (i
.types
[0].bitfield
.jumpabsolute
5996 != operand_types
[0].bitfield
.jumpabsolute
))
5998 as_warn (_("indirect %s without `*'"), t
->name
);
6001 if (t
->opcode_modifier
.isprefix
6002 && t
->opcode_modifier
.ignoresize
)
6004 /* Warn them that a data or address size prefix doesn't
6005 affect assembly of the next line of code. */
6006 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6010 /* Copy the template we found. */
6013 if (addr_prefix_disp
!= -1)
6014 i
.tm
.operand_types
[addr_prefix_disp
]
6015 = operand_types
[addr_prefix_disp
];
6017 if (found_reverse_match
)
6019 /* If we found a reverse match we must alter the opcode
6020 direction bit. found_reverse_match holds bits to change
6021 (different for int & float insns). */
6023 i
.tm
.base_opcode
^= found_reverse_match
;
6025 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6026 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6035 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6036 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6038 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6040 as_bad (_("`%s' operand %d must use `%ses' segment"),
6046 /* There's only ever one segment override allowed per instruction.
6047 This instruction possibly has a legal segment override on the
6048 second operand, so copy the segment to where non-string
6049 instructions store it, allowing common code. */
6050 i
.seg
[0] = i
.seg
[1];
6052 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6054 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6056 as_bad (_("`%s' operand %d must use `%ses' segment"),
6067 process_suffix (void)
6069 /* If matched instruction specifies an explicit instruction mnemonic
6071 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6072 i
.suffix
= WORD_MNEM_SUFFIX
;
6073 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6074 i
.suffix
= LONG_MNEM_SUFFIX
;
6075 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6076 i
.suffix
= QWORD_MNEM_SUFFIX
;
6077 else if (i
.reg_operands
)
6079 /* If there's no instruction mnemonic suffix we try to invent one
6080 based on register operands. */
6083 /* We take i.suffix from the last register operand specified,
6084 Destination register type is more significant than source
6085 register type. crc32 in SSE4.2 prefers source register
6087 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6089 if (i
.types
[0].bitfield
.byte
)
6090 i
.suffix
= BYTE_MNEM_SUFFIX
;
6091 else if (i
.types
[0].bitfield
.word
)
6092 i
.suffix
= WORD_MNEM_SUFFIX
;
6093 else if (i
.types
[0].bitfield
.dword
)
6094 i
.suffix
= LONG_MNEM_SUFFIX
;
6095 else if (i
.types
[0].bitfield
.qword
)
6096 i
.suffix
= QWORD_MNEM_SUFFIX
;
6103 if (i
.tm
.base_opcode
== 0xf20f38f0)
6105 /* We have to know the operand size for crc32. */
6106 as_bad (_("ambiguous memory operand size for `%s`"),
6111 for (op
= i
.operands
; --op
>= 0;)
6112 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6113 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6115 if (!i
.types
[op
].bitfield
.reg
)
6117 if (i
.types
[op
].bitfield
.byte
)
6118 i
.suffix
= BYTE_MNEM_SUFFIX
;
6119 else if (i
.types
[op
].bitfield
.word
)
6120 i
.suffix
= WORD_MNEM_SUFFIX
;
6121 else if (i
.types
[op
].bitfield
.dword
)
6122 i
.suffix
= LONG_MNEM_SUFFIX
;
6123 else if (i
.types
[op
].bitfield
.qword
)
6124 i
.suffix
= QWORD_MNEM_SUFFIX
;
6131 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6134 && i
.tm
.opcode_modifier
.ignoresize
6135 && i
.tm
.opcode_modifier
.no_bsuf
)
6137 else if (!check_byte_reg ())
6140 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6143 && i
.tm
.opcode_modifier
.ignoresize
6144 && i
.tm
.opcode_modifier
.no_lsuf
6145 && !i
.tm
.opcode_modifier
.todword
6146 && !i
.tm
.opcode_modifier
.toqword
)
6148 else if (!check_long_reg ())
6151 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6154 && i
.tm
.opcode_modifier
.ignoresize
6155 && i
.tm
.opcode_modifier
.no_qsuf
6156 && !i
.tm
.opcode_modifier
.todword
6157 && !i
.tm
.opcode_modifier
.toqword
)
6159 else if (!check_qword_reg ())
6162 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6165 && i
.tm
.opcode_modifier
.ignoresize
6166 && i
.tm
.opcode_modifier
.no_wsuf
)
6168 else if (!check_word_reg ())
6171 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6172 /* Do nothing if the instruction is going to ignore the prefix. */
6177 else if (i
.tm
.opcode_modifier
.defaultsize
6179 /* exclude fldenv/frstor/fsave/fstenv */
6180 && i
.tm
.opcode_modifier
.no_ssuf
)
6182 i
.suffix
= stackop_size
;
6184 else if (intel_syntax
6186 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6187 || i
.tm
.opcode_modifier
.jumpbyte
6188 || i
.tm
.opcode_modifier
.jumpintersegment
6189 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6190 && i
.tm
.extension_opcode
<= 3)))
6195 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6197 i
.suffix
= QWORD_MNEM_SUFFIX
;
6202 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6203 i
.suffix
= LONG_MNEM_SUFFIX
;
6206 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6207 i
.suffix
= WORD_MNEM_SUFFIX
;
6216 if (i
.tm
.opcode_modifier
.w
)
6218 as_bad (_("no instruction mnemonic suffix given and "
6219 "no register operands; can't size instruction"));
6225 unsigned int suffixes
;
6227 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6228 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6230 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6232 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6234 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6236 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6239 /* There are more than suffix matches. */
6240 if (i
.tm
.opcode_modifier
.w
6241 || ((suffixes
& (suffixes
- 1))
6242 && !i
.tm
.opcode_modifier
.defaultsize
6243 && !i
.tm
.opcode_modifier
.ignoresize
))
6245 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6251 /* Change the opcode based on the operand size given by i.suffix. */
6254 /* Size floating point instruction. */
6255 case LONG_MNEM_SUFFIX
:
6256 if (i
.tm
.opcode_modifier
.floatmf
)
6258 i
.tm
.base_opcode
^= 4;
6262 case WORD_MNEM_SUFFIX
:
6263 case QWORD_MNEM_SUFFIX
:
6264 /* It's not a byte, select word/dword operation. */
6265 if (i
.tm
.opcode_modifier
.w
)
6267 if (i
.tm
.opcode_modifier
.shortform
)
6268 i
.tm
.base_opcode
|= 8;
6270 i
.tm
.base_opcode
|= 1;
6273 case SHORT_MNEM_SUFFIX
:
6274 /* Now select between word & dword operations via the operand
6275 size prefix, except for instructions that will ignore this
6277 if (i
.reg_operands
> 0
6278 && i
.types
[0].bitfield
.reg
6279 && i
.tm
.opcode_modifier
.addrprefixopreg
6280 && (i
.tm
.opcode_modifier
.immext
6281 || i
.operands
== 1))
6283 /* The address size override prefix changes the size of the
6285 if ((flag_code
== CODE_32BIT
6286 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6287 || (flag_code
!= CODE_32BIT
6288 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6289 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6292 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6293 && !i
.tm
.opcode_modifier
.ignoresize
6294 && !i
.tm
.opcode_modifier
.floatmf
6295 && !i
.tm
.opcode_modifier
.vex
6296 && !i
.tm
.opcode_modifier
.vexopcode
6297 && !is_evex_encoding (&i
.tm
)
6298 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6299 || (flag_code
== CODE_64BIT
6300 && i
.tm
.opcode_modifier
.jumpbyte
)))
6302 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6304 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6305 prefix
= ADDR_PREFIX_OPCODE
;
6307 if (!add_prefix (prefix
))
6311 /* Set mode64 for an operand. */
6312 if (i
.suffix
== QWORD_MNEM_SUFFIX
6313 && flag_code
== CODE_64BIT
6314 && !i
.tm
.opcode_modifier
.norex64
6315 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6317 && ! (i
.operands
== 2
6318 && i
.tm
.base_opcode
== 0x90
6319 && i
.tm
.extension_opcode
== None
6320 && operand_type_equal (&i
.types
[0], &acc64
)
6321 && operand_type_equal (&i
.types
[1], &acc64
)))
6327 if (i
.reg_operands
!= 0
6329 && i
.tm
.opcode_modifier
.addrprefixopreg
6330 && !i
.tm
.opcode_modifier
.immext
)
6332 /* Check invalid register operand when the address size override
6333 prefix changes the size of register operands. */
6335 enum { need_word
, need_dword
, need_qword
} need
;
6337 if (flag_code
== CODE_32BIT
)
6338 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6341 if (i
.prefix
[ADDR_PREFIX
])
6344 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6347 for (op
= 0; op
< i
.operands
; op
++)
6348 if (i
.types
[op
].bitfield
.reg
6349 && ((need
== need_word
6350 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6351 || (need
== need_dword
6352 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6353 || (need
== need_qword
6354 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6356 as_bad (_("invalid register operand size for `%s'"),
6366 check_byte_reg (void)
6370 for (op
= i
.operands
; --op
>= 0;)
6372 /* Skip non-register operands. */
6373 if (!i
.types
[op
].bitfield
.reg
)
6376 /* If this is an eight bit register, it's OK. If it's the 16 or
6377 32 bit version of an eight bit register, we will just use the
6378 low portion, and that's OK too. */
6379 if (i
.types
[op
].bitfield
.byte
)
6382 /* I/O port address operands are OK too. */
6383 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6386 /* crc32 doesn't generate this warning. */
6387 if (i
.tm
.base_opcode
== 0xf20f38f0)
6390 if ((i
.types
[op
].bitfield
.word
6391 || i
.types
[op
].bitfield
.dword
6392 || i
.types
[op
].bitfield
.qword
)
6393 && i
.op
[op
].regs
->reg_num
< 4
6394 /* Prohibit these changes in 64bit mode, since the lowering
6395 would be more complicated. */
6396 && flag_code
!= CODE_64BIT
)
6398 #if REGISTER_WARNINGS
6399 if (!quiet_warnings
)
6400 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6402 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6403 ? REGNAM_AL
- REGNAM_AX
6404 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6406 i
.op
[op
].regs
->reg_name
,
6411 /* Any other register is bad. */
6412 if (i
.types
[op
].bitfield
.reg
6413 || i
.types
[op
].bitfield
.regmmx
6414 || i
.types
[op
].bitfield
.regsimd
6415 || i
.types
[op
].bitfield
.sreg2
6416 || i
.types
[op
].bitfield
.sreg3
6417 || i
.types
[op
].bitfield
.control
6418 || i
.types
[op
].bitfield
.debug
6419 || i
.types
[op
].bitfield
.test
)
6421 as_bad (_("`%s%s' not allowed with `%s%c'"),
6423 i
.op
[op
].regs
->reg_name
,
6433 check_long_reg (void)
6437 for (op
= i
.operands
; --op
>= 0;)
6438 /* Skip non-register operands. */
6439 if (!i
.types
[op
].bitfield
.reg
)
6441 /* Reject eight bit registers, except where the template requires
6442 them. (eg. movzb) */
6443 else if (i
.types
[op
].bitfield
.byte
6444 && (i
.tm
.operand_types
[op
].bitfield
.reg
6445 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6446 && (i
.tm
.operand_types
[op
].bitfield
.word
6447 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6449 as_bad (_("`%s%s' not allowed with `%s%c'"),
6451 i
.op
[op
].regs
->reg_name
,
6456 /* Warn if the e prefix on a general reg is missing. */
6457 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6458 && i
.types
[op
].bitfield
.word
6459 && (i
.tm
.operand_types
[op
].bitfield
.reg
6460 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6461 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6463 /* Prohibit these changes in the 64bit mode, since the
6464 lowering is more complicated. */
6465 if (flag_code
== CODE_64BIT
)
6467 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6468 register_prefix
, i
.op
[op
].regs
->reg_name
,
6472 #if REGISTER_WARNINGS
6473 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6475 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6476 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6479 /* Warn if the r prefix on a general reg is present. */
6480 else if (i
.types
[op
].bitfield
.qword
6481 && (i
.tm
.operand_types
[op
].bitfield
.reg
6482 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6483 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6486 && i
.tm
.opcode_modifier
.toqword
6487 && !i
.types
[0].bitfield
.regsimd
)
6489 /* Convert to QWORD. We want REX byte. */
6490 i
.suffix
= QWORD_MNEM_SUFFIX
;
6494 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6495 register_prefix
, i
.op
[op
].regs
->reg_name
,
6504 check_qword_reg (void)
6508 for (op
= i
.operands
; --op
>= 0; )
6509 /* Skip non-register operands. */
6510 if (!i
.types
[op
].bitfield
.reg
)
6512 /* Reject eight bit registers, except where the template requires
6513 them. (eg. movzb) */
6514 else if (i
.types
[op
].bitfield
.byte
6515 && (i
.tm
.operand_types
[op
].bitfield
.reg
6516 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6517 && (i
.tm
.operand_types
[op
].bitfield
.word
6518 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6520 as_bad (_("`%s%s' not allowed with `%s%c'"),
6522 i
.op
[op
].regs
->reg_name
,
6527 /* Warn if the r prefix on a general reg is missing. */
6528 else if ((i
.types
[op
].bitfield
.word
6529 || i
.types
[op
].bitfield
.dword
)
6530 && (i
.tm
.operand_types
[op
].bitfield
.reg
6531 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6532 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6534 /* Prohibit these changes in the 64bit mode, since the
6535 lowering is more complicated. */
6537 && i
.tm
.opcode_modifier
.todword
6538 && !i
.types
[0].bitfield
.regsimd
)
6540 /* Convert to DWORD. We don't want REX byte. */
6541 i
.suffix
= LONG_MNEM_SUFFIX
;
6545 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6546 register_prefix
, i
.op
[op
].regs
->reg_name
,
6555 check_word_reg (void)
6558 for (op
= i
.operands
; --op
>= 0;)
6559 /* Skip non-register operands. */
6560 if (!i
.types
[op
].bitfield
.reg
)
6562 /* Reject eight bit registers, except where the template requires
6563 them. (eg. movzb) */
6564 else if (i
.types
[op
].bitfield
.byte
6565 && (i
.tm
.operand_types
[op
].bitfield
.reg
6566 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6567 && (i
.tm
.operand_types
[op
].bitfield
.word
6568 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6570 as_bad (_("`%s%s' not allowed with `%s%c'"),
6572 i
.op
[op
].regs
->reg_name
,
6577 /* Warn if the e or r prefix on a general reg is present. */
6578 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6579 && (i
.types
[op
].bitfield
.dword
6580 || i
.types
[op
].bitfield
.qword
)
6581 && (i
.tm
.operand_types
[op
].bitfield
.reg
6582 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6583 && i
.tm
.operand_types
[op
].bitfield
.word
)
6585 /* Prohibit these changes in the 64bit mode, since the
6586 lowering is more complicated. */
6587 if (flag_code
== CODE_64BIT
)
6589 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6590 register_prefix
, i
.op
[op
].regs
->reg_name
,
6594 #if REGISTER_WARNINGS
6595 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6597 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6598 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6605 update_imm (unsigned int j
)
6607 i386_operand_type overlap
= i
.types
[j
];
6608 if ((overlap
.bitfield
.imm8
6609 || overlap
.bitfield
.imm8s
6610 || overlap
.bitfield
.imm16
6611 || overlap
.bitfield
.imm32
6612 || overlap
.bitfield
.imm32s
6613 || overlap
.bitfield
.imm64
)
6614 && !operand_type_equal (&overlap
, &imm8
)
6615 && !operand_type_equal (&overlap
, &imm8s
)
6616 && !operand_type_equal (&overlap
, &imm16
)
6617 && !operand_type_equal (&overlap
, &imm32
)
6618 && !operand_type_equal (&overlap
, &imm32s
)
6619 && !operand_type_equal (&overlap
, &imm64
))
6623 i386_operand_type temp
;
6625 operand_type_set (&temp
, 0);
6626 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6628 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6629 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6631 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6632 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6633 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6635 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6636 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6639 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6642 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6643 || operand_type_equal (&overlap
, &imm16_32
)
6644 || operand_type_equal (&overlap
, &imm16_32s
))
6646 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6651 if (!operand_type_equal (&overlap
, &imm8
)
6652 && !operand_type_equal (&overlap
, &imm8s
)
6653 && !operand_type_equal (&overlap
, &imm16
)
6654 && !operand_type_equal (&overlap
, &imm32
)
6655 && !operand_type_equal (&overlap
, &imm32s
)
6656 && !operand_type_equal (&overlap
, &imm64
))
6658 as_bad (_("no instruction mnemonic suffix given; "
6659 "can't determine immediate size"));
6663 i
.types
[j
] = overlap
;
6673 /* Update the first 2 immediate operands. */
6674 n
= i
.operands
> 2 ? 2 : i
.operands
;
6677 for (j
= 0; j
< n
; j
++)
6678 if (update_imm (j
) == 0)
6681 /* The 3rd operand can't be immediate operand. */
6682 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6689 process_operands (void)
6691 /* Default segment register this instruction will use for memory
6692 accesses. 0 means unknown. This is only for optimizing out
6693 unnecessary segment overrides. */
6694 const seg_entry
*default_seg
= 0;
6696 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6698 unsigned int dupl
= i
.operands
;
6699 unsigned int dest
= dupl
- 1;
6702 /* The destination must be an xmm register. */
6703 gas_assert (i
.reg_operands
6704 && MAX_OPERANDS
> dupl
6705 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6707 if (i
.tm
.operand_types
[0].bitfield
.acc
6708 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6710 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6712 /* Keep xmm0 for instructions with VEX prefix and 3
6714 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6715 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6720 /* We remove the first xmm0 and keep the number of
6721 operands unchanged, which in fact duplicates the
6723 for (j
= 1; j
< i
.operands
; j
++)
6725 i
.op
[j
- 1] = i
.op
[j
];
6726 i
.types
[j
- 1] = i
.types
[j
];
6727 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6731 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6733 gas_assert ((MAX_OPERANDS
- 1) > dupl
6734 && (i
.tm
.opcode_modifier
.vexsources
6737 /* Add the implicit xmm0 for instructions with VEX prefix
6739 for (j
= i
.operands
; j
> 0; j
--)
6741 i
.op
[j
] = i
.op
[j
- 1];
6742 i
.types
[j
] = i
.types
[j
- 1];
6743 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6746 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6747 i
.types
[0] = regxmm
;
6748 i
.tm
.operand_types
[0] = regxmm
;
6751 i
.reg_operands
+= 2;
6756 i
.op
[dupl
] = i
.op
[dest
];
6757 i
.types
[dupl
] = i
.types
[dest
];
6758 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6767 i
.op
[dupl
] = i
.op
[dest
];
6768 i
.types
[dupl
] = i
.types
[dest
];
6769 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6772 if (i
.tm
.opcode_modifier
.immext
)
6775 else if (i
.tm
.operand_types
[0].bitfield
.acc
6776 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6780 for (j
= 1; j
< i
.operands
; j
++)
6782 i
.op
[j
- 1] = i
.op
[j
];
6783 i
.types
[j
- 1] = i
.types
[j
];
6785 /* We need to adjust fields in i.tm since they are used by
6786 build_modrm_byte. */
6787 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6794 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6796 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6798 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6799 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6800 regnum
= register_number (i
.op
[1].regs
);
6801 first_reg_in_group
= regnum
& ~3;
6802 last_reg_in_group
= first_reg_in_group
+ 3;
6803 if (regnum
!= first_reg_in_group
)
6804 as_warn (_("source register `%s%s' implicitly denotes"
6805 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6806 register_prefix
, i
.op
[1].regs
->reg_name
,
6807 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6808 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6811 else if (i
.tm
.opcode_modifier
.regkludge
)
6813 /* The imul $imm, %reg instruction is converted into
6814 imul $imm, %reg, %reg, and the clr %reg instruction
6815 is converted into xor %reg, %reg. */
6817 unsigned int first_reg_op
;
6819 if (operand_type_check (i
.types
[0], reg
))
6823 /* Pretend we saw the extra register operand. */
6824 gas_assert (i
.reg_operands
== 1
6825 && i
.op
[first_reg_op
+ 1].regs
== 0);
6826 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6827 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6832 if (i
.tm
.opcode_modifier
.shortform
)
6834 if (i
.types
[0].bitfield
.sreg2
6835 || i
.types
[0].bitfield
.sreg3
)
6837 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6838 && i
.op
[0].regs
->reg_num
== 1)
6840 as_bad (_("you can't `pop %scs'"), register_prefix
);
6843 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6844 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6849 /* The register or float register operand is in operand
6853 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6854 || operand_type_check (i
.types
[0], reg
))
6858 /* Register goes in low 3 bits of opcode. */
6859 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6860 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6862 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6864 /* Warn about some common errors, but press on regardless.
6865 The first case can be generated by gcc (<= 2.8.1). */
6866 if (i
.operands
== 2)
6868 /* Reversed arguments on faddp, fsubp, etc. */
6869 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6870 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6871 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6875 /* Extraneous `l' suffix on fp insn. */
6876 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6877 register_prefix
, i
.op
[0].regs
->reg_name
);
6882 else if (i
.tm
.opcode_modifier
.modrm
)
6884 /* The opcode is completed (modulo i.tm.extension_opcode which
6885 must be put into the modrm byte). Now, we make the modrm and
6886 index base bytes based on all the info we've collected. */
6888 default_seg
= build_modrm_byte ();
6890 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6894 else if (i
.tm
.opcode_modifier
.isstring
)
6896 /* For the string instructions that allow a segment override
6897 on one of their operands, the default segment is ds. */
6901 if (i
.tm
.base_opcode
== 0x8d /* lea */
6904 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6906 /* If a segment was explicitly specified, and the specified segment
6907 is not the default, use an opcode prefix to select it. If we
6908 never figured out what the default segment is, then default_seg
6909 will be zero at this point, and the specified segment prefix will
6911 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6913 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6919 static const seg_entry
*
6920 build_modrm_byte (void)
6922 const seg_entry
*default_seg
= 0;
6923 unsigned int source
, dest
;
6926 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6929 unsigned int nds
, reg_slot
;
6932 dest
= i
.operands
- 1;
6935 /* There are 2 kinds of instructions:
6936 1. 5 operands: 4 register operands or 3 register operands
6937 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6938 VexW0 or VexW1. The destination must be either XMM, YMM or
6940 2. 4 operands: 4 register operands or 3 register operands
6941 plus 1 memory operand, with VexXDS. */
6942 gas_assert ((i
.reg_operands
== 4
6943 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6944 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6945 && i
.tm
.opcode_modifier
.vexw
6946 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6948 /* If VexW1 is set, the first non-immediate operand is the source and
6949 the second non-immediate one is encoded in the immediate operand. */
6950 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6952 source
= i
.imm_operands
;
6953 reg_slot
= i
.imm_operands
+ 1;
6957 source
= i
.imm_operands
+ 1;
6958 reg_slot
= i
.imm_operands
;
6961 if (i
.imm_operands
== 0)
6963 /* When there is no immediate operand, generate an 8bit
6964 immediate operand to encode the first operand. */
6965 exp
= &im_expressions
[i
.imm_operands
++];
6966 i
.op
[i
.operands
].imms
= exp
;
6967 i
.types
[i
.operands
] = imm8
;
6970 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6971 exp
->X_op
= O_constant
;
6972 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6973 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6977 unsigned int imm_slot
;
6979 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6981 if (i
.tm
.opcode_modifier
.immext
)
6983 /* When ImmExt is set, the immediate byte is the last
6985 imm_slot
= i
.operands
- 1;
6993 /* Turn on Imm8 so that output_imm will generate it. */
6994 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6997 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6998 i
.op
[imm_slot
].imms
->X_add_number
6999 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7000 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7003 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7004 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7009 /* i.reg_operands MUST be the number of real register operands;
7010 implicit registers do not count. If there are 3 register
7011 operands, it must be a instruction with VexNDS. For a
7012 instruction with VexNDD, the destination register is encoded
7013 in VEX prefix. If there are 4 register operands, it must be
7014 a instruction with VEX prefix and 3 sources. */
7015 if (i
.mem_operands
== 0
7016 && ((i
.reg_operands
== 2
7017 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7018 || (i
.reg_operands
== 3
7019 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7020 || (i
.reg_operands
== 4 && vex_3_sources
)))
7028 /* When there are 3 operands, one of them may be immediate,
7029 which may be the first or the last operand. Otherwise,
7030 the first operand must be shift count register (cl) or it
7031 is an instruction with VexNDS. */
7032 gas_assert (i
.imm_operands
== 1
7033 || (i
.imm_operands
== 0
7034 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7035 || i
.types
[0].bitfield
.shiftcount
)));
7036 if (operand_type_check (i
.types
[0], imm
)
7037 || i
.types
[0].bitfield
.shiftcount
)
7043 /* When there are 4 operands, the first two must be 8bit
7044 immediate operands. The source operand will be the 3rd
7047 For instructions with VexNDS, if the first operand
7048 an imm8, the source operand is the 2nd one. If the last
7049 operand is imm8, the source operand is the first one. */
7050 gas_assert ((i
.imm_operands
== 2
7051 && i
.types
[0].bitfield
.imm8
7052 && i
.types
[1].bitfield
.imm8
)
7053 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7054 && i
.imm_operands
== 1
7055 && (i
.types
[0].bitfield
.imm8
7056 || i
.types
[i
.operands
- 1].bitfield
.imm8
7058 if (i
.imm_operands
== 2)
7062 if (i
.types
[0].bitfield
.imm8
)
7069 if (is_evex_encoding (&i
.tm
))
7071 /* For EVEX instructions, when there are 5 operands, the
7072 first one must be immediate operand. If the second one
7073 is immediate operand, the source operand is the 3th
7074 one. If the last one is immediate operand, the source
7075 operand is the 2nd one. */
7076 gas_assert (i
.imm_operands
== 2
7077 && i
.tm
.opcode_modifier
.sae
7078 && operand_type_check (i
.types
[0], imm
));
7079 if (operand_type_check (i
.types
[1], imm
))
7081 else if (operand_type_check (i
.types
[4], imm
))
7095 /* RC/SAE operand could be between DEST and SRC. That happens
7096 when one operand is GPR and the other one is XMM/YMM/ZMM
7098 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7101 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7103 /* For instructions with VexNDS, the register-only source
7104 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7105 register. It is encoded in VEX prefix. We need to
7106 clear RegMem bit before calling operand_type_equal. */
7108 i386_operand_type op
;
7111 /* Check register-only source operand when two source
7112 operands are swapped. */
7113 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7114 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7122 op
= i
.tm
.operand_types
[vvvv
];
7123 op
.bitfield
.regmem
= 0;
7124 if ((dest
+ 1) >= i
.operands
7125 || ((!op
.bitfield
.reg
7126 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7127 && !op
.bitfield
.regsimd
7128 && !operand_type_equal (&op
, ®mask
)))
7130 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7136 /* One of the register operands will be encoded in the i.tm.reg
7137 field, the other in the combined i.tm.mode and i.tm.regmem
7138 fields. If no form of this instruction supports a memory
7139 destination operand, then we assume the source operand may
7140 sometimes be a memory operand and so we need to store the
7141 destination in the i.rm.reg field. */
7142 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7143 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7145 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7146 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7147 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7148 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7149 i
.has_regmmx
= TRUE
;
7150 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7151 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7153 if (i
.types
[dest
].bitfield
.zmmword
7154 || i
.types
[source
].bitfield
.zmmword
)
7155 i
.has_regzmm
= TRUE
;
7156 else if (i
.types
[dest
].bitfield
.ymmword
7157 || i
.types
[source
].bitfield
.ymmword
)
7158 i
.has_regymm
= TRUE
;
7160 i
.has_regxmm
= TRUE
;
7162 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7164 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7166 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7168 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7173 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7174 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7175 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7177 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7179 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7181 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7184 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7186 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7189 add_prefix (LOCK_PREFIX_OPCODE
);
7193 { /* If it's not 2 reg operands... */
7198 unsigned int fake_zero_displacement
= 0;
7201 for (op
= 0; op
< i
.operands
; op
++)
7202 if (operand_type_check (i
.types
[op
], anymem
))
7204 gas_assert (op
< i
.operands
);
7206 if (i
.tm
.opcode_modifier
.vecsib
)
7208 if (i
.index_reg
->reg_num
== RegIZ
)
7211 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7214 i
.sib
.base
= NO_BASE_REGISTER
;
7215 i
.sib
.scale
= i
.log2_scale_factor
;
7216 i
.types
[op
].bitfield
.disp8
= 0;
7217 i
.types
[op
].bitfield
.disp16
= 0;
7218 i
.types
[op
].bitfield
.disp64
= 0;
7219 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7221 /* Must be 32 bit */
7222 i
.types
[op
].bitfield
.disp32
= 1;
7223 i
.types
[op
].bitfield
.disp32s
= 0;
7227 i
.types
[op
].bitfield
.disp32
= 0;
7228 i
.types
[op
].bitfield
.disp32s
= 1;
7231 i
.sib
.index
= i
.index_reg
->reg_num
;
7232 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7234 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7240 if (i
.base_reg
== 0)
7243 if (!i
.disp_operands
)
7244 fake_zero_displacement
= 1;
7245 if (i
.index_reg
== 0)
7247 i386_operand_type newdisp
;
7249 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7250 /* Operand is just <disp> */
7251 if (flag_code
== CODE_64BIT
)
7253 /* 64bit mode overwrites the 32bit absolute
7254 addressing by RIP relative addressing and
7255 absolute addressing is encoded by one of the
7256 redundant SIB forms. */
7257 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7258 i
.sib
.base
= NO_BASE_REGISTER
;
7259 i
.sib
.index
= NO_INDEX_REGISTER
;
7260 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7262 else if ((flag_code
== CODE_16BIT
)
7263 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7265 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7270 i
.rm
.regmem
= NO_BASE_REGISTER
;
7273 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7274 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7276 else if (!i
.tm
.opcode_modifier
.vecsib
)
7278 /* !i.base_reg && i.index_reg */
7279 if (i
.index_reg
->reg_num
== RegIZ
)
7280 i
.sib
.index
= NO_INDEX_REGISTER
;
7282 i
.sib
.index
= i
.index_reg
->reg_num
;
7283 i
.sib
.base
= NO_BASE_REGISTER
;
7284 i
.sib
.scale
= i
.log2_scale_factor
;
7285 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7286 i
.types
[op
].bitfield
.disp8
= 0;
7287 i
.types
[op
].bitfield
.disp16
= 0;
7288 i
.types
[op
].bitfield
.disp64
= 0;
7289 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7291 /* Must be 32 bit */
7292 i
.types
[op
].bitfield
.disp32
= 1;
7293 i
.types
[op
].bitfield
.disp32s
= 0;
7297 i
.types
[op
].bitfield
.disp32
= 0;
7298 i
.types
[op
].bitfield
.disp32s
= 1;
7300 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7304 /* RIP addressing for 64bit mode. */
7305 else if (i
.base_reg
->reg_num
== RegIP
)
7307 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7308 i
.rm
.regmem
= NO_BASE_REGISTER
;
7309 i
.types
[op
].bitfield
.disp8
= 0;
7310 i
.types
[op
].bitfield
.disp16
= 0;
7311 i
.types
[op
].bitfield
.disp32
= 0;
7312 i
.types
[op
].bitfield
.disp32s
= 1;
7313 i
.types
[op
].bitfield
.disp64
= 0;
7314 i
.flags
[op
] |= Operand_PCrel
;
7315 if (! i
.disp_operands
)
7316 fake_zero_displacement
= 1;
7318 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7320 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7321 switch (i
.base_reg
->reg_num
)
7324 if (i
.index_reg
== 0)
7326 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7327 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7331 if (i
.index_reg
== 0)
7334 if (operand_type_check (i
.types
[op
], disp
) == 0)
7336 /* fake (%bp) into 0(%bp) */
7337 i
.types
[op
].bitfield
.disp8
= 1;
7338 fake_zero_displacement
= 1;
7341 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7342 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7344 default: /* (%si) -> 4 or (%di) -> 5 */
7345 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7347 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7349 else /* i.base_reg and 32/64 bit mode */
7351 if (flag_code
== CODE_64BIT
7352 && operand_type_check (i
.types
[op
], disp
))
7354 i
.types
[op
].bitfield
.disp16
= 0;
7355 i
.types
[op
].bitfield
.disp64
= 0;
7356 if (i
.prefix
[ADDR_PREFIX
] == 0)
7358 i
.types
[op
].bitfield
.disp32
= 0;
7359 i
.types
[op
].bitfield
.disp32s
= 1;
7363 i
.types
[op
].bitfield
.disp32
= 1;
7364 i
.types
[op
].bitfield
.disp32s
= 0;
7368 if (!i
.tm
.opcode_modifier
.vecsib
)
7369 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7370 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7372 i
.sib
.base
= i
.base_reg
->reg_num
;
7373 /* x86-64 ignores REX prefix bit here to avoid decoder
7375 if (!(i
.base_reg
->reg_flags
& RegRex
)
7376 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7377 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7379 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7381 fake_zero_displacement
= 1;
7382 i
.types
[op
].bitfield
.disp8
= 1;
7384 i
.sib
.scale
= i
.log2_scale_factor
;
7385 if (i
.index_reg
== 0)
7387 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7388 /* <disp>(%esp) becomes two byte modrm with no index
7389 register. We've already stored the code for esp
7390 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7391 Any base register besides %esp will not use the
7392 extra modrm byte. */
7393 i
.sib
.index
= NO_INDEX_REGISTER
;
7395 else if (!i
.tm
.opcode_modifier
.vecsib
)
7397 if (i
.index_reg
->reg_num
== RegIZ
)
7398 i
.sib
.index
= NO_INDEX_REGISTER
;
7400 i
.sib
.index
= i
.index_reg
->reg_num
;
7401 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7402 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7407 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7408 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7412 if (!fake_zero_displacement
7416 fake_zero_displacement
= 1;
7417 if (i
.disp_encoding
== disp_encoding_8bit
)
7418 i
.types
[op
].bitfield
.disp8
= 1;
7420 i
.types
[op
].bitfield
.disp32
= 1;
7422 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7426 if (fake_zero_displacement
)
7428 /* Fakes a zero displacement assuming that i.types[op]
7429 holds the correct displacement size. */
7432 gas_assert (i
.op
[op
].disps
== 0);
7433 exp
= &disp_expressions
[i
.disp_operands
++];
7434 i
.op
[op
].disps
= exp
;
7435 exp
->X_op
= O_constant
;
7436 exp
->X_add_number
= 0;
7437 exp
->X_add_symbol
= (symbolS
*) 0;
7438 exp
->X_op_symbol
= (symbolS
*) 0;
7446 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7448 if (operand_type_check (i
.types
[0], imm
))
7449 i
.vex
.register_specifier
= NULL
;
7452 /* VEX.vvvv encodes one of the sources when the first
7453 operand is not an immediate. */
7454 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7455 i
.vex
.register_specifier
= i
.op
[0].regs
;
7457 i
.vex
.register_specifier
= i
.op
[1].regs
;
7460 /* Destination is a XMM register encoded in the ModRM.reg
7462 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7463 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7466 /* ModRM.rm and VEX.B encodes the other source. */
7467 if (!i
.mem_operands
)
7471 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7472 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7474 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7476 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7480 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7482 i
.vex
.register_specifier
= i
.op
[2].regs
;
7483 if (!i
.mem_operands
)
7486 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7487 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7491 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7492 (if any) based on i.tm.extension_opcode. Again, we must be
7493 careful to make sure that segment/control/debug/test/MMX
7494 registers are coded into the i.rm.reg field. */
7495 else if (i
.reg_operands
)
7498 unsigned int vex_reg
= ~0;
7500 for (op
= 0; op
< i
.operands
; op
++)
7502 if (i
.types
[op
].bitfield
.reg
7503 || i
.types
[op
].bitfield
.regbnd
7504 || i
.types
[op
].bitfield
.regmask
7505 || i
.types
[op
].bitfield
.sreg2
7506 || i
.types
[op
].bitfield
.sreg3
7507 || i
.types
[op
].bitfield
.control
7508 || i
.types
[op
].bitfield
.debug
7509 || i
.types
[op
].bitfield
.test
)
7511 if (i
.types
[op
].bitfield
.regsimd
)
7513 if (i
.types
[op
].bitfield
.zmmword
)
7514 i
.has_regzmm
= TRUE
;
7515 else if (i
.types
[op
].bitfield
.ymmword
)
7516 i
.has_regymm
= TRUE
;
7518 i
.has_regxmm
= TRUE
;
7521 if (i
.types
[op
].bitfield
.regmmx
)
7523 i
.has_regmmx
= TRUE
;
7530 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7532 /* For instructions with VexNDS, the register-only
7533 source operand is encoded in VEX prefix. */
7534 gas_assert (mem
!= (unsigned int) ~0);
7539 gas_assert (op
< i
.operands
);
7543 /* Check register-only source operand when two source
7544 operands are swapped. */
7545 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7546 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7550 gas_assert (mem
== (vex_reg
+ 1)
7551 && op
< i
.operands
);
7556 gas_assert (vex_reg
< i
.operands
);
7560 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7562 /* For instructions with VexNDD, the register destination
7563 is encoded in VEX prefix. */
7564 if (i
.mem_operands
== 0)
7566 /* There is no memory operand. */
7567 gas_assert ((op
+ 2) == i
.operands
);
7572 /* There are only 2 non-immediate operands. */
7573 gas_assert (op
< i
.imm_operands
+ 2
7574 && i
.operands
== i
.imm_operands
+ 2);
7575 vex_reg
= i
.imm_operands
+ 1;
7579 gas_assert (op
< i
.operands
);
7581 if (vex_reg
!= (unsigned int) ~0)
7583 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7585 if ((!type
->bitfield
.reg
7586 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7587 && !type
->bitfield
.regsimd
7588 && !operand_type_equal (type
, ®mask
))
7591 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7594 /* Don't set OP operand twice. */
7597 /* If there is an extension opcode to put here, the
7598 register number must be put into the regmem field. */
7599 if (i
.tm
.extension_opcode
!= None
)
7601 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7602 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7604 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7609 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7610 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7612 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7617 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7618 must set it to 3 to indicate this is a register operand
7619 in the regmem field. */
7620 if (!i
.mem_operands
)
7624 /* Fill in i.rm.reg field with extension opcode (if any). */
7625 if (i
.tm
.extension_opcode
!= None
)
7626 i
.rm
.reg
= i
.tm
.extension_opcode
;
7632 output_branch (void)
7638 relax_substateT subtype
;
7642 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7643 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7646 if (i
.prefix
[DATA_PREFIX
] != 0)
7652 /* Pentium4 branch hints. */
7653 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7654 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7659 if (i
.prefix
[REX_PREFIX
] != 0)
7665 /* BND prefixed jump. */
7666 if (i
.prefix
[BND_PREFIX
] != 0)
7668 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7672 if (i
.prefixes
!= 0 && !intel_syntax
)
7673 as_warn (_("skipping prefixes on this instruction"));
7675 /* It's always a symbol; End frag & setup for relax.
7676 Make sure there is enough room in this frag for the largest
7677 instruction we may generate in md_convert_frag. This is 2
7678 bytes for the opcode and room for the prefix and largest
7680 frag_grow (prefix
+ 2 + 4);
7681 /* Prefix and 1 opcode byte go in fr_fix. */
7682 p
= frag_more (prefix
+ 1);
7683 if (i
.prefix
[DATA_PREFIX
] != 0)
7684 *p
++ = DATA_PREFIX_OPCODE
;
7685 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7686 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7687 *p
++ = i
.prefix
[SEG_PREFIX
];
7688 if (i
.prefix
[REX_PREFIX
] != 0)
7689 *p
++ = i
.prefix
[REX_PREFIX
];
7690 *p
= i
.tm
.base_opcode
;
7692 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7693 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7694 else if (cpu_arch_flags
.bitfield
.cpui386
)
7695 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7697 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7700 sym
= i
.op
[0].disps
->X_add_symbol
;
7701 off
= i
.op
[0].disps
->X_add_number
;
7703 if (i
.op
[0].disps
->X_op
!= O_constant
7704 && i
.op
[0].disps
->X_op
!= O_symbol
)
7706 /* Handle complex expressions. */
7707 sym
= make_expr_symbol (i
.op
[0].disps
);
7711 /* 1 possible extra opcode + 4 byte displacement go in var part.
7712 Pass reloc in fr_var. */
7713 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7717 /* Return TRUE iff PLT32 relocation should be used for branching to
7721 need_plt32_p (symbolS
*s
)
7723 /* PLT32 relocation is ELF only. */
7727 /* Since there is no need to prepare for PLT branch on x86-64, we
7728 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7729 be used as a marker for 32-bit PC-relative branches. */
7733 /* Weak or undefined symbol need PLT32 relocation. */
7734 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7737 /* Non-global symbol doesn't need PLT32 relocation. */
7738 if (! S_IS_EXTERNAL (s
))
7741 /* Other global symbols need PLT32 relocation. NB: Symbol with
7742 non-default visibilities are treated as normal global symbol
7743 so that PLT32 relocation can be used as a marker for 32-bit
7744 PC-relative branches. It is useful for linker relaxation. */
7755 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7757 if (i
.tm
.opcode_modifier
.jumpbyte
)
7759 /* This is a loop or jecxz type instruction. */
7761 if (i
.prefix
[ADDR_PREFIX
] != 0)
7763 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7766 /* Pentium4 branch hints. */
7767 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7768 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7770 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7779 if (flag_code
== CODE_16BIT
)
7782 if (i
.prefix
[DATA_PREFIX
] != 0)
7784 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7794 if (i
.prefix
[REX_PREFIX
] != 0)
7796 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7800 /* BND prefixed jump. */
7801 if (i
.prefix
[BND_PREFIX
] != 0)
7803 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7807 if (i
.prefixes
!= 0 && !intel_syntax
)
7808 as_warn (_("skipping prefixes on this instruction"));
7810 p
= frag_more (i
.tm
.opcode_length
+ size
);
7811 switch (i
.tm
.opcode_length
)
7814 *p
++ = i
.tm
.base_opcode
>> 8;
7817 *p
++ = i
.tm
.base_opcode
;
7823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7825 && jump_reloc
== NO_RELOC
7826 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7827 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7830 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7832 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7833 i
.op
[0].disps
, 1, jump_reloc
);
7835 /* All jumps handled here are signed, but don't use a signed limit
7836 check for 32 and 16 bit jumps as we want to allow wrap around at
7837 4G and 64k respectively. */
7839 fixP
->fx_signed
= 1;
7843 output_interseg_jump (void)
7851 if (flag_code
== CODE_16BIT
)
7855 if (i
.prefix
[DATA_PREFIX
] != 0)
7861 if (i
.prefix
[REX_PREFIX
] != 0)
7871 if (i
.prefixes
!= 0 && !intel_syntax
)
7872 as_warn (_("skipping prefixes on this instruction"));
7874 /* 1 opcode; 2 segment; offset */
7875 p
= frag_more (prefix
+ 1 + 2 + size
);
7877 if (i
.prefix
[DATA_PREFIX
] != 0)
7878 *p
++ = DATA_PREFIX_OPCODE
;
7880 if (i
.prefix
[REX_PREFIX
] != 0)
7881 *p
++ = i
.prefix
[REX_PREFIX
];
7883 *p
++ = i
.tm
.base_opcode
;
7884 if (i
.op
[1].imms
->X_op
== O_constant
)
7886 offsetT n
= i
.op
[1].imms
->X_add_number
;
7889 && !fits_in_unsigned_word (n
)
7890 && !fits_in_signed_word (n
))
7892 as_bad (_("16-bit jump out of range"));
7895 md_number_to_chars (p
, n
, size
);
7898 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7899 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7900 if (i
.op
[0].imms
->X_op
!= O_constant
)
7901 as_bad (_("can't handle non absolute segment in `%s'"),
7903 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7911 asection
*seg
= now_seg
;
7912 subsegT subseg
= now_subseg
;
7914 unsigned int alignment
, align_size_1
;
7915 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7916 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7917 unsigned int padding
;
7919 if (!IS_ELF
|| !x86_used_note
)
7922 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7924 /* The .note.gnu.property section layout:
7926 Field Length Contents
7929 n_descsz 4 The note descriptor size
7930 n_type 4 NT_GNU_PROPERTY_TYPE_0
7932 n_desc n_descsz The program property array
7936 /* Create the .note.gnu.property section. */
7937 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7938 bfd_set_section_flags (stdoutput
, sec
,
7945 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7956 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7957 elf_section_type (sec
) = SHT_NOTE
;
7959 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7961 isa_1_descsz_raw
= 4 + 4 + 4;
7962 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7963 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7965 feature_2_descsz_raw
= isa_1_descsz
;
7966 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7968 feature_2_descsz_raw
+= 4 + 4 + 4;
7969 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7970 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7973 descsz
= feature_2_descsz
;
7974 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7975 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7977 /* Write n_namsz. */
7978 md_number_to_chars (p
, (valueT
) 4, 4);
7980 /* Write n_descsz. */
7981 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7984 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7987 memcpy (p
+ 4 * 3, "GNU", 4);
7989 /* Write 4-byte type. */
7990 md_number_to_chars (p
+ 4 * 4,
7991 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7993 /* Write 4-byte data size. */
7994 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7996 /* Write 4-byte data. */
7997 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7999 /* Zero out paddings. */
8000 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8002 memset (p
+ 4 * 7, 0, padding
);
8004 /* Write 4-byte type. */
8005 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8006 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8008 /* Write 4-byte data size. */
8009 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8011 /* Write 4-byte data. */
8012 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8013 (valueT
) x86_feature_2_used
, 4);
8015 /* Zero out paddings. */
8016 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8018 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8020 /* We probably can't restore the current segment, for there likely
8023 subseg_set (seg
, subseg
);
8030 fragS
*insn_start_frag
;
8031 offsetT insn_start_off
;
8033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8034 if (IS_ELF
&& x86_used_note
)
8036 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8038 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8040 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8042 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8044 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8046 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8048 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8054 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8055 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8056 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8057 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8058 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8059 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8060 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8061 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8062 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8063 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8064 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8065 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8066 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8067 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8068 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8069 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8070 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8071 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8072 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8073 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8074 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8075 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8076 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8077 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8078 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8079 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8080 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8081 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8082 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8083 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8085 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8086 || i
.tm
.cpu_flags
.bitfield
.cpu287
8087 || i
.tm
.cpu_flags
.bitfield
.cpu387
8088 || i
.tm
.cpu_flags
.bitfield
.cpu687
8089 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8090 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8091 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8092 Xfence instructions. */
8093 if (i
.tm
.base_opcode
!= 0xf18
8094 && i
.tm
.base_opcode
!= 0xf0d
8095 && i
.tm
.base_opcode
!= 0xfae
8097 || i
.tm
.cpu_flags
.bitfield
.cpummx
8098 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8099 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8100 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8102 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8104 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8106 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8107 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8108 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8109 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8110 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8111 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8112 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8113 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8114 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8118 /* Tie dwarf2 debug info to the address at the start of the insn.
8119 We can't do this after the insn has been output as the current
8120 frag may have been closed off. eg. by frag_var. */
8121 dwarf2_emit_insn (0);
8123 insn_start_frag
= frag_now
;
8124 insn_start_off
= frag_now_fix ();
8127 if (i
.tm
.opcode_modifier
.jump
)
8129 else if (i
.tm
.opcode_modifier
.jumpbyte
8130 || i
.tm
.opcode_modifier
.jumpdword
)
8132 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8133 output_interseg_jump ();
8136 /* Output normal instructions here. */
8140 unsigned int prefix
;
8143 && i
.tm
.base_opcode
== 0xfae
8145 && i
.imm_operands
== 1
8146 && (i
.op
[0].imms
->X_add_number
== 0xe8
8147 || i
.op
[0].imms
->X_add_number
== 0xf0
8148 || i
.op
[0].imms
->X_add_number
== 0xf8))
8150 /* Encode lfence, mfence, and sfence as
8151 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8152 offsetT val
= 0x240483f0ULL
;
8154 md_number_to_chars (p
, val
, 5);
8158 /* Some processors fail on LOCK prefix. This options makes
8159 assembler ignore LOCK prefix and serves as a workaround. */
8160 if (omit_lock_prefix
)
8162 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8164 i
.prefix
[LOCK_PREFIX
] = 0;
8167 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8168 don't need the explicit prefix. */
8169 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8171 switch (i
.tm
.opcode_length
)
8174 if (i
.tm
.base_opcode
& 0xff000000)
8176 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8177 add_prefix (prefix
);
8181 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8183 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8184 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8185 || prefix
!= REPE_PREFIX_OPCODE
8186 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8187 add_prefix (prefix
);
8193 /* Check for pseudo prefixes. */
8194 as_bad_where (insn_start_frag
->fr_file
,
8195 insn_start_frag
->fr_line
,
8196 _("pseudo prefix without instruction"));
8202 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8203 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8204 R_X86_64_GOTTPOFF relocation so that linker can safely
8205 perform IE->LE optimization. */
8206 if (x86_elf_abi
== X86_64_X32_ABI
8208 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8209 && i
.prefix
[REX_PREFIX
] == 0)
8210 add_prefix (REX_OPCODE
);
8213 /* The prefix bytes. */
8214 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8216 FRAG_APPEND_1_CHAR (*q
);
8220 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8225 /* REX byte is encoded in VEX prefix. */
8229 FRAG_APPEND_1_CHAR (*q
);
8232 /* There should be no other prefixes for instructions
8237 /* For EVEX instructions i.vrex should become 0 after
8238 build_evex_prefix. For VEX instructions upper 16 registers
8239 aren't available, so VREX should be 0. */
8242 /* Now the VEX prefix. */
8243 p
= frag_more (i
.vex
.length
);
8244 for (j
= 0; j
< i
.vex
.length
; j
++)
8245 p
[j
] = i
.vex
.bytes
[j
];
8248 /* Now the opcode; be careful about word order here! */
8249 if (i
.tm
.opcode_length
== 1)
8251 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8255 switch (i
.tm
.opcode_length
)
8259 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8260 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8264 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8274 /* Put out high byte first: can't use md_number_to_chars! */
8275 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8276 *p
= i
.tm
.base_opcode
& 0xff;
8279 /* Now the modrm byte and sib byte (if present). */
8280 if (i
.tm
.opcode_modifier
.modrm
)
8282 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8285 /* If i.rm.regmem == ESP (4)
8286 && i.rm.mode != (Register mode)
8288 ==> need second modrm byte. */
8289 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8291 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8292 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8294 | i
.sib
.scale
<< 6));
8297 if (i
.disp_operands
)
8298 output_disp (insn_start_frag
, insn_start_off
);
8301 output_imm (insn_start_frag
, insn_start_off
);
8307 pi ("" /*line*/, &i
);
8309 #endif /* DEBUG386 */
8312 /* Return the size of the displacement operand N. */
8315 disp_size (unsigned int n
)
8319 if (i
.types
[n
].bitfield
.disp64
)
8321 else if (i
.types
[n
].bitfield
.disp8
)
8323 else if (i
.types
[n
].bitfield
.disp16
)
8328 /* Return the size of the immediate operand N. */
8331 imm_size (unsigned int n
)
8334 if (i
.types
[n
].bitfield
.imm64
)
8336 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8338 else if (i
.types
[n
].bitfield
.imm16
)
8344 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8349 for (n
= 0; n
< i
.operands
; n
++)
8351 if (operand_type_check (i
.types
[n
], disp
))
8353 if (i
.op
[n
].disps
->X_op
== O_constant
)
8355 int size
= disp_size (n
);
8356 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8358 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8360 p
= frag_more (size
);
8361 md_number_to_chars (p
, val
, size
);
8365 enum bfd_reloc_code_real reloc_type
;
8366 int size
= disp_size (n
);
8367 int sign
= i
.types
[n
].bitfield
.disp32s
;
8368 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8371 /* We can't have 8 bit displacement here. */
8372 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8374 /* The PC relative address is computed relative
8375 to the instruction boundary, so in case immediate
8376 fields follows, we need to adjust the value. */
8377 if (pcrel
&& i
.imm_operands
)
8382 for (n1
= 0; n1
< i
.operands
; n1
++)
8383 if (operand_type_check (i
.types
[n1
], imm
))
8385 /* Only one immediate is allowed for PC
8386 relative address. */
8387 gas_assert (sz
== 0);
8389 i
.op
[n
].disps
->X_add_number
-= sz
;
8391 /* We should find the immediate. */
8392 gas_assert (sz
!= 0);
8395 p
= frag_more (size
);
8396 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8398 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8399 && (((reloc_type
== BFD_RELOC_32
8400 || reloc_type
== BFD_RELOC_X86_64_32S
8401 || (reloc_type
== BFD_RELOC_64
8403 && (i
.op
[n
].disps
->X_op
== O_symbol
8404 || (i
.op
[n
].disps
->X_op
== O_add
8405 && ((symbol_get_value_expression
8406 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8408 || reloc_type
== BFD_RELOC_32_PCREL
))
8412 if (insn_start_frag
== frag_now
)
8413 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8418 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8419 for (fr
= insn_start_frag
->fr_next
;
8420 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8422 add
+= p
- frag_now
->fr_literal
;
8427 reloc_type
= BFD_RELOC_386_GOTPC
;
8428 i
.op
[n
].imms
->X_add_number
+= add
;
8430 else if (reloc_type
== BFD_RELOC_64
)
8431 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8433 /* Don't do the adjustment for x86-64, as there
8434 the pcrel addressing is relative to the _next_
8435 insn, and that is taken care of in other code. */
8436 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8438 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8439 size
, i
.op
[n
].disps
, pcrel
,
8441 /* Check for "call/jmp *mem", "mov mem, %reg",
8442 "test %reg, mem" and "binop mem, %reg" where binop
8443 is one of adc, add, and, cmp, or, sbb, sub, xor
8444 instructions without data prefix. Always generate
8445 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8446 if (i
.prefix
[DATA_PREFIX
] == 0
8447 && (generate_relax_relocations
8450 && i
.rm
.regmem
== 5))
8452 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8453 && ((i
.operands
== 1
8454 && i
.tm
.base_opcode
== 0xff
8455 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8457 && (i
.tm
.base_opcode
== 0x8b
8458 || i
.tm
.base_opcode
== 0x85
8459 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8463 fixP
->fx_tcbit
= i
.rex
!= 0;
8465 && (i
.base_reg
->reg_num
== RegIP
))
8466 fixP
->fx_tcbit2
= 1;
8469 fixP
->fx_tcbit2
= 1;
8477 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8482 for (n
= 0; n
< i
.operands
; n
++)
8484 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8485 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8488 if (operand_type_check (i
.types
[n
], imm
))
8490 if (i
.op
[n
].imms
->X_op
== O_constant
)
8492 int size
= imm_size (n
);
8495 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8497 p
= frag_more (size
);
8498 md_number_to_chars (p
, val
, size
);
8502 /* Not absolute_section.
8503 Need a 32-bit fixup (don't support 8bit
8504 non-absolute imms). Try to support other
8506 enum bfd_reloc_code_real reloc_type
;
8507 int size
= imm_size (n
);
8510 if (i
.types
[n
].bitfield
.imm32s
8511 && (i
.suffix
== QWORD_MNEM_SUFFIX
8512 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8517 p
= frag_more (size
);
8518 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8520 /* This is tough to explain. We end up with this one if we
8521 * have operands that look like
8522 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8523 * obtain the absolute address of the GOT, and it is strongly
8524 * preferable from a performance point of view to avoid using
8525 * a runtime relocation for this. The actual sequence of
8526 * instructions often look something like:
8531 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8533 * The call and pop essentially return the absolute address
8534 * of the label .L66 and store it in %ebx. The linker itself
8535 * will ultimately change the first operand of the addl so
8536 * that %ebx points to the GOT, but to keep things simple, the
8537 * .o file must have this operand set so that it generates not
8538 * the absolute address of .L66, but the absolute address of
8539 * itself. This allows the linker itself simply treat a GOTPC
8540 * relocation as asking for a pcrel offset to the GOT to be
8541 * added in, and the addend of the relocation is stored in the
8542 * operand field for the instruction itself.
8544 * Our job here is to fix the operand so that it would add
8545 * the correct offset so that %ebx would point to itself. The
8546 * thing that is tricky is that .-.L66 will point to the
8547 * beginning of the instruction, so we need to further modify
8548 * the operand so that it will point to itself. There are
8549 * other cases where you have something like:
8551 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8553 * and here no correction would be required. Internally in
8554 * the assembler we treat operands of this form as not being
8555 * pcrel since the '.' is explicitly mentioned, and I wonder
8556 * whether it would simplify matters to do it this way. Who
8557 * knows. In earlier versions of the PIC patches, the
8558 * pcrel_adjust field was used to store the correction, but
8559 * since the expression is not pcrel, I felt it would be
8560 * confusing to do it this way. */
8562 if ((reloc_type
== BFD_RELOC_32
8563 || reloc_type
== BFD_RELOC_X86_64_32S
8564 || reloc_type
== BFD_RELOC_64
)
8566 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8567 && (i
.op
[n
].imms
->X_op
== O_symbol
8568 || (i
.op
[n
].imms
->X_op
== O_add
8569 && ((symbol_get_value_expression
8570 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8575 if (insn_start_frag
== frag_now
)
8576 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8581 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8582 for (fr
= insn_start_frag
->fr_next
;
8583 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8585 add
+= p
- frag_now
->fr_literal
;
8589 reloc_type
= BFD_RELOC_386_GOTPC
;
8591 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8593 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8594 i
.op
[n
].imms
->X_add_number
+= add
;
8596 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8597 i
.op
[n
].imms
, 0, reloc_type
);
8603 /* x86_cons_fix_new is called via the expression parsing code when a
8604 reloc is needed. We use this hook to get the correct .got reloc. */
8605 static int cons_sign
= -1;
8608 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8609 expressionS
*exp
, bfd_reloc_code_real_type r
)
8611 r
= reloc (len
, 0, cons_sign
, r
);
8614 if (exp
->X_op
== O_secrel
)
8616 exp
->X_op
= O_symbol
;
8617 r
= BFD_RELOC_32_SECREL
;
8621 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8624 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8625 purpose of the `.dc.a' internal pseudo-op. */
8628 x86_address_bytes (void)
8630 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8632 return stdoutput
->arch_info
->bits_per_address
/ 8;
8635 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8637 # define lex_got(reloc, adjust, types) NULL
8639 /* Parse operands of the form
8640 <symbol>@GOTOFF+<nnn>
8641 and similar .plt or .got references.
8643 If we find one, set up the correct relocation in RELOC and copy the
8644 input string, minus the `@GOTOFF' into a malloc'd buffer for
8645 parsing by the calling routine. Return this buffer, and if ADJUST
8646 is non-null set it to the length of the string we removed from the
8647 input line. Otherwise return NULL. */
8649 lex_got (enum bfd_reloc_code_real
*rel
,
8651 i386_operand_type
*types
)
8653 /* Some of the relocations depend on the size of what field is to
8654 be relocated. But in our callers i386_immediate and i386_displacement
8655 we don't yet know the operand size (this will be set by insn
8656 matching). Hence we record the word32 relocation here,
8657 and adjust the reloc according to the real size in reloc(). */
8658 static const struct {
8661 const enum bfd_reloc_code_real rel
[2];
8662 const i386_operand_type types64
;
8664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8665 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8667 OPERAND_TYPE_IMM32_64
},
8669 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8670 BFD_RELOC_X86_64_PLTOFF64
},
8671 OPERAND_TYPE_IMM64
},
8672 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8673 BFD_RELOC_X86_64_PLT32
},
8674 OPERAND_TYPE_IMM32_32S_DISP32
},
8675 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8676 BFD_RELOC_X86_64_GOTPLT64
},
8677 OPERAND_TYPE_IMM64_DISP64
},
8678 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8679 BFD_RELOC_X86_64_GOTOFF64
},
8680 OPERAND_TYPE_IMM64_DISP64
},
8681 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8682 BFD_RELOC_X86_64_GOTPCREL
},
8683 OPERAND_TYPE_IMM32_32S_DISP32
},
8684 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8685 BFD_RELOC_X86_64_TLSGD
},
8686 OPERAND_TYPE_IMM32_32S_DISP32
},
8687 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8688 _dummy_first_bfd_reloc_code_real
},
8689 OPERAND_TYPE_NONE
},
8690 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8691 BFD_RELOC_X86_64_TLSLD
},
8692 OPERAND_TYPE_IMM32_32S_DISP32
},
8693 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8694 BFD_RELOC_X86_64_GOTTPOFF
},
8695 OPERAND_TYPE_IMM32_32S_DISP32
},
8696 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8697 BFD_RELOC_X86_64_TPOFF32
},
8698 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8699 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8700 _dummy_first_bfd_reloc_code_real
},
8701 OPERAND_TYPE_NONE
},
8702 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8703 BFD_RELOC_X86_64_DTPOFF32
},
8704 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8705 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8706 _dummy_first_bfd_reloc_code_real
},
8707 OPERAND_TYPE_NONE
},
8708 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8709 _dummy_first_bfd_reloc_code_real
},
8710 OPERAND_TYPE_NONE
},
8711 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8712 BFD_RELOC_X86_64_GOT32
},
8713 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8714 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8715 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8716 OPERAND_TYPE_IMM32_32S_DISP32
},
8717 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8718 BFD_RELOC_X86_64_TLSDESC_CALL
},
8719 OPERAND_TYPE_IMM32_32S_DISP32
},
8724 #if defined (OBJ_MAYBE_ELF)
8729 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8730 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8733 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8735 int len
= gotrel
[j
].len
;
8736 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8738 if (gotrel
[j
].rel
[object_64bit
] != 0)
8741 char *tmpbuf
, *past_reloc
;
8743 *rel
= gotrel
[j
].rel
[object_64bit
];
8747 if (flag_code
!= CODE_64BIT
)
8749 types
->bitfield
.imm32
= 1;
8750 types
->bitfield
.disp32
= 1;
8753 *types
= gotrel
[j
].types64
;
8756 if (j
!= 0 && GOT_symbol
== NULL
)
8757 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8759 /* The length of the first part of our input line. */
8760 first
= cp
- input_line_pointer
;
8762 /* The second part goes from after the reloc token until
8763 (and including) an end_of_line char or comma. */
8764 past_reloc
= cp
+ 1 + len
;
8766 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8768 second
= cp
+ 1 - past_reloc
;
8770 /* Allocate and copy string. The trailing NUL shouldn't
8771 be necessary, but be safe. */
8772 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8773 memcpy (tmpbuf
, input_line_pointer
, first
);
8774 if (second
!= 0 && *past_reloc
!= ' ')
8775 /* Replace the relocation token with ' ', so that
8776 errors like foo@GOTOFF1 will be detected. */
8777 tmpbuf
[first
++] = ' ';
8779 /* Increment length by 1 if the relocation token is
8784 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8785 tmpbuf
[first
+ second
] = '\0';
8789 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8790 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8795 /* Might be a symbol version string. Don't as_bad here. */
8804 /* Parse operands of the form
8805 <symbol>@SECREL32+<nnn>
8807 If we find one, set up the correct relocation in RELOC and copy the
8808 input string, minus the `@SECREL32' into a malloc'd buffer for
8809 parsing by the calling routine. Return this buffer, and if ADJUST
8810 is non-null set it to the length of the string we removed from the
8811 input line. Otherwise return NULL.
8813 This function is copied from the ELF version above adjusted for PE targets. */
8816 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8817 int *adjust ATTRIBUTE_UNUSED
,
8818 i386_operand_type
*types
)
8824 const enum bfd_reloc_code_real rel
[2];
8825 const i386_operand_type types64
;
8829 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8830 BFD_RELOC_32_SECREL
},
8831 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8837 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8838 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8841 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8843 int len
= gotrel
[j
].len
;
8845 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8847 if (gotrel
[j
].rel
[object_64bit
] != 0)
8850 char *tmpbuf
, *past_reloc
;
8852 *rel
= gotrel
[j
].rel
[object_64bit
];
8858 if (flag_code
!= CODE_64BIT
)
8860 types
->bitfield
.imm32
= 1;
8861 types
->bitfield
.disp32
= 1;
8864 *types
= gotrel
[j
].types64
;
8867 /* The length of the first part of our input line. */
8868 first
= cp
- input_line_pointer
;
8870 /* The second part goes from after the reloc token until
8871 (and including) an end_of_line char or comma. */
8872 past_reloc
= cp
+ 1 + len
;
8874 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8876 second
= cp
+ 1 - past_reloc
;
8878 /* Allocate and copy string. The trailing NUL shouldn't
8879 be necessary, but be safe. */
8880 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8881 memcpy (tmpbuf
, input_line_pointer
, first
);
8882 if (second
!= 0 && *past_reloc
!= ' ')
8883 /* Replace the relocation token with ' ', so that
8884 errors like foo@SECLREL321 will be detected. */
8885 tmpbuf
[first
++] = ' ';
8886 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8887 tmpbuf
[first
+ second
] = '\0';
8891 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8892 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8897 /* Might be a symbol version string. Don't as_bad here. */
8903 bfd_reloc_code_real_type
8904 x86_cons (expressionS
*exp
, int size
)
8906 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8908 intel_syntax
= -intel_syntax
;
8911 if (size
== 4 || (object_64bit
&& size
== 8))
8913 /* Handle @GOTOFF and the like in an expression. */
8915 char *gotfree_input_line
;
8918 save
= input_line_pointer
;
8919 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8920 if (gotfree_input_line
)
8921 input_line_pointer
= gotfree_input_line
;
8925 if (gotfree_input_line
)
8927 /* expression () has merrily parsed up to the end of line,
8928 or a comma - in the wrong buffer. Transfer how far
8929 input_line_pointer has moved to the right buffer. */
8930 input_line_pointer
= (save
8931 + (input_line_pointer
- gotfree_input_line
)
8933 free (gotfree_input_line
);
8934 if (exp
->X_op
== O_constant
8935 || exp
->X_op
== O_absent
8936 || exp
->X_op
== O_illegal
8937 || exp
->X_op
== O_register
8938 || exp
->X_op
== O_big
)
8940 char c
= *input_line_pointer
;
8941 *input_line_pointer
= 0;
8942 as_bad (_("missing or invalid expression `%s'"), save
);
8943 *input_line_pointer
= c
;
8945 else if ((got_reloc
== BFD_RELOC_386_PLT32
8946 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
8947 && exp
->X_op
!= O_symbol
)
8949 char c
= *input_line_pointer
;
8950 *input_line_pointer
= 0;
8951 as_bad (_("invalid PLT expression `%s'"), save
);
8952 *input_line_pointer
= c
;
8959 intel_syntax
= -intel_syntax
;
8962 i386_intel_simplify (exp
);
8968 signed_cons (int size
)
8970 if (flag_code
== CODE_64BIT
)
8978 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8985 if (exp
.X_op
== O_symbol
)
8986 exp
.X_op
= O_secrel
;
8988 emit_expr (&exp
, 4);
8990 while (*input_line_pointer
++ == ',');
8992 input_line_pointer
--;
8993 demand_empty_rest_of_line ();
8997 /* Handle Vector operations. */
9000 check_VecOperations (char *op_string
, char *op_end
)
9002 const reg_entry
*mask
;
9007 && (op_end
== NULL
|| op_string
< op_end
))
9010 if (*op_string
== '{')
9014 /* Check broadcasts. */
9015 if (strncmp (op_string
, "1to", 3) == 0)
9020 goto duplicated_vec_op
;
9023 if (*op_string
== '8')
9025 else if (*op_string
== '4')
9027 else if (*op_string
== '2')
9029 else if (*op_string
== '1'
9030 && *(op_string
+1) == '6')
9037 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9042 broadcast_op
.type
= bcst_type
;
9043 broadcast_op
.operand
= this_operand
;
9044 broadcast_op
.bytes
= 0;
9045 i
.broadcast
= &broadcast_op
;
9047 /* Check masking operation. */
9048 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9050 /* k0 can't be used for write mask. */
9051 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9053 as_bad (_("`%s%s' can't be used for write mask"),
9054 register_prefix
, mask
->reg_name
);
9060 mask_op
.mask
= mask
;
9061 mask_op
.zeroing
= 0;
9062 mask_op
.operand
= this_operand
;
9068 goto duplicated_vec_op
;
9070 i
.mask
->mask
= mask
;
9072 /* Only "{z}" is allowed here. No need to check
9073 zeroing mask explicitly. */
9074 if (i
.mask
->operand
!= this_operand
)
9076 as_bad (_("invalid write mask `%s'"), saved
);
9083 /* Check zeroing-flag for masking operation. */
9084 else if (*op_string
== 'z')
9088 mask_op
.mask
= NULL
;
9089 mask_op
.zeroing
= 1;
9090 mask_op
.operand
= this_operand
;
9095 if (i
.mask
->zeroing
)
9098 as_bad (_("duplicated `%s'"), saved
);
9102 i
.mask
->zeroing
= 1;
9104 /* Only "{%k}" is allowed here. No need to check mask
9105 register explicitly. */
9106 if (i
.mask
->operand
!= this_operand
)
9108 as_bad (_("invalid zeroing-masking `%s'"),
9117 goto unknown_vec_op
;
9119 if (*op_string
!= '}')
9121 as_bad (_("missing `}' in `%s'"), saved
);
9126 /* Strip whitespace since the addition of pseudo prefixes
9127 changed how the scrubber treats '{'. */
9128 if (is_space_char (*op_string
))
9134 /* We don't know this one. */
9135 as_bad (_("unknown vector operation: `%s'"), saved
);
9139 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9141 as_bad (_("zeroing-masking only allowed with write mask"));
9149 i386_immediate (char *imm_start
)
9151 char *save_input_line_pointer
;
9152 char *gotfree_input_line
;
9155 i386_operand_type types
;
9157 operand_type_set (&types
, ~0);
9159 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9161 as_bad (_("at most %d immediate operands are allowed"),
9162 MAX_IMMEDIATE_OPERANDS
);
9166 exp
= &im_expressions
[i
.imm_operands
++];
9167 i
.op
[this_operand
].imms
= exp
;
9169 if (is_space_char (*imm_start
))
9172 save_input_line_pointer
= input_line_pointer
;
9173 input_line_pointer
= imm_start
;
9175 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9176 if (gotfree_input_line
)
9177 input_line_pointer
= gotfree_input_line
;
9179 exp_seg
= expression (exp
);
9183 /* Handle vector operations. */
9184 if (*input_line_pointer
== '{')
9186 input_line_pointer
= check_VecOperations (input_line_pointer
,
9188 if (input_line_pointer
== NULL
)
9192 if (*input_line_pointer
)
9193 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9195 input_line_pointer
= save_input_line_pointer
;
9196 if (gotfree_input_line
)
9198 free (gotfree_input_line
);
9200 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9201 exp
->X_op
= O_illegal
;
9204 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9208 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9209 i386_operand_type types
, const char *imm_start
)
9211 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9214 as_bad (_("missing or invalid immediate expression `%s'"),
9218 else if (exp
->X_op
== O_constant
)
9220 /* Size it properly later. */
9221 i
.types
[this_operand
].bitfield
.imm64
= 1;
9222 /* If not 64bit, sign extend val. */
9223 if (flag_code
!= CODE_64BIT
9224 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9226 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9228 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9229 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9230 && exp_seg
!= absolute_section
9231 && exp_seg
!= text_section
9232 && exp_seg
!= data_section
9233 && exp_seg
!= bss_section
9234 && exp_seg
!= undefined_section
9235 && !bfd_is_com_section (exp_seg
))
9237 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9241 else if (!intel_syntax
&& exp_seg
== reg_section
)
9244 as_bad (_("illegal immediate register operand %s"), imm_start
);
9249 /* This is an address. The size of the address will be
9250 determined later, depending on destination register,
9251 suffix, or the default for the section. */
9252 i
.types
[this_operand
].bitfield
.imm8
= 1;
9253 i
.types
[this_operand
].bitfield
.imm16
= 1;
9254 i
.types
[this_operand
].bitfield
.imm32
= 1;
9255 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9256 i
.types
[this_operand
].bitfield
.imm64
= 1;
9257 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9265 i386_scale (char *scale
)
9268 char *save
= input_line_pointer
;
9270 input_line_pointer
= scale
;
9271 val
= get_absolute_expression ();
9276 i
.log2_scale_factor
= 0;
9279 i
.log2_scale_factor
= 1;
9282 i
.log2_scale_factor
= 2;
9285 i
.log2_scale_factor
= 3;
9289 char sep
= *input_line_pointer
;
9291 *input_line_pointer
= '\0';
9292 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9294 *input_line_pointer
= sep
;
9295 input_line_pointer
= save
;
9299 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9301 as_warn (_("scale factor of %d without an index register"),
9302 1 << i
.log2_scale_factor
);
9303 i
.log2_scale_factor
= 0;
9305 scale
= input_line_pointer
;
9306 input_line_pointer
= save
;
9311 i386_displacement (char *disp_start
, char *disp_end
)
9315 char *save_input_line_pointer
;
9316 char *gotfree_input_line
;
9318 i386_operand_type bigdisp
, types
= anydisp
;
9321 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9323 as_bad (_("at most %d displacement operands are allowed"),
9324 MAX_MEMORY_OPERANDS
);
9328 operand_type_set (&bigdisp
, 0);
9329 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9330 || (!current_templates
->start
->opcode_modifier
.jump
9331 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9333 bigdisp
.bitfield
.disp32
= 1;
9334 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9335 if (flag_code
== CODE_64BIT
)
9339 bigdisp
.bitfield
.disp32s
= 1;
9340 bigdisp
.bitfield
.disp64
= 1;
9343 else if ((flag_code
== CODE_16BIT
) ^ override
)
9345 bigdisp
.bitfield
.disp32
= 0;
9346 bigdisp
.bitfield
.disp16
= 1;
9351 /* For PC-relative branches, the width of the displacement
9352 is dependent upon data size, not address size. */
9353 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9354 if (flag_code
== CODE_64BIT
)
9356 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9357 bigdisp
.bitfield
.disp16
= 1;
9360 bigdisp
.bitfield
.disp32
= 1;
9361 bigdisp
.bitfield
.disp32s
= 1;
9367 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9369 : LONG_MNEM_SUFFIX
));
9370 bigdisp
.bitfield
.disp32
= 1;
9371 if ((flag_code
== CODE_16BIT
) ^ override
)
9373 bigdisp
.bitfield
.disp32
= 0;
9374 bigdisp
.bitfield
.disp16
= 1;
9378 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9381 exp
= &disp_expressions
[i
.disp_operands
];
9382 i
.op
[this_operand
].disps
= exp
;
9384 save_input_line_pointer
= input_line_pointer
;
9385 input_line_pointer
= disp_start
;
9386 END_STRING_AND_SAVE (disp_end
);
9388 #ifndef GCC_ASM_O_HACK
9389 #define GCC_ASM_O_HACK 0
9392 END_STRING_AND_SAVE (disp_end
+ 1);
9393 if (i
.types
[this_operand
].bitfield
.baseIndex
9394 && displacement_string_end
[-1] == '+')
9396 /* This hack is to avoid a warning when using the "o"
9397 constraint within gcc asm statements.
9400 #define _set_tssldt_desc(n,addr,limit,type) \
9401 __asm__ __volatile__ ( \
9403 "movw %w1,2+%0\n\t" \
9405 "movb %b1,4+%0\n\t" \
9406 "movb %4,5+%0\n\t" \
9407 "movb $0,6+%0\n\t" \
9408 "movb %h1,7+%0\n\t" \
9410 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9412 This works great except that the output assembler ends
9413 up looking a bit weird if it turns out that there is
9414 no offset. You end up producing code that looks like:
9427 So here we provide the missing zero. */
9429 *displacement_string_end
= '0';
9432 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9433 if (gotfree_input_line
)
9434 input_line_pointer
= gotfree_input_line
;
9436 exp_seg
= expression (exp
);
9439 if (*input_line_pointer
)
9440 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9442 RESTORE_END_STRING (disp_end
+ 1);
9444 input_line_pointer
= save_input_line_pointer
;
9445 if (gotfree_input_line
)
9447 free (gotfree_input_line
);
9449 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9450 exp
->X_op
= O_illegal
;
9453 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9455 RESTORE_END_STRING (disp_end
);
9461 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9462 i386_operand_type types
, const char *disp_start
)
9464 i386_operand_type bigdisp
;
9467 /* We do this to make sure that the section symbol is in
9468 the symbol table. We will ultimately change the relocation
9469 to be relative to the beginning of the section. */
9470 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9471 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9472 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9474 if (exp
->X_op
!= O_symbol
)
9477 if (S_IS_LOCAL (exp
->X_add_symbol
)
9478 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9479 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9480 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9481 exp
->X_op
= O_subtract
;
9482 exp
->X_op_symbol
= GOT_symbol
;
9483 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9484 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9485 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9486 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9488 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9491 else if (exp
->X_op
== O_absent
9492 || exp
->X_op
== O_illegal
9493 || exp
->X_op
== O_big
)
9496 as_bad (_("missing or invalid displacement expression `%s'"),
9501 else if (flag_code
== CODE_64BIT
9502 && !i
.prefix
[ADDR_PREFIX
]
9503 && exp
->X_op
== O_constant
)
9505 /* Since displacement is signed extended to 64bit, don't allow
9506 disp32 and turn off disp32s if they are out of range. */
9507 i
.types
[this_operand
].bitfield
.disp32
= 0;
9508 if (!fits_in_signed_long (exp
->X_add_number
))
9510 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9511 if (i
.types
[this_operand
].bitfield
.baseindex
)
9513 as_bad (_("0x%lx out range of signed 32bit displacement"),
9514 (long) exp
->X_add_number
);
9520 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9521 else if (exp
->X_op
!= O_constant
9522 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9523 && exp_seg
!= absolute_section
9524 && exp_seg
!= text_section
9525 && exp_seg
!= data_section
9526 && exp_seg
!= bss_section
9527 && exp_seg
!= undefined_section
9528 && !bfd_is_com_section (exp_seg
))
9530 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9535 /* Check if this is a displacement only operand. */
9536 bigdisp
= i
.types
[this_operand
];
9537 bigdisp
.bitfield
.disp8
= 0;
9538 bigdisp
.bitfield
.disp16
= 0;
9539 bigdisp
.bitfield
.disp32
= 0;
9540 bigdisp
.bitfield
.disp32s
= 0;
9541 bigdisp
.bitfield
.disp64
= 0;
9542 if (operand_type_all_zero (&bigdisp
))
9543 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9549 /* Return the active addressing mode, taking address override and
9550 registers forming the address into consideration. Update the
9551 address override prefix if necessary. */
9553 static enum flag_code
9554 i386_addressing_mode (void)
9556 enum flag_code addr_mode
;
9558 if (i
.prefix
[ADDR_PREFIX
])
9559 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9562 addr_mode
= flag_code
;
9564 #if INFER_ADDR_PREFIX
9565 if (i
.mem_operands
== 0)
9567 /* Infer address prefix from the first memory operand. */
9568 const reg_entry
*addr_reg
= i
.base_reg
;
9570 if (addr_reg
== NULL
)
9571 addr_reg
= i
.index_reg
;
9575 if (addr_reg
->reg_type
.bitfield
.dword
)
9576 addr_mode
= CODE_32BIT
;
9577 else if (flag_code
!= CODE_64BIT
9578 && addr_reg
->reg_type
.bitfield
.word
)
9579 addr_mode
= CODE_16BIT
;
9581 if (addr_mode
!= flag_code
)
9583 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9585 /* Change the size of any displacement too. At most one
9586 of Disp16 or Disp32 is set.
9587 FIXME. There doesn't seem to be any real need for
9588 separate Disp16 and Disp32 flags. The same goes for
9589 Imm16 and Imm32. Removing them would probably clean
9590 up the code quite a lot. */
9591 if (flag_code
!= CODE_64BIT
9592 && (i
.types
[this_operand
].bitfield
.disp16
9593 || i
.types
[this_operand
].bitfield
.disp32
))
9594 i
.types
[this_operand
]
9595 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9605 /* Make sure the memory operand we've been dealt is valid.
9606 Return 1 on success, 0 on a failure. */
9609 i386_index_check (const char *operand_string
)
9611 const char *kind
= "base/index";
9612 enum flag_code addr_mode
= i386_addressing_mode ();
9614 if (current_templates
->start
->opcode_modifier
.isstring
9615 && !current_templates
->start
->opcode_modifier
.immext
9616 && (current_templates
->end
[-1].opcode_modifier
.isstring
9619 /* Memory operands of string insns are special in that they only allow
9620 a single register (rDI, rSI, or rBX) as their memory address. */
9621 const reg_entry
*expected_reg
;
9622 static const char *di_si
[][2] =
9628 static const char *bx
[] = { "ebx", "bx", "rbx" };
9630 kind
= "string address";
9632 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9634 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9636 if (!type
.bitfield
.baseindex
9637 || ((!i
.mem_operands
!= !intel_syntax
)
9638 && current_templates
->end
[-1].operand_types
[1]
9639 .bitfield
.baseindex
))
9640 type
= current_templates
->end
[-1].operand_types
[1];
9641 expected_reg
= hash_find (reg_hash
,
9642 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9646 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9648 if (i
.base_reg
!= expected_reg
9650 || operand_type_check (i
.types
[this_operand
], disp
))
9652 /* The second memory operand must have the same size as
9656 && !((addr_mode
== CODE_64BIT
9657 && i
.base_reg
->reg_type
.bitfield
.qword
)
9658 || (addr_mode
== CODE_32BIT
9659 ? i
.base_reg
->reg_type
.bitfield
.dword
9660 : i
.base_reg
->reg_type
.bitfield
.word
)))
9663 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9665 intel_syntax
? '[' : '(',
9667 expected_reg
->reg_name
,
9668 intel_syntax
? ']' : ')');
9675 as_bad (_("`%s' is not a valid %s expression"),
9676 operand_string
, kind
);
9681 if (addr_mode
!= CODE_16BIT
)
9683 /* 32-bit/64-bit checks. */
9685 && ((addr_mode
== CODE_64BIT
9686 ? !i
.base_reg
->reg_type
.bitfield
.qword
9687 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9688 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9689 || i
.base_reg
->reg_num
== RegIZ
))
9691 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9692 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9693 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9694 && ((addr_mode
== CODE_64BIT
9695 ? !i
.index_reg
->reg_type
.bitfield
.qword
9696 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9697 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9700 /* bndmk, bndldx, and bndstx have special restrictions. */
9701 if (current_templates
->start
->base_opcode
== 0xf30f1b
9702 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9704 /* They cannot use RIP-relative addressing. */
9705 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9707 as_bad (_("`%s' cannot be used here"), operand_string
);
9711 /* bndldx and bndstx ignore their scale factor. */
9712 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9713 && i
.log2_scale_factor
)
9714 as_warn (_("register scaling is being ignored here"));
9719 /* 16-bit checks. */
9721 && (!i
.base_reg
->reg_type
.bitfield
.word
9722 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9724 && (!i
.index_reg
->reg_type
.bitfield
.word
9725 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9727 && i
.base_reg
->reg_num
< 6
9728 && i
.index_reg
->reg_num
>= 6
9729 && i
.log2_scale_factor
== 0))))
9736 /* Handle vector immediates. */
9739 RC_SAE_immediate (const char *imm_start
)
9741 unsigned int match_found
, j
;
9742 const char *pstr
= imm_start
;
9750 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9752 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9756 rc_op
.type
= RC_NamesTable
[j
].type
;
9757 rc_op
.operand
= this_operand
;
9758 i
.rounding
= &rc_op
;
9762 as_bad (_("duplicated `%s'"), imm_start
);
9765 pstr
+= RC_NamesTable
[j
].len
;
9775 as_bad (_("Missing '}': '%s'"), imm_start
);
9778 /* RC/SAE immediate string should contain nothing more. */;
9781 as_bad (_("Junk after '}': '%s'"), imm_start
);
9785 exp
= &im_expressions
[i
.imm_operands
++];
9786 i
.op
[this_operand
].imms
= exp
;
9788 exp
->X_op
= O_constant
;
9789 exp
->X_add_number
= 0;
9790 exp
->X_add_symbol
= (symbolS
*) 0;
9791 exp
->X_op_symbol
= (symbolS
*) 0;
9793 i
.types
[this_operand
].bitfield
.imm8
= 1;
9797 /* Only string instructions can have a second memory operand, so
9798 reduce current_templates to just those if it contains any. */
9800 maybe_adjust_templates (void)
9802 const insn_template
*t
;
9804 gas_assert (i
.mem_operands
== 1);
9806 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9807 if (t
->opcode_modifier
.isstring
)
9810 if (t
< current_templates
->end
)
9812 static templates aux_templates
;
9813 bfd_boolean recheck
;
9815 aux_templates
.start
= t
;
9816 for (; t
< current_templates
->end
; ++t
)
9817 if (!t
->opcode_modifier
.isstring
)
9819 aux_templates
.end
= t
;
9821 /* Determine whether to re-check the first memory operand. */
9822 recheck
= (aux_templates
.start
!= current_templates
->start
9823 || t
!= current_templates
->end
);
9825 current_templates
= &aux_templates
;
9830 if (i
.memop1_string
!= NULL
9831 && i386_index_check (i
.memop1_string
) == 0)
9840 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9844 i386_att_operand (char *operand_string
)
9848 char *op_string
= operand_string
;
9850 if (is_space_char (*op_string
))
9853 /* We check for an absolute prefix (differentiating,
9854 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9855 if (*op_string
== ABSOLUTE_PREFIX
)
9858 if (is_space_char (*op_string
))
9860 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9863 /* Check if operand is a register. */
9864 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9866 i386_operand_type temp
;
9868 /* Check for a segment override by searching for ':' after a
9869 segment register. */
9871 if (is_space_char (*op_string
))
9873 if (*op_string
== ':'
9874 && (r
->reg_type
.bitfield
.sreg2
9875 || r
->reg_type
.bitfield
.sreg3
))
9880 i
.seg
[i
.mem_operands
] = &es
;
9883 i
.seg
[i
.mem_operands
] = &cs
;
9886 i
.seg
[i
.mem_operands
] = &ss
;
9889 i
.seg
[i
.mem_operands
] = &ds
;
9892 i
.seg
[i
.mem_operands
] = &fs
;
9895 i
.seg
[i
.mem_operands
] = &gs
;
9899 /* Skip the ':' and whitespace. */
9901 if (is_space_char (*op_string
))
9904 if (!is_digit_char (*op_string
)
9905 && !is_identifier_char (*op_string
)
9906 && *op_string
!= '('
9907 && *op_string
!= ABSOLUTE_PREFIX
)
9909 as_bad (_("bad memory operand `%s'"), op_string
);
9912 /* Handle case of %es:*foo. */
9913 if (*op_string
== ABSOLUTE_PREFIX
)
9916 if (is_space_char (*op_string
))
9918 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9920 goto do_memory_reference
;
9923 /* Handle vector operations. */
9924 if (*op_string
== '{')
9926 op_string
= check_VecOperations (op_string
, NULL
);
9927 if (op_string
== NULL
)
9933 as_bad (_("junk `%s' after register"), op_string
);
9937 temp
.bitfield
.baseindex
= 0;
9938 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9940 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9941 i
.op
[this_operand
].regs
= r
;
9944 else if (*op_string
== REGISTER_PREFIX
)
9946 as_bad (_("bad register name `%s'"), op_string
);
9949 else if (*op_string
== IMMEDIATE_PREFIX
)
9952 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9954 as_bad (_("immediate operand illegal with absolute jump"));
9957 if (!i386_immediate (op_string
))
9960 else if (RC_SAE_immediate (operand_string
))
9962 /* If it is a RC or SAE immediate, do nothing. */
9965 else if (is_digit_char (*op_string
)
9966 || is_identifier_char (*op_string
)
9967 || *op_string
== '"'
9968 || *op_string
== '(')
9970 /* This is a memory reference of some sort. */
9973 /* Start and end of displacement string expression (if found). */
9974 char *displacement_string_start
;
9975 char *displacement_string_end
;
9978 do_memory_reference
:
9979 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9981 if ((i
.mem_operands
== 1
9982 && !current_templates
->start
->opcode_modifier
.isstring
)
9983 || i
.mem_operands
== 2)
9985 as_bad (_("too many memory references for `%s'"),
9986 current_templates
->start
->name
);
9990 /* Check for base index form. We detect the base index form by
9991 looking for an ')' at the end of the operand, searching
9992 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9994 base_string
= op_string
+ strlen (op_string
);
9996 /* Handle vector operations. */
9997 vop_start
= strchr (op_string
, '{');
9998 if (vop_start
&& vop_start
< base_string
)
10000 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10002 base_string
= vop_start
;
10006 if (is_space_char (*base_string
))
10009 /* If we only have a displacement, set-up for it to be parsed later. */
10010 displacement_string_start
= op_string
;
10011 displacement_string_end
= base_string
+ 1;
10013 if (*base_string
== ')')
10016 unsigned int parens_balanced
= 1;
10017 /* We've already checked that the number of left & right ()'s are
10018 equal, so this loop will not be infinite. */
10022 if (*base_string
== ')')
10024 if (*base_string
== '(')
10027 while (parens_balanced
);
10029 temp_string
= base_string
;
10031 /* Skip past '(' and whitespace. */
10033 if (is_space_char (*base_string
))
10036 if (*base_string
== ','
10037 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10040 displacement_string_end
= temp_string
;
10042 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10046 base_string
= end_op
;
10047 if (is_space_char (*base_string
))
10051 /* There may be an index reg or scale factor here. */
10052 if (*base_string
== ',')
10055 if (is_space_char (*base_string
))
10058 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10061 base_string
= end_op
;
10062 if (is_space_char (*base_string
))
10064 if (*base_string
== ',')
10067 if (is_space_char (*base_string
))
10070 else if (*base_string
!= ')')
10072 as_bad (_("expecting `,' or `)' "
10073 "after index register in `%s'"),
10078 else if (*base_string
== REGISTER_PREFIX
)
10080 end_op
= strchr (base_string
, ',');
10083 as_bad (_("bad register name `%s'"), base_string
);
10087 /* Check for scale factor. */
10088 if (*base_string
!= ')')
10090 char *end_scale
= i386_scale (base_string
);
10095 base_string
= end_scale
;
10096 if (is_space_char (*base_string
))
10098 if (*base_string
!= ')')
10100 as_bad (_("expecting `)' "
10101 "after scale factor in `%s'"),
10106 else if (!i
.index_reg
)
10108 as_bad (_("expecting index register or scale factor "
10109 "after `,'; got '%c'"),
10114 else if (*base_string
!= ')')
10116 as_bad (_("expecting `,' or `)' "
10117 "after base register in `%s'"),
10122 else if (*base_string
== REGISTER_PREFIX
)
10124 end_op
= strchr (base_string
, ',');
10127 as_bad (_("bad register name `%s'"), base_string
);
10132 /* If there's an expression beginning the operand, parse it,
10133 assuming displacement_string_start and
10134 displacement_string_end are meaningful. */
10135 if (displacement_string_start
!= displacement_string_end
)
10137 if (!i386_displacement (displacement_string_start
,
10138 displacement_string_end
))
10142 /* Special case for (%dx) while doing input/output op. */
10144 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10145 && i
.index_reg
== 0
10146 && i
.log2_scale_factor
== 0
10147 && i
.seg
[i
.mem_operands
] == 0
10148 && !operand_type_check (i
.types
[this_operand
], disp
))
10150 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10154 if (i386_index_check (operand_string
) == 0)
10156 i
.flags
[this_operand
] |= Operand_Mem
;
10157 if (i
.mem_operands
== 0)
10158 i
.memop1_string
= xstrdup (operand_string
);
10163 /* It's not a memory operand; argh! */
10164 as_bad (_("invalid char %s beginning operand %d `%s'"),
10165 output_invalid (*op_string
),
10170 return 1; /* Normal return. */
10173 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10174 that an rs_machine_dependent frag may reach. */
10177 i386_frag_max_var (fragS
*frag
)
10179 /* The only relaxable frags are for jumps.
10180 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10181 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10182 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10187 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10189 /* STT_GNU_IFUNC symbol must go through PLT. */
10190 if ((symbol_get_bfdsym (fr_symbol
)->flags
10191 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10194 if (!S_IS_EXTERNAL (fr_symbol
))
10195 /* Symbol may be weak or local. */
10196 return !S_IS_WEAK (fr_symbol
);
10198 /* Global symbols with non-default visibility can't be preempted. */
10199 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10202 if (fr_var
!= NO_RELOC
)
10203 switch ((enum bfd_reloc_code_real
) fr_var
)
10205 case BFD_RELOC_386_PLT32
:
10206 case BFD_RELOC_X86_64_PLT32
:
10207 /* Symbol with PLT relocation may be preempted. */
10213 /* Global symbols with default visibility in a shared library may be
10214 preempted by another definition. */
10219 /* md_estimate_size_before_relax()
10221 Called just before relax() for rs_machine_dependent frags. The x86
10222 assembler uses these frags to handle variable size jump
10225 Any symbol that is now undefined will not become defined.
10226 Return the correct fr_subtype in the frag.
10227 Return the initial "guess for variable size of frag" to caller.
10228 The guess is actually the growth beyond the fixed part. Whatever
10229 we do to grow the fixed or variable part contributes to our
10233 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10235 /* We've already got fragP->fr_subtype right; all we have to do is
10236 check for un-relaxable symbols. On an ELF system, we can't relax
10237 an externally visible symbol, because it may be overridden by a
10239 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10242 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10245 #if defined (OBJ_COFF) && defined (TE_PE)
10246 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10247 && S_IS_WEAK (fragP
->fr_symbol
))
10251 /* Symbol is undefined in this segment, or we need to keep a
10252 reloc so that weak symbols can be overridden. */
10253 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10254 enum bfd_reloc_code_real reloc_type
;
10255 unsigned char *opcode
;
10258 if (fragP
->fr_var
!= NO_RELOC
)
10259 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10260 else if (size
== 2)
10261 reloc_type
= BFD_RELOC_16_PCREL
;
10262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10263 else if (need_plt32_p (fragP
->fr_symbol
))
10264 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10267 reloc_type
= BFD_RELOC_32_PCREL
;
10269 old_fr_fix
= fragP
->fr_fix
;
10270 opcode
= (unsigned char *) fragP
->fr_opcode
;
10272 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10275 /* Make jmp (0xeb) a (d)word displacement jump. */
10277 fragP
->fr_fix
+= size
;
10278 fix_new (fragP
, old_fr_fix
, size
,
10280 fragP
->fr_offset
, 1,
10286 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10288 /* Negate the condition, and branch past an
10289 unconditional jump. */
10292 /* Insert an unconditional jump. */
10294 /* We added two extra opcode bytes, and have a two byte
10296 fragP
->fr_fix
+= 2 + 2;
10297 fix_new (fragP
, old_fr_fix
+ 2, 2,
10299 fragP
->fr_offset
, 1,
10303 /* Fall through. */
10306 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10310 fragP
->fr_fix
+= 1;
10311 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10313 fragP
->fr_offset
, 1,
10314 BFD_RELOC_8_PCREL
);
10315 fixP
->fx_signed
= 1;
10319 /* This changes the byte-displacement jump 0x7N
10320 to the (d)word-displacement jump 0x0f,0x8N. */
10321 opcode
[1] = opcode
[0] + 0x10;
10322 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10323 /* We've added an opcode byte. */
10324 fragP
->fr_fix
+= 1 + size
;
10325 fix_new (fragP
, old_fr_fix
+ 1, size
,
10327 fragP
->fr_offset
, 1,
10332 BAD_CASE (fragP
->fr_subtype
);
10336 return fragP
->fr_fix
- old_fr_fix
;
10339 /* Guess size depending on current relax state. Initially the relax
10340 state will correspond to a short jump and we return 1, because
10341 the variable part of the frag (the branch offset) is one byte
10342 long. However, we can relax a section more than once and in that
10343 case we must either set fr_subtype back to the unrelaxed state,
10344 or return the value for the appropriate branch. */
10345 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10348 /* Called after relax() is finished.
10350 In: Address of frag.
10351 fr_type == rs_machine_dependent.
10352 fr_subtype is what the address relaxed to.
10354 Out: Any fixSs and constants are set up.
10355 Caller will turn frag into a ".space 0". */
10358 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10361 unsigned char *opcode
;
10362 unsigned char *where_to_put_displacement
= NULL
;
10363 offsetT target_address
;
10364 offsetT opcode_address
;
10365 unsigned int extension
= 0;
10366 offsetT displacement_from_opcode_start
;
10368 opcode
= (unsigned char *) fragP
->fr_opcode
;
10370 /* Address we want to reach in file space. */
10371 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10373 /* Address opcode resides at in file space. */
10374 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10376 /* Displacement from opcode start to fill into instruction. */
10377 displacement_from_opcode_start
= target_address
- opcode_address
;
10379 if ((fragP
->fr_subtype
& BIG
) == 0)
10381 /* Don't have to change opcode. */
10382 extension
= 1; /* 1 opcode + 1 displacement */
10383 where_to_put_displacement
= &opcode
[1];
10387 if (no_cond_jump_promotion
10388 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10389 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10390 _("long jump required"));
10392 switch (fragP
->fr_subtype
)
10394 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10395 extension
= 4; /* 1 opcode + 4 displacement */
10397 where_to_put_displacement
= &opcode
[1];
10400 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10401 extension
= 2; /* 1 opcode + 2 displacement */
10403 where_to_put_displacement
= &opcode
[1];
10406 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10407 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10408 extension
= 5; /* 2 opcode + 4 displacement */
10409 opcode
[1] = opcode
[0] + 0x10;
10410 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10411 where_to_put_displacement
= &opcode
[2];
10414 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10415 extension
= 3; /* 2 opcode + 2 displacement */
10416 opcode
[1] = opcode
[0] + 0x10;
10417 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10418 where_to_put_displacement
= &opcode
[2];
10421 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10426 where_to_put_displacement
= &opcode
[3];
10430 BAD_CASE (fragP
->fr_subtype
);
10435 /* If size if less then four we are sure that the operand fits,
10436 but if it's 4, then it could be that the displacement is larger
10438 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10440 && ((addressT
) (displacement_from_opcode_start
- extension
10441 + ((addressT
) 1 << 31))
10442 > (((addressT
) 2 << 31) - 1)))
10444 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10445 _("jump target out of range"));
10446 /* Make us emit 0. */
10447 displacement_from_opcode_start
= extension
;
10449 /* Now put displacement after opcode. */
10450 md_number_to_chars ((char *) where_to_put_displacement
,
10451 (valueT
) (displacement_from_opcode_start
- extension
),
10452 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10453 fragP
->fr_fix
+= extension
;
10456 /* Apply a fixup (fixP) to segment data, once it has been determined
10457 by our caller that we have all the info we need to fix it up.
10459 Parameter valP is the pointer to the value of the bits.
10461 On the 386, immediates, displacements, and data pointers are all in
10462 the same (little-endian) format, so we don't need to care about which
10463 we are handling. */
10466 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10468 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10469 valueT value
= *valP
;
10471 #if !defined (TE_Mach)
10472 if (fixP
->fx_pcrel
)
10474 switch (fixP
->fx_r_type
)
10480 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10483 case BFD_RELOC_X86_64_32S
:
10484 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10487 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10490 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10495 if (fixP
->fx_addsy
!= NULL
10496 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10497 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10498 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10499 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10500 && !use_rela_relocations
)
10502 /* This is a hack. There should be a better way to handle this.
10503 This covers for the fact that bfd_install_relocation will
10504 subtract the current location (for partial_inplace, PC relative
10505 relocations); see more below. */
10509 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10512 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10514 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10517 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10519 if ((sym_seg
== seg
10520 || (symbol_section_p (fixP
->fx_addsy
)
10521 && sym_seg
!= absolute_section
))
10522 && !generic_force_reloc (fixP
))
10524 /* Yes, we add the values in twice. This is because
10525 bfd_install_relocation subtracts them out again. I think
10526 bfd_install_relocation is broken, but I don't dare change
10528 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10532 #if defined (OBJ_COFF) && defined (TE_PE)
10533 /* For some reason, the PE format does not store a
10534 section address offset for a PC relative symbol. */
10535 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10536 || S_IS_WEAK (fixP
->fx_addsy
))
10537 value
+= md_pcrel_from (fixP
);
10540 #if defined (OBJ_COFF) && defined (TE_PE)
10541 if (fixP
->fx_addsy
!= NULL
10542 && S_IS_WEAK (fixP
->fx_addsy
)
10543 /* PR 16858: Do not modify weak function references. */
10544 && ! fixP
->fx_pcrel
)
10546 #if !defined (TE_PEP)
10547 /* For x86 PE weak function symbols are neither PC-relative
10548 nor do they set S_IS_FUNCTION. So the only reliable way
10549 to detect them is to check the flags of their containing
10551 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10552 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10556 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10560 /* Fix a few things - the dynamic linker expects certain values here,
10561 and we must not disappoint it. */
10562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10563 if (IS_ELF
&& fixP
->fx_addsy
)
10564 switch (fixP
->fx_r_type
)
10566 case BFD_RELOC_386_PLT32
:
10567 case BFD_RELOC_X86_64_PLT32
:
10568 /* Make the jump instruction point to the address of the operand.
10569 At runtime we merely add the offset to the actual PLT entry.
10570 NB: Subtract the offset size only for jump instructions. */
10571 if (fixP
->fx_pcrel
)
10575 case BFD_RELOC_386_TLS_GD
:
10576 case BFD_RELOC_386_TLS_LDM
:
10577 case BFD_RELOC_386_TLS_IE_32
:
10578 case BFD_RELOC_386_TLS_IE
:
10579 case BFD_RELOC_386_TLS_GOTIE
:
10580 case BFD_RELOC_386_TLS_GOTDESC
:
10581 case BFD_RELOC_X86_64_TLSGD
:
10582 case BFD_RELOC_X86_64_TLSLD
:
10583 case BFD_RELOC_X86_64_GOTTPOFF
:
10584 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10585 value
= 0; /* Fully resolved at runtime. No addend. */
10587 case BFD_RELOC_386_TLS_LE
:
10588 case BFD_RELOC_386_TLS_LDO_32
:
10589 case BFD_RELOC_386_TLS_LE_32
:
10590 case BFD_RELOC_X86_64_DTPOFF32
:
10591 case BFD_RELOC_X86_64_DTPOFF64
:
10592 case BFD_RELOC_X86_64_TPOFF32
:
10593 case BFD_RELOC_X86_64_TPOFF64
:
10594 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10597 case BFD_RELOC_386_TLS_DESC_CALL
:
10598 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10599 value
= 0; /* Fully resolved at runtime. No addend. */
10600 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10604 case BFD_RELOC_VTABLE_INHERIT
:
10605 case BFD_RELOC_VTABLE_ENTRY
:
10612 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10614 #endif /* !defined (TE_Mach) */
10616 /* Are we finished with this relocation now? */
10617 if (fixP
->fx_addsy
== NULL
)
10619 #if defined (OBJ_COFF) && defined (TE_PE)
10620 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10623 /* Remember value for tc_gen_reloc. */
10624 fixP
->fx_addnumber
= value
;
10625 /* Clear out the frag for now. */
10629 else if (use_rela_relocations
)
10631 fixP
->fx_no_overflow
= 1;
10632 /* Remember value for tc_gen_reloc. */
10633 fixP
->fx_addnumber
= value
;
10637 md_number_to_chars (p
, value
, fixP
->fx_size
);
10641 md_atof (int type
, char *litP
, int *sizeP
)
10643 /* This outputs the LITTLENUMs in REVERSE order;
10644 in accord with the bigendian 386. */
10645 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10648 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10651 output_invalid (int c
)
10654 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10657 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10658 "(0x%x)", (unsigned char) c
);
10659 return output_invalid_buf
;
10662 /* REG_STRING starts *before* REGISTER_PREFIX. */
10664 static const reg_entry
*
10665 parse_real_register (char *reg_string
, char **end_op
)
10667 char *s
= reg_string
;
10669 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10670 const reg_entry
*r
;
10672 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10673 if (*s
== REGISTER_PREFIX
)
10676 if (is_space_char (*s
))
10679 p
= reg_name_given
;
10680 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10682 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10683 return (const reg_entry
*) NULL
;
10687 /* For naked regs, make sure that we are not dealing with an identifier.
10688 This prevents confusing an identifier like `eax_var' with register
10690 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10691 return (const reg_entry
*) NULL
;
10695 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10697 /* Handle floating point regs, allowing spaces in the (i) part. */
10698 if (r
== i386_regtab
/* %st is first entry of table */)
10700 if (!cpu_arch_flags
.bitfield
.cpu8087
10701 && !cpu_arch_flags
.bitfield
.cpu287
10702 && !cpu_arch_flags
.bitfield
.cpu387
)
10703 return (const reg_entry
*) NULL
;
10705 if (is_space_char (*s
))
10710 if (is_space_char (*s
))
10712 if (*s
>= '0' && *s
<= '7')
10714 int fpr
= *s
- '0';
10716 if (is_space_char (*s
))
10721 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10726 /* We have "%st(" then garbage. */
10727 return (const reg_entry
*) NULL
;
10731 if (r
== NULL
|| allow_pseudo_reg
)
10734 if (operand_type_all_zero (&r
->reg_type
))
10735 return (const reg_entry
*) NULL
;
10737 if ((r
->reg_type
.bitfield
.dword
10738 || r
->reg_type
.bitfield
.sreg3
10739 || r
->reg_type
.bitfield
.control
10740 || r
->reg_type
.bitfield
.debug
10741 || r
->reg_type
.bitfield
.test
)
10742 && !cpu_arch_flags
.bitfield
.cpui386
)
10743 return (const reg_entry
*) NULL
;
10745 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10746 return (const reg_entry
*) NULL
;
10748 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10750 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10751 return (const reg_entry
*) NULL
;
10753 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10755 if (r
->reg_type
.bitfield
.ymmword
)
10756 return (const reg_entry
*) NULL
;
10758 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10759 return (const reg_entry
*) NULL
;
10763 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10764 return (const reg_entry
*) NULL
;
10766 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10767 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10768 return (const reg_entry
*) NULL
;
10770 /* Upper 16 vector registers are only available with VREX in 64bit
10771 mode, and require EVEX encoding. */
10772 if (r
->reg_flags
& RegVRex
)
10774 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10775 || flag_code
!= CODE_64BIT
)
10776 return (const reg_entry
*) NULL
;
10778 i
.vec_encoding
= vex_encoding_evex
;
10781 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10782 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10783 && flag_code
!= CODE_64BIT
)
10784 return (const reg_entry
*) NULL
;
10786 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10787 return (const reg_entry
*) NULL
;
10792 /* REG_STRING starts *before* REGISTER_PREFIX. */
10794 static const reg_entry
*
10795 parse_register (char *reg_string
, char **end_op
)
10797 const reg_entry
*r
;
10799 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10800 r
= parse_real_register (reg_string
, end_op
);
10805 char *save
= input_line_pointer
;
10809 input_line_pointer
= reg_string
;
10810 c
= get_symbol_name (®_string
);
10811 symbolP
= symbol_find (reg_string
);
10812 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10814 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10816 know (e
->X_op
== O_register
);
10817 know (e
->X_add_number
>= 0
10818 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10819 r
= i386_regtab
+ e
->X_add_number
;
10820 if ((r
->reg_flags
& RegVRex
))
10821 i
.vec_encoding
= vex_encoding_evex
;
10822 *end_op
= input_line_pointer
;
10824 *input_line_pointer
= c
;
10825 input_line_pointer
= save
;
10831 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10833 const reg_entry
*r
;
10834 char *end
= input_line_pointer
;
10837 r
= parse_register (name
, &input_line_pointer
);
10838 if (r
&& end
<= input_line_pointer
)
10840 *nextcharP
= *input_line_pointer
;
10841 *input_line_pointer
= 0;
10842 e
->X_op
= O_register
;
10843 e
->X_add_number
= r
- i386_regtab
;
10846 input_line_pointer
= end
;
10848 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10852 md_operand (expressionS
*e
)
10855 const reg_entry
*r
;
10857 switch (*input_line_pointer
)
10859 case REGISTER_PREFIX
:
10860 r
= parse_real_register (input_line_pointer
, &end
);
10863 e
->X_op
= O_register
;
10864 e
->X_add_number
= r
- i386_regtab
;
10865 input_line_pointer
= end
;
10870 gas_assert (intel_syntax
);
10871 end
= input_line_pointer
++;
10873 if (*input_line_pointer
== ']')
10875 ++input_line_pointer
;
10876 e
->X_op_symbol
= make_expr_symbol (e
);
10877 e
->X_add_symbol
= NULL
;
10878 e
->X_add_number
= 0;
10883 e
->X_op
= O_absent
;
10884 input_line_pointer
= end
;
10891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10892 const char *md_shortopts
= "kVQ:sqnO::";
10894 const char *md_shortopts
= "qnO::";
10897 #define OPTION_32 (OPTION_MD_BASE + 0)
10898 #define OPTION_64 (OPTION_MD_BASE + 1)
10899 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10900 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10901 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10902 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10903 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10904 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10905 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10906 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10907 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10908 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10909 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10910 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10911 #define OPTION_X32 (OPTION_MD_BASE + 14)
10912 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10913 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10914 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10915 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10916 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10917 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10918 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10919 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10920 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10921 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10922 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10923 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10925 struct option md_longopts
[] =
10927 {"32", no_argument
, NULL
, OPTION_32
},
10928 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10929 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10930 {"64", no_argument
, NULL
, OPTION_64
},
10932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10933 {"x32", no_argument
, NULL
, OPTION_X32
},
10934 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10935 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10937 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10938 {"march", required_argument
, NULL
, OPTION_MARCH
},
10939 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10940 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10941 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10942 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10943 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10944 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10945 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10946 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10947 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10948 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
10949 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10950 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10951 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10952 # if defined (TE_PE) || defined (TE_PEP)
10953 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10955 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10956 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10957 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10958 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10959 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10960 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10961 {NULL
, no_argument
, NULL
, 0}
10963 size_t md_longopts_size
= sizeof (md_longopts
);
10966 md_parse_option (int c
, const char *arg
)
10969 char *arch
, *next
, *saved
;
10974 optimize_align_code
= 0;
10978 quiet_warnings
= 1;
10981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10982 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10983 should be emitted or not. FIXME: Not implemented. */
10987 /* -V: SVR4 argument to print version ID. */
10989 print_version_id ();
10992 /* -k: Ignore for FreeBSD compatibility. */
10997 /* -s: On i386 Solaris, this tells the native assembler to use
10998 .stab instead of .stab.excl. We always use .stab anyhow. */
11001 case OPTION_MSHARED
:
11005 case OPTION_X86_USED_NOTE
:
11006 if (strcasecmp (arg
, "yes") == 0)
11008 else if (strcasecmp (arg
, "no") == 0)
11011 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11016 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11017 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11020 const char **list
, **l
;
11022 list
= bfd_target_list ();
11023 for (l
= list
; *l
!= NULL
; l
++)
11024 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11025 || strcmp (*l
, "coff-x86-64") == 0
11026 || strcmp (*l
, "pe-x86-64") == 0
11027 || strcmp (*l
, "pei-x86-64") == 0
11028 || strcmp (*l
, "mach-o-x86-64") == 0)
11030 default_arch
= "x86_64";
11034 as_fatal (_("no compiled in support for x86_64"));
11040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11044 const char **list
, **l
;
11046 list
= bfd_target_list ();
11047 for (l
= list
; *l
!= NULL
; l
++)
11048 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11050 default_arch
= "x86_64:32";
11054 as_fatal (_("no compiled in support for 32bit x86_64"));
11058 as_fatal (_("32bit x86_64 is only supported for ELF"));
11063 default_arch
= "i386";
11066 case OPTION_DIVIDE
:
11067 #ifdef SVR4_COMMENT_CHARS
11072 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11074 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11078 i386_comment_chars
= n
;
11084 saved
= xstrdup (arg
);
11086 /* Allow -march=+nosse. */
11092 as_fatal (_("invalid -march= option: `%s'"), arg
);
11093 next
= strchr (arch
, '+');
11096 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11098 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11101 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11104 cpu_arch_name
= cpu_arch
[j
].name
;
11105 cpu_sub_arch_name
= NULL
;
11106 cpu_arch_flags
= cpu_arch
[j
].flags
;
11107 cpu_arch_isa
= cpu_arch
[j
].type
;
11108 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11109 if (!cpu_arch_tune_set
)
11111 cpu_arch_tune
= cpu_arch_isa
;
11112 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11116 else if (*cpu_arch
[j
].name
== '.'
11117 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11119 /* ISA extension. */
11120 i386_cpu_flags flags
;
11122 flags
= cpu_flags_or (cpu_arch_flags
,
11123 cpu_arch
[j
].flags
);
11125 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11127 if (cpu_sub_arch_name
)
11129 char *name
= cpu_sub_arch_name
;
11130 cpu_sub_arch_name
= concat (name
,
11132 (const char *) NULL
);
11136 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11137 cpu_arch_flags
= flags
;
11138 cpu_arch_isa_flags
= flags
;
11142 = cpu_flags_or (cpu_arch_isa_flags
,
11143 cpu_arch
[j
].flags
);
11148 if (j
>= ARRAY_SIZE (cpu_arch
))
11150 /* Disable an ISA extension. */
11151 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11152 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11154 i386_cpu_flags flags
;
11156 flags
= cpu_flags_and_not (cpu_arch_flags
,
11157 cpu_noarch
[j
].flags
);
11158 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11160 if (cpu_sub_arch_name
)
11162 char *name
= cpu_sub_arch_name
;
11163 cpu_sub_arch_name
= concat (arch
,
11164 (const char *) NULL
);
11168 cpu_sub_arch_name
= xstrdup (arch
);
11169 cpu_arch_flags
= flags
;
11170 cpu_arch_isa_flags
= flags
;
11175 if (j
>= ARRAY_SIZE (cpu_noarch
))
11176 j
= ARRAY_SIZE (cpu_arch
);
11179 if (j
>= ARRAY_SIZE (cpu_arch
))
11180 as_fatal (_("invalid -march= option: `%s'"), arg
);
11184 while (next
!= NULL
);
11190 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11191 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11193 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11195 cpu_arch_tune_set
= 1;
11196 cpu_arch_tune
= cpu_arch
[j
].type
;
11197 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11201 if (j
>= ARRAY_SIZE (cpu_arch
))
11202 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11205 case OPTION_MMNEMONIC
:
11206 if (strcasecmp (arg
, "att") == 0)
11207 intel_mnemonic
= 0;
11208 else if (strcasecmp (arg
, "intel") == 0)
11209 intel_mnemonic
= 1;
11211 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11214 case OPTION_MSYNTAX
:
11215 if (strcasecmp (arg
, "att") == 0)
11217 else if (strcasecmp (arg
, "intel") == 0)
11220 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11223 case OPTION_MINDEX_REG
:
11224 allow_index_reg
= 1;
11227 case OPTION_MNAKED_REG
:
11228 allow_naked_reg
= 1;
11231 case OPTION_MSSE2AVX
:
11235 case OPTION_MSSE_CHECK
:
11236 if (strcasecmp (arg
, "error") == 0)
11237 sse_check
= check_error
;
11238 else if (strcasecmp (arg
, "warning") == 0)
11239 sse_check
= check_warning
;
11240 else if (strcasecmp (arg
, "none") == 0)
11241 sse_check
= check_none
;
11243 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11246 case OPTION_MOPERAND_CHECK
:
11247 if (strcasecmp (arg
, "error") == 0)
11248 operand_check
= check_error
;
11249 else if (strcasecmp (arg
, "warning") == 0)
11250 operand_check
= check_warning
;
11251 else if (strcasecmp (arg
, "none") == 0)
11252 operand_check
= check_none
;
11254 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11257 case OPTION_MAVXSCALAR
:
11258 if (strcasecmp (arg
, "128") == 0)
11259 avxscalar
= vex128
;
11260 else if (strcasecmp (arg
, "256") == 0)
11261 avxscalar
= vex256
;
11263 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11266 case OPTION_MVEXWIG
:
11267 if (strcmp (arg
, "0") == 0)
11269 else if (strcmp (arg
, "1") == 0)
11272 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11275 case OPTION_MADD_BND_PREFIX
:
11276 add_bnd_prefix
= 1;
11279 case OPTION_MEVEXLIG
:
11280 if (strcmp (arg
, "128") == 0)
11281 evexlig
= evexl128
;
11282 else if (strcmp (arg
, "256") == 0)
11283 evexlig
= evexl256
;
11284 else if (strcmp (arg
, "512") == 0)
11285 evexlig
= evexl512
;
11287 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11290 case OPTION_MEVEXRCIG
:
11291 if (strcmp (arg
, "rne") == 0)
11293 else if (strcmp (arg
, "rd") == 0)
11295 else if (strcmp (arg
, "ru") == 0)
11297 else if (strcmp (arg
, "rz") == 0)
11300 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11303 case OPTION_MEVEXWIG
:
11304 if (strcmp (arg
, "0") == 0)
11306 else if (strcmp (arg
, "1") == 0)
11309 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11312 # if defined (TE_PE) || defined (TE_PEP)
11313 case OPTION_MBIG_OBJ
:
11318 case OPTION_MOMIT_LOCK_PREFIX
:
11319 if (strcasecmp (arg
, "yes") == 0)
11320 omit_lock_prefix
= 1;
11321 else if (strcasecmp (arg
, "no") == 0)
11322 omit_lock_prefix
= 0;
11324 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11327 case OPTION_MFENCE_AS_LOCK_ADD
:
11328 if (strcasecmp (arg
, "yes") == 0)
11330 else if (strcasecmp (arg
, "no") == 0)
11333 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11336 case OPTION_MRELAX_RELOCATIONS
:
11337 if (strcasecmp (arg
, "yes") == 0)
11338 generate_relax_relocations
= 1;
11339 else if (strcasecmp (arg
, "no") == 0)
11340 generate_relax_relocations
= 0;
11342 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11345 case OPTION_MAMD64
:
11349 case OPTION_MINTEL64
:
11357 /* Turn off -Os. */
11358 optimize_for_space
= 0;
11360 else if (*arg
== 's')
11362 optimize_for_space
= 1;
11363 /* Turn on all encoding optimizations. */
11364 optimize
= INT_MAX
;
11368 optimize
= atoi (arg
);
11369 /* Turn off -Os. */
11370 optimize_for_space
= 0;
11380 #define MESSAGE_TEMPLATE \
11384 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11385 int *left_p
, const char *name
, int len
)
11387 int size
= sizeof (MESSAGE_TEMPLATE
);
11388 int left
= *left_p
;
11390 /* Reserve 2 spaces for ", " or ",\0" */
11393 /* Check if there is any room. */
11401 p
= mempcpy (p
, name
, len
);
11405 /* Output the current message now and start a new one. */
11408 fprintf (stream
, "%s\n", message
);
11410 left
= size
- (start
- message
) - len
- 2;
11412 gas_assert (left
>= 0);
11414 p
= mempcpy (p
, name
, len
);
11422 show_arch (FILE *stream
, int ext
, int check
)
11424 static char message
[] = MESSAGE_TEMPLATE
;
11425 char *start
= message
+ 27;
11427 int size
= sizeof (MESSAGE_TEMPLATE
);
11434 left
= size
- (start
- message
);
11435 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11437 /* Should it be skipped? */
11438 if (cpu_arch
[j
].skip
)
11441 name
= cpu_arch
[j
].name
;
11442 len
= cpu_arch
[j
].len
;
11445 /* It is an extension. Skip if we aren't asked to show it. */
11456 /* It is an processor. Skip if we show only extension. */
11459 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11461 /* It is an impossible processor - skip. */
11465 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11468 /* Display disabled extensions. */
11470 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11472 name
= cpu_noarch
[j
].name
;
11473 len
= cpu_noarch
[j
].len
;
11474 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11479 fprintf (stream
, "%s\n", message
);
11483 md_show_usage (FILE *stream
)
11485 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11486 fprintf (stream
, _("\
11488 -V print assembler version number\n\
11491 fprintf (stream
, _("\
11492 -n Do not optimize code alignment\n\
11493 -q quieten some warnings\n"));
11494 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11495 fprintf (stream
, _("\
11498 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11499 || defined (TE_PE) || defined (TE_PEP))
11500 fprintf (stream
, _("\
11501 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11503 #ifdef SVR4_COMMENT_CHARS
11504 fprintf (stream
, _("\
11505 --divide do not treat `/' as a comment character\n"));
11507 fprintf (stream
, _("\
11508 --divide ignored\n"));
11510 fprintf (stream
, _("\
11511 -march=CPU[,+EXTENSION...]\n\
11512 generate code for CPU and EXTENSION, CPU is one of:\n"));
11513 show_arch (stream
, 0, 1);
11514 fprintf (stream
, _("\
11515 EXTENSION is combination of:\n"));
11516 show_arch (stream
, 1, 0);
11517 fprintf (stream
, _("\
11518 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11519 show_arch (stream
, 0, 0);
11520 fprintf (stream
, _("\
11521 -msse2avx encode SSE instructions with VEX prefix\n"));
11522 fprintf (stream
, _("\
11523 -msse-check=[none|error|warning] (default: warning)\n\
11524 check SSE instructions\n"));
11525 fprintf (stream
, _("\
11526 -moperand-check=[none|error|warning] (default: warning)\n\
11527 check operand combinations for validity\n"));
11528 fprintf (stream
, _("\
11529 -mavxscalar=[128|256] (default: 128)\n\
11530 encode scalar AVX instructions with specific vector\n\
11532 fprintf (stream
, _("\
11533 -mvexwig=[0|1] (default: 0)\n\
11534 encode VEX instructions with specific VEX.W value\n\
11535 for VEX.W bit ignored instructions\n"));
11536 fprintf (stream
, _("\
11537 -mevexlig=[128|256|512] (default: 128)\n\
11538 encode scalar EVEX instructions with specific vector\n\
11540 fprintf (stream
, _("\
11541 -mevexwig=[0|1] (default: 0)\n\
11542 encode EVEX instructions with specific EVEX.W value\n\
11543 for EVEX.W bit ignored instructions\n"));
11544 fprintf (stream
, _("\
11545 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11546 encode EVEX instructions with specific EVEX.RC value\n\
11547 for SAE-only ignored instructions\n"));
11548 fprintf (stream
, _("\
11549 -mmnemonic=[att|intel] "));
11550 if (SYSV386_COMPAT
)
11551 fprintf (stream
, _("(default: att)\n"));
11553 fprintf (stream
, _("(default: intel)\n"));
11554 fprintf (stream
, _("\
11555 use AT&T/Intel mnemonic\n"));
11556 fprintf (stream
, _("\
11557 -msyntax=[att|intel] (default: att)\n\
11558 use AT&T/Intel syntax\n"));
11559 fprintf (stream
, _("\
11560 -mindex-reg support pseudo index registers\n"));
11561 fprintf (stream
, _("\
11562 -mnaked-reg don't require `%%' prefix for registers\n"));
11563 fprintf (stream
, _("\
11564 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11566 fprintf (stream
, _("\
11567 -mshared disable branch optimization for shared code\n"));
11568 fprintf (stream
, _("\
11569 -mx86-used-note=[no|yes] "));
11570 if (DEFAULT_X86_USED_NOTE
)
11571 fprintf (stream
, _("(default: yes)\n"));
11573 fprintf (stream
, _("(default: no)\n"));
11574 fprintf (stream
, _("\
11575 generate x86 used ISA and feature properties\n"));
11577 #if defined (TE_PE) || defined (TE_PEP)
11578 fprintf (stream
, _("\
11579 -mbig-obj generate big object files\n"));
11581 fprintf (stream
, _("\
11582 -momit-lock-prefix=[no|yes] (default: no)\n\
11583 strip all lock prefixes\n"));
11584 fprintf (stream
, _("\
11585 -mfence-as-lock-add=[no|yes] (default: no)\n\
11586 encode lfence, mfence and sfence as\n\
11587 lock addl $0x0, (%%{re}sp)\n"));
11588 fprintf (stream
, _("\
11589 -mrelax-relocations=[no|yes] "));
11590 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11591 fprintf (stream
, _("(default: yes)\n"));
11593 fprintf (stream
, _("(default: no)\n"));
11594 fprintf (stream
, _("\
11595 generate relax relocations\n"));
11596 fprintf (stream
, _("\
11597 -mamd64 accept only AMD64 ISA [default]\n"));
11598 fprintf (stream
, _("\
11599 -mintel64 accept only Intel64 ISA\n"));
11602 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11603 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11604 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11606 /* Pick the target format to use. */
11609 i386_target_format (void)
11611 if (!strncmp (default_arch
, "x86_64", 6))
11613 update_code_flag (CODE_64BIT
, 1);
11614 if (default_arch
[6] == '\0')
11615 x86_elf_abi
= X86_64_ABI
;
11617 x86_elf_abi
= X86_64_X32_ABI
;
11619 else if (!strcmp (default_arch
, "i386"))
11620 update_code_flag (CODE_32BIT
, 1);
11621 else if (!strcmp (default_arch
, "iamcu"))
11623 update_code_flag (CODE_32BIT
, 1);
11624 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11626 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11627 cpu_arch_name
= "iamcu";
11628 cpu_sub_arch_name
= NULL
;
11629 cpu_arch_flags
= iamcu_flags
;
11630 cpu_arch_isa
= PROCESSOR_IAMCU
;
11631 cpu_arch_isa_flags
= iamcu_flags
;
11632 if (!cpu_arch_tune_set
)
11634 cpu_arch_tune
= cpu_arch_isa
;
11635 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11638 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11639 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11643 as_fatal (_("unknown architecture"));
11645 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11646 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11647 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11648 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11650 switch (OUTPUT_FLAVOR
)
11652 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11653 case bfd_target_aout_flavour
:
11654 return AOUT_TARGET_FORMAT
;
11656 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11657 # if defined (TE_PE) || defined (TE_PEP)
11658 case bfd_target_coff_flavour
:
11659 if (flag_code
== CODE_64BIT
)
11660 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11663 # elif defined (TE_GO32)
11664 case bfd_target_coff_flavour
:
11665 return "coff-go32";
11667 case bfd_target_coff_flavour
:
11668 return "coff-i386";
11671 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11672 case bfd_target_elf_flavour
:
11674 const char *format
;
11676 switch (x86_elf_abi
)
11679 format
= ELF_TARGET_FORMAT
;
11682 use_rela_relocations
= 1;
11684 format
= ELF_TARGET_FORMAT64
;
11686 case X86_64_X32_ABI
:
11687 use_rela_relocations
= 1;
11689 disallow_64bit_reloc
= 1;
11690 format
= ELF_TARGET_FORMAT32
;
11693 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11695 if (x86_elf_abi
!= X86_64_ABI
)
11696 as_fatal (_("Intel L1OM is 64bit only"));
11697 return ELF_TARGET_L1OM_FORMAT
;
11699 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11701 if (x86_elf_abi
!= X86_64_ABI
)
11702 as_fatal (_("Intel K1OM is 64bit only"));
11703 return ELF_TARGET_K1OM_FORMAT
;
11705 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11707 if (x86_elf_abi
!= I386_ABI
)
11708 as_fatal (_("Intel MCU is 32bit only"));
11709 return ELF_TARGET_IAMCU_FORMAT
;
11715 #if defined (OBJ_MACH_O)
11716 case bfd_target_mach_o_flavour
:
11717 if (flag_code
== CODE_64BIT
)
11719 use_rela_relocations
= 1;
11721 return "mach-o-x86-64";
11724 return "mach-o-i386";
11732 #endif /* OBJ_MAYBE_ more than one */
11735 md_undefined_symbol (char *name
)
11737 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11738 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11739 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11740 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11744 if (symbol_find (name
))
11745 as_bad (_("GOT already in symbol table"));
11746 GOT_symbol
= symbol_new (name
, undefined_section
,
11747 (valueT
) 0, &zero_address_frag
);
11754 /* Round up a section size to the appropriate boundary. */
11757 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11759 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11760 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11762 /* For a.out, force the section size to be aligned. If we don't do
11763 this, BFD will align it for us, but it will not write out the
11764 final bytes of the section. This may be a bug in BFD, but it is
11765 easier to fix it here since that is how the other a.out targets
11769 align
= bfd_get_section_alignment (stdoutput
, segment
);
11770 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11777 /* On the i386, PC-relative offsets are relative to the start of the
11778 next instruction. That is, the address of the offset, plus its
11779 size, since the offset is always the last part of the insn. */
11782 md_pcrel_from (fixS
*fixP
)
11784 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11790 s_bss (int ignore ATTRIBUTE_UNUSED
)
11794 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11796 obj_elf_section_change_hook ();
11798 temp
= get_absolute_expression ();
11799 subseg_set (bss_section
, (subsegT
) temp
);
11800 demand_empty_rest_of_line ();
11806 i386_validate_fix (fixS
*fixp
)
11808 if (fixp
->fx_subsy
)
11810 if (fixp
->fx_subsy
== GOT_symbol
)
11812 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11817 if (fixp
->fx_tcbit2
)
11818 fixp
->fx_r_type
= (fixp
->fx_tcbit
11819 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11820 : BFD_RELOC_X86_64_GOTPCRELX
);
11823 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11828 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11830 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11832 fixp
->fx_subsy
= 0;
11835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11836 else if (!object_64bit
)
11838 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11839 && fixp
->fx_tcbit2
)
11840 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11846 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11849 bfd_reloc_code_real_type code
;
11851 switch (fixp
->fx_r_type
)
11853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11854 case BFD_RELOC_SIZE32
:
11855 case BFD_RELOC_SIZE64
:
11856 if (S_IS_DEFINED (fixp
->fx_addsy
)
11857 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11859 /* Resolve size relocation against local symbol to size of
11860 the symbol plus addend. */
11861 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11862 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11863 && !fits_in_unsigned_long (value
))
11864 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11865 _("symbol size computation overflow"));
11866 fixp
->fx_addsy
= NULL
;
11867 fixp
->fx_subsy
= NULL
;
11868 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11872 /* Fall through. */
11874 case BFD_RELOC_X86_64_PLT32
:
11875 case BFD_RELOC_X86_64_GOT32
:
11876 case BFD_RELOC_X86_64_GOTPCREL
:
11877 case BFD_RELOC_X86_64_GOTPCRELX
:
11878 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11879 case BFD_RELOC_386_PLT32
:
11880 case BFD_RELOC_386_GOT32
:
11881 case BFD_RELOC_386_GOT32X
:
11882 case BFD_RELOC_386_GOTOFF
:
11883 case BFD_RELOC_386_GOTPC
:
11884 case BFD_RELOC_386_TLS_GD
:
11885 case BFD_RELOC_386_TLS_LDM
:
11886 case BFD_RELOC_386_TLS_LDO_32
:
11887 case BFD_RELOC_386_TLS_IE_32
:
11888 case BFD_RELOC_386_TLS_IE
:
11889 case BFD_RELOC_386_TLS_GOTIE
:
11890 case BFD_RELOC_386_TLS_LE_32
:
11891 case BFD_RELOC_386_TLS_LE
:
11892 case BFD_RELOC_386_TLS_GOTDESC
:
11893 case BFD_RELOC_386_TLS_DESC_CALL
:
11894 case BFD_RELOC_X86_64_TLSGD
:
11895 case BFD_RELOC_X86_64_TLSLD
:
11896 case BFD_RELOC_X86_64_DTPOFF32
:
11897 case BFD_RELOC_X86_64_DTPOFF64
:
11898 case BFD_RELOC_X86_64_GOTTPOFF
:
11899 case BFD_RELOC_X86_64_TPOFF32
:
11900 case BFD_RELOC_X86_64_TPOFF64
:
11901 case BFD_RELOC_X86_64_GOTOFF64
:
11902 case BFD_RELOC_X86_64_GOTPC32
:
11903 case BFD_RELOC_X86_64_GOT64
:
11904 case BFD_RELOC_X86_64_GOTPCREL64
:
11905 case BFD_RELOC_X86_64_GOTPC64
:
11906 case BFD_RELOC_X86_64_GOTPLT64
:
11907 case BFD_RELOC_X86_64_PLTOFF64
:
11908 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11909 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11910 case BFD_RELOC_RVA
:
11911 case BFD_RELOC_VTABLE_ENTRY
:
11912 case BFD_RELOC_VTABLE_INHERIT
:
11914 case BFD_RELOC_32_SECREL
:
11916 code
= fixp
->fx_r_type
;
11918 case BFD_RELOC_X86_64_32S
:
11919 if (!fixp
->fx_pcrel
)
11921 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11922 code
= fixp
->fx_r_type
;
11925 /* Fall through. */
11927 if (fixp
->fx_pcrel
)
11929 switch (fixp
->fx_size
)
11932 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11933 _("can not do %d byte pc-relative relocation"),
11935 code
= BFD_RELOC_32_PCREL
;
11937 case 1: code
= BFD_RELOC_8_PCREL
; break;
11938 case 2: code
= BFD_RELOC_16_PCREL
; break;
11939 case 4: code
= BFD_RELOC_32_PCREL
; break;
11941 case 8: code
= BFD_RELOC_64_PCREL
; break;
11947 switch (fixp
->fx_size
)
11950 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11951 _("can not do %d byte relocation"),
11953 code
= BFD_RELOC_32
;
11955 case 1: code
= BFD_RELOC_8
; break;
11956 case 2: code
= BFD_RELOC_16
; break;
11957 case 4: code
= BFD_RELOC_32
; break;
11959 case 8: code
= BFD_RELOC_64
; break;
11966 if ((code
== BFD_RELOC_32
11967 || code
== BFD_RELOC_32_PCREL
11968 || code
== BFD_RELOC_X86_64_32S
)
11970 && fixp
->fx_addsy
== GOT_symbol
)
11973 code
= BFD_RELOC_386_GOTPC
;
11975 code
= BFD_RELOC_X86_64_GOTPC32
;
11977 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11979 && fixp
->fx_addsy
== GOT_symbol
)
11981 code
= BFD_RELOC_X86_64_GOTPC64
;
11984 rel
= XNEW (arelent
);
11985 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11986 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11988 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11990 if (!use_rela_relocations
)
11992 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11993 vtable entry to be used in the relocation's section offset. */
11994 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11995 rel
->address
= fixp
->fx_offset
;
11996 #if defined (OBJ_COFF) && defined (TE_PE)
11997 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11998 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12003 /* Use the rela in 64bit mode. */
12006 if (disallow_64bit_reloc
)
12009 case BFD_RELOC_X86_64_DTPOFF64
:
12010 case BFD_RELOC_X86_64_TPOFF64
:
12011 case BFD_RELOC_64_PCREL
:
12012 case BFD_RELOC_X86_64_GOTOFF64
:
12013 case BFD_RELOC_X86_64_GOT64
:
12014 case BFD_RELOC_X86_64_GOTPCREL64
:
12015 case BFD_RELOC_X86_64_GOTPC64
:
12016 case BFD_RELOC_X86_64_GOTPLT64
:
12017 case BFD_RELOC_X86_64_PLTOFF64
:
12018 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12019 _("cannot represent relocation type %s in x32 mode"),
12020 bfd_get_reloc_code_name (code
));
12026 if (!fixp
->fx_pcrel
)
12027 rel
->addend
= fixp
->fx_offset
;
12031 case BFD_RELOC_X86_64_PLT32
:
12032 case BFD_RELOC_X86_64_GOT32
:
12033 case BFD_RELOC_X86_64_GOTPCREL
:
12034 case BFD_RELOC_X86_64_GOTPCRELX
:
12035 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12036 case BFD_RELOC_X86_64_TLSGD
:
12037 case BFD_RELOC_X86_64_TLSLD
:
12038 case BFD_RELOC_X86_64_GOTTPOFF
:
12039 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12040 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12041 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12044 rel
->addend
= (section
->vma
12046 + fixp
->fx_addnumber
12047 + md_pcrel_from (fixp
));
12052 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12053 if (rel
->howto
== NULL
)
12055 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12056 _("cannot represent relocation type %s"),
12057 bfd_get_reloc_code_name (code
));
12058 /* Set howto to a garbage value so that we can keep going. */
12059 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12060 gas_assert (rel
->howto
!= NULL
);
12066 #include "tc-i386-intel.c"
12069 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12071 int saved_naked_reg
;
12072 char saved_register_dot
;
12074 saved_naked_reg
= allow_naked_reg
;
12075 allow_naked_reg
= 1;
12076 saved_register_dot
= register_chars
['.'];
12077 register_chars
['.'] = '.';
12078 allow_pseudo_reg
= 1;
12079 expression_and_evaluate (exp
);
12080 allow_pseudo_reg
= 0;
12081 register_chars
['.'] = saved_register_dot
;
12082 allow_naked_reg
= saved_naked_reg
;
12084 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12086 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12088 exp
->X_op
= O_constant
;
12089 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12090 .dw2_regnum
[flag_code
>> 1];
12093 exp
->X_op
= O_illegal
;
12098 tc_x86_frame_initial_instructions (void)
12100 static unsigned int sp_regno
[2];
12102 if (!sp_regno
[flag_code
>> 1])
12104 char *saved_input
= input_line_pointer
;
12105 char sp
[][4] = {"esp", "rsp"};
12108 input_line_pointer
= sp
[flag_code
>> 1];
12109 tc_x86_parse_to_dw2regnum (&exp
);
12110 gas_assert (exp
.X_op
== O_constant
);
12111 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12112 input_line_pointer
= saved_input
;
12115 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12116 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12120 x86_dwarf2_addr_size (void)
12122 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12123 if (x86_elf_abi
== X86_64_X32_ABI
)
12126 return bfd_arch_bits_per_address (stdoutput
) / 8;
12130 i386_elf_section_type (const char *str
, size_t len
)
12132 if (flag_code
== CODE_64BIT
12133 && len
== sizeof ("unwind") - 1
12134 && strncmp (str
, "unwind", 6) == 0)
12135 return SHT_X86_64_UNWIND
;
12142 i386_solaris_fix_up_eh_frame (segT sec
)
12144 if (flag_code
== CODE_64BIT
)
12145 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12151 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12155 exp
.X_op
= O_secrel
;
12156 exp
.X_add_symbol
= symbol
;
12157 exp
.X_add_number
= 0;
12158 emit_expr (&exp
, size
);
12162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12163 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12166 x86_64_section_letter (int letter
, const char **ptr_msg
)
12168 if (flag_code
== CODE_64BIT
)
12171 return SHF_X86_64_LARGE
;
12173 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12176 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12181 x86_64_section_word (char *str
, size_t len
)
12183 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12184 return SHF_X86_64_LARGE
;
12190 handle_large_common (int small ATTRIBUTE_UNUSED
)
12192 if (flag_code
!= CODE_64BIT
)
12194 s_comm_internal (0, elf_common_parse
);
12195 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12199 static segT lbss_section
;
12200 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12201 asection
*saved_bss_section
= bss_section
;
12203 if (lbss_section
== NULL
)
12205 flagword applicable
;
12206 segT seg
= now_seg
;
12207 subsegT subseg
= now_subseg
;
12209 /* The .lbss section is for local .largecomm symbols. */
12210 lbss_section
= subseg_new (".lbss", 0);
12211 applicable
= bfd_applicable_section_flags (stdoutput
);
12212 bfd_set_section_flags (stdoutput
, lbss_section
,
12213 applicable
& SEC_ALLOC
);
12214 seg_info (lbss_section
)->bss
= 1;
12216 subseg_set (seg
, subseg
);
12219 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12220 bss_section
= lbss_section
;
12222 s_comm_internal (0, elf_common_parse
);
12224 elf_com_section_ptr
= saved_com_section_ptr
;
12225 bss_section
= saved_bss_section
;
12228 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */