1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
73 #define RELOC_ENUM enum bfd_reloc_code_real
75 #define RELOC_ENUM int
79 #define DEFAULT_ARCH "i386"
81 static char *default_arch
= DEFAULT_ARCH
;
83 /* 'md_assemble ()' gathers together information and puts it into a
90 const reg_entry
*regs
;
95 /* TM holds the template for the insn were currently assembling. */
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands
;
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
108 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types
[MAX_OPERANDS
];
114 /* Displacement expression, immediate expression, or register for each
116 union i386_op op
[MAX_OPERANDS
];
118 /* Flags for operands. */
119 unsigned int flags
[MAX_OPERANDS
];
120 #define Operand_PCrel 1
122 /* Relocation type for operand */
123 RELOC_ENUM reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
243 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 0
289 #define COND_JUMP86 2
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will have in the variable part of the frag
327 4) which index into the table to try if we can't fit into this one. */
329 /* UNCOND_JUMP states. */
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
331 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
332 /* dword jmp adds 4 bytes to frag:
333 0 extra opcode bytes, 4 displacement bytes. */
335 /* word jmp adds 2 byte2 to frag:
336 0 extra opcode bytes, 2 displacement bytes. */
339 /* COND_JUMP states. */
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
341 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
342 /* dword conditionals adds 5 bytes to frag:
343 1 extra opcode byte, 4 displacement bytes. */
345 /* word conditionals add 3 bytes to frag:
346 1 extra opcode byte, 2 displacement bytes. */
349 /* COND_JUMP86 states. */
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
351 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
352 /* dword conditionals adds 5 bytes to frag:
353 1 extra opcode byte, 4 displacement bytes. */
355 /* word conditionals add 4 bytes to frag:
356 1 displacement byte and a 3 byte long branch insn. */
360 static const arch_entry cpu_arch
[] = {
362 {"i186", Cpu086
|Cpu186
},
363 {"i286", Cpu086
|Cpu186
|Cpu286
},
364 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
365 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
366 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
367 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
368 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
369 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
370 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
371 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
372 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
373 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
378 i386_align_code (fragP
, count
)
382 /* Various efficient no-op patterns for aligning code labels.
383 Note: Don't try to assemble the instructions in the comments.
384 0L and 0w are not legal. */
385 static const char f32_1
[] =
387 static const char f32_2
[] =
388 {0x89,0xf6}; /* movl %esi,%esi */
389 static const char f32_3
[] =
390 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
391 static const char f32_4
[] =
392 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
393 static const char f32_5
[] =
395 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_6
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
398 static const char f32_7
[] =
399 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
400 static const char f32_8
[] =
402 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_9
[] =
404 {0x89,0xf6, /* movl %esi,%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_10
[] =
407 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_11
[] =
410 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_12
[] =
413 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
414 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
415 static const char f32_13
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
418 static const char f32_14
[] =
419 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_15
[] =
422 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
423 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
424 static const char f16_3
[] =
425 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
426 static const char f16_4
[] =
427 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
428 static const char f16_5
[] =
430 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_6
[] =
432 {0x89,0xf6, /* mov %si,%si */
433 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
434 static const char f16_7
[] =
435 {0x8d,0x74,0x00, /* lea 0(%si),%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_8
[] =
438 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char *const f32_patt
[] = {
441 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
442 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
444 static const char *const f16_patt
[] = {
445 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
446 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
449 /* ??? We can't use these fillers for x86_64, since they often kills the
450 upper halves. Solve later. */
451 if (flag_code
== CODE_64BIT
)
454 if (count
> 0 && count
<= 15)
456 if (flag_code
== CODE_16BIT
)
458 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
459 f16_patt
[count
- 1], count
);
461 /* Adjust jump offset. */
462 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
465 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
466 f32_patt
[count
- 1], count
);
467 fragP
->fr_var
= count
;
471 static char *output_invalid
PARAMS ((int c
));
472 static int i386_operand
PARAMS ((char *operand_string
));
473 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
474 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
478 static void s_bss
PARAMS ((int));
481 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
483 static INLINE
unsigned int
484 mode_from_disp_size (t
)
487 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
491 fits_in_signed_byte (num
)
494 return (num
>= -128) && (num
<= 127);
498 fits_in_unsigned_byte (num
)
501 return (num
& 0xff) == num
;
505 fits_in_unsigned_word (num
)
508 return (num
& 0xffff) == num
;
512 fits_in_signed_word (num
)
515 return (-32768 <= num
) && (num
<= 32767);
518 fits_in_signed_long (num
)
519 offsetT num ATTRIBUTE_UNUSED
;
524 return (!(((offsetT
) -1 << 31) & num
)
525 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
527 } /* fits_in_signed_long() */
529 fits_in_unsigned_long (num
)
530 offsetT num ATTRIBUTE_UNUSED
;
535 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
537 } /* fits_in_unsigned_long() */
540 smallest_imm_type (num
)
543 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
544 && !(cpu_arch_flags
& (CpuUnknown
)))
546 /* This code is disabled on the 486 because all the Imm1 forms
547 in the opcode table are slower on the i486. They're the
548 versions with the implicitly specified single-position
549 displacement, which has another syntax if you really want to
552 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
554 return (fits_in_signed_byte (num
)
555 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
556 : fits_in_unsigned_byte (num
)
557 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
558 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
559 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_signed_long (num
)
561 ? (Imm32
| Imm32S
| Imm64
)
562 : fits_in_unsigned_long (num
)
568 offset_in_range (val
, size
)
576 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
577 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
578 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
580 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
585 /* If BFD64, sign extend val. */
586 if (!use_rela_relocations
)
587 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
588 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
590 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
592 char buf1
[40], buf2
[40];
594 sprint_value (buf1
, val
);
595 sprint_value (buf2
, val
& mask
);
596 as_warn (_("%s shortened to %s"), buf1
, buf2
);
601 /* Returns 0 if attempting to add a prefix where one from the same
602 class already exists, 1 if non rep/repne added, 2 if rep/repne
611 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
619 case CS_PREFIX_OPCODE
:
620 case DS_PREFIX_OPCODE
:
621 case ES_PREFIX_OPCODE
:
622 case FS_PREFIX_OPCODE
:
623 case GS_PREFIX_OPCODE
:
624 case SS_PREFIX_OPCODE
:
628 case REPNE_PREFIX_OPCODE
:
629 case REPE_PREFIX_OPCODE
:
632 case LOCK_PREFIX_OPCODE
:
640 case ADDR_PREFIX_OPCODE
:
644 case DATA_PREFIX_OPCODE
:
651 as_bad (_("same type of prefix used twice"));
656 i
.prefix
[q
] = prefix
;
661 set_code_flag (value
)
665 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
666 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
667 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
669 as_bad (_("64bit mode not supported on this CPU."));
671 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
673 as_bad (_("32bit mode not supported on this CPU."));
679 set_16bit_gcc_code_flag (new_code_flag
)
682 flag_code
= new_code_flag
;
683 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
684 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
689 set_intel_syntax (syntax_flag
)
692 /* Find out if register prefixing is specified. */
693 int ask_naked_reg
= 0;
696 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
698 char *string
= input_line_pointer
;
699 int e
= get_symbol_end ();
701 if (strcmp (string
, "prefix") == 0)
703 else if (strcmp (string
, "noprefix") == 0)
706 as_bad (_("bad argument to syntax directive."));
707 *input_line_pointer
= e
;
709 demand_empty_rest_of_line ();
711 intel_syntax
= syntax_flag
;
713 if (ask_naked_reg
== 0)
716 allow_naked_reg
= (intel_syntax
717 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
719 /* Conservative default. */
724 allow_naked_reg
= (ask_naked_reg
< 0);
729 int dummy ATTRIBUTE_UNUSED
;
733 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
735 char *string
= input_line_pointer
;
736 int e
= get_symbol_end ();
739 for (i
= 0; cpu_arch
[i
].name
; i
++)
741 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
743 cpu_arch_name
= cpu_arch
[i
].name
;
744 cpu_arch_flags
= (cpu_arch
[i
].flags
745 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
749 if (!cpu_arch
[i
].name
)
750 as_bad (_("no such architecture: `%s'"), string
);
752 *input_line_pointer
= e
;
755 as_bad (_("missing cpu architecture"));
757 no_cond_jump_promotion
= 0;
758 if (*input_line_pointer
== ','
759 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
761 char *string
= ++input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "nojumps") == 0)
765 no_cond_jump_promotion
= 1;
766 else if (strcmp (string
, "jumps") == 0)
769 as_bad (_("no such architecture modifier: `%s'"), string
);
771 *input_line_pointer
= e
;
774 demand_empty_rest_of_line ();
777 const pseudo_typeS md_pseudo_table
[] =
779 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
780 {"align", s_align_bytes
, 0},
782 {"align", s_align_ptwo
, 0},
784 {"arch", set_cpu_arch
, 0},
788 {"ffloat", float_cons
, 'f'},
789 {"dfloat", float_cons
, 'd'},
790 {"tfloat", float_cons
, 'x'},
792 {"noopt", s_ignore
, 0},
793 {"optim", s_ignore
, 0},
794 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
795 {"code16", set_code_flag
, CODE_16BIT
},
796 {"code32", set_code_flag
, CODE_32BIT
},
797 {"code64", set_code_flag
, CODE_64BIT
},
798 {"intel_syntax", set_intel_syntax
, 1},
799 {"att_syntax", set_intel_syntax
, 0},
800 {"file", dwarf2_directive_file
, 0},
801 {"loc", dwarf2_directive_loc
, 0},
805 /* For interface with expression (). */
806 extern char *input_line_pointer
;
808 /* Hash table for instruction mnemonic lookup. */
809 static struct hash_control
*op_hash
;
811 /* Hash table for register lookup. */
812 static struct hash_control
*reg_hash
;
818 if (!strcmp (default_arch
, "x86_64"))
819 return bfd_mach_x86_64
;
820 else if (!strcmp (default_arch
, "i386"))
821 return bfd_mach_i386_i386
;
823 as_fatal (_("Unknown architecture"));
830 const char *hash_err
;
832 /* Initialize op_hash hash table. */
833 op_hash
= hash_new ();
836 register const template *optab
;
837 register templates
*core_optab
;
839 /* Setup for loop. */
841 core_optab
= (templates
*) xmalloc (sizeof (templates
));
842 core_optab
->start
= optab
;
847 if (optab
->name
== NULL
848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
850 /* different name --> ship out current template list;
851 add to hash table; & begin anew. */
852 core_optab
->end
= optab
;
853 hash_err
= hash_insert (op_hash
,
858 as_fatal (_("Internal Error: Can't hash %s: %s"),
862 if (optab
->name
== NULL
)
864 core_optab
= (templates
*) xmalloc (sizeof (templates
));
865 core_optab
->start
= optab
;
870 /* Initialize reg_hash hash table. */
871 reg_hash
= hash_new ();
873 register const reg_entry
*regtab
;
875 for (regtab
= i386_regtab
;
876 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
879 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
881 as_fatal (_("Internal Error: Can't hash %s: %s"),
887 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 for (c
= 0; c
< 256; c
++)
897 mnemonic_chars
[c
] = c
;
898 register_chars
[c
] = c
;
899 operand_chars
[c
] = c
;
901 else if (islower (c
))
903 mnemonic_chars
[c
] = c
;
904 register_chars
[c
] = c
;
905 operand_chars
[c
] = c
;
907 else if (isupper (c
))
909 mnemonic_chars
[c
] = tolower (c
);
910 register_chars
[c
] = mnemonic_chars
[c
];
911 operand_chars
[c
] = c
;
914 if (isalpha (c
) || isdigit (c
))
915 identifier_chars
[c
] = c
;
918 identifier_chars
[c
] = c
;
919 operand_chars
[c
] = c
;
924 identifier_chars
['@'] = '@';
926 digit_chars
['-'] = '-';
927 identifier_chars
['_'] = '_';
928 identifier_chars
['.'] = '.';
930 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
931 operand_chars
[(unsigned char) *p
] = *p
;
934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
935 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
937 record_alignment (text_section
, 2);
938 record_alignment (data_section
, 2);
939 record_alignment (bss_section
, 2);
945 i386_print_statistics (file
)
948 hash_print_statistics (file
, "i386 opcode", op_hash
);
949 hash_print_statistics (file
, "i386 register", reg_hash
);
954 /* Debugging routines for md_assemble. */
955 static void pi
PARAMS ((char *, i386_insn
*));
956 static void pte
PARAMS ((template *));
957 static void pt
PARAMS ((unsigned int));
958 static void pe
PARAMS ((expressionS
*));
959 static void ps
PARAMS ((symbolS
*));
968 fprintf (stdout
, "%s: template ", line
);
970 fprintf (stdout
, " address: base %s index %s scale %x\n",
971 x
->base_reg
? x
->base_reg
->reg_name
: "none",
972 x
->index_reg
? x
->index_reg
->reg_name
: "none",
973 x
->log2_scale_factor
);
974 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
975 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
976 fprintf (stdout
, " sib: base %x index %x scale %x\n",
977 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
978 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
979 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
980 for (i
= 0; i
< x
->operands
; i
++)
982 fprintf (stdout
, " #%d: ", i
+ 1);
984 fprintf (stdout
, "\n");
986 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
987 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
988 if (x
->types
[i
] & Imm
)
990 if (x
->types
[i
] & Disp
)
1000 fprintf (stdout
, " %d operands ", t
->operands
);
1001 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1002 if (t
->extension_opcode
!= None
)
1003 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1004 if (t
->opcode_modifier
& D
)
1005 fprintf (stdout
, "D");
1006 if (t
->opcode_modifier
& W
)
1007 fprintf (stdout
, "W");
1008 fprintf (stdout
, "\n");
1009 for (i
= 0; i
< t
->operands
; i
++)
1011 fprintf (stdout
, " #%d type ", i
+ 1);
1012 pt (t
->operand_types
[i
]);
1013 fprintf (stdout
, "\n");
1021 fprintf (stdout
, " operation %d\n", e
->X_op
);
1022 fprintf (stdout
, " add_number %ld (%lx)\n",
1023 (long) e
->X_add_number
, (long) e
->X_add_number
);
1024 if (e
->X_add_symbol
)
1026 fprintf (stdout
, " add_symbol ");
1027 ps (e
->X_add_symbol
);
1028 fprintf (stdout
, "\n");
1032 fprintf (stdout
, " op_symbol ");
1033 ps (e
->X_op_symbol
);
1034 fprintf (stdout
, "\n");
1042 fprintf (stdout
, "%s type %s%s",
1044 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1045 segment_name (S_GET_SEGMENT (s
)));
1067 { BaseIndex
, "BaseIndex" },
1071 { Disp32S
, "d32s" },
1073 { InOutPortReg
, "InOutPortReg" },
1074 { ShiftCount
, "ShiftCount" },
1075 { Control
, "control reg" },
1076 { Test
, "test reg" },
1077 { Debug
, "debug reg" },
1078 { FloatReg
, "FReg" },
1079 { FloatAcc
, "FAcc" },
1083 { JumpAbsolute
, "Jump Absolute" },
1094 register struct type_name
*ty
;
1096 for (ty
= type_names
; ty
->mask
; ty
++)
1098 fprintf (stdout
, "%s, ", ty
->tname
);
1102 #endif /* DEBUG386 */
1105 tc_i386_force_relocation (fixp
)
1108 #ifdef BFD_ASSEMBLER
1109 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1110 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1115 return fixp
->fx_r_type
== 7;
1119 #ifdef BFD_ASSEMBLER
1121 static bfd_reloc_code_real_type
1122 reloc (size
, pcrel
, sign
, other
)
1126 bfd_reloc_code_real_type other
;
1128 if (other
!= NO_RELOC
)
1134 as_bad (_("There are no unsigned pc-relative relocations"));
1137 case 1: return BFD_RELOC_8_PCREL
;
1138 case 2: return BFD_RELOC_16_PCREL
;
1139 case 4: return BFD_RELOC_32_PCREL
;
1141 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1148 case 4: return BFD_RELOC_X86_64_32S
;
1153 case 1: return BFD_RELOC_8
;
1154 case 2: return BFD_RELOC_16
;
1155 case 4: return BFD_RELOC_32
;
1156 case 8: return BFD_RELOC_64
;
1158 as_bad (_("can not do %s %d byte relocation"),
1159 sign
? "signed" : "unsigned", size
);
1163 return BFD_RELOC_NONE
;
1166 /* Here we decide which fixups can be adjusted to make them relative to
1167 the beginning of the section instead of the symbol. Basically we need
1168 to make sure that the dynamic relocations are done correctly, so in
1169 some cases we force the original symbol to be used. */
1172 tc_i386_fix_adjustable (fixP
)
1175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1176 /* Prevent all adjustments to global symbols, or else dynamic
1177 linking will not work correctly. */
1178 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1179 || S_IS_WEAK (fixP
->fx_addsy
))
1182 /* adjust_reloc_syms doesn't know about the GOT. */
1183 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1184 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1185 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1188 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1190 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1195 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1196 #define BFD_RELOC_16 0
1197 #define BFD_RELOC_32 0
1198 #define BFD_RELOC_16_PCREL 0
1199 #define BFD_RELOC_32_PCREL 0
1200 #define BFD_RELOC_386_PLT32 0
1201 #define BFD_RELOC_386_GOT32 0
1202 #define BFD_RELOC_386_GOTOFF 0
1203 #define BFD_RELOC_X86_64_PLT32 0
1204 #define BFD_RELOC_X86_64_GOT32 0
1205 #define BFD_RELOC_X86_64_GOTPCREL 0
1208 static int intel_float_operand
PARAMS ((char *mnemonic
));
1211 intel_float_operand (mnemonic
)
1214 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1217 if (mnemonic
[0] == 'f')
1223 /* This is the guts of the machine-dependent assembler. LINE points to a
1224 machine dependent instruction. This function is supposed to emit
1225 the frags/bytes it assembles to. */
1231 /* Points to template once we've found it. */
1236 char mnemonic
[MAX_MNEM_SIZE
];
1238 /* Initialize globals. */
1239 memset (&i
, '\0', sizeof (i
));
1240 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1241 i
.reloc
[j
] = NO_RELOC
;
1242 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1243 memset (im_expressions
, '\0', sizeof (im_expressions
));
1244 save_stack_p
= save_stack
;
1246 /* First parse an instruction mnemonic & call i386_operand for the operands.
1247 We assume that the scrubber has arranged it so that line[0] is the valid
1248 start of a (possibly prefixed) mnemonic. */
1251 char *token_start
= l
;
1254 /* Non-zero if we found a prefix only acceptable with string insns. */
1255 const char *expecting_string_instruction
= NULL
;
1260 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1263 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1265 as_bad (_("no such instruction: `%s'"), token_start
);
1270 if (!is_space_char (*l
)
1271 && *l
!= END_OF_INSN
1272 && *l
!= PREFIX_SEPARATOR
)
1274 as_bad (_("invalid character %s in mnemonic"),
1275 output_invalid (*l
));
1278 if (token_start
== l
)
1280 if (*l
== PREFIX_SEPARATOR
)
1281 as_bad (_("expecting prefix; got nothing"));
1283 as_bad (_("expecting mnemonic; got nothing"));
1287 /* Look up instruction (or prefix) via hash table. */
1288 current_templates
= hash_find (op_hash
, mnemonic
);
1290 if (*l
!= END_OF_INSN
1291 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1292 && current_templates
1293 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1295 /* If we are in 16-bit mode, do not allow addr16 or data16.
1296 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1297 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1298 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1299 ^ (flag_code
== CODE_16BIT
)))
1301 as_bad (_("redundant %s prefix"),
1302 current_templates
->start
->name
);
1305 /* Add prefix, checking for repeated prefixes. */
1306 switch (add_prefix (current_templates
->start
->base_opcode
))
1311 expecting_string_instruction
= current_templates
->start
->name
;
1314 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1321 if (!current_templates
)
1323 /* See if we can get a match by trimming off a suffix. */
1326 case WORD_MNEM_SUFFIX
:
1327 case BYTE_MNEM_SUFFIX
:
1328 case QWORD_MNEM_SUFFIX
:
1329 i
.suffix
= mnem_p
[-1];
1331 current_templates
= hash_find (op_hash
, mnemonic
);
1333 case SHORT_MNEM_SUFFIX
:
1334 case LONG_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1347 if (intel_float_operand (mnemonic
))
1348 i
.suffix
= SHORT_MNEM_SUFFIX
;
1350 i
.suffix
= LONG_MNEM_SUFFIX
;
1352 current_templates
= hash_find (op_hash
, mnemonic
);
1356 if (!current_templates
)
1358 as_bad (_("no such instruction: `%s'"), token_start
);
1363 /* Check if instruction is supported on specified architecture. */
1364 if (cpu_arch_flags
!= 0)
1366 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1367 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1369 as_warn (_("`%s' is not supported on `%s'"),
1370 current_templates
->start
->name
, cpu_arch_name
);
1372 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1374 as_warn (_("use .code16 to ensure correct addressing mode"));
1378 /* Check for rep/repne without a string instruction. */
1379 if (expecting_string_instruction
1380 && !(current_templates
->start
->opcode_modifier
& IsString
))
1382 as_bad (_("expecting string instruction after `%s'"),
1383 expecting_string_instruction
);
1387 /* There may be operands to parse. */
1388 if (*l
!= END_OF_INSN
)
1390 /* 1 if operand is pending after ','. */
1391 unsigned int expecting_operand
= 0;
1393 /* Non-zero if operand parens not balanced. */
1394 unsigned int paren_not_balanced
;
1398 /* Skip optional white space before operand. */
1399 if (is_space_char (*l
))
1401 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1403 as_bad (_("invalid character %s before operand %d"),
1404 output_invalid (*l
),
1408 token_start
= l
; /* after white space */
1409 paren_not_balanced
= 0;
1410 while (paren_not_balanced
|| *l
!= ',')
1412 if (*l
== END_OF_INSN
)
1414 if (paren_not_balanced
)
1417 as_bad (_("unbalanced parenthesis in operand %d."),
1420 as_bad (_("unbalanced brackets in operand %d."),
1425 break; /* we are done */
1427 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1429 as_bad (_("invalid character %s in operand %d"),
1430 output_invalid (*l
),
1437 ++paren_not_balanced
;
1439 --paren_not_balanced
;
1444 ++paren_not_balanced
;
1446 --paren_not_balanced
;
1450 if (l
!= token_start
)
1451 { /* Yes, we've read in another operand. */
1452 unsigned int operand_ok
;
1453 this_operand
= i
.operands
++;
1454 if (i
.operands
> MAX_OPERANDS
)
1456 as_bad (_("spurious operands; (%d operands/instruction max)"),
1460 /* Now parse operand adding info to 'i' as we go along. */
1461 END_STRING_AND_SAVE (l
);
1465 i386_intel_operand (token_start
,
1466 intel_float_operand (mnemonic
));
1468 operand_ok
= i386_operand (token_start
);
1470 RESTORE_END_STRING (l
);
1476 if (expecting_operand
)
1478 expecting_operand_after_comma
:
1479 as_bad (_("expecting operand after ','; got nothing"));
1484 as_bad (_("expecting operand before ','; got nothing"));
1489 /* Now *l must be either ',' or END_OF_INSN. */
1492 if (*++l
== END_OF_INSN
)
1494 /* Just skip it, if it's \n complain. */
1495 goto expecting_operand_after_comma
;
1497 expecting_operand
= 1;
1500 while (*l
!= END_OF_INSN
);
1504 /* Now we've parsed the mnemonic into a set of templates, and have the
1507 Next, we find a template that matches the given insn,
1508 making sure the overlap of the given operands types is consistent
1509 with the template operand types. */
1511 #define MATCH(overlap, given, template) \
1512 ((overlap & ~JumpAbsolute) \
1513 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1515 /* If given types r0 and r1 are registers they must be of the same type
1516 unless the expected operand type register overlap is null.
1517 Note that Acc in a template matches every size of reg. */
1518 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1519 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1520 ((g0) & Reg) == ((g1) & Reg) || \
1521 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1524 register unsigned int overlap0
, overlap1
;
1525 unsigned int overlap2
;
1526 unsigned int found_reverse_match
;
1529 /* All intel opcodes have reversed operands except for "bound" and
1530 "enter". We also don't reverse intersegment "jmp" and "call"
1531 instructions with 2 immediate operands so that the immediate segment
1532 precedes the offset, as it does when in AT&T mode. "enter" and the
1533 intersegment "jmp" and "call" instructions are the only ones that
1534 have two immediate operands. */
1535 if (intel_syntax
&& i
.operands
> 1
1536 && (strcmp (mnemonic
, "bound") != 0)
1537 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1539 union i386_op temp_op
;
1540 unsigned int temp_type
;
1541 RELOC_ENUM temp_reloc
;
1545 if (i
.operands
== 2)
1550 else if (i
.operands
== 3)
1555 temp_type
= i
.types
[xchg2
];
1556 i
.types
[xchg2
] = i
.types
[xchg1
];
1557 i
.types
[xchg1
] = temp_type
;
1558 temp_op
= i
.op
[xchg2
];
1559 i
.op
[xchg2
] = i
.op
[xchg1
];
1560 i
.op
[xchg1
] = temp_op
;
1561 temp_reloc
= i
.reloc
[xchg2
];
1562 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1563 i
.reloc
[xchg1
] = temp_reloc
;
1565 if (i
.mem_operands
== 2)
1567 const seg_entry
*temp_seg
;
1568 temp_seg
= i
.seg
[0];
1569 i
.seg
[0] = i
.seg
[1];
1570 i
.seg
[1] = temp_seg
;
1576 /* Try to ensure constant immediates are represented in the smallest
1578 char guess_suffix
= 0;
1582 guess_suffix
= i
.suffix
;
1583 else if (i
.reg_operands
)
1585 /* Figure out a suffix from the last register operand specified.
1586 We can't do this properly yet, ie. excluding InOutPortReg,
1587 but the following works for instructions with immediates.
1588 In any case, we can't set i.suffix yet. */
1589 for (op
= i
.operands
; --op
>= 0;)
1590 if (i
.types
[op
] & Reg
)
1592 if (i
.types
[op
] & Reg8
)
1593 guess_suffix
= BYTE_MNEM_SUFFIX
;
1594 else if (i
.types
[op
] & Reg16
)
1595 guess_suffix
= WORD_MNEM_SUFFIX
;
1596 else if (i
.types
[op
] & Reg32
)
1597 guess_suffix
= LONG_MNEM_SUFFIX
;
1598 else if (i
.types
[op
] & Reg64
)
1599 guess_suffix
= QWORD_MNEM_SUFFIX
;
1603 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1604 guess_suffix
= WORD_MNEM_SUFFIX
;
1606 for (op
= i
.operands
; --op
>= 0;)
1607 if (i
.types
[op
] & Imm
)
1609 switch (i
.op
[op
].imms
->X_op
)
1612 /* If a suffix is given, this operand may be shortened. */
1613 switch (guess_suffix
)
1615 case LONG_MNEM_SUFFIX
:
1616 i
.types
[op
] |= Imm32
| Imm64
;
1618 case WORD_MNEM_SUFFIX
:
1619 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1621 case BYTE_MNEM_SUFFIX
:
1622 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1626 /* If this operand is at most 16 bits, convert it
1627 to a signed 16 bit number before trying to see
1628 whether it will fit in an even smaller size.
1629 This allows a 16-bit operand such as $0xffe0 to
1630 be recognised as within Imm8S range. */
1631 if ((i
.types
[op
] & Imm16
)
1632 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1634 i
.op
[op
].imms
->X_add_number
=
1635 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1637 if ((i
.types
[op
] & Imm32
)
1638 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1640 i
.op
[op
].imms
->X_add_number
=
1641 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1643 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1644 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1645 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1646 i
.types
[op
] &= ~Imm32
;
1651 /* Symbols and expressions. */
1653 /* Convert symbolic operand to proper sizes for matching. */
1654 switch (guess_suffix
)
1656 case QWORD_MNEM_SUFFIX
:
1657 i
.types
[op
] = Imm64
| Imm32S
;
1659 case LONG_MNEM_SUFFIX
:
1660 i
.types
[op
] = Imm32
| Imm64
;
1662 case WORD_MNEM_SUFFIX
:
1663 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1666 case BYTE_MNEM_SUFFIX
:
1667 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1676 if (i
.disp_operands
)
1678 /* Try to use the smallest displacement type too. */
1681 for (op
= i
.operands
; --op
>= 0;)
1682 if ((i
.types
[op
] & Disp
)
1683 && i
.op
[op
].disps
->X_op
== O_constant
)
1685 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1687 if (i
.types
[op
] & Disp16
)
1689 /* We know this operand is at most 16 bits, so
1690 convert to a signed 16 bit number before trying
1691 to see whether it will fit in an even smaller
1694 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1696 else if (i
.types
[op
] & Disp32
)
1698 /* We know this operand is at most 32 bits, so convert to a
1699 signed 32 bit number before trying to see whether it will
1700 fit in an even smaller size. */
1701 disp
&= (((offsetT
) 2 << 31) - 1);
1702 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1704 if (flag_code
== CODE_64BIT
)
1706 if (fits_in_signed_long (disp
))
1707 i
.types
[op
] |= Disp32S
;
1708 if (fits_in_unsigned_long (disp
))
1709 i
.types
[op
] |= Disp32
;
1711 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1712 && fits_in_signed_byte (disp
))
1713 i
.types
[op
] |= Disp8
;
1720 found_reverse_match
= 0;
1721 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1723 : (i
.suffix
== WORD_MNEM_SUFFIX
1725 : (i
.suffix
== SHORT_MNEM_SUFFIX
1727 : (i
.suffix
== LONG_MNEM_SUFFIX
1729 : (i
.suffix
== QWORD_MNEM_SUFFIX
1731 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1733 for (t
= current_templates
->start
;
1734 t
< current_templates
->end
;
1737 /* Must have right number of operands. */
1738 if (i
.operands
!= t
->operands
)
1741 /* Check the suffix, except for some instructions in intel mode. */
1742 if ((t
->opcode_modifier
& suffix_check
)
1744 && (t
->opcode_modifier
& IgnoreSize
))
1746 && t
->base_opcode
== 0xd9
1747 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1748 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1751 /* Do not verify operands when there are none. */
1752 else if (!t
->operands
)
1754 if (t
->cpu_flags
& ~cpu_arch_flags
)
1756 /* We've found a match; break out of loop. */
1760 overlap0
= i
.types
[0] & t
->operand_types
[0];
1761 switch (t
->operands
)
1764 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1769 overlap1
= i
.types
[1] & t
->operand_types
[1];
1770 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1771 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1772 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1773 t
->operand_types
[0],
1774 overlap1
, i
.types
[1],
1775 t
->operand_types
[1]))
1777 /* Check if other direction is valid ... */
1778 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1781 /* Try reversing direction of operands. */
1782 overlap0
= i
.types
[0] & t
->operand_types
[1];
1783 overlap1
= i
.types
[1] & t
->operand_types
[0];
1784 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1785 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1786 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1787 t
->operand_types
[1],
1788 overlap1
, i
.types
[1],
1789 t
->operand_types
[0]))
1791 /* Does not match either direction. */
1794 /* found_reverse_match holds which of D or FloatDR
1796 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1798 /* Found a forward 2 operand match here. */
1799 else if (t
->operands
== 3)
1801 /* Here we make use of the fact that there are no
1802 reverse match 3 operand instructions, and all 3
1803 operand instructions only need to be checked for
1804 register consistency between operands 2 and 3. */
1805 overlap2
= i
.types
[2] & t
->operand_types
[2];
1806 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1807 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1808 t
->operand_types
[1],
1809 overlap2
, i
.types
[2],
1810 t
->operand_types
[2]))
1814 /* Found either forward/reverse 2 or 3 operand match here:
1815 slip through to break. */
1817 if (t
->cpu_flags
& ~cpu_arch_flags
)
1819 found_reverse_match
= 0;
1822 /* We've found a match; break out of loop. */
1825 if (t
== current_templates
->end
)
1827 /* We found no match. */
1828 as_bad (_("suffix or operands invalid for `%s'"),
1829 current_templates
->start
->name
);
1833 if (!quiet_warnings
)
1836 && ((i
.types
[0] & JumpAbsolute
)
1837 != (t
->operand_types
[0] & JumpAbsolute
)))
1839 as_warn (_("indirect %s without `*'"), t
->name
);
1842 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1843 == (IsPrefix
|IgnoreSize
))
1845 /* Warn them that a data or address size prefix doesn't
1846 affect assembly of the next line of code. */
1847 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1851 /* Copy the template we found. */
1853 if (found_reverse_match
)
1855 /* If we found a reverse match we must alter the opcode
1856 direction bit. found_reverse_match holds bits to change
1857 (different for int & float insns). */
1859 i
.tm
.base_opcode
^= found_reverse_match
;
1861 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1862 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1865 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1868 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1869 i
.tm
.base_opcode
^= FloatR
;
1871 if (i
.tm
.opcode_modifier
& FWait
)
1872 if (! add_prefix (FWAIT_OPCODE
))
1875 /* Check string instruction segment overrides. */
1876 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1878 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1879 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1881 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1883 as_bad (_("`%s' operand %d must use `%%es' segment"),
1888 /* There's only ever one segment override allowed per instruction.
1889 This instruction possibly has a legal segment override on the
1890 second operand, so copy the segment to where non-string
1891 instructions store it, allowing common code. */
1892 i
.seg
[0] = i
.seg
[1];
1894 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1896 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1898 as_bad (_("`%s' operand %d must use `%%es' segment"),
1906 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1909 for (op
= i
.operands
; --op
>= 0;)
1910 if ((i
.types
[op
] & Reg
)
1911 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1913 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1914 i
.op
[op
].regs
->reg_name
);
1919 /* If matched instruction specifies an explicit instruction mnemonic
1921 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1923 if (i
.tm
.opcode_modifier
& Size16
)
1924 i
.suffix
= WORD_MNEM_SUFFIX
;
1925 else if (i
.tm
.opcode_modifier
& Size64
)
1926 i
.suffix
= QWORD_MNEM_SUFFIX
;
1928 i
.suffix
= LONG_MNEM_SUFFIX
;
1930 else if (i
.reg_operands
)
1932 /* If there's no instruction mnemonic suffix we try to invent one
1933 based on register operands. */
1936 /* We take i.suffix from the last register operand specified,
1937 Destination register type is more significant than source
1940 for (op
= i
.operands
; --op
>= 0;)
1941 if ((i
.types
[op
] & Reg
)
1942 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1944 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1945 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1946 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1951 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1954 for (op
= i
.operands
; --op
>= 0;)
1956 /* If this is an eight bit register, it's OK. If it's
1957 the 16 or 32 bit version of an eight bit register,
1958 we will just use the low portion, and that's OK too. */
1959 if (i
.types
[op
] & Reg8
)
1962 /* movzx and movsx should not generate this warning. */
1964 && (i
.tm
.base_opcode
== 0xfb7
1965 || i
.tm
.base_opcode
== 0xfb6
1966 || i
.tm
.base_opcode
== 0x63
1967 || i
.tm
.base_opcode
== 0xfbe
1968 || i
.tm
.base_opcode
== 0xfbf))
1971 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1973 /* Check that the template allows eight bit regs
1974 This kills insns such as `orb $1,%edx', which
1975 maybe should be allowed. */
1976 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1980 /* Prohibit these changes in the 64bit mode, since
1981 the lowering is more complicated. */
1982 if (flag_code
== CODE_64BIT
1983 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1984 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1985 i
.op
[op
].regs
->reg_name
,
1987 #if REGISTER_WARNINGS
1989 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1990 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1992 + (i
.types
[op
] & Reg16
1993 ? REGNAM_AL
- REGNAM_AX
1994 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
1995 i
.op
[op
].regs
->reg_name
,
2000 /* Any other register is bad. */
2001 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2003 | Control
| Debug
| Test
2004 | FloatReg
| FloatAcc
))
2006 as_bad (_("`%%%s' not allowed with `%s%c'"),
2007 i
.op
[op
].regs
->reg_name
,
2014 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2018 for (op
= i
.operands
; --op
>= 0;)
2019 /* Reject eight bit registers, except where the template
2020 requires them. (eg. movzb) */
2021 if ((i
.types
[op
] & Reg8
) != 0
2022 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2024 as_bad (_("`%%%s' not allowed with `%s%c'"),
2025 i
.op
[op
].regs
->reg_name
,
2030 /* Warn if the e prefix on a general reg is missing. */
2031 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2032 && (i
.types
[op
] & Reg16
) != 0
2033 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2035 /* Prohibit these changes in the 64bit mode, since
2036 the lowering is more complicated. */
2037 if (flag_code
== CODE_64BIT
)
2038 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2039 i
.op
[op
].regs
->reg_name
,
2041 #if REGISTER_WARNINGS
2043 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2044 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2045 i
.op
[op
].regs
->reg_name
,
2049 /* Warn if the r prefix on a general reg is missing. */
2050 else if ((i
.types
[op
] & Reg64
) != 0
2051 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2053 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2054 i
.op
[op
].regs
->reg_name
,
2058 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2062 for (op
= i
.operands
; --op
>= 0; )
2063 /* Reject eight bit registers, except where the template
2064 requires them. (eg. movzb) */
2065 if ((i
.types
[op
] & Reg8
) != 0
2066 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2068 as_bad (_("`%%%s' not allowed with `%s%c'"),
2069 i
.op
[op
].regs
->reg_name
,
2074 /* Warn if the e prefix on a general reg is missing. */
2075 else if (((i
.types
[op
] & Reg16
) != 0
2076 || (i
.types
[op
] & Reg32
) != 0)
2077 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2079 /* Prohibit these changes in the 64bit mode, since
2080 the lowering is more complicated. */
2081 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2082 i
.op
[op
].regs
->reg_name
,
2086 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2089 for (op
= i
.operands
; --op
>= 0;)
2090 /* Reject eight bit registers, except where the template
2091 requires them. (eg. movzb) */
2092 if ((i
.types
[op
] & Reg8
) != 0
2093 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2095 as_bad (_("`%%%s' not allowed with `%s%c'"),
2096 i
.op
[op
].regs
->reg_name
,
2101 /* Warn if the e prefix on a general reg is present. */
2102 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2103 && (i
.types
[op
] & Reg32
) != 0
2104 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2106 /* Prohibit these changes in the 64bit mode, since
2107 the lowering is more complicated. */
2108 if (flag_code
== CODE_64BIT
)
2109 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2110 i
.op
[op
].regs
->reg_name
,
2113 #if REGISTER_WARNINGS
2114 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2115 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2116 i
.op
[op
].regs
->reg_name
,
2121 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2122 /* Do nothing if the instruction is going to ignore the prefix. */
2127 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2129 i
.suffix
= stackop_size
;
2131 /* Make still unresolved immediate matches conform to size of immediate
2132 given in i.suffix. Note: overlap2 cannot be an immediate! */
2133 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2134 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2135 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2136 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2140 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2141 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2142 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2144 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2145 || overlap0
== (Imm16
| Imm32
)
2146 || overlap0
== (Imm16
| Imm32S
))
2149 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2151 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2152 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2153 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2155 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2159 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2160 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2161 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2162 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2166 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2167 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2168 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2170 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2171 || overlap1
== (Imm16
| Imm32
)
2172 || overlap1
== (Imm16
| Imm32S
))
2175 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2177 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2178 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2179 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2181 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2185 assert ((overlap2
& Imm
) == 0);
2187 i
.types
[0] = overlap0
;
2188 if (overlap0
& ImplicitRegister
)
2190 if (overlap0
& Imm1
)
2191 i
.imm_operands
= 0; /* kludge for shift insns. */
2193 i
.types
[1] = overlap1
;
2194 if (overlap1
& ImplicitRegister
)
2197 i
.types
[2] = overlap2
;
2198 if (overlap2
& ImplicitRegister
)
2201 /* Finalize opcode. First, we change the opcode based on the operand
2202 size given by i.suffix: We need not change things for byte insns. */
2204 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2206 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2210 /* For movzx and movsx, need to check the register type. */
2212 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2213 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2215 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2217 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2218 if (!add_prefix (prefix
))
2222 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2224 /* It's not a byte, select word/dword operation. */
2225 if (i
.tm
.opcode_modifier
& W
)
2227 if (i
.tm
.opcode_modifier
& ShortForm
)
2228 i
.tm
.base_opcode
|= 8;
2230 i
.tm
.base_opcode
|= 1;
2232 /* Now select between word & dword operations via the operand
2233 size prefix, except for instructions that will ignore this
2235 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2236 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2237 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2239 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2240 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2241 prefix
= ADDR_PREFIX_OPCODE
;
2243 if (! add_prefix (prefix
))
2247 /* Set mode64 for an operand. */
2248 if (i
.suffix
== QWORD_MNEM_SUFFIX
2249 && !(i
.tm
.opcode_modifier
& NoRex64
))
2252 if (flag_code
< CODE_64BIT
)
2254 as_bad (_("64bit operations available only in 64bit modes."));
2259 /* Size floating point instruction. */
2260 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2262 if (i
.tm
.opcode_modifier
& FloatMF
)
2263 i
.tm
.base_opcode
^= 4;
2267 if (i
.tm
.opcode_modifier
& ImmExt
)
2269 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2270 opcode suffix which is coded in the same place as an 8-bit
2271 immediate field would be. Here we fake an 8-bit immediate
2272 operand from the opcode suffix stored in tm.extension_opcode. */
2276 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2278 exp
= &im_expressions
[i
.imm_operands
++];
2279 i
.op
[i
.operands
].imms
= exp
;
2280 i
.types
[i
.operands
++] = Imm8
;
2281 exp
->X_op
= O_constant
;
2282 exp
->X_add_number
= i
.tm
.extension_opcode
;
2283 i
.tm
.extension_opcode
= None
;
2286 /* For insns with operands there are more diddles to do to the opcode. */
2289 /* Default segment register this instruction will use
2290 for memory accesses. 0 means unknown.
2291 This is only for optimizing out unnecessary segment overrides. */
2292 const seg_entry
*default_seg
= 0;
2294 /* The imul $imm, %reg instruction is converted into
2295 imul $imm, %reg, %reg, and the clr %reg instruction
2296 is converted into xor %reg, %reg. */
2297 if (i
.tm
.opcode_modifier
& regKludge
)
2299 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2300 /* Pretend we saw the extra register operand. */
2301 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2302 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2303 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2307 if (i
.tm
.opcode_modifier
& ShortForm
)
2309 /* The register or float register operand is in operand 0 or 1. */
2310 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2311 /* Register goes in low 3 bits of opcode. */
2312 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2313 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2315 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2317 /* Warn about some common errors, but press on regardless.
2318 The first case can be generated by gcc (<= 2.8.1). */
2319 if (i
.operands
== 2)
2321 /* Reversed arguments on faddp, fsubp, etc. */
2322 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2323 i
.op
[1].regs
->reg_name
,
2324 i
.op
[0].regs
->reg_name
);
2328 /* Extraneous `l' suffix on fp insn. */
2329 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2330 i
.op
[0].regs
->reg_name
);
2334 else if (i
.tm
.opcode_modifier
& Modrm
)
2336 /* The opcode is completed (modulo i.tm.extension_opcode which
2337 must be put into the modrm byte).
2338 Now, we make the modrm & index base bytes based on all the
2339 info we've collected. */
2341 /* i.reg_operands MUST be the number of real register operands;
2342 implicit registers do not count. */
2343 if (i
.reg_operands
== 2)
2345 unsigned int source
, dest
;
2346 source
= ((i
.types
[0]
2347 & (Reg
| RegMMX
| RegXMM
2349 | Control
| Debug
| Test
))
2354 /* One of the register operands will be encoded in the
2355 i.tm.reg field, the other in the combined i.tm.mode
2356 and i.tm.regmem fields. If no form of this
2357 instruction supports a memory destination operand,
2358 then we assume the source operand may sometimes be
2359 a memory operand and so we need to store the
2360 destination in the i.rm.reg field. */
2361 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2363 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2364 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2365 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2367 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2372 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2373 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2374 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2376 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2381 { /* If it's not 2 reg operands... */
2384 unsigned int fake_zero_displacement
= 0;
2385 unsigned int op
= ((i
.types
[0] & AnyMem
)
2387 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2394 if (! i
.disp_operands
)
2395 fake_zero_displacement
= 1;
2398 /* Operand is just <disp> */
2399 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2401 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2402 i
.types
[op
] &= ~Disp
;
2403 i
.types
[op
] |= Disp16
;
2405 else if (flag_code
!= CODE_64BIT
)
2407 i
.rm
.regmem
= NO_BASE_REGISTER
;
2408 i
.types
[op
] &= ~Disp
;
2409 i
.types
[op
] |= Disp32
;
2413 /* 64bit mode overwrites the 32bit
2414 absolute addressing by RIP relative
2415 addressing and absolute addressing
2416 is encoded by one of the redundant
2419 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2420 i
.sib
.base
= NO_BASE_REGISTER
;
2421 i
.sib
.index
= NO_INDEX_REGISTER
;
2422 i
.types
[op
] &= ~Disp
;
2423 i
.types
[op
] |= Disp32S
;
2426 else /* ! i.base_reg && i.index_reg */
2428 i
.sib
.index
= i
.index_reg
->reg_num
;
2429 i
.sib
.base
= NO_BASE_REGISTER
;
2430 i
.sib
.scale
= i
.log2_scale_factor
;
2431 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2432 i
.types
[op
] &= ~Disp
;
2433 if (flag_code
!= CODE_64BIT
)
2434 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2436 i
.types
[op
] |= Disp32S
;
2437 if (i
.index_reg
->reg_flags
& RegRex
)
2441 /* RIP addressing for 64bit mode. */
2442 else if (i
.base_reg
->reg_type
== BaseIndex
)
2444 i
.rm
.regmem
= NO_BASE_REGISTER
;
2445 i
.types
[op
] &= ~Disp
;
2446 i
.types
[op
] |= Disp32S
;
2447 i
.flags
[op
] = Operand_PCrel
;
2449 else if (i
.base_reg
->reg_type
& Reg16
)
2451 switch (i
.base_reg
->reg_num
)
2456 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2457 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2464 if ((i
.types
[op
] & Disp
) == 0)
2466 /* fake (%bp) into 0(%bp) */
2467 i
.types
[op
] |= Disp8
;
2468 fake_zero_displacement
= 1;
2471 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2472 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2474 default: /* (%si) -> 4 or (%di) -> 5 */
2475 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2477 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2479 else /* i.base_reg and 32/64 bit mode */
2481 if (flag_code
== CODE_64BIT
2482 && (i
.types
[op
] & Disp
))
2484 if (i
.types
[op
] & Disp8
)
2485 i
.types
[op
] = Disp8
| Disp32S
;
2487 i
.types
[op
] = Disp32S
;
2489 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2490 if (i
.base_reg
->reg_flags
& RegRex
)
2492 i
.sib
.base
= i
.base_reg
->reg_num
;
2493 /* x86-64 ignores REX prefix bit here to avoid
2494 decoder complications. */
2495 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2498 if (i
.disp_operands
== 0)
2500 fake_zero_displacement
= 1;
2501 i
.types
[op
] |= Disp8
;
2504 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2508 i
.sib
.scale
= i
.log2_scale_factor
;
2511 /* <disp>(%esp) becomes two byte modrm
2512 with no index register. We've already
2513 stored the code for esp in i.rm.regmem
2514 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2515 base register besides %esp will not use
2516 the extra modrm byte. */
2517 i
.sib
.index
= NO_INDEX_REGISTER
;
2518 #if ! SCALE1_WHEN_NO_INDEX
2519 /* Another case where we force the second
2521 if (i
.log2_scale_factor
)
2522 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2527 i
.sib
.index
= i
.index_reg
->reg_num
;
2528 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2529 if (i
.index_reg
->reg_flags
& RegRex
)
2532 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2535 if (fake_zero_displacement
)
2537 /* Fakes a zero displacement assuming that i.types[op]
2538 holds the correct displacement size. */
2541 assert (i
.op
[op
].disps
== 0);
2542 exp
= &disp_expressions
[i
.disp_operands
++];
2543 i
.op
[op
].disps
= exp
;
2544 exp
->X_op
= O_constant
;
2545 exp
->X_add_number
= 0;
2546 exp
->X_add_symbol
= (symbolS
*) 0;
2547 exp
->X_op_symbol
= (symbolS
*) 0;
2551 /* Fill in i.rm.reg or i.rm.regmem field with register
2552 operand (if any) based on i.tm.extension_opcode.
2553 Again, we must be careful to make sure that
2554 segment/control/debug/test/MMX registers are coded
2555 into the i.rm.reg field. */
2560 & (Reg
| RegMMX
| RegXMM
2562 | Control
| Debug
| Test
))
2565 & (Reg
| RegMMX
| RegXMM
2567 | Control
| Debug
| Test
))
2570 /* If there is an extension opcode to put here, the
2571 register number must be put into the regmem field. */
2572 if (i
.tm
.extension_opcode
!= None
)
2574 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2575 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2580 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2581 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2585 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2586 we must set it to 3 to indicate this is a register
2587 operand in the regmem field. */
2588 if (!i
.mem_operands
)
2592 /* Fill in i.rm.reg field with extension opcode (if any). */
2593 if (i
.tm
.extension_opcode
!= None
)
2594 i
.rm
.reg
= i
.tm
.extension_opcode
;
2597 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2599 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2600 && i
.op
[0].regs
->reg_num
== 1)
2602 as_bad (_("you can't `pop %%cs'"));
2605 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2606 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2609 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2613 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2615 /* For the string instructions that allow a segment override
2616 on one of their operands, the default segment is ds. */
2620 /* If a segment was explicitly specified,
2621 and the specified segment is not the default,
2622 use an opcode prefix to select it.
2623 If we never figured out what the default segment is,
2624 then default_seg will be zero at this point,
2625 and the specified segment prefix will always be used. */
2626 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2628 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2632 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2634 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2635 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2639 /* Handle conversion of 'int $3' --> special int3 insn. */
2640 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2642 i
.tm
.base_opcode
= INT3_OPCODE
;
2646 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2647 && i
.op
[0].disps
->X_op
== O_constant
)
2649 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2650 the absolute address given by the constant. Since ix86 jumps and
2651 calls are pc relative, we need to generate a reloc. */
2652 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2653 i
.op
[0].disps
->X_op
= O_symbol
;
2656 if (i
.tm
.opcode_modifier
& Rex64
)
2659 /* For 8bit registers we would need an empty rex prefix.
2660 Also in the case instruction is already having prefix,
2661 we need to convert old registers to new ones. */
2663 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2664 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2665 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2666 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2670 for (x
= 0; x
< 2; x
++)
2672 /* Look for 8bit operand that does use old registers. */
2673 if (i
.types
[x
] & Reg8
2674 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2676 /* In case it is "hi" register, give up. */
2677 if (i
.op
[x
].regs
->reg_num
> 3)
2678 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2679 i
.op
[x
].regs
->reg_name
);
2681 /* Otherwise it is equivalent to the extended register.
2682 Since the encoding don't change this is merely cosmetical
2683 cleanup for debug output. */
2685 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2690 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2692 | (i
.rex
.mode64
? 8 : 0)
2693 | (i
.rex
.extX
? 4 : 0)
2694 | (i
.rex
.extY
? 2 : 0)
2695 | (i
.rex
.extZ
? 1 : 0));
2697 /* We are ready to output the insn. */
2701 /* Tie dwarf2 debug info to the address at the start of the insn.
2702 We can't do this after the insn has been output as the current
2703 frag may have been closed off. eg. by frag_var. */
2704 dwarf2_emit_insn (0);
2707 if (i
.tm
.opcode_modifier
& Jump
)
2713 if (flag_code
== CODE_16BIT
)
2717 if (i
.prefix
[DATA_PREFIX
])
2723 if (i
.prefix
[REX_PREFIX
])
2729 if (i
.prefixes
!= 0 && !intel_syntax
)
2730 as_warn (_("skipping prefixes on this instruction"));
2732 /* It's always a symbol; End frag & setup for relax.
2733 Make sure there is enough room in this frag for the largest
2734 instruction we may generate in md_convert_frag. This is 2
2735 bytes for the opcode and room for the prefix and largest
2737 frag_grow (prefix
+ 2 + 4);
2738 /* Prefix and 1 opcode byte go in fr_fix. */
2739 p
= frag_more (prefix
+ 1);
2740 if (i
.prefix
[DATA_PREFIX
])
2741 *p
++ = DATA_PREFIX_OPCODE
;
2742 if (i
.prefix
[REX_PREFIX
])
2743 *p
++ = i
.prefix
[REX_PREFIX
];
2744 *p
= i
.tm
.base_opcode
;
2745 /* 1 possible extra opcode + displacement go in var part.
2746 Pass reloc in fr_var. */
2747 frag_var (rs_machine_dependent
,
2750 ((unsigned char) *p
== JUMP_PC_RELATIVE
2751 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2752 : ((cpu_arch_flags
& Cpu386
) != 0
2753 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2754 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2755 i
.op
[0].disps
->X_add_symbol
,
2756 i
.op
[0].disps
->X_add_number
,
2759 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2763 if (i
.tm
.opcode_modifier
& JumpByte
)
2765 /* This is a loop or jecxz type instruction. */
2767 if (i
.prefix
[ADDR_PREFIX
])
2769 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2778 if (flag_code
== CODE_16BIT
)
2781 if (i
.prefix
[DATA_PREFIX
])
2783 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2793 if (i
.prefix
[REX_PREFIX
])
2795 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2799 if (i
.prefixes
!= 0 && !intel_syntax
)
2800 as_warn (_("skipping prefixes on this instruction"));
2802 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2804 p
= frag_more (1 + size
);
2808 /* Opcode can be at most two bytes. */
2809 p
= frag_more (2 + size
);
2810 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2812 *p
++ = i
.tm
.base_opcode
& 0xff;
2814 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2815 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2817 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2824 if (flag_code
== CODE_16BIT
)
2828 if (i
.prefix
[DATA_PREFIX
])
2834 if (i
.prefix
[REX_PREFIX
])
2844 if (i
.prefixes
!= 0 && !intel_syntax
)
2845 as_warn (_("skipping prefixes on this instruction"));
2847 /* 1 opcode; 2 segment; offset */
2848 p
= frag_more (prefix
+ 1 + 2 + size
);
2850 if (i
.prefix
[DATA_PREFIX
])
2851 *p
++ = DATA_PREFIX_OPCODE
;
2853 if (i
.prefix
[REX_PREFIX
])
2854 *p
++ = i
.prefix
[REX_PREFIX
];
2856 *p
++ = i
.tm
.base_opcode
;
2857 if (i
.op
[1].imms
->X_op
== O_constant
)
2859 offsetT n
= i
.op
[1].imms
->X_add_number
;
2862 && !fits_in_unsigned_word (n
)
2863 && !fits_in_signed_word (n
))
2865 as_bad (_("16-bit jump out of range"));
2868 md_number_to_chars (p
, n
, size
);
2871 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2872 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2873 if (i
.op
[0].imms
->X_op
!= O_constant
)
2874 as_bad (_("can't handle non absolute segment in `%s'"),
2876 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2880 /* Output normal instructions here. */
2883 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2884 byte for the SSE instructions to specify prefix they require. */
2885 if (i
.tm
.base_opcode
& 0xff0000)
2886 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2888 /* The prefix bytes. */
2890 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2896 md_number_to_chars (p
, (valueT
) *q
, 1);
2900 /* Now the opcode; be careful about word order here! */
2901 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2903 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2908 /* Put out high byte first: can't use md_number_to_chars! */
2909 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2910 *p
= i
.tm
.base_opcode
& 0xff;
2913 /* Now the modrm byte and sib byte (if present). */
2914 if (i
.tm
.opcode_modifier
& Modrm
)
2917 md_number_to_chars (p
,
2918 (valueT
) (i
.rm
.regmem
<< 0
2922 /* If i.rm.regmem == ESP (4)
2923 && i.rm.mode != (Register mode)
2925 ==> need second modrm byte. */
2926 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2928 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2931 md_number_to_chars (p
,
2932 (valueT
) (i
.sib
.base
<< 0
2934 | i
.sib
.scale
<< 6),
2939 if (i
.disp_operands
)
2941 register unsigned int n
;
2943 for (n
= 0; n
< i
.operands
; n
++)
2945 if (i
.types
[n
] & Disp
)
2947 if (i
.op
[n
].disps
->X_op
== O_constant
)
2953 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2956 if (i
.types
[n
] & Disp8
)
2958 if (i
.types
[n
] & Disp64
)
2961 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2963 p
= frag_more (size
);
2964 md_number_to_chars (p
, val
, size
);
2970 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2972 /* The PC relative address is computed relative
2973 to the instruction boundary, so in case immediate
2974 fields follows, we need to adjust the value. */
2975 if (pcrel
&& i
.imm_operands
)
2978 register unsigned int n1
;
2980 for (n1
= 0; n1
< i
.operands
; n1
++)
2981 if (i
.types
[n1
] & Imm
)
2983 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2986 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2988 if (i
.types
[n1
] & Imm64
)
2993 /* We should find the immediate. */
2994 if (n1
== i
.operands
)
2996 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2999 if (i
.types
[n
] & Disp32S
)
3002 if (i
.types
[n
] & (Disp16
| Disp64
))
3005 if (i
.types
[n
] & Disp64
)
3009 p
= frag_more (size
);
3010 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3011 i
.op
[n
].disps
, pcrel
,
3012 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3018 /* Output immediate. */
3021 register unsigned int n
;
3023 for (n
= 0; n
< i
.operands
; n
++)
3025 if (i
.types
[n
] & Imm
)
3027 if (i
.op
[n
].imms
->X_op
== O_constant
)
3033 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3036 if (i
.types
[n
] & (Imm8
| Imm8S
))
3038 else if (i
.types
[n
] & Imm64
)
3041 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3043 p
= frag_more (size
);
3044 md_number_to_chars (p
, val
, size
);
3048 /* Not absolute_section.
3049 Need a 32-bit fixup (don't support 8bit
3050 non-absolute imms). Try to support other
3052 RELOC_ENUM reloc_type
;
3056 if ((i
.types
[n
] & (Imm32S
))
3057 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3059 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3062 if (i
.types
[n
] & (Imm8
| Imm8S
))
3064 if (i
.types
[n
] & Imm64
)
3068 p
= frag_more (size
);
3069 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3070 #ifdef BFD_ASSEMBLER
3071 if (reloc_type
== BFD_RELOC_32
3073 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3074 && (i
.op
[n
].imms
->X_op
== O_symbol
3075 || (i
.op
[n
].imms
->X_op
== O_add
3076 && ((symbol_get_value_expression
3077 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3080 /* We don't support dynamic linking on x86-64 yet. */
3081 if (flag_code
== CODE_64BIT
)
3083 reloc_type
= BFD_RELOC_386_GOTPC
;
3084 i
.op
[n
].imms
->X_add_number
+= 3;
3087 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3088 i
.op
[n
].imms
, 0, reloc_type
);
3100 #endif /* DEBUG386 */
3105 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3107 /* Parse operands of the form
3108 <symbol>@GOTOFF+<nnn>
3109 and similar .plt or .got references.
3111 If we find one, set up the correct relocation in RELOC and copy the
3112 input string, minus the `@GOTOFF' into a malloc'd buffer for
3113 parsing by the calling routine. Return this buffer, and if ADJUST
3114 is non-null set it to the length of the string we removed from the
3115 input line. Otherwise return NULL. */
3117 lex_got (reloc
, adjust
)
3121 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3122 static const struct {
3124 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3126 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3127 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3128 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3129 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3134 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3135 if (is_end_of_line
[(unsigned char) *cp
])
3138 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3142 len
= strlen (gotrel
[j
].str
);
3143 if (strncmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3145 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3150 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3152 if (GOT_symbol
== NULL
)
3153 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3155 /* Replace the relocation token with ' ', so that
3156 errors like foo@GOTOFF1 will be detected. */
3157 first
= cp
- input_line_pointer
;
3158 tmpbuf
= xmalloc (strlen (input_line_pointer
));
3159 memcpy (tmpbuf
, input_line_pointer
, first
);
3160 tmpbuf
[first
] = ' ';
3161 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3167 as_bad (_("@%s reloc is not supported in %s bit mode"),
3168 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3173 /* Might be a symbol version string. Don't as_bad here. */
3177 /* x86_cons_fix_new is called via the expression parsing code when a
3178 reloc is needed. We use this hook to get the correct .got reloc. */
3179 static RELOC_ENUM got_reloc
= NO_RELOC
;
3182 x86_cons_fix_new (frag
, off
, len
, exp
)
3188 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3189 got_reloc
= NO_RELOC
;
3190 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3194 x86_cons (exp
, size
)
3200 /* Handle @GOTOFF and the like in an expression. */
3202 char *gotfree_input_line
;
3205 save
= input_line_pointer
;
3206 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3207 if (gotfree_input_line
)
3208 input_line_pointer
= gotfree_input_line
;
3212 if (gotfree_input_line
)
3214 /* expression () has merrily parsed up to the end of line,
3215 or a comma - in the wrong buffer. Transfer how far
3216 input_line_pointer has moved to the right buffer. */
3217 input_line_pointer
= (save
3218 + (input_line_pointer
- gotfree_input_line
)
3220 free (gotfree_input_line
);
3228 static int i386_immediate
PARAMS ((char *));
3231 i386_immediate (imm_start
)
3234 char *save_input_line_pointer
;
3236 char *gotfree_input_line
;
3241 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3243 as_bad (_("only 1 or 2 immediate operands are allowed"));
3247 exp
= &im_expressions
[i
.imm_operands
++];
3248 i
.op
[this_operand
].imms
= exp
;
3250 if (is_space_char (*imm_start
))
3253 save_input_line_pointer
= input_line_pointer
;
3254 input_line_pointer
= imm_start
;
3257 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3258 if (gotfree_input_line
)
3259 input_line_pointer
= gotfree_input_line
;
3262 exp_seg
= expression (exp
);
3265 if (*input_line_pointer
)
3266 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3268 input_line_pointer
= save_input_line_pointer
;
3270 if (gotfree_input_line
)
3271 free (gotfree_input_line
);
3274 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3276 /* Missing or bad expr becomes absolute 0. */
3277 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3279 exp
->X_op
= O_constant
;
3280 exp
->X_add_number
= 0;
3281 exp
->X_add_symbol
= (symbolS
*) 0;
3282 exp
->X_op_symbol
= (symbolS
*) 0;
3284 else if (exp
->X_op
== O_constant
)
3286 /* Size it properly later. */
3287 i
.types
[this_operand
] |= Imm64
;
3288 /* If BFD64, sign extend val. */
3289 if (!use_rela_relocations
)
3290 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3291 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3293 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3295 #ifdef BFD_ASSEMBLER
3296 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3298 && exp_seg
!= text_section
3299 && exp_seg
!= data_section
3300 && exp_seg
!= bss_section
3301 && exp_seg
!= undefined_section
3302 #ifdef BFD_ASSEMBLER
3303 && !bfd_is_com_section (exp_seg
)
3307 #ifdef BFD_ASSEMBLER
3308 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3310 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3317 /* This is an address. The size of the address will be
3318 determined later, depending on destination register,
3319 suffix, or the default for the section. */
3320 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3326 static char *i386_scale
PARAMS ((char *));
3333 char *save
= input_line_pointer
;
3335 input_line_pointer
= scale
;
3336 val
= get_absolute_expression ();
3342 i
.log2_scale_factor
= 0;
3345 i
.log2_scale_factor
= 1;
3348 i
.log2_scale_factor
= 2;
3351 i
.log2_scale_factor
= 3;
3354 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3356 input_line_pointer
= save
;
3359 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3361 as_warn (_("scale factor of %d without an index register"),
3362 1 << i
.log2_scale_factor
);
3363 #if SCALE1_WHEN_NO_INDEX
3364 i
.log2_scale_factor
= 0;
3367 scale
= input_line_pointer
;
3368 input_line_pointer
= save
;
3372 static int i386_displacement
PARAMS ((char *, char *));
3375 i386_displacement (disp_start
, disp_end
)
3379 register expressionS
*exp
;
3381 char *save_input_line_pointer
;
3383 char *gotfree_input_line
;
3385 int bigdisp
= Disp32
;
3387 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3389 if (flag_code
== CODE_64BIT
)
3391 i
.types
[this_operand
] |= bigdisp
;
3393 exp
= &disp_expressions
[i
.disp_operands
];
3394 i
.op
[this_operand
].disps
= exp
;
3396 save_input_line_pointer
= input_line_pointer
;
3397 input_line_pointer
= disp_start
;
3398 END_STRING_AND_SAVE (disp_end
);
3400 #ifndef GCC_ASM_O_HACK
3401 #define GCC_ASM_O_HACK 0
3404 END_STRING_AND_SAVE (disp_end
+ 1);
3405 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3406 && displacement_string_end
[-1] == '+')
3408 /* This hack is to avoid a warning when using the "o"
3409 constraint within gcc asm statements.
3412 #define _set_tssldt_desc(n,addr,limit,type) \
3413 __asm__ __volatile__ ( \
3415 "movw %w1,2+%0\n\t" \
3417 "movb %b1,4+%0\n\t" \
3418 "movb %4,5+%0\n\t" \
3419 "movb $0,6+%0\n\t" \
3420 "movb %h1,7+%0\n\t" \
3422 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3424 This works great except that the output assembler ends
3425 up looking a bit weird if it turns out that there is
3426 no offset. You end up producing code that looks like:
3439 So here we provide the missing zero. */
3441 *displacement_string_end
= '0';
3445 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3446 if (gotfree_input_line
)
3447 input_line_pointer
= gotfree_input_line
;
3450 exp_seg
= expression (exp
);
3453 if (*input_line_pointer
)
3454 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3456 RESTORE_END_STRING (disp_end
+ 1);
3458 RESTORE_END_STRING (disp_end
);
3459 input_line_pointer
= save_input_line_pointer
;
3461 if (gotfree_input_line
)
3462 free (gotfree_input_line
);
3465 #ifdef BFD_ASSEMBLER
3466 /* We do this to make sure that the section symbol is in
3467 the symbol table. We will ultimately change the relocation
3468 to be relative to the beginning of the section. */
3469 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3470 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3472 if (exp
->X_op
!= O_symbol
)
3474 as_bad (_("bad expression used with @%s"),
3475 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3481 if (S_IS_LOCAL (exp
->X_add_symbol
)
3482 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3483 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3484 exp
->X_op
= O_subtract
;
3485 exp
->X_op_symbol
= GOT_symbol
;
3486 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3487 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3489 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3493 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3495 /* Missing or bad expr becomes absolute 0. */
3496 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3498 exp
->X_op
= O_constant
;
3499 exp
->X_add_number
= 0;
3500 exp
->X_add_symbol
= (symbolS
*) 0;
3501 exp
->X_op_symbol
= (symbolS
*) 0;
3504 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3505 if (exp
->X_op
!= O_constant
3506 #ifdef BFD_ASSEMBLER
3507 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3509 && exp_seg
!= text_section
3510 && exp_seg
!= data_section
3511 && exp_seg
!= bss_section
3512 && exp_seg
!= undefined_section
)
3514 #ifdef BFD_ASSEMBLER
3515 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3517 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3522 else if (flag_code
== CODE_64BIT
)
3523 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3527 static int i386_index_check
PARAMS ((const char *));
3529 /* Make sure the memory operand we've been dealt is valid.
3530 Return 1 on success, 0 on a failure. */
3533 i386_index_check (operand_string
)
3534 const char *operand_string
;
3537 #if INFER_ADDR_PREFIX
3543 if (flag_code
== CODE_64BIT
)
3547 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3548 && (i
.base_reg
->reg_type
!= BaseIndex
3551 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3552 != (Reg64
|BaseIndex
))))
3557 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3561 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3562 != (Reg16
|BaseIndex
)))
3564 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3565 != (Reg16
|BaseIndex
))
3567 && i
.base_reg
->reg_num
< 6
3568 && i
.index_reg
->reg_num
>= 6
3569 && i
.log2_scale_factor
== 0))))
3576 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3578 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3579 != (Reg32
|BaseIndex
))))
3585 #if INFER_ADDR_PREFIX
3586 if (flag_code
!= CODE_64BIT
3587 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3589 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3591 /* Change the size of any displacement too. At most one of
3592 Disp16 or Disp32 is set.
3593 FIXME. There doesn't seem to be any real need for separate
3594 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3595 Removing them would probably clean up the code quite a lot. */
3596 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3597 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3602 as_bad (_("`%s' is not a valid base/index expression"),
3606 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3608 flag_code_names
[flag_code
]);
3614 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3618 i386_operand (operand_string
)
3619 char *operand_string
;
3623 char *op_string
= operand_string
;
3625 if (is_space_char (*op_string
))
3628 /* We check for an absolute prefix (differentiating,
3629 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3630 if (*op_string
== ABSOLUTE_PREFIX
)
3633 if (is_space_char (*op_string
))
3635 i
.types
[this_operand
] |= JumpAbsolute
;
3638 /* Check if operand is a register. */
3639 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3640 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3642 /* Check for a segment override by searching for ':' after a
3643 segment register. */
3645 if (is_space_char (*op_string
))
3647 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3652 i
.seg
[i
.mem_operands
] = &es
;
3655 i
.seg
[i
.mem_operands
] = &cs
;
3658 i
.seg
[i
.mem_operands
] = &ss
;
3661 i
.seg
[i
.mem_operands
] = &ds
;
3664 i
.seg
[i
.mem_operands
] = &fs
;
3667 i
.seg
[i
.mem_operands
] = &gs
;
3671 /* Skip the ':' and whitespace. */
3673 if (is_space_char (*op_string
))
3676 if (!is_digit_char (*op_string
)
3677 && !is_identifier_char (*op_string
)
3678 && *op_string
!= '('
3679 && *op_string
!= ABSOLUTE_PREFIX
)
3681 as_bad (_("bad memory operand `%s'"), op_string
);
3684 /* Handle case of %es:*foo. */
3685 if (*op_string
== ABSOLUTE_PREFIX
)
3688 if (is_space_char (*op_string
))
3690 i
.types
[this_operand
] |= JumpAbsolute
;
3692 goto do_memory_reference
;
3696 as_bad (_("junk `%s' after register"), op_string
);
3699 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3700 i
.op
[this_operand
].regs
= r
;
3703 else if (*op_string
== REGISTER_PREFIX
)
3705 as_bad (_("bad register name `%s'"), op_string
);
3708 else if (*op_string
== IMMEDIATE_PREFIX
)
3711 if (i
.types
[this_operand
] & JumpAbsolute
)
3713 as_bad (_("immediate operand illegal with absolute jump"));
3716 if (!i386_immediate (op_string
))
3719 else if (is_digit_char (*op_string
)
3720 || is_identifier_char (*op_string
)
3721 || *op_string
== '(')
3723 /* This is a memory reference of some sort. */
3726 /* Start and end of displacement string expression (if found). */
3727 char *displacement_string_start
;
3728 char *displacement_string_end
;
3730 do_memory_reference
:
3731 if ((i
.mem_operands
== 1
3732 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3733 || i
.mem_operands
== 2)
3735 as_bad (_("too many memory references for `%s'"),
3736 current_templates
->start
->name
);
3740 /* Check for base index form. We detect the base index form by
3741 looking for an ')' at the end of the operand, searching
3742 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3744 base_string
= op_string
+ strlen (op_string
);
3747 if (is_space_char (*base_string
))
3750 /* If we only have a displacement, set-up for it to be parsed later. */
3751 displacement_string_start
= op_string
;
3752 displacement_string_end
= base_string
+ 1;
3754 if (*base_string
== ')')
3757 unsigned int parens_balanced
= 1;
3758 /* We've already checked that the number of left & right ()'s are
3759 equal, so this loop will not be infinite. */
3763 if (*base_string
== ')')
3765 if (*base_string
== '(')
3768 while (parens_balanced
);
3770 temp_string
= base_string
;
3772 /* Skip past '(' and whitespace. */
3774 if (is_space_char (*base_string
))
3777 if (*base_string
== ','
3778 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3779 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3781 displacement_string_end
= temp_string
;
3783 i
.types
[this_operand
] |= BaseIndex
;
3787 base_string
= end_op
;
3788 if (is_space_char (*base_string
))
3792 /* There may be an index reg or scale factor here. */
3793 if (*base_string
== ',')
3796 if (is_space_char (*base_string
))
3799 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3800 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3802 base_string
= end_op
;
3803 if (is_space_char (*base_string
))
3805 if (*base_string
== ',')
3808 if (is_space_char (*base_string
))
3811 else if (*base_string
!= ')')
3813 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3818 else if (*base_string
== REGISTER_PREFIX
)
3820 as_bad (_("bad register name `%s'"), base_string
);
3824 /* Check for scale factor. */
3825 if (*base_string
!= ')')
3827 char *end_scale
= i386_scale (base_string
);
3832 base_string
= end_scale
;
3833 if (is_space_char (*base_string
))
3835 if (*base_string
!= ')')
3837 as_bad (_("expecting `)' after scale factor in `%s'"),
3842 else if (!i
.index_reg
)
3844 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3849 else if (*base_string
!= ')')
3851 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3856 else if (*base_string
== REGISTER_PREFIX
)
3858 as_bad (_("bad register name `%s'"), base_string
);
3863 /* If there's an expression beginning the operand, parse it,
3864 assuming displacement_string_start and
3865 displacement_string_end are meaningful. */
3866 if (displacement_string_start
!= displacement_string_end
)
3868 if (!i386_displacement (displacement_string_start
,
3869 displacement_string_end
))
3873 /* Special case for (%dx) while doing input/output op. */
3875 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3877 && i
.log2_scale_factor
== 0
3878 && i
.seg
[i
.mem_operands
] == 0
3879 && (i
.types
[this_operand
] & Disp
) == 0)
3881 i
.types
[this_operand
] = InOutPortReg
;
3885 if (i386_index_check (operand_string
) == 0)
3891 /* It's not a memory operand; argh! */
3892 as_bad (_("invalid char %s beginning operand %d `%s'"),
3893 output_invalid (*op_string
),
3898 return 1; /* Normal return. */
3901 /* md_estimate_size_before_relax()
3903 Called just before relax() for rs_machine_dependent frags. The x86
3904 assembler uses these frags to handle variable size jump
3907 Any symbol that is now undefined will not become defined.
3908 Return the correct fr_subtype in the frag.
3909 Return the initial "guess for variable size of frag" to caller.
3910 The guess is actually the growth beyond the fixed part. Whatever
3911 we do to grow the fixed or variable part contributes to our
3915 md_estimate_size_before_relax (fragP
, segment
)
3916 register fragS
*fragP
;
3917 register segT segment
;
3919 /* We've already got fragP->fr_subtype right; all we have to do is
3920 check for un-relaxable symbols. On an ELF system, we can't relax
3921 an externally visible symbol, because it may be overridden by a
3923 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3924 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3925 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3926 || S_IS_WEAK (fragP
->fr_symbol
)
3930 /* Symbol is undefined in this segment, or we need to keep a
3931 reloc so that weak symbols can be overridden. */
3932 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3933 RELOC_ENUM reloc_type
;
3934 unsigned char *opcode
;
3937 if (fragP
->fr_var
!= NO_RELOC
)
3938 reloc_type
= fragP
->fr_var
;
3940 reloc_type
= BFD_RELOC_16_PCREL
;
3942 reloc_type
= BFD_RELOC_32_PCREL
;
3944 old_fr_fix
= fragP
->fr_fix
;
3945 opcode
= (unsigned char *) fragP
->fr_opcode
;
3947 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3950 /* Make jmp (0xeb) a (d)word displacement jump. */
3952 fragP
->fr_fix
+= size
;
3953 fix_new (fragP
, old_fr_fix
, size
,
3955 fragP
->fr_offset
, 1,
3960 if (no_cond_jump_promotion
)
3965 /* Negate the condition, and branch past an
3966 unconditional jump. */
3969 /* Insert an unconditional jump. */
3971 /* We added two extra opcode bytes, and have a two byte
3973 fragP
->fr_fix
+= 2 + 2;
3974 fix_new (fragP
, old_fr_fix
+ 2, 2,
3976 fragP
->fr_offset
, 1,
3983 if (no_cond_jump_promotion
)
3986 /* This changes the byte-displacement jump 0x7N
3987 to the (d)word-displacement jump 0x0f,0x8N. */
3988 opcode
[1] = opcode
[0] + 0x10;
3989 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3990 /* We've added an opcode byte. */
3991 fragP
->fr_fix
+= 1 + size
;
3992 fix_new (fragP
, old_fr_fix
+ 1, size
,
3994 fragP
->fr_offset
, 1,
3999 BAD_CASE (fragP
->fr_subtype
);
4003 return fragP
->fr_fix
- old_fr_fix
;
4007 /* Guess size depending on current relax state. Initially the relax
4008 state will correspond to a short jump and we return 1, because
4009 the variable part of the frag (the branch offset) is one byte
4010 long. However, we can relax a section more than once and in that
4011 case we must either set fr_subtype back to the unrelaxed state,
4012 or return the value for the appropriate branch. */
4013 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4016 /* Called after relax() is finished.
4018 In: Address of frag.
4019 fr_type == rs_machine_dependent.
4020 fr_subtype is what the address relaxed to.
4022 Out: Any fixSs and constants are set up.
4023 Caller will turn frag into a ".space 0". */
4025 #ifndef BFD_ASSEMBLER
4027 md_convert_frag (headers
, sec
, fragP
)
4028 object_headers
*headers ATTRIBUTE_UNUSED
;
4029 segT sec ATTRIBUTE_UNUSED
;
4030 register fragS
*fragP
;
4033 md_convert_frag (abfd
, sec
, fragP
)
4034 bfd
*abfd ATTRIBUTE_UNUSED
;
4035 segT sec ATTRIBUTE_UNUSED
;
4036 register fragS
*fragP
;
4039 register unsigned char *opcode
;
4040 unsigned char *where_to_put_displacement
= NULL
;
4041 offsetT target_address
;
4042 offsetT opcode_address
;
4043 unsigned int extension
= 0;
4044 offsetT displacement_from_opcode_start
;
4046 opcode
= (unsigned char *) fragP
->fr_opcode
;
4048 /* Address we want to reach in file space. */
4049 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4050 #ifdef BFD_ASSEMBLER
4051 /* Not needed otherwise? */
4053 /* Local symbols which have already been resolved have a NULL frag. */
4054 fragS
*sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4056 target_address
+= sym_frag
->fr_address
;
4060 /* Address opcode resides at in file space. */
4061 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4063 /* Displacement from opcode start to fill into instruction. */
4064 displacement_from_opcode_start
= target_address
- opcode_address
;
4066 if ((fragP
->fr_subtype
& BIG
) == 0)
4068 /* Don't have to change opcode. */
4069 extension
= 1; /* 1 opcode + 1 displacement */
4070 where_to_put_displacement
= &opcode
[1];
4074 if (no_cond_jump_promotion
4075 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4076 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4078 switch (fragP
->fr_subtype
)
4080 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4081 extension
= 4; /* 1 opcode + 4 displacement */
4083 where_to_put_displacement
= &opcode
[1];
4086 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4087 extension
= 2; /* 1 opcode + 2 displacement */
4089 where_to_put_displacement
= &opcode
[1];
4092 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4093 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4094 extension
= 5; /* 2 opcode + 4 displacement */
4095 opcode
[1] = opcode
[0] + 0x10;
4096 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4097 where_to_put_displacement
= &opcode
[2];
4100 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4101 extension
= 3; /* 2 opcode + 2 displacement */
4102 opcode
[1] = opcode
[0] + 0x10;
4103 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4104 where_to_put_displacement
= &opcode
[2];
4107 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4112 where_to_put_displacement
= &opcode
[3];
4116 BAD_CASE (fragP
->fr_subtype
);
4121 /* Now put displacement after opcode. */
4122 md_number_to_chars ((char *) where_to_put_displacement
,
4123 (valueT
) (displacement_from_opcode_start
- extension
),
4124 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4125 fragP
->fr_fix
+= extension
;
4128 /* Size of byte displacement jmp. */
4129 int md_short_jump_size
= 2;
4131 /* Size of dword displacement jmp. */
4132 int md_long_jump_size
= 5;
4134 /* Size of relocation record. */
4135 const int md_reloc_size
= 8;
4138 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4140 addressT from_addr
, to_addr
;
4141 fragS
*frag ATTRIBUTE_UNUSED
;
4142 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4146 offset
= to_addr
- (from_addr
+ 2);
4147 /* Opcode for byte-disp jump. */
4148 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4149 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4153 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4155 addressT from_addr
, to_addr
;
4156 fragS
*frag ATTRIBUTE_UNUSED
;
4157 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4161 offset
= to_addr
- (from_addr
+ 5);
4162 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4163 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4166 /* Apply a fixup (fixS) to segment data, once it has been determined
4167 by our caller that we have all the info we need to fix it up.
4169 On the 386, immediates, displacements, and data pointers are all in
4170 the same (little-endian) format, so we don't need to care about which
4174 md_apply_fix3 (fixP
, valp
, seg
)
4175 /* The fix we're to put in. */
4178 /* Pointer to the value of the bits. */
4181 /* Segment fix is from. */
4182 segT seg ATTRIBUTE_UNUSED
;
4184 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4185 valueT value
= *valp
;
4187 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4190 switch (fixP
->fx_r_type
)
4196 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4199 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4202 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4207 /* This is a hack. There should be a better way to handle this.
4208 This covers for the fact that bfd_install_relocation will
4209 subtract the current location (for partial_inplace, PC relative
4210 relocations); see more below. */
4211 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4212 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4213 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4214 && fixP
->fx_addsy
&& !use_rela_relocations
)
4217 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4219 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4222 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4224 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4225 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4227 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4230 || (symbol_section_p (fixP
->fx_addsy
)
4231 && fseg
!= absolute_section
))
4232 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4233 && ! S_IS_WEAK (fixP
->fx_addsy
)
4234 && S_IS_DEFINED (fixP
->fx_addsy
)
4235 && ! S_IS_COMMON (fixP
->fx_addsy
))
4237 /* Yes, we add the values in twice. This is because
4238 bfd_perform_relocation subtracts them out again. I think
4239 bfd_perform_relocation is broken, but I don't dare change
4241 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4245 #if defined (OBJ_COFF) && defined (TE_PE)
4246 /* For some reason, the PE format does not store a section
4247 address offset for a PC relative symbol. */
4248 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4249 value
+= md_pcrel_from (fixP
);
4253 /* Fix a few things - the dynamic linker expects certain values here,
4254 and we must not dissappoint it. */
4255 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4256 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4258 switch (fixP
->fx_r_type
)
4260 case BFD_RELOC_386_PLT32
:
4261 case BFD_RELOC_X86_64_PLT32
:
4262 /* Make the jump instruction point to the address of the operand. At
4263 runtime we merely add the offset to the actual PLT entry. */
4266 case BFD_RELOC_386_GOTPC
:
4268 /* This is tough to explain. We end up with this one if we have
4269 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4270 * here is to obtain the absolute address of the GOT, and it is strongly
4271 * preferable from a performance point of view to avoid using a runtime
4272 * relocation for this. The actual sequence of instructions often look
4278 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4280 * The call and pop essentially return the absolute address of
4281 * the label .L66 and store it in %ebx. The linker itself will
4282 * ultimately change the first operand of the addl so that %ebx points to
4283 * the GOT, but to keep things simple, the .o file must have this operand
4284 * set so that it generates not the absolute address of .L66, but the
4285 * absolute address of itself. This allows the linker itself simply
4286 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4287 * added in, and the addend of the relocation is stored in the operand
4288 * field for the instruction itself.
4290 * Our job here is to fix the operand so that it would add the correct
4291 * offset so that %ebx would point to itself. The thing that is tricky is
4292 * that .-.L66 will point to the beginning of the instruction, so we need
4293 * to further modify the operand so that it will point to itself.
4294 * There are other cases where you have something like:
4296 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4298 * and here no correction would be required. Internally in the assembler
4299 * we treat operands of this form as not being pcrel since the '.' is
4300 * explicitly mentioned, and I wonder whether it would simplify matters
4301 * to do it this way. Who knows. In earlier versions of the PIC patches,
4302 * the pcrel_adjust field was used to store the correction, but since the
4303 * expression is not pcrel, I felt it would be confusing to do it this
4308 case BFD_RELOC_386_GOT32
:
4309 case BFD_RELOC_X86_64_GOT32
:
4310 value
= 0; /* Fully resolved at runtime. No addend. */
4312 case BFD_RELOC_386_GOTOFF
:
4313 case BFD_RELOC_X86_64_GOTPCREL
:
4316 case BFD_RELOC_VTABLE_INHERIT
:
4317 case BFD_RELOC_VTABLE_ENTRY
:
4324 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4326 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4328 #ifndef BFD_ASSEMBLER
4329 md_number_to_chars (p
, value
, fixP
->fx_size
);
4331 /* Are we finished with this relocation now? */
4332 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4334 else if (use_rela_relocations
)
4336 fixP
->fx_no_overflow
= 1;
4339 md_number_to_chars (p
, value
, fixP
->fx_size
);
4345 #define MAX_LITTLENUMS 6
4347 /* Turn the string pointed to by litP into a floating point constant
4348 of type TYPE, and emit the appropriate bytes. The number of
4349 LITTLENUMS emitted is stored in *SIZEP. An error message is
4350 returned, or NULL on OK. */
4353 md_atof (type
, litP
, sizeP
)
4359 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4360 LITTLENUM_TYPE
*wordP
;
4382 return _("Bad call to md_atof ()");
4384 t
= atof_ieee (input_line_pointer
, type
, words
);
4386 input_line_pointer
= t
;
4388 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4389 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4390 the bigendian 386. */
4391 for (wordP
= words
+ prec
- 1; prec
--;)
4393 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4394 litP
+= sizeof (LITTLENUM_TYPE
);
4399 char output_invalid_buf
[8];
4406 sprintf (output_invalid_buf
, "'%c'", c
);
4408 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4409 return output_invalid_buf
;
4412 /* REG_STRING starts *before* REGISTER_PREFIX. */
4414 static const reg_entry
*
4415 parse_register (reg_string
, end_op
)
4419 char *s
= reg_string
;
4421 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4424 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4425 if (*s
== REGISTER_PREFIX
)
4428 if (is_space_char (*s
))
4432 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4434 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4435 return (const reg_entry
*) NULL
;
4439 /* For naked regs, make sure that we are not dealing with an identifier.
4440 This prevents confusing an identifier like `eax_var' with register
4442 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4443 return (const reg_entry
*) NULL
;
4447 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4449 /* Handle floating point regs, allowing spaces in the (i) part. */
4450 if (r
== i386_regtab
/* %st is first entry of table */)
4452 if (is_space_char (*s
))
4457 if (is_space_char (*s
))
4459 if (*s
>= '0' && *s
<= '7')
4461 r
= &i386_float_regtab
[*s
- '0'];
4463 if (is_space_char (*s
))
4471 /* We have "%st(" then garbage. */
4472 return (const reg_entry
*) NULL
;
4479 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4480 const char *md_shortopts
= "kVQ:sq";
4482 const char *md_shortopts
= "q";
4485 struct option md_longopts
[] = {
4486 #define OPTION_32 (OPTION_MD_BASE + 0)
4487 {"32", no_argument
, NULL
, OPTION_32
},
4488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4489 #define OPTION_64 (OPTION_MD_BASE + 1)
4490 {"64", no_argument
, NULL
, OPTION_64
},
4492 {NULL
, no_argument
, NULL
, 0}
4494 size_t md_longopts_size
= sizeof (md_longopts
);
4497 md_parse_option (c
, arg
)
4499 char *arg ATTRIBUTE_UNUSED
;
4507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4508 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4509 should be emitted or not. FIXME: Not implemented. */
4513 /* -V: SVR4 argument to print version ID. */
4515 print_version_id ();
4518 /* -k: Ignore for FreeBSD compatibility. */
4523 /* -s: On i386 Solaris, this tells the native assembler to use
4524 .stab instead of .stab.excl. We always use .stab anyhow. */
4529 const char **list
, **l
;
4531 list
= bfd_target_list ();
4532 for (l
= list
; *l
!= NULL
; l
++)
4533 if (strcmp (*l
, "elf64-x86-64") == 0)
4535 default_arch
= "x86_64";
4539 as_fatal (_("No compiled in support for x86_64"));
4546 default_arch
= "i386";
4556 md_show_usage (stream
)
4559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4560 fprintf (stream
, _("\
4562 -V print assembler version number\n\
4564 -q quieten some warnings\n\
4567 fprintf (stream
, _("\
4568 -q quieten some warnings\n"));
4572 #ifdef BFD_ASSEMBLER
4573 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4574 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4576 /* Pick the target format to use. */
4579 i386_target_format ()
4581 if (!strcmp (default_arch
, "x86_64"))
4582 set_code_flag (CODE_64BIT
);
4583 else if (!strcmp (default_arch
, "i386"))
4584 set_code_flag (CODE_32BIT
);
4586 as_fatal (_("Unknown architecture"));
4587 switch (OUTPUT_FLAVOR
)
4589 #ifdef OBJ_MAYBE_AOUT
4590 case bfd_target_aout_flavour
:
4591 return AOUT_TARGET_FORMAT
;
4593 #ifdef OBJ_MAYBE_COFF
4594 case bfd_target_coff_flavour
:
4597 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4598 case bfd_target_elf_flavour
:
4600 if (flag_code
== CODE_64BIT
)
4601 use_rela_relocations
= 1;
4602 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4611 #endif /* OBJ_MAYBE_ more than one */
4612 #endif /* BFD_ASSEMBLER */
4615 md_undefined_symbol (name
)
4618 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4619 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4620 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4621 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4625 if (symbol_find (name
))
4626 as_bad (_("GOT already in symbol table"));
4627 GOT_symbol
= symbol_new (name
, undefined_section
,
4628 (valueT
) 0, &zero_address_frag
);
4635 /* Round up a section size to the appropriate boundary. */
4638 md_section_align (segment
, size
)
4639 segT segment ATTRIBUTE_UNUSED
;
4642 #ifdef BFD_ASSEMBLER
4643 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4644 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4646 /* For a.out, force the section size to be aligned. If we don't do
4647 this, BFD will align it for us, but it will not write out the
4648 final bytes of the section. This may be a bug in BFD, but it is
4649 easier to fix it here since that is how the other a.out targets
4653 align
= bfd_get_section_alignment (stdoutput
, segment
);
4654 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4662 /* On the i386, PC-relative offsets are relative to the start of the
4663 next instruction. That is, the address of the offset, plus its
4664 size, since the offset is always the last part of the insn. */
4667 md_pcrel_from (fixP
)
4670 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4677 int ignore ATTRIBUTE_UNUSED
;
4681 temp
= get_absolute_expression ();
4682 subseg_set (bss_section
, (subsegT
) temp
);
4683 demand_empty_rest_of_line ();
4688 #ifdef BFD_ASSEMBLER
4691 i386_validate_fix (fixp
)
4694 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4696 /* GOTOFF relocation are nonsense in 64bit mode. */
4697 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4699 if (flag_code
!= CODE_64BIT
)
4701 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4705 if (flag_code
== CODE_64BIT
)
4707 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4714 tc_gen_reloc (section
, fixp
)
4715 asection
*section ATTRIBUTE_UNUSED
;
4719 bfd_reloc_code_real_type code
;
4721 switch (fixp
->fx_r_type
)
4723 case BFD_RELOC_X86_64_PLT32
:
4724 case BFD_RELOC_X86_64_GOT32
:
4725 case BFD_RELOC_X86_64_GOTPCREL
:
4726 case BFD_RELOC_386_PLT32
:
4727 case BFD_RELOC_386_GOT32
:
4728 case BFD_RELOC_386_GOTOFF
:
4729 case BFD_RELOC_386_GOTPC
:
4730 case BFD_RELOC_X86_64_32S
:
4732 case BFD_RELOC_VTABLE_ENTRY
:
4733 case BFD_RELOC_VTABLE_INHERIT
:
4734 code
= fixp
->fx_r_type
;
4739 switch (fixp
->fx_size
)
4742 as_bad (_("can not do %d byte pc-relative relocation"),
4744 code
= BFD_RELOC_32_PCREL
;
4746 case 1: code
= BFD_RELOC_8_PCREL
; break;
4747 case 2: code
= BFD_RELOC_16_PCREL
; break;
4748 case 4: code
= BFD_RELOC_32_PCREL
; break;
4753 switch (fixp
->fx_size
)
4756 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4757 code
= BFD_RELOC_32
;
4759 case 1: code
= BFD_RELOC_8
; break;
4760 case 2: code
= BFD_RELOC_16
; break;
4761 case 4: code
= BFD_RELOC_32
; break;
4762 case 8: code
= BFD_RELOC_64
; break;
4768 if (code
== BFD_RELOC_32
4770 && fixp
->fx_addsy
== GOT_symbol
)
4772 /* We don't support GOTPC on 64bit targets. */
4773 if (flag_code
== CODE_64BIT
)
4775 code
= BFD_RELOC_386_GOTPC
;
4778 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4779 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4780 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4782 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4783 if (!use_rela_relocations
)
4785 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4786 vtable entry to be used in the relocation's section offset. */
4787 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4788 rel
->address
= fixp
->fx_offset
;
4791 rel
->addend
= fixp
->fx_addnumber
;
4795 /* Use the rela in 64bit mode. */
4798 rel
->addend
= fixp
->fx_offset
;
4800 rel
->addend
-= fixp
->fx_size
;
4803 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4804 if (rel
->howto
== NULL
)
4806 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4807 _("cannot represent relocation type %s"),
4808 bfd_get_reloc_code_name (code
));
4809 /* Set howto to a garbage value so that we can keep going. */
4810 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4811 assert (rel
->howto
!= NULL
);
4817 #else /* ! BFD_ASSEMBLER */
4819 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4821 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4824 relax_addressT segment_address_in_file
;
4826 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4827 Out: GNU LD relocation length code: 0, 1, or 2. */
4829 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4832 know (fixP
->fx_addsy
!= NULL
);
4834 md_number_to_chars (where
,
4835 (valueT
) (fixP
->fx_frag
->fr_address
4836 + fixP
->fx_where
- segment_address_in_file
),
4839 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4840 ? S_GET_TYPE (fixP
->fx_addsy
)
4841 : fixP
->fx_addsy
->sy_number
);
4843 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4844 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4845 where
[4] = r_symbolnum
& 0x0ff;
4846 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4847 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4848 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4851 #endif /* OBJ_AOUT or OBJ_BOUT. */
4853 #if defined (I386COFF)
4856 tc_coff_fix2rtype (fixP
)
4859 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4862 return (fixP
->fx_pcrel
?
4863 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4864 fixP
->fx_size
== 2 ? R_PCRWORD
:
4866 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4867 fixP
->fx_size
== 2 ? R_RELWORD
:
4872 tc_coff_sizemachdep (frag
)
4876 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4881 #endif /* I386COFF */
4883 #endif /* ! BFD_ASSEMBLER */
4885 /* Parse operands using Intel syntax. This implements a recursive descent
4886 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4889 FIXME: We do not recognize the full operand grammar defined in the MASM
4890 documentation. In particular, all the structure/union and
4891 high-level macro operands are missing.
4893 Uppercase words are terminals, lower case words are non-terminals.
4894 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4895 bars '|' denote choices. Most grammar productions are implemented in
4896 functions called 'intel_<production>'.
4898 Initial production is 'expr'.
4904 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4906 constant digits [[ radixOverride ]]
4908 dataType BYTE | WORD | DWORD | QWORD | XWORD
4941 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4942 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4944 hexdigit a | b | c | d | e | f
4945 | A | B | C | D | E | F
4955 register specialRegister
4959 segmentRegister CS | DS | ES | FS | GS | SS
4961 specialRegister CR0 | CR2 | CR3
4962 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4963 | TR3 | TR4 | TR5 | TR6 | TR7
4965 We simplify the grammar in obvious places (e.g., register parsing is
4966 done by calling parse_register) and eliminate immediate left recursion
4967 to implement a recursive-descent parser.
5007 /* Parsing structure for the intel syntax parser. Used to implement the
5008 semantic actions for the operand grammar. */
5009 struct intel_parser_s
5011 char *op_string
; /* The string being parsed. */
5012 int got_a_float
; /* Whether the operand is a float. */
5013 int op_modifier
; /* Operand modifier. */
5014 int is_mem
; /* 1 if operand is memory reference. */
5015 const reg_entry
*reg
; /* Last register reference found. */
5016 char *disp
; /* Displacement string being built. */
5019 static struct intel_parser_s intel_parser
;
5021 /* Token structure for parsing intel syntax. */
5024 int code
; /* Token code. */
5025 const reg_entry
*reg
; /* Register entry for register tokens. */
5026 char *str
; /* String representation. */
5029 static struct intel_token cur_token
, prev_token
;
5031 /* Token codes for the intel parser. Since T_SHORT is already used
5032 by COFF, undefine it first to prevent a warning. */
5047 /* Prototypes for intel parser functions. */
5048 static int intel_match_token
PARAMS ((int code
));
5049 static void intel_get_token
PARAMS ((void));
5050 static void intel_putback_token
PARAMS ((void));
5051 static int intel_expr
PARAMS ((void));
5052 static int intel_e05
PARAMS ((void));
5053 static int intel_e05_1
PARAMS ((void));
5054 static int intel_e06
PARAMS ((void));
5055 static int intel_e06_1
PARAMS ((void));
5056 static int intel_e09
PARAMS ((void));
5057 static int intel_e09_1
PARAMS ((void));
5058 static int intel_e10
PARAMS ((void));
5059 static int intel_e10_1
PARAMS ((void));
5060 static int intel_e11
PARAMS ((void));
5063 i386_intel_operand (operand_string
, got_a_float
)
5064 char *operand_string
;
5070 /* Initialize token holders. */
5071 cur_token
.code
= prev_token
.code
= T_NIL
;
5072 cur_token
.reg
= prev_token
.reg
= NULL
;
5073 cur_token
.str
= prev_token
.str
= NULL
;
5075 /* Initialize parser structure. */
5076 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5079 strcpy (intel_parser
.op_string
, operand_string
);
5080 intel_parser
.got_a_float
= got_a_float
;
5081 intel_parser
.op_modifier
= -1;
5082 intel_parser
.is_mem
= 0;
5083 intel_parser
.reg
= NULL
;
5084 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5085 if (intel_parser
.disp
== NULL
)
5087 intel_parser
.disp
[0] = '\0';
5089 /* Read the first token and start the parser. */
5091 ret
= intel_expr ();
5095 /* If we found a memory reference, hand it over to i386_displacement
5096 to fill in the rest of the operand fields. */
5097 if (intel_parser
.is_mem
)
5099 if ((i
.mem_operands
== 1
5100 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5101 || i
.mem_operands
== 2)
5103 as_bad (_("too many memory references for '%s'"),
5104 current_templates
->start
->name
);
5109 char *s
= intel_parser
.disp
;
5112 /* Add the displacement expression. */
5114 ret
= i386_displacement (s
, s
+ strlen (s
))
5115 && i386_index_check (s
);
5119 /* Constant and OFFSET expressions are handled by i386_immediate. */
5120 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5121 || intel_parser
.reg
== NULL
)
5122 ret
= i386_immediate (intel_parser
.disp
);
5126 free (intel_parser
.disp
);
5136 /* expr SHORT e05 */
5137 if (cur_token
.code
== T_SHORT
)
5139 intel_parser
.op_modifier
= SHORT
;
5140 intel_match_token (T_SHORT
);
5142 return (intel_e05 ());
5147 return intel_e05 ();
5157 return (intel_e06 () && intel_e05_1 ());
5163 /* e05' addOp e06 e05' */
5164 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5166 strcat (intel_parser
.disp
, cur_token
.str
);
5167 intel_match_token (cur_token
.code
);
5169 return (intel_e06 () && intel_e05_1 ());
5184 return (intel_e09 () && intel_e06_1 ());
5190 /* e06' mulOp e09 e06' */
5191 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5193 strcat (intel_parser
.disp
, cur_token
.str
);
5194 intel_match_token (cur_token
.code
);
5196 return (intel_e09 () && intel_e06_1 ());
5204 /* e09 OFFSET e10 e09'
5213 /* e09 OFFSET e10 e09' */
5214 if (cur_token
.code
== T_OFFSET
)
5216 intel_parser
.is_mem
= 0;
5217 intel_parser
.op_modifier
= OFFSET_FLAT
;
5218 intel_match_token (T_OFFSET
);
5220 return (intel_e10 () && intel_e09_1 ());
5225 return (intel_e10 () && intel_e09_1 ());
5231 /* e09' PTR e10 e09' */
5232 if (cur_token
.code
== T_PTR
)
5234 if (prev_token
.code
== T_BYTE
)
5235 i
.suffix
= BYTE_MNEM_SUFFIX
;
5237 else if (prev_token
.code
== T_WORD
)
5239 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5240 i
.suffix
= SHORT_MNEM_SUFFIX
;
5242 i
.suffix
= WORD_MNEM_SUFFIX
;
5245 else if (prev_token
.code
== T_DWORD
)
5247 if (intel_parser
.got_a_float
== 1) /* "f..." */
5248 i
.suffix
= SHORT_MNEM_SUFFIX
;
5250 i
.suffix
= LONG_MNEM_SUFFIX
;
5253 else if (prev_token
.code
== T_QWORD
)
5255 if (intel_parser
.got_a_float
== 1) /* "f..." */
5256 i
.suffix
= LONG_MNEM_SUFFIX
;
5258 i
.suffix
= QWORD_MNEM_SUFFIX
;
5261 else if (prev_token
.code
== T_XWORD
)
5262 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5266 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5270 intel_match_token (T_PTR
);
5272 return (intel_e10 () && intel_e09_1 ());
5275 /* e09 : e10 e09' */
5276 else if (cur_token
.code
== ':')
5278 /* Mark as a memory operand only if it's not already known to be an
5279 offset expression. */
5280 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5281 intel_parser
.is_mem
= 1;
5283 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5298 return (intel_e11 () && intel_e10_1 ());
5304 /* e10' [ expr ] e10' */
5305 if (cur_token
.code
== '[')
5307 intel_match_token ('[');
5309 /* Mark as a memory operand only if it's not already known to be an
5310 offset expression. If it's an offset expression, we need to keep
5312 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5313 intel_parser
.is_mem
= 1;
5315 strcat (intel_parser
.disp
, "[");
5317 /* Add a '+' to the displacement string if necessary. */
5318 if (*intel_parser
.disp
!= '\0'
5319 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5320 strcat (intel_parser
.disp
, "+");
5322 if (intel_expr () && intel_match_token (']'))
5324 /* Preserve brackets when the operand is an offset expression. */
5325 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5326 strcat (intel_parser
.disp
, "]");
5328 return intel_e10_1 ();
5355 if (cur_token
.code
== '(')
5357 intel_match_token ('(');
5358 strcat (intel_parser
.disp
, "(");
5360 if (intel_expr () && intel_match_token (')'))
5362 strcat (intel_parser
.disp
, ")");
5370 else if (cur_token
.code
== '[')
5372 intel_match_token ('[');
5374 /* Mark as a memory operand only if it's not already known to be an
5375 offset expression. If it's an offset expression, we need to keep
5377 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5378 intel_parser
.is_mem
= 1;
5380 strcat (intel_parser
.disp
, "[");
5382 /* Operands for jump/call inside brackets denote absolute addresses. */
5383 if (current_templates
->start
->opcode_modifier
& Jump
5384 || current_templates
->start
->opcode_modifier
& JumpDword
5385 || current_templates
->start
->opcode_modifier
& JumpByte
5386 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5387 i
.types
[this_operand
] |= JumpAbsolute
;
5389 /* Add a '+' to the displacement string if necessary. */
5390 if (*intel_parser
.disp
!= '\0'
5391 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5392 strcat (intel_parser
.disp
, "+");
5394 if (intel_expr () && intel_match_token (']'))
5396 /* Preserve brackets when the operand is an offset expression. */
5397 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5398 strcat (intel_parser
.disp
, "]");
5411 else if (cur_token
.code
== T_BYTE
5412 || cur_token
.code
== T_WORD
5413 || cur_token
.code
== T_DWORD
5414 || cur_token
.code
== T_QWORD
5415 || cur_token
.code
== T_XWORD
)
5417 intel_match_token (cur_token
.code
);
5424 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5426 strcat (intel_parser
.disp
, cur_token
.str
);
5427 intel_match_token (cur_token
.code
);
5429 /* Mark as a memory operand only if it's not already known to be an
5430 offset expression. */
5431 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5432 intel_parser
.is_mem
= 1;
5438 else if (cur_token
.code
== T_REG
)
5440 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5442 intel_match_token (T_REG
);
5444 /* Check for segment change. */
5445 if (cur_token
.code
== ':')
5447 if (reg
->reg_type
& (SReg2
| SReg3
))
5449 switch (reg
->reg_num
)
5452 i
.seg
[i
.mem_operands
] = &es
;
5455 i
.seg
[i
.mem_operands
] = &cs
;
5458 i
.seg
[i
.mem_operands
] = &ss
;
5461 i
.seg
[i
.mem_operands
] = &ds
;
5464 i
.seg
[i
.mem_operands
] = &fs
;
5467 i
.seg
[i
.mem_operands
] = &gs
;
5473 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5478 /* Not a segment register. Check for register scaling. */
5479 else if (cur_token
.code
== '*')
5481 if (!intel_parser
.is_mem
)
5483 as_bad (_("Register scaling only allowed in memory operands."));
5487 /* What follows must be a valid scale. */
5488 if (intel_match_token ('*')
5489 && strchr ("01248", *cur_token
.str
))
5492 i
.types
[this_operand
] |= BaseIndex
;
5494 /* Set the scale after setting the register (otherwise,
5495 i386_scale will complain) */
5496 i386_scale (cur_token
.str
);
5497 intel_match_token (T_CONST
);
5501 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5507 /* No scaling. If this is a memory operand, the register is either a
5508 base register (first occurrence) or an index register (second
5510 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5512 if (i
.base_reg
&& i
.index_reg
)
5514 as_bad (_("Too many register references in memory operand.\n"));
5518 if (i
.base_reg
== NULL
)
5523 i
.types
[this_operand
] |= BaseIndex
;
5526 /* Offset modifier. Add the register to the displacement string to be
5527 parsed as an immediate expression after we're done. */
5528 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5529 strcat (intel_parser
.disp
, reg
->reg_name
);
5531 /* It's neither base nor index nor offset. */
5534 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5535 i
.op
[this_operand
].regs
= reg
;
5539 /* Since registers are not part of the displacement string (except
5540 when we're parsing offset operands), we may need to remove any
5541 preceding '+' from the displacement string. */
5542 if (*intel_parser
.disp
!= '\0'
5543 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5545 char *s
= intel_parser
.disp
;
5546 s
+= strlen (s
) - 1;
5555 else if (cur_token
.code
== T_ID
)
5557 /* Add the identifier to the displacement string. */
5558 strcat (intel_parser
.disp
, cur_token
.str
);
5559 intel_match_token (T_ID
);
5561 /* The identifier represents a memory reference only if it's not
5562 preceded by an offset modifier. */
5563 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5564 intel_parser
.is_mem
= 1;
5570 else if (cur_token
.code
== T_CONST
5571 || cur_token
.code
== '-'
5572 || cur_token
.code
== '+')
5576 /* Allow constants that start with `+' or `-'. */
5577 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5579 strcat (intel_parser
.disp
, cur_token
.str
);
5580 intel_match_token (cur_token
.code
);
5581 if (cur_token
.code
!= T_CONST
)
5583 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5589 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5590 if (save_str
== NULL
)
5592 strcpy (save_str
, cur_token
.str
);
5594 /* Get the next token to check for register scaling. */
5595 intel_match_token (cur_token
.code
);
5597 /* Check if this constant is a scaling factor for an index register. */
5598 if (cur_token
.code
== '*')
5600 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5602 if (!intel_parser
.is_mem
)
5604 as_bad (_("Register scaling only allowed in memory operands."));
5608 /* The constant is followed by `* reg', so it must be
5610 if (strchr ("01248", *save_str
))
5612 i
.index_reg
= cur_token
.reg
;
5613 i
.types
[this_operand
] |= BaseIndex
;
5615 /* Set the scale after setting the register (otherwise,
5616 i386_scale will complain) */
5617 i386_scale (save_str
);
5618 intel_match_token (T_REG
);
5620 /* Since registers are not part of the displacement
5621 string, we may need to remove any preceding '+' from
5622 the displacement string. */
5623 if (*intel_parser
.disp
!= '\0')
5625 char *s
= intel_parser
.disp
;
5626 s
+= strlen (s
) - 1;
5639 /* The constant was not used for register scaling. Since we have
5640 already consumed the token following `*' we now need to put it
5641 back in the stream. */
5643 intel_putback_token ();
5646 /* Add the constant to the displacement string. */
5647 strcat (intel_parser
.disp
, save_str
);
5653 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5657 /* Match the given token against cur_token. If they match, read the next
5658 token from the operand string. */
5660 intel_match_token (code
)
5663 if (cur_token
.code
== code
)
5670 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5675 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5680 const reg_entry
*reg
;
5681 struct intel_token new_token
;
5683 new_token
.code
= T_NIL
;
5684 new_token
.reg
= NULL
;
5685 new_token
.str
= NULL
;
5687 /* Free the memory allocated to the previous token and move
5688 cur_token to prev_token. */
5690 free (prev_token
.str
);
5692 prev_token
= cur_token
;
5694 /* Skip whitespace. */
5695 while (is_space_char (*intel_parser
.op_string
))
5696 intel_parser
.op_string
++;
5698 /* Return an empty token if we find nothing else on the line. */
5699 if (*intel_parser
.op_string
== '\0')
5701 cur_token
= new_token
;
5705 /* The new token cannot be larger than the remainder of the operand
5707 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5708 if (new_token
.str
== NULL
)
5710 new_token
.str
[0] = '\0';
5712 if (strchr ("0123456789", *intel_parser
.op_string
))
5714 char *p
= new_token
.str
;
5715 char *q
= intel_parser
.op_string
;
5716 new_token
.code
= T_CONST
;
5718 /* Allow any kind of identifier char to encompass floating point and
5719 hexadecimal numbers. */
5720 while (is_identifier_char (*q
))
5724 /* Recognize special symbol names [0-9][bf]. */
5725 if (strlen (intel_parser
.op_string
) == 2
5726 && (intel_parser
.op_string
[1] == 'b'
5727 || intel_parser
.op_string
[1] == 'f'))
5728 new_token
.code
= T_ID
;
5731 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5733 new_token
.code
= *intel_parser
.op_string
;
5734 new_token
.str
[0] = *intel_parser
.op_string
;
5735 new_token
.str
[1] = '\0';
5738 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5739 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5741 new_token
.code
= T_REG
;
5742 new_token
.reg
= reg
;
5744 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5746 new_token
.str
[0] = REGISTER_PREFIX
;
5747 new_token
.str
[1] = '\0';
5750 strcat (new_token
.str
, reg
->reg_name
);
5753 else if (is_identifier_char (*intel_parser
.op_string
))
5755 char *p
= new_token
.str
;
5756 char *q
= intel_parser
.op_string
;
5758 /* A '.' or '$' followed by an identifier char is an identifier.
5759 Otherwise, it's operator '.' followed by an expression. */
5760 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5762 new_token
.code
= *q
;
5763 new_token
.str
[0] = *q
;
5764 new_token
.str
[1] = '\0';
5768 while (is_identifier_char (*q
) || *q
== '@')
5772 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5773 new_token
.code
= T_BYTE
;
5775 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5776 new_token
.code
= T_WORD
;
5778 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5779 new_token
.code
= T_DWORD
;
5781 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5782 new_token
.code
= T_QWORD
;
5784 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5785 new_token
.code
= T_XWORD
;
5787 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5788 new_token
.code
= T_PTR
;
5790 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5791 new_token
.code
= T_SHORT
;
5793 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5795 new_token
.code
= T_OFFSET
;
5797 /* ??? This is not mentioned in the MASM grammar but gcc
5798 makes use of it with -mintel-syntax. OFFSET may be
5799 followed by FLAT: */
5800 if (strncasecmp (q
, " FLAT:", 6) == 0)
5801 strcat (new_token
.str
, " FLAT:");
5804 /* ??? This is not mentioned in the MASM grammar. */
5805 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5806 new_token
.code
= T_OFFSET
;
5809 new_token
.code
= T_ID
;
5814 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5816 intel_parser
.op_string
+= strlen (new_token
.str
);
5817 cur_token
= new_token
;
5820 /* Put cur_token back into the token stream and make cur_token point to
5823 intel_putback_token ()
5825 intel_parser
.op_string
-= strlen (cur_token
.str
);
5826 free (cur_token
.str
);
5827 cur_token
= prev_token
;
5829 /* Forget prev_token. */
5830 prev_token
.code
= T_NIL
;
5831 prev_token
.reg
= NULL
;
5832 prev_token
.str
= NULL
;