1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
268 unsupported_with_intel_mnemonic
,
271 invalid_vsib_address
,
272 invalid_vector_register_set
,
273 unsupported_vector_index_register
,
274 unsupported_broadcast
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
312 #define Operand_Mem 2
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* Copied first memory operand string, for re-checking. */
330 /* PREFIX holds all the given prefix opcodes (usually null).
331 PREFIXES is the number of prefix opcodes. */
332 unsigned int prefixes
;
333 unsigned char prefix
[MAX_PREFIXES
];
335 /* RM and SIB are the modrm byte and the sib byte where the
336 addressing modes of this insn are encoded. */
343 /* Masking attributes. */
344 struct Mask_Operation
*mask
;
346 /* Rounding control and SAE attributes. */
347 struct RC_Operation
*rounding
;
349 /* Broadcasting attributes. */
350 struct Broadcast_Operation
*broadcast
;
352 /* Compressed disp8*N attribute. */
353 unsigned int memshift
;
355 /* Prefer load or store in encoding. */
358 dir_encoding_default
= 0,
363 /* Prefer 8bit or 32bit displacement in encoding. */
366 disp_encoding_default
= 0,
371 /* Prefer the REX byte in encoding. */
372 bfd_boolean rex_encoding
;
374 /* Disable instruction size optimization. */
375 bfd_boolean no_optimize
;
377 /* How to encode vector instructions. */
380 vex_encoding_default
= 0,
387 const char *rep_prefix
;
390 const char *hle_prefix
;
392 /* Have BND prefix. */
393 const char *bnd_prefix
;
395 /* Have NOTRACK prefix. */
396 const char *notrack_prefix
;
399 enum i386_error error
;
402 typedef struct _i386_insn i386_insn
;
404 /* Link RC type with corresponding string, that'll be looked for in
413 static const struct RC_name RC_NamesTable
[] =
415 { rne
, STRING_COMMA_LEN ("rn-sae") },
416 { rd
, STRING_COMMA_LEN ("rd-sae") },
417 { ru
, STRING_COMMA_LEN ("ru-sae") },
418 { rz
, STRING_COMMA_LEN ("rz-sae") },
419 { saeonly
, STRING_COMMA_LEN ("sae") },
422 /* List of chars besides those in app.c:symbol_chars that can start an
423 operand. Used to prevent the scrubber eating vital white-space. */
424 const char extra_symbol_chars
[] = "*%-([{}"
433 #if (defined (TE_I386AIX) \
434 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
435 && !defined (TE_GNU) \
436 && !defined (TE_LINUX) \
437 && !defined (TE_NACL) \
438 && !defined (TE_FreeBSD) \
439 && !defined (TE_DragonFly) \
440 && !defined (TE_NetBSD)))
441 /* This array holds the chars that always start a comment. If the
442 pre-processor is disabled, these aren't very useful. The option
443 --divide will remove '/' from this list. */
444 const char *i386_comment_chars
= "#/";
445 #define SVR4_COMMENT_CHARS 1
446 #define PREFIX_SEPARATOR '\\'
449 const char *i386_comment_chars
= "#";
450 #define PREFIX_SEPARATOR '/'
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output.
456 Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output.
459 Also note that comments started like this one will always work if
460 '/' isn't otherwise defined. */
461 const char line_comment_chars
[] = "#/";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant from exp in floating point
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant
472 const char FLT_CHARS
[] = "fFdDxX";
474 /* Tables for lexical analysis. */
475 static char mnemonic_chars
[256];
476 static char register_chars
[256];
477 static char operand_chars
[256];
478 static char identifier_chars
[256];
479 static char digit_chars
[256];
481 /* Lexical macros. */
482 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
483 #define is_operand_char(x) (operand_chars[(unsigned char) x])
484 #define is_register_char(x) (register_chars[(unsigned char) x])
485 #define is_space_char(x) ((x) == ' ')
486 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
487 #define is_digit_char(x) (digit_chars[(unsigned char) x])
489 /* All non-digit non-letter characters that may occur in an operand. */
490 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
492 /* md_assemble() always leaves the strings it's passed unaltered. To
493 effect this we maintain a stack of saved characters that we've smashed
494 with '\0's (indicating end of strings for various sub-fields of the
495 assembler instruction). */
496 static char save_stack
[32];
497 static char *save_stack_p
;
498 #define END_STRING_AND_SAVE(s) \
499 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
500 #define RESTORE_END_STRING(s) \
501 do { *(s) = *--save_stack_p; } while (0)
503 /* The instruction we're assembling. */
506 /* Possible templates for current insn. */
507 static const templates
*current_templates
;
509 /* Per instruction expressionS buffers: max displacements & immediates. */
510 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
511 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
513 /* Current operand we are working on. */
514 static int this_operand
= -1;
516 /* We support four different modes. FLAG_CODE variable is used to distinguish
524 static enum flag_code flag_code
;
525 static unsigned int object_64bit
;
526 static unsigned int disallow_64bit_reloc
;
527 static int use_rela_relocations
= 0;
529 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
530 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
531 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
533 /* The ELF ABI to use. */
541 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
544 #if defined (TE_PE) || defined (TE_PEP)
545 /* Use big object file format. */
546 static int use_big_obj
= 0;
549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 /* 1 if generating code for a shared library. */
551 static int shared
= 0;
554 /* 1 for intel syntax,
556 static int intel_syntax
= 0;
558 /* 1 for Intel64 ISA,
562 /* 1 for intel mnemonic,
563 0 if att mnemonic. */
564 static int intel_mnemonic
= !SYSV386_COMPAT
;
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg
= 0;
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg
= 0;
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
575 static int add_bnd_prefix
= 0;
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg
= 0;
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix
= 0;
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence
= 0;
588 /* 1 if the assembler should generate relax relocations. */
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
593 static enum check_kind
599 sse_check
, operand_check
= check_warning
;
602 1. Clear the REX_W bit with register operand if possible.
603 2. Above plus use 128bit vector instruction to clear the full vector
606 static int optimize
= 0;
609 1. Clear the REX_W bit with register operand if possible.
610 2. Above plus use 128bit vector instruction to clear the full vector
612 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
615 static int optimize_for_space
= 0;
617 /* Register prefix used for error message. */
618 static const char *register_prefix
= "%";
620 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
621 leave, push, and pop instructions so that gcc has the same stack
622 frame as in 32 bit mode. */
623 static char stackop_size
= '\0';
625 /* Non-zero to optimize code alignment. */
626 int optimize_align_code
= 1;
628 /* Non-zero to quieten some warnings. */
629 static int quiet_warnings
= 0;
632 static const char *cpu_arch_name
= NULL
;
633 static char *cpu_sub_arch_name
= NULL
;
635 /* CPU feature flags. */
636 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
638 /* If we have selected a cpu we are generating instructions for. */
639 static int cpu_arch_tune_set
= 0;
641 /* Cpu we are generating instructions for. */
642 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
644 /* CPU feature flags of cpu we are generating instructions for. */
645 static i386_cpu_flags cpu_arch_tune_flags
;
647 /* CPU instruction set architecture used. */
648 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
650 /* CPU feature flags of instruction set architecture used. */
651 i386_cpu_flags cpu_arch_isa_flags
;
653 /* If set, conditional jumps are not automatically promoted to handle
654 larger than a byte offset. */
655 static unsigned int no_cond_jump_promotion
= 0;
657 /* Encode SSE instructions with VEX prefix. */
658 static unsigned int sse2avx
;
660 /* Encode scalar AVX instructions with specific vector length. */
667 /* Encode scalar EVEX LIG instructions with specific vector length. */
675 /* Encode EVEX WIG instructions with specific evex.w. */
682 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
683 static enum rc_type evexrcig
= rne
;
685 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686 static symbolS
*GOT_symbol
;
688 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
689 unsigned int x86_dwarf2_return_column
;
691 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
692 int x86_cie_data_alignment
;
694 /* Interface to relax_segment.
695 There are 3 major relax states for 386 jump insns because the
696 different types of jumps add different sizes to frags when we're
697 figuring out what sort of jump to choose to reach a given label. */
700 #define UNCOND_JUMP 0
702 #define COND_JUMP86 2
707 #define SMALL16 (SMALL | CODE16)
709 #define BIG16 (BIG | CODE16)
713 #define INLINE __inline__
719 #define ENCODE_RELAX_STATE(type, size) \
720 ((relax_substateT) (((type) << 2) | (size)))
721 #define TYPE_FROM_RELAX_STATE(s) \
723 #define DISP_SIZE_FROM_RELAX_STATE(s) \
724 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
726 /* This table is used by relax_frag to promote short jumps to long
727 ones where necessary. SMALL (short) jumps may be promoted to BIG
728 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
729 don't allow a short jump in a 32 bit code segment to be promoted to
730 a 16 bit offset jump because it's slower (requires data size
731 prefix), and doesn't work, unless the destination is in the bottom
732 64k of the code segment (The top 16 bits of eip are zeroed). */
734 const relax_typeS md_relax_table
[] =
737 1) most positive reach of this state,
738 2) most negative reach of this state,
739 3) how many bytes this mode will have in the variable part of the frag
740 4) which index into the table to try if we can't fit into this one. */
742 /* UNCOND_JUMP states. */
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
744 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
745 /* dword jmp adds 4 bytes to frag:
746 0 extra opcode bytes, 4 displacement bytes. */
748 /* word jmp adds 2 byte2 to frag:
749 0 extra opcode bytes, 2 displacement bytes. */
752 /* COND_JUMP states. */
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
754 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
755 /* dword conditionals adds 5 bytes to frag:
756 1 extra opcode byte, 4 displacement bytes. */
758 /* word conditionals add 3 bytes to frag:
759 1 extra opcode byte, 2 displacement bytes. */
762 /* COND_JUMP86 states. */
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
764 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
765 /* dword conditionals adds 5 bytes to frag:
766 1 extra opcode byte, 4 displacement bytes. */
768 /* word conditionals add 4 bytes to frag:
769 1 displacement byte and a 3 byte long branch insn. */
773 static const arch_entry cpu_arch
[] =
775 /* Do not replace the first two entries - i386_target_format()
776 relies on them being there in this order. */
777 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
778 CPU_GENERIC32_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
780 CPU_GENERIC64_FLAGS
, 0 },
781 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
783 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
785 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
787 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
789 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
791 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
793 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
795 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
797 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
798 CPU_PENTIUMPRO_FLAGS
, 0 },
799 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
801 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
803 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
805 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
807 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
808 CPU_NOCONA_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
811 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
813 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
814 CPU_CORE2_FLAGS
, 1 },
815 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
816 CPU_CORE2_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
818 CPU_COREI7_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
821 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
823 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
824 CPU_IAMCU_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
827 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
829 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
830 CPU_ATHLON_FLAGS
, 0 },
831 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
833 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
835 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
837 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
838 CPU_AMDFAM10_FLAGS
, 0 },
839 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
840 CPU_BDVER1_FLAGS
, 0 },
841 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
842 CPU_BDVER2_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
844 CPU_BDVER3_FLAGS
, 0 },
845 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
846 CPU_BDVER4_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
848 CPU_ZNVER1_FLAGS
, 0 },
849 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
850 CPU_ZNVER2_FLAGS
, 0 },
851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
852 CPU_BTVER1_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
854 CPU_BTVER2_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
869 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
872 CPU_SSSE3_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
874 CPU_SSE4_1_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
876 CPU_SSE4_2_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
878 CPU_SSE4_2_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
883 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
884 CPU_AVX512F_FLAGS
, 0 },
885 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
886 CPU_AVX512CD_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
888 CPU_AVX512ER_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
890 CPU_AVX512PF_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
892 CPU_AVX512DQ_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
894 CPU_AVX512BW_FLAGS
, 0 },
895 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
896 CPU_AVX512VL_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
900 CPU_VMFUNC_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
904 CPU_XSAVE_FLAGS
, 0 },
905 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
906 CPU_XSAVEOPT_FLAGS
, 0 },
907 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
908 CPU_XSAVEC_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
910 CPU_XSAVES_FLAGS
, 0 },
911 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
914 CPU_PCLMUL_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
916 CPU_PCLMUL_FLAGS
, 1 },
917 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
918 CPU_FSGSBASE_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
920 CPU_RDRND_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
934 CPU_MOVBE_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
940 CPU_LZCNT_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
946 CPU_INVPCID_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
948 CPU_CLFLUSH_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
952 CPU_SYSCALL_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
954 CPU_RDTSCP_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
956 CPU_3DNOW_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
958 CPU_3DNOWA_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
960 CPU_PADLOCK_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
966 CPU_SSE4A_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
976 CPU_RDSEED_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
978 CPU_PRFCHW_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
983 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
986 CPU_CLFLUSHOPT_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
988 CPU_PREFETCHWT1_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
994 CPU_AVX512IFMA_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
996 CPU_AVX512VBMI_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512_4FMAPS_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512_VBMI2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512_VNNI_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512_BITALG_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1010 CPU_CLZERO_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1012 CPU_MWAITX_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1014 CPU_OSPKE_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1016 CPU_RDPID_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1018 CPU_PTWRITE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1022 CPU_SHSTK_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1024 CPU_GFNI_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1026 CPU_VAES_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1028 CPU_VPCLMULQDQ_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1030 CPU_WBNOINVD_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1032 CPU_PCONFIG_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1034 CPU_WAITPKG_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1036 CPU_CLDEMOTE_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1038 CPU_MOVDIRI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1040 CPU_MOVDIR64B_FLAGS
, 0 },
1043 static const noarch_entry cpu_noarch
[] =
1045 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1046 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1047 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1048 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1049 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1050 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1053 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1054 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1055 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1056 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1071 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1072 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1073 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1074 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1075 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1076 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1077 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1081 /* Like s_lcomm_internal in gas/read.c but the alignment string
1082 is allowed to be optional. */
1085 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1092 && *input_line_pointer
== ',')
1094 align
= parse_align (needs_align
- 1);
1096 if (align
== (addressT
) -1)
1111 bss_alloc (symbolP
, size
, align
);
1116 pe_lcomm (int needs_align
)
1118 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1122 const pseudo_typeS md_pseudo_table
[] =
1124 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1125 {"align", s_align_bytes
, 0},
1127 {"align", s_align_ptwo
, 0},
1129 {"arch", set_cpu_arch
, 0},
1133 {"lcomm", pe_lcomm
, 1},
1135 {"ffloat", float_cons
, 'f'},
1136 {"dfloat", float_cons
, 'd'},
1137 {"tfloat", float_cons
, 'x'},
1139 {"slong", signed_cons
, 4},
1140 {"noopt", s_ignore
, 0},
1141 {"optim", s_ignore
, 0},
1142 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1143 {"code16", set_code_flag
, CODE_16BIT
},
1144 {"code32", set_code_flag
, CODE_32BIT
},
1146 {"code64", set_code_flag
, CODE_64BIT
},
1148 {"intel_syntax", set_intel_syntax
, 1},
1149 {"att_syntax", set_intel_syntax
, 0},
1150 {"intel_mnemonic", set_intel_mnemonic
, 1},
1151 {"att_mnemonic", set_intel_mnemonic
, 0},
1152 {"allow_index_reg", set_allow_index_reg
, 1},
1153 {"disallow_index_reg", set_allow_index_reg
, 0},
1154 {"sse_check", set_check
, 0},
1155 {"operand_check", set_check
, 1},
1156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1157 {"largecomm", handle_large_common
, 0},
1159 {"file", dwarf2_directive_file
, 0},
1160 {"loc", dwarf2_directive_loc
, 0},
1161 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1164 {"secrel32", pe_directive_secrel
, 0},
1169 /* For interface with expression (). */
1170 extern char *input_line_pointer
;
1172 /* Hash table for instruction mnemonic lookup. */
1173 static struct hash_control
*op_hash
;
1175 /* Hash table for register lookup. */
1176 static struct hash_control
*reg_hash
;
1178 /* Various efficient no-op patterns for aligning code labels.
1179 Note: Don't try to assemble the instructions in the comments.
1180 0L and 0w are not legal. */
1181 static const unsigned char f32_1
[] =
1183 static const unsigned char f32_2
[] =
1184 {0x66,0x90}; /* xchg %ax,%ax */
1185 static const unsigned char f32_3
[] =
1186 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1187 static const unsigned char f32_4
[] =
1188 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1189 static const unsigned char f32_6
[] =
1190 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1191 static const unsigned char f32_7
[] =
1192 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1193 static const unsigned char f16_3
[] =
1194 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1195 static const unsigned char f16_4
[] =
1196 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1197 static const unsigned char jump_disp8
[] =
1198 {0xeb}; /* jmp disp8 */
1199 static const unsigned char jump32_disp32
[] =
1200 {0xe9}; /* jmp disp32 */
1201 static const unsigned char jump16_disp32
[] =
1202 {0x66,0xe9}; /* jmp disp32 */
1203 /* 32-bit NOPs patterns. */
1204 static const unsigned char *const f32_patt
[] = {
1205 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1207 /* 16-bit NOPs patterns. */
1208 static const unsigned char *const f16_patt
[] = {
1209 f32_1
, f32_2
, f16_3
, f16_4
1211 /* nopl (%[re]ax) */
1212 static const unsigned char alt_3
[] =
1214 /* nopl 0(%[re]ax) */
1215 static const unsigned char alt_4
[] =
1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_5
[] =
1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
1221 static const unsigned char alt_6
[] =
1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
1224 static const unsigned char alt_7
[] =
1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_8
[] =
1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_9
[] =
1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1233 static const unsigned char alt_10
[] =
1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* data16 nopw %cs:0L(%eax,%eax,1) */
1236 static const unsigned char alt_11
[] =
1237 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1238 /* 32-bit and 64-bit NOPs patterns. */
1239 static const unsigned char *const alt_patt
[] = {
1240 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1241 alt_9
, alt_10
, alt_11
1244 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1245 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1248 i386_output_nops (char *where
, const unsigned char *const *patt
,
1249 int count
, int max_single_nop_size
)
1252 /* Place the longer NOP first. */
1255 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1257 /* Use the smaller one if the requsted one isn't available. */
1260 max_single_nop_size
--;
1261 nops
= patt
[max_single_nop_size
- 1];
1264 last
= count
% max_single_nop_size
;
1267 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1268 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1272 nops
= patt
[last
- 1];
1275 /* Use the smaller one plus one-byte NOP if the needed one
1278 nops
= patt
[last
- 1];
1279 memcpy (where
+ offset
, nops
, last
);
1280 where
[offset
+ last
] = *patt
[0];
1283 memcpy (where
+ offset
, nops
, last
);
1288 fits_in_imm7 (offsetT num
)
1290 return (num
& 0x7f) == num
;
1294 fits_in_imm31 (offsetT num
)
1296 return (num
& 0x7fffffff) == num
;
1299 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1300 single NOP instruction LIMIT. */
1303 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1305 const unsigned char *const *patt
= NULL
;
1306 int max_single_nop_size
;
1307 /* Maximum number of NOPs before switching to jump over NOPs. */
1308 int max_number_of_nops
;
1310 switch (fragP
->fr_type
)
1319 /* We need to decide which NOP sequence to use for 32bit and
1320 64bit. When -mtune= is used:
1322 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1323 PROCESSOR_GENERIC32, f32_patt will be used.
1324 2. For the rest, alt_patt will be used.
1326 When -mtune= isn't used, alt_patt will be used if
1327 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1330 When -march= or .arch is used, we can't use anything beyond
1331 cpu_arch_isa_flags. */
1333 if (flag_code
== CODE_16BIT
)
1336 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1337 /* Limit number of NOPs to 2 in 16-bit mode. */
1338 max_number_of_nops
= 2;
1342 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1344 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1345 switch (cpu_arch_tune
)
1347 case PROCESSOR_UNKNOWN
:
1348 /* We use cpu_arch_isa_flags to check if we SHOULD
1349 optimize with nops. */
1350 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1355 case PROCESSOR_PENTIUM4
:
1356 case PROCESSOR_NOCONA
:
1357 case PROCESSOR_CORE
:
1358 case PROCESSOR_CORE2
:
1359 case PROCESSOR_COREI7
:
1360 case PROCESSOR_L1OM
:
1361 case PROCESSOR_K1OM
:
1362 case PROCESSOR_GENERIC64
:
1364 case PROCESSOR_ATHLON
:
1366 case PROCESSOR_AMDFAM10
:
1368 case PROCESSOR_ZNVER
:
1372 case PROCESSOR_I386
:
1373 case PROCESSOR_I486
:
1374 case PROCESSOR_PENTIUM
:
1375 case PROCESSOR_PENTIUMPRO
:
1376 case PROCESSOR_IAMCU
:
1377 case PROCESSOR_GENERIC32
:
1384 switch (fragP
->tc_frag_data
.tune
)
1386 case PROCESSOR_UNKNOWN
:
1387 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1388 PROCESSOR_UNKNOWN. */
1392 case PROCESSOR_I386
:
1393 case PROCESSOR_I486
:
1394 case PROCESSOR_PENTIUM
:
1395 case PROCESSOR_IAMCU
:
1397 case PROCESSOR_ATHLON
:
1399 case PROCESSOR_AMDFAM10
:
1401 case PROCESSOR_ZNVER
:
1403 case PROCESSOR_GENERIC32
:
1404 /* We use cpu_arch_isa_flags to check if we CAN optimize
1406 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1411 case PROCESSOR_PENTIUMPRO
:
1412 case PROCESSOR_PENTIUM4
:
1413 case PROCESSOR_NOCONA
:
1414 case PROCESSOR_CORE
:
1415 case PROCESSOR_CORE2
:
1416 case PROCESSOR_COREI7
:
1417 case PROCESSOR_L1OM
:
1418 case PROCESSOR_K1OM
:
1419 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1424 case PROCESSOR_GENERIC64
:
1430 if (patt
== f32_patt
)
1432 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1433 /* Limit number of NOPs to 2 for older processors. */
1434 max_number_of_nops
= 2;
1438 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1439 /* Limit number of NOPs to 7 for newer processors. */
1440 max_number_of_nops
= 7;
1445 limit
= max_single_nop_size
;
1447 if (fragP
->fr_type
== rs_fill_nop
)
1449 /* Output NOPs for .nop directive. */
1450 if (limit
> max_single_nop_size
)
1452 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1453 _("invalid single nop size: %d "
1454 "(expect within [0, %d])"),
1455 limit
, max_single_nop_size
);
1460 fragP
->fr_var
= count
;
1462 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1464 /* Generate jump over NOPs. */
1465 offsetT disp
= count
- 2;
1466 if (fits_in_imm7 (disp
))
1468 /* Use "jmp disp8" if possible. */
1470 where
[0] = jump_disp8
[0];
1476 unsigned int size_of_jump
;
1478 if (flag_code
== CODE_16BIT
)
1480 where
[0] = jump16_disp32
[0];
1481 where
[1] = jump16_disp32
[1];
1486 where
[0] = jump32_disp32
[0];
1490 count
-= size_of_jump
+ 4;
1491 if (!fits_in_imm31 (count
))
1493 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1494 _("jump over nop padding out of range"));
1498 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1499 where
+= size_of_jump
+ 4;
1503 /* Generate multiple NOPs. */
1504 i386_output_nops (where
, patt
, count
, limit
);
1508 operand_type_all_zero (const union i386_operand_type
*x
)
1510 switch (ARRAY_SIZE(x
->array
))
1521 return !x
->array
[0];
1528 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1530 switch (ARRAY_SIZE(x
->array
))
1548 operand_type_equal (const union i386_operand_type
*x
,
1549 const union i386_operand_type
*y
)
1551 switch (ARRAY_SIZE(x
->array
))
1554 if (x
->array
[2] != y
->array
[2])
1558 if (x
->array
[1] != y
->array
[1])
1562 return x
->array
[0] == y
->array
[0];
1570 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1572 switch (ARRAY_SIZE(x
->array
))
1587 return !x
->array
[0];
1594 cpu_flags_equal (const union i386_cpu_flags
*x
,
1595 const union i386_cpu_flags
*y
)
1597 switch (ARRAY_SIZE(x
->array
))
1600 if (x
->array
[3] != y
->array
[3])
1604 if (x
->array
[2] != y
->array
[2])
1608 if (x
->array
[1] != y
->array
[1])
1612 return x
->array
[0] == y
->array
[0];
1620 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1622 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1623 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1626 static INLINE i386_cpu_flags
1627 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1629 switch (ARRAY_SIZE (x
.array
))
1632 x
.array
[3] &= y
.array
[3];
1635 x
.array
[2] &= y
.array
[2];
1638 x
.array
[1] &= y
.array
[1];
1641 x
.array
[0] &= y
.array
[0];
1649 static INLINE i386_cpu_flags
1650 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1652 switch (ARRAY_SIZE (x
.array
))
1655 x
.array
[3] |= y
.array
[3];
1658 x
.array
[2] |= y
.array
[2];
1661 x
.array
[1] |= y
.array
[1];
1664 x
.array
[0] |= y
.array
[0];
1672 static INLINE i386_cpu_flags
1673 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1675 switch (ARRAY_SIZE (x
.array
))
1678 x
.array
[3] &= ~y
.array
[3];
1681 x
.array
[2] &= ~y
.array
[2];
1684 x
.array
[1] &= ~y
.array
[1];
1687 x
.array
[0] &= ~y
.array
[0];
1695 #define CPU_FLAGS_ARCH_MATCH 0x1
1696 #define CPU_FLAGS_64BIT_MATCH 0x2
1698 #define CPU_FLAGS_PERFECT_MATCH \
1699 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1701 /* Return CPU flags match bits. */
1704 cpu_flags_match (const insn_template
*t
)
1706 i386_cpu_flags x
= t
->cpu_flags
;
1707 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1709 x
.bitfield
.cpu64
= 0;
1710 x
.bitfield
.cpuno64
= 0;
1712 if (cpu_flags_all_zero (&x
))
1714 /* This instruction is available on all archs. */
1715 match
|= CPU_FLAGS_ARCH_MATCH
;
1719 /* This instruction is available only on some archs. */
1720 i386_cpu_flags cpu
= cpu_arch_flags
;
1722 /* AVX512VL is no standalone feature - match it and then strip it. */
1723 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1725 x
.bitfield
.cpuavx512vl
= 0;
1727 cpu
= cpu_flags_and (x
, cpu
);
1728 if (!cpu_flags_all_zero (&cpu
))
1730 if (x
.bitfield
.cpuavx
)
1732 /* We need to check a few extra flags with AVX. */
1733 if (cpu
.bitfield
.cpuavx
1734 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1735 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1736 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1737 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1738 match
|= CPU_FLAGS_ARCH_MATCH
;
1740 else if (x
.bitfield
.cpuavx512f
)
1742 /* We need to check a few extra flags with AVX512F. */
1743 if (cpu
.bitfield
.cpuavx512f
1744 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1745 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1746 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1750 match
|= CPU_FLAGS_ARCH_MATCH
;
1756 static INLINE i386_operand_type
1757 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1759 switch (ARRAY_SIZE (x
.array
))
1762 x
.array
[2] &= y
.array
[2];
1765 x
.array
[1] &= y
.array
[1];
1768 x
.array
[0] &= y
.array
[0];
1776 static INLINE i386_operand_type
1777 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1779 switch (ARRAY_SIZE (x
.array
))
1782 x
.array
[2] &= ~y
.array
[2];
1785 x
.array
[1] &= ~y
.array
[1];
1788 x
.array
[0] &= ~y
.array
[0];
1796 static INLINE i386_operand_type
1797 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[2] |= y
.array
[2];
1805 x
.array
[1] |= y
.array
[1];
1808 x
.array
[0] |= y
.array
[0];
1816 static INLINE i386_operand_type
1817 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1819 switch (ARRAY_SIZE (x
.array
))
1822 x
.array
[2] ^= y
.array
[2];
1825 x
.array
[1] ^= y
.array
[1];
1828 x
.array
[0] ^= y
.array
[0];
1836 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1837 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1838 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1839 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1840 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1841 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1842 static const i386_operand_type anydisp
1843 = OPERAND_TYPE_ANYDISP
;
1844 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1845 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1846 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1847 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1848 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1849 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1850 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1851 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1852 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1853 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1854 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1855 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1866 operand_type_check (i386_operand_type t
, enum operand_type c
)
1871 return t
.bitfield
.reg
;
1874 return (t
.bitfield
.imm8
1878 || t
.bitfield
.imm32s
1879 || t
.bitfield
.imm64
);
1882 return (t
.bitfield
.disp8
1883 || t
.bitfield
.disp16
1884 || t
.bitfield
.disp32
1885 || t
.bitfield
.disp32s
1886 || t
.bitfield
.disp64
);
1889 return (t
.bitfield
.disp8
1890 || t
.bitfield
.disp16
1891 || t
.bitfield
.disp32
1892 || t
.bitfield
.disp32s
1893 || t
.bitfield
.disp64
1894 || t
.bitfield
.baseindex
);
1903 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1904 between operand GIVEN and opeand WANTED for instruction template T. */
1907 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1910 return !((i
.types
[given
].bitfield
.byte
1911 && !t
->operand_types
[wanted
].bitfield
.byte
)
1912 || (i
.types
[given
].bitfield
.word
1913 && !t
->operand_types
[wanted
].bitfield
.word
)
1914 || (i
.types
[given
].bitfield
.dword
1915 && !t
->operand_types
[wanted
].bitfield
.dword
)
1916 || (i
.types
[given
].bitfield
.qword
1917 && !t
->operand_types
[wanted
].bitfield
.qword
)
1918 || (i
.types
[given
].bitfield
.tbyte
1919 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1922 /* Return 1 if there is no conflict in SIMD register between operand
1923 GIVEN and opeand WANTED for instruction template T. */
1926 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1929 return !((i
.types
[given
].bitfield
.xmmword
1930 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1931 || (i
.types
[given
].bitfield
.ymmword
1932 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1933 || (i
.types
[given
].bitfield
.zmmword
1934 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1937 /* Return 1 if there is no conflict in any size between operand GIVEN
1938 and opeand WANTED for instruction template T. */
1941 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1944 return (match_operand_size (t
, wanted
, given
)
1945 && !((i
.types
[given
].bitfield
.unspecified
1947 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1948 || (i
.types
[given
].bitfield
.fword
1949 && !t
->operand_types
[wanted
].bitfield
.fword
)
1950 /* For scalar opcode templates to allow register and memory
1951 operands at the same time, some special casing is needed
1952 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1953 down-conversion vpmov*. */
1954 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1955 && !t
->opcode_modifier
.broadcast
1956 && (t
->operand_types
[wanted
].bitfield
.byte
1957 || t
->operand_types
[wanted
].bitfield
.word
1958 || t
->operand_types
[wanted
].bitfield
.dword
1959 || t
->operand_types
[wanted
].bitfield
.qword
))
1960 ? (i
.types
[given
].bitfield
.xmmword
1961 || i
.types
[given
].bitfield
.ymmword
1962 || i
.types
[given
].bitfield
.zmmword
)
1963 : !match_simd_size(t
, wanted
, given
))));
1966 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1967 operands for instruction template T, and it has MATCH_REVERSE set if there
1968 is no size conflict on any operands for the template with operands reversed
1969 (and the template allows for reversing in the first place). */
1971 #define MATCH_STRAIGHT 1
1972 #define MATCH_REVERSE 2
1974 static INLINE
unsigned int
1975 operand_size_match (const insn_template
*t
)
1977 unsigned int j
, match
= MATCH_STRAIGHT
;
1979 /* Don't check jump instructions. */
1980 if (t
->opcode_modifier
.jump
1981 || t
->opcode_modifier
.jumpbyte
1982 || t
->opcode_modifier
.jumpdword
1983 || t
->opcode_modifier
.jumpintersegment
)
1986 /* Check memory and accumulator operand size. */
1987 for (j
= 0; j
< i
.operands
; j
++)
1989 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1990 && t
->operand_types
[j
].bitfield
.anysize
)
1993 if (t
->operand_types
[j
].bitfield
.reg
1994 && !match_operand_size (t
, j
, j
))
2000 if (t
->operand_types
[j
].bitfield
.regsimd
2001 && !match_simd_size (t
, j
, j
))
2007 if (t
->operand_types
[j
].bitfield
.acc
2008 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2014 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2021 if (!t
->opcode_modifier
.d
)
2025 i
.error
= operand_size_mismatch
;
2029 /* Check reverse. */
2030 gas_assert (i
.operands
== 2);
2032 for (j
= 0; j
< 2; j
++)
2034 if ((t
->operand_types
[j
].bitfield
.reg
2035 || t
->operand_types
[j
].bitfield
.acc
)
2036 && !match_operand_size (t
, j
, !j
))
2039 if ((i
.flags
[!j
] & Operand_Mem
) && !match_mem_size (t
, j
, !j
))
2043 return match
| MATCH_REVERSE
;
2047 operand_type_match (i386_operand_type overlap
,
2048 i386_operand_type given
)
2050 i386_operand_type temp
= overlap
;
2052 temp
.bitfield
.jumpabsolute
= 0;
2053 temp
.bitfield
.unspecified
= 0;
2054 temp
.bitfield
.byte
= 0;
2055 temp
.bitfield
.word
= 0;
2056 temp
.bitfield
.dword
= 0;
2057 temp
.bitfield
.fword
= 0;
2058 temp
.bitfield
.qword
= 0;
2059 temp
.bitfield
.tbyte
= 0;
2060 temp
.bitfield
.xmmword
= 0;
2061 temp
.bitfield
.ymmword
= 0;
2062 temp
.bitfield
.zmmword
= 0;
2063 if (operand_type_all_zero (&temp
))
2066 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2067 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2071 i
.error
= operand_type_mismatch
;
2075 /* If given types g0 and g1 are registers they must be of the same type
2076 unless the expected operand type register overlap is null.
2077 Memory operand size of certain SIMD instructions is also being checked
2081 operand_type_register_match (i386_operand_type g0
,
2082 i386_operand_type t0
,
2083 i386_operand_type g1
,
2084 i386_operand_type t1
)
2086 if (!g0
.bitfield
.reg
2087 && !g0
.bitfield
.regsimd
2088 && (!operand_type_check (g0
, anymem
)
2089 || g0
.bitfield
.unspecified
2090 || !t0
.bitfield
.regsimd
))
2093 if (!g1
.bitfield
.reg
2094 && !g1
.bitfield
.regsimd
2095 && (!operand_type_check (g1
, anymem
)
2096 || g1
.bitfield
.unspecified
2097 || !t1
.bitfield
.regsimd
))
2100 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2101 && g0
.bitfield
.word
== g1
.bitfield
.word
2102 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2103 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2104 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2105 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2106 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2109 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2110 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2111 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2112 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2113 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2114 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2115 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2118 i
.error
= register_type_mismatch
;
2123 static INLINE
unsigned int
2124 register_number (const reg_entry
*r
)
2126 unsigned int nr
= r
->reg_num
;
2128 if (r
->reg_flags
& RegRex
)
2131 if (r
->reg_flags
& RegVRex
)
2137 static INLINE
unsigned int
2138 mode_from_disp_size (i386_operand_type t
)
2140 if (t
.bitfield
.disp8
)
2142 else if (t
.bitfield
.disp16
2143 || t
.bitfield
.disp32
2144 || t
.bitfield
.disp32s
)
2151 fits_in_signed_byte (addressT num
)
2153 return num
+ 0x80 <= 0xff;
2157 fits_in_unsigned_byte (addressT num
)
2163 fits_in_unsigned_word (addressT num
)
2165 return num
<= 0xffff;
2169 fits_in_signed_word (addressT num
)
2171 return num
+ 0x8000 <= 0xffff;
2175 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2180 return num
+ 0x80000000 <= 0xffffffff;
2182 } /* fits_in_signed_long() */
2185 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2190 return num
<= 0xffffffff;
2192 } /* fits_in_unsigned_long() */
2195 fits_in_disp8 (offsetT num
)
2197 int shift
= i
.memshift
;
2203 mask
= (1 << shift
) - 1;
2205 /* Return 0 if NUM isn't properly aligned. */
2209 /* Check if NUM will fit in 8bit after shift. */
2210 return fits_in_signed_byte (num
>> shift
);
2214 fits_in_imm4 (offsetT num
)
2216 return (num
& 0xf) == num
;
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num
)
2222 i386_operand_type t
;
2224 operand_type_set (&t
, 0);
2225 t
.bitfield
.imm64
= 1;
2227 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2234 t
.bitfield
.imm1
= 1;
2235 t
.bitfield
.imm8
= 1;
2236 t
.bitfield
.imm8s
= 1;
2237 t
.bitfield
.imm16
= 1;
2238 t
.bitfield
.imm32
= 1;
2239 t
.bitfield
.imm32s
= 1;
2241 else if (fits_in_signed_byte (num
))
2243 t
.bitfield
.imm8
= 1;
2244 t
.bitfield
.imm8s
= 1;
2245 t
.bitfield
.imm16
= 1;
2246 t
.bitfield
.imm32
= 1;
2247 t
.bitfield
.imm32s
= 1;
2249 else if (fits_in_unsigned_byte (num
))
2251 t
.bitfield
.imm8
= 1;
2252 t
.bitfield
.imm16
= 1;
2253 t
.bitfield
.imm32
= 1;
2254 t
.bitfield
.imm32s
= 1;
2256 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2258 t
.bitfield
.imm16
= 1;
2259 t
.bitfield
.imm32
= 1;
2260 t
.bitfield
.imm32s
= 1;
2262 else if (fits_in_signed_long (num
))
2264 t
.bitfield
.imm32
= 1;
2265 t
.bitfield
.imm32s
= 1;
2267 else if (fits_in_unsigned_long (num
))
2268 t
.bitfield
.imm32
= 1;
2274 offset_in_range (offsetT val
, int size
)
2280 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2281 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2282 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2284 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code
!= CODE_64BIT
2292 || i
.prefix
[ADDR_PREFIX
])
2293 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2294 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2297 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2299 char buf1
[40], buf2
[40];
2301 sprint_value (buf1
, val
);
2302 sprint_value (buf2
, val
& mask
);
2303 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix
)
2329 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2332 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2333 && flag_code
== CODE_64BIT
)
2335 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2336 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2337 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2338 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2349 case DS_PREFIX_OPCODE
:
2352 case CS_PREFIX_OPCODE
:
2353 case ES_PREFIX_OPCODE
:
2354 case FS_PREFIX_OPCODE
:
2355 case GS_PREFIX_OPCODE
:
2356 case SS_PREFIX_OPCODE
:
2360 case REPNE_PREFIX_OPCODE
:
2361 case REPE_PREFIX_OPCODE
:
2366 case LOCK_PREFIX_OPCODE
:
2375 case ADDR_PREFIX_OPCODE
:
2379 case DATA_PREFIX_OPCODE
:
2383 if (i
.prefix
[q
] != 0)
2391 i
.prefix
[q
] |= prefix
;
2394 as_bad (_("same type of prefix used twice"));
2400 update_code_flag (int value
, int check
)
2402 PRINTF_LIKE ((*as_error
));
2404 flag_code
= (enum flag_code
) value
;
2405 if (flag_code
== CODE_64BIT
)
2407 cpu_arch_flags
.bitfield
.cpu64
= 1;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2412 cpu_arch_flags
.bitfield
.cpu64
= 0;
2413 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2415 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2418 as_error
= as_fatal
;
2421 (*as_error
) (_("64bit mode not supported on `%s'."),
2422 cpu_arch_name
? cpu_arch_name
: default_arch
);
2424 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2427 as_error
= as_fatal
;
2430 (*as_error
) (_("32bit mode not supported on `%s'."),
2431 cpu_arch_name
? cpu_arch_name
: default_arch
);
2433 stackop_size
= '\0';
2437 set_code_flag (int value
)
2439 update_code_flag (value
, 0);
2443 set_16bit_gcc_code_flag (int new_code_flag
)
2445 flag_code
= (enum flag_code
) new_code_flag
;
2446 if (flag_code
!= CODE_16BIT
)
2448 cpu_arch_flags
.bitfield
.cpu64
= 0;
2449 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2450 stackop_size
= LONG_MNEM_SUFFIX
;
2454 set_intel_syntax (int syntax_flag
)
2456 /* Find out if register prefixing is specified. */
2457 int ask_naked_reg
= 0;
2460 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2463 int e
= get_symbol_name (&string
);
2465 if (strcmp (string
, "prefix") == 0)
2467 else if (strcmp (string
, "noprefix") == 0)
2470 as_bad (_("bad argument to syntax directive."));
2471 (void) restore_line_pointer (e
);
2473 demand_empty_rest_of_line ();
2475 intel_syntax
= syntax_flag
;
2477 if (ask_naked_reg
== 0)
2478 allow_naked_reg
= (intel_syntax
2479 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2481 allow_naked_reg
= (ask_naked_reg
< 0);
2483 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2485 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2486 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2487 register_prefix
= allow_naked_reg
? "" : "%";
2491 set_intel_mnemonic (int mnemonic_flag
)
2493 intel_mnemonic
= mnemonic_flag
;
2497 set_allow_index_reg (int flag
)
2499 allow_index_reg
= flag
;
2503 set_check (int what
)
2505 enum check_kind
*kind
;
2510 kind
= &operand_check
;
2521 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2524 int e
= get_symbol_name (&string
);
2526 if (strcmp (string
, "none") == 0)
2528 else if (strcmp (string
, "warning") == 0)
2529 *kind
= check_warning
;
2530 else if (strcmp (string
, "error") == 0)
2531 *kind
= check_error
;
2533 as_bad (_("bad argument to %s_check directive."), str
);
2534 (void) restore_line_pointer (e
);
2537 as_bad (_("missing argument for %s_check directive"), str
);
2539 demand_empty_rest_of_line ();
2543 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2544 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2547 static const char *arch
;
2549 /* Intel LIOM is only supported on ELF. */
2555 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2556 use default_arch. */
2557 arch
= cpu_arch_name
;
2559 arch
= default_arch
;
2562 /* If we are targeting Intel MCU, we must enable it. */
2563 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2564 || new_flag
.bitfield
.cpuiamcu
)
2567 /* If we are targeting Intel L1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2569 || new_flag
.bitfield
.cpul1om
)
2572 /* If we are targeting Intel K1OM, we must enable it. */
2573 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2574 || new_flag
.bitfield
.cpuk1om
)
2577 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2582 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2586 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2589 int e
= get_symbol_name (&string
);
2591 i386_cpu_flags flags
;
2593 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2595 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2597 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2601 cpu_arch_name
= cpu_arch
[j
].name
;
2602 cpu_sub_arch_name
= NULL
;
2603 cpu_arch_flags
= cpu_arch
[j
].flags
;
2604 if (flag_code
== CODE_64BIT
)
2606 cpu_arch_flags
.bitfield
.cpu64
= 1;
2607 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2611 cpu_arch_flags
.bitfield
.cpu64
= 0;
2612 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2614 cpu_arch_isa
= cpu_arch
[j
].type
;
2615 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2616 if (!cpu_arch_tune_set
)
2618 cpu_arch_tune
= cpu_arch_isa
;
2619 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2624 flags
= cpu_flags_or (cpu_arch_flags
,
2627 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2629 if (cpu_sub_arch_name
)
2631 char *name
= cpu_sub_arch_name
;
2632 cpu_sub_arch_name
= concat (name
,
2634 (const char *) NULL
);
2638 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2639 cpu_arch_flags
= flags
;
2640 cpu_arch_isa_flags
= flags
;
2644 = cpu_flags_or (cpu_arch_isa_flags
,
2646 (void) restore_line_pointer (e
);
2647 demand_empty_rest_of_line ();
2652 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2654 /* Disable an ISA extension. */
2655 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2656 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2658 flags
= cpu_flags_and_not (cpu_arch_flags
,
2659 cpu_noarch
[j
].flags
);
2660 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2662 if (cpu_sub_arch_name
)
2664 char *name
= cpu_sub_arch_name
;
2665 cpu_sub_arch_name
= concat (name
, string
,
2666 (const char *) NULL
);
2670 cpu_sub_arch_name
= xstrdup (string
);
2671 cpu_arch_flags
= flags
;
2672 cpu_arch_isa_flags
= flags
;
2674 (void) restore_line_pointer (e
);
2675 demand_empty_rest_of_line ();
2679 j
= ARRAY_SIZE (cpu_arch
);
2682 if (j
>= ARRAY_SIZE (cpu_arch
))
2683 as_bad (_("no such architecture: `%s'"), string
);
2685 *input_line_pointer
= e
;
2688 as_bad (_("missing cpu architecture"));
2690 no_cond_jump_promotion
= 0;
2691 if (*input_line_pointer
== ','
2692 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2697 ++input_line_pointer
;
2698 e
= get_symbol_name (&string
);
2700 if (strcmp (string
, "nojumps") == 0)
2701 no_cond_jump_promotion
= 1;
2702 else if (strcmp (string
, "jumps") == 0)
2705 as_bad (_("no such architecture modifier: `%s'"), string
);
2707 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2713 enum bfd_architecture
2716 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2718 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2719 || flag_code
!= CODE_64BIT
)
2720 as_fatal (_("Intel L1OM is 64bit ELF only"));
2721 return bfd_arch_l1om
;
2723 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2725 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2726 || flag_code
!= CODE_64BIT
)
2727 as_fatal (_("Intel K1OM is 64bit ELF only"));
2728 return bfd_arch_k1om
;
2730 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2732 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2733 || flag_code
== CODE_64BIT
)
2734 as_fatal (_("Intel MCU is 32bit ELF only"));
2735 return bfd_arch_iamcu
;
2738 return bfd_arch_i386
;
2744 if (!strncmp (default_arch
, "x86_64", 6))
2746 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2748 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2749 || default_arch
[6] != '\0')
2750 as_fatal (_("Intel L1OM is 64bit ELF only"));
2751 return bfd_mach_l1om
;
2753 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2755 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2756 || default_arch
[6] != '\0')
2757 as_fatal (_("Intel K1OM is 64bit ELF only"));
2758 return bfd_mach_k1om
;
2760 else if (default_arch
[6] == '\0')
2761 return bfd_mach_x86_64
;
2763 return bfd_mach_x64_32
;
2765 else if (!strcmp (default_arch
, "i386")
2766 || !strcmp (default_arch
, "iamcu"))
2768 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2770 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2771 as_fatal (_("Intel MCU is 32bit ELF only"));
2772 return bfd_mach_i386_iamcu
;
2775 return bfd_mach_i386_i386
;
2778 as_fatal (_("unknown architecture"));
2784 const char *hash_err
;
2786 /* Support pseudo prefixes like {disp32}. */
2787 lex_type
['{'] = LEX_BEGIN_NAME
;
2789 /* Initialize op_hash hash table. */
2790 op_hash
= hash_new ();
2793 const insn_template
*optab
;
2794 templates
*core_optab
;
2796 /* Setup for loop. */
2798 core_optab
= XNEW (templates
);
2799 core_optab
->start
= optab
;
2804 if (optab
->name
== NULL
2805 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2807 /* different name --> ship out current template list;
2808 add to hash table; & begin anew. */
2809 core_optab
->end
= optab
;
2810 hash_err
= hash_insert (op_hash
,
2812 (void *) core_optab
);
2815 as_fatal (_("can't hash %s: %s"),
2819 if (optab
->name
== NULL
)
2821 core_optab
= XNEW (templates
);
2822 core_optab
->start
= optab
;
2827 /* Initialize reg_hash hash table. */
2828 reg_hash
= hash_new ();
2830 const reg_entry
*regtab
;
2831 unsigned int regtab_size
= i386_regtab_size
;
2833 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2835 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2837 as_fatal (_("can't hash %s: %s"),
2843 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2848 for (c
= 0; c
< 256; c
++)
2853 mnemonic_chars
[c
] = c
;
2854 register_chars
[c
] = c
;
2855 operand_chars
[c
] = c
;
2857 else if (ISLOWER (c
))
2859 mnemonic_chars
[c
] = c
;
2860 register_chars
[c
] = c
;
2861 operand_chars
[c
] = c
;
2863 else if (ISUPPER (c
))
2865 mnemonic_chars
[c
] = TOLOWER (c
);
2866 register_chars
[c
] = mnemonic_chars
[c
];
2867 operand_chars
[c
] = c
;
2869 else if (c
== '{' || c
== '}')
2871 mnemonic_chars
[c
] = c
;
2872 operand_chars
[c
] = c
;
2875 if (ISALPHA (c
) || ISDIGIT (c
))
2876 identifier_chars
[c
] = c
;
2879 identifier_chars
[c
] = c
;
2880 operand_chars
[c
] = c
;
2885 identifier_chars
['@'] = '@';
2888 identifier_chars
['?'] = '?';
2889 operand_chars
['?'] = '?';
2891 digit_chars
['-'] = '-';
2892 mnemonic_chars
['_'] = '_';
2893 mnemonic_chars
['-'] = '-';
2894 mnemonic_chars
['.'] = '.';
2895 identifier_chars
['_'] = '_';
2896 identifier_chars
['.'] = '.';
2898 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2899 operand_chars
[(unsigned char) *p
] = *p
;
2902 if (flag_code
== CODE_64BIT
)
2904 #if defined (OBJ_COFF) && defined (TE_PE)
2905 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2908 x86_dwarf2_return_column
= 16;
2910 x86_cie_data_alignment
= -8;
2914 x86_dwarf2_return_column
= 8;
2915 x86_cie_data_alignment
= -4;
2920 i386_print_statistics (FILE *file
)
2922 hash_print_statistics (file
, "i386 opcode", op_hash
);
2923 hash_print_statistics (file
, "i386 register", reg_hash
);
2928 /* Debugging routines for md_assemble. */
2929 static void pte (insn_template
*);
2930 static void pt (i386_operand_type
);
2931 static void pe (expressionS
*);
2932 static void ps (symbolS
*);
2935 pi (char *line
, i386_insn
*x
)
2939 fprintf (stdout
, "%s: template ", line
);
2941 fprintf (stdout
, " address: base %s index %s scale %x\n",
2942 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2943 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2944 x
->log2_scale_factor
);
2945 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2946 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2947 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2948 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2949 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2950 (x
->rex
& REX_W
) != 0,
2951 (x
->rex
& REX_R
) != 0,
2952 (x
->rex
& REX_X
) != 0,
2953 (x
->rex
& REX_B
) != 0);
2954 for (j
= 0; j
< x
->operands
; j
++)
2956 fprintf (stdout
, " #%d: ", j
+ 1);
2958 fprintf (stdout
, "\n");
2959 if (x
->types
[j
].bitfield
.reg
2960 || x
->types
[j
].bitfield
.regmmx
2961 || x
->types
[j
].bitfield
.regsimd
2962 || x
->types
[j
].bitfield
.sreg2
2963 || x
->types
[j
].bitfield
.sreg3
2964 || x
->types
[j
].bitfield
.control
2965 || x
->types
[j
].bitfield
.debug
2966 || x
->types
[j
].bitfield
.test
)
2967 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2968 if (operand_type_check (x
->types
[j
], imm
))
2970 if (operand_type_check (x
->types
[j
], disp
))
2971 pe (x
->op
[j
].disps
);
2976 pte (insn_template
*t
)
2979 fprintf (stdout
, " %d operands ", t
->operands
);
2980 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2981 if (t
->extension_opcode
!= None
)
2982 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2983 if (t
->opcode_modifier
.d
)
2984 fprintf (stdout
, "D");
2985 if (t
->opcode_modifier
.w
)
2986 fprintf (stdout
, "W");
2987 fprintf (stdout
, "\n");
2988 for (j
= 0; j
< t
->operands
; j
++)
2990 fprintf (stdout
, " #%d type ", j
+ 1);
2991 pt (t
->operand_types
[j
]);
2992 fprintf (stdout
, "\n");
2999 fprintf (stdout
, " operation %d\n", e
->X_op
);
3000 fprintf (stdout
, " add_number %ld (%lx)\n",
3001 (long) e
->X_add_number
, (long) e
->X_add_number
);
3002 if (e
->X_add_symbol
)
3004 fprintf (stdout
, " add_symbol ");
3005 ps (e
->X_add_symbol
);
3006 fprintf (stdout
, "\n");
3010 fprintf (stdout
, " op_symbol ");
3011 ps (e
->X_op_symbol
);
3012 fprintf (stdout
, "\n");
3019 fprintf (stdout
, "%s type %s%s",
3021 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3022 segment_name (S_GET_SEGMENT (s
)));
3025 static struct type_name
3027 i386_operand_type mask
;
3030 const type_names
[] =
3032 { OPERAND_TYPE_REG8
, "r8" },
3033 { OPERAND_TYPE_REG16
, "r16" },
3034 { OPERAND_TYPE_REG32
, "r32" },
3035 { OPERAND_TYPE_REG64
, "r64" },
3036 { OPERAND_TYPE_IMM8
, "i8" },
3037 { OPERAND_TYPE_IMM8
, "i8s" },
3038 { OPERAND_TYPE_IMM16
, "i16" },
3039 { OPERAND_TYPE_IMM32
, "i32" },
3040 { OPERAND_TYPE_IMM32S
, "i32s" },
3041 { OPERAND_TYPE_IMM64
, "i64" },
3042 { OPERAND_TYPE_IMM1
, "i1" },
3043 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3044 { OPERAND_TYPE_DISP8
, "d8" },
3045 { OPERAND_TYPE_DISP16
, "d16" },
3046 { OPERAND_TYPE_DISP32
, "d32" },
3047 { OPERAND_TYPE_DISP32S
, "d32s" },
3048 { OPERAND_TYPE_DISP64
, "d64" },
3049 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3050 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3051 { OPERAND_TYPE_CONTROL
, "control reg" },
3052 { OPERAND_TYPE_TEST
, "test reg" },
3053 { OPERAND_TYPE_DEBUG
, "debug reg" },
3054 { OPERAND_TYPE_FLOATREG
, "FReg" },
3055 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3056 { OPERAND_TYPE_SREG2
, "SReg2" },
3057 { OPERAND_TYPE_SREG3
, "SReg3" },
3058 { OPERAND_TYPE_ACC
, "Acc" },
3059 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3060 { OPERAND_TYPE_REGMMX
, "rMMX" },
3061 { OPERAND_TYPE_REGXMM
, "rXMM" },
3062 { OPERAND_TYPE_REGYMM
, "rYMM" },
3063 { OPERAND_TYPE_REGZMM
, "rZMM" },
3064 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3065 { OPERAND_TYPE_ESSEG
, "es" },
3069 pt (i386_operand_type t
)
3072 i386_operand_type a
;
3074 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3076 a
= operand_type_and (t
, type_names
[j
].mask
);
3077 if (!operand_type_all_zero (&a
))
3078 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3083 #endif /* DEBUG386 */
3085 static bfd_reloc_code_real_type
3086 reloc (unsigned int size
,
3089 bfd_reloc_code_real_type other
)
3091 if (other
!= NO_RELOC
)
3093 reloc_howto_type
*rel
;
3098 case BFD_RELOC_X86_64_GOT32
:
3099 return BFD_RELOC_X86_64_GOT64
;
3101 case BFD_RELOC_X86_64_GOTPLT64
:
3102 return BFD_RELOC_X86_64_GOTPLT64
;
3104 case BFD_RELOC_X86_64_PLTOFF64
:
3105 return BFD_RELOC_X86_64_PLTOFF64
;
3107 case BFD_RELOC_X86_64_GOTPC32
:
3108 other
= BFD_RELOC_X86_64_GOTPC64
;
3110 case BFD_RELOC_X86_64_GOTPCREL
:
3111 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3113 case BFD_RELOC_X86_64_TPOFF32
:
3114 other
= BFD_RELOC_X86_64_TPOFF64
;
3116 case BFD_RELOC_X86_64_DTPOFF32
:
3117 other
= BFD_RELOC_X86_64_DTPOFF64
;
3123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3124 if (other
== BFD_RELOC_SIZE32
)
3127 other
= BFD_RELOC_SIZE64
;
3130 as_bad (_("there are no pc-relative size relocations"));
3136 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3137 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3140 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3142 as_bad (_("unknown relocation (%u)"), other
);
3143 else if (size
!= bfd_get_reloc_size (rel
))
3144 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3145 bfd_get_reloc_size (rel
),
3147 else if (pcrel
&& !rel
->pc_relative
)
3148 as_bad (_("non-pc-relative relocation for pc-relative field"));
3149 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3151 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3153 as_bad (_("relocated field and relocation type differ in signedness"));
3162 as_bad (_("there are no unsigned pc-relative relocations"));
3165 case 1: return BFD_RELOC_8_PCREL
;
3166 case 2: return BFD_RELOC_16_PCREL
;
3167 case 4: return BFD_RELOC_32_PCREL
;
3168 case 8: return BFD_RELOC_64_PCREL
;
3170 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3177 case 4: return BFD_RELOC_X86_64_32S
;
3182 case 1: return BFD_RELOC_8
;
3183 case 2: return BFD_RELOC_16
;
3184 case 4: return BFD_RELOC_32
;
3185 case 8: return BFD_RELOC_64
;
3187 as_bad (_("cannot do %s %u byte relocation"),
3188 sign
> 0 ? "signed" : "unsigned", size
);
3194 /* Here we decide which fixups can be adjusted to make them relative to
3195 the beginning of the section instead of the symbol. Basically we need
3196 to make sure that the dynamic relocations are done correctly, so in
3197 some cases we force the original symbol to be used. */
3200 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3206 /* Don't adjust pc-relative references to merge sections in 64-bit
3208 if (use_rela_relocations
3209 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3213 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3214 and changed later by validate_fix. */
3215 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3216 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3219 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3220 for size relocations. */
3221 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3222 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3223 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3224 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3225 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3226 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3249 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3250 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3251 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3252 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3253 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3260 intel_float_operand (const char *mnemonic
)
3262 /* Note that the value returned is meaningful only for opcodes with (memory)
3263 operands, hence the code here is free to improperly handle opcodes that
3264 have no operands (for better performance and smaller code). */
3266 if (mnemonic
[0] != 'f')
3267 return 0; /* non-math */
3269 switch (mnemonic
[1])
3271 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3272 the fs segment override prefix not currently handled because no
3273 call path can make opcodes without operands get here */
3275 return 2 /* integer op */;
3277 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3278 return 3; /* fldcw/fldenv */
3281 if (mnemonic
[2] != 'o' /* fnop */)
3282 return 3; /* non-waiting control op */
3285 if (mnemonic
[2] == 's')
3286 return 3; /* frstor/frstpm */
3289 if (mnemonic
[2] == 'a')
3290 return 3; /* fsave */
3291 if (mnemonic
[2] == 't')
3293 switch (mnemonic
[3])
3295 case 'c': /* fstcw */
3296 case 'd': /* fstdw */
3297 case 'e': /* fstenv */
3298 case 's': /* fsts[gw] */
3304 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3305 return 0; /* fxsave/fxrstor are not really math ops */
3312 /* Build the VEX prefix. */
3315 build_vex_prefix (const insn_template
*t
)
3317 unsigned int register_specifier
;
3318 unsigned int implied_prefix
;
3319 unsigned int vector_length
;
3321 /* Check register specifier. */
3322 if (i
.vex
.register_specifier
)
3324 register_specifier
=
3325 ~register_number (i
.vex
.register_specifier
) & 0xf;
3326 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3329 register_specifier
= 0xf;
3331 /* Use 2-byte VEX prefix by swapping destination and source
3333 if (i
.vec_encoding
!= vex_encoding_vex3
3334 && i
.dir_encoding
== dir_encoding_default
3335 && i
.operands
== i
.reg_operands
3336 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3337 && i
.tm
.opcode_modifier
.load
3340 unsigned int xchg
= i
.operands
- 1;
3341 union i386_op temp_op
;
3342 i386_operand_type temp_type
;
3344 temp_type
= i
.types
[xchg
];
3345 i
.types
[xchg
] = i
.types
[0];
3346 i
.types
[0] = temp_type
;
3347 temp_op
= i
.op
[xchg
];
3348 i
.op
[xchg
] = i
.op
[0];
3351 gas_assert (i
.rm
.mode
== 3);
3355 i
.rm
.regmem
= i
.rm
.reg
;
3358 /* Use the next insn. */
3362 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3363 vector_length
= avxscalar
;
3364 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3370 /* Determine vector length from the last multi-length vector
3373 for (op
= t
->operands
; op
--;)
3374 if (t
->operand_types
[op
].bitfield
.xmmword
3375 && t
->operand_types
[op
].bitfield
.ymmword
3376 && i
.types
[op
].bitfield
.ymmword
)
3383 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3388 case DATA_PREFIX_OPCODE
:
3391 case REPE_PREFIX_OPCODE
:
3394 case REPNE_PREFIX_OPCODE
:
3401 /* Use 2-byte VEX prefix if possible. */
3402 if (i
.vec_encoding
!= vex_encoding_vex3
3403 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3404 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3405 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3407 /* 2-byte VEX prefix. */
3411 i
.vex
.bytes
[0] = 0xc5;
3413 /* Check the REX.R bit. */
3414 r
= (i
.rex
& REX_R
) ? 0 : 1;
3415 i
.vex
.bytes
[1] = (r
<< 7
3416 | register_specifier
<< 3
3417 | vector_length
<< 2
3422 /* 3-byte VEX prefix. */
3427 switch (i
.tm
.opcode_modifier
.vexopcode
)
3431 i
.vex
.bytes
[0] = 0xc4;
3435 i
.vex
.bytes
[0] = 0xc4;
3439 i
.vex
.bytes
[0] = 0xc4;
3443 i
.vex
.bytes
[0] = 0x8f;
3447 i
.vex
.bytes
[0] = 0x8f;
3451 i
.vex
.bytes
[0] = 0x8f;
3457 /* The high 3 bits of the second VEX byte are 1's compliment
3458 of RXB bits from REX. */
3459 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3461 /* Check the REX.W bit. */
3462 w
= (i
.rex
& REX_W
) ? 1 : 0;
3463 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3466 i
.vex
.bytes
[2] = (w
<< 7
3467 | register_specifier
<< 3
3468 | vector_length
<< 2
3473 static INLINE bfd_boolean
3474 is_evex_encoding (const insn_template
*t
)
3476 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3477 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3478 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3481 static INLINE bfd_boolean
3482 is_any_vex_encoding (const insn_template
*t
)
3484 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3485 || is_evex_encoding (t
);
3488 /* Build the EVEX prefix. */
3491 build_evex_prefix (void)
3493 unsigned int register_specifier
;
3494 unsigned int implied_prefix
;
3496 rex_byte vrex_used
= 0;
3498 /* Check register specifier. */
3499 if (i
.vex
.register_specifier
)
3501 gas_assert ((i
.vrex
& REX_X
) == 0);
3503 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3504 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3505 register_specifier
+= 8;
3506 /* The upper 16 registers are encoded in the fourth byte of the
3508 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3509 i
.vex
.bytes
[3] = 0x8;
3510 register_specifier
= ~register_specifier
& 0xf;
3514 register_specifier
= 0xf;
3516 /* Encode upper 16 vector index register in the fourth byte of
3518 if (!(i
.vrex
& REX_X
))
3519 i
.vex
.bytes
[3] = 0x8;
3524 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE
:
3532 case REPE_PREFIX_OPCODE
:
3535 case REPNE_PREFIX_OPCODE
:
3542 /* 4 byte EVEX prefix. */
3544 i
.vex
.bytes
[0] = 0x62;
3547 switch (i
.tm
.opcode_modifier
.vexopcode
)
3563 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3565 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3567 /* The fifth bit of the second EVEX byte is 1's compliment of the
3568 REX_R bit in VREX. */
3569 if (!(i
.vrex
& REX_R
))
3570 i
.vex
.bytes
[1] |= 0x10;
3574 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3576 /* When all operands are registers, the REX_X bit in REX is not
3577 used. We reuse it to encode the upper 16 registers, which is
3578 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3579 as 1's compliment. */
3580 if ((i
.vrex
& REX_B
))
3583 i
.vex
.bytes
[1] &= ~0x40;
3587 /* EVEX instructions shouldn't need the REX prefix. */
3588 i
.vrex
&= ~vrex_used
;
3589 gas_assert (i
.vrex
== 0);
3591 /* Check the REX.W bit. */
3592 w
= (i
.rex
& REX_W
) ? 1 : 0;
3593 if (i
.tm
.opcode_modifier
.vexw
)
3595 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3598 /* If w is not set it means we are dealing with WIG instruction. */
3601 if (evexwig
== evexw1
)
3605 /* Encode the U bit. */
3606 implied_prefix
|= 0x4;
3608 /* The third byte of the EVEX prefix. */
3609 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3611 /* The fourth byte of the EVEX prefix. */
3612 /* The zeroing-masking bit. */
3613 if (i
.mask
&& i
.mask
->zeroing
)
3614 i
.vex
.bytes
[3] |= 0x80;
3616 /* Don't always set the broadcast bit if there is no RC. */
3619 /* Encode the vector length. */
3620 unsigned int vec_length
;
3622 if (!i
.tm
.opcode_modifier
.evex
3623 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3627 /* Determine vector length from the last multi-length vector
3630 for (op
= i
.operands
; op
--;)
3631 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3632 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3633 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3635 if (i
.types
[op
].bitfield
.zmmword
)
3637 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3640 else if (i
.types
[op
].bitfield
.ymmword
)
3642 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3645 else if (i
.types
[op
].bitfield
.xmmword
)
3647 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3650 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3652 switch (i
.broadcast
->bytes
)
3655 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3658 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3661 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3670 if (op
>= MAX_OPERANDS
)
3674 switch (i
.tm
.opcode_modifier
.evex
)
3676 case EVEXLIG
: /* LL' is ignored */
3677 vec_length
= evexlig
<< 5;
3680 vec_length
= 0 << 5;
3683 vec_length
= 1 << 5;
3686 vec_length
= 2 << 5;
3692 i
.vex
.bytes
[3] |= vec_length
;
3693 /* Encode the broadcast bit. */
3695 i
.vex
.bytes
[3] |= 0x10;
3699 if (i
.rounding
->type
!= saeonly
)
3700 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3702 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3705 if (i
.mask
&& i
.mask
->mask
)
3706 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3710 process_immext (void)
3714 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3717 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3718 with an opcode suffix which is coded in the same place as an
3719 8-bit immediate field would be.
3720 Here we check those operands and remove them afterwards. */
3723 for (x
= 0; x
< i
.operands
; x
++)
3724 if (register_number (i
.op
[x
].regs
) != x
)
3725 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3726 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3732 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3734 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3735 suffix which is coded in the same place as an 8-bit immediate
3737 Here we check those operands and remove them afterwards. */
3740 if (i
.operands
!= 3)
3743 for (x
= 0; x
< 2; x
++)
3744 if (register_number (i
.op
[x
].regs
) != x
)
3745 goto bad_register_operand
;
3747 /* Check for third operand for mwaitx/monitorx insn. */
3748 if (register_number (i
.op
[x
].regs
)
3749 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3751 bad_register_operand
:
3752 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3753 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3760 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3761 which is coded in the same place as an 8-bit immediate field
3762 would be. Here we fake an 8-bit immediate operand from the
3763 opcode suffix stored in tm.extension_opcode.
3765 AVX instructions also use this encoding, for some of
3766 3 argument instructions. */
3768 gas_assert (i
.imm_operands
<= 1
3770 || (is_any_vex_encoding (&i
.tm
)
3771 && i
.operands
<= 4)));
3773 exp
= &im_expressions
[i
.imm_operands
++];
3774 i
.op
[i
.operands
].imms
= exp
;
3775 i
.types
[i
.operands
] = imm8
;
3777 exp
->X_op
= O_constant
;
3778 exp
->X_add_number
= i
.tm
.extension_opcode
;
3779 i
.tm
.extension_opcode
= None
;
3786 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3791 as_bad (_("invalid instruction `%s' after `%s'"),
3792 i
.tm
.name
, i
.hle_prefix
);
3795 if (i
.prefix
[LOCK_PREFIX
])
3797 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3801 case HLEPrefixRelease
:
3802 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3804 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3808 if (i
.mem_operands
== 0
3809 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3811 as_bad (_("memory destination needed for instruction `%s'"
3812 " after `xrelease'"), i
.tm
.name
);
3819 /* Try the shortest encoding by shortening operand size. */
3822 optimize_encoding (void)
3826 if (optimize_for_space
3827 && i
.reg_operands
== 1
3828 && i
.imm_operands
== 1
3829 && !i
.types
[1].bitfield
.byte
3830 && i
.op
[0].imms
->X_op
== O_constant
3831 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3832 && ((i
.tm
.base_opcode
== 0xa8
3833 && i
.tm
.extension_opcode
== None
)
3834 || (i
.tm
.base_opcode
== 0xf6
3835 && i
.tm
.extension_opcode
== 0x0)))
3838 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3840 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3841 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3843 i
.types
[1].bitfield
.byte
= 1;
3844 /* Ignore the suffix. */
3846 if (base_regnum
>= 4
3847 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3849 /* Handle SP, BP, SI and DI registers. */
3850 if (i
.types
[1].bitfield
.word
)
3852 else if (i
.types
[1].bitfield
.dword
)
3860 else if (flag_code
== CODE_64BIT
3861 && ((i
.types
[1].bitfield
.qword
3862 && i
.reg_operands
== 1
3863 && i
.imm_operands
== 1
3864 && i
.op
[0].imms
->X_op
== O_constant
3865 && ((i
.tm
.base_opcode
== 0xb0
3866 && i
.tm
.extension_opcode
== None
3867 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3868 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3869 && (((i
.tm
.base_opcode
== 0x24
3870 || i
.tm
.base_opcode
== 0xa8)
3871 && i
.tm
.extension_opcode
== None
)
3872 || (i
.tm
.base_opcode
== 0x80
3873 && i
.tm
.extension_opcode
== 0x4)
3874 || ((i
.tm
.base_opcode
== 0xf6
3875 || i
.tm
.base_opcode
== 0xc6)
3876 && i
.tm
.extension_opcode
== 0x0)))))
3877 || (i
.types
[0].bitfield
.qword
3878 && ((i
.reg_operands
== 2
3879 && i
.op
[0].regs
== i
.op
[1].regs
3880 && ((i
.tm
.base_opcode
== 0x30
3881 || i
.tm
.base_opcode
== 0x28)
3882 && i
.tm
.extension_opcode
== None
))
3883 || (i
.reg_operands
== 1
3885 && i
.tm
.base_opcode
== 0x30
3886 && i
.tm
.extension_opcode
== None
)))))
3889 andq $imm31, %r64 -> andl $imm31, %r32
3890 testq $imm31, %r64 -> testl $imm31, %r32
3891 xorq %r64, %r64 -> xorl %r32, %r32
3892 subq %r64, %r64 -> subl %r32, %r32
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3896 i
.tm
.opcode_modifier
.norex64
= 1;
3897 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3900 movq $imm31, %r64 -> movl $imm31, %r32
3901 movq $imm32, %r64 -> movl $imm32, %r32
3903 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3904 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3905 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3906 i
.types
[0].bitfield
.imm32
= 1;
3907 i
.types
[0].bitfield
.imm32s
= 0;
3908 i
.types
[0].bitfield
.imm64
= 0;
3909 i
.types
[1].bitfield
.dword
= 1;
3910 i
.types
[1].bitfield
.qword
= 0;
3911 if (i
.tm
.base_opcode
== 0xc6)
3914 movq $imm31, %r64 -> movl $imm31, %r32
3916 i
.tm
.base_opcode
= 0xb0;
3917 i
.tm
.extension_opcode
= None
;
3918 i
.tm
.opcode_modifier
.shortform
= 1;
3919 i
.tm
.opcode_modifier
.modrm
= 0;
3923 else if (optimize
> 1
3924 && i
.reg_operands
== 3
3925 && i
.op
[0].regs
== i
.op
[1].regs
3926 && !i
.types
[2].bitfield
.xmmword
3927 && (i
.tm
.opcode_modifier
.vex
3928 || ((!i
.mask
|| i
.mask
->zeroing
)
3930 && is_evex_encoding (&i
.tm
)
3931 && (i
.vec_encoding
!= vex_encoding_evex
3932 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3933 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3934 && i
.types
[2].bitfield
.ymmword
)
3935 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3936 && ((i
.tm
.base_opcode
== 0x55
3937 || i
.tm
.base_opcode
== 0x6655
3938 || i
.tm
.base_opcode
== 0x66df
3939 || i
.tm
.base_opcode
== 0x57
3940 || i
.tm
.base_opcode
== 0x6657
3941 || i
.tm
.base_opcode
== 0x66ef
3942 || i
.tm
.base_opcode
== 0x66f8
3943 || i
.tm
.base_opcode
== 0x66f9
3944 || i
.tm
.base_opcode
== 0x66fa
3945 || i
.tm
.base_opcode
== 0x66fb
3946 || i
.tm
.base_opcode
== 0x42
3947 || i
.tm
.base_opcode
== 0x6642
3948 || i
.tm
.base_opcode
== 0x47
3949 || i
.tm
.base_opcode
== 0x6647)
3950 && i
.tm
.extension_opcode
== None
))
3953 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3955 EVEX VOP %zmmM, %zmmM, %zmmN
3956 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3957 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3958 EVEX VOP %ymmM, %ymmM, %ymmN
3959 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3960 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3961 VEX VOP %ymmM, %ymmM, %ymmN
3962 -> VEX VOP %xmmM, %xmmM, %xmmN
3963 VOP, one of vpandn and vpxor:
3964 VEX VOP %ymmM, %ymmM, %ymmN
3965 -> VEX VOP %xmmM, %xmmM, %xmmN
3966 VOP, one of vpandnd and vpandnq:
3967 EVEX VOP %zmmM, %zmmM, %zmmN
3968 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3969 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3970 EVEX VOP %ymmM, %ymmM, %ymmN
3971 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3972 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3973 VOP, one of vpxord and vpxorq:
3974 EVEX VOP %zmmM, %zmmM, %zmmN
3975 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3976 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3977 EVEX VOP %ymmM, %ymmM, %ymmN
3978 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3979 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3980 VOP, one of kxord and kxorq:
3981 VEX VOP %kM, %kM, %kN
3982 -> VEX kxorw %kM, %kM, %kN
3983 VOP, one of kandnd and kandnq:
3984 VEX VOP %kM, %kM, %kN
3985 -> VEX kandnw %kM, %kM, %kN
3987 if (is_evex_encoding (&i
.tm
))
3989 if (i
.vec_encoding
== vex_encoding_evex
)
3990 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3993 i
.tm
.opcode_modifier
.vex
= VEX128
;
3994 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3995 i
.tm
.opcode_modifier
.evex
= 0;
3998 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4000 i
.tm
.base_opcode
&= 0xff;
4001 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4004 i
.tm
.opcode_modifier
.vex
= VEX128
;
4006 if (i
.tm
.opcode_modifier
.vex
)
4007 for (j
= 0; j
< 3; j
++)
4009 i
.types
[j
].bitfield
.xmmword
= 1;
4010 i
.types
[j
].bitfield
.ymmword
= 0;
4015 /* This is the guts of the machine-dependent assembler. LINE points to a
4016 machine dependent instruction. This function is supposed to emit
4017 the frags/bytes it assembles to. */
4020 md_assemble (char *line
)
4023 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4024 const insn_template
*t
;
4026 /* Initialize globals. */
4027 memset (&i
, '\0', sizeof (i
));
4028 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4029 i
.reloc
[j
] = NO_RELOC
;
4030 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4031 memset (im_expressions
, '\0', sizeof (im_expressions
));
4032 save_stack_p
= save_stack
;
4034 /* First parse an instruction mnemonic & call i386_operand for the operands.
4035 We assume that the scrubber has arranged it so that line[0] is the valid
4036 start of a (possibly prefixed) mnemonic. */
4038 line
= parse_insn (line
, mnemonic
);
4041 mnem_suffix
= i
.suffix
;
4043 line
= parse_operands (line
, mnemonic
);
4045 xfree (i
.memop1_string
);
4046 i
.memop1_string
= NULL
;
4050 /* Now we've parsed the mnemonic into a set of templates, and have the
4051 operands at hand. */
4053 /* All intel opcodes have reversed operands except for "bound" and
4054 "enter". We also don't reverse intersegment "jmp" and "call"
4055 instructions with 2 immediate operands so that the immediate segment
4056 precedes the offset, as it does when in AT&T mode. */
4059 && (strcmp (mnemonic
, "bound") != 0)
4060 && (strcmp (mnemonic
, "invlpga") != 0)
4061 && !(operand_type_check (i
.types
[0], imm
)
4062 && operand_type_check (i
.types
[1], imm
)))
4065 /* The order of the immediates should be reversed
4066 for 2 immediates extrq and insertq instructions */
4067 if (i
.imm_operands
== 2
4068 && (strcmp (mnemonic
, "extrq") == 0
4069 || strcmp (mnemonic
, "insertq") == 0))
4070 swap_2_operands (0, 1);
4075 /* Don't optimize displacement for movabs since it only takes 64bit
4078 && i
.disp_encoding
!= disp_encoding_32bit
4079 && (flag_code
!= CODE_64BIT
4080 || strcmp (mnemonic
, "movabs") != 0))
4083 /* Next, we find a template that matches the given insn,
4084 making sure the overlap of the given operands types is consistent
4085 with the template operand types. */
4087 if (!(t
= match_template (mnem_suffix
)))
4090 if (sse_check
!= check_none
4091 && !i
.tm
.opcode_modifier
.noavx
4092 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4093 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4094 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4095 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4096 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4097 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4098 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4099 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4100 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4101 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4103 (sse_check
== check_warning
4105 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4108 /* Zap movzx and movsx suffix. The suffix has been set from
4109 "word ptr" or "byte ptr" on the source operand in Intel syntax
4110 or extracted from mnemonic in AT&T syntax. But we'll use
4111 the destination register to choose the suffix for encoding. */
4112 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4114 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4115 there is no suffix, the default will be byte extension. */
4116 if (i
.reg_operands
!= 2
4119 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4124 if (i
.tm
.opcode_modifier
.fwait
)
4125 if (!add_prefix (FWAIT_OPCODE
))
4128 /* Check if REP prefix is OK. */
4129 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4131 as_bad (_("invalid instruction `%s' after `%s'"),
4132 i
.tm
.name
, i
.rep_prefix
);
4136 /* Check for lock without a lockable instruction. Destination operand
4137 must be memory unless it is xchg (0x86). */
4138 if (i
.prefix
[LOCK_PREFIX
]
4139 && (!i
.tm
.opcode_modifier
.islockable
4140 || i
.mem_operands
== 0
4141 || (i
.tm
.base_opcode
!= 0x86
4142 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4144 as_bad (_("expecting lockable instruction after `lock'"));
4148 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4149 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4151 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4155 /* Check if HLE prefix is OK. */
4156 if (i
.hle_prefix
&& !check_hle ())
4159 /* Check BND prefix. */
4160 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4161 as_bad (_("expecting valid branch instruction after `bnd'"));
4163 /* Check NOTRACK prefix. */
4164 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4165 as_bad (_("expecting indirect branch instruction after `notrack'"));
4167 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4169 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4170 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4171 else if (flag_code
!= CODE_16BIT
4172 ? i
.prefix
[ADDR_PREFIX
]
4173 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4174 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4177 /* Insert BND prefix. */
4178 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4180 if (!i
.prefix
[BND_PREFIX
])
4181 add_prefix (BND_PREFIX_OPCODE
);
4182 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4184 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4185 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4189 /* Check string instruction segment overrides. */
4190 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4192 if (!check_string ())
4194 i
.disp_operands
= 0;
4197 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4198 optimize_encoding ();
4200 if (!process_suffix ())
4203 /* Update operand types. */
4204 for (j
= 0; j
< i
.operands
; j
++)
4205 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4207 /* Make still unresolved immediate matches conform to size of immediate
4208 given in i.suffix. */
4209 if (!finalize_imm ())
4212 if (i
.types
[0].bitfield
.imm1
)
4213 i
.imm_operands
= 0; /* kludge for shift insns. */
4215 /* We only need to check those implicit registers for instructions
4216 with 3 operands or less. */
4217 if (i
.operands
<= 3)
4218 for (j
= 0; j
< i
.operands
; j
++)
4219 if (i
.types
[j
].bitfield
.inoutportreg
4220 || i
.types
[j
].bitfield
.shiftcount
4221 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4224 /* ImmExt should be processed after SSE2AVX. */
4225 if (!i
.tm
.opcode_modifier
.sse2avx
4226 && i
.tm
.opcode_modifier
.immext
)
4229 /* For insns with operands there are more diddles to do to the opcode. */
4232 if (!process_operands ())
4235 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4237 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4238 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4241 if (is_any_vex_encoding (&i
.tm
))
4243 if (flag_code
== CODE_16BIT
)
4245 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4250 if (i
.tm
.opcode_modifier
.vex
)
4251 build_vex_prefix (t
);
4253 build_evex_prefix ();
4256 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4257 instructions may define INT_OPCODE as well, so avoid this corner
4258 case for those instructions that use MODRM. */
4259 if (i
.tm
.base_opcode
== INT_OPCODE
4260 && !i
.tm
.opcode_modifier
.modrm
4261 && i
.op
[0].imms
->X_add_number
== 3)
4263 i
.tm
.base_opcode
= INT3_OPCODE
;
4267 if ((i
.tm
.opcode_modifier
.jump
4268 || i
.tm
.opcode_modifier
.jumpbyte
4269 || i
.tm
.opcode_modifier
.jumpdword
)
4270 && i
.op
[0].disps
->X_op
== O_constant
)
4272 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4273 the absolute address given by the constant. Since ix86 jumps and
4274 calls are pc relative, we need to generate a reloc. */
4275 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4276 i
.op
[0].disps
->X_op
= O_symbol
;
4279 if (i
.tm
.opcode_modifier
.rex64
)
4282 /* For 8 bit registers we need an empty rex prefix. Also if the
4283 instruction already has a prefix, we need to convert old
4284 registers to new ones. */
4286 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4287 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4288 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4289 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4290 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4291 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4296 i
.rex
|= REX_OPCODE
;
4297 for (x
= 0; x
< 2; x
++)
4299 /* Look for 8 bit operand that uses old registers. */
4300 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4301 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4303 /* In case it is "hi" register, give up. */
4304 if (i
.op
[x
].regs
->reg_num
> 3)
4305 as_bad (_("can't encode register '%s%s' in an "
4306 "instruction requiring REX prefix."),
4307 register_prefix
, i
.op
[x
].regs
->reg_name
);
4309 /* Otherwise it is equivalent to the extended register.
4310 Since the encoding doesn't change this is merely
4311 cosmetic cleanup for debug output. */
4313 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4318 if (i
.rex
== 0 && i
.rex_encoding
)
4320 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4321 that uses legacy register. If it is "hi" register, don't add
4322 the REX_OPCODE byte. */
4324 for (x
= 0; x
< 2; x
++)
4325 if (i
.types
[x
].bitfield
.reg
4326 && i
.types
[x
].bitfield
.byte
4327 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4328 && i
.op
[x
].regs
->reg_num
> 3)
4330 i
.rex_encoding
= FALSE
;
4339 add_prefix (REX_OPCODE
| i
.rex
);
4341 /* We are ready to output the insn. */
4346 parse_insn (char *line
, char *mnemonic
)
4349 char *token_start
= l
;
4352 const insn_template
*t
;
4358 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4363 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4365 as_bad (_("no such instruction: `%s'"), token_start
);
4370 if (!is_space_char (*l
)
4371 && *l
!= END_OF_INSN
4373 || (*l
!= PREFIX_SEPARATOR
4376 as_bad (_("invalid character %s in mnemonic"),
4377 output_invalid (*l
));
4380 if (token_start
== l
)
4382 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4383 as_bad (_("expecting prefix; got nothing"));
4385 as_bad (_("expecting mnemonic; got nothing"));
4389 /* Look up instruction (or prefix) via hash table. */
4390 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4392 if (*l
!= END_OF_INSN
4393 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4394 && current_templates
4395 && current_templates
->start
->opcode_modifier
.isprefix
)
4397 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4399 as_bad ((flag_code
!= CODE_64BIT
4400 ? _("`%s' is only supported in 64-bit mode")
4401 : _("`%s' is not supported in 64-bit mode")),
4402 current_templates
->start
->name
);
4405 /* If we are in 16-bit mode, do not allow addr16 or data16.
4406 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4407 if ((current_templates
->start
->opcode_modifier
.size16
4408 || current_templates
->start
->opcode_modifier
.size32
)
4409 && flag_code
!= CODE_64BIT
4410 && (current_templates
->start
->opcode_modifier
.size32
4411 ^ (flag_code
== CODE_16BIT
)))
4413 as_bad (_("redundant %s prefix"),
4414 current_templates
->start
->name
);
4417 if (current_templates
->start
->opcode_length
== 0)
4419 /* Handle pseudo prefixes. */
4420 switch (current_templates
->start
->base_opcode
)
4424 i
.disp_encoding
= disp_encoding_8bit
;
4428 i
.disp_encoding
= disp_encoding_32bit
;
4432 i
.dir_encoding
= dir_encoding_load
;
4436 i
.dir_encoding
= dir_encoding_store
;
4440 i
.vec_encoding
= vex_encoding_vex2
;
4444 i
.vec_encoding
= vex_encoding_vex3
;
4448 i
.vec_encoding
= vex_encoding_evex
;
4452 i
.rex_encoding
= TRUE
;
4456 i
.no_optimize
= TRUE
;
4464 /* Add prefix, checking for repeated prefixes. */
4465 switch (add_prefix (current_templates
->start
->base_opcode
))
4470 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4471 i
.notrack_prefix
= current_templates
->start
->name
;
4474 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4475 i
.hle_prefix
= current_templates
->start
->name
;
4476 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4477 i
.bnd_prefix
= current_templates
->start
->name
;
4479 i
.rep_prefix
= current_templates
->start
->name
;
4485 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4492 if (!current_templates
)
4494 /* Check if we should swap operand or force 32bit displacement in
4496 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4497 i
.dir_encoding
= dir_encoding_store
;
4498 else if (mnem_p
- 3 == dot_p
4501 i
.disp_encoding
= disp_encoding_8bit
;
4502 else if (mnem_p
- 4 == dot_p
4506 i
.disp_encoding
= disp_encoding_32bit
;
4511 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4514 if (!current_templates
)
4517 /* See if we can get a match by trimming off a suffix. */
4520 case WORD_MNEM_SUFFIX
:
4521 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4522 i
.suffix
= SHORT_MNEM_SUFFIX
;
4525 case BYTE_MNEM_SUFFIX
:
4526 case QWORD_MNEM_SUFFIX
:
4527 i
.suffix
= mnem_p
[-1];
4529 current_templates
= (const templates
*) hash_find (op_hash
,
4532 case SHORT_MNEM_SUFFIX
:
4533 case LONG_MNEM_SUFFIX
:
4536 i
.suffix
= mnem_p
[-1];
4538 current_templates
= (const templates
*) hash_find (op_hash
,
4547 if (intel_float_operand (mnemonic
) == 1)
4548 i
.suffix
= SHORT_MNEM_SUFFIX
;
4550 i
.suffix
= LONG_MNEM_SUFFIX
;
4552 current_templates
= (const templates
*) hash_find (op_hash
,
4557 if (!current_templates
)
4559 as_bad (_("no such instruction: `%s'"), token_start
);
4564 if (current_templates
->start
->opcode_modifier
.jump
4565 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4567 /* Check for a branch hint. We allow ",pt" and ",pn" for
4568 predict taken and predict not taken respectively.
4569 I'm not sure that branch hints actually do anything on loop
4570 and jcxz insns (JumpByte) for current Pentium4 chips. They
4571 may work in the future and it doesn't hurt to accept them
4573 if (l
[0] == ',' && l
[1] == 'p')
4577 if (!add_prefix (DS_PREFIX_OPCODE
))
4581 else if (l
[2] == 'n')
4583 if (!add_prefix (CS_PREFIX_OPCODE
))
4589 /* Any other comma loses. */
4592 as_bad (_("invalid character %s in mnemonic"),
4593 output_invalid (*l
));
4597 /* Check if instruction is supported on specified architecture. */
4599 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4601 supported
|= cpu_flags_match (t
);
4602 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4604 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4605 as_warn (_("use .code16 to ensure correct addressing mode"));
4611 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4612 as_bad (flag_code
== CODE_64BIT
4613 ? _("`%s' is not supported in 64-bit mode")
4614 : _("`%s' is only supported in 64-bit mode"),
4615 current_templates
->start
->name
);
4617 as_bad (_("`%s' is not supported on `%s%s'"),
4618 current_templates
->start
->name
,
4619 cpu_arch_name
? cpu_arch_name
: default_arch
,
4620 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4626 parse_operands (char *l
, const char *mnemonic
)
4630 /* 1 if operand is pending after ','. */
4631 unsigned int expecting_operand
= 0;
4633 /* Non-zero if operand parens not balanced. */
4634 unsigned int paren_not_balanced
;
4636 while (*l
!= END_OF_INSN
)
4638 /* Skip optional white space before operand. */
4639 if (is_space_char (*l
))
4641 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4643 as_bad (_("invalid character %s before operand %d"),
4644 output_invalid (*l
),
4648 token_start
= l
; /* After white space. */
4649 paren_not_balanced
= 0;
4650 while (paren_not_balanced
|| *l
!= ',')
4652 if (*l
== END_OF_INSN
)
4654 if (paren_not_balanced
)
4657 as_bad (_("unbalanced parenthesis in operand %d."),
4660 as_bad (_("unbalanced brackets in operand %d."),
4665 break; /* we are done */
4667 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4669 as_bad (_("invalid character %s in operand %d"),
4670 output_invalid (*l
),
4677 ++paren_not_balanced
;
4679 --paren_not_balanced
;
4684 ++paren_not_balanced
;
4686 --paren_not_balanced
;
4690 if (l
!= token_start
)
4691 { /* Yes, we've read in another operand. */
4692 unsigned int operand_ok
;
4693 this_operand
= i
.operands
++;
4694 if (i
.operands
> MAX_OPERANDS
)
4696 as_bad (_("spurious operands; (%d operands/instruction max)"),
4700 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4701 /* Now parse operand adding info to 'i' as we go along. */
4702 END_STRING_AND_SAVE (l
);
4704 if (i
.mem_operands
> 1)
4706 as_bad (_("too many memory references for `%s'"),
4713 i386_intel_operand (token_start
,
4714 intel_float_operand (mnemonic
));
4716 operand_ok
= i386_att_operand (token_start
);
4718 RESTORE_END_STRING (l
);
4724 if (expecting_operand
)
4726 expecting_operand_after_comma
:
4727 as_bad (_("expecting operand after ','; got nothing"));
4732 as_bad (_("expecting operand before ','; got nothing"));
4737 /* Now *l must be either ',' or END_OF_INSN. */
4740 if (*++l
== END_OF_INSN
)
4742 /* Just skip it, if it's \n complain. */
4743 goto expecting_operand_after_comma
;
4745 expecting_operand
= 1;
4752 swap_2_operands (int xchg1
, int xchg2
)
4754 union i386_op temp_op
;
4755 i386_operand_type temp_type
;
4756 unsigned int temp_flags
;
4757 enum bfd_reloc_code_real temp_reloc
;
4759 temp_type
= i
.types
[xchg2
];
4760 i
.types
[xchg2
] = i
.types
[xchg1
];
4761 i
.types
[xchg1
] = temp_type
;
4763 temp_flags
= i
.flags
[xchg2
];
4764 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4765 i
.flags
[xchg1
] = temp_flags
;
4767 temp_op
= i
.op
[xchg2
];
4768 i
.op
[xchg2
] = i
.op
[xchg1
];
4769 i
.op
[xchg1
] = temp_op
;
4771 temp_reloc
= i
.reloc
[xchg2
];
4772 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4773 i
.reloc
[xchg1
] = temp_reloc
;
4777 if (i
.mask
->operand
== xchg1
)
4778 i
.mask
->operand
= xchg2
;
4779 else if (i
.mask
->operand
== xchg2
)
4780 i
.mask
->operand
= xchg1
;
4784 if (i
.broadcast
->operand
== xchg1
)
4785 i
.broadcast
->operand
= xchg2
;
4786 else if (i
.broadcast
->operand
== xchg2
)
4787 i
.broadcast
->operand
= xchg1
;
4791 if (i
.rounding
->operand
== xchg1
)
4792 i
.rounding
->operand
= xchg2
;
4793 else if (i
.rounding
->operand
== xchg2
)
4794 i
.rounding
->operand
= xchg1
;
4799 swap_operands (void)
4805 swap_2_operands (1, i
.operands
- 2);
4809 swap_2_operands (0, i
.operands
- 1);
4815 if (i
.mem_operands
== 2)
4817 const seg_entry
*temp_seg
;
4818 temp_seg
= i
.seg
[0];
4819 i
.seg
[0] = i
.seg
[1];
4820 i
.seg
[1] = temp_seg
;
4824 /* Try to ensure constant immediates are represented in the smallest
4829 char guess_suffix
= 0;
4833 guess_suffix
= i
.suffix
;
4834 else if (i
.reg_operands
)
4836 /* Figure out a suffix from the last register operand specified.
4837 We can't do this properly yet, ie. excluding InOutPortReg,
4838 but the following works for instructions with immediates.
4839 In any case, we can't set i.suffix yet. */
4840 for (op
= i
.operands
; --op
>= 0;)
4841 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4843 guess_suffix
= BYTE_MNEM_SUFFIX
;
4846 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4848 guess_suffix
= WORD_MNEM_SUFFIX
;
4851 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4853 guess_suffix
= LONG_MNEM_SUFFIX
;
4856 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4858 guess_suffix
= QWORD_MNEM_SUFFIX
;
4862 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4863 guess_suffix
= WORD_MNEM_SUFFIX
;
4865 for (op
= i
.operands
; --op
>= 0;)
4866 if (operand_type_check (i
.types
[op
], imm
))
4868 switch (i
.op
[op
].imms
->X_op
)
4871 /* If a suffix is given, this operand may be shortened. */
4872 switch (guess_suffix
)
4874 case LONG_MNEM_SUFFIX
:
4875 i
.types
[op
].bitfield
.imm32
= 1;
4876 i
.types
[op
].bitfield
.imm64
= 1;
4878 case WORD_MNEM_SUFFIX
:
4879 i
.types
[op
].bitfield
.imm16
= 1;
4880 i
.types
[op
].bitfield
.imm32
= 1;
4881 i
.types
[op
].bitfield
.imm32s
= 1;
4882 i
.types
[op
].bitfield
.imm64
= 1;
4884 case BYTE_MNEM_SUFFIX
:
4885 i
.types
[op
].bitfield
.imm8
= 1;
4886 i
.types
[op
].bitfield
.imm8s
= 1;
4887 i
.types
[op
].bitfield
.imm16
= 1;
4888 i
.types
[op
].bitfield
.imm32
= 1;
4889 i
.types
[op
].bitfield
.imm32s
= 1;
4890 i
.types
[op
].bitfield
.imm64
= 1;
4894 /* If this operand is at most 16 bits, convert it
4895 to a signed 16 bit number before trying to see
4896 whether it will fit in an even smaller size.
4897 This allows a 16-bit operand such as $0xffe0 to
4898 be recognised as within Imm8S range. */
4899 if ((i
.types
[op
].bitfield
.imm16
)
4900 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4902 i
.op
[op
].imms
->X_add_number
=
4903 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4906 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4907 if ((i
.types
[op
].bitfield
.imm32
)
4908 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4911 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4912 ^ ((offsetT
) 1 << 31))
4913 - ((offsetT
) 1 << 31));
4917 = operand_type_or (i
.types
[op
],
4918 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4920 /* We must avoid matching of Imm32 templates when 64bit
4921 only immediate is available. */
4922 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4923 i
.types
[op
].bitfield
.imm32
= 0;
4930 /* Symbols and expressions. */
4932 /* Convert symbolic operand to proper sizes for matching, but don't
4933 prevent matching a set of insns that only supports sizes other
4934 than those matching the insn suffix. */
4936 i386_operand_type mask
, allowed
;
4937 const insn_template
*t
;
4939 operand_type_set (&mask
, 0);
4940 operand_type_set (&allowed
, 0);
4942 for (t
= current_templates
->start
;
4943 t
< current_templates
->end
;
4945 allowed
= operand_type_or (allowed
,
4946 t
->operand_types
[op
]);
4947 switch (guess_suffix
)
4949 case QWORD_MNEM_SUFFIX
:
4950 mask
.bitfield
.imm64
= 1;
4951 mask
.bitfield
.imm32s
= 1;
4953 case LONG_MNEM_SUFFIX
:
4954 mask
.bitfield
.imm32
= 1;
4956 case WORD_MNEM_SUFFIX
:
4957 mask
.bitfield
.imm16
= 1;
4959 case BYTE_MNEM_SUFFIX
:
4960 mask
.bitfield
.imm8
= 1;
4965 allowed
= operand_type_and (mask
, allowed
);
4966 if (!operand_type_all_zero (&allowed
))
4967 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4974 /* Try to use the smallest displacement type too. */
4976 optimize_disp (void)
4980 for (op
= i
.operands
; --op
>= 0;)
4981 if (operand_type_check (i
.types
[op
], disp
))
4983 if (i
.op
[op
].disps
->X_op
== O_constant
)
4985 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4987 if (i
.types
[op
].bitfield
.disp16
4988 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4990 /* If this operand is at most 16 bits, convert
4991 to a signed 16 bit number and don't use 64bit
4993 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4994 i
.types
[op
].bitfield
.disp64
= 0;
4997 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4998 if (i
.types
[op
].bitfield
.disp32
4999 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5001 /* If this operand is at most 32 bits, convert
5002 to a signed 32 bit number and don't use 64bit
5004 op_disp
&= (((offsetT
) 2 << 31) - 1);
5005 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5006 i
.types
[op
].bitfield
.disp64
= 0;
5009 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5011 i
.types
[op
].bitfield
.disp8
= 0;
5012 i
.types
[op
].bitfield
.disp16
= 0;
5013 i
.types
[op
].bitfield
.disp32
= 0;
5014 i
.types
[op
].bitfield
.disp32s
= 0;
5015 i
.types
[op
].bitfield
.disp64
= 0;
5019 else if (flag_code
== CODE_64BIT
)
5021 if (fits_in_signed_long (op_disp
))
5023 i
.types
[op
].bitfield
.disp64
= 0;
5024 i
.types
[op
].bitfield
.disp32s
= 1;
5026 if (i
.prefix
[ADDR_PREFIX
]
5027 && fits_in_unsigned_long (op_disp
))
5028 i
.types
[op
].bitfield
.disp32
= 1;
5030 if ((i
.types
[op
].bitfield
.disp32
5031 || i
.types
[op
].bitfield
.disp32s
5032 || i
.types
[op
].bitfield
.disp16
)
5033 && fits_in_disp8 (op_disp
))
5034 i
.types
[op
].bitfield
.disp8
= 1;
5036 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5037 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5039 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5040 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5041 i
.types
[op
].bitfield
.disp8
= 0;
5042 i
.types
[op
].bitfield
.disp16
= 0;
5043 i
.types
[op
].bitfield
.disp32
= 0;
5044 i
.types
[op
].bitfield
.disp32s
= 0;
5045 i
.types
[op
].bitfield
.disp64
= 0;
5048 /* We only support 64bit displacement on constants. */
5049 i
.types
[op
].bitfield
.disp64
= 0;
5053 /* Return 1 if there is a match in broadcast bytes between operand
5054 GIVEN and instruction template T. */
5057 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5059 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5060 && i
.types
[given
].bitfield
.byte
)
5061 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5062 && i
.types
[given
].bitfield
.word
)
5063 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5064 && i
.types
[given
].bitfield
.dword
)
5065 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5066 && i
.types
[given
].bitfield
.qword
));
5069 /* Check if operands are valid for the instruction. */
5072 check_VecOperands (const insn_template
*t
)
5076 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5078 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5079 any one operand are implicity requiring AVX512VL support if the actual
5080 operand size is YMMword or XMMword. Since this function runs after
5081 template matching, there's no need to check for YMMword/XMMword in
5083 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5084 if (!cpu_flags_all_zero (&cpu
)
5085 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5086 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5088 for (op
= 0; op
< t
->operands
; ++op
)
5090 if (t
->operand_types
[op
].bitfield
.zmmword
5091 && (i
.types
[op
].bitfield
.ymmword
5092 || i
.types
[op
].bitfield
.xmmword
))
5094 i
.error
= unsupported
;
5100 /* Without VSIB byte, we can't have a vector register for index. */
5101 if (!t
->opcode_modifier
.vecsib
5103 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5104 || i
.index_reg
->reg_type
.bitfield
.ymmword
5105 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5107 i
.error
= unsupported_vector_index_register
;
5111 /* Check if default mask is allowed. */
5112 if (t
->opcode_modifier
.nodefmask
5113 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5115 i
.error
= no_default_mask
;
5119 /* For VSIB byte, we need a vector register for index, and all vector
5120 registers must be distinct. */
5121 if (t
->opcode_modifier
.vecsib
)
5124 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5125 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5126 || (t
->opcode_modifier
.vecsib
== VecSIB256
5127 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5128 || (t
->opcode_modifier
.vecsib
== VecSIB512
5129 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5131 i
.error
= invalid_vsib_address
;
5135 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5136 if (i
.reg_operands
== 2 && !i
.mask
)
5138 gas_assert (i
.types
[0].bitfield
.regsimd
);
5139 gas_assert (i
.types
[0].bitfield
.xmmword
5140 || i
.types
[0].bitfield
.ymmword
);
5141 gas_assert (i
.types
[2].bitfield
.regsimd
);
5142 gas_assert (i
.types
[2].bitfield
.xmmword
5143 || i
.types
[2].bitfield
.ymmword
);
5144 if (operand_check
== check_none
)
5146 if (register_number (i
.op
[0].regs
)
5147 != register_number (i
.index_reg
)
5148 && register_number (i
.op
[2].regs
)
5149 != register_number (i
.index_reg
)
5150 && register_number (i
.op
[0].regs
)
5151 != register_number (i
.op
[2].regs
))
5153 if (operand_check
== check_error
)
5155 i
.error
= invalid_vector_register_set
;
5158 as_warn (_("mask, index, and destination registers should be distinct"));
5160 else if (i
.reg_operands
== 1 && i
.mask
)
5162 if (i
.types
[1].bitfield
.regsimd
5163 && (i
.types
[1].bitfield
.xmmword
5164 || i
.types
[1].bitfield
.ymmword
5165 || i
.types
[1].bitfield
.zmmword
)
5166 && (register_number (i
.op
[1].regs
)
5167 == register_number (i
.index_reg
)))
5169 if (operand_check
== check_error
)
5171 i
.error
= invalid_vector_register_set
;
5174 if (operand_check
!= check_none
)
5175 as_warn (_("index and destination registers should be distinct"));
5180 /* Check if broadcast is supported by the instruction and is applied
5181 to the memory operand. */
5184 i386_operand_type type
, overlap
;
5186 /* Check if specified broadcast is supported in this instruction,
5187 and its broadcast bytes match the memory operand. */
5188 op
= i
.broadcast
->operand
;
5189 if (!t
->opcode_modifier
.broadcast
5190 || !(i
.flags
[op
] & Operand_Mem
)
5191 || (!i
.types
[op
].bitfield
.unspecified
5192 && !match_broadcast_size (t
, op
)))
5195 i
.error
= unsupported_broadcast
;
5199 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5200 * i
.broadcast
->type
);
5201 operand_type_set (&type
, 0);
5202 switch (i
.broadcast
->bytes
)
5205 type
.bitfield
.word
= 1;
5208 type
.bitfield
.dword
= 1;
5211 type
.bitfield
.qword
= 1;
5214 type
.bitfield
.xmmword
= 1;
5217 type
.bitfield
.ymmword
= 1;
5220 type
.bitfield
.zmmword
= 1;
5226 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5227 if (operand_type_all_zero (&overlap
))
5230 if (t
->opcode_modifier
.checkregsize
)
5234 type
.bitfield
.baseindex
= 1;
5235 for (j
= 0; j
< i
.operands
; ++j
)
5238 && !operand_type_register_match(i
.types
[j
],
5239 t
->operand_types
[j
],
5241 t
->operand_types
[op
]))
5246 /* If broadcast is supported in this instruction, we need to check if
5247 operand of one-element size isn't specified without broadcast. */
5248 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5250 /* Find memory operand. */
5251 for (op
= 0; op
< i
.operands
; op
++)
5252 if (operand_type_check (i
.types
[op
], anymem
))
5254 gas_assert (op
< i
.operands
);
5255 /* Check size of the memory operand. */
5256 if (match_broadcast_size (t
, op
))
5258 i
.error
= broadcast_needed
;
5263 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5265 /* Check if requested masking is supported. */
5268 switch (t
->opcode_modifier
.masking
)
5272 case MERGING_MASKING
:
5273 if (i
.mask
->zeroing
)
5276 i
.error
= unsupported_masking
;
5280 case DYNAMIC_MASKING
:
5281 /* Memory destinations allow only merging masking. */
5282 if (i
.mask
->zeroing
&& i
.mem_operands
)
5284 /* Find memory operand. */
5285 for (op
= 0; op
< i
.operands
; op
++)
5286 if (i
.flags
[op
] & Operand_Mem
)
5288 gas_assert (op
< i
.operands
);
5289 if (op
== i
.operands
- 1)
5291 i
.error
= unsupported_masking
;
5301 /* Check if masking is applied to dest operand. */
5302 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5304 i
.error
= mask_not_on_destination
;
5311 if ((i
.rounding
->type
!= saeonly
5312 && !t
->opcode_modifier
.staticrounding
)
5313 || (i
.rounding
->type
== saeonly
5314 && (t
->opcode_modifier
.staticrounding
5315 || !t
->opcode_modifier
.sae
)))
5317 i
.error
= unsupported_rc_sae
;
5320 /* If the instruction has several immediate operands and one of
5321 them is rounding, the rounding operand should be the last
5322 immediate operand. */
5323 if (i
.imm_operands
> 1
5324 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5326 i
.error
= rc_sae_operand_not_last_imm
;
5331 /* Check vector Disp8 operand. */
5332 if (t
->opcode_modifier
.disp8memshift
5333 && i
.disp_encoding
!= disp_encoding_32bit
)
5336 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5337 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5338 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5341 const i386_operand_type
*type
= NULL
;
5344 for (op
= 0; op
< i
.operands
; op
++)
5345 if (operand_type_check (i
.types
[op
], anymem
))
5347 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5348 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5349 else if (t
->operand_types
[op
].bitfield
.xmmword
5350 + t
->operand_types
[op
].bitfield
.ymmword
5351 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5352 type
= &t
->operand_types
[op
];
5353 else if (!i
.types
[op
].bitfield
.unspecified
)
5354 type
= &i
.types
[op
];
5356 else if (i
.types
[op
].bitfield
.regsimd
5357 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5359 if (i
.types
[op
].bitfield
.zmmword
)
5361 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5363 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5369 if (type
->bitfield
.zmmword
)
5371 else if (type
->bitfield
.ymmword
)
5373 else if (type
->bitfield
.xmmword
)
5377 /* For the check in fits_in_disp8(). */
5378 if (i
.memshift
== 0)
5382 for (op
= 0; op
< i
.operands
; op
++)
5383 if (operand_type_check (i
.types
[op
], disp
)
5384 && i
.op
[op
].disps
->X_op
== O_constant
)
5386 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5388 i
.types
[op
].bitfield
.disp8
= 1;
5391 i
.types
[op
].bitfield
.disp8
= 0;
5400 /* Check if operands are valid for the instruction. Update VEX
5404 VEX_check_operands (const insn_template
*t
)
5406 if (i
.vec_encoding
== vex_encoding_evex
)
5408 /* This instruction must be encoded with EVEX prefix. */
5409 if (!is_evex_encoding (t
))
5411 i
.error
= unsupported
;
5417 if (!t
->opcode_modifier
.vex
)
5419 /* This instruction template doesn't have VEX prefix. */
5420 if (i
.vec_encoding
!= vex_encoding_default
)
5422 i
.error
= unsupported
;
5428 /* Only check VEX_Imm4, which must be the first operand. */
5429 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5431 if (i
.op
[0].imms
->X_op
!= O_constant
5432 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5438 /* Turn off Imm8 so that update_imm won't complain. */
5439 i
.types
[0] = vec_imm4
;
5445 static const insn_template
*
5446 match_template (char mnem_suffix
)
5448 /* Points to template once we've found it. */
5449 const insn_template
*t
;
5450 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5451 i386_operand_type overlap4
;
5452 unsigned int found_reverse_match
;
5453 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5454 i386_operand_type operand_types
[MAX_OPERANDS
];
5455 int addr_prefix_disp
;
5457 unsigned int found_cpu_match
, size_match
;
5458 unsigned int check_register
;
5459 enum i386_error specific_error
= 0;
5461 #if MAX_OPERANDS != 5
5462 # error "MAX_OPERANDS must be 5."
5465 found_reverse_match
= 0;
5466 addr_prefix_disp
= -1;
5468 memset (&suffix_check
, 0, sizeof (suffix_check
));
5469 if (intel_syntax
&& i
.broadcast
)
5471 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5472 suffix_check
.no_bsuf
= 1;
5473 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5474 suffix_check
.no_wsuf
= 1;
5475 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5476 suffix_check
.no_ssuf
= 1;
5477 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5478 suffix_check
.no_lsuf
= 1;
5479 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5480 suffix_check
.no_qsuf
= 1;
5481 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5482 suffix_check
.no_ldsuf
= 1;
5484 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5487 switch (mnem_suffix
)
5489 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5490 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5491 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5492 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5493 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5497 /* Must have right number of operands. */
5498 i
.error
= number_of_operands_mismatch
;
5500 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5502 addr_prefix_disp
= -1;
5504 if (i
.operands
!= t
->operands
)
5507 /* Check processor support. */
5508 i
.error
= unsupported
;
5509 found_cpu_match
= (cpu_flags_match (t
)
5510 == CPU_FLAGS_PERFECT_MATCH
);
5511 if (!found_cpu_match
)
5514 /* Check AT&T mnemonic. */
5515 i
.error
= unsupported_with_intel_mnemonic
;
5516 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5519 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5520 i
.error
= unsupported_syntax
;
5521 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5522 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5523 || (intel64
&& t
->opcode_modifier
.amd64
)
5524 || (!intel64
&& t
->opcode_modifier
.intel64
))
5527 /* Check the suffix, except for some instructions in intel mode. */
5528 i
.error
= invalid_instruction_suffix
;
5529 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5530 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5531 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5532 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5533 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5534 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5535 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5537 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5538 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5539 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5540 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5541 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5542 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5543 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5546 size_match
= operand_size_match (t
);
5550 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5551 operand_types
[j
] = t
->operand_types
[j
];
5553 /* In general, don't allow 64-bit operands in 32-bit mode. */
5554 if (i
.suffix
== QWORD_MNEM_SUFFIX
5555 && flag_code
!= CODE_64BIT
5557 ? (!t
->opcode_modifier
.ignoresize
5558 && !t
->opcode_modifier
.broadcast
5559 && !intel_float_operand (t
->name
))
5560 : intel_float_operand (t
->name
) != 2)
5561 && ((!operand_types
[0].bitfield
.regmmx
5562 && !operand_types
[0].bitfield
.regsimd
)
5563 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5564 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5565 && (t
->base_opcode
!= 0x0fc7
5566 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5569 /* In general, don't allow 32-bit operands on pre-386. */
5570 else if (i
.suffix
== LONG_MNEM_SUFFIX
5571 && !cpu_arch_flags
.bitfield
.cpui386
5573 ? (!t
->opcode_modifier
.ignoresize
5574 && !intel_float_operand (t
->name
))
5575 : intel_float_operand (t
->name
) != 2)
5576 && ((!operand_types
[0].bitfield
.regmmx
5577 && !operand_types
[0].bitfield
.regsimd
)
5578 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5579 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5582 /* Do not verify operands when there are none. */
5586 /* We've found a match; break out of loop. */
5590 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5591 into Disp32/Disp16/Disp32 operand. */
5592 if (i
.prefix
[ADDR_PREFIX
] != 0)
5594 /* There should be only one Disp operand. */
5598 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5600 if (operand_types
[j
].bitfield
.disp16
)
5602 addr_prefix_disp
= j
;
5603 operand_types
[j
].bitfield
.disp32
= 1;
5604 operand_types
[j
].bitfield
.disp16
= 0;
5610 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5612 if (operand_types
[j
].bitfield
.disp32
)
5614 addr_prefix_disp
= j
;
5615 operand_types
[j
].bitfield
.disp32
= 0;
5616 operand_types
[j
].bitfield
.disp16
= 1;
5622 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5624 if (operand_types
[j
].bitfield
.disp64
)
5626 addr_prefix_disp
= j
;
5627 operand_types
[j
].bitfield
.disp64
= 0;
5628 operand_types
[j
].bitfield
.disp32
= 1;
5636 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5637 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5640 /* We check register size if needed. */
5641 if (t
->opcode_modifier
.checkregsize
)
5643 check_register
= (1 << t
->operands
) - 1;
5645 check_register
&= ~(1 << i
.broadcast
->operand
);
5650 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5651 switch (t
->operands
)
5654 if (!operand_type_match (overlap0
, i
.types
[0]))
5658 /* xchg %eax, %eax is a special case. It is an alias for nop
5659 only in 32bit mode and we can use opcode 0x90. In 64bit
5660 mode, we can't use 0x90 for xchg %eax, %eax since it should
5661 zero-extend %eax to %rax. */
5662 if (flag_code
== CODE_64BIT
5663 && t
->base_opcode
== 0x90
5664 && operand_type_equal (&i
.types
[0], &acc32
)
5665 && operand_type_equal (&i
.types
[1], &acc32
))
5667 /* xrelease mov %eax, <disp> is another special case. It must not
5668 match the accumulator-only encoding of mov. */
5669 if (flag_code
!= CODE_64BIT
5671 && t
->base_opcode
== 0xa0
5672 && i
.types
[0].bitfield
.acc
5673 && operand_type_check (i
.types
[1], anymem
))
5675 if (!(size_match
& MATCH_STRAIGHT
))
5677 /* If we want store form, we reverse direction of operands. */
5678 if (i
.dir_encoding
== dir_encoding_store
5679 && t
->opcode_modifier
.d
)
5684 /* If we want store form, we skip the current load. */
5685 if (i
.dir_encoding
== dir_encoding_store
5686 && i
.mem_operands
== 0
5687 && t
->opcode_modifier
.load
)
5692 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5693 if (!operand_type_match (overlap0
, i
.types
[0])
5694 || !operand_type_match (overlap1
, i
.types
[1])
5695 || ((check_register
& 3) == 3
5696 && !operand_type_register_match (i
.types
[0],
5701 /* Check if other direction is valid ... */
5702 if (!t
->opcode_modifier
.d
)
5706 if (!(size_match
& MATCH_REVERSE
))
5708 /* Try reversing direction of operands. */
5709 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5710 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5711 if (!operand_type_match (overlap0
, i
.types
[0])
5712 || !operand_type_match (overlap1
, i
.types
[1])
5714 && !operand_type_register_match (i
.types
[0],
5719 /* Does not match either direction. */
5722 /* found_reverse_match holds which of D or FloatR
5724 if (!t
->opcode_modifier
.d
)
5725 found_reverse_match
= 0;
5726 else if (operand_types
[0].bitfield
.tbyte
)
5727 found_reverse_match
= Opcode_FloatD
;
5729 found_reverse_match
= Opcode_D
;
5730 if (t
->opcode_modifier
.floatr
)
5731 found_reverse_match
|= Opcode_FloatR
;
5735 /* Found a forward 2 operand match here. */
5736 switch (t
->operands
)
5739 overlap4
= operand_type_and (i
.types
[4],
5743 overlap3
= operand_type_and (i
.types
[3],
5747 overlap2
= operand_type_and (i
.types
[2],
5752 switch (t
->operands
)
5755 if (!operand_type_match (overlap4
, i
.types
[4])
5756 || !operand_type_register_match (i
.types
[3],
5763 if (!operand_type_match (overlap3
, i
.types
[3])
5764 || ((check_register
& 0xa) == 0xa
5765 && !operand_type_register_match (i
.types
[1],
5769 || ((check_register
& 0xc) == 0xc
5770 && !operand_type_register_match (i
.types
[2],
5777 /* Here we make use of the fact that there are no
5778 reverse match 3 operand instructions. */
5779 if (!operand_type_match (overlap2
, i
.types
[2])
5780 || ((check_register
& 5) == 5
5781 && !operand_type_register_match (i
.types
[0],
5785 || ((check_register
& 6) == 6
5786 && !operand_type_register_match (i
.types
[1],
5794 /* Found either forward/reverse 2, 3 or 4 operand match here:
5795 slip through to break. */
5797 if (!found_cpu_match
)
5799 found_reverse_match
= 0;
5803 /* Check if vector and VEX operands are valid. */
5804 if (check_VecOperands (t
) || VEX_check_operands (t
))
5806 specific_error
= i
.error
;
5810 /* We've found a match; break out of loop. */
5814 if (t
== current_templates
->end
)
5816 /* We found no match. */
5817 const char *err_msg
;
5818 switch (specific_error
? specific_error
: i
.error
)
5822 case operand_size_mismatch
:
5823 err_msg
= _("operand size mismatch");
5825 case operand_type_mismatch
:
5826 err_msg
= _("operand type mismatch");
5828 case register_type_mismatch
:
5829 err_msg
= _("register type mismatch");
5831 case number_of_operands_mismatch
:
5832 err_msg
= _("number of operands mismatch");
5834 case invalid_instruction_suffix
:
5835 err_msg
= _("invalid instruction suffix");
5838 err_msg
= _("constant doesn't fit in 4 bits");
5840 case unsupported_with_intel_mnemonic
:
5841 err_msg
= _("unsupported with Intel mnemonic");
5843 case unsupported_syntax
:
5844 err_msg
= _("unsupported syntax");
5847 as_bad (_("unsupported instruction `%s'"),
5848 current_templates
->start
->name
);
5850 case invalid_vsib_address
:
5851 err_msg
= _("invalid VSIB address");
5853 case invalid_vector_register_set
:
5854 err_msg
= _("mask, index, and destination registers must be distinct");
5856 case unsupported_vector_index_register
:
5857 err_msg
= _("unsupported vector index register");
5859 case unsupported_broadcast
:
5860 err_msg
= _("unsupported broadcast");
5862 case broadcast_needed
:
5863 err_msg
= _("broadcast is needed for operand of such type");
5865 case unsupported_masking
:
5866 err_msg
= _("unsupported masking");
5868 case mask_not_on_destination
:
5869 err_msg
= _("mask not on destination operand");
5871 case no_default_mask
:
5872 err_msg
= _("default mask isn't allowed");
5874 case unsupported_rc_sae
:
5875 err_msg
= _("unsupported static rounding/sae");
5877 case rc_sae_operand_not_last_imm
:
5879 err_msg
= _("RC/SAE operand must precede immediate operands");
5881 err_msg
= _("RC/SAE operand must follow immediate operands");
5883 case invalid_register_operand
:
5884 err_msg
= _("invalid register operand");
5887 as_bad (_("%s for `%s'"), err_msg
,
5888 current_templates
->start
->name
);
5892 if (!quiet_warnings
)
5895 && (i
.types
[0].bitfield
.jumpabsolute
5896 != operand_types
[0].bitfield
.jumpabsolute
))
5898 as_warn (_("indirect %s without `*'"), t
->name
);
5901 if (t
->opcode_modifier
.isprefix
5902 && t
->opcode_modifier
.ignoresize
)
5904 /* Warn them that a data or address size prefix doesn't
5905 affect assembly of the next line of code. */
5906 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5910 /* Copy the template we found. */
5913 if (addr_prefix_disp
!= -1)
5914 i
.tm
.operand_types
[addr_prefix_disp
]
5915 = operand_types
[addr_prefix_disp
];
5917 if (found_reverse_match
)
5919 /* If we found a reverse match we must alter the opcode
5920 direction bit. found_reverse_match holds bits to change
5921 (different for int & float insns). */
5923 i
.tm
.base_opcode
^= found_reverse_match
;
5925 i
.tm
.operand_types
[0] = operand_types
[1];
5926 i
.tm
.operand_types
[1] = operand_types
[0];
5935 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5936 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5938 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5940 as_bad (_("`%s' operand %d must use `%ses' segment"),
5946 /* There's only ever one segment override allowed per instruction.
5947 This instruction possibly has a legal segment override on the
5948 second operand, so copy the segment to where non-string
5949 instructions store it, allowing common code. */
5950 i
.seg
[0] = i
.seg
[1];
5952 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5954 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5956 as_bad (_("`%s' operand %d must use `%ses' segment"),
5967 process_suffix (void)
5969 /* If matched instruction specifies an explicit instruction mnemonic
5971 if (i
.tm
.opcode_modifier
.size16
)
5972 i
.suffix
= WORD_MNEM_SUFFIX
;
5973 else if (i
.tm
.opcode_modifier
.size32
)
5974 i
.suffix
= LONG_MNEM_SUFFIX
;
5975 else if (i
.tm
.opcode_modifier
.size64
)
5976 i
.suffix
= QWORD_MNEM_SUFFIX
;
5977 else if (i
.reg_operands
)
5979 /* If there's no instruction mnemonic suffix we try to invent one
5980 based on register operands. */
5983 /* We take i.suffix from the last register operand specified,
5984 Destination register type is more significant than source
5985 register type. crc32 in SSE4.2 prefers source register
5987 if (i
.tm
.base_opcode
== 0xf20f38f1)
5989 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5990 i
.suffix
= WORD_MNEM_SUFFIX
;
5991 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5992 i
.suffix
= LONG_MNEM_SUFFIX
;
5993 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5994 i
.suffix
= QWORD_MNEM_SUFFIX
;
5996 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5998 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5999 i
.suffix
= BYTE_MNEM_SUFFIX
;
6006 if (i
.tm
.base_opcode
== 0xf20f38f1
6007 || i
.tm
.base_opcode
== 0xf20f38f0)
6009 /* We have to know the operand size for crc32. */
6010 as_bad (_("ambiguous memory operand size for `%s`"),
6015 for (op
= i
.operands
; --op
>= 0;)
6016 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6017 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6019 if (!i
.types
[op
].bitfield
.reg
)
6021 if (i
.types
[op
].bitfield
.byte
)
6022 i
.suffix
= BYTE_MNEM_SUFFIX
;
6023 else if (i
.types
[op
].bitfield
.word
)
6024 i
.suffix
= WORD_MNEM_SUFFIX
;
6025 else if (i
.types
[op
].bitfield
.dword
)
6026 i
.suffix
= LONG_MNEM_SUFFIX
;
6027 else if (i
.types
[op
].bitfield
.qword
)
6028 i
.suffix
= QWORD_MNEM_SUFFIX
;
6035 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6038 && i
.tm
.opcode_modifier
.ignoresize
6039 && i
.tm
.opcode_modifier
.no_bsuf
)
6041 else if (!check_byte_reg ())
6044 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6047 && i
.tm
.opcode_modifier
.ignoresize
6048 && i
.tm
.opcode_modifier
.no_lsuf
6049 && !i
.tm
.opcode_modifier
.todword
6050 && !i
.tm
.opcode_modifier
.toqword
)
6052 else if (!check_long_reg ())
6055 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6058 && i
.tm
.opcode_modifier
.ignoresize
6059 && i
.tm
.opcode_modifier
.no_qsuf
6060 && !i
.tm
.opcode_modifier
.todword
6061 && !i
.tm
.opcode_modifier
.toqword
)
6063 else if (!check_qword_reg ())
6066 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6069 && i
.tm
.opcode_modifier
.ignoresize
6070 && i
.tm
.opcode_modifier
.no_wsuf
)
6072 else if (!check_word_reg ())
6075 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6076 /* Do nothing if the instruction is going to ignore the prefix. */
6081 else if (i
.tm
.opcode_modifier
.defaultsize
6083 /* exclude fldenv/frstor/fsave/fstenv */
6084 && i
.tm
.opcode_modifier
.no_ssuf
)
6086 i
.suffix
= stackop_size
;
6088 else if (intel_syntax
6090 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6091 || i
.tm
.opcode_modifier
.jumpbyte
6092 || i
.tm
.opcode_modifier
.jumpintersegment
6093 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6094 && i
.tm
.extension_opcode
<= 3)))
6099 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6101 i
.suffix
= QWORD_MNEM_SUFFIX
;
6106 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6107 i
.suffix
= LONG_MNEM_SUFFIX
;
6110 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6111 i
.suffix
= WORD_MNEM_SUFFIX
;
6120 if (i
.tm
.opcode_modifier
.w
)
6122 as_bad (_("no instruction mnemonic suffix given and "
6123 "no register operands; can't size instruction"));
6129 unsigned int suffixes
;
6131 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6132 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6134 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6136 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6138 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6140 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6143 /* There are more than suffix matches. */
6144 if (i
.tm
.opcode_modifier
.w
6145 || ((suffixes
& (suffixes
- 1))
6146 && !i
.tm
.opcode_modifier
.defaultsize
6147 && !i
.tm
.opcode_modifier
.ignoresize
))
6149 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6155 /* Change the opcode based on the operand size given by i.suffix. */
6158 /* Size floating point instruction. */
6159 case LONG_MNEM_SUFFIX
:
6160 if (i
.tm
.opcode_modifier
.floatmf
)
6162 i
.tm
.base_opcode
^= 4;
6166 case WORD_MNEM_SUFFIX
:
6167 case QWORD_MNEM_SUFFIX
:
6168 /* It's not a byte, select word/dword operation. */
6169 if (i
.tm
.opcode_modifier
.w
)
6171 if (i
.tm
.opcode_modifier
.shortform
)
6172 i
.tm
.base_opcode
|= 8;
6174 i
.tm
.base_opcode
|= 1;
6177 case SHORT_MNEM_SUFFIX
:
6178 /* Now select between word & dword operations via the operand
6179 size prefix, except for instructions that will ignore this
6181 if (i
.reg_operands
> 0
6182 && i
.types
[0].bitfield
.reg
6183 && i
.tm
.opcode_modifier
.addrprefixopreg
6184 && (i
.tm
.opcode_modifier
.immext
6185 || i
.operands
== 1))
6187 /* The address size override prefix changes the size of the
6189 if ((flag_code
== CODE_32BIT
6190 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6191 || (flag_code
!= CODE_32BIT
6192 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6193 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6196 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6197 && !i
.tm
.opcode_modifier
.ignoresize
6198 && !i
.tm
.opcode_modifier
.floatmf
6199 && !i
.tm
.opcode_modifier
.vex
6200 && !i
.tm
.opcode_modifier
.vexopcode
6201 && !is_evex_encoding (&i
.tm
)
6202 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6203 || (flag_code
== CODE_64BIT
6204 && i
.tm
.opcode_modifier
.jumpbyte
)))
6206 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6208 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6209 prefix
= ADDR_PREFIX_OPCODE
;
6211 if (!add_prefix (prefix
))
6215 /* Set mode64 for an operand. */
6216 if (i
.suffix
== QWORD_MNEM_SUFFIX
6217 && flag_code
== CODE_64BIT
6218 && !i
.tm
.opcode_modifier
.norex64
6219 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6221 && ! (i
.operands
== 2
6222 && i
.tm
.base_opcode
== 0x90
6223 && i
.tm
.extension_opcode
== None
6224 && operand_type_equal (&i
.types
[0], &acc64
)
6225 && operand_type_equal (&i
.types
[1], &acc64
)))
6231 if (i
.reg_operands
!= 0
6233 && i
.tm
.opcode_modifier
.addrprefixopreg
6234 && !i
.tm
.opcode_modifier
.immext
)
6236 /* Check invalid register operand when the address size override
6237 prefix changes the size of register operands. */
6239 enum { need_word
, need_dword
, need_qword
} need
;
6241 if (flag_code
== CODE_32BIT
)
6242 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6245 if (i
.prefix
[ADDR_PREFIX
])
6248 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6251 for (op
= 0; op
< i
.operands
; op
++)
6252 if (i
.types
[op
].bitfield
.reg
6253 && ((need
== need_word
6254 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6255 || (need
== need_dword
6256 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6257 || (need
== need_qword
6258 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6260 as_bad (_("invalid register operand size for `%s'"),
6270 check_byte_reg (void)
6274 for (op
= i
.operands
; --op
>= 0;)
6276 /* Skip non-register operands. */
6277 if (!i
.types
[op
].bitfield
.reg
)
6280 /* If this is an eight bit register, it's OK. If it's the 16 or
6281 32 bit version of an eight bit register, we will just use the
6282 low portion, and that's OK too. */
6283 if (i
.types
[op
].bitfield
.byte
)
6286 /* I/O port address operands are OK too. */
6287 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6290 /* crc32 doesn't generate this warning. */
6291 if (i
.tm
.base_opcode
== 0xf20f38f0)
6294 if ((i
.types
[op
].bitfield
.word
6295 || i
.types
[op
].bitfield
.dword
6296 || i
.types
[op
].bitfield
.qword
)
6297 && i
.op
[op
].regs
->reg_num
< 4
6298 /* Prohibit these changes in 64bit mode, since the lowering
6299 would be more complicated. */
6300 && flag_code
!= CODE_64BIT
)
6302 #if REGISTER_WARNINGS
6303 if (!quiet_warnings
)
6304 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6306 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6307 ? REGNAM_AL
- REGNAM_AX
6308 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6310 i
.op
[op
].regs
->reg_name
,
6315 /* Any other register is bad. */
6316 if (i
.types
[op
].bitfield
.reg
6317 || i
.types
[op
].bitfield
.regmmx
6318 || i
.types
[op
].bitfield
.regsimd
6319 || i
.types
[op
].bitfield
.sreg2
6320 || i
.types
[op
].bitfield
.sreg3
6321 || i
.types
[op
].bitfield
.control
6322 || i
.types
[op
].bitfield
.debug
6323 || i
.types
[op
].bitfield
.test
)
6325 as_bad (_("`%s%s' not allowed with `%s%c'"),
6327 i
.op
[op
].regs
->reg_name
,
6337 check_long_reg (void)
6341 for (op
= i
.operands
; --op
>= 0;)
6342 /* Skip non-register operands. */
6343 if (!i
.types
[op
].bitfield
.reg
)
6345 /* Reject eight bit registers, except where the template requires
6346 them. (eg. movzb) */
6347 else if (i
.types
[op
].bitfield
.byte
6348 && (i
.tm
.operand_types
[op
].bitfield
.reg
6349 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6350 && (i
.tm
.operand_types
[op
].bitfield
.word
6351 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6353 as_bad (_("`%s%s' not allowed with `%s%c'"),
6355 i
.op
[op
].regs
->reg_name
,
6360 /* Warn if the e prefix on a general reg is missing. */
6361 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6362 && i
.types
[op
].bitfield
.word
6363 && (i
.tm
.operand_types
[op
].bitfield
.reg
6364 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6365 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6367 /* Prohibit these changes in the 64bit mode, since the
6368 lowering is more complicated. */
6369 if (flag_code
== CODE_64BIT
)
6371 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6372 register_prefix
, i
.op
[op
].regs
->reg_name
,
6376 #if REGISTER_WARNINGS
6377 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6379 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6380 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6383 /* Warn if the r prefix on a general reg is present. */
6384 else if (i
.types
[op
].bitfield
.qword
6385 && (i
.tm
.operand_types
[op
].bitfield
.reg
6386 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6387 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6390 && i
.tm
.opcode_modifier
.toqword
6391 && !i
.types
[0].bitfield
.regsimd
)
6393 /* Convert to QWORD. We want REX byte. */
6394 i
.suffix
= QWORD_MNEM_SUFFIX
;
6398 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6399 register_prefix
, i
.op
[op
].regs
->reg_name
,
6408 check_qword_reg (void)
6412 for (op
= i
.operands
; --op
>= 0; )
6413 /* Skip non-register operands. */
6414 if (!i
.types
[op
].bitfield
.reg
)
6416 /* Reject eight bit registers, except where the template requires
6417 them. (eg. movzb) */
6418 else if (i
.types
[op
].bitfield
.byte
6419 && (i
.tm
.operand_types
[op
].bitfield
.reg
6420 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6421 && (i
.tm
.operand_types
[op
].bitfield
.word
6422 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6424 as_bad (_("`%s%s' not allowed with `%s%c'"),
6426 i
.op
[op
].regs
->reg_name
,
6431 /* Warn if the r prefix on a general reg is missing. */
6432 else if ((i
.types
[op
].bitfield
.word
6433 || i
.types
[op
].bitfield
.dword
)
6434 && (i
.tm
.operand_types
[op
].bitfield
.reg
6435 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6436 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6438 /* Prohibit these changes in the 64bit mode, since the
6439 lowering is more complicated. */
6441 && i
.tm
.opcode_modifier
.todword
6442 && !i
.types
[0].bitfield
.regsimd
)
6444 /* Convert to DWORD. We don't want REX byte. */
6445 i
.suffix
= LONG_MNEM_SUFFIX
;
6449 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6450 register_prefix
, i
.op
[op
].regs
->reg_name
,
6459 check_word_reg (void)
6462 for (op
= i
.operands
; --op
>= 0;)
6463 /* Skip non-register operands. */
6464 if (!i
.types
[op
].bitfield
.reg
)
6466 /* Reject eight bit registers, except where the template requires
6467 them. (eg. movzb) */
6468 else if (i
.types
[op
].bitfield
.byte
6469 && (i
.tm
.operand_types
[op
].bitfield
.reg
6470 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6471 && (i
.tm
.operand_types
[op
].bitfield
.word
6472 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6474 as_bad (_("`%s%s' not allowed with `%s%c'"),
6476 i
.op
[op
].regs
->reg_name
,
6481 /* Warn if the e or r prefix on a general reg is present. */
6482 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6483 && (i
.types
[op
].bitfield
.dword
6484 || i
.types
[op
].bitfield
.qword
)
6485 && (i
.tm
.operand_types
[op
].bitfield
.reg
6486 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6487 && i
.tm
.operand_types
[op
].bitfield
.word
)
6489 /* Prohibit these changes in the 64bit mode, since the
6490 lowering is more complicated. */
6491 if (flag_code
== CODE_64BIT
)
6493 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6494 register_prefix
, i
.op
[op
].regs
->reg_name
,
6498 #if REGISTER_WARNINGS
6499 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6501 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6502 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6509 update_imm (unsigned int j
)
6511 i386_operand_type overlap
= i
.types
[j
];
6512 if ((overlap
.bitfield
.imm8
6513 || overlap
.bitfield
.imm8s
6514 || overlap
.bitfield
.imm16
6515 || overlap
.bitfield
.imm32
6516 || overlap
.bitfield
.imm32s
6517 || overlap
.bitfield
.imm64
)
6518 && !operand_type_equal (&overlap
, &imm8
)
6519 && !operand_type_equal (&overlap
, &imm8s
)
6520 && !operand_type_equal (&overlap
, &imm16
)
6521 && !operand_type_equal (&overlap
, &imm32
)
6522 && !operand_type_equal (&overlap
, &imm32s
)
6523 && !operand_type_equal (&overlap
, &imm64
))
6527 i386_operand_type temp
;
6529 operand_type_set (&temp
, 0);
6530 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6532 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6533 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6535 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6536 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6537 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6539 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6540 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6543 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6546 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6547 || operand_type_equal (&overlap
, &imm16_32
)
6548 || operand_type_equal (&overlap
, &imm16_32s
))
6550 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6555 if (!operand_type_equal (&overlap
, &imm8
)
6556 && !operand_type_equal (&overlap
, &imm8s
)
6557 && !operand_type_equal (&overlap
, &imm16
)
6558 && !operand_type_equal (&overlap
, &imm32
)
6559 && !operand_type_equal (&overlap
, &imm32s
)
6560 && !operand_type_equal (&overlap
, &imm64
))
6562 as_bad (_("no instruction mnemonic suffix given; "
6563 "can't determine immediate size"));
6567 i
.types
[j
] = overlap
;
6577 /* Update the first 2 immediate operands. */
6578 n
= i
.operands
> 2 ? 2 : i
.operands
;
6581 for (j
= 0; j
< n
; j
++)
6582 if (update_imm (j
) == 0)
6585 /* The 3rd operand can't be immediate operand. */
6586 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6593 process_operands (void)
6595 /* Default segment register this instruction will use for memory
6596 accesses. 0 means unknown. This is only for optimizing out
6597 unnecessary segment overrides. */
6598 const seg_entry
*default_seg
= 0;
6600 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6602 unsigned int dupl
= i
.operands
;
6603 unsigned int dest
= dupl
- 1;
6606 /* The destination must be an xmm register. */
6607 gas_assert (i
.reg_operands
6608 && MAX_OPERANDS
> dupl
6609 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6611 if (i
.tm
.operand_types
[0].bitfield
.acc
6612 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6614 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6616 /* Keep xmm0 for instructions with VEX prefix and 3
6618 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6619 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6624 /* We remove the first xmm0 and keep the number of
6625 operands unchanged, which in fact duplicates the
6627 for (j
= 1; j
< i
.operands
; j
++)
6629 i
.op
[j
- 1] = i
.op
[j
];
6630 i
.types
[j
- 1] = i
.types
[j
];
6631 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6635 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6637 gas_assert ((MAX_OPERANDS
- 1) > dupl
6638 && (i
.tm
.opcode_modifier
.vexsources
6641 /* Add the implicit xmm0 for instructions with VEX prefix
6643 for (j
= i
.operands
; j
> 0; j
--)
6645 i
.op
[j
] = i
.op
[j
- 1];
6646 i
.types
[j
] = i
.types
[j
- 1];
6647 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6650 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6651 i
.types
[0] = regxmm
;
6652 i
.tm
.operand_types
[0] = regxmm
;
6655 i
.reg_operands
+= 2;
6660 i
.op
[dupl
] = i
.op
[dest
];
6661 i
.types
[dupl
] = i
.types
[dest
];
6662 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6671 i
.op
[dupl
] = i
.op
[dest
];
6672 i
.types
[dupl
] = i
.types
[dest
];
6673 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6676 if (i
.tm
.opcode_modifier
.immext
)
6679 else if (i
.tm
.operand_types
[0].bitfield
.acc
6680 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6684 for (j
= 1; j
< i
.operands
; j
++)
6686 i
.op
[j
- 1] = i
.op
[j
];
6687 i
.types
[j
- 1] = i
.types
[j
];
6689 /* We need to adjust fields in i.tm since they are used by
6690 build_modrm_byte. */
6691 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6698 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6700 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6702 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6703 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6704 regnum
= register_number (i
.op
[1].regs
);
6705 first_reg_in_group
= regnum
& ~3;
6706 last_reg_in_group
= first_reg_in_group
+ 3;
6707 if (regnum
!= first_reg_in_group
)
6708 as_warn (_("source register `%s%s' implicitly denotes"
6709 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6710 register_prefix
, i
.op
[1].regs
->reg_name
,
6711 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6712 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6715 else if (i
.tm
.opcode_modifier
.regkludge
)
6717 /* The imul $imm, %reg instruction is converted into
6718 imul $imm, %reg, %reg, and the clr %reg instruction
6719 is converted into xor %reg, %reg. */
6721 unsigned int first_reg_op
;
6723 if (operand_type_check (i
.types
[0], reg
))
6727 /* Pretend we saw the extra register operand. */
6728 gas_assert (i
.reg_operands
== 1
6729 && i
.op
[first_reg_op
+ 1].regs
== 0);
6730 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6731 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6736 if (i
.tm
.opcode_modifier
.shortform
)
6738 if (i
.types
[0].bitfield
.sreg2
6739 || i
.types
[0].bitfield
.sreg3
)
6741 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6742 && i
.op
[0].regs
->reg_num
== 1)
6744 as_bad (_("you can't `pop %scs'"), register_prefix
);
6747 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6748 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6753 /* The register or float register operand is in operand
6757 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6758 || operand_type_check (i
.types
[0], reg
))
6762 /* Register goes in low 3 bits of opcode. */
6763 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6764 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6766 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6768 /* Warn about some common errors, but press on regardless.
6769 The first case can be generated by gcc (<= 2.8.1). */
6770 if (i
.operands
== 2)
6772 /* Reversed arguments on faddp, fsubp, etc. */
6773 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6774 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6775 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6779 /* Extraneous `l' suffix on fp insn. */
6780 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6781 register_prefix
, i
.op
[0].regs
->reg_name
);
6786 else if (i
.tm
.opcode_modifier
.modrm
)
6788 /* The opcode is completed (modulo i.tm.extension_opcode which
6789 must be put into the modrm byte). Now, we make the modrm and
6790 index base bytes based on all the info we've collected. */
6792 default_seg
= build_modrm_byte ();
6794 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6798 else if (i
.tm
.opcode_modifier
.isstring
)
6800 /* For the string instructions that allow a segment override
6801 on one of their operands, the default segment is ds. */
6805 if (i
.tm
.base_opcode
== 0x8d /* lea */
6808 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6810 /* If a segment was explicitly specified, and the specified segment
6811 is not the default, use an opcode prefix to select it. If we
6812 never figured out what the default segment is, then default_seg
6813 will be zero at this point, and the specified segment prefix will
6815 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6817 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6823 static const seg_entry
*
6824 build_modrm_byte (void)
6826 const seg_entry
*default_seg
= 0;
6827 unsigned int source
, dest
;
6830 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6833 unsigned int nds
, reg_slot
;
6836 dest
= i
.operands
- 1;
6839 /* There are 2 kinds of instructions:
6840 1. 5 operands: 4 register operands or 3 register operands
6841 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6842 VexW0 or VexW1. The destination must be either XMM, YMM or
6844 2. 4 operands: 4 register operands or 3 register operands
6845 plus 1 memory operand, with VexXDS. */
6846 gas_assert ((i
.reg_operands
== 4
6847 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6848 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6849 && i
.tm
.opcode_modifier
.vexw
6850 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6852 /* If VexW1 is set, the first non-immediate operand is the source and
6853 the second non-immediate one is encoded in the immediate operand. */
6854 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6856 source
= i
.imm_operands
;
6857 reg_slot
= i
.imm_operands
+ 1;
6861 source
= i
.imm_operands
+ 1;
6862 reg_slot
= i
.imm_operands
;
6865 if (i
.imm_operands
== 0)
6867 /* When there is no immediate operand, generate an 8bit
6868 immediate operand to encode the first operand. */
6869 exp
= &im_expressions
[i
.imm_operands
++];
6870 i
.op
[i
.operands
].imms
= exp
;
6871 i
.types
[i
.operands
] = imm8
;
6874 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6875 exp
->X_op
= O_constant
;
6876 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6877 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6881 unsigned int imm_slot
;
6883 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6885 if (i
.tm
.opcode_modifier
.immext
)
6887 /* When ImmExt is set, the immediate byte is the last
6889 imm_slot
= i
.operands
- 1;
6897 /* Turn on Imm8 so that output_imm will generate it. */
6898 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6901 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6902 i
.op
[imm_slot
].imms
->X_add_number
6903 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6904 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6907 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6908 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6913 /* i.reg_operands MUST be the number of real register operands;
6914 implicit registers do not count. If there are 3 register
6915 operands, it must be a instruction with VexNDS. For a
6916 instruction with VexNDD, the destination register is encoded
6917 in VEX prefix. If there are 4 register operands, it must be
6918 a instruction with VEX prefix and 3 sources. */
6919 if (i
.mem_operands
== 0
6920 && ((i
.reg_operands
== 2
6921 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6922 || (i
.reg_operands
== 3
6923 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6924 || (i
.reg_operands
== 4 && vex_3_sources
)))
6932 /* When there are 3 operands, one of them may be immediate,
6933 which may be the first or the last operand. Otherwise,
6934 the first operand must be shift count register (cl) or it
6935 is an instruction with VexNDS. */
6936 gas_assert (i
.imm_operands
== 1
6937 || (i
.imm_operands
== 0
6938 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6939 || i
.types
[0].bitfield
.shiftcount
)));
6940 if (operand_type_check (i
.types
[0], imm
)
6941 || i
.types
[0].bitfield
.shiftcount
)
6947 /* When there are 4 operands, the first two must be 8bit
6948 immediate operands. The source operand will be the 3rd
6951 For instructions with VexNDS, if the first operand
6952 an imm8, the source operand is the 2nd one. If the last
6953 operand is imm8, the source operand is the first one. */
6954 gas_assert ((i
.imm_operands
== 2
6955 && i
.types
[0].bitfield
.imm8
6956 && i
.types
[1].bitfield
.imm8
)
6957 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6958 && i
.imm_operands
== 1
6959 && (i
.types
[0].bitfield
.imm8
6960 || i
.types
[i
.operands
- 1].bitfield
.imm8
6962 if (i
.imm_operands
== 2)
6966 if (i
.types
[0].bitfield
.imm8
)
6973 if (is_evex_encoding (&i
.tm
))
6975 /* For EVEX instructions, when there are 5 operands, the
6976 first one must be immediate operand. If the second one
6977 is immediate operand, the source operand is the 3th
6978 one. If the last one is immediate operand, the source
6979 operand is the 2nd one. */
6980 gas_assert (i
.imm_operands
== 2
6981 && i
.tm
.opcode_modifier
.sae
6982 && operand_type_check (i
.types
[0], imm
));
6983 if (operand_type_check (i
.types
[1], imm
))
6985 else if (operand_type_check (i
.types
[4], imm
))
6999 /* RC/SAE operand could be between DEST and SRC. That happens
7000 when one operand is GPR and the other one is XMM/YMM/ZMM
7002 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7005 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7007 /* For instructions with VexNDS, the register-only source
7008 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7009 register. It is encoded in VEX prefix. We need to
7010 clear RegMem bit before calling operand_type_equal. */
7012 i386_operand_type op
;
7015 /* Check register-only source operand when two source
7016 operands are swapped. */
7017 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7018 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7026 op
= i
.tm
.operand_types
[vvvv
];
7027 op
.bitfield
.regmem
= 0;
7028 if ((dest
+ 1) >= i
.operands
7029 || ((!op
.bitfield
.reg
7030 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7031 && !op
.bitfield
.regsimd
7032 && !operand_type_equal (&op
, ®mask
)))
7034 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7040 /* One of the register operands will be encoded in the i.tm.reg
7041 field, the other in the combined i.tm.mode and i.tm.regmem
7042 fields. If no form of this instruction supports a memory
7043 destination operand, then we assume the source operand may
7044 sometimes be a memory operand and so we need to store the
7045 destination in the i.rm.reg field. */
7046 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7047 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7049 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7050 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7051 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7053 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7055 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7057 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7062 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7063 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7064 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7066 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7068 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7070 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7073 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7075 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7078 add_prefix (LOCK_PREFIX_OPCODE
);
7082 { /* If it's not 2 reg operands... */
7087 unsigned int fake_zero_displacement
= 0;
7090 for (op
= 0; op
< i
.operands
; op
++)
7091 if (operand_type_check (i
.types
[op
], anymem
))
7093 gas_assert (op
< i
.operands
);
7095 if (i
.tm
.opcode_modifier
.vecsib
)
7097 if (i
.index_reg
->reg_num
== RegEiz
7098 || i
.index_reg
->reg_num
== RegRiz
)
7101 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7104 i
.sib
.base
= NO_BASE_REGISTER
;
7105 i
.sib
.scale
= i
.log2_scale_factor
;
7106 i
.types
[op
].bitfield
.disp8
= 0;
7107 i
.types
[op
].bitfield
.disp16
= 0;
7108 i
.types
[op
].bitfield
.disp64
= 0;
7109 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7111 /* Must be 32 bit */
7112 i
.types
[op
].bitfield
.disp32
= 1;
7113 i
.types
[op
].bitfield
.disp32s
= 0;
7117 i
.types
[op
].bitfield
.disp32
= 0;
7118 i
.types
[op
].bitfield
.disp32s
= 1;
7121 i
.sib
.index
= i
.index_reg
->reg_num
;
7122 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7124 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7130 if (i
.base_reg
== 0)
7133 if (!i
.disp_operands
)
7134 fake_zero_displacement
= 1;
7135 if (i
.index_reg
== 0)
7137 i386_operand_type newdisp
;
7139 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7140 /* Operand is just <disp> */
7141 if (flag_code
== CODE_64BIT
)
7143 /* 64bit mode overwrites the 32bit absolute
7144 addressing by RIP relative addressing and
7145 absolute addressing is encoded by one of the
7146 redundant SIB forms. */
7147 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7148 i
.sib
.base
= NO_BASE_REGISTER
;
7149 i
.sib
.index
= NO_INDEX_REGISTER
;
7150 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7152 else if ((flag_code
== CODE_16BIT
)
7153 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7155 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7160 i
.rm
.regmem
= NO_BASE_REGISTER
;
7163 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7164 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7166 else if (!i
.tm
.opcode_modifier
.vecsib
)
7168 /* !i.base_reg && i.index_reg */
7169 if (i
.index_reg
->reg_num
== RegEiz
7170 || i
.index_reg
->reg_num
== RegRiz
)
7171 i
.sib
.index
= NO_INDEX_REGISTER
;
7173 i
.sib
.index
= i
.index_reg
->reg_num
;
7174 i
.sib
.base
= NO_BASE_REGISTER
;
7175 i
.sib
.scale
= i
.log2_scale_factor
;
7176 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7177 i
.types
[op
].bitfield
.disp8
= 0;
7178 i
.types
[op
].bitfield
.disp16
= 0;
7179 i
.types
[op
].bitfield
.disp64
= 0;
7180 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7182 /* Must be 32 bit */
7183 i
.types
[op
].bitfield
.disp32
= 1;
7184 i
.types
[op
].bitfield
.disp32s
= 0;
7188 i
.types
[op
].bitfield
.disp32
= 0;
7189 i
.types
[op
].bitfield
.disp32s
= 1;
7191 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7195 /* RIP addressing for 64bit mode. */
7196 else if (i
.base_reg
->reg_num
== RegRip
||
7197 i
.base_reg
->reg_num
== RegEip
)
7199 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7200 i
.rm
.regmem
= NO_BASE_REGISTER
;
7201 i
.types
[op
].bitfield
.disp8
= 0;
7202 i
.types
[op
].bitfield
.disp16
= 0;
7203 i
.types
[op
].bitfield
.disp32
= 0;
7204 i
.types
[op
].bitfield
.disp32s
= 1;
7205 i
.types
[op
].bitfield
.disp64
= 0;
7206 i
.flags
[op
] |= Operand_PCrel
;
7207 if (! i
.disp_operands
)
7208 fake_zero_displacement
= 1;
7210 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7212 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7213 switch (i
.base_reg
->reg_num
)
7216 if (i
.index_reg
== 0)
7218 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7219 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7223 if (i
.index_reg
== 0)
7226 if (operand_type_check (i
.types
[op
], disp
) == 0)
7228 /* fake (%bp) into 0(%bp) */
7229 i
.types
[op
].bitfield
.disp8
= 1;
7230 fake_zero_displacement
= 1;
7233 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7234 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7236 default: /* (%si) -> 4 or (%di) -> 5 */
7237 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7239 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7241 else /* i.base_reg and 32/64 bit mode */
7243 if (flag_code
== CODE_64BIT
7244 && operand_type_check (i
.types
[op
], disp
))
7246 i
.types
[op
].bitfield
.disp16
= 0;
7247 i
.types
[op
].bitfield
.disp64
= 0;
7248 if (i
.prefix
[ADDR_PREFIX
] == 0)
7250 i
.types
[op
].bitfield
.disp32
= 0;
7251 i
.types
[op
].bitfield
.disp32s
= 1;
7255 i
.types
[op
].bitfield
.disp32
= 1;
7256 i
.types
[op
].bitfield
.disp32s
= 0;
7260 if (!i
.tm
.opcode_modifier
.vecsib
)
7261 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7262 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7264 i
.sib
.base
= i
.base_reg
->reg_num
;
7265 /* x86-64 ignores REX prefix bit here to avoid decoder
7267 if (!(i
.base_reg
->reg_flags
& RegRex
)
7268 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7269 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7271 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7273 fake_zero_displacement
= 1;
7274 i
.types
[op
].bitfield
.disp8
= 1;
7276 i
.sib
.scale
= i
.log2_scale_factor
;
7277 if (i
.index_reg
== 0)
7279 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7280 /* <disp>(%esp) becomes two byte modrm with no index
7281 register. We've already stored the code for esp
7282 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7283 Any base register besides %esp will not use the
7284 extra modrm byte. */
7285 i
.sib
.index
= NO_INDEX_REGISTER
;
7287 else if (!i
.tm
.opcode_modifier
.vecsib
)
7289 if (i
.index_reg
->reg_num
== RegEiz
7290 || i
.index_reg
->reg_num
== RegRiz
)
7291 i
.sib
.index
= NO_INDEX_REGISTER
;
7293 i
.sib
.index
= i
.index_reg
->reg_num
;
7294 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7295 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7300 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7301 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7305 if (!fake_zero_displacement
7309 fake_zero_displacement
= 1;
7310 if (i
.disp_encoding
== disp_encoding_8bit
)
7311 i
.types
[op
].bitfield
.disp8
= 1;
7313 i
.types
[op
].bitfield
.disp32
= 1;
7315 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7319 if (fake_zero_displacement
)
7321 /* Fakes a zero displacement assuming that i.types[op]
7322 holds the correct displacement size. */
7325 gas_assert (i
.op
[op
].disps
== 0);
7326 exp
= &disp_expressions
[i
.disp_operands
++];
7327 i
.op
[op
].disps
= exp
;
7328 exp
->X_op
= O_constant
;
7329 exp
->X_add_number
= 0;
7330 exp
->X_add_symbol
= (symbolS
*) 0;
7331 exp
->X_op_symbol
= (symbolS
*) 0;
7339 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7341 if (operand_type_check (i
.types
[0], imm
))
7342 i
.vex
.register_specifier
= NULL
;
7345 /* VEX.vvvv encodes one of the sources when the first
7346 operand is not an immediate. */
7347 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7348 i
.vex
.register_specifier
= i
.op
[0].regs
;
7350 i
.vex
.register_specifier
= i
.op
[1].regs
;
7353 /* Destination is a XMM register encoded in the ModRM.reg
7355 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7356 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7359 /* ModRM.rm and VEX.B encodes the other source. */
7360 if (!i
.mem_operands
)
7364 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7365 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7367 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7369 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7373 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7375 i
.vex
.register_specifier
= i
.op
[2].regs
;
7376 if (!i
.mem_operands
)
7379 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7380 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7384 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7385 (if any) based on i.tm.extension_opcode. Again, we must be
7386 careful to make sure that segment/control/debug/test/MMX
7387 registers are coded into the i.rm.reg field. */
7388 else if (i
.reg_operands
)
7391 unsigned int vex_reg
= ~0;
7393 for (op
= 0; op
< i
.operands
; op
++)
7394 if (i
.types
[op
].bitfield
.reg
7395 || i
.types
[op
].bitfield
.regmmx
7396 || i
.types
[op
].bitfield
.regsimd
7397 || i
.types
[op
].bitfield
.regbnd
7398 || i
.types
[op
].bitfield
.regmask
7399 || i
.types
[op
].bitfield
.sreg2
7400 || i
.types
[op
].bitfield
.sreg3
7401 || i
.types
[op
].bitfield
.control
7402 || i
.types
[op
].bitfield
.debug
7403 || i
.types
[op
].bitfield
.test
)
7408 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7410 /* For instructions with VexNDS, the register-only
7411 source operand is encoded in VEX prefix. */
7412 gas_assert (mem
!= (unsigned int) ~0);
7417 gas_assert (op
< i
.operands
);
7421 /* Check register-only source operand when two source
7422 operands are swapped. */
7423 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7424 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7428 gas_assert (mem
== (vex_reg
+ 1)
7429 && op
< i
.operands
);
7434 gas_assert (vex_reg
< i
.operands
);
7438 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7440 /* For instructions with VexNDD, the register destination
7441 is encoded in VEX prefix. */
7442 if (i
.mem_operands
== 0)
7444 /* There is no memory operand. */
7445 gas_assert ((op
+ 2) == i
.operands
);
7450 /* There are only 2 non-immediate operands. */
7451 gas_assert (op
< i
.imm_operands
+ 2
7452 && i
.operands
== i
.imm_operands
+ 2);
7453 vex_reg
= i
.imm_operands
+ 1;
7457 gas_assert (op
< i
.operands
);
7459 if (vex_reg
!= (unsigned int) ~0)
7461 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7463 if ((!type
->bitfield
.reg
7464 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7465 && !type
->bitfield
.regsimd
7466 && !operand_type_equal (type
, ®mask
))
7469 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7472 /* Don't set OP operand twice. */
7475 /* If there is an extension opcode to put here, the
7476 register number must be put into the regmem field. */
7477 if (i
.tm
.extension_opcode
!= None
)
7479 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7480 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7482 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7487 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7488 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7490 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7495 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7496 must set it to 3 to indicate this is a register operand
7497 in the regmem field. */
7498 if (!i
.mem_operands
)
7502 /* Fill in i.rm.reg field with extension opcode (if any). */
7503 if (i
.tm
.extension_opcode
!= None
)
7504 i
.rm
.reg
= i
.tm
.extension_opcode
;
7510 output_branch (void)
7516 relax_substateT subtype
;
7520 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7521 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7524 if (i
.prefix
[DATA_PREFIX
] != 0)
7530 /* Pentium4 branch hints. */
7531 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7532 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7537 if (i
.prefix
[REX_PREFIX
] != 0)
7543 /* BND prefixed jump. */
7544 if (i
.prefix
[BND_PREFIX
] != 0)
7546 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7550 if (i
.prefixes
!= 0 && !intel_syntax
)
7551 as_warn (_("skipping prefixes on this instruction"));
7553 /* It's always a symbol; End frag & setup for relax.
7554 Make sure there is enough room in this frag for the largest
7555 instruction we may generate in md_convert_frag. This is 2
7556 bytes for the opcode and room for the prefix and largest
7558 frag_grow (prefix
+ 2 + 4);
7559 /* Prefix and 1 opcode byte go in fr_fix. */
7560 p
= frag_more (prefix
+ 1);
7561 if (i
.prefix
[DATA_PREFIX
] != 0)
7562 *p
++ = DATA_PREFIX_OPCODE
;
7563 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7564 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7565 *p
++ = i
.prefix
[SEG_PREFIX
];
7566 if (i
.prefix
[REX_PREFIX
] != 0)
7567 *p
++ = i
.prefix
[REX_PREFIX
];
7568 *p
= i
.tm
.base_opcode
;
7570 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7571 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7572 else if (cpu_arch_flags
.bitfield
.cpui386
)
7573 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7575 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7578 sym
= i
.op
[0].disps
->X_add_symbol
;
7579 off
= i
.op
[0].disps
->X_add_number
;
7581 if (i
.op
[0].disps
->X_op
!= O_constant
7582 && i
.op
[0].disps
->X_op
!= O_symbol
)
7584 /* Handle complex expressions. */
7585 sym
= make_expr_symbol (i
.op
[0].disps
);
7589 /* 1 possible extra opcode + 4 byte displacement go in var part.
7590 Pass reloc in fr_var. */
7591 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7595 /* Return TRUE iff PLT32 relocation should be used for branching to
7599 need_plt32_p (symbolS
*s
)
7601 /* PLT32 relocation is ELF only. */
7605 /* Since there is no need to prepare for PLT branch on x86-64, we
7606 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7607 be used as a marker for 32-bit PC-relative branches. */
7611 /* Weak or undefined symbol need PLT32 relocation. */
7612 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7615 /* Non-global symbol doesn't need PLT32 relocation. */
7616 if (! S_IS_EXTERNAL (s
))
7619 /* Other global symbols need PLT32 relocation. NB: Symbol with
7620 non-default visibilities are treated as normal global symbol
7621 so that PLT32 relocation can be used as a marker for 32-bit
7622 PC-relative branches. It is useful for linker relaxation. */
7633 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7635 if (i
.tm
.opcode_modifier
.jumpbyte
)
7637 /* This is a loop or jecxz type instruction. */
7639 if (i
.prefix
[ADDR_PREFIX
] != 0)
7641 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7644 /* Pentium4 branch hints. */
7645 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7646 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7648 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7657 if (flag_code
== CODE_16BIT
)
7660 if (i
.prefix
[DATA_PREFIX
] != 0)
7662 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7672 if (i
.prefix
[REX_PREFIX
] != 0)
7674 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7678 /* BND prefixed jump. */
7679 if (i
.prefix
[BND_PREFIX
] != 0)
7681 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7685 if (i
.prefixes
!= 0 && !intel_syntax
)
7686 as_warn (_("skipping prefixes on this instruction"));
7688 p
= frag_more (i
.tm
.opcode_length
+ size
);
7689 switch (i
.tm
.opcode_length
)
7692 *p
++ = i
.tm
.base_opcode
>> 8;
7695 *p
++ = i
.tm
.base_opcode
;
7701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7703 && jump_reloc
== NO_RELOC
7704 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7705 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7708 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7710 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7711 i
.op
[0].disps
, 1, jump_reloc
);
7713 /* All jumps handled here are signed, but don't use a signed limit
7714 check for 32 and 16 bit jumps as we want to allow wrap around at
7715 4G and 64k respectively. */
7717 fixP
->fx_signed
= 1;
7721 output_interseg_jump (void)
7729 if (flag_code
== CODE_16BIT
)
7733 if (i
.prefix
[DATA_PREFIX
] != 0)
7739 if (i
.prefix
[REX_PREFIX
] != 0)
7749 if (i
.prefixes
!= 0 && !intel_syntax
)
7750 as_warn (_("skipping prefixes on this instruction"));
7752 /* 1 opcode; 2 segment; offset */
7753 p
= frag_more (prefix
+ 1 + 2 + size
);
7755 if (i
.prefix
[DATA_PREFIX
] != 0)
7756 *p
++ = DATA_PREFIX_OPCODE
;
7758 if (i
.prefix
[REX_PREFIX
] != 0)
7759 *p
++ = i
.prefix
[REX_PREFIX
];
7761 *p
++ = i
.tm
.base_opcode
;
7762 if (i
.op
[1].imms
->X_op
== O_constant
)
7764 offsetT n
= i
.op
[1].imms
->X_add_number
;
7767 && !fits_in_unsigned_word (n
)
7768 && !fits_in_signed_word (n
))
7770 as_bad (_("16-bit jump out of range"));
7773 md_number_to_chars (p
, n
, size
);
7776 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7777 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7778 if (i
.op
[0].imms
->X_op
!= O_constant
)
7779 as_bad (_("can't handle non absolute segment in `%s'"),
7781 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7787 fragS
*insn_start_frag
;
7788 offsetT insn_start_off
;
7790 /* Tie dwarf2 debug info to the address at the start of the insn.
7791 We can't do this after the insn has been output as the current
7792 frag may have been closed off. eg. by frag_var. */
7793 dwarf2_emit_insn (0);
7795 insn_start_frag
= frag_now
;
7796 insn_start_off
= frag_now_fix ();
7799 if (i
.tm
.opcode_modifier
.jump
)
7801 else if (i
.tm
.opcode_modifier
.jumpbyte
7802 || i
.tm
.opcode_modifier
.jumpdword
)
7804 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7805 output_interseg_jump ();
7808 /* Output normal instructions here. */
7812 unsigned int prefix
;
7815 && i
.tm
.base_opcode
== 0xfae
7817 && i
.imm_operands
== 1
7818 && (i
.op
[0].imms
->X_add_number
== 0xe8
7819 || i
.op
[0].imms
->X_add_number
== 0xf0
7820 || i
.op
[0].imms
->X_add_number
== 0xf8))
7822 /* Encode lfence, mfence, and sfence as
7823 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7824 offsetT val
= 0x240483f0ULL
;
7826 md_number_to_chars (p
, val
, 5);
7830 /* Some processors fail on LOCK prefix. This options makes
7831 assembler ignore LOCK prefix and serves as a workaround. */
7832 if (omit_lock_prefix
)
7834 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7836 i
.prefix
[LOCK_PREFIX
] = 0;
7839 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7840 don't need the explicit prefix. */
7841 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7843 switch (i
.tm
.opcode_length
)
7846 if (i
.tm
.base_opcode
& 0xff000000)
7848 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7849 add_prefix (prefix
);
7853 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7855 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7856 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7857 || prefix
!= REPE_PREFIX_OPCODE
7858 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7859 add_prefix (prefix
);
7865 /* Check for pseudo prefixes. */
7866 as_bad_where (insn_start_frag
->fr_file
,
7867 insn_start_frag
->fr_line
,
7868 _("pseudo prefix without instruction"));
7874 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7875 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7876 R_X86_64_GOTTPOFF relocation so that linker can safely
7877 perform IE->LE optimization. */
7878 if (x86_elf_abi
== X86_64_X32_ABI
7880 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7881 && i
.prefix
[REX_PREFIX
] == 0)
7882 add_prefix (REX_OPCODE
);
7885 /* The prefix bytes. */
7886 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7888 FRAG_APPEND_1_CHAR (*q
);
7892 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7897 /* REX byte is encoded in VEX prefix. */
7901 FRAG_APPEND_1_CHAR (*q
);
7904 /* There should be no other prefixes for instructions
7909 /* For EVEX instructions i.vrex should become 0 after
7910 build_evex_prefix. For VEX instructions upper 16 registers
7911 aren't available, so VREX should be 0. */
7914 /* Now the VEX prefix. */
7915 p
= frag_more (i
.vex
.length
);
7916 for (j
= 0; j
< i
.vex
.length
; j
++)
7917 p
[j
] = i
.vex
.bytes
[j
];
7920 /* Now the opcode; be careful about word order here! */
7921 if (i
.tm
.opcode_length
== 1)
7923 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7927 switch (i
.tm
.opcode_length
)
7931 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7932 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7936 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7946 /* Put out high byte first: can't use md_number_to_chars! */
7947 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7948 *p
= i
.tm
.base_opcode
& 0xff;
7951 /* Now the modrm byte and sib byte (if present). */
7952 if (i
.tm
.opcode_modifier
.modrm
)
7954 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7957 /* If i.rm.regmem == ESP (4)
7958 && i.rm.mode != (Register mode)
7960 ==> need second modrm byte. */
7961 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7963 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7964 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7966 | i
.sib
.scale
<< 6));
7969 if (i
.disp_operands
)
7970 output_disp (insn_start_frag
, insn_start_off
);
7973 output_imm (insn_start_frag
, insn_start_off
);
7979 pi ("" /*line*/, &i
);
7981 #endif /* DEBUG386 */
7984 /* Return the size of the displacement operand N. */
7987 disp_size (unsigned int n
)
7991 if (i
.types
[n
].bitfield
.disp64
)
7993 else if (i
.types
[n
].bitfield
.disp8
)
7995 else if (i
.types
[n
].bitfield
.disp16
)
8000 /* Return the size of the immediate operand N. */
8003 imm_size (unsigned int n
)
8006 if (i
.types
[n
].bitfield
.imm64
)
8008 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8010 else if (i
.types
[n
].bitfield
.imm16
)
8016 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8021 for (n
= 0; n
< i
.operands
; n
++)
8023 if (operand_type_check (i
.types
[n
], disp
))
8025 if (i
.op
[n
].disps
->X_op
== O_constant
)
8027 int size
= disp_size (n
);
8028 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8030 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8032 p
= frag_more (size
);
8033 md_number_to_chars (p
, val
, size
);
8037 enum bfd_reloc_code_real reloc_type
;
8038 int size
= disp_size (n
);
8039 int sign
= i
.types
[n
].bitfield
.disp32s
;
8040 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8043 /* We can't have 8 bit displacement here. */
8044 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8046 /* The PC relative address is computed relative
8047 to the instruction boundary, so in case immediate
8048 fields follows, we need to adjust the value. */
8049 if (pcrel
&& i
.imm_operands
)
8054 for (n1
= 0; n1
< i
.operands
; n1
++)
8055 if (operand_type_check (i
.types
[n1
], imm
))
8057 /* Only one immediate is allowed for PC
8058 relative address. */
8059 gas_assert (sz
== 0);
8061 i
.op
[n
].disps
->X_add_number
-= sz
;
8063 /* We should find the immediate. */
8064 gas_assert (sz
!= 0);
8067 p
= frag_more (size
);
8068 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8070 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8071 && (((reloc_type
== BFD_RELOC_32
8072 || reloc_type
== BFD_RELOC_X86_64_32S
8073 || (reloc_type
== BFD_RELOC_64
8075 && (i
.op
[n
].disps
->X_op
== O_symbol
8076 || (i
.op
[n
].disps
->X_op
== O_add
8077 && ((symbol_get_value_expression
8078 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8080 || reloc_type
== BFD_RELOC_32_PCREL
))
8084 if (insn_start_frag
== frag_now
)
8085 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8090 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8091 for (fr
= insn_start_frag
->fr_next
;
8092 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8094 add
+= p
- frag_now
->fr_literal
;
8099 reloc_type
= BFD_RELOC_386_GOTPC
;
8100 i
.op
[n
].imms
->X_add_number
+= add
;
8102 else if (reloc_type
== BFD_RELOC_64
)
8103 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8105 /* Don't do the adjustment for x86-64, as there
8106 the pcrel addressing is relative to the _next_
8107 insn, and that is taken care of in other code. */
8108 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8110 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8111 size
, i
.op
[n
].disps
, pcrel
,
8113 /* Check for "call/jmp *mem", "mov mem, %reg",
8114 "test %reg, mem" and "binop mem, %reg" where binop
8115 is one of adc, add, and, cmp, or, sbb, sub, xor
8116 instructions. Always generate R_386_GOT32X for
8117 "sym*GOT" operand in 32-bit mode. */
8118 if ((generate_relax_relocations
8121 && i
.rm
.regmem
== 5))
8123 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8124 && ((i
.operands
== 1
8125 && i
.tm
.base_opcode
== 0xff
8126 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8128 && (i
.tm
.base_opcode
== 0x8b
8129 || i
.tm
.base_opcode
== 0x85
8130 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8134 fixP
->fx_tcbit
= i
.rex
!= 0;
8136 && (i
.base_reg
->reg_num
== RegRip
8137 || i
.base_reg
->reg_num
== RegEip
))
8138 fixP
->fx_tcbit2
= 1;
8141 fixP
->fx_tcbit2
= 1;
8149 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8154 for (n
= 0; n
< i
.operands
; n
++)
8156 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8157 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8160 if (operand_type_check (i
.types
[n
], imm
))
8162 if (i
.op
[n
].imms
->X_op
== O_constant
)
8164 int size
= imm_size (n
);
8167 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8169 p
= frag_more (size
);
8170 md_number_to_chars (p
, val
, size
);
8174 /* Not absolute_section.
8175 Need a 32-bit fixup (don't support 8bit
8176 non-absolute imms). Try to support other
8178 enum bfd_reloc_code_real reloc_type
;
8179 int size
= imm_size (n
);
8182 if (i
.types
[n
].bitfield
.imm32s
8183 && (i
.suffix
== QWORD_MNEM_SUFFIX
8184 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8189 p
= frag_more (size
);
8190 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8192 /* This is tough to explain. We end up with this one if we
8193 * have operands that look like
8194 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8195 * obtain the absolute address of the GOT, and it is strongly
8196 * preferable from a performance point of view to avoid using
8197 * a runtime relocation for this. The actual sequence of
8198 * instructions often look something like:
8203 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8205 * The call and pop essentially return the absolute address
8206 * of the label .L66 and store it in %ebx. The linker itself
8207 * will ultimately change the first operand of the addl so
8208 * that %ebx points to the GOT, but to keep things simple, the
8209 * .o file must have this operand set so that it generates not
8210 * the absolute address of .L66, but the absolute address of
8211 * itself. This allows the linker itself simply treat a GOTPC
8212 * relocation as asking for a pcrel offset to the GOT to be
8213 * added in, and the addend of the relocation is stored in the
8214 * operand field for the instruction itself.
8216 * Our job here is to fix the operand so that it would add
8217 * the correct offset so that %ebx would point to itself. The
8218 * thing that is tricky is that .-.L66 will point to the
8219 * beginning of the instruction, so we need to further modify
8220 * the operand so that it will point to itself. There are
8221 * other cases where you have something like:
8223 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8225 * and here no correction would be required. Internally in
8226 * the assembler we treat operands of this form as not being
8227 * pcrel since the '.' is explicitly mentioned, and I wonder
8228 * whether it would simplify matters to do it this way. Who
8229 * knows. In earlier versions of the PIC patches, the
8230 * pcrel_adjust field was used to store the correction, but
8231 * since the expression is not pcrel, I felt it would be
8232 * confusing to do it this way. */
8234 if ((reloc_type
== BFD_RELOC_32
8235 || reloc_type
== BFD_RELOC_X86_64_32S
8236 || reloc_type
== BFD_RELOC_64
)
8238 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8239 && (i
.op
[n
].imms
->X_op
== O_symbol
8240 || (i
.op
[n
].imms
->X_op
== O_add
8241 && ((symbol_get_value_expression
8242 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8247 if (insn_start_frag
== frag_now
)
8248 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8253 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8254 for (fr
= insn_start_frag
->fr_next
;
8255 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8257 add
+= p
- frag_now
->fr_literal
;
8261 reloc_type
= BFD_RELOC_386_GOTPC
;
8263 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8265 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8266 i
.op
[n
].imms
->X_add_number
+= add
;
8268 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8269 i
.op
[n
].imms
, 0, reloc_type
);
8275 /* x86_cons_fix_new is called via the expression parsing code when a
8276 reloc is needed. We use this hook to get the correct .got reloc. */
8277 static int cons_sign
= -1;
8280 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8281 expressionS
*exp
, bfd_reloc_code_real_type r
)
8283 r
= reloc (len
, 0, cons_sign
, r
);
8286 if (exp
->X_op
== O_secrel
)
8288 exp
->X_op
= O_symbol
;
8289 r
= BFD_RELOC_32_SECREL
;
8293 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8296 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8297 purpose of the `.dc.a' internal pseudo-op. */
8300 x86_address_bytes (void)
8302 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8304 return stdoutput
->arch_info
->bits_per_address
/ 8;
8307 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8309 # define lex_got(reloc, adjust, types) NULL
8311 /* Parse operands of the form
8312 <symbol>@GOTOFF+<nnn>
8313 and similar .plt or .got references.
8315 If we find one, set up the correct relocation in RELOC and copy the
8316 input string, minus the `@GOTOFF' into a malloc'd buffer for
8317 parsing by the calling routine. Return this buffer, and if ADJUST
8318 is non-null set it to the length of the string we removed from the
8319 input line. Otherwise return NULL. */
8321 lex_got (enum bfd_reloc_code_real
*rel
,
8323 i386_operand_type
*types
)
8325 /* Some of the relocations depend on the size of what field is to
8326 be relocated. But in our callers i386_immediate and i386_displacement
8327 we don't yet know the operand size (this will be set by insn
8328 matching). Hence we record the word32 relocation here,
8329 and adjust the reloc according to the real size in reloc(). */
8330 static const struct {
8333 const enum bfd_reloc_code_real rel
[2];
8334 const i386_operand_type types64
;
8336 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8337 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8339 OPERAND_TYPE_IMM32_64
},
8341 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8342 BFD_RELOC_X86_64_PLTOFF64
},
8343 OPERAND_TYPE_IMM64
},
8344 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8345 BFD_RELOC_X86_64_PLT32
},
8346 OPERAND_TYPE_IMM32_32S_DISP32
},
8347 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8348 BFD_RELOC_X86_64_GOTPLT64
},
8349 OPERAND_TYPE_IMM64_DISP64
},
8350 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8351 BFD_RELOC_X86_64_GOTOFF64
},
8352 OPERAND_TYPE_IMM64_DISP64
},
8353 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8354 BFD_RELOC_X86_64_GOTPCREL
},
8355 OPERAND_TYPE_IMM32_32S_DISP32
},
8356 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8357 BFD_RELOC_X86_64_TLSGD
},
8358 OPERAND_TYPE_IMM32_32S_DISP32
},
8359 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8360 _dummy_first_bfd_reloc_code_real
},
8361 OPERAND_TYPE_NONE
},
8362 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8363 BFD_RELOC_X86_64_TLSLD
},
8364 OPERAND_TYPE_IMM32_32S_DISP32
},
8365 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8366 BFD_RELOC_X86_64_GOTTPOFF
},
8367 OPERAND_TYPE_IMM32_32S_DISP32
},
8368 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8369 BFD_RELOC_X86_64_TPOFF32
},
8370 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8371 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8372 _dummy_first_bfd_reloc_code_real
},
8373 OPERAND_TYPE_NONE
},
8374 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8375 BFD_RELOC_X86_64_DTPOFF32
},
8376 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8377 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8378 _dummy_first_bfd_reloc_code_real
},
8379 OPERAND_TYPE_NONE
},
8380 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8381 _dummy_first_bfd_reloc_code_real
},
8382 OPERAND_TYPE_NONE
},
8383 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8384 BFD_RELOC_X86_64_GOT32
},
8385 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8386 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8387 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8388 OPERAND_TYPE_IMM32_32S_DISP32
},
8389 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8390 BFD_RELOC_X86_64_TLSDESC_CALL
},
8391 OPERAND_TYPE_IMM32_32S_DISP32
},
8396 #if defined (OBJ_MAYBE_ELF)
8401 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8402 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8405 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8407 int len
= gotrel
[j
].len
;
8408 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8410 if (gotrel
[j
].rel
[object_64bit
] != 0)
8413 char *tmpbuf
, *past_reloc
;
8415 *rel
= gotrel
[j
].rel
[object_64bit
];
8419 if (flag_code
!= CODE_64BIT
)
8421 types
->bitfield
.imm32
= 1;
8422 types
->bitfield
.disp32
= 1;
8425 *types
= gotrel
[j
].types64
;
8428 if (j
!= 0 && GOT_symbol
== NULL
)
8429 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8431 /* The length of the first part of our input line. */
8432 first
= cp
- input_line_pointer
;
8434 /* The second part goes from after the reloc token until
8435 (and including) an end_of_line char or comma. */
8436 past_reloc
= cp
+ 1 + len
;
8438 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8440 second
= cp
+ 1 - past_reloc
;
8442 /* Allocate and copy string. The trailing NUL shouldn't
8443 be necessary, but be safe. */
8444 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8445 memcpy (tmpbuf
, input_line_pointer
, first
);
8446 if (second
!= 0 && *past_reloc
!= ' ')
8447 /* Replace the relocation token with ' ', so that
8448 errors like foo@GOTOFF1 will be detected. */
8449 tmpbuf
[first
++] = ' ';
8451 /* Increment length by 1 if the relocation token is
8456 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8457 tmpbuf
[first
+ second
] = '\0';
8461 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8462 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8467 /* Might be a symbol version string. Don't as_bad here. */
8476 /* Parse operands of the form
8477 <symbol>@SECREL32+<nnn>
8479 If we find one, set up the correct relocation in RELOC and copy the
8480 input string, minus the `@SECREL32' into a malloc'd buffer for
8481 parsing by the calling routine. Return this buffer, and if ADJUST
8482 is non-null set it to the length of the string we removed from the
8483 input line. Otherwise return NULL.
8485 This function is copied from the ELF version above adjusted for PE targets. */
8488 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8489 int *adjust ATTRIBUTE_UNUSED
,
8490 i386_operand_type
*types
)
8496 const enum bfd_reloc_code_real rel
[2];
8497 const i386_operand_type types64
;
8501 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8502 BFD_RELOC_32_SECREL
},
8503 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8509 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8510 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8513 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8515 int len
= gotrel
[j
].len
;
8517 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8519 if (gotrel
[j
].rel
[object_64bit
] != 0)
8522 char *tmpbuf
, *past_reloc
;
8524 *rel
= gotrel
[j
].rel
[object_64bit
];
8530 if (flag_code
!= CODE_64BIT
)
8532 types
->bitfield
.imm32
= 1;
8533 types
->bitfield
.disp32
= 1;
8536 *types
= gotrel
[j
].types64
;
8539 /* The length of the first part of our input line. */
8540 first
= cp
- input_line_pointer
;
8542 /* The second part goes from after the reloc token until
8543 (and including) an end_of_line char or comma. */
8544 past_reloc
= cp
+ 1 + len
;
8546 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8548 second
= cp
+ 1 - past_reloc
;
8550 /* Allocate and copy string. The trailing NUL shouldn't
8551 be necessary, but be safe. */
8552 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8553 memcpy (tmpbuf
, input_line_pointer
, first
);
8554 if (second
!= 0 && *past_reloc
!= ' ')
8555 /* Replace the relocation token with ' ', so that
8556 errors like foo@SECLREL321 will be detected. */
8557 tmpbuf
[first
++] = ' ';
8558 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8559 tmpbuf
[first
+ second
] = '\0';
8563 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8564 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8569 /* Might be a symbol version string. Don't as_bad here. */
8575 bfd_reloc_code_real_type
8576 x86_cons (expressionS
*exp
, int size
)
8578 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8580 intel_syntax
= -intel_syntax
;
8583 if (size
== 4 || (object_64bit
&& size
== 8))
8585 /* Handle @GOTOFF and the like in an expression. */
8587 char *gotfree_input_line
;
8590 save
= input_line_pointer
;
8591 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8592 if (gotfree_input_line
)
8593 input_line_pointer
= gotfree_input_line
;
8597 if (gotfree_input_line
)
8599 /* expression () has merrily parsed up to the end of line,
8600 or a comma - in the wrong buffer. Transfer how far
8601 input_line_pointer has moved to the right buffer. */
8602 input_line_pointer
= (save
8603 + (input_line_pointer
- gotfree_input_line
)
8605 free (gotfree_input_line
);
8606 if (exp
->X_op
== O_constant
8607 || exp
->X_op
== O_absent
8608 || exp
->X_op
== O_illegal
8609 || exp
->X_op
== O_register
8610 || exp
->X_op
== O_big
)
8612 char c
= *input_line_pointer
;
8613 *input_line_pointer
= 0;
8614 as_bad (_("missing or invalid expression `%s'"), save
);
8615 *input_line_pointer
= c
;
8622 intel_syntax
= -intel_syntax
;
8625 i386_intel_simplify (exp
);
8631 signed_cons (int size
)
8633 if (flag_code
== CODE_64BIT
)
8641 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8648 if (exp
.X_op
== O_symbol
)
8649 exp
.X_op
= O_secrel
;
8651 emit_expr (&exp
, 4);
8653 while (*input_line_pointer
++ == ',');
8655 input_line_pointer
--;
8656 demand_empty_rest_of_line ();
8660 /* Handle Vector operations. */
8663 check_VecOperations (char *op_string
, char *op_end
)
8665 const reg_entry
*mask
;
8670 && (op_end
== NULL
|| op_string
< op_end
))
8673 if (*op_string
== '{')
8677 /* Check broadcasts. */
8678 if (strncmp (op_string
, "1to", 3) == 0)
8683 goto duplicated_vec_op
;
8686 if (*op_string
== '8')
8688 else if (*op_string
== '4')
8690 else if (*op_string
== '2')
8692 else if (*op_string
== '1'
8693 && *(op_string
+1) == '6')
8700 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8705 broadcast_op
.type
= bcst_type
;
8706 broadcast_op
.operand
= this_operand
;
8707 broadcast_op
.bytes
= 0;
8708 i
.broadcast
= &broadcast_op
;
8710 /* Check masking operation. */
8711 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8713 /* k0 can't be used for write mask. */
8714 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8716 as_bad (_("`%s%s' can't be used for write mask"),
8717 register_prefix
, mask
->reg_name
);
8723 mask_op
.mask
= mask
;
8724 mask_op
.zeroing
= 0;
8725 mask_op
.operand
= this_operand
;
8731 goto duplicated_vec_op
;
8733 i
.mask
->mask
= mask
;
8735 /* Only "{z}" is allowed here. No need to check
8736 zeroing mask explicitly. */
8737 if (i
.mask
->operand
!= this_operand
)
8739 as_bad (_("invalid write mask `%s'"), saved
);
8746 /* Check zeroing-flag for masking operation. */
8747 else if (*op_string
== 'z')
8751 mask_op
.mask
= NULL
;
8752 mask_op
.zeroing
= 1;
8753 mask_op
.operand
= this_operand
;
8758 if (i
.mask
->zeroing
)
8761 as_bad (_("duplicated `%s'"), saved
);
8765 i
.mask
->zeroing
= 1;
8767 /* Only "{%k}" is allowed here. No need to check mask
8768 register explicitly. */
8769 if (i
.mask
->operand
!= this_operand
)
8771 as_bad (_("invalid zeroing-masking `%s'"),
8780 goto unknown_vec_op
;
8782 if (*op_string
!= '}')
8784 as_bad (_("missing `}' in `%s'"), saved
);
8789 /* Strip whitespace since the addition of pseudo prefixes
8790 changed how the scrubber treats '{'. */
8791 if (is_space_char (*op_string
))
8797 /* We don't know this one. */
8798 as_bad (_("unknown vector operation: `%s'"), saved
);
8802 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8804 as_bad (_("zeroing-masking only allowed with write mask"));
8812 i386_immediate (char *imm_start
)
8814 char *save_input_line_pointer
;
8815 char *gotfree_input_line
;
8818 i386_operand_type types
;
8820 operand_type_set (&types
, ~0);
8822 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8824 as_bad (_("at most %d immediate operands are allowed"),
8825 MAX_IMMEDIATE_OPERANDS
);
8829 exp
= &im_expressions
[i
.imm_operands
++];
8830 i
.op
[this_operand
].imms
= exp
;
8832 if (is_space_char (*imm_start
))
8835 save_input_line_pointer
= input_line_pointer
;
8836 input_line_pointer
= imm_start
;
8838 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8839 if (gotfree_input_line
)
8840 input_line_pointer
= gotfree_input_line
;
8842 exp_seg
= expression (exp
);
8846 /* Handle vector operations. */
8847 if (*input_line_pointer
== '{')
8849 input_line_pointer
= check_VecOperations (input_line_pointer
,
8851 if (input_line_pointer
== NULL
)
8855 if (*input_line_pointer
)
8856 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8858 input_line_pointer
= save_input_line_pointer
;
8859 if (gotfree_input_line
)
8861 free (gotfree_input_line
);
8863 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8864 exp
->X_op
= O_illegal
;
8867 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8871 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8872 i386_operand_type types
, const char *imm_start
)
8874 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8877 as_bad (_("missing or invalid immediate expression `%s'"),
8881 else if (exp
->X_op
== O_constant
)
8883 /* Size it properly later. */
8884 i
.types
[this_operand
].bitfield
.imm64
= 1;
8885 /* If not 64bit, sign extend val. */
8886 if (flag_code
!= CODE_64BIT
8887 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8889 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8891 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8892 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8893 && exp_seg
!= absolute_section
8894 && exp_seg
!= text_section
8895 && exp_seg
!= data_section
8896 && exp_seg
!= bss_section
8897 && exp_seg
!= undefined_section
8898 && !bfd_is_com_section (exp_seg
))
8900 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8904 else if (!intel_syntax
&& exp_seg
== reg_section
)
8907 as_bad (_("illegal immediate register operand %s"), imm_start
);
8912 /* This is an address. The size of the address will be
8913 determined later, depending on destination register,
8914 suffix, or the default for the section. */
8915 i
.types
[this_operand
].bitfield
.imm8
= 1;
8916 i
.types
[this_operand
].bitfield
.imm16
= 1;
8917 i
.types
[this_operand
].bitfield
.imm32
= 1;
8918 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8919 i
.types
[this_operand
].bitfield
.imm64
= 1;
8920 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8928 i386_scale (char *scale
)
8931 char *save
= input_line_pointer
;
8933 input_line_pointer
= scale
;
8934 val
= get_absolute_expression ();
8939 i
.log2_scale_factor
= 0;
8942 i
.log2_scale_factor
= 1;
8945 i
.log2_scale_factor
= 2;
8948 i
.log2_scale_factor
= 3;
8952 char sep
= *input_line_pointer
;
8954 *input_line_pointer
= '\0';
8955 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8957 *input_line_pointer
= sep
;
8958 input_line_pointer
= save
;
8962 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8964 as_warn (_("scale factor of %d without an index register"),
8965 1 << i
.log2_scale_factor
);
8966 i
.log2_scale_factor
= 0;
8968 scale
= input_line_pointer
;
8969 input_line_pointer
= save
;
8974 i386_displacement (char *disp_start
, char *disp_end
)
8978 char *save_input_line_pointer
;
8979 char *gotfree_input_line
;
8981 i386_operand_type bigdisp
, types
= anydisp
;
8984 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8986 as_bad (_("at most %d displacement operands are allowed"),
8987 MAX_MEMORY_OPERANDS
);
8991 operand_type_set (&bigdisp
, 0);
8992 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8993 || (!current_templates
->start
->opcode_modifier
.jump
8994 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8996 bigdisp
.bitfield
.disp32
= 1;
8997 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8998 if (flag_code
== CODE_64BIT
)
9002 bigdisp
.bitfield
.disp32s
= 1;
9003 bigdisp
.bitfield
.disp64
= 1;
9006 else if ((flag_code
== CODE_16BIT
) ^ override
)
9008 bigdisp
.bitfield
.disp32
= 0;
9009 bigdisp
.bitfield
.disp16
= 1;
9014 /* For PC-relative branches, the width of the displacement
9015 is dependent upon data size, not address size. */
9016 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9017 if (flag_code
== CODE_64BIT
)
9019 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9020 bigdisp
.bitfield
.disp16
= 1;
9023 bigdisp
.bitfield
.disp32
= 1;
9024 bigdisp
.bitfield
.disp32s
= 1;
9030 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9032 : LONG_MNEM_SUFFIX
));
9033 bigdisp
.bitfield
.disp32
= 1;
9034 if ((flag_code
== CODE_16BIT
) ^ override
)
9036 bigdisp
.bitfield
.disp32
= 0;
9037 bigdisp
.bitfield
.disp16
= 1;
9041 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9044 exp
= &disp_expressions
[i
.disp_operands
];
9045 i
.op
[this_operand
].disps
= exp
;
9047 save_input_line_pointer
= input_line_pointer
;
9048 input_line_pointer
= disp_start
;
9049 END_STRING_AND_SAVE (disp_end
);
9051 #ifndef GCC_ASM_O_HACK
9052 #define GCC_ASM_O_HACK 0
9055 END_STRING_AND_SAVE (disp_end
+ 1);
9056 if (i
.types
[this_operand
].bitfield
.baseIndex
9057 && displacement_string_end
[-1] == '+')
9059 /* This hack is to avoid a warning when using the "o"
9060 constraint within gcc asm statements.
9063 #define _set_tssldt_desc(n,addr,limit,type) \
9064 __asm__ __volatile__ ( \
9066 "movw %w1,2+%0\n\t" \
9068 "movb %b1,4+%0\n\t" \
9069 "movb %4,5+%0\n\t" \
9070 "movb $0,6+%0\n\t" \
9071 "movb %h1,7+%0\n\t" \
9073 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9075 This works great except that the output assembler ends
9076 up looking a bit weird if it turns out that there is
9077 no offset. You end up producing code that looks like:
9090 So here we provide the missing zero. */
9092 *displacement_string_end
= '0';
9095 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9096 if (gotfree_input_line
)
9097 input_line_pointer
= gotfree_input_line
;
9099 exp_seg
= expression (exp
);
9102 if (*input_line_pointer
)
9103 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9105 RESTORE_END_STRING (disp_end
+ 1);
9107 input_line_pointer
= save_input_line_pointer
;
9108 if (gotfree_input_line
)
9110 free (gotfree_input_line
);
9112 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9113 exp
->X_op
= O_illegal
;
9116 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9118 RESTORE_END_STRING (disp_end
);
9124 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9125 i386_operand_type types
, const char *disp_start
)
9127 i386_operand_type bigdisp
;
9130 /* We do this to make sure that the section symbol is in
9131 the symbol table. We will ultimately change the relocation
9132 to be relative to the beginning of the section. */
9133 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9134 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9135 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9137 if (exp
->X_op
!= O_symbol
)
9140 if (S_IS_LOCAL (exp
->X_add_symbol
)
9141 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9142 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9143 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9144 exp
->X_op
= O_subtract
;
9145 exp
->X_op_symbol
= GOT_symbol
;
9146 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9147 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9148 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9149 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9151 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9154 else if (exp
->X_op
== O_absent
9155 || exp
->X_op
== O_illegal
9156 || exp
->X_op
== O_big
)
9159 as_bad (_("missing or invalid displacement expression `%s'"),
9164 else if (flag_code
== CODE_64BIT
9165 && !i
.prefix
[ADDR_PREFIX
]
9166 && exp
->X_op
== O_constant
)
9168 /* Since displacement is signed extended to 64bit, don't allow
9169 disp32 and turn off disp32s if they are out of range. */
9170 i
.types
[this_operand
].bitfield
.disp32
= 0;
9171 if (!fits_in_signed_long (exp
->X_add_number
))
9173 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9174 if (i
.types
[this_operand
].bitfield
.baseindex
)
9176 as_bad (_("0x%lx out range of signed 32bit displacement"),
9177 (long) exp
->X_add_number
);
9183 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9184 else if (exp
->X_op
!= O_constant
9185 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9186 && exp_seg
!= absolute_section
9187 && exp_seg
!= text_section
9188 && exp_seg
!= data_section
9189 && exp_seg
!= bss_section
9190 && exp_seg
!= undefined_section
9191 && !bfd_is_com_section (exp_seg
))
9193 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9198 /* Check if this is a displacement only operand. */
9199 bigdisp
= i
.types
[this_operand
];
9200 bigdisp
.bitfield
.disp8
= 0;
9201 bigdisp
.bitfield
.disp16
= 0;
9202 bigdisp
.bitfield
.disp32
= 0;
9203 bigdisp
.bitfield
.disp32s
= 0;
9204 bigdisp
.bitfield
.disp64
= 0;
9205 if (operand_type_all_zero (&bigdisp
))
9206 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9212 /* Return the active addressing mode, taking address override and
9213 registers forming the address into consideration. Update the
9214 address override prefix if necessary. */
9216 static enum flag_code
9217 i386_addressing_mode (void)
9219 enum flag_code addr_mode
;
9221 if (i
.prefix
[ADDR_PREFIX
])
9222 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9225 addr_mode
= flag_code
;
9227 #if INFER_ADDR_PREFIX
9228 if (i
.mem_operands
== 0)
9230 /* Infer address prefix from the first memory operand. */
9231 const reg_entry
*addr_reg
= i
.base_reg
;
9233 if (addr_reg
== NULL
)
9234 addr_reg
= i
.index_reg
;
9238 if (addr_reg
->reg_num
== RegEip
9239 || addr_reg
->reg_num
== RegEiz
9240 || addr_reg
->reg_type
.bitfield
.dword
)
9241 addr_mode
= CODE_32BIT
;
9242 else if (flag_code
!= CODE_64BIT
9243 && addr_reg
->reg_type
.bitfield
.word
)
9244 addr_mode
= CODE_16BIT
;
9246 if (addr_mode
!= flag_code
)
9248 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9250 /* Change the size of any displacement too. At most one
9251 of Disp16 or Disp32 is set.
9252 FIXME. There doesn't seem to be any real need for
9253 separate Disp16 and Disp32 flags. The same goes for
9254 Imm16 and Imm32. Removing them would probably clean
9255 up the code quite a lot. */
9256 if (flag_code
!= CODE_64BIT
9257 && (i
.types
[this_operand
].bitfield
.disp16
9258 || i
.types
[this_operand
].bitfield
.disp32
))
9259 i
.types
[this_operand
]
9260 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9270 /* Make sure the memory operand we've been dealt is valid.
9271 Return 1 on success, 0 on a failure. */
9274 i386_index_check (const char *operand_string
)
9276 const char *kind
= "base/index";
9277 enum flag_code addr_mode
= i386_addressing_mode ();
9279 if (current_templates
->start
->opcode_modifier
.isstring
9280 && !current_templates
->start
->opcode_modifier
.immext
9281 && (current_templates
->end
[-1].opcode_modifier
.isstring
9284 /* Memory operands of string insns are special in that they only allow
9285 a single register (rDI, rSI, or rBX) as their memory address. */
9286 const reg_entry
*expected_reg
;
9287 static const char *di_si
[][2] =
9293 static const char *bx
[] = { "ebx", "bx", "rbx" };
9295 kind
= "string address";
9297 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9299 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9301 if (!type
.bitfield
.baseindex
9302 || ((!i
.mem_operands
!= !intel_syntax
)
9303 && current_templates
->end
[-1].operand_types
[1]
9304 .bitfield
.baseindex
))
9305 type
= current_templates
->end
[-1].operand_types
[1];
9306 expected_reg
= hash_find (reg_hash
,
9307 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9311 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9313 if (i
.base_reg
!= expected_reg
9315 || operand_type_check (i
.types
[this_operand
], disp
))
9317 /* The second memory operand must have the same size as
9321 && !((addr_mode
== CODE_64BIT
9322 && i
.base_reg
->reg_type
.bitfield
.qword
)
9323 || (addr_mode
== CODE_32BIT
9324 ? i
.base_reg
->reg_type
.bitfield
.dword
9325 : i
.base_reg
->reg_type
.bitfield
.word
)))
9328 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9330 intel_syntax
? '[' : '(',
9332 expected_reg
->reg_name
,
9333 intel_syntax
? ']' : ')');
9340 as_bad (_("`%s' is not a valid %s expression"),
9341 operand_string
, kind
);
9346 if (addr_mode
!= CODE_16BIT
)
9348 /* 32-bit/64-bit checks. */
9350 && (addr_mode
== CODE_64BIT
9351 ? !i
.base_reg
->reg_type
.bitfield
.qword
9352 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9354 || (i
.base_reg
->reg_num
9355 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9357 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9358 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9359 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9360 && ((addr_mode
== CODE_64BIT
9361 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9362 || i
.index_reg
->reg_num
== RegRiz
)
9363 : !(i
.index_reg
->reg_type
.bitfield
.dword
9364 || i
.index_reg
->reg_num
== RegEiz
))
9365 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9368 /* bndmk, bndldx, and bndstx have special restrictions. */
9369 if (current_templates
->start
->base_opcode
== 0xf30f1b
9370 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9372 /* They cannot use RIP-relative addressing. */
9373 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9375 as_bad (_("`%s' cannot be used here"), operand_string
);
9379 /* bndldx and bndstx ignore their scale factor. */
9380 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9381 && i
.log2_scale_factor
)
9382 as_warn (_("register scaling is being ignored here"));
9387 /* 16-bit checks. */
9389 && (!i
.base_reg
->reg_type
.bitfield
.word
9390 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9392 && (!i
.index_reg
->reg_type
.bitfield
.word
9393 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9395 && i
.base_reg
->reg_num
< 6
9396 && i
.index_reg
->reg_num
>= 6
9397 && i
.log2_scale_factor
== 0))))
9404 /* Handle vector immediates. */
9407 RC_SAE_immediate (const char *imm_start
)
9409 unsigned int match_found
, j
;
9410 const char *pstr
= imm_start
;
9418 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9420 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9424 rc_op
.type
= RC_NamesTable
[j
].type
;
9425 rc_op
.operand
= this_operand
;
9426 i
.rounding
= &rc_op
;
9430 as_bad (_("duplicated `%s'"), imm_start
);
9433 pstr
+= RC_NamesTable
[j
].len
;
9443 as_bad (_("Missing '}': '%s'"), imm_start
);
9446 /* RC/SAE immediate string should contain nothing more. */;
9449 as_bad (_("Junk after '}': '%s'"), imm_start
);
9453 exp
= &im_expressions
[i
.imm_operands
++];
9454 i
.op
[this_operand
].imms
= exp
;
9456 exp
->X_op
= O_constant
;
9457 exp
->X_add_number
= 0;
9458 exp
->X_add_symbol
= (symbolS
*) 0;
9459 exp
->X_op_symbol
= (symbolS
*) 0;
9461 i
.types
[this_operand
].bitfield
.imm8
= 1;
9465 /* Only string instructions can have a second memory operand, so
9466 reduce current_templates to just those if it contains any. */
9468 maybe_adjust_templates (void)
9470 const insn_template
*t
;
9472 gas_assert (i
.mem_operands
== 1);
9474 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9475 if (t
->opcode_modifier
.isstring
)
9478 if (t
< current_templates
->end
)
9480 static templates aux_templates
;
9481 bfd_boolean recheck
;
9483 aux_templates
.start
= t
;
9484 for (; t
< current_templates
->end
; ++t
)
9485 if (!t
->opcode_modifier
.isstring
)
9487 aux_templates
.end
= t
;
9489 /* Determine whether to re-check the first memory operand. */
9490 recheck
= (aux_templates
.start
!= current_templates
->start
9491 || t
!= current_templates
->end
);
9493 current_templates
= &aux_templates
;
9498 if (i
.memop1_string
!= NULL
9499 && i386_index_check (i
.memop1_string
) == 0)
9508 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9512 i386_att_operand (char *operand_string
)
9516 char *op_string
= operand_string
;
9518 if (is_space_char (*op_string
))
9521 /* We check for an absolute prefix (differentiating,
9522 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9523 if (*op_string
== ABSOLUTE_PREFIX
)
9526 if (is_space_char (*op_string
))
9528 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9531 /* Check if operand is a register. */
9532 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9534 i386_operand_type temp
;
9536 /* Check for a segment override by searching for ':' after a
9537 segment register. */
9539 if (is_space_char (*op_string
))
9541 if (*op_string
== ':'
9542 && (r
->reg_type
.bitfield
.sreg2
9543 || r
->reg_type
.bitfield
.sreg3
))
9548 i
.seg
[i
.mem_operands
] = &es
;
9551 i
.seg
[i
.mem_operands
] = &cs
;
9554 i
.seg
[i
.mem_operands
] = &ss
;
9557 i
.seg
[i
.mem_operands
] = &ds
;
9560 i
.seg
[i
.mem_operands
] = &fs
;
9563 i
.seg
[i
.mem_operands
] = &gs
;
9567 /* Skip the ':' and whitespace. */
9569 if (is_space_char (*op_string
))
9572 if (!is_digit_char (*op_string
)
9573 && !is_identifier_char (*op_string
)
9574 && *op_string
!= '('
9575 && *op_string
!= ABSOLUTE_PREFIX
)
9577 as_bad (_("bad memory operand `%s'"), op_string
);
9580 /* Handle case of %es:*foo. */
9581 if (*op_string
== ABSOLUTE_PREFIX
)
9584 if (is_space_char (*op_string
))
9586 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9588 goto do_memory_reference
;
9591 /* Handle vector operations. */
9592 if (*op_string
== '{')
9594 op_string
= check_VecOperations (op_string
, NULL
);
9595 if (op_string
== NULL
)
9601 as_bad (_("junk `%s' after register"), op_string
);
9605 temp
.bitfield
.baseindex
= 0;
9606 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9608 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9609 i
.op
[this_operand
].regs
= r
;
9612 else if (*op_string
== REGISTER_PREFIX
)
9614 as_bad (_("bad register name `%s'"), op_string
);
9617 else if (*op_string
== IMMEDIATE_PREFIX
)
9620 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9622 as_bad (_("immediate operand illegal with absolute jump"));
9625 if (!i386_immediate (op_string
))
9628 else if (RC_SAE_immediate (operand_string
))
9630 /* If it is a RC or SAE immediate, do nothing. */
9633 else if (is_digit_char (*op_string
)
9634 || is_identifier_char (*op_string
)
9635 || *op_string
== '"'
9636 || *op_string
== '(')
9638 /* This is a memory reference of some sort. */
9641 /* Start and end of displacement string expression (if found). */
9642 char *displacement_string_start
;
9643 char *displacement_string_end
;
9646 do_memory_reference
:
9647 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9649 if ((i
.mem_operands
== 1
9650 && !current_templates
->start
->opcode_modifier
.isstring
)
9651 || i
.mem_operands
== 2)
9653 as_bad (_("too many memory references for `%s'"),
9654 current_templates
->start
->name
);
9658 /* Check for base index form. We detect the base index form by
9659 looking for an ')' at the end of the operand, searching
9660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9662 base_string
= op_string
+ strlen (op_string
);
9664 /* Handle vector operations. */
9665 vop_start
= strchr (op_string
, '{');
9666 if (vop_start
&& vop_start
< base_string
)
9668 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9670 base_string
= vop_start
;
9674 if (is_space_char (*base_string
))
9677 /* If we only have a displacement, set-up for it to be parsed later. */
9678 displacement_string_start
= op_string
;
9679 displacement_string_end
= base_string
+ 1;
9681 if (*base_string
== ')')
9684 unsigned int parens_balanced
= 1;
9685 /* We've already checked that the number of left & right ()'s are
9686 equal, so this loop will not be infinite. */
9690 if (*base_string
== ')')
9692 if (*base_string
== '(')
9695 while (parens_balanced
);
9697 temp_string
= base_string
;
9699 /* Skip past '(' and whitespace. */
9701 if (is_space_char (*base_string
))
9704 if (*base_string
== ','
9705 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9708 displacement_string_end
= temp_string
;
9710 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9714 base_string
= end_op
;
9715 if (is_space_char (*base_string
))
9719 /* There may be an index reg or scale factor here. */
9720 if (*base_string
== ',')
9723 if (is_space_char (*base_string
))
9726 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9729 base_string
= end_op
;
9730 if (is_space_char (*base_string
))
9732 if (*base_string
== ',')
9735 if (is_space_char (*base_string
))
9738 else if (*base_string
!= ')')
9740 as_bad (_("expecting `,' or `)' "
9741 "after index register in `%s'"),
9746 else if (*base_string
== REGISTER_PREFIX
)
9748 end_op
= strchr (base_string
, ',');
9751 as_bad (_("bad register name `%s'"), base_string
);
9755 /* Check for scale factor. */
9756 if (*base_string
!= ')')
9758 char *end_scale
= i386_scale (base_string
);
9763 base_string
= end_scale
;
9764 if (is_space_char (*base_string
))
9766 if (*base_string
!= ')')
9768 as_bad (_("expecting `)' "
9769 "after scale factor in `%s'"),
9774 else if (!i
.index_reg
)
9776 as_bad (_("expecting index register or scale factor "
9777 "after `,'; got '%c'"),
9782 else if (*base_string
!= ')')
9784 as_bad (_("expecting `,' or `)' "
9785 "after base register in `%s'"),
9790 else if (*base_string
== REGISTER_PREFIX
)
9792 end_op
= strchr (base_string
, ',');
9795 as_bad (_("bad register name `%s'"), base_string
);
9800 /* If there's an expression beginning the operand, parse it,
9801 assuming displacement_string_start and
9802 displacement_string_end are meaningful. */
9803 if (displacement_string_start
!= displacement_string_end
)
9805 if (!i386_displacement (displacement_string_start
,
9806 displacement_string_end
))
9810 /* Special case for (%dx) while doing input/output op. */
9812 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9814 && i
.log2_scale_factor
== 0
9815 && i
.seg
[i
.mem_operands
] == 0
9816 && !operand_type_check (i
.types
[this_operand
], disp
))
9818 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9822 if (i386_index_check (operand_string
) == 0)
9824 i
.flags
[this_operand
] |= Operand_Mem
;
9825 if (i
.mem_operands
== 0)
9826 i
.memop1_string
= xstrdup (operand_string
);
9831 /* It's not a memory operand; argh! */
9832 as_bad (_("invalid char %s beginning operand %d `%s'"),
9833 output_invalid (*op_string
),
9838 return 1; /* Normal return. */
9841 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9842 that an rs_machine_dependent frag may reach. */
9845 i386_frag_max_var (fragS
*frag
)
9847 /* The only relaxable frags are for jumps.
9848 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9849 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9850 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9855 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9857 /* STT_GNU_IFUNC symbol must go through PLT. */
9858 if ((symbol_get_bfdsym (fr_symbol
)->flags
9859 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9862 if (!S_IS_EXTERNAL (fr_symbol
))
9863 /* Symbol may be weak or local. */
9864 return !S_IS_WEAK (fr_symbol
);
9866 /* Global symbols with non-default visibility can't be preempted. */
9867 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9870 if (fr_var
!= NO_RELOC
)
9871 switch ((enum bfd_reloc_code_real
) fr_var
)
9873 case BFD_RELOC_386_PLT32
:
9874 case BFD_RELOC_X86_64_PLT32
:
9875 /* Symbol with PLT relocation may be preempted. */
9881 /* Global symbols with default visibility in a shared library may be
9882 preempted by another definition. */
9887 /* md_estimate_size_before_relax()
9889 Called just before relax() for rs_machine_dependent frags. The x86
9890 assembler uses these frags to handle variable size jump
9893 Any symbol that is now undefined will not become defined.
9894 Return the correct fr_subtype in the frag.
9895 Return the initial "guess for variable size of frag" to caller.
9896 The guess is actually the growth beyond the fixed part. Whatever
9897 we do to grow the fixed or variable part contributes to our
9901 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9903 /* We've already got fragP->fr_subtype right; all we have to do is
9904 check for un-relaxable symbols. On an ELF system, we can't relax
9905 an externally visible symbol, because it may be overridden by a
9907 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9910 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9913 #if defined (OBJ_COFF) && defined (TE_PE)
9914 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9915 && S_IS_WEAK (fragP
->fr_symbol
))
9919 /* Symbol is undefined in this segment, or we need to keep a
9920 reloc so that weak symbols can be overridden. */
9921 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9922 enum bfd_reloc_code_real reloc_type
;
9923 unsigned char *opcode
;
9926 if (fragP
->fr_var
!= NO_RELOC
)
9927 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9929 reloc_type
= BFD_RELOC_16_PCREL
;
9930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9931 else if (need_plt32_p (fragP
->fr_symbol
))
9932 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9935 reloc_type
= BFD_RELOC_32_PCREL
;
9937 old_fr_fix
= fragP
->fr_fix
;
9938 opcode
= (unsigned char *) fragP
->fr_opcode
;
9940 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9943 /* Make jmp (0xeb) a (d)word displacement jump. */
9945 fragP
->fr_fix
+= size
;
9946 fix_new (fragP
, old_fr_fix
, size
,
9948 fragP
->fr_offset
, 1,
9954 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9956 /* Negate the condition, and branch past an
9957 unconditional jump. */
9960 /* Insert an unconditional jump. */
9962 /* We added two extra opcode bytes, and have a two byte
9964 fragP
->fr_fix
+= 2 + 2;
9965 fix_new (fragP
, old_fr_fix
+ 2, 2,
9967 fragP
->fr_offset
, 1,
9974 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9979 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9981 fragP
->fr_offset
, 1,
9983 fixP
->fx_signed
= 1;
9987 /* This changes the byte-displacement jump 0x7N
9988 to the (d)word-displacement jump 0x0f,0x8N. */
9989 opcode
[1] = opcode
[0] + 0x10;
9990 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9991 /* We've added an opcode byte. */
9992 fragP
->fr_fix
+= 1 + size
;
9993 fix_new (fragP
, old_fr_fix
+ 1, size
,
9995 fragP
->fr_offset
, 1,
10000 BAD_CASE (fragP
->fr_subtype
);
10004 return fragP
->fr_fix
- old_fr_fix
;
10007 /* Guess size depending on current relax state. Initially the relax
10008 state will correspond to a short jump and we return 1, because
10009 the variable part of the frag (the branch offset) is one byte
10010 long. However, we can relax a section more than once and in that
10011 case we must either set fr_subtype back to the unrelaxed state,
10012 or return the value for the appropriate branch. */
10013 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10016 /* Called after relax() is finished.
10018 In: Address of frag.
10019 fr_type == rs_machine_dependent.
10020 fr_subtype is what the address relaxed to.
10022 Out: Any fixSs and constants are set up.
10023 Caller will turn frag into a ".space 0". */
10026 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10029 unsigned char *opcode
;
10030 unsigned char *where_to_put_displacement
= NULL
;
10031 offsetT target_address
;
10032 offsetT opcode_address
;
10033 unsigned int extension
= 0;
10034 offsetT displacement_from_opcode_start
;
10036 opcode
= (unsigned char *) fragP
->fr_opcode
;
10038 /* Address we want to reach in file space. */
10039 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10041 /* Address opcode resides at in file space. */
10042 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10044 /* Displacement from opcode start to fill into instruction. */
10045 displacement_from_opcode_start
= target_address
- opcode_address
;
10047 if ((fragP
->fr_subtype
& BIG
) == 0)
10049 /* Don't have to change opcode. */
10050 extension
= 1; /* 1 opcode + 1 displacement */
10051 where_to_put_displacement
= &opcode
[1];
10055 if (no_cond_jump_promotion
10056 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10057 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10058 _("long jump required"));
10060 switch (fragP
->fr_subtype
)
10062 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10063 extension
= 4; /* 1 opcode + 4 displacement */
10065 where_to_put_displacement
= &opcode
[1];
10068 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10069 extension
= 2; /* 1 opcode + 2 displacement */
10071 where_to_put_displacement
= &opcode
[1];
10074 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10075 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10076 extension
= 5; /* 2 opcode + 4 displacement */
10077 opcode
[1] = opcode
[0] + 0x10;
10078 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10079 where_to_put_displacement
= &opcode
[2];
10082 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10083 extension
= 3; /* 2 opcode + 2 displacement */
10084 opcode
[1] = opcode
[0] + 0x10;
10085 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10086 where_to_put_displacement
= &opcode
[2];
10089 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10094 where_to_put_displacement
= &opcode
[3];
10098 BAD_CASE (fragP
->fr_subtype
);
10103 /* If size if less then four we are sure that the operand fits,
10104 but if it's 4, then it could be that the displacement is larger
10106 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10108 && ((addressT
) (displacement_from_opcode_start
- extension
10109 + ((addressT
) 1 << 31))
10110 > (((addressT
) 2 << 31) - 1)))
10112 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10113 _("jump target out of range"));
10114 /* Make us emit 0. */
10115 displacement_from_opcode_start
= extension
;
10117 /* Now put displacement after opcode. */
10118 md_number_to_chars ((char *) where_to_put_displacement
,
10119 (valueT
) (displacement_from_opcode_start
- extension
),
10120 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10121 fragP
->fr_fix
+= extension
;
10124 /* Apply a fixup (fixP) to segment data, once it has been determined
10125 by our caller that we have all the info we need to fix it up.
10127 Parameter valP is the pointer to the value of the bits.
10129 On the 386, immediates, displacements, and data pointers are all in
10130 the same (little-endian) format, so we don't need to care about which
10131 we are handling. */
10134 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10136 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10137 valueT value
= *valP
;
10139 #if !defined (TE_Mach)
10140 if (fixP
->fx_pcrel
)
10142 switch (fixP
->fx_r_type
)
10148 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10151 case BFD_RELOC_X86_64_32S
:
10152 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10155 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10158 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10163 if (fixP
->fx_addsy
!= NULL
10164 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10165 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10166 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10167 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10168 && !use_rela_relocations
)
10170 /* This is a hack. There should be a better way to handle this.
10171 This covers for the fact that bfd_install_relocation will
10172 subtract the current location (for partial_inplace, PC relative
10173 relocations); see more below. */
10177 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10180 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10185 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10187 if ((sym_seg
== seg
10188 || (symbol_section_p (fixP
->fx_addsy
)
10189 && sym_seg
!= absolute_section
))
10190 && !generic_force_reloc (fixP
))
10192 /* Yes, we add the values in twice. This is because
10193 bfd_install_relocation subtracts them out again. I think
10194 bfd_install_relocation is broken, but I don't dare change
10196 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10200 #if defined (OBJ_COFF) && defined (TE_PE)
10201 /* For some reason, the PE format does not store a
10202 section address offset for a PC relative symbol. */
10203 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10204 || S_IS_WEAK (fixP
->fx_addsy
))
10205 value
+= md_pcrel_from (fixP
);
10208 #if defined (OBJ_COFF) && defined (TE_PE)
10209 if (fixP
->fx_addsy
!= NULL
10210 && S_IS_WEAK (fixP
->fx_addsy
)
10211 /* PR 16858: Do not modify weak function references. */
10212 && ! fixP
->fx_pcrel
)
10214 #if !defined (TE_PEP)
10215 /* For x86 PE weak function symbols are neither PC-relative
10216 nor do they set S_IS_FUNCTION. So the only reliable way
10217 to detect them is to check the flags of their containing
10219 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10220 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10224 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10228 /* Fix a few things - the dynamic linker expects certain values here,
10229 and we must not disappoint it. */
10230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10231 if (IS_ELF
&& fixP
->fx_addsy
)
10232 switch (fixP
->fx_r_type
)
10234 case BFD_RELOC_386_PLT32
:
10235 case BFD_RELOC_X86_64_PLT32
:
10236 /* Make the jump instruction point to the address of the operand. At
10237 runtime we merely add the offset to the actual PLT entry. */
10241 case BFD_RELOC_386_TLS_GD
:
10242 case BFD_RELOC_386_TLS_LDM
:
10243 case BFD_RELOC_386_TLS_IE_32
:
10244 case BFD_RELOC_386_TLS_IE
:
10245 case BFD_RELOC_386_TLS_GOTIE
:
10246 case BFD_RELOC_386_TLS_GOTDESC
:
10247 case BFD_RELOC_X86_64_TLSGD
:
10248 case BFD_RELOC_X86_64_TLSLD
:
10249 case BFD_RELOC_X86_64_GOTTPOFF
:
10250 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10251 value
= 0; /* Fully resolved at runtime. No addend. */
10253 case BFD_RELOC_386_TLS_LE
:
10254 case BFD_RELOC_386_TLS_LDO_32
:
10255 case BFD_RELOC_386_TLS_LE_32
:
10256 case BFD_RELOC_X86_64_DTPOFF32
:
10257 case BFD_RELOC_X86_64_DTPOFF64
:
10258 case BFD_RELOC_X86_64_TPOFF32
:
10259 case BFD_RELOC_X86_64_TPOFF64
:
10260 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10263 case BFD_RELOC_386_TLS_DESC_CALL
:
10264 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10265 value
= 0; /* Fully resolved at runtime. No addend. */
10266 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10270 case BFD_RELOC_VTABLE_INHERIT
:
10271 case BFD_RELOC_VTABLE_ENTRY
:
10278 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10280 #endif /* !defined (TE_Mach) */
10282 /* Are we finished with this relocation now? */
10283 if (fixP
->fx_addsy
== NULL
)
10285 #if defined (OBJ_COFF) && defined (TE_PE)
10286 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10289 /* Remember value for tc_gen_reloc. */
10290 fixP
->fx_addnumber
= value
;
10291 /* Clear out the frag for now. */
10295 else if (use_rela_relocations
)
10297 fixP
->fx_no_overflow
= 1;
10298 /* Remember value for tc_gen_reloc. */
10299 fixP
->fx_addnumber
= value
;
10303 md_number_to_chars (p
, value
, fixP
->fx_size
);
10307 md_atof (int type
, char *litP
, int *sizeP
)
10309 /* This outputs the LITTLENUMs in REVERSE order;
10310 in accord with the bigendian 386. */
10311 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10314 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10317 output_invalid (int c
)
10320 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10323 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10324 "(0x%x)", (unsigned char) c
);
10325 return output_invalid_buf
;
10328 /* REG_STRING starts *before* REGISTER_PREFIX. */
10330 static const reg_entry
*
10331 parse_real_register (char *reg_string
, char **end_op
)
10333 char *s
= reg_string
;
10335 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10336 const reg_entry
*r
;
10338 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10339 if (*s
== REGISTER_PREFIX
)
10342 if (is_space_char (*s
))
10345 p
= reg_name_given
;
10346 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10348 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10349 return (const reg_entry
*) NULL
;
10353 /* For naked regs, make sure that we are not dealing with an identifier.
10354 This prevents confusing an identifier like `eax_var' with register
10356 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10357 return (const reg_entry
*) NULL
;
10361 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10363 /* Handle floating point regs, allowing spaces in the (i) part. */
10364 if (r
== i386_regtab
/* %st is first entry of table */)
10366 if (!cpu_arch_flags
.bitfield
.cpu8087
10367 && !cpu_arch_flags
.bitfield
.cpu287
10368 && !cpu_arch_flags
.bitfield
.cpu387
)
10369 return (const reg_entry
*) NULL
;
10371 if (is_space_char (*s
))
10376 if (is_space_char (*s
))
10378 if (*s
>= '0' && *s
<= '7')
10380 int fpr
= *s
- '0';
10382 if (is_space_char (*s
))
10387 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10392 /* We have "%st(" then garbage. */
10393 return (const reg_entry
*) NULL
;
10397 if (r
== NULL
|| allow_pseudo_reg
)
10400 if (operand_type_all_zero (&r
->reg_type
))
10401 return (const reg_entry
*) NULL
;
10403 if ((r
->reg_type
.bitfield
.dword
10404 || r
->reg_type
.bitfield
.sreg3
10405 || r
->reg_type
.bitfield
.control
10406 || r
->reg_type
.bitfield
.debug
10407 || r
->reg_type
.bitfield
.test
)
10408 && !cpu_arch_flags
.bitfield
.cpui386
)
10409 return (const reg_entry
*) NULL
;
10411 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10412 return (const reg_entry
*) NULL
;
10414 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10416 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10417 return (const reg_entry
*) NULL
;
10419 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10421 if (r
->reg_type
.bitfield
.ymmword
)
10422 return (const reg_entry
*) NULL
;
10424 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10425 return (const reg_entry
*) NULL
;
10429 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10430 return (const reg_entry
*) NULL
;
10432 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10433 if (!allow_index_reg
10434 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10435 return (const reg_entry
*) NULL
;
10437 /* Upper 16 vector registers are only available with VREX in 64bit
10438 mode, and require EVEX encoding. */
10439 if (r
->reg_flags
& RegVRex
)
10441 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10442 || flag_code
!= CODE_64BIT
)
10443 return (const reg_entry
*) NULL
;
10445 i
.vec_encoding
= vex_encoding_evex
;
10448 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10449 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10450 && flag_code
!= CODE_64BIT
)
10451 return (const reg_entry
*) NULL
;
10453 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10454 return (const reg_entry
*) NULL
;
10459 /* REG_STRING starts *before* REGISTER_PREFIX. */
10461 static const reg_entry
*
10462 parse_register (char *reg_string
, char **end_op
)
10464 const reg_entry
*r
;
10466 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10467 r
= parse_real_register (reg_string
, end_op
);
10472 char *save
= input_line_pointer
;
10476 input_line_pointer
= reg_string
;
10477 c
= get_symbol_name (®_string
);
10478 symbolP
= symbol_find (reg_string
);
10479 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10481 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10483 know (e
->X_op
== O_register
);
10484 know (e
->X_add_number
>= 0
10485 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10486 r
= i386_regtab
+ e
->X_add_number
;
10487 if ((r
->reg_flags
& RegVRex
))
10488 i
.vec_encoding
= vex_encoding_evex
;
10489 *end_op
= input_line_pointer
;
10491 *input_line_pointer
= c
;
10492 input_line_pointer
= save
;
10498 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10500 const reg_entry
*r
;
10501 char *end
= input_line_pointer
;
10504 r
= parse_register (name
, &input_line_pointer
);
10505 if (r
&& end
<= input_line_pointer
)
10507 *nextcharP
= *input_line_pointer
;
10508 *input_line_pointer
= 0;
10509 e
->X_op
= O_register
;
10510 e
->X_add_number
= r
- i386_regtab
;
10513 input_line_pointer
= end
;
10515 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10519 md_operand (expressionS
*e
)
10522 const reg_entry
*r
;
10524 switch (*input_line_pointer
)
10526 case REGISTER_PREFIX
:
10527 r
= parse_real_register (input_line_pointer
, &end
);
10530 e
->X_op
= O_register
;
10531 e
->X_add_number
= r
- i386_regtab
;
10532 input_line_pointer
= end
;
10537 gas_assert (intel_syntax
);
10538 end
= input_line_pointer
++;
10540 if (*input_line_pointer
== ']')
10542 ++input_line_pointer
;
10543 e
->X_op_symbol
= make_expr_symbol (e
);
10544 e
->X_add_symbol
= NULL
;
10545 e
->X_add_number
= 0;
10550 e
->X_op
= O_absent
;
10551 input_line_pointer
= end
;
10558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10559 const char *md_shortopts
= "kVQ:sqnO::";
10561 const char *md_shortopts
= "qnO::";
10564 #define OPTION_32 (OPTION_MD_BASE + 0)
10565 #define OPTION_64 (OPTION_MD_BASE + 1)
10566 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10567 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10568 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10569 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10570 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10571 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10572 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10573 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10574 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10575 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10576 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10577 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10578 #define OPTION_X32 (OPTION_MD_BASE + 14)
10579 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10580 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10581 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10582 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10583 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10584 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10585 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10586 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10587 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10588 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10590 struct option md_longopts
[] =
10592 {"32", no_argument
, NULL
, OPTION_32
},
10593 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10594 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10595 {"64", no_argument
, NULL
, OPTION_64
},
10597 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10598 {"x32", no_argument
, NULL
, OPTION_X32
},
10599 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10601 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10602 {"march", required_argument
, NULL
, OPTION_MARCH
},
10603 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10604 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10605 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10606 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10607 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10608 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10609 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10610 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10611 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10612 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10613 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10614 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10615 # if defined (TE_PE) || defined (TE_PEP)
10616 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10618 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10619 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10620 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10621 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10622 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10623 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10624 {NULL
, no_argument
, NULL
, 0}
10626 size_t md_longopts_size
= sizeof (md_longopts
);
10629 md_parse_option (int c
, const char *arg
)
10632 char *arch
, *next
, *saved
;
10637 optimize_align_code
= 0;
10641 quiet_warnings
= 1;
10644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10645 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10646 should be emitted or not. FIXME: Not implemented. */
10650 /* -V: SVR4 argument to print version ID. */
10652 print_version_id ();
10655 /* -k: Ignore for FreeBSD compatibility. */
10660 /* -s: On i386 Solaris, this tells the native assembler to use
10661 .stab instead of .stab.excl. We always use .stab anyhow. */
10664 case OPTION_MSHARED
:
10668 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10669 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10672 const char **list
, **l
;
10674 list
= bfd_target_list ();
10675 for (l
= list
; *l
!= NULL
; l
++)
10676 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10677 || strcmp (*l
, "coff-x86-64") == 0
10678 || strcmp (*l
, "pe-x86-64") == 0
10679 || strcmp (*l
, "pei-x86-64") == 0
10680 || strcmp (*l
, "mach-o-x86-64") == 0)
10682 default_arch
= "x86_64";
10686 as_fatal (_("no compiled in support for x86_64"));
10692 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10696 const char **list
, **l
;
10698 list
= bfd_target_list ();
10699 for (l
= list
; *l
!= NULL
; l
++)
10700 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10702 default_arch
= "x86_64:32";
10706 as_fatal (_("no compiled in support for 32bit x86_64"));
10710 as_fatal (_("32bit x86_64 is only supported for ELF"));
10715 default_arch
= "i386";
10718 case OPTION_DIVIDE
:
10719 #ifdef SVR4_COMMENT_CHARS
10724 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10726 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10730 i386_comment_chars
= n
;
10736 saved
= xstrdup (arg
);
10738 /* Allow -march=+nosse. */
10744 as_fatal (_("invalid -march= option: `%s'"), arg
);
10745 next
= strchr (arch
, '+');
10748 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10750 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10753 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10756 cpu_arch_name
= cpu_arch
[j
].name
;
10757 cpu_sub_arch_name
= NULL
;
10758 cpu_arch_flags
= cpu_arch
[j
].flags
;
10759 cpu_arch_isa
= cpu_arch
[j
].type
;
10760 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10761 if (!cpu_arch_tune_set
)
10763 cpu_arch_tune
= cpu_arch_isa
;
10764 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10768 else if (*cpu_arch
[j
].name
== '.'
10769 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10771 /* ISA extension. */
10772 i386_cpu_flags flags
;
10774 flags
= cpu_flags_or (cpu_arch_flags
,
10775 cpu_arch
[j
].flags
);
10777 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10779 if (cpu_sub_arch_name
)
10781 char *name
= cpu_sub_arch_name
;
10782 cpu_sub_arch_name
= concat (name
,
10784 (const char *) NULL
);
10788 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10789 cpu_arch_flags
= flags
;
10790 cpu_arch_isa_flags
= flags
;
10794 = cpu_flags_or (cpu_arch_isa_flags
,
10795 cpu_arch
[j
].flags
);
10800 if (j
>= ARRAY_SIZE (cpu_arch
))
10802 /* Disable an ISA extension. */
10803 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10804 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10806 i386_cpu_flags flags
;
10808 flags
= cpu_flags_and_not (cpu_arch_flags
,
10809 cpu_noarch
[j
].flags
);
10810 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10812 if (cpu_sub_arch_name
)
10814 char *name
= cpu_sub_arch_name
;
10815 cpu_sub_arch_name
= concat (arch
,
10816 (const char *) NULL
);
10820 cpu_sub_arch_name
= xstrdup (arch
);
10821 cpu_arch_flags
= flags
;
10822 cpu_arch_isa_flags
= flags
;
10827 if (j
>= ARRAY_SIZE (cpu_noarch
))
10828 j
= ARRAY_SIZE (cpu_arch
);
10831 if (j
>= ARRAY_SIZE (cpu_arch
))
10832 as_fatal (_("invalid -march= option: `%s'"), arg
);
10836 while (next
!= NULL
);
10842 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10843 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10845 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10847 cpu_arch_tune_set
= 1;
10848 cpu_arch_tune
= cpu_arch
[j
].type
;
10849 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10853 if (j
>= ARRAY_SIZE (cpu_arch
))
10854 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10857 case OPTION_MMNEMONIC
:
10858 if (strcasecmp (arg
, "att") == 0)
10859 intel_mnemonic
= 0;
10860 else if (strcasecmp (arg
, "intel") == 0)
10861 intel_mnemonic
= 1;
10863 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10866 case OPTION_MSYNTAX
:
10867 if (strcasecmp (arg
, "att") == 0)
10869 else if (strcasecmp (arg
, "intel") == 0)
10872 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10875 case OPTION_MINDEX_REG
:
10876 allow_index_reg
= 1;
10879 case OPTION_MNAKED_REG
:
10880 allow_naked_reg
= 1;
10883 case OPTION_MSSE2AVX
:
10887 case OPTION_MSSE_CHECK
:
10888 if (strcasecmp (arg
, "error") == 0)
10889 sse_check
= check_error
;
10890 else if (strcasecmp (arg
, "warning") == 0)
10891 sse_check
= check_warning
;
10892 else if (strcasecmp (arg
, "none") == 0)
10893 sse_check
= check_none
;
10895 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10898 case OPTION_MOPERAND_CHECK
:
10899 if (strcasecmp (arg
, "error") == 0)
10900 operand_check
= check_error
;
10901 else if (strcasecmp (arg
, "warning") == 0)
10902 operand_check
= check_warning
;
10903 else if (strcasecmp (arg
, "none") == 0)
10904 operand_check
= check_none
;
10906 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10909 case OPTION_MAVXSCALAR
:
10910 if (strcasecmp (arg
, "128") == 0)
10911 avxscalar
= vex128
;
10912 else if (strcasecmp (arg
, "256") == 0)
10913 avxscalar
= vex256
;
10915 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10918 case OPTION_MADD_BND_PREFIX
:
10919 add_bnd_prefix
= 1;
10922 case OPTION_MEVEXLIG
:
10923 if (strcmp (arg
, "128") == 0)
10924 evexlig
= evexl128
;
10925 else if (strcmp (arg
, "256") == 0)
10926 evexlig
= evexl256
;
10927 else if (strcmp (arg
, "512") == 0)
10928 evexlig
= evexl512
;
10930 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10933 case OPTION_MEVEXRCIG
:
10934 if (strcmp (arg
, "rne") == 0)
10936 else if (strcmp (arg
, "rd") == 0)
10938 else if (strcmp (arg
, "ru") == 0)
10940 else if (strcmp (arg
, "rz") == 0)
10943 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10946 case OPTION_MEVEXWIG
:
10947 if (strcmp (arg
, "0") == 0)
10949 else if (strcmp (arg
, "1") == 0)
10952 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10955 # if defined (TE_PE) || defined (TE_PEP)
10956 case OPTION_MBIG_OBJ
:
10961 case OPTION_MOMIT_LOCK_PREFIX
:
10962 if (strcasecmp (arg
, "yes") == 0)
10963 omit_lock_prefix
= 1;
10964 else if (strcasecmp (arg
, "no") == 0)
10965 omit_lock_prefix
= 0;
10967 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10970 case OPTION_MFENCE_AS_LOCK_ADD
:
10971 if (strcasecmp (arg
, "yes") == 0)
10973 else if (strcasecmp (arg
, "no") == 0)
10976 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10979 case OPTION_MRELAX_RELOCATIONS
:
10980 if (strcasecmp (arg
, "yes") == 0)
10981 generate_relax_relocations
= 1;
10982 else if (strcasecmp (arg
, "no") == 0)
10983 generate_relax_relocations
= 0;
10985 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10988 case OPTION_MAMD64
:
10992 case OPTION_MINTEL64
:
11000 /* Turn off -Os. */
11001 optimize_for_space
= 0;
11003 else if (*arg
== 's')
11005 optimize_for_space
= 1;
11006 /* Turn on all encoding optimizations. */
11011 optimize
= atoi (arg
);
11012 /* Turn off -Os. */
11013 optimize_for_space
= 0;
11023 #define MESSAGE_TEMPLATE \
11027 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11028 int *left_p
, const char *name
, int len
)
11030 int size
= sizeof (MESSAGE_TEMPLATE
);
11031 int left
= *left_p
;
11033 /* Reserve 2 spaces for ", " or ",\0" */
11036 /* Check if there is any room. */
11044 p
= mempcpy (p
, name
, len
);
11048 /* Output the current message now and start a new one. */
11051 fprintf (stream
, "%s\n", message
);
11053 left
= size
- (start
- message
) - len
- 2;
11055 gas_assert (left
>= 0);
11057 p
= mempcpy (p
, name
, len
);
11065 show_arch (FILE *stream
, int ext
, int check
)
11067 static char message
[] = MESSAGE_TEMPLATE
;
11068 char *start
= message
+ 27;
11070 int size
= sizeof (MESSAGE_TEMPLATE
);
11077 left
= size
- (start
- message
);
11078 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11080 /* Should it be skipped? */
11081 if (cpu_arch
[j
].skip
)
11084 name
= cpu_arch
[j
].name
;
11085 len
= cpu_arch
[j
].len
;
11088 /* It is an extension. Skip if we aren't asked to show it. */
11099 /* It is an processor. Skip if we show only extension. */
11102 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11104 /* It is an impossible processor - skip. */
11108 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11111 /* Display disabled extensions. */
11113 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11115 name
= cpu_noarch
[j
].name
;
11116 len
= cpu_noarch
[j
].len
;
11117 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11122 fprintf (stream
, "%s\n", message
);
11126 md_show_usage (FILE *stream
)
11128 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11129 fprintf (stream
, _("\
11131 -V print assembler version number\n\
11134 fprintf (stream
, _("\
11135 -n Do not optimize code alignment\n\
11136 -q quieten some warnings\n"));
11137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11138 fprintf (stream
, _("\
11141 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11142 || defined (TE_PE) || defined (TE_PEP))
11143 fprintf (stream
, _("\
11144 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11146 #ifdef SVR4_COMMENT_CHARS
11147 fprintf (stream
, _("\
11148 --divide do not treat `/' as a comment character\n"));
11150 fprintf (stream
, _("\
11151 --divide ignored\n"));
11153 fprintf (stream
, _("\
11154 -march=CPU[,+EXTENSION...]\n\
11155 generate code for CPU and EXTENSION, CPU is one of:\n"));
11156 show_arch (stream
, 0, 1);
11157 fprintf (stream
, _("\
11158 EXTENSION is combination of:\n"));
11159 show_arch (stream
, 1, 0);
11160 fprintf (stream
, _("\
11161 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11162 show_arch (stream
, 0, 0);
11163 fprintf (stream
, _("\
11164 -msse2avx encode SSE instructions with VEX prefix\n"));
11165 fprintf (stream
, _("\
11166 -msse-check=[none|error|warning]\n\
11167 check SSE instructions\n"));
11168 fprintf (stream
, _("\
11169 -moperand-check=[none|error|warning]\n\
11170 check operand combinations for validity\n"));
11171 fprintf (stream
, _("\
11172 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11174 fprintf (stream
, _("\
11175 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11177 fprintf (stream
, _("\
11178 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11179 for EVEX.W bit ignored instructions\n"));
11180 fprintf (stream
, _("\
11181 -mevexrcig=[rne|rd|ru|rz]\n\
11182 encode EVEX instructions with specific EVEX.RC value\n\
11183 for SAE-only ignored instructions\n"));
11184 fprintf (stream
, _("\
11185 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11186 fprintf (stream
, _("\
11187 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11188 fprintf (stream
, _("\
11189 -mindex-reg support pseudo index registers\n"));
11190 fprintf (stream
, _("\
11191 -mnaked-reg don't require `%%' prefix for registers\n"));
11192 fprintf (stream
, _("\
11193 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11194 fprintf (stream
, _("\
11195 -mshared disable branch optimization for shared code\n"));
11196 # if defined (TE_PE) || defined (TE_PEP)
11197 fprintf (stream
, _("\
11198 -mbig-obj generate big object files\n"));
11200 fprintf (stream
, _("\
11201 -momit-lock-prefix=[no|yes]\n\
11202 strip all lock prefixes\n"));
11203 fprintf (stream
, _("\
11204 -mfence-as-lock-add=[no|yes]\n\
11205 encode lfence, mfence and sfence as\n\
11206 lock addl $0x0, (%%{re}sp)\n"));
11207 fprintf (stream
, _("\
11208 -mrelax-relocations=[no|yes]\n\
11209 generate relax relocations\n"));
11210 fprintf (stream
, _("\
11211 -mamd64 accept only AMD64 ISA\n"));
11212 fprintf (stream
, _("\
11213 -mintel64 accept only Intel64 ISA\n"));
11216 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11217 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11218 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11220 /* Pick the target format to use. */
11223 i386_target_format (void)
11225 if (!strncmp (default_arch
, "x86_64", 6))
11227 update_code_flag (CODE_64BIT
, 1);
11228 if (default_arch
[6] == '\0')
11229 x86_elf_abi
= X86_64_ABI
;
11231 x86_elf_abi
= X86_64_X32_ABI
;
11233 else if (!strcmp (default_arch
, "i386"))
11234 update_code_flag (CODE_32BIT
, 1);
11235 else if (!strcmp (default_arch
, "iamcu"))
11237 update_code_flag (CODE_32BIT
, 1);
11238 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11240 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11241 cpu_arch_name
= "iamcu";
11242 cpu_sub_arch_name
= NULL
;
11243 cpu_arch_flags
= iamcu_flags
;
11244 cpu_arch_isa
= PROCESSOR_IAMCU
;
11245 cpu_arch_isa_flags
= iamcu_flags
;
11246 if (!cpu_arch_tune_set
)
11248 cpu_arch_tune
= cpu_arch_isa
;
11249 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11252 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11253 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11257 as_fatal (_("unknown architecture"));
11259 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11260 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11261 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11262 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11264 switch (OUTPUT_FLAVOR
)
11266 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11267 case bfd_target_aout_flavour
:
11268 return AOUT_TARGET_FORMAT
;
11270 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11271 # if defined (TE_PE) || defined (TE_PEP)
11272 case bfd_target_coff_flavour
:
11273 if (flag_code
== CODE_64BIT
)
11274 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11277 # elif defined (TE_GO32)
11278 case bfd_target_coff_flavour
:
11279 return "coff-go32";
11281 case bfd_target_coff_flavour
:
11282 return "coff-i386";
11285 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11286 case bfd_target_elf_flavour
:
11288 const char *format
;
11290 switch (x86_elf_abi
)
11293 format
= ELF_TARGET_FORMAT
;
11296 use_rela_relocations
= 1;
11298 format
= ELF_TARGET_FORMAT64
;
11300 case X86_64_X32_ABI
:
11301 use_rela_relocations
= 1;
11303 disallow_64bit_reloc
= 1;
11304 format
= ELF_TARGET_FORMAT32
;
11307 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11309 if (x86_elf_abi
!= X86_64_ABI
)
11310 as_fatal (_("Intel L1OM is 64bit only"));
11311 return ELF_TARGET_L1OM_FORMAT
;
11313 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11315 if (x86_elf_abi
!= X86_64_ABI
)
11316 as_fatal (_("Intel K1OM is 64bit only"));
11317 return ELF_TARGET_K1OM_FORMAT
;
11319 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11321 if (x86_elf_abi
!= I386_ABI
)
11322 as_fatal (_("Intel MCU is 32bit only"));
11323 return ELF_TARGET_IAMCU_FORMAT
;
11329 #if defined (OBJ_MACH_O)
11330 case bfd_target_mach_o_flavour
:
11331 if (flag_code
== CODE_64BIT
)
11333 use_rela_relocations
= 1;
11335 return "mach-o-x86-64";
11338 return "mach-o-i386";
11346 #endif /* OBJ_MAYBE_ more than one */
11349 md_undefined_symbol (char *name
)
11351 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11352 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11353 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11354 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11358 if (symbol_find (name
))
11359 as_bad (_("GOT already in symbol table"));
11360 GOT_symbol
= symbol_new (name
, undefined_section
,
11361 (valueT
) 0, &zero_address_frag
);
11368 /* Round up a section size to the appropriate boundary. */
11371 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11373 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11374 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11376 /* For a.out, force the section size to be aligned. If we don't do
11377 this, BFD will align it for us, but it will not write out the
11378 final bytes of the section. This may be a bug in BFD, but it is
11379 easier to fix it here since that is how the other a.out targets
11383 align
= bfd_get_section_alignment (stdoutput
, segment
);
11384 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11391 /* On the i386, PC-relative offsets are relative to the start of the
11392 next instruction. That is, the address of the offset, plus its
11393 size, since the offset is always the last part of the insn. */
11396 md_pcrel_from (fixS
*fixP
)
11398 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11404 s_bss (int ignore ATTRIBUTE_UNUSED
)
11408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11410 obj_elf_section_change_hook ();
11412 temp
= get_absolute_expression ();
11413 subseg_set (bss_section
, (subsegT
) temp
);
11414 demand_empty_rest_of_line ();
11420 i386_validate_fix (fixS
*fixp
)
11422 if (fixp
->fx_subsy
)
11424 if (fixp
->fx_subsy
== GOT_symbol
)
11426 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11431 if (fixp
->fx_tcbit2
)
11432 fixp
->fx_r_type
= (fixp
->fx_tcbit
11433 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11434 : BFD_RELOC_X86_64_GOTPCRELX
);
11437 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11442 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11444 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11446 fixp
->fx_subsy
= 0;
11449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11450 else if (!object_64bit
)
11452 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11453 && fixp
->fx_tcbit2
)
11454 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11460 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11463 bfd_reloc_code_real_type code
;
11465 switch (fixp
->fx_r_type
)
11467 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11468 case BFD_RELOC_SIZE32
:
11469 case BFD_RELOC_SIZE64
:
11470 if (S_IS_DEFINED (fixp
->fx_addsy
)
11471 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11473 /* Resolve size relocation against local symbol to size of
11474 the symbol plus addend. */
11475 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11476 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11477 && !fits_in_unsigned_long (value
))
11478 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11479 _("symbol size computation overflow"));
11480 fixp
->fx_addsy
= NULL
;
11481 fixp
->fx_subsy
= NULL
;
11482 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11486 /* Fall through. */
11488 case BFD_RELOC_X86_64_PLT32
:
11489 case BFD_RELOC_X86_64_GOT32
:
11490 case BFD_RELOC_X86_64_GOTPCREL
:
11491 case BFD_RELOC_X86_64_GOTPCRELX
:
11492 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11493 case BFD_RELOC_386_PLT32
:
11494 case BFD_RELOC_386_GOT32
:
11495 case BFD_RELOC_386_GOT32X
:
11496 case BFD_RELOC_386_GOTOFF
:
11497 case BFD_RELOC_386_GOTPC
:
11498 case BFD_RELOC_386_TLS_GD
:
11499 case BFD_RELOC_386_TLS_LDM
:
11500 case BFD_RELOC_386_TLS_LDO_32
:
11501 case BFD_RELOC_386_TLS_IE_32
:
11502 case BFD_RELOC_386_TLS_IE
:
11503 case BFD_RELOC_386_TLS_GOTIE
:
11504 case BFD_RELOC_386_TLS_LE_32
:
11505 case BFD_RELOC_386_TLS_LE
:
11506 case BFD_RELOC_386_TLS_GOTDESC
:
11507 case BFD_RELOC_386_TLS_DESC_CALL
:
11508 case BFD_RELOC_X86_64_TLSGD
:
11509 case BFD_RELOC_X86_64_TLSLD
:
11510 case BFD_RELOC_X86_64_DTPOFF32
:
11511 case BFD_RELOC_X86_64_DTPOFF64
:
11512 case BFD_RELOC_X86_64_GOTTPOFF
:
11513 case BFD_RELOC_X86_64_TPOFF32
:
11514 case BFD_RELOC_X86_64_TPOFF64
:
11515 case BFD_RELOC_X86_64_GOTOFF64
:
11516 case BFD_RELOC_X86_64_GOTPC32
:
11517 case BFD_RELOC_X86_64_GOT64
:
11518 case BFD_RELOC_X86_64_GOTPCREL64
:
11519 case BFD_RELOC_X86_64_GOTPC64
:
11520 case BFD_RELOC_X86_64_GOTPLT64
:
11521 case BFD_RELOC_X86_64_PLTOFF64
:
11522 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11523 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11524 case BFD_RELOC_RVA
:
11525 case BFD_RELOC_VTABLE_ENTRY
:
11526 case BFD_RELOC_VTABLE_INHERIT
:
11528 case BFD_RELOC_32_SECREL
:
11530 code
= fixp
->fx_r_type
;
11532 case BFD_RELOC_X86_64_32S
:
11533 if (!fixp
->fx_pcrel
)
11535 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11536 code
= fixp
->fx_r_type
;
11539 /* Fall through. */
11541 if (fixp
->fx_pcrel
)
11543 switch (fixp
->fx_size
)
11546 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11547 _("can not do %d byte pc-relative relocation"),
11549 code
= BFD_RELOC_32_PCREL
;
11551 case 1: code
= BFD_RELOC_8_PCREL
; break;
11552 case 2: code
= BFD_RELOC_16_PCREL
; break;
11553 case 4: code
= BFD_RELOC_32_PCREL
; break;
11555 case 8: code
= BFD_RELOC_64_PCREL
; break;
11561 switch (fixp
->fx_size
)
11564 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11565 _("can not do %d byte relocation"),
11567 code
= BFD_RELOC_32
;
11569 case 1: code
= BFD_RELOC_8
; break;
11570 case 2: code
= BFD_RELOC_16
; break;
11571 case 4: code
= BFD_RELOC_32
; break;
11573 case 8: code
= BFD_RELOC_64
; break;
11580 if ((code
== BFD_RELOC_32
11581 || code
== BFD_RELOC_32_PCREL
11582 || code
== BFD_RELOC_X86_64_32S
)
11584 && fixp
->fx_addsy
== GOT_symbol
)
11587 code
= BFD_RELOC_386_GOTPC
;
11589 code
= BFD_RELOC_X86_64_GOTPC32
;
11591 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11593 && fixp
->fx_addsy
== GOT_symbol
)
11595 code
= BFD_RELOC_X86_64_GOTPC64
;
11598 rel
= XNEW (arelent
);
11599 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11600 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11602 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11604 if (!use_rela_relocations
)
11606 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11607 vtable entry to be used in the relocation's section offset. */
11608 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11609 rel
->address
= fixp
->fx_offset
;
11610 #if defined (OBJ_COFF) && defined (TE_PE)
11611 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11612 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11617 /* Use the rela in 64bit mode. */
11620 if (disallow_64bit_reloc
)
11623 case BFD_RELOC_X86_64_DTPOFF64
:
11624 case BFD_RELOC_X86_64_TPOFF64
:
11625 case BFD_RELOC_64_PCREL
:
11626 case BFD_RELOC_X86_64_GOTOFF64
:
11627 case BFD_RELOC_X86_64_GOT64
:
11628 case BFD_RELOC_X86_64_GOTPCREL64
:
11629 case BFD_RELOC_X86_64_GOTPC64
:
11630 case BFD_RELOC_X86_64_GOTPLT64
:
11631 case BFD_RELOC_X86_64_PLTOFF64
:
11632 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11633 _("cannot represent relocation type %s in x32 mode"),
11634 bfd_get_reloc_code_name (code
));
11640 if (!fixp
->fx_pcrel
)
11641 rel
->addend
= fixp
->fx_offset
;
11645 case BFD_RELOC_X86_64_PLT32
:
11646 case BFD_RELOC_X86_64_GOT32
:
11647 case BFD_RELOC_X86_64_GOTPCREL
:
11648 case BFD_RELOC_X86_64_GOTPCRELX
:
11649 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11650 case BFD_RELOC_X86_64_TLSGD
:
11651 case BFD_RELOC_X86_64_TLSLD
:
11652 case BFD_RELOC_X86_64_GOTTPOFF
:
11653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11654 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11655 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11658 rel
->addend
= (section
->vma
11660 + fixp
->fx_addnumber
11661 + md_pcrel_from (fixp
));
11666 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11667 if (rel
->howto
== NULL
)
11669 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11670 _("cannot represent relocation type %s"),
11671 bfd_get_reloc_code_name (code
));
11672 /* Set howto to a garbage value so that we can keep going. */
11673 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11674 gas_assert (rel
->howto
!= NULL
);
11680 #include "tc-i386-intel.c"
11683 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11685 int saved_naked_reg
;
11686 char saved_register_dot
;
11688 saved_naked_reg
= allow_naked_reg
;
11689 allow_naked_reg
= 1;
11690 saved_register_dot
= register_chars
['.'];
11691 register_chars
['.'] = '.';
11692 allow_pseudo_reg
= 1;
11693 expression_and_evaluate (exp
);
11694 allow_pseudo_reg
= 0;
11695 register_chars
['.'] = saved_register_dot
;
11696 allow_naked_reg
= saved_naked_reg
;
11698 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11700 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11702 exp
->X_op
= O_constant
;
11703 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11704 .dw2_regnum
[flag_code
>> 1];
11707 exp
->X_op
= O_illegal
;
11712 tc_x86_frame_initial_instructions (void)
11714 static unsigned int sp_regno
[2];
11716 if (!sp_regno
[flag_code
>> 1])
11718 char *saved_input
= input_line_pointer
;
11719 char sp
[][4] = {"esp", "rsp"};
11722 input_line_pointer
= sp
[flag_code
>> 1];
11723 tc_x86_parse_to_dw2regnum (&exp
);
11724 gas_assert (exp
.X_op
== O_constant
);
11725 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11726 input_line_pointer
= saved_input
;
11729 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11730 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11734 x86_dwarf2_addr_size (void)
11736 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11737 if (x86_elf_abi
== X86_64_X32_ABI
)
11740 return bfd_arch_bits_per_address (stdoutput
) / 8;
11744 i386_elf_section_type (const char *str
, size_t len
)
11746 if (flag_code
== CODE_64BIT
11747 && len
== sizeof ("unwind") - 1
11748 && strncmp (str
, "unwind", 6) == 0)
11749 return SHT_X86_64_UNWIND
;
11756 i386_solaris_fix_up_eh_frame (segT sec
)
11758 if (flag_code
== CODE_64BIT
)
11759 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11765 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11769 exp
.X_op
= O_secrel
;
11770 exp
.X_add_symbol
= symbol
;
11771 exp
.X_add_number
= 0;
11772 emit_expr (&exp
, size
);
11776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11777 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11780 x86_64_section_letter (int letter
, const char **ptr_msg
)
11782 if (flag_code
== CODE_64BIT
)
11785 return SHF_X86_64_LARGE
;
11787 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11790 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11795 x86_64_section_word (char *str
, size_t len
)
11797 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11798 return SHF_X86_64_LARGE
;
11804 handle_large_common (int small ATTRIBUTE_UNUSED
)
11806 if (flag_code
!= CODE_64BIT
)
11808 s_comm_internal (0, elf_common_parse
);
11809 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11813 static segT lbss_section
;
11814 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11815 asection
*saved_bss_section
= bss_section
;
11817 if (lbss_section
== NULL
)
11819 flagword applicable
;
11820 segT seg
= now_seg
;
11821 subsegT subseg
= now_subseg
;
11823 /* The .lbss section is for local .largecomm symbols. */
11824 lbss_section
= subseg_new (".lbss", 0);
11825 applicable
= bfd_applicable_section_flags (stdoutput
);
11826 bfd_set_section_flags (stdoutput
, lbss_section
,
11827 applicable
& SEC_ALLOC
);
11828 seg_info (lbss_section
)->bss
= 1;
11830 subseg_set (seg
, subseg
);
11833 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11834 bss_section
= lbss_section
;
11836 s_comm_internal (0, elf_common_parse
);
11838 elf_com_section_ptr
= saved_com_section_ptr
;
11839 bss_section
= saved_bss_section
;
11842 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */