1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
73 #define RELOC_ENUM enum bfd_reloc_code_real
75 #define RELOC_ENUM int
79 #define DEFAULT_ARCH "i386"
81 static char *default_arch
= DEFAULT_ARCH
;
83 /* 'md_assemble ()' gathers together information and puts it into a
90 const reg_entry
*regs
;
95 /* TM holds the template for the insn were currently assembling. */
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands
;
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
108 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types
[MAX_OPERANDS
];
114 /* Displacement expression, immediate expression, or register for each
116 union i386_op op
[MAX_OPERANDS
];
118 /* Flags for operands. */
119 unsigned int flags
[MAX_OPERANDS
];
120 #define Operand_PCrel 1
122 /* Relocation type for operand */
123 RELOC_ENUM reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
243 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 0
289 #define COND_JUMP86 2
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will have in the variable part of the frag
327 4) which index into the table to try if we can't fit into this one. */
329 /* UNCOND_JUMP states. */
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
331 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
332 /* dword jmp adds 4 bytes to frag:
333 0 extra opcode bytes, 4 displacement bytes. */
335 /* word jmp adds 2 byte2 to frag:
336 0 extra opcode bytes, 2 displacement bytes. */
339 /* COND_JUMP states. */
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
341 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
342 /* dword conditionals adds 5 bytes to frag:
343 1 extra opcode byte, 4 displacement bytes. */
345 /* word conditionals add 3 bytes to frag:
346 1 extra opcode byte, 2 displacement bytes. */
349 /* COND_JUMP86 states. */
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
351 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
352 /* dword conditionals adds 5 bytes to frag:
353 1 extra opcode byte, 4 displacement bytes. */
355 /* word conditionals add 4 bytes to frag:
356 1 displacement byte and a 3 byte long branch insn. */
360 static const arch_entry cpu_arch
[] = {
362 {"i186", Cpu086
|Cpu186
},
363 {"i286", Cpu086
|Cpu186
|Cpu286
},
364 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
365 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
366 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
367 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
368 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
369 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
370 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
371 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
372 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
373 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
378 i386_align_code (fragP
, count
)
382 /* Various efficient no-op patterns for aligning code labels.
383 Note: Don't try to assemble the instructions in the comments.
384 0L and 0w are not legal. */
385 static const char f32_1
[] =
387 static const char f32_2
[] =
388 {0x89,0xf6}; /* movl %esi,%esi */
389 static const char f32_3
[] =
390 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
391 static const char f32_4
[] =
392 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
393 static const char f32_5
[] =
395 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_6
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
398 static const char f32_7
[] =
399 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
400 static const char f32_8
[] =
402 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_9
[] =
404 {0x89,0xf6, /* movl %esi,%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_10
[] =
407 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_11
[] =
410 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_12
[] =
413 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
414 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
415 static const char f32_13
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
418 static const char f32_14
[] =
419 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_15
[] =
422 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
423 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
424 static const char f16_3
[] =
425 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
426 static const char f16_4
[] =
427 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
428 static const char f16_5
[] =
430 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_6
[] =
432 {0x89,0xf6, /* mov %si,%si */
433 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
434 static const char f16_7
[] =
435 {0x8d,0x74,0x00, /* lea 0(%si),%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_8
[] =
438 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char *const f32_patt
[] = {
441 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
442 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
444 static const char *const f16_patt
[] = {
445 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
446 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
449 /* ??? We can't use these fillers for x86_64, since they often kills the
450 upper halves. Solve later. */
451 if (flag_code
== CODE_64BIT
)
454 if (count
> 0 && count
<= 15)
456 if (flag_code
== CODE_16BIT
)
458 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
459 f16_patt
[count
- 1], count
);
461 /* Adjust jump offset. */
462 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
465 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
466 f32_patt
[count
- 1], count
);
467 fragP
->fr_var
= count
;
471 static char *output_invalid
PARAMS ((int c
));
472 static int i386_operand
PARAMS ((char *operand_string
));
473 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
474 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
478 static void s_bss
PARAMS ((int));
481 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
483 static INLINE
unsigned int
484 mode_from_disp_size (t
)
487 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
491 fits_in_signed_byte (num
)
494 return (num
>= -128) && (num
<= 127);
498 fits_in_unsigned_byte (num
)
501 return (num
& 0xff) == num
;
505 fits_in_unsigned_word (num
)
508 return (num
& 0xffff) == num
;
512 fits_in_signed_word (num
)
515 return (-32768 <= num
) && (num
<= 32767);
518 fits_in_signed_long (num
)
519 offsetT num ATTRIBUTE_UNUSED
;
524 return (!(((offsetT
) -1 << 31) & num
)
525 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
527 } /* fits_in_signed_long() */
529 fits_in_unsigned_long (num
)
530 offsetT num ATTRIBUTE_UNUSED
;
535 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
537 } /* fits_in_unsigned_long() */
540 smallest_imm_type (num
)
543 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
544 && !(cpu_arch_flags
& (CpuUnknown
)))
546 /* This code is disabled on the 486 because all the Imm1 forms
547 in the opcode table are slower on the i486. They're the
548 versions with the implicitly specified single-position
549 displacement, which has another syntax if you really want to
552 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
554 return (fits_in_signed_byte (num
)
555 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
556 : fits_in_unsigned_byte (num
)
557 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
558 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
559 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_signed_long (num
)
561 ? (Imm32
| Imm32S
| Imm64
)
562 : fits_in_unsigned_long (num
)
568 offset_in_range (val
, size
)
576 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
577 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
578 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
580 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
585 /* If BFD64, sign extend val. */
586 if (!use_rela_relocations
)
587 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
588 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
590 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
592 char buf1
[40], buf2
[40];
594 sprint_value (buf1
, val
);
595 sprint_value (buf2
, val
& mask
);
596 as_warn (_("%s shortened to %s"), buf1
, buf2
);
601 /* Returns 0 if attempting to add a prefix where one from the same
602 class already exists, 1 if non rep/repne added, 2 if rep/repne
611 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
619 case CS_PREFIX_OPCODE
:
620 case DS_PREFIX_OPCODE
:
621 case ES_PREFIX_OPCODE
:
622 case FS_PREFIX_OPCODE
:
623 case GS_PREFIX_OPCODE
:
624 case SS_PREFIX_OPCODE
:
628 case REPNE_PREFIX_OPCODE
:
629 case REPE_PREFIX_OPCODE
:
632 case LOCK_PREFIX_OPCODE
:
640 case ADDR_PREFIX_OPCODE
:
644 case DATA_PREFIX_OPCODE
:
651 as_bad (_("same type of prefix used twice"));
656 i
.prefix
[q
] = prefix
;
661 set_code_flag (value
)
665 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
666 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
667 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
669 as_bad (_("64bit mode not supported on this CPU."));
671 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
673 as_bad (_("32bit mode not supported on this CPU."));
679 set_16bit_gcc_code_flag (new_code_flag
)
682 flag_code
= new_code_flag
;
683 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
684 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
689 set_intel_syntax (syntax_flag
)
692 /* Find out if register prefixing is specified. */
693 int ask_naked_reg
= 0;
696 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
698 char *string
= input_line_pointer
;
699 int e
= get_symbol_end ();
701 if (strcmp (string
, "prefix") == 0)
703 else if (strcmp (string
, "noprefix") == 0)
706 as_bad (_("bad argument to syntax directive."));
707 *input_line_pointer
= e
;
709 demand_empty_rest_of_line ();
711 intel_syntax
= syntax_flag
;
713 if (ask_naked_reg
== 0)
716 allow_naked_reg
= (intel_syntax
717 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
719 /* Conservative default. */
724 allow_naked_reg
= (ask_naked_reg
< 0);
729 int dummy ATTRIBUTE_UNUSED
;
733 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
735 char *string
= input_line_pointer
;
736 int e
= get_symbol_end ();
739 for (i
= 0; cpu_arch
[i
].name
; i
++)
741 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
743 cpu_arch_name
= cpu_arch
[i
].name
;
744 cpu_arch_flags
= (cpu_arch
[i
].flags
745 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
749 if (!cpu_arch
[i
].name
)
750 as_bad (_("no such architecture: `%s'"), string
);
752 *input_line_pointer
= e
;
755 as_bad (_("missing cpu architecture"));
757 no_cond_jump_promotion
= 0;
758 if (*input_line_pointer
== ','
759 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
761 char *string
= ++input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "nojumps") == 0)
765 no_cond_jump_promotion
= 1;
766 else if (strcmp (string
, "jumps") == 0)
769 as_bad (_("no such architecture modifier: `%s'"), string
);
771 *input_line_pointer
= e
;
774 demand_empty_rest_of_line ();
777 const pseudo_typeS md_pseudo_table
[] =
779 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
780 {"align", s_align_bytes
, 0},
782 {"align", s_align_ptwo
, 0},
784 {"arch", set_cpu_arch
, 0},
788 {"ffloat", float_cons
, 'f'},
789 {"dfloat", float_cons
, 'd'},
790 {"tfloat", float_cons
, 'x'},
792 {"noopt", s_ignore
, 0},
793 {"optim", s_ignore
, 0},
794 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
795 {"code16", set_code_flag
, CODE_16BIT
},
796 {"code32", set_code_flag
, CODE_32BIT
},
797 {"code64", set_code_flag
, CODE_64BIT
},
798 {"intel_syntax", set_intel_syntax
, 1},
799 {"att_syntax", set_intel_syntax
, 0},
800 {"file", dwarf2_directive_file
, 0},
801 {"loc", dwarf2_directive_loc
, 0},
805 /* For interface with expression (). */
806 extern char *input_line_pointer
;
808 /* Hash table for instruction mnemonic lookup. */
809 static struct hash_control
*op_hash
;
811 /* Hash table for register lookup. */
812 static struct hash_control
*reg_hash
;
818 if (!strcmp (default_arch
, "x86_64"))
819 return bfd_mach_x86_64
;
820 else if (!strcmp (default_arch
, "i386"))
821 return bfd_mach_i386_i386
;
823 as_fatal (_("Unknown architecture"));
830 const char *hash_err
;
832 /* Initialize op_hash hash table. */
833 op_hash
= hash_new ();
836 register const template *optab
;
837 register templates
*core_optab
;
839 /* Setup for loop. */
841 core_optab
= (templates
*) xmalloc (sizeof (templates
));
842 core_optab
->start
= optab
;
847 if (optab
->name
== NULL
848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
850 /* different name --> ship out current template list;
851 add to hash table; & begin anew. */
852 core_optab
->end
= optab
;
853 hash_err
= hash_insert (op_hash
,
858 as_fatal (_("Internal Error: Can't hash %s: %s"),
862 if (optab
->name
== NULL
)
864 core_optab
= (templates
*) xmalloc (sizeof (templates
));
865 core_optab
->start
= optab
;
870 /* Initialize reg_hash hash table. */
871 reg_hash
= hash_new ();
873 register const reg_entry
*regtab
;
875 for (regtab
= i386_regtab
;
876 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
879 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
881 as_fatal (_("Internal Error: Can't hash %s: %s"),
887 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 for (c
= 0; c
< 256; c
++)
897 mnemonic_chars
[c
] = c
;
898 register_chars
[c
] = c
;
899 operand_chars
[c
] = c
;
901 else if (islower (c
))
903 mnemonic_chars
[c
] = c
;
904 register_chars
[c
] = c
;
905 operand_chars
[c
] = c
;
907 else if (isupper (c
))
909 mnemonic_chars
[c
] = tolower (c
);
910 register_chars
[c
] = mnemonic_chars
[c
];
911 operand_chars
[c
] = c
;
914 if (isalpha (c
) || isdigit (c
))
915 identifier_chars
[c
] = c
;
918 identifier_chars
[c
] = c
;
919 operand_chars
[c
] = c
;
924 identifier_chars
['@'] = '@';
926 digit_chars
['-'] = '-';
927 identifier_chars
['_'] = '_';
928 identifier_chars
['.'] = '.';
930 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
931 operand_chars
[(unsigned char) *p
] = *p
;
934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
935 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
937 record_alignment (text_section
, 2);
938 record_alignment (data_section
, 2);
939 record_alignment (bss_section
, 2);
945 i386_print_statistics (file
)
948 hash_print_statistics (file
, "i386 opcode", op_hash
);
949 hash_print_statistics (file
, "i386 register", reg_hash
);
954 /* Debugging routines for md_assemble. */
955 static void pi
PARAMS ((char *, i386_insn
*));
956 static void pte
PARAMS ((template *));
957 static void pt
PARAMS ((unsigned int));
958 static void pe
PARAMS ((expressionS
*));
959 static void ps
PARAMS ((symbolS
*));
968 fprintf (stdout
, "%s: template ", line
);
970 fprintf (stdout
, " address: base %s index %s scale %x\n",
971 x
->base_reg
? x
->base_reg
->reg_name
: "none",
972 x
->index_reg
? x
->index_reg
->reg_name
: "none",
973 x
->log2_scale_factor
);
974 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
975 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
976 fprintf (stdout
, " sib: base %x index %x scale %x\n",
977 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
978 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
979 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
980 for (i
= 0; i
< x
->operands
; i
++)
982 fprintf (stdout
, " #%d: ", i
+ 1);
984 fprintf (stdout
, "\n");
986 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
987 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
988 if (x
->types
[i
] & Imm
)
990 if (x
->types
[i
] & Disp
)
1000 fprintf (stdout
, " %d operands ", t
->operands
);
1001 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1002 if (t
->extension_opcode
!= None
)
1003 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1004 if (t
->opcode_modifier
& D
)
1005 fprintf (stdout
, "D");
1006 if (t
->opcode_modifier
& W
)
1007 fprintf (stdout
, "W");
1008 fprintf (stdout
, "\n");
1009 for (i
= 0; i
< t
->operands
; i
++)
1011 fprintf (stdout
, " #%d type ", i
+ 1);
1012 pt (t
->operand_types
[i
]);
1013 fprintf (stdout
, "\n");
1021 fprintf (stdout
, " operation %d\n", e
->X_op
);
1022 fprintf (stdout
, " add_number %ld (%lx)\n",
1023 (long) e
->X_add_number
, (long) e
->X_add_number
);
1024 if (e
->X_add_symbol
)
1026 fprintf (stdout
, " add_symbol ");
1027 ps (e
->X_add_symbol
);
1028 fprintf (stdout
, "\n");
1032 fprintf (stdout
, " op_symbol ");
1033 ps (e
->X_op_symbol
);
1034 fprintf (stdout
, "\n");
1042 fprintf (stdout
, "%s type %s%s",
1044 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1045 segment_name (S_GET_SEGMENT (s
)));
1067 { BaseIndex
, "BaseIndex" },
1071 { Disp32S
, "d32s" },
1073 { InOutPortReg
, "InOutPortReg" },
1074 { ShiftCount
, "ShiftCount" },
1075 { Control
, "control reg" },
1076 { Test
, "test reg" },
1077 { Debug
, "debug reg" },
1078 { FloatReg
, "FReg" },
1079 { FloatAcc
, "FAcc" },
1083 { JumpAbsolute
, "Jump Absolute" },
1094 register struct type_name
*ty
;
1096 for (ty
= type_names
; ty
->mask
; ty
++)
1098 fprintf (stdout
, "%s, ", ty
->tname
);
1102 #endif /* DEBUG386 */
1105 tc_i386_force_relocation (fixp
)
1108 #ifdef BFD_ASSEMBLER
1109 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1110 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1115 return fixp
->fx_r_type
== 7;
1119 #ifdef BFD_ASSEMBLER
1121 static bfd_reloc_code_real_type
1122 reloc (size
, pcrel
, sign
, other
)
1126 bfd_reloc_code_real_type other
;
1128 if (other
!= NO_RELOC
)
1134 as_bad (_("There are no unsigned pc-relative relocations"));
1137 case 1: return BFD_RELOC_8_PCREL
;
1138 case 2: return BFD_RELOC_16_PCREL
;
1139 case 4: return BFD_RELOC_32_PCREL
;
1141 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1148 case 4: return BFD_RELOC_X86_64_32S
;
1153 case 1: return BFD_RELOC_8
;
1154 case 2: return BFD_RELOC_16
;
1155 case 4: return BFD_RELOC_32
;
1156 case 8: return BFD_RELOC_64
;
1158 as_bad (_("can not do %s %d byte relocation"),
1159 sign
? "signed" : "unsigned", size
);
1163 return BFD_RELOC_NONE
;
1166 /* Here we decide which fixups can be adjusted to make them relative to
1167 the beginning of the section instead of the symbol. Basically we need
1168 to make sure that the dynamic relocations are done correctly, so in
1169 some cases we force the original symbol to be used. */
1172 tc_i386_fix_adjustable (fixP
)
1175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1176 /* Prevent all adjustments to global symbols, or else dynamic
1177 linking will not work correctly. */
1178 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1179 || S_IS_WEAK (fixP
->fx_addsy
))
1182 /* adjust_reloc_syms doesn't know about the GOT. */
1183 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1184 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1185 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1188 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1190 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1195 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1196 #define BFD_RELOC_16 0
1197 #define BFD_RELOC_32 0
1198 #define BFD_RELOC_16_PCREL 0
1199 #define BFD_RELOC_32_PCREL 0
1200 #define BFD_RELOC_386_PLT32 0
1201 #define BFD_RELOC_386_GOT32 0
1202 #define BFD_RELOC_386_GOTOFF 0
1203 #define BFD_RELOC_X86_64_PLT32 0
1204 #define BFD_RELOC_X86_64_GOT32 0
1205 #define BFD_RELOC_X86_64_GOTPCREL 0
1208 static int intel_float_operand
PARAMS ((char *mnemonic
));
1211 intel_float_operand (mnemonic
)
1214 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1217 if (mnemonic
[0] == 'f')
1223 /* This is the guts of the machine-dependent assembler. LINE points to a
1224 machine dependent instruction. This function is supposed to emit
1225 the frags/bytes it assembles to. */
1231 /* Points to template once we've found it. */
1236 char mnemonic
[MAX_MNEM_SIZE
];
1238 /* Initialize globals. */
1239 memset (&i
, '\0', sizeof (i
));
1240 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1241 i
.reloc
[j
] = NO_RELOC
;
1242 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1243 memset (im_expressions
, '\0', sizeof (im_expressions
));
1244 save_stack_p
= save_stack
;
1246 /* First parse an instruction mnemonic & call i386_operand for the operands.
1247 We assume that the scrubber has arranged it so that line[0] is the valid
1248 start of a (possibly prefixed) mnemonic. */
1251 char *token_start
= l
;
1254 /* Non-zero if we found a prefix only acceptable with string insns. */
1255 const char *expecting_string_instruction
= NULL
;
1260 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1263 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1265 as_bad (_("no such instruction: `%s'"), token_start
);
1270 if (!is_space_char (*l
)
1271 && *l
!= END_OF_INSN
1272 && *l
!= PREFIX_SEPARATOR
)
1274 as_bad (_("invalid character %s in mnemonic"),
1275 output_invalid (*l
));
1278 if (token_start
== l
)
1280 if (*l
== PREFIX_SEPARATOR
)
1281 as_bad (_("expecting prefix; got nothing"));
1283 as_bad (_("expecting mnemonic; got nothing"));
1287 /* Look up instruction (or prefix) via hash table. */
1288 current_templates
= hash_find (op_hash
, mnemonic
);
1290 if (*l
!= END_OF_INSN
1291 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1292 && current_templates
1293 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1295 /* If we are in 16-bit mode, do not allow addr16 or data16.
1296 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1297 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1298 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1299 ^ (flag_code
== CODE_16BIT
)))
1301 as_bad (_("redundant %s prefix"),
1302 current_templates
->start
->name
);
1305 /* Add prefix, checking for repeated prefixes. */
1306 switch (add_prefix (current_templates
->start
->base_opcode
))
1311 expecting_string_instruction
= current_templates
->start
->name
;
1314 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1321 if (!current_templates
)
1323 /* See if we can get a match by trimming off a suffix. */
1326 case WORD_MNEM_SUFFIX
:
1327 case BYTE_MNEM_SUFFIX
:
1328 case QWORD_MNEM_SUFFIX
:
1329 i
.suffix
= mnem_p
[-1];
1331 current_templates
= hash_find (op_hash
, mnemonic
);
1333 case SHORT_MNEM_SUFFIX
:
1334 case LONG_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1347 if (intel_float_operand (mnemonic
))
1348 i
.suffix
= SHORT_MNEM_SUFFIX
;
1350 i
.suffix
= LONG_MNEM_SUFFIX
;
1352 current_templates
= hash_find (op_hash
, mnemonic
);
1356 if (!current_templates
)
1358 as_bad (_("no such instruction: `%s'"), token_start
);
1363 /* Check if instruction is supported on specified architecture. */
1364 if (cpu_arch_flags
!= 0)
1366 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1367 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1369 as_warn (_("`%s' is not supported on `%s'"),
1370 current_templates
->start
->name
, cpu_arch_name
);
1372 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1374 as_warn (_("use .code16 to ensure correct addressing mode"));
1378 /* Check for rep/repne without a string instruction. */
1379 if (expecting_string_instruction
1380 && !(current_templates
->start
->opcode_modifier
& IsString
))
1382 as_bad (_("expecting string instruction after `%s'"),
1383 expecting_string_instruction
);
1387 /* There may be operands to parse. */
1388 if (*l
!= END_OF_INSN
)
1390 /* 1 if operand is pending after ','. */
1391 unsigned int expecting_operand
= 0;
1393 /* Non-zero if operand parens not balanced. */
1394 unsigned int paren_not_balanced
;
1398 /* Skip optional white space before operand. */
1399 if (is_space_char (*l
))
1401 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1403 as_bad (_("invalid character %s before operand %d"),
1404 output_invalid (*l
),
1408 token_start
= l
; /* after white space */
1409 paren_not_balanced
= 0;
1410 while (paren_not_balanced
|| *l
!= ',')
1412 if (*l
== END_OF_INSN
)
1414 if (paren_not_balanced
)
1417 as_bad (_("unbalanced parenthesis in operand %d."),
1420 as_bad (_("unbalanced brackets in operand %d."),
1425 break; /* we are done */
1427 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1429 as_bad (_("invalid character %s in operand %d"),
1430 output_invalid (*l
),
1437 ++paren_not_balanced
;
1439 --paren_not_balanced
;
1444 ++paren_not_balanced
;
1446 --paren_not_balanced
;
1450 if (l
!= token_start
)
1451 { /* Yes, we've read in another operand. */
1452 unsigned int operand_ok
;
1453 this_operand
= i
.operands
++;
1454 if (i
.operands
> MAX_OPERANDS
)
1456 as_bad (_("spurious operands; (%d operands/instruction max)"),
1460 /* Now parse operand adding info to 'i' as we go along. */
1461 END_STRING_AND_SAVE (l
);
1465 i386_intel_operand (token_start
,
1466 intel_float_operand (mnemonic
));
1468 operand_ok
= i386_operand (token_start
);
1470 RESTORE_END_STRING (l
);
1476 if (expecting_operand
)
1478 expecting_operand_after_comma
:
1479 as_bad (_("expecting operand after ','; got nothing"));
1484 as_bad (_("expecting operand before ','; got nothing"));
1489 /* Now *l must be either ',' or END_OF_INSN. */
1492 if (*++l
== END_OF_INSN
)
1494 /* Just skip it, if it's \n complain. */
1495 goto expecting_operand_after_comma
;
1497 expecting_operand
= 1;
1500 while (*l
!= END_OF_INSN
);
1504 /* Now we've parsed the mnemonic into a set of templates, and have the
1507 Next, we find a template that matches the given insn,
1508 making sure the overlap of the given operands types is consistent
1509 with the template operand types. */
1511 #define MATCH(overlap, given, template) \
1512 ((overlap & ~JumpAbsolute) \
1513 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1515 /* If given types r0 and r1 are registers they must be of the same type
1516 unless the expected operand type register overlap is null.
1517 Note that Acc in a template matches every size of reg. */
1518 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1519 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1520 ((g0) & Reg) == ((g1) & Reg) || \
1521 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1524 register unsigned int overlap0
, overlap1
;
1525 unsigned int overlap2
;
1526 unsigned int found_reverse_match
;
1529 /* All intel opcodes have reversed operands except for "bound" and
1530 "enter". We also don't reverse intersegment "jmp" and "call"
1531 instructions with 2 immediate operands so that the immediate segment
1532 precedes the offset, as it does when in AT&T mode. "enter" and the
1533 intersegment "jmp" and "call" instructions are the only ones that
1534 have two immediate operands. */
1535 if (intel_syntax
&& i
.operands
> 1
1536 && (strcmp (mnemonic
, "bound") != 0)
1537 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1539 union i386_op temp_op
;
1540 unsigned int temp_type
;
1541 RELOC_ENUM temp_reloc
;
1545 if (i
.operands
== 2)
1550 else if (i
.operands
== 3)
1555 temp_type
= i
.types
[xchg2
];
1556 i
.types
[xchg2
] = i
.types
[xchg1
];
1557 i
.types
[xchg1
] = temp_type
;
1558 temp_op
= i
.op
[xchg2
];
1559 i
.op
[xchg2
] = i
.op
[xchg1
];
1560 i
.op
[xchg1
] = temp_op
;
1561 temp_reloc
= i
.reloc
[xchg2
];
1562 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1563 i
.reloc
[xchg1
] = temp_reloc
;
1565 if (i
.mem_operands
== 2)
1567 const seg_entry
*temp_seg
;
1568 temp_seg
= i
.seg
[0];
1569 i
.seg
[0] = i
.seg
[1];
1570 i
.seg
[1] = temp_seg
;
1576 /* Try to ensure constant immediates are represented in the smallest
1578 char guess_suffix
= 0;
1582 guess_suffix
= i
.suffix
;
1583 else if (i
.reg_operands
)
1585 /* Figure out a suffix from the last register operand specified.
1586 We can't do this properly yet, ie. excluding InOutPortReg,
1587 but the following works for instructions with immediates.
1588 In any case, we can't set i.suffix yet. */
1589 for (op
= i
.operands
; --op
>= 0;)
1590 if (i
.types
[op
] & Reg
)
1592 if (i
.types
[op
] & Reg8
)
1593 guess_suffix
= BYTE_MNEM_SUFFIX
;
1594 else if (i
.types
[op
] & Reg16
)
1595 guess_suffix
= WORD_MNEM_SUFFIX
;
1596 else if (i
.types
[op
] & Reg32
)
1597 guess_suffix
= LONG_MNEM_SUFFIX
;
1598 else if (i
.types
[op
] & Reg64
)
1599 guess_suffix
= QWORD_MNEM_SUFFIX
;
1603 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1604 guess_suffix
= WORD_MNEM_SUFFIX
;
1606 for (op
= i
.operands
; --op
>= 0;)
1607 if (i
.types
[op
] & Imm
)
1609 switch (i
.op
[op
].imms
->X_op
)
1612 /* If a suffix is given, this operand may be shortened. */
1613 switch (guess_suffix
)
1615 case LONG_MNEM_SUFFIX
:
1616 i
.types
[op
] |= Imm32
| Imm64
;
1618 case WORD_MNEM_SUFFIX
:
1619 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1621 case BYTE_MNEM_SUFFIX
:
1622 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1626 /* If this operand is at most 16 bits, convert it
1627 to a signed 16 bit number before trying to see
1628 whether it will fit in an even smaller size.
1629 This allows a 16-bit operand such as $0xffe0 to
1630 be recognised as within Imm8S range. */
1631 if ((i
.types
[op
] & Imm16
)
1632 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1634 i
.op
[op
].imms
->X_add_number
=
1635 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1637 if ((i
.types
[op
] & Imm32
)
1638 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1640 i
.op
[op
].imms
->X_add_number
=
1641 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1643 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1644 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1645 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1646 i
.types
[op
] &= ~Imm32
;
1651 /* Symbols and expressions. */
1653 /* Convert symbolic operand to proper sizes for matching. */
1654 switch (guess_suffix
)
1656 case QWORD_MNEM_SUFFIX
:
1657 i
.types
[op
] = Imm64
| Imm32S
;
1659 case LONG_MNEM_SUFFIX
:
1660 i
.types
[op
] = Imm32
| Imm64
;
1662 case WORD_MNEM_SUFFIX
:
1663 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1666 case BYTE_MNEM_SUFFIX
:
1667 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1676 if (i
.disp_operands
)
1678 /* Try to use the smallest displacement type too. */
1681 for (op
= i
.operands
; --op
>= 0;)
1682 if ((i
.types
[op
] & Disp
)
1683 && i
.op
[op
].disps
->X_op
== O_constant
)
1685 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1687 if (i
.types
[op
] & Disp16
)
1689 /* We know this operand is at most 16 bits, so
1690 convert to a signed 16 bit number before trying
1691 to see whether it will fit in an even smaller
1694 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1696 else if (i
.types
[op
] & Disp32
)
1698 /* We know this operand is at most 32 bits, so convert to a
1699 signed 32 bit number before trying to see whether it will
1700 fit in an even smaller size. */
1701 disp
&= (((offsetT
) 2 << 31) - 1);
1702 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1704 if (flag_code
== CODE_64BIT
)
1706 if (fits_in_signed_long (disp
))
1707 i
.types
[op
] |= Disp32S
;
1708 if (fits_in_unsigned_long (disp
))
1709 i
.types
[op
] |= Disp32
;
1711 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1712 && fits_in_signed_byte (disp
))
1713 i
.types
[op
] |= Disp8
;
1720 found_reverse_match
= 0;
1721 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1723 : (i
.suffix
== WORD_MNEM_SUFFIX
1725 : (i
.suffix
== SHORT_MNEM_SUFFIX
1727 : (i
.suffix
== LONG_MNEM_SUFFIX
1729 : (i
.suffix
== QWORD_MNEM_SUFFIX
1731 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1733 for (t
= current_templates
->start
;
1734 t
< current_templates
->end
;
1737 /* Must have right number of operands. */
1738 if (i
.operands
!= t
->operands
)
1741 /* Check the suffix, except for some instructions in intel mode. */
1742 if ((t
->opcode_modifier
& suffix_check
)
1744 && (t
->opcode_modifier
& IgnoreSize
))
1746 && t
->base_opcode
== 0xd9
1747 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1748 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1751 /* Do not verify operands when there are none. */
1752 else if (!t
->operands
)
1754 if (t
->cpu_flags
& ~cpu_arch_flags
)
1756 /* We've found a match; break out of loop. */
1760 overlap0
= i
.types
[0] & t
->operand_types
[0];
1761 switch (t
->operands
)
1764 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1769 overlap1
= i
.types
[1] & t
->operand_types
[1];
1770 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1771 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1772 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1773 t
->operand_types
[0],
1774 overlap1
, i
.types
[1],
1775 t
->operand_types
[1]))
1777 /* Check if other direction is valid ... */
1778 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1781 /* Try reversing direction of operands. */
1782 overlap0
= i
.types
[0] & t
->operand_types
[1];
1783 overlap1
= i
.types
[1] & t
->operand_types
[0];
1784 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1785 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1786 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1787 t
->operand_types
[1],
1788 overlap1
, i
.types
[1],
1789 t
->operand_types
[0]))
1791 /* Does not match either direction. */
1794 /* found_reverse_match holds which of D or FloatDR
1796 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1798 /* Found a forward 2 operand match here. */
1799 else if (t
->operands
== 3)
1801 /* Here we make use of the fact that there are no
1802 reverse match 3 operand instructions, and all 3
1803 operand instructions only need to be checked for
1804 register consistency between operands 2 and 3. */
1805 overlap2
= i
.types
[2] & t
->operand_types
[2];
1806 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1807 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1808 t
->operand_types
[1],
1809 overlap2
, i
.types
[2],
1810 t
->operand_types
[2]))
1814 /* Found either forward/reverse 2 or 3 operand match here:
1815 slip through to break. */
1817 if (t
->cpu_flags
& ~cpu_arch_flags
)
1819 found_reverse_match
= 0;
1822 /* We've found a match; break out of loop. */
1825 if (t
== current_templates
->end
)
1827 /* We found no match. */
1828 as_bad (_("suffix or operands invalid for `%s'"),
1829 current_templates
->start
->name
);
1833 if (!quiet_warnings
)
1836 && ((i
.types
[0] & JumpAbsolute
)
1837 != (t
->operand_types
[0] & JumpAbsolute
)))
1839 as_warn (_("indirect %s without `*'"), t
->name
);
1842 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1843 == (IsPrefix
|IgnoreSize
))
1845 /* Warn them that a data or address size prefix doesn't
1846 affect assembly of the next line of code. */
1847 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1851 /* Copy the template we found. */
1853 if (found_reverse_match
)
1855 /* If we found a reverse match we must alter the opcode
1856 direction bit. found_reverse_match holds bits to change
1857 (different for int & float insns). */
1859 i
.tm
.base_opcode
^= found_reverse_match
;
1861 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1862 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1865 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1868 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1869 i
.tm
.base_opcode
^= FloatR
;
1871 if (i
.tm
.opcode_modifier
& FWait
)
1872 if (! add_prefix (FWAIT_OPCODE
))
1875 /* Check string instruction segment overrides. */
1876 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1878 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1879 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1881 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1883 as_bad (_("`%s' operand %d must use `%%es' segment"),
1888 /* There's only ever one segment override allowed per instruction.
1889 This instruction possibly has a legal segment override on the
1890 second operand, so copy the segment to where non-string
1891 instructions store it, allowing common code. */
1892 i
.seg
[0] = i
.seg
[1];
1894 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1896 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1898 as_bad (_("`%s' operand %d must use `%%es' segment"),
1906 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1909 for (op
= i
.operands
; --op
>= 0;)
1910 if ((i
.types
[op
] & Reg
)
1911 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1913 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1914 i
.op
[op
].regs
->reg_name
);
1919 /* If matched instruction specifies an explicit instruction mnemonic
1921 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1923 if (i
.tm
.opcode_modifier
& Size16
)
1924 i
.suffix
= WORD_MNEM_SUFFIX
;
1925 else if (i
.tm
.opcode_modifier
& Size64
)
1926 i
.suffix
= QWORD_MNEM_SUFFIX
;
1928 i
.suffix
= LONG_MNEM_SUFFIX
;
1930 else if (i
.reg_operands
)
1932 /* If there's no instruction mnemonic suffix we try to invent one
1933 based on register operands. */
1936 /* We take i.suffix from the last register operand specified,
1937 Destination register type is more significant than source
1940 for (op
= i
.operands
; --op
>= 0;)
1941 if ((i
.types
[op
] & Reg
)
1942 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1944 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1945 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1946 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1951 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1954 for (op
= i
.operands
; --op
>= 0;)
1956 /* If this is an eight bit register, it's OK. If it's
1957 the 16 or 32 bit version of an eight bit register,
1958 we will just use the low portion, and that's OK too. */
1959 if (i
.types
[op
] & Reg8
)
1962 /* movzx and movsx should not generate this warning. */
1964 && (i
.tm
.base_opcode
== 0xfb7
1965 || i
.tm
.base_opcode
== 0xfb6
1966 || i
.tm
.base_opcode
== 0x63
1967 || i
.tm
.base_opcode
== 0xfbe
1968 || i
.tm
.base_opcode
== 0xfbf))
1971 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1973 /* Check that the template allows eight bit regs
1974 This kills insns such as `orb $1,%edx', which
1975 maybe should be allowed. */
1976 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1980 /* Prohibit these changes in the 64bit mode, since
1981 the lowering is more complicated. */
1982 if (flag_code
== CODE_64BIT
1983 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1984 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1985 i
.op
[op
].regs
->reg_name
,
1987 #if REGISTER_WARNINGS
1989 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1990 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1992 + (i
.types
[op
] & Reg16
1993 ? REGNAM_AL
- REGNAM_AX
1994 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
1995 i
.op
[op
].regs
->reg_name
,
2000 /* Any other register is bad. */
2001 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2003 | Control
| Debug
| Test
2004 | FloatReg
| FloatAcc
))
2006 as_bad (_("`%%%s' not allowed with `%s%c'"),
2007 i
.op
[op
].regs
->reg_name
,
2014 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2018 for (op
= i
.operands
; --op
>= 0;)
2019 /* Reject eight bit registers, except where the template
2020 requires them. (eg. movzb) */
2021 if ((i
.types
[op
] & Reg8
) != 0
2022 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2024 as_bad (_("`%%%s' not allowed with `%s%c'"),
2025 i
.op
[op
].regs
->reg_name
,
2030 /* Warn if the e prefix on a general reg is missing. */
2031 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2032 && (i
.types
[op
] & Reg16
) != 0
2033 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2035 /* Prohibit these changes in the 64bit mode, since
2036 the lowering is more complicated. */
2037 if (flag_code
== CODE_64BIT
)
2038 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2039 i
.op
[op
].regs
->reg_name
,
2041 #if REGISTER_WARNINGS
2043 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2044 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2045 i
.op
[op
].regs
->reg_name
,
2049 /* Warn if the r prefix on a general reg is missing. */
2050 else if ((i
.types
[op
] & Reg64
) != 0
2051 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2053 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2054 i
.op
[op
].regs
->reg_name
,
2058 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2062 for (op
= i
.operands
; --op
>= 0; )
2063 /* Reject eight bit registers, except where the template
2064 requires them. (eg. movzb) */
2065 if ((i
.types
[op
] & Reg8
) != 0
2066 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2068 as_bad (_("`%%%s' not allowed with `%s%c'"),
2069 i
.op
[op
].regs
->reg_name
,
2074 /* Warn if the e prefix on a general reg is missing. */
2075 else if (((i
.types
[op
] & Reg16
) != 0
2076 || (i
.types
[op
] & Reg32
) != 0)
2077 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2079 /* Prohibit these changes in the 64bit mode, since
2080 the lowering is more complicated. */
2081 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2082 i
.op
[op
].regs
->reg_name
,
2086 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2089 for (op
= i
.operands
; --op
>= 0;)
2090 /* Reject eight bit registers, except where the template
2091 requires them. (eg. movzb) */
2092 if ((i
.types
[op
] & Reg8
) != 0
2093 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2095 as_bad (_("`%%%s' not allowed with `%s%c'"),
2096 i
.op
[op
].regs
->reg_name
,
2101 /* Warn if the e prefix on a general reg is present. */
2102 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2103 && (i
.types
[op
] & Reg32
) != 0
2104 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2106 /* Prohibit these changes in the 64bit mode, since
2107 the lowering is more complicated. */
2108 if (flag_code
== CODE_64BIT
)
2109 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2110 i
.op
[op
].regs
->reg_name
,
2113 #if REGISTER_WARNINGS
2114 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2115 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2116 i
.op
[op
].regs
->reg_name
,
2121 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2122 /* Do nothing if the instruction is going to ignore the prefix. */
2127 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2129 i
.suffix
= stackop_size
;
2131 /* Make still unresolved immediate matches conform to size of immediate
2132 given in i.suffix. Note: overlap2 cannot be an immediate! */
2133 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2134 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2135 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2136 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2140 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2141 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2142 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2144 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2145 || overlap0
== (Imm16
| Imm32
)
2146 || overlap0
== (Imm16
| Imm32S
))
2149 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2151 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2152 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2153 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2155 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2159 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2160 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2161 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2162 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2166 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2167 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2168 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2170 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2171 || overlap1
== (Imm16
| Imm32
)
2172 || overlap1
== (Imm16
| Imm32S
))
2175 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2177 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2178 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2179 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2181 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2185 assert ((overlap2
& Imm
) == 0);
2187 i
.types
[0] = overlap0
;
2188 if (overlap0
& ImplicitRegister
)
2190 if (overlap0
& Imm1
)
2191 i
.imm_operands
= 0; /* kludge for shift insns. */
2193 i
.types
[1] = overlap1
;
2194 if (overlap1
& ImplicitRegister
)
2197 i
.types
[2] = overlap2
;
2198 if (overlap2
& ImplicitRegister
)
2201 /* Finalize opcode. First, we change the opcode based on the operand
2202 size given by i.suffix: We need not change things for byte insns. */
2204 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2206 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2210 /* For movzx and movsx, need to check the register type. */
2212 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2213 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2215 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2217 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2218 if (!add_prefix (prefix
))
2222 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2224 /* It's not a byte, select word/dword operation. */
2225 if (i
.tm
.opcode_modifier
& W
)
2227 if (i
.tm
.opcode_modifier
& ShortForm
)
2228 i
.tm
.base_opcode
|= 8;
2230 i
.tm
.base_opcode
|= 1;
2232 /* Now select between word & dword operations via the operand
2233 size prefix, except for instructions that will ignore this
2235 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2236 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2237 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2239 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2240 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2241 prefix
= ADDR_PREFIX_OPCODE
;
2243 if (! add_prefix (prefix
))
2247 /* Set mode64 for an operand. */
2248 if (i
.suffix
== QWORD_MNEM_SUFFIX
2249 && !(i
.tm
.opcode_modifier
& NoRex64
))
2252 if (flag_code
< CODE_64BIT
)
2254 as_bad (_("64bit operations available only in 64bit modes."));
2259 /* Size floating point instruction. */
2260 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2262 if (i
.tm
.opcode_modifier
& FloatMF
)
2263 i
.tm
.base_opcode
^= 4;
2267 if (i
.tm
.opcode_modifier
& ImmExt
)
2269 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2270 opcode suffix which is coded in the same place as an 8-bit
2271 immediate field would be. Here we fake an 8-bit immediate
2272 operand from the opcode suffix stored in tm.extension_opcode. */
2276 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2278 exp
= &im_expressions
[i
.imm_operands
++];
2279 i
.op
[i
.operands
].imms
= exp
;
2280 i
.types
[i
.operands
++] = Imm8
;
2281 exp
->X_op
= O_constant
;
2282 exp
->X_add_number
= i
.tm
.extension_opcode
;
2283 i
.tm
.extension_opcode
= None
;
2286 /* For insns with operands there are more diddles to do to the opcode. */
2289 /* Default segment register this instruction will use
2290 for memory accesses. 0 means unknown.
2291 This is only for optimizing out unnecessary segment overrides. */
2292 const seg_entry
*default_seg
= 0;
2294 /* The imul $imm, %reg instruction is converted into
2295 imul $imm, %reg, %reg, and the clr %reg instruction
2296 is converted into xor %reg, %reg. */
2297 if (i
.tm
.opcode_modifier
& regKludge
)
2299 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2300 /* Pretend we saw the extra register operand. */
2301 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2302 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2303 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2307 if (i
.tm
.opcode_modifier
& ShortForm
)
2309 /* The register or float register operand is in operand 0 or 1. */
2310 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2311 /* Register goes in low 3 bits of opcode. */
2312 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2313 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2315 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2317 /* Warn about some common errors, but press on regardless.
2318 The first case can be generated by gcc (<= 2.8.1). */
2319 if (i
.operands
== 2)
2321 /* Reversed arguments on faddp, fsubp, etc. */
2322 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2323 i
.op
[1].regs
->reg_name
,
2324 i
.op
[0].regs
->reg_name
);
2328 /* Extraneous `l' suffix on fp insn. */
2329 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2330 i
.op
[0].regs
->reg_name
);
2334 else if (i
.tm
.opcode_modifier
& Modrm
)
2336 /* The opcode is completed (modulo i.tm.extension_opcode which
2337 must be put into the modrm byte).
2338 Now, we make the modrm & index base bytes based on all the
2339 info we've collected. */
2341 /* i.reg_operands MUST be the number of real register operands;
2342 implicit registers do not count. */
2343 if (i
.reg_operands
== 2)
2345 unsigned int source
, dest
;
2346 source
= ((i
.types
[0]
2347 & (Reg
| RegMMX
| RegXMM
2349 | Control
| Debug
| Test
))
2354 /* One of the register operands will be encoded in the
2355 i.tm.reg field, the other in the combined i.tm.mode
2356 and i.tm.regmem fields. If no form of this
2357 instruction supports a memory destination operand,
2358 then we assume the source operand may sometimes be
2359 a memory operand and so we need to store the
2360 destination in the i.rm.reg field. */
2361 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2363 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2364 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2365 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2367 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2372 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2373 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2374 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2376 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2381 { /* If it's not 2 reg operands... */
2384 unsigned int fake_zero_displacement
= 0;
2385 unsigned int op
= ((i
.types
[0] & AnyMem
)
2387 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2394 if (! i
.disp_operands
)
2395 fake_zero_displacement
= 1;
2398 /* Operand is just <disp> */
2399 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2401 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2402 i
.types
[op
] &= ~Disp
;
2403 i
.types
[op
] |= Disp16
;
2405 else if (flag_code
!= CODE_64BIT
)
2407 i
.rm
.regmem
= NO_BASE_REGISTER
;
2408 i
.types
[op
] &= ~Disp
;
2409 i
.types
[op
] |= Disp32
;
2413 /* 64bit mode overwrites the 32bit
2414 absolute addressing by RIP relative
2415 addressing and absolute addressing
2416 is encoded by one of the redundant
2419 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2420 i
.sib
.base
= NO_BASE_REGISTER
;
2421 i
.sib
.index
= NO_INDEX_REGISTER
;
2422 i
.types
[op
] &= ~Disp
;
2423 i
.types
[op
] |= Disp32S
;
2426 else /* ! i.base_reg && i.index_reg */
2428 i
.sib
.index
= i
.index_reg
->reg_num
;
2429 i
.sib
.base
= NO_BASE_REGISTER
;
2430 i
.sib
.scale
= i
.log2_scale_factor
;
2431 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2432 i
.types
[op
] &= ~Disp
;
2433 if (flag_code
!= CODE_64BIT
)
2434 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2436 i
.types
[op
] |= Disp32S
;
2437 if (i
.index_reg
->reg_flags
& RegRex
)
2441 /* RIP addressing for 64bit mode. */
2442 else if (i
.base_reg
->reg_type
== BaseIndex
)
2444 i
.rm
.regmem
= NO_BASE_REGISTER
;
2445 i
.types
[op
] &= ~Disp
;
2446 i
.types
[op
] |= Disp32S
;
2447 i
.flags
[op
] = Operand_PCrel
;
2449 else if (i
.base_reg
->reg_type
& Reg16
)
2451 switch (i
.base_reg
->reg_num
)
2456 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2457 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2464 if ((i
.types
[op
] & Disp
) == 0)
2466 /* fake (%bp) into 0(%bp) */
2467 i
.types
[op
] |= Disp8
;
2468 fake_zero_displacement
= 1;
2471 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2472 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2474 default: /* (%si) -> 4 or (%di) -> 5 */
2475 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2477 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2479 else /* i.base_reg and 32/64 bit mode */
2481 if (flag_code
== CODE_64BIT
2482 && (i
.types
[op
] & Disp
))
2484 if (i
.types
[op
] & Disp8
)
2485 i
.types
[op
] = Disp8
| Disp32S
;
2487 i
.types
[op
] = Disp32S
;
2489 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2490 if (i
.base_reg
->reg_flags
& RegRex
)
2492 i
.sib
.base
= i
.base_reg
->reg_num
;
2493 /* x86-64 ignores REX prefix bit here to avoid
2494 decoder complications. */
2495 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2498 if (i
.disp_operands
== 0)
2500 fake_zero_displacement
= 1;
2501 i
.types
[op
] |= Disp8
;
2504 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2508 i
.sib
.scale
= i
.log2_scale_factor
;
2511 /* <disp>(%esp) becomes two byte modrm
2512 with no index register. We've already
2513 stored the code for esp in i.rm.regmem
2514 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2515 base register besides %esp will not use
2516 the extra modrm byte. */
2517 i
.sib
.index
= NO_INDEX_REGISTER
;
2518 #if ! SCALE1_WHEN_NO_INDEX
2519 /* Another case where we force the second
2521 if (i
.log2_scale_factor
)
2522 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2527 i
.sib
.index
= i
.index_reg
->reg_num
;
2528 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2529 if (i
.index_reg
->reg_flags
& RegRex
)
2532 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2535 if (fake_zero_displacement
)
2537 /* Fakes a zero displacement assuming that i.types[op]
2538 holds the correct displacement size. */
2541 assert (i
.op
[op
].disps
== 0);
2542 exp
= &disp_expressions
[i
.disp_operands
++];
2543 i
.op
[op
].disps
= exp
;
2544 exp
->X_op
= O_constant
;
2545 exp
->X_add_number
= 0;
2546 exp
->X_add_symbol
= (symbolS
*) 0;
2547 exp
->X_op_symbol
= (symbolS
*) 0;
2551 /* Fill in i.rm.reg or i.rm.regmem field with register
2552 operand (if any) based on i.tm.extension_opcode.
2553 Again, we must be careful to make sure that
2554 segment/control/debug/test/MMX registers are coded
2555 into the i.rm.reg field. */
2560 & (Reg
| RegMMX
| RegXMM
2562 | Control
| Debug
| Test
))
2565 & (Reg
| RegMMX
| RegXMM
2567 | Control
| Debug
| Test
))
2570 /* If there is an extension opcode to put here, the
2571 register number must be put into the regmem field. */
2572 if (i
.tm
.extension_opcode
!= None
)
2574 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2575 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2580 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2581 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2585 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2586 we must set it to 3 to indicate this is a register
2587 operand in the regmem field. */
2588 if (!i
.mem_operands
)
2592 /* Fill in i.rm.reg field with extension opcode (if any). */
2593 if (i
.tm
.extension_opcode
!= None
)
2594 i
.rm
.reg
= i
.tm
.extension_opcode
;
2597 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2599 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2600 && i
.op
[0].regs
->reg_num
== 1)
2602 as_bad (_("you can't `pop %%cs'"));
2605 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2606 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2609 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2613 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2615 /* For the string instructions that allow a segment override
2616 on one of their operands, the default segment is ds. */
2620 /* If a segment was explicitly specified,
2621 and the specified segment is not the default,
2622 use an opcode prefix to select it.
2623 If we never figured out what the default segment is,
2624 then default_seg will be zero at this point,
2625 and the specified segment prefix will always be used. */
2626 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2628 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2632 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2634 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2635 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2639 /* Handle conversion of 'int $3' --> special int3 insn. */
2640 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2642 i
.tm
.base_opcode
= INT3_OPCODE
;
2646 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2647 && i
.op
[0].disps
->X_op
== O_constant
)
2649 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2650 the absolute address given by the constant. Since ix86 jumps and
2651 calls are pc relative, we need to generate a reloc. */
2652 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2653 i
.op
[0].disps
->X_op
= O_symbol
;
2656 if (i
.tm
.opcode_modifier
& Rex64
)
2659 /* For 8bit registers we would need an empty rex prefix.
2660 Also in the case instruction is already having prefix,
2661 we need to convert old registers to new ones. */
2663 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2664 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2665 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2666 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2670 for (x
= 0; x
< 2; x
++)
2672 /* Look for 8bit operand that does use old registers. */
2673 if (i
.types
[x
] & Reg8
2674 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2676 /* In case it is "hi" register, give up. */
2677 if (i
.op
[x
].regs
->reg_num
> 3)
2678 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2679 i
.op
[x
].regs
->reg_name
);
2681 /* Otherwise it is equivalent to the extended register.
2682 Since the encoding don't change this is merely cosmetical
2683 cleanup for debug output. */
2685 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2690 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2692 | (i
.rex
.mode64
? 8 : 0)
2693 | (i
.rex
.extX
? 4 : 0)
2694 | (i
.rex
.extY
? 2 : 0)
2695 | (i
.rex
.extZ
? 1 : 0));
2697 /* We are ready to output the insn. */
2701 /* Tie dwarf2 debug info to the address at the start of the insn.
2702 We can't do this after the insn has been output as the current
2703 frag may have been closed off. eg. by frag_var. */
2704 dwarf2_emit_insn (0);
2707 if (i
.tm
.opcode_modifier
& Jump
)
2713 if (flag_code
== CODE_16BIT
)
2717 if (i
.prefix
[DATA_PREFIX
])
2723 /* Pentium4 branch hints. */
2724 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2725 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2730 if (i
.prefix
[REX_PREFIX
])
2736 if (i
.prefixes
!= 0 && !intel_syntax
)
2737 as_warn (_("skipping prefixes on this instruction"));
2739 /* It's always a symbol; End frag & setup for relax.
2740 Make sure there is enough room in this frag for the largest
2741 instruction we may generate in md_convert_frag. This is 2
2742 bytes for the opcode and room for the prefix and largest
2744 frag_grow (prefix
+ 2 + 4);
2745 /* Prefix and 1 opcode byte go in fr_fix. */
2746 p
= frag_more (prefix
+ 1);
2747 if (i
.prefix
[DATA_PREFIX
])
2748 *p
++ = DATA_PREFIX_OPCODE
;
2749 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2750 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2751 *p
++ = i
.prefix
[SEG_PREFIX
];
2752 if (i
.prefix
[REX_PREFIX
])
2753 *p
++ = i
.prefix
[REX_PREFIX
];
2754 *p
= i
.tm
.base_opcode
;
2755 /* 1 possible extra opcode + displacement go in var part.
2756 Pass reloc in fr_var. */
2757 frag_var (rs_machine_dependent
,
2760 ((unsigned char) *p
== JUMP_PC_RELATIVE
2761 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2762 : ((cpu_arch_flags
& Cpu386
) != 0
2763 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2764 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2765 i
.op
[0].disps
->X_add_symbol
,
2766 i
.op
[0].disps
->X_add_number
,
2769 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2773 if (i
.tm
.opcode_modifier
& JumpByte
)
2775 /* This is a loop or jecxz type instruction. */
2777 if (i
.prefix
[ADDR_PREFIX
])
2779 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2782 /* Pentium4 branch hints. */
2783 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2784 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2786 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2795 if (flag_code
== CODE_16BIT
)
2798 if (i
.prefix
[DATA_PREFIX
])
2800 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2810 if (i
.prefix
[REX_PREFIX
])
2812 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2816 if (i
.prefixes
!= 0 && !intel_syntax
)
2817 as_warn (_("skipping prefixes on this instruction"));
2819 p
= frag_more (1 + size
);
2820 *p
++ = i
.tm
.base_opcode
;
2822 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2823 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2825 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2832 if (flag_code
== CODE_16BIT
)
2836 if (i
.prefix
[DATA_PREFIX
])
2842 if (i
.prefix
[REX_PREFIX
])
2852 if (i
.prefixes
!= 0 && !intel_syntax
)
2853 as_warn (_("skipping prefixes on this instruction"));
2855 /* 1 opcode; 2 segment; offset */
2856 p
= frag_more (prefix
+ 1 + 2 + size
);
2858 if (i
.prefix
[DATA_PREFIX
])
2859 *p
++ = DATA_PREFIX_OPCODE
;
2861 if (i
.prefix
[REX_PREFIX
])
2862 *p
++ = i
.prefix
[REX_PREFIX
];
2864 *p
++ = i
.tm
.base_opcode
;
2865 if (i
.op
[1].imms
->X_op
== O_constant
)
2867 offsetT n
= i
.op
[1].imms
->X_add_number
;
2870 && !fits_in_unsigned_word (n
)
2871 && !fits_in_signed_word (n
))
2873 as_bad (_("16-bit jump out of range"));
2876 md_number_to_chars (p
, n
, size
);
2879 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2880 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2881 if (i
.op
[0].imms
->X_op
!= O_constant
)
2882 as_bad (_("can't handle non absolute segment in `%s'"),
2884 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2888 /* Output normal instructions here. */
2891 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2892 byte for the SSE instructions to specify prefix they require. */
2893 if (i
.tm
.base_opcode
& 0xff0000)
2894 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2896 /* The prefix bytes. */
2898 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2904 md_number_to_chars (p
, (valueT
) *q
, 1);
2908 /* Now the opcode; be careful about word order here! */
2909 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2911 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2916 /* Put out high byte first: can't use md_number_to_chars! */
2917 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2918 *p
= i
.tm
.base_opcode
& 0xff;
2921 /* Now the modrm byte and sib byte (if present). */
2922 if (i
.tm
.opcode_modifier
& Modrm
)
2925 md_number_to_chars (p
,
2926 (valueT
) (i
.rm
.regmem
<< 0
2930 /* If i.rm.regmem == ESP (4)
2931 && i.rm.mode != (Register mode)
2933 ==> need second modrm byte. */
2934 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2936 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2939 md_number_to_chars (p
,
2940 (valueT
) (i
.sib
.base
<< 0
2942 | i
.sib
.scale
<< 6),
2947 if (i
.disp_operands
)
2949 register unsigned int n
;
2951 for (n
= 0; n
< i
.operands
; n
++)
2953 if (i
.types
[n
] & Disp
)
2955 if (i
.op
[n
].disps
->X_op
== O_constant
)
2961 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2964 if (i
.types
[n
] & Disp8
)
2966 if (i
.types
[n
] & Disp64
)
2969 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2971 p
= frag_more (size
);
2972 md_number_to_chars (p
, val
, size
);
2978 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2980 /* The PC relative address is computed relative
2981 to the instruction boundary, so in case immediate
2982 fields follows, we need to adjust the value. */
2983 if (pcrel
&& i
.imm_operands
)
2986 register unsigned int n1
;
2988 for (n1
= 0; n1
< i
.operands
; n1
++)
2989 if (i
.types
[n1
] & Imm
)
2991 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2994 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2996 if (i
.types
[n1
] & Imm64
)
3001 /* We should find the immediate. */
3002 if (n1
== i
.operands
)
3004 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3007 if (i
.types
[n
] & Disp32S
)
3010 if (i
.types
[n
] & (Disp16
| Disp64
))
3013 if (i
.types
[n
] & Disp64
)
3017 p
= frag_more (size
);
3018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3019 i
.op
[n
].disps
, pcrel
,
3020 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3026 /* Output immediate. */
3029 register unsigned int n
;
3031 for (n
= 0; n
< i
.operands
; n
++)
3033 if (i
.types
[n
] & Imm
)
3035 if (i
.op
[n
].imms
->X_op
== O_constant
)
3041 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3044 if (i
.types
[n
] & (Imm8
| Imm8S
))
3046 else if (i
.types
[n
] & Imm64
)
3049 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3051 p
= frag_more (size
);
3052 md_number_to_chars (p
, val
, size
);
3056 /* Not absolute_section.
3057 Need a 32-bit fixup (don't support 8bit
3058 non-absolute imms). Try to support other
3060 RELOC_ENUM reloc_type
;
3064 if ((i
.types
[n
] & (Imm32S
))
3065 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3067 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3070 if (i
.types
[n
] & (Imm8
| Imm8S
))
3072 if (i
.types
[n
] & Imm64
)
3076 p
= frag_more (size
);
3077 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3078 #ifdef BFD_ASSEMBLER
3079 if (reloc_type
== BFD_RELOC_32
3081 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3082 && (i
.op
[n
].imms
->X_op
== O_symbol
3083 || (i
.op
[n
].imms
->X_op
== O_add
3084 && ((symbol_get_value_expression
3085 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3088 /* We don't support dynamic linking on x86-64 yet. */
3089 if (flag_code
== CODE_64BIT
)
3091 reloc_type
= BFD_RELOC_386_GOTPC
;
3092 i
.op
[n
].imms
->X_add_number
+= 3;
3095 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3096 i
.op
[n
].imms
, 0, reloc_type
);
3108 #endif /* DEBUG386 */
3113 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3115 /* Parse operands of the form
3116 <symbol>@GOTOFF+<nnn>
3117 and similar .plt or .got references.
3119 If we find one, set up the correct relocation in RELOC and copy the
3120 input string, minus the `@GOTOFF' into a malloc'd buffer for
3121 parsing by the calling routine. Return this buffer, and if ADJUST
3122 is non-null set it to the length of the string we removed from the
3123 input line. Otherwise return NULL. */
3125 lex_got (reloc
, adjust
)
3129 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3130 static const struct {
3132 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3134 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3135 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3136 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3137 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3142 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3143 if (is_end_of_line
[(unsigned char) *cp
])
3146 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3150 len
= strlen (gotrel
[j
].str
);
3151 if (strncmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3153 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3158 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3160 if (GOT_symbol
== NULL
)
3161 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3163 /* Replace the relocation token with ' ', so that
3164 errors like foo@GOTOFF1 will be detected. */
3165 first
= cp
- input_line_pointer
;
3166 tmpbuf
= xmalloc (strlen (input_line_pointer
));
3167 memcpy (tmpbuf
, input_line_pointer
, first
);
3168 tmpbuf
[first
] = ' ';
3169 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3175 as_bad (_("@%s reloc is not supported in %s bit mode"),
3176 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3181 /* Might be a symbol version string. Don't as_bad here. */
3185 /* x86_cons_fix_new is called via the expression parsing code when a
3186 reloc is needed. We use this hook to get the correct .got reloc. */
3187 static RELOC_ENUM got_reloc
= NO_RELOC
;
3190 x86_cons_fix_new (frag
, off
, len
, exp
)
3196 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3197 got_reloc
= NO_RELOC
;
3198 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3202 x86_cons (exp
, size
)
3208 /* Handle @GOTOFF and the like in an expression. */
3210 char *gotfree_input_line
;
3213 save
= input_line_pointer
;
3214 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3215 if (gotfree_input_line
)
3216 input_line_pointer
= gotfree_input_line
;
3220 if (gotfree_input_line
)
3222 /* expression () has merrily parsed up to the end of line,
3223 or a comma - in the wrong buffer. Transfer how far
3224 input_line_pointer has moved to the right buffer. */
3225 input_line_pointer
= (save
3226 + (input_line_pointer
- gotfree_input_line
)
3228 free (gotfree_input_line
);
3236 static int i386_immediate
PARAMS ((char *));
3239 i386_immediate (imm_start
)
3242 char *save_input_line_pointer
;
3244 char *gotfree_input_line
;
3249 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3251 as_bad (_("only 1 or 2 immediate operands are allowed"));
3255 exp
= &im_expressions
[i
.imm_operands
++];
3256 i
.op
[this_operand
].imms
= exp
;
3258 if (is_space_char (*imm_start
))
3261 save_input_line_pointer
= input_line_pointer
;
3262 input_line_pointer
= imm_start
;
3265 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3266 if (gotfree_input_line
)
3267 input_line_pointer
= gotfree_input_line
;
3270 exp_seg
= expression (exp
);
3273 if (*input_line_pointer
)
3274 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3276 input_line_pointer
= save_input_line_pointer
;
3278 if (gotfree_input_line
)
3279 free (gotfree_input_line
);
3282 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3284 /* Missing or bad expr becomes absolute 0. */
3285 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3287 exp
->X_op
= O_constant
;
3288 exp
->X_add_number
= 0;
3289 exp
->X_add_symbol
= (symbolS
*) 0;
3290 exp
->X_op_symbol
= (symbolS
*) 0;
3292 else if (exp
->X_op
== O_constant
)
3294 /* Size it properly later. */
3295 i
.types
[this_operand
] |= Imm64
;
3296 /* If BFD64, sign extend val. */
3297 if (!use_rela_relocations
)
3298 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3299 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3301 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3303 #ifdef BFD_ASSEMBLER
3304 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3306 && exp_seg
!= text_section
3307 && exp_seg
!= data_section
3308 && exp_seg
!= bss_section
3309 && exp_seg
!= undefined_section
3310 #ifdef BFD_ASSEMBLER
3311 && !bfd_is_com_section (exp_seg
)
3315 #ifdef BFD_ASSEMBLER
3316 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3318 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3325 /* This is an address. The size of the address will be
3326 determined later, depending on destination register,
3327 suffix, or the default for the section. */
3328 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3334 static char *i386_scale
PARAMS ((char *));
3341 char *save
= input_line_pointer
;
3343 input_line_pointer
= scale
;
3344 val
= get_absolute_expression ();
3350 i
.log2_scale_factor
= 0;
3353 i
.log2_scale_factor
= 1;
3356 i
.log2_scale_factor
= 2;
3359 i
.log2_scale_factor
= 3;
3362 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3364 input_line_pointer
= save
;
3367 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3369 as_warn (_("scale factor of %d without an index register"),
3370 1 << i
.log2_scale_factor
);
3371 #if SCALE1_WHEN_NO_INDEX
3372 i
.log2_scale_factor
= 0;
3375 scale
= input_line_pointer
;
3376 input_line_pointer
= save
;
3380 static int i386_displacement
PARAMS ((char *, char *));
3383 i386_displacement (disp_start
, disp_end
)
3387 register expressionS
*exp
;
3389 char *save_input_line_pointer
;
3391 char *gotfree_input_line
;
3393 int bigdisp
= Disp32
;
3395 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3397 if (flag_code
== CODE_64BIT
)
3399 i
.types
[this_operand
] |= bigdisp
;
3401 exp
= &disp_expressions
[i
.disp_operands
];
3402 i
.op
[this_operand
].disps
= exp
;
3404 save_input_line_pointer
= input_line_pointer
;
3405 input_line_pointer
= disp_start
;
3406 END_STRING_AND_SAVE (disp_end
);
3408 #ifndef GCC_ASM_O_HACK
3409 #define GCC_ASM_O_HACK 0
3412 END_STRING_AND_SAVE (disp_end
+ 1);
3413 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3414 && displacement_string_end
[-1] == '+')
3416 /* This hack is to avoid a warning when using the "o"
3417 constraint within gcc asm statements.
3420 #define _set_tssldt_desc(n,addr,limit,type) \
3421 __asm__ __volatile__ ( \
3423 "movw %w1,2+%0\n\t" \
3425 "movb %b1,4+%0\n\t" \
3426 "movb %4,5+%0\n\t" \
3427 "movb $0,6+%0\n\t" \
3428 "movb %h1,7+%0\n\t" \
3430 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3432 This works great except that the output assembler ends
3433 up looking a bit weird if it turns out that there is
3434 no offset. You end up producing code that looks like:
3447 So here we provide the missing zero. */
3449 *displacement_string_end
= '0';
3453 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3454 if (gotfree_input_line
)
3455 input_line_pointer
= gotfree_input_line
;
3458 exp_seg
= expression (exp
);
3461 if (*input_line_pointer
)
3462 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3464 RESTORE_END_STRING (disp_end
+ 1);
3466 RESTORE_END_STRING (disp_end
);
3467 input_line_pointer
= save_input_line_pointer
;
3469 if (gotfree_input_line
)
3470 free (gotfree_input_line
);
3473 #ifdef BFD_ASSEMBLER
3474 /* We do this to make sure that the section symbol is in
3475 the symbol table. We will ultimately change the relocation
3476 to be relative to the beginning of the section. */
3477 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3478 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3480 if (exp
->X_op
!= O_symbol
)
3482 as_bad (_("bad expression used with @%s"),
3483 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3489 if (S_IS_LOCAL (exp
->X_add_symbol
)
3490 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3491 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3492 exp
->X_op
= O_subtract
;
3493 exp
->X_op_symbol
= GOT_symbol
;
3494 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3495 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3497 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3501 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3503 /* Missing or bad expr becomes absolute 0. */
3504 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3506 exp
->X_op
= O_constant
;
3507 exp
->X_add_number
= 0;
3508 exp
->X_add_symbol
= (symbolS
*) 0;
3509 exp
->X_op_symbol
= (symbolS
*) 0;
3512 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3513 if (exp
->X_op
!= O_constant
3514 #ifdef BFD_ASSEMBLER
3515 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3517 && exp_seg
!= text_section
3518 && exp_seg
!= data_section
3519 && exp_seg
!= bss_section
3520 && exp_seg
!= undefined_section
)
3522 #ifdef BFD_ASSEMBLER
3523 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3525 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3530 else if (flag_code
== CODE_64BIT
)
3531 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3535 static int i386_index_check
PARAMS ((const char *));
3537 /* Make sure the memory operand we've been dealt is valid.
3538 Return 1 on success, 0 on a failure. */
3541 i386_index_check (operand_string
)
3542 const char *operand_string
;
3545 #if INFER_ADDR_PREFIX
3551 if (flag_code
== CODE_64BIT
)
3555 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3556 && (i
.base_reg
->reg_type
!= BaseIndex
3559 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3560 != (Reg64
|BaseIndex
))))
3565 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3569 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3570 != (Reg16
|BaseIndex
)))
3572 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3573 != (Reg16
|BaseIndex
))
3575 && i
.base_reg
->reg_num
< 6
3576 && i
.index_reg
->reg_num
>= 6
3577 && i
.log2_scale_factor
== 0))))
3584 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3586 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3587 != (Reg32
|BaseIndex
))))
3593 #if INFER_ADDR_PREFIX
3594 if (flag_code
!= CODE_64BIT
3595 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3597 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3599 /* Change the size of any displacement too. At most one of
3600 Disp16 or Disp32 is set.
3601 FIXME. There doesn't seem to be any real need for separate
3602 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3603 Removing them would probably clean up the code quite a lot. */
3604 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3605 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3610 as_bad (_("`%s' is not a valid base/index expression"),
3614 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3616 flag_code_names
[flag_code
]);
3622 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3626 i386_operand (operand_string
)
3627 char *operand_string
;
3631 char *op_string
= operand_string
;
3633 if (is_space_char (*op_string
))
3636 /* We check for an absolute prefix (differentiating,
3637 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3638 if (*op_string
== ABSOLUTE_PREFIX
)
3641 if (is_space_char (*op_string
))
3643 i
.types
[this_operand
] |= JumpAbsolute
;
3646 /* Check if operand is a register. */
3647 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3648 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3650 /* Check for a segment override by searching for ':' after a
3651 segment register. */
3653 if (is_space_char (*op_string
))
3655 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3660 i
.seg
[i
.mem_operands
] = &es
;
3663 i
.seg
[i
.mem_operands
] = &cs
;
3666 i
.seg
[i
.mem_operands
] = &ss
;
3669 i
.seg
[i
.mem_operands
] = &ds
;
3672 i
.seg
[i
.mem_operands
] = &fs
;
3675 i
.seg
[i
.mem_operands
] = &gs
;
3679 /* Skip the ':' and whitespace. */
3681 if (is_space_char (*op_string
))
3684 if (!is_digit_char (*op_string
)
3685 && !is_identifier_char (*op_string
)
3686 && *op_string
!= '('
3687 && *op_string
!= ABSOLUTE_PREFIX
)
3689 as_bad (_("bad memory operand `%s'"), op_string
);
3692 /* Handle case of %es:*foo. */
3693 if (*op_string
== ABSOLUTE_PREFIX
)
3696 if (is_space_char (*op_string
))
3698 i
.types
[this_operand
] |= JumpAbsolute
;
3700 goto do_memory_reference
;
3704 as_bad (_("junk `%s' after register"), op_string
);
3707 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3708 i
.op
[this_operand
].regs
= r
;
3711 else if (*op_string
== REGISTER_PREFIX
)
3713 as_bad (_("bad register name `%s'"), op_string
);
3716 else if (*op_string
== IMMEDIATE_PREFIX
)
3719 if (i
.types
[this_operand
] & JumpAbsolute
)
3721 as_bad (_("immediate operand illegal with absolute jump"));
3724 if (!i386_immediate (op_string
))
3727 else if (is_digit_char (*op_string
)
3728 || is_identifier_char (*op_string
)
3729 || *op_string
== '(')
3731 /* This is a memory reference of some sort. */
3734 /* Start and end of displacement string expression (if found). */
3735 char *displacement_string_start
;
3736 char *displacement_string_end
;
3738 do_memory_reference
:
3739 if ((i
.mem_operands
== 1
3740 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3741 || i
.mem_operands
== 2)
3743 as_bad (_("too many memory references for `%s'"),
3744 current_templates
->start
->name
);
3748 /* Check for base index form. We detect the base index form by
3749 looking for an ')' at the end of the operand, searching
3750 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3752 base_string
= op_string
+ strlen (op_string
);
3755 if (is_space_char (*base_string
))
3758 /* If we only have a displacement, set-up for it to be parsed later. */
3759 displacement_string_start
= op_string
;
3760 displacement_string_end
= base_string
+ 1;
3762 if (*base_string
== ')')
3765 unsigned int parens_balanced
= 1;
3766 /* We've already checked that the number of left & right ()'s are
3767 equal, so this loop will not be infinite. */
3771 if (*base_string
== ')')
3773 if (*base_string
== '(')
3776 while (parens_balanced
);
3778 temp_string
= base_string
;
3780 /* Skip past '(' and whitespace. */
3782 if (is_space_char (*base_string
))
3785 if (*base_string
== ','
3786 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3787 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3789 displacement_string_end
= temp_string
;
3791 i
.types
[this_operand
] |= BaseIndex
;
3795 base_string
= end_op
;
3796 if (is_space_char (*base_string
))
3800 /* There may be an index reg or scale factor here. */
3801 if (*base_string
== ',')
3804 if (is_space_char (*base_string
))
3807 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3808 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3810 base_string
= end_op
;
3811 if (is_space_char (*base_string
))
3813 if (*base_string
== ',')
3816 if (is_space_char (*base_string
))
3819 else if (*base_string
!= ')')
3821 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3826 else if (*base_string
== REGISTER_PREFIX
)
3828 as_bad (_("bad register name `%s'"), base_string
);
3832 /* Check for scale factor. */
3833 if (*base_string
!= ')')
3835 char *end_scale
= i386_scale (base_string
);
3840 base_string
= end_scale
;
3841 if (is_space_char (*base_string
))
3843 if (*base_string
!= ')')
3845 as_bad (_("expecting `)' after scale factor in `%s'"),
3850 else if (!i
.index_reg
)
3852 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3857 else if (*base_string
!= ')')
3859 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3864 else if (*base_string
== REGISTER_PREFIX
)
3866 as_bad (_("bad register name `%s'"), base_string
);
3871 /* If there's an expression beginning the operand, parse it,
3872 assuming displacement_string_start and
3873 displacement_string_end are meaningful. */
3874 if (displacement_string_start
!= displacement_string_end
)
3876 if (!i386_displacement (displacement_string_start
,
3877 displacement_string_end
))
3881 /* Special case for (%dx) while doing input/output op. */
3883 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3885 && i
.log2_scale_factor
== 0
3886 && i
.seg
[i
.mem_operands
] == 0
3887 && (i
.types
[this_operand
] & Disp
) == 0)
3889 i
.types
[this_operand
] = InOutPortReg
;
3893 if (i386_index_check (operand_string
) == 0)
3899 /* It's not a memory operand; argh! */
3900 as_bad (_("invalid char %s beginning operand %d `%s'"),
3901 output_invalid (*op_string
),
3906 return 1; /* Normal return. */
3909 /* md_estimate_size_before_relax()
3911 Called just before relax() for rs_machine_dependent frags. The x86
3912 assembler uses these frags to handle variable size jump
3915 Any symbol that is now undefined will not become defined.
3916 Return the correct fr_subtype in the frag.
3917 Return the initial "guess for variable size of frag" to caller.
3918 The guess is actually the growth beyond the fixed part. Whatever
3919 we do to grow the fixed or variable part contributes to our
3923 md_estimate_size_before_relax (fragP
, segment
)
3924 register fragS
*fragP
;
3925 register segT segment
;
3927 /* We've already got fragP->fr_subtype right; all we have to do is
3928 check for un-relaxable symbols. On an ELF system, we can't relax
3929 an externally visible symbol, because it may be overridden by a
3931 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3933 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3934 || S_IS_WEAK (fragP
->fr_symbol
)
3938 /* Symbol is undefined in this segment, or we need to keep a
3939 reloc so that weak symbols can be overridden. */
3940 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3941 RELOC_ENUM reloc_type
;
3942 unsigned char *opcode
;
3945 if (fragP
->fr_var
!= NO_RELOC
)
3946 reloc_type
= fragP
->fr_var
;
3948 reloc_type
= BFD_RELOC_16_PCREL
;
3950 reloc_type
= BFD_RELOC_32_PCREL
;
3952 old_fr_fix
= fragP
->fr_fix
;
3953 opcode
= (unsigned char *) fragP
->fr_opcode
;
3955 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3958 /* Make jmp (0xeb) a (d)word displacement jump. */
3960 fragP
->fr_fix
+= size
;
3961 fix_new (fragP
, old_fr_fix
, size
,
3963 fragP
->fr_offset
, 1,
3968 if (no_cond_jump_promotion
)
3973 /* Negate the condition, and branch past an
3974 unconditional jump. */
3977 /* Insert an unconditional jump. */
3979 /* We added two extra opcode bytes, and have a two byte
3981 fragP
->fr_fix
+= 2 + 2;
3982 fix_new (fragP
, old_fr_fix
+ 2, 2,
3984 fragP
->fr_offset
, 1,
3991 if (no_cond_jump_promotion
)
3994 /* This changes the byte-displacement jump 0x7N
3995 to the (d)word-displacement jump 0x0f,0x8N. */
3996 opcode
[1] = opcode
[0] + 0x10;
3997 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3998 /* We've added an opcode byte. */
3999 fragP
->fr_fix
+= 1 + size
;
4000 fix_new (fragP
, old_fr_fix
+ 1, size
,
4002 fragP
->fr_offset
, 1,
4007 BAD_CASE (fragP
->fr_subtype
);
4011 return fragP
->fr_fix
- old_fr_fix
;
4015 /* Guess size depending on current relax state. Initially the relax
4016 state will correspond to a short jump and we return 1, because
4017 the variable part of the frag (the branch offset) is one byte
4018 long. However, we can relax a section more than once and in that
4019 case we must either set fr_subtype back to the unrelaxed state,
4020 or return the value for the appropriate branch. */
4021 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4024 /* Called after relax() is finished.
4026 In: Address of frag.
4027 fr_type == rs_machine_dependent.
4028 fr_subtype is what the address relaxed to.
4030 Out: Any fixSs and constants are set up.
4031 Caller will turn frag into a ".space 0". */
4033 #ifndef BFD_ASSEMBLER
4035 md_convert_frag (headers
, sec
, fragP
)
4036 object_headers
*headers ATTRIBUTE_UNUSED
;
4037 segT sec ATTRIBUTE_UNUSED
;
4038 register fragS
*fragP
;
4041 md_convert_frag (abfd
, sec
, fragP
)
4042 bfd
*abfd ATTRIBUTE_UNUSED
;
4043 segT sec ATTRIBUTE_UNUSED
;
4044 register fragS
*fragP
;
4047 register unsigned char *opcode
;
4048 unsigned char *where_to_put_displacement
= NULL
;
4049 offsetT target_address
;
4050 offsetT opcode_address
;
4051 unsigned int extension
= 0;
4052 offsetT displacement_from_opcode_start
;
4054 opcode
= (unsigned char *) fragP
->fr_opcode
;
4056 /* Address we want to reach in file space. */
4057 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4058 #ifdef BFD_ASSEMBLER
4059 /* Not needed otherwise? */
4061 /* Local symbols which have already been resolved have a NULL frag. */
4062 fragS
*sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4064 target_address
+= sym_frag
->fr_address
;
4068 /* Address opcode resides at in file space. */
4069 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4071 /* Displacement from opcode start to fill into instruction. */
4072 displacement_from_opcode_start
= target_address
- opcode_address
;
4074 if ((fragP
->fr_subtype
& BIG
) == 0)
4076 /* Don't have to change opcode. */
4077 extension
= 1; /* 1 opcode + 1 displacement */
4078 where_to_put_displacement
= &opcode
[1];
4082 if (no_cond_jump_promotion
4083 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4084 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4086 switch (fragP
->fr_subtype
)
4088 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4089 extension
= 4; /* 1 opcode + 4 displacement */
4091 where_to_put_displacement
= &opcode
[1];
4094 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4095 extension
= 2; /* 1 opcode + 2 displacement */
4097 where_to_put_displacement
= &opcode
[1];
4100 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4101 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4102 extension
= 5; /* 2 opcode + 4 displacement */
4103 opcode
[1] = opcode
[0] + 0x10;
4104 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4105 where_to_put_displacement
= &opcode
[2];
4108 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4109 extension
= 3; /* 2 opcode + 2 displacement */
4110 opcode
[1] = opcode
[0] + 0x10;
4111 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4112 where_to_put_displacement
= &opcode
[2];
4115 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4120 where_to_put_displacement
= &opcode
[3];
4124 BAD_CASE (fragP
->fr_subtype
);
4129 /* Now put displacement after opcode. */
4130 md_number_to_chars ((char *) where_to_put_displacement
,
4131 (valueT
) (displacement_from_opcode_start
- extension
),
4132 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4133 fragP
->fr_fix
+= extension
;
4136 /* Size of byte displacement jmp. */
4137 int md_short_jump_size
= 2;
4139 /* Size of dword displacement jmp. */
4140 int md_long_jump_size
= 5;
4142 /* Size of relocation record. */
4143 const int md_reloc_size
= 8;
4146 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4148 addressT from_addr
, to_addr
;
4149 fragS
*frag ATTRIBUTE_UNUSED
;
4150 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4154 offset
= to_addr
- (from_addr
+ 2);
4155 /* Opcode for byte-disp jump. */
4156 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4157 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4161 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4163 addressT from_addr
, to_addr
;
4164 fragS
*frag ATTRIBUTE_UNUSED
;
4165 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4169 offset
= to_addr
- (from_addr
+ 5);
4170 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4171 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4174 /* Apply a fixup (fixS) to segment data, once it has been determined
4175 by our caller that we have all the info we need to fix it up.
4177 On the 386, immediates, displacements, and data pointers are all in
4178 the same (little-endian) format, so we don't need to care about which
4182 md_apply_fix3 (fixP
, valp
, seg
)
4183 /* The fix we're to put in. */
4186 /* Pointer to the value of the bits. */
4189 /* Segment fix is from. */
4190 segT seg ATTRIBUTE_UNUSED
;
4192 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4193 valueT value
= *valp
;
4195 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4198 switch (fixP
->fx_r_type
)
4204 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4207 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4210 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4215 /* This is a hack. There should be a better way to handle this.
4216 This covers for the fact that bfd_install_relocation will
4217 subtract the current location (for partial_inplace, PC relative
4218 relocations); see more below. */
4219 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4220 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4221 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4222 && fixP
->fx_addsy
&& !use_rela_relocations
)
4225 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4227 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4230 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4233 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4235 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4238 || (symbol_section_p (fixP
->fx_addsy
)
4239 && fseg
!= absolute_section
))
4240 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4241 && ! S_IS_WEAK (fixP
->fx_addsy
)
4242 && S_IS_DEFINED (fixP
->fx_addsy
)
4243 && ! S_IS_COMMON (fixP
->fx_addsy
))
4245 /* Yes, we add the values in twice. This is because
4246 bfd_perform_relocation subtracts them out again. I think
4247 bfd_perform_relocation is broken, but I don't dare change
4249 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4253 #if defined (OBJ_COFF) && defined (TE_PE)
4254 /* For some reason, the PE format does not store a section
4255 address offset for a PC relative symbol. */
4256 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4257 value
+= md_pcrel_from (fixP
);
4261 /* Fix a few things - the dynamic linker expects certain values here,
4262 and we must not dissappoint it. */
4263 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4264 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4266 switch (fixP
->fx_r_type
)
4268 case BFD_RELOC_386_PLT32
:
4269 case BFD_RELOC_X86_64_PLT32
:
4270 /* Make the jump instruction point to the address of the operand. At
4271 runtime we merely add the offset to the actual PLT entry. */
4274 case BFD_RELOC_386_GOTPC
:
4276 /* This is tough to explain. We end up with this one if we have
4277 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4278 * here is to obtain the absolute address of the GOT, and it is strongly
4279 * preferable from a performance point of view to avoid using a runtime
4280 * relocation for this. The actual sequence of instructions often look
4286 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4288 * The call and pop essentially return the absolute address of
4289 * the label .L66 and store it in %ebx. The linker itself will
4290 * ultimately change the first operand of the addl so that %ebx points to
4291 * the GOT, but to keep things simple, the .o file must have this operand
4292 * set so that it generates not the absolute address of .L66, but the
4293 * absolute address of itself. This allows the linker itself simply
4294 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4295 * added in, and the addend of the relocation is stored in the operand
4296 * field for the instruction itself.
4298 * Our job here is to fix the operand so that it would add the correct
4299 * offset so that %ebx would point to itself. The thing that is tricky is
4300 * that .-.L66 will point to the beginning of the instruction, so we need
4301 * to further modify the operand so that it will point to itself.
4302 * There are other cases where you have something like:
4304 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4306 * and here no correction would be required. Internally in the assembler
4307 * we treat operands of this form as not being pcrel since the '.' is
4308 * explicitly mentioned, and I wonder whether it would simplify matters
4309 * to do it this way. Who knows. In earlier versions of the PIC patches,
4310 * the pcrel_adjust field was used to store the correction, but since the
4311 * expression is not pcrel, I felt it would be confusing to do it this
4316 case BFD_RELOC_386_GOT32
:
4317 case BFD_RELOC_X86_64_GOT32
:
4318 value
= 0; /* Fully resolved at runtime. No addend. */
4320 case BFD_RELOC_386_GOTOFF
:
4321 case BFD_RELOC_X86_64_GOTPCREL
:
4324 case BFD_RELOC_VTABLE_INHERIT
:
4325 case BFD_RELOC_VTABLE_ENTRY
:
4332 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4334 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4336 #ifndef BFD_ASSEMBLER
4337 md_number_to_chars (p
, value
, fixP
->fx_size
);
4339 /* Are we finished with this relocation now? */
4340 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4342 else if (use_rela_relocations
)
4344 fixP
->fx_no_overflow
= 1;
4347 md_number_to_chars (p
, value
, fixP
->fx_size
);
4353 #define MAX_LITTLENUMS 6
4355 /* Turn the string pointed to by litP into a floating point constant
4356 of type TYPE, and emit the appropriate bytes. The number of
4357 LITTLENUMS emitted is stored in *SIZEP. An error message is
4358 returned, or NULL on OK. */
4361 md_atof (type
, litP
, sizeP
)
4367 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4368 LITTLENUM_TYPE
*wordP
;
4390 return _("Bad call to md_atof ()");
4392 t
= atof_ieee (input_line_pointer
, type
, words
);
4394 input_line_pointer
= t
;
4396 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4397 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4398 the bigendian 386. */
4399 for (wordP
= words
+ prec
- 1; prec
--;)
4401 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4402 litP
+= sizeof (LITTLENUM_TYPE
);
4407 char output_invalid_buf
[8];
4414 sprintf (output_invalid_buf
, "'%c'", c
);
4416 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4417 return output_invalid_buf
;
4420 /* REG_STRING starts *before* REGISTER_PREFIX. */
4422 static const reg_entry
*
4423 parse_register (reg_string
, end_op
)
4427 char *s
= reg_string
;
4429 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4432 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4433 if (*s
== REGISTER_PREFIX
)
4436 if (is_space_char (*s
))
4440 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4442 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4443 return (const reg_entry
*) NULL
;
4447 /* For naked regs, make sure that we are not dealing with an identifier.
4448 This prevents confusing an identifier like `eax_var' with register
4450 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4451 return (const reg_entry
*) NULL
;
4455 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4457 /* Handle floating point regs, allowing spaces in the (i) part. */
4458 if (r
== i386_regtab
/* %st is first entry of table */)
4460 if (is_space_char (*s
))
4465 if (is_space_char (*s
))
4467 if (*s
>= '0' && *s
<= '7')
4469 r
= &i386_float_regtab
[*s
- '0'];
4471 if (is_space_char (*s
))
4479 /* We have "%st(" then garbage. */
4480 return (const reg_entry
*) NULL
;
4487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4488 const char *md_shortopts
= "kVQ:sq";
4490 const char *md_shortopts
= "q";
4493 struct option md_longopts
[] = {
4494 #define OPTION_32 (OPTION_MD_BASE + 0)
4495 {"32", no_argument
, NULL
, OPTION_32
},
4496 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4497 #define OPTION_64 (OPTION_MD_BASE + 1)
4498 {"64", no_argument
, NULL
, OPTION_64
},
4500 {NULL
, no_argument
, NULL
, 0}
4502 size_t md_longopts_size
= sizeof (md_longopts
);
4505 md_parse_option (c
, arg
)
4507 char *arg ATTRIBUTE_UNUSED
;
4515 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4516 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4517 should be emitted or not. FIXME: Not implemented. */
4521 /* -V: SVR4 argument to print version ID. */
4523 print_version_id ();
4526 /* -k: Ignore for FreeBSD compatibility. */
4531 /* -s: On i386 Solaris, this tells the native assembler to use
4532 .stab instead of .stab.excl. We always use .stab anyhow. */
4537 const char **list
, **l
;
4539 list
= bfd_target_list ();
4540 for (l
= list
; *l
!= NULL
; l
++)
4541 if (strcmp (*l
, "elf64-x86-64") == 0)
4543 default_arch
= "x86_64";
4547 as_fatal (_("No compiled in support for x86_64"));
4554 default_arch
= "i386";
4564 md_show_usage (stream
)
4567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4568 fprintf (stream
, _("\
4570 -V print assembler version number\n\
4572 -q quieten some warnings\n\
4575 fprintf (stream
, _("\
4576 -q quieten some warnings\n"));
4580 #ifdef BFD_ASSEMBLER
4581 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4582 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4584 /* Pick the target format to use. */
4587 i386_target_format ()
4589 if (!strcmp (default_arch
, "x86_64"))
4590 set_code_flag (CODE_64BIT
);
4591 else if (!strcmp (default_arch
, "i386"))
4592 set_code_flag (CODE_32BIT
);
4594 as_fatal (_("Unknown architecture"));
4595 switch (OUTPUT_FLAVOR
)
4597 #ifdef OBJ_MAYBE_AOUT
4598 case bfd_target_aout_flavour
:
4599 return AOUT_TARGET_FORMAT
;
4601 #ifdef OBJ_MAYBE_COFF
4602 case bfd_target_coff_flavour
:
4605 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4606 case bfd_target_elf_flavour
:
4608 if (flag_code
== CODE_64BIT
)
4609 use_rela_relocations
= 1;
4610 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4619 #endif /* OBJ_MAYBE_ more than one */
4620 #endif /* BFD_ASSEMBLER */
4623 md_undefined_symbol (name
)
4626 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4627 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4628 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4629 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4633 if (symbol_find (name
))
4634 as_bad (_("GOT already in symbol table"));
4635 GOT_symbol
= symbol_new (name
, undefined_section
,
4636 (valueT
) 0, &zero_address_frag
);
4643 /* Round up a section size to the appropriate boundary. */
4646 md_section_align (segment
, size
)
4647 segT segment ATTRIBUTE_UNUSED
;
4650 #ifdef BFD_ASSEMBLER
4651 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4652 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4654 /* For a.out, force the section size to be aligned. If we don't do
4655 this, BFD will align it for us, but it will not write out the
4656 final bytes of the section. This may be a bug in BFD, but it is
4657 easier to fix it here since that is how the other a.out targets
4661 align
= bfd_get_section_alignment (stdoutput
, segment
);
4662 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4670 /* On the i386, PC-relative offsets are relative to the start of the
4671 next instruction. That is, the address of the offset, plus its
4672 size, since the offset is always the last part of the insn. */
4675 md_pcrel_from (fixP
)
4678 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4685 int ignore ATTRIBUTE_UNUSED
;
4689 temp
= get_absolute_expression ();
4690 subseg_set (bss_section
, (subsegT
) temp
);
4691 demand_empty_rest_of_line ();
4696 #ifdef BFD_ASSEMBLER
4699 i386_validate_fix (fixp
)
4702 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4704 /* GOTOFF relocation are nonsense in 64bit mode. */
4705 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4707 if (flag_code
!= CODE_64BIT
)
4709 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4713 if (flag_code
== CODE_64BIT
)
4715 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4722 tc_gen_reloc (section
, fixp
)
4723 asection
*section ATTRIBUTE_UNUSED
;
4727 bfd_reloc_code_real_type code
;
4729 switch (fixp
->fx_r_type
)
4731 case BFD_RELOC_X86_64_PLT32
:
4732 case BFD_RELOC_X86_64_GOT32
:
4733 case BFD_RELOC_X86_64_GOTPCREL
:
4734 case BFD_RELOC_386_PLT32
:
4735 case BFD_RELOC_386_GOT32
:
4736 case BFD_RELOC_386_GOTOFF
:
4737 case BFD_RELOC_386_GOTPC
:
4738 case BFD_RELOC_X86_64_32S
:
4740 case BFD_RELOC_VTABLE_ENTRY
:
4741 case BFD_RELOC_VTABLE_INHERIT
:
4742 code
= fixp
->fx_r_type
;
4747 switch (fixp
->fx_size
)
4750 as_bad (_("can not do %d byte pc-relative relocation"),
4752 code
= BFD_RELOC_32_PCREL
;
4754 case 1: code
= BFD_RELOC_8_PCREL
; break;
4755 case 2: code
= BFD_RELOC_16_PCREL
; break;
4756 case 4: code
= BFD_RELOC_32_PCREL
; break;
4761 switch (fixp
->fx_size
)
4764 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4765 code
= BFD_RELOC_32
;
4767 case 1: code
= BFD_RELOC_8
; break;
4768 case 2: code
= BFD_RELOC_16
; break;
4769 case 4: code
= BFD_RELOC_32
; break;
4770 case 8: code
= BFD_RELOC_64
; break;
4776 if (code
== BFD_RELOC_32
4778 && fixp
->fx_addsy
== GOT_symbol
)
4780 /* We don't support GOTPC on 64bit targets. */
4781 if (flag_code
== CODE_64BIT
)
4783 code
= BFD_RELOC_386_GOTPC
;
4786 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4787 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4788 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4790 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4791 if (!use_rela_relocations
)
4793 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4794 vtable entry to be used in the relocation's section offset. */
4795 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4796 rel
->address
= fixp
->fx_offset
;
4799 rel
->addend
= fixp
->fx_addnumber
;
4803 /* Use the rela in 64bit mode. */
4806 rel
->addend
= fixp
->fx_offset
;
4808 rel
->addend
-= fixp
->fx_size
;
4811 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4812 if (rel
->howto
== NULL
)
4814 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4815 _("cannot represent relocation type %s"),
4816 bfd_get_reloc_code_name (code
));
4817 /* Set howto to a garbage value so that we can keep going. */
4818 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4819 assert (rel
->howto
!= NULL
);
4825 #else /* ! BFD_ASSEMBLER */
4827 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4829 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4832 relax_addressT segment_address_in_file
;
4834 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4835 Out: GNU LD relocation length code: 0, 1, or 2. */
4837 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4840 know (fixP
->fx_addsy
!= NULL
);
4842 md_number_to_chars (where
,
4843 (valueT
) (fixP
->fx_frag
->fr_address
4844 + fixP
->fx_where
- segment_address_in_file
),
4847 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4848 ? S_GET_TYPE (fixP
->fx_addsy
)
4849 : fixP
->fx_addsy
->sy_number
);
4851 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4852 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4853 where
[4] = r_symbolnum
& 0x0ff;
4854 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4855 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4856 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4859 #endif /* OBJ_AOUT or OBJ_BOUT. */
4861 #if defined (I386COFF)
4864 tc_coff_fix2rtype (fixP
)
4867 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4870 return (fixP
->fx_pcrel
?
4871 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4872 fixP
->fx_size
== 2 ? R_PCRWORD
:
4874 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4875 fixP
->fx_size
== 2 ? R_RELWORD
:
4880 tc_coff_sizemachdep (frag
)
4884 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4889 #endif /* I386COFF */
4891 #endif /* ! BFD_ASSEMBLER */
4893 /* Parse operands using Intel syntax. This implements a recursive descent
4894 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4897 FIXME: We do not recognize the full operand grammar defined in the MASM
4898 documentation. In particular, all the structure/union and
4899 high-level macro operands are missing.
4901 Uppercase words are terminals, lower case words are non-terminals.
4902 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4903 bars '|' denote choices. Most grammar productions are implemented in
4904 functions called 'intel_<production>'.
4906 Initial production is 'expr'.
4912 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4914 constant digits [[ radixOverride ]]
4916 dataType BYTE | WORD | DWORD | QWORD | XWORD
4949 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4950 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4952 hexdigit a | b | c | d | e | f
4953 | A | B | C | D | E | F
4963 register specialRegister
4967 segmentRegister CS | DS | ES | FS | GS | SS
4969 specialRegister CR0 | CR2 | CR3
4970 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4971 | TR3 | TR4 | TR5 | TR6 | TR7
4973 We simplify the grammar in obvious places (e.g., register parsing is
4974 done by calling parse_register) and eliminate immediate left recursion
4975 to implement a recursive-descent parser.
5015 /* Parsing structure for the intel syntax parser. Used to implement the
5016 semantic actions for the operand grammar. */
5017 struct intel_parser_s
5019 char *op_string
; /* The string being parsed. */
5020 int got_a_float
; /* Whether the operand is a float. */
5021 int op_modifier
; /* Operand modifier. */
5022 int is_mem
; /* 1 if operand is memory reference. */
5023 const reg_entry
*reg
; /* Last register reference found. */
5024 char *disp
; /* Displacement string being built. */
5027 static struct intel_parser_s intel_parser
;
5029 /* Token structure for parsing intel syntax. */
5032 int code
; /* Token code. */
5033 const reg_entry
*reg
; /* Register entry for register tokens. */
5034 char *str
; /* String representation. */
5037 static struct intel_token cur_token
, prev_token
;
5039 /* Token codes for the intel parser. Since T_SHORT is already used
5040 by COFF, undefine it first to prevent a warning. */
5055 /* Prototypes for intel parser functions. */
5056 static int intel_match_token
PARAMS ((int code
));
5057 static void intel_get_token
PARAMS ((void));
5058 static void intel_putback_token
PARAMS ((void));
5059 static int intel_expr
PARAMS ((void));
5060 static int intel_e05
PARAMS ((void));
5061 static int intel_e05_1
PARAMS ((void));
5062 static int intel_e06
PARAMS ((void));
5063 static int intel_e06_1
PARAMS ((void));
5064 static int intel_e09
PARAMS ((void));
5065 static int intel_e09_1
PARAMS ((void));
5066 static int intel_e10
PARAMS ((void));
5067 static int intel_e10_1
PARAMS ((void));
5068 static int intel_e11
PARAMS ((void));
5071 i386_intel_operand (operand_string
, got_a_float
)
5072 char *operand_string
;
5078 /* Initialize token holders. */
5079 cur_token
.code
= prev_token
.code
= T_NIL
;
5080 cur_token
.reg
= prev_token
.reg
= NULL
;
5081 cur_token
.str
= prev_token
.str
= NULL
;
5083 /* Initialize parser structure. */
5084 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5087 strcpy (intel_parser
.op_string
, operand_string
);
5088 intel_parser
.got_a_float
= got_a_float
;
5089 intel_parser
.op_modifier
= -1;
5090 intel_parser
.is_mem
= 0;
5091 intel_parser
.reg
= NULL
;
5092 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5093 if (intel_parser
.disp
== NULL
)
5095 intel_parser
.disp
[0] = '\0';
5097 /* Read the first token and start the parser. */
5099 ret
= intel_expr ();
5103 /* If we found a memory reference, hand it over to i386_displacement
5104 to fill in the rest of the operand fields. */
5105 if (intel_parser
.is_mem
)
5107 if ((i
.mem_operands
== 1
5108 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5109 || i
.mem_operands
== 2)
5111 as_bad (_("too many memory references for '%s'"),
5112 current_templates
->start
->name
);
5117 char *s
= intel_parser
.disp
;
5120 /* Add the displacement expression. */
5122 ret
= i386_displacement (s
, s
+ strlen (s
))
5123 && i386_index_check (s
);
5127 /* Constant and OFFSET expressions are handled by i386_immediate. */
5128 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5129 || intel_parser
.reg
== NULL
)
5130 ret
= i386_immediate (intel_parser
.disp
);
5134 free (intel_parser
.disp
);
5144 /* expr SHORT e05 */
5145 if (cur_token
.code
== T_SHORT
)
5147 intel_parser
.op_modifier
= SHORT
;
5148 intel_match_token (T_SHORT
);
5150 return (intel_e05 ());
5155 return intel_e05 ();
5165 return (intel_e06 () && intel_e05_1 ());
5171 /* e05' addOp e06 e05' */
5172 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5174 strcat (intel_parser
.disp
, cur_token
.str
);
5175 intel_match_token (cur_token
.code
);
5177 return (intel_e06 () && intel_e05_1 ());
5192 return (intel_e09 () && intel_e06_1 ());
5198 /* e06' mulOp e09 e06' */
5199 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5201 strcat (intel_parser
.disp
, cur_token
.str
);
5202 intel_match_token (cur_token
.code
);
5204 return (intel_e09 () && intel_e06_1 ());
5212 /* e09 OFFSET e10 e09'
5221 /* e09 OFFSET e10 e09' */
5222 if (cur_token
.code
== T_OFFSET
)
5224 intel_parser
.is_mem
= 0;
5225 intel_parser
.op_modifier
= OFFSET_FLAT
;
5226 intel_match_token (T_OFFSET
);
5228 return (intel_e10 () && intel_e09_1 ());
5233 return (intel_e10 () && intel_e09_1 ());
5239 /* e09' PTR e10 e09' */
5240 if (cur_token
.code
== T_PTR
)
5242 if (prev_token
.code
== T_BYTE
)
5243 i
.suffix
= BYTE_MNEM_SUFFIX
;
5245 else if (prev_token
.code
== T_WORD
)
5247 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5248 i
.suffix
= SHORT_MNEM_SUFFIX
;
5250 i
.suffix
= WORD_MNEM_SUFFIX
;
5253 else if (prev_token
.code
== T_DWORD
)
5255 if (intel_parser
.got_a_float
== 1) /* "f..." */
5256 i
.suffix
= SHORT_MNEM_SUFFIX
;
5258 i
.suffix
= LONG_MNEM_SUFFIX
;
5261 else if (prev_token
.code
== T_QWORD
)
5263 if (intel_parser
.got_a_float
== 1) /* "f..." */
5264 i
.suffix
= LONG_MNEM_SUFFIX
;
5266 i
.suffix
= QWORD_MNEM_SUFFIX
;
5269 else if (prev_token
.code
== T_XWORD
)
5270 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5274 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5278 intel_match_token (T_PTR
);
5280 return (intel_e10 () && intel_e09_1 ());
5283 /* e09 : e10 e09' */
5284 else if (cur_token
.code
== ':')
5286 /* Mark as a memory operand only if it's not already known to be an
5287 offset expression. */
5288 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5289 intel_parser
.is_mem
= 1;
5291 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5306 return (intel_e11 () && intel_e10_1 ());
5312 /* e10' [ expr ] e10' */
5313 if (cur_token
.code
== '[')
5315 intel_match_token ('[');
5317 /* Mark as a memory operand only if it's not already known to be an
5318 offset expression. If it's an offset expression, we need to keep
5320 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5321 intel_parser
.is_mem
= 1;
5323 strcat (intel_parser
.disp
, "[");
5325 /* Add a '+' to the displacement string if necessary. */
5326 if (*intel_parser
.disp
!= '\0'
5327 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5328 strcat (intel_parser
.disp
, "+");
5330 if (intel_expr () && intel_match_token (']'))
5332 /* Preserve brackets when the operand is an offset expression. */
5333 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5334 strcat (intel_parser
.disp
, "]");
5336 return intel_e10_1 ();
5363 if (cur_token
.code
== '(')
5365 intel_match_token ('(');
5366 strcat (intel_parser
.disp
, "(");
5368 if (intel_expr () && intel_match_token (')'))
5370 strcat (intel_parser
.disp
, ")");
5378 else if (cur_token
.code
== '[')
5380 intel_match_token ('[');
5382 /* Mark as a memory operand only if it's not already known to be an
5383 offset expression. If it's an offset expression, we need to keep
5385 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5386 intel_parser
.is_mem
= 1;
5388 strcat (intel_parser
.disp
, "[");
5390 /* Operands for jump/call inside brackets denote absolute addresses. */
5391 if (current_templates
->start
->opcode_modifier
& Jump
5392 || current_templates
->start
->opcode_modifier
& JumpDword
5393 || current_templates
->start
->opcode_modifier
& JumpByte
5394 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5395 i
.types
[this_operand
] |= JumpAbsolute
;
5397 /* Add a '+' to the displacement string if necessary. */
5398 if (*intel_parser
.disp
!= '\0'
5399 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5400 strcat (intel_parser
.disp
, "+");
5402 if (intel_expr () && intel_match_token (']'))
5404 /* Preserve brackets when the operand is an offset expression. */
5405 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5406 strcat (intel_parser
.disp
, "]");
5419 else if (cur_token
.code
== T_BYTE
5420 || cur_token
.code
== T_WORD
5421 || cur_token
.code
== T_DWORD
5422 || cur_token
.code
== T_QWORD
5423 || cur_token
.code
== T_XWORD
)
5425 intel_match_token (cur_token
.code
);
5432 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5434 strcat (intel_parser
.disp
, cur_token
.str
);
5435 intel_match_token (cur_token
.code
);
5437 /* Mark as a memory operand only if it's not already known to be an
5438 offset expression. */
5439 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5440 intel_parser
.is_mem
= 1;
5446 else if (cur_token
.code
== T_REG
)
5448 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5450 intel_match_token (T_REG
);
5452 /* Check for segment change. */
5453 if (cur_token
.code
== ':')
5455 if (reg
->reg_type
& (SReg2
| SReg3
))
5457 switch (reg
->reg_num
)
5460 i
.seg
[i
.mem_operands
] = &es
;
5463 i
.seg
[i
.mem_operands
] = &cs
;
5466 i
.seg
[i
.mem_operands
] = &ss
;
5469 i
.seg
[i
.mem_operands
] = &ds
;
5472 i
.seg
[i
.mem_operands
] = &fs
;
5475 i
.seg
[i
.mem_operands
] = &gs
;
5481 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5486 /* Not a segment register. Check for register scaling. */
5487 else if (cur_token
.code
== '*')
5489 if (!intel_parser
.is_mem
)
5491 as_bad (_("Register scaling only allowed in memory operands."));
5495 /* What follows must be a valid scale. */
5496 if (intel_match_token ('*')
5497 && strchr ("01248", *cur_token
.str
))
5500 i
.types
[this_operand
] |= BaseIndex
;
5502 /* Set the scale after setting the register (otherwise,
5503 i386_scale will complain) */
5504 i386_scale (cur_token
.str
);
5505 intel_match_token (T_CONST
);
5509 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5515 /* No scaling. If this is a memory operand, the register is either a
5516 base register (first occurrence) or an index register (second
5518 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5520 if (i
.base_reg
&& i
.index_reg
)
5522 as_bad (_("Too many register references in memory operand.\n"));
5526 if (i
.base_reg
== NULL
)
5531 i
.types
[this_operand
] |= BaseIndex
;
5534 /* Offset modifier. Add the register to the displacement string to be
5535 parsed as an immediate expression after we're done. */
5536 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5537 strcat (intel_parser
.disp
, reg
->reg_name
);
5539 /* It's neither base nor index nor offset. */
5542 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5543 i
.op
[this_operand
].regs
= reg
;
5547 /* Since registers are not part of the displacement string (except
5548 when we're parsing offset operands), we may need to remove any
5549 preceding '+' from the displacement string. */
5550 if (*intel_parser
.disp
!= '\0'
5551 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5553 char *s
= intel_parser
.disp
;
5554 s
+= strlen (s
) - 1;
5563 else if (cur_token
.code
== T_ID
)
5565 /* Add the identifier to the displacement string. */
5566 strcat (intel_parser
.disp
, cur_token
.str
);
5567 intel_match_token (T_ID
);
5569 /* The identifier represents a memory reference only if it's not
5570 preceded by an offset modifier. */
5571 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5572 intel_parser
.is_mem
= 1;
5578 else if (cur_token
.code
== T_CONST
5579 || cur_token
.code
== '-'
5580 || cur_token
.code
== '+')
5584 /* Allow constants that start with `+' or `-'. */
5585 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5587 strcat (intel_parser
.disp
, cur_token
.str
);
5588 intel_match_token (cur_token
.code
);
5589 if (cur_token
.code
!= T_CONST
)
5591 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5597 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5598 if (save_str
== NULL
)
5600 strcpy (save_str
, cur_token
.str
);
5602 /* Get the next token to check for register scaling. */
5603 intel_match_token (cur_token
.code
);
5605 /* Check if this constant is a scaling factor for an index register. */
5606 if (cur_token
.code
== '*')
5608 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5610 if (!intel_parser
.is_mem
)
5612 as_bad (_("Register scaling only allowed in memory operands."));
5616 /* The constant is followed by `* reg', so it must be
5618 if (strchr ("01248", *save_str
))
5620 i
.index_reg
= cur_token
.reg
;
5621 i
.types
[this_operand
] |= BaseIndex
;
5623 /* Set the scale after setting the register (otherwise,
5624 i386_scale will complain) */
5625 i386_scale (save_str
);
5626 intel_match_token (T_REG
);
5628 /* Since registers are not part of the displacement
5629 string, we may need to remove any preceding '+' from
5630 the displacement string. */
5631 if (*intel_parser
.disp
!= '\0')
5633 char *s
= intel_parser
.disp
;
5634 s
+= strlen (s
) - 1;
5647 /* The constant was not used for register scaling. Since we have
5648 already consumed the token following `*' we now need to put it
5649 back in the stream. */
5651 intel_putback_token ();
5654 /* Add the constant to the displacement string. */
5655 strcat (intel_parser
.disp
, save_str
);
5661 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5665 /* Match the given token against cur_token. If they match, read the next
5666 token from the operand string. */
5668 intel_match_token (code
)
5671 if (cur_token
.code
== code
)
5678 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5683 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5688 const reg_entry
*reg
;
5689 struct intel_token new_token
;
5691 new_token
.code
= T_NIL
;
5692 new_token
.reg
= NULL
;
5693 new_token
.str
= NULL
;
5695 /* Free the memory allocated to the previous token and move
5696 cur_token to prev_token. */
5698 free (prev_token
.str
);
5700 prev_token
= cur_token
;
5702 /* Skip whitespace. */
5703 while (is_space_char (*intel_parser
.op_string
))
5704 intel_parser
.op_string
++;
5706 /* Return an empty token if we find nothing else on the line. */
5707 if (*intel_parser
.op_string
== '\0')
5709 cur_token
= new_token
;
5713 /* The new token cannot be larger than the remainder of the operand
5715 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5716 if (new_token
.str
== NULL
)
5718 new_token
.str
[0] = '\0';
5720 if (strchr ("0123456789", *intel_parser
.op_string
))
5722 char *p
= new_token
.str
;
5723 char *q
= intel_parser
.op_string
;
5724 new_token
.code
= T_CONST
;
5726 /* Allow any kind of identifier char to encompass floating point and
5727 hexadecimal numbers. */
5728 while (is_identifier_char (*q
))
5732 /* Recognize special symbol names [0-9][bf]. */
5733 if (strlen (intel_parser
.op_string
) == 2
5734 && (intel_parser
.op_string
[1] == 'b'
5735 || intel_parser
.op_string
[1] == 'f'))
5736 new_token
.code
= T_ID
;
5739 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5741 new_token
.code
= *intel_parser
.op_string
;
5742 new_token
.str
[0] = *intel_parser
.op_string
;
5743 new_token
.str
[1] = '\0';
5746 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5747 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5749 new_token
.code
= T_REG
;
5750 new_token
.reg
= reg
;
5752 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5754 new_token
.str
[0] = REGISTER_PREFIX
;
5755 new_token
.str
[1] = '\0';
5758 strcat (new_token
.str
, reg
->reg_name
);
5761 else if (is_identifier_char (*intel_parser
.op_string
))
5763 char *p
= new_token
.str
;
5764 char *q
= intel_parser
.op_string
;
5766 /* A '.' or '$' followed by an identifier char is an identifier.
5767 Otherwise, it's operator '.' followed by an expression. */
5768 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5770 new_token
.code
= *q
;
5771 new_token
.str
[0] = *q
;
5772 new_token
.str
[1] = '\0';
5776 while (is_identifier_char (*q
) || *q
== '@')
5780 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5781 new_token
.code
= T_BYTE
;
5783 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5784 new_token
.code
= T_WORD
;
5786 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5787 new_token
.code
= T_DWORD
;
5789 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5790 new_token
.code
= T_QWORD
;
5792 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5793 new_token
.code
= T_XWORD
;
5795 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5796 new_token
.code
= T_PTR
;
5798 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5799 new_token
.code
= T_SHORT
;
5801 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5803 new_token
.code
= T_OFFSET
;
5805 /* ??? This is not mentioned in the MASM grammar but gcc
5806 makes use of it with -mintel-syntax. OFFSET may be
5807 followed by FLAT: */
5808 if (strncasecmp (q
, " FLAT:", 6) == 0)
5809 strcat (new_token
.str
, " FLAT:");
5812 /* ??? This is not mentioned in the MASM grammar. */
5813 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5814 new_token
.code
= T_OFFSET
;
5817 new_token
.code
= T_ID
;
5822 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5824 intel_parser
.op_string
+= strlen (new_token
.str
);
5825 cur_token
= new_token
;
5828 /* Put cur_token back into the token stream and make cur_token point to
5831 intel_putback_token ()
5833 intel_parser
.op_string
-= strlen (cur_token
.str
);
5834 free (cur_token
.str
);
5835 cur_token
= prev_token
;
5837 /* Forget prev_token. */
5838 prev_token
.code
= T_NIL
;
5839 prev_token
.reg
= NULL
;
5840 prev_token
.str
= NULL
;