1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
70 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
73 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
75 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
76 static int smallest_imm_type
PARAMS ((offsetT
));
77 static offsetT offset_in_range
PARAMS ((offsetT
, int));
78 static int add_prefix
PARAMS ((unsigned int));
79 static void set_code_flag
PARAMS ((int));
80 static void set_16bit_gcc_code_flag
PARAMS ((int));
81 static void set_intel_syntax
PARAMS ((int));
82 static void set_cpu_arch
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((void));
108 static void output_disp
PARAMS ((void));
110 static void s_bss
PARAMS ((int));
113 static const char *default_arch
= DEFAULT_ARCH
;
115 /* 'md_assemble ()' gathers together information and puts it into a
122 const reg_entry
*regs
;
127 /* TM holds the template for the insn were currently assembling. */
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
134 /* OPERANDS gives the number of given operands. */
135 unsigned int operands
;
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
140 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
142 /* TYPES [i] is the type (see above #defines) which tells us how to
143 use OP[i] for the corresponding operand. */
144 unsigned int types
[MAX_OPERANDS
];
146 /* Displacement expression, immediate expression, or register for each
148 union i386_op op
[MAX_OPERANDS
];
150 /* Flags for operands. */
151 unsigned int flags
[MAX_OPERANDS
];
152 #define Operand_PCrel 1
154 /* Relocation type for operand */
155 RELOC_ENUM reloc
[MAX_OPERANDS
];
157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry
*base_reg
;
160 const reg_entry
*index_reg
;
161 unsigned int log2_scale_factor
;
163 /* SEG gives the seg_entries of this insn. They are zero unless
164 explicit segment overrides are given. */
165 const seg_entry
*seg
[2];
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes
;
170 unsigned char prefix
[MAX_PREFIXES
];
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
180 typedef struct _i386_insn i386_insn
;
182 /* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars
[] = "*%-(@[";
187 const char extra_symbol_chars
[] = "*%-([";
190 #if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
195 /* This array holds the chars that always start a comment. If the
196 pre-processor is disabled, these aren't very useful. */
197 const char comment_chars
[] = "#/";
198 #define PREFIX_SEPARATOR '\\'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "";
211 /* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213 const char comment_chars
[] = "#";
214 #define PREFIX_SEPARATOR '/'
216 const char line_comment_chars
[] = "/";
219 const char line_separator_chars
[] = ";";
221 /* Chars that can be used to separate mant from exp in floating point
223 const char EXP_CHARS
[] = "eE";
225 /* Chars that mean this number is a floating point constant
228 const char FLT_CHARS
[] = "fFdDxX";
230 /* Tables for lexical analysis. */
231 static char mnemonic_chars
[256];
232 static char register_chars
[256];
233 static char operand_chars
[256];
234 static char identifier_chars
[256];
235 static char digit_chars
[256];
237 /* Lexical macros. */
238 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239 #define is_operand_char(x) (operand_chars[(unsigned char) x])
240 #define is_register_char(x) (register_chars[(unsigned char) x])
241 #define is_space_char(x) ((x) == ' ')
242 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243 #define is_digit_char(x) (digit_chars[(unsigned char) x])
245 /* All non-digit non-letter charcters that may occur in an operand. */
246 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
248 /* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
251 assembler instruction). */
252 static char save_stack
[32];
253 static char *save_stack_p
;
254 #define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256 #define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
259 /* The instruction we're assembling. */
262 /* Possible templates for current insn. */
263 static const templates
*current_templates
;
265 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
266 static expressionS disp_expressions
[2], im_expressions
[2];
268 /* Current operand we are working on. */
269 static int this_operand
;
271 /* We support four different modes. FLAG_CODE variable is used to distinguish
278 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
280 static enum flag_code flag_code
;
281 static int use_rela_relocations
= 0;
283 /* The names used to print error messages. */
284 static const char *flag_code_names
[] =
291 /* 1 for intel syntax,
293 static int intel_syntax
= 0;
295 /* 1 if register prefix % not required. */
296 static int allow_naked_reg
= 0;
298 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301 static char stackop_size
= '\0';
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings
= 0;
307 static const char *cpu_arch_name
= NULL
;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion
= 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* Interface to relax_segment.
320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
325 #define UNCOND_JUMP 0
327 #define COND_JUMP86 2
332 #define SMALL16 (SMALL | CODE16)
334 #define BIG16 (BIG | CODE16)
338 #define INLINE __inline__
344 #define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346 #define TYPE_FROM_RELAX_STATE(s) \
348 #define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
351 /* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
359 const relax_typeS md_relax_table
[] =
362 1) most positive reach of this state,
363 2) most negative reach of this state,
364 3) how many bytes this mode will have in the variable part of the frag
365 4) which index into the table to try if we can't fit into this one. */
367 /* UNCOND_JUMP states. */
368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
383 /* word conditionals add 3 bytes to frag:
384 1 extra opcode byte, 2 displacement bytes. */
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
398 static const arch_entry cpu_arch
[] = {
400 {"i186", Cpu086
|Cpu186
},
401 {"i286", Cpu086
|Cpu186
|Cpu286
},
402 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
403 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
404 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
405 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
406 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
407 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
408 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
409 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
410 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
411 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
415 const pseudo_typeS md_pseudo_table
[] =
417 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes
, 0},
420 {"align", s_align_ptwo
, 0},
422 {"arch", set_cpu_arch
, 0},
426 {"ffloat", float_cons
, 'f'},
427 {"dfloat", float_cons
, 'd'},
428 {"tfloat", float_cons
, 'x'},
430 {"noopt", s_ignore
, 0},
431 {"optim", s_ignore
, 0},
432 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
433 {"code16", set_code_flag
, CODE_16BIT
},
434 {"code32", set_code_flag
, CODE_32BIT
},
435 {"code64", set_code_flag
, CODE_64BIT
},
436 {"intel_syntax", set_intel_syntax
, 1},
437 {"att_syntax", set_intel_syntax
, 0},
438 {"file", dwarf2_directive_file
, 0},
439 {"loc", dwarf2_directive_loc
, 0},
443 /* For interface with expression (). */
444 extern char *input_line_pointer
;
446 /* Hash table for instruction mnemonic lookup. */
447 static struct hash_control
*op_hash
;
449 /* Hash table for register lookup. */
450 static struct hash_control
*reg_hash
;
453 i386_align_code (fragP
, count
)
457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
460 static const char f32_1
[] =
462 static const char f32_2
[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3
[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4
[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5
[] =
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6
[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7
[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8
[] =
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9
[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10
[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11
[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12
[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13
[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14
[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15
[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
499 static const char f16_3
[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
501 static const char f16_4
[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5
[] =
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6
[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7
[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8
[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt
[] = {
516 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
517 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
519 static const char *const f16_patt
[] = {
520 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
521 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code
== CODE_64BIT
)
529 if (count
> 0 && count
<= 15)
531 if (flag_code
== CODE_16BIT
)
533 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
534 f16_patt
[count
- 1], count
);
536 /* Adjust jump offset. */
537 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
540 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
541 f32_patt
[count
- 1], count
);
542 fragP
->fr_var
= count
;
546 static INLINE
unsigned int
547 mode_from_disp_size (t
)
550 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
554 fits_in_signed_byte (num
)
557 return (num
>= -128) && (num
<= 127);
561 fits_in_unsigned_byte (num
)
564 return (num
& 0xff) == num
;
568 fits_in_unsigned_word (num
)
571 return (num
& 0xffff) == num
;
575 fits_in_signed_word (num
)
578 return (-32768 <= num
) && (num
<= 32767);
581 fits_in_signed_long (num
)
582 offsetT num ATTRIBUTE_UNUSED
;
587 return (!(((offsetT
) -1 << 31) & num
)
588 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
590 } /* fits_in_signed_long() */
592 fits_in_unsigned_long (num
)
593 offsetT num ATTRIBUTE_UNUSED
;
598 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
600 } /* fits_in_unsigned_long() */
603 smallest_imm_type (num
)
606 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
614 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
616 return (fits_in_signed_byte (num
)
617 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
618 : fits_in_unsigned_byte (num
)
619 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
620 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
621 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
622 : fits_in_signed_long (num
)
623 ? (Imm32
| Imm32S
| Imm64
)
624 : fits_in_unsigned_long (num
)
630 offset_in_range (val
, size
)
638 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
639 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
640 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
642 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
647 /* If BFD64, sign extend val. */
648 if (!use_rela_relocations
)
649 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
650 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
652 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
654 char buf1
[40], buf2
[40];
656 sprint_value (buf1
, val
);
657 sprint_value (buf2
, val
& mask
);
658 as_warn (_("%s shortened to %s"), buf1
, buf2
);
663 /* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
673 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
674 && flag_code
== CODE_64BIT
)
682 case CS_PREFIX_OPCODE
:
683 case DS_PREFIX_OPCODE
:
684 case ES_PREFIX_OPCODE
:
685 case FS_PREFIX_OPCODE
:
686 case GS_PREFIX_OPCODE
:
687 case SS_PREFIX_OPCODE
:
691 case REPNE_PREFIX_OPCODE
:
692 case REPE_PREFIX_OPCODE
:
695 case LOCK_PREFIX_OPCODE
:
703 case ADDR_PREFIX_OPCODE
:
707 case DATA_PREFIX_OPCODE
:
712 if (i
.prefix
[q
] != 0)
714 as_bad (_("same type of prefix used twice"));
719 i
.prefix
[q
] = prefix
;
724 set_code_flag (value
)
728 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
729 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
730 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
732 as_bad (_("64bit mode not supported on this CPU."));
734 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
736 as_bad (_("32bit mode not supported on this CPU."));
742 set_16bit_gcc_code_flag (new_code_flag
)
745 flag_code
= new_code_flag
;
746 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
747 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
752 set_intel_syntax (syntax_flag
)
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg
= 0;
759 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
761 char *string
= input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "prefix") == 0)
766 else if (strcmp (string
, "noprefix") == 0)
769 as_bad (_("bad argument to syntax directive."));
770 *input_line_pointer
= e
;
772 demand_empty_rest_of_line ();
774 intel_syntax
= syntax_flag
;
776 if (ask_naked_reg
== 0)
779 allow_naked_reg
= (intel_syntax
780 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
782 /* Conservative default. */
787 allow_naked_reg
= (ask_naked_reg
< 0);
792 int dummy ATTRIBUTE_UNUSED
;
796 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
798 char *string
= input_line_pointer
;
799 int e
= get_symbol_end ();
802 for (i
= 0; cpu_arch
[i
].name
; i
++)
804 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
806 cpu_arch_name
= cpu_arch
[i
].name
;
807 cpu_arch_flags
= (cpu_arch
[i
].flags
808 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
812 if (!cpu_arch
[i
].name
)
813 as_bad (_("no such architecture: `%s'"), string
);
815 *input_line_pointer
= e
;
818 as_bad (_("missing cpu architecture"));
820 no_cond_jump_promotion
= 0;
821 if (*input_line_pointer
== ','
822 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
824 char *string
= ++input_line_pointer
;
825 int e
= get_symbol_end ();
827 if (strcmp (string
, "nojumps") == 0)
828 no_cond_jump_promotion
= 1;
829 else if (strcmp (string
, "jumps") == 0)
832 as_bad (_("no such architecture modifier: `%s'"), string
);
834 *input_line_pointer
= e
;
837 demand_empty_rest_of_line ();
844 if (!strcmp (default_arch
, "x86_64"))
845 return bfd_mach_x86_64
;
846 else if (!strcmp (default_arch
, "i386"))
847 return bfd_mach_i386_i386
;
849 as_fatal (_("Unknown architecture"));
856 const char *hash_err
;
858 /* Initialize op_hash hash table. */
859 op_hash
= hash_new ();
862 const template *optab
;
863 templates
*core_optab
;
865 /* Setup for loop. */
867 core_optab
= (templates
*) xmalloc (sizeof (templates
));
868 core_optab
->start
= optab
;
873 if (optab
->name
== NULL
874 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
876 /* different name --> ship out current template list;
877 add to hash table; & begin anew. */
878 core_optab
->end
= optab
;
879 hash_err
= hash_insert (op_hash
,
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
888 if (optab
->name
== NULL
)
890 core_optab
= (templates
*) xmalloc (sizeof (templates
));
891 core_optab
->start
= optab
;
896 /* Initialize reg_hash hash table. */
897 reg_hash
= hash_new ();
899 const reg_entry
*regtab
;
901 for (regtab
= i386_regtab
;
902 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
905 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
907 as_fatal (_("Internal Error: Can't hash %s: %s"),
913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
918 for (c
= 0; c
< 256; c
++)
923 mnemonic_chars
[c
] = c
;
924 register_chars
[c
] = c
;
925 operand_chars
[c
] = c
;
927 else if (ISLOWER (c
))
929 mnemonic_chars
[c
] = c
;
930 register_chars
[c
] = c
;
931 operand_chars
[c
] = c
;
933 else if (ISUPPER (c
))
935 mnemonic_chars
[c
] = TOLOWER (c
);
936 register_chars
[c
] = mnemonic_chars
[c
];
937 operand_chars
[c
] = c
;
940 if (ISALPHA (c
) || ISDIGIT (c
))
941 identifier_chars
[c
] = c
;
944 identifier_chars
[c
] = c
;
945 operand_chars
[c
] = c
;
950 identifier_chars
['@'] = '@';
952 digit_chars
['-'] = '-';
953 identifier_chars
['_'] = '_';
954 identifier_chars
['.'] = '.';
956 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
957 operand_chars
[(unsigned char) *p
] = *p
;
960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
963 record_alignment (text_section
, 2);
964 record_alignment (data_section
, 2);
965 record_alignment (bss_section
, 2);
971 i386_print_statistics (file
)
974 hash_print_statistics (file
, "i386 opcode", op_hash
);
975 hash_print_statistics (file
, "i386 register", reg_hash
);
980 /* Debugging routines for md_assemble. */
981 static void pi
PARAMS ((char *, i386_insn
*));
982 static void pte
PARAMS ((template *));
983 static void pt
PARAMS ((unsigned int));
984 static void pe
PARAMS ((expressionS
*));
985 static void ps
PARAMS ((symbolS
*));
994 fprintf (stdout
, "%s: template ", line
);
996 fprintf (stdout
, " address: base %s index %s scale %x\n",
997 x
->base_reg
? x
->base_reg
->reg_name
: "none",
998 x
->index_reg
? x
->index_reg
->reg_name
: "none",
999 x
->log2_scale_factor
);
1000 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1001 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1002 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1003 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1004 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1005 (x
->rex
& REX_MODE64
) != 0,
1006 (x
->rex
& REX_EXTX
) != 0,
1007 (x
->rex
& REX_EXTY
) != 0,
1008 (x
->rex
& REX_EXTZ
) != 0);
1009 for (i
= 0; i
< x
->operands
; i
++)
1011 fprintf (stdout
, " #%d: ", i
+ 1);
1013 fprintf (stdout
, "\n");
1015 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1016 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1017 if (x
->types
[i
] & Imm
)
1019 if (x
->types
[i
] & Disp
)
1020 pe (x
->op
[i
].disps
);
1029 fprintf (stdout
, " %d operands ", t
->operands
);
1030 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1031 if (t
->extension_opcode
!= None
)
1032 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1033 if (t
->opcode_modifier
& D
)
1034 fprintf (stdout
, "D");
1035 if (t
->opcode_modifier
& W
)
1036 fprintf (stdout
, "W");
1037 fprintf (stdout
, "\n");
1038 for (i
= 0; i
< t
->operands
; i
++)
1040 fprintf (stdout
, " #%d type ", i
+ 1);
1041 pt (t
->operand_types
[i
]);
1042 fprintf (stdout
, "\n");
1050 fprintf (stdout
, " operation %d\n", e
->X_op
);
1051 fprintf (stdout
, " add_number %ld (%lx)\n",
1052 (long) e
->X_add_number
, (long) e
->X_add_number
);
1053 if (e
->X_add_symbol
)
1055 fprintf (stdout
, " add_symbol ");
1056 ps (e
->X_add_symbol
);
1057 fprintf (stdout
, "\n");
1061 fprintf (stdout
, " op_symbol ");
1062 ps (e
->X_op_symbol
);
1063 fprintf (stdout
, "\n");
1071 fprintf (stdout
, "%s type %s%s",
1073 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s
)));
1083 static const type_names
[] =
1096 { BaseIndex
, "BaseIndex" },
1100 { Disp32S
, "d32s" },
1102 { InOutPortReg
, "InOutPortReg" },
1103 { ShiftCount
, "ShiftCount" },
1104 { Control
, "control reg" },
1105 { Test
, "test reg" },
1106 { Debug
, "debug reg" },
1107 { FloatReg
, "FReg" },
1108 { FloatAcc
, "FAcc" },
1112 { JumpAbsolute
, "Jump Absolute" },
1123 const struct type_name
*ty
;
1125 for (ty
= type_names
; ty
->mask
; ty
++)
1127 fprintf (stdout
, "%s, ", ty
->tname
);
1131 #endif /* DEBUG386 */
1134 tc_i386_force_relocation (fixp
)
1137 #ifdef BFD_ASSEMBLER
1138 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1139 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1144 return fixp
->fx_r_type
== 7;
1148 #ifdef BFD_ASSEMBLER
1149 static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1152 static bfd_reloc_code_real_type
1153 reloc (size
, pcrel
, sign
, other
)
1157 bfd_reloc_code_real_type other
;
1159 if (other
!= NO_RELOC
)
1165 as_bad (_("There are no unsigned pc-relative relocations"));
1168 case 1: return BFD_RELOC_8_PCREL
;
1169 case 2: return BFD_RELOC_16_PCREL
;
1170 case 4: return BFD_RELOC_32_PCREL
;
1172 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1179 case 4: return BFD_RELOC_X86_64_32S
;
1184 case 1: return BFD_RELOC_8
;
1185 case 2: return BFD_RELOC_16
;
1186 case 4: return BFD_RELOC_32
;
1187 case 8: return BFD_RELOC_64
;
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign
? "signed" : "unsigned", size
);
1194 return BFD_RELOC_NONE
;
1197 /* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1203 tc_i386_fix_adjustable (fixP
)
1206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
1209 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1210 || S_IS_WEAK (fixP
->fx_addsy
)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1218 /* adjust_reloc_syms doesn't know about the GOT. */
1219 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1220 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1221 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1222 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1223 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1228 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1229 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1230 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1231 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1232 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1237 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1238 #define BFD_RELOC_16 0
1239 #define BFD_RELOC_32 0
1240 #define BFD_RELOC_16_PCREL 0
1241 #define BFD_RELOC_32_PCREL 0
1242 #define BFD_RELOC_386_PLT32 0
1243 #define BFD_RELOC_386_GOT32 0
1244 #define BFD_RELOC_386_GOTOFF 0
1245 #define BFD_RELOC_386_TLS_GD 0
1246 #define BFD_RELOC_386_TLS_LDM 0
1247 #define BFD_RELOC_386_TLS_LDO_32 0
1248 #define BFD_RELOC_386_TLS_IE_32 0
1249 #define BFD_RELOC_386_TLS_LE_32 0
1250 #define BFD_RELOC_386_TLS_LE 0
1251 #define BFD_RELOC_X86_64_PLT32 0
1252 #define BFD_RELOC_X86_64_GOT32 0
1253 #define BFD_RELOC_X86_64_GOTPCREL 0
1256 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1259 intel_float_operand (mnemonic
)
1260 const char *mnemonic
;
1262 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1265 if (mnemonic
[0] == 'f')
1271 /* This is the guts of the machine-dependent assembler. LINE points to a
1272 machine dependent instruction. This function is supposed to emit
1273 the frags/bytes it assembles to. */
1280 char mnemonic
[MAX_MNEM_SIZE
];
1282 /* Initialize globals. */
1283 memset (&i
, '\0', sizeof (i
));
1284 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1285 i
.reloc
[j
] = NO_RELOC
;
1286 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1287 memset (im_expressions
, '\0', sizeof (im_expressions
));
1288 save_stack_p
= save_stack
;
1290 /* First parse an instruction mnemonic & call i386_operand for the operands.
1291 We assume that the scrubber has arranged it so that line[0] is the valid
1292 start of a (possibly prefixed) mnemonic. */
1294 line
= parse_insn (line
, mnemonic
);
1298 line
= parse_operands (line
, mnemonic
);
1302 /* Now we've parsed the mnemonic into a set of templates, and have the
1303 operands at hand. */
1305 /* All intel opcodes have reversed operands except for "bound" and
1306 "enter". We also don't reverse intersegment "jmp" and "call"
1307 instructions with 2 immediate operands so that the immediate segment
1308 precedes the offset, as it does when in AT&T mode. "enter" and the
1309 intersegment "jmp" and "call" instructions are the only ones that
1310 have two immediate operands. */
1311 if (intel_syntax
&& i
.operands
> 1
1312 && (strcmp (mnemonic
, "bound") != 0)
1313 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1319 if (i
.disp_operands
)
1322 /* Next, we find a template that matches the given insn,
1323 making sure the overlap of the given operands types is consistent
1324 with the template operand types. */
1326 if (!match_template ())
1331 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1333 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1334 i
.tm
.base_opcode
^= FloatR
;
1336 /* Zap movzx and movsx suffix. The suffix may have been set from
1337 "word ptr" or "byte ptr" on the source operand, but we'll use
1338 the suffix later to choose the destination register. */
1339 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1343 if (i
.tm
.opcode_modifier
& FWait
)
1344 if (!add_prefix (FWAIT_OPCODE
))
1347 /* Check string instruction segment overrides. */
1348 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1350 if (!check_string ())
1354 if (!process_suffix ())
1357 /* Make still unresolved immediate matches conform to size of immediate
1358 given in i.suffix. */
1359 if (!finalize_imm ())
1362 if (i
.types
[0] & Imm1
)
1363 i
.imm_operands
= 0; /* kludge for shift insns. */
1364 if (i
.types
[0] & ImplicitRegister
)
1366 if (i
.types
[1] & ImplicitRegister
)
1368 if (i
.types
[2] & ImplicitRegister
)
1371 if (i
.tm
.opcode_modifier
& ImmExt
)
1373 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1374 opcode suffix which is coded in the same place as an 8-bit
1375 immediate field would be. Here we fake an 8-bit immediate
1376 operand from the opcode suffix stored in tm.extension_opcode. */
1380 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1382 exp
= &im_expressions
[i
.imm_operands
++];
1383 i
.op
[i
.operands
].imms
= exp
;
1384 i
.types
[i
.operands
++] = Imm8
;
1385 exp
->X_op
= O_constant
;
1386 exp
->X_add_number
= i
.tm
.extension_opcode
;
1387 i
.tm
.extension_opcode
= None
;
1390 /* For insns with operands there are more diddles to do to the opcode. */
1393 if (!process_operands ())
1396 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1398 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1399 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1402 /* Handle conversion of 'int $3' --> special int3 insn. */
1403 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1405 i
.tm
.base_opcode
= INT3_OPCODE
;
1409 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1410 && i
.op
[0].disps
->X_op
== O_constant
)
1412 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1413 the absolute address given by the constant. Since ix86 jumps and
1414 calls are pc relative, we need to generate a reloc. */
1415 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1416 i
.op
[0].disps
->X_op
= O_symbol
;
1419 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1420 i
.rex
|= REX_MODE64
;
1422 /* For 8 bit registers we need an empty rex prefix. Also if the
1423 instruction already has a prefix, we need to convert old
1424 registers to new ones. */
1426 if (((i
.types
[0] & Reg8
) != 0
1427 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1428 || ((i
.types
[1] & Reg8
) != 0
1429 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1430 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1435 i
.rex
|= REX_OPCODE
;
1436 for (x
= 0; x
< 2; x
++)
1438 /* Look for 8 bit operand that uses old registers. */
1439 if ((i
.types
[x
] & Reg8
) != 0
1440 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1442 /* In case it is "hi" register, give up. */
1443 if (i
.op
[x
].regs
->reg_num
> 3)
1444 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1445 i
.op
[x
].regs
->reg_name
);
1447 /* Otherwise it is equivalent to the extended register.
1448 Since the encoding doesn't change this is merely
1449 cosmetic cleanup for debug output. */
1451 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1457 add_prefix (REX_OPCODE
| i
.rex
);
1459 /* We are ready to output the insn. */
1464 parse_insn (line
, mnemonic
)
1469 char *token_start
= l
;
1472 /* Non-zero if we found a prefix only acceptable with string insns. */
1473 const char *expecting_string_instruction
= NULL
;
1478 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1481 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1483 as_bad (_("no such instruction: `%s'"), token_start
);
1488 if (!is_space_char (*l
)
1489 && *l
!= END_OF_INSN
1490 && *l
!= PREFIX_SEPARATOR
1493 as_bad (_("invalid character %s in mnemonic"),
1494 output_invalid (*l
));
1497 if (token_start
== l
)
1499 if (*l
== PREFIX_SEPARATOR
)
1500 as_bad (_("expecting prefix; got nothing"));
1502 as_bad (_("expecting mnemonic; got nothing"));
1506 /* Look up instruction (or prefix) via hash table. */
1507 current_templates
= hash_find (op_hash
, mnemonic
);
1509 if (*l
!= END_OF_INSN
1510 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1511 && current_templates
1512 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1514 /* If we are in 16-bit mode, do not allow addr16 or data16.
1515 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1516 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1517 && flag_code
!= CODE_64BIT
1518 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1519 ^ (flag_code
== CODE_16BIT
)))
1521 as_bad (_("redundant %s prefix"),
1522 current_templates
->start
->name
);
1525 /* Add prefix, checking for repeated prefixes. */
1526 switch (add_prefix (current_templates
->start
->base_opcode
))
1531 expecting_string_instruction
= current_templates
->start
->name
;
1534 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1541 if (!current_templates
)
1543 /* See if we can get a match by trimming off a suffix. */
1546 case WORD_MNEM_SUFFIX
:
1547 case BYTE_MNEM_SUFFIX
:
1548 case QWORD_MNEM_SUFFIX
:
1549 i
.suffix
= mnem_p
[-1];
1551 current_templates
= hash_find (op_hash
, mnemonic
);
1553 case SHORT_MNEM_SUFFIX
:
1554 case LONG_MNEM_SUFFIX
:
1557 i
.suffix
= mnem_p
[-1];
1559 current_templates
= hash_find (op_hash
, mnemonic
);
1567 if (intel_float_operand (mnemonic
))
1568 i
.suffix
= SHORT_MNEM_SUFFIX
;
1570 i
.suffix
= LONG_MNEM_SUFFIX
;
1572 current_templates
= hash_find (op_hash
, mnemonic
);
1576 if (!current_templates
)
1578 as_bad (_("no such instruction: `%s'"), token_start
);
1583 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1585 /* Check for a branch hint. We allow ",pt" and ",pn" for
1586 predict taken and predict not taken respectively.
1587 I'm not sure that branch hints actually do anything on loop
1588 and jcxz insns (JumpByte) for current Pentium4 chips. They
1589 may work in the future and it doesn't hurt to accept them
1591 if (l
[0] == ',' && l
[1] == 'p')
1595 if (!add_prefix (DS_PREFIX_OPCODE
))
1599 else if (l
[2] == 'n')
1601 if (!add_prefix (CS_PREFIX_OPCODE
))
1607 /* Any other comma loses. */
1610 as_bad (_("invalid character %s in mnemonic"),
1611 output_invalid (*l
));
1615 /* Check if instruction is supported on specified architecture. */
1616 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1617 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1619 as_warn (_("`%s' is not supported on `%s'"),
1620 current_templates
->start
->name
, cpu_arch_name
);
1622 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1624 as_warn (_("use .code16 to ensure correct addressing mode"));
1627 /* Check for rep/repne without a string instruction. */
1628 if (expecting_string_instruction
1629 && !(current_templates
->start
->opcode_modifier
& IsString
))
1631 as_bad (_("expecting string instruction after `%s'"),
1632 expecting_string_instruction
);
1640 parse_operands (l
, mnemonic
)
1642 const char *mnemonic
;
1646 /* 1 if operand is pending after ','. */
1647 unsigned int expecting_operand
= 0;
1649 /* Non-zero if operand parens not balanced. */
1650 unsigned int paren_not_balanced
;
1652 while (*l
!= END_OF_INSN
)
1654 /* Skip optional white space before operand. */
1655 if (is_space_char (*l
))
1657 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1659 as_bad (_("invalid character %s before operand %d"),
1660 output_invalid (*l
),
1664 token_start
= l
; /* after white space */
1665 paren_not_balanced
= 0;
1666 while (paren_not_balanced
|| *l
!= ',')
1668 if (*l
== END_OF_INSN
)
1670 if (paren_not_balanced
)
1673 as_bad (_("unbalanced parenthesis in operand %d."),
1676 as_bad (_("unbalanced brackets in operand %d."),
1681 break; /* we are done */
1683 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1685 as_bad (_("invalid character %s in operand %d"),
1686 output_invalid (*l
),
1693 ++paren_not_balanced
;
1695 --paren_not_balanced
;
1700 ++paren_not_balanced
;
1702 --paren_not_balanced
;
1706 if (l
!= token_start
)
1707 { /* Yes, we've read in another operand. */
1708 unsigned int operand_ok
;
1709 this_operand
= i
.operands
++;
1710 if (i
.operands
> MAX_OPERANDS
)
1712 as_bad (_("spurious operands; (%d operands/instruction max)"),
1716 /* Now parse operand adding info to 'i' as we go along. */
1717 END_STRING_AND_SAVE (l
);
1721 i386_intel_operand (token_start
,
1722 intel_float_operand (mnemonic
));
1724 operand_ok
= i386_operand (token_start
);
1726 RESTORE_END_STRING (l
);
1732 if (expecting_operand
)
1734 expecting_operand_after_comma
:
1735 as_bad (_("expecting operand after ','; got nothing"));
1740 as_bad (_("expecting operand before ','; got nothing"));
1745 /* Now *l must be either ',' or END_OF_INSN. */
1748 if (*++l
== END_OF_INSN
)
1750 /* Just skip it, if it's \n complain. */
1751 goto expecting_operand_after_comma
;
1753 expecting_operand
= 1;
1762 union i386_op temp_op
;
1763 unsigned int temp_type
;
1764 RELOC_ENUM temp_reloc
;
1768 if (i
.operands
== 2)
1773 else if (i
.operands
== 3)
1778 temp_type
= i
.types
[xchg2
];
1779 i
.types
[xchg2
] = i
.types
[xchg1
];
1780 i
.types
[xchg1
] = temp_type
;
1781 temp_op
= i
.op
[xchg2
];
1782 i
.op
[xchg2
] = i
.op
[xchg1
];
1783 i
.op
[xchg1
] = temp_op
;
1784 temp_reloc
= i
.reloc
[xchg2
];
1785 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1786 i
.reloc
[xchg1
] = temp_reloc
;
1788 if (i
.mem_operands
== 2)
1790 const seg_entry
*temp_seg
;
1791 temp_seg
= i
.seg
[0];
1792 i
.seg
[0] = i
.seg
[1];
1793 i
.seg
[1] = temp_seg
;
1797 /* Try to ensure constant immediates are represented in the smallest
1802 char guess_suffix
= 0;
1806 guess_suffix
= i
.suffix
;
1807 else if (i
.reg_operands
)
1809 /* Figure out a suffix from the last register operand specified.
1810 We can't do this properly yet, ie. excluding InOutPortReg,
1811 but the following works for instructions with immediates.
1812 In any case, we can't set i.suffix yet. */
1813 for (op
= i
.operands
; --op
>= 0;)
1814 if (i
.types
[op
] & Reg
)
1816 if (i
.types
[op
] & Reg8
)
1817 guess_suffix
= BYTE_MNEM_SUFFIX
;
1818 else if (i
.types
[op
] & Reg16
)
1819 guess_suffix
= WORD_MNEM_SUFFIX
;
1820 else if (i
.types
[op
] & Reg32
)
1821 guess_suffix
= LONG_MNEM_SUFFIX
;
1822 else if (i
.types
[op
] & Reg64
)
1823 guess_suffix
= QWORD_MNEM_SUFFIX
;
1827 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1828 guess_suffix
= WORD_MNEM_SUFFIX
;
1830 for (op
= i
.operands
; --op
>= 0;)
1831 if (i
.types
[op
] & Imm
)
1833 switch (i
.op
[op
].imms
->X_op
)
1836 /* If a suffix is given, this operand may be shortened. */
1837 switch (guess_suffix
)
1839 case LONG_MNEM_SUFFIX
:
1840 i
.types
[op
] |= Imm32
| Imm64
;
1842 case WORD_MNEM_SUFFIX
:
1843 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1845 case BYTE_MNEM_SUFFIX
:
1846 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1850 /* If this operand is at most 16 bits, convert it
1851 to a signed 16 bit number before trying to see
1852 whether it will fit in an even smaller size.
1853 This allows a 16-bit operand such as $0xffe0 to
1854 be recognised as within Imm8S range. */
1855 if ((i
.types
[op
] & Imm16
)
1856 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1858 i
.op
[op
].imms
->X_add_number
=
1859 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1861 if ((i
.types
[op
] & Imm32
)
1862 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1865 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1866 ^ ((offsetT
) 1 << 31))
1867 - ((offsetT
) 1 << 31));
1869 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1871 /* We must avoid matching of Imm32 templates when 64bit
1872 only immediate is available. */
1873 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1874 i
.types
[op
] &= ~Imm32
;
1881 /* Symbols and expressions. */
1883 /* Convert symbolic operand to proper sizes for matching. */
1884 switch (guess_suffix
)
1886 case QWORD_MNEM_SUFFIX
:
1887 i
.types
[op
] = Imm64
| Imm32S
;
1889 case LONG_MNEM_SUFFIX
:
1890 i
.types
[op
] = Imm32
| Imm64
;
1892 case WORD_MNEM_SUFFIX
:
1893 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1896 case BYTE_MNEM_SUFFIX
:
1897 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1906 /* Try to use the smallest displacement type too. */
1912 for (op
= i
.operands
; --op
>= 0;)
1913 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1915 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1917 if (i
.types
[op
] & Disp16
)
1919 /* We know this operand is at most 16 bits, so
1920 convert to a signed 16 bit number before trying
1921 to see whether it will fit in an even smaller
1924 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1926 else if (i
.types
[op
] & Disp32
)
1928 /* We know this operand is at most 32 bits, so convert to a
1929 signed 32 bit number before trying to see whether it will
1930 fit in an even smaller size. */
1931 disp
&= (((offsetT
) 2 << 31) - 1);
1932 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1934 if (flag_code
== CODE_64BIT
)
1936 if (fits_in_signed_long (disp
))
1937 i
.types
[op
] |= Disp32S
;
1938 if (fits_in_unsigned_long (disp
))
1939 i
.types
[op
] |= Disp32
;
1941 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1942 && fits_in_signed_byte (disp
))
1943 i
.types
[op
] |= Disp8
;
1950 /* Points to template once we've found it. */
1952 unsigned int overlap0
, overlap1
, overlap2
;
1953 unsigned int found_reverse_match
;
1956 #define MATCH(overlap, given, template) \
1957 ((overlap & ~JumpAbsolute) \
1958 && (((given) & (BaseIndex | JumpAbsolute)) \
1959 == ((overlap) & (BaseIndex | JumpAbsolute))))
1961 /* If given types r0 and r1 are registers they must be of the same type
1962 unless the expected operand type register overlap is null.
1963 Note that Acc in a template matches every size of reg. */
1964 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1965 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1966 || ((g0) & Reg) == ((g1) & Reg) \
1967 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1972 found_reverse_match
= 0;
1973 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1975 : (i
.suffix
== WORD_MNEM_SUFFIX
1977 : (i
.suffix
== SHORT_MNEM_SUFFIX
1979 : (i
.suffix
== LONG_MNEM_SUFFIX
1981 : (i
.suffix
== QWORD_MNEM_SUFFIX
1983 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1984 ? No_xSuf
: 0))))));
1986 for (t
= current_templates
->start
;
1987 t
< current_templates
->end
;
1990 /* Must have right number of operands. */
1991 if (i
.operands
!= t
->operands
)
1994 /* Check the suffix, except for some instructions in intel mode. */
1995 if ((t
->opcode_modifier
& suffix_check
)
1997 && (t
->opcode_modifier
& IgnoreSize
))
1999 && t
->base_opcode
== 0xd9
2000 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2001 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2004 /* Do not verify operands when there are none. */
2005 else if (!t
->operands
)
2007 if (t
->cpu_flags
& ~cpu_arch_flags
)
2009 /* We've found a match; break out of loop. */
2013 overlap0
= i
.types
[0] & t
->operand_types
[0];
2014 switch (t
->operands
)
2017 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2022 overlap1
= i
.types
[1] & t
->operand_types
[1];
2023 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2024 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2025 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2026 t
->operand_types
[0],
2027 overlap1
, i
.types
[1],
2028 t
->operand_types
[1]))
2030 /* Check if other direction is valid ... */
2031 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2034 /* Try reversing direction of operands. */
2035 overlap0
= i
.types
[0] & t
->operand_types
[1];
2036 overlap1
= i
.types
[1] & t
->operand_types
[0];
2037 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2038 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2039 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2040 t
->operand_types
[1],
2041 overlap1
, i
.types
[1],
2042 t
->operand_types
[0]))
2044 /* Does not match either direction. */
2047 /* found_reverse_match holds which of D or FloatDR
2049 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2051 /* Found a forward 2 operand match here. */
2052 else if (t
->operands
== 3)
2054 /* Here we make use of the fact that there are no
2055 reverse match 3 operand instructions, and all 3
2056 operand instructions only need to be checked for
2057 register consistency between operands 2 and 3. */
2058 overlap2
= i
.types
[2] & t
->operand_types
[2];
2059 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2060 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2061 t
->operand_types
[1],
2062 overlap2
, i
.types
[2],
2063 t
->operand_types
[2]))
2067 /* Found either forward/reverse 2 or 3 operand match here:
2068 slip through to break. */
2070 if (t
->cpu_flags
& ~cpu_arch_flags
)
2072 found_reverse_match
= 0;
2075 /* We've found a match; break out of loop. */
2079 if (t
== current_templates
->end
)
2081 /* We found no match. */
2082 as_bad (_("suffix or operands invalid for `%s'"),
2083 current_templates
->start
->name
);
2087 if (!quiet_warnings
)
2090 && ((i
.types
[0] & JumpAbsolute
)
2091 != (t
->operand_types
[0] & JumpAbsolute
)))
2093 as_warn (_("indirect %s without `*'"), t
->name
);
2096 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2097 == (IsPrefix
| IgnoreSize
))
2099 /* Warn them that a data or address size prefix doesn't
2100 affect assembly of the next line of code. */
2101 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2105 /* Copy the template we found. */
2107 if (found_reverse_match
)
2109 /* If we found a reverse match we must alter the opcode
2110 direction bit. found_reverse_match holds bits to change
2111 (different for int & float insns). */
2113 i
.tm
.base_opcode
^= found_reverse_match
;
2115 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2116 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2125 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2126 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2128 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2130 as_bad (_("`%s' operand %d must use `%%es' segment"),
2135 /* There's only ever one segment override allowed per instruction.
2136 This instruction possibly has a legal segment override on the
2137 second operand, so copy the segment to where non-string
2138 instructions store it, allowing common code. */
2139 i
.seg
[0] = i
.seg
[1];
2141 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2143 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2145 as_bad (_("`%s' operand %d must use `%%es' segment"),
2157 /* If matched instruction specifies an explicit instruction mnemonic
2159 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2161 if (i
.tm
.opcode_modifier
& Size16
)
2162 i
.suffix
= WORD_MNEM_SUFFIX
;
2163 else if (i
.tm
.opcode_modifier
& Size64
)
2164 i
.suffix
= QWORD_MNEM_SUFFIX
;
2166 i
.suffix
= LONG_MNEM_SUFFIX
;
2168 else if (i
.reg_operands
)
2170 /* If there's no instruction mnemonic suffix we try to invent one
2171 based on register operands. */
2174 /* We take i.suffix from the last register operand specified,
2175 Destination register type is more significant than source
2178 for (op
= i
.operands
; --op
>= 0;)
2179 if ((i
.types
[op
] & Reg
)
2180 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2182 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2183 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2184 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2189 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2191 if (!check_byte_reg ())
2194 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2196 if (!check_long_reg ())
2199 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2201 if (!check_qword_reg ())
2204 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2206 if (!check_word_reg ())
2209 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2210 /* Do nothing if the instruction is going to ignore the prefix. */
2215 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2217 i
.suffix
= stackop_size
;
2220 /* Change the opcode based on the operand size given by i.suffix;
2221 We need not change things for byte insns. */
2223 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2225 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2229 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2231 /* It's not a byte, select word/dword operation. */
2232 if (i
.tm
.opcode_modifier
& W
)
2234 if (i
.tm
.opcode_modifier
& ShortForm
)
2235 i
.tm
.base_opcode
|= 8;
2237 i
.tm
.base_opcode
|= 1;
2240 /* Now select between word & dword operations via the operand
2241 size prefix, except for instructions that will ignore this
2243 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2244 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2245 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2247 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2248 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2249 prefix
= ADDR_PREFIX_OPCODE
;
2251 if (!add_prefix (prefix
))
2255 if (i
.suffix
!= QWORD_MNEM_SUFFIX
&& (flag_code
== CODE_64BIT
)
2256 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2257 && (i
.tm
.opcode_modifier
& JumpByte
))
2259 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2263 /* Set mode64 for an operand. */
2264 if (i
.suffix
== QWORD_MNEM_SUFFIX
2265 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2267 i
.rex
|= REX_MODE64
;
2268 if (flag_code
< CODE_64BIT
)
2270 as_bad (_("64bit operations available only in 64bit modes."));
2275 /* Size floating point instruction. */
2276 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2278 if (i
.tm
.opcode_modifier
& FloatMF
)
2279 i
.tm
.base_opcode
^= 4;
2290 for (op
= i
.operands
; --op
>= 0;)
2292 /* If this is an eight bit register, it's OK. If it's the 16 or
2293 32 bit version of an eight bit register, we will just use the
2294 low portion, and that's OK too. */
2295 if (i
.types
[op
] & Reg8
)
2298 /* movzx and movsx should not generate this warning. */
2300 && (i
.tm
.base_opcode
== 0xfb7
2301 || i
.tm
.base_opcode
== 0xfb6
2302 || i
.tm
.base_opcode
== 0x63
2303 || i
.tm
.base_opcode
== 0xfbe
2304 || i
.tm
.base_opcode
== 0xfbf))
2307 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2309 /* Check that the template allows eight bit regs. This
2310 kills insns such as `orb $1,%edx', which maybe should be
2312 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2316 /* Prohibit these changes in the 64bit mode, since the
2317 lowering is more complicated. */
2318 if (flag_code
== CODE_64BIT
2319 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2321 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2322 i
.op
[op
].regs
->reg_name
,
2326 #if REGISTER_WARNINGS
2328 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2329 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2330 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2331 ? REGNAM_AL
- REGNAM_AX
2332 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2333 i
.op
[op
].regs
->reg_name
,
2338 /* Any other register is bad. */
2339 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2341 | Control
| Debug
| Test
2342 | FloatReg
| FloatAcc
))
2344 as_bad (_("`%%%s' not allowed with `%s%c'"),
2345 i
.op
[op
].regs
->reg_name
,
2359 for (op
= i
.operands
; --op
>= 0;)
2360 /* Reject eight bit registers, except where the template requires
2361 them. (eg. movzb) */
2362 if ((i
.types
[op
] & Reg8
) != 0
2363 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2365 as_bad (_("`%%%s' not allowed with `%s%c'"),
2366 i
.op
[op
].regs
->reg_name
,
2371 /* Warn if the e prefix on a general reg is missing. */
2372 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2373 && (i
.types
[op
] & Reg16
) != 0
2374 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2376 /* Prohibit these changes in the 64bit mode, since the
2377 lowering is more complicated. */
2378 if (flag_code
== CODE_64BIT
)
2380 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2381 i
.op
[op
].regs
->reg_name
,
2385 #if REGISTER_WARNINGS
2387 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2388 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2389 i
.op
[op
].regs
->reg_name
,
2393 /* Warn if the r prefix on a general reg is missing. */
2394 else if ((i
.types
[op
] & Reg64
) != 0
2395 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2397 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2398 i
.op
[op
].regs
->reg_name
,
2410 for (op
= i
.operands
; --op
>= 0; )
2411 /* Reject eight bit registers, except where the template requires
2412 them. (eg. movzb) */
2413 if ((i
.types
[op
] & Reg8
) != 0
2414 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2416 as_bad (_("`%%%s' not allowed with `%s%c'"),
2417 i
.op
[op
].regs
->reg_name
,
2422 /* Warn if the e prefix on a general reg is missing. */
2423 else if (((i
.types
[op
] & Reg16
) != 0
2424 || (i
.types
[op
] & Reg32
) != 0)
2425 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2427 /* Prohibit these changes in the 64bit mode, since the
2428 lowering is more complicated. */
2429 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2430 i
.op
[op
].regs
->reg_name
,
2441 for (op
= i
.operands
; --op
>= 0;)
2442 /* Reject eight bit registers, except where the template requires
2443 them. (eg. movzb) */
2444 if ((i
.types
[op
] & Reg8
) != 0
2445 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2447 as_bad (_("`%%%s' not allowed with `%s%c'"),
2448 i
.op
[op
].regs
->reg_name
,
2453 /* Warn if the e prefix on a general reg is present. */
2454 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2455 && (i
.types
[op
] & Reg32
) != 0
2456 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2458 /* Prohibit these changes in the 64bit mode, since the
2459 lowering is more complicated. */
2460 if (flag_code
== CODE_64BIT
)
2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2463 i
.op
[op
].regs
->reg_name
,
2468 #if REGISTER_WARNINGS
2469 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2470 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2471 i
.op
[op
].regs
->reg_name
,
2481 unsigned int overlap0
, overlap1
, overlap2
;
2483 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2484 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2485 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2486 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2487 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2491 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2493 : (i
.suffix
== WORD_MNEM_SUFFIX
2495 : (i
.suffix
== QWORD_MNEM_SUFFIX
2499 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2500 || overlap0
== (Imm16
| Imm32
)
2501 || overlap0
== (Imm16
| Imm32S
))
2503 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2506 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2507 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2508 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2510 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2514 i
.types
[0] = overlap0
;
2516 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2517 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2518 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2519 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2520 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2524 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2526 : (i
.suffix
== WORD_MNEM_SUFFIX
2528 : (i
.suffix
== QWORD_MNEM_SUFFIX
2532 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2533 || overlap1
== (Imm16
| Imm32
)
2534 || overlap1
== (Imm16
| Imm32S
))
2536 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2539 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2540 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2541 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2547 i
.types
[1] = overlap1
;
2549 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2550 assert ((overlap2
& Imm
) == 0);
2551 i
.types
[2] = overlap2
;
2559 /* Default segment register this instruction will use for memory
2560 accesses. 0 means unknown. This is only for optimizing out
2561 unnecessary segment overrides. */
2562 const seg_entry
*default_seg
= 0;
2564 /* The imul $imm, %reg instruction is converted into
2565 imul $imm, %reg, %reg, and the clr %reg instruction
2566 is converted into xor %reg, %reg. */
2567 if (i
.tm
.opcode_modifier
& regKludge
)
2569 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2570 /* Pretend we saw the extra register operand. */
2571 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2572 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2573 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2577 if (i
.tm
.opcode_modifier
& ShortForm
)
2579 /* The register or float register operand is in operand 0 or 1. */
2580 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2581 /* Register goes in low 3 bits of opcode. */
2582 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2583 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2585 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2587 /* Warn about some common errors, but press on regardless.
2588 The first case can be generated by gcc (<= 2.8.1). */
2589 if (i
.operands
== 2)
2591 /* Reversed arguments on faddp, fsubp, etc. */
2592 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2593 i
.op
[1].regs
->reg_name
,
2594 i
.op
[0].regs
->reg_name
);
2598 /* Extraneous `l' suffix on fp insn. */
2599 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2600 i
.op
[0].regs
->reg_name
);
2604 else if (i
.tm
.opcode_modifier
& Modrm
)
2606 /* The opcode is completed (modulo i.tm.extension_opcode which
2607 must be put into the modrm byte).
2608 Now, we make the modrm & index base bytes based on all the
2609 info we've collected. */
2611 default_seg
= build_modrm_byte ();
2613 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2615 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2616 && i
.op
[0].regs
->reg_num
== 1)
2618 as_bad (_("you can't `pop %%cs'"));
2621 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2622 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2625 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2629 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2631 /* For the string instructions that allow a segment override
2632 on one of their operands, the default segment is ds. */
2636 /* If a segment was explicitly specified,
2637 and the specified segment is not the default,
2638 use an opcode prefix to select it.
2639 If we never figured out what the default segment is,
2640 then default_seg will be zero at this point,
2641 and the specified segment prefix will always be used. */
2642 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2644 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2650 static const seg_entry
*
2653 const seg_entry
*default_seg
= 0;
2655 /* i.reg_operands MUST be the number of real register operands;
2656 implicit registers do not count. */
2657 if (i
.reg_operands
== 2)
2659 unsigned int source
, dest
;
2660 source
= ((i
.types
[0]
2661 & (Reg
| RegMMX
| RegXMM
2663 | Control
| Debug
| Test
))
2668 /* One of the register operands will be encoded in the i.tm.reg
2669 field, the other in the combined i.tm.mode and i.tm.regmem
2670 fields. If no form of this instruction supports a memory
2671 destination operand, then we assume the source operand may
2672 sometimes be a memory operand and so we need to store the
2673 destination in the i.rm.reg field. */
2674 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2676 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2677 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2678 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2680 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2685 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2686 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2687 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2689 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2694 { /* If it's not 2 reg operands... */
2697 unsigned int fake_zero_displacement
= 0;
2698 unsigned int op
= ((i
.types
[0] & AnyMem
)
2700 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2704 if (i
.base_reg
== 0)
2707 if (!i
.disp_operands
)
2708 fake_zero_displacement
= 1;
2709 if (i
.index_reg
== 0)
2711 /* Operand is just <disp> */
2712 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2713 && (flag_code
!= CODE_64BIT
))
2715 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2716 i
.types
[op
] &= ~Disp
;
2717 i
.types
[op
] |= Disp16
;
2719 else if (flag_code
!= CODE_64BIT
2720 || (i
.prefix
[ADDR_PREFIX
] != 0))
2722 i
.rm
.regmem
= NO_BASE_REGISTER
;
2723 i
.types
[op
] &= ~Disp
;
2724 i
.types
[op
] |= Disp32
;
2728 /* 64bit mode overwrites the 32bit absolute
2729 addressing by RIP relative addressing and
2730 absolute addressing is encoded by one of the
2731 redundant SIB forms. */
2732 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2733 i
.sib
.base
= NO_BASE_REGISTER
;
2734 i
.sib
.index
= NO_INDEX_REGISTER
;
2735 i
.types
[op
] &= ~Disp
;
2736 i
.types
[op
] |= Disp32S
;
2739 else /* !i.base_reg && i.index_reg */
2741 i
.sib
.index
= i
.index_reg
->reg_num
;
2742 i
.sib
.base
= NO_BASE_REGISTER
;
2743 i
.sib
.scale
= i
.log2_scale_factor
;
2744 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2745 i
.types
[op
] &= ~Disp
;
2746 if (flag_code
!= CODE_64BIT
)
2747 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2749 i
.types
[op
] |= Disp32S
;
2750 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2754 /* RIP addressing for 64bit mode. */
2755 else if (i
.base_reg
->reg_type
== BaseIndex
)
2757 i
.rm
.regmem
= NO_BASE_REGISTER
;
2758 i
.types
[op
] &= ~Disp
;
2759 i
.types
[op
] |= Disp32S
;
2760 i
.flags
[op
] = Operand_PCrel
;
2762 else if (i
.base_reg
->reg_type
& Reg16
)
2764 switch (i
.base_reg
->reg_num
)
2767 if (i
.index_reg
== 0)
2769 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2770 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2774 if (i
.index_reg
== 0)
2777 if ((i
.types
[op
] & Disp
) == 0)
2779 /* fake (%bp) into 0(%bp) */
2780 i
.types
[op
] |= Disp8
;
2781 fake_zero_displacement
= 1;
2784 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2785 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2787 default: /* (%si) -> 4 or (%di) -> 5 */
2788 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2790 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2792 else /* i.base_reg and 32/64 bit mode */
2794 if (flag_code
== CODE_64BIT
2795 && (i
.types
[op
] & Disp
))
2797 if (i
.types
[op
] & Disp8
)
2798 i
.types
[op
] = Disp8
| Disp32S
;
2800 i
.types
[op
] = Disp32S
;
2802 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2803 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2805 i
.sib
.base
= i
.base_reg
->reg_num
;
2806 /* x86-64 ignores REX prefix bit here to avoid decoder
2808 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2811 if (i
.disp_operands
== 0)
2813 fake_zero_displacement
= 1;
2814 i
.types
[op
] |= Disp8
;
2817 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2821 i
.sib
.scale
= i
.log2_scale_factor
;
2822 if (i
.index_reg
== 0)
2824 /* <disp>(%esp) becomes two byte modrm with no index
2825 register. We've already stored the code for esp
2826 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2827 Any base register besides %esp will not use the
2828 extra modrm byte. */
2829 i
.sib
.index
= NO_INDEX_REGISTER
;
2830 #if !SCALE1_WHEN_NO_INDEX
2831 /* Another case where we force the second modrm byte. */
2832 if (i
.log2_scale_factor
)
2833 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2838 i
.sib
.index
= i
.index_reg
->reg_num
;
2839 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2840 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2843 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2846 if (fake_zero_displacement
)
2848 /* Fakes a zero displacement assuming that i.types[op]
2849 holds the correct displacement size. */
2852 assert (i
.op
[op
].disps
== 0);
2853 exp
= &disp_expressions
[i
.disp_operands
++];
2854 i
.op
[op
].disps
= exp
;
2855 exp
->X_op
= O_constant
;
2856 exp
->X_add_number
= 0;
2857 exp
->X_add_symbol
= (symbolS
*) 0;
2858 exp
->X_op_symbol
= (symbolS
*) 0;
2862 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2863 (if any) based on i.tm.extension_opcode. Again, we must be
2864 careful to make sure that segment/control/debug/test/MMX
2865 registers are coded into the i.rm.reg field. */
2870 & (Reg
| RegMMX
| RegXMM
2872 | Control
| Debug
| Test
))
2875 & (Reg
| RegMMX
| RegXMM
2877 | Control
| Debug
| Test
))
2880 /* If there is an extension opcode to put here, the register
2881 number must be put into the regmem field. */
2882 if (i
.tm
.extension_opcode
!= None
)
2884 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2885 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2890 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2891 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2895 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2896 must set it to 3 to indicate this is a register operand
2897 in the regmem field. */
2898 if (!i
.mem_operands
)
2902 /* Fill in i.rm.reg field with extension opcode (if any). */
2903 if (i
.tm
.extension_opcode
!= None
)
2904 i
.rm
.reg
= i
.tm
.extension_opcode
;
2915 relax_substateT subtype
;
2920 if (flag_code
== CODE_16BIT
)
2924 if (i
.prefix
[DATA_PREFIX
] != 0)
2930 /* Pentium4 branch hints. */
2931 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2932 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2937 if (i
.prefix
[REX_PREFIX
] != 0)
2943 if (i
.prefixes
!= 0 && !intel_syntax
)
2944 as_warn (_("skipping prefixes on this instruction"));
2946 /* It's always a symbol; End frag & setup for relax.
2947 Make sure there is enough room in this frag for the largest
2948 instruction we may generate in md_convert_frag. This is 2
2949 bytes for the opcode and room for the prefix and largest
2951 frag_grow (prefix
+ 2 + 4);
2952 /* Prefix and 1 opcode byte go in fr_fix. */
2953 p
= frag_more (prefix
+ 1);
2954 if (i
.prefix
[DATA_PREFIX
] != 0)
2955 *p
++ = DATA_PREFIX_OPCODE
;
2956 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2957 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2958 *p
++ = i
.prefix
[SEG_PREFIX
];
2959 if (i
.prefix
[REX_PREFIX
] != 0)
2960 *p
++ = i
.prefix
[REX_PREFIX
];
2961 *p
= i
.tm
.base_opcode
;
2963 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2964 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2965 else if ((cpu_arch_flags
& Cpu386
) != 0)
2966 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2968 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2971 sym
= i
.op
[0].disps
->X_add_symbol
;
2972 off
= i
.op
[0].disps
->X_add_number
;
2974 if (i
.op
[0].disps
->X_op
!= O_constant
2975 && i
.op
[0].disps
->X_op
!= O_symbol
)
2977 /* Handle complex expressions. */
2978 sym
= make_expr_symbol (i
.op
[0].disps
);
2982 /* 1 possible extra opcode + 4 byte displacement go in var part.
2983 Pass reloc in fr_var. */
2984 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2993 if (i
.tm
.opcode_modifier
& JumpByte
)
2995 /* This is a loop or jecxz type instruction. */
2997 if (i
.prefix
[ADDR_PREFIX
] != 0)
2999 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3002 /* Pentium4 branch hints. */
3003 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3004 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3006 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3015 if (flag_code
== CODE_16BIT
)
3018 if (i
.prefix
[DATA_PREFIX
] != 0)
3020 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3030 if (i
.prefix
[REX_PREFIX
] != 0)
3032 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3036 if (i
.prefixes
!= 0 && !intel_syntax
)
3037 as_warn (_("skipping prefixes on this instruction"));
3039 p
= frag_more (1 + size
);
3040 *p
++ = i
.tm
.base_opcode
;
3042 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3043 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3047 output_interseg_jump ()
3055 if (flag_code
== CODE_16BIT
)
3059 if (i
.prefix
[DATA_PREFIX
] != 0)
3065 if (i
.prefix
[REX_PREFIX
] != 0)
3075 if (i
.prefixes
!= 0 && !intel_syntax
)
3076 as_warn (_("skipping prefixes on this instruction"));
3078 /* 1 opcode; 2 segment; offset */
3079 p
= frag_more (prefix
+ 1 + 2 + size
);
3081 if (i
.prefix
[DATA_PREFIX
] != 0)
3082 *p
++ = DATA_PREFIX_OPCODE
;
3084 if (i
.prefix
[REX_PREFIX
] != 0)
3085 *p
++ = i
.prefix
[REX_PREFIX
];
3087 *p
++ = i
.tm
.base_opcode
;
3088 if (i
.op
[1].imms
->X_op
== O_constant
)
3090 offsetT n
= i
.op
[1].imms
->X_add_number
;
3093 && !fits_in_unsigned_word (n
)
3094 && !fits_in_signed_word (n
))
3096 as_bad (_("16-bit jump out of range"));
3099 md_number_to_chars (p
, n
, size
);
3102 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3103 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3104 if (i
.op
[0].imms
->X_op
!= O_constant
)
3105 as_bad (_("can't handle non absolute segment in `%s'"),
3107 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3113 /* Tie dwarf2 debug info to the address at the start of the insn.
3114 We can't do this after the insn has been output as the current
3115 frag may have been closed off. eg. by frag_var. */
3116 dwarf2_emit_insn (0);
3119 if (i
.tm
.opcode_modifier
& Jump
)
3121 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3123 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3124 output_interseg_jump ();
3127 /* Output normal instructions here. */
3131 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3132 byte for the SSE instructions to specify a prefix they require. */
3133 if (i
.tm
.base_opcode
& 0xff0000)
3134 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3136 /* The prefix bytes. */
3138 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3144 md_number_to_chars (p
, (valueT
) *q
, 1);
3148 /* Now the opcode; be careful about word order here! */
3149 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3151 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3156 /* Put out high byte first: can't use md_number_to_chars! */
3157 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3158 *p
= i
.tm
.base_opcode
& 0xff;
3161 /* Now the modrm byte and sib byte (if present). */
3162 if (i
.tm
.opcode_modifier
& Modrm
)
3165 md_number_to_chars (p
,
3166 (valueT
) (i
.rm
.regmem
<< 0
3170 /* If i.rm.regmem == ESP (4)
3171 && i.rm.mode != (Register mode)
3173 ==> need second modrm byte. */
3174 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3176 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3179 md_number_to_chars (p
,
3180 (valueT
) (i
.sib
.base
<< 0
3182 | i
.sib
.scale
<< 6),
3187 if (i
.disp_operands
)
3199 #endif /* DEBUG386 */
3208 for (n
= 0; n
< i
.operands
; n
++)
3210 if (i
.types
[n
] & Disp
)
3212 if (i
.op
[n
].disps
->X_op
== O_constant
)
3218 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3221 if (i
.types
[n
] & Disp8
)
3223 if (i
.types
[n
] & Disp64
)
3226 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3228 p
= frag_more (size
);
3229 md_number_to_chars (p
, val
, size
);
3235 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3237 /* The PC relative address is computed relative
3238 to the instruction boundary, so in case immediate
3239 fields follows, we need to adjust the value. */
3240 if (pcrel
&& i
.imm_operands
)
3245 for (n1
= 0; n1
< i
.operands
; n1
++)
3246 if (i
.types
[n1
] & Imm
)
3248 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3251 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3253 if (i
.types
[n1
] & Imm64
)
3258 /* We should find the immediate. */
3259 if (n1
== i
.operands
)
3261 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3264 if (i
.types
[n
] & Disp32S
)
3267 if (i
.types
[n
] & (Disp16
| Disp64
))
3270 if (i
.types
[n
] & Disp64
)
3274 p
= frag_more (size
);
3275 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3276 i
.op
[n
].disps
, pcrel
,
3277 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3289 for (n
= 0; n
< i
.operands
; n
++)
3291 if (i
.types
[n
] & Imm
)
3293 if (i
.op
[n
].imms
->X_op
== O_constant
)
3299 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3302 if (i
.types
[n
] & (Imm8
| Imm8S
))
3304 else if (i
.types
[n
] & Imm64
)
3307 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3309 p
= frag_more (size
);
3310 md_number_to_chars (p
, val
, size
);
3314 /* Not absolute_section.
3315 Need a 32-bit fixup (don't support 8bit
3316 non-absolute imms). Try to support other
3318 RELOC_ENUM reloc_type
;
3322 if ((i
.types
[n
] & (Imm32S
))
3323 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3325 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3328 if (i
.types
[n
] & (Imm8
| Imm8S
))
3330 if (i
.types
[n
] & Imm64
)
3334 p
= frag_more (size
);
3335 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3336 #ifdef BFD_ASSEMBLER
3337 if (reloc_type
== BFD_RELOC_32
3339 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3340 && (i
.op
[n
].imms
->X_op
== O_symbol
3341 || (i
.op
[n
].imms
->X_op
== O_add
3342 && ((symbol_get_value_expression
3343 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3346 /* We don't support dynamic linking on x86-64 yet. */
3347 if (flag_code
== CODE_64BIT
)
3349 reloc_type
= BFD_RELOC_386_GOTPC
;
3350 i
.op
[n
].imms
->X_add_number
+= 3;
3353 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3354 i
.op
[n
].imms
, 0, reloc_type
);
3361 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3363 /* Parse operands of the form
3364 <symbol>@GOTOFF+<nnn>
3365 and similar .plt or .got references.
3367 If we find one, set up the correct relocation in RELOC and copy the
3368 input string, minus the `@GOTOFF' into a malloc'd buffer for
3369 parsing by the calling routine. Return this buffer, and if ADJUST
3370 is non-null set it to the length of the string we removed from the
3371 input line. Otherwise return NULL. */
3373 lex_got (reloc
, adjust
)
3377 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3378 static const struct {
3380 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3382 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3383 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3384 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3385 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, 0 } },
3386 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3387 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, 0 } },
3388 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, 0 } },
3389 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3390 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, 0 } },
3391 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3396 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3397 if (is_end_of_line
[(unsigned char) *cp
])
3400 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3404 len
= strlen (gotrel
[j
].str
);
3405 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3407 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3410 char *tmpbuf
, *past_reloc
;
3412 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3416 if (GOT_symbol
== NULL
)
3417 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3419 /* Replace the relocation token with ' ', so that
3420 errors like foo@GOTOFF1 will be detected. */
3422 /* The length of the first part of our input line. */
3423 first
= cp
- input_line_pointer
;
3425 /* The second part goes from after the reloc token until
3426 (and including) an end_of_line char. Don't use strlen
3427 here as the end_of_line char may not be a NUL. */
3428 past_reloc
= cp
+ 1 + len
;
3429 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3431 second
= cp
- past_reloc
;
3433 /* Allocate and copy string. The trailing NUL shouldn't
3434 be necessary, but be safe. */
3435 tmpbuf
= xmalloc (first
+ second
+ 2);
3436 memcpy (tmpbuf
, input_line_pointer
, first
);
3437 tmpbuf
[first
] = ' ';
3438 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3439 tmpbuf
[first
+ second
+ 1] = '\0';
3443 as_bad (_("@%s reloc is not supported in %s bit mode"),
3444 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3449 /* Might be a symbol version string. Don't as_bad here. */
3453 /* x86_cons_fix_new is called via the expression parsing code when a
3454 reloc is needed. We use this hook to get the correct .got reloc. */
3455 static RELOC_ENUM got_reloc
= NO_RELOC
;
3458 x86_cons_fix_new (frag
, off
, len
, exp
)
3464 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3465 got_reloc
= NO_RELOC
;
3466 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3470 x86_cons (exp
, size
)
3476 /* Handle @GOTOFF and the like in an expression. */
3478 char *gotfree_input_line
;
3481 save
= input_line_pointer
;
3482 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3483 if (gotfree_input_line
)
3484 input_line_pointer
= gotfree_input_line
;
3488 if (gotfree_input_line
)
3490 /* expression () has merrily parsed up to the end of line,
3491 or a comma - in the wrong buffer. Transfer how far
3492 input_line_pointer has moved to the right buffer. */
3493 input_line_pointer
= (save
3494 + (input_line_pointer
- gotfree_input_line
)
3496 free (gotfree_input_line
);
3504 static int i386_immediate
PARAMS ((char *));
3507 i386_immediate (imm_start
)
3510 char *save_input_line_pointer
;
3512 char *gotfree_input_line
;
3517 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3519 as_bad (_("only 1 or 2 immediate operands are allowed"));
3523 exp
= &im_expressions
[i
.imm_operands
++];
3524 i
.op
[this_operand
].imms
= exp
;
3526 if (is_space_char (*imm_start
))
3529 save_input_line_pointer
= input_line_pointer
;
3530 input_line_pointer
= imm_start
;
3533 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3534 if (gotfree_input_line
)
3535 input_line_pointer
= gotfree_input_line
;
3538 exp_seg
= expression (exp
);
3541 if (*input_line_pointer
)
3542 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3544 input_line_pointer
= save_input_line_pointer
;
3546 if (gotfree_input_line
)
3547 free (gotfree_input_line
);
3550 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3552 /* Missing or bad expr becomes absolute 0. */
3553 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3555 exp
->X_op
= O_constant
;
3556 exp
->X_add_number
= 0;
3557 exp
->X_add_symbol
= (symbolS
*) 0;
3558 exp
->X_op_symbol
= (symbolS
*) 0;
3560 else if (exp
->X_op
== O_constant
)
3562 /* Size it properly later. */
3563 i
.types
[this_operand
] |= Imm64
;
3564 /* If BFD64, sign extend val. */
3565 if (!use_rela_relocations
)
3566 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3567 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3569 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3571 #ifdef BFD_ASSEMBLER
3572 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3574 && exp_seg
!= text_section
3575 && exp_seg
!= data_section
3576 && exp_seg
!= bss_section
3577 && exp_seg
!= undefined_section
3578 #ifdef BFD_ASSEMBLER
3579 && !bfd_is_com_section (exp_seg
)
3583 #ifdef BFD_ASSEMBLER
3584 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3586 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3593 /* This is an address. The size of the address will be
3594 determined later, depending on destination register,
3595 suffix, or the default for the section. */
3596 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3602 static char *i386_scale
PARAMS ((char *));
3609 char *save
= input_line_pointer
;
3611 input_line_pointer
= scale
;
3612 val
= get_absolute_expression ();
3618 i
.log2_scale_factor
= 0;
3621 i
.log2_scale_factor
= 1;
3624 i
.log2_scale_factor
= 2;
3627 i
.log2_scale_factor
= 3;
3630 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3632 input_line_pointer
= save
;
3635 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3637 as_warn (_("scale factor of %d without an index register"),
3638 1 << i
.log2_scale_factor
);
3639 #if SCALE1_WHEN_NO_INDEX
3640 i
.log2_scale_factor
= 0;
3643 scale
= input_line_pointer
;
3644 input_line_pointer
= save
;
3648 static int i386_displacement
PARAMS ((char *, char *));
3651 i386_displacement (disp_start
, disp_end
)
3657 char *save_input_line_pointer
;
3659 char *gotfree_input_line
;
3661 int bigdisp
= Disp32
;
3663 if (flag_code
== CODE_64BIT
)
3665 if (i
.prefix
[ADDR_PREFIX
] == 0)
3668 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3670 i
.types
[this_operand
] |= bigdisp
;
3672 exp
= &disp_expressions
[i
.disp_operands
];
3673 i
.op
[this_operand
].disps
= exp
;
3675 save_input_line_pointer
= input_line_pointer
;
3676 input_line_pointer
= disp_start
;
3677 END_STRING_AND_SAVE (disp_end
);
3679 #ifndef GCC_ASM_O_HACK
3680 #define GCC_ASM_O_HACK 0
3683 END_STRING_AND_SAVE (disp_end
+ 1);
3684 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3685 && displacement_string_end
[-1] == '+')
3687 /* This hack is to avoid a warning when using the "o"
3688 constraint within gcc asm statements.
3691 #define _set_tssldt_desc(n,addr,limit,type) \
3692 __asm__ __volatile__ ( \
3694 "movw %w1,2+%0\n\t" \
3696 "movb %b1,4+%0\n\t" \
3697 "movb %4,5+%0\n\t" \
3698 "movb $0,6+%0\n\t" \
3699 "movb %h1,7+%0\n\t" \
3701 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3703 This works great except that the output assembler ends
3704 up looking a bit weird if it turns out that there is
3705 no offset. You end up producing code that looks like:
3718 So here we provide the missing zero. */
3720 *displacement_string_end
= '0';
3724 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3725 if (gotfree_input_line
)
3726 input_line_pointer
= gotfree_input_line
;
3729 exp_seg
= expression (exp
);
3732 if (*input_line_pointer
)
3733 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3735 RESTORE_END_STRING (disp_end
+ 1);
3737 RESTORE_END_STRING (disp_end
);
3738 input_line_pointer
= save_input_line_pointer
;
3740 if (gotfree_input_line
)
3741 free (gotfree_input_line
);
3744 #ifdef BFD_ASSEMBLER
3745 /* We do this to make sure that the section symbol is in
3746 the symbol table. We will ultimately change the relocation
3747 to be relative to the beginning of the section. */
3748 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3749 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3751 if (exp
->X_op
!= O_symbol
)
3753 as_bad (_("bad expression used with @%s"),
3754 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3760 if (S_IS_LOCAL (exp
->X_add_symbol
)
3761 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3762 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3763 exp
->X_op
= O_subtract
;
3764 exp
->X_op_symbol
= GOT_symbol
;
3765 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3766 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3768 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3772 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3774 /* Missing or bad expr becomes absolute 0. */
3775 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3777 exp
->X_op
= O_constant
;
3778 exp
->X_add_number
= 0;
3779 exp
->X_add_symbol
= (symbolS
*) 0;
3780 exp
->X_op_symbol
= (symbolS
*) 0;
3783 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3784 if (exp
->X_op
!= O_constant
3785 #ifdef BFD_ASSEMBLER
3786 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3788 && exp_seg
!= text_section
3789 && exp_seg
!= data_section
3790 && exp_seg
!= bss_section
3791 && exp_seg
!= undefined_section
)
3793 #ifdef BFD_ASSEMBLER
3794 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3796 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3801 else if (flag_code
== CODE_64BIT
)
3802 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3806 static int i386_index_check
PARAMS ((const char *));
3808 /* Make sure the memory operand we've been dealt is valid.
3809 Return 1 on success, 0 on a failure. */
3812 i386_index_check (operand_string
)
3813 const char *operand_string
;
3816 #if INFER_ADDR_PREFIX
3822 if (flag_code
== CODE_64BIT
)
3824 if (i
.prefix
[ADDR_PREFIX
] == 0)
3828 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3829 && (i
.base_reg
->reg_type
!= BaseIndex
3832 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3833 != (Reg64
| BaseIndex
))))
3840 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3842 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3843 != (Reg32
| BaseIndex
))))
3849 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3853 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3854 != (Reg16
| BaseIndex
)))
3856 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3857 != (Reg16
| BaseIndex
))
3859 && i
.base_reg
->reg_num
< 6
3860 && i
.index_reg
->reg_num
>= 6
3861 && i
.log2_scale_factor
== 0))))
3868 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3870 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3871 != (Reg32
| BaseIndex
))))
3877 #if INFER_ADDR_PREFIX
3878 if (flag_code
!= CODE_64BIT
3879 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3881 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3883 /* Change the size of any displacement too. At most one of
3884 Disp16 or Disp32 is set.
3885 FIXME. There doesn't seem to be any real need for separate
3886 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3887 Removing them would probably clean up the code quite a lot. */
3888 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3889 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3894 as_bad (_("`%s' is not a valid base/index expression"),
3898 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3900 flag_code_names
[flag_code
]);
3906 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3910 i386_operand (operand_string
)
3911 char *operand_string
;
3915 char *op_string
= operand_string
;
3917 if (is_space_char (*op_string
))
3920 /* We check for an absolute prefix (differentiating,
3921 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3922 if (*op_string
== ABSOLUTE_PREFIX
)
3925 if (is_space_char (*op_string
))
3927 i
.types
[this_operand
] |= JumpAbsolute
;
3930 /* Check if operand is a register. */
3931 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3932 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3934 /* Check for a segment override by searching for ':' after a
3935 segment register. */
3937 if (is_space_char (*op_string
))
3939 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3944 i
.seg
[i
.mem_operands
] = &es
;
3947 i
.seg
[i
.mem_operands
] = &cs
;
3950 i
.seg
[i
.mem_operands
] = &ss
;
3953 i
.seg
[i
.mem_operands
] = &ds
;
3956 i
.seg
[i
.mem_operands
] = &fs
;
3959 i
.seg
[i
.mem_operands
] = &gs
;
3963 /* Skip the ':' and whitespace. */
3965 if (is_space_char (*op_string
))
3968 if (!is_digit_char (*op_string
)
3969 && !is_identifier_char (*op_string
)
3970 && *op_string
!= '('
3971 && *op_string
!= ABSOLUTE_PREFIX
)
3973 as_bad (_("bad memory operand `%s'"), op_string
);
3976 /* Handle case of %es:*foo. */
3977 if (*op_string
== ABSOLUTE_PREFIX
)
3980 if (is_space_char (*op_string
))
3982 i
.types
[this_operand
] |= JumpAbsolute
;
3984 goto do_memory_reference
;
3988 as_bad (_("junk `%s' after register"), op_string
);
3991 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3992 i
.op
[this_operand
].regs
= r
;
3995 else if (*op_string
== REGISTER_PREFIX
)
3997 as_bad (_("bad register name `%s'"), op_string
);
4000 else if (*op_string
== IMMEDIATE_PREFIX
)
4003 if (i
.types
[this_operand
] & JumpAbsolute
)
4005 as_bad (_("immediate operand illegal with absolute jump"));
4008 if (!i386_immediate (op_string
))
4011 else if (is_digit_char (*op_string
)
4012 || is_identifier_char (*op_string
)
4013 || *op_string
== '(')
4015 /* This is a memory reference of some sort. */
4018 /* Start and end of displacement string expression (if found). */
4019 char *displacement_string_start
;
4020 char *displacement_string_end
;
4022 do_memory_reference
:
4023 if ((i
.mem_operands
== 1
4024 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4025 || i
.mem_operands
== 2)
4027 as_bad (_("too many memory references for `%s'"),
4028 current_templates
->start
->name
);
4032 /* Check for base index form. We detect the base index form by
4033 looking for an ')' at the end of the operand, searching
4034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4036 base_string
= op_string
+ strlen (op_string
);
4039 if (is_space_char (*base_string
))
4042 /* If we only have a displacement, set-up for it to be parsed later. */
4043 displacement_string_start
= op_string
;
4044 displacement_string_end
= base_string
+ 1;
4046 if (*base_string
== ')')
4049 unsigned int parens_balanced
= 1;
4050 /* We've already checked that the number of left & right ()'s are
4051 equal, so this loop will not be infinite. */
4055 if (*base_string
== ')')
4057 if (*base_string
== '(')
4060 while (parens_balanced
);
4062 temp_string
= base_string
;
4064 /* Skip past '(' and whitespace. */
4066 if (is_space_char (*base_string
))
4069 if (*base_string
== ','
4070 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4071 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4073 displacement_string_end
= temp_string
;
4075 i
.types
[this_operand
] |= BaseIndex
;
4079 base_string
= end_op
;
4080 if (is_space_char (*base_string
))
4084 /* There may be an index reg or scale factor here. */
4085 if (*base_string
== ',')
4088 if (is_space_char (*base_string
))
4091 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4092 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4094 base_string
= end_op
;
4095 if (is_space_char (*base_string
))
4097 if (*base_string
== ',')
4100 if (is_space_char (*base_string
))
4103 else if (*base_string
!= ')')
4105 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4110 else if (*base_string
== REGISTER_PREFIX
)
4112 as_bad (_("bad register name `%s'"), base_string
);
4116 /* Check for scale factor. */
4117 if (*base_string
!= ')')
4119 char *end_scale
= i386_scale (base_string
);
4124 base_string
= end_scale
;
4125 if (is_space_char (*base_string
))
4127 if (*base_string
!= ')')
4129 as_bad (_("expecting `)' after scale factor in `%s'"),
4134 else if (!i
.index_reg
)
4136 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4141 else if (*base_string
!= ')')
4143 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4148 else if (*base_string
== REGISTER_PREFIX
)
4150 as_bad (_("bad register name `%s'"), base_string
);
4155 /* If there's an expression beginning the operand, parse it,
4156 assuming displacement_string_start and
4157 displacement_string_end are meaningful. */
4158 if (displacement_string_start
!= displacement_string_end
)
4160 if (!i386_displacement (displacement_string_start
,
4161 displacement_string_end
))
4165 /* Special case for (%dx) while doing input/output op. */
4167 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4169 && i
.log2_scale_factor
== 0
4170 && i
.seg
[i
.mem_operands
] == 0
4171 && (i
.types
[this_operand
] & Disp
) == 0)
4173 i
.types
[this_operand
] = InOutPortReg
;
4177 if (i386_index_check (operand_string
) == 0)
4183 /* It's not a memory operand; argh! */
4184 as_bad (_("invalid char %s beginning operand %d `%s'"),
4185 output_invalid (*op_string
),
4190 return 1; /* Normal return. */
4193 /* md_estimate_size_before_relax()
4195 Called just before relax() for rs_machine_dependent frags. The x86
4196 assembler uses these frags to handle variable size jump
4199 Any symbol that is now undefined will not become defined.
4200 Return the correct fr_subtype in the frag.
4201 Return the initial "guess for variable size of frag" to caller.
4202 The guess is actually the growth beyond the fixed part. Whatever
4203 we do to grow the fixed or variable part contributes to our
4207 md_estimate_size_before_relax (fragP
, segment
)
4211 /* We've already got fragP->fr_subtype right; all we have to do is
4212 check for un-relaxable symbols. On an ELF system, we can't relax
4213 an externally visible symbol, because it may be overridden by a
4215 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4217 || S_IS_EXTERNAL (fragP
->fr_symbol
)
4218 || S_IS_WEAK (fragP
->fr_symbol
)
4222 /* Symbol is undefined in this segment, or we need to keep a
4223 reloc so that weak symbols can be overridden. */
4224 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4225 RELOC_ENUM reloc_type
;
4226 unsigned char *opcode
;
4229 if (fragP
->fr_var
!= NO_RELOC
)
4230 reloc_type
= fragP
->fr_var
;
4232 reloc_type
= BFD_RELOC_16_PCREL
;
4234 reloc_type
= BFD_RELOC_32_PCREL
;
4236 old_fr_fix
= fragP
->fr_fix
;
4237 opcode
= (unsigned char *) fragP
->fr_opcode
;
4239 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4242 /* Make jmp (0xeb) a (d)word displacement jump. */
4244 fragP
->fr_fix
+= size
;
4245 fix_new (fragP
, old_fr_fix
, size
,
4247 fragP
->fr_offset
, 1,
4253 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4255 /* Negate the condition, and branch past an
4256 unconditional jump. */
4259 /* Insert an unconditional jump. */
4261 /* We added two extra opcode bytes, and have a two byte
4263 fragP
->fr_fix
+= 2 + 2;
4264 fix_new (fragP
, old_fr_fix
+ 2, 2,
4266 fragP
->fr_offset
, 1,
4273 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4276 fix_new (fragP
, old_fr_fix
, 1,
4278 fragP
->fr_offset
, 1,
4283 /* This changes the byte-displacement jump 0x7N
4284 to the (d)word-displacement jump 0x0f,0x8N. */
4285 opcode
[1] = opcode
[0] + 0x10;
4286 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4287 /* We've added an opcode byte. */
4288 fragP
->fr_fix
+= 1 + size
;
4289 fix_new (fragP
, old_fr_fix
+ 1, size
,
4291 fragP
->fr_offset
, 1,
4296 BAD_CASE (fragP
->fr_subtype
);
4300 return fragP
->fr_fix
- old_fr_fix
;
4303 /* Guess size depending on current relax state. Initially the relax
4304 state will correspond to a short jump and we return 1, because
4305 the variable part of the frag (the branch offset) is one byte
4306 long. However, we can relax a section more than once and in that
4307 case we must either set fr_subtype back to the unrelaxed state,
4308 or return the value for the appropriate branch. */
4309 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4312 /* Called after relax() is finished.
4314 In: Address of frag.
4315 fr_type == rs_machine_dependent.
4316 fr_subtype is what the address relaxed to.
4318 Out: Any fixSs and constants are set up.
4319 Caller will turn frag into a ".space 0". */
4321 #ifndef BFD_ASSEMBLER
4323 md_convert_frag (headers
, sec
, fragP
)
4324 object_headers
*headers ATTRIBUTE_UNUSED
;
4325 segT sec ATTRIBUTE_UNUSED
;
4329 md_convert_frag (abfd
, sec
, fragP
)
4330 bfd
*abfd ATTRIBUTE_UNUSED
;
4331 segT sec ATTRIBUTE_UNUSED
;
4335 unsigned char *opcode
;
4336 unsigned char *where_to_put_displacement
= NULL
;
4337 offsetT target_address
;
4338 offsetT opcode_address
;
4339 unsigned int extension
= 0;
4340 offsetT displacement_from_opcode_start
;
4342 opcode
= (unsigned char *) fragP
->fr_opcode
;
4344 /* Address we want to reach in file space. */
4345 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4347 /* Address opcode resides at in file space. */
4348 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4350 /* Displacement from opcode start to fill into instruction. */
4351 displacement_from_opcode_start
= target_address
- opcode_address
;
4353 if ((fragP
->fr_subtype
& BIG
) == 0)
4355 /* Don't have to change opcode. */
4356 extension
= 1; /* 1 opcode + 1 displacement */
4357 where_to_put_displacement
= &opcode
[1];
4361 if (no_cond_jump_promotion
4362 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4363 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4365 switch (fragP
->fr_subtype
)
4367 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4368 extension
= 4; /* 1 opcode + 4 displacement */
4370 where_to_put_displacement
= &opcode
[1];
4373 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4374 extension
= 2; /* 1 opcode + 2 displacement */
4376 where_to_put_displacement
= &opcode
[1];
4379 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4380 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4381 extension
= 5; /* 2 opcode + 4 displacement */
4382 opcode
[1] = opcode
[0] + 0x10;
4383 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4384 where_to_put_displacement
= &opcode
[2];
4387 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4388 extension
= 3; /* 2 opcode + 2 displacement */
4389 opcode
[1] = opcode
[0] + 0x10;
4390 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4391 where_to_put_displacement
= &opcode
[2];
4394 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4399 where_to_put_displacement
= &opcode
[3];
4403 BAD_CASE (fragP
->fr_subtype
);
4408 /* Now put displacement after opcode. */
4409 md_number_to_chars ((char *) where_to_put_displacement
,
4410 (valueT
) (displacement_from_opcode_start
- extension
),
4411 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4412 fragP
->fr_fix
+= extension
;
4415 /* Size of byte displacement jmp. */
4416 int md_short_jump_size
= 2;
4418 /* Size of dword displacement jmp. */
4419 int md_long_jump_size
= 5;
4421 /* Size of relocation record. */
4422 const int md_reloc_size
= 8;
4425 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4427 addressT from_addr
, to_addr
;
4428 fragS
*frag ATTRIBUTE_UNUSED
;
4429 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4433 offset
= to_addr
- (from_addr
+ 2);
4434 /* Opcode for byte-disp jump. */
4435 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4436 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4440 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4442 addressT from_addr
, to_addr
;
4443 fragS
*frag ATTRIBUTE_UNUSED
;
4444 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4448 offset
= to_addr
- (from_addr
+ 5);
4449 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4450 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4453 /* Apply a fixup (fixS) to segment data, once it has been determined
4454 by our caller that we have all the info we need to fix it up.
4456 On the 386, immediates, displacements, and data pointers are all in
4457 the same (little-endian) format, so we don't need to care about which
4461 md_apply_fix3 (fixP
, valP
, seg
)
4462 /* The fix we're to put in. */
4464 /* Pointer to the value of the bits. */
4466 /* Segment fix is from. */
4467 segT seg ATTRIBUTE_UNUSED
;
4469 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4470 valueT value
= * valP
;
4472 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4475 switch (fixP
->fx_r_type
)
4481 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4484 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4487 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4492 /* This is a hack. There should be a better way to handle this.
4493 This covers for the fact that bfd_install_relocation will
4494 subtract the current location (for partial_inplace, PC relative
4495 relocations); see more below. */
4496 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4497 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4498 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4499 && fixP
->fx_addsy
&& !use_rela_relocations
)
4502 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4504 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4507 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4510 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4512 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4515 || (symbol_section_p (fixP
->fx_addsy
)
4516 && fseg
!= absolute_section
))
4517 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
4518 && !S_IS_WEAK (fixP
->fx_addsy
)
4519 && S_IS_DEFINED (fixP
->fx_addsy
)
4520 && !S_IS_COMMON (fixP
->fx_addsy
))
4522 /* Yes, we add the values in twice. This is because
4523 bfd_perform_relocation subtracts them out again. I think
4524 bfd_perform_relocation is broken, but I don't dare change
4526 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4530 #if defined (OBJ_COFF) && defined (TE_PE)
4531 /* For some reason, the PE format does not store a section
4532 address offset for a PC relative symbol. */
4533 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4534 value
+= md_pcrel_from (fixP
);
4538 /* Fix a few things - the dynamic linker expects certain values here,
4539 and we must not dissappoint it. */
4540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4541 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4543 switch (fixP
->fx_r_type
)
4545 case BFD_RELOC_386_PLT32
:
4546 case BFD_RELOC_X86_64_PLT32
:
4547 /* Make the jump instruction point to the address of the operand. At
4548 runtime we merely add the offset to the actual PLT entry. */
4551 case BFD_RELOC_386_GOTPC
:
4553 /* This is tough to explain. We end up with this one if we have
4554 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4555 * here is to obtain the absolute address of the GOT, and it is strongly
4556 * preferable from a performance point of view to avoid using a runtime
4557 * relocation for this. The actual sequence of instructions often look
4563 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4565 * The call and pop essentially return the absolute address of
4566 * the label .L66 and store it in %ebx. The linker itself will
4567 * ultimately change the first operand of the addl so that %ebx points to
4568 * the GOT, but to keep things simple, the .o file must have this operand
4569 * set so that it generates not the absolute address of .L66, but the
4570 * absolute address of itself. This allows the linker itself simply
4571 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4572 * added in, and the addend of the relocation is stored in the operand
4573 * field for the instruction itself.
4575 * Our job here is to fix the operand so that it would add the correct
4576 * offset so that %ebx would point to itself. The thing that is tricky is
4577 * that .-.L66 will point to the beginning of the instruction, so we need
4578 * to further modify the operand so that it will point to itself.
4579 * There are other cases where you have something like:
4581 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4583 * and here no correction would be required. Internally in the assembler
4584 * we treat operands of this form as not being pcrel since the '.' is
4585 * explicitly mentioned, and I wonder whether it would simplify matters
4586 * to do it this way. Who knows. In earlier versions of the PIC patches,
4587 * the pcrel_adjust field was used to store the correction, but since the
4588 * expression is not pcrel, I felt it would be confusing to do it this
4593 case BFD_RELOC_386_GOT32
:
4594 case BFD_RELOC_386_TLS_GD
:
4595 case BFD_RELOC_386_TLS_LDM
:
4596 case BFD_RELOC_386_TLS_LDO_32
:
4597 case BFD_RELOC_386_TLS_IE_32
:
4598 case BFD_RELOC_386_TLS_LE_32
:
4599 case BFD_RELOC_386_TLS_LE
:
4600 case BFD_RELOC_X86_64_GOT32
:
4601 value
= 0; /* Fully resolved at runtime. No addend. */
4603 case BFD_RELOC_386_GOTOFF
:
4604 case BFD_RELOC_X86_64_GOTPCREL
:
4607 case BFD_RELOC_VTABLE_INHERIT
:
4608 case BFD_RELOC_VTABLE_ENTRY
:
4615 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4617 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4619 /* Are we finished with this relocation now? */
4620 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4622 #ifdef BFD_ASSEMBLER
4623 else if (use_rela_relocations
)
4625 fixP
->fx_no_overflow
= 1;
4626 /* Remember value for tc_gen_reloc. */
4627 fixP
->fx_addnumber
= value
;
4631 md_number_to_chars (p
, value
, fixP
->fx_size
);
4634 #define MAX_LITTLENUMS 6
4636 /* Turn the string pointed to by litP into a floating point constant
4637 of type TYPE, and emit the appropriate bytes. The number of
4638 LITTLENUMS emitted is stored in *SIZEP. An error message is
4639 returned, or NULL on OK. */
4642 md_atof (type
, litP
, sizeP
)
4648 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4649 LITTLENUM_TYPE
*wordP
;
4671 return _("Bad call to md_atof ()");
4673 t
= atof_ieee (input_line_pointer
, type
, words
);
4675 input_line_pointer
= t
;
4677 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4678 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4679 the bigendian 386. */
4680 for (wordP
= words
+ prec
- 1; prec
--;)
4682 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4683 litP
+= sizeof (LITTLENUM_TYPE
);
4688 char output_invalid_buf
[8];
4695 sprintf (output_invalid_buf
, "'%c'", c
);
4697 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4698 return output_invalid_buf
;
4701 /* REG_STRING starts *before* REGISTER_PREFIX. */
4703 static const reg_entry
*
4704 parse_register (reg_string
, end_op
)
4708 char *s
= reg_string
;
4710 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4713 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4714 if (*s
== REGISTER_PREFIX
)
4717 if (is_space_char (*s
))
4721 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4723 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4724 return (const reg_entry
*) NULL
;
4728 /* For naked regs, make sure that we are not dealing with an identifier.
4729 This prevents confusing an identifier like `eax_var' with register
4731 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4732 return (const reg_entry
*) NULL
;
4736 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4738 /* Handle floating point regs, allowing spaces in the (i) part. */
4739 if (r
== i386_regtab
/* %st is first entry of table */)
4741 if (is_space_char (*s
))
4746 if (is_space_char (*s
))
4748 if (*s
>= '0' && *s
<= '7')
4750 r
= &i386_float_regtab
[*s
- '0'];
4752 if (is_space_char (*s
))
4760 /* We have "%st(" then garbage. */
4761 return (const reg_entry
*) NULL
;
4766 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4767 && flag_code
!= CODE_64BIT
)
4769 return (const reg_entry
*) NULL
;
4775 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4776 const char *md_shortopts
= "kVQ:sq";
4778 const char *md_shortopts
= "q";
4781 struct option md_longopts
[] = {
4782 #define OPTION_32 (OPTION_MD_BASE + 0)
4783 {"32", no_argument
, NULL
, OPTION_32
},
4784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4785 #define OPTION_64 (OPTION_MD_BASE + 1)
4786 {"64", no_argument
, NULL
, OPTION_64
},
4788 {NULL
, no_argument
, NULL
, 0}
4790 size_t md_longopts_size
= sizeof (md_longopts
);
4793 md_parse_option (c
, arg
)
4795 char *arg ATTRIBUTE_UNUSED
;
4803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4804 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4805 should be emitted or not. FIXME: Not implemented. */
4809 /* -V: SVR4 argument to print version ID. */
4811 print_version_id ();
4814 /* -k: Ignore for FreeBSD compatibility. */
4819 /* -s: On i386 Solaris, this tells the native assembler to use
4820 .stab instead of .stab.excl. We always use .stab anyhow. */
4825 const char **list
, **l
;
4827 list
= bfd_target_list ();
4828 for (l
= list
; *l
!= NULL
; l
++)
4829 if (strcmp (*l
, "elf64-x86-64") == 0)
4831 default_arch
= "x86_64";
4835 as_fatal (_("No compiled in support for x86_64"));
4842 default_arch
= "i386";
4852 md_show_usage (stream
)
4855 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4856 fprintf (stream
, _("\
4858 -V print assembler version number\n\
4860 -q quieten some warnings\n\
4863 fprintf (stream
, _("\
4864 -q quieten some warnings\n"));
4868 #ifdef BFD_ASSEMBLER
4869 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4870 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4872 /* Pick the target format to use. */
4875 i386_target_format ()
4877 if (!strcmp (default_arch
, "x86_64"))
4878 set_code_flag (CODE_64BIT
);
4879 else if (!strcmp (default_arch
, "i386"))
4880 set_code_flag (CODE_32BIT
);
4882 as_fatal (_("Unknown architecture"));
4883 switch (OUTPUT_FLAVOR
)
4885 #ifdef OBJ_MAYBE_AOUT
4886 case bfd_target_aout_flavour
:
4887 return AOUT_TARGET_FORMAT
;
4889 #ifdef OBJ_MAYBE_COFF
4890 case bfd_target_coff_flavour
:
4893 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4894 case bfd_target_elf_flavour
:
4896 if (flag_code
== CODE_64BIT
)
4897 use_rela_relocations
= 1;
4898 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4907 #endif /* OBJ_MAYBE_ more than one */
4909 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4910 void i386_elf_emit_arch_note ()
4912 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4913 && cpu_arch_name
!= NULL
)
4916 asection
*seg
= now_seg
;
4917 subsegT subseg
= now_subseg
;
4918 Elf_Internal_Note i_note
;
4919 Elf_External_Note e_note
;
4920 asection
*note_secp
;
4923 /* Create the .note section. */
4924 note_secp
= subseg_new (".note", 0);
4925 bfd_set_section_flags (stdoutput
,
4927 SEC_HAS_CONTENTS
| SEC_READONLY
);
4929 /* Process the arch string. */
4930 len
= strlen (cpu_arch_name
);
4932 i_note
.namesz
= len
+ 1;
4934 i_note
.type
= NT_ARCH
;
4935 p
= frag_more (sizeof (e_note
.namesz
));
4936 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4937 p
= frag_more (sizeof (e_note
.descsz
));
4938 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4939 p
= frag_more (sizeof (e_note
.type
));
4940 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4941 p
= frag_more (len
+ 1);
4942 strcpy (p
, cpu_arch_name
);
4944 frag_align (2, 0, 0);
4946 subseg_set (seg
, subseg
);
4950 #endif /* BFD_ASSEMBLER */
4953 md_undefined_symbol (name
)
4956 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4957 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4958 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4959 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4963 if (symbol_find (name
))
4964 as_bad (_("GOT already in symbol table"));
4965 GOT_symbol
= symbol_new (name
, undefined_section
,
4966 (valueT
) 0, &zero_address_frag
);
4973 /* Round up a section size to the appropriate boundary. */
4976 md_section_align (segment
, size
)
4977 segT segment ATTRIBUTE_UNUSED
;
4980 #ifdef BFD_ASSEMBLER
4981 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4982 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4984 /* For a.out, force the section size to be aligned. If we don't do
4985 this, BFD will align it for us, but it will not write out the
4986 final bytes of the section. This may be a bug in BFD, but it is
4987 easier to fix it here since that is how the other a.out targets
4991 align
= bfd_get_section_alignment (stdoutput
, segment
);
4992 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5000 /* On the i386, PC-relative offsets are relative to the start of the
5001 next instruction. That is, the address of the offset, plus its
5002 size, since the offset is always the last part of the insn. */
5005 md_pcrel_from (fixP
)
5008 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5015 int ignore ATTRIBUTE_UNUSED
;
5019 temp
= get_absolute_expression ();
5020 subseg_set (bss_section
, (subsegT
) temp
);
5021 demand_empty_rest_of_line ();
5026 #ifdef BFD_ASSEMBLER
5029 i386_validate_fix (fixp
)
5032 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5034 /* GOTOFF relocation are nonsense in 64bit mode. */
5035 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5037 if (flag_code
!= CODE_64BIT
)
5039 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5043 if (flag_code
== CODE_64BIT
)
5045 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5052 tc_gen_reloc (section
, fixp
)
5053 asection
*section ATTRIBUTE_UNUSED
;
5057 bfd_reloc_code_real_type code
;
5059 switch (fixp
->fx_r_type
)
5061 case BFD_RELOC_X86_64_PLT32
:
5062 case BFD_RELOC_X86_64_GOT32
:
5063 case BFD_RELOC_X86_64_GOTPCREL
:
5064 case BFD_RELOC_386_PLT32
:
5065 case BFD_RELOC_386_GOT32
:
5066 case BFD_RELOC_386_GOTOFF
:
5067 case BFD_RELOC_386_GOTPC
:
5068 case BFD_RELOC_386_TLS_GD
:
5069 case BFD_RELOC_386_TLS_LDM
:
5070 case BFD_RELOC_386_TLS_LDO_32
:
5071 case BFD_RELOC_386_TLS_IE_32
:
5072 case BFD_RELOC_386_TLS_LE_32
:
5073 case BFD_RELOC_386_TLS_LE
:
5074 case BFD_RELOC_X86_64_32S
:
5076 case BFD_RELOC_VTABLE_ENTRY
:
5077 case BFD_RELOC_VTABLE_INHERIT
:
5078 code
= fixp
->fx_r_type
;
5083 switch (fixp
->fx_size
)
5086 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5087 _("can not do %d byte pc-relative relocation"),
5089 code
= BFD_RELOC_32_PCREL
;
5091 case 1: code
= BFD_RELOC_8_PCREL
; break;
5092 case 2: code
= BFD_RELOC_16_PCREL
; break;
5093 case 4: code
= BFD_RELOC_32_PCREL
; break;
5098 switch (fixp
->fx_size
)
5101 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5102 _("can not do %d byte relocation"),
5104 code
= BFD_RELOC_32
;
5106 case 1: code
= BFD_RELOC_8
; break;
5107 case 2: code
= BFD_RELOC_16
; break;
5108 case 4: code
= BFD_RELOC_32
; break;
5110 case 8: code
= BFD_RELOC_64
; break;
5117 if (code
== BFD_RELOC_32
5119 && fixp
->fx_addsy
== GOT_symbol
)
5121 /* We don't support GOTPC on 64bit targets. */
5122 if (flag_code
== CODE_64BIT
)
5124 code
= BFD_RELOC_386_GOTPC
;
5127 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5128 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5129 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5131 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5132 if (!use_rela_relocations
)
5134 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5135 vtable entry to be used in the relocation's section offset. */
5136 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5137 rel
->address
= fixp
->fx_offset
;
5140 rel
->addend
= fixp
->fx_addnumber
;
5144 /* Use the rela in 64bit mode. */
5147 if (!fixp
->fx_pcrel
)
5148 rel
->addend
= fixp
->fx_offset
;
5152 case BFD_RELOC_X86_64_PLT32
:
5153 case BFD_RELOC_X86_64_GOT32
:
5154 case BFD_RELOC_X86_64_GOTPCREL
:
5155 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5158 rel
->addend
= (section
->vma
5160 + fixp
->fx_addnumber
5161 + md_pcrel_from (fixp
));
5166 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5167 if (rel
->howto
== NULL
)
5169 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5170 _("cannot represent relocation type %s"),
5171 bfd_get_reloc_code_name (code
));
5172 /* Set howto to a garbage value so that we can keep going. */
5173 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5174 assert (rel
->howto
!= NULL
);
5180 #else /* !BFD_ASSEMBLER */
5182 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5184 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5187 relax_addressT segment_address_in_file
;
5189 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5190 Out: GNU LD relocation length code: 0, 1, or 2. */
5192 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5195 know (fixP
->fx_addsy
!= NULL
);
5197 md_number_to_chars (where
,
5198 (valueT
) (fixP
->fx_frag
->fr_address
5199 + fixP
->fx_where
- segment_address_in_file
),
5202 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5203 ? S_GET_TYPE (fixP
->fx_addsy
)
5204 : fixP
->fx_addsy
->sy_number
);
5206 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5207 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5208 where
[4] = r_symbolnum
& 0x0ff;
5209 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5210 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5211 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5214 #endif /* OBJ_AOUT or OBJ_BOUT. */
5216 #if defined (I386COFF)
5219 tc_coff_fix2rtype (fixP
)
5222 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5225 return (fixP
->fx_pcrel
?
5226 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5227 fixP
->fx_size
== 2 ? R_PCRWORD
:
5229 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5230 fixP
->fx_size
== 2 ? R_RELWORD
:
5235 tc_coff_sizemachdep (frag
)
5239 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5244 #endif /* I386COFF */
5246 #endif /* !BFD_ASSEMBLER */
5248 /* Parse operands using Intel syntax. This implements a recursive descent
5249 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5252 FIXME: We do not recognize the full operand grammar defined in the MASM
5253 documentation. In particular, all the structure/union and
5254 high-level macro operands are missing.
5256 Uppercase words are terminals, lower case words are non-terminals.
5257 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5258 bars '|' denote choices. Most grammar productions are implemented in
5259 functions called 'intel_<production>'.
5261 Initial production is 'expr'.
5267 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5269 constant digits [[ radixOverride ]]
5271 dataType BYTE | WORD | DWORD | QWORD | XWORD
5304 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5305 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5307 hexdigit a | b | c | d | e | f
5308 | A | B | C | D | E | F
5318 register specialRegister
5322 segmentRegister CS | DS | ES | FS | GS | SS
5324 specialRegister CR0 | CR2 | CR3
5325 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5326 | TR3 | TR4 | TR5 | TR6 | TR7
5328 We simplify the grammar in obvious places (e.g., register parsing is
5329 done by calling parse_register) and eliminate immediate left recursion
5330 to implement a recursive-descent parser.
5370 /* Parsing structure for the intel syntax parser. Used to implement the
5371 semantic actions for the operand grammar. */
5372 struct intel_parser_s
5374 char *op_string
; /* The string being parsed. */
5375 int got_a_float
; /* Whether the operand is a float. */
5376 int op_modifier
; /* Operand modifier. */
5377 int is_mem
; /* 1 if operand is memory reference. */
5378 const reg_entry
*reg
; /* Last register reference found. */
5379 char *disp
; /* Displacement string being built. */
5382 static struct intel_parser_s intel_parser
;
5384 /* Token structure for parsing intel syntax. */
5387 int code
; /* Token code. */
5388 const reg_entry
*reg
; /* Register entry for register tokens. */
5389 char *str
; /* String representation. */
5392 static struct intel_token cur_token
, prev_token
;
5394 /* Token codes for the intel parser. Since T_SHORT is already used
5395 by COFF, undefine it first to prevent a warning. */
5410 /* Prototypes for intel parser functions. */
5411 static int intel_match_token
PARAMS ((int code
));
5412 static void intel_get_token
PARAMS ((void));
5413 static void intel_putback_token
PARAMS ((void));
5414 static int intel_expr
PARAMS ((void));
5415 static int intel_e05
PARAMS ((void));
5416 static int intel_e05_1
PARAMS ((void));
5417 static int intel_e06
PARAMS ((void));
5418 static int intel_e06_1
PARAMS ((void));
5419 static int intel_e09
PARAMS ((void));
5420 static int intel_e09_1
PARAMS ((void));
5421 static int intel_e10
PARAMS ((void));
5422 static int intel_e10_1
PARAMS ((void));
5423 static int intel_e11
PARAMS ((void));
5426 i386_intel_operand (operand_string
, got_a_float
)
5427 char *operand_string
;
5433 /* Initialize token holders. */
5434 cur_token
.code
= prev_token
.code
= T_NIL
;
5435 cur_token
.reg
= prev_token
.reg
= NULL
;
5436 cur_token
.str
= prev_token
.str
= NULL
;
5438 /* Initialize parser structure. */
5439 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5442 strcpy (intel_parser
.op_string
, operand_string
);
5443 intel_parser
.got_a_float
= got_a_float
;
5444 intel_parser
.op_modifier
= -1;
5445 intel_parser
.is_mem
= 0;
5446 intel_parser
.reg
= NULL
;
5447 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5448 if (intel_parser
.disp
== NULL
)
5450 intel_parser
.disp
[0] = '\0';
5452 /* Read the first token and start the parser. */
5454 ret
= intel_expr ();
5458 /* If we found a memory reference, hand it over to i386_displacement
5459 to fill in the rest of the operand fields. */
5460 if (intel_parser
.is_mem
)
5462 if ((i
.mem_operands
== 1
5463 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5464 || i
.mem_operands
== 2)
5466 as_bad (_("too many memory references for '%s'"),
5467 current_templates
->start
->name
);
5472 char *s
= intel_parser
.disp
;
5475 /* Add the displacement expression. */
5477 ret
= i386_displacement (s
, s
+ strlen (s
))
5478 && i386_index_check (s
);
5482 /* Constant and OFFSET expressions are handled by i386_immediate. */
5483 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5484 || intel_parser
.reg
== NULL
)
5485 ret
= i386_immediate (intel_parser
.disp
);
5489 free (intel_parser
.disp
);
5499 /* expr SHORT e05 */
5500 if (cur_token
.code
== T_SHORT
)
5502 intel_parser
.op_modifier
= SHORT
;
5503 intel_match_token (T_SHORT
);
5505 return (intel_e05 ());
5510 return intel_e05 ();
5520 return (intel_e06 () && intel_e05_1 ());
5526 /* e05' addOp e06 e05' */
5527 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5529 strcat (intel_parser
.disp
, cur_token
.str
);
5530 intel_match_token (cur_token
.code
);
5532 return (intel_e06 () && intel_e05_1 ());
5547 return (intel_e09 () && intel_e06_1 ());
5553 /* e06' mulOp e09 e06' */
5554 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5556 strcat (intel_parser
.disp
, cur_token
.str
);
5557 intel_match_token (cur_token
.code
);
5559 return (intel_e09 () && intel_e06_1 ());
5567 /* e09 OFFSET e10 e09'
5576 /* e09 OFFSET e10 e09' */
5577 if (cur_token
.code
== T_OFFSET
)
5579 intel_parser
.is_mem
= 0;
5580 intel_parser
.op_modifier
= OFFSET_FLAT
;
5581 intel_match_token (T_OFFSET
);
5583 return (intel_e10 () && intel_e09_1 ());
5588 return (intel_e10 () && intel_e09_1 ());
5594 /* e09' PTR e10 e09' */
5595 if (cur_token
.code
== T_PTR
)
5597 if (prev_token
.code
== T_BYTE
)
5598 i
.suffix
= BYTE_MNEM_SUFFIX
;
5600 else if (prev_token
.code
== T_WORD
)
5602 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5603 i
.suffix
= SHORT_MNEM_SUFFIX
;
5605 i
.suffix
= WORD_MNEM_SUFFIX
;
5608 else if (prev_token
.code
== T_DWORD
)
5610 if (intel_parser
.got_a_float
== 1) /* "f..." */
5611 i
.suffix
= SHORT_MNEM_SUFFIX
;
5613 i
.suffix
= LONG_MNEM_SUFFIX
;
5616 else if (prev_token
.code
== T_QWORD
)
5618 if (intel_parser
.got_a_float
== 1) /* "f..." */
5619 i
.suffix
= LONG_MNEM_SUFFIX
;
5621 i
.suffix
= QWORD_MNEM_SUFFIX
;
5624 else if (prev_token
.code
== T_XWORD
)
5625 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5629 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5633 intel_match_token (T_PTR
);
5635 return (intel_e10 () && intel_e09_1 ());
5638 /* e09 : e10 e09' */
5639 else if (cur_token
.code
== ':')
5641 /* Mark as a memory operand only if it's not already known to be an
5642 offset expression. */
5643 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5644 intel_parser
.is_mem
= 1;
5646 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5661 return (intel_e11 () && intel_e10_1 ());
5667 /* e10' [ expr ] e10' */
5668 if (cur_token
.code
== '[')
5670 intel_match_token ('[');
5672 /* Mark as a memory operand only if it's not already known to be an
5673 offset expression. If it's an offset expression, we need to keep
5675 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5676 intel_parser
.is_mem
= 1;
5678 strcat (intel_parser
.disp
, "[");
5680 /* Add a '+' to the displacement string if necessary. */
5681 if (*intel_parser
.disp
!= '\0'
5682 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5683 strcat (intel_parser
.disp
, "+");
5685 if (intel_expr () && intel_match_token (']'))
5687 /* Preserve brackets when the operand is an offset expression. */
5688 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5689 strcat (intel_parser
.disp
, "]");
5691 return intel_e10_1 ();
5718 if (cur_token
.code
== '(')
5720 intel_match_token ('(');
5721 strcat (intel_parser
.disp
, "(");
5723 if (intel_expr () && intel_match_token (')'))
5725 strcat (intel_parser
.disp
, ")");
5733 else if (cur_token
.code
== '[')
5735 intel_match_token ('[');
5737 /* Mark as a memory operand only if it's not already known to be an
5738 offset expression. If it's an offset expression, we need to keep
5740 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5741 intel_parser
.is_mem
= 1;
5743 strcat (intel_parser
.disp
, "[");
5745 /* Operands for jump/call inside brackets denote absolute addresses. */
5746 if (current_templates
->start
->opcode_modifier
& Jump
5747 || current_templates
->start
->opcode_modifier
& JumpDword
5748 || current_templates
->start
->opcode_modifier
& JumpByte
5749 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5750 i
.types
[this_operand
] |= JumpAbsolute
;
5752 /* Add a '+' to the displacement string if necessary. */
5753 if (*intel_parser
.disp
!= '\0'
5754 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5755 strcat (intel_parser
.disp
, "+");
5757 if (intel_expr () && intel_match_token (']'))
5759 /* Preserve brackets when the operand is an offset expression. */
5760 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5761 strcat (intel_parser
.disp
, "]");
5774 else if (cur_token
.code
== T_BYTE
5775 || cur_token
.code
== T_WORD
5776 || cur_token
.code
== T_DWORD
5777 || cur_token
.code
== T_QWORD
5778 || cur_token
.code
== T_XWORD
)
5780 intel_match_token (cur_token
.code
);
5787 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5789 strcat (intel_parser
.disp
, cur_token
.str
);
5790 intel_match_token (cur_token
.code
);
5792 /* Mark as a memory operand only if it's not already known to be an
5793 offset expression. */
5794 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5795 intel_parser
.is_mem
= 1;
5801 else if (cur_token
.code
== T_REG
)
5803 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5805 intel_match_token (T_REG
);
5807 /* Check for segment change. */
5808 if (cur_token
.code
== ':')
5810 if (reg
->reg_type
& (SReg2
| SReg3
))
5812 switch (reg
->reg_num
)
5815 i
.seg
[i
.mem_operands
] = &es
;
5818 i
.seg
[i
.mem_operands
] = &cs
;
5821 i
.seg
[i
.mem_operands
] = &ss
;
5824 i
.seg
[i
.mem_operands
] = &ds
;
5827 i
.seg
[i
.mem_operands
] = &fs
;
5830 i
.seg
[i
.mem_operands
] = &gs
;
5836 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5841 /* Not a segment register. Check for register scaling. */
5842 else if (cur_token
.code
== '*')
5844 if (!intel_parser
.is_mem
)
5846 as_bad (_("Register scaling only allowed in memory operands."));
5850 /* What follows must be a valid scale. */
5851 if (intel_match_token ('*')
5852 && strchr ("01248", *cur_token
.str
))
5855 i
.types
[this_operand
] |= BaseIndex
;
5857 /* Set the scale after setting the register (otherwise,
5858 i386_scale will complain) */
5859 i386_scale (cur_token
.str
);
5860 intel_match_token (T_CONST
);
5864 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5870 /* No scaling. If this is a memory operand, the register is either a
5871 base register (first occurrence) or an index register (second
5873 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5875 if (i
.base_reg
&& i
.index_reg
)
5877 as_bad (_("Too many register references in memory operand.\n"));
5881 if (i
.base_reg
== NULL
)
5886 i
.types
[this_operand
] |= BaseIndex
;
5889 /* Offset modifier. Add the register to the displacement string to be
5890 parsed as an immediate expression after we're done. */
5891 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5892 strcat (intel_parser
.disp
, reg
->reg_name
);
5894 /* It's neither base nor index nor offset. */
5897 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5898 i
.op
[this_operand
].regs
= reg
;
5902 /* Since registers are not part of the displacement string (except
5903 when we're parsing offset operands), we may need to remove any
5904 preceding '+' from the displacement string. */
5905 if (*intel_parser
.disp
!= '\0'
5906 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5908 char *s
= intel_parser
.disp
;
5909 s
+= strlen (s
) - 1;
5918 else if (cur_token
.code
== T_ID
)
5920 /* Add the identifier to the displacement string. */
5921 strcat (intel_parser
.disp
, cur_token
.str
);
5922 intel_match_token (T_ID
);
5924 /* The identifier represents a memory reference only if it's not
5925 preceded by an offset modifier. */
5926 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5927 intel_parser
.is_mem
= 1;
5933 else if (cur_token
.code
== T_CONST
5934 || cur_token
.code
== '-'
5935 || cur_token
.code
== '+')
5939 /* Allow constants that start with `+' or `-'. */
5940 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5942 strcat (intel_parser
.disp
, cur_token
.str
);
5943 intel_match_token (cur_token
.code
);
5944 if (cur_token
.code
!= T_CONST
)
5946 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5952 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5953 if (save_str
== NULL
)
5955 strcpy (save_str
, cur_token
.str
);
5957 /* Get the next token to check for register scaling. */
5958 intel_match_token (cur_token
.code
);
5960 /* Check if this constant is a scaling factor for an index register. */
5961 if (cur_token
.code
== '*')
5963 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5965 if (!intel_parser
.is_mem
)
5967 as_bad (_("Register scaling only allowed in memory operands."));
5971 /* The constant is followed by `* reg', so it must be
5973 if (strchr ("01248", *save_str
))
5975 i
.index_reg
= cur_token
.reg
;
5976 i
.types
[this_operand
] |= BaseIndex
;
5978 /* Set the scale after setting the register (otherwise,
5979 i386_scale will complain) */
5980 i386_scale (save_str
);
5981 intel_match_token (T_REG
);
5983 /* Since registers are not part of the displacement
5984 string, we may need to remove any preceding '+' from
5985 the displacement string. */
5986 if (*intel_parser
.disp
!= '\0')
5988 char *s
= intel_parser
.disp
;
5989 s
+= strlen (s
) - 1;
6002 /* The constant was not used for register scaling. Since we have
6003 already consumed the token following `*' we now need to put it
6004 back in the stream. */
6006 intel_putback_token ();
6009 /* Add the constant to the displacement string. */
6010 strcat (intel_parser
.disp
, save_str
);
6016 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6020 /* Match the given token against cur_token. If they match, read the next
6021 token from the operand string. */
6023 intel_match_token (code
)
6026 if (cur_token
.code
== code
)
6033 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6038 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6043 const reg_entry
*reg
;
6044 struct intel_token new_token
;
6046 new_token
.code
= T_NIL
;
6047 new_token
.reg
= NULL
;
6048 new_token
.str
= NULL
;
6050 /* Free the memory allocated to the previous token and move
6051 cur_token to prev_token. */
6053 free (prev_token
.str
);
6055 prev_token
= cur_token
;
6057 /* Skip whitespace. */
6058 while (is_space_char (*intel_parser
.op_string
))
6059 intel_parser
.op_string
++;
6061 /* Return an empty token if we find nothing else on the line. */
6062 if (*intel_parser
.op_string
== '\0')
6064 cur_token
= new_token
;
6068 /* The new token cannot be larger than the remainder of the operand
6070 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6071 if (new_token
.str
== NULL
)
6073 new_token
.str
[0] = '\0';
6075 if (strchr ("0123456789", *intel_parser
.op_string
))
6077 char *p
= new_token
.str
;
6078 char *q
= intel_parser
.op_string
;
6079 new_token
.code
= T_CONST
;
6081 /* Allow any kind of identifier char to encompass floating point and
6082 hexadecimal numbers. */
6083 while (is_identifier_char (*q
))
6087 /* Recognize special symbol names [0-9][bf]. */
6088 if (strlen (intel_parser
.op_string
) == 2
6089 && (intel_parser
.op_string
[1] == 'b'
6090 || intel_parser
.op_string
[1] == 'f'))
6091 new_token
.code
= T_ID
;
6094 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6096 new_token
.code
= *intel_parser
.op_string
;
6097 new_token
.str
[0] = *intel_parser
.op_string
;
6098 new_token
.str
[1] = '\0';
6101 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6102 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6104 new_token
.code
= T_REG
;
6105 new_token
.reg
= reg
;
6107 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6109 new_token
.str
[0] = REGISTER_PREFIX
;
6110 new_token
.str
[1] = '\0';
6113 strcat (new_token
.str
, reg
->reg_name
);
6116 else if (is_identifier_char (*intel_parser
.op_string
))
6118 char *p
= new_token
.str
;
6119 char *q
= intel_parser
.op_string
;
6121 /* A '.' or '$' followed by an identifier char is an identifier.
6122 Otherwise, it's operator '.' followed by an expression. */
6123 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6125 new_token
.code
= *q
;
6126 new_token
.str
[0] = *q
;
6127 new_token
.str
[1] = '\0';
6131 while (is_identifier_char (*q
) || *q
== '@')
6135 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6136 new_token
.code
= T_BYTE
;
6138 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6139 new_token
.code
= T_WORD
;
6141 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6142 new_token
.code
= T_DWORD
;
6144 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6145 new_token
.code
= T_QWORD
;
6147 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6148 new_token
.code
= T_XWORD
;
6150 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6151 new_token
.code
= T_PTR
;
6153 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6154 new_token
.code
= T_SHORT
;
6156 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6158 new_token
.code
= T_OFFSET
;
6160 /* ??? This is not mentioned in the MASM grammar but gcc
6161 makes use of it with -mintel-syntax. OFFSET may be
6162 followed by FLAT: */
6163 if (strncasecmp (q
, " FLAT:", 6) == 0)
6164 strcat (new_token
.str
, " FLAT:");
6167 /* ??? This is not mentioned in the MASM grammar. */
6168 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6169 new_token
.code
= T_OFFSET
;
6172 new_token
.code
= T_ID
;
6177 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6179 intel_parser
.op_string
+= strlen (new_token
.str
);
6180 cur_token
= new_token
;
6183 /* Put cur_token back into the token stream and make cur_token point to
6186 intel_putback_token ()
6188 intel_parser
.op_string
-= strlen (cur_token
.str
);
6189 free (cur_token
.str
);
6190 cur_token
= prev_token
;
6192 /* Forget prev_token. */
6193 prev_token
.code
= T_NIL
;
6194 prev_token
.reg
= NULL
;
6195 prev_token
.str
= NULL
;