1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512DQ_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512BW_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512VL_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
837 CPU_ANY_AVX_FLAGS
, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
839 CPU_VMX_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
841 CPU_VMFUNC_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
843 CPU_SMX_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
845 CPU_XSAVE_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
847 CPU_XSAVEOPT_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
849 CPU_XSAVEC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
851 CPU_XSAVES_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
853 CPU_AES_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
855 CPU_PCLMUL_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
857 CPU_PCLMUL_FLAGS
, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
859 CPU_FSGSBASE_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
861 CPU_RDRND_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
863 CPU_F16C_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
865 CPU_BMI2_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
867 CPU_FMA_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
869 CPU_FMA4_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
871 CPU_XOP_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
873 CPU_LWP_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
875 CPU_MOVBE_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
877 CPU_CX16_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
879 CPU_EPT_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
881 CPU_LZCNT_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
883 CPU_HLE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
885 CPU_RTM_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
887 CPU_INVPCID_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
889 CPU_CLFLUSH_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
891 CPU_NOP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
893 CPU_SYSCALL_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
895 CPU_RDTSCP_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
897 CPU_3DNOW_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
899 CPU_3DNOWA_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
901 CPU_PADLOCK_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
903 CPU_SVME_FLAGS
, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
905 CPU_SVME_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4A_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
909 CPU_ABM_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
911 CPU_BMI_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
913 CPU_TBM_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
915 CPU_ADX_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
917 CPU_RDSEED_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
919 CPU_PRFCHW_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
921 CPU_SMAP_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
923 CPU_MPX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
925 CPU_SHA_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
927 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
929 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
931 CPU_SE1_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
933 CPU_CLWB_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
935 CPU_PCOMMIT_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512IFMA_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512VBMI_FLAGS
, 0, 0 },
943 /* Like s_lcomm_internal in gas/read.c but the alignment string
944 is allowed to be optional. */
947 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
954 && *input_line_pointer
== ',')
956 align
= parse_align (needs_align
- 1);
958 if (align
== (addressT
) -1)
973 bss_alloc (symbolP
, size
, align
);
978 pe_lcomm (int needs_align
)
980 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
984 const pseudo_typeS md_pseudo_table
[] =
986 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
987 {"align", s_align_bytes
, 0},
989 {"align", s_align_ptwo
, 0},
991 {"arch", set_cpu_arch
, 0},
995 {"lcomm", pe_lcomm
, 1},
997 {"ffloat", float_cons
, 'f'},
998 {"dfloat", float_cons
, 'd'},
999 {"tfloat", float_cons
, 'x'},
1001 {"slong", signed_cons
, 4},
1002 {"noopt", s_ignore
, 0},
1003 {"optim", s_ignore
, 0},
1004 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1005 {"code16", set_code_flag
, CODE_16BIT
},
1006 {"code32", set_code_flag
, CODE_32BIT
},
1007 {"code64", set_code_flag
, CODE_64BIT
},
1008 {"intel_syntax", set_intel_syntax
, 1},
1009 {"att_syntax", set_intel_syntax
, 0},
1010 {"intel_mnemonic", set_intel_mnemonic
, 1},
1011 {"att_mnemonic", set_intel_mnemonic
, 0},
1012 {"allow_index_reg", set_allow_index_reg
, 1},
1013 {"disallow_index_reg", set_allow_index_reg
, 0},
1014 {"sse_check", set_check
, 0},
1015 {"operand_check", set_check
, 1},
1016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1017 {"largecomm", handle_large_common
, 0},
1019 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1020 {"loc", dwarf2_directive_loc
, 0},
1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1024 {"secrel32", pe_directive_secrel
, 0},
1029 /* For interface with expression (). */
1030 extern char *input_line_pointer
;
1032 /* Hash table for instruction mnemonic lookup. */
1033 static struct hash_control
*op_hash
;
1035 /* Hash table for register lookup. */
1036 static struct hash_control
*reg_hash
;
1039 i386_align_code (fragS
*fragP
, int count
)
1041 /* Various efficient no-op patterns for aligning code labels.
1042 Note: Don't try to assemble the instructions in the comments.
1043 0L and 0w are not legal. */
1044 static const char f32_1
[] =
1046 static const char f32_2
[] =
1047 {0x66,0x90}; /* xchg %ax,%ax */
1048 static const char f32_3
[] =
1049 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1050 static const char f32_4
[] =
1051 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1052 static const char f32_5
[] =
1054 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1055 static const char f32_6
[] =
1056 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1057 static const char f32_7
[] =
1058 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1059 static const char f32_8
[] =
1061 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1062 static const char f32_9
[] =
1063 {0x89,0xf6, /* movl %esi,%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f32_10
[] =
1066 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1067 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1068 static const char f32_11
[] =
1069 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1070 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1071 static const char f32_12
[] =
1072 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1073 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1074 static const char f32_13
[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_14
[] =
1078 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f16_3
[] =
1081 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1082 static const char f16_4
[] =
1083 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1084 static const char f16_5
[] =
1086 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1087 static const char f16_6
[] =
1088 {0x89,0xf6, /* mov %si,%si */
1089 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1090 static const char f16_7
[] =
1091 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1092 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1093 static const char f16_8
[] =
1094 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1095 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1096 static const char jump_31
[] =
1097 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1101 static const char *const f32_patt
[] = {
1102 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1103 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1105 static const char *const f16_patt
[] = {
1106 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1108 /* nopl (%[re]ax) */
1109 static const char alt_3
[] =
1111 /* nopl 0(%[re]ax) */
1112 static const char alt_4
[] =
1113 {0x0f,0x1f,0x40,0x00};
1114 /* nopl 0(%[re]ax,%[re]ax,1) */
1115 static const char alt_5
[] =
1116 {0x0f,0x1f,0x44,0x00,0x00};
1117 /* nopw 0(%[re]ax,%[re]ax,1) */
1118 static const char alt_6
[] =
1119 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1120 /* nopl 0L(%[re]ax) */
1121 static const char alt_7
[] =
1122 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1123 /* nopl 0L(%[re]ax,%[re]ax,1) */
1124 static const char alt_8
[] =
1125 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* nopw 0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_9
[] =
1128 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_10
[] =
1131 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1133 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_long_11
[] =
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_12
[] =
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1147 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1148 static const char alt_long_13
[] =
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1157 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1158 static const char alt_long_14
[] =
1163 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1170 static const char alt_long_15
[] =
1176 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1177 /* nopl 0(%[re]ax,%[re]ax,1)
1178 nopw 0(%[re]ax,%[re]ax,1) */
1179 static const char alt_short_11
[] =
1180 {0x0f,0x1f,0x44,0x00,0x00,
1181 0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopw 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_12
[] =
1185 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1189 static const char alt_short_13
[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1194 static const char alt_short_14
[] =
1195 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1198 nopl 0L(%[re]ax,%[re]ax,1) */
1199 static const char alt_short_15
[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1202 static const char *const alt_short_patt
[] = {
1203 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1204 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1205 alt_short_14
, alt_short_15
1207 static const char *const alt_long_patt
[] = {
1208 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1209 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1210 alt_long_14
, alt_long_15
1213 /* Only align for at least a positive non-zero boundary. */
1214 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1217 /* We need to decide which NOP sequence to use for 32bit and
1218 64bit. When -mtune= is used:
1220 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1221 PROCESSOR_GENERIC32, f32_patt will be used.
1222 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1223 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1224 PROCESSOR_GENERIC64, alt_long_patt will be used.
1225 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1226 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1229 When -mtune= isn't used, alt_long_patt will be used if
1230 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1233 When -march= or .arch is used, we can't use anything beyond
1234 cpu_arch_isa_flags. */
1236 if (flag_code
== CODE_16BIT
)
1240 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1242 /* Adjust jump offset. */
1243 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1246 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1247 f16_patt
[count
- 1], count
);
1251 const char *const *patt
= NULL
;
1253 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1255 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1256 switch (cpu_arch_tune
)
1258 case PROCESSOR_UNKNOWN
:
1259 /* We use cpu_arch_isa_flags to check if we SHOULD
1260 optimize with nops. */
1261 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1262 patt
= alt_long_patt
;
1266 case PROCESSOR_PENTIUM4
:
1267 case PROCESSOR_NOCONA
:
1268 case PROCESSOR_CORE
:
1269 case PROCESSOR_CORE2
:
1270 case PROCESSOR_COREI7
:
1271 case PROCESSOR_L1OM
:
1272 case PROCESSOR_K1OM
:
1273 case PROCESSOR_GENERIC64
:
1274 patt
= alt_long_patt
;
1277 case PROCESSOR_ATHLON
:
1279 case PROCESSOR_AMDFAM10
:
1282 patt
= alt_short_patt
;
1284 case PROCESSOR_I386
:
1285 case PROCESSOR_I486
:
1286 case PROCESSOR_PENTIUM
:
1287 case PROCESSOR_PENTIUMPRO
:
1288 case PROCESSOR_GENERIC32
:
1295 switch (fragP
->tc_frag_data
.tune
)
1297 case PROCESSOR_UNKNOWN
:
1298 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1299 PROCESSOR_UNKNOWN. */
1303 case PROCESSOR_I386
:
1304 case PROCESSOR_I486
:
1305 case PROCESSOR_PENTIUM
:
1307 case PROCESSOR_ATHLON
:
1309 case PROCESSOR_AMDFAM10
:
1312 case PROCESSOR_GENERIC32
:
1313 /* We use cpu_arch_isa_flags to check if we CAN optimize
1315 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1316 patt
= alt_short_patt
;
1320 case PROCESSOR_PENTIUMPRO
:
1321 case PROCESSOR_PENTIUM4
:
1322 case PROCESSOR_NOCONA
:
1323 case PROCESSOR_CORE
:
1324 case PROCESSOR_CORE2
:
1325 case PROCESSOR_COREI7
:
1326 case PROCESSOR_L1OM
:
1327 case PROCESSOR_K1OM
:
1328 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1329 patt
= alt_long_patt
;
1333 case PROCESSOR_GENERIC64
:
1334 patt
= alt_long_patt
;
1339 if (patt
== f32_patt
)
1341 /* If the padding is less than 15 bytes, we use the normal
1342 ones. Otherwise, we use a jump instruction and adjust
1346 /* For 64bit, the limit is 3 bytes. */
1347 if (flag_code
== CODE_64BIT
1348 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1353 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1354 patt
[count
- 1], count
);
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1359 /* Adjust jump offset. */
1360 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1365 /* Maximum length of an instruction is 15 byte. If the
1366 padding is greater than 15 bytes and we don't use jump,
1367 we have to break it into smaller pieces. */
1368 int padding
= count
;
1369 while (padding
> 15)
1372 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1378 patt
[padding
- 1], padding
);
1381 fragP
->fr_var
= count
;
1385 operand_type_all_zero (const union i386_operand_type
*x
)
1387 switch (ARRAY_SIZE(x
->array
))
1396 return !x
->array
[0];
1403 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1405 switch (ARRAY_SIZE(x
->array
))
1420 operand_type_equal (const union i386_operand_type
*x
,
1421 const union i386_operand_type
*y
)
1423 switch (ARRAY_SIZE(x
->array
))
1426 if (x
->array
[2] != y
->array
[2])
1429 if (x
->array
[1] != y
->array
[1])
1432 return x
->array
[0] == y
->array
[0];
1440 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1442 switch (ARRAY_SIZE(x
->array
))
1451 return !x
->array
[0];
1458 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1460 switch (ARRAY_SIZE(x
->array
))
1475 cpu_flags_equal (const union i386_cpu_flags
*x
,
1476 const union i386_cpu_flags
*y
)
1478 switch (ARRAY_SIZE(x
->array
))
1481 if (x
->array
[2] != y
->array
[2])
1484 if (x
->array
[1] != y
->array
[1])
1487 return x
->array
[0] == y
->array
[0];
1495 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1497 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1498 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1501 static INLINE i386_cpu_flags
1502 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1504 switch (ARRAY_SIZE (x
.array
))
1507 x
.array
[2] &= y
.array
[2];
1509 x
.array
[1] &= y
.array
[1];
1511 x
.array
[0] &= y
.array
[0];
1519 static INLINE i386_cpu_flags
1520 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1522 switch (ARRAY_SIZE (x
.array
))
1525 x
.array
[2] |= y
.array
[2];
1527 x
.array
[1] |= y
.array
[1];
1529 x
.array
[0] |= y
.array
[0];
1537 static INLINE i386_cpu_flags
1538 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1540 switch (ARRAY_SIZE (x
.array
))
1543 x
.array
[2] &= ~y
.array
[2];
1545 x
.array
[1] &= ~y
.array
[1];
1547 x
.array
[0] &= ~y
.array
[0];
1555 #define CPU_FLAGS_ARCH_MATCH 0x1
1556 #define CPU_FLAGS_64BIT_MATCH 0x2
1557 #define CPU_FLAGS_AES_MATCH 0x4
1558 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1559 #define CPU_FLAGS_AVX_MATCH 0x10
1561 #define CPU_FLAGS_32BIT_MATCH \
1562 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1563 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1564 #define CPU_FLAGS_PERFECT_MATCH \
1565 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1567 /* Return CPU flags match bits. */
1570 cpu_flags_match (const insn_template
*t
)
1572 i386_cpu_flags x
= t
->cpu_flags
;
1573 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1575 x
.bitfield
.cpu64
= 0;
1576 x
.bitfield
.cpuno64
= 0;
1578 if (cpu_flags_all_zero (&x
))
1580 /* This instruction is available on all archs. */
1581 match
|= CPU_FLAGS_32BIT_MATCH
;
1585 /* This instruction is available only on some archs. */
1586 i386_cpu_flags cpu
= cpu_arch_flags
;
1588 cpu
.bitfield
.cpu64
= 0;
1589 cpu
.bitfield
.cpuno64
= 0;
1590 cpu
= cpu_flags_and (x
, cpu
);
1591 if (!cpu_flags_all_zero (&cpu
))
1593 if (x
.bitfield
.cpuavx
)
1595 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1596 if (cpu
.bitfield
.cpuavx
)
1598 /* Check SSE2AVX. */
1599 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1601 match
|= (CPU_FLAGS_ARCH_MATCH
1602 | CPU_FLAGS_AVX_MATCH
);
1604 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1605 match
|= CPU_FLAGS_AES_MATCH
;
1607 if (!x
.bitfield
.cpupclmul
1608 || cpu
.bitfield
.cpupclmul
)
1609 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1613 match
|= CPU_FLAGS_ARCH_MATCH
;
1616 match
|= CPU_FLAGS_32BIT_MATCH
;
1622 static INLINE i386_operand_type
1623 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1625 switch (ARRAY_SIZE (x
.array
))
1628 x
.array
[2] &= y
.array
[2];
1630 x
.array
[1] &= y
.array
[1];
1632 x
.array
[0] &= y
.array
[0];
1640 static INLINE i386_operand_type
1641 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1643 switch (ARRAY_SIZE (x
.array
))
1646 x
.array
[2] |= y
.array
[2];
1648 x
.array
[1] |= y
.array
[1];
1650 x
.array
[0] |= y
.array
[0];
1658 static INLINE i386_operand_type
1659 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1661 switch (ARRAY_SIZE (x
.array
))
1664 x
.array
[2] ^= y
.array
[2];
1666 x
.array
[1] ^= y
.array
[1];
1668 x
.array
[0] ^= y
.array
[0];
1676 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1677 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1678 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1679 static const i386_operand_type inoutportreg
1680 = OPERAND_TYPE_INOUTPORTREG
;
1681 static const i386_operand_type reg16_inoutportreg
1682 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1683 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1684 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1685 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1686 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1687 static const i386_operand_type anydisp
1688 = OPERAND_TYPE_ANYDISP
;
1689 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1690 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1691 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1692 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1693 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1694 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1695 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1696 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1697 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1698 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1699 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1700 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1701 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1702 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1713 operand_type_check (i386_operand_type t
, enum operand_type c
)
1718 return (t
.bitfield
.reg8
1721 || t
.bitfield
.reg64
);
1724 return (t
.bitfield
.imm8
1728 || t
.bitfield
.imm32s
1729 || t
.bitfield
.imm64
);
1732 return (t
.bitfield
.disp8
1733 || t
.bitfield
.disp16
1734 || t
.bitfield
.disp32
1735 || t
.bitfield
.disp32s
1736 || t
.bitfield
.disp64
);
1739 return (t
.bitfield
.disp8
1740 || t
.bitfield
.disp16
1741 || t
.bitfield
.disp32
1742 || t
.bitfield
.disp32s
1743 || t
.bitfield
.disp64
1744 || t
.bitfield
.baseindex
);
1753 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1754 operand J for instruction template T. */
1757 match_reg_size (const insn_template
*t
, unsigned int j
)
1759 return !((i
.types
[j
].bitfield
.byte
1760 && !t
->operand_types
[j
].bitfield
.byte
)
1761 || (i
.types
[j
].bitfield
.word
1762 && !t
->operand_types
[j
].bitfield
.word
)
1763 || (i
.types
[j
].bitfield
.dword
1764 && !t
->operand_types
[j
].bitfield
.dword
)
1765 || (i
.types
[j
].bitfield
.qword
1766 && !t
->operand_types
[j
].bitfield
.qword
));
1769 /* Return 1 if there is no conflict in any size on operand J for
1770 instruction template T. */
1773 match_mem_size (const insn_template
*t
, unsigned int j
)
1775 return (match_reg_size (t
, j
)
1776 && !((i
.types
[j
].bitfield
.unspecified
1777 && !t
->operand_types
[j
].bitfield
.unspecified
)
1778 || (i
.types
[j
].bitfield
.fword
1779 && !t
->operand_types
[j
].bitfield
.fword
)
1780 || (i
.types
[j
].bitfield
.tbyte
1781 && !t
->operand_types
[j
].bitfield
.tbyte
)
1782 || (i
.types
[j
].bitfield
.xmmword
1783 && !t
->operand_types
[j
].bitfield
.xmmword
)
1784 || (i
.types
[j
].bitfield
.ymmword
1785 && !t
->operand_types
[j
].bitfield
.ymmword
)
1786 || (i
.types
[j
].bitfield
.zmmword
1787 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1790 /* Return 1 if there is no size conflict on any operands for
1791 instruction template T. */
1794 operand_size_match (const insn_template
*t
)
1799 /* Don't check jump instructions. */
1800 if (t
->opcode_modifier
.jump
1801 || t
->opcode_modifier
.jumpbyte
1802 || t
->opcode_modifier
.jumpdword
1803 || t
->opcode_modifier
.jumpintersegment
)
1806 /* Check memory and accumulator operand size. */
1807 for (j
= 0; j
< i
.operands
; j
++)
1809 if (t
->operand_types
[j
].bitfield
.anysize
)
1812 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1818 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1827 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1830 i
.error
= operand_size_mismatch
;
1834 /* Check reverse. */
1835 gas_assert (i
.operands
== 2);
1838 for (j
= 0; j
< 2; j
++)
1840 if (t
->operand_types
[j
].bitfield
.acc
1841 && !match_reg_size (t
, j
? 0 : 1))
1844 if (i
.types
[j
].bitfield
.mem
1845 && !match_mem_size (t
, j
? 0 : 1))
1853 operand_type_match (i386_operand_type overlap
,
1854 i386_operand_type given
)
1856 i386_operand_type temp
= overlap
;
1858 temp
.bitfield
.jumpabsolute
= 0;
1859 temp
.bitfield
.unspecified
= 0;
1860 temp
.bitfield
.byte
= 0;
1861 temp
.bitfield
.word
= 0;
1862 temp
.bitfield
.dword
= 0;
1863 temp
.bitfield
.fword
= 0;
1864 temp
.bitfield
.qword
= 0;
1865 temp
.bitfield
.tbyte
= 0;
1866 temp
.bitfield
.xmmword
= 0;
1867 temp
.bitfield
.ymmword
= 0;
1868 temp
.bitfield
.zmmword
= 0;
1869 if (operand_type_all_zero (&temp
))
1872 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1873 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1877 i
.error
= operand_type_mismatch
;
1881 /* If given types g0 and g1 are registers they must be of the same type
1882 unless the expected operand type register overlap is null.
1883 Note that Acc in a template matches every size of reg. */
1886 operand_type_register_match (i386_operand_type m0
,
1887 i386_operand_type g0
,
1888 i386_operand_type t0
,
1889 i386_operand_type m1
,
1890 i386_operand_type g1
,
1891 i386_operand_type t1
)
1893 if (!operand_type_check (g0
, reg
))
1896 if (!operand_type_check (g1
, reg
))
1899 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1900 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1901 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1902 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1905 if (m0
.bitfield
.acc
)
1907 t0
.bitfield
.reg8
= 1;
1908 t0
.bitfield
.reg16
= 1;
1909 t0
.bitfield
.reg32
= 1;
1910 t0
.bitfield
.reg64
= 1;
1913 if (m1
.bitfield
.acc
)
1915 t1
.bitfield
.reg8
= 1;
1916 t1
.bitfield
.reg16
= 1;
1917 t1
.bitfield
.reg32
= 1;
1918 t1
.bitfield
.reg64
= 1;
1921 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1922 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1923 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1924 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1927 i
.error
= register_type_mismatch
;
1932 static INLINE
unsigned int
1933 register_number (const reg_entry
*r
)
1935 unsigned int nr
= r
->reg_num
;
1937 if (r
->reg_flags
& RegRex
)
1943 static INLINE
unsigned int
1944 mode_from_disp_size (i386_operand_type t
)
1946 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1948 else if (t
.bitfield
.disp16
1949 || t
.bitfield
.disp32
1950 || t
.bitfield
.disp32s
)
1957 fits_in_signed_byte (addressT num
)
1959 return num
+ 0x80 <= 0xff;
1963 fits_in_unsigned_byte (addressT num
)
1969 fits_in_unsigned_word (addressT num
)
1971 return num
<= 0xffff;
1975 fits_in_signed_word (addressT num
)
1977 return num
+ 0x8000 <= 0xffff;
1981 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1986 return num
+ 0x80000000 <= 0xffffffff;
1988 } /* fits_in_signed_long() */
1991 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1996 return num
<= 0xffffffff;
1998 } /* fits_in_unsigned_long() */
2001 fits_in_vec_disp8 (offsetT num
)
2003 int shift
= i
.memshift
;
2009 mask
= (1 << shift
) - 1;
2011 /* Return 0 if NUM isn't properly aligned. */
2015 /* Check if NUM will fit in 8bit after shift. */
2016 return fits_in_signed_byte (num
>> shift
);
2020 fits_in_imm4 (offsetT num
)
2022 return (num
& 0xf) == num
;
2025 static i386_operand_type
2026 smallest_imm_type (offsetT num
)
2028 i386_operand_type t
;
2030 operand_type_set (&t
, 0);
2031 t
.bitfield
.imm64
= 1;
2033 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2035 /* This code is disabled on the 486 because all the Imm1 forms
2036 in the opcode table are slower on the i486. They're the
2037 versions with the implicitly specified single-position
2038 displacement, which has another syntax if you really want to
2040 t
.bitfield
.imm1
= 1;
2041 t
.bitfield
.imm8
= 1;
2042 t
.bitfield
.imm8s
= 1;
2043 t
.bitfield
.imm16
= 1;
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_signed_byte (num
))
2049 t
.bitfield
.imm8
= 1;
2050 t
.bitfield
.imm8s
= 1;
2051 t
.bitfield
.imm16
= 1;
2052 t
.bitfield
.imm32
= 1;
2053 t
.bitfield
.imm32s
= 1;
2055 else if (fits_in_unsigned_byte (num
))
2057 t
.bitfield
.imm8
= 1;
2058 t
.bitfield
.imm16
= 1;
2059 t
.bitfield
.imm32
= 1;
2060 t
.bitfield
.imm32s
= 1;
2062 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2064 t
.bitfield
.imm16
= 1;
2065 t
.bitfield
.imm32
= 1;
2066 t
.bitfield
.imm32s
= 1;
2068 else if (fits_in_signed_long (num
))
2070 t
.bitfield
.imm32
= 1;
2071 t
.bitfield
.imm32s
= 1;
2073 else if (fits_in_unsigned_long (num
))
2074 t
.bitfield
.imm32
= 1;
2080 offset_in_range (offsetT val
, int size
)
2086 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2087 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2088 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2090 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2096 /* If BFD64, sign extend val for 32bit address mode. */
2097 if (flag_code
!= CODE_64BIT
2098 || i
.prefix
[ADDR_PREFIX
])
2099 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2100 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2103 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2105 char buf1
[40], buf2
[40];
2107 sprint_value (buf1
, val
);
2108 sprint_value (buf2
, val
& mask
);
2109 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2123 a. PREFIX_EXIST if attempting to add a prefix where one from the
2124 same class already exists.
2125 b. PREFIX_LOCK if lock prefix is added.
2126 c. PREFIX_REP if rep/repne prefix is added.
2127 d. PREFIX_OTHER if other prefix is added.
2130 static enum PREFIX_GROUP
2131 add_prefix (unsigned int prefix
)
2133 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2136 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2137 && flag_code
== CODE_64BIT
)
2139 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2140 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2141 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2152 case CS_PREFIX_OPCODE
:
2153 case DS_PREFIX_OPCODE
:
2154 case ES_PREFIX_OPCODE
:
2155 case FS_PREFIX_OPCODE
:
2156 case GS_PREFIX_OPCODE
:
2157 case SS_PREFIX_OPCODE
:
2161 case REPNE_PREFIX_OPCODE
:
2162 case REPE_PREFIX_OPCODE
:
2167 case LOCK_PREFIX_OPCODE
:
2176 case ADDR_PREFIX_OPCODE
:
2180 case DATA_PREFIX_OPCODE
:
2184 if (i
.prefix
[q
] != 0)
2192 i
.prefix
[q
] |= prefix
;
2195 as_bad (_("same type of prefix used twice"));
2201 update_code_flag (int value
, int check
)
2203 PRINTF_LIKE ((*as_error
));
2205 flag_code
= (enum flag_code
) value
;
2206 if (flag_code
== CODE_64BIT
)
2208 cpu_arch_flags
.bitfield
.cpu64
= 1;
2209 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2213 cpu_arch_flags
.bitfield
.cpu64
= 0;
2214 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2216 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2219 as_error
= as_fatal
;
2222 (*as_error
) (_("64bit mode not supported on `%s'."),
2223 cpu_arch_name
? cpu_arch_name
: default_arch
);
2225 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2228 as_error
= as_fatal
;
2231 (*as_error
) (_("32bit mode not supported on `%s'."),
2232 cpu_arch_name
? cpu_arch_name
: default_arch
);
2234 stackop_size
= '\0';
2238 set_code_flag (int value
)
2240 update_code_flag (value
, 0);
2244 set_16bit_gcc_code_flag (int new_code_flag
)
2246 flag_code
= (enum flag_code
) new_code_flag
;
2247 if (flag_code
!= CODE_16BIT
)
2249 cpu_arch_flags
.bitfield
.cpu64
= 0;
2250 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2251 stackop_size
= LONG_MNEM_SUFFIX
;
2255 set_intel_syntax (int syntax_flag
)
2257 /* Find out if register prefixing is specified. */
2258 int ask_naked_reg
= 0;
2261 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2263 char *string
= input_line_pointer
;
2264 int e
= get_symbol_end ();
2266 if (strcmp (string
, "prefix") == 0)
2268 else if (strcmp (string
, "noprefix") == 0)
2271 as_bad (_("bad argument to syntax directive."));
2272 *input_line_pointer
= e
;
2274 demand_empty_rest_of_line ();
2276 intel_syntax
= syntax_flag
;
2278 if (ask_naked_reg
== 0)
2279 allow_naked_reg
= (intel_syntax
2280 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2282 allow_naked_reg
= (ask_naked_reg
< 0);
2284 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2286 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2287 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2288 register_prefix
= allow_naked_reg
? "" : "%";
2292 set_intel_mnemonic (int mnemonic_flag
)
2294 intel_mnemonic
= mnemonic_flag
;
2298 set_allow_index_reg (int flag
)
2300 allow_index_reg
= flag
;
2304 set_check (int what
)
2306 enum check_kind
*kind
;
2311 kind
= &operand_check
;
2322 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2324 char *string
= input_line_pointer
;
2325 int e
= get_symbol_end ();
2327 if (strcmp (string
, "none") == 0)
2329 else if (strcmp (string
, "warning") == 0)
2330 *kind
= check_warning
;
2331 else if (strcmp (string
, "error") == 0)
2332 *kind
= check_error
;
2334 as_bad (_("bad argument to %s_check directive."), str
);
2335 *input_line_pointer
= e
;
2338 as_bad (_("missing argument for %s_check directive"), str
);
2340 demand_empty_rest_of_line ();
2344 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2345 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2348 static const char *arch
;
2350 /* Intel LIOM is only supported on ELF. */
2356 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2357 use default_arch. */
2358 arch
= cpu_arch_name
;
2360 arch
= default_arch
;
2363 /* If we are targeting Intel L1OM, we must enable it. */
2364 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2365 || new_flag
.bitfield
.cpul1om
)
2368 /* If we are targeting Intel K1OM, we must enable it. */
2369 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2370 || new_flag
.bitfield
.cpuk1om
)
2373 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2378 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2382 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2384 char *string
= input_line_pointer
;
2385 int e
= get_symbol_end ();
2387 i386_cpu_flags flags
;
2389 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2391 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2393 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2397 cpu_arch_name
= cpu_arch
[j
].name
;
2398 cpu_sub_arch_name
= NULL
;
2399 cpu_arch_flags
= cpu_arch
[j
].flags
;
2400 if (flag_code
== CODE_64BIT
)
2402 cpu_arch_flags
.bitfield
.cpu64
= 1;
2403 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2407 cpu_arch_flags
.bitfield
.cpu64
= 0;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2410 cpu_arch_isa
= cpu_arch
[j
].type
;
2411 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2412 if (!cpu_arch_tune_set
)
2414 cpu_arch_tune
= cpu_arch_isa
;
2415 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2420 if (!cpu_arch
[j
].negated
)
2421 flags
= cpu_flags_or (cpu_arch_flags
,
2424 flags
= cpu_flags_and_not (cpu_arch_flags
,
2426 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2428 if (cpu_sub_arch_name
)
2430 char *name
= cpu_sub_arch_name
;
2431 cpu_sub_arch_name
= concat (name
,
2433 (const char *) NULL
);
2437 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2438 cpu_arch_flags
= flags
;
2439 cpu_arch_isa_flags
= flags
;
2441 *input_line_pointer
= e
;
2442 demand_empty_rest_of_line ();
2446 if (j
>= ARRAY_SIZE (cpu_arch
))
2447 as_bad (_("no such architecture: `%s'"), string
);
2449 *input_line_pointer
= e
;
2452 as_bad (_("missing cpu architecture"));
2454 no_cond_jump_promotion
= 0;
2455 if (*input_line_pointer
== ','
2456 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2458 char *string
= ++input_line_pointer
;
2459 int e
= get_symbol_end ();
2461 if (strcmp (string
, "nojumps") == 0)
2462 no_cond_jump_promotion
= 1;
2463 else if (strcmp (string
, "jumps") == 0)
2466 as_bad (_("no such architecture modifier: `%s'"), string
);
2468 *input_line_pointer
= e
;
2471 demand_empty_rest_of_line ();
2474 enum bfd_architecture
2477 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2479 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2480 || flag_code
!= CODE_64BIT
)
2481 as_fatal (_("Intel L1OM is 64bit ELF only"));
2482 return bfd_arch_l1om
;
2484 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2486 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2487 || flag_code
!= CODE_64BIT
)
2488 as_fatal (_("Intel K1OM is 64bit ELF only"));
2489 return bfd_arch_k1om
;
2492 return bfd_arch_i386
;
2498 if (!strncmp (default_arch
, "x86_64", 6))
2500 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2502 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2503 || default_arch
[6] != '\0')
2504 as_fatal (_("Intel L1OM is 64bit ELF only"));
2505 return bfd_mach_l1om
;
2507 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2509 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2510 || default_arch
[6] != '\0')
2511 as_fatal (_("Intel K1OM is 64bit ELF only"));
2512 return bfd_mach_k1om
;
2514 else if (default_arch
[6] == '\0')
2515 return bfd_mach_x86_64
;
2517 return bfd_mach_x64_32
;
2519 else if (!strcmp (default_arch
, "i386"))
2520 return bfd_mach_i386_i386
;
2522 as_fatal (_("unknown architecture"));
2528 const char *hash_err
;
2530 /* Initialize op_hash hash table. */
2531 op_hash
= hash_new ();
2534 const insn_template
*optab
;
2535 templates
*core_optab
;
2537 /* Setup for loop. */
2539 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2540 core_optab
->start
= optab
;
2545 if (optab
->name
== NULL
2546 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2548 /* different name --> ship out current template list;
2549 add to hash table; & begin anew. */
2550 core_optab
->end
= optab
;
2551 hash_err
= hash_insert (op_hash
,
2553 (void *) core_optab
);
2556 as_fatal (_("can't hash %s: %s"),
2560 if (optab
->name
== NULL
)
2562 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2563 core_optab
->start
= optab
;
2568 /* Initialize reg_hash hash table. */
2569 reg_hash
= hash_new ();
2571 const reg_entry
*regtab
;
2572 unsigned int regtab_size
= i386_regtab_size
;
2574 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2576 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2578 as_fatal (_("can't hash %s: %s"),
2584 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2589 for (c
= 0; c
< 256; c
++)
2594 mnemonic_chars
[c
] = c
;
2595 register_chars
[c
] = c
;
2596 operand_chars
[c
] = c
;
2598 else if (ISLOWER (c
))
2600 mnemonic_chars
[c
] = c
;
2601 register_chars
[c
] = c
;
2602 operand_chars
[c
] = c
;
2604 else if (ISUPPER (c
))
2606 mnemonic_chars
[c
] = TOLOWER (c
);
2607 register_chars
[c
] = mnemonic_chars
[c
];
2608 operand_chars
[c
] = c
;
2610 else if (c
== '{' || c
== '}')
2611 operand_chars
[c
] = c
;
2613 if (ISALPHA (c
) || ISDIGIT (c
))
2614 identifier_chars
[c
] = c
;
2617 identifier_chars
[c
] = c
;
2618 operand_chars
[c
] = c
;
2623 identifier_chars
['@'] = '@';
2626 identifier_chars
['?'] = '?';
2627 operand_chars
['?'] = '?';
2629 digit_chars
['-'] = '-';
2630 mnemonic_chars
['_'] = '_';
2631 mnemonic_chars
['-'] = '-';
2632 mnemonic_chars
['.'] = '.';
2633 identifier_chars
['_'] = '_';
2634 identifier_chars
['.'] = '.';
2636 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2637 operand_chars
[(unsigned char) *p
] = *p
;
2640 if (flag_code
== CODE_64BIT
)
2642 #if defined (OBJ_COFF) && defined (TE_PE)
2643 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2646 x86_dwarf2_return_column
= 16;
2648 x86_cie_data_alignment
= -8;
2652 x86_dwarf2_return_column
= 8;
2653 x86_cie_data_alignment
= -4;
2658 i386_print_statistics (FILE *file
)
2660 hash_print_statistics (file
, "i386 opcode", op_hash
);
2661 hash_print_statistics (file
, "i386 register", reg_hash
);
2666 /* Debugging routines for md_assemble. */
2667 static void pte (insn_template
*);
2668 static void pt (i386_operand_type
);
2669 static void pe (expressionS
*);
2670 static void ps (symbolS
*);
2673 pi (char *line
, i386_insn
*x
)
2677 fprintf (stdout
, "%s: template ", line
);
2679 fprintf (stdout
, " address: base %s index %s scale %x\n",
2680 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2681 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2682 x
->log2_scale_factor
);
2683 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2684 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2685 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2686 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2687 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2688 (x
->rex
& REX_W
) != 0,
2689 (x
->rex
& REX_R
) != 0,
2690 (x
->rex
& REX_X
) != 0,
2691 (x
->rex
& REX_B
) != 0);
2692 for (j
= 0; j
< x
->operands
; j
++)
2694 fprintf (stdout
, " #%d: ", j
+ 1);
2696 fprintf (stdout
, "\n");
2697 if (x
->types
[j
].bitfield
.reg8
2698 || x
->types
[j
].bitfield
.reg16
2699 || x
->types
[j
].bitfield
.reg32
2700 || x
->types
[j
].bitfield
.reg64
2701 || x
->types
[j
].bitfield
.regmmx
2702 || x
->types
[j
].bitfield
.regxmm
2703 || x
->types
[j
].bitfield
.regymm
2704 || x
->types
[j
].bitfield
.regzmm
2705 || x
->types
[j
].bitfield
.sreg2
2706 || x
->types
[j
].bitfield
.sreg3
2707 || x
->types
[j
].bitfield
.control
2708 || x
->types
[j
].bitfield
.debug
2709 || x
->types
[j
].bitfield
.test
)
2710 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2711 if (operand_type_check (x
->types
[j
], imm
))
2713 if (operand_type_check (x
->types
[j
], disp
))
2714 pe (x
->op
[j
].disps
);
2719 pte (insn_template
*t
)
2722 fprintf (stdout
, " %d operands ", t
->operands
);
2723 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2724 if (t
->extension_opcode
!= None
)
2725 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2726 if (t
->opcode_modifier
.d
)
2727 fprintf (stdout
, "D");
2728 if (t
->opcode_modifier
.w
)
2729 fprintf (stdout
, "W");
2730 fprintf (stdout
, "\n");
2731 for (j
= 0; j
< t
->operands
; j
++)
2733 fprintf (stdout
, " #%d type ", j
+ 1);
2734 pt (t
->operand_types
[j
]);
2735 fprintf (stdout
, "\n");
2742 fprintf (stdout
, " operation %d\n", e
->X_op
);
2743 fprintf (stdout
, " add_number %ld (%lx)\n",
2744 (long) e
->X_add_number
, (long) e
->X_add_number
);
2745 if (e
->X_add_symbol
)
2747 fprintf (stdout
, " add_symbol ");
2748 ps (e
->X_add_symbol
);
2749 fprintf (stdout
, "\n");
2753 fprintf (stdout
, " op_symbol ");
2754 ps (e
->X_op_symbol
);
2755 fprintf (stdout
, "\n");
2762 fprintf (stdout
, "%s type %s%s",
2764 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2765 segment_name (S_GET_SEGMENT (s
)));
2768 static struct type_name
2770 i386_operand_type mask
;
2773 const type_names
[] =
2775 { OPERAND_TYPE_REG8
, "r8" },
2776 { OPERAND_TYPE_REG16
, "r16" },
2777 { OPERAND_TYPE_REG32
, "r32" },
2778 { OPERAND_TYPE_REG64
, "r64" },
2779 { OPERAND_TYPE_IMM8
, "i8" },
2780 { OPERAND_TYPE_IMM8
, "i8s" },
2781 { OPERAND_TYPE_IMM16
, "i16" },
2782 { OPERAND_TYPE_IMM32
, "i32" },
2783 { OPERAND_TYPE_IMM32S
, "i32s" },
2784 { OPERAND_TYPE_IMM64
, "i64" },
2785 { OPERAND_TYPE_IMM1
, "i1" },
2786 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2787 { OPERAND_TYPE_DISP8
, "d8" },
2788 { OPERAND_TYPE_DISP16
, "d16" },
2789 { OPERAND_TYPE_DISP32
, "d32" },
2790 { OPERAND_TYPE_DISP32S
, "d32s" },
2791 { OPERAND_TYPE_DISP64
, "d64" },
2792 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2793 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2794 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2795 { OPERAND_TYPE_CONTROL
, "control reg" },
2796 { OPERAND_TYPE_TEST
, "test reg" },
2797 { OPERAND_TYPE_DEBUG
, "debug reg" },
2798 { OPERAND_TYPE_FLOATREG
, "FReg" },
2799 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2800 { OPERAND_TYPE_SREG2
, "SReg2" },
2801 { OPERAND_TYPE_SREG3
, "SReg3" },
2802 { OPERAND_TYPE_ACC
, "Acc" },
2803 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2804 { OPERAND_TYPE_REGMMX
, "rMMX" },
2805 { OPERAND_TYPE_REGXMM
, "rXMM" },
2806 { OPERAND_TYPE_REGYMM
, "rYMM" },
2807 { OPERAND_TYPE_REGZMM
, "rZMM" },
2808 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2809 { OPERAND_TYPE_ESSEG
, "es" },
2813 pt (i386_operand_type t
)
2816 i386_operand_type a
;
2818 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2820 a
= operand_type_and (t
, type_names
[j
].mask
);
2821 if (!operand_type_all_zero (&a
))
2822 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2827 #endif /* DEBUG386 */
2829 static bfd_reloc_code_real_type
2830 reloc (unsigned int size
,
2833 bfd_reloc_code_real_type other
)
2835 if (other
!= NO_RELOC
)
2837 reloc_howto_type
*rel
;
2842 case BFD_RELOC_X86_64_GOT32
:
2843 return BFD_RELOC_X86_64_GOT64
;
2845 case BFD_RELOC_X86_64_GOTPLT64
:
2846 return BFD_RELOC_X86_64_GOTPLT64
;
2848 case BFD_RELOC_X86_64_PLTOFF64
:
2849 return BFD_RELOC_X86_64_PLTOFF64
;
2851 case BFD_RELOC_X86_64_GOTPC32
:
2852 other
= BFD_RELOC_X86_64_GOTPC64
;
2854 case BFD_RELOC_X86_64_GOTPCREL
:
2855 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2857 case BFD_RELOC_X86_64_TPOFF32
:
2858 other
= BFD_RELOC_X86_64_TPOFF64
;
2860 case BFD_RELOC_X86_64_DTPOFF32
:
2861 other
= BFD_RELOC_X86_64_DTPOFF64
;
2867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2868 if (other
== BFD_RELOC_SIZE32
)
2871 other
= BFD_RELOC_SIZE64
;
2874 as_bad (_("there are no pc-relative size relocations"));
2880 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2881 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2884 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2886 as_bad (_("unknown relocation (%u)"), other
);
2887 else if (size
!= bfd_get_reloc_size (rel
))
2888 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2889 bfd_get_reloc_size (rel
),
2891 else if (pcrel
&& !rel
->pc_relative
)
2892 as_bad (_("non-pc-relative relocation for pc-relative field"));
2893 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2895 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2897 as_bad (_("relocated field and relocation type differ in signedness"));
2906 as_bad (_("there are no unsigned pc-relative relocations"));
2909 case 1: return BFD_RELOC_8_PCREL
;
2910 case 2: return BFD_RELOC_16_PCREL
;
2911 case 4: return BFD_RELOC_32_PCREL
;
2912 case 8: return BFD_RELOC_64_PCREL
;
2914 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2921 case 4: return BFD_RELOC_X86_64_32S
;
2926 case 1: return BFD_RELOC_8
;
2927 case 2: return BFD_RELOC_16
;
2928 case 4: return BFD_RELOC_32
;
2929 case 8: return BFD_RELOC_64
;
2931 as_bad (_("cannot do %s %u byte relocation"),
2932 sign
> 0 ? "signed" : "unsigned", size
);
2938 /* Here we decide which fixups can be adjusted to make them relative to
2939 the beginning of the section instead of the symbol. Basically we need
2940 to make sure that the dynamic relocations are done correctly, so in
2941 some cases we force the original symbol to be used. */
2944 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2946 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2950 /* Don't adjust pc-relative references to merge sections in 64-bit
2952 if (use_rela_relocations
2953 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2957 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2958 and changed later by validate_fix. */
2959 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2960 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2963 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2964 for size relocations. */
2965 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2966 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2967 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2968 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2969 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2970 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2971 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2972 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2973 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2974 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2975 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2976 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2977 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2978 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2979 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2980 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2986 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2987 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2988 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2989 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2990 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2992 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2993 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2994 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3001 intel_float_operand (const char *mnemonic
)
3003 /* Note that the value returned is meaningful only for opcodes with (memory)
3004 operands, hence the code here is free to improperly handle opcodes that
3005 have no operands (for better performance and smaller code). */
3007 if (mnemonic
[0] != 'f')
3008 return 0; /* non-math */
3010 switch (mnemonic
[1])
3012 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3013 the fs segment override prefix not currently handled because no
3014 call path can make opcodes without operands get here */
3016 return 2 /* integer op */;
3018 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3019 return 3; /* fldcw/fldenv */
3022 if (mnemonic
[2] != 'o' /* fnop */)
3023 return 3; /* non-waiting control op */
3026 if (mnemonic
[2] == 's')
3027 return 3; /* frstor/frstpm */
3030 if (mnemonic
[2] == 'a')
3031 return 3; /* fsave */
3032 if (mnemonic
[2] == 't')
3034 switch (mnemonic
[3])
3036 case 'c': /* fstcw */
3037 case 'd': /* fstdw */
3038 case 'e': /* fstenv */
3039 case 's': /* fsts[gw] */
3045 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3046 return 0; /* fxsave/fxrstor are not really math ops */
3053 /* Build the VEX prefix. */
3056 build_vex_prefix (const insn_template
*t
)
3058 unsigned int register_specifier
;
3059 unsigned int implied_prefix
;
3060 unsigned int vector_length
;
3062 /* Check register specifier. */
3063 if (i
.vex
.register_specifier
)
3065 register_specifier
=
3066 ~register_number (i
.vex
.register_specifier
) & 0xf;
3067 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3070 register_specifier
= 0xf;
3072 /* Use 2-byte VEX prefix by swappping destination and source
3075 && i
.operands
== i
.reg_operands
3076 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3077 && i
.tm
.opcode_modifier
.s
3080 unsigned int xchg
= i
.operands
- 1;
3081 union i386_op temp_op
;
3082 i386_operand_type temp_type
;
3084 temp_type
= i
.types
[xchg
];
3085 i
.types
[xchg
] = i
.types
[0];
3086 i
.types
[0] = temp_type
;
3087 temp_op
= i
.op
[xchg
];
3088 i
.op
[xchg
] = i
.op
[0];
3091 gas_assert (i
.rm
.mode
== 3);
3095 i
.rm
.regmem
= i
.rm
.reg
;
3098 /* Use the next insn. */
3102 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3103 vector_length
= avxscalar
;
3105 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3107 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3112 case DATA_PREFIX_OPCODE
:
3115 case REPE_PREFIX_OPCODE
:
3118 case REPNE_PREFIX_OPCODE
:
3125 /* Use 2-byte VEX prefix if possible. */
3126 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3127 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3128 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3130 /* 2-byte VEX prefix. */
3134 i
.vex
.bytes
[0] = 0xc5;
3136 /* Check the REX.R bit. */
3137 r
= (i
.rex
& REX_R
) ? 0 : 1;
3138 i
.vex
.bytes
[1] = (r
<< 7
3139 | register_specifier
<< 3
3140 | vector_length
<< 2
3145 /* 3-byte VEX prefix. */
3150 switch (i
.tm
.opcode_modifier
.vexopcode
)
3154 i
.vex
.bytes
[0] = 0xc4;
3158 i
.vex
.bytes
[0] = 0xc4;
3162 i
.vex
.bytes
[0] = 0xc4;
3166 i
.vex
.bytes
[0] = 0x8f;
3170 i
.vex
.bytes
[0] = 0x8f;
3174 i
.vex
.bytes
[0] = 0x8f;
3180 /* The high 3 bits of the second VEX byte are 1's compliment
3181 of RXB bits from REX. */
3182 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3184 /* Check the REX.W bit. */
3185 w
= (i
.rex
& REX_W
) ? 1 : 0;
3186 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3189 i
.vex
.bytes
[2] = (w
<< 7
3190 | register_specifier
<< 3
3191 | vector_length
<< 2
3196 /* Build the EVEX prefix. */
3199 build_evex_prefix (void)
3201 unsigned int register_specifier
;
3202 unsigned int implied_prefix
;
3204 rex_byte vrex_used
= 0;
3206 /* Check register specifier. */
3207 if (i
.vex
.register_specifier
)
3209 gas_assert ((i
.vrex
& REX_X
) == 0);
3211 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3212 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3213 register_specifier
+= 8;
3214 /* The upper 16 registers are encoded in the fourth byte of the
3216 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3217 i
.vex
.bytes
[3] = 0x8;
3218 register_specifier
= ~register_specifier
& 0xf;
3222 register_specifier
= 0xf;
3224 /* Encode upper 16 vector index register in the fourth byte of
3226 if (!(i
.vrex
& REX_X
))
3227 i
.vex
.bytes
[3] = 0x8;
3232 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3237 case DATA_PREFIX_OPCODE
:
3240 case REPE_PREFIX_OPCODE
:
3243 case REPNE_PREFIX_OPCODE
:
3250 /* 4 byte EVEX prefix. */
3252 i
.vex
.bytes
[0] = 0x62;
3255 switch (i
.tm
.opcode_modifier
.vexopcode
)
3271 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3273 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3275 /* The fifth bit of the second EVEX byte is 1's compliment of the
3276 REX_R bit in VREX. */
3277 if (!(i
.vrex
& REX_R
))
3278 i
.vex
.bytes
[1] |= 0x10;
3282 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3284 /* When all operands are registers, the REX_X bit in REX is not
3285 used. We reuse it to encode the upper 16 registers, which is
3286 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3287 as 1's compliment. */
3288 if ((i
.vrex
& REX_B
))
3291 i
.vex
.bytes
[1] &= ~0x40;
3295 /* EVEX instructions shouldn't need the REX prefix. */
3296 i
.vrex
&= ~vrex_used
;
3297 gas_assert (i
.vrex
== 0);
3299 /* Check the REX.W bit. */
3300 w
= (i
.rex
& REX_W
) ? 1 : 0;
3301 if (i
.tm
.opcode_modifier
.vexw
)
3303 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3306 /* If w is not set it means we are dealing with WIG instruction. */
3309 if (evexwig
== evexw1
)
3313 /* Encode the U bit. */
3314 implied_prefix
|= 0x4;
3316 /* The third byte of the EVEX prefix. */
3317 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3319 /* The fourth byte of the EVEX prefix. */
3320 /* The zeroing-masking bit. */
3321 if (i
.mask
&& i
.mask
->zeroing
)
3322 i
.vex
.bytes
[3] |= 0x80;
3324 /* Don't always set the broadcast bit if there is no RC. */
3327 /* Encode the vector length. */
3328 unsigned int vec_length
;
3330 switch (i
.tm
.opcode_modifier
.evex
)
3332 case EVEXLIG
: /* LL' is ignored */
3333 vec_length
= evexlig
<< 5;
3336 vec_length
= 0 << 5;
3339 vec_length
= 1 << 5;
3342 vec_length
= 2 << 5;
3348 i
.vex
.bytes
[3] |= vec_length
;
3349 /* Encode the broadcast bit. */
3351 i
.vex
.bytes
[3] |= 0x10;
3355 if (i
.rounding
->type
!= saeonly
)
3356 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3358 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3361 if (i
.mask
&& i
.mask
->mask
)
3362 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3366 process_immext (void)
3370 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3373 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3374 with an opcode suffix which is coded in the same place as an
3375 8-bit immediate field would be.
3376 Here we check those operands and remove them afterwards. */
3379 for (x
= 0; x
< i
.operands
; x
++)
3380 if (register_number (i
.op
[x
].regs
) != x
)
3381 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3382 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3388 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3389 which is coded in the same place as an 8-bit immediate field
3390 would be. Here we fake an 8-bit immediate operand from the
3391 opcode suffix stored in tm.extension_opcode.
3393 AVX instructions also use this encoding, for some of
3394 3 argument instructions. */
3396 gas_assert (i
.imm_operands
<= 1
3398 || ((i
.tm
.opcode_modifier
.vex
3399 || i
.tm
.opcode_modifier
.evex
)
3400 && i
.operands
<= 4)));
3402 exp
= &im_expressions
[i
.imm_operands
++];
3403 i
.op
[i
.operands
].imms
= exp
;
3404 i
.types
[i
.operands
] = imm8
;
3406 exp
->X_op
= O_constant
;
3407 exp
->X_add_number
= i
.tm
.extension_opcode
;
3408 i
.tm
.extension_opcode
= None
;
3415 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3420 as_bad (_("invalid instruction `%s' after `%s'"),
3421 i
.tm
.name
, i
.hle_prefix
);
3424 if (i
.prefix
[LOCK_PREFIX
])
3426 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3430 case HLEPrefixRelease
:
3431 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3433 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3437 if (i
.mem_operands
== 0
3438 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3440 as_bad (_("memory destination needed for instruction `%s'"
3441 " after `xrelease'"), i
.tm
.name
);
3448 /* This is the guts of the machine-dependent assembler. LINE points to a
3449 machine dependent instruction. This function is supposed to emit
3450 the frags/bytes it assembles to. */
3453 md_assemble (char *line
)
3456 char mnemonic
[MAX_MNEM_SIZE
];
3457 const insn_template
*t
;
3459 /* Initialize globals. */
3460 memset (&i
, '\0', sizeof (i
));
3461 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3462 i
.reloc
[j
] = NO_RELOC
;
3463 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3464 memset (im_expressions
, '\0', sizeof (im_expressions
));
3465 save_stack_p
= save_stack
;
3467 /* First parse an instruction mnemonic & call i386_operand for the operands.
3468 We assume that the scrubber has arranged it so that line[0] is the valid
3469 start of a (possibly prefixed) mnemonic. */
3471 line
= parse_insn (line
, mnemonic
);
3475 line
= parse_operands (line
, mnemonic
);
3480 /* Now we've parsed the mnemonic into a set of templates, and have the
3481 operands at hand. */
3483 /* All intel opcodes have reversed operands except for "bound" and
3484 "enter". We also don't reverse intersegment "jmp" and "call"
3485 instructions with 2 immediate operands so that the immediate segment
3486 precedes the offset, as it does when in AT&T mode. */
3489 && (strcmp (mnemonic
, "bound") != 0)
3490 && (strcmp (mnemonic
, "invlpga") != 0)
3491 && !(operand_type_check (i
.types
[0], imm
)
3492 && operand_type_check (i
.types
[1], imm
)))
3495 /* The order of the immediates should be reversed
3496 for 2 immediates extrq and insertq instructions */
3497 if (i
.imm_operands
== 2
3498 && (strcmp (mnemonic
, "extrq") == 0
3499 || strcmp (mnemonic
, "insertq") == 0))
3500 swap_2_operands (0, 1);
3505 /* Don't optimize displacement for movabs since it only takes 64bit
3508 && i
.disp_encoding
!= disp_encoding_32bit
3509 && (flag_code
!= CODE_64BIT
3510 || strcmp (mnemonic
, "movabs") != 0))
3513 /* Next, we find a template that matches the given insn,
3514 making sure the overlap of the given operands types is consistent
3515 with the template operand types. */
3517 if (!(t
= match_template ()))
3520 if (sse_check
!= check_none
3521 && !i
.tm
.opcode_modifier
.noavx
3522 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3523 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3524 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3525 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3526 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3527 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3529 (sse_check
== check_warning
3531 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3534 /* Zap movzx and movsx suffix. The suffix has been set from
3535 "word ptr" or "byte ptr" on the source operand in Intel syntax
3536 or extracted from mnemonic in AT&T syntax. But we'll use
3537 the destination register to choose the suffix for encoding. */
3538 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3540 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3541 there is no suffix, the default will be byte extension. */
3542 if (i
.reg_operands
!= 2
3545 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3550 if (i
.tm
.opcode_modifier
.fwait
)
3551 if (!add_prefix (FWAIT_OPCODE
))
3554 /* Check if REP prefix is OK. */
3555 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3557 as_bad (_("invalid instruction `%s' after `%s'"),
3558 i
.tm
.name
, i
.rep_prefix
);
3562 /* Check for lock without a lockable instruction. Destination operand
3563 must be memory unless it is xchg (0x86). */
3564 if (i
.prefix
[LOCK_PREFIX
]
3565 && (!i
.tm
.opcode_modifier
.islockable
3566 || i
.mem_operands
== 0
3567 || (i
.tm
.base_opcode
!= 0x86
3568 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3570 as_bad (_("expecting lockable instruction after `lock'"));
3574 /* Check if HLE prefix is OK. */
3575 if (i
.hle_prefix
&& !check_hle ())
3578 /* Check BND prefix. */
3579 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3580 as_bad (_("expecting valid branch instruction after `bnd'"));
3582 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3583 && flag_code
== CODE_64BIT
3584 && i
.prefix
[ADDR_PREFIX
])
3585 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3587 /* Insert BND prefix. */
3589 && i
.tm
.opcode_modifier
.bndprefixok
3590 && !i
.prefix
[BND_PREFIX
])
3591 add_prefix (BND_PREFIX_OPCODE
);
3593 /* Check string instruction segment overrides. */
3594 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3596 if (!check_string ())
3598 i
.disp_operands
= 0;
3601 if (!process_suffix ())
3604 /* Update operand types. */
3605 for (j
= 0; j
< i
.operands
; j
++)
3606 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3608 /* Make still unresolved immediate matches conform to size of immediate
3609 given in i.suffix. */
3610 if (!finalize_imm ())
3613 if (i
.types
[0].bitfield
.imm1
)
3614 i
.imm_operands
= 0; /* kludge for shift insns. */
3616 /* We only need to check those implicit registers for instructions
3617 with 3 operands or less. */
3618 if (i
.operands
<= 3)
3619 for (j
= 0; j
< i
.operands
; j
++)
3620 if (i
.types
[j
].bitfield
.inoutportreg
3621 || i
.types
[j
].bitfield
.shiftcount
3622 || i
.types
[j
].bitfield
.acc
3623 || i
.types
[j
].bitfield
.floatacc
)
3626 /* ImmExt should be processed after SSE2AVX. */
3627 if (!i
.tm
.opcode_modifier
.sse2avx
3628 && i
.tm
.opcode_modifier
.immext
)
3631 /* For insns with operands there are more diddles to do to the opcode. */
3634 if (!process_operands ())
3637 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3639 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3640 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3643 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3645 if (flag_code
== CODE_16BIT
)
3647 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3652 if (i
.tm
.opcode_modifier
.vex
)
3653 build_vex_prefix (t
);
3655 build_evex_prefix ();
3658 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3659 instructions may define INT_OPCODE as well, so avoid this corner
3660 case for those instructions that use MODRM. */
3661 if (i
.tm
.base_opcode
== INT_OPCODE
3662 && !i
.tm
.opcode_modifier
.modrm
3663 && i
.op
[0].imms
->X_add_number
== 3)
3665 i
.tm
.base_opcode
= INT3_OPCODE
;
3669 if ((i
.tm
.opcode_modifier
.jump
3670 || i
.tm
.opcode_modifier
.jumpbyte
3671 || i
.tm
.opcode_modifier
.jumpdword
)
3672 && i
.op
[0].disps
->X_op
== O_constant
)
3674 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3675 the absolute address given by the constant. Since ix86 jumps and
3676 calls are pc relative, we need to generate a reloc. */
3677 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3678 i
.op
[0].disps
->X_op
= O_symbol
;
3681 if (i
.tm
.opcode_modifier
.rex64
)
3684 /* For 8 bit registers we need an empty rex prefix. Also if the
3685 instruction already has a prefix, we need to convert old
3686 registers to new ones. */
3688 if ((i
.types
[0].bitfield
.reg8
3689 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3690 || (i
.types
[1].bitfield
.reg8
3691 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3692 || ((i
.types
[0].bitfield
.reg8
3693 || i
.types
[1].bitfield
.reg8
)
3698 i
.rex
|= REX_OPCODE
;
3699 for (x
= 0; x
< 2; x
++)
3701 /* Look for 8 bit operand that uses old registers. */
3702 if (i
.types
[x
].bitfield
.reg8
3703 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3705 /* In case it is "hi" register, give up. */
3706 if (i
.op
[x
].regs
->reg_num
> 3)
3707 as_bad (_("can't encode register '%s%s' in an "
3708 "instruction requiring REX prefix."),
3709 register_prefix
, i
.op
[x
].regs
->reg_name
);
3711 /* Otherwise it is equivalent to the extended register.
3712 Since the encoding doesn't change this is merely
3713 cosmetic cleanup for debug output. */
3715 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3721 add_prefix (REX_OPCODE
| i
.rex
);
3723 /* We are ready to output the insn. */
3728 parse_insn (char *line
, char *mnemonic
)
3731 char *token_start
= l
;
3734 const insn_template
*t
;
3740 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3745 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3747 as_bad (_("no such instruction: `%s'"), token_start
);
3752 if (!is_space_char (*l
)
3753 && *l
!= END_OF_INSN
3755 || (*l
!= PREFIX_SEPARATOR
3758 as_bad (_("invalid character %s in mnemonic"),
3759 output_invalid (*l
));
3762 if (token_start
== l
)
3764 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3765 as_bad (_("expecting prefix; got nothing"));
3767 as_bad (_("expecting mnemonic; got nothing"));
3771 /* Look up instruction (or prefix) via hash table. */
3772 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3774 if (*l
!= END_OF_INSN
3775 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3776 && current_templates
3777 && current_templates
->start
->opcode_modifier
.isprefix
)
3779 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3781 as_bad ((flag_code
!= CODE_64BIT
3782 ? _("`%s' is only supported in 64-bit mode")
3783 : _("`%s' is not supported in 64-bit mode")),
3784 current_templates
->start
->name
);
3787 /* If we are in 16-bit mode, do not allow addr16 or data16.
3788 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3789 if ((current_templates
->start
->opcode_modifier
.size16
3790 || current_templates
->start
->opcode_modifier
.size32
)
3791 && flag_code
!= CODE_64BIT
3792 && (current_templates
->start
->opcode_modifier
.size32
3793 ^ (flag_code
== CODE_16BIT
)))
3795 as_bad (_("redundant %s prefix"),
3796 current_templates
->start
->name
);
3799 /* Add prefix, checking for repeated prefixes. */
3800 switch (add_prefix (current_templates
->start
->base_opcode
))
3805 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3806 i
.hle_prefix
= current_templates
->start
->name
;
3807 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3808 i
.bnd_prefix
= current_templates
->start
->name
;
3810 i
.rep_prefix
= current_templates
->start
->name
;
3815 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3822 if (!current_templates
)
3824 /* Check if we should swap operand or force 32bit displacement in
3826 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3828 else if (mnem_p
- 3 == dot_p
3831 i
.disp_encoding
= disp_encoding_8bit
;
3832 else if (mnem_p
- 4 == dot_p
3836 i
.disp_encoding
= disp_encoding_32bit
;
3841 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3844 if (!current_templates
)
3847 /* See if we can get a match by trimming off a suffix. */
3850 case WORD_MNEM_SUFFIX
:
3851 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3852 i
.suffix
= SHORT_MNEM_SUFFIX
;
3854 case BYTE_MNEM_SUFFIX
:
3855 case QWORD_MNEM_SUFFIX
:
3856 i
.suffix
= mnem_p
[-1];
3858 current_templates
= (const templates
*) hash_find (op_hash
,
3861 case SHORT_MNEM_SUFFIX
:
3862 case LONG_MNEM_SUFFIX
:
3865 i
.suffix
= mnem_p
[-1];
3867 current_templates
= (const templates
*) hash_find (op_hash
,
3876 if (intel_float_operand (mnemonic
) == 1)
3877 i
.suffix
= SHORT_MNEM_SUFFIX
;
3879 i
.suffix
= LONG_MNEM_SUFFIX
;
3881 current_templates
= (const templates
*) hash_find (op_hash
,
3886 if (!current_templates
)
3888 as_bad (_("no such instruction: `%s'"), token_start
);
3893 if (current_templates
->start
->opcode_modifier
.jump
3894 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3896 /* Check for a branch hint. We allow ",pt" and ",pn" for
3897 predict taken and predict not taken respectively.
3898 I'm not sure that branch hints actually do anything on loop
3899 and jcxz insns (JumpByte) for current Pentium4 chips. They
3900 may work in the future and it doesn't hurt to accept them
3902 if (l
[0] == ',' && l
[1] == 'p')
3906 if (!add_prefix (DS_PREFIX_OPCODE
))
3910 else if (l
[2] == 'n')
3912 if (!add_prefix (CS_PREFIX_OPCODE
))
3918 /* Any other comma loses. */
3921 as_bad (_("invalid character %s in mnemonic"),
3922 output_invalid (*l
));
3926 /* Check if instruction is supported on specified architecture. */
3928 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3930 supported
|= cpu_flags_match (t
);
3931 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3935 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3937 as_bad (flag_code
== CODE_64BIT
3938 ? _("`%s' is not supported in 64-bit mode")
3939 : _("`%s' is only supported in 64-bit mode"),
3940 current_templates
->start
->name
);
3943 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3945 as_bad (_("`%s' is not supported on `%s%s'"),
3946 current_templates
->start
->name
,
3947 cpu_arch_name
? cpu_arch_name
: default_arch
,
3948 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3953 if (!cpu_arch_flags
.bitfield
.cpui386
3954 && (flag_code
!= CODE_16BIT
))
3956 as_warn (_("use .code16 to ensure correct addressing mode"));
3963 parse_operands (char *l
, const char *mnemonic
)
3967 /* 1 if operand is pending after ','. */
3968 unsigned int expecting_operand
= 0;
3970 /* Non-zero if operand parens not balanced. */
3971 unsigned int paren_not_balanced
;
3973 while (*l
!= END_OF_INSN
)
3975 /* Skip optional white space before operand. */
3976 if (is_space_char (*l
))
3978 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3980 as_bad (_("invalid character %s before operand %d"),
3981 output_invalid (*l
),
3985 token_start
= l
; /* after white space */
3986 paren_not_balanced
= 0;
3987 while (paren_not_balanced
|| *l
!= ',')
3989 if (*l
== END_OF_INSN
)
3991 if (paren_not_balanced
)
3994 as_bad (_("unbalanced parenthesis in operand %d."),
3997 as_bad (_("unbalanced brackets in operand %d."),
4002 break; /* we are done */
4004 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4006 as_bad (_("invalid character %s in operand %d"),
4007 output_invalid (*l
),
4014 ++paren_not_balanced
;
4016 --paren_not_balanced
;
4021 ++paren_not_balanced
;
4023 --paren_not_balanced
;
4027 if (l
!= token_start
)
4028 { /* Yes, we've read in another operand. */
4029 unsigned int operand_ok
;
4030 this_operand
= i
.operands
++;
4031 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4032 if (i
.operands
> MAX_OPERANDS
)
4034 as_bad (_("spurious operands; (%d operands/instruction max)"),
4038 /* Now parse operand adding info to 'i' as we go along. */
4039 END_STRING_AND_SAVE (l
);
4043 i386_intel_operand (token_start
,
4044 intel_float_operand (mnemonic
));
4046 operand_ok
= i386_att_operand (token_start
);
4048 RESTORE_END_STRING (l
);
4054 if (expecting_operand
)
4056 expecting_operand_after_comma
:
4057 as_bad (_("expecting operand after ','; got nothing"));
4062 as_bad (_("expecting operand before ','; got nothing"));
4067 /* Now *l must be either ',' or END_OF_INSN. */
4070 if (*++l
== END_OF_INSN
)
4072 /* Just skip it, if it's \n complain. */
4073 goto expecting_operand_after_comma
;
4075 expecting_operand
= 1;
4082 swap_2_operands (int xchg1
, int xchg2
)
4084 union i386_op temp_op
;
4085 i386_operand_type temp_type
;
4086 enum bfd_reloc_code_real temp_reloc
;
4088 temp_type
= i
.types
[xchg2
];
4089 i
.types
[xchg2
] = i
.types
[xchg1
];
4090 i
.types
[xchg1
] = temp_type
;
4091 temp_op
= i
.op
[xchg2
];
4092 i
.op
[xchg2
] = i
.op
[xchg1
];
4093 i
.op
[xchg1
] = temp_op
;
4094 temp_reloc
= i
.reloc
[xchg2
];
4095 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4096 i
.reloc
[xchg1
] = temp_reloc
;
4100 if (i
.mask
->operand
== xchg1
)
4101 i
.mask
->operand
= xchg2
;
4102 else if (i
.mask
->operand
== xchg2
)
4103 i
.mask
->operand
= xchg1
;
4107 if (i
.broadcast
->operand
== xchg1
)
4108 i
.broadcast
->operand
= xchg2
;
4109 else if (i
.broadcast
->operand
== xchg2
)
4110 i
.broadcast
->operand
= xchg1
;
4114 if (i
.rounding
->operand
== xchg1
)
4115 i
.rounding
->operand
= xchg2
;
4116 else if (i
.rounding
->operand
== xchg2
)
4117 i
.rounding
->operand
= xchg1
;
4122 swap_operands (void)
4128 swap_2_operands (1, i
.operands
- 2);
4131 swap_2_operands (0, i
.operands
- 1);
4137 if (i
.mem_operands
== 2)
4139 const seg_entry
*temp_seg
;
4140 temp_seg
= i
.seg
[0];
4141 i
.seg
[0] = i
.seg
[1];
4142 i
.seg
[1] = temp_seg
;
4146 /* Try to ensure constant immediates are represented in the smallest
4151 char guess_suffix
= 0;
4155 guess_suffix
= i
.suffix
;
4156 else if (i
.reg_operands
)
4158 /* Figure out a suffix from the last register operand specified.
4159 We can't do this properly yet, ie. excluding InOutPortReg,
4160 but the following works for instructions with immediates.
4161 In any case, we can't set i.suffix yet. */
4162 for (op
= i
.operands
; --op
>= 0;)
4163 if (i
.types
[op
].bitfield
.reg8
)
4165 guess_suffix
= BYTE_MNEM_SUFFIX
;
4168 else if (i
.types
[op
].bitfield
.reg16
)
4170 guess_suffix
= WORD_MNEM_SUFFIX
;
4173 else if (i
.types
[op
].bitfield
.reg32
)
4175 guess_suffix
= LONG_MNEM_SUFFIX
;
4178 else if (i
.types
[op
].bitfield
.reg64
)
4180 guess_suffix
= QWORD_MNEM_SUFFIX
;
4184 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4185 guess_suffix
= WORD_MNEM_SUFFIX
;
4187 for (op
= i
.operands
; --op
>= 0;)
4188 if (operand_type_check (i
.types
[op
], imm
))
4190 switch (i
.op
[op
].imms
->X_op
)
4193 /* If a suffix is given, this operand may be shortened. */
4194 switch (guess_suffix
)
4196 case LONG_MNEM_SUFFIX
:
4197 i
.types
[op
].bitfield
.imm32
= 1;
4198 i
.types
[op
].bitfield
.imm64
= 1;
4200 case WORD_MNEM_SUFFIX
:
4201 i
.types
[op
].bitfield
.imm16
= 1;
4202 i
.types
[op
].bitfield
.imm32
= 1;
4203 i
.types
[op
].bitfield
.imm32s
= 1;
4204 i
.types
[op
].bitfield
.imm64
= 1;
4206 case BYTE_MNEM_SUFFIX
:
4207 i
.types
[op
].bitfield
.imm8
= 1;
4208 i
.types
[op
].bitfield
.imm8s
= 1;
4209 i
.types
[op
].bitfield
.imm16
= 1;
4210 i
.types
[op
].bitfield
.imm32
= 1;
4211 i
.types
[op
].bitfield
.imm32s
= 1;
4212 i
.types
[op
].bitfield
.imm64
= 1;
4216 /* If this operand is at most 16 bits, convert it
4217 to a signed 16 bit number before trying to see
4218 whether it will fit in an even smaller size.
4219 This allows a 16-bit operand such as $0xffe0 to
4220 be recognised as within Imm8S range. */
4221 if ((i
.types
[op
].bitfield
.imm16
)
4222 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4224 i
.op
[op
].imms
->X_add_number
=
4225 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4227 if ((i
.types
[op
].bitfield
.imm32
)
4228 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4231 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4232 ^ ((offsetT
) 1 << 31))
4233 - ((offsetT
) 1 << 31));
4236 = operand_type_or (i
.types
[op
],
4237 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4239 /* We must avoid matching of Imm32 templates when 64bit
4240 only immediate is available. */
4241 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4242 i
.types
[op
].bitfield
.imm32
= 0;
4249 /* Symbols and expressions. */
4251 /* Convert symbolic operand to proper sizes for matching, but don't
4252 prevent matching a set of insns that only supports sizes other
4253 than those matching the insn suffix. */
4255 i386_operand_type mask
, allowed
;
4256 const insn_template
*t
;
4258 operand_type_set (&mask
, 0);
4259 operand_type_set (&allowed
, 0);
4261 for (t
= current_templates
->start
;
4262 t
< current_templates
->end
;
4264 allowed
= operand_type_or (allowed
,
4265 t
->operand_types
[op
]);
4266 switch (guess_suffix
)
4268 case QWORD_MNEM_SUFFIX
:
4269 mask
.bitfield
.imm64
= 1;
4270 mask
.bitfield
.imm32s
= 1;
4272 case LONG_MNEM_SUFFIX
:
4273 mask
.bitfield
.imm32
= 1;
4275 case WORD_MNEM_SUFFIX
:
4276 mask
.bitfield
.imm16
= 1;
4278 case BYTE_MNEM_SUFFIX
:
4279 mask
.bitfield
.imm8
= 1;
4284 allowed
= operand_type_and (mask
, allowed
);
4285 if (!operand_type_all_zero (&allowed
))
4286 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4293 /* Try to use the smallest displacement type too. */
4295 optimize_disp (void)
4299 for (op
= i
.operands
; --op
>= 0;)
4300 if (operand_type_check (i
.types
[op
], disp
))
4302 if (i
.op
[op
].disps
->X_op
== O_constant
)
4304 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4306 if (i
.types
[op
].bitfield
.disp16
4307 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4309 /* If this operand is at most 16 bits, convert
4310 to a signed 16 bit number and don't use 64bit
4312 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4313 i
.types
[op
].bitfield
.disp64
= 0;
4315 if (i
.types
[op
].bitfield
.disp32
4316 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4318 /* If this operand is at most 32 bits, convert
4319 to a signed 32 bit number and don't use 64bit
4321 op_disp
&= (((offsetT
) 2 << 31) - 1);
4322 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4323 i
.types
[op
].bitfield
.disp64
= 0;
4325 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4327 i
.types
[op
].bitfield
.disp8
= 0;
4328 i
.types
[op
].bitfield
.disp16
= 0;
4329 i
.types
[op
].bitfield
.disp32
= 0;
4330 i
.types
[op
].bitfield
.disp32s
= 0;
4331 i
.types
[op
].bitfield
.disp64
= 0;
4335 else if (flag_code
== CODE_64BIT
)
4337 if (fits_in_signed_long (op_disp
))
4339 i
.types
[op
].bitfield
.disp64
= 0;
4340 i
.types
[op
].bitfield
.disp32s
= 1;
4342 if (i
.prefix
[ADDR_PREFIX
]
4343 && fits_in_unsigned_long (op_disp
))
4344 i
.types
[op
].bitfield
.disp32
= 1;
4346 if ((i
.types
[op
].bitfield
.disp32
4347 || i
.types
[op
].bitfield
.disp32s
4348 || i
.types
[op
].bitfield
.disp16
)
4349 && fits_in_signed_byte (op_disp
))
4350 i
.types
[op
].bitfield
.disp8
= 1;
4352 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4353 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4355 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4356 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4357 i
.types
[op
].bitfield
.disp8
= 0;
4358 i
.types
[op
].bitfield
.disp16
= 0;
4359 i
.types
[op
].bitfield
.disp32
= 0;
4360 i
.types
[op
].bitfield
.disp32s
= 0;
4361 i
.types
[op
].bitfield
.disp64
= 0;
4364 /* We only support 64bit displacement on constants. */
4365 i
.types
[op
].bitfield
.disp64
= 0;
4369 /* Check if operands are valid for the instruction. */
4372 check_VecOperands (const insn_template
*t
)
4376 /* Without VSIB byte, we can't have a vector register for index. */
4377 if (!t
->opcode_modifier
.vecsib
4379 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4380 || i
.index_reg
->reg_type
.bitfield
.regymm
4381 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4383 i
.error
= unsupported_vector_index_register
;
4387 /* Check if default mask is allowed. */
4388 if (t
->opcode_modifier
.nodefmask
4389 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4391 i
.error
= no_default_mask
;
4395 /* For VSIB byte, we need a vector register for index, and all vector
4396 registers must be distinct. */
4397 if (t
->opcode_modifier
.vecsib
)
4400 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4401 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4402 || (t
->opcode_modifier
.vecsib
== VecSIB256
4403 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4404 || (t
->opcode_modifier
.vecsib
== VecSIB512
4405 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4407 i
.error
= invalid_vsib_address
;
4411 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4412 if (i
.reg_operands
== 2 && !i
.mask
)
4414 gas_assert (i
.types
[0].bitfield
.regxmm
4415 || i
.types
[0].bitfield
.regymm
);
4416 gas_assert (i
.types
[2].bitfield
.regxmm
4417 || i
.types
[2].bitfield
.regymm
);
4418 if (operand_check
== check_none
)
4420 if (register_number (i
.op
[0].regs
)
4421 != register_number (i
.index_reg
)
4422 && register_number (i
.op
[2].regs
)
4423 != register_number (i
.index_reg
)
4424 && register_number (i
.op
[0].regs
)
4425 != register_number (i
.op
[2].regs
))
4427 if (operand_check
== check_error
)
4429 i
.error
= invalid_vector_register_set
;
4432 as_warn (_("mask, index, and destination registers should be distinct"));
4434 else if (i
.reg_operands
== 1 && i
.mask
)
4436 if ((i
.types
[1].bitfield
.regymm
4437 || i
.types
[1].bitfield
.regzmm
)
4438 && (register_number (i
.op
[1].regs
)
4439 == register_number (i
.index_reg
)))
4441 if (operand_check
== check_error
)
4443 i
.error
= invalid_vector_register_set
;
4446 if (operand_check
!= check_none
)
4447 as_warn (_("index and destination registers should be distinct"));
4452 /* Check if broadcast is supported by the instruction and is applied
4453 to the memory operand. */
4456 int broadcasted_opnd_size
;
4458 /* Check if specified broadcast is supported in this instruction,
4459 and it's applied to memory operand of DWORD or QWORD type,
4460 depending on VecESize. */
4461 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4462 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4463 || (t
->opcode_modifier
.vecesize
== 0
4464 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4465 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4466 || (t
->opcode_modifier
.vecesize
== 1
4467 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4468 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4471 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4472 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4473 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4474 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4475 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4476 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4477 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4478 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4479 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4483 if ((broadcasted_opnd_size
== 256
4484 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4485 || (broadcasted_opnd_size
== 512
4486 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4489 i
.error
= unsupported_broadcast
;
4493 /* If broadcast is supported in this instruction, we need to check if
4494 operand of one-element size isn't specified without broadcast. */
4495 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4497 /* Find memory operand. */
4498 for (op
= 0; op
< i
.operands
; op
++)
4499 if (operand_type_check (i
.types
[op
], anymem
))
4501 gas_assert (op
< i
.operands
);
4502 /* Check size of the memory operand. */
4503 if ((t
->opcode_modifier
.vecesize
== 0
4504 && i
.types
[op
].bitfield
.dword
)
4505 || (t
->opcode_modifier
.vecesize
== 1
4506 && i
.types
[op
].bitfield
.qword
))
4508 i
.error
= broadcast_needed
;
4513 /* Check if requested masking is supported. */
4515 && (!t
->opcode_modifier
.masking
4517 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4519 i
.error
= unsupported_masking
;
4523 /* Check if masking is applied to dest operand. */
4524 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4526 i
.error
= mask_not_on_destination
;
4533 if ((i
.rounding
->type
!= saeonly
4534 && !t
->opcode_modifier
.staticrounding
)
4535 || (i
.rounding
->type
== saeonly
4536 && (t
->opcode_modifier
.staticrounding
4537 || !t
->opcode_modifier
.sae
)))
4539 i
.error
= unsupported_rc_sae
;
4542 /* If the instruction has several immediate operands and one of
4543 them is rounding, the rounding operand should be the last
4544 immediate operand. */
4545 if (i
.imm_operands
> 1
4546 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4548 i
.error
= rc_sae_operand_not_last_imm
;
4553 /* Check vector Disp8 operand. */
4554 if (t
->opcode_modifier
.disp8memshift
)
4557 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4559 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4561 for (op
= 0; op
< i
.operands
; op
++)
4562 if (operand_type_check (i
.types
[op
], disp
)
4563 && i
.op
[op
].disps
->X_op
== O_constant
)
4565 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4566 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4567 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4570 i
.types
[op
].bitfield
.vec_disp8
= 1;
4573 /* Vector insn can only have Vec_Disp8/Disp32 in
4574 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4576 i
.types
[op
].bitfield
.disp8
= 0;
4577 if (flag_code
!= CODE_16BIT
)
4578 i
.types
[op
].bitfield
.disp16
= 0;
4581 else if (flag_code
!= CODE_16BIT
)
4583 /* One form of this instruction supports vector Disp8.
4584 Try vector Disp8 if we need to use Disp32. */
4585 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4587 i
.error
= try_vector_disp8
;
4599 /* Check if operands are valid for the instruction. Update VEX
4603 VEX_check_operands (const insn_template
*t
)
4605 /* VREX is only valid with EVEX prefix. */
4606 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4608 i
.error
= invalid_register_operand
;
4612 if (!t
->opcode_modifier
.vex
)
4615 /* Only check VEX_Imm4, which must be the first operand. */
4616 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4618 if (i
.op
[0].imms
->X_op
!= O_constant
4619 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4625 /* Turn off Imm8 so that update_imm won't complain. */
4626 i
.types
[0] = vec_imm4
;
4632 static const insn_template
*
4633 match_template (void)
4635 /* Points to template once we've found it. */
4636 const insn_template
*t
;
4637 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4638 i386_operand_type overlap4
;
4639 unsigned int found_reverse_match
;
4640 i386_opcode_modifier suffix_check
;
4641 i386_operand_type operand_types
[MAX_OPERANDS
];
4642 int addr_prefix_disp
;
4644 unsigned int found_cpu_match
;
4645 unsigned int check_register
;
4646 enum i386_error specific_error
= 0;
4648 #if MAX_OPERANDS != 5
4649 # error "MAX_OPERANDS must be 5."
4652 found_reverse_match
= 0;
4653 addr_prefix_disp
= -1;
4655 memset (&suffix_check
, 0, sizeof (suffix_check
));
4656 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4657 suffix_check
.no_bsuf
= 1;
4658 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4659 suffix_check
.no_wsuf
= 1;
4660 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4661 suffix_check
.no_ssuf
= 1;
4662 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4663 suffix_check
.no_lsuf
= 1;
4664 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4665 suffix_check
.no_qsuf
= 1;
4666 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4667 suffix_check
.no_ldsuf
= 1;
4669 /* Must have right number of operands. */
4670 i
.error
= number_of_operands_mismatch
;
4672 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4674 addr_prefix_disp
= -1;
4676 if (i
.operands
!= t
->operands
)
4679 /* Check processor support. */
4680 i
.error
= unsupported
;
4681 found_cpu_match
= (cpu_flags_match (t
)
4682 == CPU_FLAGS_PERFECT_MATCH
);
4683 if (!found_cpu_match
)
4686 /* Check old gcc support. */
4687 i
.error
= old_gcc_only
;
4688 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4691 /* Check AT&T mnemonic. */
4692 i
.error
= unsupported_with_intel_mnemonic
;
4693 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4696 /* Check AT&T/Intel syntax. */
4697 i
.error
= unsupported_syntax
;
4698 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4699 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4702 /* Check the suffix, except for some instructions in intel mode. */
4703 i
.error
= invalid_instruction_suffix
;
4704 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4705 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4706 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4707 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4708 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4709 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4710 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4713 if (!operand_size_match (t
))
4716 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4717 operand_types
[j
] = t
->operand_types
[j
];
4719 /* In general, don't allow 64-bit operands in 32-bit mode. */
4720 if (i
.suffix
== QWORD_MNEM_SUFFIX
4721 && flag_code
!= CODE_64BIT
4723 ? (!t
->opcode_modifier
.ignoresize
4724 && !intel_float_operand (t
->name
))
4725 : intel_float_operand (t
->name
) != 2)
4726 && ((!operand_types
[0].bitfield
.regmmx
4727 && !operand_types
[0].bitfield
.regxmm
4728 && !operand_types
[0].bitfield
.regymm
4729 && !operand_types
[0].bitfield
.regzmm
)
4730 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4731 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4732 && operand_types
[t
->operands
> 1].bitfield
.regymm
4733 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4734 && (t
->base_opcode
!= 0x0fc7
4735 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4738 /* In general, don't allow 32-bit operands on pre-386. */
4739 else if (i
.suffix
== LONG_MNEM_SUFFIX
4740 && !cpu_arch_flags
.bitfield
.cpui386
4742 ? (!t
->opcode_modifier
.ignoresize
4743 && !intel_float_operand (t
->name
))
4744 : intel_float_operand (t
->name
) != 2)
4745 && ((!operand_types
[0].bitfield
.regmmx
4746 && !operand_types
[0].bitfield
.regxmm
)
4747 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4748 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4751 /* Do not verify operands when there are none. */
4755 /* We've found a match; break out of loop. */
4759 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4760 into Disp32/Disp16/Disp32 operand. */
4761 if (i
.prefix
[ADDR_PREFIX
] != 0)
4763 /* There should be only one Disp operand. */
4767 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4769 if (operand_types
[j
].bitfield
.disp16
)
4771 addr_prefix_disp
= j
;
4772 operand_types
[j
].bitfield
.disp32
= 1;
4773 operand_types
[j
].bitfield
.disp16
= 0;
4779 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4781 if (operand_types
[j
].bitfield
.disp32
)
4783 addr_prefix_disp
= j
;
4784 operand_types
[j
].bitfield
.disp32
= 0;
4785 operand_types
[j
].bitfield
.disp16
= 1;
4791 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4793 if (operand_types
[j
].bitfield
.disp64
)
4795 addr_prefix_disp
= j
;
4796 operand_types
[j
].bitfield
.disp64
= 0;
4797 operand_types
[j
].bitfield
.disp32
= 1;
4805 /* We check register size if needed. */
4806 check_register
= t
->opcode_modifier
.checkregsize
;
4807 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4808 switch (t
->operands
)
4811 if (!operand_type_match (overlap0
, i
.types
[0]))
4815 /* xchg %eax, %eax is a special case. It is an aliase for nop
4816 only in 32bit mode and we can use opcode 0x90. In 64bit
4817 mode, we can't use 0x90 for xchg %eax, %eax since it should
4818 zero-extend %eax to %rax. */
4819 if (flag_code
== CODE_64BIT
4820 && t
->base_opcode
== 0x90
4821 && operand_type_equal (&i
.types
[0], &acc32
)
4822 && operand_type_equal (&i
.types
[1], &acc32
))
4826 /* If we swap operand in encoding, we either match
4827 the next one or reverse direction of operands. */
4828 if (t
->opcode_modifier
.s
)
4830 else if (t
->opcode_modifier
.d
)
4835 /* If we swap operand in encoding, we match the next one. */
4836 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4840 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4841 if (!operand_type_match (overlap0
, i
.types
[0])
4842 || !operand_type_match (overlap1
, i
.types
[1])
4844 && !operand_type_register_match (overlap0
, i
.types
[0],
4846 overlap1
, i
.types
[1],
4849 /* Check if other direction is valid ... */
4850 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4854 /* Try reversing direction of operands. */
4855 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4856 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4857 if (!operand_type_match (overlap0
, i
.types
[0])
4858 || !operand_type_match (overlap1
, i
.types
[1])
4860 && !operand_type_register_match (overlap0
,
4867 /* Does not match either direction. */
4870 /* found_reverse_match holds which of D or FloatDR
4872 if (t
->opcode_modifier
.d
)
4873 found_reverse_match
= Opcode_D
;
4874 else if (t
->opcode_modifier
.floatd
)
4875 found_reverse_match
= Opcode_FloatD
;
4877 found_reverse_match
= 0;
4878 if (t
->opcode_modifier
.floatr
)
4879 found_reverse_match
|= Opcode_FloatR
;
4883 /* Found a forward 2 operand match here. */
4884 switch (t
->operands
)
4887 overlap4
= operand_type_and (i
.types
[4],
4890 overlap3
= operand_type_and (i
.types
[3],
4893 overlap2
= operand_type_and (i
.types
[2],
4898 switch (t
->operands
)
4901 if (!operand_type_match (overlap4
, i
.types
[4])
4902 || !operand_type_register_match (overlap3
,
4910 if (!operand_type_match (overlap3
, i
.types
[3])
4912 && !operand_type_register_match (overlap2
,
4920 /* Here we make use of the fact that there are no
4921 reverse match 3 operand instructions, and all 3
4922 operand instructions only need to be checked for
4923 register consistency between operands 2 and 3. */
4924 if (!operand_type_match (overlap2
, i
.types
[2])
4926 && !operand_type_register_match (overlap1
,
4936 /* Found either forward/reverse 2, 3 or 4 operand match here:
4937 slip through to break. */
4939 if (!found_cpu_match
)
4941 found_reverse_match
= 0;
4945 /* Check if vector and VEX operands are valid. */
4946 if (check_VecOperands (t
) || VEX_check_operands (t
))
4948 specific_error
= i
.error
;
4952 /* We've found a match; break out of loop. */
4956 if (t
== current_templates
->end
)
4958 /* We found no match. */
4959 const char *err_msg
;
4960 switch (specific_error
? specific_error
: i
.error
)
4964 case operand_size_mismatch
:
4965 err_msg
= _("operand size mismatch");
4967 case operand_type_mismatch
:
4968 err_msg
= _("operand type mismatch");
4970 case register_type_mismatch
:
4971 err_msg
= _("register type mismatch");
4973 case number_of_operands_mismatch
:
4974 err_msg
= _("number of operands mismatch");
4976 case invalid_instruction_suffix
:
4977 err_msg
= _("invalid instruction suffix");
4980 err_msg
= _("constant doesn't fit in 4 bits");
4983 err_msg
= _("only supported with old gcc");
4985 case unsupported_with_intel_mnemonic
:
4986 err_msg
= _("unsupported with Intel mnemonic");
4988 case unsupported_syntax
:
4989 err_msg
= _("unsupported syntax");
4992 as_bad (_("unsupported instruction `%s'"),
4993 current_templates
->start
->name
);
4995 case invalid_vsib_address
:
4996 err_msg
= _("invalid VSIB address");
4998 case invalid_vector_register_set
:
4999 err_msg
= _("mask, index, and destination registers must be distinct");
5001 case unsupported_vector_index_register
:
5002 err_msg
= _("unsupported vector index register");
5004 case unsupported_broadcast
:
5005 err_msg
= _("unsupported broadcast");
5007 case broadcast_not_on_src_operand
:
5008 err_msg
= _("broadcast not on source memory operand");
5010 case broadcast_needed
:
5011 err_msg
= _("broadcast is needed for operand of such type");
5013 case unsupported_masking
:
5014 err_msg
= _("unsupported masking");
5016 case mask_not_on_destination
:
5017 err_msg
= _("mask not on destination operand");
5019 case no_default_mask
:
5020 err_msg
= _("default mask isn't allowed");
5022 case unsupported_rc_sae
:
5023 err_msg
= _("unsupported static rounding/sae");
5025 case rc_sae_operand_not_last_imm
:
5027 err_msg
= _("RC/SAE operand must precede immediate operands");
5029 err_msg
= _("RC/SAE operand must follow immediate operands");
5031 case invalid_register_operand
:
5032 err_msg
= _("invalid register operand");
5035 as_bad (_("%s for `%s'"), err_msg
,
5036 current_templates
->start
->name
);
5040 if (!quiet_warnings
)
5043 && (i
.types
[0].bitfield
.jumpabsolute
5044 != operand_types
[0].bitfield
.jumpabsolute
))
5046 as_warn (_("indirect %s without `*'"), t
->name
);
5049 if (t
->opcode_modifier
.isprefix
5050 && t
->opcode_modifier
.ignoresize
)
5052 /* Warn them that a data or address size prefix doesn't
5053 affect assembly of the next line of code. */
5054 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5058 /* Copy the template we found. */
5061 if (addr_prefix_disp
!= -1)
5062 i
.tm
.operand_types
[addr_prefix_disp
]
5063 = operand_types
[addr_prefix_disp
];
5065 if (found_reverse_match
)
5067 /* If we found a reverse match we must alter the opcode
5068 direction bit. found_reverse_match holds bits to change
5069 (different for int & float insns). */
5071 i
.tm
.base_opcode
^= found_reverse_match
;
5073 i
.tm
.operand_types
[0] = operand_types
[1];
5074 i
.tm
.operand_types
[1] = operand_types
[0];
5083 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5084 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5086 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5088 as_bad (_("`%s' operand %d must use `%ses' segment"),
5094 /* There's only ever one segment override allowed per instruction.
5095 This instruction possibly has a legal segment override on the
5096 second operand, so copy the segment to where non-string
5097 instructions store it, allowing common code. */
5098 i
.seg
[0] = i
.seg
[1];
5100 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5102 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5104 as_bad (_("`%s' operand %d must use `%ses' segment"),
5115 process_suffix (void)
5117 /* If matched instruction specifies an explicit instruction mnemonic
5119 if (i
.tm
.opcode_modifier
.size16
)
5120 i
.suffix
= WORD_MNEM_SUFFIX
;
5121 else if (i
.tm
.opcode_modifier
.size32
)
5122 i
.suffix
= LONG_MNEM_SUFFIX
;
5123 else if (i
.tm
.opcode_modifier
.size64
)
5124 i
.suffix
= QWORD_MNEM_SUFFIX
;
5125 else if (i
.reg_operands
)
5127 /* If there's no instruction mnemonic suffix we try to invent one
5128 based on register operands. */
5131 /* We take i.suffix from the last register operand specified,
5132 Destination register type is more significant than source
5133 register type. crc32 in SSE4.2 prefers source register
5135 if (i
.tm
.base_opcode
== 0xf20f38f1)
5137 if (i
.types
[0].bitfield
.reg16
)
5138 i
.suffix
= WORD_MNEM_SUFFIX
;
5139 else if (i
.types
[0].bitfield
.reg32
)
5140 i
.suffix
= LONG_MNEM_SUFFIX
;
5141 else if (i
.types
[0].bitfield
.reg64
)
5142 i
.suffix
= QWORD_MNEM_SUFFIX
;
5144 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5146 if (i
.types
[0].bitfield
.reg8
)
5147 i
.suffix
= BYTE_MNEM_SUFFIX
;
5154 if (i
.tm
.base_opcode
== 0xf20f38f1
5155 || i
.tm
.base_opcode
== 0xf20f38f0)
5157 /* We have to know the operand size for crc32. */
5158 as_bad (_("ambiguous memory operand size for `%s`"),
5163 for (op
= i
.operands
; --op
>= 0;)
5164 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5166 if (i
.types
[op
].bitfield
.reg8
)
5168 i
.suffix
= BYTE_MNEM_SUFFIX
;
5171 else if (i
.types
[op
].bitfield
.reg16
)
5173 i
.suffix
= WORD_MNEM_SUFFIX
;
5176 else if (i
.types
[op
].bitfield
.reg32
)
5178 i
.suffix
= LONG_MNEM_SUFFIX
;
5181 else if (i
.types
[op
].bitfield
.reg64
)
5183 i
.suffix
= QWORD_MNEM_SUFFIX
;
5189 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5192 && i
.tm
.opcode_modifier
.ignoresize
5193 && i
.tm
.opcode_modifier
.no_bsuf
)
5195 else if (!check_byte_reg ())
5198 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5201 && i
.tm
.opcode_modifier
.ignoresize
5202 && i
.tm
.opcode_modifier
.no_lsuf
)
5204 else if (!check_long_reg ())
5207 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5210 && i
.tm
.opcode_modifier
.ignoresize
5211 && i
.tm
.opcode_modifier
.no_qsuf
)
5213 else if (!check_qword_reg ())
5216 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5219 && i
.tm
.opcode_modifier
.ignoresize
5220 && i
.tm
.opcode_modifier
.no_wsuf
)
5222 else if (!check_word_reg ())
5225 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5226 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5227 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5229 /* Skip if the instruction has x/y/z suffix. match_template
5230 should check if it is a valid suffix. */
5232 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5233 /* Do nothing if the instruction is going to ignore the prefix. */
5238 else if (i
.tm
.opcode_modifier
.defaultsize
5240 /* exclude fldenv/frstor/fsave/fstenv */
5241 && i
.tm
.opcode_modifier
.no_ssuf
)
5243 i
.suffix
= stackop_size
;
5245 else if (intel_syntax
5247 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5248 || i
.tm
.opcode_modifier
.jumpbyte
5249 || i
.tm
.opcode_modifier
.jumpintersegment
5250 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5251 && i
.tm
.extension_opcode
<= 3)))
5256 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5258 i
.suffix
= QWORD_MNEM_SUFFIX
;
5262 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5263 i
.suffix
= LONG_MNEM_SUFFIX
;
5266 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5267 i
.suffix
= WORD_MNEM_SUFFIX
;
5276 if (i
.tm
.opcode_modifier
.w
)
5278 as_bad (_("no instruction mnemonic suffix given and "
5279 "no register operands; can't size instruction"));
5285 unsigned int suffixes
;
5287 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5288 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5290 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5292 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5294 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5296 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5299 /* There are more than suffix matches. */
5300 if (i
.tm
.opcode_modifier
.w
5301 || ((suffixes
& (suffixes
- 1))
5302 && !i
.tm
.opcode_modifier
.defaultsize
5303 && !i
.tm
.opcode_modifier
.ignoresize
))
5305 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5311 /* Change the opcode based on the operand size given by i.suffix;
5312 We don't need to change things for byte insns. */
5315 && i
.suffix
!= BYTE_MNEM_SUFFIX
5316 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5317 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5318 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5320 /* It's not a byte, select word/dword operation. */
5321 if (i
.tm
.opcode_modifier
.w
)
5323 if (i
.tm
.opcode_modifier
.shortform
)
5324 i
.tm
.base_opcode
|= 8;
5326 i
.tm
.base_opcode
|= 1;
5329 /* Now select between word & dword operations via the operand
5330 size prefix, except for instructions that will ignore this
5332 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5334 /* The address size override prefix changes the size of the
5336 if ((flag_code
== CODE_32BIT
5337 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5338 || (flag_code
!= CODE_32BIT
5339 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5340 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5343 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5344 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5345 && !i
.tm
.opcode_modifier
.ignoresize
5346 && !i
.tm
.opcode_modifier
.floatmf
5347 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5348 || (flag_code
== CODE_64BIT
5349 && i
.tm
.opcode_modifier
.jumpbyte
)))
5351 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5353 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5354 prefix
= ADDR_PREFIX_OPCODE
;
5356 if (!add_prefix (prefix
))
5360 /* Set mode64 for an operand. */
5361 if (i
.suffix
== QWORD_MNEM_SUFFIX
5362 && flag_code
== CODE_64BIT
5363 && !i
.tm
.opcode_modifier
.norex64
)
5365 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5366 need rex64. cmpxchg8b is also a special case. */
5367 if (! (i
.operands
== 2
5368 && i
.tm
.base_opcode
== 0x90
5369 && i
.tm
.extension_opcode
== None
5370 && operand_type_equal (&i
.types
[0], &acc64
)
5371 && operand_type_equal (&i
.types
[1], &acc64
))
5372 && ! (i
.operands
== 1
5373 && i
.tm
.base_opcode
== 0xfc7
5374 && i
.tm
.extension_opcode
== 1
5375 && !operand_type_check (i
.types
[0], reg
)
5376 && operand_type_check (i
.types
[0], anymem
)))
5380 /* Size floating point instruction. */
5381 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5382 if (i
.tm
.opcode_modifier
.floatmf
)
5383 i
.tm
.base_opcode
^= 4;
5390 check_byte_reg (void)
5394 for (op
= i
.operands
; --op
>= 0;)
5396 /* If this is an eight bit register, it's OK. If it's the 16 or
5397 32 bit version of an eight bit register, we will just use the
5398 low portion, and that's OK too. */
5399 if (i
.types
[op
].bitfield
.reg8
)
5402 /* I/O port address operands are OK too. */
5403 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5406 /* crc32 doesn't generate this warning. */
5407 if (i
.tm
.base_opcode
== 0xf20f38f0)
5410 if ((i
.types
[op
].bitfield
.reg16
5411 || i
.types
[op
].bitfield
.reg32
5412 || i
.types
[op
].bitfield
.reg64
)
5413 && i
.op
[op
].regs
->reg_num
< 4
5414 /* Prohibit these changes in 64bit mode, since the lowering
5415 would be more complicated. */
5416 && flag_code
!= CODE_64BIT
)
5418 #if REGISTER_WARNINGS
5419 if (!quiet_warnings
)
5420 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5422 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5423 ? REGNAM_AL
- REGNAM_AX
5424 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5426 i
.op
[op
].regs
->reg_name
,
5431 /* Any other register is bad. */
5432 if (i
.types
[op
].bitfield
.reg16
5433 || i
.types
[op
].bitfield
.reg32
5434 || i
.types
[op
].bitfield
.reg64
5435 || i
.types
[op
].bitfield
.regmmx
5436 || i
.types
[op
].bitfield
.regxmm
5437 || i
.types
[op
].bitfield
.regymm
5438 || i
.types
[op
].bitfield
.regzmm
5439 || i
.types
[op
].bitfield
.sreg2
5440 || i
.types
[op
].bitfield
.sreg3
5441 || i
.types
[op
].bitfield
.control
5442 || i
.types
[op
].bitfield
.debug
5443 || i
.types
[op
].bitfield
.test
5444 || i
.types
[op
].bitfield
.floatreg
5445 || i
.types
[op
].bitfield
.floatacc
)
5447 as_bad (_("`%s%s' not allowed with `%s%c'"),
5449 i
.op
[op
].regs
->reg_name
,
5459 check_long_reg (void)
5463 for (op
= i
.operands
; --op
>= 0;)
5464 /* Reject eight bit registers, except where the template requires
5465 them. (eg. movzb) */
5466 if (i
.types
[op
].bitfield
.reg8
5467 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5468 || i
.tm
.operand_types
[op
].bitfield
.reg32
5469 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5471 as_bad (_("`%s%s' not allowed with `%s%c'"),
5473 i
.op
[op
].regs
->reg_name
,
5478 /* Warn if the e prefix on a general reg is missing. */
5479 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5480 && i
.types
[op
].bitfield
.reg16
5481 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5482 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5484 /* Prohibit these changes in the 64bit mode, since the
5485 lowering is more complicated. */
5486 if (flag_code
== CODE_64BIT
)
5488 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5489 register_prefix
, i
.op
[op
].regs
->reg_name
,
5493 #if REGISTER_WARNINGS
5494 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5496 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5497 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5500 /* Warn if the r prefix on a general reg is present. */
5501 else if (i
.types
[op
].bitfield
.reg64
5502 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5503 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5506 && i
.tm
.opcode_modifier
.toqword
5507 && !i
.types
[0].bitfield
.regxmm
)
5509 /* Convert to QWORD. We want REX byte. */
5510 i
.suffix
= QWORD_MNEM_SUFFIX
;
5514 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5515 register_prefix
, i
.op
[op
].regs
->reg_name
,
5524 check_qword_reg (void)
5528 for (op
= i
.operands
; --op
>= 0; )
5529 /* Reject eight bit registers, except where the template requires
5530 them. (eg. movzb) */
5531 if (i
.types
[op
].bitfield
.reg8
5532 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5533 || i
.tm
.operand_types
[op
].bitfield
.reg32
5534 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5536 as_bad (_("`%s%s' not allowed with `%s%c'"),
5538 i
.op
[op
].regs
->reg_name
,
5543 /* Warn if the r prefix on a general reg is missing. */
5544 else if ((i
.types
[op
].bitfield
.reg16
5545 || i
.types
[op
].bitfield
.reg32
)
5546 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5547 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5549 /* Prohibit these changes in the 64bit mode, since the
5550 lowering is more complicated. */
5552 && i
.tm
.opcode_modifier
.todword
5553 && !i
.types
[0].bitfield
.regxmm
)
5555 /* Convert to DWORD. We don't want REX byte. */
5556 i
.suffix
= LONG_MNEM_SUFFIX
;
5560 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5561 register_prefix
, i
.op
[op
].regs
->reg_name
,
5570 check_word_reg (void)
5573 for (op
= i
.operands
; --op
>= 0;)
5574 /* Reject eight bit registers, except where the template requires
5575 them. (eg. movzb) */
5576 if (i
.types
[op
].bitfield
.reg8
5577 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5578 || i
.tm
.operand_types
[op
].bitfield
.reg32
5579 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5581 as_bad (_("`%s%s' not allowed with `%s%c'"),
5583 i
.op
[op
].regs
->reg_name
,
5588 /* Warn if the e or r prefix on a general reg is present. */
5589 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5590 && (i
.types
[op
].bitfield
.reg32
5591 || i
.types
[op
].bitfield
.reg64
)
5592 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5593 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5595 /* Prohibit these changes in the 64bit mode, since the
5596 lowering is more complicated. */
5597 if (flag_code
== CODE_64BIT
)
5599 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5600 register_prefix
, i
.op
[op
].regs
->reg_name
,
5604 #if REGISTER_WARNINGS
5605 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5607 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5608 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5615 update_imm (unsigned int j
)
5617 i386_operand_type overlap
= i
.types
[j
];
5618 if ((overlap
.bitfield
.imm8
5619 || overlap
.bitfield
.imm8s
5620 || overlap
.bitfield
.imm16
5621 || overlap
.bitfield
.imm32
5622 || overlap
.bitfield
.imm32s
5623 || overlap
.bitfield
.imm64
)
5624 && !operand_type_equal (&overlap
, &imm8
)
5625 && !operand_type_equal (&overlap
, &imm8s
)
5626 && !operand_type_equal (&overlap
, &imm16
)
5627 && !operand_type_equal (&overlap
, &imm32
)
5628 && !operand_type_equal (&overlap
, &imm32s
)
5629 && !operand_type_equal (&overlap
, &imm64
))
5633 i386_operand_type temp
;
5635 operand_type_set (&temp
, 0);
5636 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5638 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5639 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5641 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5642 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5643 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5645 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5646 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5649 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5652 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5653 || operand_type_equal (&overlap
, &imm16_32
)
5654 || operand_type_equal (&overlap
, &imm16_32s
))
5656 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5661 if (!operand_type_equal (&overlap
, &imm8
)
5662 && !operand_type_equal (&overlap
, &imm8s
)
5663 && !operand_type_equal (&overlap
, &imm16
)
5664 && !operand_type_equal (&overlap
, &imm32
)
5665 && !operand_type_equal (&overlap
, &imm32s
)
5666 && !operand_type_equal (&overlap
, &imm64
))
5668 as_bad (_("no instruction mnemonic suffix given; "
5669 "can't determine immediate size"));
5673 i
.types
[j
] = overlap
;
5683 /* Update the first 2 immediate operands. */
5684 n
= i
.operands
> 2 ? 2 : i
.operands
;
5687 for (j
= 0; j
< n
; j
++)
5688 if (update_imm (j
) == 0)
5691 /* The 3rd operand can't be immediate operand. */
5692 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5699 bad_implicit_operand (int xmm
)
5701 const char *ireg
= xmm
? "xmm0" : "ymm0";
5704 as_bad (_("the last operand of `%s' must be `%s%s'"),
5705 i
.tm
.name
, register_prefix
, ireg
);
5707 as_bad (_("the first operand of `%s' must be `%s%s'"),
5708 i
.tm
.name
, register_prefix
, ireg
);
5713 process_operands (void)
5715 /* Default segment register this instruction will use for memory
5716 accesses. 0 means unknown. This is only for optimizing out
5717 unnecessary segment overrides. */
5718 const seg_entry
*default_seg
= 0;
5720 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5722 unsigned int dupl
= i
.operands
;
5723 unsigned int dest
= dupl
- 1;
5726 /* The destination must be an xmm register. */
5727 gas_assert (i
.reg_operands
5728 && MAX_OPERANDS
> dupl
5729 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5731 if (i
.tm
.opcode_modifier
.firstxmm0
)
5733 /* The first operand is implicit and must be xmm0. */
5734 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5735 if (register_number (i
.op
[0].regs
) != 0)
5736 return bad_implicit_operand (1);
5738 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5740 /* Keep xmm0 for instructions with VEX prefix and 3
5746 /* We remove the first xmm0 and keep the number of
5747 operands unchanged, which in fact duplicates the
5749 for (j
= 1; j
< i
.operands
; j
++)
5751 i
.op
[j
- 1] = i
.op
[j
];
5752 i
.types
[j
- 1] = i
.types
[j
];
5753 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5757 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5759 gas_assert ((MAX_OPERANDS
- 1) > dupl
5760 && (i
.tm
.opcode_modifier
.vexsources
5763 /* Add the implicit xmm0 for instructions with VEX prefix
5765 for (j
= i
.operands
; j
> 0; j
--)
5767 i
.op
[j
] = i
.op
[j
- 1];
5768 i
.types
[j
] = i
.types
[j
- 1];
5769 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5772 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5773 i
.types
[0] = regxmm
;
5774 i
.tm
.operand_types
[0] = regxmm
;
5777 i
.reg_operands
+= 2;
5782 i
.op
[dupl
] = i
.op
[dest
];
5783 i
.types
[dupl
] = i
.types
[dest
];
5784 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5793 i
.op
[dupl
] = i
.op
[dest
];
5794 i
.types
[dupl
] = i
.types
[dest
];
5795 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5798 if (i
.tm
.opcode_modifier
.immext
)
5801 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5805 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5806 gas_assert (i
.reg_operands
5807 && (operand_type_equal (&i
.types
[0], ®xmm
)
5808 || operand_type_equal (&i
.types
[0], ®ymm
)
5809 || operand_type_equal (&i
.types
[0], ®zmm
)));
5810 if (register_number (i
.op
[0].regs
) != 0)
5811 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5813 for (j
= 1; j
< i
.operands
; j
++)
5815 i
.op
[j
- 1] = i
.op
[j
];
5816 i
.types
[j
- 1] = i
.types
[j
];
5818 /* We need to adjust fields in i.tm since they are used by
5819 build_modrm_byte. */
5820 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5827 else if (i
.tm
.opcode_modifier
.regkludge
)
5829 /* The imul $imm, %reg instruction is converted into
5830 imul $imm, %reg, %reg, and the clr %reg instruction
5831 is converted into xor %reg, %reg. */
5833 unsigned int first_reg_op
;
5835 if (operand_type_check (i
.types
[0], reg
))
5839 /* Pretend we saw the extra register operand. */
5840 gas_assert (i
.reg_operands
== 1
5841 && i
.op
[first_reg_op
+ 1].regs
== 0);
5842 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5843 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5848 if (i
.tm
.opcode_modifier
.shortform
)
5850 if (i
.types
[0].bitfield
.sreg2
5851 || i
.types
[0].bitfield
.sreg3
)
5853 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5854 && i
.op
[0].regs
->reg_num
== 1)
5856 as_bad (_("you can't `pop %scs'"), register_prefix
);
5859 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5860 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5865 /* The register or float register operand is in operand
5869 if (i
.types
[0].bitfield
.floatreg
5870 || operand_type_check (i
.types
[0], reg
))
5874 /* Register goes in low 3 bits of opcode. */
5875 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5876 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5878 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5880 /* Warn about some common errors, but press on regardless.
5881 The first case can be generated by gcc (<= 2.8.1). */
5882 if (i
.operands
== 2)
5884 /* Reversed arguments on faddp, fsubp, etc. */
5885 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5886 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5887 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5891 /* Extraneous `l' suffix on fp insn. */
5892 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5893 register_prefix
, i
.op
[0].regs
->reg_name
);
5898 else if (i
.tm
.opcode_modifier
.modrm
)
5900 /* The opcode is completed (modulo i.tm.extension_opcode which
5901 must be put into the modrm byte). Now, we make the modrm and
5902 index base bytes based on all the info we've collected. */
5904 default_seg
= build_modrm_byte ();
5906 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5910 else if (i
.tm
.opcode_modifier
.isstring
)
5912 /* For the string instructions that allow a segment override
5913 on one of their operands, the default segment is ds. */
5917 if (i
.tm
.base_opcode
== 0x8d /* lea */
5920 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5922 /* If a segment was explicitly specified, and the specified segment
5923 is not the default, use an opcode prefix to select it. If we
5924 never figured out what the default segment is, then default_seg
5925 will be zero at this point, and the specified segment prefix will
5927 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5929 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5935 static const seg_entry
*
5936 build_modrm_byte (void)
5938 const seg_entry
*default_seg
= 0;
5939 unsigned int source
, dest
;
5942 /* The first operand of instructions with VEX prefix and 3 sources
5943 must be VEX_Imm4. */
5944 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5947 unsigned int nds
, reg_slot
;
5950 if (i
.tm
.opcode_modifier
.veximmext
5951 && i
.tm
.opcode_modifier
.immext
)
5953 dest
= i
.operands
- 2;
5954 gas_assert (dest
== 3);
5957 dest
= i
.operands
- 1;
5960 /* There are 2 kinds of instructions:
5961 1. 5 operands: 4 register operands or 3 register operands
5962 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5963 VexW0 or VexW1. The destination must be either XMM, YMM or
5965 2. 4 operands: 4 register operands or 3 register operands
5966 plus 1 memory operand, VexXDS, and VexImmExt */
5967 gas_assert ((i
.reg_operands
== 4
5968 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5969 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5970 && (i
.tm
.opcode_modifier
.veximmext
5971 || (i
.imm_operands
== 1
5972 && i
.types
[0].bitfield
.vec_imm4
5973 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5974 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5975 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5976 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5977 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5979 if (i
.imm_operands
== 0)
5981 /* When there is no immediate operand, generate an 8bit
5982 immediate operand to encode the first operand. */
5983 exp
= &im_expressions
[i
.imm_operands
++];
5984 i
.op
[i
.operands
].imms
= exp
;
5985 i
.types
[i
.operands
] = imm8
;
5987 /* If VexW1 is set, the first operand is the source and
5988 the second operand is encoded in the immediate operand. */
5989 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6000 /* FMA swaps REG and NDS. */
6001 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6009 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6011 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6013 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6015 exp
->X_op
= O_constant
;
6016 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6017 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6021 unsigned int imm_slot
;
6023 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6025 /* If VexW0 is set, the third operand is the source and
6026 the second operand is encoded in the immediate
6033 /* VexW1 is set, the second operand is the source and
6034 the third operand is encoded in the immediate
6040 if (i
.tm
.opcode_modifier
.immext
)
6042 /* When ImmExt is set, the immdiate byte is the last
6044 imm_slot
= i
.operands
- 1;
6052 /* Turn on Imm8 so that output_imm will generate it. */
6053 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6056 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6058 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6060 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6062 i
.op
[imm_slot
].imms
->X_add_number
6063 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6064 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6067 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6068 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6070 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6072 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6077 /* i.reg_operands MUST be the number of real register operands;
6078 implicit registers do not count. If there are 3 register
6079 operands, it must be a instruction with VexNDS. For a
6080 instruction with VexNDD, the destination register is encoded
6081 in VEX prefix. If there are 4 register operands, it must be
6082 a instruction with VEX prefix and 3 sources. */
6083 if (i
.mem_operands
== 0
6084 && ((i
.reg_operands
== 2
6085 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6086 || (i
.reg_operands
== 3
6087 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6088 || (i
.reg_operands
== 4 && vex_3_sources
)))
6096 /* When there are 3 operands, one of them may be immediate,
6097 which may be the first or the last operand. Otherwise,
6098 the first operand must be shift count register (cl) or it
6099 is an instruction with VexNDS. */
6100 gas_assert (i
.imm_operands
== 1
6101 || (i
.imm_operands
== 0
6102 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6103 || i
.types
[0].bitfield
.shiftcount
)));
6104 if (operand_type_check (i
.types
[0], imm
)
6105 || i
.types
[0].bitfield
.shiftcount
)
6111 /* When there are 4 operands, the first two must be 8bit
6112 immediate operands. The source operand will be the 3rd
6115 For instructions with VexNDS, if the first operand
6116 an imm8, the source operand is the 2nd one. If the last
6117 operand is imm8, the source operand is the first one. */
6118 gas_assert ((i
.imm_operands
== 2
6119 && i
.types
[0].bitfield
.imm8
6120 && i
.types
[1].bitfield
.imm8
)
6121 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6122 && i
.imm_operands
== 1
6123 && (i
.types
[0].bitfield
.imm8
6124 || i
.types
[i
.operands
- 1].bitfield
.imm8
6126 if (i
.imm_operands
== 2)
6130 if (i
.types
[0].bitfield
.imm8
)
6137 if (i
.tm
.opcode_modifier
.evex
)
6139 /* For EVEX instructions, when there are 5 operands, the
6140 first one must be immediate operand. If the second one
6141 is immediate operand, the source operand is the 3th
6142 one. If the last one is immediate operand, the source
6143 operand is the 2nd one. */
6144 gas_assert (i
.imm_operands
== 2
6145 && i
.tm
.opcode_modifier
.sae
6146 && operand_type_check (i
.types
[0], imm
));
6147 if (operand_type_check (i
.types
[1], imm
))
6149 else if (operand_type_check (i
.types
[4], imm
))
6163 /* RC/SAE operand could be between DEST and SRC. That happens
6164 when one operand is GPR and the other one is XMM/YMM/ZMM
6166 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6169 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6171 /* For instructions with VexNDS, the register-only source
6172 operand must be 32/64bit integer, XMM, YMM or ZMM
6173 register. It is encoded in VEX prefix. We need to
6174 clear RegMem bit before calling operand_type_equal. */
6176 i386_operand_type op
;
6179 /* Check register-only source operand when two source
6180 operands are swapped. */
6181 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6182 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6190 op
= i
.tm
.operand_types
[vvvv
];
6191 op
.bitfield
.regmem
= 0;
6192 if ((dest
+ 1) >= i
.operands
6193 || (!op
.bitfield
.reg32
6194 && op
.bitfield
.reg64
6195 && !operand_type_equal (&op
, ®xmm
)
6196 && !operand_type_equal (&op
, ®ymm
)
6197 && !operand_type_equal (&op
, ®zmm
)
6198 && !operand_type_equal (&op
, ®mask
)))
6200 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6206 /* One of the register operands will be encoded in the i.tm.reg
6207 field, the other in the combined i.tm.mode and i.tm.regmem
6208 fields. If no form of this instruction supports a memory
6209 destination operand, then we assume the source operand may
6210 sometimes be a memory operand and so we need to store the
6211 destination in the i.rm.reg field. */
6212 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6213 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6215 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6216 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6217 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6219 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6221 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6223 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6228 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6229 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6230 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6232 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6234 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6236 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6239 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6241 if (!i
.types
[0].bitfield
.control
6242 && !i
.types
[1].bitfield
.control
)
6244 i
.rex
&= ~(REX_R
| REX_B
);
6245 add_prefix (LOCK_PREFIX_OPCODE
);
6249 { /* If it's not 2 reg operands... */
6254 unsigned int fake_zero_displacement
= 0;
6257 for (op
= 0; op
< i
.operands
; op
++)
6258 if (operand_type_check (i
.types
[op
], anymem
))
6260 gas_assert (op
< i
.operands
);
6262 if (i
.tm
.opcode_modifier
.vecsib
)
6264 if (i
.index_reg
->reg_num
== RegEiz
6265 || i
.index_reg
->reg_num
== RegRiz
)
6268 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6271 i
.sib
.base
= NO_BASE_REGISTER
;
6272 i
.sib
.scale
= i
.log2_scale_factor
;
6273 /* No Vec_Disp8 if there is no base. */
6274 i
.types
[op
].bitfield
.vec_disp8
= 0;
6275 i
.types
[op
].bitfield
.disp8
= 0;
6276 i
.types
[op
].bitfield
.disp16
= 0;
6277 i
.types
[op
].bitfield
.disp64
= 0;
6278 if (flag_code
!= CODE_64BIT
)
6280 /* Must be 32 bit */
6281 i
.types
[op
].bitfield
.disp32
= 1;
6282 i
.types
[op
].bitfield
.disp32s
= 0;
6286 i
.types
[op
].bitfield
.disp32
= 0;
6287 i
.types
[op
].bitfield
.disp32s
= 1;
6290 i
.sib
.index
= i
.index_reg
->reg_num
;
6291 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6293 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6299 if (i
.base_reg
== 0)
6302 if (!i
.disp_operands
)
6304 fake_zero_displacement
= 1;
6305 /* Instructions with VSIB byte need 32bit displacement
6306 if there is no base register. */
6307 if (i
.tm
.opcode_modifier
.vecsib
)
6308 i
.types
[op
].bitfield
.disp32
= 1;
6310 if (i
.index_reg
== 0)
6312 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6313 /* Operand is just <disp> */
6314 if (flag_code
== CODE_64BIT
)
6316 /* 64bit mode overwrites the 32bit absolute
6317 addressing by RIP relative addressing and
6318 absolute addressing is encoded by one of the
6319 redundant SIB forms. */
6320 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6321 i
.sib
.base
= NO_BASE_REGISTER
;
6322 i
.sib
.index
= NO_INDEX_REGISTER
;
6323 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6324 ? disp32s
: disp32
);
6326 else if ((flag_code
== CODE_16BIT
)
6327 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6329 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6330 i
.types
[op
] = disp16
;
6334 i
.rm
.regmem
= NO_BASE_REGISTER
;
6335 i
.types
[op
] = disp32
;
6338 else if (!i
.tm
.opcode_modifier
.vecsib
)
6340 /* !i.base_reg && i.index_reg */
6341 if (i
.index_reg
->reg_num
== RegEiz
6342 || i
.index_reg
->reg_num
== RegRiz
)
6343 i
.sib
.index
= NO_INDEX_REGISTER
;
6345 i
.sib
.index
= i
.index_reg
->reg_num
;
6346 i
.sib
.base
= NO_BASE_REGISTER
;
6347 i
.sib
.scale
= i
.log2_scale_factor
;
6348 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6349 /* No Vec_Disp8 if there is no base. */
6350 i
.types
[op
].bitfield
.vec_disp8
= 0;
6351 i
.types
[op
].bitfield
.disp8
= 0;
6352 i
.types
[op
].bitfield
.disp16
= 0;
6353 i
.types
[op
].bitfield
.disp64
= 0;
6354 if (flag_code
!= CODE_64BIT
)
6356 /* Must be 32 bit */
6357 i
.types
[op
].bitfield
.disp32
= 1;
6358 i
.types
[op
].bitfield
.disp32s
= 0;
6362 i
.types
[op
].bitfield
.disp32
= 0;
6363 i
.types
[op
].bitfield
.disp32s
= 1;
6365 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6369 /* RIP addressing for 64bit mode. */
6370 else if (i
.base_reg
->reg_num
== RegRip
||
6371 i
.base_reg
->reg_num
== RegEip
)
6373 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6374 i
.rm
.regmem
= NO_BASE_REGISTER
;
6375 i
.types
[op
].bitfield
.disp8
= 0;
6376 i
.types
[op
].bitfield
.disp16
= 0;
6377 i
.types
[op
].bitfield
.disp32
= 0;
6378 i
.types
[op
].bitfield
.disp32s
= 1;
6379 i
.types
[op
].bitfield
.disp64
= 0;
6380 i
.types
[op
].bitfield
.vec_disp8
= 0;
6381 i
.flags
[op
] |= Operand_PCrel
;
6382 if (! i
.disp_operands
)
6383 fake_zero_displacement
= 1;
6385 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6387 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6388 switch (i
.base_reg
->reg_num
)
6391 if (i
.index_reg
== 0)
6393 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6394 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6398 if (i
.index_reg
== 0)
6401 if (operand_type_check (i
.types
[op
], disp
) == 0)
6403 /* fake (%bp) into 0(%bp) */
6404 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6405 i
.types
[op
].bitfield
.vec_disp8
= 1;
6407 i
.types
[op
].bitfield
.disp8
= 1;
6408 fake_zero_displacement
= 1;
6411 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6412 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6414 default: /* (%si) -> 4 or (%di) -> 5 */
6415 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6417 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6419 else /* i.base_reg and 32/64 bit mode */
6421 if (flag_code
== CODE_64BIT
6422 && operand_type_check (i
.types
[op
], disp
))
6424 i386_operand_type temp
;
6425 operand_type_set (&temp
, 0);
6426 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6427 temp
.bitfield
.vec_disp8
6428 = i
.types
[op
].bitfield
.vec_disp8
;
6430 if (i
.prefix
[ADDR_PREFIX
] == 0)
6431 i
.types
[op
].bitfield
.disp32s
= 1;
6433 i
.types
[op
].bitfield
.disp32
= 1;
6436 if (!i
.tm
.opcode_modifier
.vecsib
)
6437 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6438 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6440 i
.sib
.base
= i
.base_reg
->reg_num
;
6441 /* x86-64 ignores REX prefix bit here to avoid decoder
6443 if (!(i
.base_reg
->reg_flags
& RegRex
)
6444 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6445 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6447 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6449 fake_zero_displacement
= 1;
6450 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6451 i
.types
[op
].bitfield
.vec_disp8
= 1;
6453 i
.types
[op
].bitfield
.disp8
= 1;
6455 i
.sib
.scale
= i
.log2_scale_factor
;
6456 if (i
.index_reg
== 0)
6458 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6459 /* <disp>(%esp) becomes two byte modrm with no index
6460 register. We've already stored the code for esp
6461 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6462 Any base register besides %esp will not use the
6463 extra modrm byte. */
6464 i
.sib
.index
= NO_INDEX_REGISTER
;
6466 else if (!i
.tm
.opcode_modifier
.vecsib
)
6468 if (i
.index_reg
->reg_num
== RegEiz
6469 || i
.index_reg
->reg_num
== RegRiz
)
6470 i
.sib
.index
= NO_INDEX_REGISTER
;
6472 i
.sib
.index
= i
.index_reg
->reg_num
;
6473 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6474 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6479 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6480 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6484 if (!fake_zero_displacement
6488 fake_zero_displacement
= 1;
6489 if (i
.disp_encoding
== disp_encoding_8bit
)
6490 i
.types
[op
].bitfield
.disp8
= 1;
6492 i
.types
[op
].bitfield
.disp32
= 1;
6494 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6498 if (fake_zero_displacement
)
6500 /* Fakes a zero displacement assuming that i.types[op]
6501 holds the correct displacement size. */
6504 gas_assert (i
.op
[op
].disps
== 0);
6505 exp
= &disp_expressions
[i
.disp_operands
++];
6506 i
.op
[op
].disps
= exp
;
6507 exp
->X_op
= O_constant
;
6508 exp
->X_add_number
= 0;
6509 exp
->X_add_symbol
= (symbolS
*) 0;
6510 exp
->X_op_symbol
= (symbolS
*) 0;
6518 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6520 if (operand_type_check (i
.types
[0], imm
))
6521 i
.vex
.register_specifier
= NULL
;
6524 /* VEX.vvvv encodes one of the sources when the first
6525 operand is not an immediate. */
6526 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6527 i
.vex
.register_specifier
= i
.op
[0].regs
;
6529 i
.vex
.register_specifier
= i
.op
[1].regs
;
6532 /* Destination is a XMM register encoded in the ModRM.reg
6534 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6535 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6538 /* ModRM.rm and VEX.B encodes the other source. */
6539 if (!i
.mem_operands
)
6543 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6544 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6546 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6548 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6552 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6554 i
.vex
.register_specifier
= i
.op
[2].regs
;
6555 if (!i
.mem_operands
)
6558 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6559 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6563 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6564 (if any) based on i.tm.extension_opcode. Again, we must be
6565 careful to make sure that segment/control/debug/test/MMX
6566 registers are coded into the i.rm.reg field. */
6567 else if (i
.reg_operands
)
6570 unsigned int vex_reg
= ~0;
6572 for (op
= 0; op
< i
.operands
; op
++)
6573 if (i
.types
[op
].bitfield
.reg8
6574 || i
.types
[op
].bitfield
.reg16
6575 || i
.types
[op
].bitfield
.reg32
6576 || i
.types
[op
].bitfield
.reg64
6577 || i
.types
[op
].bitfield
.regmmx
6578 || i
.types
[op
].bitfield
.regxmm
6579 || i
.types
[op
].bitfield
.regymm
6580 || i
.types
[op
].bitfield
.regbnd
6581 || i
.types
[op
].bitfield
.regzmm
6582 || i
.types
[op
].bitfield
.regmask
6583 || i
.types
[op
].bitfield
.sreg2
6584 || i
.types
[op
].bitfield
.sreg3
6585 || i
.types
[op
].bitfield
.control
6586 || i
.types
[op
].bitfield
.debug
6587 || i
.types
[op
].bitfield
.test
)
6592 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6594 /* For instructions with VexNDS, the register-only
6595 source operand is encoded in VEX prefix. */
6596 gas_assert (mem
!= (unsigned int) ~0);
6601 gas_assert (op
< i
.operands
);
6605 /* Check register-only source operand when two source
6606 operands are swapped. */
6607 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6608 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6612 gas_assert (mem
== (vex_reg
+ 1)
6613 && op
< i
.operands
);
6618 gas_assert (vex_reg
< i
.operands
);
6622 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6624 /* For instructions with VexNDD, the register destination
6625 is encoded in VEX prefix. */
6626 if (i
.mem_operands
== 0)
6628 /* There is no memory operand. */
6629 gas_assert ((op
+ 2) == i
.operands
);
6634 /* There are only 2 operands. */
6635 gas_assert (op
< 2 && i
.operands
== 2);
6640 gas_assert (op
< i
.operands
);
6642 if (vex_reg
!= (unsigned int) ~0)
6644 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6646 if (type
->bitfield
.reg32
!= 1
6647 && type
->bitfield
.reg64
!= 1
6648 && !operand_type_equal (type
, ®xmm
)
6649 && !operand_type_equal (type
, ®ymm
)
6650 && !operand_type_equal (type
, ®zmm
)
6651 && !operand_type_equal (type
, ®mask
))
6654 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6657 /* Don't set OP operand twice. */
6660 /* If there is an extension opcode to put here, the
6661 register number must be put into the regmem field. */
6662 if (i
.tm
.extension_opcode
!= None
)
6664 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6665 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6667 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6672 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6673 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6675 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6680 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6681 must set it to 3 to indicate this is a register operand
6682 in the regmem field. */
6683 if (!i
.mem_operands
)
6687 /* Fill in i.rm.reg field with extension opcode (if any). */
6688 if (i
.tm
.extension_opcode
!= None
)
6689 i
.rm
.reg
= i
.tm
.extension_opcode
;
6695 output_branch (void)
6701 relax_substateT subtype
;
6705 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6706 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6709 if (i
.prefix
[DATA_PREFIX
] != 0)
6715 /* Pentium4 branch hints. */
6716 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6717 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6722 if (i
.prefix
[REX_PREFIX
] != 0)
6728 /* BND prefixed jump. */
6729 if (i
.prefix
[BND_PREFIX
] != 0)
6731 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6735 if (i
.prefixes
!= 0 && !intel_syntax
)
6736 as_warn (_("skipping prefixes on this instruction"));
6738 /* It's always a symbol; End frag & setup for relax.
6739 Make sure there is enough room in this frag for the largest
6740 instruction we may generate in md_convert_frag. This is 2
6741 bytes for the opcode and room for the prefix and largest
6743 frag_grow (prefix
+ 2 + 4);
6744 /* Prefix and 1 opcode byte go in fr_fix. */
6745 p
= frag_more (prefix
+ 1);
6746 if (i
.prefix
[DATA_PREFIX
] != 0)
6747 *p
++ = DATA_PREFIX_OPCODE
;
6748 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6749 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6750 *p
++ = i
.prefix
[SEG_PREFIX
];
6751 if (i
.prefix
[REX_PREFIX
] != 0)
6752 *p
++ = i
.prefix
[REX_PREFIX
];
6753 *p
= i
.tm
.base_opcode
;
6755 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6756 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6757 else if (cpu_arch_flags
.bitfield
.cpui386
)
6758 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6760 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6763 sym
= i
.op
[0].disps
->X_add_symbol
;
6764 off
= i
.op
[0].disps
->X_add_number
;
6766 if (i
.op
[0].disps
->X_op
!= O_constant
6767 && i
.op
[0].disps
->X_op
!= O_symbol
)
6769 /* Handle complex expressions. */
6770 sym
= make_expr_symbol (i
.op
[0].disps
);
6774 /* 1 possible extra opcode + 4 byte displacement go in var part.
6775 Pass reloc in fr_var. */
6776 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6786 if (i
.tm
.opcode_modifier
.jumpbyte
)
6788 /* This is a loop or jecxz type instruction. */
6790 if (i
.prefix
[ADDR_PREFIX
] != 0)
6792 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6795 /* Pentium4 branch hints. */
6796 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6797 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6799 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6808 if (flag_code
== CODE_16BIT
)
6811 if (i
.prefix
[DATA_PREFIX
] != 0)
6813 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6823 if (i
.prefix
[REX_PREFIX
] != 0)
6825 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6829 /* BND prefixed jump. */
6830 if (i
.prefix
[BND_PREFIX
] != 0)
6832 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6836 if (i
.prefixes
!= 0 && !intel_syntax
)
6837 as_warn (_("skipping prefixes on this instruction"));
6839 p
= frag_more (i
.tm
.opcode_length
+ size
);
6840 switch (i
.tm
.opcode_length
)
6843 *p
++ = i
.tm
.base_opcode
>> 8;
6845 *p
++ = i
.tm
.base_opcode
;
6851 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6852 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6854 /* All jumps handled here are signed, but don't use a signed limit
6855 check for 32 and 16 bit jumps as we want to allow wrap around at
6856 4G and 64k respectively. */
6858 fixP
->fx_signed
= 1;
6862 output_interseg_jump (void)
6870 if (flag_code
== CODE_16BIT
)
6874 if (i
.prefix
[DATA_PREFIX
] != 0)
6880 if (i
.prefix
[REX_PREFIX
] != 0)
6890 if (i
.prefixes
!= 0 && !intel_syntax
)
6891 as_warn (_("skipping prefixes on this instruction"));
6893 /* 1 opcode; 2 segment; offset */
6894 p
= frag_more (prefix
+ 1 + 2 + size
);
6896 if (i
.prefix
[DATA_PREFIX
] != 0)
6897 *p
++ = DATA_PREFIX_OPCODE
;
6899 if (i
.prefix
[REX_PREFIX
] != 0)
6900 *p
++ = i
.prefix
[REX_PREFIX
];
6902 *p
++ = i
.tm
.base_opcode
;
6903 if (i
.op
[1].imms
->X_op
== O_constant
)
6905 offsetT n
= i
.op
[1].imms
->X_add_number
;
6908 && !fits_in_unsigned_word (n
)
6909 && !fits_in_signed_word (n
))
6911 as_bad (_("16-bit jump out of range"));
6914 md_number_to_chars (p
, n
, size
);
6917 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6918 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6919 if (i
.op
[0].imms
->X_op
!= O_constant
)
6920 as_bad (_("can't handle non absolute segment in `%s'"),
6922 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6928 fragS
*insn_start_frag
;
6929 offsetT insn_start_off
;
6931 /* Tie dwarf2 debug info to the address at the start of the insn.
6932 We can't do this after the insn has been output as the current
6933 frag may have been closed off. eg. by frag_var. */
6934 dwarf2_emit_insn (0);
6936 insn_start_frag
= frag_now
;
6937 insn_start_off
= frag_now_fix ();
6940 if (i
.tm
.opcode_modifier
.jump
)
6942 else if (i
.tm
.opcode_modifier
.jumpbyte
6943 || i
.tm
.opcode_modifier
.jumpdword
)
6945 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6946 output_interseg_jump ();
6949 /* Output normal instructions here. */
6953 unsigned int prefix
;
6955 /* Some processors fail on LOCK prefix. This options makes
6956 assembler ignore LOCK prefix and serves as a workaround. */
6957 if (omit_lock_prefix
)
6959 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6961 i
.prefix
[LOCK_PREFIX
] = 0;
6964 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6965 don't need the explicit prefix. */
6966 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6968 switch (i
.tm
.opcode_length
)
6971 if (i
.tm
.base_opcode
& 0xff000000)
6973 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6978 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6980 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6981 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6984 if (prefix
!= REPE_PREFIX_OPCODE
6985 || (i
.prefix
[REP_PREFIX
]
6986 != REPE_PREFIX_OPCODE
))
6987 add_prefix (prefix
);
6990 add_prefix (prefix
);
6999 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7000 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7001 R_X86_64_GOTTPOFF relocation so that linker can safely
7002 perform IE->LE optimization. */
7003 if (x86_elf_abi
== X86_64_X32_ABI
7005 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7006 && i
.prefix
[REX_PREFIX
] == 0)
7007 add_prefix (REX_OPCODE
);
7010 /* The prefix bytes. */
7011 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7013 FRAG_APPEND_1_CHAR (*q
);
7017 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7022 /* REX byte is encoded in VEX prefix. */
7026 FRAG_APPEND_1_CHAR (*q
);
7029 /* There should be no other prefixes for instructions
7034 /* For EVEX instructions i.vrex should become 0 after
7035 build_evex_prefix. For VEX instructions upper 16 registers
7036 aren't available, so VREX should be 0. */
7039 /* Now the VEX prefix. */
7040 p
= frag_more (i
.vex
.length
);
7041 for (j
= 0; j
< i
.vex
.length
; j
++)
7042 p
[j
] = i
.vex
.bytes
[j
];
7045 /* Now the opcode; be careful about word order here! */
7046 if (i
.tm
.opcode_length
== 1)
7048 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7052 switch (i
.tm
.opcode_length
)
7056 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7057 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7061 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7071 /* Put out high byte first: can't use md_number_to_chars! */
7072 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7073 *p
= i
.tm
.base_opcode
& 0xff;
7076 /* Now the modrm byte and sib byte (if present). */
7077 if (i
.tm
.opcode_modifier
.modrm
)
7079 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7082 /* If i.rm.regmem == ESP (4)
7083 && i.rm.mode != (Register mode)
7085 ==> need second modrm byte. */
7086 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7088 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7089 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7091 | i
.sib
.scale
<< 6));
7094 if (i
.disp_operands
)
7095 output_disp (insn_start_frag
, insn_start_off
);
7098 output_imm (insn_start_frag
, insn_start_off
);
7104 pi ("" /*line*/, &i
);
7106 #endif /* DEBUG386 */
7109 /* Return the size of the displacement operand N. */
7112 disp_size (unsigned int n
)
7116 /* Vec_Disp8 has to be 8bit. */
7117 if (i
.types
[n
].bitfield
.vec_disp8
)
7119 else if (i
.types
[n
].bitfield
.disp64
)
7121 else if (i
.types
[n
].bitfield
.disp8
)
7123 else if (i
.types
[n
].bitfield
.disp16
)
7128 /* Return the size of the immediate operand N. */
7131 imm_size (unsigned int n
)
7134 if (i
.types
[n
].bitfield
.imm64
)
7136 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7138 else if (i
.types
[n
].bitfield
.imm16
)
7144 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7149 for (n
= 0; n
< i
.operands
; n
++)
7151 if (i
.types
[n
].bitfield
.vec_disp8
7152 || operand_type_check (i
.types
[n
], disp
))
7154 if (i
.op
[n
].disps
->X_op
== O_constant
)
7156 int size
= disp_size (n
);
7157 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7159 if (i
.types
[n
].bitfield
.vec_disp8
)
7161 val
= offset_in_range (val
, size
);
7162 p
= frag_more (size
);
7163 md_number_to_chars (p
, val
, size
);
7167 enum bfd_reloc_code_real reloc_type
;
7168 int size
= disp_size (n
);
7169 int sign
= i
.types
[n
].bitfield
.disp32s
;
7170 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7172 /* We can't have 8 bit displacement here. */
7173 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7175 /* The PC relative address is computed relative
7176 to the instruction boundary, so in case immediate
7177 fields follows, we need to adjust the value. */
7178 if (pcrel
&& i
.imm_operands
)
7183 for (n1
= 0; n1
< i
.operands
; n1
++)
7184 if (operand_type_check (i
.types
[n1
], imm
))
7186 /* Only one immediate is allowed for PC
7187 relative address. */
7188 gas_assert (sz
== 0);
7190 i
.op
[n
].disps
->X_add_number
-= sz
;
7192 /* We should find the immediate. */
7193 gas_assert (sz
!= 0);
7196 p
= frag_more (size
);
7197 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7199 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7200 && (((reloc_type
== BFD_RELOC_32
7201 || reloc_type
== BFD_RELOC_X86_64_32S
7202 || (reloc_type
== BFD_RELOC_64
7204 && (i
.op
[n
].disps
->X_op
== O_symbol
7205 || (i
.op
[n
].disps
->X_op
== O_add
7206 && ((symbol_get_value_expression
7207 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7209 || reloc_type
== BFD_RELOC_32_PCREL
))
7213 if (insn_start_frag
== frag_now
)
7214 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7219 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7220 for (fr
= insn_start_frag
->fr_next
;
7221 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7223 add
+= p
- frag_now
->fr_literal
;
7228 reloc_type
= BFD_RELOC_386_GOTPC
;
7229 i
.op
[n
].imms
->X_add_number
+= add
;
7231 else if (reloc_type
== BFD_RELOC_64
)
7232 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7234 /* Don't do the adjustment for x86-64, as there
7235 the pcrel addressing is relative to the _next_
7236 insn, and that is taken care of in other code. */
7237 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7239 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7240 i
.op
[n
].disps
, pcrel
, reloc_type
);
7247 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7252 for (n
= 0; n
< i
.operands
; n
++)
7254 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7255 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7258 if (operand_type_check (i
.types
[n
], imm
))
7260 if (i
.op
[n
].imms
->X_op
== O_constant
)
7262 int size
= imm_size (n
);
7265 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7267 p
= frag_more (size
);
7268 md_number_to_chars (p
, val
, size
);
7272 /* Not absolute_section.
7273 Need a 32-bit fixup (don't support 8bit
7274 non-absolute imms). Try to support other
7276 enum bfd_reloc_code_real reloc_type
;
7277 int size
= imm_size (n
);
7280 if (i
.types
[n
].bitfield
.imm32s
7281 && (i
.suffix
== QWORD_MNEM_SUFFIX
7282 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7287 p
= frag_more (size
);
7288 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7290 /* This is tough to explain. We end up with this one if we
7291 * have operands that look like
7292 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7293 * obtain the absolute address of the GOT, and it is strongly
7294 * preferable from a performance point of view to avoid using
7295 * a runtime relocation for this. The actual sequence of
7296 * instructions often look something like:
7301 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7303 * The call and pop essentially return the absolute address
7304 * of the label .L66 and store it in %ebx. The linker itself
7305 * will ultimately change the first operand of the addl so
7306 * that %ebx points to the GOT, but to keep things simple, the
7307 * .o file must have this operand set so that it generates not
7308 * the absolute address of .L66, but the absolute address of
7309 * itself. This allows the linker itself simply treat a GOTPC
7310 * relocation as asking for a pcrel offset to the GOT to be
7311 * added in, and the addend of the relocation is stored in the
7312 * operand field for the instruction itself.
7314 * Our job here is to fix the operand so that it would add
7315 * the correct offset so that %ebx would point to itself. The
7316 * thing that is tricky is that .-.L66 will point to the
7317 * beginning of the instruction, so we need to further modify
7318 * the operand so that it will point to itself. There are
7319 * other cases where you have something like:
7321 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7323 * and here no correction would be required. Internally in
7324 * the assembler we treat operands of this form as not being
7325 * pcrel since the '.' is explicitly mentioned, and I wonder
7326 * whether it would simplify matters to do it this way. Who
7327 * knows. In earlier versions of the PIC patches, the
7328 * pcrel_adjust field was used to store the correction, but
7329 * since the expression is not pcrel, I felt it would be
7330 * confusing to do it this way. */
7332 if ((reloc_type
== BFD_RELOC_32
7333 || reloc_type
== BFD_RELOC_X86_64_32S
7334 || reloc_type
== BFD_RELOC_64
)
7336 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7337 && (i
.op
[n
].imms
->X_op
== O_symbol
7338 || (i
.op
[n
].imms
->X_op
== O_add
7339 && ((symbol_get_value_expression
7340 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7345 if (insn_start_frag
== frag_now
)
7346 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7351 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7352 for (fr
= insn_start_frag
->fr_next
;
7353 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7355 add
+= p
- frag_now
->fr_literal
;
7359 reloc_type
= BFD_RELOC_386_GOTPC
;
7361 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7363 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7364 i
.op
[n
].imms
->X_add_number
+= add
;
7366 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7367 i
.op
[n
].imms
, 0, reloc_type
);
7373 /* x86_cons_fix_new is called via the expression parsing code when a
7374 reloc is needed. We use this hook to get the correct .got reloc. */
7375 static int cons_sign
= -1;
7378 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7379 expressionS
*exp
, bfd_reloc_code_real_type r
)
7381 r
= reloc (len
, 0, cons_sign
, r
);
7384 if (exp
->X_op
== O_secrel
)
7386 exp
->X_op
= O_symbol
;
7387 r
= BFD_RELOC_32_SECREL
;
7391 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7394 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7395 purpose of the `.dc.a' internal pseudo-op. */
7398 x86_address_bytes (void)
7400 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7402 return stdoutput
->arch_info
->bits_per_address
/ 8;
7405 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7407 # define lex_got(reloc, adjust, types) NULL
7409 /* Parse operands of the form
7410 <symbol>@GOTOFF+<nnn>
7411 and similar .plt or .got references.
7413 If we find one, set up the correct relocation in RELOC and copy the
7414 input string, minus the `@GOTOFF' into a malloc'd buffer for
7415 parsing by the calling routine. Return this buffer, and if ADJUST
7416 is non-null set it to the length of the string we removed from the
7417 input line. Otherwise return NULL. */
7419 lex_got (enum bfd_reloc_code_real
*rel
,
7421 i386_operand_type
*types
)
7423 /* Some of the relocations depend on the size of what field is to
7424 be relocated. But in our callers i386_immediate and i386_displacement
7425 we don't yet know the operand size (this will be set by insn
7426 matching). Hence we record the word32 relocation here,
7427 and adjust the reloc according to the real size in reloc(). */
7428 static const struct {
7431 const enum bfd_reloc_code_real rel
[2];
7432 const i386_operand_type types64
;
7434 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7435 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7437 OPERAND_TYPE_IMM32_64
},
7439 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7440 BFD_RELOC_X86_64_PLTOFF64
},
7441 OPERAND_TYPE_IMM64
},
7442 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7443 BFD_RELOC_X86_64_PLT32
},
7444 OPERAND_TYPE_IMM32_32S_DISP32
},
7445 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7446 BFD_RELOC_X86_64_GOTPLT64
},
7447 OPERAND_TYPE_IMM64_DISP64
},
7448 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7449 BFD_RELOC_X86_64_GOTOFF64
},
7450 OPERAND_TYPE_IMM64_DISP64
},
7451 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7452 BFD_RELOC_X86_64_GOTPCREL
},
7453 OPERAND_TYPE_IMM32_32S_DISP32
},
7454 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7455 BFD_RELOC_X86_64_TLSGD
},
7456 OPERAND_TYPE_IMM32_32S_DISP32
},
7457 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7458 _dummy_first_bfd_reloc_code_real
},
7459 OPERAND_TYPE_NONE
},
7460 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7461 BFD_RELOC_X86_64_TLSLD
},
7462 OPERAND_TYPE_IMM32_32S_DISP32
},
7463 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7464 BFD_RELOC_X86_64_GOTTPOFF
},
7465 OPERAND_TYPE_IMM32_32S_DISP32
},
7466 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7467 BFD_RELOC_X86_64_TPOFF32
},
7468 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7469 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7470 _dummy_first_bfd_reloc_code_real
},
7471 OPERAND_TYPE_NONE
},
7472 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7473 BFD_RELOC_X86_64_DTPOFF32
},
7474 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7475 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7476 _dummy_first_bfd_reloc_code_real
},
7477 OPERAND_TYPE_NONE
},
7478 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7479 _dummy_first_bfd_reloc_code_real
},
7480 OPERAND_TYPE_NONE
},
7481 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7482 BFD_RELOC_X86_64_GOT32
},
7483 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7484 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7485 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7486 OPERAND_TYPE_IMM32_32S_DISP32
},
7487 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7488 BFD_RELOC_X86_64_TLSDESC_CALL
},
7489 OPERAND_TYPE_IMM32_32S_DISP32
},
7494 #if defined (OBJ_MAYBE_ELF)
7499 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7500 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7503 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7505 int len
= gotrel
[j
].len
;
7506 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7508 if (gotrel
[j
].rel
[object_64bit
] != 0)
7511 char *tmpbuf
, *past_reloc
;
7513 *rel
= gotrel
[j
].rel
[object_64bit
];
7517 if (flag_code
!= CODE_64BIT
)
7519 types
->bitfield
.imm32
= 1;
7520 types
->bitfield
.disp32
= 1;
7523 *types
= gotrel
[j
].types64
;
7526 if (j
!= 0 && GOT_symbol
== NULL
)
7527 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7529 /* The length of the first part of our input line. */
7530 first
= cp
- input_line_pointer
;
7532 /* The second part goes from after the reloc token until
7533 (and including) an end_of_line char or comma. */
7534 past_reloc
= cp
+ 1 + len
;
7536 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7538 second
= cp
+ 1 - past_reloc
;
7540 /* Allocate and copy string. The trailing NUL shouldn't
7541 be necessary, but be safe. */
7542 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7543 memcpy (tmpbuf
, input_line_pointer
, first
);
7544 if (second
!= 0 && *past_reloc
!= ' ')
7545 /* Replace the relocation token with ' ', so that
7546 errors like foo@GOTOFF1 will be detected. */
7547 tmpbuf
[first
++] = ' ';
7549 /* Increment length by 1 if the relocation token is
7554 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7555 tmpbuf
[first
+ second
] = '\0';
7559 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7560 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7565 /* Might be a symbol version string. Don't as_bad here. */
7574 /* Parse operands of the form
7575 <symbol>@SECREL32+<nnn>
7577 If we find one, set up the correct relocation in RELOC and copy the
7578 input string, minus the `@SECREL32' into a malloc'd buffer for
7579 parsing by the calling routine. Return this buffer, and if ADJUST
7580 is non-null set it to the length of the string we removed from the
7581 input line. Otherwise return NULL.
7583 This function is copied from the ELF version above adjusted for PE targets. */
7586 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7587 int *adjust ATTRIBUTE_UNUSED
,
7588 i386_operand_type
*types
)
7594 const enum bfd_reloc_code_real rel
[2];
7595 const i386_operand_type types64
;
7599 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7600 BFD_RELOC_32_SECREL
},
7601 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7607 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7608 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7611 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7613 int len
= gotrel
[j
].len
;
7615 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7617 if (gotrel
[j
].rel
[object_64bit
] != 0)
7620 char *tmpbuf
, *past_reloc
;
7622 *rel
= gotrel
[j
].rel
[object_64bit
];
7628 if (flag_code
!= CODE_64BIT
)
7630 types
->bitfield
.imm32
= 1;
7631 types
->bitfield
.disp32
= 1;
7634 *types
= gotrel
[j
].types64
;
7637 /* The length of the first part of our input line. */
7638 first
= cp
- input_line_pointer
;
7640 /* The second part goes from after the reloc token until
7641 (and including) an end_of_line char or comma. */
7642 past_reloc
= cp
+ 1 + len
;
7644 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7646 second
= cp
+ 1 - past_reloc
;
7648 /* Allocate and copy string. The trailing NUL shouldn't
7649 be necessary, but be safe. */
7650 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7651 memcpy (tmpbuf
, input_line_pointer
, first
);
7652 if (second
!= 0 && *past_reloc
!= ' ')
7653 /* Replace the relocation token with ' ', so that
7654 errors like foo@SECLREL321 will be detected. */
7655 tmpbuf
[first
++] = ' ';
7656 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7657 tmpbuf
[first
+ second
] = '\0';
7661 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7662 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7667 /* Might be a symbol version string. Don't as_bad here. */
7673 bfd_reloc_code_real_type
7674 x86_cons (expressionS
*exp
, int size
)
7676 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7678 intel_syntax
= -intel_syntax
;
7681 if (size
== 4 || (object_64bit
&& size
== 8))
7683 /* Handle @GOTOFF and the like in an expression. */
7685 char *gotfree_input_line
;
7688 save
= input_line_pointer
;
7689 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7690 if (gotfree_input_line
)
7691 input_line_pointer
= gotfree_input_line
;
7695 if (gotfree_input_line
)
7697 /* expression () has merrily parsed up to the end of line,
7698 or a comma - in the wrong buffer. Transfer how far
7699 input_line_pointer has moved to the right buffer. */
7700 input_line_pointer
= (save
7701 + (input_line_pointer
- gotfree_input_line
)
7703 free (gotfree_input_line
);
7704 if (exp
->X_op
== O_constant
7705 || exp
->X_op
== O_absent
7706 || exp
->X_op
== O_illegal
7707 || exp
->X_op
== O_register
7708 || exp
->X_op
== O_big
)
7710 char c
= *input_line_pointer
;
7711 *input_line_pointer
= 0;
7712 as_bad (_("missing or invalid expression `%s'"), save
);
7713 *input_line_pointer
= c
;
7720 intel_syntax
= -intel_syntax
;
7723 i386_intel_simplify (exp
);
7729 signed_cons (int size
)
7731 if (flag_code
== CODE_64BIT
)
7739 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7746 if (exp
.X_op
== O_symbol
)
7747 exp
.X_op
= O_secrel
;
7749 emit_expr (&exp
, 4);
7751 while (*input_line_pointer
++ == ',');
7753 input_line_pointer
--;
7754 demand_empty_rest_of_line ();
7758 /* Handle Vector operations. */
7761 check_VecOperations (char *op_string
, char *op_end
)
7763 const reg_entry
*mask
;
7768 && (op_end
== NULL
|| op_string
< op_end
))
7771 if (*op_string
== '{')
7775 /* Check broadcasts. */
7776 if (strncmp (op_string
, "1to", 3) == 0)
7781 goto duplicated_vec_op
;
7784 if (*op_string
== '8')
7785 bcst_type
= BROADCAST_1TO8
;
7786 else if (*op_string
== '4')
7787 bcst_type
= BROADCAST_1TO4
;
7788 else if (*op_string
== '2')
7789 bcst_type
= BROADCAST_1TO2
;
7790 else if (*op_string
== '1'
7791 && *(op_string
+1) == '6')
7793 bcst_type
= BROADCAST_1TO16
;
7798 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7803 broadcast_op
.type
= bcst_type
;
7804 broadcast_op
.operand
= this_operand
;
7805 i
.broadcast
= &broadcast_op
;
7807 /* Check masking operation. */
7808 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7810 /* k0 can't be used for write mask. */
7811 if (mask
->reg_num
== 0)
7813 as_bad (_("`%s' can't be used for write mask"),
7820 mask_op
.mask
= mask
;
7821 mask_op
.zeroing
= 0;
7822 mask_op
.operand
= this_operand
;
7828 goto duplicated_vec_op
;
7830 i
.mask
->mask
= mask
;
7832 /* Only "{z}" is allowed here. No need to check
7833 zeroing mask explicitly. */
7834 if (i
.mask
->operand
!= this_operand
)
7836 as_bad (_("invalid write mask `%s'"), saved
);
7843 /* Check zeroing-flag for masking operation. */
7844 else if (*op_string
== 'z')
7848 mask_op
.mask
= NULL
;
7849 mask_op
.zeroing
= 1;
7850 mask_op
.operand
= this_operand
;
7855 if (i
.mask
->zeroing
)
7858 as_bad (_("duplicated `%s'"), saved
);
7862 i
.mask
->zeroing
= 1;
7864 /* Only "{%k}" is allowed here. No need to check mask
7865 register explicitly. */
7866 if (i
.mask
->operand
!= this_operand
)
7868 as_bad (_("invalid zeroing-masking `%s'"),
7877 goto unknown_vec_op
;
7879 if (*op_string
!= '}')
7881 as_bad (_("missing `}' in `%s'"), saved
);
7888 /* We don't know this one. */
7889 as_bad (_("unknown vector operation: `%s'"), saved
);
7897 i386_immediate (char *imm_start
)
7899 char *save_input_line_pointer
;
7900 char *gotfree_input_line
;
7903 i386_operand_type types
;
7905 operand_type_set (&types
, ~0);
7907 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7909 as_bad (_("at most %d immediate operands are allowed"),
7910 MAX_IMMEDIATE_OPERANDS
);
7914 exp
= &im_expressions
[i
.imm_operands
++];
7915 i
.op
[this_operand
].imms
= exp
;
7917 if (is_space_char (*imm_start
))
7920 save_input_line_pointer
= input_line_pointer
;
7921 input_line_pointer
= imm_start
;
7923 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7924 if (gotfree_input_line
)
7925 input_line_pointer
= gotfree_input_line
;
7927 exp_seg
= expression (exp
);
7931 /* Handle vector operations. */
7932 if (*input_line_pointer
== '{')
7934 input_line_pointer
= check_VecOperations (input_line_pointer
,
7936 if (input_line_pointer
== NULL
)
7940 if (*input_line_pointer
)
7941 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7943 input_line_pointer
= save_input_line_pointer
;
7944 if (gotfree_input_line
)
7946 free (gotfree_input_line
);
7948 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7949 exp
->X_op
= O_illegal
;
7952 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7956 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7957 i386_operand_type types
, const char *imm_start
)
7959 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7962 as_bad (_("missing or invalid immediate expression `%s'"),
7966 else if (exp
->X_op
== O_constant
)
7968 /* Size it properly later. */
7969 i
.types
[this_operand
].bitfield
.imm64
= 1;
7970 /* If not 64bit, sign extend val. */
7971 if (flag_code
!= CODE_64BIT
7972 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7974 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7976 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7977 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7978 && exp_seg
!= absolute_section
7979 && exp_seg
!= text_section
7980 && exp_seg
!= data_section
7981 && exp_seg
!= bss_section
7982 && exp_seg
!= undefined_section
7983 && !bfd_is_com_section (exp_seg
))
7985 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7989 else if (!intel_syntax
&& exp_seg
== reg_section
)
7992 as_bad (_("illegal immediate register operand %s"), imm_start
);
7997 /* This is an address. The size of the address will be
7998 determined later, depending on destination register,
7999 suffix, or the default for the section. */
8000 i
.types
[this_operand
].bitfield
.imm8
= 1;
8001 i
.types
[this_operand
].bitfield
.imm16
= 1;
8002 i
.types
[this_operand
].bitfield
.imm32
= 1;
8003 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8004 i
.types
[this_operand
].bitfield
.imm64
= 1;
8005 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8013 i386_scale (char *scale
)
8016 char *save
= input_line_pointer
;
8018 input_line_pointer
= scale
;
8019 val
= get_absolute_expression ();
8024 i
.log2_scale_factor
= 0;
8027 i
.log2_scale_factor
= 1;
8030 i
.log2_scale_factor
= 2;
8033 i
.log2_scale_factor
= 3;
8037 char sep
= *input_line_pointer
;
8039 *input_line_pointer
= '\0';
8040 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8042 *input_line_pointer
= sep
;
8043 input_line_pointer
= save
;
8047 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8049 as_warn (_("scale factor of %d without an index register"),
8050 1 << i
.log2_scale_factor
);
8051 i
.log2_scale_factor
= 0;
8053 scale
= input_line_pointer
;
8054 input_line_pointer
= save
;
8059 i386_displacement (char *disp_start
, char *disp_end
)
8063 char *save_input_line_pointer
;
8064 char *gotfree_input_line
;
8066 i386_operand_type bigdisp
, types
= anydisp
;
8069 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8071 as_bad (_("at most %d displacement operands are allowed"),
8072 MAX_MEMORY_OPERANDS
);
8076 operand_type_set (&bigdisp
, 0);
8077 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8078 || (!current_templates
->start
->opcode_modifier
.jump
8079 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8081 bigdisp
.bitfield
.disp32
= 1;
8082 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8083 if (flag_code
== CODE_64BIT
)
8087 bigdisp
.bitfield
.disp32s
= 1;
8088 bigdisp
.bitfield
.disp64
= 1;
8091 else if ((flag_code
== CODE_16BIT
) ^ override
)
8093 bigdisp
.bitfield
.disp32
= 0;
8094 bigdisp
.bitfield
.disp16
= 1;
8099 /* For PC-relative branches, the width of the displacement
8100 is dependent upon data size, not address size. */
8101 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8102 if (flag_code
== CODE_64BIT
)
8104 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8105 bigdisp
.bitfield
.disp16
= 1;
8108 bigdisp
.bitfield
.disp32
= 1;
8109 bigdisp
.bitfield
.disp32s
= 1;
8115 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8117 : LONG_MNEM_SUFFIX
));
8118 bigdisp
.bitfield
.disp32
= 1;
8119 if ((flag_code
== CODE_16BIT
) ^ override
)
8121 bigdisp
.bitfield
.disp32
= 0;
8122 bigdisp
.bitfield
.disp16
= 1;
8126 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8129 exp
= &disp_expressions
[i
.disp_operands
];
8130 i
.op
[this_operand
].disps
= exp
;
8132 save_input_line_pointer
= input_line_pointer
;
8133 input_line_pointer
= disp_start
;
8134 END_STRING_AND_SAVE (disp_end
);
8136 #ifndef GCC_ASM_O_HACK
8137 #define GCC_ASM_O_HACK 0
8140 END_STRING_AND_SAVE (disp_end
+ 1);
8141 if (i
.types
[this_operand
].bitfield
.baseIndex
8142 && displacement_string_end
[-1] == '+')
8144 /* This hack is to avoid a warning when using the "o"
8145 constraint within gcc asm statements.
8148 #define _set_tssldt_desc(n,addr,limit,type) \
8149 __asm__ __volatile__ ( \
8151 "movw %w1,2+%0\n\t" \
8153 "movb %b1,4+%0\n\t" \
8154 "movb %4,5+%0\n\t" \
8155 "movb $0,6+%0\n\t" \
8156 "movb %h1,7+%0\n\t" \
8158 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8160 This works great except that the output assembler ends
8161 up looking a bit weird if it turns out that there is
8162 no offset. You end up producing code that looks like:
8175 So here we provide the missing zero. */
8177 *displacement_string_end
= '0';
8180 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8181 if (gotfree_input_line
)
8182 input_line_pointer
= gotfree_input_line
;
8184 exp_seg
= expression (exp
);
8187 if (*input_line_pointer
)
8188 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8190 RESTORE_END_STRING (disp_end
+ 1);
8192 input_line_pointer
= save_input_line_pointer
;
8193 if (gotfree_input_line
)
8195 free (gotfree_input_line
);
8197 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8198 exp
->X_op
= O_illegal
;
8201 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8203 RESTORE_END_STRING (disp_end
);
8209 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8210 i386_operand_type types
, const char *disp_start
)
8212 i386_operand_type bigdisp
;
8215 /* We do this to make sure that the section symbol is in
8216 the symbol table. We will ultimately change the relocation
8217 to be relative to the beginning of the section. */
8218 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8219 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8220 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8222 if (exp
->X_op
!= O_symbol
)
8225 if (S_IS_LOCAL (exp
->X_add_symbol
)
8226 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8227 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8228 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8229 exp
->X_op
= O_subtract
;
8230 exp
->X_op_symbol
= GOT_symbol
;
8231 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8232 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8233 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8234 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8236 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8239 else if (exp
->X_op
== O_absent
8240 || exp
->X_op
== O_illegal
8241 || exp
->X_op
== O_big
)
8244 as_bad (_("missing or invalid displacement expression `%s'"),
8249 else if (flag_code
== CODE_64BIT
8250 && !i
.prefix
[ADDR_PREFIX
]
8251 && exp
->X_op
== O_constant
)
8253 /* Since displacement is signed extended to 64bit, don't allow
8254 disp32 and turn off disp32s if they are out of range. */
8255 i
.types
[this_operand
].bitfield
.disp32
= 0;
8256 if (!fits_in_signed_long (exp
->X_add_number
))
8258 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8259 if (i
.types
[this_operand
].bitfield
.baseindex
)
8261 as_bad (_("0x%lx out range of signed 32bit displacement"),
8262 (long) exp
->X_add_number
);
8268 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8269 else if (exp
->X_op
!= O_constant
8270 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8271 && exp_seg
!= absolute_section
8272 && exp_seg
!= text_section
8273 && exp_seg
!= data_section
8274 && exp_seg
!= bss_section
8275 && exp_seg
!= undefined_section
8276 && !bfd_is_com_section (exp_seg
))
8278 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8283 /* Check if this is a displacement only operand. */
8284 bigdisp
= i
.types
[this_operand
];
8285 bigdisp
.bitfield
.disp8
= 0;
8286 bigdisp
.bitfield
.disp16
= 0;
8287 bigdisp
.bitfield
.disp32
= 0;
8288 bigdisp
.bitfield
.disp32s
= 0;
8289 bigdisp
.bitfield
.disp64
= 0;
8290 if (operand_type_all_zero (&bigdisp
))
8291 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8297 /* Make sure the memory operand we've been dealt is valid.
8298 Return 1 on success, 0 on a failure. */
8301 i386_index_check (const char *operand_string
)
8303 const char *kind
= "base/index";
8304 enum flag_code addr_mode
;
8306 if (i
.prefix
[ADDR_PREFIX
])
8307 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8310 addr_mode
= flag_code
;
8312 #if INFER_ADDR_PREFIX
8313 if (i
.mem_operands
== 0)
8315 /* Infer address prefix from the first memory operand. */
8316 const reg_entry
*addr_reg
= i
.base_reg
;
8318 if (addr_reg
== NULL
)
8319 addr_reg
= i
.index_reg
;
8323 if (addr_reg
->reg_num
== RegEip
8324 || addr_reg
->reg_num
== RegEiz
8325 || addr_reg
->reg_type
.bitfield
.reg32
)
8326 addr_mode
= CODE_32BIT
;
8327 else if (flag_code
!= CODE_64BIT
8328 && addr_reg
->reg_type
.bitfield
.reg16
)
8329 addr_mode
= CODE_16BIT
;
8331 if (addr_mode
!= flag_code
)
8333 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8335 /* Change the size of any displacement too. At most one
8336 of Disp16 or Disp32 is set.
8337 FIXME. There doesn't seem to be any real need for
8338 separate Disp16 and Disp32 flags. The same goes for
8339 Imm16 and Imm32. Removing them would probably clean
8340 up the code quite a lot. */
8341 if (flag_code
!= CODE_64BIT
8342 && (i
.types
[this_operand
].bitfield
.disp16
8343 || i
.types
[this_operand
].bitfield
.disp32
))
8344 i
.types
[this_operand
]
8345 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8352 if (current_templates
->start
->opcode_modifier
.isstring
8353 && !current_templates
->start
->opcode_modifier
.immext
8354 && (current_templates
->end
[-1].opcode_modifier
.isstring
8357 /* Memory operands of string insns are special in that they only allow
8358 a single register (rDI, rSI, or rBX) as their memory address. */
8359 const reg_entry
*expected_reg
;
8360 static const char *di_si
[][2] =
8366 static const char *bx
[] = { "ebx", "bx", "rbx" };
8368 kind
= "string address";
8370 if (current_templates
->start
->opcode_modifier
.w
)
8372 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8374 if (!type
.bitfield
.baseindex
8375 || ((!i
.mem_operands
!= !intel_syntax
)
8376 && current_templates
->end
[-1].operand_types
[1]
8377 .bitfield
.baseindex
))
8378 type
= current_templates
->end
[-1].operand_types
[1];
8379 expected_reg
= hash_find (reg_hash
,
8380 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8384 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8386 if (i
.base_reg
!= expected_reg
8388 || operand_type_check (i
.types
[this_operand
], disp
))
8390 /* The second memory operand must have the same size as
8394 && !((addr_mode
== CODE_64BIT
8395 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8396 || (addr_mode
== CODE_32BIT
8397 ? i
.base_reg
->reg_type
.bitfield
.reg32
8398 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8401 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8403 intel_syntax
? '[' : '(',
8405 expected_reg
->reg_name
,
8406 intel_syntax
? ']' : ')');
8413 as_bad (_("`%s' is not a valid %s expression"),
8414 operand_string
, kind
);
8419 if (addr_mode
!= CODE_16BIT
)
8421 /* 32-bit/64-bit checks. */
8423 && (addr_mode
== CODE_64BIT
8424 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8425 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8427 || (i
.base_reg
->reg_num
8428 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8430 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8431 && !i
.index_reg
->reg_type
.bitfield
.regymm
8432 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8433 && ((addr_mode
== CODE_64BIT
8434 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8435 || i
.index_reg
->reg_num
== RegRiz
)
8436 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8437 || i
.index_reg
->reg_num
== RegEiz
))
8438 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8443 /* 16-bit checks. */
8445 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8446 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8448 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8449 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8451 && i
.base_reg
->reg_num
< 6
8452 && i
.index_reg
->reg_num
>= 6
8453 && i
.log2_scale_factor
== 0))))
8460 /* Handle vector immediates. */
8463 RC_SAE_immediate (const char *imm_start
)
8465 unsigned int match_found
, j
;
8466 const char *pstr
= imm_start
;
8474 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8476 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8480 rc_op
.type
= RC_NamesTable
[j
].type
;
8481 rc_op
.operand
= this_operand
;
8482 i
.rounding
= &rc_op
;
8486 as_bad (_("duplicated `%s'"), imm_start
);
8489 pstr
+= RC_NamesTable
[j
].len
;
8499 as_bad (_("Missing '}': '%s'"), imm_start
);
8502 /* RC/SAE immediate string should contain nothing more. */;
8505 as_bad (_("Junk after '}': '%s'"), imm_start
);
8509 exp
= &im_expressions
[i
.imm_operands
++];
8510 i
.op
[this_operand
].imms
= exp
;
8512 exp
->X_op
= O_constant
;
8513 exp
->X_add_number
= 0;
8514 exp
->X_add_symbol
= (symbolS
*) 0;
8515 exp
->X_op_symbol
= (symbolS
*) 0;
8517 i
.types
[this_operand
].bitfield
.imm8
= 1;
8521 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8525 i386_att_operand (char *operand_string
)
8529 char *op_string
= operand_string
;
8531 if (is_space_char (*op_string
))
8534 /* We check for an absolute prefix (differentiating,
8535 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8536 if (*op_string
== ABSOLUTE_PREFIX
)
8539 if (is_space_char (*op_string
))
8541 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8544 /* Check if operand is a register. */
8545 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8547 i386_operand_type temp
;
8549 /* Check for a segment override by searching for ':' after a
8550 segment register. */
8552 if (is_space_char (*op_string
))
8554 if (*op_string
== ':'
8555 && (r
->reg_type
.bitfield
.sreg2
8556 || r
->reg_type
.bitfield
.sreg3
))
8561 i
.seg
[i
.mem_operands
] = &es
;
8564 i
.seg
[i
.mem_operands
] = &cs
;
8567 i
.seg
[i
.mem_operands
] = &ss
;
8570 i
.seg
[i
.mem_operands
] = &ds
;
8573 i
.seg
[i
.mem_operands
] = &fs
;
8576 i
.seg
[i
.mem_operands
] = &gs
;
8580 /* Skip the ':' and whitespace. */
8582 if (is_space_char (*op_string
))
8585 if (!is_digit_char (*op_string
)
8586 && !is_identifier_char (*op_string
)
8587 && *op_string
!= '('
8588 && *op_string
!= ABSOLUTE_PREFIX
)
8590 as_bad (_("bad memory operand `%s'"), op_string
);
8593 /* Handle case of %es:*foo. */
8594 if (*op_string
== ABSOLUTE_PREFIX
)
8597 if (is_space_char (*op_string
))
8599 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8601 goto do_memory_reference
;
8604 /* Handle vector operations. */
8605 if (*op_string
== '{')
8607 op_string
= check_VecOperations (op_string
, NULL
);
8608 if (op_string
== NULL
)
8614 as_bad (_("junk `%s' after register"), op_string
);
8618 temp
.bitfield
.baseindex
= 0;
8619 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8621 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8622 i
.op
[this_operand
].regs
= r
;
8625 else if (*op_string
== REGISTER_PREFIX
)
8627 as_bad (_("bad register name `%s'"), op_string
);
8630 else if (*op_string
== IMMEDIATE_PREFIX
)
8633 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8635 as_bad (_("immediate operand illegal with absolute jump"));
8638 if (!i386_immediate (op_string
))
8641 else if (RC_SAE_immediate (operand_string
))
8643 /* If it is a RC or SAE immediate, do nothing. */
8646 else if (is_digit_char (*op_string
)
8647 || is_identifier_char (*op_string
)
8648 || *op_string
== '(')
8650 /* This is a memory reference of some sort. */
8653 /* Start and end of displacement string expression (if found). */
8654 char *displacement_string_start
;
8655 char *displacement_string_end
;
8658 do_memory_reference
:
8659 if ((i
.mem_operands
== 1
8660 && !current_templates
->start
->opcode_modifier
.isstring
)
8661 || i
.mem_operands
== 2)
8663 as_bad (_("too many memory references for `%s'"),
8664 current_templates
->start
->name
);
8668 /* Check for base index form. We detect the base index form by
8669 looking for an ')' at the end of the operand, searching
8670 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8672 base_string
= op_string
+ strlen (op_string
);
8674 /* Handle vector operations. */
8675 vop_start
= strchr (op_string
, '{');
8676 if (vop_start
&& vop_start
< base_string
)
8678 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8680 base_string
= vop_start
;
8684 if (is_space_char (*base_string
))
8687 /* If we only have a displacement, set-up for it to be parsed later. */
8688 displacement_string_start
= op_string
;
8689 displacement_string_end
= base_string
+ 1;
8691 if (*base_string
== ')')
8694 unsigned int parens_balanced
= 1;
8695 /* We've already checked that the number of left & right ()'s are
8696 equal, so this loop will not be infinite. */
8700 if (*base_string
== ')')
8702 if (*base_string
== '(')
8705 while (parens_balanced
);
8707 temp_string
= base_string
;
8709 /* Skip past '(' and whitespace. */
8711 if (is_space_char (*base_string
))
8714 if (*base_string
== ','
8715 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8718 displacement_string_end
= temp_string
;
8720 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8724 base_string
= end_op
;
8725 if (is_space_char (*base_string
))
8729 /* There may be an index reg or scale factor here. */
8730 if (*base_string
== ',')
8733 if (is_space_char (*base_string
))
8736 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8739 base_string
= end_op
;
8740 if (is_space_char (*base_string
))
8742 if (*base_string
== ',')
8745 if (is_space_char (*base_string
))
8748 else if (*base_string
!= ')')
8750 as_bad (_("expecting `,' or `)' "
8751 "after index register in `%s'"),
8756 else if (*base_string
== REGISTER_PREFIX
)
8758 end_op
= strchr (base_string
, ',');
8761 as_bad (_("bad register name `%s'"), base_string
);
8765 /* Check for scale factor. */
8766 if (*base_string
!= ')')
8768 char *end_scale
= i386_scale (base_string
);
8773 base_string
= end_scale
;
8774 if (is_space_char (*base_string
))
8776 if (*base_string
!= ')')
8778 as_bad (_("expecting `)' "
8779 "after scale factor in `%s'"),
8784 else if (!i
.index_reg
)
8786 as_bad (_("expecting index register or scale factor "
8787 "after `,'; got '%c'"),
8792 else if (*base_string
!= ')')
8794 as_bad (_("expecting `,' or `)' "
8795 "after base register in `%s'"),
8800 else if (*base_string
== REGISTER_PREFIX
)
8802 end_op
= strchr (base_string
, ',');
8805 as_bad (_("bad register name `%s'"), base_string
);
8810 /* If there's an expression beginning the operand, parse it,
8811 assuming displacement_string_start and
8812 displacement_string_end are meaningful. */
8813 if (displacement_string_start
!= displacement_string_end
)
8815 if (!i386_displacement (displacement_string_start
,
8816 displacement_string_end
))
8820 /* Special case for (%dx) while doing input/output op. */
8822 && operand_type_equal (&i
.base_reg
->reg_type
,
8823 ®16_inoutportreg
)
8825 && i
.log2_scale_factor
== 0
8826 && i
.seg
[i
.mem_operands
] == 0
8827 && !operand_type_check (i
.types
[this_operand
], disp
))
8829 i
.types
[this_operand
] = inoutportreg
;
8833 if (i386_index_check (operand_string
) == 0)
8835 i
.types
[this_operand
].bitfield
.mem
= 1;
8840 /* It's not a memory operand; argh! */
8841 as_bad (_("invalid char %s beginning operand %d `%s'"),
8842 output_invalid (*op_string
),
8847 return 1; /* Normal return. */
8850 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8851 that an rs_machine_dependent frag may reach. */
8854 i386_frag_max_var (fragS
*frag
)
8856 /* The only relaxable frags are for jumps.
8857 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8858 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8859 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8862 /* md_estimate_size_before_relax()
8864 Called just before relax() for rs_machine_dependent frags. The x86
8865 assembler uses these frags to handle variable size jump
8868 Any symbol that is now undefined will not become defined.
8869 Return the correct fr_subtype in the frag.
8870 Return the initial "guess for variable size of frag" to caller.
8871 The guess is actually the growth beyond the fixed part. Whatever
8872 we do to grow the fixed or variable part contributes to our
8876 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8878 /* We've already got fragP->fr_subtype right; all we have to do is
8879 check for un-relaxable symbols. On an ELF system, we can't relax
8880 an externally visible symbol, because it may be overridden by a
8882 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8883 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8885 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8886 || S_IS_WEAK (fragP
->fr_symbol
)
8887 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8888 & BSF_GNU_INDIRECT_FUNCTION
))))
8890 #if defined (OBJ_COFF) && defined (TE_PE)
8891 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8892 && S_IS_WEAK (fragP
->fr_symbol
))
8896 /* Symbol is undefined in this segment, or we need to keep a
8897 reloc so that weak symbols can be overridden. */
8898 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8899 enum bfd_reloc_code_real reloc_type
;
8900 unsigned char *opcode
;
8903 if (fragP
->fr_var
!= NO_RELOC
)
8904 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8906 reloc_type
= BFD_RELOC_16_PCREL
;
8908 reloc_type
= BFD_RELOC_32_PCREL
;
8910 old_fr_fix
= fragP
->fr_fix
;
8911 opcode
= (unsigned char *) fragP
->fr_opcode
;
8913 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8916 /* Make jmp (0xeb) a (d)word displacement jump. */
8918 fragP
->fr_fix
+= size
;
8919 fix_new (fragP
, old_fr_fix
, size
,
8921 fragP
->fr_offset
, 1,
8927 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8929 /* Negate the condition, and branch past an
8930 unconditional jump. */
8933 /* Insert an unconditional jump. */
8935 /* We added two extra opcode bytes, and have a two byte
8937 fragP
->fr_fix
+= 2 + 2;
8938 fix_new (fragP
, old_fr_fix
+ 2, 2,
8940 fragP
->fr_offset
, 1,
8947 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8952 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8954 fragP
->fr_offset
, 1,
8956 fixP
->fx_signed
= 1;
8960 /* This changes the byte-displacement jump 0x7N
8961 to the (d)word-displacement jump 0x0f,0x8N. */
8962 opcode
[1] = opcode
[0] + 0x10;
8963 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8964 /* We've added an opcode byte. */
8965 fragP
->fr_fix
+= 1 + size
;
8966 fix_new (fragP
, old_fr_fix
+ 1, size
,
8968 fragP
->fr_offset
, 1,
8973 BAD_CASE (fragP
->fr_subtype
);
8977 return fragP
->fr_fix
- old_fr_fix
;
8980 /* Guess size depending on current relax state. Initially the relax
8981 state will correspond to a short jump and we return 1, because
8982 the variable part of the frag (the branch offset) is one byte
8983 long. However, we can relax a section more than once and in that
8984 case we must either set fr_subtype back to the unrelaxed state,
8985 or return the value for the appropriate branch. */
8986 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8989 /* Called after relax() is finished.
8991 In: Address of frag.
8992 fr_type == rs_machine_dependent.
8993 fr_subtype is what the address relaxed to.
8995 Out: Any fixSs and constants are set up.
8996 Caller will turn frag into a ".space 0". */
8999 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9002 unsigned char *opcode
;
9003 unsigned char *where_to_put_displacement
= NULL
;
9004 offsetT target_address
;
9005 offsetT opcode_address
;
9006 unsigned int extension
= 0;
9007 offsetT displacement_from_opcode_start
;
9009 opcode
= (unsigned char *) fragP
->fr_opcode
;
9011 /* Address we want to reach in file space. */
9012 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9014 /* Address opcode resides at in file space. */
9015 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9017 /* Displacement from opcode start to fill into instruction. */
9018 displacement_from_opcode_start
= target_address
- opcode_address
;
9020 if ((fragP
->fr_subtype
& BIG
) == 0)
9022 /* Don't have to change opcode. */
9023 extension
= 1; /* 1 opcode + 1 displacement */
9024 where_to_put_displacement
= &opcode
[1];
9028 if (no_cond_jump_promotion
9029 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9030 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9031 _("long jump required"));
9033 switch (fragP
->fr_subtype
)
9035 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9036 extension
= 4; /* 1 opcode + 4 displacement */
9038 where_to_put_displacement
= &opcode
[1];
9041 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9042 extension
= 2; /* 1 opcode + 2 displacement */
9044 where_to_put_displacement
= &opcode
[1];
9047 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9048 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9049 extension
= 5; /* 2 opcode + 4 displacement */
9050 opcode
[1] = opcode
[0] + 0x10;
9051 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9052 where_to_put_displacement
= &opcode
[2];
9055 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9056 extension
= 3; /* 2 opcode + 2 displacement */
9057 opcode
[1] = opcode
[0] + 0x10;
9058 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9059 where_to_put_displacement
= &opcode
[2];
9062 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9067 where_to_put_displacement
= &opcode
[3];
9071 BAD_CASE (fragP
->fr_subtype
);
9076 /* If size if less then four we are sure that the operand fits,
9077 but if it's 4, then it could be that the displacement is larger
9079 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9081 && ((addressT
) (displacement_from_opcode_start
- extension
9082 + ((addressT
) 1 << 31))
9083 > (((addressT
) 2 << 31) - 1)))
9085 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9086 _("jump target out of range"));
9087 /* Make us emit 0. */
9088 displacement_from_opcode_start
= extension
;
9090 /* Now put displacement after opcode. */
9091 md_number_to_chars ((char *) where_to_put_displacement
,
9092 (valueT
) (displacement_from_opcode_start
- extension
),
9093 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9094 fragP
->fr_fix
+= extension
;
9097 /* Apply a fixup (fixP) to segment data, once it has been determined
9098 by our caller that we have all the info we need to fix it up.
9100 Parameter valP is the pointer to the value of the bits.
9102 On the 386, immediates, displacements, and data pointers are all in
9103 the same (little-endian) format, so we don't need to care about which
9107 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9109 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9110 valueT value
= *valP
;
9112 #if !defined (TE_Mach)
9115 switch (fixP
->fx_r_type
)
9121 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9124 case BFD_RELOC_X86_64_32S
:
9125 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9128 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9131 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9136 if (fixP
->fx_addsy
!= NULL
9137 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9138 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9139 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9140 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9141 && !use_rela_relocations
)
9143 /* This is a hack. There should be a better way to handle this.
9144 This covers for the fact that bfd_install_relocation will
9145 subtract the current location (for partial_inplace, PC relative
9146 relocations); see more below. */
9150 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9153 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9158 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9161 || (symbol_section_p (fixP
->fx_addsy
)
9162 && sym_seg
!= absolute_section
))
9163 && !generic_force_reloc (fixP
))
9165 /* Yes, we add the values in twice. This is because
9166 bfd_install_relocation subtracts them out again. I think
9167 bfd_install_relocation is broken, but I don't dare change
9169 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9173 #if defined (OBJ_COFF) && defined (TE_PE)
9174 /* For some reason, the PE format does not store a
9175 section address offset for a PC relative symbol. */
9176 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9177 || S_IS_WEAK (fixP
->fx_addsy
))
9178 value
+= md_pcrel_from (fixP
);
9181 #if defined (OBJ_COFF) && defined (TE_PE)
9182 if (fixP
->fx_addsy
!= NULL
9183 && S_IS_WEAK (fixP
->fx_addsy
)
9184 /* PR 16858: Do not modify weak function references. */
9185 && ! fixP
->fx_pcrel
)
9187 #if !defined (TE_PEP)
9188 /* For x86 PE weak function symbols are neither PC-relative
9189 nor do they set S_IS_FUNCTION. So the only reliable way
9190 to detect them is to check the flags of their containing
9192 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9193 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9197 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9201 /* Fix a few things - the dynamic linker expects certain values here,
9202 and we must not disappoint it. */
9203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9204 if (IS_ELF
&& fixP
->fx_addsy
)
9205 switch (fixP
->fx_r_type
)
9207 case BFD_RELOC_386_PLT32
:
9208 case BFD_RELOC_X86_64_PLT32
:
9209 /* Make the jump instruction point to the address of the operand. At
9210 runtime we merely add the offset to the actual PLT entry. */
9214 case BFD_RELOC_386_TLS_GD
:
9215 case BFD_RELOC_386_TLS_LDM
:
9216 case BFD_RELOC_386_TLS_IE_32
:
9217 case BFD_RELOC_386_TLS_IE
:
9218 case BFD_RELOC_386_TLS_GOTIE
:
9219 case BFD_RELOC_386_TLS_GOTDESC
:
9220 case BFD_RELOC_X86_64_TLSGD
:
9221 case BFD_RELOC_X86_64_TLSLD
:
9222 case BFD_RELOC_X86_64_GOTTPOFF
:
9223 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9224 value
= 0; /* Fully resolved at runtime. No addend. */
9226 case BFD_RELOC_386_TLS_LE
:
9227 case BFD_RELOC_386_TLS_LDO_32
:
9228 case BFD_RELOC_386_TLS_LE_32
:
9229 case BFD_RELOC_X86_64_DTPOFF32
:
9230 case BFD_RELOC_X86_64_DTPOFF64
:
9231 case BFD_RELOC_X86_64_TPOFF32
:
9232 case BFD_RELOC_X86_64_TPOFF64
:
9233 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9236 case BFD_RELOC_386_TLS_DESC_CALL
:
9237 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9238 value
= 0; /* Fully resolved at runtime. No addend. */
9239 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9243 case BFD_RELOC_386_GOT32
:
9244 case BFD_RELOC_X86_64_GOT32
:
9245 value
= 0; /* Fully resolved at runtime. No addend. */
9248 case BFD_RELOC_VTABLE_INHERIT
:
9249 case BFD_RELOC_VTABLE_ENTRY
:
9256 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9258 #endif /* !defined (TE_Mach) */
9260 /* Are we finished with this relocation now? */
9261 if (fixP
->fx_addsy
== NULL
)
9263 #if defined (OBJ_COFF) && defined (TE_PE)
9264 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9267 /* Remember value for tc_gen_reloc. */
9268 fixP
->fx_addnumber
= value
;
9269 /* Clear out the frag for now. */
9273 else if (use_rela_relocations
)
9275 fixP
->fx_no_overflow
= 1;
9276 /* Remember value for tc_gen_reloc. */
9277 fixP
->fx_addnumber
= value
;
9281 md_number_to_chars (p
, value
, fixP
->fx_size
);
9285 md_atof (int type
, char *litP
, int *sizeP
)
9287 /* This outputs the LITTLENUMs in REVERSE order;
9288 in accord with the bigendian 386. */
9289 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9292 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9295 output_invalid (int c
)
9298 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9301 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9302 "(0x%x)", (unsigned char) c
);
9303 return output_invalid_buf
;
9306 /* REG_STRING starts *before* REGISTER_PREFIX. */
9308 static const reg_entry
*
9309 parse_real_register (char *reg_string
, char **end_op
)
9311 char *s
= reg_string
;
9313 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9316 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9317 if (*s
== REGISTER_PREFIX
)
9320 if (is_space_char (*s
))
9324 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9326 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9327 return (const reg_entry
*) NULL
;
9331 /* For naked regs, make sure that we are not dealing with an identifier.
9332 This prevents confusing an identifier like `eax_var' with register
9334 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9335 return (const reg_entry
*) NULL
;
9339 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9341 /* Handle floating point regs, allowing spaces in the (i) part. */
9342 if (r
== i386_regtab
/* %st is first entry of table */)
9344 if (is_space_char (*s
))
9349 if (is_space_char (*s
))
9351 if (*s
>= '0' && *s
<= '7')
9355 if (is_space_char (*s
))
9360 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9365 /* We have "%st(" then garbage. */
9366 return (const reg_entry
*) NULL
;
9370 if (r
== NULL
|| allow_pseudo_reg
)
9373 if (operand_type_all_zero (&r
->reg_type
))
9374 return (const reg_entry
*) NULL
;
9376 if ((r
->reg_type
.bitfield
.reg32
9377 || r
->reg_type
.bitfield
.sreg3
9378 || r
->reg_type
.bitfield
.control
9379 || r
->reg_type
.bitfield
.debug
9380 || r
->reg_type
.bitfield
.test
)
9381 && !cpu_arch_flags
.bitfield
.cpui386
)
9382 return (const reg_entry
*) NULL
;
9384 if (r
->reg_type
.bitfield
.floatreg
9385 && !cpu_arch_flags
.bitfield
.cpu8087
9386 && !cpu_arch_flags
.bitfield
.cpu287
9387 && !cpu_arch_flags
.bitfield
.cpu387
)
9388 return (const reg_entry
*) NULL
;
9390 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9391 return (const reg_entry
*) NULL
;
9393 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9394 return (const reg_entry
*) NULL
;
9396 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9397 return (const reg_entry
*) NULL
;
9399 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9400 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9401 return (const reg_entry
*) NULL
;
9403 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9404 if (!allow_index_reg
9405 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9406 return (const reg_entry
*) NULL
;
9408 /* Upper 16 vector register is only available with VREX in 64bit
9410 if ((r
->reg_flags
& RegVRex
))
9412 if (!cpu_arch_flags
.bitfield
.cpuvrex
9413 || flag_code
!= CODE_64BIT
)
9414 return (const reg_entry
*) NULL
;
9419 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9420 || r
->reg_type
.bitfield
.reg64
)
9421 && (!cpu_arch_flags
.bitfield
.cpulm
9422 || !operand_type_equal (&r
->reg_type
, &control
))
9423 && flag_code
!= CODE_64BIT
)
9424 return (const reg_entry
*) NULL
;
9426 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9427 return (const reg_entry
*) NULL
;
9432 /* REG_STRING starts *before* REGISTER_PREFIX. */
9434 static const reg_entry
*
9435 parse_register (char *reg_string
, char **end_op
)
9439 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9440 r
= parse_real_register (reg_string
, end_op
);
9445 char *save
= input_line_pointer
;
9449 input_line_pointer
= reg_string
;
9450 c
= get_symbol_end ();
9451 symbolP
= symbol_find (reg_string
);
9452 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9454 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9456 know (e
->X_op
== O_register
);
9457 know (e
->X_add_number
>= 0
9458 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9459 r
= i386_regtab
+ e
->X_add_number
;
9460 if ((r
->reg_flags
& RegVRex
))
9462 *end_op
= input_line_pointer
;
9464 *input_line_pointer
= c
;
9465 input_line_pointer
= save
;
9471 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9474 char *end
= input_line_pointer
;
9477 r
= parse_register (name
, &input_line_pointer
);
9478 if (r
&& end
<= input_line_pointer
)
9480 *nextcharP
= *input_line_pointer
;
9481 *input_line_pointer
= 0;
9482 e
->X_op
= O_register
;
9483 e
->X_add_number
= r
- i386_regtab
;
9486 input_line_pointer
= end
;
9488 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9492 md_operand (expressionS
*e
)
9497 switch (*input_line_pointer
)
9499 case REGISTER_PREFIX
:
9500 r
= parse_real_register (input_line_pointer
, &end
);
9503 e
->X_op
= O_register
;
9504 e
->X_add_number
= r
- i386_regtab
;
9505 input_line_pointer
= end
;
9510 gas_assert (intel_syntax
);
9511 end
= input_line_pointer
++;
9513 if (*input_line_pointer
== ']')
9515 ++input_line_pointer
;
9516 e
->X_op_symbol
= make_expr_symbol (e
);
9517 e
->X_add_symbol
= NULL
;
9518 e
->X_add_number
= 0;
9524 input_line_pointer
= end
;
9531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9532 const char *md_shortopts
= "kVQ:sqn";
9534 const char *md_shortopts
= "qn";
9537 #define OPTION_32 (OPTION_MD_BASE + 0)
9538 #define OPTION_64 (OPTION_MD_BASE + 1)
9539 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9540 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9541 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9542 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9543 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9544 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9545 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9546 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9547 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9548 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9549 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9550 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9551 #define OPTION_X32 (OPTION_MD_BASE + 14)
9552 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9553 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9554 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9555 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9556 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9557 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9559 struct option md_longopts
[] =
9561 {"32", no_argument
, NULL
, OPTION_32
},
9562 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9563 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9564 {"64", no_argument
, NULL
, OPTION_64
},
9566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9567 {"x32", no_argument
, NULL
, OPTION_X32
},
9569 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9570 {"march", required_argument
, NULL
, OPTION_MARCH
},
9571 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9572 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9573 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9574 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9575 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9576 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9577 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9578 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9579 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9580 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9581 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9582 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9583 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9584 # if defined (TE_PE) || defined (TE_PEP)
9585 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9587 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9588 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9589 {NULL
, no_argument
, NULL
, 0}
9591 size_t md_longopts_size
= sizeof (md_longopts
);
9594 md_parse_option (int c
, char *arg
)
9602 optimize_align_code
= 0;
9609 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9610 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9611 should be emitted or not. FIXME: Not implemented. */
9615 /* -V: SVR4 argument to print version ID. */
9617 print_version_id ();
9620 /* -k: Ignore for FreeBSD compatibility. */
9625 /* -s: On i386 Solaris, this tells the native assembler to use
9626 .stab instead of .stab.excl. We always use .stab anyhow. */
9629 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9630 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9633 const char **list
, **l
;
9635 list
= bfd_target_list ();
9636 for (l
= list
; *l
!= NULL
; l
++)
9637 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9638 || strcmp (*l
, "coff-x86-64") == 0
9639 || strcmp (*l
, "pe-x86-64") == 0
9640 || strcmp (*l
, "pei-x86-64") == 0
9641 || strcmp (*l
, "mach-o-x86-64") == 0)
9643 default_arch
= "x86_64";
9647 as_fatal (_("no compiled in support for x86_64"));
9653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9657 const char **list
, **l
;
9659 list
= bfd_target_list ();
9660 for (l
= list
; *l
!= NULL
; l
++)
9661 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9663 default_arch
= "x86_64:32";
9667 as_fatal (_("no compiled in support for 32bit x86_64"));
9671 as_fatal (_("32bit x86_64 is only supported for ELF"));
9676 default_arch
= "i386";
9680 #ifdef SVR4_COMMENT_CHARS
9685 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9687 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9691 i386_comment_chars
= n
;
9697 arch
= xstrdup (arg
);
9701 as_fatal (_("invalid -march= option: `%s'"), arg
);
9702 next
= strchr (arch
, '+');
9705 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9707 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9710 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9713 cpu_arch_name
= cpu_arch
[j
].name
;
9714 cpu_sub_arch_name
= NULL
;
9715 cpu_arch_flags
= cpu_arch
[j
].flags
;
9716 cpu_arch_isa
= cpu_arch
[j
].type
;
9717 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9718 if (!cpu_arch_tune_set
)
9720 cpu_arch_tune
= cpu_arch_isa
;
9721 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9725 else if (*cpu_arch
[j
].name
== '.'
9726 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9728 /* ISA entension. */
9729 i386_cpu_flags flags
;
9731 if (!cpu_arch
[j
].negated
)
9732 flags
= cpu_flags_or (cpu_arch_flags
,
9735 flags
= cpu_flags_and_not (cpu_arch_flags
,
9737 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9739 if (cpu_sub_arch_name
)
9741 char *name
= cpu_sub_arch_name
;
9742 cpu_sub_arch_name
= concat (name
,
9744 (const char *) NULL
);
9748 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9749 cpu_arch_flags
= flags
;
9750 cpu_arch_isa_flags
= flags
;
9756 if (j
>= ARRAY_SIZE (cpu_arch
))
9757 as_fatal (_("invalid -march= option: `%s'"), arg
);
9761 while (next
!= NULL
);
9766 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9767 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9769 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9771 cpu_arch_tune_set
= 1;
9772 cpu_arch_tune
= cpu_arch
[j
].type
;
9773 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9777 if (j
>= ARRAY_SIZE (cpu_arch
))
9778 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9781 case OPTION_MMNEMONIC
:
9782 if (strcasecmp (arg
, "att") == 0)
9784 else if (strcasecmp (arg
, "intel") == 0)
9787 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9790 case OPTION_MSYNTAX
:
9791 if (strcasecmp (arg
, "att") == 0)
9793 else if (strcasecmp (arg
, "intel") == 0)
9796 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9799 case OPTION_MINDEX_REG
:
9800 allow_index_reg
= 1;
9803 case OPTION_MNAKED_REG
:
9804 allow_naked_reg
= 1;
9807 case OPTION_MOLD_GCC
:
9811 case OPTION_MSSE2AVX
:
9815 case OPTION_MSSE_CHECK
:
9816 if (strcasecmp (arg
, "error") == 0)
9817 sse_check
= check_error
;
9818 else if (strcasecmp (arg
, "warning") == 0)
9819 sse_check
= check_warning
;
9820 else if (strcasecmp (arg
, "none") == 0)
9821 sse_check
= check_none
;
9823 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9826 case OPTION_MOPERAND_CHECK
:
9827 if (strcasecmp (arg
, "error") == 0)
9828 operand_check
= check_error
;
9829 else if (strcasecmp (arg
, "warning") == 0)
9830 operand_check
= check_warning
;
9831 else if (strcasecmp (arg
, "none") == 0)
9832 operand_check
= check_none
;
9834 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9837 case OPTION_MAVXSCALAR
:
9838 if (strcasecmp (arg
, "128") == 0)
9840 else if (strcasecmp (arg
, "256") == 0)
9843 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9846 case OPTION_MADD_BND_PREFIX
:
9850 case OPTION_MEVEXLIG
:
9851 if (strcmp (arg
, "128") == 0)
9853 else if (strcmp (arg
, "256") == 0)
9855 else if (strcmp (arg
, "512") == 0)
9858 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9861 case OPTION_MEVEXRCIG
:
9862 if (strcmp (arg
, "rne") == 0)
9864 else if (strcmp (arg
, "rd") == 0)
9866 else if (strcmp (arg
, "ru") == 0)
9868 else if (strcmp (arg
, "rz") == 0)
9871 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9874 case OPTION_MEVEXWIG
:
9875 if (strcmp (arg
, "0") == 0)
9877 else if (strcmp (arg
, "1") == 0)
9880 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9883 # if defined (TE_PE) || defined (TE_PEP)
9884 case OPTION_MBIG_OBJ
:
9889 case OPTION_OMIT_LOCK_PREFIX
:
9890 if (strcasecmp (arg
, "yes") == 0)
9891 omit_lock_prefix
= 1;
9892 else if (strcasecmp (arg
, "no") == 0)
9893 omit_lock_prefix
= 0;
9895 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9904 #define MESSAGE_TEMPLATE \
9908 show_arch (FILE *stream
, int ext
, int check
)
9910 static char message
[] = MESSAGE_TEMPLATE
;
9911 char *start
= message
+ 27;
9913 int size
= sizeof (MESSAGE_TEMPLATE
);
9920 left
= size
- (start
- message
);
9921 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9923 /* Should it be skipped? */
9924 if (cpu_arch
[j
].skip
)
9927 name
= cpu_arch
[j
].name
;
9928 len
= cpu_arch
[j
].len
;
9931 /* It is an extension. Skip if we aren't asked to show it. */
9942 /* It is an processor. Skip if we show only extension. */
9945 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9947 /* It is an impossible processor - skip. */
9951 /* Reserve 2 spaces for ", " or ",\0" */
9954 /* Check if there is any room. */
9962 p
= mempcpy (p
, name
, len
);
9966 /* Output the current message now and start a new one. */
9969 fprintf (stream
, "%s\n", message
);
9971 left
= size
- (start
- message
) - len
- 2;
9973 gas_assert (left
>= 0);
9975 p
= mempcpy (p
, name
, len
);
9980 fprintf (stream
, "%s\n", message
);
9984 md_show_usage (FILE *stream
)
9986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 fprintf (stream
, _("\
9989 -V print assembler version number\n\
9992 fprintf (stream
, _("\
9993 -n Do not optimize code alignment\n\
9994 -q quieten some warnings\n"));
9995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9996 fprintf (stream
, _("\
9999 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10000 || defined (TE_PE) || defined (TE_PEP))
10001 fprintf (stream
, _("\
10002 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10004 #ifdef SVR4_COMMENT_CHARS
10005 fprintf (stream
, _("\
10006 --divide do not treat `/' as a comment character\n"));
10008 fprintf (stream
, _("\
10009 --divide ignored\n"));
10011 fprintf (stream
, _("\
10012 -march=CPU[,+EXTENSION...]\n\
10013 generate code for CPU and EXTENSION, CPU is one of:\n"));
10014 show_arch (stream
, 0, 1);
10015 fprintf (stream
, _("\
10016 EXTENSION is combination of:\n"));
10017 show_arch (stream
, 1, 0);
10018 fprintf (stream
, _("\
10019 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10020 show_arch (stream
, 0, 0);
10021 fprintf (stream
, _("\
10022 -msse2avx encode SSE instructions with VEX prefix\n"));
10023 fprintf (stream
, _("\
10024 -msse-check=[none|error|warning]\n\
10025 check SSE instructions\n"));
10026 fprintf (stream
, _("\
10027 -moperand-check=[none|error|warning]\n\
10028 check operand combinations for validity\n"));
10029 fprintf (stream
, _("\
10030 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10032 fprintf (stream
, _("\
10033 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10035 fprintf (stream
, _("\
10036 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10037 for EVEX.W bit ignored instructions\n"));
10038 fprintf (stream
, _("\
10039 -mevexrcig=[rne|rd|ru|rz]\n\
10040 encode EVEX instructions with specific EVEX.RC value\n\
10041 for SAE-only ignored instructions\n"));
10042 fprintf (stream
, _("\
10043 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10044 fprintf (stream
, _("\
10045 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10046 fprintf (stream
, _("\
10047 -mindex-reg support pseudo index registers\n"));
10048 fprintf (stream
, _("\
10049 -mnaked-reg don't require `%%' prefix for registers\n"));
10050 fprintf (stream
, _("\
10051 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10052 fprintf (stream
, _("\
10053 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10054 # if defined (TE_PE) || defined (TE_PEP)
10055 fprintf (stream
, _("\
10056 -mbig-obj generate big object files\n"));
10058 fprintf (stream
, _("\
10059 -momit-lock-prefix=[no|yes]\n\
10060 strip all lock prefixes\n"));
10063 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10064 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10065 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10067 /* Pick the target format to use. */
10070 i386_target_format (void)
10072 if (!strncmp (default_arch
, "x86_64", 6))
10074 update_code_flag (CODE_64BIT
, 1);
10075 if (default_arch
[6] == '\0')
10076 x86_elf_abi
= X86_64_ABI
;
10078 x86_elf_abi
= X86_64_X32_ABI
;
10080 else if (!strcmp (default_arch
, "i386"))
10081 update_code_flag (CODE_32BIT
, 1);
10083 as_fatal (_("unknown architecture"));
10085 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10086 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10087 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10088 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10090 switch (OUTPUT_FLAVOR
)
10092 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10093 case bfd_target_aout_flavour
:
10094 return AOUT_TARGET_FORMAT
;
10096 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10097 # if defined (TE_PE) || defined (TE_PEP)
10098 case bfd_target_coff_flavour
:
10099 if (flag_code
== CODE_64BIT
)
10100 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10103 # elif defined (TE_GO32)
10104 case bfd_target_coff_flavour
:
10105 return "coff-go32";
10107 case bfd_target_coff_flavour
:
10108 return "coff-i386";
10111 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10112 case bfd_target_elf_flavour
:
10114 const char *format
;
10116 switch (x86_elf_abi
)
10119 format
= ELF_TARGET_FORMAT
;
10122 use_rela_relocations
= 1;
10124 format
= ELF_TARGET_FORMAT64
;
10126 case X86_64_X32_ABI
:
10127 use_rela_relocations
= 1;
10129 disallow_64bit_reloc
= 1;
10130 format
= ELF_TARGET_FORMAT32
;
10133 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10135 if (x86_elf_abi
!= X86_64_ABI
)
10136 as_fatal (_("Intel L1OM is 64bit only"));
10137 return ELF_TARGET_L1OM_FORMAT
;
10139 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10141 if (x86_elf_abi
!= X86_64_ABI
)
10142 as_fatal (_("Intel K1OM is 64bit only"));
10143 return ELF_TARGET_K1OM_FORMAT
;
10149 #if defined (OBJ_MACH_O)
10150 case bfd_target_mach_o_flavour
:
10151 if (flag_code
== CODE_64BIT
)
10153 use_rela_relocations
= 1;
10155 return "mach-o-x86-64";
10158 return "mach-o-i386";
10166 #endif /* OBJ_MAYBE_ more than one */
10168 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10170 i386_elf_emit_arch_note (void)
10172 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10175 asection
*seg
= now_seg
;
10176 subsegT subseg
= now_subseg
;
10177 Elf_Internal_Note i_note
;
10178 Elf_External_Note e_note
;
10179 asection
*note_secp
;
10182 /* Create the .note section. */
10183 note_secp
= subseg_new (".note", 0);
10184 bfd_set_section_flags (stdoutput
,
10186 SEC_HAS_CONTENTS
| SEC_READONLY
);
10188 /* Process the arch string. */
10189 len
= strlen (cpu_arch_name
);
10191 i_note
.namesz
= len
+ 1;
10193 i_note
.type
= NT_ARCH
;
10194 p
= frag_more (sizeof (e_note
.namesz
));
10195 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10196 p
= frag_more (sizeof (e_note
.descsz
));
10197 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10198 p
= frag_more (sizeof (e_note
.type
));
10199 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10200 p
= frag_more (len
+ 1);
10201 strcpy (p
, cpu_arch_name
);
10203 frag_align (2, 0, 0);
10205 subseg_set (seg
, subseg
);
10211 md_undefined_symbol (char *name
)
10213 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10214 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10215 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10216 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10220 if (symbol_find (name
))
10221 as_bad (_("GOT already in symbol table"));
10222 GOT_symbol
= symbol_new (name
, undefined_section
,
10223 (valueT
) 0, &zero_address_frag
);
10230 /* Round up a section size to the appropriate boundary. */
10233 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10235 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10236 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10238 /* For a.out, force the section size to be aligned. If we don't do
10239 this, BFD will align it for us, but it will not write out the
10240 final bytes of the section. This may be a bug in BFD, but it is
10241 easier to fix it here since that is how the other a.out targets
10245 align
= bfd_get_section_alignment (stdoutput
, segment
);
10246 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10253 /* On the i386, PC-relative offsets are relative to the start of the
10254 next instruction. That is, the address of the offset, plus its
10255 size, since the offset is always the last part of the insn. */
10258 md_pcrel_from (fixS
*fixP
)
10260 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10266 s_bss (int ignore ATTRIBUTE_UNUSED
)
10270 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10272 obj_elf_section_change_hook ();
10274 temp
= get_absolute_expression ();
10275 subseg_set (bss_section
, (subsegT
) temp
);
10276 demand_empty_rest_of_line ();
10282 i386_validate_fix (fixS
*fixp
)
10284 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10286 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10290 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10295 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10297 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10299 fixp
->fx_subsy
= 0;
10304 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10307 bfd_reloc_code_real_type code
;
10309 switch (fixp
->fx_r_type
)
10311 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10312 case BFD_RELOC_SIZE32
:
10313 case BFD_RELOC_SIZE64
:
10314 if (S_IS_DEFINED (fixp
->fx_addsy
)
10315 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10317 /* Resolve size relocation against local symbol to size of
10318 the symbol plus addend. */
10319 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10320 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10321 && !fits_in_unsigned_long (value
))
10322 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10323 _("symbol size computation overflow"));
10324 fixp
->fx_addsy
= NULL
;
10325 fixp
->fx_subsy
= NULL
;
10326 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10331 case BFD_RELOC_X86_64_PLT32
:
10332 case BFD_RELOC_X86_64_GOT32
:
10333 case BFD_RELOC_X86_64_GOTPCREL
:
10334 case BFD_RELOC_386_PLT32
:
10335 case BFD_RELOC_386_GOT32
:
10336 case BFD_RELOC_386_GOTOFF
:
10337 case BFD_RELOC_386_GOTPC
:
10338 case BFD_RELOC_386_TLS_GD
:
10339 case BFD_RELOC_386_TLS_LDM
:
10340 case BFD_RELOC_386_TLS_LDO_32
:
10341 case BFD_RELOC_386_TLS_IE_32
:
10342 case BFD_RELOC_386_TLS_IE
:
10343 case BFD_RELOC_386_TLS_GOTIE
:
10344 case BFD_RELOC_386_TLS_LE_32
:
10345 case BFD_RELOC_386_TLS_LE
:
10346 case BFD_RELOC_386_TLS_GOTDESC
:
10347 case BFD_RELOC_386_TLS_DESC_CALL
:
10348 case BFD_RELOC_X86_64_TLSGD
:
10349 case BFD_RELOC_X86_64_TLSLD
:
10350 case BFD_RELOC_X86_64_DTPOFF32
:
10351 case BFD_RELOC_X86_64_DTPOFF64
:
10352 case BFD_RELOC_X86_64_GOTTPOFF
:
10353 case BFD_RELOC_X86_64_TPOFF32
:
10354 case BFD_RELOC_X86_64_TPOFF64
:
10355 case BFD_RELOC_X86_64_GOTOFF64
:
10356 case BFD_RELOC_X86_64_GOTPC32
:
10357 case BFD_RELOC_X86_64_GOT64
:
10358 case BFD_RELOC_X86_64_GOTPCREL64
:
10359 case BFD_RELOC_X86_64_GOTPC64
:
10360 case BFD_RELOC_X86_64_GOTPLT64
:
10361 case BFD_RELOC_X86_64_PLTOFF64
:
10362 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10363 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10364 case BFD_RELOC_RVA
:
10365 case BFD_RELOC_VTABLE_ENTRY
:
10366 case BFD_RELOC_VTABLE_INHERIT
:
10368 case BFD_RELOC_32_SECREL
:
10370 code
= fixp
->fx_r_type
;
10372 case BFD_RELOC_X86_64_32S
:
10373 if (!fixp
->fx_pcrel
)
10375 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10376 code
= fixp
->fx_r_type
;
10380 if (fixp
->fx_pcrel
)
10382 switch (fixp
->fx_size
)
10385 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10386 _("can not do %d byte pc-relative relocation"),
10388 code
= BFD_RELOC_32_PCREL
;
10390 case 1: code
= BFD_RELOC_8_PCREL
; break;
10391 case 2: code
= BFD_RELOC_16_PCREL
; break;
10392 case 4: code
= BFD_RELOC_32_PCREL
; break;
10394 case 8: code
= BFD_RELOC_64_PCREL
; break;
10400 switch (fixp
->fx_size
)
10403 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10404 _("can not do %d byte relocation"),
10406 code
= BFD_RELOC_32
;
10408 case 1: code
= BFD_RELOC_8
; break;
10409 case 2: code
= BFD_RELOC_16
; break;
10410 case 4: code
= BFD_RELOC_32
; break;
10412 case 8: code
= BFD_RELOC_64
; break;
10419 if ((code
== BFD_RELOC_32
10420 || code
== BFD_RELOC_32_PCREL
10421 || code
== BFD_RELOC_X86_64_32S
)
10423 && fixp
->fx_addsy
== GOT_symbol
)
10426 code
= BFD_RELOC_386_GOTPC
;
10428 code
= BFD_RELOC_X86_64_GOTPC32
;
10430 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10432 && fixp
->fx_addsy
== GOT_symbol
)
10434 code
= BFD_RELOC_X86_64_GOTPC64
;
10437 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10438 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10439 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10441 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10443 if (!use_rela_relocations
)
10445 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10446 vtable entry to be used in the relocation's section offset. */
10447 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10448 rel
->address
= fixp
->fx_offset
;
10449 #if defined (OBJ_COFF) && defined (TE_PE)
10450 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10451 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10456 /* Use the rela in 64bit mode. */
10459 if (disallow_64bit_reloc
)
10462 case BFD_RELOC_X86_64_DTPOFF64
:
10463 case BFD_RELOC_X86_64_TPOFF64
:
10464 case BFD_RELOC_64_PCREL
:
10465 case BFD_RELOC_X86_64_GOTOFF64
:
10466 case BFD_RELOC_X86_64_GOT64
:
10467 case BFD_RELOC_X86_64_GOTPCREL64
:
10468 case BFD_RELOC_X86_64_GOTPC64
:
10469 case BFD_RELOC_X86_64_GOTPLT64
:
10470 case BFD_RELOC_X86_64_PLTOFF64
:
10471 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10472 _("cannot represent relocation type %s in x32 mode"),
10473 bfd_get_reloc_code_name (code
));
10479 if (!fixp
->fx_pcrel
)
10480 rel
->addend
= fixp
->fx_offset
;
10484 case BFD_RELOC_X86_64_PLT32
:
10485 case BFD_RELOC_X86_64_GOT32
:
10486 case BFD_RELOC_X86_64_GOTPCREL
:
10487 case BFD_RELOC_X86_64_TLSGD
:
10488 case BFD_RELOC_X86_64_TLSLD
:
10489 case BFD_RELOC_X86_64_GOTTPOFF
:
10490 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10491 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10492 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10495 rel
->addend
= (section
->vma
10497 + fixp
->fx_addnumber
10498 + md_pcrel_from (fixp
));
10503 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10504 if (rel
->howto
== NULL
)
10506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10507 _("cannot represent relocation type %s"),
10508 bfd_get_reloc_code_name (code
));
10509 /* Set howto to a garbage value so that we can keep going. */
10510 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10511 gas_assert (rel
->howto
!= NULL
);
10517 #include "tc-i386-intel.c"
10520 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10522 int saved_naked_reg
;
10523 char saved_register_dot
;
10525 saved_naked_reg
= allow_naked_reg
;
10526 allow_naked_reg
= 1;
10527 saved_register_dot
= register_chars
['.'];
10528 register_chars
['.'] = '.';
10529 allow_pseudo_reg
= 1;
10530 expression_and_evaluate (exp
);
10531 allow_pseudo_reg
= 0;
10532 register_chars
['.'] = saved_register_dot
;
10533 allow_naked_reg
= saved_naked_reg
;
10535 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10537 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10539 exp
->X_op
= O_constant
;
10540 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10541 .dw2_regnum
[flag_code
>> 1];
10544 exp
->X_op
= O_illegal
;
10549 tc_x86_frame_initial_instructions (void)
10551 static unsigned int sp_regno
[2];
10553 if (!sp_regno
[flag_code
>> 1])
10555 char *saved_input
= input_line_pointer
;
10556 char sp
[][4] = {"esp", "rsp"};
10559 input_line_pointer
= sp
[flag_code
>> 1];
10560 tc_x86_parse_to_dw2regnum (&exp
);
10561 gas_assert (exp
.X_op
== O_constant
);
10562 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10563 input_line_pointer
= saved_input
;
10566 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10567 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10571 x86_dwarf2_addr_size (void)
10573 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10574 if (x86_elf_abi
== X86_64_X32_ABI
)
10577 return bfd_arch_bits_per_address (stdoutput
) / 8;
10581 i386_elf_section_type (const char *str
, size_t len
)
10583 if (flag_code
== CODE_64BIT
10584 && len
== sizeof ("unwind") - 1
10585 && strncmp (str
, "unwind", 6) == 0)
10586 return SHT_X86_64_UNWIND
;
10593 i386_solaris_fix_up_eh_frame (segT sec
)
10595 if (flag_code
== CODE_64BIT
)
10596 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10602 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10606 exp
.X_op
= O_secrel
;
10607 exp
.X_add_symbol
= symbol
;
10608 exp
.X_add_number
= 0;
10609 emit_expr (&exp
, size
);
10613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10614 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10617 x86_64_section_letter (int letter
, char **ptr_msg
)
10619 if (flag_code
== CODE_64BIT
)
10622 return SHF_X86_64_LARGE
;
10624 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10627 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10632 x86_64_section_word (char *str
, size_t len
)
10634 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10635 return SHF_X86_64_LARGE
;
10641 handle_large_common (int small ATTRIBUTE_UNUSED
)
10643 if (flag_code
!= CODE_64BIT
)
10645 s_comm_internal (0, elf_common_parse
);
10646 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10650 static segT lbss_section
;
10651 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10652 asection
*saved_bss_section
= bss_section
;
10654 if (lbss_section
== NULL
)
10656 flagword applicable
;
10657 segT seg
= now_seg
;
10658 subsegT subseg
= now_subseg
;
10660 /* The .lbss section is for local .largecomm symbols. */
10661 lbss_section
= subseg_new (".lbss", 0);
10662 applicable
= bfd_applicable_section_flags (stdoutput
);
10663 bfd_set_section_flags (stdoutput
, lbss_section
,
10664 applicable
& SEC_ALLOC
);
10665 seg_info (lbss_section
)->bss
= 1;
10667 subseg_set (seg
, subseg
);
10670 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10671 bss_section
= lbss_section
;
10673 s_comm_internal (0, elf_common_parse
);
10675 elf_com_section_ptr
= saved_com_section_ptr
;
10676 bss_section
= saved_bss_section
;
10679 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */