1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "opcode/i386.h"
33 #ifndef REGISTER_WARNINGS
34 #define REGISTER_WARNINGS 1
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
41 #ifndef SCALE1_WHEN_NO_INDEX
42 /* Specifying a scale factor besides 1 when there is no index is
43 futile. eg. `mov (%ebx,2),%al' does exactly the same as
44 `mov (%ebx),%al'. To slavishly follow what the programmer
45 specified, set SCALE1_WHEN_NO_INDEX to 0. */
46 #define SCALE1_WHEN_NO_INDEX 1
52 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
53 static int fits_in_signed_byte
PARAMS ((offsetT
));
54 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_word
PARAMS ((offsetT
));
56 static int fits_in_signed_word
PARAMS ((offsetT
));
57 static int smallest_imm_type
PARAMS ((offsetT
));
58 static offsetT offset_in_range
PARAMS ((offsetT
, int));
59 static int add_prefix
PARAMS ((unsigned int));
60 static void set_16bit_code_flag
PARAMS ((int));
61 static void set_16bit_gcc_code_flag
PARAMS ((int));
62 static void set_intel_syntax
PARAMS ((int));
63 static void set_cpu_arch
PARAMS ((int));
66 static bfd_reloc_code_real_type reloc
67 PARAMS ((int, int, bfd_reloc_code_real_type
));
70 /* 'md_assemble ()' gathers together information and puts it into a
77 const reg_entry
*regs
;
82 /* TM holds the template for the insn were currently assembling. */
85 /* SUFFIX holds the instruction mnemonic suffix if given.
86 (e.g. 'l' for 'movl') */
89 /* OPERANDS gives the number of given operands. */
90 unsigned int operands
;
92 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
93 of given register, displacement, memory operands and immediate
95 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
97 /* TYPES [i] is the type (see above #defines) which tells us how to
98 use OP[i] for the corresponding operand. */
99 unsigned int types
[MAX_OPERANDS
];
101 /* Displacement expression, immediate expression, or register for each
103 union i386_op op
[MAX_OPERANDS
];
105 /* Relocation type for operand */
107 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
109 int disp_reloc
[MAX_OPERANDS
];
112 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
113 the base index byte below. */
114 const reg_entry
*base_reg
;
115 const reg_entry
*index_reg
;
116 unsigned int log2_scale_factor
;
118 /* SEG gives the seg_entries of this insn. They are zero unless
119 explicit segment overrides are given. */
120 const seg_entry
*seg
[2];
122 /* PREFIX holds all the given prefix opcodes (usually null).
123 PREFIXES is the number of prefix opcodes. */
124 unsigned int prefixes
;
125 unsigned char prefix
[MAX_PREFIXES
];
127 /* RM and SIB are the modrm byte and the sib byte where the
128 addressing modes of this insn are encoded. */
134 typedef struct _i386_insn i386_insn
;
136 /* List of chars besides those in app.c:symbol_chars that can start an
137 operand. Used to prevent the scrubber eating vital white-space. */
139 const char extra_symbol_chars
[] = "*%-(@";
141 const char extra_symbol_chars
[] = "*%-(";
144 /* This array holds the chars that always start a comment. If the
145 pre-processor is disabled, these aren't very useful. */
146 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
147 /* Putting '/' here makes it impossible to use the divide operator.
148 However, we need it for compatibility with SVR4 systems. */
149 const char comment_chars
[] = "#/";
150 #define PREFIX_SEPARATOR '\\'
152 const char comment_chars
[] = "#";
153 #define PREFIX_SEPARATOR '/'
156 /* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output.
159 Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output.
162 Also note that comments started like this one will always work if
163 '/' isn't otherwise defined. */
164 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165 const char line_comment_chars
[] = "";
167 const char line_comment_chars
[] = "/";
170 const char line_separator_chars
[] = ";";
172 /* Chars that can be used to separate mant from exp in floating point
174 const char EXP_CHARS
[] = "eE";
176 /* Chars that mean this number is a floating point constant
179 const char FLT_CHARS
[] = "fFdDxX";
181 /* Tables for lexical analysis. */
182 static char mnemonic_chars
[256];
183 static char register_chars
[256];
184 static char operand_chars
[256];
185 static char identifier_chars
[256];
186 static char digit_chars
[256];
188 /* Lexical macros. */
189 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
190 #define is_operand_char(x) (operand_chars[(unsigned char) x])
191 #define is_register_char(x) (register_chars[(unsigned char) x])
192 #define is_space_char(x) ((x) == ' ')
193 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
194 #define is_digit_char(x) (digit_chars[(unsigned char) x])
196 /* All non-digit non-letter charcters that may occur in an operand. */
197 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
199 /* md_assemble() always leaves the strings it's passed unaltered. To
200 effect this we maintain a stack of saved characters that we've smashed
201 with '\0's (indicating end of strings for various sub-fields of the
202 assembler instruction). */
203 static char save_stack
[32];
204 static char *save_stack_p
;
205 #define END_STRING_AND_SAVE(s) \
206 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
207 #define RESTORE_END_STRING(s) \
208 do { *(s) = *--save_stack_p; } while (0)
210 /* The instruction we're assembling. */
213 /* Possible templates for current insn. */
214 static const templates
*current_templates
;
216 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
217 static expressionS disp_expressions
[2], im_expressions
[2];
219 /* Current operand we are working on. */
220 static int this_operand
;
222 /* 1 if we're writing 16-bit code,
224 static int flag_16bit_code
;
226 /* 1 for intel syntax,
228 static int intel_syntax
= 0;
230 /* 1 if register prefix % not required. */
231 static int allow_naked_reg
= 0;
233 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
234 leave, push, and pop instructions so that gcc has the same stack
235 frame as in 32 bit mode. */
236 static char stackop_size
= '\0';
238 /* Non-zero to quieten some warnings. */
239 static int quiet_warnings
= 0;
242 static const char *cpu_arch_name
= NULL
;
244 /* CPU feature flags. */
245 static unsigned int cpu_arch_flags
= 0;
247 /* Interface to relax_segment.
248 There are 2 relax states for 386 jump insns: one for conditional &
249 one for unconditional jumps. This is because these two types of
250 jumps add different sizes to frags when we're figuring out what
251 sort of jump to choose to reach a given label. */
255 #define UNCOND_JUMP 2
259 #define SMALL16 (SMALL|CODE16)
261 #define BIG16 (BIG|CODE16)
265 #define INLINE __inline__
271 #define ENCODE_RELAX_STATE(type,size) \
272 ((relax_substateT)((type<<2) | (size)))
273 #define SIZE_FROM_RELAX_STATE(s) \
274 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
276 /* This table is used by relax_frag to promote short jumps to long
277 ones where necessary. SMALL (short) jumps may be promoted to BIG
278 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
279 don't allow a short jump in a 32 bit code segment to be promoted to
280 a 16 bit offset jump because it's slower (requires data size
281 prefix), and doesn't work, unless the destination is in the bottom
282 64k of the code segment (The top 16 bits of eip are zeroed). */
284 const relax_typeS md_relax_table
[] =
287 1) most positive reach of this state,
288 2) most negative reach of this state,
289 3) how many bytes this mode will add to the size of the current frag
290 4) which index into the table to try if we can't fit into this one. */
296 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
298 /* dword conditionals adds 4 bytes to frag:
299 1 extra opcode byte, 3 extra displacement bytes. */
301 /* word conditionals add 2 bytes to frag:
302 1 extra opcode byte, 1 extra displacement byte. */
305 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
307 /* dword jmp adds 3 bytes to frag:
308 0 extra opcode bytes, 3 extra displacement bytes. */
310 /* word jmp adds 1 byte to frag:
311 0 extra opcode bytes, 1 extra displacement byte. */
316 static const arch_entry cpu_arch
[] = {
318 {"i186", Cpu086
|Cpu186
},
319 {"i286", Cpu086
|Cpu186
|Cpu286
},
320 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
321 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
322 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
323 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
324 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
325 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
326 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
327 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
332 i386_align_code (fragP
, count
)
336 /* Various efficient no-op patterns for aligning code labels.
337 Note: Don't try to assemble the instructions in the comments.
338 0L and 0w are not legal. */
339 static const char f32_1
[] =
341 static const char f32_2
[] =
342 {0x89,0xf6}; /* movl %esi,%esi */
343 static const char f32_3
[] =
344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
345 static const char f32_4
[] =
346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
347 static const char f32_5
[] =
349 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
350 static const char f32_6
[] =
351 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
352 static const char f32_7
[] =
353 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
354 static const char f32_8
[] =
356 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
357 static const char f32_9
[] =
358 {0x89,0xf6, /* movl %esi,%esi */
359 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
360 static const char f32_10
[] =
361 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
362 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
363 static const char f32_11
[] =
364 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
365 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
366 static const char f32_12
[] =
367 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
368 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
369 static const char f32_13
[] =
370 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
371 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
372 static const char f32_14
[] =
373 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
374 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
375 static const char f32_15
[] =
376 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
377 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
378 static const char f16_3
[] =
379 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
380 static const char f16_4
[] =
381 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
382 static const char f16_5
[] =
384 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
385 static const char f16_6
[] =
386 {0x89,0xf6, /* mov %si,%si */
387 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
388 static const char f16_7
[] =
389 {0x8d,0x74,0x00, /* lea 0(%si),%si */
390 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
391 static const char f16_8
[] =
392 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
393 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
394 static const char *const f32_patt
[] = {
395 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
396 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
398 static const char *const f16_patt
[] = {
399 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
400 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
403 if (count
> 0 && count
<= 15)
407 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
408 f16_patt
[count
- 1], count
);
410 /* Adjust jump offset. */
411 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
414 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
415 f32_patt
[count
- 1], count
);
416 fragP
->fr_var
= count
;
420 static char *output_invalid
PARAMS ((int c
));
421 static int i386_operand
PARAMS ((char *operand_string
));
422 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
423 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
427 static void s_bss
PARAMS ((int));
430 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
432 static INLINE
unsigned int
433 mode_from_disp_size (t
)
436 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
440 fits_in_signed_byte (num
)
443 return (num
>= -128) && (num
<= 127);
447 fits_in_unsigned_byte (num
)
450 return (num
& 0xff) == num
;
454 fits_in_unsigned_word (num
)
457 return (num
& 0xffff) == num
;
461 fits_in_signed_word (num
)
464 return (-32768 <= num
) && (num
<= 32767);
468 smallest_imm_type (num
)
471 if (cpu_arch_flags
!= 0
472 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
474 /* This code is disabled on the 486 because all the Imm1 forms
475 in the opcode table are slower on the i486. They're the
476 versions with the implicitly specified single-position
477 displacement, which has another syntax if you really want to
480 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
482 return (fits_in_signed_byte (num
)
483 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
484 : fits_in_unsigned_byte (num
)
485 ? (Imm8
| Imm16
| Imm32
)
486 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
492 offset_in_range (val
, size
)
500 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
501 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
502 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
506 /* If BFD64, sign extend val. */
507 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
508 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
510 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
512 char buf1
[40], buf2
[40];
514 sprint_value (buf1
, val
);
515 sprint_value (buf2
, val
& mask
);
516 as_warn (_("%s shortened to %s"), buf1
, buf2
);
521 /* Returns 0 if attempting to add a prefix where one from the same
522 class already exists, 1 if non rep/repne added, 2 if rep/repne
536 case CS_PREFIX_OPCODE
:
537 case DS_PREFIX_OPCODE
:
538 case ES_PREFIX_OPCODE
:
539 case FS_PREFIX_OPCODE
:
540 case GS_PREFIX_OPCODE
:
541 case SS_PREFIX_OPCODE
:
545 case REPNE_PREFIX_OPCODE
:
546 case REPE_PREFIX_OPCODE
:
549 case LOCK_PREFIX_OPCODE
:
557 case ADDR_PREFIX_OPCODE
:
561 case DATA_PREFIX_OPCODE
:
568 as_bad (_("same type of prefix used twice"));
573 i
.prefix
[q
] = prefix
;
578 set_16bit_code_flag (new_16bit_code_flag
)
579 int new_16bit_code_flag
;
581 flag_16bit_code
= new_16bit_code_flag
;
586 set_16bit_gcc_code_flag (new_16bit_code_flag
)
587 int new_16bit_code_flag
;
589 flag_16bit_code
= new_16bit_code_flag
;
590 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
594 set_intel_syntax (syntax_flag
)
597 /* Find out if register prefixing is specified. */
598 int ask_naked_reg
= 0;
601 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
603 char *string
= input_line_pointer
;
604 int e
= get_symbol_end ();
606 if (strcmp (string
, "prefix") == 0)
608 else if (strcmp (string
, "noprefix") == 0)
611 as_bad (_("bad argument to syntax directive."));
612 *input_line_pointer
= e
;
614 demand_empty_rest_of_line ();
616 intel_syntax
= syntax_flag
;
618 if (ask_naked_reg
== 0)
621 allow_naked_reg
= (intel_syntax
622 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
624 /* Conservative default. */
629 allow_naked_reg
= (ask_naked_reg
< 0);
634 int dummy ATTRIBUTE_UNUSED
;
638 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
640 char *string
= input_line_pointer
;
641 int e
= get_symbol_end ();
644 for (i
= 0; cpu_arch
[i
].name
; i
++)
646 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
648 cpu_arch_name
= cpu_arch
[i
].name
;
649 cpu_arch_flags
= cpu_arch
[i
].flags
;
653 if (!cpu_arch
[i
].name
)
654 as_bad (_("no such architecture: `%s'"), string
);
656 *input_line_pointer
= e
;
659 as_bad (_("missing cpu architecture"));
661 demand_empty_rest_of_line ();
664 const pseudo_typeS md_pseudo_table
[] =
666 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
667 {"align", s_align_bytes
, 0},
669 {"align", s_align_ptwo
, 0},
671 {"arch", set_cpu_arch
, 0},
675 {"ffloat", float_cons
, 'f'},
676 {"dfloat", float_cons
, 'd'},
677 {"tfloat", float_cons
, 'x'},
679 {"noopt", s_ignore
, 0},
680 {"optim", s_ignore
, 0},
681 {"code16gcc", set_16bit_gcc_code_flag
, 1},
682 {"code16", set_16bit_code_flag
, 1},
683 {"code32", set_16bit_code_flag
, 0},
684 {"intel_syntax", set_intel_syntax
, 1},
685 {"att_syntax", set_intel_syntax
, 0},
689 /* For interface with expression (). */
690 extern char *input_line_pointer
;
692 /* Hash table for instruction mnemonic lookup. */
693 static struct hash_control
*op_hash
;
695 /* Hash table for register lookup. */
696 static struct hash_control
*reg_hash
;
701 const char *hash_err
;
703 /* Initialize op_hash hash table. */
704 op_hash
= hash_new ();
707 register const template *optab
;
708 register templates
*core_optab
;
710 /* Setup for loop. */
712 core_optab
= (templates
*) xmalloc (sizeof (templates
));
713 core_optab
->start
= optab
;
718 if (optab
->name
== NULL
719 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
721 /* different name --> ship out current template list;
722 add to hash table; & begin anew. */
723 core_optab
->end
= optab
;
724 hash_err
= hash_insert (op_hash
,
730 as_fatal (_("Internal Error: Can't hash %s: %s"),
734 if (optab
->name
== NULL
)
736 core_optab
= (templates
*) xmalloc (sizeof (templates
));
737 core_optab
->start
= optab
;
742 /* Initialize reg_hash hash table. */
743 reg_hash
= hash_new ();
745 register const reg_entry
*regtab
;
747 for (regtab
= i386_regtab
;
748 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
751 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
757 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
762 for (c
= 0; c
< 256; c
++)
767 mnemonic_chars
[c
] = c
;
768 register_chars
[c
] = c
;
769 operand_chars
[c
] = c
;
771 else if (islower (c
))
773 mnemonic_chars
[c
] = c
;
774 register_chars
[c
] = c
;
775 operand_chars
[c
] = c
;
777 else if (isupper (c
))
779 mnemonic_chars
[c
] = tolower (c
);
780 register_chars
[c
] = mnemonic_chars
[c
];
781 operand_chars
[c
] = c
;
784 if (isalpha (c
) || isdigit (c
))
785 identifier_chars
[c
] = c
;
788 identifier_chars
[c
] = c
;
789 operand_chars
[c
] = c
;
794 identifier_chars
['@'] = '@';
796 digit_chars
['-'] = '-';
797 identifier_chars
['_'] = '_';
798 identifier_chars
['.'] = '.';
800 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
801 operand_chars
[(unsigned char) *p
] = *p
;
804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
805 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
807 record_alignment (text_section
, 2);
808 record_alignment (data_section
, 2);
809 record_alignment (bss_section
, 2);
815 i386_print_statistics (file
)
818 hash_print_statistics (file
, "i386 opcode", op_hash
);
819 hash_print_statistics (file
, "i386 register", reg_hash
);
824 /* Debugging routines for md_assemble. */
825 static void pi
PARAMS ((char *, i386_insn
*));
826 static void pte
PARAMS ((template *));
827 static void pt
PARAMS ((unsigned int));
828 static void pe
PARAMS ((expressionS
*));
829 static void ps
PARAMS ((symbolS
*));
836 register template *p
;
839 fprintf (stdout
, "%s: template ", line
);
841 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
842 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
843 fprintf (stdout
, " base %x index %x scale %x\n",
844 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
845 for (i
= 0; i
< x
->operands
; i
++)
847 fprintf (stdout
, " #%d: ", i
+ 1);
849 fprintf (stdout
, "\n");
851 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
852 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
853 if (x
->types
[i
] & Imm
)
855 if (x
->types
[i
] & Disp
)
865 fprintf (stdout
, " %d operands ", t
->operands
);
866 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
867 if (t
->extension_opcode
!= None
)
868 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
869 if (t
->opcode_modifier
& D
)
870 fprintf (stdout
, "D");
871 if (t
->opcode_modifier
& W
)
872 fprintf (stdout
, "W");
873 fprintf (stdout
, "\n");
874 for (i
= 0; i
< t
->operands
; i
++)
876 fprintf (stdout
, " #%d type ", i
+ 1);
877 pt (t
->operand_types
[i
]);
878 fprintf (stdout
, "\n");
886 fprintf (stdout
, " operation %d\n", e
->X_op
);
887 fprintf (stdout
, " add_number %ld (%lx)\n",
888 (long) e
->X_add_number
, (long) e
->X_add_number
);
891 fprintf (stdout
, " add_symbol ");
892 ps (e
->X_add_symbol
);
893 fprintf (stdout
, "\n");
897 fprintf (stdout
, " op_symbol ");
899 fprintf (stdout
, "\n");
907 fprintf (stdout
, "%s type %s%s",
909 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
910 segment_name (S_GET_SEGMENT (s
)));
929 { BaseIndex
, "BaseIndex" },
933 { InOutPortReg
, "InOutPortReg" },
934 { ShiftCount
, "ShiftCount" },
935 { Control
, "control reg" },
936 { Test
, "test reg" },
937 { Debug
, "debug reg" },
938 { FloatReg
, "FReg" },
939 { FloatAcc
, "FAcc" },
943 { JumpAbsolute
, "Jump Absolute" },
954 register struct type_name
*ty
;
958 fprintf (stdout
, _("Unknown"));
962 for (ty
= type_names
; ty
->mask
; ty
++)
964 fprintf (stdout
, "%s, ", ty
->tname
);
969 #endif /* DEBUG386 */
972 tc_i386_force_relocation (fixp
)
976 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
977 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
982 return fixp
->fx_r_type
== 7;
987 static bfd_reloc_code_real_type reloc
988 PARAMS ((int, int, bfd_reloc_code_real_type
));
990 static bfd_reloc_code_real_type
991 reloc (size
, pcrel
, other
)
994 bfd_reloc_code_real_type other
;
996 if (other
!= NO_RELOC
)
1003 case 1: return BFD_RELOC_8_PCREL
;
1004 case 2: return BFD_RELOC_16_PCREL
;
1005 case 4: return BFD_RELOC_32_PCREL
;
1007 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1013 case 1: return BFD_RELOC_8
;
1014 case 2: return BFD_RELOC_16
;
1015 case 4: return BFD_RELOC_32
;
1017 as_bad (_("can not do %d byte relocation"), size
);
1020 return BFD_RELOC_NONE
;
1023 /* Here we decide which fixups can be adjusted to make them relative to
1024 the beginning of the section instead of the symbol. Basically we need
1025 to make sure that the dynamic relocations are done correctly, so in
1026 some cases we force the original symbol to be used. */
1029 tc_i386_fix_adjustable (fixP
)
1032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1033 /* Prevent all adjustments to global symbols, or else dynamic
1034 linking will not work correctly. */
1035 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1036 || S_IS_WEAK (fixP
->fx_addsy
))
1039 /* adjust_reloc_syms doesn't know about the GOT. */
1040 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1041 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1042 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1043 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1044 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1049 #define reloc(SIZE,PCREL,OTHER) 0
1050 #define BFD_RELOC_16 0
1051 #define BFD_RELOC_32 0
1052 #define BFD_RELOC_16_PCREL 0
1053 #define BFD_RELOC_32_PCREL 0
1054 #define BFD_RELOC_386_PLT32 0
1055 #define BFD_RELOC_386_GOT32 0
1056 #define BFD_RELOC_386_GOTOFF 0
1059 static int intel_float_operand
PARAMS ((char *mnemonic
));
1062 intel_float_operand (mnemonic
)
1065 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1068 if (mnemonic
[0] == 'f')
1074 /* This is the guts of the machine-dependent assembler. LINE points to a
1075 machine dependent instruction. This function is supposed to emit
1076 the frags/bytes it assembles to. */
1082 /* Points to template once we've found it. */
1085 /* Count the size of the instruction generated. */
1090 char mnemonic
[MAX_MNEM_SIZE
];
1092 /* Initialize globals. */
1093 memset (&i
, '\0', sizeof (i
));
1094 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1095 i
.disp_reloc
[j
] = NO_RELOC
;
1096 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1097 memset (im_expressions
, '\0', sizeof (im_expressions
));
1098 save_stack_p
= save_stack
;
1100 /* First parse an instruction mnemonic & call i386_operand for the operands.
1101 We assume that the scrubber has arranged it so that line[0] is the valid
1102 start of a (possibly prefixed) mnemonic. */
1105 char *token_start
= l
;
1108 /* Non-zero if we found a prefix only acceptable with string insns. */
1109 const char *expecting_string_instruction
= NULL
;
1114 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1117 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1119 as_bad (_("no such instruction: `%s'"), token_start
);
1124 if (!is_space_char (*l
)
1125 && *l
!= END_OF_INSN
1126 && *l
!= PREFIX_SEPARATOR
)
1128 as_bad (_("invalid character %s in mnemonic"),
1129 output_invalid (*l
));
1132 if (token_start
== l
)
1134 if (*l
== PREFIX_SEPARATOR
)
1135 as_bad (_("expecting prefix; got nothing"));
1137 as_bad (_("expecting mnemonic; got nothing"));
1141 /* Look up instruction (or prefix) via hash table. */
1142 current_templates
= hash_find (op_hash
, mnemonic
);
1144 if (*l
!= END_OF_INSN
1145 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1146 && current_templates
1147 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1149 /* If we are in 16-bit mode, do not allow addr16 or data16.
1150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1151 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1152 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1155 as_bad (_("redundant %s prefix"),
1156 current_templates
->start
->name
);
1159 /* Add prefix, checking for repeated prefixes. */
1160 switch (add_prefix (current_templates
->start
->base_opcode
))
1165 expecting_string_instruction
= current_templates
->start
->name
;
1168 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1175 if (!current_templates
)
1177 /* See if we can get a match by trimming off a suffix. */
1180 case WORD_MNEM_SUFFIX
:
1181 case BYTE_MNEM_SUFFIX
:
1182 case SHORT_MNEM_SUFFIX
:
1183 case LONG_MNEM_SUFFIX
:
1184 i
.suffix
= mnem_p
[-1];
1186 current_templates
= hash_find (op_hash
, mnemonic
);
1190 case DWORD_MNEM_SUFFIX
:
1193 i
.suffix
= mnem_p
[-1];
1195 current_templates
= hash_find (op_hash
, mnemonic
);
1199 if (!current_templates
)
1201 as_bad (_("no such instruction: `%s'"), token_start
);
1206 /* Check if instruction is supported on specified architecture. */
1207 if (cpu_arch_flags
!= 0)
1209 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1211 as_warn (_("`%s' is not supported on `%s'"),
1212 current_templates
->start
->name
, cpu_arch_name
);
1214 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1216 as_warn (_("use .code16 to ensure correct addressing mode"));
1220 /* Check for rep/repne without a string instruction. */
1221 if (expecting_string_instruction
1222 && !(current_templates
->start
->opcode_modifier
& IsString
))
1224 as_bad (_("expecting string instruction after `%s'"),
1225 expecting_string_instruction
);
1229 /* There may be operands to parse. */
1230 if (*l
!= END_OF_INSN
)
1232 /* 1 if operand is pending after ','. */
1233 unsigned int expecting_operand
= 0;
1235 /* Non-zero if operand parens not balanced. */
1236 unsigned int paren_not_balanced
;
1240 /* Skip optional white space before operand. */
1241 if (is_space_char (*l
))
1243 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1245 as_bad (_("invalid character %s before operand %d"),
1246 output_invalid (*l
),
1250 token_start
= l
; /* after white space */
1251 paren_not_balanced
= 0;
1252 while (paren_not_balanced
|| *l
!= ',')
1254 if (*l
== END_OF_INSN
)
1256 if (paren_not_balanced
)
1259 as_bad (_("unbalanced parenthesis in operand %d."),
1262 as_bad (_("unbalanced brackets in operand %d."),
1267 break; /* we are done */
1269 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1271 as_bad (_("invalid character %s in operand %d"),
1272 output_invalid (*l
),
1279 ++paren_not_balanced
;
1281 --paren_not_balanced
;
1286 ++paren_not_balanced
;
1288 --paren_not_balanced
;
1292 if (l
!= token_start
)
1293 { /* Yes, we've read in another operand. */
1294 unsigned int operand_ok
;
1295 this_operand
= i
.operands
++;
1296 if (i
.operands
> MAX_OPERANDS
)
1298 as_bad (_("spurious operands; (%d operands/instruction max)"),
1302 /* Now parse operand adding info to 'i' as we go along. */
1303 END_STRING_AND_SAVE (l
);
1307 i386_intel_operand (token_start
,
1308 intel_float_operand (mnemonic
));
1310 operand_ok
= i386_operand (token_start
);
1312 RESTORE_END_STRING (l
);
1318 if (expecting_operand
)
1320 expecting_operand_after_comma
:
1321 as_bad (_("expecting operand after ','; got nothing"));
1326 as_bad (_("expecting operand before ','; got nothing"));
1331 /* Now *l must be either ',' or END_OF_INSN. */
1334 if (*++l
== END_OF_INSN
)
1336 /* Just skip it, if it's \n complain. */
1337 goto expecting_operand_after_comma
;
1339 expecting_operand
= 1;
1342 while (*l
!= END_OF_INSN
);
1346 /* Now we've parsed the mnemonic into a set of templates, and have the
1349 Next, we find a template that matches the given insn,
1350 making sure the overlap of the given operands types is consistent
1351 with the template operand types. */
1353 #define MATCH(overlap, given, template) \
1354 ((overlap & ~JumpAbsolute) \
1355 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1357 /* If given types r0 and r1 are registers they must be of the same type
1358 unless the expected operand type register overlap is null.
1359 Note that Acc in a template matches every size of reg. */
1360 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1361 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1362 ((g0) & Reg) == ((g1) & Reg) || \
1363 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1366 register unsigned int overlap0
, overlap1
;
1367 unsigned int overlap2
;
1368 unsigned int found_reverse_match
;
1371 /* All intel opcodes have reversed operands except for "bound" and
1372 "enter". We also don't reverse intersegment "jmp" and "call"
1373 instructions with 2 immediate operands so that the immediate segment
1374 precedes the offset, as it does when in AT&T mode. "enter" and the
1375 intersegment "jmp" and "call" instructions are the only ones that
1376 have two immediate operands. */
1377 if (intel_syntax
&& i
.operands
> 1
1378 && (strcmp (mnemonic
, "bound") != 0)
1379 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1381 union i386_op temp_op
;
1382 unsigned int temp_type
;
1386 if (i
.operands
== 2)
1391 else if (i
.operands
== 3)
1396 temp_type
= i
.types
[xchg2
];
1397 i
.types
[xchg2
] = i
.types
[xchg1
];
1398 i
.types
[xchg1
] = temp_type
;
1399 temp_op
= i
.op
[xchg2
];
1400 i
.op
[xchg2
] = i
.op
[xchg1
];
1401 i
.op
[xchg1
] = temp_op
;
1403 if (i
.mem_operands
== 2)
1405 const seg_entry
*temp_seg
;
1406 temp_seg
= i
.seg
[0];
1407 i
.seg
[0] = i
.seg
[1];
1408 i
.seg
[1] = temp_seg
;
1414 /* Try to ensure constant immediates are represented in the smallest
1416 char guess_suffix
= 0;
1420 guess_suffix
= i
.suffix
;
1421 else if (i
.reg_operands
)
1423 /* Figure out a suffix from the last register operand specified.
1424 We can't do this properly yet, ie. excluding InOutPortReg,
1425 but the following works for instructions with immediates.
1426 In any case, we can't set i.suffix yet. */
1427 for (op
= i
.operands
; --op
>= 0;)
1428 if (i
.types
[op
] & Reg
)
1430 if (i
.types
[op
] & Reg8
)
1431 guess_suffix
= BYTE_MNEM_SUFFIX
;
1432 else if (i
.types
[op
] & Reg16
)
1433 guess_suffix
= WORD_MNEM_SUFFIX
;
1437 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1438 guess_suffix
= WORD_MNEM_SUFFIX
;
1440 for (op
= i
.operands
; --op
>= 0;)
1441 if ((i
.types
[op
] & Imm
)
1442 && i
.op
[op
].imms
->X_op
== O_constant
)
1444 /* If a suffix is given, this operand may be shortened. */
1445 switch (guess_suffix
)
1447 case WORD_MNEM_SUFFIX
:
1448 i
.types
[op
] |= Imm16
;
1450 case BYTE_MNEM_SUFFIX
:
1451 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1455 /* If this operand is at most 16 bits, convert it to a
1456 signed 16 bit number before trying to see whether it will
1457 fit in an even smaller size. This allows a 16-bit operand
1458 such as $0xffe0 to be recognised as within Imm8S range. */
1459 if ((i
.types
[op
] & Imm16
)
1460 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1462 i
.op
[op
].imms
->X_add_number
=
1463 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1465 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1469 if (i
.disp_operands
)
1471 /* Try to use the smallest displacement type too. */
1474 for (op
= i
.operands
; --op
>= 0;)
1475 if ((i
.types
[op
] & Disp
)
1476 && i
.op
[op
].imms
->X_op
== O_constant
)
1478 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1480 if (i
.types
[op
] & Disp16
)
1482 /* We know this operand is at most 16 bits, so
1483 convert to a signed 16 bit number before trying
1484 to see whether it will fit in an even smaller
1487 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1489 if (fits_in_signed_byte (disp
))
1490 i
.types
[op
] |= Disp8
;
1497 found_reverse_match
= 0;
1498 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1500 : (i
.suffix
== WORD_MNEM_SUFFIX
1502 : (i
.suffix
== SHORT_MNEM_SUFFIX
1504 : (i
.suffix
== LONG_MNEM_SUFFIX
1506 : (i
.suffix
== DWORD_MNEM_SUFFIX
1508 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1510 for (t
= current_templates
->start
;
1511 t
< current_templates
->end
;
1514 /* Must have right number of operands. */
1515 if (i
.operands
!= t
->operands
)
1518 /* Check the suffix, except for some instructions in intel mode. */
1519 if ((t
->opcode_modifier
& suffix_check
)
1521 && (t
->opcode_modifier
& IgnoreSize
))
1523 && t
->base_opcode
== 0xd9
1524 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1525 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1528 else if (!t
->operands
)
1529 /* 0 operands always matches. */
1532 overlap0
= i
.types
[0] & t
->operand_types
[0];
1533 switch (t
->operands
)
1536 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1541 overlap1
= i
.types
[1] & t
->operand_types
[1];
1542 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1543 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1544 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1545 t
->operand_types
[0],
1546 overlap1
, i
.types
[1],
1547 t
->operand_types
[1]))
1549 /* Check if other direction is valid ... */
1550 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1553 /* Try reversing direction of operands. */
1554 overlap0
= i
.types
[0] & t
->operand_types
[1];
1555 overlap1
= i
.types
[1] & t
->operand_types
[0];
1556 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1557 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1558 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1559 t
->operand_types
[1],
1560 overlap1
, i
.types
[1],
1561 t
->operand_types
[0]))
1563 /* Does not match either direction. */
1566 /* found_reverse_match holds which of D or FloatDR
1568 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1571 /* Found a forward 2 operand match here. */
1572 if (t
->operands
== 3)
1574 /* Here we make use of the fact that there are no
1575 reverse match 3 operand instructions, and all 3
1576 operand instructions only need to be checked for
1577 register consistency between operands 2 and 3. */
1578 overlap2
= i
.types
[2] & t
->operand_types
[2];
1579 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1580 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1581 t
->operand_types
[1],
1582 overlap2
, i
.types
[2],
1583 t
->operand_types
[2]))
1587 /* Found either forward/reverse 2 or 3 operand match here:
1588 slip through to break. */
1590 /* We've found a match; break out of loop. */
1593 if (t
== current_templates
->end
)
1595 /* We found no match. */
1596 as_bad (_("suffix or operands invalid for `%s'"),
1597 current_templates
->start
->name
);
1601 if (!quiet_warnings
)
1604 && ((i
.types
[0] & JumpAbsolute
)
1605 != (t
->operand_types
[0] & JumpAbsolute
)))
1607 as_warn (_("indirect %s without `*'"), t
->name
);
1610 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1611 == (IsPrefix
|IgnoreSize
))
1613 /* Warn them that a data or address size prefix doesn't
1614 affect assembly of the next line of code. */
1615 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1619 /* Copy the template we found. */
1621 if (found_reverse_match
)
1623 /* If we found a reverse match we must alter the opcode
1624 direction bit. found_reverse_match holds bits to change
1625 (different for int & float insns). */
1627 i
.tm
.base_opcode
^= found_reverse_match
;
1629 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1630 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1633 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1636 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1637 i
.tm
.base_opcode
^= FloatR
;
1639 if (i
.tm
.opcode_modifier
& FWait
)
1640 if (! add_prefix (FWAIT_OPCODE
))
1643 /* Check string instruction segment overrides. */
1644 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1646 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1647 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1649 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1651 as_bad (_("`%s' operand %d must use `%%es' segment"),
1656 /* There's only ever one segment override allowed per instruction.
1657 This instruction possibly has a legal segment override on the
1658 second operand, so copy the segment to where non-string
1659 instructions store it, allowing common code. */
1660 i
.seg
[0] = i
.seg
[1];
1662 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1664 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1666 as_bad (_("`%s' operand %d must use `%%es' segment"),
1674 /* If matched instruction specifies an explicit instruction mnemonic
1676 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1678 if (i
.tm
.opcode_modifier
& Size16
)
1679 i
.suffix
= WORD_MNEM_SUFFIX
;
1681 i
.suffix
= LONG_MNEM_SUFFIX
;
1683 else if (i
.reg_operands
)
1685 /* If there's no instruction mnemonic suffix we try to invent one
1686 based on register operands. */
1689 /* We take i.suffix from the last register operand specified,
1690 Destination register type is more significant than source
1693 for (op
= i
.operands
; --op
>= 0;)
1694 if ((i
.types
[op
] & Reg
)
1695 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1697 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1698 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1703 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1706 for (op
= i
.operands
; --op
>= 0;)
1708 /* If this is an eight bit register, it's OK. If it's
1709 the 16 or 32 bit version of an eight bit register,
1710 we will just use the low portion, and that's OK too. */
1711 if (i
.types
[op
] & Reg8
)
1714 /* movzx and movsx should not generate this warning. */
1716 && (i
.tm
.base_opcode
== 0xfb7
1717 || i
.tm
.base_opcode
== 0xfb6
1718 || i
.tm
.base_opcode
== 0xfbe
1719 || i
.tm
.base_opcode
== 0xfbf))
1722 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1724 /* Check that the template allows eight bit regs
1725 This kills insns such as `orb $1,%edx', which
1726 maybe should be allowed. */
1727 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1731 #if REGISTER_WARNINGS
1733 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1734 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1735 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1736 i
.op
[op
].regs
->reg_name
,
1741 /* Any other register is bad. */
1742 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1744 | Control
| Debug
| Test
1745 | FloatReg
| FloatAcc
))
1747 as_bad (_("`%%%s' not allowed with `%s%c'"),
1748 i
.op
[op
].regs
->reg_name
,
1755 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1759 for (op
= i
.operands
; --op
>= 0;)
1760 /* Reject eight bit registers, except where the template
1761 requires them. (eg. movzb) */
1762 if ((i
.types
[op
] & Reg8
) != 0
1763 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1765 as_bad (_("`%%%s' not allowed with `%s%c'"),
1766 i
.op
[op
].regs
->reg_name
,
1771 #if REGISTER_WARNINGS
1772 /* Warn if the e prefix on a general reg is missing. */
1773 else if (!quiet_warnings
1774 && (i
.types
[op
] & Reg16
) != 0
1775 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1777 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1778 (i
.op
[op
].regs
+ 8)->reg_name
,
1779 i
.op
[op
].regs
->reg_name
,
1784 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1787 for (op
= i
.operands
; --op
>= 0;)
1788 /* Reject eight bit registers, except where the template
1789 requires them. (eg. movzb) */
1790 if ((i
.types
[op
] & Reg8
) != 0
1791 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1793 as_bad (_("`%%%s' not allowed with `%s%c'"),
1794 i
.op
[op
].regs
->reg_name
,
1799 #if REGISTER_WARNINGS
1800 /* Warn if the e prefix on a general reg is present. */
1801 else if (!quiet_warnings
1802 && (i
.types
[op
] & Reg32
) != 0
1803 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1805 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1806 (i
.op
[op
].regs
- 8)->reg_name
,
1807 i
.op
[op
].regs
->reg_name
,
1812 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
1813 /* Do nothing if the instruction is going to ignore the prefix. */
1818 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1820 i
.suffix
= stackop_size
;
1823 /* Make still unresolved immediate matches conform to size of immediate
1824 given in i.suffix. Note: overlap2 cannot be an immediate! */
1825 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1826 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1827 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1831 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1832 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1834 else if (overlap0
== (Imm16
| Imm32
))
1837 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1841 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1845 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1846 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1847 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1851 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1852 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1854 else if (overlap1
== (Imm16
| Imm32
))
1857 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1861 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1865 assert ((overlap2
& Imm
) == 0);
1867 i
.types
[0] = overlap0
;
1868 if (overlap0
& ImplicitRegister
)
1870 if (overlap0
& Imm1
)
1871 i
.imm_operands
= 0; /* kludge for shift insns. */
1873 i
.types
[1] = overlap1
;
1874 if (overlap1
& ImplicitRegister
)
1877 i
.types
[2] = overlap2
;
1878 if (overlap2
& ImplicitRegister
)
1881 /* Finalize opcode. First, we change the opcode based on the operand
1882 size given by i.suffix: We need not change things for byte insns. */
1884 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1886 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1890 /* For movzx and movsx, need to check the register type. */
1892 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1893 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1895 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1897 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1898 if (!add_prefix (prefix
))
1902 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1904 /* It's not a byte, select word/dword operation. */
1905 if (i
.tm
.opcode_modifier
& W
)
1907 if (i
.tm
.opcode_modifier
& ShortForm
)
1908 i
.tm
.base_opcode
|= 8;
1910 i
.tm
.base_opcode
|= 1;
1912 /* Now select between word & dword operations via the operand
1913 size prefix, except for instructions that will ignore this
1915 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1916 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1917 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1919 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1920 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1921 prefix
= ADDR_PREFIX_OPCODE
;
1923 if (! add_prefix (prefix
))
1926 /* Size floating point instruction. */
1927 if (i
.suffix
== LONG_MNEM_SUFFIX
1928 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1930 if (i
.tm
.opcode_modifier
& FloatMF
)
1931 i
.tm
.base_opcode
^= 4;
1935 if (i
.tm
.opcode_modifier
& ImmExt
)
1937 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1938 opcode suffix which is coded in the same place as an 8-bit
1939 immediate field would be. Here we fake an 8-bit immediate
1940 operand from the opcode suffix stored in tm.extension_opcode. */
1944 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1946 exp
= &im_expressions
[i
.imm_operands
++];
1947 i
.op
[i
.operands
].imms
= exp
;
1948 i
.types
[i
.operands
++] = Imm8
;
1949 exp
->X_op
= O_constant
;
1950 exp
->X_add_number
= i
.tm
.extension_opcode
;
1951 i
.tm
.extension_opcode
= None
;
1954 /* For insns with operands there are more diddles to do to the opcode. */
1957 /* Default segment register this instruction will use
1958 for memory accesses. 0 means unknown.
1959 This is only for optimizing out unnecessary segment overrides. */
1960 const seg_entry
*default_seg
= 0;
1962 /* The imul $imm, %reg instruction is converted into
1963 imul $imm, %reg, %reg, and the clr %reg instruction
1964 is converted into xor %reg, %reg. */
1965 if (i
.tm
.opcode_modifier
& regKludge
)
1967 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1968 /* Pretend we saw the extra register operand. */
1969 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1970 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1971 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1975 if (i
.tm
.opcode_modifier
& ShortForm
)
1977 /* The register or float register operand is in operand 0 or 1. */
1978 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1979 /* Register goes in low 3 bits of opcode. */
1980 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1981 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1983 /* Warn about some common errors, but press on regardless.
1984 The first case can be generated by gcc (<= 2.8.1). */
1985 if (i
.operands
== 2)
1987 /* Reversed arguments on faddp, fsubp, etc. */
1988 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1989 i
.op
[1].regs
->reg_name
,
1990 i
.op
[0].regs
->reg_name
);
1994 /* Extraneous `l' suffix on fp insn. */
1995 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1996 i
.op
[0].regs
->reg_name
);
2000 else if (i
.tm
.opcode_modifier
& Modrm
)
2002 /* The opcode is completed (modulo i.tm.extension_opcode which
2003 must be put into the modrm byte).
2004 Now, we make the modrm & index base bytes based on all the
2005 info we've collected. */
2007 /* i.reg_operands MUST be the number of real register operands;
2008 implicit registers do not count. */
2009 if (i
.reg_operands
== 2)
2011 unsigned int source
, dest
;
2012 source
= ((i
.types
[0]
2013 & (Reg
| RegMMX
| RegXMM
2015 | Control
| Debug
| Test
))
2020 /* One of the register operands will be encoded in the
2021 i.tm.reg field, the other in the combined i.tm.mode
2022 and i.tm.regmem fields. If no form of this
2023 instruction supports a memory destination operand,
2024 then we assume the source operand may sometimes be
2025 a memory operand and so we need to store the
2026 destination in the i.rm.reg field. */
2027 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2029 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2030 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2034 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2035 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2039 { /* If it's not 2 reg operands... */
2042 unsigned int fake_zero_displacement
= 0;
2043 unsigned int op
= ((i
.types
[0] & AnyMem
)
2045 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2052 if (! i
.disp_operands
)
2053 fake_zero_displacement
= 1;
2056 /* Operand is just <disp> */
2057 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2059 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2060 i
.types
[op
] &= ~Disp
;
2061 i
.types
[op
] |= Disp16
;
2065 i
.rm
.regmem
= NO_BASE_REGISTER
;
2066 i
.types
[op
] &= ~Disp
;
2067 i
.types
[op
] |= Disp32
;
2070 else /* ! i.base_reg && i.index_reg */
2072 i
.sib
.index
= i
.index_reg
->reg_num
;
2073 i
.sib
.base
= NO_BASE_REGISTER
;
2074 i
.sib
.scale
= i
.log2_scale_factor
;
2075 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2076 i
.types
[op
] &= ~Disp
;
2077 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2080 else if (i
.base_reg
->reg_type
& Reg16
)
2082 switch (i
.base_reg
->reg_num
)
2087 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2088 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2095 if ((i
.types
[op
] & Disp
) == 0)
2097 /* fake (%bp) into 0(%bp) */
2098 i
.types
[op
] |= Disp8
;
2099 fake_zero_displacement
= 1;
2102 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2103 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2105 default: /* (%si) -> 4 or (%di) -> 5 */
2106 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2108 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2110 else /* i.base_reg and 32 bit mode */
2112 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2113 i
.sib
.base
= i
.base_reg
->reg_num
;
2114 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2117 if (i
.disp_operands
== 0)
2119 fake_zero_displacement
= 1;
2120 i
.types
[op
] |= Disp8
;
2123 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2127 i
.sib
.scale
= i
.log2_scale_factor
;
2130 /* <disp>(%esp) becomes two byte modrm
2131 with no index register. We've already
2132 stored the code for esp in i.rm.regmem
2133 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2134 base register besides %esp will not use
2135 the extra modrm byte. */
2136 i
.sib
.index
= NO_INDEX_REGISTER
;
2137 #if ! SCALE1_WHEN_NO_INDEX
2138 /* Another case where we force the second
2140 if (i
.log2_scale_factor
)
2141 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2146 i
.sib
.index
= i
.index_reg
->reg_num
;
2147 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2149 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2152 if (fake_zero_displacement
)
2154 /* Fakes a zero displacement assuming that i.types[op]
2155 holds the correct displacement size. */
2158 assert (i
.op
[op
].disps
== 0);
2159 exp
= &disp_expressions
[i
.disp_operands
++];
2160 i
.op
[op
].disps
= exp
;
2161 exp
->X_op
= O_constant
;
2162 exp
->X_add_number
= 0;
2163 exp
->X_add_symbol
= (symbolS
*) 0;
2164 exp
->X_op_symbol
= (symbolS
*) 0;
2168 /* Fill in i.rm.reg or i.rm.regmem field with register
2169 operand (if any) based on i.tm.extension_opcode.
2170 Again, we must be careful to make sure that
2171 segment/control/debug/test/MMX registers are coded
2172 into the i.rm.reg field. */
2177 & (Reg
| RegMMX
| RegXMM
2179 | Control
| Debug
| Test
))
2182 & (Reg
| RegMMX
| RegXMM
2184 | Control
| Debug
| Test
))
2187 /* If there is an extension opcode to put here, the
2188 register number must be put into the regmem field. */
2189 if (i
.tm
.extension_opcode
!= None
)
2190 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2192 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2194 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2195 we must set it to 3 to indicate this is a register
2196 operand in the regmem field. */
2197 if (!i
.mem_operands
)
2201 /* Fill in i.rm.reg field with extension opcode (if any). */
2202 if (i
.tm
.extension_opcode
!= None
)
2203 i
.rm
.reg
= i
.tm
.extension_opcode
;
2206 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2208 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2209 && i
.op
[0].regs
->reg_num
== 1)
2211 as_bad (_("you can't `pop %%cs'"));
2214 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2216 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2220 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2222 /* For the string instructions that allow a segment override
2223 on one of their operands, the default segment is ds. */
2227 /* If a segment was explicitly specified,
2228 and the specified segment is not the default,
2229 use an opcode prefix to select it.
2230 If we never figured out what the default segment is,
2231 then default_seg will be zero at this point,
2232 and the specified segment prefix will always be used. */
2233 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2235 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2239 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2241 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2242 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2246 /* Handle conversion of 'int $3' --> special int3 insn. */
2247 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2249 i
.tm
.base_opcode
= INT3_OPCODE
;
2253 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2254 && i
.op
[0].disps
->X_op
== O_constant
)
2256 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2257 the absolute address given by the constant. Since ix86 jumps and
2258 calls are pc relative, we need to generate a reloc. */
2259 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2260 i
.op
[0].disps
->X_op
= O_symbol
;
2263 /* We are ready to output the insn. */
2268 if (i
.tm
.opcode_modifier
& Jump
)
2275 if (flag_16bit_code
)
2279 if (i
.prefix
[DATA_PREFIX
])
2290 if (i
.prefixes
!= 0 && !intel_syntax
)
2291 as_warn (_("skipping prefixes on this instruction"));
2293 /* It's always a symbol; End frag & setup for relax.
2294 Make sure there is enough room in this frag for the largest
2295 instruction we may generate in md_convert_frag. This is 2
2296 bytes for the opcode and room for the prefix and largest
2298 frag_grow (prefix
+ 2 + size
);
2299 insn_size
+= prefix
+ 1;
2300 /* Prefix and 1 opcode byte go in fr_fix. */
2301 p
= frag_more (prefix
+ 1);
2303 *p
++ = DATA_PREFIX_OPCODE
;
2304 *p
= i
.tm
.base_opcode
;
2305 /* 1 possible extra opcode + displacement go in var part.
2306 Pass reloc in fr_var. */
2307 frag_var (rs_machine_dependent
,
2310 ((unsigned char) *p
== JUMP_PC_RELATIVE
2311 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2312 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2313 i
.op
[0].disps
->X_add_symbol
,
2314 i
.op
[0].disps
->X_add_number
,
2317 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2321 if (i
.tm
.opcode_modifier
& JumpByte
)
2323 /* This is a loop or jecxz type instruction. */
2325 if (i
.prefix
[ADDR_PREFIX
])
2328 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2337 if (flag_16bit_code
)
2340 if (i
.prefix
[DATA_PREFIX
])
2343 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2353 if (i
.prefixes
!= 0 && !intel_syntax
)
2354 as_warn (_("skipping prefixes on this instruction"));
2356 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2358 insn_size
+= 1 + size
;
2359 p
= frag_more (1 + size
);
2363 /* Opcode can be at most two bytes. */
2364 insn_size
+= 2 + size
;
2365 p
= frag_more (2 + size
);
2366 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2368 *p
++ = i
.tm
.base_opcode
& 0xff;
2370 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2371 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2373 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2380 if (flag_16bit_code
)
2384 if (i
.prefix
[DATA_PREFIX
])
2395 if (i
.prefixes
!= 0 && !intel_syntax
)
2396 as_warn (_("skipping prefixes on this instruction"));
2398 /* 1 opcode; 2 segment; offset */
2399 insn_size
+= prefix
+ 1 + 2 + size
;
2400 p
= frag_more (prefix
+ 1 + 2 + size
);
2402 *p
++ = DATA_PREFIX_OPCODE
;
2403 *p
++ = i
.tm
.base_opcode
;
2404 if (i
.op
[1].imms
->X_op
== O_constant
)
2406 offsetT n
= i
.op
[1].imms
->X_add_number
;
2409 && !fits_in_unsigned_word (n
)
2410 && !fits_in_signed_word (n
))
2412 as_bad (_("16-bit jump out of range"));
2415 md_number_to_chars (p
, n
, size
);
2418 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2419 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2420 if (i
.op
[0].imms
->X_op
!= O_constant
)
2421 as_bad (_("can't handle non absolute segment in `%s'"),
2423 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2427 /* Output normal instructions here. */
2430 /* The prefix bytes. */
2432 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2439 md_number_to_chars (p
, (valueT
) *q
, 1);
2443 /* Now the opcode; be careful about word order here! */
2444 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2447 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2449 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2453 /* Put out high byte first: can't use md_number_to_chars! */
2454 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2455 *p
= i
.tm
.base_opcode
& 0xff;
2458 { /* Opcode is either 3 or 4 bytes. */
2459 if (i
.tm
.base_opcode
& 0xff000000)
2463 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2470 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2471 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2472 *p
= (i
.tm
.base_opcode
) & 0xff;
2475 /* Now the modrm byte and sib byte (if present). */
2476 if (i
.tm
.opcode_modifier
& Modrm
)
2480 md_number_to_chars (p
,
2481 (valueT
) (i
.rm
.regmem
<< 0
2485 /* If i.rm.regmem == ESP (4)
2486 && i.rm.mode != (Register mode)
2488 ==> need second modrm byte. */
2489 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2491 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2495 md_number_to_chars (p
,
2496 (valueT
) (i
.sib
.base
<< 0
2498 | i
.sib
.scale
<< 6),
2503 if (i
.disp_operands
)
2505 register unsigned int n
;
2507 for (n
= 0; n
< i
.operands
; n
++)
2509 if (i
.types
[n
] & Disp
)
2511 if (i
.op
[n
].disps
->X_op
== O_constant
)
2517 if (i
.types
[n
] & (Disp8
| Disp16
))
2520 if (i
.types
[n
] & Disp8
)
2523 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2526 p
= frag_more (size
);
2527 md_number_to_chars (p
, val
, size
);
2533 if (i
.types
[n
] & Disp16
)
2537 p
= frag_more (size
);
2538 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2540 reloc (size
, 0, i
.disp_reloc
[n
]));
2546 /* Output immediate. */
2549 register unsigned int n
;
2551 for (n
= 0; n
< i
.operands
; n
++)
2553 if (i
.types
[n
] & Imm
)
2555 if (i
.op
[n
].imms
->X_op
== O_constant
)
2561 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2564 if (i
.types
[n
] & (Imm8
| Imm8S
))
2567 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2570 p
= frag_more (size
);
2571 md_number_to_chars (p
, val
, size
);
2575 /* Not absolute_section.
2576 Need a 32-bit fixup (don't support 8bit
2577 non-absolute imms). Try to support other
2579 #ifdef BFD_ASSEMBLER
2580 enum bfd_reloc_code_real reloc_type
;
2586 if (i
.types
[n
] & Imm16
)
2588 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2592 p
= frag_more (size
);
2593 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2594 #ifdef BFD_ASSEMBLER
2595 if (reloc_type
== BFD_RELOC_32
2597 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2598 && (i
.op
[n
].imms
->X_op
== O_symbol
2599 || (i
.op
[n
].imms
->X_op
== O_add
2600 && ((symbol_get_value_expression
2601 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2604 reloc_type
= BFD_RELOC_386_GOTPC
;
2605 i
.op
[n
].imms
->X_add_number
+= 3;
2608 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2609 i
.op
[n
].imms
, 0, reloc_type
);
2616 dwarf2_emit_insn (insn_size
);
2623 #endif /* DEBUG386 */
2627 static int i386_immediate
PARAMS ((char *));
2630 i386_immediate (imm_start
)
2633 char *save_input_line_pointer
;
2637 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2639 as_bad (_("only 1 or 2 immediate operands are allowed"));
2643 exp
= &im_expressions
[i
.imm_operands
++];
2644 i
.op
[this_operand
].imms
= exp
;
2646 if (is_space_char (*imm_start
))
2649 save_input_line_pointer
= input_line_pointer
;
2650 input_line_pointer
= imm_start
;
2654 /* We can have operands of the form
2655 <symbol>@GOTOFF+<nnn>
2656 Take the easy way out here and copy everything
2657 into a temporary buffer... */
2660 cp
= strchr (input_line_pointer
, '@');
2667 /* GOT relocations are not supported in 16 bit mode. */
2668 if (flag_16bit_code
)
2669 as_bad (_("GOT relocations not supported in 16 bit mode"));
2671 if (GOT_symbol
== NULL
)
2672 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2674 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2676 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2679 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2681 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2684 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2686 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2690 as_bad (_("bad reloc specifier in expression"));
2692 /* Replace the relocation token with ' ', so that errors like
2693 foo@GOTOFF1 will be detected. */
2694 first
= cp
- input_line_pointer
;
2695 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2696 memcpy (tmpbuf
, input_line_pointer
, first
);
2697 tmpbuf
[first
] = ' ';
2698 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2699 input_line_pointer
= tmpbuf
;
2704 exp_seg
= expression (exp
);
2707 if (*input_line_pointer
)
2708 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2710 input_line_pointer
= save_input_line_pointer
;
2712 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2714 /* Missing or bad expr becomes absolute 0. */
2715 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2717 exp
->X_op
= O_constant
;
2718 exp
->X_add_number
= 0;
2719 exp
->X_add_symbol
= (symbolS
*) 0;
2720 exp
->X_op_symbol
= (symbolS
*) 0;
2723 if (exp
->X_op
== O_constant
)
2725 /* Size it properly later. */
2726 i
.types
[this_operand
] |= Imm32
;
2728 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2730 #ifdef BFD_ASSEMBLER
2731 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2733 && exp_seg
!= text_section
2734 && exp_seg
!= data_section
2735 && exp_seg
!= bss_section
2736 && exp_seg
!= undefined_section
2737 #ifdef BFD_ASSEMBLER
2738 && !bfd_is_com_section (exp_seg
)
2742 #ifdef BFD_ASSEMBLER
2743 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2745 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2752 /* This is an address. The size of the address will be
2753 determined later, depending on destination register,
2754 suffix, or the default for the section. We exclude
2755 Imm8S here so that `push $foo' and other instructions
2756 with an Imm8S form will use Imm16 or Imm32. */
2757 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2763 static int i386_scale
PARAMS ((char *));
2769 if (!isdigit (*scale
))
2776 i
.log2_scale_factor
= 0;
2779 i
.log2_scale_factor
= 1;
2782 i
.log2_scale_factor
= 2;
2785 i
.log2_scale_factor
= 3;
2789 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2793 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2795 as_warn (_("scale factor of %d without an index register"),
2796 1 << i
.log2_scale_factor
);
2797 #if SCALE1_WHEN_NO_INDEX
2798 i
.log2_scale_factor
= 0;
2804 static int i386_displacement
PARAMS ((char *, char *));
2807 i386_displacement (disp_start
, disp_end
)
2811 register expressionS
*exp
;
2813 char *save_input_line_pointer
;
2814 int bigdisp
= Disp32
;
2816 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2818 i
.types
[this_operand
] |= bigdisp
;
2820 exp
= &disp_expressions
[i
.disp_operands
];
2821 i
.op
[this_operand
].disps
= exp
;
2823 save_input_line_pointer
= input_line_pointer
;
2824 input_line_pointer
= disp_start
;
2825 END_STRING_AND_SAVE (disp_end
);
2827 #ifndef GCC_ASM_O_HACK
2828 #define GCC_ASM_O_HACK 0
2831 END_STRING_AND_SAVE (disp_end
+ 1);
2832 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2833 && displacement_string_end
[-1] == '+')
2835 /* This hack is to avoid a warning when using the "o"
2836 constraint within gcc asm statements.
2839 #define _set_tssldt_desc(n,addr,limit,type) \
2840 __asm__ __volatile__ ( \
2842 "movw %w1,2+%0\n\t" \
2844 "movb %b1,4+%0\n\t" \
2845 "movb %4,5+%0\n\t" \
2846 "movb $0,6+%0\n\t" \
2847 "movb %h1,7+%0\n\t" \
2849 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2851 This works great except that the output assembler ends
2852 up looking a bit weird if it turns out that there is
2853 no offset. You end up producing code that looks like:
2866 So here we provide the missing zero. */
2868 *displacement_string_end
= '0';
2873 /* We can have operands of the form
2874 <symbol>@GOTOFF+<nnn>
2875 Take the easy way out here and copy everything
2876 into a temporary buffer... */
2879 cp
= strchr (input_line_pointer
, '@');
2886 /* GOT relocations are not supported in 16 bit mode. */
2887 if (flag_16bit_code
)
2888 as_bad (_("GOT relocations not supported in 16 bit mode"));
2890 if (GOT_symbol
== NULL
)
2891 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2893 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2895 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2898 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2900 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2903 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2905 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2909 as_bad (_("bad reloc specifier in expression"));
2911 /* Replace the relocation token with ' ', so that errors like
2912 foo@GOTOFF1 will be detected. */
2913 first
= cp
- input_line_pointer
;
2914 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2915 memcpy (tmpbuf
, input_line_pointer
, first
);
2916 tmpbuf
[first
] = ' ';
2917 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2918 input_line_pointer
= tmpbuf
;
2923 exp_seg
= expression (exp
);
2925 #ifdef BFD_ASSEMBLER
2926 /* We do this to make sure that the section symbol is in
2927 the symbol table. We will ultimately change the relocation
2928 to be relative to the beginning of the section. */
2929 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2931 if (S_IS_LOCAL(exp
->X_add_symbol
)
2932 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2933 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2934 assert (exp
->X_op
== O_symbol
);
2935 exp
->X_op
= O_subtract
;
2936 exp
->X_op_symbol
= GOT_symbol
;
2937 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2942 if (*input_line_pointer
)
2943 as_bad (_("ignoring junk `%s' after expression"),
2944 input_line_pointer
);
2946 RESTORE_END_STRING (disp_end
+ 1);
2948 RESTORE_END_STRING (disp_end
);
2949 input_line_pointer
= save_input_line_pointer
;
2951 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2953 /* Missing or bad expr becomes absolute 0. */
2954 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2956 exp
->X_op
= O_constant
;
2957 exp
->X_add_number
= 0;
2958 exp
->X_add_symbol
= (symbolS
*) 0;
2959 exp
->X_op_symbol
= (symbolS
*) 0;
2962 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2963 if (exp
->X_op
!= O_constant
2964 #ifdef BFD_ASSEMBLER
2965 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2967 && exp_seg
!= text_section
2968 && exp_seg
!= data_section
2969 && exp_seg
!= bss_section
2970 && exp_seg
!= undefined_section
)
2972 #ifdef BFD_ASSEMBLER
2973 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2975 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2983 static int i386_index_check
PARAMS((const char *));
2985 /* Make sure the memory operand we've been dealt is valid.
2986 Return 1 on success, 0 on a failure. */
2989 i386_index_check (operand_string
)
2990 const char *operand_string
;
2992 #if INFER_ADDR_PREFIX
2997 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
2998 /* 16 bit mode checks. */
3000 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3001 != (Reg16
|BaseIndex
)))
3003 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3004 != (Reg16
|BaseIndex
))
3006 && i
.base_reg
->reg_num
< 6
3007 && i
.index_reg
->reg_num
>= 6
3008 && i
.log2_scale_factor
== 0))))
3009 /* 32 bit mode checks. */
3011 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3013 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3014 != (Reg32
|BaseIndex
)))))
3016 #if INFER_ADDR_PREFIX
3017 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3019 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3021 /* Change the size of any displacement too. At most one of
3022 Disp16 or Disp32 is set.
3023 FIXME. There doesn't seem to be any real need for separate
3024 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3025 Removing them would probably clean up the code quite a lot. */
3026 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3027 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3032 as_bad (_("`%s' is not a valid base/index expression"),
3036 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3038 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3044 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3048 i386_operand (operand_string
)
3049 char *operand_string
;
3053 char *op_string
= operand_string
;
3055 if (is_space_char (*op_string
))
3058 /* We check for an absolute prefix (differentiating,
3059 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3060 if (*op_string
== ABSOLUTE_PREFIX
)
3063 if (is_space_char (*op_string
))
3065 i
.types
[this_operand
] |= JumpAbsolute
;
3068 /* Check if operand is a register. */
3069 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3070 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3072 /* Check for a segment override by searching for ':' after a
3073 segment register. */
3075 if (is_space_char (*op_string
))
3077 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3082 i
.seg
[i
.mem_operands
] = &es
;
3085 i
.seg
[i
.mem_operands
] = &cs
;
3088 i
.seg
[i
.mem_operands
] = &ss
;
3091 i
.seg
[i
.mem_operands
] = &ds
;
3094 i
.seg
[i
.mem_operands
] = &fs
;
3097 i
.seg
[i
.mem_operands
] = &gs
;
3101 /* Skip the ':' and whitespace. */
3103 if (is_space_char (*op_string
))
3106 if (!is_digit_char (*op_string
)
3107 && !is_identifier_char (*op_string
)
3108 && *op_string
!= '('
3109 && *op_string
!= ABSOLUTE_PREFIX
)
3111 as_bad (_("bad memory operand `%s'"), op_string
);
3114 /* Handle case of %es:*foo. */
3115 if (*op_string
== ABSOLUTE_PREFIX
)
3118 if (is_space_char (*op_string
))
3120 i
.types
[this_operand
] |= JumpAbsolute
;
3122 goto do_memory_reference
;
3126 as_bad (_("junk `%s' after register"), op_string
);
3129 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3130 i
.op
[this_operand
].regs
= r
;
3133 else if (*op_string
== REGISTER_PREFIX
)
3135 as_bad (_("bad register name `%s'"), op_string
);
3138 else if (*op_string
== IMMEDIATE_PREFIX
)
3141 if (i
.types
[this_operand
] & JumpAbsolute
)
3143 as_bad (_("immediate operand illegal with absolute jump"));
3146 if (!i386_immediate (op_string
))
3149 else if (is_digit_char (*op_string
)
3150 || is_identifier_char (*op_string
)
3151 || *op_string
== '(' )
3153 /* This is a memory reference of some sort. */
3156 /* Start and end of displacement string expression (if found). */
3157 char *displacement_string_start
;
3158 char *displacement_string_end
;
3160 do_memory_reference
:
3161 if ((i
.mem_operands
== 1
3162 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3163 || i
.mem_operands
== 2)
3165 as_bad (_("too many memory references for `%s'"),
3166 current_templates
->start
->name
);
3170 /* Check for base index form. We detect the base index form by
3171 looking for an ')' at the end of the operand, searching
3172 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3174 base_string
= op_string
+ strlen (op_string
);
3177 if (is_space_char (*base_string
))
3180 /* If we only have a displacement, set-up for it to be parsed later. */
3181 displacement_string_start
= op_string
;
3182 displacement_string_end
= base_string
+ 1;
3184 if (*base_string
== ')')
3187 unsigned int parens_balanced
= 1;
3188 /* We've already checked that the number of left & right ()'s are
3189 equal, so this loop will not be infinite. */
3193 if (*base_string
== ')')
3195 if (*base_string
== '(')
3198 while (parens_balanced
);
3200 temp_string
= base_string
;
3202 /* Skip past '(' and whitespace. */
3204 if (is_space_char (*base_string
))
3207 if (*base_string
== ','
3208 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3209 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3211 displacement_string_end
= temp_string
;
3213 i
.types
[this_operand
] |= BaseIndex
;
3217 base_string
= end_op
;
3218 if (is_space_char (*base_string
))
3222 /* There may be an index reg or scale factor here. */
3223 if (*base_string
== ',')
3226 if (is_space_char (*base_string
))
3229 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3230 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3232 base_string
= end_op
;
3233 if (is_space_char (*base_string
))
3235 if (*base_string
== ',')
3238 if (is_space_char (*base_string
))
3241 else if (*base_string
!= ')' )
3243 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3248 else if (*base_string
== REGISTER_PREFIX
)
3250 as_bad (_("bad register name `%s'"), base_string
);
3254 /* Check for scale factor. */
3255 if (isdigit ((unsigned char) *base_string
))
3257 if (!i386_scale (base_string
))
3261 if (is_space_char (*base_string
))
3263 if (*base_string
!= ')')
3265 as_bad (_("expecting `)' after scale factor in `%s'"),
3270 else if (!i
.index_reg
)
3272 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3277 else if (*base_string
!= ')')
3279 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3284 else if (*base_string
== REGISTER_PREFIX
)
3286 as_bad (_("bad register name `%s'"), base_string
);
3291 /* If there's an expression beginning the operand, parse it,
3292 assuming displacement_string_start and
3293 displacement_string_end are meaningful. */
3294 if (displacement_string_start
!= displacement_string_end
)
3296 if (!i386_displacement (displacement_string_start
,
3297 displacement_string_end
))
3301 /* Special case for (%dx) while doing input/output op. */
3303 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3305 && i
.log2_scale_factor
== 0
3306 && i
.seg
[i
.mem_operands
] == 0
3307 && (i
.types
[this_operand
] & Disp
) == 0)
3309 i
.types
[this_operand
] = InOutPortReg
;
3313 if (i386_index_check (operand_string
) == 0)
3319 /* It's not a memory operand; argh! */
3320 as_bad (_("invalid char %s beginning operand %d `%s'"),
3321 output_invalid (*op_string
),
3326 return 1; /* Normal return. */
3329 /* md_estimate_size_before_relax()
3331 Called just before relax() for rs_machine_dependent frags. The x86
3332 assembler uses these frags to handle variable size jump
3335 Any symbol that is now undefined will not become defined.
3336 Return the correct fr_subtype in the frag.
3337 Return the initial "guess for variable size of frag" to caller.
3338 The guess is actually the growth beyond the fixed part. Whatever
3339 we do to grow the fixed or variable part contributes to our
3343 md_estimate_size_before_relax (fragP
, segment
)
3344 register fragS
*fragP
;
3345 register segT segment
;
3347 /* We've already got fragP->fr_subtype right; all we have to do is
3348 check for un-relaxable symbols. On an ELF system, we can't relax
3349 an externally visible symbol, because it may be overridden by a
3351 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3353 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3354 || S_IS_WEAK (fragP
->fr_symbol
)
3358 /* Symbol is undefined in this segment, or we need to keep a
3359 reloc so that weak symbols can be overridden. */
3360 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3361 #ifdef BFD_ASSEMBLER
3362 enum bfd_reloc_code_real reloc_type
;
3366 unsigned char *opcode
;
3369 if (fragP
->fr_var
!= NO_RELOC
)
3370 reloc_type
= fragP
->fr_var
;
3372 reloc_type
= BFD_RELOC_16_PCREL
;
3374 reloc_type
= BFD_RELOC_32_PCREL
;
3376 old_fr_fix
= fragP
->fr_fix
;
3377 opcode
= (unsigned char *) fragP
->fr_opcode
;
3381 case JUMP_PC_RELATIVE
:
3382 /* Make jmp (0xeb) a dword displacement jump. */
3384 fragP
->fr_fix
+= size
;
3385 fix_new (fragP
, old_fr_fix
, size
,
3387 fragP
->fr_offset
, 1,
3392 /* This changes the byte-displacement jump 0x7N
3393 to the dword-displacement jump 0x0f,0x8N. */
3394 opcode
[1] = opcode
[0] + 0x10;
3395 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3396 /* We've added an opcode byte. */
3397 fragP
->fr_fix
+= 1 + size
;
3398 fix_new (fragP
, old_fr_fix
+ 1, size
,
3400 fragP
->fr_offset
, 1,
3405 return fragP
->fr_fix
- old_fr_fix
;
3407 /* Guess a short jump. */
3411 /* Called after relax() is finished.
3413 In: Address of frag.
3414 fr_type == rs_machine_dependent.
3415 fr_subtype is what the address relaxed to.
3417 Out: Any fixSs and constants are set up.
3418 Caller will turn frag into a ".space 0". */
3420 #ifndef BFD_ASSEMBLER
3422 md_convert_frag (headers
, sec
, fragP
)
3423 object_headers
*headers ATTRIBUTE_UNUSED
;
3424 segT sec ATTRIBUTE_UNUSED
;
3425 register fragS
*fragP
;
3428 md_convert_frag (abfd
, sec
, fragP
)
3429 bfd
*abfd ATTRIBUTE_UNUSED
;
3430 segT sec ATTRIBUTE_UNUSED
;
3431 register fragS
*fragP
;
3434 register unsigned char *opcode
;
3435 unsigned char *where_to_put_displacement
= NULL
;
3436 offsetT target_address
;
3437 offsetT opcode_address
;
3438 unsigned int extension
= 0;
3439 offsetT displacement_from_opcode_start
;
3441 opcode
= (unsigned char *) fragP
->fr_opcode
;
3443 /* Address we want to reach in file space. */
3444 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3445 #ifdef BFD_ASSEMBLER
3446 /* Not needed otherwise? */
3447 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3450 /* Address opcode resides at in file space. */
3451 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3453 /* Displacement from opcode start to fill into instruction. */
3454 displacement_from_opcode_start
= target_address
- opcode_address
;
3456 switch (fragP
->fr_subtype
)
3458 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3459 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3460 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3461 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3462 /* Don't have to change opcode. */
3463 extension
= 1; /* 1 opcode + 1 displacement */
3464 where_to_put_displacement
= &opcode
[1];
3467 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3468 extension
= 5; /* 2 opcode + 4 displacement */
3469 opcode
[1] = opcode
[0] + 0x10;
3470 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3471 where_to_put_displacement
= &opcode
[2];
3474 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3475 extension
= 4; /* 1 opcode + 4 displacement */
3477 where_to_put_displacement
= &opcode
[1];
3480 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3481 extension
= 3; /* 2 opcode + 2 displacement */
3482 opcode
[1] = opcode
[0] + 0x10;
3483 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3484 where_to_put_displacement
= &opcode
[2];
3487 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3488 extension
= 2; /* 1 opcode + 2 displacement */
3490 where_to_put_displacement
= &opcode
[1];
3494 BAD_CASE (fragP
->fr_subtype
);
3497 /* Now put displacement after opcode. */
3498 md_number_to_chars ((char *) where_to_put_displacement
,
3499 (valueT
) (displacement_from_opcode_start
- extension
),
3500 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3501 fragP
->fr_fix
+= extension
;
3504 /* Size of byte displacement jmp. */
3505 int md_short_jump_size
= 2;
3507 /* Size of dword displacement jmp. */
3508 int md_long_jump_size
= 5;
3510 /* Size of relocation record. */
3511 const int md_reloc_size
= 8;
3514 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3516 addressT from_addr
, to_addr
;
3517 fragS
*frag ATTRIBUTE_UNUSED
;
3518 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3522 offset
= to_addr
- (from_addr
+ 2);
3523 /* Opcode for byte-disp jump. */
3524 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3525 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3529 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3531 addressT from_addr
, to_addr
;
3532 fragS
*frag ATTRIBUTE_UNUSED
;
3533 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3537 offset
= to_addr
- (from_addr
+ 5);
3538 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3539 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3542 /* Apply a fixup (fixS) to segment data, once it has been determined
3543 by our caller that we have all the info we need to fix it up.
3545 On the 386, immediates, displacements, and data pointers are all in
3546 the same (little-endian) format, so we don't need to care about which
3550 md_apply_fix3 (fixP
, valp
, seg
)
3551 /* The fix we're to put in. */
3554 /* Pointer to the value of the bits. */
3557 /* Segment fix is from. */
3558 segT seg ATTRIBUTE_UNUSED
;
3560 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3561 valueT value
= *valp
;
3563 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3566 switch (fixP
->fx_r_type
)
3572 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3575 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
3578 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
3583 /* This is a hack. There should be a better way to handle this.
3584 This covers for the fact that bfd_install_relocation will
3585 subtract the current location (for partial_inplace, PC relative
3586 relocations); see more below. */
3587 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
3588 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
3589 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
3593 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3595 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
3598 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3601 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
3603 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
3606 || (symbol_section_p (fixP
->fx_addsy
)
3607 && fseg
!= absolute_section
))
3608 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
3609 && ! S_IS_WEAK (fixP
->fx_addsy
)
3610 && S_IS_DEFINED (fixP
->fx_addsy
)
3611 && ! S_IS_COMMON (fixP
->fx_addsy
))
3613 /* Yes, we add the values in twice. This is because
3614 bfd_perform_relocation subtracts them out again. I think
3615 bfd_perform_relocation is broken, but I don't dare change
3617 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3621 #if defined (OBJ_COFF) && defined (TE_PE)
3622 /* For some reason, the PE format does not store a section
3623 address offset for a PC relative symbol. */
3624 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
3625 value
+= md_pcrel_from (fixP
);
3629 /* Fix a few things - the dynamic linker expects certain values here,
3630 and we must not dissappoint it. */
3631 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3632 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3634 switch (fixP
->fx_r_type
)
3636 case BFD_RELOC_386_PLT32
:
3637 /* Make the jump instruction point to the address of the operand. At
3638 runtime we merely add the offset to the actual PLT entry. */
3641 case BFD_RELOC_386_GOTPC
:
3643 /* This is tough to explain. We end up with this one if we have
3644 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3645 * here is to obtain the absolute address of the GOT, and it is strongly
3646 * preferable from a performance point of view to avoid using a runtime
3647 * relocation for this. The actual sequence of instructions often look
3653 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3655 * The call and pop essentially return the absolute address of
3656 * the label .L66 and store it in %ebx. The linker itself will
3657 * ultimately change the first operand of the addl so that %ebx points to
3658 * the GOT, but to keep things simple, the .o file must have this operand
3659 * set so that it generates not the absolute address of .L66, but the
3660 * absolute address of itself. This allows the linker itself simply
3661 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
3662 * added in, and the addend of the relocation is stored in the operand
3663 * field for the instruction itself.
3665 * Our job here is to fix the operand so that it would add the correct
3666 * offset so that %ebx would point to itself. The thing that is tricky is
3667 * that .-.L66 will point to the beginning of the instruction, so we need
3668 * to further modify the operand so that it will point to itself.
3669 * There are other cases where you have something like:
3671 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3673 * and here no correction would be required. Internally in the assembler
3674 * we treat operands of this form as not being pcrel since the '.' is
3675 * explicitly mentioned, and I wonder whether it would simplify matters
3676 * to do it this way. Who knows. In earlier versions of the PIC patches,
3677 * the pcrel_adjust field was used to store the correction, but since the
3678 * expression is not pcrel, I felt it would be confusing to do it this
3683 case BFD_RELOC_386_GOT32
:
3684 value
= 0; /* Fully resolved at runtime. No addend. */
3686 case BFD_RELOC_386_GOTOFF
:
3689 case BFD_RELOC_VTABLE_INHERIT
:
3690 case BFD_RELOC_VTABLE_ENTRY
:
3697 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
3699 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3700 md_number_to_chars (p
, value
, fixP
->fx_size
);
3705 #define MAX_LITTLENUMS 6
3707 /* Turn the string pointed to by litP into a floating point constant
3708 of type TYPE, and emit the appropriate bytes. The number of
3709 LITTLENUMS emitted is stored in *SIZEP. An error message is
3710 returned, or NULL on OK. */
3713 md_atof (type
, litP
, sizeP
)
3719 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3720 LITTLENUM_TYPE
*wordP
;
3742 return _("Bad call to md_atof ()");
3744 t
= atof_ieee (input_line_pointer
, type
, words
);
3746 input_line_pointer
= t
;
3748 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3749 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
3750 the bigendian 386. */
3751 for (wordP
= words
+ prec
- 1; prec
--;)
3753 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
3754 litP
+= sizeof (LITTLENUM_TYPE
);
3759 char output_invalid_buf
[8];
3766 sprintf (output_invalid_buf
, "'%c'", c
);
3768 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
3769 return output_invalid_buf
;
3772 /* REG_STRING starts *before* REGISTER_PREFIX. */
3774 static const reg_entry
*
3775 parse_register (reg_string
, end_op
)
3779 char *s
= reg_string
;
3781 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
3784 /* Skip possible REGISTER_PREFIX and possible whitespace. */
3785 if (*s
== REGISTER_PREFIX
)
3788 if (is_space_char (*s
))
3792 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
3794 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
3795 return (const reg_entry
*) NULL
;
3799 /* For naked regs, make sure that we are not dealing with an identifier.
3800 This prevents confusing an identifier like `eax_var' with register
3802 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
3803 return (const reg_entry
*) NULL
;
3807 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
3809 /* Handle floating point regs, allowing spaces in the (i) part. */
3810 if (r
== i386_regtab
/* %st is first entry of table */)
3812 if (is_space_char (*s
))
3817 if (is_space_char (*s
))
3819 if (*s
>= '0' && *s
<= '7')
3821 r
= &i386_float_regtab
[*s
- '0'];
3823 if (is_space_char (*s
))
3831 /* We have "%st(" then garbage. */
3832 return (const reg_entry
*) NULL
;
3839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3840 const char *md_shortopts
= "kVQ:sq";
3842 const char *md_shortopts
= "q";
3844 struct option md_longopts
[] = {
3845 {NULL
, no_argument
, NULL
, 0}
3847 size_t md_longopts_size
= sizeof (md_longopts
);
3850 md_parse_option (c
, arg
)
3852 char *arg ATTRIBUTE_UNUSED
;
3860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3861 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
3862 should be emitted or not. FIXME: Not implemented. */
3866 /* -V: SVR4 argument to print version ID. */
3868 print_version_id ();
3871 /* -k: Ignore for FreeBSD compatibility. */
3876 /* -s: On i386 Solaris, this tells the native assembler to use
3877 .stab instead of .stab.excl. We always use .stab anyhow. */
3888 md_show_usage (stream
)
3891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3892 fprintf (stream
, _("\
3894 -V print assembler version number\n\
3896 -q quieten some warnings\n\
3899 fprintf (stream
, _("\
3900 -q quieten some warnings\n"));
3904 #ifdef BFD_ASSEMBLER
3905 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
3906 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
3907 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
3909 /* Pick the target format to use. */
3912 i386_target_format ()
3914 switch (OUTPUT_FLAVOR
)
3916 #ifdef OBJ_MAYBE_AOUT
3917 case bfd_target_aout_flavour
:
3918 return AOUT_TARGET_FORMAT
;
3920 #ifdef OBJ_MAYBE_COFF
3921 case bfd_target_coff_flavour
:
3924 #ifdef OBJ_MAYBE_ELF
3925 case bfd_target_elf_flavour
:
3926 return "elf32-i386";
3934 #endif /* OBJ_MAYBE_ more than one */
3935 #endif /* BFD_ASSEMBLER */
3938 md_undefined_symbol (name
)
3941 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
3942 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
3943 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
3944 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
3948 if (symbol_find (name
))
3949 as_bad (_("GOT already in symbol table"));
3950 GOT_symbol
= symbol_new (name
, undefined_section
,
3951 (valueT
) 0, &zero_address_frag
);
3958 /* Round up a section size to the appropriate boundary. */
3961 md_section_align (segment
, size
)
3962 segT segment ATTRIBUTE_UNUSED
;
3965 #ifdef BFD_ASSEMBLER
3966 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3967 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
3969 /* For a.out, force the section size to be aligned. If we don't do
3970 this, BFD will align it for us, but it will not write out the
3971 final bytes of the section. This may be a bug in BFD, but it is
3972 easier to fix it here since that is how the other a.out targets
3976 align
= bfd_get_section_alignment (stdoutput
, segment
);
3977 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
3985 /* On the i386, PC-relative offsets are relative to the start of the
3986 next instruction. That is, the address of the offset, plus its
3987 size, since the offset is always the last part of the insn. */
3990 md_pcrel_from (fixP
)
3993 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4000 int ignore ATTRIBUTE_UNUSED
;
4004 temp
= get_absolute_expression ();
4005 subseg_set (bss_section
, (subsegT
) temp
);
4006 demand_empty_rest_of_line ();
4011 #ifdef BFD_ASSEMBLER
4014 i386_validate_fix (fixp
)
4017 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4019 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4025 tc_gen_reloc (section
, fixp
)
4026 asection
*section ATTRIBUTE_UNUSED
;
4030 bfd_reloc_code_real_type code
;
4032 switch (fixp
->fx_r_type
)
4034 case BFD_RELOC_386_PLT32
:
4035 case BFD_RELOC_386_GOT32
:
4036 case BFD_RELOC_386_GOTOFF
:
4037 case BFD_RELOC_386_GOTPC
:
4039 case BFD_RELOC_VTABLE_ENTRY
:
4040 case BFD_RELOC_VTABLE_INHERIT
:
4041 code
= fixp
->fx_r_type
;
4046 switch (fixp
->fx_size
)
4049 as_bad (_("can not do %d byte pc-relative relocation"),
4051 code
= BFD_RELOC_32_PCREL
;
4053 case 1: code
= BFD_RELOC_8_PCREL
; break;
4054 case 2: code
= BFD_RELOC_16_PCREL
; break;
4055 case 4: code
= BFD_RELOC_32_PCREL
; break;
4060 switch (fixp
->fx_size
)
4063 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4064 code
= BFD_RELOC_32
;
4066 case 1: code
= BFD_RELOC_8
; break;
4067 case 2: code
= BFD_RELOC_16
; break;
4068 case 4: code
= BFD_RELOC_32
; break;
4074 if (code
== BFD_RELOC_32
4076 && fixp
->fx_addsy
== GOT_symbol
)
4077 code
= BFD_RELOC_386_GOTPC
;
4079 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4080 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4081 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4083 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4084 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4085 vtable entry to be used in the relocation's section offset. */
4086 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4087 rel
->address
= fixp
->fx_offset
;
4090 rel
->addend
= fixp
->fx_addnumber
;
4094 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4095 if (rel
->howto
== NULL
)
4097 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4098 _("cannot represent relocation type %s"),
4099 bfd_get_reloc_code_name (code
));
4100 /* Set howto to a garbage value so that we can keep going. */
4101 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4102 assert (rel
->howto
!= NULL
);
4108 #else /* ! BFD_ASSEMBLER */
4110 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4112 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4115 relax_addressT segment_address_in_file
;
4117 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4118 Out: GNU LD relocation length code: 0, 1, or 2. */
4120 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4123 know (fixP
->fx_addsy
!= NULL
);
4125 md_number_to_chars (where
,
4126 (valueT
) (fixP
->fx_frag
->fr_address
4127 + fixP
->fx_where
- segment_address_in_file
),
4130 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4131 ? S_GET_TYPE (fixP
->fx_addsy
)
4132 : fixP
->fx_addsy
->sy_number
);
4134 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4135 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4136 where
[4] = r_symbolnum
& 0x0ff;
4137 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4138 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4139 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4142 #endif /* OBJ_AOUT or OBJ_BOUT. */
4144 #if defined (I386COFF)
4147 tc_coff_fix2rtype (fixP
)
4150 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4153 return (fixP
->fx_pcrel
?
4154 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4155 fixP
->fx_size
== 2 ? R_PCRWORD
:
4157 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4158 fixP
->fx_size
== 2 ? R_RELWORD
:
4163 tc_coff_sizemachdep (frag
)
4167 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4172 #endif /* I386COFF */
4174 #endif /* ! BFD_ASSEMBLER */
4176 /* Parse operands using Intel syntax. This implements a recursive descent
4177 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4180 FIXME: We do not recognize the full operand grammar defined in the MASM
4181 documentation. In particular, all the structure/union and
4182 high-level macro operands are missing.
4184 Uppercase words are terminals, lower case words are non-terminals.
4185 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4186 bars '|' denote choices. Most grammar productions are implemented in
4187 functions called 'intel_<production>'.
4189 Initial production is 'expr'.
4195 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4197 constant digits [[ radixOverride ]]
4199 dataType BYTE | WORD | DWORD | QWORD | XWORD
4232 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4233 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4235 hexdigit a | b | c | d | e | f
4236 | A | B | C | D | E | F
4246 register specialRegister
4250 segmentRegister CS | DS | ES | FS | GS | SS
4252 specialRegister CR0 | CR2 | CR3
4253 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4254 | TR3 | TR4 | TR5 | TR6 | TR7
4256 We simplify the grammar in obvious places (e.g., register parsing is
4257 done by calling parse_register) and eliminate immediate left recursion
4258 to implement a recursive-descent parser.
4298 /* Parsing structure for the intel syntax parser. Used to implement the
4299 semantic actions for the operand grammar. */
4300 struct intel_parser_s
4302 char *op_string
; /* The string being parsed. */
4303 int got_a_float
; /* Whether the operand is a float. */
4304 int op_modifier
; /* Operand modifier. */
4305 int is_mem
; /* 1 if operand is memory reference. */
4306 const reg_entry
*reg
; /* Last register reference found. */
4307 char *disp
; /* Displacement string being built. */
4310 static struct intel_parser_s intel_parser
;
4312 /* Token structure for parsing intel syntax. */
4315 int code
; /* Token code. */
4316 const reg_entry
*reg
; /* Register entry for register tokens. */
4317 char *str
; /* String representation. */
4320 static struct intel_token cur_token
, prev_token
;
4322 /* Token codes for the intel parser. */
4336 /* Prototypes for intel parser functions. */
4337 static int intel_match_token
PARAMS ((int code
));
4338 static void intel_get_token
PARAMS ((void));
4339 static void intel_putback_token
PARAMS ((void));
4340 static int intel_expr
PARAMS ((void));
4341 static int intel_e05
PARAMS ((void));
4342 static int intel_e05_1
PARAMS ((void));
4343 static int intel_e06
PARAMS ((void));
4344 static int intel_e06_1
PARAMS ((void));
4345 static int intel_e09
PARAMS ((void));
4346 static int intel_e09_1
PARAMS ((void));
4347 static int intel_e10
PARAMS ((void));
4348 static int intel_e10_1
PARAMS ((void));
4349 static int intel_e11
PARAMS ((void));
4352 i386_intel_operand (operand_string
, got_a_float
)
4353 char *operand_string
;
4359 /* Initialize token holders. */
4360 cur_token
.code
= prev_token
.code
= T_NIL
;
4361 cur_token
.reg
= prev_token
.reg
= NULL
;
4362 cur_token
.str
= prev_token
.str
= NULL
;
4364 /* Initialize parser structure. */
4365 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4368 strcpy (intel_parser
.op_string
, operand_string
);
4369 intel_parser
.got_a_float
= got_a_float
;
4370 intel_parser
.op_modifier
= -1;
4371 intel_parser
.is_mem
= 0;
4372 intel_parser
.reg
= NULL
;
4373 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4374 if (intel_parser
.disp
== NULL
)
4376 intel_parser
.disp
[0] = '\0';
4378 /* Read the first token and start the parser. */
4380 ret
= intel_expr ();
4384 /* If we found a memory reference, hand it over to i386_displacement
4385 to fill in the rest of the operand fields. */
4386 if (intel_parser
.is_mem
)
4388 if ((i
.mem_operands
== 1
4389 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4390 || i
.mem_operands
== 2)
4392 as_bad (_("too many memory references for '%s'"),
4393 current_templates
->start
->name
);
4398 char *s
= intel_parser
.disp
;
4401 /* Add the displacement expression. */
4403 ret
= i386_displacement (s
, s
+ strlen (s
))
4404 && i386_index_check (s
);
4408 /* Constant and OFFSET expressions are handled by i386_immediate. */
4409 else if (intel_parser
.op_modifier
== OFFSET_FLAT
4410 || intel_parser
.reg
== NULL
)
4411 ret
= i386_immediate (intel_parser
.disp
);
4415 free (intel_parser
.disp
);
4425 /* expr SHORT e05 */
4426 if (cur_token
.code
== T_SHORT
)
4428 intel_parser
.op_modifier
= SHORT
;
4429 intel_match_token (T_SHORT
);
4431 return (intel_e05 ());
4436 return intel_e05 ();
4446 return (intel_e06 () && intel_e05_1 ());
4452 /* e05' addOp e06 e05' */
4453 if (cur_token
.code
== '+' || cur_token
.code
== '-')
4455 strcat (intel_parser
.disp
, cur_token
.str
);
4456 intel_match_token (cur_token
.code
);
4458 return (intel_e06 () && intel_e05_1 ());
4473 return (intel_e09 () && intel_e06_1 ());
4479 /* e06' mulOp e09 e06' */
4480 if (cur_token
.code
== '*' || cur_token
.code
== '/')
4482 strcat (intel_parser
.disp
, cur_token
.str
);
4483 intel_match_token (cur_token
.code
);
4485 return (intel_e09 () && intel_e06_1 ());
4493 /* e09 OFFSET e10 e09'
4502 /* e09 OFFSET e10 e09' */
4503 if (cur_token
.code
== T_OFFSET
)
4505 intel_parser
.is_mem
= 0;
4506 intel_parser
.op_modifier
= OFFSET_FLAT
;
4507 intel_match_token (T_OFFSET
);
4509 return (intel_e10 () && intel_e09_1 ());
4514 return (intel_e10 () && intel_e09_1 ());
4520 /* e09' PTR e10 e09' */
4521 if (cur_token
.code
== T_PTR
)
4523 if (prev_token
.code
== T_BYTE
)
4524 i
.suffix
= BYTE_MNEM_SUFFIX
;
4526 else if (prev_token
.code
== T_WORD
)
4528 if (intel_parser
.got_a_float
== 2) /* "fi..." */
4529 i
.suffix
= SHORT_MNEM_SUFFIX
;
4531 i
.suffix
= WORD_MNEM_SUFFIX
;
4534 else if (prev_token
.code
== T_DWORD
)
4536 if (intel_parser
.got_a_float
== 1) /* "f..." */
4537 i
.suffix
= SHORT_MNEM_SUFFIX
;
4539 i
.suffix
= LONG_MNEM_SUFFIX
;
4542 else if (prev_token
.code
== T_QWORD
)
4543 i
.suffix
= DWORD_MNEM_SUFFIX
;
4545 else if (prev_token
.code
== T_XWORD
)
4546 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
4550 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
4554 intel_match_token (T_PTR
);
4556 return (intel_e10 () && intel_e09_1 ());
4559 /* e09 : e10 e09' */
4560 else if (cur_token
.code
== ':')
4562 intel_parser
.is_mem
= 1;
4564 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
4579 return (intel_e11 () && intel_e10_1 ());
4585 /* e10' [ expr ] e10' */
4586 if (cur_token
.code
== '[')
4588 intel_match_token ('[');
4589 intel_parser
.is_mem
= 1;
4591 /* Add a '+' to the displacement string if necessary. */
4592 if (*intel_parser
.disp
!= '\0')
4593 strcat (intel_parser
.disp
, "+");
4595 return (intel_expr () && intel_match_token (']') && intel_e10_1 ());
4619 if (cur_token
.code
== '(')
4621 intel_match_token ('(');
4622 strcat (intel_parser
.disp
, "(");
4624 if (intel_expr () && intel_match_token (')'))
4626 strcat (intel_parser
.disp
, ")");
4634 else if (cur_token
.code
== '[')
4636 intel_match_token ('[');
4637 intel_parser
.is_mem
= 1;
4639 /* Operands for jump/call inside brackets denote absolute addresses. */
4640 if (current_templates
->start
->opcode_modifier
& Jump
4641 || current_templates
->start
->opcode_modifier
& JumpDword
4642 || current_templates
->start
->opcode_modifier
& JumpByte
4643 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
4644 i
.types
[this_operand
] |= JumpAbsolute
;
4646 /* Add a '+' to the displacement string if necessary. */
4647 if (*intel_parser
.disp
!= '\0')
4648 strcat (intel_parser
.disp
, "+");
4650 return (intel_expr () && intel_match_token (']'));
4658 else if (cur_token
.code
== T_BYTE
4659 || cur_token
.code
== T_WORD
4660 || cur_token
.code
== T_DWORD
4661 || cur_token
.code
== T_QWORD
4662 || cur_token
.code
== T_XWORD
)
4664 intel_match_token (cur_token
.code
);
4671 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
4673 strcat (intel_parser
.disp
, cur_token
.str
);
4674 intel_match_token (cur_token
.code
);
4675 intel_parser
.is_mem
= 1;
4681 else if (cur_token
.code
== T_REG
)
4683 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
4685 intel_match_token (T_REG
);
4687 /* Check for segment change. */
4688 if (cur_token
.code
== ':')
4690 if (reg
->reg_type
& (SReg2
| SReg3
))
4692 switch (reg
->reg_num
)
4695 i
.seg
[i
.mem_operands
] = &es
;
4698 i
.seg
[i
.mem_operands
] = &cs
;
4701 i
.seg
[i
.mem_operands
] = &ss
;
4704 i
.seg
[i
.mem_operands
] = &ds
;
4707 i
.seg
[i
.mem_operands
] = &fs
;
4710 i
.seg
[i
.mem_operands
] = &gs
;
4716 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
4721 /* Not a segment register. Check for register scaling. */
4722 else if (cur_token
.code
== '*')
4724 if (!intel_parser
.is_mem
)
4726 as_bad (_("Register scaling only allowed in memory operands."));
4730 /* What follows must be a valid scale. */
4731 if (intel_match_token ('*')
4732 && strchr ("01248", *cur_token
.str
))
4735 i
.types
[this_operand
] |= BaseIndex
;
4737 /* Set the scale after setting the register (otherwise,
4738 i386_scale will complain) */
4739 i386_scale (cur_token
.str
);
4740 intel_match_token (T_CONST
);
4744 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4750 /* No scaling. If this is a memory operand, the register is either a
4751 base register (first occurrence) or an index register (second
4753 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
4755 if (i
.base_reg
&& i
.index_reg
)
4757 as_bad (_("Too many register references in memory operand.\n"));
4761 if (i
.base_reg
== NULL
)
4766 i
.types
[this_operand
] |= BaseIndex
;
4769 /* Offset modifier. Add the register to the displacement string to be
4770 parsed as an immediate expression after we're done. */
4771 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
4772 strcat (intel_parser
.disp
, reg
->reg_name
);
4774 /* It's neither base nor index nor offset. */
4777 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
4778 i
.op
[this_operand
].regs
= reg
;
4782 /* Since registers are not part of the displacement string (except
4783 when we're parsing offset operands), we may need to remove any
4784 preceding '+' from the displacement string. */
4785 if (*intel_parser
.disp
!= '\0'
4786 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
4788 char *s
= intel_parser
.disp
;
4789 s
+= strlen (s
) - 1;
4798 else if (cur_token
.code
== T_ID
)
4800 /* Add the identifier to the displacement string. */
4801 strcat (intel_parser
.disp
, cur_token
.str
);
4802 intel_match_token (T_ID
);
4804 /* The identifier represents a memory reference only if it's not
4805 preceded by an offset modifier. */
4806 if (intel_parser
.op_modifier
!= OFFSET_FLAT
4807 && intel_parser
.op_modifier
!= FLAT
)
4808 intel_parser
.is_mem
= 1;
4814 else if (cur_token
.code
== T_CONST
4815 || cur_token
.code
== '-'
4816 || cur_token
.code
== '+')
4820 /* Allow constants that start with `+' or `-'. */
4821 if (cur_token
.code
== '-' || cur_token
.code
== '+')
4823 strcat (intel_parser
.disp
, cur_token
.str
);
4824 intel_match_token (cur_token
.code
);
4825 if (cur_token
.code
!= T_CONST
)
4827 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
4833 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
4834 if (save_str
== NULL
)
4836 strcpy (save_str
, cur_token
.str
);
4838 /* Get the next token to check for register scaling. */
4839 intel_match_token (cur_token
.code
);
4841 /* Check if this constant is a scaling factor for an index register. */
4842 if (cur_token
.code
== '*')
4844 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
4846 if (!intel_parser
.is_mem
)
4848 as_bad (_("Register scaling only allowed in memory operands."));
4852 /* The constant is followed by `* reg', so it must be
4854 if (strchr ("01248", *save_str
))
4856 i
.index_reg
= cur_token
.reg
;
4857 i
.types
[this_operand
] |= BaseIndex
;
4859 /* Set the scale after setting the register (otherwise,
4860 i386_scale will complain) */
4861 i386_scale (save_str
);
4862 intel_match_token (T_REG
);
4864 /* Since registers are not part of the displacement
4865 string, we may need to remove any preceding '+' from
4866 the displacement string. */
4867 if (*intel_parser
.disp
!= '\0')
4869 char *s
= intel_parser
.disp
;
4870 s
+= strlen (s
) - 1;
4883 /* The constant was not used for register scaling. Since we have
4884 already consumed the token following `*' we now need to put it
4885 back in the stream. */
4887 intel_putback_token ();
4890 /* Add the constant to the displacement string. */
4891 strcat (intel_parser
.disp
, save_str
);
4897 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
4901 /* Match the given token against cur_token. If they match, read the next
4902 token from the operand string. */
4904 intel_match_token (code
)
4907 if (cur_token
.code
== code
)
4914 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
4919 /* Read a new token from intel_parser.op_string and store it in cur_token. */
4924 const reg_entry
*reg
;
4925 struct intel_token new_token
;
4927 new_token
.code
= T_NIL
;
4928 new_token
.reg
= NULL
;
4929 new_token
.str
= NULL
;
4931 /* Free the memory allocated to the previous token and move
4932 cur_token to prev_token. */
4934 free (prev_token
.str
);
4936 prev_token
= cur_token
;
4938 /* Skip whitespace. */
4939 while (is_space_char (*intel_parser
.op_string
))
4940 intel_parser
.op_string
++;
4942 /* Return an empty token if we find nothing else on the line. */
4943 if (*intel_parser
.op_string
== '\0')
4945 cur_token
= new_token
;
4949 /* The new token cannot be larger than the remainder of the operand
4951 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
4952 if (new_token
.str
== NULL
)
4954 new_token
.str
[0] = '\0';
4956 if (strchr ("0123456789", *intel_parser
.op_string
))
4958 char *p
= new_token
.str
;
4959 char *q
= intel_parser
.op_string
;
4960 new_token
.code
= T_CONST
;
4962 /* Allow any kind of identifier char to encompass floating point and
4963 hexadecimal numbers. */
4964 while (is_identifier_char (*q
))
4968 /* Recognize special symbol names [0-9][bf]. */
4969 if (strlen (intel_parser
.op_string
) == 2
4970 && (intel_parser
.op_string
[1] == 'b'
4971 || intel_parser
.op_string
[1] == 'f'))
4972 new_token
.code
= T_ID
;
4975 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
4977 new_token
.code
= *intel_parser
.op_string
;
4978 new_token
.str
[0] = *intel_parser
.op_string
;
4979 new_token
.str
[1] = '\0';
4982 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4983 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
4985 new_token
.code
= T_REG
;
4986 new_token
.reg
= reg
;
4988 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
4990 new_token
.str
[0] = REGISTER_PREFIX
;
4991 new_token
.str
[1] = '\0';
4994 strcat (new_token
.str
, reg
->reg_name
);
4997 else if (is_identifier_char (*intel_parser
.op_string
))
4999 char *p
= new_token
.str
;
5000 char *q
= intel_parser
.op_string
;
5002 /* A '.' or '$' followed by an identifier char is an identifier.
5003 Otherwise, it's operator '.' followed by an expression. */
5004 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5006 new_token
.code
= *q
;
5007 new_token
.str
[0] = *q
;
5008 new_token
.str
[1] = '\0';
5012 while (is_identifier_char (*q
) || *q
== '@')
5016 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5017 new_token
.code
= T_BYTE
;
5019 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5020 new_token
.code
= T_WORD
;
5022 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5023 new_token
.code
= T_DWORD
;
5025 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5026 new_token
.code
= T_QWORD
;
5028 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5029 new_token
.code
= T_XWORD
;
5031 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5032 new_token
.code
= T_PTR
;
5034 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5035 new_token
.code
= T_SHORT
;
5037 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5039 new_token
.code
= T_OFFSET
;
5041 /* ??? This is not mentioned in the MASM grammar but gcc
5042 makes use of it with -mintel-syntax. OFFSET may be
5043 followed by FLAT: */
5044 if (strncasecmp (q
, " FLAT:", 6) == 0)
5045 strcat (new_token
.str
, " FLAT:");
5048 /* ??? This is not mentioned in the MASM grammar. */
5049 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5050 new_token
.code
= T_OFFSET
;
5053 new_token
.code
= T_ID
;
5058 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5060 intel_parser
.op_string
+= strlen (new_token
.str
);
5061 cur_token
= new_token
;
5064 /* Put cur_token back into the token stream and make cur_token point to
5067 intel_putback_token ()
5069 intel_parser
.op_string
-= strlen (cur_token
.str
);
5070 free (cur_token
.str
);
5071 cur_token
= prev_token
;
5073 /* Forget prev_token. */
5074 prev_token
.code
= T_NIL
;
5075 prev_token
.reg
= NULL
;
5076 prev_token
.str
= NULL
;