1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c
);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry
*parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_imm_operands (void);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry
*build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS
*, offsetT
);
96 static void output_disp (fragS
*, offsetT
);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
104 static const char *default_arch
= DEFAULT_ARCH
;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry
*regs
;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands
;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 unsigned int types
[MAX_OPERANDS
];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op
[MAX_OPERANDS
];
141 /* Flags for operands. */
142 unsigned int flags
[MAX_OPERANDS
];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry
*base_reg
;
151 const reg_entry
*index_reg
;
152 unsigned int log2_scale_factor
;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry
*seg
[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes
;
161 unsigned char prefix
[MAX_PREFIXES
];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn
;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars
[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars
= "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars
= "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars
[] = "#/";
213 const char line_separator_chars
[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS
[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS
[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars
[256];
226 static char register_chars
[256];
227 static char operand_chars
[256];
228 static char identifier_chars
[256];
229 static char digit_chars
[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack
[32];
247 static char *save_stack_p
;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates
*current_templates
;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
261 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
263 /* Current operand we are working on. */
264 static int this_operand
;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code
;
276 static unsigned int object_64bit
;
277 static int use_rela_relocations
= 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names
[] =
287 /* 1 for intel syntax,
289 static int intel_syntax
= 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg
= 0;
294 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
295 leave, push, and pop instructions so that gcc has the same stack
296 frame as in 32 bit mode. */
297 static char stackop_size
= '\0';
299 /* Non-zero to optimize code alignment. */
300 int optimize_align_code
= 1;
302 /* Non-zero to quieten some warnings. */
303 static int quiet_warnings
= 0;
306 static const char *cpu_arch_name
= NULL
;
307 static const char *cpu_sub_arch_name
= NULL
;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
312 /* If we have selected a cpu we are generating instructions for. */
313 static int cpu_arch_tune_set
= 0;
315 /* Cpu we are generating instructions for. */
316 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
318 /* CPU feature flags of cpu we are generating instructions for. */
319 static unsigned int cpu_arch_tune_flags
= 0;
321 /* CPU instruction set architecture used. */
322 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
324 /* CPU feature flags of instruction set architecture used. */
325 static unsigned int cpu_arch_isa_flags
= 0;
327 /* If set, conditional jumps are not automatically promoted to handle
328 larger than a byte offset. */
329 static unsigned int no_cond_jump_promotion
= 0;
331 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
332 static symbolS
*GOT_symbol
;
334 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
335 unsigned int x86_dwarf2_return_column
;
337 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
338 int x86_cie_data_alignment
;
340 /* Interface to relax_segment.
341 There are 3 major relax states for 386 jump insns because the
342 different types of jumps add different sizes to frags when we're
343 figuring out what sort of jump to choose to reach a given label. */
346 #define UNCOND_JUMP 0
348 #define COND_JUMP86 2
353 #define SMALL16 (SMALL | CODE16)
355 #define BIG16 (BIG | CODE16)
359 #define INLINE __inline__
365 #define ENCODE_RELAX_STATE(type, size) \
366 ((relax_substateT) (((type) << 2) | (size)))
367 #define TYPE_FROM_RELAX_STATE(s) \
369 #define DISP_SIZE_FROM_RELAX_STATE(s) \
370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
372 /* This table is used by relax_frag to promote short jumps to long
373 ones where necessary. SMALL (short) jumps may be promoted to BIG
374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
375 don't allow a short jump in a 32 bit code segment to be promoted to
376 a 16 bit offset jump because it's slower (requires data size
377 prefix), and doesn't work, unless the destination is in the bottom
378 64k of the code segment (The top 16 bits of eip are zeroed). */
380 const relax_typeS md_relax_table
[] =
383 1) most positive reach of this state,
384 2) most negative reach of this state,
385 3) how many bytes this mode will have in the variable part of the frag
386 4) which index into the table to try if we can't fit into this one. */
388 /* UNCOND_JUMP states. */
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
391 /* dword jmp adds 4 bytes to frag:
392 0 extra opcode bytes, 4 displacement bytes. */
394 /* word jmp adds 2 byte2 to frag:
395 0 extra opcode bytes, 2 displacement bytes. */
398 /* COND_JUMP states. */
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
401 /* dword conditionals adds 5 bytes to frag:
402 1 extra opcode byte, 4 displacement bytes. */
404 /* word conditionals add 3 bytes to frag:
405 1 extra opcode byte, 2 displacement bytes. */
408 /* COND_JUMP86 states. */
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
411 /* dword conditionals adds 5 bytes to frag:
412 1 extra opcode byte, 4 displacement bytes. */
414 /* word conditionals add 4 bytes to frag:
415 1 displacement byte and a 3 byte long branch insn. */
419 static const arch_entry cpu_arch
[] =
421 {"generic32", PROCESSOR_GENERIC32
,
422 Cpu186
|Cpu286
|Cpu386
},
423 {"generic64", PROCESSOR_GENERIC64
,
424 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
425 |CpuMMX2
|CpuSSE
|CpuSSE2
},
426 {"i8086", PROCESSOR_UNKNOWN
,
428 {"i186", PROCESSOR_UNKNOWN
,
430 {"i286", PROCESSOR_UNKNOWN
,
432 {"i386", PROCESSOR_GENERIC32
,
433 Cpu186
|Cpu286
|Cpu386
},
434 {"i486", PROCESSOR_I486
,
435 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
436 {"i586", PROCESSOR_PENTIUM
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
438 {"i686", PROCESSOR_PENTIUMPRO
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
440 {"pentium", PROCESSOR_PENTIUM
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
442 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
444 {"pentiumii", PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
446 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
448 {"pentium4", PROCESSOR_PENTIUM4
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
450 |CpuMMX2
|CpuSSE
|CpuSSE2
},
451 {"prescott", PROCESSOR_NOCONA
,
452 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
453 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
454 {"nocona", PROCESSOR_NOCONA
,
455 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
456 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
457 {"yonah", PROCESSOR_CORE
,
458 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
459 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
460 {"core", PROCESSOR_CORE
,
461 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
462 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
463 {"merom", PROCESSOR_CORE2
,
464 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
465 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
466 {"core2", PROCESSOR_CORE2
,
467 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
468 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
470 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
471 {"k6_2", PROCESSOR_K6
,
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
473 {"athlon", PROCESSOR_ATHLON
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
475 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
476 {"sledgehammer", PROCESSOR_K8
,
477 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
478 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
479 {"opteron", PROCESSOR_K8
,
480 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
481 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
483 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
484 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 {"amdfam10", PROCESSOR_AMDFAM10
,
486 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
487 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
489 {".mmx", PROCESSOR_UNKNOWN
,
491 {".sse", PROCESSOR_UNKNOWN
,
492 CpuMMX
|CpuMMX2
|CpuSSE
},
493 {".sse2", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
495 {".sse3", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
497 {".ssse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
499 {".3dnow", PROCESSOR_UNKNOWN
,
501 {".3dnowa", PROCESSOR_UNKNOWN
,
502 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
503 {".padlock", PROCESSOR_UNKNOWN
,
505 {".pacifica", PROCESSOR_UNKNOWN
,
507 {".svme", PROCESSOR_UNKNOWN
,
509 {".sse4a", PROCESSOR_UNKNOWN
,
510 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
511 {".abm", PROCESSOR_UNKNOWN
,
515 const pseudo_typeS md_pseudo_table
[] =
517 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
518 {"align", s_align_bytes
, 0},
520 {"align", s_align_ptwo
, 0},
522 {"arch", set_cpu_arch
, 0},
526 {"ffloat", float_cons
, 'f'},
527 {"dfloat", float_cons
, 'd'},
528 {"tfloat", float_cons
, 'x'},
530 {"slong", signed_cons
, 4},
531 {"noopt", s_ignore
, 0},
532 {"optim", s_ignore
, 0},
533 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
534 {"code16", set_code_flag
, CODE_16BIT
},
535 {"code32", set_code_flag
, CODE_32BIT
},
536 {"code64", set_code_flag
, CODE_64BIT
},
537 {"intel_syntax", set_intel_syntax
, 1},
538 {"att_syntax", set_intel_syntax
, 0},
539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common
, 0},
542 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
543 {"loc", dwarf2_directive_loc
, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
547 {"secrel32", pe_directive_secrel
, 0},
552 /* For interface with expression (). */
553 extern char *input_line_pointer
;
555 /* Hash table for instruction mnemonic lookup. */
556 static struct hash_control
*op_hash
;
558 /* Hash table for register lookup. */
559 static struct hash_control
*reg_hash
;
562 i386_align_code (fragS
*fragP
, int count
)
564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
567 static const char f32_1
[] =
569 static const char f32_2
[] =
570 {0x66,0x90}; /* xchg %ax,%ax */
571 static const char f32_3
[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4
[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5
[] =
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6
[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7
[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8
[] =
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9
[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10
[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11
[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12
[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13
[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14
[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_15
[] =
604 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
605 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
606 static const char f16_3
[] =
607 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
608 static const char f16_4
[] =
609 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_5
[] =
612 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_6
[] =
614 {0x89,0xf6, /* mov %si,%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_7
[] =
617 {0x8d,0x74,0x00, /* lea 0(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_8
[] =
620 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char *const f32_patt
[] = {
623 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
624 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
626 static const char *const f16_patt
[] = {
627 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
628 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
631 static const char alt_3
[] =
633 /* nopl 0(%[re]ax) */
634 static const char alt_4
[] =
635 {0x0f,0x1f,0x40,0x00};
636 /* nopl 0(%[re]ax,%[re]ax,1) */
637 static const char alt_5
[] =
638 {0x0f,0x1f,0x44,0x00,0x00};
639 /* nopw 0(%[re]ax,%[re]ax,1) */
640 static const char alt_6
[] =
641 {0x66,0x0f,0x1f,0x44,0x00,0x00};
642 /* nopl 0L(%[re]ax) */
643 static const char alt_7
[] =
644 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
645 /* nopl 0L(%[re]ax,%[re]ax,1) */
646 static const char alt_8
[] =
647 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
648 /* nopw 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_9
[] =
650 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
652 static const char alt_10
[] =
653 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_long_11
[] =
658 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
661 nopw %cs:0L(%[re]ax,%[re]ax,1) */
662 static const char alt_long_12
[] =
665 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_13
[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
679 nopw %cs:0L(%[re]ax,%[re]ax,1) */
680 static const char alt_long_14
[] =
685 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
691 nopw %cs:0L(%[re]ax,%[re]ax,1) */
692 static const char alt_long_15
[] =
698 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 /* nopl 0(%[re]ax,%[re]ax,1)
700 nopw 0(%[re]ax,%[re]ax,1) */
701 static const char alt_short_11
[] =
702 {0x0f,0x1f,0x44,0x00,0x00,
703 0x66,0x0f,0x1f,0x44,0x00,0x00};
704 /* nopw 0(%[re]ax,%[re]ax,1)
705 nopw 0(%[re]ax,%[re]ax,1) */
706 static const char alt_short_12
[] =
707 {0x66,0x0f,0x1f,0x44,0x00,0x00,
708 0x66,0x0f,0x1f,0x44,0x00,0x00};
709 /* nopw 0(%[re]ax,%[re]ax,1)
711 static const char alt_short_13
[] =
712 {0x66,0x0f,0x1f,0x44,0x00,0x00,
713 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
716 static const char alt_short_14
[] =
717 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
718 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 nopl 0L(%[re]ax,%[re]ax,1) */
721 static const char alt_short_15
[] =
722 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
723 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
724 static const char *const alt_short_patt
[] = {
725 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
726 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
727 alt_short_14
, alt_short_15
729 static const char *const alt_long_patt
[] = {
730 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
731 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
732 alt_long_14
, alt_long_15
735 if (count
<= 0 || count
> 15)
738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
741 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
742 f32_patt will be used.
743 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
744 3. For PROCESSOR_CORE2, alt_long_patt will be used.
745 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
747 and PROCESSOR_GENERIC64, alt_short_patt will be used.
749 When -mtune= isn't used, alt_short_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
752 When -march= or .arch is used, we can't use anything beyond
753 cpu_arch_isa_flags. */
755 if (flag_code
== CODE_16BIT
)
757 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
758 f16_patt
[count
- 1], count
);
760 /* Adjust jump offset. */
761 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
763 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
766 int nnops
= (count
+ 3) / 4;
767 int len
= count
/ nnops
;
768 int remains
= count
- nnops
* len
;
771 /* The recommended way to pad 64bit code is to use NOPs preceded
772 by maximally four 0x66 prefixes. Balance the size of nops. */
773 for (i
= 0; i
< remains
; i
++)
775 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
776 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
779 for (; i
< nnops
; i
++)
781 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
782 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
788 const char *const *patt
= NULL
;
790 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
792 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
793 switch (cpu_arch_tune
)
795 case PROCESSOR_UNKNOWN
:
796 /* We use cpu_arch_isa_flags to check if we SHOULD
797 optimize for Cpu686. */
798 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
799 patt
= alt_short_patt
;
803 case PROCESSOR_CORE2
:
804 patt
= alt_long_patt
;
806 case PROCESSOR_PENTIUMPRO
:
807 case PROCESSOR_PENTIUM4
:
808 case PROCESSOR_NOCONA
:
811 case PROCESSOR_ATHLON
:
813 case PROCESSOR_GENERIC64
:
814 case PROCESSOR_AMDFAM10
:
815 patt
= alt_short_patt
;
818 case PROCESSOR_PENTIUM
:
819 case PROCESSOR_GENERIC32
:
826 switch (cpu_arch_tune
)
828 case PROCESSOR_UNKNOWN
:
829 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
830 PROCESSOR_UNKNOWN. */
835 case PROCESSOR_PENTIUM
:
836 case PROCESSOR_PENTIUMPRO
:
837 case PROCESSOR_PENTIUM4
:
838 case PROCESSOR_NOCONA
:
841 case PROCESSOR_ATHLON
:
843 case PROCESSOR_AMDFAM10
:
844 case PROCESSOR_GENERIC32
:
845 /* We use cpu_arch_isa_flags to check if we CAN optimize
847 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
848 patt
= alt_short_patt
;
852 case PROCESSOR_CORE2
:
853 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
854 patt
= alt_long_patt
;
858 case PROCESSOR_GENERIC64
:
859 patt
= alt_short_patt
;
864 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
865 patt
[count
- 1], count
);
867 fragP
->fr_var
= count
;
870 static INLINE
unsigned int
871 mode_from_disp_size (unsigned int t
)
873 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
877 fits_in_signed_byte (offsetT num
)
879 return (num
>= -128) && (num
<= 127);
883 fits_in_unsigned_byte (offsetT num
)
885 return (num
& 0xff) == num
;
889 fits_in_unsigned_word (offsetT num
)
891 return (num
& 0xffff) == num
;
895 fits_in_signed_word (offsetT num
)
897 return (-32768 <= num
) && (num
<= 32767);
901 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
906 return (!(((offsetT
) -1 << 31) & num
)
907 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
909 } /* fits_in_signed_long() */
912 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
917 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
919 } /* fits_in_unsigned_long() */
922 smallest_imm_type (offsetT num
)
924 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
926 /* This code is disabled on the 486 because all the Imm1 forms
927 in the opcode table are slower on the i486. They're the
928 versions with the implicitly specified single-position
929 displacement, which has another syntax if you really want to
932 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
934 return (fits_in_signed_byte (num
)
935 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
936 : fits_in_unsigned_byte (num
)
937 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
938 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
939 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
940 : fits_in_signed_long (num
)
941 ? (Imm32
| Imm32S
| Imm64
)
942 : fits_in_unsigned_long (num
)
948 offset_in_range (offsetT val
, int size
)
954 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
955 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
956 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
958 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
963 /* If BFD64, sign extend val. */
964 if (!use_rela_relocations
)
965 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
966 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
968 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
970 char buf1
[40], buf2
[40];
972 sprint_value (buf1
, val
);
973 sprint_value (buf2
, val
& mask
);
974 as_warn (_("%s shortened to %s"), buf1
, buf2
);
979 /* Returns 0 if attempting to add a prefix where one from the same
980 class already exists, 1 if non rep/repne added, 2 if rep/repne
983 add_prefix (unsigned int prefix
)
988 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
989 && flag_code
== CODE_64BIT
)
991 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
992 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
993 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
1004 case CS_PREFIX_OPCODE
:
1005 case DS_PREFIX_OPCODE
:
1006 case ES_PREFIX_OPCODE
:
1007 case FS_PREFIX_OPCODE
:
1008 case GS_PREFIX_OPCODE
:
1009 case SS_PREFIX_OPCODE
:
1013 case REPNE_PREFIX_OPCODE
:
1014 case REPE_PREFIX_OPCODE
:
1017 case LOCK_PREFIX_OPCODE
:
1025 case ADDR_PREFIX_OPCODE
:
1029 case DATA_PREFIX_OPCODE
:
1033 if (i
.prefix
[q
] != 0)
1041 i
.prefix
[q
] |= prefix
;
1044 as_bad (_("same type of prefix used twice"));
1050 set_code_flag (int value
)
1053 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1054 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1055 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1057 as_bad (_("64bit mode not supported on this CPU."));
1059 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1061 as_bad (_("32bit mode not supported on this CPU."));
1063 stackop_size
= '\0';
1067 set_16bit_gcc_code_flag (int new_code_flag
)
1069 flag_code
= new_code_flag
;
1070 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1071 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1072 stackop_size
= LONG_MNEM_SUFFIX
;
1076 set_intel_syntax (int syntax_flag
)
1078 /* Find out if register prefixing is specified. */
1079 int ask_naked_reg
= 0;
1082 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1084 char *string
= input_line_pointer
;
1085 int e
= get_symbol_end ();
1087 if (strcmp (string
, "prefix") == 0)
1089 else if (strcmp (string
, "noprefix") == 0)
1092 as_bad (_("bad argument to syntax directive."));
1093 *input_line_pointer
= e
;
1095 demand_empty_rest_of_line ();
1097 intel_syntax
= syntax_flag
;
1099 if (ask_naked_reg
== 0)
1100 allow_naked_reg
= (intel_syntax
1101 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1103 allow_naked_reg
= (ask_naked_reg
< 0);
1105 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1106 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1110 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1114 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1116 char *string
= input_line_pointer
;
1117 int e
= get_symbol_end ();
1120 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1122 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1126 cpu_arch_name
= cpu_arch
[i
].name
;
1127 cpu_sub_arch_name
= NULL
;
1128 cpu_arch_flags
= (cpu_arch
[i
].flags
1129 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
1130 cpu_arch_isa
= cpu_arch
[i
].type
;
1131 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1132 if (!cpu_arch_tune_set
)
1134 cpu_arch_tune
= cpu_arch_isa
;
1135 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1139 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1141 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1142 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1144 *input_line_pointer
= e
;
1145 demand_empty_rest_of_line ();
1149 if (i
>= ARRAY_SIZE (cpu_arch
))
1150 as_bad (_("no such architecture: `%s'"), string
);
1152 *input_line_pointer
= e
;
1155 as_bad (_("missing cpu architecture"));
1157 no_cond_jump_promotion
= 0;
1158 if (*input_line_pointer
== ','
1159 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1161 char *string
= ++input_line_pointer
;
1162 int e
= get_symbol_end ();
1164 if (strcmp (string
, "nojumps") == 0)
1165 no_cond_jump_promotion
= 1;
1166 else if (strcmp (string
, "jumps") == 0)
1169 as_bad (_("no such architecture modifier: `%s'"), string
);
1171 *input_line_pointer
= e
;
1174 demand_empty_rest_of_line ();
1180 if (!strcmp (default_arch
, "x86_64"))
1181 return bfd_mach_x86_64
;
1182 else if (!strcmp (default_arch
, "i386"))
1183 return bfd_mach_i386_i386
;
1185 as_fatal (_("Unknown architecture"));
1191 const char *hash_err
;
1193 /* Initialize op_hash hash table. */
1194 op_hash
= hash_new ();
1197 const template *optab
;
1198 templates
*core_optab
;
1200 /* Setup for loop. */
1202 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1203 core_optab
->start
= optab
;
1208 if (optab
->name
== NULL
1209 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1211 /* different name --> ship out current template list;
1212 add to hash table; & begin anew. */
1213 core_optab
->end
= optab
;
1214 hash_err
= hash_insert (op_hash
,
1219 as_fatal (_("Internal Error: Can't hash %s: %s"),
1223 if (optab
->name
== NULL
)
1225 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1226 core_optab
->start
= optab
;
1231 /* Initialize reg_hash hash table. */
1232 reg_hash
= hash_new ();
1234 const reg_entry
*regtab
;
1236 for (regtab
= i386_regtab
;
1237 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
1240 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1242 as_fatal (_("Internal Error: Can't hash %s: %s"),
1248 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1253 for (c
= 0; c
< 256; c
++)
1258 mnemonic_chars
[c
] = c
;
1259 register_chars
[c
] = c
;
1260 operand_chars
[c
] = c
;
1262 else if (ISLOWER (c
))
1264 mnemonic_chars
[c
] = c
;
1265 register_chars
[c
] = c
;
1266 operand_chars
[c
] = c
;
1268 else if (ISUPPER (c
))
1270 mnemonic_chars
[c
] = TOLOWER (c
);
1271 register_chars
[c
] = mnemonic_chars
[c
];
1272 operand_chars
[c
] = c
;
1275 if (ISALPHA (c
) || ISDIGIT (c
))
1276 identifier_chars
[c
] = c
;
1279 identifier_chars
[c
] = c
;
1280 operand_chars
[c
] = c
;
1285 identifier_chars
['@'] = '@';
1288 identifier_chars
['?'] = '?';
1289 operand_chars
['?'] = '?';
1291 digit_chars
['-'] = '-';
1292 mnemonic_chars
['-'] = '-';
1293 identifier_chars
['_'] = '_';
1294 identifier_chars
['.'] = '.';
1296 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1297 operand_chars
[(unsigned char) *p
] = *p
;
1300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1303 record_alignment (text_section
, 2);
1304 record_alignment (data_section
, 2);
1305 record_alignment (bss_section
, 2);
1309 if (flag_code
== CODE_64BIT
)
1311 x86_dwarf2_return_column
= 16;
1312 x86_cie_data_alignment
= -8;
1316 x86_dwarf2_return_column
= 8;
1317 x86_cie_data_alignment
= -4;
1322 i386_print_statistics (FILE *file
)
1324 hash_print_statistics (file
, "i386 opcode", op_hash
);
1325 hash_print_statistics (file
, "i386 register", reg_hash
);
1330 /* Debugging routines for md_assemble. */
1331 static void pte (template *);
1332 static void pt (unsigned int);
1333 static void pe (expressionS
*);
1334 static void ps (symbolS
*);
1337 pi (char *line
, i386_insn
*x
)
1341 fprintf (stdout
, "%s: template ", line
);
1343 fprintf (stdout
, " address: base %s index %s scale %x\n",
1344 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1345 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1346 x
->log2_scale_factor
);
1347 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1348 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1349 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1350 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1351 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1352 (x
->rex
& REX_MODE64
) != 0,
1353 (x
->rex
& REX_EXTX
) != 0,
1354 (x
->rex
& REX_EXTY
) != 0,
1355 (x
->rex
& REX_EXTZ
) != 0);
1356 for (i
= 0; i
< x
->operands
; i
++)
1358 fprintf (stdout
, " #%d: ", i
+ 1);
1360 fprintf (stdout
, "\n");
1362 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1363 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1364 if (x
->types
[i
] & Imm
)
1366 if (x
->types
[i
] & Disp
)
1367 pe (x
->op
[i
].disps
);
1375 fprintf (stdout
, " %d operands ", t
->operands
);
1376 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1377 if (t
->extension_opcode
!= None
)
1378 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1379 if (t
->opcode_modifier
& D
)
1380 fprintf (stdout
, "D");
1381 if (t
->opcode_modifier
& W
)
1382 fprintf (stdout
, "W");
1383 fprintf (stdout
, "\n");
1384 for (i
= 0; i
< t
->operands
; i
++)
1386 fprintf (stdout
, " #%d type ", i
+ 1);
1387 pt (t
->operand_types
[i
]);
1388 fprintf (stdout
, "\n");
1395 fprintf (stdout
, " operation %d\n", e
->X_op
);
1396 fprintf (stdout
, " add_number %ld (%lx)\n",
1397 (long) e
->X_add_number
, (long) e
->X_add_number
);
1398 if (e
->X_add_symbol
)
1400 fprintf (stdout
, " add_symbol ");
1401 ps (e
->X_add_symbol
);
1402 fprintf (stdout
, "\n");
1406 fprintf (stdout
, " op_symbol ");
1407 ps (e
->X_op_symbol
);
1408 fprintf (stdout
, "\n");
1415 fprintf (stdout
, "%s type %s%s",
1417 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1418 segment_name (S_GET_SEGMENT (s
)));
1421 static struct type_name
1426 const type_names
[] =
1439 { BaseIndex
, "BaseIndex" },
1443 { Disp32S
, "d32s" },
1445 { InOutPortReg
, "InOutPortReg" },
1446 { ShiftCount
, "ShiftCount" },
1447 { Control
, "control reg" },
1448 { Test
, "test reg" },
1449 { Debug
, "debug reg" },
1450 { FloatReg
, "FReg" },
1451 { FloatAcc
, "FAcc" },
1455 { JumpAbsolute
, "Jump Absolute" },
1466 const struct type_name
*ty
;
1468 for (ty
= type_names
; ty
->mask
; ty
++)
1470 fprintf (stdout
, "%s, ", ty
->tname
);
1474 #endif /* DEBUG386 */
1476 static bfd_reloc_code_real_type
1477 reloc (unsigned int size
,
1480 bfd_reloc_code_real_type other
)
1482 if (other
!= NO_RELOC
)
1484 reloc_howto_type
*reloc
;
1489 case BFD_RELOC_X86_64_GOT32
:
1490 return BFD_RELOC_X86_64_GOT64
;
1492 case BFD_RELOC_X86_64_PLTOFF64
:
1493 return BFD_RELOC_X86_64_PLTOFF64
;
1495 case BFD_RELOC_X86_64_GOTPC32
:
1496 other
= BFD_RELOC_X86_64_GOTPC64
;
1498 case BFD_RELOC_X86_64_GOTPCREL
:
1499 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1501 case BFD_RELOC_X86_64_TPOFF32
:
1502 other
= BFD_RELOC_X86_64_TPOFF64
;
1504 case BFD_RELOC_X86_64_DTPOFF32
:
1505 other
= BFD_RELOC_X86_64_DTPOFF64
;
1511 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1512 if (size
== 4 && flag_code
!= CODE_64BIT
)
1515 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1517 as_bad (_("unknown relocation (%u)"), other
);
1518 else if (size
!= bfd_get_reloc_size (reloc
))
1519 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1520 bfd_get_reloc_size (reloc
),
1522 else if (pcrel
&& !reloc
->pc_relative
)
1523 as_bad (_("non-pc-relative relocation for pc-relative field"));
1524 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1526 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1528 as_bad (_("relocated field and relocation type differ in signedness"));
1537 as_bad (_("there are no unsigned pc-relative relocations"));
1540 case 1: return BFD_RELOC_8_PCREL
;
1541 case 2: return BFD_RELOC_16_PCREL
;
1542 case 4: return BFD_RELOC_32_PCREL
;
1543 case 8: return BFD_RELOC_64_PCREL
;
1545 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1552 case 4: return BFD_RELOC_X86_64_32S
;
1557 case 1: return BFD_RELOC_8
;
1558 case 2: return BFD_RELOC_16
;
1559 case 4: return BFD_RELOC_32
;
1560 case 8: return BFD_RELOC_64
;
1562 as_bad (_("cannot do %s %u byte relocation"),
1563 sign
> 0 ? "signed" : "unsigned", size
);
1567 return BFD_RELOC_NONE
;
1570 /* Here we decide which fixups can be adjusted to make them relative to
1571 the beginning of the section instead of the symbol. Basically we need
1572 to make sure that the dynamic relocations are done correctly, so in
1573 some cases we force the original symbol to be used. */
1576 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1578 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1582 /* Don't adjust pc-relative references to merge sections in 64-bit
1584 if (use_rela_relocations
1585 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1589 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1590 and changed later by validate_fix. */
1591 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1592 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1595 /* adjust_reloc_syms doesn't know about the GOT. */
1596 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1597 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1598 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1599 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1600 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1601 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1602 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1603 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1604 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1606 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1607 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1608 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1609 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1610 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1611 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1612 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1613 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1622 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1623 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1630 intel_float_operand (const char *mnemonic
)
1632 /* Note that the value returned is meaningful only for opcodes with (memory)
1633 operands, hence the code here is free to improperly handle opcodes that
1634 have no operands (for better performance and smaller code). */
1636 if (mnemonic
[0] != 'f')
1637 return 0; /* non-math */
1639 switch (mnemonic
[1])
1641 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1642 the fs segment override prefix not currently handled because no
1643 call path can make opcodes without operands get here */
1645 return 2 /* integer op */;
1647 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1648 return 3; /* fldcw/fldenv */
1651 if (mnemonic
[2] != 'o' /* fnop */)
1652 return 3; /* non-waiting control op */
1655 if (mnemonic
[2] == 's')
1656 return 3; /* frstor/frstpm */
1659 if (mnemonic
[2] == 'a')
1660 return 3; /* fsave */
1661 if (mnemonic
[2] == 't')
1663 switch (mnemonic
[3])
1665 case 'c': /* fstcw */
1666 case 'd': /* fstdw */
1667 case 'e': /* fstenv */
1668 case 's': /* fsts[gw] */
1674 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1675 return 0; /* fxsave/fxrstor are not really math ops */
1682 /* This is the guts of the machine-dependent assembler. LINE points to a
1683 machine dependent instruction. This function is supposed to emit
1684 the frags/bytes it assembles to. */
1691 char mnemonic
[MAX_MNEM_SIZE
];
1693 /* Initialize globals. */
1694 memset (&i
, '\0', sizeof (i
));
1695 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1696 i
.reloc
[j
] = NO_RELOC
;
1697 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1698 memset (im_expressions
, '\0', sizeof (im_expressions
));
1699 save_stack_p
= save_stack
;
1701 /* First parse an instruction mnemonic & call i386_operand for the operands.
1702 We assume that the scrubber has arranged it so that line[0] is the valid
1703 start of a (possibly prefixed) mnemonic. */
1705 line
= parse_insn (line
, mnemonic
);
1709 line
= parse_operands (line
, mnemonic
);
1713 /* The order of the immediates should be reversed
1714 for 2 immediates extrq and insertq instructions */
1715 if ((i
.imm_operands
== 2) &&
1716 ((strcmp (mnemonic
, "extrq") == 0)
1717 || (strcmp (mnemonic
, "insertq") == 0)))
1719 swap_imm_operands ();
1720 /* "extrq" and insertq" are the only two instructions whose operands
1721 have to be reversed even though they have two immediate operands.
1727 /* Now we've parsed the mnemonic into a set of templates, and have the
1728 operands at hand. */
1730 /* All intel opcodes have reversed operands except for "bound" and
1731 "enter". We also don't reverse intersegment "jmp" and "call"
1732 instructions with 2 immediate operands so that the immediate segment
1733 precedes the offset, as it does when in AT&T mode. */
1734 if (intel_syntax
&& i
.operands
> 1
1735 && (strcmp (mnemonic
, "bound") != 0)
1736 && (strcmp (mnemonic
, "invlpga") != 0)
1737 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1743 /* Don't optimize displacement for movabs since it only takes 64bit
1746 && (flag_code
!= CODE_64BIT
1747 || strcmp (mnemonic
, "movabs") != 0))
1750 /* Next, we find a template that matches the given insn,
1751 making sure the overlap of the given operands types is consistent
1752 with the template operand types. */
1754 if (!match_template ())
1759 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1761 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1762 i
.tm
.base_opcode
^= FloatR
;
1764 /* Zap movzx and movsx suffix. The suffix may have been set from
1765 "word ptr" or "byte ptr" on the source operand, but we'll use
1766 the suffix later to choose the destination register. */
1767 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1769 if (i
.reg_operands
< 2
1771 && (~i
.tm
.opcode_modifier
1778 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1784 if (i
.tm
.opcode_modifier
& FWait
)
1785 if (!add_prefix (FWAIT_OPCODE
))
1788 /* Check string instruction segment overrides. */
1789 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1791 if (!check_string ())
1795 if (!process_suffix ())
1798 /* Make still unresolved immediate matches conform to size of immediate
1799 given in i.suffix. */
1800 if (!finalize_imm ())
1803 if (i
.types
[0] & Imm1
)
1804 i
.imm_operands
= 0; /* kludge for shift insns. */
1805 if (i
.types
[0] & ImplicitRegister
)
1807 if (i
.types
[1] & ImplicitRegister
)
1809 if (i
.types
[2] & ImplicitRegister
)
1812 if (i
.tm
.opcode_modifier
& ImmExt
)
1816 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1818 /* Streaming SIMD extensions 3 Instructions have the fixed
1819 operands with an opcode suffix which is coded in the same
1820 place as an 8-bit immediate field would be. Here we check
1821 those operands and remove them afterwards. */
1824 for (x
= 0; x
< i
.operands
; x
++)
1825 if (i
.op
[x
].regs
->reg_num
!= x
)
1826 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1827 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1831 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1832 opcode suffix which is coded in the same place as an 8-bit
1833 immediate field would be. Here we fake an 8-bit immediate
1834 operand from the opcode suffix stored in tm.extension_opcode. */
1836 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1838 exp
= &im_expressions
[i
.imm_operands
++];
1839 i
.op
[i
.operands
].imms
= exp
;
1840 i
.types
[i
.operands
++] = Imm8
;
1841 exp
->X_op
= O_constant
;
1842 exp
->X_add_number
= i
.tm
.extension_opcode
;
1843 i
.tm
.extension_opcode
= None
;
1846 /* For insns with operands there are more diddles to do to the opcode. */
1849 if (!process_operands ())
1852 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1854 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1855 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1858 /* Handle conversion of 'int $3' --> special int3 insn. */
1859 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1861 i
.tm
.base_opcode
= INT3_OPCODE
;
1865 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1866 && i
.op
[0].disps
->X_op
== O_constant
)
1868 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1869 the absolute address given by the constant. Since ix86 jumps and
1870 calls are pc relative, we need to generate a reloc. */
1871 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1872 i
.op
[0].disps
->X_op
= O_symbol
;
1875 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1876 i
.rex
|= REX_MODE64
;
1878 /* For 8 bit registers we need an empty rex prefix. Also if the
1879 instruction already has a prefix, we need to convert old
1880 registers to new ones. */
1882 if (((i
.types
[0] & Reg8
) != 0
1883 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1884 || ((i
.types
[1] & Reg8
) != 0
1885 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1886 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1891 i
.rex
|= REX_OPCODE
;
1892 for (x
= 0; x
< 2; x
++)
1894 /* Look for 8 bit operand that uses old registers. */
1895 if ((i
.types
[x
] & Reg8
) != 0
1896 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1898 /* In case it is "hi" register, give up. */
1899 if (i
.op
[x
].regs
->reg_num
> 3)
1900 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1901 i
.op
[x
].regs
->reg_name
);
1903 /* Otherwise it is equivalent to the extended register.
1904 Since the encoding doesn't change this is merely
1905 cosmetic cleanup for debug output. */
1907 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1913 add_prefix (REX_OPCODE
| i
.rex
);
1915 /* We are ready to output the insn. */
1920 parse_insn (char *line
, char *mnemonic
)
1923 char *token_start
= l
;
1928 /* Non-zero if we found a prefix only acceptable with string insns. */
1929 const char *expecting_string_instruction
= NULL
;
1934 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1937 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1939 as_bad (_("no such instruction: `%s'"), token_start
);
1944 if (!is_space_char (*l
)
1945 && *l
!= END_OF_INSN
1947 || (*l
!= PREFIX_SEPARATOR
1950 as_bad (_("invalid character %s in mnemonic"),
1951 output_invalid (*l
));
1954 if (token_start
== l
)
1956 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1957 as_bad (_("expecting prefix; got nothing"));
1959 as_bad (_("expecting mnemonic; got nothing"));
1963 /* Look up instruction (or prefix) via hash table. */
1964 current_templates
= hash_find (op_hash
, mnemonic
);
1966 if (*l
!= END_OF_INSN
1967 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1968 && current_templates
1969 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1971 if (current_templates
->start
->cpu_flags
1972 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1974 as_bad ((flag_code
!= CODE_64BIT
1975 ? _("`%s' is only supported in 64-bit mode")
1976 : _("`%s' is not supported in 64-bit mode")),
1977 current_templates
->start
->name
);
1980 /* If we are in 16-bit mode, do not allow addr16 or data16.
1981 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1982 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1983 && flag_code
!= CODE_64BIT
1984 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1985 ^ (flag_code
== CODE_16BIT
)))
1987 as_bad (_("redundant %s prefix"),
1988 current_templates
->start
->name
);
1991 /* Add prefix, checking for repeated prefixes. */
1992 switch (add_prefix (current_templates
->start
->base_opcode
))
1997 expecting_string_instruction
= current_templates
->start
->name
;
2000 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2007 if (!current_templates
)
2009 /* See if we can get a match by trimming off a suffix. */
2012 case WORD_MNEM_SUFFIX
:
2013 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2014 i
.suffix
= SHORT_MNEM_SUFFIX
;
2016 case BYTE_MNEM_SUFFIX
:
2017 case QWORD_MNEM_SUFFIX
:
2018 i
.suffix
= mnem_p
[-1];
2020 current_templates
= hash_find (op_hash
, mnemonic
);
2022 case SHORT_MNEM_SUFFIX
:
2023 case LONG_MNEM_SUFFIX
:
2026 i
.suffix
= mnem_p
[-1];
2028 current_templates
= hash_find (op_hash
, mnemonic
);
2036 if (intel_float_operand (mnemonic
) == 1)
2037 i
.suffix
= SHORT_MNEM_SUFFIX
;
2039 i
.suffix
= LONG_MNEM_SUFFIX
;
2041 current_templates
= hash_find (op_hash
, mnemonic
);
2045 if (!current_templates
)
2047 as_bad (_("no such instruction: `%s'"), token_start
);
2052 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2054 /* Check for a branch hint. We allow ",pt" and ",pn" for
2055 predict taken and predict not taken respectively.
2056 I'm not sure that branch hints actually do anything on loop
2057 and jcxz insns (JumpByte) for current Pentium4 chips. They
2058 may work in the future and it doesn't hurt to accept them
2060 if (l
[0] == ',' && l
[1] == 'p')
2064 if (!add_prefix (DS_PREFIX_OPCODE
))
2068 else if (l
[2] == 'n')
2070 if (!add_prefix (CS_PREFIX_OPCODE
))
2076 /* Any other comma loses. */
2079 as_bad (_("invalid character %s in mnemonic"),
2080 output_invalid (*l
));
2084 /* Check if instruction is supported on specified architecture. */
2086 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2088 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2089 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2091 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2094 if (!(supported
& 2))
2096 as_bad (flag_code
== CODE_64BIT
2097 ? _("`%s' is not supported in 64-bit mode")
2098 : _("`%s' is only supported in 64-bit mode"),
2099 current_templates
->start
->name
);
2102 if (!(supported
& 1))
2104 as_warn (_("`%s' is not supported on `%s%s'"),
2105 current_templates
->start
->name
,
2107 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2109 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2111 as_warn (_("use .code16 to ensure correct addressing mode"));
2114 /* Check for rep/repne without a string instruction. */
2115 if (expecting_string_instruction
)
2117 static templates override
;
2119 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2120 if (t
->opcode_modifier
& IsString
)
2122 if (t
>= current_templates
->end
)
2124 as_bad (_("expecting string instruction after `%s'"),
2125 expecting_string_instruction
);
2128 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2129 if (!(t
->opcode_modifier
& IsString
))
2132 current_templates
= &override
;
2139 parse_operands (char *l
, const char *mnemonic
)
2143 /* 1 if operand is pending after ','. */
2144 unsigned int expecting_operand
= 0;
2146 /* Non-zero if operand parens not balanced. */
2147 unsigned int paren_not_balanced
;
2149 while (*l
!= END_OF_INSN
)
2151 /* Skip optional white space before operand. */
2152 if (is_space_char (*l
))
2154 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2156 as_bad (_("invalid character %s before operand %d"),
2157 output_invalid (*l
),
2161 token_start
= l
; /* after white space */
2162 paren_not_balanced
= 0;
2163 while (paren_not_balanced
|| *l
!= ',')
2165 if (*l
== END_OF_INSN
)
2167 if (paren_not_balanced
)
2170 as_bad (_("unbalanced parenthesis in operand %d."),
2173 as_bad (_("unbalanced brackets in operand %d."),
2178 break; /* we are done */
2180 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2182 as_bad (_("invalid character %s in operand %d"),
2183 output_invalid (*l
),
2190 ++paren_not_balanced
;
2192 --paren_not_balanced
;
2197 ++paren_not_balanced
;
2199 --paren_not_balanced
;
2203 if (l
!= token_start
)
2204 { /* Yes, we've read in another operand. */
2205 unsigned int operand_ok
;
2206 this_operand
= i
.operands
++;
2207 if (i
.operands
> MAX_OPERANDS
)
2209 as_bad (_("spurious operands; (%d operands/instruction max)"),
2213 /* Now parse operand adding info to 'i' as we go along. */
2214 END_STRING_AND_SAVE (l
);
2218 i386_intel_operand (token_start
,
2219 intel_float_operand (mnemonic
));
2221 operand_ok
= i386_operand (token_start
);
2223 RESTORE_END_STRING (l
);
2229 if (expecting_operand
)
2231 expecting_operand_after_comma
:
2232 as_bad (_("expecting operand after ','; got nothing"));
2237 as_bad (_("expecting operand before ','; got nothing"));
2242 /* Now *l must be either ',' or END_OF_INSN. */
2245 if (*++l
== END_OF_INSN
)
2247 /* Just skip it, if it's \n complain. */
2248 goto expecting_operand_after_comma
;
2250 expecting_operand
= 1;
2257 swap_imm_operands (void)
2259 union i386_op temp_op
;
2260 unsigned int temp_type
;
2261 enum bfd_reloc_code_real temp_reloc
;
2265 temp_type
= i
.types
[xchg2
];
2266 i
.types
[xchg2
] = i
.types
[xchg1
];
2267 i
.types
[xchg1
] = temp_type
;
2268 temp_op
= i
.op
[xchg2
];
2269 i
.op
[xchg2
] = i
.op
[xchg1
];
2270 i
.op
[xchg1
] = temp_op
;
2271 temp_reloc
= i
.reloc
[xchg2
];
2272 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2273 i
.reloc
[xchg1
] = temp_reloc
;
2278 swap_operands (void)
2280 union i386_op temp_op
;
2281 unsigned int temp_type
;
2282 enum bfd_reloc_code_real temp_reloc
;
2286 if (i
.operands
== 4)
2287 /* There will be two exchanges in a 4 operand instruction.
2288 First exchange is the done inside this block.(1st and 4rth operand)
2289 The next exchange is done outside this block.(2nd and 3rd operand) */
2293 temp_type
= i
.types
[xchg2
];
2294 i
.types
[xchg2
] = i
.types
[xchg1
];
2295 i
.types
[xchg1
] = temp_type
;
2296 temp_op
= i
.op
[xchg2
];
2297 i
.op
[xchg2
] = i
.op
[xchg1
];
2298 i
.op
[xchg1
] = temp_op
;
2299 temp_reloc
= i
.reloc
[xchg2
];
2300 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2301 i
.reloc
[xchg1
] = temp_reloc
;
2306 if (i
.operands
== 2)
2311 else if (i
.operands
== 3)
2316 temp_type
= i
.types
[xchg2
];
2317 i
.types
[xchg2
] = i
.types
[xchg1
];
2318 i
.types
[xchg1
] = temp_type
;
2319 temp_op
= i
.op
[xchg2
];
2320 i
.op
[xchg2
] = i
.op
[xchg1
];
2321 i
.op
[xchg1
] = temp_op
;
2322 temp_reloc
= i
.reloc
[xchg2
];
2323 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2324 i
.reloc
[xchg1
] = temp_reloc
;
2326 if (i
.mem_operands
== 2)
2328 const seg_entry
*temp_seg
;
2329 temp_seg
= i
.seg
[0];
2330 i
.seg
[0] = i
.seg
[1];
2331 i
.seg
[1] = temp_seg
;
2335 /* Try to ensure constant immediates are represented in the smallest
2340 char guess_suffix
= 0;
2344 guess_suffix
= i
.suffix
;
2345 else if (i
.reg_operands
)
2347 /* Figure out a suffix from the last register operand specified.
2348 We can't do this properly yet, ie. excluding InOutPortReg,
2349 but the following works for instructions with immediates.
2350 In any case, we can't set i.suffix yet. */
2351 for (op
= i
.operands
; --op
>= 0;)
2352 if (i
.types
[op
] & Reg
)
2354 if (i
.types
[op
] & Reg8
)
2355 guess_suffix
= BYTE_MNEM_SUFFIX
;
2356 else if (i
.types
[op
] & Reg16
)
2357 guess_suffix
= WORD_MNEM_SUFFIX
;
2358 else if (i
.types
[op
] & Reg32
)
2359 guess_suffix
= LONG_MNEM_SUFFIX
;
2360 else if (i
.types
[op
] & Reg64
)
2361 guess_suffix
= QWORD_MNEM_SUFFIX
;
2365 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2366 guess_suffix
= WORD_MNEM_SUFFIX
;
2368 for (op
= i
.operands
; --op
>= 0;)
2369 if (i
.types
[op
] & Imm
)
2371 switch (i
.op
[op
].imms
->X_op
)
2374 /* If a suffix is given, this operand may be shortened. */
2375 switch (guess_suffix
)
2377 case LONG_MNEM_SUFFIX
:
2378 i
.types
[op
] |= Imm32
| Imm64
;
2380 case WORD_MNEM_SUFFIX
:
2381 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2383 case BYTE_MNEM_SUFFIX
:
2384 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2388 /* If this operand is at most 16 bits, convert it
2389 to a signed 16 bit number before trying to see
2390 whether it will fit in an even smaller size.
2391 This allows a 16-bit operand such as $0xffe0 to
2392 be recognised as within Imm8S range. */
2393 if ((i
.types
[op
] & Imm16
)
2394 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2396 i
.op
[op
].imms
->X_add_number
=
2397 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2399 if ((i
.types
[op
] & Imm32
)
2400 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2403 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2404 ^ ((offsetT
) 1 << 31))
2405 - ((offsetT
) 1 << 31));
2407 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2409 /* We must avoid matching of Imm32 templates when 64bit
2410 only immediate is available. */
2411 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2412 i
.types
[op
] &= ~Imm32
;
2419 /* Symbols and expressions. */
2421 /* Convert symbolic operand to proper sizes for matching, but don't
2422 prevent matching a set of insns that only supports sizes other
2423 than those matching the insn suffix. */
2425 unsigned int mask
, allowed
= 0;
2428 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2429 allowed
|= t
->operand_types
[op
];
2430 switch (guess_suffix
)
2432 case QWORD_MNEM_SUFFIX
:
2433 mask
= Imm64
| Imm32S
;
2435 case LONG_MNEM_SUFFIX
:
2438 case WORD_MNEM_SUFFIX
:
2441 case BYTE_MNEM_SUFFIX
:
2449 i
.types
[op
] &= mask
;
2456 /* Try to use the smallest displacement type too. */
2458 optimize_disp (void)
2462 for (op
= i
.operands
; --op
>= 0;)
2463 if (i
.types
[op
] & Disp
)
2465 if (i
.op
[op
].disps
->X_op
== O_constant
)
2467 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2469 if ((i
.types
[op
] & Disp16
)
2470 && (disp
& ~(offsetT
) 0xffff) == 0)
2472 /* If this operand is at most 16 bits, convert
2473 to a signed 16 bit number and don't use 64bit
2475 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2476 i
.types
[op
] &= ~Disp64
;
2478 if ((i
.types
[op
] & Disp32
)
2479 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2481 /* If this operand is at most 32 bits, convert
2482 to a signed 32 bit number and don't use 64bit
2484 disp
&= (((offsetT
) 2 << 31) - 1);
2485 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2486 i
.types
[op
] &= ~Disp64
;
2488 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2490 i
.types
[op
] &= ~Disp
;
2494 else if (flag_code
== CODE_64BIT
)
2496 if (fits_in_signed_long (disp
))
2498 i
.types
[op
] &= ~Disp64
;
2499 i
.types
[op
] |= Disp32S
;
2501 if (fits_in_unsigned_long (disp
))
2502 i
.types
[op
] |= Disp32
;
2504 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2505 && fits_in_signed_byte (disp
))
2506 i
.types
[op
] |= Disp8
;
2508 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2509 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2511 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2512 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2513 i
.types
[op
] &= ~Disp
;
2516 /* We only support 64bit displacement on constants. */
2517 i
.types
[op
] &= ~Disp64
;
2522 match_template (void)
2524 /* Points to template once we've found it. */
2526 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2527 unsigned int found_reverse_match
;
2529 unsigned int operand_types
[MAX_OPERANDS
];
2530 int addr_prefix_disp
;
2533 #if MAX_OPERANDS != 4
2534 # error "MAX_OPERANDS must be 4."
2537 #define MATCH(overlap, given, template) \
2538 ((overlap & ~JumpAbsolute) \
2539 && (((given) & (BaseIndex | JumpAbsolute)) \
2540 == ((overlap) & (BaseIndex | JumpAbsolute))))
2542 /* If given types r0 and r1 are registers they must be of the same type
2543 unless the expected operand type register overlap is null.
2544 Note that Acc in a template matches every size of reg. */
2545 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2546 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2547 || ((g0) & Reg) == ((g1) & Reg) \
2548 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2554 found_reverse_match
= 0;
2555 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2556 operand_types
[j
] = 0;
2557 addr_prefix_disp
= -1;
2558 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2560 : (i
.suffix
== WORD_MNEM_SUFFIX
2562 : (i
.suffix
== SHORT_MNEM_SUFFIX
2564 : (i
.suffix
== LONG_MNEM_SUFFIX
2566 : (i
.suffix
== QWORD_MNEM_SUFFIX
2568 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2569 ? No_xSuf
: 0))))));
2571 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2573 addr_prefix_disp
= -1;
2575 /* Must have right number of operands. */
2576 if (i
.operands
!= t
->operands
)
2579 /* Check the suffix, except for some instructions in intel mode. */
2580 if ((t
->opcode_modifier
& suffix_check
)
2582 && (t
->opcode_modifier
& IgnoreSize
)))
2585 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2586 operand_types
[j
] = t
->operand_types
[j
];
2588 /* In general, don't allow 64-bit operands in 32-bit mode. */
2589 if (i
.suffix
== QWORD_MNEM_SUFFIX
2590 && flag_code
!= CODE_64BIT
2592 ? (!(t
->opcode_modifier
& IgnoreSize
)
2593 && !intel_float_operand (t
->name
))
2594 : intel_float_operand (t
->name
) != 2)
2595 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2596 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2597 && (t
->base_opcode
!= 0x0fc7
2598 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2601 /* Do not verify operands when there are none. */
2602 else if (!t
->operands
)
2604 if (t
->cpu_flags
& ~cpu_arch_flags
)
2606 /* We've found a match; break out of loop. */
2610 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2611 into Disp32/Disp16/Disp32 operand. */
2612 if (i
.prefix
[ADDR_PREFIX
] != 0)
2614 unsigned int DispOn
= 0, DispOff
= 0;
2632 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2634 /* There should be only one Disp operand. */
2635 if ((operand_types
[j
] & DispOff
))
2637 addr_prefix_disp
= j
;
2638 operand_types
[j
] |= DispOn
;
2639 operand_types
[j
] &= ~DispOff
;
2645 overlap0
= i
.types
[0] & operand_types
[0];
2646 switch (t
->operands
)
2649 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2655 overlap1
= i
.types
[1] & operand_types
[1];
2656 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2657 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2658 /* monitor in SSE3 is a very special case. The first
2659 register and the second register may have different
2661 || !((t
->base_opcode
== 0x0f01
2662 && t
->extension_opcode
== 0xc8)
2663 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2665 overlap1
, i
.types
[1],
2668 /* Check if other direction is valid ... */
2669 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2672 /* Try reversing direction of operands. */
2673 overlap0
= i
.types
[0] & operand_types
[1];
2674 overlap1
= i
.types
[1] & operand_types
[0];
2675 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2676 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2677 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2679 overlap1
, i
.types
[1],
2682 /* Does not match either direction. */
2685 /* found_reverse_match holds which of D or FloatDR
2687 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2691 /* Found a forward 2 operand match here. */
2692 switch (t
->operands
)
2695 overlap3
= i
.types
[3] & operand_types
[3];
2697 overlap2
= i
.types
[2] & operand_types
[2];
2701 switch (t
->operands
)
2704 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2705 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2713 /* Here we make use of the fact that there are no
2714 reverse match 3 operand instructions, and all 3
2715 operand instructions only need to be checked for
2716 register consistency between operands 2 and 3. */
2717 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2718 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2728 /* Found either forward/reverse 2, 3 or 4 operand match here:
2729 slip through to break. */
2731 if (t
->cpu_flags
& ~cpu_arch_flags
)
2733 found_reverse_match
= 0;
2736 /* We've found a match; break out of loop. */
2740 if (t
== current_templates
->end
)
2742 /* We found no match. */
2743 as_bad (_("suffix or operands invalid for `%s'"),
2744 current_templates
->start
->name
);
2748 if (!quiet_warnings
)
2751 && ((i
.types
[0] & JumpAbsolute
)
2752 != (operand_types
[0] & JumpAbsolute
)))
2754 as_warn (_("indirect %s without `*'"), t
->name
);
2757 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2758 == (IsPrefix
| IgnoreSize
))
2760 /* Warn them that a data or address size prefix doesn't
2761 affect assembly of the next line of code. */
2762 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2766 /* Copy the template we found. */
2769 if (addr_prefix_disp
!= -1)
2770 i
.tm
.operand_types
[addr_prefix_disp
]
2771 = operand_types
[addr_prefix_disp
];
2773 if (found_reverse_match
)
2775 /* If we found a reverse match we must alter the opcode
2776 direction bit. found_reverse_match holds bits to change
2777 (different for int & float insns). */
2779 i
.tm
.base_opcode
^= found_reverse_match
;
2781 i
.tm
.operand_types
[0] = operand_types
[1];
2782 i
.tm
.operand_types
[1] = operand_types
[0];
2791 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2792 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2794 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2796 as_bad (_("`%s' operand %d must use `%%es' segment"),
2801 /* There's only ever one segment override allowed per instruction.
2802 This instruction possibly has a legal segment override on the
2803 second operand, so copy the segment to where non-string
2804 instructions store it, allowing common code. */
2805 i
.seg
[0] = i
.seg
[1];
2807 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2809 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2821 process_suffix (void)
2823 /* If matched instruction specifies an explicit instruction mnemonic
2825 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2827 if (i
.tm
.opcode_modifier
& Size16
)
2828 i
.suffix
= WORD_MNEM_SUFFIX
;
2829 else if (i
.tm
.opcode_modifier
& Size64
)
2830 i
.suffix
= QWORD_MNEM_SUFFIX
;
2832 i
.suffix
= LONG_MNEM_SUFFIX
;
2834 else if (i
.reg_operands
)
2836 /* If there's no instruction mnemonic suffix we try to invent one
2837 based on register operands. */
2840 /* We take i.suffix from the last register operand specified,
2841 Destination register type is more significant than source
2845 for (op
= i
.operands
; --op
>= 0;)
2846 if ((i
.types
[op
] & Reg
)
2847 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2849 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2850 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2851 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2856 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2858 if (!check_byte_reg ())
2861 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2863 if (!check_long_reg ())
2866 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2868 if (!check_qword_reg ())
2871 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2873 if (!check_word_reg ())
2876 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2877 /* Do nothing if the instruction is going to ignore the prefix. */
2882 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2884 /* exclude fldenv/frstor/fsave/fstenv */
2885 && (i
.tm
.opcode_modifier
& No_sSuf
))
2887 i
.suffix
= stackop_size
;
2889 else if (intel_syntax
2891 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2892 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2893 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2894 && i
.tm
.extension_opcode
<= 3)))
2899 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2901 i
.suffix
= QWORD_MNEM_SUFFIX
;
2905 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2906 i
.suffix
= LONG_MNEM_SUFFIX
;
2909 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2910 i
.suffix
= WORD_MNEM_SUFFIX
;
2919 if (i
.tm
.opcode_modifier
& W
)
2921 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2927 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2935 if ((i
.tm
.opcode_modifier
& W
)
2936 || ((suffixes
& (suffixes
- 1))
2937 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2939 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2945 /* Change the opcode based on the operand size given by i.suffix;
2946 We don't need to change things for byte insns. */
2948 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2950 /* It's not a byte, select word/dword operation. */
2951 if (i
.tm
.opcode_modifier
& W
)
2953 if (i
.tm
.opcode_modifier
& ShortForm
)
2954 i
.tm
.base_opcode
|= 8;
2956 i
.tm
.base_opcode
|= 1;
2959 /* Now select between word & dword operations via the operand
2960 size prefix, except for instructions that will ignore this
2962 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2964 /* monitor in SSE3 is a very special case. The default size
2965 of AX is the size of mode. The address size override
2966 prefix will change the size of AX. */
2967 if (i
.op
->regs
[0].reg_type
&
2968 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2969 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2972 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2973 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2974 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2975 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2976 || (flag_code
== CODE_64BIT
2977 && (i
.tm
.opcode_modifier
& JumpByte
))))
2979 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2981 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2982 prefix
= ADDR_PREFIX_OPCODE
;
2984 if (!add_prefix (prefix
))
2988 /* Set mode64 for an operand. */
2989 if (i
.suffix
== QWORD_MNEM_SUFFIX
2990 && flag_code
== CODE_64BIT
2991 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2993 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2996 || i
.types
[0] != (Acc
| Reg64
)
2997 || i
.types
[1] != (Acc
| Reg64
)
2998 || strcmp (i
.tm
.name
, "xchg") != 0)
2999 i
.rex
|= REX_MODE64
;
3002 /* Size floating point instruction. */
3003 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3004 if (i
.tm
.opcode_modifier
& FloatMF
)
3005 i
.tm
.base_opcode
^= 4;
3012 check_byte_reg (void)
3016 for (op
= i
.operands
; --op
>= 0;)
3018 /* If this is an eight bit register, it's OK. If it's the 16 or
3019 32 bit version of an eight bit register, we will just use the
3020 low portion, and that's OK too. */
3021 if (i
.types
[op
] & Reg8
)
3024 /* movzx and movsx should not generate this warning. */
3026 && (i
.tm
.base_opcode
== 0xfb7
3027 || i
.tm
.base_opcode
== 0xfb6
3028 || i
.tm
.base_opcode
== 0x63
3029 || i
.tm
.base_opcode
== 0xfbe
3030 || i
.tm
.base_opcode
== 0xfbf))
3033 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3035 /* Prohibit these changes in the 64bit mode, since the
3036 lowering is more complicated. */
3037 if (flag_code
== CODE_64BIT
3038 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3040 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3041 i
.op
[op
].regs
->reg_name
,
3045 #if REGISTER_WARNINGS
3047 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3048 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3049 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3050 ? REGNAM_AL
- REGNAM_AX
3051 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3052 i
.op
[op
].regs
->reg_name
,
3057 /* Any other register is bad. */
3058 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3060 | Control
| Debug
| Test
3061 | FloatReg
| FloatAcc
))
3063 as_bad (_("`%%%s' not allowed with `%s%c'"),
3064 i
.op
[op
].regs
->reg_name
,
3074 check_long_reg (void)
3078 for (op
= i
.operands
; --op
>= 0;)
3079 /* Reject eight bit registers, except where the template requires
3080 them. (eg. movzb) */
3081 if ((i
.types
[op
] & Reg8
) != 0
3082 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3084 as_bad (_("`%%%s' not allowed with `%s%c'"),
3085 i
.op
[op
].regs
->reg_name
,
3090 /* Warn if the e prefix on a general reg is missing. */
3091 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3092 && (i
.types
[op
] & Reg16
) != 0
3093 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3095 /* Prohibit these changes in the 64bit mode, since the
3096 lowering is more complicated. */
3097 if (flag_code
== CODE_64BIT
)
3099 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3100 i
.op
[op
].regs
->reg_name
,
3104 #if REGISTER_WARNINGS
3106 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3107 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3108 i
.op
[op
].regs
->reg_name
,
3112 /* Warn if the r prefix on a general reg is missing. */
3113 else if ((i
.types
[op
] & Reg64
) != 0
3114 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3116 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3117 i
.op
[op
].regs
->reg_name
,
3125 check_qword_reg (void)
3129 for (op
= i
.operands
; --op
>= 0; )
3130 /* Reject eight bit registers, except where the template requires
3131 them. (eg. movzb) */
3132 if ((i
.types
[op
] & Reg8
) != 0
3133 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3135 as_bad (_("`%%%s' not allowed with `%s%c'"),
3136 i
.op
[op
].regs
->reg_name
,
3141 /* Warn if the e prefix on a general reg is missing. */
3142 else if (((i
.types
[op
] & Reg16
) != 0
3143 || (i
.types
[op
] & Reg32
) != 0)
3144 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3146 /* Prohibit these changes in the 64bit mode, since the
3147 lowering is more complicated. */
3148 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3149 i
.op
[op
].regs
->reg_name
,
3157 check_word_reg (void)
3160 for (op
= i
.operands
; --op
>= 0;)
3161 /* Reject eight bit registers, except where the template requires
3162 them. (eg. movzb) */
3163 if ((i
.types
[op
] & Reg8
) != 0
3164 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3166 as_bad (_("`%%%s' not allowed with `%s%c'"),
3167 i
.op
[op
].regs
->reg_name
,
3172 /* Warn if the e prefix on a general reg is present. */
3173 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3174 && (i
.types
[op
] & Reg32
) != 0
3175 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3177 /* Prohibit these changes in the 64bit mode, since the
3178 lowering is more complicated. */
3179 if (flag_code
== CODE_64BIT
)
3181 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3182 i
.op
[op
].regs
->reg_name
,
3187 #if REGISTER_WARNINGS
3188 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3189 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3190 i
.op
[op
].regs
->reg_name
,
3200 unsigned int overlap0
, overlap1
, overlap2
;
3202 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3203 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3204 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3205 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3206 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3210 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3212 : (i
.suffix
== WORD_MNEM_SUFFIX
3214 : (i
.suffix
== QWORD_MNEM_SUFFIX
3218 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3219 || overlap0
== (Imm16
| Imm32
)
3220 || overlap0
== (Imm16
| Imm32S
))
3222 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3225 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3226 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3227 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3229 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3233 i
.types
[0] = overlap0
;
3235 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3236 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3237 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3238 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3239 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3243 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3245 : (i
.suffix
== WORD_MNEM_SUFFIX
3247 : (i
.suffix
== QWORD_MNEM_SUFFIX
3251 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3252 || overlap1
== (Imm16
| Imm32
)
3253 || overlap1
== (Imm16
| Imm32S
))
3255 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3258 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3259 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3260 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3262 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
3266 i
.types
[1] = overlap1
;
3268 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3269 assert ((overlap2
& Imm
) == 0);
3270 i
.types
[2] = overlap2
;
3276 process_operands (void)
3278 /* Default segment register this instruction will use for memory
3279 accesses. 0 means unknown. This is only for optimizing out
3280 unnecessary segment overrides. */
3281 const seg_entry
*default_seg
= 0;
3283 /* The imul $imm, %reg instruction is converted into
3284 imul $imm, %reg, %reg, and the clr %reg instruction
3285 is converted into xor %reg, %reg. */
3286 if (i
.tm
.opcode_modifier
& regKludge
)
3288 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3289 /* Pretend we saw the extra register operand. */
3290 assert (i
.reg_operands
== 1
3291 && i
.op
[first_reg_op
+ 1].regs
== 0);
3292 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3293 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3298 if (i
.tm
.opcode_modifier
& ShortForm
)
3300 /* The register or float register operand is in operand 0 or 1. */
3301 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3302 /* Register goes in low 3 bits of opcode. */
3303 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3304 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3306 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3308 /* Warn about some common errors, but press on regardless.
3309 The first case can be generated by gcc (<= 2.8.1). */
3310 if (i
.operands
== 2)
3312 /* Reversed arguments on faddp, fsubp, etc. */
3313 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3314 i
.op
[1].regs
->reg_name
,
3315 i
.op
[0].regs
->reg_name
);
3319 /* Extraneous `l' suffix on fp insn. */
3320 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3321 i
.op
[0].regs
->reg_name
);
3325 else if (i
.tm
.opcode_modifier
& Modrm
)
3327 /* The opcode is completed (modulo i.tm.extension_opcode which
3328 must be put into the modrm byte). Now, we make the modrm and
3329 index base bytes based on all the info we've collected. */
3331 default_seg
= build_modrm_byte ();
3333 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
3335 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3336 && i
.op
[0].regs
->reg_num
== 1)
3338 as_bad (_("you can't `pop %%cs'"));
3341 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3342 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3345 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
3349 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3351 /* For the string instructions that allow a segment override
3352 on one of their operands, the default segment is ds. */
3356 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3357 || (i
.tm
.cpu_flags
& CpuSVME
))
3358 && i
.seg
[0] && !quiet_warnings
)
3359 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3361 /* If a segment was explicitly specified, and the specified segment
3362 is not the default, use an opcode prefix to select it. If we
3363 never figured out what the default segment is, then default_seg
3364 will be zero at this point, and the specified segment prefix will
3366 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3368 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3374 static const seg_entry
*
3375 build_modrm_byte (void)
3377 const seg_entry
*default_seg
= 0;
3379 /* i.reg_operands MUST be the number of real register operands;
3380 implicit registers do not count. */
3381 if (i
.reg_operands
== 2)
3383 unsigned int source
, dest
;
3391 /* When there are 3 operands, one of them may be immediate,
3392 which may be the first or the last operand. Otherwise,
3393 the first operand must be shift count register (cl). */
3394 assert (i
.imm_operands
== 1
3395 || (i
.imm_operands
== 0
3396 && (i
.types
[0] & ShiftCount
)));
3397 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3400 /* When there are 4 operands, the first two must be immediate
3401 operands. The source operand will be the 3rd one. */
3402 assert (i
.imm_operands
== 2
3403 && (i
.types
[0] & Imm
)
3404 && (i
.types
[1] & Imm
));
3414 /* One of the register operands will be encoded in the i.tm.reg
3415 field, the other in the combined i.tm.mode and i.tm.regmem
3416 fields. If no form of this instruction supports a memory
3417 destination operand, then we assume the source operand may
3418 sometimes be a memory operand and so we need to store the
3419 destination in the i.rm.reg field. */
3420 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3422 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3423 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3424 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3426 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3431 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3432 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3433 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3435 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3438 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3440 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3442 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3443 add_prefix (LOCK_PREFIX_OPCODE
);
3447 { /* If it's not 2 reg operands... */
3450 unsigned int fake_zero_displacement
= 0;
3451 unsigned int op
= ((i
.types
[0] & AnyMem
)
3453 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3457 if (i
.base_reg
== 0)
3460 if (!i
.disp_operands
)
3461 fake_zero_displacement
= 1;
3462 if (i
.index_reg
== 0)
3464 /* Operand is just <disp> */
3465 if (flag_code
== CODE_64BIT
)
3467 /* 64bit mode overwrites the 32bit absolute
3468 addressing by RIP relative addressing and
3469 absolute addressing is encoded by one of the
3470 redundant SIB forms. */
3471 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3472 i
.sib
.base
= NO_BASE_REGISTER
;
3473 i
.sib
.index
= NO_INDEX_REGISTER
;
3474 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3475 ? Disp32S
: Disp32
);
3477 else if ((flag_code
== CODE_16BIT
)
3478 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3480 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3481 i
.types
[op
] = Disp16
;
3485 i
.rm
.regmem
= NO_BASE_REGISTER
;
3486 i
.types
[op
] = Disp32
;
3489 else /* !i.base_reg && i.index_reg */
3491 i
.sib
.index
= i
.index_reg
->reg_num
;
3492 i
.sib
.base
= NO_BASE_REGISTER
;
3493 i
.sib
.scale
= i
.log2_scale_factor
;
3494 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3495 i
.types
[op
] &= ~Disp
;
3496 if (flag_code
!= CODE_64BIT
)
3497 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3499 i
.types
[op
] |= Disp32S
;
3500 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3504 /* RIP addressing for 64bit mode. */
3505 else if (i
.base_reg
->reg_type
== BaseIndex
)
3507 i
.rm
.regmem
= NO_BASE_REGISTER
;
3508 i
.types
[op
] &= ~ Disp
;
3509 i
.types
[op
] |= Disp32S
;
3510 i
.flags
[op
] |= Operand_PCrel
;
3511 if (! i
.disp_operands
)
3512 fake_zero_displacement
= 1;
3514 else if (i
.base_reg
->reg_type
& Reg16
)
3516 switch (i
.base_reg
->reg_num
)
3519 if (i
.index_reg
== 0)
3521 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3522 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3526 if (i
.index_reg
== 0)
3529 if ((i
.types
[op
] & Disp
) == 0)
3531 /* fake (%bp) into 0(%bp) */
3532 i
.types
[op
] |= Disp8
;
3533 fake_zero_displacement
= 1;
3536 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3537 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3539 default: /* (%si) -> 4 or (%di) -> 5 */
3540 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3542 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3544 else /* i.base_reg and 32/64 bit mode */
3546 if (flag_code
== CODE_64BIT
3547 && (i
.types
[op
] & Disp
))
3548 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3549 | (i
.prefix
[ADDR_PREFIX
] == 0
3550 ? Disp32S
: Disp32
));
3552 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3553 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3555 i
.sib
.base
= i
.base_reg
->reg_num
;
3556 /* x86-64 ignores REX prefix bit here to avoid decoder
3558 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3561 if (i
.disp_operands
== 0)
3563 fake_zero_displacement
= 1;
3564 i
.types
[op
] |= Disp8
;
3567 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3571 i
.sib
.scale
= i
.log2_scale_factor
;
3572 if (i
.index_reg
== 0)
3574 /* <disp>(%esp) becomes two byte modrm with no index
3575 register. We've already stored the code for esp
3576 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3577 Any base register besides %esp will not use the
3578 extra modrm byte. */
3579 i
.sib
.index
= NO_INDEX_REGISTER
;
3580 #if !SCALE1_WHEN_NO_INDEX
3581 /* Another case where we force the second modrm byte. */
3582 if (i
.log2_scale_factor
)
3583 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3588 i
.sib
.index
= i
.index_reg
->reg_num
;
3589 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3590 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3595 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3596 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3599 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3602 if (fake_zero_displacement
)
3604 /* Fakes a zero displacement assuming that i.types[op]
3605 holds the correct displacement size. */
3608 assert (i
.op
[op
].disps
== 0);
3609 exp
= &disp_expressions
[i
.disp_operands
++];
3610 i
.op
[op
].disps
= exp
;
3611 exp
->X_op
= O_constant
;
3612 exp
->X_add_number
= 0;
3613 exp
->X_add_symbol
= (symbolS
*) 0;
3614 exp
->X_op_symbol
= (symbolS
*) 0;
3618 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3619 (if any) based on i.tm.extension_opcode. Again, we must be
3620 careful to make sure that segment/control/debug/test/MMX
3621 registers are coded into the i.rm.reg field. */
3626 & (Reg
| RegMMX
| RegXMM
3628 | Control
| Debug
| Test
))
3631 & (Reg
| RegMMX
| RegXMM
3633 | Control
| Debug
| Test
))
3636 /* If there is an extension opcode to put here, the register
3637 number must be put into the regmem field. */
3638 if (i
.tm
.extension_opcode
!= None
)
3640 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3641 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3646 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3647 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3651 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3652 must set it to 3 to indicate this is a register operand
3653 in the regmem field. */
3654 if (!i
.mem_operands
)
3658 /* Fill in i.rm.reg field with extension opcode (if any). */
3659 if (i
.tm
.extension_opcode
!= None
)
3660 i
.rm
.reg
= i
.tm
.extension_opcode
;
3666 output_branch (void)
3671 relax_substateT subtype
;
3676 if (flag_code
== CODE_16BIT
)
3680 if (i
.prefix
[DATA_PREFIX
] != 0)
3686 /* Pentium4 branch hints. */
3687 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3688 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3693 if (i
.prefix
[REX_PREFIX
] != 0)
3699 if (i
.prefixes
!= 0 && !intel_syntax
)
3700 as_warn (_("skipping prefixes on this instruction"));
3702 /* It's always a symbol; End frag & setup for relax.
3703 Make sure there is enough room in this frag for the largest
3704 instruction we may generate in md_convert_frag. This is 2
3705 bytes for the opcode and room for the prefix and largest
3707 frag_grow (prefix
+ 2 + 4);
3708 /* Prefix and 1 opcode byte go in fr_fix. */
3709 p
= frag_more (prefix
+ 1);
3710 if (i
.prefix
[DATA_PREFIX
] != 0)
3711 *p
++ = DATA_PREFIX_OPCODE
;
3712 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3713 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3714 *p
++ = i
.prefix
[SEG_PREFIX
];
3715 if (i
.prefix
[REX_PREFIX
] != 0)
3716 *p
++ = i
.prefix
[REX_PREFIX
];
3717 *p
= i
.tm
.base_opcode
;
3719 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3720 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3721 else if ((cpu_arch_flags
& Cpu386
) != 0)
3722 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3724 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3727 sym
= i
.op
[0].disps
->X_add_symbol
;
3728 off
= i
.op
[0].disps
->X_add_number
;
3730 if (i
.op
[0].disps
->X_op
!= O_constant
3731 && i
.op
[0].disps
->X_op
!= O_symbol
)
3733 /* Handle complex expressions. */
3734 sym
= make_expr_symbol (i
.op
[0].disps
);
3738 /* 1 possible extra opcode + 4 byte displacement go in var part.
3739 Pass reloc in fr_var. */
3740 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3750 if (i
.tm
.opcode_modifier
& JumpByte
)
3752 /* This is a loop or jecxz type instruction. */
3754 if (i
.prefix
[ADDR_PREFIX
] != 0)
3756 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3759 /* Pentium4 branch hints. */
3760 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3761 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3763 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3772 if (flag_code
== CODE_16BIT
)
3775 if (i
.prefix
[DATA_PREFIX
] != 0)
3777 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3787 if (i
.prefix
[REX_PREFIX
] != 0)
3789 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3793 if (i
.prefixes
!= 0 && !intel_syntax
)
3794 as_warn (_("skipping prefixes on this instruction"));
3796 p
= frag_more (1 + size
);
3797 *p
++ = i
.tm
.base_opcode
;
3799 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3800 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3802 /* All jumps handled here are signed, but don't use a signed limit
3803 check for 32 and 16 bit jumps as we want to allow wrap around at
3804 4G and 64k respectively. */
3806 fixP
->fx_signed
= 1;
3810 output_interseg_jump (void)
3818 if (flag_code
== CODE_16BIT
)
3822 if (i
.prefix
[DATA_PREFIX
] != 0)
3828 if (i
.prefix
[REX_PREFIX
] != 0)
3838 if (i
.prefixes
!= 0 && !intel_syntax
)
3839 as_warn (_("skipping prefixes on this instruction"));
3841 /* 1 opcode; 2 segment; offset */
3842 p
= frag_more (prefix
+ 1 + 2 + size
);
3844 if (i
.prefix
[DATA_PREFIX
] != 0)
3845 *p
++ = DATA_PREFIX_OPCODE
;
3847 if (i
.prefix
[REX_PREFIX
] != 0)
3848 *p
++ = i
.prefix
[REX_PREFIX
];
3850 *p
++ = i
.tm
.base_opcode
;
3851 if (i
.op
[1].imms
->X_op
== O_constant
)
3853 offsetT n
= i
.op
[1].imms
->X_add_number
;
3856 && !fits_in_unsigned_word (n
)
3857 && !fits_in_signed_word (n
))
3859 as_bad (_("16-bit jump out of range"));
3862 md_number_to_chars (p
, n
, size
);
3865 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3866 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3867 if (i
.op
[0].imms
->X_op
!= O_constant
)
3868 as_bad (_("can't handle non absolute segment in `%s'"),
3870 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3876 fragS
*insn_start_frag
;
3877 offsetT insn_start_off
;
3879 /* Tie dwarf2 debug info to the address at the start of the insn.
3880 We can't do this after the insn has been output as the current
3881 frag may have been closed off. eg. by frag_var. */
3882 dwarf2_emit_insn (0);
3884 insn_start_frag
= frag_now
;
3885 insn_start_off
= frag_now_fix ();
3888 if (i
.tm
.opcode_modifier
& Jump
)
3890 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3892 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3893 output_interseg_jump ();
3896 /* Output normal instructions here. */
3899 unsigned int prefix
;
3901 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3902 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3903 use one more higher byte to specify a prefix the instruction
3905 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3907 if (i
.tm
.base_opcode
& 0xff000000)
3909 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3913 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3915 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3916 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3919 if (prefix
!= REPE_PREFIX_OPCODE
3920 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3921 add_prefix (prefix
);
3924 add_prefix (prefix
);
3927 /* The prefix bytes. */
3929 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3935 md_number_to_chars (p
, (valueT
) *q
, 1);
3939 /* Now the opcode; be careful about word order here! */
3940 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3942 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3946 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3949 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3954 /* Put out high byte first: can't use md_number_to_chars! */
3955 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3956 *p
= i
.tm
.base_opcode
& 0xff;
3959 /* Now the modrm byte and sib byte (if present). */
3960 if (i
.tm
.opcode_modifier
& Modrm
)
3963 md_number_to_chars (p
,
3964 (valueT
) (i
.rm
.regmem
<< 0
3968 /* If i.rm.regmem == ESP (4)
3969 && i.rm.mode != (Register mode)
3971 ==> need second modrm byte. */
3972 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3974 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3977 md_number_to_chars (p
,
3978 (valueT
) (i
.sib
.base
<< 0
3980 | i
.sib
.scale
<< 6),
3985 if (i
.disp_operands
)
3986 output_disp (insn_start_frag
, insn_start_off
);
3989 output_imm (insn_start_frag
, insn_start_off
);
3995 pi ("" /*line*/, &i
);
3997 #endif /* DEBUG386 */
4001 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4006 for (n
= 0; n
< i
.operands
; n
++)
4008 if (i
.types
[n
] & Disp
)
4010 if (i
.op
[n
].disps
->X_op
== O_constant
)
4016 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4019 if (i
.types
[n
] & Disp8
)
4021 if (i
.types
[n
] & Disp64
)
4024 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4026 p
= frag_more (size
);
4027 md_number_to_chars (p
, val
, size
);
4031 enum bfd_reloc_code_real reloc_type
;
4034 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4036 /* The PC relative address is computed relative
4037 to the instruction boundary, so in case immediate
4038 fields follows, we need to adjust the value. */
4039 if (pcrel
&& i
.imm_operands
)
4044 for (n1
= 0; n1
< i
.operands
; n1
++)
4045 if (i
.types
[n1
] & Imm
)
4047 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4050 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4052 if (i
.types
[n1
] & Imm64
)
4057 /* We should find the immediate. */
4058 if (n1
== i
.operands
)
4060 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4063 if (i
.types
[n
] & Disp32S
)
4066 if (i
.types
[n
] & (Disp16
| Disp64
))
4069 if (i
.types
[n
] & Disp64
)
4073 p
= frag_more (size
);
4074 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4076 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4077 && (((reloc_type
== BFD_RELOC_32
4078 || reloc_type
== BFD_RELOC_X86_64_32S
4079 || (reloc_type
== BFD_RELOC_64
4081 && (i
.op
[n
].disps
->X_op
== O_symbol
4082 || (i
.op
[n
].disps
->X_op
== O_add
4083 && ((symbol_get_value_expression
4084 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4086 || reloc_type
== BFD_RELOC_32_PCREL
))
4090 if (insn_start_frag
== frag_now
)
4091 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4096 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4097 for (fr
= insn_start_frag
->fr_next
;
4098 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4100 add
+= p
- frag_now
->fr_literal
;
4105 reloc_type
= BFD_RELOC_386_GOTPC
;
4106 i
.op
[n
].imms
->X_add_number
+= add
;
4108 else if (reloc_type
== BFD_RELOC_64
)
4109 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4111 /* Don't do the adjustment for x86-64, as there
4112 the pcrel addressing is relative to the _next_
4113 insn, and that is taken care of in other code. */
4114 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4116 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4117 i
.op
[n
].disps
, pcrel
, reloc_type
);
4124 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4129 for (n
= 0; n
< i
.operands
; n
++)
4131 if (i
.types
[n
] & Imm
)
4133 if (i
.op
[n
].imms
->X_op
== O_constant
)
4139 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4142 if (i
.types
[n
] & (Imm8
| Imm8S
))
4144 else if (i
.types
[n
] & Imm64
)
4147 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4149 p
= frag_more (size
);
4150 md_number_to_chars (p
, val
, size
);
4154 /* Not absolute_section.
4155 Need a 32-bit fixup (don't support 8bit
4156 non-absolute imms). Try to support other
4158 enum bfd_reloc_code_real reloc_type
;
4162 if ((i
.types
[n
] & (Imm32S
))
4163 && (i
.suffix
== QWORD_MNEM_SUFFIX
4164 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4166 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4169 if (i
.types
[n
] & (Imm8
| Imm8S
))
4171 if (i
.types
[n
] & Imm64
)
4175 p
= frag_more (size
);
4176 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4178 /* This is tough to explain. We end up with this one if we
4179 * have operands that look like
4180 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4181 * obtain the absolute address of the GOT, and it is strongly
4182 * preferable from a performance point of view to avoid using
4183 * a runtime relocation for this. The actual sequence of
4184 * instructions often look something like:
4189 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4191 * The call and pop essentially return the absolute address
4192 * of the label .L66 and store it in %ebx. The linker itself
4193 * will ultimately change the first operand of the addl so
4194 * that %ebx points to the GOT, but to keep things simple, the
4195 * .o file must have this operand set so that it generates not
4196 * the absolute address of .L66, but the absolute address of
4197 * itself. This allows the linker itself simply treat a GOTPC
4198 * relocation as asking for a pcrel offset to the GOT to be
4199 * added in, and the addend of the relocation is stored in the
4200 * operand field for the instruction itself.
4202 * Our job here is to fix the operand so that it would add
4203 * the correct offset so that %ebx would point to itself. The
4204 * thing that is tricky is that .-.L66 will point to the
4205 * beginning of the instruction, so we need to further modify
4206 * the operand so that it will point to itself. There are
4207 * other cases where you have something like:
4209 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4211 * and here no correction would be required. Internally in
4212 * the assembler we treat operands of this form as not being
4213 * pcrel since the '.' is explicitly mentioned, and I wonder
4214 * whether it would simplify matters to do it this way. Who
4215 * knows. In earlier versions of the PIC patches, the
4216 * pcrel_adjust field was used to store the correction, but
4217 * since the expression is not pcrel, I felt it would be
4218 * confusing to do it this way. */
4220 if ((reloc_type
== BFD_RELOC_32
4221 || reloc_type
== BFD_RELOC_X86_64_32S
4222 || reloc_type
== BFD_RELOC_64
)
4224 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4225 && (i
.op
[n
].imms
->X_op
== O_symbol
4226 || (i
.op
[n
].imms
->X_op
== O_add
4227 && ((symbol_get_value_expression
4228 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4233 if (insn_start_frag
== frag_now
)
4234 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4239 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4240 for (fr
= insn_start_frag
->fr_next
;
4241 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4243 add
+= p
- frag_now
->fr_literal
;
4247 reloc_type
= BFD_RELOC_386_GOTPC
;
4249 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4251 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4252 i
.op
[n
].imms
->X_add_number
+= add
;
4254 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4255 i
.op
[n
].imms
, 0, reloc_type
);
4261 /* x86_cons_fix_new is called via the expression parsing code when a
4262 reloc is needed. We use this hook to get the correct .got reloc. */
4263 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4264 static int cons_sign
= -1;
4267 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4270 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4272 got_reloc
= NO_RELOC
;
4275 if (exp
->X_op
== O_secrel
)
4277 exp
->X_op
= O_symbol
;
4278 r
= BFD_RELOC_32_SECREL
;
4282 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4285 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4286 # define lex_got(reloc, adjust, types) NULL
4288 /* Parse operands of the form
4289 <symbol>@GOTOFF+<nnn>
4290 and similar .plt or .got references.
4292 If we find one, set up the correct relocation in RELOC and copy the
4293 input string, minus the `@GOTOFF' into a malloc'd buffer for
4294 parsing by the calling routine. Return this buffer, and if ADJUST
4295 is non-null set it to the length of the string we removed from the
4296 input line. Otherwise return NULL. */
4298 lex_got (enum bfd_reloc_code_real
*reloc
,
4300 unsigned int *types
)
4302 /* Some of the relocations depend on the size of what field is to
4303 be relocated. But in our callers i386_immediate and i386_displacement
4304 we don't yet know the operand size (this will be set by insn
4305 matching). Hence we record the word32 relocation here,
4306 and adjust the reloc according to the real size in reloc(). */
4307 static const struct {
4309 const enum bfd_reloc_code_real rel
[2];
4310 const unsigned int types64
;
4312 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
4313 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
4314 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
4315 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
4316 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
4317 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
4318 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
4319 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
4320 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
4321 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4322 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
4323 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4324 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
4325 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
4326 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
4327 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
4328 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
4336 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4337 if (is_end_of_line
[(unsigned char) *cp
])
4340 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4344 len
= strlen (gotrel
[j
].str
);
4345 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4347 if (gotrel
[j
].rel
[object_64bit
] != 0)
4350 char *tmpbuf
, *past_reloc
;
4352 *reloc
= gotrel
[j
].rel
[object_64bit
];
4358 if (flag_code
!= CODE_64BIT
)
4359 *types
= Imm32
|Disp32
;
4361 *types
= gotrel
[j
].types64
;
4364 if (GOT_symbol
== NULL
)
4365 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4367 /* Replace the relocation token with ' ', so that
4368 errors like foo@GOTOFF1 will be detected. */
4370 /* The length of the first part of our input line. */
4371 first
= cp
- input_line_pointer
;
4373 /* The second part goes from after the reloc token until
4374 (and including) an end_of_line char. Don't use strlen
4375 here as the end_of_line char may not be a NUL. */
4376 past_reloc
= cp
+ 1 + len
;
4377 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4379 second
= cp
- past_reloc
;
4381 /* Allocate and copy string. The trailing NUL shouldn't
4382 be necessary, but be safe. */
4383 tmpbuf
= xmalloc (first
+ second
+ 2);
4384 memcpy (tmpbuf
, input_line_pointer
, first
);
4385 tmpbuf
[first
] = ' ';
4386 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4387 tmpbuf
[first
+ second
+ 1] = '\0';
4391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4392 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4397 /* Might be a symbol version string. Don't as_bad here. */
4402 x86_cons (expressionS
*exp
, int size
)
4404 if (size
== 4 || (object_64bit
&& size
== 8))
4406 /* Handle @GOTOFF and the like in an expression. */
4408 char *gotfree_input_line
;
4411 save
= input_line_pointer
;
4412 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4413 if (gotfree_input_line
)
4414 input_line_pointer
= gotfree_input_line
;
4418 if (gotfree_input_line
)
4420 /* expression () has merrily parsed up to the end of line,
4421 or a comma - in the wrong buffer. Transfer how far
4422 input_line_pointer has moved to the right buffer. */
4423 input_line_pointer
= (save
4424 + (input_line_pointer
- gotfree_input_line
)
4426 free (gotfree_input_line
);
4434 static void signed_cons (int size
)
4436 if (flag_code
== CODE_64BIT
)
4444 pe_directive_secrel (dummy
)
4445 int dummy ATTRIBUTE_UNUSED
;
4452 if (exp
.X_op
== O_symbol
)
4453 exp
.X_op
= O_secrel
;
4455 emit_expr (&exp
, 4);
4457 while (*input_line_pointer
++ == ',');
4459 input_line_pointer
--;
4460 demand_empty_rest_of_line ();
4465 i386_immediate (char *imm_start
)
4467 char *save_input_line_pointer
;
4468 char *gotfree_input_line
;
4471 unsigned int types
= ~0U;
4473 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4475 as_bad (_("at most %d immediate operands are allowed"),
4476 MAX_IMMEDIATE_OPERANDS
);
4480 exp
= &im_expressions
[i
.imm_operands
++];
4481 i
.op
[this_operand
].imms
= exp
;
4483 if (is_space_char (*imm_start
))
4486 save_input_line_pointer
= input_line_pointer
;
4487 input_line_pointer
= imm_start
;
4489 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4490 if (gotfree_input_line
)
4491 input_line_pointer
= gotfree_input_line
;
4493 exp_seg
= expression (exp
);
4496 if (*input_line_pointer
)
4497 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4499 input_line_pointer
= save_input_line_pointer
;
4500 if (gotfree_input_line
)
4501 free (gotfree_input_line
);
4503 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4505 /* Missing or bad expr becomes absolute 0. */
4506 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4508 exp
->X_op
= O_constant
;
4509 exp
->X_add_number
= 0;
4510 exp
->X_add_symbol
= (symbolS
*) 0;
4511 exp
->X_op_symbol
= (symbolS
*) 0;
4513 else if (exp
->X_op
== O_constant
)
4515 /* Size it properly later. */
4516 i
.types
[this_operand
] |= Imm64
;
4517 /* If BFD64, sign extend val. */
4518 if (!use_rela_relocations
)
4519 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4520 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4522 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4523 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4524 && exp_seg
!= absolute_section
4525 && exp_seg
!= text_section
4526 && exp_seg
!= data_section
4527 && exp_seg
!= bss_section
4528 && exp_seg
!= undefined_section
4529 && !bfd_is_com_section (exp_seg
))
4531 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4535 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4537 as_bad (_("illegal immediate register operand %s"), imm_start
);
4542 /* This is an address. The size of the address will be
4543 determined later, depending on destination register,
4544 suffix, or the default for the section. */
4545 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4546 i
.types
[this_operand
] &= types
;
4553 i386_scale (char *scale
)
4556 char *save
= input_line_pointer
;
4558 input_line_pointer
= scale
;
4559 val
= get_absolute_expression ();
4564 i
.log2_scale_factor
= 0;
4567 i
.log2_scale_factor
= 1;
4570 i
.log2_scale_factor
= 2;
4573 i
.log2_scale_factor
= 3;
4577 char sep
= *input_line_pointer
;
4579 *input_line_pointer
= '\0';
4580 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4582 *input_line_pointer
= sep
;
4583 input_line_pointer
= save
;
4587 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4589 as_warn (_("scale factor of %d without an index register"),
4590 1 << i
.log2_scale_factor
);
4591 #if SCALE1_WHEN_NO_INDEX
4592 i
.log2_scale_factor
= 0;
4595 scale
= input_line_pointer
;
4596 input_line_pointer
= save
;
4601 i386_displacement (char *disp_start
, char *disp_end
)
4605 char *save_input_line_pointer
;
4606 char *gotfree_input_line
;
4607 int bigdisp
, override
;
4608 unsigned int types
= Disp
;
4610 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4612 as_bad (_("at most %d displacement operands are allowed"),
4613 MAX_MEMORY_OPERANDS
);
4617 if ((i
.types
[this_operand
] & JumpAbsolute
)
4618 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4621 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4625 /* For PC-relative branches, the width of the displacement
4626 is dependent upon data size, not address size. */
4628 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4630 if (flag_code
== CODE_64BIT
)
4633 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4635 : Disp32S
| Disp32
);
4637 bigdisp
= Disp64
| Disp32S
| Disp32
;
4644 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4646 : LONG_MNEM_SUFFIX
));
4649 if ((flag_code
== CODE_16BIT
) ^ override
)
4652 i
.types
[this_operand
] |= bigdisp
;
4654 exp
= &disp_expressions
[i
.disp_operands
];
4655 i
.op
[this_operand
].disps
= exp
;
4657 save_input_line_pointer
= input_line_pointer
;
4658 input_line_pointer
= disp_start
;
4659 END_STRING_AND_SAVE (disp_end
);
4661 #ifndef GCC_ASM_O_HACK
4662 #define GCC_ASM_O_HACK 0
4665 END_STRING_AND_SAVE (disp_end
+ 1);
4666 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4667 && displacement_string_end
[-1] == '+')
4669 /* This hack is to avoid a warning when using the "o"
4670 constraint within gcc asm statements.
4673 #define _set_tssldt_desc(n,addr,limit,type) \
4674 __asm__ __volatile__ ( \
4676 "movw %w1,2+%0\n\t" \
4678 "movb %b1,4+%0\n\t" \
4679 "movb %4,5+%0\n\t" \
4680 "movb $0,6+%0\n\t" \
4681 "movb %h1,7+%0\n\t" \
4683 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4685 This works great except that the output assembler ends
4686 up looking a bit weird if it turns out that there is
4687 no offset. You end up producing code that looks like:
4700 So here we provide the missing zero. */
4702 *displacement_string_end
= '0';
4705 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4706 if (gotfree_input_line
)
4707 input_line_pointer
= gotfree_input_line
;
4709 exp_seg
= expression (exp
);
4712 if (*input_line_pointer
)
4713 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4715 RESTORE_END_STRING (disp_end
+ 1);
4717 RESTORE_END_STRING (disp_end
);
4718 input_line_pointer
= save_input_line_pointer
;
4719 if (gotfree_input_line
)
4720 free (gotfree_input_line
);
4722 /* We do this to make sure that the section symbol is in
4723 the symbol table. We will ultimately change the relocation
4724 to be relative to the beginning of the section. */
4725 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4726 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4727 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4729 if (exp
->X_op
!= O_symbol
)
4731 as_bad (_("bad expression used with @%s"),
4732 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4738 if (S_IS_LOCAL (exp
->X_add_symbol
)
4739 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4740 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4741 exp
->X_op
= O_subtract
;
4742 exp
->X_op_symbol
= GOT_symbol
;
4743 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4744 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4745 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4746 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4748 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4751 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4753 /* Missing or bad expr becomes absolute 0. */
4754 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4756 exp
->X_op
= O_constant
;
4757 exp
->X_add_number
= 0;
4758 exp
->X_add_symbol
= (symbolS
*) 0;
4759 exp
->X_op_symbol
= (symbolS
*) 0;
4762 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4763 if (exp
->X_op
!= O_constant
4764 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4765 && exp_seg
!= absolute_section
4766 && exp_seg
!= text_section
4767 && exp_seg
!= data_section
4768 && exp_seg
!= bss_section
4769 && exp_seg
!= undefined_section
4770 && !bfd_is_com_section (exp_seg
))
4772 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4777 if (!(i
.types
[this_operand
] & ~Disp
))
4778 i
.types
[this_operand
] &= types
;
4783 /* Make sure the memory operand we've been dealt is valid.
4784 Return 1 on success, 0 on a failure. */
4787 i386_index_check (const char *operand_string
)
4790 #if INFER_ADDR_PREFIX
4796 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4797 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4799 /* Memory operands of SVME insns are special in that they only allow
4800 rAX as their memory address and ignore any segment override. */
4803 /* SKINIT is even more restrictive: it always requires EAX. */
4804 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4806 else if (flag_code
== CODE_64BIT
)
4807 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4809 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4813 || !(i
.base_reg
->reg_type
& Acc
)
4814 || !(i
.base_reg
->reg_type
& RegXX
)
4816 || (i
.types
[0] & Disp
))
4819 else if (flag_code
== CODE_64BIT
)
4821 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4824 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4825 && (i
.base_reg
->reg_type
!= BaseIndex
4828 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4829 != (RegXX
| BaseIndex
))))
4834 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4838 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4839 != (Reg16
| BaseIndex
)))
4841 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4842 != (Reg16
| BaseIndex
))
4844 && i
.base_reg
->reg_num
< 6
4845 && i
.index_reg
->reg_num
>= 6
4846 && i
.log2_scale_factor
== 0))))
4853 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4855 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4856 != (Reg32
| BaseIndex
))))
4862 #if INFER_ADDR_PREFIX
4863 if (i
.prefix
[ADDR_PREFIX
] == 0)
4865 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4867 /* Change the size of any displacement too. At most one of
4868 Disp16 or Disp32 is set.
4869 FIXME. There doesn't seem to be any real need for separate
4870 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4871 Removing them would probably clean up the code quite a lot. */
4872 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4873 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4878 as_bad (_("`%s' is not a valid base/index expression"),
4882 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4884 flag_code_names
[flag_code
]);
4889 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4893 i386_operand (char *operand_string
)
4897 char *op_string
= operand_string
;
4899 if (is_space_char (*op_string
))
4902 /* We check for an absolute prefix (differentiating,
4903 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4904 if (*op_string
== ABSOLUTE_PREFIX
)
4907 if (is_space_char (*op_string
))
4909 i
.types
[this_operand
] |= JumpAbsolute
;
4912 /* Check if operand is a register. */
4913 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4915 /* Check for a segment override by searching for ':' after a
4916 segment register. */
4918 if (is_space_char (*op_string
))
4920 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4925 i
.seg
[i
.mem_operands
] = &es
;
4928 i
.seg
[i
.mem_operands
] = &cs
;
4931 i
.seg
[i
.mem_operands
] = &ss
;
4934 i
.seg
[i
.mem_operands
] = &ds
;
4937 i
.seg
[i
.mem_operands
] = &fs
;
4940 i
.seg
[i
.mem_operands
] = &gs
;
4944 /* Skip the ':' and whitespace. */
4946 if (is_space_char (*op_string
))
4949 if (!is_digit_char (*op_string
)
4950 && !is_identifier_char (*op_string
)
4951 && *op_string
!= '('
4952 && *op_string
!= ABSOLUTE_PREFIX
)
4954 as_bad (_("bad memory operand `%s'"), op_string
);
4957 /* Handle case of %es:*foo. */
4958 if (*op_string
== ABSOLUTE_PREFIX
)
4961 if (is_space_char (*op_string
))
4963 i
.types
[this_operand
] |= JumpAbsolute
;
4965 goto do_memory_reference
;
4969 as_bad (_("junk `%s' after register"), op_string
);
4972 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4973 i
.op
[this_operand
].regs
= r
;
4976 else if (*op_string
== REGISTER_PREFIX
)
4978 as_bad (_("bad register name `%s'"), op_string
);
4981 else if (*op_string
== IMMEDIATE_PREFIX
)
4984 if (i
.types
[this_operand
] & JumpAbsolute
)
4986 as_bad (_("immediate operand illegal with absolute jump"));
4989 if (!i386_immediate (op_string
))
4992 else if (is_digit_char (*op_string
)
4993 || is_identifier_char (*op_string
)
4994 || *op_string
== '(')
4996 /* This is a memory reference of some sort. */
4999 /* Start and end of displacement string expression (if found). */
5000 char *displacement_string_start
;
5001 char *displacement_string_end
;
5003 do_memory_reference
:
5004 if ((i
.mem_operands
== 1
5005 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5006 || i
.mem_operands
== 2)
5008 as_bad (_("too many memory references for `%s'"),
5009 current_templates
->start
->name
);
5013 /* Check for base index form. We detect the base index form by
5014 looking for an ')' at the end of the operand, searching
5015 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5017 base_string
= op_string
+ strlen (op_string
);
5020 if (is_space_char (*base_string
))
5023 /* If we only have a displacement, set-up for it to be parsed later. */
5024 displacement_string_start
= op_string
;
5025 displacement_string_end
= base_string
+ 1;
5027 if (*base_string
== ')')
5030 unsigned int parens_balanced
= 1;
5031 /* We've already checked that the number of left & right ()'s are
5032 equal, so this loop will not be infinite. */
5036 if (*base_string
== ')')
5038 if (*base_string
== '(')
5041 while (parens_balanced
);
5043 temp_string
= base_string
;
5045 /* Skip past '(' and whitespace. */
5047 if (is_space_char (*base_string
))
5050 if (*base_string
== ','
5051 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
5053 displacement_string_end
= temp_string
;
5055 i
.types
[this_operand
] |= BaseIndex
;
5059 base_string
= end_op
;
5060 if (is_space_char (*base_string
))
5064 /* There may be an index reg or scale factor here. */
5065 if (*base_string
== ',')
5068 if (is_space_char (*base_string
))
5071 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
5073 base_string
= end_op
;
5074 if (is_space_char (*base_string
))
5076 if (*base_string
== ',')
5079 if (is_space_char (*base_string
))
5082 else if (*base_string
!= ')')
5084 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5089 else if (*base_string
== REGISTER_PREFIX
)
5091 as_bad (_("bad register name `%s'"), base_string
);
5095 /* Check for scale factor. */
5096 if (*base_string
!= ')')
5098 char *end_scale
= i386_scale (base_string
);
5103 base_string
= end_scale
;
5104 if (is_space_char (*base_string
))
5106 if (*base_string
!= ')')
5108 as_bad (_("expecting `)' after scale factor in `%s'"),
5113 else if (!i
.index_reg
)
5115 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5120 else if (*base_string
!= ')')
5122 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5127 else if (*base_string
== REGISTER_PREFIX
)
5129 as_bad (_("bad register name `%s'"), base_string
);
5134 /* If there's an expression beginning the operand, parse it,
5135 assuming displacement_string_start and
5136 displacement_string_end are meaningful. */
5137 if (displacement_string_start
!= displacement_string_end
)
5139 if (!i386_displacement (displacement_string_start
,
5140 displacement_string_end
))
5144 /* Special case for (%dx) while doing input/output op. */
5146 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5148 && i
.log2_scale_factor
== 0
5149 && i
.seg
[i
.mem_operands
] == 0
5150 && (i
.types
[this_operand
] & Disp
) == 0)
5152 i
.types
[this_operand
] = InOutPortReg
;
5156 if (i386_index_check (operand_string
) == 0)
5162 /* It's not a memory operand; argh! */
5163 as_bad (_("invalid char %s beginning operand %d `%s'"),
5164 output_invalid (*op_string
),
5169 return 1; /* Normal return. */
5172 /* md_estimate_size_before_relax()
5174 Called just before relax() for rs_machine_dependent frags. The x86
5175 assembler uses these frags to handle variable size jump
5178 Any symbol that is now undefined will not become defined.
5179 Return the correct fr_subtype in the frag.
5180 Return the initial "guess for variable size of frag" to caller.
5181 The guess is actually the growth beyond the fixed part. Whatever
5182 we do to grow the fixed or variable part contributes to our
5186 md_estimate_size_before_relax (fragP
, segment
)
5190 /* We've already got fragP->fr_subtype right; all we have to do is
5191 check for un-relaxable symbols. On an ELF system, we can't relax
5192 an externally visible symbol, because it may be overridden by a
5194 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5197 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5198 || S_IS_WEAK (fragP
->fr_symbol
)))
5202 /* Symbol is undefined in this segment, or we need to keep a
5203 reloc so that weak symbols can be overridden. */
5204 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5205 enum bfd_reloc_code_real reloc_type
;
5206 unsigned char *opcode
;
5209 if (fragP
->fr_var
!= NO_RELOC
)
5210 reloc_type
= fragP
->fr_var
;
5212 reloc_type
= BFD_RELOC_16_PCREL
;
5214 reloc_type
= BFD_RELOC_32_PCREL
;
5216 old_fr_fix
= fragP
->fr_fix
;
5217 opcode
= (unsigned char *) fragP
->fr_opcode
;
5219 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5222 /* Make jmp (0xeb) a (d)word displacement jump. */
5224 fragP
->fr_fix
+= size
;
5225 fix_new (fragP
, old_fr_fix
, size
,
5227 fragP
->fr_offset
, 1,
5233 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5235 /* Negate the condition, and branch past an
5236 unconditional jump. */
5239 /* Insert an unconditional jump. */
5241 /* We added two extra opcode bytes, and have a two byte
5243 fragP
->fr_fix
+= 2 + 2;
5244 fix_new (fragP
, old_fr_fix
+ 2, 2,
5246 fragP
->fr_offset
, 1,
5253 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5258 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5260 fragP
->fr_offset
, 1,
5262 fixP
->fx_signed
= 1;
5266 /* This changes the byte-displacement jump 0x7N
5267 to the (d)word-displacement jump 0x0f,0x8N. */
5268 opcode
[1] = opcode
[0] + 0x10;
5269 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5270 /* We've added an opcode byte. */
5271 fragP
->fr_fix
+= 1 + size
;
5272 fix_new (fragP
, old_fr_fix
+ 1, size
,
5274 fragP
->fr_offset
, 1,
5279 BAD_CASE (fragP
->fr_subtype
);
5283 return fragP
->fr_fix
- old_fr_fix
;
5286 /* Guess size depending on current relax state. Initially the relax
5287 state will correspond to a short jump and we return 1, because
5288 the variable part of the frag (the branch offset) is one byte
5289 long. However, we can relax a section more than once and in that
5290 case we must either set fr_subtype back to the unrelaxed state,
5291 or return the value for the appropriate branch. */
5292 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5295 /* Called after relax() is finished.
5297 In: Address of frag.
5298 fr_type == rs_machine_dependent.
5299 fr_subtype is what the address relaxed to.
5301 Out: Any fixSs and constants are set up.
5302 Caller will turn frag into a ".space 0". */
5305 md_convert_frag (abfd
, sec
, fragP
)
5306 bfd
*abfd ATTRIBUTE_UNUSED
;
5307 segT sec ATTRIBUTE_UNUSED
;
5310 unsigned char *opcode
;
5311 unsigned char *where_to_put_displacement
= NULL
;
5312 offsetT target_address
;
5313 offsetT opcode_address
;
5314 unsigned int extension
= 0;
5315 offsetT displacement_from_opcode_start
;
5317 opcode
= (unsigned char *) fragP
->fr_opcode
;
5319 /* Address we want to reach in file space. */
5320 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5322 /* Address opcode resides at in file space. */
5323 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5325 /* Displacement from opcode start to fill into instruction. */
5326 displacement_from_opcode_start
= target_address
- opcode_address
;
5328 if ((fragP
->fr_subtype
& BIG
) == 0)
5330 /* Don't have to change opcode. */
5331 extension
= 1; /* 1 opcode + 1 displacement */
5332 where_to_put_displacement
= &opcode
[1];
5336 if (no_cond_jump_promotion
5337 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5338 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
5340 switch (fragP
->fr_subtype
)
5342 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5343 extension
= 4; /* 1 opcode + 4 displacement */
5345 where_to_put_displacement
= &opcode
[1];
5348 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5349 extension
= 2; /* 1 opcode + 2 displacement */
5351 where_to_put_displacement
= &opcode
[1];
5354 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5355 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5356 extension
= 5; /* 2 opcode + 4 displacement */
5357 opcode
[1] = opcode
[0] + 0x10;
5358 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5359 where_to_put_displacement
= &opcode
[2];
5362 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5363 extension
= 3; /* 2 opcode + 2 displacement */
5364 opcode
[1] = opcode
[0] + 0x10;
5365 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5366 where_to_put_displacement
= &opcode
[2];
5369 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5374 where_to_put_displacement
= &opcode
[3];
5378 BAD_CASE (fragP
->fr_subtype
);
5383 /* If size if less then four we are sure that the operand fits,
5384 but if it's 4, then it could be that the displacement is larger
5386 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5388 && ((addressT
) (displacement_from_opcode_start
- extension
5389 + ((addressT
) 1 << 31))
5390 > (((addressT
) 2 << 31) - 1)))
5392 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5393 _("jump target out of range"));
5394 /* Make us emit 0. */
5395 displacement_from_opcode_start
= extension
;
5397 /* Now put displacement after opcode. */
5398 md_number_to_chars ((char *) where_to_put_displacement
,
5399 (valueT
) (displacement_from_opcode_start
- extension
),
5400 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5401 fragP
->fr_fix
+= extension
;
5404 /* Size of byte displacement jmp. */
5405 int md_short_jump_size
= 2;
5407 /* Size of dword displacement jmp. */
5408 int md_long_jump_size
= 5;
5411 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5413 addressT from_addr
, to_addr
;
5414 fragS
*frag ATTRIBUTE_UNUSED
;
5415 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5419 offset
= to_addr
- (from_addr
+ 2);
5420 /* Opcode for byte-disp jump. */
5421 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5422 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5426 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5428 addressT from_addr
, to_addr
;
5429 fragS
*frag ATTRIBUTE_UNUSED
;
5430 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5434 offset
= to_addr
- (from_addr
+ 5);
5435 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5436 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5439 /* Apply a fixup (fixS) to segment data, once it has been determined
5440 by our caller that we have all the info we need to fix it up.
5442 On the 386, immediates, displacements, and data pointers are all in
5443 the same (little-endian) format, so we don't need to care about which
5447 md_apply_fix (fixP
, valP
, seg
)
5448 /* The fix we're to put in. */
5450 /* Pointer to the value of the bits. */
5452 /* Segment fix is from. */
5453 segT seg ATTRIBUTE_UNUSED
;
5455 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5456 valueT value
= *valP
;
5458 #if !defined (TE_Mach)
5461 switch (fixP
->fx_r_type
)
5467 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5470 case BFD_RELOC_X86_64_32S
:
5471 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5474 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5477 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5482 if (fixP
->fx_addsy
!= NULL
5483 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5484 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5485 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5486 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5487 && !use_rela_relocations
)
5489 /* This is a hack. There should be a better way to handle this.
5490 This covers for the fact that bfd_install_relocation will
5491 subtract the current location (for partial_inplace, PC relative
5492 relocations); see more below. */
5496 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5499 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5501 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5504 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5507 || (symbol_section_p (fixP
->fx_addsy
)
5508 && sym_seg
!= absolute_section
))
5509 && !generic_force_reloc (fixP
))
5511 /* Yes, we add the values in twice. This is because
5512 bfd_install_relocation subtracts them out again. I think
5513 bfd_install_relocation is broken, but I don't dare change
5515 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5519 #if defined (OBJ_COFF) && defined (TE_PE)
5520 /* For some reason, the PE format does not store a
5521 section address offset for a PC relative symbol. */
5522 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5523 || S_IS_WEAK (fixP
->fx_addsy
))
5524 value
+= md_pcrel_from (fixP
);
5528 /* Fix a few things - the dynamic linker expects certain values here,
5529 and we must not disappoint it. */
5530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5531 if (IS_ELF
&& fixP
->fx_addsy
)
5532 switch (fixP
->fx_r_type
)
5534 case BFD_RELOC_386_PLT32
:
5535 case BFD_RELOC_X86_64_PLT32
:
5536 /* Make the jump instruction point to the address of the operand. At
5537 runtime we merely add the offset to the actual PLT entry. */
5541 case BFD_RELOC_386_TLS_GD
:
5542 case BFD_RELOC_386_TLS_LDM
:
5543 case BFD_RELOC_386_TLS_IE_32
:
5544 case BFD_RELOC_386_TLS_IE
:
5545 case BFD_RELOC_386_TLS_GOTIE
:
5546 case BFD_RELOC_386_TLS_GOTDESC
:
5547 case BFD_RELOC_X86_64_TLSGD
:
5548 case BFD_RELOC_X86_64_TLSLD
:
5549 case BFD_RELOC_X86_64_GOTTPOFF
:
5550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5551 value
= 0; /* Fully resolved at runtime. No addend. */
5553 case BFD_RELOC_386_TLS_LE
:
5554 case BFD_RELOC_386_TLS_LDO_32
:
5555 case BFD_RELOC_386_TLS_LE_32
:
5556 case BFD_RELOC_X86_64_DTPOFF32
:
5557 case BFD_RELOC_X86_64_DTPOFF64
:
5558 case BFD_RELOC_X86_64_TPOFF32
:
5559 case BFD_RELOC_X86_64_TPOFF64
:
5560 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5563 case BFD_RELOC_386_TLS_DESC_CALL
:
5564 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5565 value
= 0; /* Fully resolved at runtime. No addend. */
5566 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5570 case BFD_RELOC_386_GOT32
:
5571 case BFD_RELOC_X86_64_GOT32
:
5572 value
= 0; /* Fully resolved at runtime. No addend. */
5575 case BFD_RELOC_VTABLE_INHERIT
:
5576 case BFD_RELOC_VTABLE_ENTRY
:
5583 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5585 #endif /* !defined (TE_Mach) */
5587 /* Are we finished with this relocation now? */
5588 if (fixP
->fx_addsy
== NULL
)
5590 else if (use_rela_relocations
)
5592 fixP
->fx_no_overflow
= 1;
5593 /* Remember value for tc_gen_reloc. */
5594 fixP
->fx_addnumber
= value
;
5598 md_number_to_chars (p
, value
, fixP
->fx_size
);
5601 #define MAX_LITTLENUMS 6
5603 /* Turn the string pointed to by litP into a floating point constant
5604 of type TYPE, and emit the appropriate bytes. The number of
5605 LITTLENUMS emitted is stored in *SIZEP. An error message is
5606 returned, or NULL on OK. */
5609 md_atof (type
, litP
, sizeP
)
5615 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5616 LITTLENUM_TYPE
*wordP
;
5638 return _("Bad call to md_atof ()");
5640 t
= atof_ieee (input_line_pointer
, type
, words
);
5642 input_line_pointer
= t
;
5644 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5645 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5646 the bigendian 386. */
5647 for (wordP
= words
+ prec
- 1; prec
--;)
5649 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5650 litP
+= sizeof (LITTLENUM_TYPE
);
5655 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5658 output_invalid (int c
)
5661 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5664 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5665 "(0x%x)", (unsigned char) c
);
5666 return output_invalid_buf
;
5669 /* REG_STRING starts *before* REGISTER_PREFIX. */
5671 static const reg_entry
*
5672 parse_real_register (char *reg_string
, char **end_op
)
5674 char *s
= reg_string
;
5676 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5679 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5680 if (*s
== REGISTER_PREFIX
)
5683 if (is_space_char (*s
))
5687 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5689 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5690 return (const reg_entry
*) NULL
;
5694 /* For naked regs, make sure that we are not dealing with an identifier.
5695 This prevents confusing an identifier like `eax_var' with register
5697 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5698 return (const reg_entry
*) NULL
;
5702 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5704 /* Handle floating point regs, allowing spaces in the (i) part. */
5705 if (r
== i386_regtab
/* %st is first entry of table */)
5707 if (is_space_char (*s
))
5712 if (is_space_char (*s
))
5714 if (*s
>= '0' && *s
<= '7')
5716 r
= &i386_float_regtab
[*s
- '0'];
5718 if (is_space_char (*s
))
5726 /* We have "%st(" then garbage. */
5727 return (const reg_entry
*) NULL
;
5732 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5733 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5734 && flag_code
!= CODE_64BIT
)
5735 return (const reg_entry
*) NULL
;
5740 /* REG_STRING starts *before* REGISTER_PREFIX. */
5742 static const reg_entry
*
5743 parse_register (char *reg_string
, char **end_op
)
5747 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5748 r
= parse_real_register (reg_string
, end_op
);
5753 char *save
= input_line_pointer
;
5757 input_line_pointer
= reg_string
;
5758 c
= get_symbol_end ();
5759 symbolP
= symbol_find (reg_string
);
5760 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5762 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5764 know (e
->X_op
== O_register
);
5765 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5766 r
= i386_regtab
+ e
->X_add_number
;
5767 *end_op
= input_line_pointer
;
5769 *input_line_pointer
= c
;
5770 input_line_pointer
= save
;
5776 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5779 char *end
= input_line_pointer
;
5782 r
= parse_register (name
, &input_line_pointer
);
5783 if (r
&& end
<= input_line_pointer
)
5785 *nextcharP
= *input_line_pointer
;
5786 *input_line_pointer
= 0;
5787 e
->X_op
= O_register
;
5788 e
->X_add_number
= r
- i386_regtab
;
5791 input_line_pointer
= end
;
5797 md_operand (expressionS
*e
)
5799 if (*input_line_pointer
== REGISTER_PREFIX
)
5802 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5806 e
->X_op
= O_register
;
5807 e
->X_add_number
= r
- i386_regtab
;
5808 input_line_pointer
= end
;
5814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5815 const char *md_shortopts
= "kVQ:sqn";
5817 const char *md_shortopts
= "qn";
5820 #define OPTION_32 (OPTION_MD_BASE + 0)
5821 #define OPTION_64 (OPTION_MD_BASE + 1)
5822 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5823 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5824 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5826 struct option md_longopts
[] =
5828 {"32", no_argument
, NULL
, OPTION_32
},
5829 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5830 {"64", no_argument
, NULL
, OPTION_64
},
5832 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5833 {"march", required_argument
, NULL
, OPTION_MARCH
},
5834 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5835 {NULL
, no_argument
, NULL
, 0}
5837 size_t md_longopts_size
= sizeof (md_longopts
);
5840 md_parse_option (int c
, char *arg
)
5847 optimize_align_code
= 0;
5854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5855 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5856 should be emitted or not. FIXME: Not implemented. */
5860 /* -V: SVR4 argument to print version ID. */
5862 print_version_id ();
5865 /* -k: Ignore for FreeBSD compatibility. */
5870 /* -s: On i386 Solaris, this tells the native assembler to use
5871 .stab instead of .stab.excl. We always use .stab anyhow. */
5874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5877 const char **list
, **l
;
5879 list
= bfd_target_list ();
5880 for (l
= list
; *l
!= NULL
; l
++)
5881 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5882 || strcmp (*l
, "coff-x86-64") == 0
5883 || strcmp (*l
, "pe-x86-64") == 0
5884 || strcmp (*l
, "pei-x86-64") == 0)
5886 default_arch
= "x86_64";
5890 as_fatal (_("No compiled in support for x86_64"));
5897 default_arch
= "i386";
5901 #ifdef SVR4_COMMENT_CHARS
5906 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5908 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5912 i386_comment_chars
= n
;
5919 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5920 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5922 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5924 cpu_arch_isa
= cpu_arch
[i
].type
;
5925 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5926 if (!cpu_arch_tune_set
)
5928 cpu_arch_tune
= cpu_arch_isa
;
5929 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5934 if (i
>= ARRAY_SIZE (cpu_arch
))
5935 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5940 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5941 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5943 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5945 cpu_arch_tune_set
= 1;
5946 cpu_arch_tune
= cpu_arch
[i
].type
;
5947 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5951 if (i
>= ARRAY_SIZE (cpu_arch
))
5952 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5962 md_show_usage (stream
)
5965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5966 fprintf (stream
, _("\
5968 -V print assembler version number\n\
5971 fprintf (stream
, _("\
5972 -n Do not optimize code alignment\n\
5973 -q quieten some warnings\n"));
5974 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5975 fprintf (stream
, _("\
5978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5979 fprintf (stream
, _("\
5980 --32/--64 generate 32bit/64bit code\n"));
5982 #ifdef SVR4_COMMENT_CHARS
5983 fprintf (stream
, _("\
5984 --divide do not treat `/' as a comment character\n"));
5986 fprintf (stream
, _("\
5987 --divide ignored\n"));
5989 fprintf (stream
, _("\
5990 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5991 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5992 core, core2, k6, athlon, k8, generic32, generic64\n"));
5998 x86_64_target_format (void)
6000 if (strcmp (default_arch
, "x86_64") == 0)
6002 set_code_flag (CODE_64BIT
);
6003 return COFF_TARGET_FORMAT
;
6005 else if (strcmp (default_arch
, "i386") == 0)
6007 set_code_flag (CODE_32BIT
);
6011 as_fatal (_("Unknown architecture"));
6016 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6017 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6019 /* Pick the target format to use. */
6022 i386_target_format (void)
6024 if (!strcmp (default_arch
, "x86_64"))
6026 set_code_flag (CODE_64BIT
);
6027 if (cpu_arch_isa_flags
== 0)
6028 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6029 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6031 if (cpu_arch_tune_flags
== 0)
6032 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6033 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6036 else if (!strcmp (default_arch
, "i386"))
6038 set_code_flag (CODE_32BIT
);
6039 if (cpu_arch_isa_flags
== 0)
6040 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6041 if (cpu_arch_tune_flags
== 0)
6042 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6045 as_fatal (_("Unknown architecture"));
6046 switch (OUTPUT_FLAVOR
)
6048 #ifdef OBJ_MAYBE_AOUT
6049 case bfd_target_aout_flavour
:
6050 return AOUT_TARGET_FORMAT
;
6052 #ifdef OBJ_MAYBE_COFF
6053 case bfd_target_coff_flavour
:
6056 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6057 case bfd_target_elf_flavour
:
6059 if (flag_code
== CODE_64BIT
)
6062 use_rela_relocations
= 1;
6064 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6073 #endif /* OBJ_MAYBE_ more than one */
6075 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6077 i386_elf_emit_arch_note (void)
6079 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6082 asection
*seg
= now_seg
;
6083 subsegT subseg
= now_subseg
;
6084 Elf_Internal_Note i_note
;
6085 Elf_External_Note e_note
;
6086 asection
*note_secp
;
6089 /* Create the .note section. */
6090 note_secp
= subseg_new (".note", 0);
6091 bfd_set_section_flags (stdoutput
,
6093 SEC_HAS_CONTENTS
| SEC_READONLY
);
6095 /* Process the arch string. */
6096 len
= strlen (cpu_arch_name
);
6098 i_note
.namesz
= len
+ 1;
6100 i_note
.type
= NT_ARCH
;
6101 p
= frag_more (sizeof (e_note
.namesz
));
6102 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6103 p
= frag_more (sizeof (e_note
.descsz
));
6104 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6105 p
= frag_more (sizeof (e_note
.type
));
6106 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6107 p
= frag_more (len
+ 1);
6108 strcpy (p
, cpu_arch_name
);
6110 frag_align (2, 0, 0);
6112 subseg_set (seg
, subseg
);
6118 md_undefined_symbol (name
)
6121 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6122 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6123 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6124 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6128 if (symbol_find (name
))
6129 as_bad (_("GOT already in symbol table"));
6130 GOT_symbol
= symbol_new (name
, undefined_section
,
6131 (valueT
) 0, &zero_address_frag
);
6138 /* Round up a section size to the appropriate boundary. */
6141 md_section_align (segment
, size
)
6142 segT segment ATTRIBUTE_UNUSED
;
6145 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6146 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6148 /* For a.out, force the section size to be aligned. If we don't do
6149 this, BFD will align it for us, but it will not write out the
6150 final bytes of the section. This may be a bug in BFD, but it is
6151 easier to fix it here since that is how the other a.out targets
6155 align
= bfd_get_section_alignment (stdoutput
, segment
);
6156 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6163 /* On the i386, PC-relative offsets are relative to the start of the
6164 next instruction. That is, the address of the offset, plus its
6165 size, since the offset is always the last part of the insn. */
6168 md_pcrel_from (fixS
*fixP
)
6170 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6176 s_bss (int ignore ATTRIBUTE_UNUSED
)
6180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6182 obj_elf_section_change_hook ();
6184 temp
= get_absolute_expression ();
6185 subseg_set (bss_section
, (subsegT
) temp
);
6186 demand_empty_rest_of_line ();
6192 i386_validate_fix (fixS
*fixp
)
6194 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6196 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6200 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6205 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6207 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6214 tc_gen_reloc (section
, fixp
)
6215 asection
*section ATTRIBUTE_UNUSED
;
6219 bfd_reloc_code_real_type code
;
6221 switch (fixp
->fx_r_type
)
6223 case BFD_RELOC_X86_64_PLT32
:
6224 case BFD_RELOC_X86_64_GOT32
:
6225 case BFD_RELOC_X86_64_GOTPCREL
:
6226 case BFD_RELOC_386_PLT32
:
6227 case BFD_RELOC_386_GOT32
:
6228 case BFD_RELOC_386_GOTOFF
:
6229 case BFD_RELOC_386_GOTPC
:
6230 case BFD_RELOC_386_TLS_GD
:
6231 case BFD_RELOC_386_TLS_LDM
:
6232 case BFD_RELOC_386_TLS_LDO_32
:
6233 case BFD_RELOC_386_TLS_IE_32
:
6234 case BFD_RELOC_386_TLS_IE
:
6235 case BFD_RELOC_386_TLS_GOTIE
:
6236 case BFD_RELOC_386_TLS_LE_32
:
6237 case BFD_RELOC_386_TLS_LE
:
6238 case BFD_RELOC_386_TLS_GOTDESC
:
6239 case BFD_RELOC_386_TLS_DESC_CALL
:
6240 case BFD_RELOC_X86_64_TLSGD
:
6241 case BFD_RELOC_X86_64_TLSLD
:
6242 case BFD_RELOC_X86_64_DTPOFF32
:
6243 case BFD_RELOC_X86_64_DTPOFF64
:
6244 case BFD_RELOC_X86_64_GOTTPOFF
:
6245 case BFD_RELOC_X86_64_TPOFF32
:
6246 case BFD_RELOC_X86_64_TPOFF64
:
6247 case BFD_RELOC_X86_64_GOTOFF64
:
6248 case BFD_RELOC_X86_64_GOTPC32
:
6249 case BFD_RELOC_X86_64_GOT64
:
6250 case BFD_RELOC_X86_64_GOTPCREL64
:
6251 case BFD_RELOC_X86_64_GOTPC64
:
6252 case BFD_RELOC_X86_64_GOTPLT64
:
6253 case BFD_RELOC_X86_64_PLTOFF64
:
6254 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6255 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6257 case BFD_RELOC_VTABLE_ENTRY
:
6258 case BFD_RELOC_VTABLE_INHERIT
:
6260 case BFD_RELOC_32_SECREL
:
6262 code
= fixp
->fx_r_type
;
6264 case BFD_RELOC_X86_64_32S
:
6265 if (!fixp
->fx_pcrel
)
6267 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6268 code
= fixp
->fx_r_type
;
6274 switch (fixp
->fx_size
)
6277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6278 _("can not do %d byte pc-relative relocation"),
6280 code
= BFD_RELOC_32_PCREL
;
6282 case 1: code
= BFD_RELOC_8_PCREL
; break;
6283 case 2: code
= BFD_RELOC_16_PCREL
; break;
6284 case 4: code
= BFD_RELOC_32_PCREL
; break;
6286 case 8: code
= BFD_RELOC_64_PCREL
; break;
6292 switch (fixp
->fx_size
)
6295 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6296 _("can not do %d byte relocation"),
6298 code
= BFD_RELOC_32
;
6300 case 1: code
= BFD_RELOC_8
; break;
6301 case 2: code
= BFD_RELOC_16
; break;
6302 case 4: code
= BFD_RELOC_32
; break;
6304 case 8: code
= BFD_RELOC_64
; break;
6311 if ((code
== BFD_RELOC_32
6312 || code
== BFD_RELOC_32_PCREL
6313 || code
== BFD_RELOC_X86_64_32S
)
6315 && fixp
->fx_addsy
== GOT_symbol
)
6318 code
= BFD_RELOC_386_GOTPC
;
6320 code
= BFD_RELOC_X86_64_GOTPC32
;
6322 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6324 && fixp
->fx_addsy
== GOT_symbol
)
6326 code
= BFD_RELOC_X86_64_GOTPC64
;
6329 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6330 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6331 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6333 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6335 if (!use_rela_relocations
)
6337 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6338 vtable entry to be used in the relocation's section offset. */
6339 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6340 rel
->address
= fixp
->fx_offset
;
6344 /* Use the rela in 64bit mode. */
6347 if (!fixp
->fx_pcrel
)
6348 rel
->addend
= fixp
->fx_offset
;
6352 case BFD_RELOC_X86_64_PLT32
:
6353 case BFD_RELOC_X86_64_GOT32
:
6354 case BFD_RELOC_X86_64_GOTPCREL
:
6355 case BFD_RELOC_X86_64_TLSGD
:
6356 case BFD_RELOC_X86_64_TLSLD
:
6357 case BFD_RELOC_X86_64_GOTTPOFF
:
6358 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6359 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6360 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6363 rel
->addend
= (section
->vma
6365 + fixp
->fx_addnumber
6366 + md_pcrel_from (fixp
));
6371 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6372 if (rel
->howto
== NULL
)
6374 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6375 _("cannot represent relocation type %s"),
6376 bfd_get_reloc_code_name (code
));
6377 /* Set howto to a garbage value so that we can keep going. */
6378 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6379 assert (rel
->howto
!= NULL
);
6386 /* Parse operands using Intel syntax. This implements a recursive descent
6387 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6390 FIXME: We do not recognize the full operand grammar defined in the MASM
6391 documentation. In particular, all the structure/union and
6392 high-level macro operands are missing.
6394 Uppercase words are terminals, lower case words are non-terminals.
6395 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6396 bars '|' denote choices. Most grammar productions are implemented in
6397 functions called 'intel_<production>'.
6399 Initial production is 'expr'.
6405 binOp & | AND | \| | OR | ^ | XOR
6407 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6409 constant digits [[ radixOverride ]]
6411 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6449 => expr expr cmpOp e04
6452 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6453 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6455 hexdigit a | b | c | d | e | f
6456 | A | B | C | D | E | F
6462 mulOp * | / | % | MOD | << | SHL | >> | SHR
6466 register specialRegister
6470 segmentRegister CS | DS | ES | FS | GS | SS
6472 specialRegister CR0 | CR2 | CR3 | CR4
6473 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6474 | TR3 | TR4 | TR5 | TR6 | TR7
6476 We simplify the grammar in obvious places (e.g., register parsing is
6477 done by calling parse_register) and eliminate immediate left recursion
6478 to implement a recursive-descent parser.
6482 expr' cmpOp e04 expr'
6533 /* Parsing structure for the intel syntax parser. Used to implement the
6534 semantic actions for the operand grammar. */
6535 struct intel_parser_s
6537 char *op_string
; /* The string being parsed. */
6538 int got_a_float
; /* Whether the operand is a float. */
6539 int op_modifier
; /* Operand modifier. */
6540 int is_mem
; /* 1 if operand is memory reference. */
6541 int in_offset
; /* >=1 if parsing operand of offset. */
6542 int in_bracket
; /* >=1 if parsing operand in brackets. */
6543 const reg_entry
*reg
; /* Last register reference found. */
6544 char *disp
; /* Displacement string being built. */
6545 char *next_operand
; /* Resume point when splitting operands. */
6548 static struct intel_parser_s intel_parser
;
6550 /* Token structure for parsing intel syntax. */
6553 int code
; /* Token code. */
6554 const reg_entry
*reg
; /* Register entry for register tokens. */
6555 char *str
; /* String representation. */
6558 static struct intel_token cur_token
, prev_token
;
6560 /* Token codes for the intel parser. Since T_SHORT is already used
6561 by COFF, undefine it first to prevent a warning. */
6580 /* Prototypes for intel parser functions. */
6581 static int intel_match_token (int);
6582 static void intel_putback_token (void);
6583 static void intel_get_token (void);
6584 static int intel_expr (void);
6585 static int intel_e04 (void);
6586 static int intel_e05 (void);
6587 static int intel_e06 (void);
6588 static int intel_e09 (void);
6589 static int intel_e10 (void);
6590 static int intel_e11 (void);
6593 i386_intel_operand (char *operand_string
, int got_a_float
)
6598 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6599 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6603 /* Initialize token holders. */
6604 cur_token
.code
= prev_token
.code
= T_NIL
;
6605 cur_token
.reg
= prev_token
.reg
= NULL
;
6606 cur_token
.str
= prev_token
.str
= NULL
;
6608 /* Initialize parser structure. */
6609 intel_parser
.got_a_float
= got_a_float
;
6610 intel_parser
.op_modifier
= 0;
6611 intel_parser
.is_mem
= 0;
6612 intel_parser
.in_offset
= 0;
6613 intel_parser
.in_bracket
= 0;
6614 intel_parser
.reg
= NULL
;
6615 intel_parser
.disp
[0] = '\0';
6616 intel_parser
.next_operand
= NULL
;
6618 /* Read the first token and start the parser. */
6620 ret
= intel_expr ();
6625 if (cur_token
.code
!= T_NIL
)
6627 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6628 current_templates
->start
->name
, cur_token
.str
);
6631 /* If we found a memory reference, hand it over to i386_displacement
6632 to fill in the rest of the operand fields. */
6633 else if (intel_parser
.is_mem
)
6635 if ((i
.mem_operands
== 1
6636 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6637 || i
.mem_operands
== 2)
6639 as_bad (_("too many memory references for '%s'"),
6640 current_templates
->start
->name
);
6645 char *s
= intel_parser
.disp
;
6648 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6649 /* See the comments in intel_bracket_expr. */
6650 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6652 /* Add the displacement expression. */
6654 ret
= i386_displacement (s
, s
+ strlen (s
));
6657 /* Swap base and index in 16-bit memory operands like
6658 [si+bx]. Since i386_index_check is also used in AT&T
6659 mode we have to do that here. */
6662 && (i
.base_reg
->reg_type
& Reg16
)
6663 && (i
.index_reg
->reg_type
& Reg16
)
6664 && i
.base_reg
->reg_num
>= 6
6665 && i
.index_reg
->reg_num
< 6)
6667 const reg_entry
*base
= i
.index_reg
;
6669 i
.index_reg
= i
.base_reg
;
6672 ret
= i386_index_check (operand_string
);
6677 /* Constant and OFFSET expressions are handled by i386_immediate. */
6678 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6679 || intel_parser
.reg
== NULL
)
6680 ret
= i386_immediate (intel_parser
.disp
);
6682 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6684 if (!ret
|| !intel_parser
.next_operand
)
6686 intel_parser
.op_string
= intel_parser
.next_operand
;
6687 this_operand
= i
.operands
++;
6691 free (intel_parser
.disp
);
6696 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6700 expr' cmpOp e04 expr'
6705 /* XXX Implement the comparison operators. */
6706 return intel_e04 ();
6723 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6724 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6726 if (cur_token
.code
== '+')
6728 else if (cur_token
.code
== '-')
6729 nregs
= NUM_ADDRESS_REGS
;
6733 strcat (intel_parser
.disp
, cur_token
.str
);
6734 intel_match_token (cur_token
.code
);
6745 int nregs
= ~NUM_ADDRESS_REGS
;
6752 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6756 str
[0] = cur_token
.code
;
6758 strcat (intel_parser
.disp
, str
);
6763 intel_match_token (cur_token
.code
);
6768 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6769 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6780 int nregs
= ~NUM_ADDRESS_REGS
;
6787 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6791 str
[0] = cur_token
.code
;
6793 strcat (intel_parser
.disp
, str
);
6795 else if (cur_token
.code
== T_SHL
)
6796 strcat (intel_parser
.disp
, "<<");
6797 else if (cur_token
.code
== T_SHR
)
6798 strcat (intel_parser
.disp
, ">>");
6802 intel_match_token (cur_token
.code
);
6807 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6808 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6826 int nregs
= ~NUM_ADDRESS_REGS
;
6831 /* Don't consume constants here. */
6832 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6834 /* Need to look one token ahead - if the next token
6835 is a constant, the current token is its sign. */
6838 intel_match_token (cur_token
.code
);
6839 next_code
= cur_token
.code
;
6840 intel_putback_token ();
6841 if (next_code
== T_CONST
)
6845 /* e09 OFFSET e09 */
6846 if (cur_token
.code
== T_OFFSET
)
6849 ++intel_parser
.in_offset
;
6853 else if (cur_token
.code
== T_SHORT
)
6854 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6857 else if (cur_token
.code
== '+')
6858 strcat (intel_parser
.disp
, "+");
6863 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6869 str
[0] = cur_token
.code
;
6871 strcat (intel_parser
.disp
, str
);
6878 intel_match_token (cur_token
.code
);
6886 /* e09' PTR e10 e09' */
6887 if (cur_token
.code
== T_PTR
)
6891 if (prev_token
.code
== T_BYTE
)
6892 suffix
= BYTE_MNEM_SUFFIX
;
6894 else if (prev_token
.code
== T_WORD
)
6896 if (current_templates
->start
->name
[0] == 'l'
6897 && current_templates
->start
->name
[2] == 's'
6898 && current_templates
->start
->name
[3] == 0)
6899 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6900 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6901 suffix
= SHORT_MNEM_SUFFIX
;
6903 suffix
= WORD_MNEM_SUFFIX
;
6906 else if (prev_token
.code
== T_DWORD
)
6908 if (current_templates
->start
->name
[0] == 'l'
6909 && current_templates
->start
->name
[2] == 's'
6910 && current_templates
->start
->name
[3] == 0)
6911 suffix
= WORD_MNEM_SUFFIX
;
6912 else if (flag_code
== CODE_16BIT
6913 && (current_templates
->start
->opcode_modifier
6914 & (Jump
| JumpDword
)))
6915 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6916 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6917 suffix
= SHORT_MNEM_SUFFIX
;
6919 suffix
= LONG_MNEM_SUFFIX
;
6922 else if (prev_token
.code
== T_FWORD
)
6924 if (current_templates
->start
->name
[0] == 'l'
6925 && current_templates
->start
->name
[2] == 's'
6926 && current_templates
->start
->name
[3] == 0)
6927 suffix
= LONG_MNEM_SUFFIX
;
6928 else if (!intel_parser
.got_a_float
)
6930 if (flag_code
== CODE_16BIT
)
6931 add_prefix (DATA_PREFIX_OPCODE
);
6932 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6935 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6938 else if (prev_token
.code
== T_QWORD
)
6940 if (intel_parser
.got_a_float
== 1) /* "f..." */
6941 suffix
= LONG_MNEM_SUFFIX
;
6943 suffix
= QWORD_MNEM_SUFFIX
;
6946 else if (prev_token
.code
== T_TBYTE
)
6948 if (intel_parser
.got_a_float
== 1)
6949 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6951 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6954 else if (prev_token
.code
== T_XMMWORD
)
6956 /* XXX ignored for now, but accepted since gcc uses it */
6962 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6966 /* Operands for jump/call using 'ptr' notation denote absolute
6968 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6969 i
.types
[this_operand
] |= JumpAbsolute
;
6971 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6975 else if (i
.suffix
!= suffix
)
6977 as_bad (_("Conflicting operand modifiers"));
6983 /* e09' : e10 e09' */
6984 else if (cur_token
.code
== ':')
6986 if (prev_token
.code
!= T_REG
)
6988 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6989 segment/group identifier (which we don't have), using comma
6990 as the operand separator there is even less consistent, since
6991 there all branches only have a single operand. */
6992 if (this_operand
!= 0
6993 || intel_parser
.in_offset
6994 || intel_parser
.in_bracket
6995 || (!(current_templates
->start
->opcode_modifier
6996 & (Jump
|JumpDword
|JumpInterSegment
))
6997 && !(current_templates
->start
->operand_types
[0]
6999 return intel_match_token (T_NIL
);
7000 /* Remember the start of the 2nd operand and terminate 1st
7002 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7003 another expression), but it gets at least the simplest case
7004 (a plain number or symbol on the left side) right. */
7005 intel_parser
.next_operand
= intel_parser
.op_string
;
7006 *--intel_parser
.op_string
= '\0';
7007 return intel_match_token (':');
7015 intel_match_token (cur_token
.code
);
7021 --intel_parser
.in_offset
;
7024 if (NUM_ADDRESS_REGS
> nregs
)
7026 as_bad (_("Invalid operand to `OFFSET'"));
7029 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7032 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7033 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7038 intel_bracket_expr (void)
7040 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7041 const char *start
= intel_parser
.op_string
;
7044 if (i
.op
[this_operand
].regs
)
7045 return intel_match_token (T_NIL
);
7047 intel_match_token ('[');
7049 /* Mark as a memory operand only if it's not already known to be an
7050 offset expression. If it's an offset expression, we need to keep
7052 if (!intel_parser
.in_offset
)
7054 ++intel_parser
.in_bracket
;
7056 /* Operands for jump/call inside brackets denote absolute addresses. */
7057 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7058 i
.types
[this_operand
] |= JumpAbsolute
;
7060 /* Unfortunately gas always diverged from MASM in a respect that can't
7061 be easily fixed without risking to break code sequences likely to be
7062 encountered (the testsuite even check for this): MASM doesn't consider
7063 an expression inside brackets unconditionally as a memory reference.
7064 When that is e.g. a constant, an offset expression, or the sum of the
7065 two, this is still taken as a constant load. gas, however, always
7066 treated these as memory references. As a compromise, we'll try to make
7067 offset expressions inside brackets work the MASM way (since that's
7068 less likely to be found in real world code), but make constants alone
7069 continue to work the traditional gas way. In either case, issue a
7071 intel_parser
.op_modifier
&= ~was_offset
;
7074 strcat (intel_parser
.disp
, "[");
7076 /* Add a '+' to the displacement string if necessary. */
7077 if (*intel_parser
.disp
!= '\0'
7078 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7079 strcat (intel_parser
.disp
, "+");
7082 && (len
= intel_parser
.op_string
- start
- 1,
7083 intel_match_token (']')))
7085 /* Preserve brackets when the operand is an offset expression. */
7086 if (intel_parser
.in_offset
)
7087 strcat (intel_parser
.disp
, "]");
7090 --intel_parser
.in_bracket
;
7091 if (i
.base_reg
|| i
.index_reg
)
7092 intel_parser
.is_mem
= 1;
7093 if (!intel_parser
.is_mem
)
7095 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7096 /* Defer the warning until all of the operand was parsed. */
7097 intel_parser
.is_mem
= -1;
7098 else if (!quiet_warnings
)
7099 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
7102 intel_parser
.op_modifier
|= was_offset
;
7119 while (cur_token
.code
== '[')
7121 if (!intel_bracket_expr ())
7146 switch (cur_token
.code
)
7150 intel_match_token ('(');
7151 strcat (intel_parser
.disp
, "(");
7153 if (intel_expr () && intel_match_token (')'))
7155 strcat (intel_parser
.disp
, ")");
7162 return intel_bracket_expr ();
7167 strcat (intel_parser
.disp
, cur_token
.str
);
7168 intel_match_token (cur_token
.code
);
7170 /* Mark as a memory operand only if it's not already known to be an
7171 offset expression. */
7172 if (!intel_parser
.in_offset
)
7173 intel_parser
.is_mem
= 1;
7180 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7182 intel_match_token (T_REG
);
7184 /* Check for segment change. */
7185 if (cur_token
.code
== ':')
7187 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7189 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
7192 else if (i
.seg
[i
.mem_operands
])
7193 as_warn (_("Extra segment override ignored"));
7196 if (!intel_parser
.in_offset
)
7197 intel_parser
.is_mem
= 1;
7198 switch (reg
->reg_num
)
7201 i
.seg
[i
.mem_operands
] = &es
;
7204 i
.seg
[i
.mem_operands
] = &cs
;
7207 i
.seg
[i
.mem_operands
] = &ss
;
7210 i
.seg
[i
.mem_operands
] = &ds
;
7213 i
.seg
[i
.mem_operands
] = &fs
;
7216 i
.seg
[i
.mem_operands
] = &gs
;
7222 /* Not a segment register. Check for register scaling. */
7223 else if (cur_token
.code
== '*')
7225 if (!intel_parser
.in_bracket
)
7227 as_bad (_("Register scaling only allowed in memory operands"));
7231 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7232 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7233 else if (i
.index_reg
)
7234 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7236 /* What follows must be a valid scale. */
7237 intel_match_token ('*');
7239 i
.types
[this_operand
] |= BaseIndex
;
7241 /* Set the scale after setting the register (otherwise,
7242 i386_scale will complain) */
7243 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7245 char *str
, sign
= cur_token
.code
;
7246 intel_match_token (cur_token
.code
);
7247 if (cur_token
.code
!= T_CONST
)
7249 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7253 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7254 strcpy (str
+ 1, cur_token
.str
);
7256 if (!i386_scale (str
))
7260 else if (!i386_scale (cur_token
.str
))
7262 intel_match_token (cur_token
.code
);
7265 /* No scaling. If this is a memory operand, the register is either a
7266 base register (first occurrence) or an index register (second
7268 else if (intel_parser
.in_bracket
)
7273 else if (!i
.index_reg
)
7277 as_bad (_("Too many register references in memory operand"));
7281 i
.types
[this_operand
] |= BaseIndex
;
7284 /* It's neither base nor index. */
7285 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7287 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7288 i
.op
[this_operand
].regs
= reg
;
7293 as_bad (_("Invalid use of register"));
7297 /* Since registers are not part of the displacement string (except
7298 when we're parsing offset operands), we may need to remove any
7299 preceding '+' from the displacement string. */
7300 if (*intel_parser
.disp
!= '\0'
7301 && !intel_parser
.in_offset
)
7303 char *s
= intel_parser
.disp
;
7304 s
+= strlen (s
) - 1;
7327 intel_match_token (cur_token
.code
);
7329 if (cur_token
.code
== T_PTR
)
7332 /* It must have been an identifier. */
7333 intel_putback_token ();
7334 cur_token
.code
= T_ID
;
7340 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7344 /* The identifier represents a memory reference only if it's not
7345 preceded by an offset modifier and if it's not an equate. */
7346 symbolP
= symbol_find(cur_token
.str
);
7347 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7348 intel_parser
.is_mem
= 1;
7356 char *save_str
, sign
= 0;
7358 /* Allow constants that start with `+' or `-'. */
7359 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7361 sign
= cur_token
.code
;
7362 intel_match_token (cur_token
.code
);
7363 if (cur_token
.code
!= T_CONST
)
7365 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7371 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7372 strcpy (save_str
+ !!sign
, cur_token
.str
);
7376 /* Get the next token to check for register scaling. */
7377 intel_match_token (cur_token
.code
);
7379 /* Check if this constant is a scaling factor for an index register. */
7380 if (cur_token
.code
== '*')
7382 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7384 const reg_entry
*reg
= cur_token
.reg
;
7386 if (!intel_parser
.in_bracket
)
7388 as_bad (_("Register scaling only allowed in memory operands"));
7392 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
7393 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7394 else if (i
.index_reg
)
7395 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7397 /* The constant is followed by `* reg', so it must be
7400 i
.types
[this_operand
] |= BaseIndex
;
7402 /* Set the scale after setting the register (otherwise,
7403 i386_scale will complain) */
7404 if (!i386_scale (save_str
))
7406 intel_match_token (T_REG
);
7408 /* Since registers are not part of the displacement
7409 string, we may need to remove any preceding '+' from
7410 the displacement string. */
7411 if (*intel_parser
.disp
!= '\0')
7413 char *s
= intel_parser
.disp
;
7414 s
+= strlen (s
) - 1;
7424 /* The constant was not used for register scaling. Since we have
7425 already consumed the token following `*' we now need to put it
7426 back in the stream. */
7427 intel_putback_token ();
7430 /* Add the constant to the displacement string. */
7431 strcat (intel_parser
.disp
, save_str
);
7438 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7442 /* Match the given token against cur_token. If they match, read the next
7443 token from the operand string. */
7445 intel_match_token (int code
)
7447 if (cur_token
.code
== code
)
7454 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7459 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7461 intel_get_token (void)
7464 const reg_entry
*reg
;
7465 struct intel_token new_token
;
7467 new_token
.code
= T_NIL
;
7468 new_token
.reg
= NULL
;
7469 new_token
.str
= NULL
;
7471 /* Free the memory allocated to the previous token and move
7472 cur_token to prev_token. */
7474 free (prev_token
.str
);
7476 prev_token
= cur_token
;
7478 /* Skip whitespace. */
7479 while (is_space_char (*intel_parser
.op_string
))
7480 intel_parser
.op_string
++;
7482 /* Return an empty token if we find nothing else on the line. */
7483 if (*intel_parser
.op_string
== '\0')
7485 cur_token
= new_token
;
7489 /* The new token cannot be larger than the remainder of the operand
7491 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7492 new_token
.str
[0] = '\0';
7494 if (strchr ("0123456789", *intel_parser
.op_string
))
7496 char *p
= new_token
.str
;
7497 char *q
= intel_parser
.op_string
;
7498 new_token
.code
= T_CONST
;
7500 /* Allow any kind of identifier char to encompass floating point and
7501 hexadecimal numbers. */
7502 while (is_identifier_char (*q
))
7506 /* Recognize special symbol names [0-9][bf]. */
7507 if (strlen (intel_parser
.op_string
) == 2
7508 && (intel_parser
.op_string
[1] == 'b'
7509 || intel_parser
.op_string
[1] == 'f'))
7510 new_token
.code
= T_ID
;
7513 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7515 size_t len
= end_op
- intel_parser
.op_string
;
7517 new_token
.code
= T_REG
;
7518 new_token
.reg
= reg
;
7520 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7521 new_token
.str
[len
] = '\0';
7524 else if (is_identifier_char (*intel_parser
.op_string
))
7526 char *p
= new_token
.str
;
7527 char *q
= intel_parser
.op_string
;
7529 /* A '.' or '$' followed by an identifier char is an identifier.
7530 Otherwise, it's operator '.' followed by an expression. */
7531 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7533 new_token
.code
= '.';
7534 new_token
.str
[0] = '.';
7535 new_token
.str
[1] = '\0';
7539 while (is_identifier_char (*q
) || *q
== '@')
7543 if (strcasecmp (new_token
.str
, "NOT") == 0)
7544 new_token
.code
= '~';
7546 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7547 new_token
.code
= '%';
7549 else if (strcasecmp (new_token
.str
, "AND") == 0)
7550 new_token
.code
= '&';
7552 else if (strcasecmp (new_token
.str
, "OR") == 0)
7553 new_token
.code
= '|';
7555 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7556 new_token
.code
= '^';
7558 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7559 new_token
.code
= T_SHL
;
7561 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7562 new_token
.code
= T_SHR
;
7564 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7565 new_token
.code
= T_BYTE
;
7567 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7568 new_token
.code
= T_WORD
;
7570 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7571 new_token
.code
= T_DWORD
;
7573 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7574 new_token
.code
= T_FWORD
;
7576 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7577 new_token
.code
= T_QWORD
;
7579 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7580 /* XXX remove (gcc still uses it) */
7581 || strcasecmp (new_token
.str
, "XWORD") == 0)
7582 new_token
.code
= T_TBYTE
;
7584 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7585 || strcasecmp (new_token
.str
, "OWORD") == 0)
7586 new_token
.code
= T_XMMWORD
;
7588 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7589 new_token
.code
= T_PTR
;
7591 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7592 new_token
.code
= T_SHORT
;
7594 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7596 new_token
.code
= T_OFFSET
;
7598 /* ??? This is not mentioned in the MASM grammar but gcc
7599 makes use of it with -mintel-syntax. OFFSET may be
7600 followed by FLAT: */
7601 if (strncasecmp (q
, " FLAT:", 6) == 0)
7602 strcat (new_token
.str
, " FLAT:");
7605 /* ??? This is not mentioned in the MASM grammar. */
7606 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7608 new_token
.code
= T_OFFSET
;
7610 strcat (new_token
.str
, ":");
7612 as_bad (_("`:' expected"));
7616 new_token
.code
= T_ID
;
7620 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7622 new_token
.code
= *intel_parser
.op_string
;
7623 new_token
.str
[0] = *intel_parser
.op_string
;
7624 new_token
.str
[1] = '\0';
7627 else if (strchr ("<>", *intel_parser
.op_string
)
7628 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7630 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7631 new_token
.str
[0] = *intel_parser
.op_string
;
7632 new_token
.str
[1] = *intel_parser
.op_string
;
7633 new_token
.str
[2] = '\0';
7637 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7639 intel_parser
.op_string
+= strlen (new_token
.str
);
7640 cur_token
= new_token
;
7643 /* Put cur_token back into the token stream and make cur_token point to
7646 intel_putback_token (void)
7648 if (cur_token
.code
!= T_NIL
)
7650 intel_parser
.op_string
-= strlen (cur_token
.str
);
7651 free (cur_token
.str
);
7653 cur_token
= prev_token
;
7655 /* Forget prev_token. */
7656 prev_token
.code
= T_NIL
;
7657 prev_token
.reg
= NULL
;
7658 prev_token
.str
= NULL
;
7662 tc_x86_regname_to_dw2regnum (char *regname
)
7664 unsigned int regnum
;
7665 unsigned int regnames_count
;
7666 static const char *const regnames_32
[] =
7668 "eax", "ecx", "edx", "ebx",
7669 "esp", "ebp", "esi", "edi",
7670 "eip", "eflags", NULL
,
7671 "st0", "st1", "st2", "st3",
7672 "st4", "st5", "st6", "st7",
7674 "xmm0", "xmm1", "xmm2", "xmm3",
7675 "xmm4", "xmm5", "xmm6", "xmm7",
7676 "mm0", "mm1", "mm2", "mm3",
7677 "mm4", "mm5", "mm6", "mm7",
7678 "fcw", "fsw", "mxcsr",
7679 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7682 static const char *const regnames_64
[] =
7684 "rax", "rdx", "rcx", "rbx",
7685 "rsi", "rdi", "rbp", "rsp",
7686 "r8", "r9", "r10", "r11",
7687 "r12", "r13", "r14", "r15",
7689 "xmm0", "xmm1", "xmm2", "xmm3",
7690 "xmm4", "xmm5", "xmm6", "xmm7",
7691 "xmm8", "xmm9", "xmm10", "xmm11",
7692 "xmm12", "xmm13", "xmm14", "xmm15",
7693 "st0", "st1", "st2", "st3",
7694 "st4", "st5", "st6", "st7",
7695 "mm0", "mm1", "mm2", "mm3",
7696 "mm4", "mm5", "mm6", "mm7",
7698 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7699 "fs.base", "gs.base", NULL
, NULL
,
7701 "mxcsr", "fcw", "fsw"
7703 const char *const *regnames
;
7705 if (flag_code
== CODE_64BIT
)
7707 regnames
= regnames_64
;
7708 regnames_count
= ARRAY_SIZE (regnames_64
);
7712 regnames
= regnames_32
;
7713 regnames_count
= ARRAY_SIZE (regnames_32
);
7716 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7717 if (regnames
[regnum
] != NULL
7718 && strcmp (regname
, regnames
[regnum
]) == 0)
7725 tc_x86_frame_initial_instructions (void)
7727 static unsigned int sp_regno
;
7730 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7733 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7734 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7738 i386_elf_section_type (const char *str
, size_t len
)
7740 if (flag_code
== CODE_64BIT
7741 && len
== sizeof ("unwind") - 1
7742 && strncmp (str
, "unwind", 6) == 0)
7743 return SHT_X86_64_UNWIND
;
7750 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7754 expr
.X_op
= O_secrel
;
7755 expr
.X_add_symbol
= symbol
;
7756 expr
.X_add_number
= 0;
7757 emit_expr (&expr
, size
);
7761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7762 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7765 x86_64_section_letter (int letter
, char **ptr_msg
)
7767 if (flag_code
== CODE_64BIT
)
7770 return SHF_X86_64_LARGE
;
7772 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7775 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7780 x86_64_section_word (char *str
, size_t len
)
7782 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7783 return SHF_X86_64_LARGE
;
7789 handle_large_common (int small ATTRIBUTE_UNUSED
)
7791 if (flag_code
!= CODE_64BIT
)
7793 s_comm_internal (0, elf_common_parse
);
7794 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7798 static segT lbss_section
;
7799 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7800 asection
*saved_bss_section
= bss_section
;
7802 if (lbss_section
== NULL
)
7804 flagword applicable
;
7806 subsegT subseg
= now_subseg
;
7808 /* The .lbss section is for local .largecomm symbols. */
7809 lbss_section
= subseg_new (".lbss", 0);
7810 applicable
= bfd_applicable_section_flags (stdoutput
);
7811 bfd_set_section_flags (stdoutput
, lbss_section
,
7812 applicable
& SEC_ALLOC
);
7813 seg_info (lbss_section
)->bss
= 1;
7815 subseg_set (seg
, subseg
);
7818 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7819 bss_section
= lbss_section
;
7821 s_comm_internal (0, elf_common_parse
);
7823 elf_com_section_ptr
= saved_com_section_ptr
;
7824 bss_section
= saved_bss_section
;
7827 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */