1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 /* 1 for intel syntax,
529 static int intel_syntax
= 0;
531 /* 1 for intel mnemonic,
532 0 if att mnemonic. */
533 static int intel_mnemonic
= !SYSV386_COMPAT
;
535 /* 1 if support old (<= 2.8.1) versions of gcc. */
536 static int old_gcc
= OLDGCC_COMPAT
;
538 /* 1 if pseudo registers are permitted. */
539 static int allow_pseudo_reg
= 0;
541 /* 1 if register prefix % not required. */
542 static int allow_naked_reg
= 0;
544 /* 1 if the assembler should add BND prefix for all control-tranferring
545 instructions supporting it, even if this prefix wasn't specified
547 static int add_bnd_prefix
= 0;
549 /* 1 if pseudo index register, eiz/riz, is allowed . */
550 static int allow_index_reg
= 0;
552 /* 1 if the assembler should ignore LOCK prefix, even if it was
553 specified explicitly. */
554 static int omit_lock_prefix
= 0;
556 static enum check_kind
562 sse_check
, operand_check
= check_warning
;
564 /* Register prefix used for error message. */
565 static const char *register_prefix
= "%";
567 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
568 leave, push, and pop instructions so that gcc has the same stack
569 frame as in 32 bit mode. */
570 static char stackop_size
= '\0';
572 /* Non-zero to optimize code alignment. */
573 int optimize_align_code
= 1;
575 /* Non-zero to quieten some warnings. */
576 static int quiet_warnings
= 0;
579 static const char *cpu_arch_name
= NULL
;
580 static char *cpu_sub_arch_name
= NULL
;
582 /* CPU feature flags. */
583 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
585 /* If we have selected a cpu we are generating instructions for. */
586 static int cpu_arch_tune_set
= 0;
588 /* Cpu we are generating instructions for. */
589 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of cpu we are generating instructions for. */
592 static i386_cpu_flags cpu_arch_tune_flags
;
594 /* CPU instruction set architecture used. */
595 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
597 /* CPU feature flags of instruction set architecture used. */
598 i386_cpu_flags cpu_arch_isa_flags
;
600 /* If set, conditional jumps are not automatically promoted to handle
601 larger than a byte offset. */
602 static unsigned int no_cond_jump_promotion
= 0;
604 /* Encode SSE instructions with VEX prefix. */
605 static unsigned int sse2avx
;
607 /* Encode scalar AVX instructions with specific vector length. */
614 /* Encode scalar EVEX LIG instructions with specific vector length. */
622 /* Encode EVEX WIG instructions with specific evex.w. */
629 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
630 static enum rc_type evexrcig
= rne
;
632 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
633 static symbolS
*GOT_symbol
;
635 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
636 unsigned int x86_dwarf2_return_column
;
638 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
639 int x86_cie_data_alignment
;
641 /* Interface to relax_segment.
642 There are 3 major relax states for 386 jump insns because the
643 different types of jumps add different sizes to frags when we're
644 figuring out what sort of jump to choose to reach a given label. */
647 #define UNCOND_JUMP 0
649 #define COND_JUMP86 2
654 #define SMALL16 (SMALL | CODE16)
656 #define BIG16 (BIG | CODE16)
660 #define INLINE __inline__
666 #define ENCODE_RELAX_STATE(type, size) \
667 ((relax_substateT) (((type) << 2) | (size)))
668 #define TYPE_FROM_RELAX_STATE(s) \
670 #define DISP_SIZE_FROM_RELAX_STATE(s) \
671 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
673 /* This table is used by relax_frag to promote short jumps to long
674 ones where necessary. SMALL (short) jumps may be promoted to BIG
675 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
676 don't allow a short jump in a 32 bit code segment to be promoted to
677 a 16 bit offset jump because it's slower (requires data size
678 prefix), and doesn't work, unless the destination is in the bottom
679 64k of the code segment (The top 16 bits of eip are zeroed). */
681 const relax_typeS md_relax_table
[] =
684 1) most positive reach of this state,
685 2) most negative reach of this state,
686 3) how many bytes this mode will have in the variable part of the frag
687 4) which index into the table to try if we can't fit into this one. */
689 /* UNCOND_JUMP states. */
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
692 /* dword jmp adds 4 bytes to frag:
693 0 extra opcode bytes, 4 displacement bytes. */
695 /* word jmp adds 2 byte2 to frag:
696 0 extra opcode bytes, 2 displacement bytes. */
699 /* COND_JUMP states. */
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
702 /* dword conditionals adds 5 bytes to frag:
703 1 extra opcode byte, 4 displacement bytes. */
705 /* word conditionals add 3 bytes to frag:
706 1 extra opcode byte, 2 displacement bytes. */
709 /* COND_JUMP86 states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
712 /* dword conditionals adds 5 bytes to frag:
713 1 extra opcode byte, 4 displacement bytes. */
715 /* word conditionals add 4 bytes to frag:
716 1 displacement byte and a 3 byte long branch insn. */
720 static const arch_entry cpu_arch
[] =
722 /* Do not replace the first two entries - i386_target_format()
723 relies on them being there in this order. */
724 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
725 CPU_GENERIC32_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
727 CPU_GENERIC64_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
729 CPU_NONE_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
731 CPU_I186_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
733 CPU_I286_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
735 CPU_I386_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
737 CPU_I486_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
739 CPU_I586_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
741 CPU_I686_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
743 CPU_I586_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
745 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
747 CPU_P2_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
749 CPU_P3_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
751 CPU_P4_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
755 CPU_NOCONA_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
757 CPU_CORE_FLAGS
, 1, 0 },
758 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
759 CPU_CORE_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
761 CPU_CORE2_FLAGS
, 1, 0 },
762 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
763 CPU_CORE2_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
765 CPU_COREI7_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
767 CPU_L1OM_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
769 CPU_K1OM_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
771 CPU_IAMCU_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
773 CPU_K6_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
775 CPU_K6_2_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
777 CPU_ATHLON_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
779 CPU_K8_FLAGS
, 1, 0 },
780 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
781 CPU_K8_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
783 CPU_K8_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
785 CPU_AMDFAM10_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
787 CPU_BDVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
789 CPU_BDVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
791 CPU_BDVER3_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
793 CPU_BDVER4_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
795 CPU_ZNVER1_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
797 CPU_BTVER1_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
799 CPU_BTVER2_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
801 CPU_8087_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
803 CPU_287_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
805 CPU_387_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
807 CPU_ANY87_FLAGS
, 0, 1 },
808 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
809 CPU_MMX_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
811 CPU_3DNOWA_FLAGS
, 0, 1 },
812 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
813 CPU_SSE_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
815 CPU_SSE2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
817 CPU_SSE3_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
819 CPU_SSSE3_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
821 CPU_SSE4_1_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
823 CPU_SSE4_2_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
825 CPU_SSE4_2_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
827 CPU_ANY_SSE_FLAGS
, 0, 1 },
828 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
829 CPU_AVX_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
831 CPU_AVX2_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512F_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512CD_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
837 CPU_AVX512ER_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
839 CPU_AVX512PF_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
841 CPU_AVX512DQ_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512BW_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512VL_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
847 CPU_ANY_AVX_FLAGS
, 0, 1 },
848 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
849 CPU_VMX_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
851 CPU_VMFUNC_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
853 CPU_SMX_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
855 CPU_XSAVE_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
857 CPU_XSAVEOPT_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
859 CPU_XSAVEC_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
861 CPU_XSAVES_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
863 CPU_AES_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
865 CPU_PCLMUL_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
867 CPU_PCLMUL_FLAGS
, 1, 0 },
868 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
869 CPU_FSGSBASE_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
871 CPU_RDRND_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
873 CPU_F16C_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
875 CPU_BMI2_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
877 CPU_FMA_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
879 CPU_FMA4_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
881 CPU_XOP_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
883 CPU_LWP_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
885 CPU_MOVBE_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
887 CPU_CX16_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
889 CPU_EPT_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
891 CPU_LZCNT_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
893 CPU_HLE_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
895 CPU_RTM_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
897 CPU_INVPCID_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
899 CPU_CLFLUSH_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
901 CPU_NOP_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
903 CPU_SYSCALL_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
905 CPU_RDTSCP_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
907 CPU_3DNOW_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
909 CPU_3DNOWA_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
911 CPU_PADLOCK_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
913 CPU_SVME_FLAGS
, 1, 0 },
914 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
915 CPU_SVME_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
917 CPU_SSE4A_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
919 CPU_ABM_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
921 CPU_BMI_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
923 CPU_TBM_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
925 CPU_ADX_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
927 CPU_RDSEED_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
929 CPU_PRFCHW_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
931 CPU_SMAP_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
933 CPU_MPX_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
935 CPU_SHA_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
937 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
939 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
940 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
941 CPU_SE1_FLAGS
, 0, 0 },
942 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
943 CPU_CLWB_FLAGS
, 0, 0 },
944 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
945 CPU_PCOMMIT_FLAGS
, 0, 0 },
946 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
947 CPU_AVX512IFMA_FLAGS
, 0, 0 },
948 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
949 CPU_AVX512VBMI_FLAGS
, 0, 0 },
950 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
951 CPU_CLZERO_FLAGS
, 0, 0 },
955 /* Like s_lcomm_internal in gas/read.c but the alignment string
956 is allowed to be optional. */
959 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
966 && *input_line_pointer
== ',')
968 align
= parse_align (needs_align
- 1);
970 if (align
== (addressT
) -1)
985 bss_alloc (symbolP
, size
, align
);
990 pe_lcomm (int needs_align
)
992 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
996 const pseudo_typeS md_pseudo_table
[] =
998 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
999 {"align", s_align_bytes
, 0},
1001 {"align", s_align_ptwo
, 0},
1003 {"arch", set_cpu_arch
, 0},
1007 {"lcomm", pe_lcomm
, 1},
1009 {"ffloat", float_cons
, 'f'},
1010 {"dfloat", float_cons
, 'd'},
1011 {"tfloat", float_cons
, 'x'},
1013 {"slong", signed_cons
, 4},
1014 {"noopt", s_ignore
, 0},
1015 {"optim", s_ignore
, 0},
1016 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1017 {"code16", set_code_flag
, CODE_16BIT
},
1018 {"code32", set_code_flag
, CODE_32BIT
},
1019 {"code64", set_code_flag
, CODE_64BIT
},
1020 {"intel_syntax", set_intel_syntax
, 1},
1021 {"att_syntax", set_intel_syntax
, 0},
1022 {"intel_mnemonic", set_intel_mnemonic
, 1},
1023 {"att_mnemonic", set_intel_mnemonic
, 0},
1024 {"allow_index_reg", set_allow_index_reg
, 1},
1025 {"disallow_index_reg", set_allow_index_reg
, 0},
1026 {"sse_check", set_check
, 0},
1027 {"operand_check", set_check
, 1},
1028 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1029 {"largecomm", handle_large_common
, 0},
1031 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1032 {"loc", dwarf2_directive_loc
, 0},
1033 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1036 {"secrel32", pe_directive_secrel
, 0},
1041 /* For interface with expression (). */
1042 extern char *input_line_pointer
;
1044 /* Hash table for instruction mnemonic lookup. */
1045 static struct hash_control
*op_hash
;
1047 /* Hash table for register lookup. */
1048 static struct hash_control
*reg_hash
;
1051 i386_align_code (fragS
*fragP
, int count
)
1053 /* Various efficient no-op patterns for aligning code labels.
1054 Note: Don't try to assemble the instructions in the comments.
1055 0L and 0w are not legal. */
1056 static const char f32_1
[] =
1058 static const char f32_2
[] =
1059 {0x66,0x90}; /* xchg %ax,%ax */
1060 static const char f32_3
[] =
1061 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1062 static const char f32_4
[] =
1063 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1064 static const char f32_5
[] =
1066 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1067 static const char f32_6
[] =
1068 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1069 static const char f32_7
[] =
1070 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1071 static const char f32_8
[] =
1073 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1074 static const char f32_9
[] =
1075 {0x89,0xf6, /* movl %esi,%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_10
[] =
1078 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_11
[] =
1081 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1082 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1083 static const char f32_12
[] =
1084 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1085 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1086 static const char f32_13
[] =
1087 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1089 static const char f32_14
[] =
1090 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const char f16_3
[] =
1093 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1094 static const char f16_4
[] =
1095 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1096 static const char f16_5
[] =
1098 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1099 static const char f16_6
[] =
1100 {0x89,0xf6, /* mov %si,%si */
1101 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1102 static const char f16_7
[] =
1103 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1105 static const char f16_8
[] =
1106 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1107 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1108 static const char jump_31
[] =
1109 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1110 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1113 static const char *const f32_patt
[] = {
1114 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1115 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1117 static const char *const f16_patt
[] = {
1118 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1120 /* nopl (%[re]ax) */
1121 static const char alt_3
[] =
1123 /* nopl 0(%[re]ax) */
1124 static const char alt_4
[] =
1125 {0x0f,0x1f,0x40,0x00};
1126 /* nopl 0(%[re]ax,%[re]ax,1) */
1127 static const char alt_5
[] =
1128 {0x0f,0x1f,0x44,0x00,0x00};
1129 /* nopw 0(%[re]ax,%[re]ax,1) */
1130 static const char alt_6
[] =
1131 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1132 /* nopl 0L(%[re]ax) */
1133 static const char alt_7
[] =
1134 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1135 /* nopl 0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_8
[] =
1137 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1138 /* nopw 0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_9
[] =
1140 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_10
[] =
1143 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 static const char *const alt_patt
[] = {
1145 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1149 /* Only align for at least a positive non-zero boundary. */
1150 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1153 /* We need to decide which NOP sequence to use for 32bit and
1154 64bit. When -mtune= is used:
1156 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1157 PROCESSOR_GENERIC32, f32_patt will be used.
1158 2. For the rest, alt_patt will be used.
1160 When -mtune= isn't used, alt_patt will be used if
1161 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1164 When -march= or .arch is used, we can't use anything beyond
1165 cpu_arch_isa_flags. */
1167 if (flag_code
== CODE_16BIT
)
1171 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1173 /* Adjust jump offset. */
1174 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1177 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1178 f16_patt
[count
- 1], count
);
1182 const char *const *patt
= NULL
;
1184 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1186 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1187 switch (cpu_arch_tune
)
1189 case PROCESSOR_UNKNOWN
:
1190 /* We use cpu_arch_isa_flags to check if we SHOULD
1191 optimize with nops. */
1192 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1197 case PROCESSOR_PENTIUM4
:
1198 case PROCESSOR_NOCONA
:
1199 case PROCESSOR_CORE
:
1200 case PROCESSOR_CORE2
:
1201 case PROCESSOR_COREI7
:
1202 case PROCESSOR_L1OM
:
1203 case PROCESSOR_K1OM
:
1204 case PROCESSOR_GENERIC64
:
1206 case PROCESSOR_ATHLON
:
1208 case PROCESSOR_AMDFAM10
:
1210 case PROCESSOR_ZNVER
:
1214 case PROCESSOR_I386
:
1215 case PROCESSOR_I486
:
1216 case PROCESSOR_PENTIUM
:
1217 case PROCESSOR_PENTIUMPRO
:
1218 case PROCESSOR_IAMCU
:
1219 case PROCESSOR_GENERIC32
:
1226 switch (fragP
->tc_frag_data
.tune
)
1228 case PROCESSOR_UNKNOWN
:
1229 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1230 PROCESSOR_UNKNOWN. */
1234 case PROCESSOR_I386
:
1235 case PROCESSOR_I486
:
1236 case PROCESSOR_PENTIUM
:
1237 case PROCESSOR_IAMCU
:
1239 case PROCESSOR_ATHLON
:
1241 case PROCESSOR_AMDFAM10
:
1243 case PROCESSOR_ZNVER
:
1245 case PROCESSOR_GENERIC32
:
1246 /* We use cpu_arch_isa_flags to check if we CAN optimize
1248 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1253 case PROCESSOR_PENTIUMPRO
:
1254 case PROCESSOR_PENTIUM4
:
1255 case PROCESSOR_NOCONA
:
1256 case PROCESSOR_CORE
:
1257 case PROCESSOR_CORE2
:
1258 case PROCESSOR_COREI7
:
1259 case PROCESSOR_L1OM
:
1260 case PROCESSOR_K1OM
:
1261 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1266 case PROCESSOR_GENERIC64
:
1272 if (patt
== f32_patt
)
1274 /* If the padding is less than 15 bytes, we use the normal
1275 ones. Otherwise, we use a jump instruction and adjust
1279 /* For 64bit, the limit is 3 bytes. */
1280 if (flag_code
== CODE_64BIT
1281 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1286 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1287 patt
[count
- 1], count
);
1290 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1292 /* Adjust jump offset. */
1293 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1298 /* Maximum length of an instruction is 10 byte. If the
1299 padding is greater than 10 bytes and we don't use jump,
1300 we have to break it into smaller pieces. */
1301 int padding
= count
;
1302 while (padding
> 10)
1305 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1310 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1311 patt
[padding
- 1], padding
);
1314 fragP
->fr_var
= count
;
1318 operand_type_all_zero (const union i386_operand_type
*x
)
1320 switch (ARRAY_SIZE(x
->array
))
1329 return !x
->array
[0];
1336 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1338 switch (ARRAY_SIZE(x
->array
))
1353 operand_type_equal (const union i386_operand_type
*x
,
1354 const union i386_operand_type
*y
)
1356 switch (ARRAY_SIZE(x
->array
))
1359 if (x
->array
[2] != y
->array
[2])
1362 if (x
->array
[1] != y
->array
[1])
1365 return x
->array
[0] == y
->array
[0];
1373 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1375 switch (ARRAY_SIZE(x
->array
))
1384 return !x
->array
[0];
1391 cpu_flags_equal (const union i386_cpu_flags
*x
,
1392 const union i386_cpu_flags
*y
)
1394 switch (ARRAY_SIZE(x
->array
))
1397 if (x
->array
[2] != y
->array
[2])
1400 if (x
->array
[1] != y
->array
[1])
1403 return x
->array
[0] == y
->array
[0];
1411 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1413 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1414 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1417 static INLINE i386_cpu_flags
1418 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1420 switch (ARRAY_SIZE (x
.array
))
1423 x
.array
[2] &= y
.array
[2];
1425 x
.array
[1] &= y
.array
[1];
1427 x
.array
[0] &= y
.array
[0];
1435 static INLINE i386_cpu_flags
1436 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1438 switch (ARRAY_SIZE (x
.array
))
1441 x
.array
[2] |= y
.array
[2];
1443 x
.array
[1] |= y
.array
[1];
1445 x
.array
[0] |= y
.array
[0];
1453 static INLINE i386_cpu_flags
1454 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1456 switch (ARRAY_SIZE (x
.array
))
1459 x
.array
[2] &= ~y
.array
[2];
1461 x
.array
[1] &= ~y
.array
[1];
1463 x
.array
[0] &= ~y
.array
[0];
1472 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1474 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1476 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1477 i386_cpu_flags compat_flags
;
1478 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1479 return cpu_flags_all_zero (&compat_flags
);
1485 #define CPU_FLAGS_ARCH_MATCH 0x1
1486 #define CPU_FLAGS_64BIT_MATCH 0x2
1487 #define CPU_FLAGS_AES_MATCH 0x4
1488 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1489 #define CPU_FLAGS_AVX_MATCH 0x10
1491 #define CPU_FLAGS_32BIT_MATCH \
1492 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1493 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1494 #define CPU_FLAGS_PERFECT_MATCH \
1495 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1497 /* Return CPU flags match bits. */
1500 cpu_flags_match (const insn_template
*t
)
1502 i386_cpu_flags x
= t
->cpu_flags
;
1503 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1505 x
.bitfield
.cpu64
= 0;
1506 x
.bitfield
.cpuno64
= 0;
1508 if (cpu_flags_all_zero (&x
))
1510 /* This instruction is available on all archs. */
1511 match
|= CPU_FLAGS_32BIT_MATCH
;
1515 /* This instruction is available only on some archs. */
1516 i386_cpu_flags cpu
= cpu_arch_flags
;
1518 cpu
.bitfield
.cpu64
= 0;
1519 cpu
.bitfield
.cpuno64
= 0;
1520 cpu
= cpu_flags_and (x
, cpu
);
1521 if (!cpu_flags_all_zero (&cpu
))
1523 if (x
.bitfield
.cpuavx
)
1525 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1526 if (cpu
.bitfield
.cpuavx
)
1528 /* Check SSE2AVX. */
1529 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1531 match
|= (CPU_FLAGS_ARCH_MATCH
1532 | CPU_FLAGS_AVX_MATCH
);
1534 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1535 match
|= CPU_FLAGS_AES_MATCH
;
1537 if (!x
.bitfield
.cpupclmul
1538 || cpu
.bitfield
.cpupclmul
)
1539 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1543 match
|= CPU_FLAGS_ARCH_MATCH
;
1546 match
|= CPU_FLAGS_32BIT_MATCH
;
1552 static INLINE i386_operand_type
1553 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1555 switch (ARRAY_SIZE (x
.array
))
1558 x
.array
[2] &= y
.array
[2];
1560 x
.array
[1] &= y
.array
[1];
1562 x
.array
[0] &= y
.array
[0];
1570 static INLINE i386_operand_type
1571 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1573 switch (ARRAY_SIZE (x
.array
))
1576 x
.array
[2] |= y
.array
[2];
1578 x
.array
[1] |= y
.array
[1];
1580 x
.array
[0] |= y
.array
[0];
1588 static INLINE i386_operand_type
1589 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1591 switch (ARRAY_SIZE (x
.array
))
1594 x
.array
[2] ^= y
.array
[2];
1596 x
.array
[1] ^= y
.array
[1];
1598 x
.array
[0] ^= y
.array
[0];
1606 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1607 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1608 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1609 static const i386_operand_type inoutportreg
1610 = OPERAND_TYPE_INOUTPORTREG
;
1611 static const i386_operand_type reg16_inoutportreg
1612 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1613 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1614 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1615 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1616 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1617 static const i386_operand_type anydisp
1618 = OPERAND_TYPE_ANYDISP
;
1619 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1620 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1621 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1622 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1623 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1624 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1625 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1626 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1627 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1628 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1629 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1630 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1631 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1632 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1643 operand_type_check (i386_operand_type t
, enum operand_type c
)
1648 return (t
.bitfield
.reg8
1651 || t
.bitfield
.reg64
);
1654 return (t
.bitfield
.imm8
1658 || t
.bitfield
.imm32s
1659 || t
.bitfield
.imm64
);
1662 return (t
.bitfield
.disp8
1663 || t
.bitfield
.disp16
1664 || t
.bitfield
.disp32
1665 || t
.bitfield
.disp32s
1666 || t
.bitfield
.disp64
);
1669 return (t
.bitfield
.disp8
1670 || t
.bitfield
.disp16
1671 || t
.bitfield
.disp32
1672 || t
.bitfield
.disp32s
1673 || t
.bitfield
.disp64
1674 || t
.bitfield
.baseindex
);
1683 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1684 operand J for instruction template T. */
1687 match_reg_size (const insn_template
*t
, unsigned int j
)
1689 return !((i
.types
[j
].bitfield
.byte
1690 && !t
->operand_types
[j
].bitfield
.byte
)
1691 || (i
.types
[j
].bitfield
.word
1692 && !t
->operand_types
[j
].bitfield
.word
)
1693 || (i
.types
[j
].bitfield
.dword
1694 && !t
->operand_types
[j
].bitfield
.dword
)
1695 || (i
.types
[j
].bitfield
.qword
1696 && !t
->operand_types
[j
].bitfield
.qword
));
1699 /* Return 1 if there is no conflict in any size on operand J for
1700 instruction template T. */
1703 match_mem_size (const insn_template
*t
, unsigned int j
)
1705 return (match_reg_size (t
, j
)
1706 && !((i
.types
[j
].bitfield
.unspecified
1708 && !t
->operand_types
[j
].bitfield
.unspecified
)
1709 || (i
.types
[j
].bitfield
.fword
1710 && !t
->operand_types
[j
].bitfield
.fword
)
1711 || (i
.types
[j
].bitfield
.tbyte
1712 && !t
->operand_types
[j
].bitfield
.tbyte
)
1713 || (i
.types
[j
].bitfield
.xmmword
1714 && !t
->operand_types
[j
].bitfield
.xmmword
)
1715 || (i
.types
[j
].bitfield
.ymmword
1716 && !t
->operand_types
[j
].bitfield
.ymmword
)
1717 || (i
.types
[j
].bitfield
.zmmword
1718 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1721 /* Return 1 if there is no size conflict on any operands for
1722 instruction template T. */
1725 operand_size_match (const insn_template
*t
)
1730 /* Don't check jump instructions. */
1731 if (t
->opcode_modifier
.jump
1732 || t
->opcode_modifier
.jumpbyte
1733 || t
->opcode_modifier
.jumpdword
1734 || t
->opcode_modifier
.jumpintersegment
)
1737 /* Check memory and accumulator operand size. */
1738 for (j
= 0; j
< i
.operands
; j
++)
1740 if (t
->operand_types
[j
].bitfield
.anysize
)
1743 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1749 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1758 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1761 i
.error
= operand_size_mismatch
;
1765 /* Check reverse. */
1766 gas_assert (i
.operands
== 2);
1769 for (j
= 0; j
< 2; j
++)
1771 if (t
->operand_types
[j
].bitfield
.acc
1772 && !match_reg_size (t
, j
? 0 : 1))
1775 if (i
.types
[j
].bitfield
.mem
1776 && !match_mem_size (t
, j
? 0 : 1))
1784 operand_type_match (i386_operand_type overlap
,
1785 i386_operand_type given
)
1787 i386_operand_type temp
= overlap
;
1789 temp
.bitfield
.jumpabsolute
= 0;
1790 temp
.bitfield
.unspecified
= 0;
1791 temp
.bitfield
.byte
= 0;
1792 temp
.bitfield
.word
= 0;
1793 temp
.bitfield
.dword
= 0;
1794 temp
.bitfield
.fword
= 0;
1795 temp
.bitfield
.qword
= 0;
1796 temp
.bitfield
.tbyte
= 0;
1797 temp
.bitfield
.xmmword
= 0;
1798 temp
.bitfield
.ymmword
= 0;
1799 temp
.bitfield
.zmmword
= 0;
1800 if (operand_type_all_zero (&temp
))
1803 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1804 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1808 i
.error
= operand_type_mismatch
;
1812 /* If given types g0 and g1 are registers they must be of the same type
1813 unless the expected operand type register overlap is null.
1814 Note that Acc in a template matches every size of reg. */
1817 operand_type_register_match (i386_operand_type m0
,
1818 i386_operand_type g0
,
1819 i386_operand_type t0
,
1820 i386_operand_type m1
,
1821 i386_operand_type g1
,
1822 i386_operand_type t1
)
1824 if (!operand_type_check (g0
, reg
))
1827 if (!operand_type_check (g1
, reg
))
1830 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1831 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1832 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1833 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1836 if (m0
.bitfield
.acc
)
1838 t0
.bitfield
.reg8
= 1;
1839 t0
.bitfield
.reg16
= 1;
1840 t0
.bitfield
.reg32
= 1;
1841 t0
.bitfield
.reg64
= 1;
1844 if (m1
.bitfield
.acc
)
1846 t1
.bitfield
.reg8
= 1;
1847 t1
.bitfield
.reg16
= 1;
1848 t1
.bitfield
.reg32
= 1;
1849 t1
.bitfield
.reg64
= 1;
1852 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1853 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1854 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1855 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1858 i
.error
= register_type_mismatch
;
1863 static INLINE
unsigned int
1864 register_number (const reg_entry
*r
)
1866 unsigned int nr
= r
->reg_num
;
1868 if (r
->reg_flags
& RegRex
)
1874 static INLINE
unsigned int
1875 mode_from_disp_size (i386_operand_type t
)
1877 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1879 else if (t
.bitfield
.disp16
1880 || t
.bitfield
.disp32
1881 || t
.bitfield
.disp32s
)
1888 fits_in_signed_byte (addressT num
)
1890 return num
+ 0x80 <= 0xff;
1894 fits_in_unsigned_byte (addressT num
)
1900 fits_in_unsigned_word (addressT num
)
1902 return num
<= 0xffff;
1906 fits_in_signed_word (addressT num
)
1908 return num
+ 0x8000 <= 0xffff;
1912 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1917 return num
+ 0x80000000 <= 0xffffffff;
1919 } /* fits_in_signed_long() */
1922 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1927 return num
<= 0xffffffff;
1929 } /* fits_in_unsigned_long() */
1932 fits_in_vec_disp8 (offsetT num
)
1934 int shift
= i
.memshift
;
1940 mask
= (1 << shift
) - 1;
1942 /* Return 0 if NUM isn't properly aligned. */
1946 /* Check if NUM will fit in 8bit after shift. */
1947 return fits_in_signed_byte (num
>> shift
);
1951 fits_in_imm4 (offsetT num
)
1953 return (num
& 0xf) == num
;
1956 static i386_operand_type
1957 smallest_imm_type (offsetT num
)
1959 i386_operand_type t
;
1961 operand_type_set (&t
, 0);
1962 t
.bitfield
.imm64
= 1;
1964 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1966 /* This code is disabled on the 486 because all the Imm1 forms
1967 in the opcode table are slower on the i486. They're the
1968 versions with the implicitly specified single-position
1969 displacement, which has another syntax if you really want to
1971 t
.bitfield
.imm1
= 1;
1972 t
.bitfield
.imm8
= 1;
1973 t
.bitfield
.imm8s
= 1;
1974 t
.bitfield
.imm16
= 1;
1975 t
.bitfield
.imm32
= 1;
1976 t
.bitfield
.imm32s
= 1;
1978 else if (fits_in_signed_byte (num
))
1980 t
.bitfield
.imm8
= 1;
1981 t
.bitfield
.imm8s
= 1;
1982 t
.bitfield
.imm16
= 1;
1983 t
.bitfield
.imm32
= 1;
1984 t
.bitfield
.imm32s
= 1;
1986 else if (fits_in_unsigned_byte (num
))
1988 t
.bitfield
.imm8
= 1;
1989 t
.bitfield
.imm16
= 1;
1990 t
.bitfield
.imm32
= 1;
1991 t
.bitfield
.imm32s
= 1;
1993 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1995 t
.bitfield
.imm16
= 1;
1996 t
.bitfield
.imm32
= 1;
1997 t
.bitfield
.imm32s
= 1;
1999 else if (fits_in_signed_long (num
))
2001 t
.bitfield
.imm32
= 1;
2002 t
.bitfield
.imm32s
= 1;
2004 else if (fits_in_unsigned_long (num
))
2005 t
.bitfield
.imm32
= 1;
2011 offset_in_range (offsetT val
, int size
)
2017 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2018 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2019 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2021 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2027 /* If BFD64, sign extend val for 32bit address mode. */
2028 if (flag_code
!= CODE_64BIT
2029 || i
.prefix
[ADDR_PREFIX
])
2030 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2031 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2034 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2036 char buf1
[40], buf2
[40];
2038 sprint_value (buf1
, val
);
2039 sprint_value (buf2
, val
& mask
);
2040 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2054 a. PREFIX_EXIST if attempting to add a prefix where one from the
2055 same class already exists.
2056 b. PREFIX_LOCK if lock prefix is added.
2057 c. PREFIX_REP if rep/repne prefix is added.
2058 d. PREFIX_OTHER if other prefix is added.
2061 static enum PREFIX_GROUP
2062 add_prefix (unsigned int prefix
)
2064 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2067 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2068 && flag_code
== CODE_64BIT
)
2070 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2071 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2072 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2083 case CS_PREFIX_OPCODE
:
2084 case DS_PREFIX_OPCODE
:
2085 case ES_PREFIX_OPCODE
:
2086 case FS_PREFIX_OPCODE
:
2087 case GS_PREFIX_OPCODE
:
2088 case SS_PREFIX_OPCODE
:
2092 case REPNE_PREFIX_OPCODE
:
2093 case REPE_PREFIX_OPCODE
:
2098 case LOCK_PREFIX_OPCODE
:
2107 case ADDR_PREFIX_OPCODE
:
2111 case DATA_PREFIX_OPCODE
:
2115 if (i
.prefix
[q
] != 0)
2123 i
.prefix
[q
] |= prefix
;
2126 as_bad (_("same type of prefix used twice"));
2132 update_code_flag (int value
, int check
)
2134 PRINTF_LIKE ((*as_error
));
2136 flag_code
= (enum flag_code
) value
;
2137 if (flag_code
== CODE_64BIT
)
2139 cpu_arch_flags
.bitfield
.cpu64
= 1;
2140 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2144 cpu_arch_flags
.bitfield
.cpu64
= 0;
2145 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2147 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2150 as_error
= as_fatal
;
2153 (*as_error
) (_("64bit mode not supported on `%s'."),
2154 cpu_arch_name
? cpu_arch_name
: default_arch
);
2156 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2159 as_error
= as_fatal
;
2162 (*as_error
) (_("32bit mode not supported on `%s'."),
2163 cpu_arch_name
? cpu_arch_name
: default_arch
);
2165 stackop_size
= '\0';
2169 set_code_flag (int value
)
2171 update_code_flag (value
, 0);
2175 set_16bit_gcc_code_flag (int new_code_flag
)
2177 flag_code
= (enum flag_code
) new_code_flag
;
2178 if (flag_code
!= CODE_16BIT
)
2180 cpu_arch_flags
.bitfield
.cpu64
= 0;
2181 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2182 stackop_size
= LONG_MNEM_SUFFIX
;
2186 set_intel_syntax (int syntax_flag
)
2188 /* Find out if register prefixing is specified. */
2189 int ask_naked_reg
= 0;
2192 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2194 char *string
= input_line_pointer
;
2195 int e
= get_symbol_end ();
2197 if (strcmp (string
, "prefix") == 0)
2199 else if (strcmp (string
, "noprefix") == 0)
2202 as_bad (_("bad argument to syntax directive."));
2203 *input_line_pointer
= e
;
2205 demand_empty_rest_of_line ();
2207 intel_syntax
= syntax_flag
;
2209 if (ask_naked_reg
== 0)
2210 allow_naked_reg
= (intel_syntax
2211 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2213 allow_naked_reg
= (ask_naked_reg
< 0);
2215 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2217 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2218 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2219 register_prefix
= allow_naked_reg
? "" : "%";
2223 set_intel_mnemonic (int mnemonic_flag
)
2225 intel_mnemonic
= mnemonic_flag
;
2229 set_allow_index_reg (int flag
)
2231 allow_index_reg
= flag
;
2235 set_check (int what
)
2237 enum check_kind
*kind
;
2242 kind
= &operand_check
;
2253 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2255 char *string
= input_line_pointer
;
2256 int e
= get_symbol_end ();
2258 if (strcmp (string
, "none") == 0)
2260 else if (strcmp (string
, "warning") == 0)
2261 *kind
= check_warning
;
2262 else if (strcmp (string
, "error") == 0)
2263 *kind
= check_error
;
2265 as_bad (_("bad argument to %s_check directive."), str
);
2266 *input_line_pointer
= e
;
2269 as_bad (_("missing argument for %s_check directive"), str
);
2271 demand_empty_rest_of_line ();
2275 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2276 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2278 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2279 static const char *arch
;
2281 /* Intel LIOM is only supported on ELF. */
2287 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2288 use default_arch. */
2289 arch
= cpu_arch_name
;
2291 arch
= default_arch
;
2294 /* If we are targeting Intel MCU, we must enable it. */
2295 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2296 || new_flag
.bitfield
.cpuiamcu
)
2299 /* If we are targeting Intel L1OM, we must enable it. */
2300 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2301 || new_flag
.bitfield
.cpul1om
)
2304 /* If we are targeting Intel K1OM, we must enable it. */
2305 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2306 || new_flag
.bitfield
.cpuk1om
)
2309 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2314 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2318 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2320 char *string
= input_line_pointer
;
2321 int e
= get_symbol_end ();
2323 i386_cpu_flags flags
;
2325 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2327 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2329 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2333 cpu_arch_name
= cpu_arch
[j
].name
;
2334 cpu_sub_arch_name
= NULL
;
2335 cpu_arch_flags
= cpu_arch
[j
].flags
;
2336 if (flag_code
== CODE_64BIT
)
2338 cpu_arch_flags
.bitfield
.cpu64
= 1;
2339 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2343 cpu_arch_flags
.bitfield
.cpu64
= 0;
2344 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2346 cpu_arch_isa
= cpu_arch
[j
].type
;
2347 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2348 if (!cpu_arch_tune_set
)
2350 cpu_arch_tune
= cpu_arch_isa
;
2351 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2356 if (!cpu_arch
[j
].negated
)
2357 flags
= cpu_flags_or (cpu_arch_flags
,
2360 flags
= cpu_flags_and_not (cpu_arch_flags
,
2363 if (!valid_iamcu_cpu_flags (&flags
))
2364 as_fatal (_("`%s' isn't valid for Intel MCU"),
2366 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2368 if (cpu_sub_arch_name
)
2370 char *name
= cpu_sub_arch_name
;
2371 cpu_sub_arch_name
= concat (name
,
2373 (const char *) NULL
);
2377 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2378 cpu_arch_flags
= flags
;
2379 cpu_arch_isa_flags
= flags
;
2381 *input_line_pointer
= e
;
2382 demand_empty_rest_of_line ();
2386 if (j
>= ARRAY_SIZE (cpu_arch
))
2387 as_bad (_("no such architecture: `%s'"), string
);
2389 *input_line_pointer
= e
;
2392 as_bad (_("missing cpu architecture"));
2394 no_cond_jump_promotion
= 0;
2395 if (*input_line_pointer
== ','
2396 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2398 char *string
= ++input_line_pointer
;
2399 int e
= get_symbol_end ();
2401 if (strcmp (string
, "nojumps") == 0)
2402 no_cond_jump_promotion
= 1;
2403 else if (strcmp (string
, "jumps") == 0)
2406 as_bad (_("no such architecture modifier: `%s'"), string
);
2408 *input_line_pointer
= e
;
2411 demand_empty_rest_of_line ();
2414 enum bfd_architecture
2417 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2419 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2420 || flag_code
!= CODE_64BIT
)
2421 as_fatal (_("Intel L1OM is 64bit ELF only"));
2422 return bfd_arch_l1om
;
2424 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2426 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2427 || flag_code
!= CODE_64BIT
)
2428 as_fatal (_("Intel K1OM is 64bit ELF only"));
2429 return bfd_arch_k1om
;
2431 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2433 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2434 || flag_code
== CODE_64BIT
)
2435 as_fatal (_("Intel MCU is 32bit ELF only"));
2436 return bfd_arch_iamcu
;
2439 return bfd_arch_i386
;
2445 if (!strncmp (default_arch
, "x86_64", 6))
2447 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2449 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2450 || default_arch
[6] != '\0')
2451 as_fatal (_("Intel L1OM is 64bit ELF only"));
2452 return bfd_mach_l1om
;
2454 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2456 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2457 || default_arch
[6] != '\0')
2458 as_fatal (_("Intel K1OM is 64bit ELF only"));
2459 return bfd_mach_k1om
;
2461 else if (default_arch
[6] == '\0')
2462 return bfd_mach_x86_64
;
2464 return bfd_mach_x64_32
;
2466 else if (!strcmp (default_arch
, "i386")
2467 || !strcmp (default_arch
, "iamcu"))
2469 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2471 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2472 as_fatal (_("Intel MCU is 32bit ELF only"));
2473 return bfd_mach_i386_iamcu
;
2476 return bfd_mach_i386_i386
;
2479 as_fatal (_("unknown architecture"));
2485 const char *hash_err
;
2487 /* Initialize op_hash hash table. */
2488 op_hash
= hash_new ();
2491 const insn_template
*optab
;
2492 templates
*core_optab
;
2494 /* Setup for loop. */
2496 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2497 core_optab
->start
= optab
;
2502 if (optab
->name
== NULL
2503 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2505 /* different name --> ship out current template list;
2506 add to hash table; & begin anew. */
2507 core_optab
->end
= optab
;
2508 hash_err
= hash_insert (op_hash
,
2510 (void *) core_optab
);
2513 as_fatal (_("can't hash %s: %s"),
2517 if (optab
->name
== NULL
)
2519 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2520 core_optab
->start
= optab
;
2525 /* Initialize reg_hash hash table. */
2526 reg_hash
= hash_new ();
2528 const reg_entry
*regtab
;
2529 unsigned int regtab_size
= i386_regtab_size
;
2531 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2533 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2535 as_fatal (_("can't hash %s: %s"),
2541 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2546 for (c
= 0; c
< 256; c
++)
2551 mnemonic_chars
[c
] = c
;
2552 register_chars
[c
] = c
;
2553 operand_chars
[c
] = c
;
2555 else if (ISLOWER (c
))
2557 mnemonic_chars
[c
] = c
;
2558 register_chars
[c
] = c
;
2559 operand_chars
[c
] = c
;
2561 else if (ISUPPER (c
))
2563 mnemonic_chars
[c
] = TOLOWER (c
);
2564 register_chars
[c
] = mnemonic_chars
[c
];
2565 operand_chars
[c
] = c
;
2567 else if (c
== '{' || c
== '}')
2568 operand_chars
[c
] = c
;
2570 if (ISALPHA (c
) || ISDIGIT (c
))
2571 identifier_chars
[c
] = c
;
2574 identifier_chars
[c
] = c
;
2575 operand_chars
[c
] = c
;
2580 identifier_chars
['@'] = '@';
2583 identifier_chars
['?'] = '?';
2584 operand_chars
['?'] = '?';
2586 digit_chars
['-'] = '-';
2587 mnemonic_chars
['_'] = '_';
2588 mnemonic_chars
['-'] = '-';
2589 mnemonic_chars
['.'] = '.';
2590 identifier_chars
['_'] = '_';
2591 identifier_chars
['.'] = '.';
2593 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2594 operand_chars
[(unsigned char) *p
] = *p
;
2597 if (flag_code
== CODE_64BIT
)
2599 #if defined (OBJ_COFF) && defined (TE_PE)
2600 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2603 x86_dwarf2_return_column
= 16;
2605 x86_cie_data_alignment
= -8;
2609 x86_dwarf2_return_column
= 8;
2610 x86_cie_data_alignment
= -4;
2615 i386_print_statistics (FILE *file
)
2617 hash_print_statistics (file
, "i386 opcode", op_hash
);
2618 hash_print_statistics (file
, "i386 register", reg_hash
);
2623 /* Debugging routines for md_assemble. */
2624 static void pte (insn_template
*);
2625 static void pt (i386_operand_type
);
2626 static void pe (expressionS
*);
2627 static void ps (symbolS
*);
2630 pi (char *line
, i386_insn
*x
)
2634 fprintf (stdout
, "%s: template ", line
);
2636 fprintf (stdout
, " address: base %s index %s scale %x\n",
2637 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2638 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2639 x
->log2_scale_factor
);
2640 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2641 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2642 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2643 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2644 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2645 (x
->rex
& REX_W
) != 0,
2646 (x
->rex
& REX_R
) != 0,
2647 (x
->rex
& REX_X
) != 0,
2648 (x
->rex
& REX_B
) != 0);
2649 for (j
= 0; j
< x
->operands
; j
++)
2651 fprintf (stdout
, " #%d: ", j
+ 1);
2653 fprintf (stdout
, "\n");
2654 if (x
->types
[j
].bitfield
.reg8
2655 || x
->types
[j
].bitfield
.reg16
2656 || x
->types
[j
].bitfield
.reg32
2657 || x
->types
[j
].bitfield
.reg64
2658 || x
->types
[j
].bitfield
.regmmx
2659 || x
->types
[j
].bitfield
.regxmm
2660 || x
->types
[j
].bitfield
.regymm
2661 || x
->types
[j
].bitfield
.regzmm
2662 || x
->types
[j
].bitfield
.sreg2
2663 || x
->types
[j
].bitfield
.sreg3
2664 || x
->types
[j
].bitfield
.control
2665 || x
->types
[j
].bitfield
.debug
2666 || x
->types
[j
].bitfield
.test
)
2667 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2668 if (operand_type_check (x
->types
[j
], imm
))
2670 if (operand_type_check (x
->types
[j
], disp
))
2671 pe (x
->op
[j
].disps
);
2676 pte (insn_template
*t
)
2679 fprintf (stdout
, " %d operands ", t
->operands
);
2680 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2681 if (t
->extension_opcode
!= None
)
2682 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2683 if (t
->opcode_modifier
.d
)
2684 fprintf (stdout
, "D");
2685 if (t
->opcode_modifier
.w
)
2686 fprintf (stdout
, "W");
2687 fprintf (stdout
, "\n");
2688 for (j
= 0; j
< t
->operands
; j
++)
2690 fprintf (stdout
, " #%d type ", j
+ 1);
2691 pt (t
->operand_types
[j
]);
2692 fprintf (stdout
, "\n");
2699 fprintf (stdout
, " operation %d\n", e
->X_op
);
2700 fprintf (stdout
, " add_number %ld (%lx)\n",
2701 (long) e
->X_add_number
, (long) e
->X_add_number
);
2702 if (e
->X_add_symbol
)
2704 fprintf (stdout
, " add_symbol ");
2705 ps (e
->X_add_symbol
);
2706 fprintf (stdout
, "\n");
2710 fprintf (stdout
, " op_symbol ");
2711 ps (e
->X_op_symbol
);
2712 fprintf (stdout
, "\n");
2719 fprintf (stdout
, "%s type %s%s",
2721 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2722 segment_name (S_GET_SEGMENT (s
)));
2725 static struct type_name
2727 i386_operand_type mask
;
2730 const type_names
[] =
2732 { OPERAND_TYPE_REG8
, "r8" },
2733 { OPERAND_TYPE_REG16
, "r16" },
2734 { OPERAND_TYPE_REG32
, "r32" },
2735 { OPERAND_TYPE_REG64
, "r64" },
2736 { OPERAND_TYPE_IMM8
, "i8" },
2737 { OPERAND_TYPE_IMM8
, "i8s" },
2738 { OPERAND_TYPE_IMM16
, "i16" },
2739 { OPERAND_TYPE_IMM32
, "i32" },
2740 { OPERAND_TYPE_IMM32S
, "i32s" },
2741 { OPERAND_TYPE_IMM64
, "i64" },
2742 { OPERAND_TYPE_IMM1
, "i1" },
2743 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2744 { OPERAND_TYPE_DISP8
, "d8" },
2745 { OPERAND_TYPE_DISP16
, "d16" },
2746 { OPERAND_TYPE_DISP32
, "d32" },
2747 { OPERAND_TYPE_DISP32S
, "d32s" },
2748 { OPERAND_TYPE_DISP64
, "d64" },
2749 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2750 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2751 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2752 { OPERAND_TYPE_CONTROL
, "control reg" },
2753 { OPERAND_TYPE_TEST
, "test reg" },
2754 { OPERAND_TYPE_DEBUG
, "debug reg" },
2755 { OPERAND_TYPE_FLOATREG
, "FReg" },
2756 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2757 { OPERAND_TYPE_SREG2
, "SReg2" },
2758 { OPERAND_TYPE_SREG3
, "SReg3" },
2759 { OPERAND_TYPE_ACC
, "Acc" },
2760 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2761 { OPERAND_TYPE_REGMMX
, "rMMX" },
2762 { OPERAND_TYPE_REGXMM
, "rXMM" },
2763 { OPERAND_TYPE_REGYMM
, "rYMM" },
2764 { OPERAND_TYPE_REGZMM
, "rZMM" },
2765 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2766 { OPERAND_TYPE_ESSEG
, "es" },
2770 pt (i386_operand_type t
)
2773 i386_operand_type a
;
2775 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2777 a
= operand_type_and (t
, type_names
[j
].mask
);
2778 if (!operand_type_all_zero (&a
))
2779 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2784 #endif /* DEBUG386 */
2786 static bfd_reloc_code_real_type
2787 reloc (unsigned int size
,
2790 bfd_reloc_code_real_type other
)
2792 if (other
!= NO_RELOC
)
2794 reloc_howto_type
*rel
;
2799 case BFD_RELOC_X86_64_GOT32
:
2800 return BFD_RELOC_X86_64_GOT64
;
2802 case BFD_RELOC_X86_64_GOTPLT64
:
2803 return BFD_RELOC_X86_64_GOTPLT64
;
2805 case BFD_RELOC_X86_64_PLTOFF64
:
2806 return BFD_RELOC_X86_64_PLTOFF64
;
2808 case BFD_RELOC_X86_64_GOTPC32
:
2809 other
= BFD_RELOC_X86_64_GOTPC64
;
2811 case BFD_RELOC_X86_64_GOTPCREL
:
2812 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2814 case BFD_RELOC_X86_64_TPOFF32
:
2815 other
= BFD_RELOC_X86_64_TPOFF64
;
2817 case BFD_RELOC_X86_64_DTPOFF32
:
2818 other
= BFD_RELOC_X86_64_DTPOFF64
;
2824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2825 if (other
== BFD_RELOC_SIZE32
)
2828 other
= BFD_RELOC_SIZE64
;
2831 as_bad (_("there are no pc-relative size relocations"));
2837 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2838 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2841 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2843 as_bad (_("unknown relocation (%u)"), other
);
2844 else if (size
!= bfd_get_reloc_size (rel
))
2845 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2846 bfd_get_reloc_size (rel
),
2848 else if (pcrel
&& !rel
->pc_relative
)
2849 as_bad (_("non-pc-relative relocation for pc-relative field"));
2850 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2852 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2854 as_bad (_("relocated field and relocation type differ in signedness"));
2863 as_bad (_("there are no unsigned pc-relative relocations"));
2866 case 1: return BFD_RELOC_8_PCREL
;
2867 case 2: return BFD_RELOC_16_PCREL
;
2868 case 4: return BFD_RELOC_32_PCREL
;
2869 case 8: return BFD_RELOC_64_PCREL
;
2871 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2878 case 4: return BFD_RELOC_X86_64_32S
;
2883 case 1: return BFD_RELOC_8
;
2884 case 2: return BFD_RELOC_16
;
2885 case 4: return BFD_RELOC_32
;
2886 case 8: return BFD_RELOC_64
;
2888 as_bad (_("cannot do %s %u byte relocation"),
2889 sign
> 0 ? "signed" : "unsigned", size
);
2895 /* Here we decide which fixups can be adjusted to make them relative to
2896 the beginning of the section instead of the symbol. Basically we need
2897 to make sure that the dynamic relocations are done correctly, so in
2898 some cases we force the original symbol to be used. */
2901 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2903 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2907 /* Don't adjust pc-relative references to merge sections in 64-bit
2909 if (use_rela_relocations
2910 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2914 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2915 and changed later by validate_fix. */
2916 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2917 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2920 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2921 for size relocations. */
2922 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2923 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2924 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2925 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2926 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2927 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2928 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2929 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2930 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2931 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2932 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2933 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2937 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2938 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2939 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2940 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2941 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2942 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2943 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2950 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2951 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2958 intel_float_operand (const char *mnemonic
)
2960 /* Note that the value returned is meaningful only for opcodes with (memory)
2961 operands, hence the code here is free to improperly handle opcodes that
2962 have no operands (for better performance and smaller code). */
2964 if (mnemonic
[0] != 'f')
2965 return 0; /* non-math */
2967 switch (mnemonic
[1])
2969 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2970 the fs segment override prefix not currently handled because no
2971 call path can make opcodes without operands get here */
2973 return 2 /* integer op */;
2975 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2976 return 3; /* fldcw/fldenv */
2979 if (mnemonic
[2] != 'o' /* fnop */)
2980 return 3; /* non-waiting control op */
2983 if (mnemonic
[2] == 's')
2984 return 3; /* frstor/frstpm */
2987 if (mnemonic
[2] == 'a')
2988 return 3; /* fsave */
2989 if (mnemonic
[2] == 't')
2991 switch (mnemonic
[3])
2993 case 'c': /* fstcw */
2994 case 'd': /* fstdw */
2995 case 'e': /* fstenv */
2996 case 's': /* fsts[gw] */
3002 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3003 return 0; /* fxsave/fxrstor are not really math ops */
3010 /* Build the VEX prefix. */
3013 build_vex_prefix (const insn_template
*t
)
3015 unsigned int register_specifier
;
3016 unsigned int implied_prefix
;
3017 unsigned int vector_length
;
3019 /* Check register specifier. */
3020 if (i
.vex
.register_specifier
)
3022 register_specifier
=
3023 ~register_number (i
.vex
.register_specifier
) & 0xf;
3024 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3027 register_specifier
= 0xf;
3029 /* Use 2-byte VEX prefix by swappping destination and source
3032 && i
.operands
== i
.reg_operands
3033 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3034 && i
.tm
.opcode_modifier
.s
3037 unsigned int xchg
= i
.operands
- 1;
3038 union i386_op temp_op
;
3039 i386_operand_type temp_type
;
3041 temp_type
= i
.types
[xchg
];
3042 i
.types
[xchg
] = i
.types
[0];
3043 i
.types
[0] = temp_type
;
3044 temp_op
= i
.op
[xchg
];
3045 i
.op
[xchg
] = i
.op
[0];
3048 gas_assert (i
.rm
.mode
== 3);
3052 i
.rm
.regmem
= i
.rm
.reg
;
3055 /* Use the next insn. */
3059 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3060 vector_length
= avxscalar
;
3062 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3064 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3069 case DATA_PREFIX_OPCODE
:
3072 case REPE_PREFIX_OPCODE
:
3075 case REPNE_PREFIX_OPCODE
:
3082 /* Use 2-byte VEX prefix if possible. */
3083 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3084 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3085 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3087 /* 2-byte VEX prefix. */
3091 i
.vex
.bytes
[0] = 0xc5;
3093 /* Check the REX.R bit. */
3094 r
= (i
.rex
& REX_R
) ? 0 : 1;
3095 i
.vex
.bytes
[1] = (r
<< 7
3096 | register_specifier
<< 3
3097 | vector_length
<< 2
3102 /* 3-byte VEX prefix. */
3107 switch (i
.tm
.opcode_modifier
.vexopcode
)
3111 i
.vex
.bytes
[0] = 0xc4;
3115 i
.vex
.bytes
[0] = 0xc4;
3119 i
.vex
.bytes
[0] = 0xc4;
3123 i
.vex
.bytes
[0] = 0x8f;
3127 i
.vex
.bytes
[0] = 0x8f;
3131 i
.vex
.bytes
[0] = 0x8f;
3137 /* The high 3 bits of the second VEX byte are 1's compliment
3138 of RXB bits from REX. */
3139 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3141 /* Check the REX.W bit. */
3142 w
= (i
.rex
& REX_W
) ? 1 : 0;
3143 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3146 i
.vex
.bytes
[2] = (w
<< 7
3147 | register_specifier
<< 3
3148 | vector_length
<< 2
3153 /* Build the EVEX prefix. */
3156 build_evex_prefix (void)
3158 unsigned int register_specifier
;
3159 unsigned int implied_prefix
;
3161 rex_byte vrex_used
= 0;
3163 /* Check register specifier. */
3164 if (i
.vex
.register_specifier
)
3166 gas_assert ((i
.vrex
& REX_X
) == 0);
3168 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3169 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3170 register_specifier
+= 8;
3171 /* The upper 16 registers are encoded in the fourth byte of the
3173 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3174 i
.vex
.bytes
[3] = 0x8;
3175 register_specifier
= ~register_specifier
& 0xf;
3179 register_specifier
= 0xf;
3181 /* Encode upper 16 vector index register in the fourth byte of
3183 if (!(i
.vrex
& REX_X
))
3184 i
.vex
.bytes
[3] = 0x8;
3189 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3194 case DATA_PREFIX_OPCODE
:
3197 case REPE_PREFIX_OPCODE
:
3200 case REPNE_PREFIX_OPCODE
:
3207 /* 4 byte EVEX prefix. */
3209 i
.vex
.bytes
[0] = 0x62;
3212 switch (i
.tm
.opcode_modifier
.vexopcode
)
3228 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3230 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3232 /* The fifth bit of the second EVEX byte is 1's compliment of the
3233 REX_R bit in VREX. */
3234 if (!(i
.vrex
& REX_R
))
3235 i
.vex
.bytes
[1] |= 0x10;
3239 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3241 /* When all operands are registers, the REX_X bit in REX is not
3242 used. We reuse it to encode the upper 16 registers, which is
3243 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3244 as 1's compliment. */
3245 if ((i
.vrex
& REX_B
))
3248 i
.vex
.bytes
[1] &= ~0x40;
3252 /* EVEX instructions shouldn't need the REX prefix. */
3253 i
.vrex
&= ~vrex_used
;
3254 gas_assert (i
.vrex
== 0);
3256 /* Check the REX.W bit. */
3257 w
= (i
.rex
& REX_W
) ? 1 : 0;
3258 if (i
.tm
.opcode_modifier
.vexw
)
3260 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3263 /* If w is not set it means we are dealing with WIG instruction. */
3266 if (evexwig
== evexw1
)
3270 /* Encode the U bit. */
3271 implied_prefix
|= 0x4;
3273 /* The third byte of the EVEX prefix. */
3274 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3276 /* The fourth byte of the EVEX prefix. */
3277 /* The zeroing-masking bit. */
3278 if (i
.mask
&& i
.mask
->zeroing
)
3279 i
.vex
.bytes
[3] |= 0x80;
3281 /* Don't always set the broadcast bit if there is no RC. */
3284 /* Encode the vector length. */
3285 unsigned int vec_length
;
3287 switch (i
.tm
.opcode_modifier
.evex
)
3289 case EVEXLIG
: /* LL' is ignored */
3290 vec_length
= evexlig
<< 5;
3293 vec_length
= 0 << 5;
3296 vec_length
= 1 << 5;
3299 vec_length
= 2 << 5;
3305 i
.vex
.bytes
[3] |= vec_length
;
3306 /* Encode the broadcast bit. */
3308 i
.vex
.bytes
[3] |= 0x10;
3312 if (i
.rounding
->type
!= saeonly
)
3313 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3315 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3318 if (i
.mask
&& i
.mask
->mask
)
3319 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3323 process_immext (void)
3327 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3330 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3331 with an opcode suffix which is coded in the same place as an
3332 8-bit immediate field would be.
3333 Here we check those operands and remove them afterwards. */
3336 for (x
= 0; x
< i
.operands
; x
++)
3337 if (register_number (i
.op
[x
].regs
) != x
)
3338 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3339 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3345 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3346 which is coded in the same place as an 8-bit immediate field
3347 would be. Here we fake an 8-bit immediate operand from the
3348 opcode suffix stored in tm.extension_opcode.
3350 AVX instructions also use this encoding, for some of
3351 3 argument instructions. */
3353 gas_assert (i
.imm_operands
<= 1
3355 || ((i
.tm
.opcode_modifier
.vex
3356 || i
.tm
.opcode_modifier
.evex
)
3357 && i
.operands
<= 4)));
3359 exp
= &im_expressions
[i
.imm_operands
++];
3360 i
.op
[i
.operands
].imms
= exp
;
3361 i
.types
[i
.operands
] = imm8
;
3363 exp
->X_op
= O_constant
;
3364 exp
->X_add_number
= i
.tm
.extension_opcode
;
3365 i
.tm
.extension_opcode
= None
;
3372 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3377 as_bad (_("invalid instruction `%s' after `%s'"),
3378 i
.tm
.name
, i
.hle_prefix
);
3381 if (i
.prefix
[LOCK_PREFIX
])
3383 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3387 case HLEPrefixRelease
:
3388 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3390 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3394 if (i
.mem_operands
== 0
3395 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3397 as_bad (_("memory destination needed for instruction `%s'"
3398 " after `xrelease'"), i
.tm
.name
);
3405 /* This is the guts of the machine-dependent assembler. LINE points to a
3406 machine dependent instruction. This function is supposed to emit
3407 the frags/bytes it assembles to. */
3410 md_assemble (char *line
)
3413 char mnemonic
[MAX_MNEM_SIZE
];
3414 const insn_template
*t
;
3416 /* Initialize globals. */
3417 memset (&i
, '\0', sizeof (i
));
3418 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3419 i
.reloc
[j
] = NO_RELOC
;
3420 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3421 memset (im_expressions
, '\0', sizeof (im_expressions
));
3422 save_stack_p
= save_stack
;
3424 /* First parse an instruction mnemonic & call i386_operand for the operands.
3425 We assume that the scrubber has arranged it so that line[0] is the valid
3426 start of a (possibly prefixed) mnemonic. */
3428 line
= parse_insn (line
, mnemonic
);
3432 line
= parse_operands (line
, mnemonic
);
3437 /* Now we've parsed the mnemonic into a set of templates, and have the
3438 operands at hand. */
3440 /* All intel opcodes have reversed operands except for "bound" and
3441 "enter". We also don't reverse intersegment "jmp" and "call"
3442 instructions with 2 immediate operands so that the immediate segment
3443 precedes the offset, as it does when in AT&T mode. */
3446 && (strcmp (mnemonic
, "bound") != 0)
3447 && (strcmp (mnemonic
, "invlpga") != 0)
3448 && !(operand_type_check (i
.types
[0], imm
)
3449 && operand_type_check (i
.types
[1], imm
)))
3452 /* The order of the immediates should be reversed
3453 for 2 immediates extrq and insertq instructions */
3454 if (i
.imm_operands
== 2
3455 && (strcmp (mnemonic
, "extrq") == 0
3456 || strcmp (mnemonic
, "insertq") == 0))
3457 swap_2_operands (0, 1);
3462 /* Don't optimize displacement for movabs since it only takes 64bit
3465 && i
.disp_encoding
!= disp_encoding_32bit
3466 && (flag_code
!= CODE_64BIT
3467 || strcmp (mnemonic
, "movabs") != 0))
3470 /* Next, we find a template that matches the given insn,
3471 making sure the overlap of the given operands types is consistent
3472 with the template operand types. */
3474 if (!(t
= match_template ()))
3477 if (sse_check
!= check_none
3478 && !i
.tm
.opcode_modifier
.noavx
3479 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3480 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3481 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3482 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3483 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3484 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3486 (sse_check
== check_warning
3488 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3491 /* Zap movzx and movsx suffix. The suffix has been set from
3492 "word ptr" or "byte ptr" on the source operand in Intel syntax
3493 or extracted from mnemonic in AT&T syntax. But we'll use
3494 the destination register to choose the suffix for encoding. */
3495 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3497 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3498 there is no suffix, the default will be byte extension. */
3499 if (i
.reg_operands
!= 2
3502 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3507 if (i
.tm
.opcode_modifier
.fwait
)
3508 if (!add_prefix (FWAIT_OPCODE
))
3511 /* Check if REP prefix is OK. */
3512 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3514 as_bad (_("invalid instruction `%s' after `%s'"),
3515 i
.tm
.name
, i
.rep_prefix
);
3519 /* Check for lock without a lockable instruction. Destination operand
3520 must be memory unless it is xchg (0x86). */
3521 if (i
.prefix
[LOCK_PREFIX
]
3522 && (!i
.tm
.opcode_modifier
.islockable
3523 || i
.mem_operands
== 0
3524 || (i
.tm
.base_opcode
!= 0x86
3525 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3527 as_bad (_("expecting lockable instruction after `lock'"));
3531 /* Check if HLE prefix is OK. */
3532 if (i
.hle_prefix
&& !check_hle ())
3535 /* Check BND prefix. */
3536 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3537 as_bad (_("expecting valid branch instruction after `bnd'"));
3539 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3540 && flag_code
== CODE_64BIT
3541 && i
.prefix
[ADDR_PREFIX
])
3542 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3544 /* Insert BND prefix. */
3546 && i
.tm
.opcode_modifier
.bndprefixok
3547 && !i
.prefix
[BND_PREFIX
])
3548 add_prefix (BND_PREFIX_OPCODE
);
3550 /* Check string instruction segment overrides. */
3551 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3553 if (!check_string ())
3555 i
.disp_operands
= 0;
3558 if (!process_suffix ())
3561 /* Update operand types. */
3562 for (j
= 0; j
< i
.operands
; j
++)
3563 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3565 /* Make still unresolved immediate matches conform to size of immediate
3566 given in i.suffix. */
3567 if (!finalize_imm ())
3570 if (i
.types
[0].bitfield
.imm1
)
3571 i
.imm_operands
= 0; /* kludge for shift insns. */
3573 /* We only need to check those implicit registers for instructions
3574 with 3 operands or less. */
3575 if (i
.operands
<= 3)
3576 for (j
= 0; j
< i
.operands
; j
++)
3577 if (i
.types
[j
].bitfield
.inoutportreg
3578 || i
.types
[j
].bitfield
.shiftcount
3579 || i
.types
[j
].bitfield
.acc
3580 || i
.types
[j
].bitfield
.floatacc
)
3583 /* ImmExt should be processed after SSE2AVX. */
3584 if (!i
.tm
.opcode_modifier
.sse2avx
3585 && i
.tm
.opcode_modifier
.immext
)
3588 /* For insns with operands there are more diddles to do to the opcode. */
3591 if (!process_operands ())
3594 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3596 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3597 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3600 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3602 if (flag_code
== CODE_16BIT
)
3604 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3609 if (i
.tm
.opcode_modifier
.vex
)
3610 build_vex_prefix (t
);
3612 build_evex_prefix ();
3615 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3616 instructions may define INT_OPCODE as well, so avoid this corner
3617 case for those instructions that use MODRM. */
3618 if (i
.tm
.base_opcode
== INT_OPCODE
3619 && !i
.tm
.opcode_modifier
.modrm
3620 && i
.op
[0].imms
->X_add_number
== 3)
3622 i
.tm
.base_opcode
= INT3_OPCODE
;
3626 if ((i
.tm
.opcode_modifier
.jump
3627 || i
.tm
.opcode_modifier
.jumpbyte
3628 || i
.tm
.opcode_modifier
.jumpdword
)
3629 && i
.op
[0].disps
->X_op
== O_constant
)
3631 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3632 the absolute address given by the constant. Since ix86 jumps and
3633 calls are pc relative, we need to generate a reloc. */
3634 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3635 i
.op
[0].disps
->X_op
= O_symbol
;
3638 if (i
.tm
.opcode_modifier
.rex64
)
3641 /* For 8 bit registers we need an empty rex prefix. Also if the
3642 instruction already has a prefix, we need to convert old
3643 registers to new ones. */
3645 if ((i
.types
[0].bitfield
.reg8
3646 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3647 || (i
.types
[1].bitfield
.reg8
3648 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3649 || ((i
.types
[0].bitfield
.reg8
3650 || i
.types
[1].bitfield
.reg8
)
3655 i
.rex
|= REX_OPCODE
;
3656 for (x
= 0; x
< 2; x
++)
3658 /* Look for 8 bit operand that uses old registers. */
3659 if (i
.types
[x
].bitfield
.reg8
3660 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3662 /* In case it is "hi" register, give up. */
3663 if (i
.op
[x
].regs
->reg_num
> 3)
3664 as_bad (_("can't encode register '%s%s' in an "
3665 "instruction requiring REX prefix."),
3666 register_prefix
, i
.op
[x
].regs
->reg_name
);
3668 /* Otherwise it is equivalent to the extended register.
3669 Since the encoding doesn't change this is merely
3670 cosmetic cleanup for debug output. */
3672 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3678 add_prefix (REX_OPCODE
| i
.rex
);
3680 /* We are ready to output the insn. */
3685 parse_insn (char *line
, char *mnemonic
)
3688 char *token_start
= l
;
3691 const insn_template
*t
;
3697 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3702 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3704 as_bad (_("no such instruction: `%s'"), token_start
);
3709 if (!is_space_char (*l
)
3710 && *l
!= END_OF_INSN
3712 || (*l
!= PREFIX_SEPARATOR
3715 as_bad (_("invalid character %s in mnemonic"),
3716 output_invalid (*l
));
3719 if (token_start
== l
)
3721 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3722 as_bad (_("expecting prefix; got nothing"));
3724 as_bad (_("expecting mnemonic; got nothing"));
3728 /* Look up instruction (or prefix) via hash table. */
3729 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3731 if (*l
!= END_OF_INSN
3732 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3733 && current_templates
3734 && current_templates
->start
->opcode_modifier
.isprefix
)
3736 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3738 as_bad ((flag_code
!= CODE_64BIT
3739 ? _("`%s' is only supported in 64-bit mode")
3740 : _("`%s' is not supported in 64-bit mode")),
3741 current_templates
->start
->name
);
3744 /* If we are in 16-bit mode, do not allow addr16 or data16.
3745 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3746 if ((current_templates
->start
->opcode_modifier
.size16
3747 || current_templates
->start
->opcode_modifier
.size32
)
3748 && flag_code
!= CODE_64BIT
3749 && (current_templates
->start
->opcode_modifier
.size32
3750 ^ (flag_code
== CODE_16BIT
)))
3752 as_bad (_("redundant %s prefix"),
3753 current_templates
->start
->name
);
3756 /* Add prefix, checking for repeated prefixes. */
3757 switch (add_prefix (current_templates
->start
->base_opcode
))
3762 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3763 i
.hle_prefix
= current_templates
->start
->name
;
3764 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3765 i
.bnd_prefix
= current_templates
->start
->name
;
3767 i
.rep_prefix
= current_templates
->start
->name
;
3772 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3779 if (!current_templates
)
3781 /* Check if we should swap operand or force 32bit displacement in
3783 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3785 else if (mnem_p
- 3 == dot_p
3788 i
.disp_encoding
= disp_encoding_8bit
;
3789 else if (mnem_p
- 4 == dot_p
3793 i
.disp_encoding
= disp_encoding_32bit
;
3798 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3801 if (!current_templates
)
3804 /* See if we can get a match by trimming off a suffix. */
3807 case WORD_MNEM_SUFFIX
:
3808 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3809 i
.suffix
= SHORT_MNEM_SUFFIX
;
3811 case BYTE_MNEM_SUFFIX
:
3812 case QWORD_MNEM_SUFFIX
:
3813 i
.suffix
= mnem_p
[-1];
3815 current_templates
= (const templates
*) hash_find (op_hash
,
3818 case SHORT_MNEM_SUFFIX
:
3819 case LONG_MNEM_SUFFIX
:
3822 i
.suffix
= mnem_p
[-1];
3824 current_templates
= (const templates
*) hash_find (op_hash
,
3833 if (intel_float_operand (mnemonic
) == 1)
3834 i
.suffix
= SHORT_MNEM_SUFFIX
;
3836 i
.suffix
= LONG_MNEM_SUFFIX
;
3838 current_templates
= (const templates
*) hash_find (op_hash
,
3843 if (!current_templates
)
3845 as_bad (_("no such instruction: `%s'"), token_start
);
3850 if (current_templates
->start
->opcode_modifier
.jump
3851 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3853 /* Check for a branch hint. We allow ",pt" and ",pn" for
3854 predict taken and predict not taken respectively.
3855 I'm not sure that branch hints actually do anything on loop
3856 and jcxz insns (JumpByte) for current Pentium4 chips. They
3857 may work in the future and it doesn't hurt to accept them
3859 if (l
[0] == ',' && l
[1] == 'p')
3863 if (!add_prefix (DS_PREFIX_OPCODE
))
3867 else if (l
[2] == 'n')
3869 if (!add_prefix (CS_PREFIX_OPCODE
))
3875 /* Any other comma loses. */
3878 as_bad (_("invalid character %s in mnemonic"),
3879 output_invalid (*l
));
3883 /* Check if instruction is supported on specified architecture. */
3885 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3887 supported
|= cpu_flags_match (t
);
3888 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3892 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3894 as_bad (flag_code
== CODE_64BIT
3895 ? _("`%s' is not supported in 64-bit mode")
3896 : _("`%s' is only supported in 64-bit mode"),
3897 current_templates
->start
->name
);
3900 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3902 as_bad (_("`%s' is not supported on `%s%s'"),
3903 current_templates
->start
->name
,
3904 cpu_arch_name
? cpu_arch_name
: default_arch
,
3905 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3910 if (!cpu_arch_flags
.bitfield
.cpui386
3911 && (flag_code
!= CODE_16BIT
))
3913 as_warn (_("use .code16 to ensure correct addressing mode"));
3920 parse_operands (char *l
, const char *mnemonic
)
3924 /* 1 if operand is pending after ','. */
3925 unsigned int expecting_operand
= 0;
3927 /* Non-zero if operand parens not balanced. */
3928 unsigned int paren_not_balanced
;
3930 while (*l
!= END_OF_INSN
)
3932 /* Skip optional white space before operand. */
3933 if (is_space_char (*l
))
3935 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3937 as_bad (_("invalid character %s before operand %d"),
3938 output_invalid (*l
),
3942 token_start
= l
; /* after white space */
3943 paren_not_balanced
= 0;
3944 while (paren_not_balanced
|| *l
!= ',')
3946 if (*l
== END_OF_INSN
)
3948 if (paren_not_balanced
)
3951 as_bad (_("unbalanced parenthesis in operand %d."),
3954 as_bad (_("unbalanced brackets in operand %d."),
3959 break; /* we are done */
3961 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3963 as_bad (_("invalid character %s in operand %d"),
3964 output_invalid (*l
),
3971 ++paren_not_balanced
;
3973 --paren_not_balanced
;
3978 ++paren_not_balanced
;
3980 --paren_not_balanced
;
3984 if (l
!= token_start
)
3985 { /* Yes, we've read in another operand. */
3986 unsigned int operand_ok
;
3987 this_operand
= i
.operands
++;
3988 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3989 if (i
.operands
> MAX_OPERANDS
)
3991 as_bad (_("spurious operands; (%d operands/instruction max)"),
3995 /* Now parse operand adding info to 'i' as we go along. */
3996 END_STRING_AND_SAVE (l
);
4000 i386_intel_operand (token_start
,
4001 intel_float_operand (mnemonic
));
4003 operand_ok
= i386_att_operand (token_start
);
4005 RESTORE_END_STRING (l
);
4011 if (expecting_operand
)
4013 expecting_operand_after_comma
:
4014 as_bad (_("expecting operand after ','; got nothing"));
4019 as_bad (_("expecting operand before ','; got nothing"));
4024 /* Now *l must be either ',' or END_OF_INSN. */
4027 if (*++l
== END_OF_INSN
)
4029 /* Just skip it, if it's \n complain. */
4030 goto expecting_operand_after_comma
;
4032 expecting_operand
= 1;
4039 swap_2_operands (int xchg1
, int xchg2
)
4041 union i386_op temp_op
;
4042 i386_operand_type temp_type
;
4043 enum bfd_reloc_code_real temp_reloc
;
4045 temp_type
= i
.types
[xchg2
];
4046 i
.types
[xchg2
] = i
.types
[xchg1
];
4047 i
.types
[xchg1
] = temp_type
;
4048 temp_op
= i
.op
[xchg2
];
4049 i
.op
[xchg2
] = i
.op
[xchg1
];
4050 i
.op
[xchg1
] = temp_op
;
4051 temp_reloc
= i
.reloc
[xchg2
];
4052 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4053 i
.reloc
[xchg1
] = temp_reloc
;
4057 if (i
.mask
->operand
== xchg1
)
4058 i
.mask
->operand
= xchg2
;
4059 else if (i
.mask
->operand
== xchg2
)
4060 i
.mask
->operand
= xchg1
;
4064 if (i
.broadcast
->operand
== xchg1
)
4065 i
.broadcast
->operand
= xchg2
;
4066 else if (i
.broadcast
->operand
== xchg2
)
4067 i
.broadcast
->operand
= xchg1
;
4071 if (i
.rounding
->operand
== xchg1
)
4072 i
.rounding
->operand
= xchg2
;
4073 else if (i
.rounding
->operand
== xchg2
)
4074 i
.rounding
->operand
= xchg1
;
4079 swap_operands (void)
4085 swap_2_operands (1, i
.operands
- 2);
4088 swap_2_operands (0, i
.operands
- 1);
4094 if (i
.mem_operands
== 2)
4096 const seg_entry
*temp_seg
;
4097 temp_seg
= i
.seg
[0];
4098 i
.seg
[0] = i
.seg
[1];
4099 i
.seg
[1] = temp_seg
;
4103 /* Try to ensure constant immediates are represented in the smallest
4108 char guess_suffix
= 0;
4112 guess_suffix
= i
.suffix
;
4113 else if (i
.reg_operands
)
4115 /* Figure out a suffix from the last register operand specified.
4116 We can't do this properly yet, ie. excluding InOutPortReg,
4117 but the following works for instructions with immediates.
4118 In any case, we can't set i.suffix yet. */
4119 for (op
= i
.operands
; --op
>= 0;)
4120 if (i
.types
[op
].bitfield
.reg8
)
4122 guess_suffix
= BYTE_MNEM_SUFFIX
;
4125 else if (i
.types
[op
].bitfield
.reg16
)
4127 guess_suffix
= WORD_MNEM_SUFFIX
;
4130 else if (i
.types
[op
].bitfield
.reg32
)
4132 guess_suffix
= LONG_MNEM_SUFFIX
;
4135 else if (i
.types
[op
].bitfield
.reg64
)
4137 guess_suffix
= QWORD_MNEM_SUFFIX
;
4141 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4142 guess_suffix
= WORD_MNEM_SUFFIX
;
4144 for (op
= i
.operands
; --op
>= 0;)
4145 if (operand_type_check (i
.types
[op
], imm
))
4147 switch (i
.op
[op
].imms
->X_op
)
4150 /* If a suffix is given, this operand may be shortened. */
4151 switch (guess_suffix
)
4153 case LONG_MNEM_SUFFIX
:
4154 i
.types
[op
].bitfield
.imm32
= 1;
4155 i
.types
[op
].bitfield
.imm64
= 1;
4157 case WORD_MNEM_SUFFIX
:
4158 i
.types
[op
].bitfield
.imm16
= 1;
4159 i
.types
[op
].bitfield
.imm32
= 1;
4160 i
.types
[op
].bitfield
.imm32s
= 1;
4161 i
.types
[op
].bitfield
.imm64
= 1;
4163 case BYTE_MNEM_SUFFIX
:
4164 i
.types
[op
].bitfield
.imm8
= 1;
4165 i
.types
[op
].bitfield
.imm8s
= 1;
4166 i
.types
[op
].bitfield
.imm16
= 1;
4167 i
.types
[op
].bitfield
.imm32
= 1;
4168 i
.types
[op
].bitfield
.imm32s
= 1;
4169 i
.types
[op
].bitfield
.imm64
= 1;
4173 /* If this operand is at most 16 bits, convert it
4174 to a signed 16 bit number before trying to see
4175 whether it will fit in an even smaller size.
4176 This allows a 16-bit operand such as $0xffe0 to
4177 be recognised as within Imm8S range. */
4178 if ((i
.types
[op
].bitfield
.imm16
)
4179 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4181 i
.op
[op
].imms
->X_add_number
=
4182 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4184 if ((i
.types
[op
].bitfield
.imm32
)
4185 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4188 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4189 ^ ((offsetT
) 1 << 31))
4190 - ((offsetT
) 1 << 31));
4193 = operand_type_or (i
.types
[op
],
4194 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4196 /* We must avoid matching of Imm32 templates when 64bit
4197 only immediate is available. */
4198 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4199 i
.types
[op
].bitfield
.imm32
= 0;
4206 /* Symbols and expressions. */
4208 /* Convert symbolic operand to proper sizes for matching, but don't
4209 prevent matching a set of insns that only supports sizes other
4210 than those matching the insn suffix. */
4212 i386_operand_type mask
, allowed
;
4213 const insn_template
*t
;
4215 operand_type_set (&mask
, 0);
4216 operand_type_set (&allowed
, 0);
4218 for (t
= current_templates
->start
;
4219 t
< current_templates
->end
;
4221 allowed
= operand_type_or (allowed
,
4222 t
->operand_types
[op
]);
4223 switch (guess_suffix
)
4225 case QWORD_MNEM_SUFFIX
:
4226 mask
.bitfield
.imm64
= 1;
4227 mask
.bitfield
.imm32s
= 1;
4229 case LONG_MNEM_SUFFIX
:
4230 mask
.bitfield
.imm32
= 1;
4232 case WORD_MNEM_SUFFIX
:
4233 mask
.bitfield
.imm16
= 1;
4235 case BYTE_MNEM_SUFFIX
:
4236 mask
.bitfield
.imm8
= 1;
4241 allowed
= operand_type_and (mask
, allowed
);
4242 if (!operand_type_all_zero (&allowed
))
4243 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4250 /* Try to use the smallest displacement type too. */
4252 optimize_disp (void)
4256 for (op
= i
.operands
; --op
>= 0;)
4257 if (operand_type_check (i
.types
[op
], disp
))
4259 if (i
.op
[op
].disps
->X_op
== O_constant
)
4261 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4263 if (i
.types
[op
].bitfield
.disp16
4264 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4266 /* If this operand is at most 16 bits, convert
4267 to a signed 16 bit number and don't use 64bit
4269 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4270 i
.types
[op
].bitfield
.disp64
= 0;
4272 if (i
.types
[op
].bitfield
.disp32
4273 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4275 /* If this operand is at most 32 bits, convert
4276 to a signed 32 bit number and don't use 64bit
4278 op_disp
&= (((offsetT
) 2 << 31) - 1);
4279 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4280 i
.types
[op
].bitfield
.disp64
= 0;
4282 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4284 i
.types
[op
].bitfield
.disp8
= 0;
4285 i
.types
[op
].bitfield
.disp16
= 0;
4286 i
.types
[op
].bitfield
.disp32
= 0;
4287 i
.types
[op
].bitfield
.disp32s
= 0;
4288 i
.types
[op
].bitfield
.disp64
= 0;
4292 else if (flag_code
== CODE_64BIT
)
4294 if (fits_in_signed_long (op_disp
))
4296 i
.types
[op
].bitfield
.disp64
= 0;
4297 i
.types
[op
].bitfield
.disp32s
= 1;
4299 if (i
.prefix
[ADDR_PREFIX
]
4300 && fits_in_unsigned_long (op_disp
))
4301 i
.types
[op
].bitfield
.disp32
= 1;
4303 if ((i
.types
[op
].bitfield
.disp32
4304 || i
.types
[op
].bitfield
.disp32s
4305 || i
.types
[op
].bitfield
.disp16
)
4306 && fits_in_signed_byte (op_disp
))
4307 i
.types
[op
].bitfield
.disp8
= 1;
4309 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4310 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4312 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4313 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4314 i
.types
[op
].bitfield
.disp8
= 0;
4315 i
.types
[op
].bitfield
.disp16
= 0;
4316 i
.types
[op
].bitfield
.disp32
= 0;
4317 i
.types
[op
].bitfield
.disp32s
= 0;
4318 i
.types
[op
].bitfield
.disp64
= 0;
4321 /* We only support 64bit displacement on constants. */
4322 i
.types
[op
].bitfield
.disp64
= 0;
4326 /* Check if operands are valid for the instruction. */
4329 check_VecOperands (const insn_template
*t
)
4333 /* Without VSIB byte, we can't have a vector register for index. */
4334 if (!t
->opcode_modifier
.vecsib
4336 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4337 || i
.index_reg
->reg_type
.bitfield
.regymm
4338 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4340 i
.error
= unsupported_vector_index_register
;
4344 /* Check if default mask is allowed. */
4345 if (t
->opcode_modifier
.nodefmask
4346 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4348 i
.error
= no_default_mask
;
4352 /* For VSIB byte, we need a vector register for index, and all vector
4353 registers must be distinct. */
4354 if (t
->opcode_modifier
.vecsib
)
4357 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4358 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4359 || (t
->opcode_modifier
.vecsib
== VecSIB256
4360 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4361 || (t
->opcode_modifier
.vecsib
== VecSIB512
4362 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4364 i
.error
= invalid_vsib_address
;
4368 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4369 if (i
.reg_operands
== 2 && !i
.mask
)
4371 gas_assert (i
.types
[0].bitfield
.regxmm
4372 || i
.types
[0].bitfield
.regymm
);
4373 gas_assert (i
.types
[2].bitfield
.regxmm
4374 || i
.types
[2].bitfield
.regymm
);
4375 if (operand_check
== check_none
)
4377 if (register_number (i
.op
[0].regs
)
4378 != register_number (i
.index_reg
)
4379 && register_number (i
.op
[2].regs
)
4380 != register_number (i
.index_reg
)
4381 && register_number (i
.op
[0].regs
)
4382 != register_number (i
.op
[2].regs
))
4384 if (operand_check
== check_error
)
4386 i
.error
= invalid_vector_register_set
;
4389 as_warn (_("mask, index, and destination registers should be distinct"));
4391 else if (i
.reg_operands
== 1 && i
.mask
)
4393 if ((i
.types
[1].bitfield
.regymm
4394 || i
.types
[1].bitfield
.regzmm
)
4395 && (register_number (i
.op
[1].regs
)
4396 == register_number (i
.index_reg
)))
4398 if (operand_check
== check_error
)
4400 i
.error
= invalid_vector_register_set
;
4403 if (operand_check
!= check_none
)
4404 as_warn (_("index and destination registers should be distinct"));
4409 /* Check if broadcast is supported by the instruction and is applied
4410 to the memory operand. */
4413 int broadcasted_opnd_size
;
4415 /* Check if specified broadcast is supported in this instruction,
4416 and it's applied to memory operand of DWORD or QWORD type,
4417 depending on VecESize. */
4418 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4419 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4420 || (t
->opcode_modifier
.vecesize
== 0
4421 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4422 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4423 || (t
->opcode_modifier
.vecesize
== 1
4424 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4425 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4428 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4429 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4430 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4431 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4432 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4433 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4434 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4435 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4436 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4440 if ((broadcasted_opnd_size
== 256
4441 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4442 || (broadcasted_opnd_size
== 512
4443 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4446 i
.error
= unsupported_broadcast
;
4450 /* If broadcast is supported in this instruction, we need to check if
4451 operand of one-element size isn't specified without broadcast. */
4452 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4454 /* Find memory operand. */
4455 for (op
= 0; op
< i
.operands
; op
++)
4456 if (operand_type_check (i
.types
[op
], anymem
))
4458 gas_assert (op
< i
.operands
);
4459 /* Check size of the memory operand. */
4460 if ((t
->opcode_modifier
.vecesize
== 0
4461 && i
.types
[op
].bitfield
.dword
)
4462 || (t
->opcode_modifier
.vecesize
== 1
4463 && i
.types
[op
].bitfield
.qword
))
4465 i
.error
= broadcast_needed
;
4470 /* Check if requested masking is supported. */
4472 && (!t
->opcode_modifier
.masking
4474 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4476 i
.error
= unsupported_masking
;
4480 /* Check if masking is applied to dest operand. */
4481 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4483 i
.error
= mask_not_on_destination
;
4490 if ((i
.rounding
->type
!= saeonly
4491 && !t
->opcode_modifier
.staticrounding
)
4492 || (i
.rounding
->type
== saeonly
4493 && (t
->opcode_modifier
.staticrounding
4494 || !t
->opcode_modifier
.sae
)))
4496 i
.error
= unsupported_rc_sae
;
4499 /* If the instruction has several immediate operands and one of
4500 them is rounding, the rounding operand should be the last
4501 immediate operand. */
4502 if (i
.imm_operands
> 1
4503 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4505 i
.error
= rc_sae_operand_not_last_imm
;
4510 /* Check vector Disp8 operand. */
4511 if (t
->opcode_modifier
.disp8memshift
)
4514 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4516 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4518 for (op
= 0; op
< i
.operands
; op
++)
4519 if (operand_type_check (i
.types
[op
], disp
)
4520 && i
.op
[op
].disps
->X_op
== O_constant
)
4522 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4523 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4524 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4527 i
.types
[op
].bitfield
.vec_disp8
= 1;
4530 /* Vector insn can only have Vec_Disp8/Disp32 in
4531 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4533 i
.types
[op
].bitfield
.disp8
= 0;
4534 if (flag_code
!= CODE_16BIT
)
4535 i
.types
[op
].bitfield
.disp16
= 0;
4538 else if (flag_code
!= CODE_16BIT
)
4540 /* One form of this instruction supports vector Disp8.
4541 Try vector Disp8 if we need to use Disp32. */
4542 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4544 i
.error
= try_vector_disp8
;
4556 /* Check if operands are valid for the instruction. Update VEX
4560 VEX_check_operands (const insn_template
*t
)
4562 /* VREX is only valid with EVEX prefix. */
4563 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4565 i
.error
= invalid_register_operand
;
4569 if (!t
->opcode_modifier
.vex
)
4572 /* Only check VEX_Imm4, which must be the first operand. */
4573 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4575 if (i
.op
[0].imms
->X_op
!= O_constant
4576 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4582 /* Turn off Imm8 so that update_imm won't complain. */
4583 i
.types
[0] = vec_imm4
;
4589 static const insn_template
*
4590 match_template (void)
4592 /* Points to template once we've found it. */
4593 const insn_template
*t
;
4594 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4595 i386_operand_type overlap4
;
4596 unsigned int found_reverse_match
;
4597 i386_opcode_modifier suffix_check
;
4598 i386_operand_type operand_types
[MAX_OPERANDS
];
4599 int addr_prefix_disp
;
4601 unsigned int found_cpu_match
;
4602 unsigned int check_register
;
4603 enum i386_error specific_error
= 0;
4605 #if MAX_OPERANDS != 5
4606 # error "MAX_OPERANDS must be 5."
4609 found_reverse_match
= 0;
4610 addr_prefix_disp
= -1;
4612 memset (&suffix_check
, 0, sizeof (suffix_check
));
4613 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4614 suffix_check
.no_bsuf
= 1;
4615 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4616 suffix_check
.no_wsuf
= 1;
4617 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4618 suffix_check
.no_ssuf
= 1;
4619 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4620 suffix_check
.no_lsuf
= 1;
4621 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4622 suffix_check
.no_qsuf
= 1;
4623 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4624 suffix_check
.no_ldsuf
= 1;
4626 /* Must have right number of operands. */
4627 i
.error
= number_of_operands_mismatch
;
4629 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4631 addr_prefix_disp
= -1;
4633 if (i
.operands
!= t
->operands
)
4636 /* Check processor support. */
4637 i
.error
= unsupported
;
4638 found_cpu_match
= (cpu_flags_match (t
)
4639 == CPU_FLAGS_PERFECT_MATCH
);
4640 if (!found_cpu_match
)
4643 /* Check old gcc support. */
4644 i
.error
= old_gcc_only
;
4645 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4648 /* Check AT&T mnemonic. */
4649 i
.error
= unsupported_with_intel_mnemonic
;
4650 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4653 /* Check AT&T/Intel syntax. */
4654 i
.error
= unsupported_syntax
;
4655 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4656 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4659 /* Check the suffix, except for some instructions in intel mode. */
4660 i
.error
= invalid_instruction_suffix
;
4661 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4662 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4663 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4664 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4665 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4666 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4667 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4670 if (!operand_size_match (t
))
4673 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4674 operand_types
[j
] = t
->operand_types
[j
];
4676 /* In general, don't allow 64-bit operands in 32-bit mode. */
4677 if (i
.suffix
== QWORD_MNEM_SUFFIX
4678 && flag_code
!= CODE_64BIT
4680 ? (!t
->opcode_modifier
.ignoresize
4681 && !intel_float_operand (t
->name
))
4682 : intel_float_operand (t
->name
) != 2)
4683 && ((!operand_types
[0].bitfield
.regmmx
4684 && !operand_types
[0].bitfield
.regxmm
4685 && !operand_types
[0].bitfield
.regymm
4686 && !operand_types
[0].bitfield
.regzmm
)
4687 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4688 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4689 && operand_types
[t
->operands
> 1].bitfield
.regymm
4690 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4691 && (t
->base_opcode
!= 0x0fc7
4692 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4695 /* In general, don't allow 32-bit operands on pre-386. */
4696 else if (i
.suffix
== LONG_MNEM_SUFFIX
4697 && !cpu_arch_flags
.bitfield
.cpui386
4699 ? (!t
->opcode_modifier
.ignoresize
4700 && !intel_float_operand (t
->name
))
4701 : intel_float_operand (t
->name
) != 2)
4702 && ((!operand_types
[0].bitfield
.regmmx
4703 && !operand_types
[0].bitfield
.regxmm
)
4704 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4705 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4708 /* Do not verify operands when there are none. */
4712 /* We've found a match; break out of loop. */
4716 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4717 into Disp32/Disp16/Disp32 operand. */
4718 if (i
.prefix
[ADDR_PREFIX
] != 0)
4720 /* There should be only one Disp operand. */
4724 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4726 if (operand_types
[j
].bitfield
.disp16
)
4728 addr_prefix_disp
= j
;
4729 operand_types
[j
].bitfield
.disp32
= 1;
4730 operand_types
[j
].bitfield
.disp16
= 0;
4736 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4738 if (operand_types
[j
].bitfield
.disp32
)
4740 addr_prefix_disp
= j
;
4741 operand_types
[j
].bitfield
.disp32
= 0;
4742 operand_types
[j
].bitfield
.disp16
= 1;
4748 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4750 if (operand_types
[j
].bitfield
.disp64
)
4752 addr_prefix_disp
= j
;
4753 operand_types
[j
].bitfield
.disp64
= 0;
4754 operand_types
[j
].bitfield
.disp32
= 1;
4762 /* We check register size if needed. */
4763 check_register
= t
->opcode_modifier
.checkregsize
;
4764 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4765 switch (t
->operands
)
4768 if (!operand_type_match (overlap0
, i
.types
[0]))
4772 /* xchg %eax, %eax is a special case. It is an aliase for nop
4773 only in 32bit mode and we can use opcode 0x90. In 64bit
4774 mode, we can't use 0x90 for xchg %eax, %eax since it should
4775 zero-extend %eax to %rax. */
4776 if (flag_code
== CODE_64BIT
4777 && t
->base_opcode
== 0x90
4778 && operand_type_equal (&i
.types
[0], &acc32
)
4779 && operand_type_equal (&i
.types
[1], &acc32
))
4783 /* If we swap operand in encoding, we either match
4784 the next one or reverse direction of operands. */
4785 if (t
->opcode_modifier
.s
)
4787 else if (t
->opcode_modifier
.d
)
4792 /* If we swap operand in encoding, we match the next one. */
4793 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4797 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4798 if (!operand_type_match (overlap0
, i
.types
[0])
4799 || !operand_type_match (overlap1
, i
.types
[1])
4801 && !operand_type_register_match (overlap0
, i
.types
[0],
4803 overlap1
, i
.types
[1],
4806 /* Check if other direction is valid ... */
4807 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4811 /* Try reversing direction of operands. */
4812 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4813 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4814 if (!operand_type_match (overlap0
, i
.types
[0])
4815 || !operand_type_match (overlap1
, i
.types
[1])
4817 && !operand_type_register_match (overlap0
,
4824 /* Does not match either direction. */
4827 /* found_reverse_match holds which of D or FloatDR
4829 if (t
->opcode_modifier
.d
)
4830 found_reverse_match
= Opcode_D
;
4831 else if (t
->opcode_modifier
.floatd
)
4832 found_reverse_match
= Opcode_FloatD
;
4834 found_reverse_match
= 0;
4835 if (t
->opcode_modifier
.floatr
)
4836 found_reverse_match
|= Opcode_FloatR
;
4840 /* Found a forward 2 operand match here. */
4841 switch (t
->operands
)
4844 overlap4
= operand_type_and (i
.types
[4],
4847 overlap3
= operand_type_and (i
.types
[3],
4850 overlap2
= operand_type_and (i
.types
[2],
4855 switch (t
->operands
)
4858 if (!operand_type_match (overlap4
, i
.types
[4])
4859 || !operand_type_register_match (overlap3
,
4867 if (!operand_type_match (overlap3
, i
.types
[3])
4869 && !operand_type_register_match (overlap2
,
4877 /* Here we make use of the fact that there are no
4878 reverse match 3 operand instructions, and all 3
4879 operand instructions only need to be checked for
4880 register consistency between operands 2 and 3. */
4881 if (!operand_type_match (overlap2
, i
.types
[2])
4883 && !operand_type_register_match (overlap1
,
4893 /* Found either forward/reverse 2, 3 or 4 operand match here:
4894 slip through to break. */
4896 if (!found_cpu_match
)
4898 found_reverse_match
= 0;
4902 /* Check if vector and VEX operands are valid. */
4903 if (check_VecOperands (t
) || VEX_check_operands (t
))
4905 specific_error
= i
.error
;
4909 /* We've found a match; break out of loop. */
4913 if (t
== current_templates
->end
)
4915 /* We found no match. */
4916 const char *err_msg
;
4917 switch (specific_error
? specific_error
: i
.error
)
4921 case operand_size_mismatch
:
4922 err_msg
= _("operand size mismatch");
4924 case operand_type_mismatch
:
4925 err_msg
= _("operand type mismatch");
4927 case register_type_mismatch
:
4928 err_msg
= _("register type mismatch");
4930 case number_of_operands_mismatch
:
4931 err_msg
= _("number of operands mismatch");
4933 case invalid_instruction_suffix
:
4934 err_msg
= _("invalid instruction suffix");
4937 err_msg
= _("constant doesn't fit in 4 bits");
4940 err_msg
= _("only supported with old gcc");
4942 case unsupported_with_intel_mnemonic
:
4943 err_msg
= _("unsupported with Intel mnemonic");
4945 case unsupported_syntax
:
4946 err_msg
= _("unsupported syntax");
4949 as_bad (_("unsupported instruction `%s'"),
4950 current_templates
->start
->name
);
4952 case invalid_vsib_address
:
4953 err_msg
= _("invalid VSIB address");
4955 case invalid_vector_register_set
:
4956 err_msg
= _("mask, index, and destination registers must be distinct");
4958 case unsupported_vector_index_register
:
4959 err_msg
= _("unsupported vector index register");
4961 case unsupported_broadcast
:
4962 err_msg
= _("unsupported broadcast");
4964 case broadcast_not_on_src_operand
:
4965 err_msg
= _("broadcast not on source memory operand");
4967 case broadcast_needed
:
4968 err_msg
= _("broadcast is needed for operand of such type");
4970 case unsupported_masking
:
4971 err_msg
= _("unsupported masking");
4973 case mask_not_on_destination
:
4974 err_msg
= _("mask not on destination operand");
4976 case no_default_mask
:
4977 err_msg
= _("default mask isn't allowed");
4979 case unsupported_rc_sae
:
4980 err_msg
= _("unsupported static rounding/sae");
4982 case rc_sae_operand_not_last_imm
:
4984 err_msg
= _("RC/SAE operand must precede immediate operands");
4986 err_msg
= _("RC/SAE operand must follow immediate operands");
4988 case invalid_register_operand
:
4989 err_msg
= _("invalid register operand");
4992 as_bad (_("%s for `%s'"), err_msg
,
4993 current_templates
->start
->name
);
4997 if (!quiet_warnings
)
5000 && (i
.types
[0].bitfield
.jumpabsolute
5001 != operand_types
[0].bitfield
.jumpabsolute
))
5003 as_warn (_("indirect %s without `*'"), t
->name
);
5006 if (t
->opcode_modifier
.isprefix
5007 && t
->opcode_modifier
.ignoresize
)
5009 /* Warn them that a data or address size prefix doesn't
5010 affect assembly of the next line of code. */
5011 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5015 /* Copy the template we found. */
5018 if (addr_prefix_disp
!= -1)
5019 i
.tm
.operand_types
[addr_prefix_disp
]
5020 = operand_types
[addr_prefix_disp
];
5022 if (found_reverse_match
)
5024 /* If we found a reverse match we must alter the opcode
5025 direction bit. found_reverse_match holds bits to change
5026 (different for int & float insns). */
5028 i
.tm
.base_opcode
^= found_reverse_match
;
5030 i
.tm
.operand_types
[0] = operand_types
[1];
5031 i
.tm
.operand_types
[1] = operand_types
[0];
5040 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5041 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5043 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5045 as_bad (_("`%s' operand %d must use `%ses' segment"),
5051 /* There's only ever one segment override allowed per instruction.
5052 This instruction possibly has a legal segment override on the
5053 second operand, so copy the segment to where non-string
5054 instructions store it, allowing common code. */
5055 i
.seg
[0] = i
.seg
[1];
5057 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5059 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5061 as_bad (_("`%s' operand %d must use `%ses' segment"),
5072 process_suffix (void)
5074 /* If matched instruction specifies an explicit instruction mnemonic
5076 if (i
.tm
.opcode_modifier
.size16
)
5077 i
.suffix
= WORD_MNEM_SUFFIX
;
5078 else if (i
.tm
.opcode_modifier
.size32
)
5079 i
.suffix
= LONG_MNEM_SUFFIX
;
5080 else if (i
.tm
.opcode_modifier
.size64
)
5081 i
.suffix
= QWORD_MNEM_SUFFIX
;
5082 else if (i
.reg_operands
)
5084 /* If there's no instruction mnemonic suffix we try to invent one
5085 based on register operands. */
5088 /* We take i.suffix from the last register operand specified,
5089 Destination register type is more significant than source
5090 register type. crc32 in SSE4.2 prefers source register
5092 if (i
.tm
.base_opcode
== 0xf20f38f1)
5094 if (i
.types
[0].bitfield
.reg16
)
5095 i
.suffix
= WORD_MNEM_SUFFIX
;
5096 else if (i
.types
[0].bitfield
.reg32
)
5097 i
.suffix
= LONG_MNEM_SUFFIX
;
5098 else if (i
.types
[0].bitfield
.reg64
)
5099 i
.suffix
= QWORD_MNEM_SUFFIX
;
5101 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5103 if (i
.types
[0].bitfield
.reg8
)
5104 i
.suffix
= BYTE_MNEM_SUFFIX
;
5111 if (i
.tm
.base_opcode
== 0xf20f38f1
5112 || i
.tm
.base_opcode
== 0xf20f38f0)
5114 /* We have to know the operand size for crc32. */
5115 as_bad (_("ambiguous memory operand size for `%s`"),
5120 for (op
= i
.operands
; --op
>= 0;)
5121 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5123 if (i
.types
[op
].bitfield
.reg8
)
5125 i
.suffix
= BYTE_MNEM_SUFFIX
;
5128 else if (i
.types
[op
].bitfield
.reg16
)
5130 i
.suffix
= WORD_MNEM_SUFFIX
;
5133 else if (i
.types
[op
].bitfield
.reg32
)
5135 i
.suffix
= LONG_MNEM_SUFFIX
;
5138 else if (i
.types
[op
].bitfield
.reg64
)
5140 i
.suffix
= QWORD_MNEM_SUFFIX
;
5146 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5149 && i
.tm
.opcode_modifier
.ignoresize
5150 && i
.tm
.opcode_modifier
.no_bsuf
)
5152 else if (!check_byte_reg ())
5155 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5158 && i
.tm
.opcode_modifier
.ignoresize
5159 && i
.tm
.opcode_modifier
.no_lsuf
)
5161 else if (!check_long_reg ())
5164 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5167 && i
.tm
.opcode_modifier
.ignoresize
5168 && i
.tm
.opcode_modifier
.no_qsuf
)
5170 else if (!check_qword_reg ())
5173 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5176 && i
.tm
.opcode_modifier
.ignoresize
5177 && i
.tm
.opcode_modifier
.no_wsuf
)
5179 else if (!check_word_reg ())
5182 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5183 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5184 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5186 /* Skip if the instruction has x/y/z suffix. match_template
5187 should check if it is a valid suffix. */
5189 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5190 /* Do nothing if the instruction is going to ignore the prefix. */
5195 else if (i
.tm
.opcode_modifier
.defaultsize
5197 /* exclude fldenv/frstor/fsave/fstenv */
5198 && i
.tm
.opcode_modifier
.no_ssuf
)
5200 i
.suffix
= stackop_size
;
5202 else if (intel_syntax
5204 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5205 || i
.tm
.opcode_modifier
.jumpbyte
5206 || i
.tm
.opcode_modifier
.jumpintersegment
5207 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5208 && i
.tm
.extension_opcode
<= 3)))
5213 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5215 i
.suffix
= QWORD_MNEM_SUFFIX
;
5219 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5220 i
.suffix
= LONG_MNEM_SUFFIX
;
5223 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5224 i
.suffix
= WORD_MNEM_SUFFIX
;
5233 if (i
.tm
.opcode_modifier
.w
)
5235 as_bad (_("no instruction mnemonic suffix given and "
5236 "no register operands; can't size instruction"));
5242 unsigned int suffixes
;
5244 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5245 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5247 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5249 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5251 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5253 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5256 /* There are more than suffix matches. */
5257 if (i
.tm
.opcode_modifier
.w
5258 || ((suffixes
& (suffixes
- 1))
5259 && !i
.tm
.opcode_modifier
.defaultsize
5260 && !i
.tm
.opcode_modifier
.ignoresize
))
5262 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5268 /* Change the opcode based on the operand size given by i.suffix;
5269 We don't need to change things for byte insns. */
5272 && i
.suffix
!= BYTE_MNEM_SUFFIX
5273 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5274 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5275 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5277 /* It's not a byte, select word/dword operation. */
5278 if (i
.tm
.opcode_modifier
.w
)
5280 if (i
.tm
.opcode_modifier
.shortform
)
5281 i
.tm
.base_opcode
|= 8;
5283 i
.tm
.base_opcode
|= 1;
5286 /* Now select between word & dword operations via the operand
5287 size prefix, except for instructions that will ignore this
5289 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5291 /* The address size override prefix changes the size of the
5293 if ((flag_code
== CODE_32BIT
5294 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5295 || (flag_code
!= CODE_32BIT
5296 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5297 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5300 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5301 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5302 && !i
.tm
.opcode_modifier
.ignoresize
5303 && !i
.tm
.opcode_modifier
.floatmf
5304 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5305 || (flag_code
== CODE_64BIT
5306 && i
.tm
.opcode_modifier
.jumpbyte
)))
5308 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5310 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5311 prefix
= ADDR_PREFIX_OPCODE
;
5313 if (!add_prefix (prefix
))
5317 /* Set mode64 for an operand. */
5318 if (i
.suffix
== QWORD_MNEM_SUFFIX
5319 && flag_code
== CODE_64BIT
5320 && !i
.tm
.opcode_modifier
.norex64
)
5322 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5323 need rex64. cmpxchg8b is also a special case. */
5324 if (! (i
.operands
== 2
5325 && i
.tm
.base_opcode
== 0x90
5326 && i
.tm
.extension_opcode
== None
5327 && operand_type_equal (&i
.types
[0], &acc64
)
5328 && operand_type_equal (&i
.types
[1], &acc64
))
5329 && ! (i
.operands
== 1
5330 && i
.tm
.base_opcode
== 0xfc7
5331 && i
.tm
.extension_opcode
== 1
5332 && !operand_type_check (i
.types
[0], reg
)
5333 && operand_type_check (i
.types
[0], anymem
)))
5337 /* Size floating point instruction. */
5338 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5339 if (i
.tm
.opcode_modifier
.floatmf
)
5340 i
.tm
.base_opcode
^= 4;
5347 check_byte_reg (void)
5351 for (op
= i
.operands
; --op
>= 0;)
5353 /* If this is an eight bit register, it's OK. If it's the 16 or
5354 32 bit version of an eight bit register, we will just use the
5355 low portion, and that's OK too. */
5356 if (i
.types
[op
].bitfield
.reg8
)
5359 /* I/O port address operands are OK too. */
5360 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5363 /* crc32 doesn't generate this warning. */
5364 if (i
.tm
.base_opcode
== 0xf20f38f0)
5367 if ((i
.types
[op
].bitfield
.reg16
5368 || i
.types
[op
].bitfield
.reg32
5369 || i
.types
[op
].bitfield
.reg64
)
5370 && i
.op
[op
].regs
->reg_num
< 4
5371 /* Prohibit these changes in 64bit mode, since the lowering
5372 would be more complicated. */
5373 && flag_code
!= CODE_64BIT
)
5375 #if REGISTER_WARNINGS
5376 if (!quiet_warnings
)
5377 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5379 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5380 ? REGNAM_AL
- REGNAM_AX
5381 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5383 i
.op
[op
].regs
->reg_name
,
5388 /* Any other register is bad. */
5389 if (i
.types
[op
].bitfield
.reg16
5390 || i
.types
[op
].bitfield
.reg32
5391 || i
.types
[op
].bitfield
.reg64
5392 || i
.types
[op
].bitfield
.regmmx
5393 || i
.types
[op
].bitfield
.regxmm
5394 || i
.types
[op
].bitfield
.regymm
5395 || i
.types
[op
].bitfield
.regzmm
5396 || i
.types
[op
].bitfield
.sreg2
5397 || i
.types
[op
].bitfield
.sreg3
5398 || i
.types
[op
].bitfield
.control
5399 || i
.types
[op
].bitfield
.debug
5400 || i
.types
[op
].bitfield
.test
5401 || i
.types
[op
].bitfield
.floatreg
5402 || i
.types
[op
].bitfield
.floatacc
)
5404 as_bad (_("`%s%s' not allowed with `%s%c'"),
5406 i
.op
[op
].regs
->reg_name
,
5416 check_long_reg (void)
5420 for (op
= i
.operands
; --op
>= 0;)
5421 /* Reject eight bit registers, except where the template requires
5422 them. (eg. movzb) */
5423 if (i
.types
[op
].bitfield
.reg8
5424 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5425 || i
.tm
.operand_types
[op
].bitfield
.reg32
5426 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5428 as_bad (_("`%s%s' not allowed with `%s%c'"),
5430 i
.op
[op
].regs
->reg_name
,
5435 /* Warn if the e prefix on a general reg is missing. */
5436 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5437 && i
.types
[op
].bitfield
.reg16
5438 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5439 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5441 /* Prohibit these changes in the 64bit mode, since the
5442 lowering is more complicated. */
5443 if (flag_code
== CODE_64BIT
)
5445 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5446 register_prefix
, i
.op
[op
].regs
->reg_name
,
5450 #if REGISTER_WARNINGS
5451 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5453 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5454 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5457 /* Warn if the r prefix on a general reg is present. */
5458 else if (i
.types
[op
].bitfield
.reg64
5459 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5460 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5463 && i
.tm
.opcode_modifier
.toqword
5464 && !i
.types
[0].bitfield
.regxmm
)
5466 /* Convert to QWORD. We want REX byte. */
5467 i
.suffix
= QWORD_MNEM_SUFFIX
;
5471 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5472 register_prefix
, i
.op
[op
].regs
->reg_name
,
5481 check_qword_reg (void)
5485 for (op
= i
.operands
; --op
>= 0; )
5486 /* Reject eight bit registers, except where the template requires
5487 them. (eg. movzb) */
5488 if (i
.types
[op
].bitfield
.reg8
5489 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5490 || i
.tm
.operand_types
[op
].bitfield
.reg32
5491 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5493 as_bad (_("`%s%s' not allowed with `%s%c'"),
5495 i
.op
[op
].regs
->reg_name
,
5500 /* Warn if the r prefix on a general reg is missing. */
5501 else if ((i
.types
[op
].bitfield
.reg16
5502 || i
.types
[op
].bitfield
.reg32
)
5503 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5504 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5506 /* Prohibit these changes in the 64bit mode, since the
5507 lowering is more complicated. */
5509 && i
.tm
.opcode_modifier
.todword
5510 && !i
.types
[0].bitfield
.regxmm
)
5512 /* Convert to DWORD. We don't want REX byte. */
5513 i
.suffix
= LONG_MNEM_SUFFIX
;
5517 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5518 register_prefix
, i
.op
[op
].regs
->reg_name
,
5527 check_word_reg (void)
5530 for (op
= i
.operands
; --op
>= 0;)
5531 /* Reject eight bit registers, except where the template requires
5532 them. (eg. movzb) */
5533 if (i
.types
[op
].bitfield
.reg8
5534 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5535 || i
.tm
.operand_types
[op
].bitfield
.reg32
5536 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5538 as_bad (_("`%s%s' not allowed with `%s%c'"),
5540 i
.op
[op
].regs
->reg_name
,
5545 /* Warn if the e or r prefix on a general reg is present. */
5546 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5547 && (i
.types
[op
].bitfield
.reg32
5548 || i
.types
[op
].bitfield
.reg64
)
5549 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5550 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5552 /* Prohibit these changes in the 64bit mode, since the
5553 lowering is more complicated. */
5554 if (flag_code
== CODE_64BIT
)
5556 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5557 register_prefix
, i
.op
[op
].regs
->reg_name
,
5561 #if REGISTER_WARNINGS
5562 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5564 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5565 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5572 update_imm (unsigned int j
)
5574 i386_operand_type overlap
= i
.types
[j
];
5575 if ((overlap
.bitfield
.imm8
5576 || overlap
.bitfield
.imm8s
5577 || overlap
.bitfield
.imm16
5578 || overlap
.bitfield
.imm32
5579 || overlap
.bitfield
.imm32s
5580 || overlap
.bitfield
.imm64
)
5581 && !operand_type_equal (&overlap
, &imm8
)
5582 && !operand_type_equal (&overlap
, &imm8s
)
5583 && !operand_type_equal (&overlap
, &imm16
)
5584 && !operand_type_equal (&overlap
, &imm32
)
5585 && !operand_type_equal (&overlap
, &imm32s
)
5586 && !operand_type_equal (&overlap
, &imm64
))
5590 i386_operand_type temp
;
5592 operand_type_set (&temp
, 0);
5593 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5595 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5596 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5598 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5599 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5600 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5602 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5603 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5606 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5609 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5610 || operand_type_equal (&overlap
, &imm16_32
)
5611 || operand_type_equal (&overlap
, &imm16_32s
))
5613 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5618 if (!operand_type_equal (&overlap
, &imm8
)
5619 && !operand_type_equal (&overlap
, &imm8s
)
5620 && !operand_type_equal (&overlap
, &imm16
)
5621 && !operand_type_equal (&overlap
, &imm32
)
5622 && !operand_type_equal (&overlap
, &imm32s
)
5623 && !operand_type_equal (&overlap
, &imm64
))
5625 as_bad (_("no instruction mnemonic suffix given; "
5626 "can't determine immediate size"));
5630 i
.types
[j
] = overlap
;
5640 /* Update the first 2 immediate operands. */
5641 n
= i
.operands
> 2 ? 2 : i
.operands
;
5644 for (j
= 0; j
< n
; j
++)
5645 if (update_imm (j
) == 0)
5648 /* The 3rd operand can't be immediate operand. */
5649 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5656 bad_implicit_operand (int xmm
)
5658 const char *ireg
= xmm
? "xmm0" : "ymm0";
5661 as_bad (_("the last operand of `%s' must be `%s%s'"),
5662 i
.tm
.name
, register_prefix
, ireg
);
5664 as_bad (_("the first operand of `%s' must be `%s%s'"),
5665 i
.tm
.name
, register_prefix
, ireg
);
5670 process_operands (void)
5672 /* Default segment register this instruction will use for memory
5673 accesses. 0 means unknown. This is only for optimizing out
5674 unnecessary segment overrides. */
5675 const seg_entry
*default_seg
= 0;
5677 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5679 unsigned int dupl
= i
.operands
;
5680 unsigned int dest
= dupl
- 1;
5683 /* The destination must be an xmm register. */
5684 gas_assert (i
.reg_operands
5685 && MAX_OPERANDS
> dupl
5686 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5688 if (i
.tm
.opcode_modifier
.firstxmm0
)
5690 /* The first operand is implicit and must be xmm0. */
5691 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5692 if (register_number (i
.op
[0].regs
) != 0)
5693 return bad_implicit_operand (1);
5695 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5697 /* Keep xmm0 for instructions with VEX prefix and 3
5703 /* We remove the first xmm0 and keep the number of
5704 operands unchanged, which in fact duplicates the
5706 for (j
= 1; j
< i
.operands
; j
++)
5708 i
.op
[j
- 1] = i
.op
[j
];
5709 i
.types
[j
- 1] = i
.types
[j
];
5710 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5714 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5716 gas_assert ((MAX_OPERANDS
- 1) > dupl
5717 && (i
.tm
.opcode_modifier
.vexsources
5720 /* Add the implicit xmm0 for instructions with VEX prefix
5722 for (j
= i
.operands
; j
> 0; j
--)
5724 i
.op
[j
] = i
.op
[j
- 1];
5725 i
.types
[j
] = i
.types
[j
- 1];
5726 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5729 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5730 i
.types
[0] = regxmm
;
5731 i
.tm
.operand_types
[0] = regxmm
;
5734 i
.reg_operands
+= 2;
5739 i
.op
[dupl
] = i
.op
[dest
];
5740 i
.types
[dupl
] = i
.types
[dest
];
5741 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5750 i
.op
[dupl
] = i
.op
[dest
];
5751 i
.types
[dupl
] = i
.types
[dest
];
5752 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5755 if (i
.tm
.opcode_modifier
.immext
)
5758 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5762 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5763 gas_assert (i
.reg_operands
5764 && (operand_type_equal (&i
.types
[0], ®xmm
)
5765 || operand_type_equal (&i
.types
[0], ®ymm
)
5766 || operand_type_equal (&i
.types
[0], ®zmm
)));
5767 if (register_number (i
.op
[0].regs
) != 0)
5768 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5770 for (j
= 1; j
< i
.operands
; j
++)
5772 i
.op
[j
- 1] = i
.op
[j
];
5773 i
.types
[j
- 1] = i
.types
[j
];
5775 /* We need to adjust fields in i.tm since they are used by
5776 build_modrm_byte. */
5777 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5784 else if (i
.tm
.opcode_modifier
.regkludge
)
5786 /* The imul $imm, %reg instruction is converted into
5787 imul $imm, %reg, %reg, and the clr %reg instruction
5788 is converted into xor %reg, %reg. */
5790 unsigned int first_reg_op
;
5792 if (operand_type_check (i
.types
[0], reg
))
5796 /* Pretend we saw the extra register operand. */
5797 gas_assert (i
.reg_operands
== 1
5798 && i
.op
[first_reg_op
+ 1].regs
== 0);
5799 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5800 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5805 if (i
.tm
.opcode_modifier
.shortform
)
5807 if (i
.types
[0].bitfield
.sreg2
5808 || i
.types
[0].bitfield
.sreg3
)
5810 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5811 && i
.op
[0].regs
->reg_num
== 1)
5813 as_bad (_("you can't `pop %scs'"), register_prefix
);
5816 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5817 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5822 /* The register or float register operand is in operand
5826 if (i
.types
[0].bitfield
.floatreg
5827 || operand_type_check (i
.types
[0], reg
))
5831 /* Register goes in low 3 bits of opcode. */
5832 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5833 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5835 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5837 /* Warn about some common errors, but press on regardless.
5838 The first case can be generated by gcc (<= 2.8.1). */
5839 if (i
.operands
== 2)
5841 /* Reversed arguments on faddp, fsubp, etc. */
5842 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5843 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5844 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5848 /* Extraneous `l' suffix on fp insn. */
5849 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5850 register_prefix
, i
.op
[0].regs
->reg_name
);
5855 else if (i
.tm
.opcode_modifier
.modrm
)
5857 /* The opcode is completed (modulo i.tm.extension_opcode which
5858 must be put into the modrm byte). Now, we make the modrm and
5859 index base bytes based on all the info we've collected. */
5861 default_seg
= build_modrm_byte ();
5863 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5867 else if (i
.tm
.opcode_modifier
.isstring
)
5869 /* For the string instructions that allow a segment override
5870 on one of their operands, the default segment is ds. */
5874 if (i
.tm
.base_opcode
== 0x8d /* lea */
5877 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5879 /* If a segment was explicitly specified, and the specified segment
5880 is not the default, use an opcode prefix to select it. If we
5881 never figured out what the default segment is, then default_seg
5882 will be zero at this point, and the specified segment prefix will
5884 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5886 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5892 static const seg_entry
*
5893 build_modrm_byte (void)
5895 const seg_entry
*default_seg
= 0;
5896 unsigned int source
, dest
;
5899 /* The first operand of instructions with VEX prefix and 3 sources
5900 must be VEX_Imm4. */
5901 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5904 unsigned int nds
, reg_slot
;
5907 if (i
.tm
.opcode_modifier
.veximmext
5908 && i
.tm
.opcode_modifier
.immext
)
5910 dest
= i
.operands
- 2;
5911 gas_assert (dest
== 3);
5914 dest
= i
.operands
- 1;
5917 /* There are 2 kinds of instructions:
5918 1. 5 operands: 4 register operands or 3 register operands
5919 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5920 VexW0 or VexW1. The destination must be either XMM, YMM or
5922 2. 4 operands: 4 register operands or 3 register operands
5923 plus 1 memory operand, VexXDS, and VexImmExt */
5924 gas_assert ((i
.reg_operands
== 4
5925 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5926 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5927 && (i
.tm
.opcode_modifier
.veximmext
5928 || (i
.imm_operands
== 1
5929 && i
.types
[0].bitfield
.vec_imm4
5930 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5931 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5932 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5933 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5934 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5936 if (i
.imm_operands
== 0)
5938 /* When there is no immediate operand, generate an 8bit
5939 immediate operand to encode the first operand. */
5940 exp
= &im_expressions
[i
.imm_operands
++];
5941 i
.op
[i
.operands
].imms
= exp
;
5942 i
.types
[i
.operands
] = imm8
;
5944 /* If VexW1 is set, the first operand is the source and
5945 the second operand is encoded in the immediate operand. */
5946 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5957 /* FMA swaps REG and NDS. */
5958 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5966 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5968 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5970 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5972 exp
->X_op
= O_constant
;
5973 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5974 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5978 unsigned int imm_slot
;
5980 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5982 /* If VexW0 is set, the third operand is the source and
5983 the second operand is encoded in the immediate
5990 /* VexW1 is set, the second operand is the source and
5991 the third operand is encoded in the immediate
5997 if (i
.tm
.opcode_modifier
.immext
)
5999 /* When ImmExt is set, the immdiate byte is the last
6001 imm_slot
= i
.operands
- 1;
6009 /* Turn on Imm8 so that output_imm will generate it. */
6010 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6013 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6015 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6017 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6019 i
.op
[imm_slot
].imms
->X_add_number
6020 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6021 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6024 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6025 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6027 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6029 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6034 /* i.reg_operands MUST be the number of real register operands;
6035 implicit registers do not count. If there are 3 register
6036 operands, it must be a instruction with VexNDS. For a
6037 instruction with VexNDD, the destination register is encoded
6038 in VEX prefix. If there are 4 register operands, it must be
6039 a instruction with VEX prefix and 3 sources. */
6040 if (i
.mem_operands
== 0
6041 && ((i
.reg_operands
== 2
6042 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6043 || (i
.reg_operands
== 3
6044 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6045 || (i
.reg_operands
== 4 && vex_3_sources
)))
6053 /* When there are 3 operands, one of them may be immediate,
6054 which may be the first or the last operand. Otherwise,
6055 the first operand must be shift count register (cl) or it
6056 is an instruction with VexNDS. */
6057 gas_assert (i
.imm_operands
== 1
6058 || (i
.imm_operands
== 0
6059 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6060 || i
.types
[0].bitfield
.shiftcount
)));
6061 if (operand_type_check (i
.types
[0], imm
)
6062 || i
.types
[0].bitfield
.shiftcount
)
6068 /* When there are 4 operands, the first two must be 8bit
6069 immediate operands. The source operand will be the 3rd
6072 For instructions with VexNDS, if the first operand
6073 an imm8, the source operand is the 2nd one. If the last
6074 operand is imm8, the source operand is the first one. */
6075 gas_assert ((i
.imm_operands
== 2
6076 && i
.types
[0].bitfield
.imm8
6077 && i
.types
[1].bitfield
.imm8
)
6078 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6079 && i
.imm_operands
== 1
6080 && (i
.types
[0].bitfield
.imm8
6081 || i
.types
[i
.operands
- 1].bitfield
.imm8
6083 if (i
.imm_operands
== 2)
6087 if (i
.types
[0].bitfield
.imm8
)
6094 if (i
.tm
.opcode_modifier
.evex
)
6096 /* For EVEX instructions, when there are 5 operands, the
6097 first one must be immediate operand. If the second one
6098 is immediate operand, the source operand is the 3th
6099 one. If the last one is immediate operand, the source
6100 operand is the 2nd one. */
6101 gas_assert (i
.imm_operands
== 2
6102 && i
.tm
.opcode_modifier
.sae
6103 && operand_type_check (i
.types
[0], imm
));
6104 if (operand_type_check (i
.types
[1], imm
))
6106 else if (operand_type_check (i
.types
[4], imm
))
6120 /* RC/SAE operand could be between DEST and SRC. That happens
6121 when one operand is GPR and the other one is XMM/YMM/ZMM
6123 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6126 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6128 /* For instructions with VexNDS, the register-only source
6129 operand must be 32/64bit integer, XMM, YMM or ZMM
6130 register. It is encoded in VEX prefix. We need to
6131 clear RegMem bit before calling operand_type_equal. */
6133 i386_operand_type op
;
6136 /* Check register-only source operand when two source
6137 operands are swapped. */
6138 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6139 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6147 op
= i
.tm
.operand_types
[vvvv
];
6148 op
.bitfield
.regmem
= 0;
6149 if ((dest
+ 1) >= i
.operands
6150 || (!op
.bitfield
.reg32
6151 && op
.bitfield
.reg64
6152 && !operand_type_equal (&op
, ®xmm
)
6153 && !operand_type_equal (&op
, ®ymm
)
6154 && !operand_type_equal (&op
, ®zmm
)
6155 && !operand_type_equal (&op
, ®mask
)))
6157 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6163 /* One of the register operands will be encoded in the i.tm.reg
6164 field, the other in the combined i.tm.mode and i.tm.regmem
6165 fields. If no form of this instruction supports a memory
6166 destination operand, then we assume the source operand may
6167 sometimes be a memory operand and so we need to store the
6168 destination in the i.rm.reg field. */
6169 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6170 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6172 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6173 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6174 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6176 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6178 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6180 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6185 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6186 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6187 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6189 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6191 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6193 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6196 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6198 if (!i
.types
[0].bitfield
.control
6199 && !i
.types
[1].bitfield
.control
)
6201 i
.rex
&= ~(REX_R
| REX_B
);
6202 add_prefix (LOCK_PREFIX_OPCODE
);
6206 { /* If it's not 2 reg operands... */
6211 unsigned int fake_zero_displacement
= 0;
6214 for (op
= 0; op
< i
.operands
; op
++)
6215 if (operand_type_check (i
.types
[op
], anymem
))
6217 gas_assert (op
< i
.operands
);
6219 if (i
.tm
.opcode_modifier
.vecsib
)
6221 if (i
.index_reg
->reg_num
== RegEiz
6222 || i
.index_reg
->reg_num
== RegRiz
)
6225 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6228 i
.sib
.base
= NO_BASE_REGISTER
;
6229 i
.sib
.scale
= i
.log2_scale_factor
;
6230 /* No Vec_Disp8 if there is no base. */
6231 i
.types
[op
].bitfield
.vec_disp8
= 0;
6232 i
.types
[op
].bitfield
.disp8
= 0;
6233 i
.types
[op
].bitfield
.disp16
= 0;
6234 i
.types
[op
].bitfield
.disp64
= 0;
6235 if (flag_code
!= CODE_64BIT
)
6237 /* Must be 32 bit */
6238 i
.types
[op
].bitfield
.disp32
= 1;
6239 i
.types
[op
].bitfield
.disp32s
= 0;
6243 i
.types
[op
].bitfield
.disp32
= 0;
6244 i
.types
[op
].bitfield
.disp32s
= 1;
6247 i
.sib
.index
= i
.index_reg
->reg_num
;
6248 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6250 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6256 if (i
.base_reg
== 0)
6259 if (!i
.disp_operands
)
6261 fake_zero_displacement
= 1;
6262 /* Instructions with VSIB byte need 32bit displacement
6263 if there is no base register. */
6264 if (i
.tm
.opcode_modifier
.vecsib
)
6265 i
.types
[op
].bitfield
.disp32
= 1;
6267 if (i
.index_reg
== 0)
6269 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6270 /* Operand is just <disp> */
6271 if (flag_code
== CODE_64BIT
)
6273 /* 64bit mode overwrites the 32bit absolute
6274 addressing by RIP relative addressing and
6275 absolute addressing is encoded by one of the
6276 redundant SIB forms. */
6277 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6278 i
.sib
.base
= NO_BASE_REGISTER
;
6279 i
.sib
.index
= NO_INDEX_REGISTER
;
6280 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6281 ? disp32s
: disp32
);
6283 else if ((flag_code
== CODE_16BIT
)
6284 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6286 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6287 i
.types
[op
] = disp16
;
6291 i
.rm
.regmem
= NO_BASE_REGISTER
;
6292 i
.types
[op
] = disp32
;
6295 else if (!i
.tm
.opcode_modifier
.vecsib
)
6297 /* !i.base_reg && i.index_reg */
6298 if (i
.index_reg
->reg_num
== RegEiz
6299 || i
.index_reg
->reg_num
== RegRiz
)
6300 i
.sib
.index
= NO_INDEX_REGISTER
;
6302 i
.sib
.index
= i
.index_reg
->reg_num
;
6303 i
.sib
.base
= NO_BASE_REGISTER
;
6304 i
.sib
.scale
= i
.log2_scale_factor
;
6305 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6306 /* No Vec_Disp8 if there is no base. */
6307 i
.types
[op
].bitfield
.vec_disp8
= 0;
6308 i
.types
[op
].bitfield
.disp8
= 0;
6309 i
.types
[op
].bitfield
.disp16
= 0;
6310 i
.types
[op
].bitfield
.disp64
= 0;
6311 if (flag_code
!= CODE_64BIT
)
6313 /* Must be 32 bit */
6314 i
.types
[op
].bitfield
.disp32
= 1;
6315 i
.types
[op
].bitfield
.disp32s
= 0;
6319 i
.types
[op
].bitfield
.disp32
= 0;
6320 i
.types
[op
].bitfield
.disp32s
= 1;
6322 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6326 /* RIP addressing for 64bit mode. */
6327 else if (i
.base_reg
->reg_num
== RegRip
||
6328 i
.base_reg
->reg_num
== RegEip
)
6330 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6331 i
.rm
.regmem
= NO_BASE_REGISTER
;
6332 i
.types
[op
].bitfield
.disp8
= 0;
6333 i
.types
[op
].bitfield
.disp16
= 0;
6334 i
.types
[op
].bitfield
.disp32
= 0;
6335 i
.types
[op
].bitfield
.disp32s
= 1;
6336 i
.types
[op
].bitfield
.disp64
= 0;
6337 i
.types
[op
].bitfield
.vec_disp8
= 0;
6338 i
.flags
[op
] |= Operand_PCrel
;
6339 if (! i
.disp_operands
)
6340 fake_zero_displacement
= 1;
6342 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6344 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6345 switch (i
.base_reg
->reg_num
)
6348 if (i
.index_reg
== 0)
6350 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6351 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6355 if (i
.index_reg
== 0)
6358 if (operand_type_check (i
.types
[op
], disp
) == 0)
6360 /* fake (%bp) into 0(%bp) */
6361 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6362 i
.types
[op
].bitfield
.vec_disp8
= 1;
6364 i
.types
[op
].bitfield
.disp8
= 1;
6365 fake_zero_displacement
= 1;
6368 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6369 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6371 default: /* (%si) -> 4 or (%di) -> 5 */
6372 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6374 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6376 else /* i.base_reg and 32/64 bit mode */
6378 if (flag_code
== CODE_64BIT
6379 && operand_type_check (i
.types
[op
], disp
))
6381 i386_operand_type temp
;
6382 operand_type_set (&temp
, 0);
6383 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6384 temp
.bitfield
.vec_disp8
6385 = i
.types
[op
].bitfield
.vec_disp8
;
6387 if (i
.prefix
[ADDR_PREFIX
] == 0)
6388 i
.types
[op
].bitfield
.disp32s
= 1;
6390 i
.types
[op
].bitfield
.disp32
= 1;
6393 if (!i
.tm
.opcode_modifier
.vecsib
)
6394 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6395 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6397 i
.sib
.base
= i
.base_reg
->reg_num
;
6398 /* x86-64 ignores REX prefix bit here to avoid decoder
6400 if (!(i
.base_reg
->reg_flags
& RegRex
)
6401 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6402 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6404 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6406 fake_zero_displacement
= 1;
6407 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6408 i
.types
[op
].bitfield
.vec_disp8
= 1;
6410 i
.types
[op
].bitfield
.disp8
= 1;
6412 i
.sib
.scale
= i
.log2_scale_factor
;
6413 if (i
.index_reg
== 0)
6415 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6416 /* <disp>(%esp) becomes two byte modrm with no index
6417 register. We've already stored the code for esp
6418 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6419 Any base register besides %esp will not use the
6420 extra modrm byte. */
6421 i
.sib
.index
= NO_INDEX_REGISTER
;
6423 else if (!i
.tm
.opcode_modifier
.vecsib
)
6425 if (i
.index_reg
->reg_num
== RegEiz
6426 || i
.index_reg
->reg_num
== RegRiz
)
6427 i
.sib
.index
= NO_INDEX_REGISTER
;
6429 i
.sib
.index
= i
.index_reg
->reg_num
;
6430 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6431 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6436 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6437 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6441 if (!fake_zero_displacement
6445 fake_zero_displacement
= 1;
6446 if (i
.disp_encoding
== disp_encoding_8bit
)
6447 i
.types
[op
].bitfield
.disp8
= 1;
6449 i
.types
[op
].bitfield
.disp32
= 1;
6451 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6455 if (fake_zero_displacement
)
6457 /* Fakes a zero displacement assuming that i.types[op]
6458 holds the correct displacement size. */
6461 gas_assert (i
.op
[op
].disps
== 0);
6462 exp
= &disp_expressions
[i
.disp_operands
++];
6463 i
.op
[op
].disps
= exp
;
6464 exp
->X_op
= O_constant
;
6465 exp
->X_add_number
= 0;
6466 exp
->X_add_symbol
= (symbolS
*) 0;
6467 exp
->X_op_symbol
= (symbolS
*) 0;
6475 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6477 if (operand_type_check (i
.types
[0], imm
))
6478 i
.vex
.register_specifier
= NULL
;
6481 /* VEX.vvvv encodes one of the sources when the first
6482 operand is not an immediate. */
6483 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6484 i
.vex
.register_specifier
= i
.op
[0].regs
;
6486 i
.vex
.register_specifier
= i
.op
[1].regs
;
6489 /* Destination is a XMM register encoded in the ModRM.reg
6491 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6492 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6495 /* ModRM.rm and VEX.B encodes the other source. */
6496 if (!i
.mem_operands
)
6500 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6501 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6503 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6505 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6509 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6511 i
.vex
.register_specifier
= i
.op
[2].regs
;
6512 if (!i
.mem_operands
)
6515 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6516 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6520 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6521 (if any) based on i.tm.extension_opcode. Again, we must be
6522 careful to make sure that segment/control/debug/test/MMX
6523 registers are coded into the i.rm.reg field. */
6524 else if (i
.reg_operands
)
6527 unsigned int vex_reg
= ~0;
6529 for (op
= 0; op
< i
.operands
; op
++)
6530 if (i
.types
[op
].bitfield
.reg8
6531 || i
.types
[op
].bitfield
.reg16
6532 || i
.types
[op
].bitfield
.reg32
6533 || i
.types
[op
].bitfield
.reg64
6534 || i
.types
[op
].bitfield
.regmmx
6535 || i
.types
[op
].bitfield
.regxmm
6536 || i
.types
[op
].bitfield
.regymm
6537 || i
.types
[op
].bitfield
.regbnd
6538 || i
.types
[op
].bitfield
.regzmm
6539 || i
.types
[op
].bitfield
.regmask
6540 || i
.types
[op
].bitfield
.sreg2
6541 || i
.types
[op
].bitfield
.sreg3
6542 || i
.types
[op
].bitfield
.control
6543 || i
.types
[op
].bitfield
.debug
6544 || i
.types
[op
].bitfield
.test
)
6549 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6551 /* For instructions with VexNDS, the register-only
6552 source operand is encoded in VEX prefix. */
6553 gas_assert (mem
!= (unsigned int) ~0);
6558 gas_assert (op
< i
.operands
);
6562 /* Check register-only source operand when two source
6563 operands are swapped. */
6564 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6565 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6569 gas_assert (mem
== (vex_reg
+ 1)
6570 && op
< i
.operands
);
6575 gas_assert (vex_reg
< i
.operands
);
6579 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6581 /* For instructions with VexNDD, the register destination
6582 is encoded in VEX prefix. */
6583 if (i
.mem_operands
== 0)
6585 /* There is no memory operand. */
6586 gas_assert ((op
+ 2) == i
.operands
);
6591 /* There are only 2 operands. */
6592 gas_assert (op
< 2 && i
.operands
== 2);
6597 gas_assert (op
< i
.operands
);
6599 if (vex_reg
!= (unsigned int) ~0)
6601 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6603 if (type
->bitfield
.reg32
!= 1
6604 && type
->bitfield
.reg64
!= 1
6605 && !operand_type_equal (type
, ®xmm
)
6606 && !operand_type_equal (type
, ®ymm
)
6607 && !operand_type_equal (type
, ®zmm
)
6608 && !operand_type_equal (type
, ®mask
))
6611 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6614 /* Don't set OP operand twice. */
6617 /* If there is an extension opcode to put here, the
6618 register number must be put into the regmem field. */
6619 if (i
.tm
.extension_opcode
!= None
)
6621 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6622 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6624 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6629 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6630 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6632 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6637 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6638 must set it to 3 to indicate this is a register operand
6639 in the regmem field. */
6640 if (!i
.mem_operands
)
6644 /* Fill in i.rm.reg field with extension opcode (if any). */
6645 if (i
.tm
.extension_opcode
!= None
)
6646 i
.rm
.reg
= i
.tm
.extension_opcode
;
6652 output_branch (void)
6658 relax_substateT subtype
;
6662 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6663 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6666 if (i
.prefix
[DATA_PREFIX
] != 0)
6672 /* Pentium4 branch hints. */
6673 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6674 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6679 if (i
.prefix
[REX_PREFIX
] != 0)
6685 /* BND prefixed jump. */
6686 if (i
.prefix
[BND_PREFIX
] != 0)
6688 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6692 if (i
.prefixes
!= 0 && !intel_syntax
)
6693 as_warn (_("skipping prefixes on this instruction"));
6695 /* It's always a symbol; End frag & setup for relax.
6696 Make sure there is enough room in this frag for the largest
6697 instruction we may generate in md_convert_frag. This is 2
6698 bytes for the opcode and room for the prefix and largest
6700 frag_grow (prefix
+ 2 + 4);
6701 /* Prefix and 1 opcode byte go in fr_fix. */
6702 p
= frag_more (prefix
+ 1);
6703 if (i
.prefix
[DATA_PREFIX
] != 0)
6704 *p
++ = DATA_PREFIX_OPCODE
;
6705 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6706 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6707 *p
++ = i
.prefix
[SEG_PREFIX
];
6708 if (i
.prefix
[REX_PREFIX
] != 0)
6709 *p
++ = i
.prefix
[REX_PREFIX
];
6710 *p
= i
.tm
.base_opcode
;
6712 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6713 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6714 else if (cpu_arch_flags
.bitfield
.cpui386
)
6715 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6717 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6720 sym
= i
.op
[0].disps
->X_add_symbol
;
6721 off
= i
.op
[0].disps
->X_add_number
;
6723 if (i
.op
[0].disps
->X_op
!= O_constant
6724 && i
.op
[0].disps
->X_op
!= O_symbol
)
6726 /* Handle complex expressions. */
6727 sym
= make_expr_symbol (i
.op
[0].disps
);
6731 /* 1 possible extra opcode + 4 byte displacement go in var part.
6732 Pass reloc in fr_var. */
6733 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6743 if (i
.tm
.opcode_modifier
.jumpbyte
)
6745 /* This is a loop or jecxz type instruction. */
6747 if (i
.prefix
[ADDR_PREFIX
] != 0)
6749 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6752 /* Pentium4 branch hints. */
6753 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6754 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6756 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6765 if (flag_code
== CODE_16BIT
)
6768 if (i
.prefix
[DATA_PREFIX
] != 0)
6770 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6780 if (i
.prefix
[REX_PREFIX
] != 0)
6782 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6786 /* BND prefixed jump. */
6787 if (i
.prefix
[BND_PREFIX
] != 0)
6789 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6793 if (i
.prefixes
!= 0 && !intel_syntax
)
6794 as_warn (_("skipping prefixes on this instruction"));
6796 p
= frag_more (i
.tm
.opcode_length
+ size
);
6797 switch (i
.tm
.opcode_length
)
6800 *p
++ = i
.tm
.base_opcode
>> 8;
6802 *p
++ = i
.tm
.base_opcode
;
6808 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6809 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6811 /* All jumps handled here are signed, but don't use a signed limit
6812 check for 32 and 16 bit jumps as we want to allow wrap around at
6813 4G and 64k respectively. */
6815 fixP
->fx_signed
= 1;
6819 output_interseg_jump (void)
6827 if (flag_code
== CODE_16BIT
)
6831 if (i
.prefix
[DATA_PREFIX
] != 0)
6837 if (i
.prefix
[REX_PREFIX
] != 0)
6847 if (i
.prefixes
!= 0 && !intel_syntax
)
6848 as_warn (_("skipping prefixes on this instruction"));
6850 /* 1 opcode; 2 segment; offset */
6851 p
= frag_more (prefix
+ 1 + 2 + size
);
6853 if (i
.prefix
[DATA_PREFIX
] != 0)
6854 *p
++ = DATA_PREFIX_OPCODE
;
6856 if (i
.prefix
[REX_PREFIX
] != 0)
6857 *p
++ = i
.prefix
[REX_PREFIX
];
6859 *p
++ = i
.tm
.base_opcode
;
6860 if (i
.op
[1].imms
->X_op
== O_constant
)
6862 offsetT n
= i
.op
[1].imms
->X_add_number
;
6865 && !fits_in_unsigned_word (n
)
6866 && !fits_in_signed_word (n
))
6868 as_bad (_("16-bit jump out of range"));
6871 md_number_to_chars (p
, n
, size
);
6874 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6875 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6876 if (i
.op
[0].imms
->X_op
!= O_constant
)
6877 as_bad (_("can't handle non absolute segment in `%s'"),
6879 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6885 fragS
*insn_start_frag
;
6886 offsetT insn_start_off
;
6888 /* Tie dwarf2 debug info to the address at the start of the insn.
6889 We can't do this after the insn has been output as the current
6890 frag may have been closed off. eg. by frag_var. */
6891 dwarf2_emit_insn (0);
6893 insn_start_frag
= frag_now
;
6894 insn_start_off
= frag_now_fix ();
6897 if (i
.tm
.opcode_modifier
.jump
)
6899 else if (i
.tm
.opcode_modifier
.jumpbyte
6900 || i
.tm
.opcode_modifier
.jumpdword
)
6902 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6903 output_interseg_jump ();
6906 /* Output normal instructions here. */
6910 unsigned int prefix
;
6912 /* Some processors fail on LOCK prefix. This options makes
6913 assembler ignore LOCK prefix and serves as a workaround. */
6914 if (omit_lock_prefix
)
6916 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6918 i
.prefix
[LOCK_PREFIX
] = 0;
6921 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6922 don't need the explicit prefix. */
6923 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6925 switch (i
.tm
.opcode_length
)
6928 if (i
.tm
.base_opcode
& 0xff000000)
6930 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6935 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6937 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6938 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6941 if (prefix
!= REPE_PREFIX_OPCODE
6942 || (i
.prefix
[REP_PREFIX
]
6943 != REPE_PREFIX_OPCODE
))
6944 add_prefix (prefix
);
6947 add_prefix (prefix
);
6956 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6957 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6958 R_X86_64_GOTTPOFF relocation so that linker can safely
6959 perform IE->LE optimization. */
6960 if (x86_elf_abi
== X86_64_X32_ABI
6962 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6963 && i
.prefix
[REX_PREFIX
] == 0)
6964 add_prefix (REX_OPCODE
);
6967 /* The prefix bytes. */
6968 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6970 FRAG_APPEND_1_CHAR (*q
);
6974 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6979 /* REX byte is encoded in VEX prefix. */
6983 FRAG_APPEND_1_CHAR (*q
);
6986 /* There should be no other prefixes for instructions
6991 /* For EVEX instructions i.vrex should become 0 after
6992 build_evex_prefix. For VEX instructions upper 16 registers
6993 aren't available, so VREX should be 0. */
6996 /* Now the VEX prefix. */
6997 p
= frag_more (i
.vex
.length
);
6998 for (j
= 0; j
< i
.vex
.length
; j
++)
6999 p
[j
] = i
.vex
.bytes
[j
];
7002 /* Now the opcode; be careful about word order here! */
7003 if (i
.tm
.opcode_length
== 1)
7005 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7009 switch (i
.tm
.opcode_length
)
7013 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7014 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7018 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7028 /* Put out high byte first: can't use md_number_to_chars! */
7029 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7030 *p
= i
.tm
.base_opcode
& 0xff;
7033 /* Now the modrm byte and sib byte (if present). */
7034 if (i
.tm
.opcode_modifier
.modrm
)
7036 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7039 /* If i.rm.regmem == ESP (4)
7040 && i.rm.mode != (Register mode)
7042 ==> need second modrm byte. */
7043 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7045 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7046 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7048 | i
.sib
.scale
<< 6));
7051 if (i
.disp_operands
)
7052 output_disp (insn_start_frag
, insn_start_off
);
7055 output_imm (insn_start_frag
, insn_start_off
);
7061 pi ("" /*line*/, &i
);
7063 #endif /* DEBUG386 */
7066 /* Return the size of the displacement operand N. */
7069 disp_size (unsigned int n
)
7073 /* Vec_Disp8 has to be 8bit. */
7074 if (i
.types
[n
].bitfield
.vec_disp8
)
7076 else if (i
.types
[n
].bitfield
.disp64
)
7078 else if (i
.types
[n
].bitfield
.disp8
)
7080 else if (i
.types
[n
].bitfield
.disp16
)
7085 /* Return the size of the immediate operand N. */
7088 imm_size (unsigned int n
)
7091 if (i
.types
[n
].bitfield
.imm64
)
7093 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7095 else if (i
.types
[n
].bitfield
.imm16
)
7101 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7106 for (n
= 0; n
< i
.operands
; n
++)
7108 if (i
.types
[n
].bitfield
.vec_disp8
7109 || operand_type_check (i
.types
[n
], disp
))
7111 if (i
.op
[n
].disps
->X_op
== O_constant
)
7113 int size
= disp_size (n
);
7114 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7116 if (i
.types
[n
].bitfield
.vec_disp8
)
7118 val
= offset_in_range (val
, size
);
7119 p
= frag_more (size
);
7120 md_number_to_chars (p
, val
, size
);
7124 enum bfd_reloc_code_real reloc_type
;
7125 int size
= disp_size (n
);
7126 int sign
= i
.types
[n
].bitfield
.disp32s
;
7127 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7129 /* We can't have 8 bit displacement here. */
7130 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7132 /* The PC relative address is computed relative
7133 to the instruction boundary, so in case immediate
7134 fields follows, we need to adjust the value. */
7135 if (pcrel
&& i
.imm_operands
)
7140 for (n1
= 0; n1
< i
.operands
; n1
++)
7141 if (operand_type_check (i
.types
[n1
], imm
))
7143 /* Only one immediate is allowed for PC
7144 relative address. */
7145 gas_assert (sz
== 0);
7147 i
.op
[n
].disps
->X_add_number
-= sz
;
7149 /* We should find the immediate. */
7150 gas_assert (sz
!= 0);
7153 p
= frag_more (size
);
7154 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7156 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7157 && (((reloc_type
== BFD_RELOC_32
7158 || reloc_type
== BFD_RELOC_X86_64_32S
7159 || (reloc_type
== BFD_RELOC_64
7161 && (i
.op
[n
].disps
->X_op
== O_symbol
7162 || (i
.op
[n
].disps
->X_op
== O_add
7163 && ((symbol_get_value_expression
7164 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7166 || reloc_type
== BFD_RELOC_32_PCREL
))
7170 if (insn_start_frag
== frag_now
)
7171 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7176 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7177 for (fr
= insn_start_frag
->fr_next
;
7178 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7180 add
+= p
- frag_now
->fr_literal
;
7185 reloc_type
= BFD_RELOC_386_GOTPC
;
7186 i
.op
[n
].imms
->X_add_number
+= add
;
7188 else if (reloc_type
== BFD_RELOC_64
)
7189 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7191 /* Don't do the adjustment for x86-64, as there
7192 the pcrel addressing is relative to the _next_
7193 insn, and that is taken care of in other code. */
7194 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7196 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7197 i
.op
[n
].disps
, pcrel
, reloc_type
);
7204 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7209 for (n
= 0; n
< i
.operands
; n
++)
7211 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7212 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7215 if (operand_type_check (i
.types
[n
], imm
))
7217 if (i
.op
[n
].imms
->X_op
== O_constant
)
7219 int size
= imm_size (n
);
7222 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7224 p
= frag_more (size
);
7225 md_number_to_chars (p
, val
, size
);
7229 /* Not absolute_section.
7230 Need a 32-bit fixup (don't support 8bit
7231 non-absolute imms). Try to support other
7233 enum bfd_reloc_code_real reloc_type
;
7234 int size
= imm_size (n
);
7237 if (i
.types
[n
].bitfield
.imm32s
7238 && (i
.suffix
== QWORD_MNEM_SUFFIX
7239 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7244 p
= frag_more (size
);
7245 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7247 /* This is tough to explain. We end up with this one if we
7248 * have operands that look like
7249 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7250 * obtain the absolute address of the GOT, and it is strongly
7251 * preferable from a performance point of view to avoid using
7252 * a runtime relocation for this. The actual sequence of
7253 * instructions often look something like:
7258 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7260 * The call and pop essentially return the absolute address
7261 * of the label .L66 and store it in %ebx. The linker itself
7262 * will ultimately change the first operand of the addl so
7263 * that %ebx points to the GOT, but to keep things simple, the
7264 * .o file must have this operand set so that it generates not
7265 * the absolute address of .L66, but the absolute address of
7266 * itself. This allows the linker itself simply treat a GOTPC
7267 * relocation as asking for a pcrel offset to the GOT to be
7268 * added in, and the addend of the relocation is stored in the
7269 * operand field for the instruction itself.
7271 * Our job here is to fix the operand so that it would add
7272 * the correct offset so that %ebx would point to itself. The
7273 * thing that is tricky is that .-.L66 will point to the
7274 * beginning of the instruction, so we need to further modify
7275 * the operand so that it will point to itself. There are
7276 * other cases where you have something like:
7278 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7280 * and here no correction would be required. Internally in
7281 * the assembler we treat operands of this form as not being
7282 * pcrel since the '.' is explicitly mentioned, and I wonder
7283 * whether it would simplify matters to do it this way. Who
7284 * knows. In earlier versions of the PIC patches, the
7285 * pcrel_adjust field was used to store the correction, but
7286 * since the expression is not pcrel, I felt it would be
7287 * confusing to do it this way. */
7289 if ((reloc_type
== BFD_RELOC_32
7290 || reloc_type
== BFD_RELOC_X86_64_32S
7291 || reloc_type
== BFD_RELOC_64
)
7293 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7294 && (i
.op
[n
].imms
->X_op
== O_symbol
7295 || (i
.op
[n
].imms
->X_op
== O_add
7296 && ((symbol_get_value_expression
7297 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7302 if (insn_start_frag
== frag_now
)
7303 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7308 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7309 for (fr
= insn_start_frag
->fr_next
;
7310 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7312 add
+= p
- frag_now
->fr_literal
;
7316 reloc_type
= BFD_RELOC_386_GOTPC
;
7318 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7320 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7321 i
.op
[n
].imms
->X_add_number
+= add
;
7323 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7324 i
.op
[n
].imms
, 0, reloc_type
);
7330 /* x86_cons_fix_new is called via the expression parsing code when a
7331 reloc is needed. We use this hook to get the correct .got reloc. */
7332 static int cons_sign
= -1;
7335 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7336 expressionS
*exp
, bfd_reloc_code_real_type r
)
7338 r
= reloc (len
, 0, cons_sign
, r
);
7341 if (exp
->X_op
== O_secrel
)
7343 exp
->X_op
= O_symbol
;
7344 r
= BFD_RELOC_32_SECREL
;
7348 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7351 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7352 purpose of the `.dc.a' internal pseudo-op. */
7355 x86_address_bytes (void)
7357 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7359 return stdoutput
->arch_info
->bits_per_address
/ 8;
7362 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7364 # define lex_got(reloc, adjust, types) NULL
7366 /* Parse operands of the form
7367 <symbol>@GOTOFF+<nnn>
7368 and similar .plt or .got references.
7370 If we find one, set up the correct relocation in RELOC and copy the
7371 input string, minus the `@GOTOFF' into a malloc'd buffer for
7372 parsing by the calling routine. Return this buffer, and if ADJUST
7373 is non-null set it to the length of the string we removed from the
7374 input line. Otherwise return NULL. */
7376 lex_got (enum bfd_reloc_code_real
*rel
,
7378 i386_operand_type
*types
)
7380 /* Some of the relocations depend on the size of what field is to
7381 be relocated. But in our callers i386_immediate and i386_displacement
7382 we don't yet know the operand size (this will be set by insn
7383 matching). Hence we record the word32 relocation here,
7384 and adjust the reloc according to the real size in reloc(). */
7385 static const struct {
7388 const enum bfd_reloc_code_real rel
[2];
7389 const i386_operand_type types64
;
7391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7392 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7394 OPERAND_TYPE_IMM32_64
},
7396 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7397 BFD_RELOC_X86_64_PLTOFF64
},
7398 OPERAND_TYPE_IMM64
},
7399 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7400 BFD_RELOC_X86_64_PLT32
},
7401 OPERAND_TYPE_IMM32_32S_DISP32
},
7402 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7403 BFD_RELOC_X86_64_GOTPLT64
},
7404 OPERAND_TYPE_IMM64_DISP64
},
7405 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7406 BFD_RELOC_X86_64_GOTOFF64
},
7407 OPERAND_TYPE_IMM64_DISP64
},
7408 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7409 BFD_RELOC_X86_64_GOTPCREL
},
7410 OPERAND_TYPE_IMM32_32S_DISP32
},
7411 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7412 BFD_RELOC_X86_64_TLSGD
},
7413 OPERAND_TYPE_IMM32_32S_DISP32
},
7414 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7415 _dummy_first_bfd_reloc_code_real
},
7416 OPERAND_TYPE_NONE
},
7417 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7418 BFD_RELOC_X86_64_TLSLD
},
7419 OPERAND_TYPE_IMM32_32S_DISP32
},
7420 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7421 BFD_RELOC_X86_64_GOTTPOFF
},
7422 OPERAND_TYPE_IMM32_32S_DISP32
},
7423 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7424 BFD_RELOC_X86_64_TPOFF32
},
7425 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7426 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7427 _dummy_first_bfd_reloc_code_real
},
7428 OPERAND_TYPE_NONE
},
7429 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7430 BFD_RELOC_X86_64_DTPOFF32
},
7431 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7432 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7433 _dummy_first_bfd_reloc_code_real
},
7434 OPERAND_TYPE_NONE
},
7435 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7436 _dummy_first_bfd_reloc_code_real
},
7437 OPERAND_TYPE_NONE
},
7438 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7439 BFD_RELOC_X86_64_GOT32
},
7440 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7441 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7442 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7443 OPERAND_TYPE_IMM32_32S_DISP32
},
7444 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7445 BFD_RELOC_X86_64_TLSDESC_CALL
},
7446 OPERAND_TYPE_IMM32_32S_DISP32
},
7451 #if defined (OBJ_MAYBE_ELF)
7456 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7457 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7460 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7462 int len
= gotrel
[j
].len
;
7463 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7465 if (gotrel
[j
].rel
[object_64bit
] != 0)
7468 char *tmpbuf
, *past_reloc
;
7470 *rel
= gotrel
[j
].rel
[object_64bit
];
7474 if (flag_code
!= CODE_64BIT
)
7476 types
->bitfield
.imm32
= 1;
7477 types
->bitfield
.disp32
= 1;
7480 *types
= gotrel
[j
].types64
;
7483 if (j
!= 0 && GOT_symbol
== NULL
)
7484 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7486 /* The length of the first part of our input line. */
7487 first
= cp
- input_line_pointer
;
7489 /* The second part goes from after the reloc token until
7490 (and including) an end_of_line char or comma. */
7491 past_reloc
= cp
+ 1 + len
;
7493 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7495 second
= cp
+ 1 - past_reloc
;
7497 /* Allocate and copy string. The trailing NUL shouldn't
7498 be necessary, but be safe. */
7499 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7500 memcpy (tmpbuf
, input_line_pointer
, first
);
7501 if (second
!= 0 && *past_reloc
!= ' ')
7502 /* Replace the relocation token with ' ', so that
7503 errors like foo@GOTOFF1 will be detected. */
7504 tmpbuf
[first
++] = ' ';
7506 /* Increment length by 1 if the relocation token is
7511 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7512 tmpbuf
[first
+ second
] = '\0';
7516 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7517 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7522 /* Might be a symbol version string. Don't as_bad here. */
7531 /* Parse operands of the form
7532 <symbol>@SECREL32+<nnn>
7534 If we find one, set up the correct relocation in RELOC and copy the
7535 input string, minus the `@SECREL32' into a malloc'd buffer for
7536 parsing by the calling routine. Return this buffer, and if ADJUST
7537 is non-null set it to the length of the string we removed from the
7538 input line. Otherwise return NULL.
7540 This function is copied from the ELF version above adjusted for PE targets. */
7543 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7544 int *adjust ATTRIBUTE_UNUSED
,
7545 i386_operand_type
*types
)
7551 const enum bfd_reloc_code_real rel
[2];
7552 const i386_operand_type types64
;
7556 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7557 BFD_RELOC_32_SECREL
},
7558 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7564 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7565 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7568 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7570 int len
= gotrel
[j
].len
;
7572 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7574 if (gotrel
[j
].rel
[object_64bit
] != 0)
7577 char *tmpbuf
, *past_reloc
;
7579 *rel
= gotrel
[j
].rel
[object_64bit
];
7585 if (flag_code
!= CODE_64BIT
)
7587 types
->bitfield
.imm32
= 1;
7588 types
->bitfield
.disp32
= 1;
7591 *types
= gotrel
[j
].types64
;
7594 /* The length of the first part of our input line. */
7595 first
= cp
- input_line_pointer
;
7597 /* The second part goes from after the reloc token until
7598 (and including) an end_of_line char or comma. */
7599 past_reloc
= cp
+ 1 + len
;
7601 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7603 second
= cp
+ 1 - past_reloc
;
7605 /* Allocate and copy string. The trailing NUL shouldn't
7606 be necessary, but be safe. */
7607 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7608 memcpy (tmpbuf
, input_line_pointer
, first
);
7609 if (second
!= 0 && *past_reloc
!= ' ')
7610 /* Replace the relocation token with ' ', so that
7611 errors like foo@SECLREL321 will be detected. */
7612 tmpbuf
[first
++] = ' ';
7613 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7614 tmpbuf
[first
+ second
] = '\0';
7618 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7619 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7624 /* Might be a symbol version string. Don't as_bad here. */
7630 bfd_reloc_code_real_type
7631 x86_cons (expressionS
*exp
, int size
)
7633 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7635 intel_syntax
= -intel_syntax
;
7638 if (size
== 4 || (object_64bit
&& size
== 8))
7640 /* Handle @GOTOFF and the like in an expression. */
7642 char *gotfree_input_line
;
7645 save
= input_line_pointer
;
7646 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7647 if (gotfree_input_line
)
7648 input_line_pointer
= gotfree_input_line
;
7652 if (gotfree_input_line
)
7654 /* expression () has merrily parsed up to the end of line,
7655 or a comma - in the wrong buffer. Transfer how far
7656 input_line_pointer has moved to the right buffer. */
7657 input_line_pointer
= (save
7658 + (input_line_pointer
- gotfree_input_line
)
7660 free (gotfree_input_line
);
7661 if (exp
->X_op
== O_constant
7662 || exp
->X_op
== O_absent
7663 || exp
->X_op
== O_illegal
7664 || exp
->X_op
== O_register
7665 || exp
->X_op
== O_big
)
7667 char c
= *input_line_pointer
;
7668 *input_line_pointer
= 0;
7669 as_bad (_("missing or invalid expression `%s'"), save
);
7670 *input_line_pointer
= c
;
7677 intel_syntax
= -intel_syntax
;
7680 i386_intel_simplify (exp
);
7686 signed_cons (int size
)
7688 if (flag_code
== CODE_64BIT
)
7696 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7703 if (exp
.X_op
== O_symbol
)
7704 exp
.X_op
= O_secrel
;
7706 emit_expr (&exp
, 4);
7708 while (*input_line_pointer
++ == ',');
7710 input_line_pointer
--;
7711 demand_empty_rest_of_line ();
7715 /* Handle Vector operations. */
7718 check_VecOperations (char *op_string
, char *op_end
)
7720 const reg_entry
*mask
;
7725 && (op_end
== NULL
|| op_string
< op_end
))
7728 if (*op_string
== '{')
7732 /* Check broadcasts. */
7733 if (strncmp (op_string
, "1to", 3) == 0)
7738 goto duplicated_vec_op
;
7741 if (*op_string
== '8')
7742 bcst_type
= BROADCAST_1TO8
;
7743 else if (*op_string
== '4')
7744 bcst_type
= BROADCAST_1TO4
;
7745 else if (*op_string
== '2')
7746 bcst_type
= BROADCAST_1TO2
;
7747 else if (*op_string
== '1'
7748 && *(op_string
+1) == '6')
7750 bcst_type
= BROADCAST_1TO16
;
7755 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7760 broadcast_op
.type
= bcst_type
;
7761 broadcast_op
.operand
= this_operand
;
7762 i
.broadcast
= &broadcast_op
;
7764 /* Check masking operation. */
7765 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7767 /* k0 can't be used for write mask. */
7768 if (mask
->reg_num
== 0)
7770 as_bad (_("`%s' can't be used for write mask"),
7777 mask_op
.mask
= mask
;
7778 mask_op
.zeroing
= 0;
7779 mask_op
.operand
= this_operand
;
7785 goto duplicated_vec_op
;
7787 i
.mask
->mask
= mask
;
7789 /* Only "{z}" is allowed here. No need to check
7790 zeroing mask explicitly. */
7791 if (i
.mask
->operand
!= this_operand
)
7793 as_bad (_("invalid write mask `%s'"), saved
);
7800 /* Check zeroing-flag for masking operation. */
7801 else if (*op_string
== 'z')
7805 mask_op
.mask
= NULL
;
7806 mask_op
.zeroing
= 1;
7807 mask_op
.operand
= this_operand
;
7812 if (i
.mask
->zeroing
)
7815 as_bad (_("duplicated `%s'"), saved
);
7819 i
.mask
->zeroing
= 1;
7821 /* Only "{%k}" is allowed here. No need to check mask
7822 register explicitly. */
7823 if (i
.mask
->operand
!= this_operand
)
7825 as_bad (_("invalid zeroing-masking `%s'"),
7834 goto unknown_vec_op
;
7836 if (*op_string
!= '}')
7838 as_bad (_("missing `}' in `%s'"), saved
);
7845 /* We don't know this one. */
7846 as_bad (_("unknown vector operation: `%s'"), saved
);
7854 i386_immediate (char *imm_start
)
7856 char *save_input_line_pointer
;
7857 char *gotfree_input_line
;
7860 i386_operand_type types
;
7862 operand_type_set (&types
, ~0);
7864 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7866 as_bad (_("at most %d immediate operands are allowed"),
7867 MAX_IMMEDIATE_OPERANDS
);
7871 exp
= &im_expressions
[i
.imm_operands
++];
7872 i
.op
[this_operand
].imms
= exp
;
7874 if (is_space_char (*imm_start
))
7877 save_input_line_pointer
= input_line_pointer
;
7878 input_line_pointer
= imm_start
;
7880 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7881 if (gotfree_input_line
)
7882 input_line_pointer
= gotfree_input_line
;
7884 exp_seg
= expression (exp
);
7888 /* Handle vector operations. */
7889 if (*input_line_pointer
== '{')
7891 input_line_pointer
= check_VecOperations (input_line_pointer
,
7893 if (input_line_pointer
== NULL
)
7897 if (*input_line_pointer
)
7898 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7900 input_line_pointer
= save_input_line_pointer
;
7901 if (gotfree_input_line
)
7903 free (gotfree_input_line
);
7905 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7906 exp
->X_op
= O_illegal
;
7909 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7913 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7914 i386_operand_type types
, const char *imm_start
)
7916 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7919 as_bad (_("missing or invalid immediate expression `%s'"),
7923 else if (exp
->X_op
== O_constant
)
7925 /* Size it properly later. */
7926 i
.types
[this_operand
].bitfield
.imm64
= 1;
7927 /* If not 64bit, sign extend val. */
7928 if (flag_code
!= CODE_64BIT
7929 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7931 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7933 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7934 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7935 && exp_seg
!= absolute_section
7936 && exp_seg
!= text_section
7937 && exp_seg
!= data_section
7938 && exp_seg
!= bss_section
7939 && exp_seg
!= undefined_section
7940 && !bfd_is_com_section (exp_seg
))
7942 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7946 else if (!intel_syntax
&& exp_seg
== reg_section
)
7949 as_bad (_("illegal immediate register operand %s"), imm_start
);
7954 /* This is an address. The size of the address will be
7955 determined later, depending on destination register,
7956 suffix, or the default for the section. */
7957 i
.types
[this_operand
].bitfield
.imm8
= 1;
7958 i
.types
[this_operand
].bitfield
.imm16
= 1;
7959 i
.types
[this_operand
].bitfield
.imm32
= 1;
7960 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7961 i
.types
[this_operand
].bitfield
.imm64
= 1;
7962 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7970 i386_scale (char *scale
)
7973 char *save
= input_line_pointer
;
7975 input_line_pointer
= scale
;
7976 val
= get_absolute_expression ();
7981 i
.log2_scale_factor
= 0;
7984 i
.log2_scale_factor
= 1;
7987 i
.log2_scale_factor
= 2;
7990 i
.log2_scale_factor
= 3;
7994 char sep
= *input_line_pointer
;
7996 *input_line_pointer
= '\0';
7997 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7999 *input_line_pointer
= sep
;
8000 input_line_pointer
= save
;
8004 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8006 as_warn (_("scale factor of %d without an index register"),
8007 1 << i
.log2_scale_factor
);
8008 i
.log2_scale_factor
= 0;
8010 scale
= input_line_pointer
;
8011 input_line_pointer
= save
;
8016 i386_displacement (char *disp_start
, char *disp_end
)
8020 char *save_input_line_pointer
;
8021 char *gotfree_input_line
;
8023 i386_operand_type bigdisp
, types
= anydisp
;
8026 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8028 as_bad (_("at most %d displacement operands are allowed"),
8029 MAX_MEMORY_OPERANDS
);
8033 operand_type_set (&bigdisp
, 0);
8034 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8035 || (!current_templates
->start
->opcode_modifier
.jump
8036 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8038 bigdisp
.bitfield
.disp32
= 1;
8039 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8040 if (flag_code
== CODE_64BIT
)
8044 bigdisp
.bitfield
.disp32s
= 1;
8045 bigdisp
.bitfield
.disp64
= 1;
8048 else if ((flag_code
== CODE_16BIT
) ^ override
)
8050 bigdisp
.bitfield
.disp32
= 0;
8051 bigdisp
.bitfield
.disp16
= 1;
8056 /* For PC-relative branches, the width of the displacement
8057 is dependent upon data size, not address size. */
8058 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8059 if (flag_code
== CODE_64BIT
)
8061 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8062 bigdisp
.bitfield
.disp16
= 1;
8065 bigdisp
.bitfield
.disp32
= 1;
8066 bigdisp
.bitfield
.disp32s
= 1;
8072 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8074 : LONG_MNEM_SUFFIX
));
8075 bigdisp
.bitfield
.disp32
= 1;
8076 if ((flag_code
== CODE_16BIT
) ^ override
)
8078 bigdisp
.bitfield
.disp32
= 0;
8079 bigdisp
.bitfield
.disp16
= 1;
8083 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8086 exp
= &disp_expressions
[i
.disp_operands
];
8087 i
.op
[this_operand
].disps
= exp
;
8089 save_input_line_pointer
= input_line_pointer
;
8090 input_line_pointer
= disp_start
;
8091 END_STRING_AND_SAVE (disp_end
);
8093 #ifndef GCC_ASM_O_HACK
8094 #define GCC_ASM_O_HACK 0
8097 END_STRING_AND_SAVE (disp_end
+ 1);
8098 if (i
.types
[this_operand
].bitfield
.baseIndex
8099 && displacement_string_end
[-1] == '+')
8101 /* This hack is to avoid a warning when using the "o"
8102 constraint within gcc asm statements.
8105 #define _set_tssldt_desc(n,addr,limit,type) \
8106 __asm__ __volatile__ ( \
8108 "movw %w1,2+%0\n\t" \
8110 "movb %b1,4+%0\n\t" \
8111 "movb %4,5+%0\n\t" \
8112 "movb $0,6+%0\n\t" \
8113 "movb %h1,7+%0\n\t" \
8115 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8117 This works great except that the output assembler ends
8118 up looking a bit weird if it turns out that there is
8119 no offset. You end up producing code that looks like:
8132 So here we provide the missing zero. */
8134 *displacement_string_end
= '0';
8137 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8138 if (gotfree_input_line
)
8139 input_line_pointer
= gotfree_input_line
;
8141 exp_seg
= expression (exp
);
8144 if (*input_line_pointer
)
8145 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8147 RESTORE_END_STRING (disp_end
+ 1);
8149 input_line_pointer
= save_input_line_pointer
;
8150 if (gotfree_input_line
)
8152 free (gotfree_input_line
);
8154 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8155 exp
->X_op
= O_illegal
;
8158 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8160 RESTORE_END_STRING (disp_end
);
8166 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8167 i386_operand_type types
, const char *disp_start
)
8169 i386_operand_type bigdisp
;
8172 /* We do this to make sure that the section symbol is in
8173 the symbol table. We will ultimately change the relocation
8174 to be relative to the beginning of the section. */
8175 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8176 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8177 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8179 if (exp
->X_op
!= O_symbol
)
8182 if (S_IS_LOCAL (exp
->X_add_symbol
)
8183 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8184 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8185 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8186 exp
->X_op
= O_subtract
;
8187 exp
->X_op_symbol
= GOT_symbol
;
8188 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8189 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8190 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8191 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8193 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8196 else if (exp
->X_op
== O_absent
8197 || exp
->X_op
== O_illegal
8198 || exp
->X_op
== O_big
)
8201 as_bad (_("missing or invalid displacement expression `%s'"),
8206 else if (flag_code
== CODE_64BIT
8207 && !i
.prefix
[ADDR_PREFIX
]
8208 && exp
->X_op
== O_constant
)
8210 /* Since displacement is signed extended to 64bit, don't allow
8211 disp32 and turn off disp32s if they are out of range. */
8212 i
.types
[this_operand
].bitfield
.disp32
= 0;
8213 if (!fits_in_signed_long (exp
->X_add_number
))
8215 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8216 if (i
.types
[this_operand
].bitfield
.baseindex
)
8218 as_bad (_("0x%lx out range of signed 32bit displacement"),
8219 (long) exp
->X_add_number
);
8225 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8226 else if (exp
->X_op
!= O_constant
8227 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8228 && exp_seg
!= absolute_section
8229 && exp_seg
!= text_section
8230 && exp_seg
!= data_section
8231 && exp_seg
!= bss_section
8232 && exp_seg
!= undefined_section
8233 && !bfd_is_com_section (exp_seg
))
8235 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8240 /* Check if this is a displacement only operand. */
8241 bigdisp
= i
.types
[this_operand
];
8242 bigdisp
.bitfield
.disp8
= 0;
8243 bigdisp
.bitfield
.disp16
= 0;
8244 bigdisp
.bitfield
.disp32
= 0;
8245 bigdisp
.bitfield
.disp32s
= 0;
8246 bigdisp
.bitfield
.disp64
= 0;
8247 if (operand_type_all_zero (&bigdisp
))
8248 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8254 /* Make sure the memory operand we've been dealt is valid.
8255 Return 1 on success, 0 on a failure. */
8258 i386_index_check (const char *operand_string
)
8260 const char *kind
= "base/index";
8261 enum flag_code addr_mode
;
8263 if (i
.prefix
[ADDR_PREFIX
])
8264 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8267 addr_mode
= flag_code
;
8269 #if INFER_ADDR_PREFIX
8270 if (i
.mem_operands
== 0)
8272 /* Infer address prefix from the first memory operand. */
8273 const reg_entry
*addr_reg
= i
.base_reg
;
8275 if (addr_reg
== NULL
)
8276 addr_reg
= i
.index_reg
;
8280 if (addr_reg
->reg_num
== RegEip
8281 || addr_reg
->reg_num
== RegEiz
8282 || addr_reg
->reg_type
.bitfield
.reg32
)
8283 addr_mode
= CODE_32BIT
;
8284 else if (flag_code
!= CODE_64BIT
8285 && addr_reg
->reg_type
.bitfield
.reg16
)
8286 addr_mode
= CODE_16BIT
;
8288 if (addr_mode
!= flag_code
)
8290 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8292 /* Change the size of any displacement too. At most one
8293 of Disp16 or Disp32 is set.
8294 FIXME. There doesn't seem to be any real need for
8295 separate Disp16 and Disp32 flags. The same goes for
8296 Imm16 and Imm32. Removing them would probably clean
8297 up the code quite a lot. */
8298 if (flag_code
!= CODE_64BIT
8299 && (i
.types
[this_operand
].bitfield
.disp16
8300 || i
.types
[this_operand
].bitfield
.disp32
))
8301 i
.types
[this_operand
]
8302 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8309 if (current_templates
->start
->opcode_modifier
.isstring
8310 && !current_templates
->start
->opcode_modifier
.immext
8311 && (current_templates
->end
[-1].opcode_modifier
.isstring
8314 /* Memory operands of string insns are special in that they only allow
8315 a single register (rDI, rSI, or rBX) as their memory address. */
8316 const reg_entry
*expected_reg
;
8317 static const char *di_si
[][2] =
8323 static const char *bx
[] = { "ebx", "bx", "rbx" };
8325 kind
= "string address";
8327 if (current_templates
->start
->opcode_modifier
.w
)
8329 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8331 if (!type
.bitfield
.baseindex
8332 || ((!i
.mem_operands
!= !intel_syntax
)
8333 && current_templates
->end
[-1].operand_types
[1]
8334 .bitfield
.baseindex
))
8335 type
= current_templates
->end
[-1].operand_types
[1];
8336 expected_reg
= hash_find (reg_hash
,
8337 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8341 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8343 if (i
.base_reg
!= expected_reg
8345 || operand_type_check (i
.types
[this_operand
], disp
))
8347 /* The second memory operand must have the same size as
8351 && !((addr_mode
== CODE_64BIT
8352 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8353 || (addr_mode
== CODE_32BIT
8354 ? i
.base_reg
->reg_type
.bitfield
.reg32
8355 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8358 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8360 intel_syntax
? '[' : '(',
8362 expected_reg
->reg_name
,
8363 intel_syntax
? ']' : ')');
8370 as_bad (_("`%s' is not a valid %s expression"),
8371 operand_string
, kind
);
8376 if (addr_mode
!= CODE_16BIT
)
8378 /* 32-bit/64-bit checks. */
8380 && (addr_mode
== CODE_64BIT
8381 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8382 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8384 || (i
.base_reg
->reg_num
8385 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8387 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8388 && !i
.index_reg
->reg_type
.bitfield
.regymm
8389 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8390 && ((addr_mode
== CODE_64BIT
8391 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8392 || i
.index_reg
->reg_num
== RegRiz
)
8393 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8394 || i
.index_reg
->reg_num
== RegEiz
))
8395 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8400 /* 16-bit checks. */
8402 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8403 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8405 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8406 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8408 && i
.base_reg
->reg_num
< 6
8409 && i
.index_reg
->reg_num
>= 6
8410 && i
.log2_scale_factor
== 0))))
8417 /* Handle vector immediates. */
8420 RC_SAE_immediate (const char *imm_start
)
8422 unsigned int match_found
, j
;
8423 const char *pstr
= imm_start
;
8431 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8433 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8437 rc_op
.type
= RC_NamesTable
[j
].type
;
8438 rc_op
.operand
= this_operand
;
8439 i
.rounding
= &rc_op
;
8443 as_bad (_("duplicated `%s'"), imm_start
);
8446 pstr
+= RC_NamesTable
[j
].len
;
8456 as_bad (_("Missing '}': '%s'"), imm_start
);
8459 /* RC/SAE immediate string should contain nothing more. */;
8462 as_bad (_("Junk after '}': '%s'"), imm_start
);
8466 exp
= &im_expressions
[i
.imm_operands
++];
8467 i
.op
[this_operand
].imms
= exp
;
8469 exp
->X_op
= O_constant
;
8470 exp
->X_add_number
= 0;
8471 exp
->X_add_symbol
= (symbolS
*) 0;
8472 exp
->X_op_symbol
= (symbolS
*) 0;
8474 i
.types
[this_operand
].bitfield
.imm8
= 1;
8478 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8482 i386_att_operand (char *operand_string
)
8486 char *op_string
= operand_string
;
8488 if (is_space_char (*op_string
))
8491 /* We check for an absolute prefix (differentiating,
8492 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8493 if (*op_string
== ABSOLUTE_PREFIX
)
8496 if (is_space_char (*op_string
))
8498 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8501 /* Check if operand is a register. */
8502 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8504 i386_operand_type temp
;
8506 /* Check for a segment override by searching for ':' after a
8507 segment register. */
8509 if (is_space_char (*op_string
))
8511 if (*op_string
== ':'
8512 && (r
->reg_type
.bitfield
.sreg2
8513 || r
->reg_type
.bitfield
.sreg3
))
8518 i
.seg
[i
.mem_operands
] = &es
;
8521 i
.seg
[i
.mem_operands
] = &cs
;
8524 i
.seg
[i
.mem_operands
] = &ss
;
8527 i
.seg
[i
.mem_operands
] = &ds
;
8530 i
.seg
[i
.mem_operands
] = &fs
;
8533 i
.seg
[i
.mem_operands
] = &gs
;
8537 /* Skip the ':' and whitespace. */
8539 if (is_space_char (*op_string
))
8542 if (!is_digit_char (*op_string
)
8543 && !is_identifier_char (*op_string
)
8544 && *op_string
!= '('
8545 && *op_string
!= ABSOLUTE_PREFIX
)
8547 as_bad (_("bad memory operand `%s'"), op_string
);
8550 /* Handle case of %es:*foo. */
8551 if (*op_string
== ABSOLUTE_PREFIX
)
8554 if (is_space_char (*op_string
))
8556 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8558 goto do_memory_reference
;
8561 /* Handle vector operations. */
8562 if (*op_string
== '{')
8564 op_string
= check_VecOperations (op_string
, NULL
);
8565 if (op_string
== NULL
)
8571 as_bad (_("junk `%s' after register"), op_string
);
8575 temp
.bitfield
.baseindex
= 0;
8576 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8578 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8579 i
.op
[this_operand
].regs
= r
;
8582 else if (*op_string
== REGISTER_PREFIX
)
8584 as_bad (_("bad register name `%s'"), op_string
);
8587 else if (*op_string
== IMMEDIATE_PREFIX
)
8590 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8592 as_bad (_("immediate operand illegal with absolute jump"));
8595 if (!i386_immediate (op_string
))
8598 else if (RC_SAE_immediate (operand_string
))
8600 /* If it is a RC or SAE immediate, do nothing. */
8603 else if (is_digit_char (*op_string
)
8604 || is_identifier_char (*op_string
)
8605 || *op_string
== '(')
8607 /* This is a memory reference of some sort. */
8610 /* Start and end of displacement string expression (if found). */
8611 char *displacement_string_start
;
8612 char *displacement_string_end
;
8615 do_memory_reference
:
8616 if ((i
.mem_operands
== 1
8617 && !current_templates
->start
->opcode_modifier
.isstring
)
8618 || i
.mem_operands
== 2)
8620 as_bad (_("too many memory references for `%s'"),
8621 current_templates
->start
->name
);
8625 /* Check for base index form. We detect the base index form by
8626 looking for an ')' at the end of the operand, searching
8627 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8629 base_string
= op_string
+ strlen (op_string
);
8631 /* Handle vector operations. */
8632 vop_start
= strchr (op_string
, '{');
8633 if (vop_start
&& vop_start
< base_string
)
8635 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8637 base_string
= vop_start
;
8641 if (is_space_char (*base_string
))
8644 /* If we only have a displacement, set-up for it to be parsed later. */
8645 displacement_string_start
= op_string
;
8646 displacement_string_end
= base_string
+ 1;
8648 if (*base_string
== ')')
8651 unsigned int parens_balanced
= 1;
8652 /* We've already checked that the number of left & right ()'s are
8653 equal, so this loop will not be infinite. */
8657 if (*base_string
== ')')
8659 if (*base_string
== '(')
8662 while (parens_balanced
);
8664 temp_string
= base_string
;
8666 /* Skip past '(' and whitespace. */
8668 if (is_space_char (*base_string
))
8671 if (*base_string
== ','
8672 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8675 displacement_string_end
= temp_string
;
8677 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8681 base_string
= end_op
;
8682 if (is_space_char (*base_string
))
8686 /* There may be an index reg or scale factor here. */
8687 if (*base_string
== ',')
8690 if (is_space_char (*base_string
))
8693 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8696 base_string
= end_op
;
8697 if (is_space_char (*base_string
))
8699 if (*base_string
== ',')
8702 if (is_space_char (*base_string
))
8705 else if (*base_string
!= ')')
8707 as_bad (_("expecting `,' or `)' "
8708 "after index register in `%s'"),
8713 else if (*base_string
== REGISTER_PREFIX
)
8715 end_op
= strchr (base_string
, ',');
8718 as_bad (_("bad register name `%s'"), base_string
);
8722 /* Check for scale factor. */
8723 if (*base_string
!= ')')
8725 char *end_scale
= i386_scale (base_string
);
8730 base_string
= end_scale
;
8731 if (is_space_char (*base_string
))
8733 if (*base_string
!= ')')
8735 as_bad (_("expecting `)' "
8736 "after scale factor in `%s'"),
8741 else if (!i
.index_reg
)
8743 as_bad (_("expecting index register or scale factor "
8744 "after `,'; got '%c'"),
8749 else if (*base_string
!= ')')
8751 as_bad (_("expecting `,' or `)' "
8752 "after base register in `%s'"),
8757 else if (*base_string
== REGISTER_PREFIX
)
8759 end_op
= strchr (base_string
, ',');
8762 as_bad (_("bad register name `%s'"), base_string
);
8767 /* If there's an expression beginning the operand, parse it,
8768 assuming displacement_string_start and
8769 displacement_string_end are meaningful. */
8770 if (displacement_string_start
!= displacement_string_end
)
8772 if (!i386_displacement (displacement_string_start
,
8773 displacement_string_end
))
8777 /* Special case for (%dx) while doing input/output op. */
8779 && operand_type_equal (&i
.base_reg
->reg_type
,
8780 ®16_inoutportreg
)
8782 && i
.log2_scale_factor
== 0
8783 && i
.seg
[i
.mem_operands
] == 0
8784 && !operand_type_check (i
.types
[this_operand
], disp
))
8786 i
.types
[this_operand
] = inoutportreg
;
8790 if (i386_index_check (operand_string
) == 0)
8792 i
.types
[this_operand
].bitfield
.mem
= 1;
8797 /* It's not a memory operand; argh! */
8798 as_bad (_("invalid char %s beginning operand %d `%s'"),
8799 output_invalid (*op_string
),
8804 return 1; /* Normal return. */
8807 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8808 that an rs_machine_dependent frag may reach. */
8811 i386_frag_max_var (fragS
*frag
)
8813 /* The only relaxable frags are for jumps.
8814 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8815 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8816 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8819 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8821 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
)
8823 /* STT_GNU_IFUNC symbol must go through PLT. */
8824 if ((symbol_get_bfdsym (fr_symbol
)->flags
8825 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8828 if (!S_IS_EXTERNAL (fr_symbol
))
8829 /* Symbol may be weak or local. */
8830 return !S_IS_WEAK (fr_symbol
);
8832 /* Global symbols with default visibility in a shared library may be
8833 preempted by another definition. */
8834 return ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
;
8838 /* md_estimate_size_before_relax()
8840 Called just before relax() for rs_machine_dependent frags. The x86
8841 assembler uses these frags to handle variable size jump
8844 Any symbol that is now undefined will not become defined.
8845 Return the correct fr_subtype in the frag.
8846 Return the initial "guess for variable size of frag" to caller.
8847 The guess is actually the growth beyond the fixed part. Whatever
8848 we do to grow the fixed or variable part contributes to our
8852 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8854 /* We've already got fragP->fr_subtype right; all we have to do is
8855 check for un-relaxable symbols. On an ELF system, we can't relax
8856 an externally visible symbol, because it may be overridden by a
8858 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8861 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
))
8863 #if defined (OBJ_COFF) && defined (TE_PE)
8864 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8865 && S_IS_WEAK (fragP
->fr_symbol
))
8869 /* Symbol is undefined in this segment, or we need to keep a
8870 reloc so that weak symbols can be overridden. */
8871 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8872 enum bfd_reloc_code_real reloc_type
;
8873 unsigned char *opcode
;
8876 if (fragP
->fr_var
!= NO_RELOC
)
8877 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8879 reloc_type
= BFD_RELOC_16_PCREL
;
8881 reloc_type
= BFD_RELOC_32_PCREL
;
8883 old_fr_fix
= fragP
->fr_fix
;
8884 opcode
= (unsigned char *) fragP
->fr_opcode
;
8886 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8889 /* Make jmp (0xeb) a (d)word displacement jump. */
8891 fragP
->fr_fix
+= size
;
8892 fix_new (fragP
, old_fr_fix
, size
,
8894 fragP
->fr_offset
, 1,
8900 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8902 /* Negate the condition, and branch past an
8903 unconditional jump. */
8906 /* Insert an unconditional jump. */
8908 /* We added two extra opcode bytes, and have a two byte
8910 fragP
->fr_fix
+= 2 + 2;
8911 fix_new (fragP
, old_fr_fix
+ 2, 2,
8913 fragP
->fr_offset
, 1,
8920 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8925 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8927 fragP
->fr_offset
, 1,
8929 fixP
->fx_signed
= 1;
8933 /* This changes the byte-displacement jump 0x7N
8934 to the (d)word-displacement jump 0x0f,0x8N. */
8935 opcode
[1] = opcode
[0] + 0x10;
8936 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8937 /* We've added an opcode byte. */
8938 fragP
->fr_fix
+= 1 + size
;
8939 fix_new (fragP
, old_fr_fix
+ 1, size
,
8941 fragP
->fr_offset
, 1,
8946 BAD_CASE (fragP
->fr_subtype
);
8950 return fragP
->fr_fix
- old_fr_fix
;
8953 /* Guess size depending on current relax state. Initially the relax
8954 state will correspond to a short jump and we return 1, because
8955 the variable part of the frag (the branch offset) is one byte
8956 long. However, we can relax a section more than once and in that
8957 case we must either set fr_subtype back to the unrelaxed state,
8958 or return the value for the appropriate branch. */
8959 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8962 /* Called after relax() is finished.
8964 In: Address of frag.
8965 fr_type == rs_machine_dependent.
8966 fr_subtype is what the address relaxed to.
8968 Out: Any fixSs and constants are set up.
8969 Caller will turn frag into a ".space 0". */
8972 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8975 unsigned char *opcode
;
8976 unsigned char *where_to_put_displacement
= NULL
;
8977 offsetT target_address
;
8978 offsetT opcode_address
;
8979 unsigned int extension
= 0;
8980 offsetT displacement_from_opcode_start
;
8982 opcode
= (unsigned char *) fragP
->fr_opcode
;
8984 /* Address we want to reach in file space. */
8985 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8987 /* Address opcode resides at in file space. */
8988 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8990 /* Displacement from opcode start to fill into instruction. */
8991 displacement_from_opcode_start
= target_address
- opcode_address
;
8993 if ((fragP
->fr_subtype
& BIG
) == 0)
8995 /* Don't have to change opcode. */
8996 extension
= 1; /* 1 opcode + 1 displacement */
8997 where_to_put_displacement
= &opcode
[1];
9001 if (no_cond_jump_promotion
9002 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9003 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9004 _("long jump required"));
9006 switch (fragP
->fr_subtype
)
9008 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9009 extension
= 4; /* 1 opcode + 4 displacement */
9011 where_to_put_displacement
= &opcode
[1];
9014 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9015 extension
= 2; /* 1 opcode + 2 displacement */
9017 where_to_put_displacement
= &opcode
[1];
9020 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9021 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9022 extension
= 5; /* 2 opcode + 4 displacement */
9023 opcode
[1] = opcode
[0] + 0x10;
9024 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9025 where_to_put_displacement
= &opcode
[2];
9028 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9029 extension
= 3; /* 2 opcode + 2 displacement */
9030 opcode
[1] = opcode
[0] + 0x10;
9031 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9032 where_to_put_displacement
= &opcode
[2];
9035 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9040 where_to_put_displacement
= &opcode
[3];
9044 BAD_CASE (fragP
->fr_subtype
);
9049 /* If size if less then four we are sure that the operand fits,
9050 but if it's 4, then it could be that the displacement is larger
9052 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9054 && ((addressT
) (displacement_from_opcode_start
- extension
9055 + ((addressT
) 1 << 31))
9056 > (((addressT
) 2 << 31) - 1)))
9058 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9059 _("jump target out of range"));
9060 /* Make us emit 0. */
9061 displacement_from_opcode_start
= extension
;
9063 /* Now put displacement after opcode. */
9064 md_number_to_chars ((char *) where_to_put_displacement
,
9065 (valueT
) (displacement_from_opcode_start
- extension
),
9066 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9067 fragP
->fr_fix
+= extension
;
9070 /* Apply a fixup (fixP) to segment data, once it has been determined
9071 by our caller that we have all the info we need to fix it up.
9073 Parameter valP is the pointer to the value of the bits.
9075 On the 386, immediates, displacements, and data pointers are all in
9076 the same (little-endian) format, so we don't need to care about which
9080 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9082 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9083 valueT value
= *valP
;
9085 #if !defined (TE_Mach)
9088 switch (fixP
->fx_r_type
)
9094 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9097 case BFD_RELOC_X86_64_32S
:
9098 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9101 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9104 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9109 if (fixP
->fx_addsy
!= NULL
9110 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9111 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9112 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9113 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9114 && !use_rela_relocations
)
9116 /* This is a hack. There should be a better way to handle this.
9117 This covers for the fact that bfd_install_relocation will
9118 subtract the current location (for partial_inplace, PC relative
9119 relocations); see more below. */
9123 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9126 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9128 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9131 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9134 || (symbol_section_p (fixP
->fx_addsy
)
9135 && sym_seg
!= absolute_section
))
9136 && !generic_force_reloc (fixP
))
9138 /* Yes, we add the values in twice. This is because
9139 bfd_install_relocation subtracts them out again. I think
9140 bfd_install_relocation is broken, but I don't dare change
9142 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9146 #if defined (OBJ_COFF) && defined (TE_PE)
9147 /* For some reason, the PE format does not store a
9148 section address offset for a PC relative symbol. */
9149 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9150 || S_IS_WEAK (fixP
->fx_addsy
))
9151 value
+= md_pcrel_from (fixP
);
9154 #if defined (OBJ_COFF) && defined (TE_PE)
9155 if (fixP
->fx_addsy
!= NULL
9156 && S_IS_WEAK (fixP
->fx_addsy
)
9157 /* PR 16858: Do not modify weak function references. */
9158 && ! fixP
->fx_pcrel
)
9160 #if !defined (TE_PEP)
9161 /* For x86 PE weak function symbols are neither PC-relative
9162 nor do they set S_IS_FUNCTION. So the only reliable way
9163 to detect them is to check the flags of their containing
9165 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9166 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9170 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9174 /* Fix a few things - the dynamic linker expects certain values here,
9175 and we must not disappoint it. */
9176 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9177 if (IS_ELF
&& fixP
->fx_addsy
)
9178 switch (fixP
->fx_r_type
)
9180 case BFD_RELOC_386_PLT32
:
9181 case BFD_RELOC_X86_64_PLT32
:
9182 /* Make the jump instruction point to the address of the operand. At
9183 runtime we merely add the offset to the actual PLT entry. */
9187 case BFD_RELOC_386_TLS_GD
:
9188 case BFD_RELOC_386_TLS_LDM
:
9189 case BFD_RELOC_386_TLS_IE_32
:
9190 case BFD_RELOC_386_TLS_IE
:
9191 case BFD_RELOC_386_TLS_GOTIE
:
9192 case BFD_RELOC_386_TLS_GOTDESC
:
9193 case BFD_RELOC_X86_64_TLSGD
:
9194 case BFD_RELOC_X86_64_TLSLD
:
9195 case BFD_RELOC_X86_64_GOTTPOFF
:
9196 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9197 value
= 0; /* Fully resolved at runtime. No addend. */
9199 case BFD_RELOC_386_TLS_LE
:
9200 case BFD_RELOC_386_TLS_LDO_32
:
9201 case BFD_RELOC_386_TLS_LE_32
:
9202 case BFD_RELOC_X86_64_DTPOFF32
:
9203 case BFD_RELOC_X86_64_DTPOFF64
:
9204 case BFD_RELOC_X86_64_TPOFF32
:
9205 case BFD_RELOC_X86_64_TPOFF64
:
9206 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9209 case BFD_RELOC_386_TLS_DESC_CALL
:
9210 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9211 value
= 0; /* Fully resolved at runtime. No addend. */
9212 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9216 case BFD_RELOC_386_GOT32
:
9217 case BFD_RELOC_X86_64_GOT32
:
9218 value
= 0; /* Fully resolved at runtime. No addend. */
9221 case BFD_RELOC_VTABLE_INHERIT
:
9222 case BFD_RELOC_VTABLE_ENTRY
:
9229 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9231 #endif /* !defined (TE_Mach) */
9233 /* Are we finished with this relocation now? */
9234 if (fixP
->fx_addsy
== NULL
)
9236 #if defined (OBJ_COFF) && defined (TE_PE)
9237 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9240 /* Remember value for tc_gen_reloc. */
9241 fixP
->fx_addnumber
= value
;
9242 /* Clear out the frag for now. */
9246 else if (use_rela_relocations
)
9248 fixP
->fx_no_overflow
= 1;
9249 /* Remember value for tc_gen_reloc. */
9250 fixP
->fx_addnumber
= value
;
9254 md_number_to_chars (p
, value
, fixP
->fx_size
);
9258 md_atof (int type
, char *litP
, int *sizeP
)
9260 /* This outputs the LITTLENUMs in REVERSE order;
9261 in accord with the bigendian 386. */
9262 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9265 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9268 output_invalid (int c
)
9271 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9274 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9275 "(0x%x)", (unsigned char) c
);
9276 return output_invalid_buf
;
9279 /* REG_STRING starts *before* REGISTER_PREFIX. */
9281 static const reg_entry
*
9282 parse_real_register (char *reg_string
, char **end_op
)
9284 char *s
= reg_string
;
9286 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9289 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9290 if (*s
== REGISTER_PREFIX
)
9293 if (is_space_char (*s
))
9297 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9299 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9300 return (const reg_entry
*) NULL
;
9304 /* For naked regs, make sure that we are not dealing with an identifier.
9305 This prevents confusing an identifier like `eax_var' with register
9307 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9308 return (const reg_entry
*) NULL
;
9312 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9314 /* Handle floating point regs, allowing spaces in the (i) part. */
9315 if (r
== i386_regtab
/* %st is first entry of table */)
9317 if (is_space_char (*s
))
9322 if (is_space_char (*s
))
9324 if (*s
>= '0' && *s
<= '7')
9328 if (is_space_char (*s
))
9333 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9338 /* We have "%st(" then garbage. */
9339 return (const reg_entry
*) NULL
;
9343 if (r
== NULL
|| allow_pseudo_reg
)
9346 if (operand_type_all_zero (&r
->reg_type
))
9347 return (const reg_entry
*) NULL
;
9349 if ((r
->reg_type
.bitfield
.reg32
9350 || r
->reg_type
.bitfield
.sreg3
9351 || r
->reg_type
.bitfield
.control
9352 || r
->reg_type
.bitfield
.debug
9353 || r
->reg_type
.bitfield
.test
)
9354 && !cpu_arch_flags
.bitfield
.cpui386
)
9355 return (const reg_entry
*) NULL
;
9357 if (r
->reg_type
.bitfield
.floatreg
9358 && !cpu_arch_flags
.bitfield
.cpu8087
9359 && !cpu_arch_flags
.bitfield
.cpu287
9360 && !cpu_arch_flags
.bitfield
.cpu387
)
9361 return (const reg_entry
*) NULL
;
9363 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9364 return (const reg_entry
*) NULL
;
9366 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9367 return (const reg_entry
*) NULL
;
9369 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9370 return (const reg_entry
*) NULL
;
9372 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9373 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9374 return (const reg_entry
*) NULL
;
9376 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9377 if (!allow_index_reg
9378 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9379 return (const reg_entry
*) NULL
;
9381 /* Upper 16 vector register is only available with VREX in 64bit
9383 if ((r
->reg_flags
& RegVRex
))
9385 if (!cpu_arch_flags
.bitfield
.cpuvrex
9386 || flag_code
!= CODE_64BIT
)
9387 return (const reg_entry
*) NULL
;
9392 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9393 || r
->reg_type
.bitfield
.reg64
)
9394 && (!cpu_arch_flags
.bitfield
.cpulm
9395 || !operand_type_equal (&r
->reg_type
, &control
))
9396 && flag_code
!= CODE_64BIT
)
9397 return (const reg_entry
*) NULL
;
9399 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9400 return (const reg_entry
*) NULL
;
9405 /* REG_STRING starts *before* REGISTER_PREFIX. */
9407 static const reg_entry
*
9408 parse_register (char *reg_string
, char **end_op
)
9412 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9413 r
= parse_real_register (reg_string
, end_op
);
9418 char *save
= input_line_pointer
;
9422 input_line_pointer
= reg_string
;
9423 c
= get_symbol_end ();
9424 symbolP
= symbol_find (reg_string
);
9425 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9427 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9429 know (e
->X_op
== O_register
);
9430 know (e
->X_add_number
>= 0
9431 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9432 r
= i386_regtab
+ e
->X_add_number
;
9433 if ((r
->reg_flags
& RegVRex
))
9435 *end_op
= input_line_pointer
;
9437 *input_line_pointer
= c
;
9438 input_line_pointer
= save
;
9444 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9447 char *end
= input_line_pointer
;
9450 r
= parse_register (name
, &input_line_pointer
);
9451 if (r
&& end
<= input_line_pointer
)
9453 *nextcharP
= *input_line_pointer
;
9454 *input_line_pointer
= 0;
9455 e
->X_op
= O_register
;
9456 e
->X_add_number
= r
- i386_regtab
;
9459 input_line_pointer
= end
;
9461 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9465 md_operand (expressionS
*e
)
9470 switch (*input_line_pointer
)
9472 case REGISTER_PREFIX
:
9473 r
= parse_real_register (input_line_pointer
, &end
);
9476 e
->X_op
= O_register
;
9477 e
->X_add_number
= r
- i386_regtab
;
9478 input_line_pointer
= end
;
9483 gas_assert (intel_syntax
);
9484 end
= input_line_pointer
++;
9486 if (*input_line_pointer
== ']')
9488 ++input_line_pointer
;
9489 e
->X_op_symbol
= make_expr_symbol (e
);
9490 e
->X_add_symbol
= NULL
;
9491 e
->X_add_number
= 0;
9497 input_line_pointer
= end
;
9504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9505 const char *md_shortopts
= "kVQ:sqn";
9507 const char *md_shortopts
= "qn";
9510 #define OPTION_32 (OPTION_MD_BASE + 0)
9511 #define OPTION_64 (OPTION_MD_BASE + 1)
9512 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9513 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9514 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9515 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9516 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9517 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9518 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9519 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9520 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9521 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9522 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9523 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9524 #define OPTION_X32 (OPTION_MD_BASE + 14)
9525 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9526 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9527 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9528 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9529 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9530 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9532 struct option md_longopts
[] =
9534 {"32", no_argument
, NULL
, OPTION_32
},
9535 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9536 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9537 {"64", no_argument
, NULL
, OPTION_64
},
9539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9540 {"x32", no_argument
, NULL
, OPTION_X32
},
9542 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9543 {"march", required_argument
, NULL
, OPTION_MARCH
},
9544 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9545 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9546 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9547 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9548 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9549 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9550 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9551 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9552 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9553 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9554 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9555 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9556 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9557 # if defined (TE_PE) || defined (TE_PEP)
9558 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9560 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9561 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9562 {NULL
, no_argument
, NULL
, 0}
9564 size_t md_longopts_size
= sizeof (md_longopts
);
9567 md_parse_option (int c
, char *arg
)
9575 optimize_align_code
= 0;
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9583 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9584 should be emitted or not. FIXME: Not implemented. */
9588 /* -V: SVR4 argument to print version ID. */
9590 print_version_id ();
9593 /* -k: Ignore for FreeBSD compatibility. */
9598 /* -s: On i386 Solaris, this tells the native assembler to use
9599 .stab instead of .stab.excl. We always use .stab anyhow. */
9602 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9603 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9606 const char **list
, **l
;
9608 list
= bfd_target_list ();
9609 for (l
= list
; *l
!= NULL
; l
++)
9610 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9611 || strcmp (*l
, "coff-x86-64") == 0
9612 || strcmp (*l
, "pe-x86-64") == 0
9613 || strcmp (*l
, "pei-x86-64") == 0
9614 || strcmp (*l
, "mach-o-x86-64") == 0)
9616 default_arch
= "x86_64";
9620 as_fatal (_("no compiled in support for x86_64"));
9626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9630 const char **list
, **l
;
9632 list
= bfd_target_list ();
9633 for (l
= list
; *l
!= NULL
; l
++)
9634 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9636 default_arch
= "x86_64:32";
9640 as_fatal (_("no compiled in support for 32bit x86_64"));
9644 as_fatal (_("32bit x86_64 is only supported for ELF"));
9649 default_arch
= "i386";
9653 #ifdef SVR4_COMMENT_CHARS
9658 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9660 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9664 i386_comment_chars
= n
;
9670 arch
= xstrdup (arg
);
9674 as_fatal (_("invalid -march= option: `%s'"), arg
);
9675 next
= strchr (arch
, '+');
9678 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9680 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9683 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9686 cpu_arch_name
= cpu_arch
[j
].name
;
9687 cpu_sub_arch_name
= NULL
;
9688 cpu_arch_flags
= cpu_arch
[j
].flags
;
9689 cpu_arch_isa
= cpu_arch
[j
].type
;
9690 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9691 if (!cpu_arch_tune_set
)
9693 cpu_arch_tune
= cpu_arch_isa
;
9694 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9698 else if (*cpu_arch
[j
].name
== '.'
9699 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9701 /* ISA entension. */
9702 i386_cpu_flags flags
;
9704 if (!cpu_arch
[j
].negated
)
9705 flags
= cpu_flags_or (cpu_arch_flags
,
9708 flags
= cpu_flags_and_not (cpu_arch_flags
,
9711 if (!valid_iamcu_cpu_flags (&flags
))
9712 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9713 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9715 if (cpu_sub_arch_name
)
9717 char *name
= cpu_sub_arch_name
;
9718 cpu_sub_arch_name
= concat (name
,
9720 (const char *) NULL
);
9724 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9725 cpu_arch_flags
= flags
;
9726 cpu_arch_isa_flags
= flags
;
9732 if (j
>= ARRAY_SIZE (cpu_arch
))
9733 as_fatal (_("invalid -march= option: `%s'"), arg
);
9737 while (next
!= NULL
);
9742 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9743 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9745 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9747 cpu_arch_tune_set
= 1;
9748 cpu_arch_tune
= cpu_arch
[j
].type
;
9749 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9753 if (j
>= ARRAY_SIZE (cpu_arch
))
9754 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9757 case OPTION_MMNEMONIC
:
9758 if (strcasecmp (arg
, "att") == 0)
9760 else if (strcasecmp (arg
, "intel") == 0)
9763 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9766 case OPTION_MSYNTAX
:
9767 if (strcasecmp (arg
, "att") == 0)
9769 else if (strcasecmp (arg
, "intel") == 0)
9772 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9775 case OPTION_MINDEX_REG
:
9776 allow_index_reg
= 1;
9779 case OPTION_MNAKED_REG
:
9780 allow_naked_reg
= 1;
9783 case OPTION_MOLD_GCC
:
9787 case OPTION_MSSE2AVX
:
9791 case OPTION_MSSE_CHECK
:
9792 if (strcasecmp (arg
, "error") == 0)
9793 sse_check
= check_error
;
9794 else if (strcasecmp (arg
, "warning") == 0)
9795 sse_check
= check_warning
;
9796 else if (strcasecmp (arg
, "none") == 0)
9797 sse_check
= check_none
;
9799 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9802 case OPTION_MOPERAND_CHECK
:
9803 if (strcasecmp (arg
, "error") == 0)
9804 operand_check
= check_error
;
9805 else if (strcasecmp (arg
, "warning") == 0)
9806 operand_check
= check_warning
;
9807 else if (strcasecmp (arg
, "none") == 0)
9808 operand_check
= check_none
;
9810 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9813 case OPTION_MAVXSCALAR
:
9814 if (strcasecmp (arg
, "128") == 0)
9816 else if (strcasecmp (arg
, "256") == 0)
9819 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9822 case OPTION_MADD_BND_PREFIX
:
9826 case OPTION_MEVEXLIG
:
9827 if (strcmp (arg
, "128") == 0)
9829 else if (strcmp (arg
, "256") == 0)
9831 else if (strcmp (arg
, "512") == 0)
9834 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9837 case OPTION_MEVEXRCIG
:
9838 if (strcmp (arg
, "rne") == 0)
9840 else if (strcmp (arg
, "rd") == 0)
9842 else if (strcmp (arg
, "ru") == 0)
9844 else if (strcmp (arg
, "rz") == 0)
9847 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9850 case OPTION_MEVEXWIG
:
9851 if (strcmp (arg
, "0") == 0)
9853 else if (strcmp (arg
, "1") == 0)
9856 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9859 # if defined (TE_PE) || defined (TE_PEP)
9860 case OPTION_MBIG_OBJ
:
9865 case OPTION_OMIT_LOCK_PREFIX
:
9866 if (strcasecmp (arg
, "yes") == 0)
9867 omit_lock_prefix
= 1;
9868 else if (strcasecmp (arg
, "no") == 0)
9869 omit_lock_prefix
= 0;
9871 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9880 #define MESSAGE_TEMPLATE \
9884 show_arch (FILE *stream
, int ext
, int check
)
9886 static char message
[] = MESSAGE_TEMPLATE
;
9887 char *start
= message
+ 27;
9889 int size
= sizeof (MESSAGE_TEMPLATE
);
9896 left
= size
- (start
- message
);
9897 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9899 /* Should it be skipped? */
9900 if (cpu_arch
[j
].skip
)
9903 name
= cpu_arch
[j
].name
;
9904 len
= cpu_arch
[j
].len
;
9907 /* It is an extension. Skip if we aren't asked to show it. */
9918 /* It is an processor. Skip if we show only extension. */
9921 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9923 /* It is an impossible processor - skip. */
9927 /* Reserve 2 spaces for ", " or ",\0" */
9930 /* Check if there is any room. */
9938 p
= mempcpy (p
, name
, len
);
9942 /* Output the current message now and start a new one. */
9945 fprintf (stream
, "%s\n", message
);
9947 left
= size
- (start
- message
) - len
- 2;
9949 gas_assert (left
>= 0);
9951 p
= mempcpy (p
, name
, len
);
9956 fprintf (stream
, "%s\n", message
);
9960 md_show_usage (FILE *stream
)
9962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9963 fprintf (stream
, _("\
9965 -V print assembler version number\n\
9968 fprintf (stream
, _("\
9969 -n Do not optimize code alignment\n\
9970 -q quieten some warnings\n"));
9971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9972 fprintf (stream
, _("\
9975 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9976 || defined (TE_PE) || defined (TE_PEP))
9977 fprintf (stream
, _("\
9978 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9980 #ifdef SVR4_COMMENT_CHARS
9981 fprintf (stream
, _("\
9982 --divide do not treat `/' as a comment character\n"));
9984 fprintf (stream
, _("\
9985 --divide ignored\n"));
9987 fprintf (stream
, _("\
9988 -march=CPU[,+EXTENSION...]\n\
9989 generate code for CPU and EXTENSION, CPU is one of:\n"));
9990 show_arch (stream
, 0, 1);
9991 fprintf (stream
, _("\
9992 EXTENSION is combination of:\n"));
9993 show_arch (stream
, 1, 0);
9994 fprintf (stream
, _("\
9995 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9996 show_arch (stream
, 0, 0);
9997 fprintf (stream
, _("\
9998 -msse2avx encode SSE instructions with VEX prefix\n"));
9999 fprintf (stream
, _("\
10000 -msse-check=[none|error|warning]\n\
10001 check SSE instructions\n"));
10002 fprintf (stream
, _("\
10003 -moperand-check=[none|error|warning]\n\
10004 check operand combinations for validity\n"));
10005 fprintf (stream
, _("\
10006 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10008 fprintf (stream
, _("\
10009 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10011 fprintf (stream
, _("\
10012 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10013 for EVEX.W bit ignored instructions\n"));
10014 fprintf (stream
, _("\
10015 -mevexrcig=[rne|rd|ru|rz]\n\
10016 encode EVEX instructions with specific EVEX.RC value\n\
10017 for SAE-only ignored instructions\n"));
10018 fprintf (stream
, _("\
10019 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10020 fprintf (stream
, _("\
10021 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10022 fprintf (stream
, _("\
10023 -mindex-reg support pseudo index registers\n"));
10024 fprintf (stream
, _("\
10025 -mnaked-reg don't require `%%' prefix for registers\n"));
10026 fprintf (stream
, _("\
10027 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10028 fprintf (stream
, _("\
10029 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10030 # if defined (TE_PE) || defined (TE_PEP)
10031 fprintf (stream
, _("\
10032 -mbig-obj generate big object files\n"));
10034 fprintf (stream
, _("\
10035 -momit-lock-prefix=[no|yes]\n\
10036 strip all lock prefixes\n"));
10039 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10040 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10041 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10043 /* Pick the target format to use. */
10046 i386_target_format (void)
10048 if (!strncmp (default_arch
, "x86_64", 6))
10050 update_code_flag (CODE_64BIT
, 1);
10051 if (default_arch
[6] == '\0')
10052 x86_elf_abi
= X86_64_ABI
;
10054 x86_elf_abi
= X86_64_X32_ABI
;
10056 else if (!strcmp (default_arch
, "i386"))
10057 update_code_flag (CODE_32BIT
, 1);
10058 else if (!strcmp (default_arch
, "iamcu"))
10060 update_code_flag (CODE_32BIT
, 1);
10061 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10063 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10064 cpu_arch_name
= "iamcu";
10065 cpu_sub_arch_name
= NULL
;
10066 cpu_arch_flags
= iamcu_flags
;
10067 cpu_arch_isa
= PROCESSOR_IAMCU
;
10068 cpu_arch_isa_flags
= iamcu_flags
;
10069 if (!cpu_arch_tune_set
)
10071 cpu_arch_tune
= cpu_arch_isa
;
10072 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10076 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10080 as_fatal (_("unknown architecture"));
10082 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10083 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10084 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10085 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10087 switch (OUTPUT_FLAVOR
)
10089 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10090 case bfd_target_aout_flavour
:
10091 return AOUT_TARGET_FORMAT
;
10093 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10094 # if defined (TE_PE) || defined (TE_PEP)
10095 case bfd_target_coff_flavour
:
10096 if (flag_code
== CODE_64BIT
)
10097 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10100 # elif defined (TE_GO32)
10101 case bfd_target_coff_flavour
:
10102 return "coff-go32";
10104 case bfd_target_coff_flavour
:
10105 return "coff-i386";
10108 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10109 case bfd_target_elf_flavour
:
10111 const char *format
;
10113 switch (x86_elf_abi
)
10116 format
= ELF_TARGET_FORMAT
;
10119 use_rela_relocations
= 1;
10121 format
= ELF_TARGET_FORMAT64
;
10123 case X86_64_X32_ABI
:
10124 use_rela_relocations
= 1;
10126 disallow_64bit_reloc
= 1;
10127 format
= ELF_TARGET_FORMAT32
;
10130 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10132 if (x86_elf_abi
!= X86_64_ABI
)
10133 as_fatal (_("Intel L1OM is 64bit only"));
10134 return ELF_TARGET_L1OM_FORMAT
;
10136 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10138 if (x86_elf_abi
!= X86_64_ABI
)
10139 as_fatal (_("Intel K1OM is 64bit only"));
10140 return ELF_TARGET_K1OM_FORMAT
;
10142 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10144 if (x86_elf_abi
!= I386_ABI
)
10145 as_fatal (_("Intel MCU is 32bit only"));
10146 return ELF_TARGET_IAMCU_FORMAT
;
10152 #if defined (OBJ_MACH_O)
10153 case bfd_target_mach_o_flavour
:
10154 if (flag_code
== CODE_64BIT
)
10156 use_rela_relocations
= 1;
10158 return "mach-o-x86-64";
10161 return "mach-o-i386";
10169 #endif /* OBJ_MAYBE_ more than one */
10172 md_undefined_symbol (char *name
)
10174 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10175 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10176 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10177 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10181 if (symbol_find (name
))
10182 as_bad (_("GOT already in symbol table"));
10183 GOT_symbol
= symbol_new (name
, undefined_section
,
10184 (valueT
) 0, &zero_address_frag
);
10191 /* Round up a section size to the appropriate boundary. */
10194 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10196 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10197 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10199 /* For a.out, force the section size to be aligned. If we don't do
10200 this, BFD will align it for us, but it will not write out the
10201 final bytes of the section. This may be a bug in BFD, but it is
10202 easier to fix it here since that is how the other a.out targets
10206 align
= bfd_get_section_alignment (stdoutput
, segment
);
10207 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10214 /* On the i386, PC-relative offsets are relative to the start of the
10215 next instruction. That is, the address of the offset, plus its
10216 size, since the offset is always the last part of the insn. */
10219 md_pcrel_from (fixS
*fixP
)
10221 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10227 s_bss (int ignore ATTRIBUTE_UNUSED
)
10231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10233 obj_elf_section_change_hook ();
10235 temp
= get_absolute_expression ();
10236 subseg_set (bss_section
, (subsegT
) temp
);
10237 demand_empty_rest_of_line ();
10243 i386_validate_fix (fixS
*fixp
)
10245 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10247 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10251 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10256 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10258 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10260 fixp
->fx_subsy
= 0;
10265 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10268 bfd_reloc_code_real_type code
;
10270 switch (fixp
->fx_r_type
)
10272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10273 case BFD_RELOC_SIZE32
:
10274 case BFD_RELOC_SIZE64
:
10275 if (S_IS_DEFINED (fixp
->fx_addsy
)
10276 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10278 /* Resolve size relocation against local symbol to size of
10279 the symbol plus addend. */
10280 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10281 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10282 && !fits_in_unsigned_long (value
))
10283 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10284 _("symbol size computation overflow"));
10285 fixp
->fx_addsy
= NULL
;
10286 fixp
->fx_subsy
= NULL
;
10287 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10292 case BFD_RELOC_X86_64_PLT32
:
10293 case BFD_RELOC_X86_64_GOT32
:
10294 case BFD_RELOC_X86_64_GOTPCREL
:
10295 case BFD_RELOC_386_PLT32
:
10296 case BFD_RELOC_386_GOT32
:
10297 case BFD_RELOC_386_GOTOFF
:
10298 case BFD_RELOC_386_GOTPC
:
10299 case BFD_RELOC_386_TLS_GD
:
10300 case BFD_RELOC_386_TLS_LDM
:
10301 case BFD_RELOC_386_TLS_LDO_32
:
10302 case BFD_RELOC_386_TLS_IE_32
:
10303 case BFD_RELOC_386_TLS_IE
:
10304 case BFD_RELOC_386_TLS_GOTIE
:
10305 case BFD_RELOC_386_TLS_LE_32
:
10306 case BFD_RELOC_386_TLS_LE
:
10307 case BFD_RELOC_386_TLS_GOTDESC
:
10308 case BFD_RELOC_386_TLS_DESC_CALL
:
10309 case BFD_RELOC_X86_64_TLSGD
:
10310 case BFD_RELOC_X86_64_TLSLD
:
10311 case BFD_RELOC_X86_64_DTPOFF32
:
10312 case BFD_RELOC_X86_64_DTPOFF64
:
10313 case BFD_RELOC_X86_64_GOTTPOFF
:
10314 case BFD_RELOC_X86_64_TPOFF32
:
10315 case BFD_RELOC_X86_64_TPOFF64
:
10316 case BFD_RELOC_X86_64_GOTOFF64
:
10317 case BFD_RELOC_X86_64_GOTPC32
:
10318 case BFD_RELOC_X86_64_GOT64
:
10319 case BFD_RELOC_X86_64_GOTPCREL64
:
10320 case BFD_RELOC_X86_64_GOTPC64
:
10321 case BFD_RELOC_X86_64_GOTPLT64
:
10322 case BFD_RELOC_X86_64_PLTOFF64
:
10323 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10324 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10325 case BFD_RELOC_RVA
:
10326 case BFD_RELOC_VTABLE_ENTRY
:
10327 case BFD_RELOC_VTABLE_INHERIT
:
10329 case BFD_RELOC_32_SECREL
:
10331 code
= fixp
->fx_r_type
;
10333 case BFD_RELOC_X86_64_32S
:
10334 if (!fixp
->fx_pcrel
)
10336 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10337 code
= fixp
->fx_r_type
;
10341 if (fixp
->fx_pcrel
)
10343 switch (fixp
->fx_size
)
10346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10347 _("can not do %d byte pc-relative relocation"),
10349 code
= BFD_RELOC_32_PCREL
;
10351 case 1: code
= BFD_RELOC_8_PCREL
; break;
10352 case 2: code
= BFD_RELOC_16_PCREL
; break;
10353 case 4: code
= BFD_RELOC_32_PCREL
; break;
10355 case 8: code
= BFD_RELOC_64_PCREL
; break;
10361 switch (fixp
->fx_size
)
10364 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10365 _("can not do %d byte relocation"),
10367 code
= BFD_RELOC_32
;
10369 case 1: code
= BFD_RELOC_8
; break;
10370 case 2: code
= BFD_RELOC_16
; break;
10371 case 4: code
= BFD_RELOC_32
; break;
10373 case 8: code
= BFD_RELOC_64
; break;
10380 if ((code
== BFD_RELOC_32
10381 || code
== BFD_RELOC_32_PCREL
10382 || code
== BFD_RELOC_X86_64_32S
)
10384 && fixp
->fx_addsy
== GOT_symbol
)
10387 code
= BFD_RELOC_386_GOTPC
;
10389 code
= BFD_RELOC_X86_64_GOTPC32
;
10391 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10393 && fixp
->fx_addsy
== GOT_symbol
)
10395 code
= BFD_RELOC_X86_64_GOTPC64
;
10398 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10399 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10400 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10402 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10404 if (!use_rela_relocations
)
10406 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10407 vtable entry to be used in the relocation's section offset. */
10408 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10409 rel
->address
= fixp
->fx_offset
;
10410 #if defined (OBJ_COFF) && defined (TE_PE)
10411 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10412 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10417 /* Use the rela in 64bit mode. */
10420 if (disallow_64bit_reloc
)
10423 case BFD_RELOC_X86_64_DTPOFF64
:
10424 case BFD_RELOC_X86_64_TPOFF64
:
10425 case BFD_RELOC_64_PCREL
:
10426 case BFD_RELOC_X86_64_GOTOFF64
:
10427 case BFD_RELOC_X86_64_GOT64
:
10428 case BFD_RELOC_X86_64_GOTPCREL64
:
10429 case BFD_RELOC_X86_64_GOTPC64
:
10430 case BFD_RELOC_X86_64_GOTPLT64
:
10431 case BFD_RELOC_X86_64_PLTOFF64
:
10432 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10433 _("cannot represent relocation type %s in x32 mode"),
10434 bfd_get_reloc_code_name (code
));
10440 if (!fixp
->fx_pcrel
)
10441 rel
->addend
= fixp
->fx_offset
;
10445 case BFD_RELOC_X86_64_PLT32
:
10446 case BFD_RELOC_X86_64_GOT32
:
10447 case BFD_RELOC_X86_64_GOTPCREL
:
10448 case BFD_RELOC_X86_64_TLSGD
:
10449 case BFD_RELOC_X86_64_TLSLD
:
10450 case BFD_RELOC_X86_64_GOTTPOFF
:
10451 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10452 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10453 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10456 rel
->addend
= (section
->vma
10458 + fixp
->fx_addnumber
10459 + md_pcrel_from (fixp
));
10464 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10465 if (rel
->howto
== NULL
)
10467 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10468 _("cannot represent relocation type %s"),
10469 bfd_get_reloc_code_name (code
));
10470 /* Set howto to a garbage value so that we can keep going. */
10471 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10472 gas_assert (rel
->howto
!= NULL
);
10478 #include "tc-i386-intel.c"
10481 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10483 int saved_naked_reg
;
10484 char saved_register_dot
;
10486 saved_naked_reg
= allow_naked_reg
;
10487 allow_naked_reg
= 1;
10488 saved_register_dot
= register_chars
['.'];
10489 register_chars
['.'] = '.';
10490 allow_pseudo_reg
= 1;
10491 expression_and_evaluate (exp
);
10492 allow_pseudo_reg
= 0;
10493 register_chars
['.'] = saved_register_dot
;
10494 allow_naked_reg
= saved_naked_reg
;
10496 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10498 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10500 exp
->X_op
= O_constant
;
10501 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10502 .dw2_regnum
[flag_code
>> 1];
10505 exp
->X_op
= O_illegal
;
10510 tc_x86_frame_initial_instructions (void)
10512 static unsigned int sp_regno
[2];
10514 if (!sp_regno
[flag_code
>> 1])
10516 char *saved_input
= input_line_pointer
;
10517 char sp
[][4] = {"esp", "rsp"};
10520 input_line_pointer
= sp
[flag_code
>> 1];
10521 tc_x86_parse_to_dw2regnum (&exp
);
10522 gas_assert (exp
.X_op
== O_constant
);
10523 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10524 input_line_pointer
= saved_input
;
10527 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10528 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10532 x86_dwarf2_addr_size (void)
10534 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10535 if (x86_elf_abi
== X86_64_X32_ABI
)
10538 return bfd_arch_bits_per_address (stdoutput
) / 8;
10542 i386_elf_section_type (const char *str
, size_t len
)
10544 if (flag_code
== CODE_64BIT
10545 && len
== sizeof ("unwind") - 1
10546 && strncmp (str
, "unwind", 6) == 0)
10547 return SHT_X86_64_UNWIND
;
10554 i386_solaris_fix_up_eh_frame (segT sec
)
10556 if (flag_code
== CODE_64BIT
)
10557 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10563 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10567 exp
.X_op
= O_secrel
;
10568 exp
.X_add_symbol
= symbol
;
10569 exp
.X_add_number
= 0;
10570 emit_expr (&exp
, size
);
10574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10575 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10578 x86_64_section_letter (int letter
, char **ptr_msg
)
10580 if (flag_code
== CODE_64BIT
)
10583 return SHF_X86_64_LARGE
;
10585 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10588 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10593 x86_64_section_word (char *str
, size_t len
)
10595 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10596 return SHF_X86_64_LARGE
;
10602 handle_large_common (int small ATTRIBUTE_UNUSED
)
10604 if (flag_code
!= CODE_64BIT
)
10606 s_comm_internal (0, elf_common_parse
);
10607 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10611 static segT lbss_section
;
10612 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10613 asection
*saved_bss_section
= bss_section
;
10615 if (lbss_section
== NULL
)
10617 flagword applicable
;
10618 segT seg
= now_seg
;
10619 subsegT subseg
= now_subseg
;
10621 /* The .lbss section is for local .largecomm symbols. */
10622 lbss_section
= subseg_new (".lbss", 0);
10623 applicable
= bfd_applicable_section_flags (stdoutput
);
10624 bfd_set_section_flags (stdoutput
, lbss_section
,
10625 applicable
& SEC_ALLOC
);
10626 seg_info (lbss_section
)->bss
= 1;
10628 subseg_set (seg
, subseg
);
10631 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10632 bss_section
= lbss_section
;
10634 s_comm_internal (0, elf_common_parse
);
10636 elf_com_section_ptr
= saved_com_section_ptr
;
10637 bss_section
= saved_bss_section
;
10640 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */