1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 static enum check_kind
552 sse_check
, operand_check
= check_warning
;
554 /* Register prefix used for error message. */
555 static const char *register_prefix
= "%";
557 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560 static char stackop_size
= '\0';
562 /* Non-zero to optimize code alignment. */
563 int optimize_align_code
= 1;
565 /* Non-zero to quieten some warnings. */
566 static int quiet_warnings
= 0;
569 static const char *cpu_arch_name
= NULL
;
570 static char *cpu_sub_arch_name
= NULL
;
572 /* CPU feature flags. */
573 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
575 /* If we have selected a cpu we are generating instructions for. */
576 static int cpu_arch_tune_set
= 0;
578 /* Cpu we are generating instructions for. */
579 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
581 /* CPU feature flags of cpu we are generating instructions for. */
582 static i386_cpu_flags cpu_arch_tune_flags
;
584 /* CPU instruction set architecture used. */
585 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
587 /* CPU feature flags of instruction set architecture used. */
588 i386_cpu_flags cpu_arch_isa_flags
;
590 /* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592 static unsigned int no_cond_jump_promotion
= 0;
594 /* Encode SSE instructions with VEX prefix. */
595 static unsigned int sse2avx
;
597 /* Encode scalar AVX instructions with specific vector length. */
604 /* Encode scalar EVEX LIG instructions with specific vector length. */
612 /* Encode EVEX WIG instructions with specific evex.w. */
619 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
620 static symbolS
*GOT_symbol
;
622 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
623 unsigned int x86_dwarf2_return_column
;
625 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626 int x86_cie_data_alignment
;
628 /* Interface to relax_segment.
629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
634 #define UNCOND_JUMP 0
636 #define COND_JUMP86 2
641 #define SMALL16 (SMALL | CODE16)
643 #define BIG16 (BIG | CODE16)
647 #define INLINE __inline__
653 #define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655 #define TYPE_FROM_RELAX_STATE(s) \
657 #define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
660 /* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
668 const relax_typeS md_relax_table
[] =
671 1) most positive reach of this state,
672 2) most negative reach of this state,
673 3) how many bytes this mode will have in the variable part of the frag
674 4) which index into the table to try if we can't fit into this one. */
676 /* UNCOND_JUMP states. */
677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
692 /* word conditionals add 3 bytes to frag:
693 1 extra opcode byte, 2 displacement bytes. */
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
707 static const arch_entry cpu_arch
[] =
709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
712 CPU_GENERIC32_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
714 CPU_GENERIC64_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
716 CPU_NONE_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
718 CPU_I186_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
720 CPU_I286_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
722 CPU_I386_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
724 CPU_I486_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
726 CPU_I586_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
728 CPU_I686_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
730 CPU_I586_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
732 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
734 CPU_P2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
736 CPU_P3_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
738 CPU_P4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
740 CPU_CORE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
742 CPU_NOCONA_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 1, 0 },
745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
746 CPU_CORE_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 1, 0 },
749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
750 CPU_CORE2_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
752 CPU_COREI7_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
754 CPU_L1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
756 CPU_K1OM_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
758 CPU_K6_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
760 CPU_K6_2_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
762 CPU_ATHLON_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 1, 0 },
765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
768 CPU_K8_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
770 CPU_AMDFAM10_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
772 CPU_BDVER1_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
774 CPU_BDVER2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
776 CPU_BDVER3_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
778 CPU_BDVER4_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
780 CPU_BTVER1_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
782 CPU_BTVER2_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
784 CPU_8087_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
786 CPU_287_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
788 CPU_387_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
790 CPU_ANY87_FLAGS
, 0, 1 },
791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
792 CPU_MMX_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
794 CPU_3DNOWA_FLAGS
, 0, 1 },
795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
796 CPU_SSE_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
798 CPU_SSE2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
802 CPU_SSSE3_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_1_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
808 CPU_SSE4_2_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
810 CPU_ANY_SSE_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
812 CPU_AVX_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
814 CPU_AVX2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512F_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512CD_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512ER_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
822 CPU_AVX512PF_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
824 CPU_ANY_AVX_FLAGS
, 0, 1 },
825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
826 CPU_VMX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
828 CPU_VMFUNC_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
830 CPU_SMX_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVE_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
834 CPU_XSAVEOPT_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
836 CPU_AES_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
840 CPU_PCLMUL_FLAGS
, 1, 0 },
841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
842 CPU_FSGSBASE_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
844 CPU_RDRND_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
846 CPU_F16C_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
848 CPU_BMI2_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
850 CPU_FMA_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
852 CPU_FMA4_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
854 CPU_XOP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
856 CPU_LWP_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
858 CPU_MOVBE_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
860 CPU_CX16_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
862 CPU_EPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
864 CPU_LZCNT_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
866 CPU_HLE_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
868 CPU_RTM_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
870 CPU_INVPCID_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
872 CPU_CLFLUSH_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
874 CPU_NOP_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
876 CPU_SYSCALL_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
878 CPU_RDTSCP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOW_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
882 CPU_3DNOWA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
884 CPU_PADLOCK_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 1, 0 },
887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
888 CPU_SVME_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
890 CPU_SSE4A_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
892 CPU_ABM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
894 CPU_BMI_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
896 CPU_TBM_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
898 CPU_ADX_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
900 CPU_RDSEED_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
902 CPU_PRFCHW_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
904 CPU_SMAP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
906 CPU_MPX_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
908 CPU_SHA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
910 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVEC_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
914 CPU_XSAVES_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
916 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
918 CPU_SE1_FLAGS
, 0, 0 },
922 /* Like s_lcomm_internal in gas/read.c but the alignment string
923 is allowed to be optional. */
926 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
933 && *input_line_pointer
== ',')
935 align
= parse_align (needs_align
- 1);
937 if (align
== (addressT
) -1)
952 bss_alloc (symbolP
, size
, align
);
957 pe_lcomm (int needs_align
)
959 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
963 const pseudo_typeS md_pseudo_table
[] =
965 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
966 {"align", s_align_bytes
, 0},
968 {"align", s_align_ptwo
, 0},
970 {"arch", set_cpu_arch
, 0},
974 {"lcomm", pe_lcomm
, 1},
976 {"ffloat", float_cons
, 'f'},
977 {"dfloat", float_cons
, 'd'},
978 {"tfloat", float_cons
, 'x'},
980 {"slong", signed_cons
, 4},
981 {"noopt", s_ignore
, 0},
982 {"optim", s_ignore
, 0},
983 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
984 {"code16", set_code_flag
, CODE_16BIT
},
985 {"code32", set_code_flag
, CODE_32BIT
},
986 {"code64", set_code_flag
, CODE_64BIT
},
987 {"intel_syntax", set_intel_syntax
, 1},
988 {"att_syntax", set_intel_syntax
, 0},
989 {"intel_mnemonic", set_intel_mnemonic
, 1},
990 {"att_mnemonic", set_intel_mnemonic
, 0},
991 {"allow_index_reg", set_allow_index_reg
, 1},
992 {"disallow_index_reg", set_allow_index_reg
, 0},
993 {"sse_check", set_check
, 0},
994 {"operand_check", set_check
, 1},
995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
996 {"largecomm", handle_large_common
, 0},
998 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
999 {"loc", dwarf2_directive_loc
, 0},
1000 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1003 {"secrel32", pe_directive_secrel
, 0},
1008 /* For interface with expression (). */
1009 extern char *input_line_pointer
;
1011 /* Hash table for instruction mnemonic lookup. */
1012 static struct hash_control
*op_hash
;
1014 /* Hash table for register lookup. */
1015 static struct hash_control
*reg_hash
;
1018 i386_align_code (fragS
*fragP
, int count
)
1020 /* Various efficient no-op patterns for aligning code labels.
1021 Note: Don't try to assemble the instructions in the comments.
1022 0L and 0w are not legal. */
1023 static const char f32_1
[] =
1025 static const char f32_2
[] =
1026 {0x66,0x90}; /* xchg %ax,%ax */
1027 static const char f32_3
[] =
1028 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1029 static const char f32_4
[] =
1030 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1031 static const char f32_5
[] =
1033 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1034 static const char f32_6
[] =
1035 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1036 static const char f32_7
[] =
1037 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1038 static const char f32_8
[] =
1040 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1041 static const char f32_9
[] =
1042 {0x89,0xf6, /* movl %esi,%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_10
[] =
1045 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f32_11
[] =
1048 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_12
[] =
1051 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1052 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1053 static const char f32_13
[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1055 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1056 static const char f32_14
[] =
1057 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1058 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1059 static const char f16_3
[] =
1060 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1061 static const char f16_4
[] =
1062 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1063 static const char f16_5
[] =
1065 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1066 static const char f16_6
[] =
1067 {0x89,0xf6, /* mov %si,%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1069 static const char f16_7
[] =
1070 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1071 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1072 static const char f16_8
[] =
1073 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1074 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1075 static const char jump_31
[] =
1076 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1077 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1078 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1079 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1080 static const char *const f32_patt
[] = {
1081 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1082 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1084 static const char *const f16_patt
[] = {
1085 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1087 /* nopl (%[re]ax) */
1088 static const char alt_3
[] =
1090 /* nopl 0(%[re]ax) */
1091 static const char alt_4
[] =
1092 {0x0f,0x1f,0x40,0x00};
1093 /* nopl 0(%[re]ax,%[re]ax,1) */
1094 static const char alt_5
[] =
1095 {0x0f,0x1f,0x44,0x00,0x00};
1096 /* nopw 0(%[re]ax,%[re]ax,1) */
1097 static const char alt_6
[] =
1098 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1099 /* nopl 0L(%[re]ax) */
1100 static const char alt_7
[] =
1101 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1102 /* nopl 0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_8
[] =
1104 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 /* nopw 0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_9
[] =
1107 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1108 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1109 static const char alt_10
[] =
1110 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_11
[] =
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_long_12
[] =
1122 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_long_13
[] =
1131 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_14
[] =
1142 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_15
[] =
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 /* nopl 0(%[re]ax,%[re]ax,1)
1157 nopw 0(%[re]ax,%[re]ax,1) */
1158 static const char alt_short_11
[] =
1159 {0x0f,0x1f,0x44,0x00,0x00,
1160 0x66,0x0f,0x1f,0x44,0x00,0x00};
1161 /* nopw 0(%[re]ax,%[re]ax,1)
1162 nopw 0(%[re]ax,%[re]ax,1) */
1163 static const char alt_short_12
[] =
1164 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1165 0x66,0x0f,0x1f,0x44,0x00,0x00};
1166 /* nopw 0(%[re]ax,%[re]ax,1)
1168 static const char alt_short_13
[] =
1169 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1170 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1173 static const char alt_short_14
[] =
1174 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1175 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1177 nopl 0L(%[re]ax,%[re]ax,1) */
1178 static const char alt_short_15
[] =
1179 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1180 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1181 static const char *const alt_short_patt
[] = {
1182 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1183 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1184 alt_short_14
, alt_short_15
1186 static const char *const alt_long_patt
[] = {
1187 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1188 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1189 alt_long_14
, alt_long_15
1192 /* Only align for at least a positive non-zero boundary. */
1193 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1196 /* We need to decide which NOP sequence to use for 32bit and
1197 64bit. When -mtune= is used:
1199 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1200 PROCESSOR_GENERIC32, f32_patt will be used.
1201 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1202 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1203 PROCESSOR_GENERIC64, alt_long_patt will be used.
1204 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1205 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1208 When -mtune= isn't used, alt_long_patt will be used if
1209 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1212 When -march= or .arch is used, we can't use anything beyond
1213 cpu_arch_isa_flags. */
1215 if (flag_code
== CODE_16BIT
)
1219 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1221 /* Adjust jump offset. */
1222 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1225 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1226 f16_patt
[count
- 1], count
);
1230 const char *const *patt
= NULL
;
1232 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1234 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1235 switch (cpu_arch_tune
)
1237 case PROCESSOR_UNKNOWN
:
1238 /* We use cpu_arch_isa_flags to check if we SHOULD
1239 optimize with nops. */
1240 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1241 patt
= alt_long_patt
;
1245 case PROCESSOR_PENTIUM4
:
1246 case PROCESSOR_NOCONA
:
1247 case PROCESSOR_CORE
:
1248 case PROCESSOR_CORE2
:
1249 case PROCESSOR_COREI7
:
1250 case PROCESSOR_L1OM
:
1251 case PROCESSOR_K1OM
:
1252 case PROCESSOR_GENERIC64
:
1253 patt
= alt_long_patt
;
1256 case PROCESSOR_ATHLON
:
1258 case PROCESSOR_AMDFAM10
:
1261 patt
= alt_short_patt
;
1263 case PROCESSOR_I386
:
1264 case PROCESSOR_I486
:
1265 case PROCESSOR_PENTIUM
:
1266 case PROCESSOR_PENTIUMPRO
:
1267 case PROCESSOR_GENERIC32
:
1274 switch (fragP
->tc_frag_data
.tune
)
1276 case PROCESSOR_UNKNOWN
:
1277 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1278 PROCESSOR_UNKNOWN. */
1282 case PROCESSOR_I386
:
1283 case PROCESSOR_I486
:
1284 case PROCESSOR_PENTIUM
:
1286 case PROCESSOR_ATHLON
:
1288 case PROCESSOR_AMDFAM10
:
1291 case PROCESSOR_GENERIC32
:
1292 /* We use cpu_arch_isa_flags to check if we CAN optimize
1294 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1295 patt
= alt_short_patt
;
1299 case PROCESSOR_PENTIUMPRO
:
1300 case PROCESSOR_PENTIUM4
:
1301 case PROCESSOR_NOCONA
:
1302 case PROCESSOR_CORE
:
1303 case PROCESSOR_CORE2
:
1304 case PROCESSOR_COREI7
:
1305 case PROCESSOR_L1OM
:
1306 case PROCESSOR_K1OM
:
1307 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1308 patt
= alt_long_patt
;
1312 case PROCESSOR_GENERIC64
:
1313 patt
= alt_long_patt
;
1318 if (patt
== f32_patt
)
1320 /* If the padding is less than 15 bytes, we use the normal
1321 ones. Otherwise, we use a jump instruction and adjust
1325 /* For 64bit, the limit is 3 bytes. */
1326 if (flag_code
== CODE_64BIT
1327 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1332 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1333 patt
[count
- 1], count
);
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1338 /* Adjust jump offset. */
1339 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1344 /* Maximum length of an instruction is 15 byte. If the
1345 padding is greater than 15 bytes and we don't use jump,
1346 we have to break it into smaller pieces. */
1347 int padding
= count
;
1348 while (padding
> 15)
1351 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1356 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1357 patt
[padding
- 1], padding
);
1360 fragP
->fr_var
= count
;
1364 operand_type_all_zero (const union i386_operand_type
*x
)
1366 switch (ARRAY_SIZE(x
->array
))
1375 return !x
->array
[0];
1382 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1384 switch (ARRAY_SIZE(x
->array
))
1399 operand_type_equal (const union i386_operand_type
*x
,
1400 const union i386_operand_type
*y
)
1402 switch (ARRAY_SIZE(x
->array
))
1405 if (x
->array
[2] != y
->array
[2])
1408 if (x
->array
[1] != y
->array
[1])
1411 return x
->array
[0] == y
->array
[0];
1419 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1421 switch (ARRAY_SIZE(x
->array
))
1430 return !x
->array
[0];
1437 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1439 switch (ARRAY_SIZE(x
->array
))
1454 cpu_flags_equal (const union i386_cpu_flags
*x
,
1455 const union i386_cpu_flags
*y
)
1457 switch (ARRAY_SIZE(x
->array
))
1460 if (x
->array
[2] != y
->array
[2])
1463 if (x
->array
[1] != y
->array
[1])
1466 return x
->array
[0] == y
->array
[0];
1474 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1476 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1477 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1480 static INLINE i386_cpu_flags
1481 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1483 switch (ARRAY_SIZE (x
.array
))
1486 x
.array
[2] &= y
.array
[2];
1488 x
.array
[1] &= y
.array
[1];
1490 x
.array
[0] &= y
.array
[0];
1498 static INLINE i386_cpu_flags
1499 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1501 switch (ARRAY_SIZE (x
.array
))
1504 x
.array
[2] |= y
.array
[2];
1506 x
.array
[1] |= y
.array
[1];
1508 x
.array
[0] |= y
.array
[0];
1516 static INLINE i386_cpu_flags
1517 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1519 switch (ARRAY_SIZE (x
.array
))
1522 x
.array
[2] &= ~y
.array
[2];
1524 x
.array
[1] &= ~y
.array
[1];
1526 x
.array
[0] &= ~y
.array
[0];
1534 #define CPU_FLAGS_ARCH_MATCH 0x1
1535 #define CPU_FLAGS_64BIT_MATCH 0x2
1536 #define CPU_FLAGS_AES_MATCH 0x4
1537 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1538 #define CPU_FLAGS_AVX_MATCH 0x10
1540 #define CPU_FLAGS_32BIT_MATCH \
1541 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1542 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1543 #define CPU_FLAGS_PERFECT_MATCH \
1544 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1546 /* Return CPU flags match bits. */
1549 cpu_flags_match (const insn_template
*t
)
1551 i386_cpu_flags x
= t
->cpu_flags
;
1552 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1554 x
.bitfield
.cpu64
= 0;
1555 x
.bitfield
.cpuno64
= 0;
1557 if (cpu_flags_all_zero (&x
))
1559 /* This instruction is available on all archs. */
1560 match
|= CPU_FLAGS_32BIT_MATCH
;
1564 /* This instruction is available only on some archs. */
1565 i386_cpu_flags cpu
= cpu_arch_flags
;
1567 cpu
.bitfield
.cpu64
= 0;
1568 cpu
.bitfield
.cpuno64
= 0;
1569 cpu
= cpu_flags_and (x
, cpu
);
1570 if (!cpu_flags_all_zero (&cpu
))
1572 if (x
.bitfield
.cpuavx
)
1574 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1575 if (cpu
.bitfield
.cpuavx
)
1577 /* Check SSE2AVX. */
1578 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1580 match
|= (CPU_FLAGS_ARCH_MATCH
1581 | CPU_FLAGS_AVX_MATCH
);
1583 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1584 match
|= CPU_FLAGS_AES_MATCH
;
1586 if (!x
.bitfield
.cpupclmul
1587 || cpu
.bitfield
.cpupclmul
)
1588 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1592 match
|= CPU_FLAGS_ARCH_MATCH
;
1595 match
|= CPU_FLAGS_32BIT_MATCH
;
1601 static INLINE i386_operand_type
1602 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1604 switch (ARRAY_SIZE (x
.array
))
1607 x
.array
[2] &= y
.array
[2];
1609 x
.array
[1] &= y
.array
[1];
1611 x
.array
[0] &= y
.array
[0];
1619 static INLINE i386_operand_type
1620 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1622 switch (ARRAY_SIZE (x
.array
))
1625 x
.array
[2] |= y
.array
[2];
1627 x
.array
[1] |= y
.array
[1];
1629 x
.array
[0] |= y
.array
[0];
1637 static INLINE i386_operand_type
1638 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1640 switch (ARRAY_SIZE (x
.array
))
1643 x
.array
[2] ^= y
.array
[2];
1645 x
.array
[1] ^= y
.array
[1];
1647 x
.array
[0] ^= y
.array
[0];
1655 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1656 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1657 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1658 static const i386_operand_type inoutportreg
1659 = OPERAND_TYPE_INOUTPORTREG
;
1660 static const i386_operand_type reg16_inoutportreg
1661 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1662 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1663 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1664 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1665 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1666 static const i386_operand_type anydisp
1667 = OPERAND_TYPE_ANYDISP
;
1668 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1669 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1670 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1671 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1672 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1673 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1674 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1675 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1676 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1677 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1678 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1679 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1680 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1681 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1692 operand_type_check (i386_operand_type t
, enum operand_type c
)
1697 return (t
.bitfield
.reg8
1700 || t
.bitfield
.reg64
);
1703 return (t
.bitfield
.imm8
1707 || t
.bitfield
.imm32s
1708 || t
.bitfield
.imm64
);
1711 return (t
.bitfield
.disp8
1712 || t
.bitfield
.disp16
1713 || t
.bitfield
.disp32
1714 || t
.bitfield
.disp32s
1715 || t
.bitfield
.disp64
);
1718 return (t
.bitfield
.disp8
1719 || t
.bitfield
.disp16
1720 || t
.bitfield
.disp32
1721 || t
.bitfield
.disp32s
1722 || t
.bitfield
.disp64
1723 || t
.bitfield
.baseindex
);
1732 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1733 operand J for instruction template T. */
1736 match_reg_size (const insn_template
*t
, unsigned int j
)
1738 return !((i
.types
[j
].bitfield
.byte
1739 && !t
->operand_types
[j
].bitfield
.byte
)
1740 || (i
.types
[j
].bitfield
.word
1741 && !t
->operand_types
[j
].bitfield
.word
)
1742 || (i
.types
[j
].bitfield
.dword
1743 && !t
->operand_types
[j
].bitfield
.dword
)
1744 || (i
.types
[j
].bitfield
.qword
1745 && !t
->operand_types
[j
].bitfield
.qword
));
1748 /* Return 1 if there is no conflict in any size on operand J for
1749 instruction template T. */
1752 match_mem_size (const insn_template
*t
, unsigned int j
)
1754 return (match_reg_size (t
, j
)
1755 && !((i
.types
[j
].bitfield
.unspecified
1756 && !t
->operand_types
[j
].bitfield
.unspecified
)
1757 || (i
.types
[j
].bitfield
.fword
1758 && !t
->operand_types
[j
].bitfield
.fword
)
1759 || (i
.types
[j
].bitfield
.tbyte
1760 && !t
->operand_types
[j
].bitfield
.tbyte
)
1761 || (i
.types
[j
].bitfield
.xmmword
1762 && !t
->operand_types
[j
].bitfield
.xmmword
)
1763 || (i
.types
[j
].bitfield
.ymmword
1764 && !t
->operand_types
[j
].bitfield
.ymmword
)
1765 || (i
.types
[j
].bitfield
.zmmword
1766 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1769 /* Return 1 if there is no size conflict on any operands for
1770 instruction template T. */
1773 operand_size_match (const insn_template
*t
)
1778 /* Don't check jump instructions. */
1779 if (t
->opcode_modifier
.jump
1780 || t
->opcode_modifier
.jumpbyte
1781 || t
->opcode_modifier
.jumpdword
1782 || t
->opcode_modifier
.jumpintersegment
)
1785 /* Check memory and accumulator operand size. */
1786 for (j
= 0; j
< i
.operands
; j
++)
1788 if (t
->operand_types
[j
].bitfield
.anysize
)
1791 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1797 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1806 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1809 i
.error
= operand_size_mismatch
;
1813 /* Check reverse. */
1814 gas_assert (i
.operands
== 2);
1817 for (j
= 0; j
< 2; j
++)
1819 if (t
->operand_types
[j
].bitfield
.acc
1820 && !match_reg_size (t
, j
? 0 : 1))
1823 if (i
.types
[j
].bitfield
.mem
1824 && !match_mem_size (t
, j
? 0 : 1))
1832 operand_type_match (i386_operand_type overlap
,
1833 i386_operand_type given
)
1835 i386_operand_type temp
= overlap
;
1837 temp
.bitfield
.jumpabsolute
= 0;
1838 temp
.bitfield
.unspecified
= 0;
1839 temp
.bitfield
.byte
= 0;
1840 temp
.bitfield
.word
= 0;
1841 temp
.bitfield
.dword
= 0;
1842 temp
.bitfield
.fword
= 0;
1843 temp
.bitfield
.qword
= 0;
1844 temp
.bitfield
.tbyte
= 0;
1845 temp
.bitfield
.xmmword
= 0;
1846 temp
.bitfield
.ymmword
= 0;
1847 temp
.bitfield
.zmmword
= 0;
1848 if (operand_type_all_zero (&temp
))
1851 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1852 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1856 i
.error
= operand_type_mismatch
;
1860 /* If given types g0 and g1 are registers they must be of the same type
1861 unless the expected operand type register overlap is null.
1862 Note that Acc in a template matches every size of reg. */
1865 operand_type_register_match (i386_operand_type m0
,
1866 i386_operand_type g0
,
1867 i386_operand_type t0
,
1868 i386_operand_type m1
,
1869 i386_operand_type g1
,
1870 i386_operand_type t1
)
1872 if (!operand_type_check (g0
, reg
))
1875 if (!operand_type_check (g1
, reg
))
1878 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1879 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1880 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1881 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1884 if (m0
.bitfield
.acc
)
1886 t0
.bitfield
.reg8
= 1;
1887 t0
.bitfield
.reg16
= 1;
1888 t0
.bitfield
.reg32
= 1;
1889 t0
.bitfield
.reg64
= 1;
1892 if (m1
.bitfield
.acc
)
1894 t1
.bitfield
.reg8
= 1;
1895 t1
.bitfield
.reg16
= 1;
1896 t1
.bitfield
.reg32
= 1;
1897 t1
.bitfield
.reg64
= 1;
1900 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1901 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1902 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1903 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1906 i
.error
= register_type_mismatch
;
1911 static INLINE
unsigned int
1912 register_number (const reg_entry
*r
)
1914 unsigned int nr
= r
->reg_num
;
1916 if (r
->reg_flags
& RegRex
)
1922 static INLINE
unsigned int
1923 mode_from_disp_size (i386_operand_type t
)
1925 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1927 else if (t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
)
1936 fits_in_signed_byte (offsetT num
)
1938 return (num
>= -128) && (num
<= 127);
1942 fits_in_unsigned_byte (offsetT num
)
1944 return (num
& 0xff) == num
;
1948 fits_in_unsigned_word (offsetT num
)
1950 return (num
& 0xffff) == num
;
1954 fits_in_signed_word (offsetT num
)
1956 return (-32768 <= num
) && (num
<= 32767);
1960 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1965 return (!(((offsetT
) -1 << 31) & num
)
1966 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1968 } /* fits_in_signed_long() */
1971 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1976 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1978 } /* fits_in_unsigned_long() */
1981 fits_in_vec_disp8 (offsetT num
)
1983 int shift
= i
.memshift
;
1989 mask
= (1 << shift
) - 1;
1991 /* Return 0 if NUM isn't properly aligned. */
1995 /* Check if NUM will fit in 8bit after shift. */
1996 return fits_in_signed_byte (num
>> shift
);
2000 fits_in_imm4 (offsetT num
)
2002 return (num
& 0xf) == num
;
2005 static i386_operand_type
2006 smallest_imm_type (offsetT num
)
2008 i386_operand_type t
;
2010 operand_type_set (&t
, 0);
2011 t
.bitfield
.imm64
= 1;
2013 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2015 /* This code is disabled on the 486 because all the Imm1 forms
2016 in the opcode table are slower on the i486. They're the
2017 versions with the implicitly specified single-position
2018 displacement, which has another syntax if you really want to
2020 t
.bitfield
.imm1
= 1;
2021 t
.bitfield
.imm8
= 1;
2022 t
.bitfield
.imm8s
= 1;
2023 t
.bitfield
.imm16
= 1;
2024 t
.bitfield
.imm32
= 1;
2025 t
.bitfield
.imm32s
= 1;
2027 else if (fits_in_signed_byte (num
))
2029 t
.bitfield
.imm8
= 1;
2030 t
.bitfield
.imm8s
= 1;
2031 t
.bitfield
.imm16
= 1;
2032 t
.bitfield
.imm32
= 1;
2033 t
.bitfield
.imm32s
= 1;
2035 else if (fits_in_unsigned_byte (num
))
2037 t
.bitfield
.imm8
= 1;
2038 t
.bitfield
.imm16
= 1;
2039 t
.bitfield
.imm32
= 1;
2040 t
.bitfield
.imm32s
= 1;
2042 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2044 t
.bitfield
.imm16
= 1;
2045 t
.bitfield
.imm32
= 1;
2046 t
.bitfield
.imm32s
= 1;
2048 else if (fits_in_signed_long (num
))
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_unsigned_long (num
))
2054 t
.bitfield
.imm32
= 1;
2060 offset_in_range (offsetT val
, int size
)
2066 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2067 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2068 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2070 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2076 /* If BFD64, sign extend val for 32bit address mode. */
2077 if (flag_code
!= CODE_64BIT
2078 || i
.prefix
[ADDR_PREFIX
])
2079 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2080 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2083 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2085 char buf1
[40], buf2
[40];
2087 sprint_value (buf1
, val
);
2088 sprint_value (buf2
, val
& mask
);
2089 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2103 a. PREFIX_EXIST if attempting to add a prefix where one from the
2104 same class already exists.
2105 b. PREFIX_LOCK if lock prefix is added.
2106 c. PREFIX_REP if rep/repne prefix is added.
2107 d. PREFIX_OTHER if other prefix is added.
2110 static enum PREFIX_GROUP
2111 add_prefix (unsigned int prefix
)
2113 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2116 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2117 && flag_code
== CODE_64BIT
)
2119 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2120 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2121 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2132 case CS_PREFIX_OPCODE
:
2133 case DS_PREFIX_OPCODE
:
2134 case ES_PREFIX_OPCODE
:
2135 case FS_PREFIX_OPCODE
:
2136 case GS_PREFIX_OPCODE
:
2137 case SS_PREFIX_OPCODE
:
2141 case REPNE_PREFIX_OPCODE
:
2142 case REPE_PREFIX_OPCODE
:
2147 case LOCK_PREFIX_OPCODE
:
2156 case ADDR_PREFIX_OPCODE
:
2160 case DATA_PREFIX_OPCODE
:
2164 if (i
.prefix
[q
] != 0)
2172 i
.prefix
[q
] |= prefix
;
2175 as_bad (_("same type of prefix used twice"));
2181 update_code_flag (int value
, int check
)
2183 PRINTF_LIKE ((*as_error
));
2185 flag_code
= (enum flag_code
) value
;
2186 if (flag_code
== CODE_64BIT
)
2188 cpu_arch_flags
.bitfield
.cpu64
= 1;
2189 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2193 cpu_arch_flags
.bitfield
.cpu64
= 0;
2194 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2196 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2199 as_error
= as_fatal
;
2202 (*as_error
) (_("64bit mode not supported on `%s'."),
2203 cpu_arch_name
? cpu_arch_name
: default_arch
);
2205 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2208 as_error
= as_fatal
;
2211 (*as_error
) (_("32bit mode not supported on `%s'."),
2212 cpu_arch_name
? cpu_arch_name
: default_arch
);
2214 stackop_size
= '\0';
2218 set_code_flag (int value
)
2220 update_code_flag (value
, 0);
2224 set_16bit_gcc_code_flag (int new_code_flag
)
2226 flag_code
= (enum flag_code
) new_code_flag
;
2227 if (flag_code
!= CODE_16BIT
)
2229 cpu_arch_flags
.bitfield
.cpu64
= 0;
2230 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2231 stackop_size
= LONG_MNEM_SUFFIX
;
2235 set_intel_syntax (int syntax_flag
)
2237 /* Find out if register prefixing is specified. */
2238 int ask_naked_reg
= 0;
2241 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2243 char *string
= input_line_pointer
;
2244 int e
= get_symbol_end ();
2246 if (strcmp (string
, "prefix") == 0)
2248 else if (strcmp (string
, "noprefix") == 0)
2251 as_bad (_("bad argument to syntax directive."));
2252 *input_line_pointer
= e
;
2254 demand_empty_rest_of_line ();
2256 intel_syntax
= syntax_flag
;
2258 if (ask_naked_reg
== 0)
2259 allow_naked_reg
= (intel_syntax
2260 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2262 allow_naked_reg
= (ask_naked_reg
< 0);
2264 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2266 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2267 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2268 register_prefix
= allow_naked_reg
? "" : "%";
2272 set_intel_mnemonic (int mnemonic_flag
)
2274 intel_mnemonic
= mnemonic_flag
;
2278 set_allow_index_reg (int flag
)
2280 allow_index_reg
= flag
;
2284 set_check (int what
)
2286 enum check_kind
*kind
;
2291 kind
= &operand_check
;
2302 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2304 char *string
= input_line_pointer
;
2305 int e
= get_symbol_end ();
2307 if (strcmp (string
, "none") == 0)
2309 else if (strcmp (string
, "warning") == 0)
2310 *kind
= check_warning
;
2311 else if (strcmp (string
, "error") == 0)
2312 *kind
= check_error
;
2314 as_bad (_("bad argument to %s_check directive."), str
);
2315 *input_line_pointer
= e
;
2318 as_bad (_("missing argument for %s_check directive"), str
);
2320 demand_empty_rest_of_line ();
2324 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2325 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2328 static const char *arch
;
2330 /* Intel LIOM is only supported on ELF. */
2336 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2337 use default_arch. */
2338 arch
= cpu_arch_name
;
2340 arch
= default_arch
;
2343 /* If we are targeting Intel L1OM, we must enable it. */
2344 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2345 || new_flag
.bitfield
.cpul1om
)
2348 /* If we are targeting Intel K1OM, we must enable it. */
2349 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2350 || new_flag
.bitfield
.cpuk1om
)
2353 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2358 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2362 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2364 char *string
= input_line_pointer
;
2365 int e
= get_symbol_end ();
2367 i386_cpu_flags flags
;
2369 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2371 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2373 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2377 cpu_arch_name
= cpu_arch
[j
].name
;
2378 cpu_sub_arch_name
= NULL
;
2379 cpu_arch_flags
= cpu_arch
[j
].flags
;
2380 if (flag_code
== CODE_64BIT
)
2382 cpu_arch_flags
.bitfield
.cpu64
= 1;
2383 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2387 cpu_arch_flags
.bitfield
.cpu64
= 0;
2388 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2390 cpu_arch_isa
= cpu_arch
[j
].type
;
2391 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2392 if (!cpu_arch_tune_set
)
2394 cpu_arch_tune
= cpu_arch_isa
;
2395 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2400 if (!cpu_arch
[j
].negated
)
2401 flags
= cpu_flags_or (cpu_arch_flags
,
2404 flags
= cpu_flags_and_not (cpu_arch_flags
,
2406 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2408 if (cpu_sub_arch_name
)
2410 char *name
= cpu_sub_arch_name
;
2411 cpu_sub_arch_name
= concat (name
,
2413 (const char *) NULL
);
2417 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2418 cpu_arch_flags
= flags
;
2419 cpu_arch_isa_flags
= flags
;
2421 *input_line_pointer
= e
;
2422 demand_empty_rest_of_line ();
2426 if (j
>= ARRAY_SIZE (cpu_arch
))
2427 as_bad (_("no such architecture: `%s'"), string
);
2429 *input_line_pointer
= e
;
2432 as_bad (_("missing cpu architecture"));
2434 no_cond_jump_promotion
= 0;
2435 if (*input_line_pointer
== ','
2436 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2438 char *string
= ++input_line_pointer
;
2439 int e
= get_symbol_end ();
2441 if (strcmp (string
, "nojumps") == 0)
2442 no_cond_jump_promotion
= 1;
2443 else if (strcmp (string
, "jumps") == 0)
2446 as_bad (_("no such architecture modifier: `%s'"), string
);
2448 *input_line_pointer
= e
;
2451 demand_empty_rest_of_line ();
2454 enum bfd_architecture
2457 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2459 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2460 || flag_code
!= CODE_64BIT
)
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_arch_l1om
;
2464 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2466 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2467 || flag_code
!= CODE_64BIT
)
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_arch_k1om
;
2472 return bfd_arch_i386
;
2478 if (!strncmp (default_arch
, "x86_64", 6))
2480 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2482 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2483 || default_arch
[6] != '\0')
2484 as_fatal (_("Intel L1OM is 64bit ELF only"));
2485 return bfd_mach_l1om
;
2487 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2489 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2490 || default_arch
[6] != '\0')
2491 as_fatal (_("Intel K1OM is 64bit ELF only"));
2492 return bfd_mach_k1om
;
2494 else if (default_arch
[6] == '\0')
2495 return bfd_mach_x86_64
;
2497 return bfd_mach_x64_32
;
2499 else if (!strcmp (default_arch
, "i386"))
2500 return bfd_mach_i386_i386
;
2502 as_fatal (_("unknown architecture"));
2508 const char *hash_err
;
2510 /* Initialize op_hash hash table. */
2511 op_hash
= hash_new ();
2514 const insn_template
*optab
;
2515 templates
*core_optab
;
2517 /* Setup for loop. */
2519 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2520 core_optab
->start
= optab
;
2525 if (optab
->name
== NULL
2526 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2528 /* different name --> ship out current template list;
2529 add to hash table; & begin anew. */
2530 core_optab
->end
= optab
;
2531 hash_err
= hash_insert (op_hash
,
2533 (void *) core_optab
);
2536 as_fatal (_("can't hash %s: %s"),
2540 if (optab
->name
== NULL
)
2542 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2543 core_optab
->start
= optab
;
2548 /* Initialize reg_hash hash table. */
2549 reg_hash
= hash_new ();
2551 const reg_entry
*regtab
;
2552 unsigned int regtab_size
= i386_regtab_size
;
2554 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2556 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2558 as_fatal (_("can't hash %s: %s"),
2564 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2569 for (c
= 0; c
< 256; c
++)
2574 mnemonic_chars
[c
] = c
;
2575 register_chars
[c
] = c
;
2576 operand_chars
[c
] = c
;
2578 else if (ISLOWER (c
))
2580 mnemonic_chars
[c
] = c
;
2581 register_chars
[c
] = c
;
2582 operand_chars
[c
] = c
;
2584 else if (ISUPPER (c
))
2586 mnemonic_chars
[c
] = TOLOWER (c
);
2587 register_chars
[c
] = mnemonic_chars
[c
];
2588 operand_chars
[c
] = c
;
2590 else if (c
== '{' || c
== '}')
2591 operand_chars
[c
] = c
;
2593 if (ISALPHA (c
) || ISDIGIT (c
))
2594 identifier_chars
[c
] = c
;
2597 identifier_chars
[c
] = c
;
2598 operand_chars
[c
] = c
;
2603 identifier_chars
['@'] = '@';
2606 identifier_chars
['?'] = '?';
2607 operand_chars
['?'] = '?';
2609 digit_chars
['-'] = '-';
2610 mnemonic_chars
['_'] = '_';
2611 mnemonic_chars
['-'] = '-';
2612 mnemonic_chars
['.'] = '.';
2613 identifier_chars
['_'] = '_';
2614 identifier_chars
['.'] = '.';
2616 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2617 operand_chars
[(unsigned char) *p
] = *p
;
2620 if (flag_code
== CODE_64BIT
)
2622 #if defined (OBJ_COFF) && defined (TE_PE)
2623 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2626 x86_dwarf2_return_column
= 16;
2628 x86_cie_data_alignment
= -8;
2632 x86_dwarf2_return_column
= 8;
2633 x86_cie_data_alignment
= -4;
2638 i386_print_statistics (FILE *file
)
2640 hash_print_statistics (file
, "i386 opcode", op_hash
);
2641 hash_print_statistics (file
, "i386 register", reg_hash
);
2646 /* Debugging routines for md_assemble. */
2647 static void pte (insn_template
*);
2648 static void pt (i386_operand_type
);
2649 static void pe (expressionS
*);
2650 static void ps (symbolS
*);
2653 pi (char *line
, i386_insn
*x
)
2657 fprintf (stdout
, "%s: template ", line
);
2659 fprintf (stdout
, " address: base %s index %s scale %x\n",
2660 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2661 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2662 x
->log2_scale_factor
);
2663 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2664 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2665 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2666 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2667 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2668 (x
->rex
& REX_W
) != 0,
2669 (x
->rex
& REX_R
) != 0,
2670 (x
->rex
& REX_X
) != 0,
2671 (x
->rex
& REX_B
) != 0);
2672 for (j
= 0; j
< x
->operands
; j
++)
2674 fprintf (stdout
, " #%d: ", j
+ 1);
2676 fprintf (stdout
, "\n");
2677 if (x
->types
[j
].bitfield
.reg8
2678 || x
->types
[j
].bitfield
.reg16
2679 || x
->types
[j
].bitfield
.reg32
2680 || x
->types
[j
].bitfield
.reg64
2681 || x
->types
[j
].bitfield
.regmmx
2682 || x
->types
[j
].bitfield
.regxmm
2683 || x
->types
[j
].bitfield
.regymm
2684 || x
->types
[j
].bitfield
.regzmm
2685 || x
->types
[j
].bitfield
.sreg2
2686 || x
->types
[j
].bitfield
.sreg3
2687 || x
->types
[j
].bitfield
.control
2688 || x
->types
[j
].bitfield
.debug
2689 || x
->types
[j
].bitfield
.test
)
2690 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2691 if (operand_type_check (x
->types
[j
], imm
))
2693 if (operand_type_check (x
->types
[j
], disp
))
2694 pe (x
->op
[j
].disps
);
2699 pte (insn_template
*t
)
2702 fprintf (stdout
, " %d operands ", t
->operands
);
2703 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2704 if (t
->extension_opcode
!= None
)
2705 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2706 if (t
->opcode_modifier
.d
)
2707 fprintf (stdout
, "D");
2708 if (t
->opcode_modifier
.w
)
2709 fprintf (stdout
, "W");
2710 fprintf (stdout
, "\n");
2711 for (j
= 0; j
< t
->operands
; j
++)
2713 fprintf (stdout
, " #%d type ", j
+ 1);
2714 pt (t
->operand_types
[j
]);
2715 fprintf (stdout
, "\n");
2722 fprintf (stdout
, " operation %d\n", e
->X_op
);
2723 fprintf (stdout
, " add_number %ld (%lx)\n",
2724 (long) e
->X_add_number
, (long) e
->X_add_number
);
2725 if (e
->X_add_symbol
)
2727 fprintf (stdout
, " add_symbol ");
2728 ps (e
->X_add_symbol
);
2729 fprintf (stdout
, "\n");
2733 fprintf (stdout
, " op_symbol ");
2734 ps (e
->X_op_symbol
);
2735 fprintf (stdout
, "\n");
2742 fprintf (stdout
, "%s type %s%s",
2744 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2745 segment_name (S_GET_SEGMENT (s
)));
2748 static struct type_name
2750 i386_operand_type mask
;
2753 const type_names
[] =
2755 { OPERAND_TYPE_REG8
, "r8" },
2756 { OPERAND_TYPE_REG16
, "r16" },
2757 { OPERAND_TYPE_REG32
, "r32" },
2758 { OPERAND_TYPE_REG64
, "r64" },
2759 { OPERAND_TYPE_IMM8
, "i8" },
2760 { OPERAND_TYPE_IMM8
, "i8s" },
2761 { OPERAND_TYPE_IMM16
, "i16" },
2762 { OPERAND_TYPE_IMM32
, "i32" },
2763 { OPERAND_TYPE_IMM32S
, "i32s" },
2764 { OPERAND_TYPE_IMM64
, "i64" },
2765 { OPERAND_TYPE_IMM1
, "i1" },
2766 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2767 { OPERAND_TYPE_DISP8
, "d8" },
2768 { OPERAND_TYPE_DISP16
, "d16" },
2769 { OPERAND_TYPE_DISP32
, "d32" },
2770 { OPERAND_TYPE_DISP32S
, "d32s" },
2771 { OPERAND_TYPE_DISP64
, "d64" },
2772 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2773 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2774 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2775 { OPERAND_TYPE_CONTROL
, "control reg" },
2776 { OPERAND_TYPE_TEST
, "test reg" },
2777 { OPERAND_TYPE_DEBUG
, "debug reg" },
2778 { OPERAND_TYPE_FLOATREG
, "FReg" },
2779 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2780 { OPERAND_TYPE_SREG2
, "SReg2" },
2781 { OPERAND_TYPE_SREG3
, "SReg3" },
2782 { OPERAND_TYPE_ACC
, "Acc" },
2783 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2784 { OPERAND_TYPE_REGMMX
, "rMMX" },
2785 { OPERAND_TYPE_REGXMM
, "rXMM" },
2786 { OPERAND_TYPE_REGYMM
, "rYMM" },
2787 { OPERAND_TYPE_REGZMM
, "rZMM" },
2788 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2789 { OPERAND_TYPE_ESSEG
, "es" },
2793 pt (i386_operand_type t
)
2796 i386_operand_type a
;
2798 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2800 a
= operand_type_and (t
, type_names
[j
].mask
);
2801 if (!operand_type_all_zero (&a
))
2802 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2807 #endif /* DEBUG386 */
2809 static bfd_reloc_code_real_type
2810 reloc (unsigned int size
,
2814 bfd_reloc_code_real_type other
)
2816 if (other
!= NO_RELOC
)
2818 reloc_howto_type
*rel
;
2823 case BFD_RELOC_X86_64_GOT32
:
2824 return BFD_RELOC_X86_64_GOT64
;
2826 case BFD_RELOC_X86_64_PLTOFF64
:
2827 return BFD_RELOC_X86_64_PLTOFF64
;
2829 case BFD_RELOC_X86_64_GOTPC32
:
2830 other
= BFD_RELOC_X86_64_GOTPC64
;
2832 case BFD_RELOC_X86_64_GOTPCREL
:
2833 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2835 case BFD_RELOC_X86_64_TPOFF32
:
2836 other
= BFD_RELOC_X86_64_TPOFF64
;
2838 case BFD_RELOC_X86_64_DTPOFF32
:
2839 other
= BFD_RELOC_X86_64_DTPOFF64
;
2845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2846 if (other
== BFD_RELOC_SIZE32
)
2849 return BFD_RELOC_SIZE64
;
2851 as_bad (_("there are no pc-relative size relocations"));
2855 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2856 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2859 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2861 as_bad (_("unknown relocation (%u)"), other
);
2862 else if (size
!= bfd_get_reloc_size (rel
))
2863 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2864 bfd_get_reloc_size (rel
),
2866 else if (pcrel
&& !rel
->pc_relative
)
2867 as_bad (_("non-pc-relative relocation for pc-relative field"));
2868 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2870 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2872 as_bad (_("relocated field and relocation type differ in signedness"));
2881 as_bad (_("there are no unsigned pc-relative relocations"));
2884 case 1: return BFD_RELOC_8_PCREL
;
2885 case 2: return BFD_RELOC_16_PCREL
;
2886 case 4: return (bnd_prefix
&& object_64bit
2887 ? BFD_RELOC_X86_64_PC32_BND
2888 : BFD_RELOC_32_PCREL
);
2889 case 8: return BFD_RELOC_64_PCREL
;
2891 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2898 case 4: return BFD_RELOC_X86_64_32S
;
2903 case 1: return BFD_RELOC_8
;
2904 case 2: return BFD_RELOC_16
;
2905 case 4: return BFD_RELOC_32
;
2906 case 8: return BFD_RELOC_64
;
2908 as_bad (_("cannot do %s %u byte relocation"),
2909 sign
> 0 ? "signed" : "unsigned", size
);
2915 /* Here we decide which fixups can be adjusted to make them relative to
2916 the beginning of the section instead of the symbol. Basically we need
2917 to make sure that the dynamic relocations are done correctly, so in
2918 some cases we force the original symbol to be used. */
2921 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2927 /* Don't adjust pc-relative references to merge sections in 64-bit
2929 if (use_rela_relocations
2930 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2934 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2935 and changed later by validate_fix. */
2936 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2937 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2940 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2941 for size relocations. */
2942 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2943 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2944 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2945 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2946 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2948 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2949 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2950 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2951 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2952 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2953 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2954 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2955 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2956 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2963 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2964 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2965 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2968 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2969 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2970 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2971 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2978 intel_float_operand (const char *mnemonic
)
2980 /* Note that the value returned is meaningful only for opcodes with (memory)
2981 operands, hence the code here is free to improperly handle opcodes that
2982 have no operands (for better performance and smaller code). */
2984 if (mnemonic
[0] != 'f')
2985 return 0; /* non-math */
2987 switch (mnemonic
[1])
2989 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2990 the fs segment override prefix not currently handled because no
2991 call path can make opcodes without operands get here */
2993 return 2 /* integer op */;
2995 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2996 return 3; /* fldcw/fldenv */
2999 if (mnemonic
[2] != 'o' /* fnop */)
3000 return 3; /* non-waiting control op */
3003 if (mnemonic
[2] == 's')
3004 return 3; /* frstor/frstpm */
3007 if (mnemonic
[2] == 'a')
3008 return 3; /* fsave */
3009 if (mnemonic
[2] == 't')
3011 switch (mnemonic
[3])
3013 case 'c': /* fstcw */
3014 case 'd': /* fstdw */
3015 case 'e': /* fstenv */
3016 case 's': /* fsts[gw] */
3022 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3023 return 0; /* fxsave/fxrstor are not really math ops */
3030 /* Build the VEX prefix. */
3033 build_vex_prefix (const insn_template
*t
)
3035 unsigned int register_specifier
;
3036 unsigned int implied_prefix
;
3037 unsigned int vector_length
;
3039 /* Check register specifier. */
3040 if (i
.vex
.register_specifier
)
3042 register_specifier
=
3043 ~register_number (i
.vex
.register_specifier
) & 0xf;
3044 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3047 register_specifier
= 0xf;
3049 /* Use 2-byte VEX prefix by swappping destination and source
3052 && i
.operands
== i
.reg_operands
3053 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3054 && i
.tm
.opcode_modifier
.s
3057 unsigned int xchg
= i
.operands
- 1;
3058 union i386_op temp_op
;
3059 i386_operand_type temp_type
;
3061 temp_type
= i
.types
[xchg
];
3062 i
.types
[xchg
] = i
.types
[0];
3063 i
.types
[0] = temp_type
;
3064 temp_op
= i
.op
[xchg
];
3065 i
.op
[xchg
] = i
.op
[0];
3068 gas_assert (i
.rm
.mode
== 3);
3072 i
.rm
.regmem
= i
.rm
.reg
;
3075 /* Use the next insn. */
3079 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3080 vector_length
= avxscalar
;
3082 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3084 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3089 case DATA_PREFIX_OPCODE
:
3092 case REPE_PREFIX_OPCODE
:
3095 case REPNE_PREFIX_OPCODE
:
3102 /* Use 2-byte VEX prefix if possible. */
3103 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3104 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3105 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3107 /* 2-byte VEX prefix. */
3111 i
.vex
.bytes
[0] = 0xc5;
3113 /* Check the REX.R bit. */
3114 r
= (i
.rex
& REX_R
) ? 0 : 1;
3115 i
.vex
.bytes
[1] = (r
<< 7
3116 | register_specifier
<< 3
3117 | vector_length
<< 2
3122 /* 3-byte VEX prefix. */
3127 switch (i
.tm
.opcode_modifier
.vexopcode
)
3131 i
.vex
.bytes
[0] = 0xc4;
3135 i
.vex
.bytes
[0] = 0xc4;
3139 i
.vex
.bytes
[0] = 0xc4;
3143 i
.vex
.bytes
[0] = 0x8f;
3147 i
.vex
.bytes
[0] = 0x8f;
3151 i
.vex
.bytes
[0] = 0x8f;
3157 /* The high 3 bits of the second VEX byte are 1's compliment
3158 of RXB bits from REX. */
3159 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3161 /* Check the REX.W bit. */
3162 w
= (i
.rex
& REX_W
) ? 1 : 0;
3163 if (i
.tm
.opcode_modifier
.vexw
)
3168 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3172 i
.vex
.bytes
[2] = (w
<< 7
3173 | register_specifier
<< 3
3174 | vector_length
<< 2
3179 /* Build the EVEX prefix. */
3182 build_evex_prefix (void)
3184 unsigned int register_specifier
;
3185 unsigned int implied_prefix
;
3187 rex_byte vrex_used
= 0;
3189 /* Check register specifier. */
3190 if (i
.vex
.register_specifier
)
3192 gas_assert ((i
.vrex
& REX_X
) == 0);
3194 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3195 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3196 register_specifier
+= 8;
3197 /* The upper 16 registers are encoded in the fourth byte of the
3199 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3200 i
.vex
.bytes
[3] = 0x8;
3201 register_specifier
= ~register_specifier
& 0xf;
3205 register_specifier
= 0xf;
3207 /* Encode upper 16 vector index register in the fourth byte of
3209 if (!(i
.vrex
& REX_X
))
3210 i
.vex
.bytes
[3] = 0x8;
3215 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3220 case DATA_PREFIX_OPCODE
:
3223 case REPE_PREFIX_OPCODE
:
3226 case REPNE_PREFIX_OPCODE
:
3233 /* 4 byte EVEX prefix. */
3235 i
.vex
.bytes
[0] = 0x62;
3238 switch (i
.tm
.opcode_modifier
.vexopcode
)
3254 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3256 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3258 /* The fifth bit of the second EVEX byte is 1's compliment of the
3259 REX_R bit in VREX. */
3260 if (!(i
.vrex
& REX_R
))
3261 i
.vex
.bytes
[1] |= 0x10;
3265 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3267 /* When all operands are registers, the REX_X bit in REX is not
3268 used. We reuse it to encode the upper 16 registers, which is
3269 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3270 as 1's compliment. */
3271 if ((i
.vrex
& REX_B
))
3274 i
.vex
.bytes
[1] &= ~0x40;
3278 /* EVEX instructions shouldn't need the REX prefix. */
3279 i
.vrex
&= ~vrex_used
;
3280 gas_assert (i
.vrex
== 0);
3282 /* Check the REX.W bit. */
3283 w
= (i
.rex
& REX_W
) ? 1 : 0;
3284 if (i
.tm
.opcode_modifier
.vexw
)
3286 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3289 /* If w is not set it means we are dealing with WIG instruction. */
3292 if (evexwig
== evexw1
)
3296 /* Encode the U bit. */
3297 implied_prefix
|= 0x4;
3299 /* The third byte of the EVEX prefix. */
3300 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3302 /* The fourth byte of the EVEX prefix. */
3303 /* The zeroing-masking bit. */
3304 if (i
.mask
&& i
.mask
->zeroing
)
3305 i
.vex
.bytes
[3] |= 0x80;
3307 /* Don't always set the broadcast bit if there is no RC. */
3310 /* Encode the vector length. */
3311 unsigned int vec_length
;
3313 switch (i
.tm
.opcode_modifier
.evex
)
3315 case EVEXLIG
: /* LL' is ignored */
3316 vec_length
= evexlig
<< 5;
3319 vec_length
= 0 << 5;
3322 vec_length
= 1 << 5;
3325 vec_length
= 2 << 5;
3331 i
.vex
.bytes
[3] |= vec_length
;
3332 /* Encode the broadcast bit. */
3334 i
.vex
.bytes
[3] |= 0x10;
3338 if (i
.rounding
->type
!= saeonly
)
3339 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3341 i
.vex
.bytes
[3] |= 0x10;
3344 if (i
.mask
&& i
.mask
->mask
)
3345 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3349 process_immext (void)
3353 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3356 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3357 with an opcode suffix which is coded in the same place as an
3358 8-bit immediate field would be.
3359 Here we check those operands and remove them afterwards. */
3362 for (x
= 0; x
< i
.operands
; x
++)
3363 if (register_number (i
.op
[x
].regs
) != x
)
3364 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3365 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3371 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3372 which is coded in the same place as an 8-bit immediate field
3373 would be. Here we fake an 8-bit immediate operand from the
3374 opcode suffix stored in tm.extension_opcode.
3376 AVX instructions also use this encoding, for some of
3377 3 argument instructions. */
3379 gas_assert (i
.imm_operands
<= 1
3381 || ((i
.tm
.opcode_modifier
.vex
3382 || i
.tm
.opcode_modifier
.evex
)
3383 && i
.operands
<= 4)));
3385 exp
= &im_expressions
[i
.imm_operands
++];
3386 i
.op
[i
.operands
].imms
= exp
;
3387 i
.types
[i
.operands
] = imm8
;
3389 exp
->X_op
= O_constant
;
3390 exp
->X_add_number
= i
.tm
.extension_opcode
;
3391 i
.tm
.extension_opcode
= None
;
3398 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3403 as_bad (_("invalid instruction `%s' after `%s'"),
3404 i
.tm
.name
, i
.hle_prefix
);
3407 if (i
.prefix
[LOCK_PREFIX
])
3409 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3413 case HLEPrefixRelease
:
3414 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3416 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3420 if (i
.mem_operands
== 0
3421 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3423 as_bad (_("memory destination needed for instruction `%s'"
3424 " after `xrelease'"), i
.tm
.name
);
3431 /* This is the guts of the machine-dependent assembler. LINE points to a
3432 machine dependent instruction. This function is supposed to emit
3433 the frags/bytes it assembles to. */
3436 md_assemble (char *line
)
3439 char mnemonic
[MAX_MNEM_SIZE
];
3440 const insn_template
*t
;
3442 /* Initialize globals. */
3443 memset (&i
, '\0', sizeof (i
));
3444 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3445 i
.reloc
[j
] = NO_RELOC
;
3446 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3447 memset (im_expressions
, '\0', sizeof (im_expressions
));
3448 save_stack_p
= save_stack
;
3450 /* First parse an instruction mnemonic & call i386_operand for the operands.
3451 We assume that the scrubber has arranged it so that line[0] is the valid
3452 start of a (possibly prefixed) mnemonic. */
3454 line
= parse_insn (line
, mnemonic
);
3458 line
= parse_operands (line
, mnemonic
);
3463 /* Now we've parsed the mnemonic into a set of templates, and have the
3464 operands at hand. */
3466 /* All intel opcodes have reversed operands except for "bound" and
3467 "enter". We also don't reverse intersegment "jmp" and "call"
3468 instructions with 2 immediate operands so that the immediate segment
3469 precedes the offset, as it does when in AT&T mode. */
3472 && (strcmp (mnemonic
, "bound") != 0)
3473 && (strcmp (mnemonic
, "invlpga") != 0)
3474 && !(operand_type_check (i
.types
[0], imm
)
3475 && operand_type_check (i
.types
[1], imm
)))
3478 /* The order of the immediates should be reversed
3479 for 2 immediates extrq and insertq instructions */
3480 if (i
.imm_operands
== 2
3481 && (strcmp (mnemonic
, "extrq") == 0
3482 || strcmp (mnemonic
, "insertq") == 0))
3483 swap_2_operands (0, 1);
3488 /* Don't optimize displacement for movabs since it only takes 64bit
3491 && i
.disp_encoding
!= disp_encoding_32bit
3492 && (flag_code
!= CODE_64BIT
3493 || strcmp (mnemonic
, "movabs") != 0))
3496 /* Next, we find a template that matches the given insn,
3497 making sure the overlap of the given operands types is consistent
3498 with the template operand types. */
3500 if (!(t
= match_template ()))
3503 if (sse_check
!= check_none
3504 && !i
.tm
.opcode_modifier
.noavx
3505 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3506 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3507 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3508 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3509 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3510 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3512 (sse_check
== check_warning
3514 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3517 /* Zap movzx and movsx suffix. The suffix has been set from
3518 "word ptr" or "byte ptr" on the source operand in Intel syntax
3519 or extracted from mnemonic in AT&T syntax. But we'll use
3520 the destination register to choose the suffix for encoding. */
3521 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3523 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3524 there is no suffix, the default will be byte extension. */
3525 if (i
.reg_operands
!= 2
3528 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3533 if (i
.tm
.opcode_modifier
.fwait
)
3534 if (!add_prefix (FWAIT_OPCODE
))
3537 /* Check if REP prefix is OK. */
3538 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3540 as_bad (_("invalid instruction `%s' after `%s'"),
3541 i
.tm
.name
, i
.rep_prefix
);
3545 /* Check for lock without a lockable instruction. Destination operand
3546 must be memory unless it is xchg (0x86). */
3547 if (i
.prefix
[LOCK_PREFIX
]
3548 && (!i
.tm
.opcode_modifier
.islockable
3549 || i
.mem_operands
== 0
3550 || (i
.tm
.base_opcode
!= 0x86
3551 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3553 as_bad (_("expecting lockable instruction after `lock'"));
3557 /* Check if HLE prefix is OK. */
3558 if (i
.hle_prefix
&& !check_hle ())
3561 /* Check BND prefix. */
3562 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3563 as_bad (_("expecting valid branch instruction after `bnd'"));
3565 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3566 && flag_code
== CODE_64BIT
3567 && i
.prefix
[ADDR_PREFIX
])
3568 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3570 /* Insert BND prefix. */
3572 && i
.tm
.opcode_modifier
.bndprefixok
3573 && !i
.prefix
[BND_PREFIX
])
3574 add_prefix (BND_PREFIX_OPCODE
);
3576 /* Check string instruction segment overrides. */
3577 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3579 if (!check_string ())
3581 i
.disp_operands
= 0;
3584 if (!process_suffix ())
3587 /* Update operand types. */
3588 for (j
= 0; j
< i
.operands
; j
++)
3589 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3591 /* Make still unresolved immediate matches conform to size of immediate
3592 given in i.suffix. */
3593 if (!finalize_imm ())
3596 if (i
.types
[0].bitfield
.imm1
)
3597 i
.imm_operands
= 0; /* kludge for shift insns. */
3599 /* We only need to check those implicit registers for instructions
3600 with 3 operands or less. */
3601 if (i
.operands
<= 3)
3602 for (j
= 0; j
< i
.operands
; j
++)
3603 if (i
.types
[j
].bitfield
.inoutportreg
3604 || i
.types
[j
].bitfield
.shiftcount
3605 || i
.types
[j
].bitfield
.acc
3606 || i
.types
[j
].bitfield
.floatacc
)
3609 /* ImmExt should be processed after SSE2AVX. */
3610 if (!i
.tm
.opcode_modifier
.sse2avx
3611 && i
.tm
.opcode_modifier
.immext
)
3614 /* For insns with operands there are more diddles to do to the opcode. */
3617 if (!process_operands ())
3620 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3622 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3623 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3626 if (i
.tm
.opcode_modifier
.vex
)
3627 build_vex_prefix (t
);
3629 if (i
.tm
.opcode_modifier
.evex
)
3630 build_evex_prefix ();
3632 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3633 instructions may define INT_OPCODE as well, so avoid this corner
3634 case for those instructions that use MODRM. */
3635 if (i
.tm
.base_opcode
== INT_OPCODE
3636 && !i
.tm
.opcode_modifier
.modrm
3637 && i
.op
[0].imms
->X_add_number
== 3)
3639 i
.tm
.base_opcode
= INT3_OPCODE
;
3643 if ((i
.tm
.opcode_modifier
.jump
3644 || i
.tm
.opcode_modifier
.jumpbyte
3645 || i
.tm
.opcode_modifier
.jumpdword
)
3646 && i
.op
[0].disps
->X_op
== O_constant
)
3648 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3649 the absolute address given by the constant. Since ix86 jumps and
3650 calls are pc relative, we need to generate a reloc. */
3651 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3652 i
.op
[0].disps
->X_op
= O_symbol
;
3655 if (i
.tm
.opcode_modifier
.rex64
)
3658 /* For 8 bit registers we need an empty rex prefix. Also if the
3659 instruction already has a prefix, we need to convert old
3660 registers to new ones. */
3662 if ((i
.types
[0].bitfield
.reg8
3663 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3664 || (i
.types
[1].bitfield
.reg8
3665 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3666 || ((i
.types
[0].bitfield
.reg8
3667 || i
.types
[1].bitfield
.reg8
)
3672 i
.rex
|= REX_OPCODE
;
3673 for (x
= 0; x
< 2; x
++)
3675 /* Look for 8 bit operand that uses old registers. */
3676 if (i
.types
[x
].bitfield
.reg8
3677 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3679 /* In case it is "hi" register, give up. */
3680 if (i
.op
[x
].regs
->reg_num
> 3)
3681 as_bad (_("can't encode register '%s%s' in an "
3682 "instruction requiring REX prefix."),
3683 register_prefix
, i
.op
[x
].regs
->reg_name
);
3685 /* Otherwise it is equivalent to the extended register.
3686 Since the encoding doesn't change this is merely
3687 cosmetic cleanup for debug output. */
3689 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3695 add_prefix (REX_OPCODE
| i
.rex
);
3697 /* We are ready to output the insn. */
3702 parse_insn (char *line
, char *mnemonic
)
3705 char *token_start
= l
;
3708 const insn_template
*t
;
3714 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3719 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3721 as_bad (_("no such instruction: `%s'"), token_start
);
3726 if (!is_space_char (*l
)
3727 && *l
!= END_OF_INSN
3729 || (*l
!= PREFIX_SEPARATOR
3732 as_bad (_("invalid character %s in mnemonic"),
3733 output_invalid (*l
));
3736 if (token_start
== l
)
3738 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3739 as_bad (_("expecting prefix; got nothing"));
3741 as_bad (_("expecting mnemonic; got nothing"));
3745 /* Look up instruction (or prefix) via hash table. */
3746 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3748 if (*l
!= END_OF_INSN
3749 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3750 && current_templates
3751 && current_templates
->start
->opcode_modifier
.isprefix
)
3753 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3755 as_bad ((flag_code
!= CODE_64BIT
3756 ? _("`%s' is only supported in 64-bit mode")
3757 : _("`%s' is not supported in 64-bit mode")),
3758 current_templates
->start
->name
);
3761 /* If we are in 16-bit mode, do not allow addr16 or data16.
3762 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3763 if ((current_templates
->start
->opcode_modifier
.size16
3764 || current_templates
->start
->opcode_modifier
.size32
)
3765 && flag_code
!= CODE_64BIT
3766 && (current_templates
->start
->opcode_modifier
.size32
3767 ^ (flag_code
== CODE_16BIT
)))
3769 as_bad (_("redundant %s prefix"),
3770 current_templates
->start
->name
);
3773 /* Add prefix, checking for repeated prefixes. */
3774 switch (add_prefix (current_templates
->start
->base_opcode
))
3779 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3780 i
.hle_prefix
= current_templates
->start
->name
;
3781 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3782 i
.bnd_prefix
= current_templates
->start
->name
;
3784 i
.rep_prefix
= current_templates
->start
->name
;
3789 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3796 if (!current_templates
)
3798 /* Check if we should swap operand or force 32bit displacement in
3800 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3802 else if (mnem_p
- 3 == dot_p
3805 i
.disp_encoding
= disp_encoding_8bit
;
3806 else if (mnem_p
- 4 == dot_p
3810 i
.disp_encoding
= disp_encoding_32bit
;
3815 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3818 if (!current_templates
)
3821 /* See if we can get a match by trimming off a suffix. */
3824 case WORD_MNEM_SUFFIX
:
3825 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3826 i
.suffix
= SHORT_MNEM_SUFFIX
;
3828 case BYTE_MNEM_SUFFIX
:
3829 case QWORD_MNEM_SUFFIX
:
3830 i
.suffix
= mnem_p
[-1];
3832 current_templates
= (const templates
*) hash_find (op_hash
,
3835 case SHORT_MNEM_SUFFIX
:
3836 case LONG_MNEM_SUFFIX
:
3839 i
.suffix
= mnem_p
[-1];
3841 current_templates
= (const templates
*) hash_find (op_hash
,
3850 if (intel_float_operand (mnemonic
) == 1)
3851 i
.suffix
= SHORT_MNEM_SUFFIX
;
3853 i
.suffix
= LONG_MNEM_SUFFIX
;
3855 current_templates
= (const templates
*) hash_find (op_hash
,
3860 if (!current_templates
)
3862 as_bad (_("no such instruction: `%s'"), token_start
);
3867 if (current_templates
->start
->opcode_modifier
.jump
3868 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3870 /* Check for a branch hint. We allow ",pt" and ",pn" for
3871 predict taken and predict not taken respectively.
3872 I'm not sure that branch hints actually do anything on loop
3873 and jcxz insns (JumpByte) for current Pentium4 chips. They
3874 may work in the future and it doesn't hurt to accept them
3876 if (l
[0] == ',' && l
[1] == 'p')
3880 if (!add_prefix (DS_PREFIX_OPCODE
))
3884 else if (l
[2] == 'n')
3886 if (!add_prefix (CS_PREFIX_OPCODE
))
3892 /* Any other comma loses. */
3895 as_bad (_("invalid character %s in mnemonic"),
3896 output_invalid (*l
));
3900 /* Check if instruction is supported on specified architecture. */
3902 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3904 supported
|= cpu_flags_match (t
);
3905 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3909 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3911 as_bad (flag_code
== CODE_64BIT
3912 ? _("`%s' is not supported in 64-bit mode")
3913 : _("`%s' is only supported in 64-bit mode"),
3914 current_templates
->start
->name
);
3917 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3919 as_bad (_("`%s' is not supported on `%s%s'"),
3920 current_templates
->start
->name
,
3921 cpu_arch_name
? cpu_arch_name
: default_arch
,
3922 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3927 if (!cpu_arch_flags
.bitfield
.cpui386
3928 && (flag_code
!= CODE_16BIT
))
3930 as_warn (_("use .code16 to ensure correct addressing mode"));
3937 parse_operands (char *l
, const char *mnemonic
)
3941 /* 1 if operand is pending after ','. */
3942 unsigned int expecting_operand
= 0;
3944 /* Non-zero if operand parens not balanced. */
3945 unsigned int paren_not_balanced
;
3947 while (*l
!= END_OF_INSN
)
3949 /* Skip optional white space before operand. */
3950 if (is_space_char (*l
))
3952 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3954 as_bad (_("invalid character %s before operand %d"),
3955 output_invalid (*l
),
3959 token_start
= l
; /* after white space */
3960 paren_not_balanced
= 0;
3961 while (paren_not_balanced
|| *l
!= ',')
3963 if (*l
== END_OF_INSN
)
3965 if (paren_not_balanced
)
3968 as_bad (_("unbalanced parenthesis in operand %d."),
3971 as_bad (_("unbalanced brackets in operand %d."),
3976 break; /* we are done */
3978 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3980 as_bad (_("invalid character %s in operand %d"),
3981 output_invalid (*l
),
3988 ++paren_not_balanced
;
3990 --paren_not_balanced
;
3995 ++paren_not_balanced
;
3997 --paren_not_balanced
;
4001 if (l
!= token_start
)
4002 { /* Yes, we've read in another operand. */
4003 unsigned int operand_ok
;
4004 this_operand
= i
.operands
++;
4005 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4006 if (i
.operands
> MAX_OPERANDS
)
4008 as_bad (_("spurious operands; (%d operands/instruction max)"),
4012 /* Now parse operand adding info to 'i' as we go along. */
4013 END_STRING_AND_SAVE (l
);
4017 i386_intel_operand (token_start
,
4018 intel_float_operand (mnemonic
));
4020 operand_ok
= i386_att_operand (token_start
);
4022 RESTORE_END_STRING (l
);
4028 if (expecting_operand
)
4030 expecting_operand_after_comma
:
4031 as_bad (_("expecting operand after ','; got nothing"));
4036 as_bad (_("expecting operand before ','; got nothing"));
4041 /* Now *l must be either ',' or END_OF_INSN. */
4044 if (*++l
== END_OF_INSN
)
4046 /* Just skip it, if it's \n complain. */
4047 goto expecting_operand_after_comma
;
4049 expecting_operand
= 1;
4056 swap_2_operands (int xchg1
, int xchg2
)
4058 union i386_op temp_op
;
4059 i386_operand_type temp_type
;
4060 enum bfd_reloc_code_real temp_reloc
;
4062 temp_type
= i
.types
[xchg2
];
4063 i
.types
[xchg2
] = i
.types
[xchg1
];
4064 i
.types
[xchg1
] = temp_type
;
4065 temp_op
= i
.op
[xchg2
];
4066 i
.op
[xchg2
] = i
.op
[xchg1
];
4067 i
.op
[xchg1
] = temp_op
;
4068 temp_reloc
= i
.reloc
[xchg2
];
4069 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4070 i
.reloc
[xchg1
] = temp_reloc
;
4074 if (i
.mask
->operand
== xchg1
)
4075 i
.mask
->operand
= xchg2
;
4076 else if (i
.mask
->operand
== xchg2
)
4077 i
.mask
->operand
= xchg1
;
4081 if (i
.broadcast
->operand
== xchg1
)
4082 i
.broadcast
->operand
= xchg2
;
4083 else if (i
.broadcast
->operand
== xchg2
)
4084 i
.broadcast
->operand
= xchg1
;
4088 if (i
.rounding
->operand
== xchg1
)
4089 i
.rounding
->operand
= xchg2
;
4090 else if (i
.rounding
->operand
== xchg2
)
4091 i
.rounding
->operand
= xchg1
;
4096 swap_operands (void)
4102 swap_2_operands (1, i
.operands
- 2);
4105 swap_2_operands (0, i
.operands
- 1);
4111 if (i
.mem_operands
== 2)
4113 const seg_entry
*temp_seg
;
4114 temp_seg
= i
.seg
[0];
4115 i
.seg
[0] = i
.seg
[1];
4116 i
.seg
[1] = temp_seg
;
4120 /* Try to ensure constant immediates are represented in the smallest
4125 char guess_suffix
= 0;
4129 guess_suffix
= i
.suffix
;
4130 else if (i
.reg_operands
)
4132 /* Figure out a suffix from the last register operand specified.
4133 We can't do this properly yet, ie. excluding InOutPortReg,
4134 but the following works for instructions with immediates.
4135 In any case, we can't set i.suffix yet. */
4136 for (op
= i
.operands
; --op
>= 0;)
4137 if (i
.types
[op
].bitfield
.reg8
)
4139 guess_suffix
= BYTE_MNEM_SUFFIX
;
4142 else if (i
.types
[op
].bitfield
.reg16
)
4144 guess_suffix
= WORD_MNEM_SUFFIX
;
4147 else if (i
.types
[op
].bitfield
.reg32
)
4149 guess_suffix
= LONG_MNEM_SUFFIX
;
4152 else if (i
.types
[op
].bitfield
.reg64
)
4154 guess_suffix
= QWORD_MNEM_SUFFIX
;
4158 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4159 guess_suffix
= WORD_MNEM_SUFFIX
;
4161 for (op
= i
.operands
; --op
>= 0;)
4162 if (operand_type_check (i
.types
[op
], imm
))
4164 switch (i
.op
[op
].imms
->X_op
)
4167 /* If a suffix is given, this operand may be shortened. */
4168 switch (guess_suffix
)
4170 case LONG_MNEM_SUFFIX
:
4171 i
.types
[op
].bitfield
.imm32
= 1;
4172 i
.types
[op
].bitfield
.imm64
= 1;
4174 case WORD_MNEM_SUFFIX
:
4175 i
.types
[op
].bitfield
.imm16
= 1;
4176 i
.types
[op
].bitfield
.imm32
= 1;
4177 i
.types
[op
].bitfield
.imm32s
= 1;
4178 i
.types
[op
].bitfield
.imm64
= 1;
4180 case BYTE_MNEM_SUFFIX
:
4181 i
.types
[op
].bitfield
.imm8
= 1;
4182 i
.types
[op
].bitfield
.imm8s
= 1;
4183 i
.types
[op
].bitfield
.imm16
= 1;
4184 i
.types
[op
].bitfield
.imm32
= 1;
4185 i
.types
[op
].bitfield
.imm32s
= 1;
4186 i
.types
[op
].bitfield
.imm64
= 1;
4190 /* If this operand is at most 16 bits, convert it
4191 to a signed 16 bit number before trying to see
4192 whether it will fit in an even smaller size.
4193 This allows a 16-bit operand such as $0xffe0 to
4194 be recognised as within Imm8S range. */
4195 if ((i
.types
[op
].bitfield
.imm16
)
4196 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4198 i
.op
[op
].imms
->X_add_number
=
4199 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4201 if ((i
.types
[op
].bitfield
.imm32
)
4202 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4205 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4206 ^ ((offsetT
) 1 << 31))
4207 - ((offsetT
) 1 << 31));
4210 = operand_type_or (i
.types
[op
],
4211 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4213 /* We must avoid matching of Imm32 templates when 64bit
4214 only immediate is available. */
4215 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4216 i
.types
[op
].bitfield
.imm32
= 0;
4223 /* Symbols and expressions. */
4225 /* Convert symbolic operand to proper sizes for matching, but don't
4226 prevent matching a set of insns that only supports sizes other
4227 than those matching the insn suffix. */
4229 i386_operand_type mask
, allowed
;
4230 const insn_template
*t
;
4232 operand_type_set (&mask
, 0);
4233 operand_type_set (&allowed
, 0);
4235 for (t
= current_templates
->start
;
4236 t
< current_templates
->end
;
4238 allowed
= operand_type_or (allowed
,
4239 t
->operand_types
[op
]);
4240 switch (guess_suffix
)
4242 case QWORD_MNEM_SUFFIX
:
4243 mask
.bitfield
.imm64
= 1;
4244 mask
.bitfield
.imm32s
= 1;
4246 case LONG_MNEM_SUFFIX
:
4247 mask
.bitfield
.imm32
= 1;
4249 case WORD_MNEM_SUFFIX
:
4250 mask
.bitfield
.imm16
= 1;
4252 case BYTE_MNEM_SUFFIX
:
4253 mask
.bitfield
.imm8
= 1;
4258 allowed
= operand_type_and (mask
, allowed
);
4259 if (!operand_type_all_zero (&allowed
))
4260 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4267 /* Try to use the smallest displacement type too. */
4269 optimize_disp (void)
4273 for (op
= i
.operands
; --op
>= 0;)
4274 if (operand_type_check (i
.types
[op
], disp
))
4276 if (i
.op
[op
].disps
->X_op
== O_constant
)
4278 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4280 if (i
.types
[op
].bitfield
.disp16
4281 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4283 /* If this operand is at most 16 bits, convert
4284 to a signed 16 bit number and don't use 64bit
4286 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4287 i
.types
[op
].bitfield
.disp64
= 0;
4289 if (i
.types
[op
].bitfield
.disp32
4290 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4292 /* If this operand is at most 32 bits, convert
4293 to a signed 32 bit number and don't use 64bit
4295 op_disp
&= (((offsetT
) 2 << 31) - 1);
4296 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4297 i
.types
[op
].bitfield
.disp64
= 0;
4299 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4301 i
.types
[op
].bitfield
.disp8
= 0;
4302 i
.types
[op
].bitfield
.disp16
= 0;
4303 i
.types
[op
].bitfield
.disp32
= 0;
4304 i
.types
[op
].bitfield
.disp32s
= 0;
4305 i
.types
[op
].bitfield
.disp64
= 0;
4309 else if (flag_code
== CODE_64BIT
)
4311 if (fits_in_signed_long (op_disp
))
4313 i
.types
[op
].bitfield
.disp64
= 0;
4314 i
.types
[op
].bitfield
.disp32s
= 1;
4316 if (i
.prefix
[ADDR_PREFIX
]
4317 && fits_in_unsigned_long (op_disp
))
4318 i
.types
[op
].bitfield
.disp32
= 1;
4320 if ((i
.types
[op
].bitfield
.disp32
4321 || i
.types
[op
].bitfield
.disp32s
4322 || i
.types
[op
].bitfield
.disp16
)
4323 && fits_in_signed_byte (op_disp
))
4324 i
.types
[op
].bitfield
.disp8
= 1;
4326 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4327 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4329 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4330 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4331 i
.types
[op
].bitfield
.disp8
= 0;
4332 i
.types
[op
].bitfield
.disp16
= 0;
4333 i
.types
[op
].bitfield
.disp32
= 0;
4334 i
.types
[op
].bitfield
.disp32s
= 0;
4335 i
.types
[op
].bitfield
.disp64
= 0;
4338 /* We only support 64bit displacement on constants. */
4339 i
.types
[op
].bitfield
.disp64
= 0;
4343 /* Check if operands are valid for the instruction. */
4346 check_VecOperands (const insn_template
*t
)
4350 /* Without VSIB byte, we can't have a vector register for index. */
4351 if (!t
->opcode_modifier
.vecsib
4353 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4354 || i
.index_reg
->reg_type
.bitfield
.regymm
4355 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4357 i
.error
= unsupported_vector_index_register
;
4361 /* Check if default mask is allowed. */
4362 if (t
->opcode_modifier
.nodefmask
4363 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4365 i
.error
= no_default_mask
;
4369 /* For VSIB byte, we need a vector register for index, and all vector
4370 registers must be distinct. */
4371 if (t
->opcode_modifier
.vecsib
)
4374 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4375 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4376 || (t
->opcode_modifier
.vecsib
== VecSIB256
4377 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4378 || (t
->opcode_modifier
.vecsib
== VecSIB512
4379 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4381 i
.error
= invalid_vsib_address
;
4385 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4386 if (i
.reg_operands
== 2 && !i
.mask
)
4388 gas_assert (i
.types
[0].bitfield
.regxmm
4389 || i
.types
[0].bitfield
.regymm
);
4390 gas_assert (i
.types
[2].bitfield
.regxmm
4391 || i
.types
[2].bitfield
.regymm
);
4392 if (operand_check
== check_none
)
4394 if (register_number (i
.op
[0].regs
)
4395 != register_number (i
.index_reg
)
4396 && register_number (i
.op
[2].regs
)
4397 != register_number (i
.index_reg
)
4398 && register_number (i
.op
[0].regs
)
4399 != register_number (i
.op
[2].regs
))
4401 if (operand_check
== check_error
)
4403 i
.error
= invalid_vector_register_set
;
4406 as_warn (_("mask, index, and destination registers should be distinct"));
4408 else if (i
.reg_operands
== 1 && i
.mask
)
4410 if ((i
.types
[1].bitfield
.regymm
4411 || i
.types
[1].bitfield
.regzmm
)
4412 && (register_number (i
.op
[1].regs
)
4413 == register_number (i
.index_reg
)))
4415 if (operand_check
== check_error
)
4417 i
.error
= invalid_vector_register_set
;
4420 if (operand_check
!= check_none
)
4421 as_warn (_("index and destination registers should be distinct"));
4426 /* Check if broadcast is supported by the instruction and is applied
4427 to the memory operand. */
4430 int broadcasted_opnd_size
;
4432 /* Check if specified broadcast is supported in this instruction,
4433 and it's applied to memory operand of DWORD or QWORD type,
4434 depending on VecESize. */
4435 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4436 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4437 || (t
->opcode_modifier
.vecesize
== 0
4438 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4439 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4440 || (t
->opcode_modifier
.vecesize
== 1
4441 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4442 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4445 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4446 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4447 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4448 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4449 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4453 if ((broadcasted_opnd_size
== 256
4454 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4455 || (broadcasted_opnd_size
== 512
4456 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4459 i
.error
= unsupported_broadcast
;
4463 /* If broadcast is supported in this instruction, we need to check if
4464 operand of one-element size isn't specified without broadcast. */
4465 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4467 /* Find memory operand. */
4468 for (op
= 0; op
< i
.operands
; op
++)
4469 if (operand_type_check (i
.types
[op
], anymem
))
4471 gas_assert (op
< i
.operands
);
4472 /* Check size of the memory operand. */
4473 if ((t
->opcode_modifier
.vecesize
== 0
4474 && i
.types
[op
].bitfield
.dword
)
4475 || (t
->opcode_modifier
.vecesize
== 1
4476 && i
.types
[op
].bitfield
.qword
))
4478 i
.error
= broadcast_needed
;
4483 /* Check if requested masking is supported. */
4485 && (!t
->opcode_modifier
.masking
4487 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4489 i
.error
= unsupported_masking
;
4493 /* Check if masking is applied to dest operand. */
4494 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4496 i
.error
= mask_not_on_destination
;
4503 if ((i
.rounding
->type
!= saeonly
4504 && !t
->opcode_modifier
.staticrounding
)
4505 || (i
.rounding
->type
== saeonly
4506 && (t
->opcode_modifier
.staticrounding
4507 || !t
->opcode_modifier
.sae
)))
4509 i
.error
= unsupported_rc_sae
;
4512 /* If the instruction has several immediate operands and one of
4513 them is rounding, the rounding operand should be the last
4514 immediate operand. */
4515 if (i
.imm_operands
> 1
4516 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4518 i
.error
= rc_sae_operand_not_last_imm
;
4523 /* Check vector Disp8 operand. */
4524 if (t
->opcode_modifier
.disp8memshift
)
4527 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4529 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4531 for (op
= 0; op
< i
.operands
; op
++)
4532 if (operand_type_check (i
.types
[op
], disp
)
4533 && i
.op
[op
].disps
->X_op
== O_constant
)
4535 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4536 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4537 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4540 i
.types
[op
].bitfield
.vec_disp8
= 1;
4543 /* Vector insn can only have Vec_Disp8/Disp32 in
4544 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4546 i
.types
[op
].bitfield
.disp8
= 0;
4547 if (flag_code
!= CODE_16BIT
)
4548 i
.types
[op
].bitfield
.disp16
= 0;
4551 else if (flag_code
!= CODE_16BIT
)
4553 /* One form of this instruction supports vector Disp8.
4554 Try vector Disp8 if we need to use Disp32. */
4555 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4557 i
.error
= try_vector_disp8
;
4569 /* Check if operands are valid for the instruction. Update VEX
4573 VEX_check_operands (const insn_template
*t
)
4575 /* VREX is only valid with EVEX prefix. */
4576 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4578 i
.error
= invalid_register_operand
;
4582 if (!t
->opcode_modifier
.vex
)
4585 /* Only check VEX_Imm4, which must be the first operand. */
4586 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4588 if (i
.op
[0].imms
->X_op
!= O_constant
4589 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4595 /* Turn off Imm8 so that update_imm won't complain. */
4596 i
.types
[0] = vec_imm4
;
4602 static const insn_template
*
4603 match_template (void)
4605 /* Points to template once we've found it. */
4606 const insn_template
*t
;
4607 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4608 i386_operand_type overlap4
;
4609 unsigned int found_reverse_match
;
4610 i386_opcode_modifier suffix_check
;
4611 i386_operand_type operand_types
[MAX_OPERANDS
];
4612 int addr_prefix_disp
;
4614 unsigned int found_cpu_match
;
4615 unsigned int check_register
;
4616 enum i386_error specific_error
= 0;
4618 #if MAX_OPERANDS != 5
4619 # error "MAX_OPERANDS must be 5."
4622 found_reverse_match
= 0;
4623 addr_prefix_disp
= -1;
4625 memset (&suffix_check
, 0, sizeof (suffix_check
));
4626 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4627 suffix_check
.no_bsuf
= 1;
4628 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4629 suffix_check
.no_wsuf
= 1;
4630 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4631 suffix_check
.no_ssuf
= 1;
4632 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4633 suffix_check
.no_lsuf
= 1;
4634 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4635 suffix_check
.no_qsuf
= 1;
4636 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4637 suffix_check
.no_ldsuf
= 1;
4639 /* Must have right number of operands. */
4640 i
.error
= number_of_operands_mismatch
;
4642 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4644 addr_prefix_disp
= -1;
4646 if (i
.operands
!= t
->operands
)
4649 /* Check processor support. */
4650 i
.error
= unsupported
;
4651 found_cpu_match
= (cpu_flags_match (t
)
4652 == CPU_FLAGS_PERFECT_MATCH
);
4653 if (!found_cpu_match
)
4656 /* Check old gcc support. */
4657 i
.error
= old_gcc_only
;
4658 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4661 /* Check AT&T mnemonic. */
4662 i
.error
= unsupported_with_intel_mnemonic
;
4663 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4666 /* Check AT&T/Intel syntax. */
4667 i
.error
= unsupported_syntax
;
4668 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4669 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4672 /* Check the suffix, except for some instructions in intel mode. */
4673 i
.error
= invalid_instruction_suffix
;
4674 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4675 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4676 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4677 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4678 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4679 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4680 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4683 if (!operand_size_match (t
))
4686 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4687 operand_types
[j
] = t
->operand_types
[j
];
4689 /* In general, don't allow 64-bit operands in 32-bit mode. */
4690 if (i
.suffix
== QWORD_MNEM_SUFFIX
4691 && flag_code
!= CODE_64BIT
4693 ? (!t
->opcode_modifier
.ignoresize
4694 && !intel_float_operand (t
->name
))
4695 : intel_float_operand (t
->name
) != 2)
4696 && ((!operand_types
[0].bitfield
.regmmx
4697 && !operand_types
[0].bitfield
.regxmm
4698 && !operand_types
[0].bitfield
.regymm
4699 && !operand_types
[0].bitfield
.regzmm
)
4700 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4701 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4702 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4703 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4704 && (t
->base_opcode
!= 0x0fc7
4705 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4708 /* In general, don't allow 32-bit operands on pre-386. */
4709 else if (i
.suffix
== LONG_MNEM_SUFFIX
4710 && !cpu_arch_flags
.bitfield
.cpui386
4712 ? (!t
->opcode_modifier
.ignoresize
4713 && !intel_float_operand (t
->name
))
4714 : intel_float_operand (t
->name
) != 2)
4715 && ((!operand_types
[0].bitfield
.regmmx
4716 && !operand_types
[0].bitfield
.regxmm
)
4717 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4718 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4721 /* Do not verify operands when there are none. */
4725 /* We've found a match; break out of loop. */
4729 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4730 into Disp32/Disp16/Disp32 operand. */
4731 if (i
.prefix
[ADDR_PREFIX
] != 0)
4733 /* There should be only one Disp operand. */
4737 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4739 if (operand_types
[j
].bitfield
.disp16
)
4741 addr_prefix_disp
= j
;
4742 operand_types
[j
].bitfield
.disp32
= 1;
4743 operand_types
[j
].bitfield
.disp16
= 0;
4749 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4751 if (operand_types
[j
].bitfield
.disp32
)
4753 addr_prefix_disp
= j
;
4754 operand_types
[j
].bitfield
.disp32
= 0;
4755 operand_types
[j
].bitfield
.disp16
= 1;
4761 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4763 if (operand_types
[j
].bitfield
.disp64
)
4765 addr_prefix_disp
= j
;
4766 operand_types
[j
].bitfield
.disp64
= 0;
4767 operand_types
[j
].bitfield
.disp32
= 1;
4775 /* We check register size if needed. */
4776 check_register
= t
->opcode_modifier
.checkregsize
;
4777 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4778 switch (t
->operands
)
4781 if (!operand_type_match (overlap0
, i
.types
[0]))
4785 /* xchg %eax, %eax is a special case. It is an aliase for nop
4786 only in 32bit mode and we can use opcode 0x90. In 64bit
4787 mode, we can't use 0x90 for xchg %eax, %eax since it should
4788 zero-extend %eax to %rax. */
4789 if (flag_code
== CODE_64BIT
4790 && t
->base_opcode
== 0x90
4791 && operand_type_equal (&i
.types
[0], &acc32
)
4792 && operand_type_equal (&i
.types
[1], &acc32
))
4796 /* If we swap operand in encoding, we either match
4797 the next one or reverse direction of operands. */
4798 if (t
->opcode_modifier
.s
)
4800 else if (t
->opcode_modifier
.d
)
4805 /* If we swap operand in encoding, we match the next one. */
4806 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4810 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4811 if (!operand_type_match (overlap0
, i
.types
[0])
4812 || !operand_type_match (overlap1
, i
.types
[1])
4814 && !operand_type_register_match (overlap0
, i
.types
[0],
4816 overlap1
, i
.types
[1],
4819 /* Check if other direction is valid ... */
4820 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4824 /* Try reversing direction of operands. */
4825 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4826 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4827 if (!operand_type_match (overlap0
, i
.types
[0])
4828 || !operand_type_match (overlap1
, i
.types
[1])
4830 && !operand_type_register_match (overlap0
,
4837 /* Does not match either direction. */
4840 /* found_reverse_match holds which of D or FloatDR
4842 if (t
->opcode_modifier
.d
)
4843 found_reverse_match
= Opcode_D
;
4844 else if (t
->opcode_modifier
.floatd
)
4845 found_reverse_match
= Opcode_FloatD
;
4847 found_reverse_match
= 0;
4848 if (t
->opcode_modifier
.floatr
)
4849 found_reverse_match
|= Opcode_FloatR
;
4853 /* Found a forward 2 operand match here. */
4854 switch (t
->operands
)
4857 overlap4
= operand_type_and (i
.types
[4],
4860 overlap3
= operand_type_and (i
.types
[3],
4863 overlap2
= operand_type_and (i
.types
[2],
4868 switch (t
->operands
)
4871 if (!operand_type_match (overlap4
, i
.types
[4])
4872 || !operand_type_register_match (overlap3
,
4880 if (!operand_type_match (overlap3
, i
.types
[3])
4882 && !operand_type_register_match (overlap2
,
4890 /* Here we make use of the fact that there are no
4891 reverse match 3 operand instructions, and all 3
4892 operand instructions only need to be checked for
4893 register consistency between operands 2 and 3. */
4894 if (!operand_type_match (overlap2
, i
.types
[2])
4896 && !operand_type_register_match (overlap1
,
4906 /* Found either forward/reverse 2, 3 or 4 operand match here:
4907 slip through to break. */
4909 if (!found_cpu_match
)
4911 found_reverse_match
= 0;
4915 /* Check if vector and VEX operands are valid. */
4916 if (check_VecOperands (t
) || VEX_check_operands (t
))
4918 specific_error
= i
.error
;
4922 /* We've found a match; break out of loop. */
4926 if (t
== current_templates
->end
)
4928 /* We found no match. */
4929 const char *err_msg
;
4930 switch (specific_error
? specific_error
: i
.error
)
4934 case operand_size_mismatch
:
4935 err_msg
= _("operand size mismatch");
4937 case operand_type_mismatch
:
4938 err_msg
= _("operand type mismatch");
4940 case register_type_mismatch
:
4941 err_msg
= _("register type mismatch");
4943 case number_of_operands_mismatch
:
4944 err_msg
= _("number of operands mismatch");
4946 case invalid_instruction_suffix
:
4947 err_msg
= _("invalid instruction suffix");
4950 err_msg
= _("constant doesn't fit in 4 bits");
4953 err_msg
= _("only supported with old gcc");
4955 case unsupported_with_intel_mnemonic
:
4956 err_msg
= _("unsupported with Intel mnemonic");
4958 case unsupported_syntax
:
4959 err_msg
= _("unsupported syntax");
4962 as_bad (_("unsupported instruction `%s'"),
4963 current_templates
->start
->name
);
4965 case invalid_vsib_address
:
4966 err_msg
= _("invalid VSIB address");
4968 case invalid_vector_register_set
:
4969 err_msg
= _("mask, index, and destination registers must be distinct");
4971 case unsupported_vector_index_register
:
4972 err_msg
= _("unsupported vector index register");
4974 case unsupported_broadcast
:
4975 err_msg
= _("unsupported broadcast");
4977 case broadcast_not_on_src_operand
:
4978 err_msg
= _("broadcast not on source memory operand");
4980 case broadcast_needed
:
4981 err_msg
= _("broadcast is needed for operand of such type");
4983 case unsupported_masking
:
4984 err_msg
= _("unsupported masking");
4986 case mask_not_on_destination
:
4987 err_msg
= _("mask not on destination operand");
4989 case no_default_mask
:
4990 err_msg
= _("default mask isn't allowed");
4992 case unsupported_rc_sae
:
4993 err_msg
= _("unsupported static rounding/sae");
4995 case rc_sae_operand_not_last_imm
:
4997 err_msg
= _("RC/SAE operand must precede immediate operands");
4999 err_msg
= _("RC/SAE operand must follow immediate operands");
5001 case invalid_register_operand
:
5002 err_msg
= _("invalid register operand");
5005 as_bad (_("%s for `%s'"), err_msg
,
5006 current_templates
->start
->name
);
5010 if (!quiet_warnings
)
5013 && (i
.types
[0].bitfield
.jumpabsolute
5014 != operand_types
[0].bitfield
.jumpabsolute
))
5016 as_warn (_("indirect %s without `*'"), t
->name
);
5019 if (t
->opcode_modifier
.isprefix
5020 && t
->opcode_modifier
.ignoresize
)
5022 /* Warn them that a data or address size prefix doesn't
5023 affect assembly of the next line of code. */
5024 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5028 /* Copy the template we found. */
5031 if (addr_prefix_disp
!= -1)
5032 i
.tm
.operand_types
[addr_prefix_disp
]
5033 = operand_types
[addr_prefix_disp
];
5035 if (found_reverse_match
)
5037 /* If we found a reverse match we must alter the opcode
5038 direction bit. found_reverse_match holds bits to change
5039 (different for int & float insns). */
5041 i
.tm
.base_opcode
^= found_reverse_match
;
5043 i
.tm
.operand_types
[0] = operand_types
[1];
5044 i
.tm
.operand_types
[1] = operand_types
[0];
5053 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5054 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5056 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5058 as_bad (_("`%s' operand %d must use `%ses' segment"),
5064 /* There's only ever one segment override allowed per instruction.
5065 This instruction possibly has a legal segment override on the
5066 second operand, so copy the segment to where non-string
5067 instructions store it, allowing common code. */
5068 i
.seg
[0] = i
.seg
[1];
5070 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5072 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5074 as_bad (_("`%s' operand %d must use `%ses' segment"),
5085 process_suffix (void)
5087 /* If matched instruction specifies an explicit instruction mnemonic
5089 if (i
.tm
.opcode_modifier
.size16
)
5090 i
.suffix
= WORD_MNEM_SUFFIX
;
5091 else if (i
.tm
.opcode_modifier
.size32
)
5092 i
.suffix
= LONG_MNEM_SUFFIX
;
5093 else if (i
.tm
.opcode_modifier
.size64
)
5094 i
.suffix
= QWORD_MNEM_SUFFIX
;
5095 else if (i
.reg_operands
)
5097 /* If there's no instruction mnemonic suffix we try to invent one
5098 based on register operands. */
5101 /* We take i.suffix from the last register operand specified,
5102 Destination register type is more significant than source
5103 register type. crc32 in SSE4.2 prefers source register
5105 if (i
.tm
.base_opcode
== 0xf20f38f1)
5107 if (i
.types
[0].bitfield
.reg16
)
5108 i
.suffix
= WORD_MNEM_SUFFIX
;
5109 else if (i
.types
[0].bitfield
.reg32
)
5110 i
.suffix
= LONG_MNEM_SUFFIX
;
5111 else if (i
.types
[0].bitfield
.reg64
)
5112 i
.suffix
= QWORD_MNEM_SUFFIX
;
5114 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5116 if (i
.types
[0].bitfield
.reg8
)
5117 i
.suffix
= BYTE_MNEM_SUFFIX
;
5124 if (i
.tm
.base_opcode
== 0xf20f38f1
5125 || i
.tm
.base_opcode
== 0xf20f38f0)
5127 /* We have to know the operand size for crc32. */
5128 as_bad (_("ambiguous memory operand size for `%s`"),
5133 for (op
= i
.operands
; --op
>= 0;)
5134 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5136 if (i
.types
[op
].bitfield
.reg8
)
5138 i
.suffix
= BYTE_MNEM_SUFFIX
;
5141 else if (i
.types
[op
].bitfield
.reg16
)
5143 i
.suffix
= WORD_MNEM_SUFFIX
;
5146 else if (i
.types
[op
].bitfield
.reg32
)
5148 i
.suffix
= LONG_MNEM_SUFFIX
;
5151 else if (i
.types
[op
].bitfield
.reg64
)
5153 i
.suffix
= QWORD_MNEM_SUFFIX
;
5159 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5162 && i
.tm
.opcode_modifier
.ignoresize
5163 && i
.tm
.opcode_modifier
.no_bsuf
)
5165 else if (!check_byte_reg ())
5168 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5171 && i
.tm
.opcode_modifier
.ignoresize
5172 && i
.tm
.opcode_modifier
.no_lsuf
)
5174 else if (!check_long_reg ())
5177 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5180 && i
.tm
.opcode_modifier
.ignoresize
5181 && i
.tm
.opcode_modifier
.no_qsuf
)
5183 else if (!check_qword_reg ())
5186 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5189 && i
.tm
.opcode_modifier
.ignoresize
5190 && i
.tm
.opcode_modifier
.no_wsuf
)
5192 else if (!check_word_reg ())
5195 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5196 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5197 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5199 /* Skip if the instruction has x/y/z suffix. match_template
5200 should check if it is a valid suffix. */
5202 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5203 /* Do nothing if the instruction is going to ignore the prefix. */
5208 else if (i
.tm
.opcode_modifier
.defaultsize
5210 /* exclude fldenv/frstor/fsave/fstenv */
5211 && i
.tm
.opcode_modifier
.no_ssuf
)
5213 i
.suffix
= stackop_size
;
5215 else if (intel_syntax
5217 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5218 || i
.tm
.opcode_modifier
.jumpbyte
5219 || i
.tm
.opcode_modifier
.jumpintersegment
5220 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5221 && i
.tm
.extension_opcode
<= 3)))
5226 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5228 i
.suffix
= QWORD_MNEM_SUFFIX
;
5232 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5233 i
.suffix
= LONG_MNEM_SUFFIX
;
5236 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5237 i
.suffix
= WORD_MNEM_SUFFIX
;
5246 if (i
.tm
.opcode_modifier
.w
)
5248 as_bad (_("no instruction mnemonic suffix given and "
5249 "no register operands; can't size instruction"));
5255 unsigned int suffixes
;
5257 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5258 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5260 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5262 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5264 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5266 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5269 /* There are more than suffix matches. */
5270 if (i
.tm
.opcode_modifier
.w
5271 || ((suffixes
& (suffixes
- 1))
5272 && !i
.tm
.opcode_modifier
.defaultsize
5273 && !i
.tm
.opcode_modifier
.ignoresize
))
5275 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5281 /* Change the opcode based on the operand size given by i.suffix;
5282 We don't need to change things for byte insns. */
5285 && i
.suffix
!= BYTE_MNEM_SUFFIX
5286 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5287 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5288 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5290 /* It's not a byte, select word/dword operation. */
5291 if (i
.tm
.opcode_modifier
.w
)
5293 if (i
.tm
.opcode_modifier
.shortform
)
5294 i
.tm
.base_opcode
|= 8;
5296 i
.tm
.base_opcode
|= 1;
5299 /* Now select between word & dword operations via the operand
5300 size prefix, except for instructions that will ignore this
5302 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5304 /* The address size override prefix changes the size of the
5306 if ((flag_code
== CODE_32BIT
5307 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5308 || (flag_code
!= CODE_32BIT
5309 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5310 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5313 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5314 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5315 && !i
.tm
.opcode_modifier
.ignoresize
5316 && !i
.tm
.opcode_modifier
.floatmf
5317 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5318 || (flag_code
== CODE_64BIT
5319 && i
.tm
.opcode_modifier
.jumpbyte
)))
5321 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5323 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5324 prefix
= ADDR_PREFIX_OPCODE
;
5326 if (!add_prefix (prefix
))
5330 /* Set mode64 for an operand. */
5331 if (i
.suffix
== QWORD_MNEM_SUFFIX
5332 && flag_code
== CODE_64BIT
5333 && !i
.tm
.opcode_modifier
.norex64
)
5335 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5336 need rex64. cmpxchg8b is also a special case. */
5337 if (! (i
.operands
== 2
5338 && i
.tm
.base_opcode
== 0x90
5339 && i
.tm
.extension_opcode
== None
5340 && operand_type_equal (&i
.types
[0], &acc64
)
5341 && operand_type_equal (&i
.types
[1], &acc64
))
5342 && ! (i
.operands
== 1
5343 && i
.tm
.base_opcode
== 0xfc7
5344 && i
.tm
.extension_opcode
== 1
5345 && !operand_type_check (i
.types
[0], reg
)
5346 && operand_type_check (i
.types
[0], anymem
)))
5350 /* Size floating point instruction. */
5351 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5352 if (i
.tm
.opcode_modifier
.floatmf
)
5353 i
.tm
.base_opcode
^= 4;
5360 check_byte_reg (void)
5364 for (op
= i
.operands
; --op
>= 0;)
5366 /* If this is an eight bit register, it's OK. If it's the 16 or
5367 32 bit version of an eight bit register, we will just use the
5368 low portion, and that's OK too. */
5369 if (i
.types
[op
].bitfield
.reg8
)
5372 /* I/O port address operands are OK too. */
5373 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5376 /* crc32 doesn't generate this warning. */
5377 if (i
.tm
.base_opcode
== 0xf20f38f0)
5380 if ((i
.types
[op
].bitfield
.reg16
5381 || i
.types
[op
].bitfield
.reg32
5382 || i
.types
[op
].bitfield
.reg64
)
5383 && i
.op
[op
].regs
->reg_num
< 4
5384 /* Prohibit these changes in 64bit mode, since the lowering
5385 would be more complicated. */
5386 && flag_code
!= CODE_64BIT
)
5388 #if REGISTER_WARNINGS
5389 if (!quiet_warnings
)
5390 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5392 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5393 ? REGNAM_AL
- REGNAM_AX
5394 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5396 i
.op
[op
].regs
->reg_name
,
5401 /* Any other register is bad. */
5402 if (i
.types
[op
].bitfield
.reg16
5403 || i
.types
[op
].bitfield
.reg32
5404 || i
.types
[op
].bitfield
.reg64
5405 || i
.types
[op
].bitfield
.regmmx
5406 || i
.types
[op
].bitfield
.regxmm
5407 || i
.types
[op
].bitfield
.regymm
5408 || i
.types
[op
].bitfield
.regzmm
5409 || i
.types
[op
].bitfield
.sreg2
5410 || i
.types
[op
].bitfield
.sreg3
5411 || i
.types
[op
].bitfield
.control
5412 || i
.types
[op
].bitfield
.debug
5413 || i
.types
[op
].bitfield
.test
5414 || i
.types
[op
].bitfield
.floatreg
5415 || i
.types
[op
].bitfield
.floatacc
)
5417 as_bad (_("`%s%s' not allowed with `%s%c'"),
5419 i
.op
[op
].regs
->reg_name
,
5429 check_long_reg (void)
5433 for (op
= i
.operands
; --op
>= 0;)
5434 /* Reject eight bit registers, except where the template requires
5435 them. (eg. movzb) */
5436 if (i
.types
[op
].bitfield
.reg8
5437 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5438 || i
.tm
.operand_types
[op
].bitfield
.reg32
5439 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5441 as_bad (_("`%s%s' not allowed with `%s%c'"),
5443 i
.op
[op
].regs
->reg_name
,
5448 /* Warn if the e prefix on a general reg is missing. */
5449 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5450 && i
.types
[op
].bitfield
.reg16
5451 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5452 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5454 /* Prohibit these changes in the 64bit mode, since the
5455 lowering is more complicated. */
5456 if (flag_code
== CODE_64BIT
)
5458 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5459 register_prefix
, i
.op
[op
].regs
->reg_name
,
5463 #if REGISTER_WARNINGS
5464 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5466 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5467 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5470 /* Warn if the r prefix on a general reg is present. */
5471 else if (i
.types
[op
].bitfield
.reg64
5472 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5473 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5476 && i
.tm
.opcode_modifier
.toqword
5477 && !i
.types
[0].bitfield
.regxmm
)
5479 /* Convert to QWORD. We want REX byte. */
5480 i
.suffix
= QWORD_MNEM_SUFFIX
;
5484 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5485 register_prefix
, i
.op
[op
].regs
->reg_name
,
5494 check_qword_reg (void)
5498 for (op
= i
.operands
; --op
>= 0; )
5499 /* Reject eight bit registers, except where the template requires
5500 them. (eg. movzb) */
5501 if (i
.types
[op
].bitfield
.reg8
5502 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5503 || i
.tm
.operand_types
[op
].bitfield
.reg32
5504 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5506 as_bad (_("`%s%s' not allowed with `%s%c'"),
5508 i
.op
[op
].regs
->reg_name
,
5513 /* Warn if the r prefix on a general reg is missing. */
5514 else if ((i
.types
[op
].bitfield
.reg16
5515 || i
.types
[op
].bitfield
.reg32
)
5516 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5517 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5519 /* Prohibit these changes in the 64bit mode, since the
5520 lowering is more complicated. */
5522 && i
.tm
.opcode_modifier
.todword
5523 && !i
.types
[0].bitfield
.regxmm
)
5525 /* Convert to DWORD. We don't want REX byte. */
5526 i
.suffix
= LONG_MNEM_SUFFIX
;
5530 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5531 register_prefix
, i
.op
[op
].regs
->reg_name
,
5540 check_word_reg (void)
5543 for (op
= i
.operands
; --op
>= 0;)
5544 /* Reject eight bit registers, except where the template requires
5545 them. (eg. movzb) */
5546 if (i
.types
[op
].bitfield
.reg8
5547 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5548 || i
.tm
.operand_types
[op
].bitfield
.reg32
5549 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5551 as_bad (_("`%s%s' not allowed with `%s%c'"),
5553 i
.op
[op
].regs
->reg_name
,
5558 /* Warn if the e or r prefix on a general reg is present. */
5559 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5560 && (i
.types
[op
].bitfield
.reg32
5561 || i
.types
[op
].bitfield
.reg64
)
5562 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5563 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5565 /* Prohibit these changes in the 64bit mode, since the
5566 lowering is more complicated. */
5567 if (flag_code
== CODE_64BIT
)
5569 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5570 register_prefix
, i
.op
[op
].regs
->reg_name
,
5574 #if REGISTER_WARNINGS
5575 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5577 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5578 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5585 update_imm (unsigned int j
)
5587 i386_operand_type overlap
= i
.types
[j
];
5588 if ((overlap
.bitfield
.imm8
5589 || overlap
.bitfield
.imm8s
5590 || overlap
.bitfield
.imm16
5591 || overlap
.bitfield
.imm32
5592 || overlap
.bitfield
.imm32s
5593 || overlap
.bitfield
.imm64
)
5594 && !operand_type_equal (&overlap
, &imm8
)
5595 && !operand_type_equal (&overlap
, &imm8s
)
5596 && !operand_type_equal (&overlap
, &imm16
)
5597 && !operand_type_equal (&overlap
, &imm32
)
5598 && !operand_type_equal (&overlap
, &imm32s
)
5599 && !operand_type_equal (&overlap
, &imm64
))
5603 i386_operand_type temp
;
5605 operand_type_set (&temp
, 0);
5606 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5608 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5609 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5611 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5612 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5613 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5615 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5616 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5619 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5622 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5623 || operand_type_equal (&overlap
, &imm16_32
)
5624 || operand_type_equal (&overlap
, &imm16_32s
))
5626 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5631 if (!operand_type_equal (&overlap
, &imm8
)
5632 && !operand_type_equal (&overlap
, &imm8s
)
5633 && !operand_type_equal (&overlap
, &imm16
)
5634 && !operand_type_equal (&overlap
, &imm32
)
5635 && !operand_type_equal (&overlap
, &imm32s
)
5636 && !operand_type_equal (&overlap
, &imm64
))
5638 as_bad (_("no instruction mnemonic suffix given; "
5639 "can't determine immediate size"));
5643 i
.types
[j
] = overlap
;
5653 /* Update the first 2 immediate operands. */
5654 n
= i
.operands
> 2 ? 2 : i
.operands
;
5657 for (j
= 0; j
< n
; j
++)
5658 if (update_imm (j
) == 0)
5661 /* The 3rd operand can't be immediate operand. */
5662 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5669 bad_implicit_operand (int xmm
)
5671 const char *ireg
= xmm
? "xmm0" : "ymm0";
5674 as_bad (_("the last operand of `%s' must be `%s%s'"),
5675 i
.tm
.name
, register_prefix
, ireg
);
5677 as_bad (_("the first operand of `%s' must be `%s%s'"),
5678 i
.tm
.name
, register_prefix
, ireg
);
5683 process_operands (void)
5685 /* Default segment register this instruction will use for memory
5686 accesses. 0 means unknown. This is only for optimizing out
5687 unnecessary segment overrides. */
5688 const seg_entry
*default_seg
= 0;
5690 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5692 unsigned int dupl
= i
.operands
;
5693 unsigned int dest
= dupl
- 1;
5696 /* The destination must be an xmm register. */
5697 gas_assert (i
.reg_operands
5698 && MAX_OPERANDS
> dupl
5699 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5701 if (i
.tm
.opcode_modifier
.firstxmm0
)
5703 /* The first operand is implicit and must be xmm0. */
5704 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5705 if (register_number (i
.op
[0].regs
) != 0)
5706 return bad_implicit_operand (1);
5708 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5710 /* Keep xmm0 for instructions with VEX prefix and 3
5716 /* We remove the first xmm0 and keep the number of
5717 operands unchanged, which in fact duplicates the
5719 for (j
= 1; j
< i
.operands
; j
++)
5721 i
.op
[j
- 1] = i
.op
[j
];
5722 i
.types
[j
- 1] = i
.types
[j
];
5723 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5727 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5729 gas_assert ((MAX_OPERANDS
- 1) > dupl
5730 && (i
.tm
.opcode_modifier
.vexsources
5733 /* Add the implicit xmm0 for instructions with VEX prefix
5735 for (j
= i
.operands
; j
> 0; j
--)
5737 i
.op
[j
] = i
.op
[j
- 1];
5738 i
.types
[j
] = i
.types
[j
- 1];
5739 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5742 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5743 i
.types
[0] = regxmm
;
5744 i
.tm
.operand_types
[0] = regxmm
;
5747 i
.reg_operands
+= 2;
5752 i
.op
[dupl
] = i
.op
[dest
];
5753 i
.types
[dupl
] = i
.types
[dest
];
5754 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5763 i
.op
[dupl
] = i
.op
[dest
];
5764 i
.types
[dupl
] = i
.types
[dest
];
5765 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5768 if (i
.tm
.opcode_modifier
.immext
)
5771 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5775 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5776 gas_assert (i
.reg_operands
5777 && (operand_type_equal (&i
.types
[0], ®xmm
)
5778 || operand_type_equal (&i
.types
[0], ®ymm
)
5779 || operand_type_equal (&i
.types
[0], ®zmm
)));
5780 if (register_number (i
.op
[0].regs
) != 0)
5781 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5783 for (j
= 1; j
< i
.operands
; j
++)
5785 i
.op
[j
- 1] = i
.op
[j
];
5786 i
.types
[j
- 1] = i
.types
[j
];
5788 /* We need to adjust fields in i.tm since they are used by
5789 build_modrm_byte. */
5790 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5797 else if (i
.tm
.opcode_modifier
.regkludge
)
5799 /* The imul $imm, %reg instruction is converted into
5800 imul $imm, %reg, %reg, and the clr %reg instruction
5801 is converted into xor %reg, %reg. */
5803 unsigned int first_reg_op
;
5805 if (operand_type_check (i
.types
[0], reg
))
5809 /* Pretend we saw the extra register operand. */
5810 gas_assert (i
.reg_operands
== 1
5811 && i
.op
[first_reg_op
+ 1].regs
== 0);
5812 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5813 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5818 if (i
.tm
.opcode_modifier
.shortform
)
5820 if (i
.types
[0].bitfield
.sreg2
5821 || i
.types
[0].bitfield
.sreg3
)
5823 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5824 && i
.op
[0].regs
->reg_num
== 1)
5826 as_bad (_("you can't `pop %scs'"), register_prefix
);
5829 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5830 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5835 /* The register or float register operand is in operand
5839 if (i
.types
[0].bitfield
.floatreg
5840 || operand_type_check (i
.types
[0], reg
))
5844 /* Register goes in low 3 bits of opcode. */
5845 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5846 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5848 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5850 /* Warn about some common errors, but press on regardless.
5851 The first case can be generated by gcc (<= 2.8.1). */
5852 if (i
.operands
== 2)
5854 /* Reversed arguments on faddp, fsubp, etc. */
5855 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5856 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5857 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5861 /* Extraneous `l' suffix on fp insn. */
5862 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5863 register_prefix
, i
.op
[0].regs
->reg_name
);
5868 else if (i
.tm
.opcode_modifier
.modrm
)
5870 /* The opcode is completed (modulo i.tm.extension_opcode which
5871 must be put into the modrm byte). Now, we make the modrm and
5872 index base bytes based on all the info we've collected. */
5874 default_seg
= build_modrm_byte ();
5876 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5880 else if (i
.tm
.opcode_modifier
.isstring
)
5882 /* For the string instructions that allow a segment override
5883 on one of their operands, the default segment is ds. */
5887 if (i
.tm
.base_opcode
== 0x8d /* lea */
5890 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5892 /* If a segment was explicitly specified, and the specified segment
5893 is not the default, use an opcode prefix to select it. If we
5894 never figured out what the default segment is, then default_seg
5895 will be zero at this point, and the specified segment prefix will
5897 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5899 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5905 static const seg_entry
*
5906 build_modrm_byte (void)
5908 const seg_entry
*default_seg
= 0;
5909 unsigned int source
, dest
;
5912 /* The first operand of instructions with VEX prefix and 3 sources
5913 must be VEX_Imm4. */
5914 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5917 unsigned int nds
, reg_slot
;
5920 if (i
.tm
.opcode_modifier
.veximmext
5921 && i
.tm
.opcode_modifier
.immext
)
5923 dest
= i
.operands
- 2;
5924 gas_assert (dest
== 3);
5927 dest
= i
.operands
- 1;
5930 /* There are 2 kinds of instructions:
5931 1. 5 operands: 4 register operands or 3 register operands
5932 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5933 VexW0 or VexW1. The destination must be either XMM, YMM or
5935 2. 4 operands: 4 register operands or 3 register operands
5936 plus 1 memory operand, VexXDS, and VexImmExt */
5937 gas_assert ((i
.reg_operands
== 4
5938 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5939 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5940 && (i
.tm
.opcode_modifier
.veximmext
5941 || (i
.imm_operands
== 1
5942 && i
.types
[0].bitfield
.vec_imm4
5943 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5944 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5945 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5946 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5947 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5949 if (i
.imm_operands
== 0)
5951 /* When there is no immediate operand, generate an 8bit
5952 immediate operand to encode the first operand. */
5953 exp
= &im_expressions
[i
.imm_operands
++];
5954 i
.op
[i
.operands
].imms
= exp
;
5955 i
.types
[i
.operands
] = imm8
;
5957 /* If VexW1 is set, the first operand is the source and
5958 the second operand is encoded in the immediate operand. */
5959 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5970 /* FMA swaps REG and NDS. */
5971 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5979 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5981 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5983 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5985 exp
->X_op
= O_constant
;
5986 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5987 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5991 unsigned int imm_slot
;
5993 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5995 /* If VexW0 is set, the third operand is the source and
5996 the second operand is encoded in the immediate
6003 /* VexW1 is set, the second operand is the source and
6004 the third operand is encoded in the immediate
6010 if (i
.tm
.opcode_modifier
.immext
)
6012 /* When ImmExt is set, the immdiate byte is the last
6014 imm_slot
= i
.operands
- 1;
6022 /* Turn on Imm8 so that output_imm will generate it. */
6023 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6026 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6028 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6030 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6032 i
.op
[imm_slot
].imms
->X_add_number
6033 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6034 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6037 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6038 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6040 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6042 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6047 /* i.reg_operands MUST be the number of real register operands;
6048 implicit registers do not count. If there are 3 register
6049 operands, it must be a instruction with VexNDS. For a
6050 instruction with VexNDD, the destination register is encoded
6051 in VEX prefix. If there are 4 register operands, it must be
6052 a instruction with VEX prefix and 3 sources. */
6053 if (i
.mem_operands
== 0
6054 && ((i
.reg_operands
== 2
6055 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6056 || (i
.reg_operands
== 3
6057 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6058 || (i
.reg_operands
== 4 && vex_3_sources
)))
6066 /* When there are 3 operands, one of them may be immediate,
6067 which may be the first or the last operand. Otherwise,
6068 the first operand must be shift count register (cl) or it
6069 is an instruction with VexNDS. */
6070 gas_assert (i
.imm_operands
== 1
6071 || (i
.imm_operands
== 0
6072 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6073 || i
.types
[0].bitfield
.shiftcount
)));
6074 if (operand_type_check (i
.types
[0], imm
)
6075 || i
.types
[0].bitfield
.shiftcount
)
6081 /* When there are 4 operands, the first two must be 8bit
6082 immediate operands. The source operand will be the 3rd
6085 For instructions with VexNDS, if the first operand
6086 an imm8, the source operand is the 2nd one. If the last
6087 operand is imm8, the source operand is the first one. */
6088 gas_assert ((i
.imm_operands
== 2
6089 && i
.types
[0].bitfield
.imm8
6090 && i
.types
[1].bitfield
.imm8
)
6091 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6092 && i
.imm_operands
== 1
6093 && (i
.types
[0].bitfield
.imm8
6094 || i
.types
[i
.operands
- 1].bitfield
.imm8
6096 if (i
.imm_operands
== 2)
6100 if (i
.types
[0].bitfield
.imm8
)
6107 if (i
.tm
.opcode_modifier
.evex
)
6109 /* For EVEX instructions, when there are 5 operands, the
6110 first one must be immediate operand. If the second one
6111 is immediate operand, the source operand is the 3th
6112 one. If the last one is immediate operand, the source
6113 operand is the 2nd one. */
6114 gas_assert (i
.imm_operands
== 2
6115 && i
.tm
.opcode_modifier
.sae
6116 && operand_type_check (i
.types
[0], imm
));
6117 if (operand_type_check (i
.types
[1], imm
))
6119 else if (operand_type_check (i
.types
[4], imm
))
6133 /* RC/SAE operand could be between DEST and SRC. That happens
6134 when one operand is GPR and the other one is XMM/YMM/ZMM
6136 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6139 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6141 /* For instructions with VexNDS, the register-only source
6142 operand must be 32/64bit integer, XMM, YMM or ZMM
6143 register. It is encoded in VEX prefix. We need to
6144 clear RegMem bit before calling operand_type_equal. */
6146 i386_operand_type op
;
6149 /* Check register-only source operand when two source
6150 operands are swapped. */
6151 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6152 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6160 op
= i
.tm
.operand_types
[vvvv
];
6161 op
.bitfield
.regmem
= 0;
6162 if ((dest
+ 1) >= i
.operands
6163 || (op
.bitfield
.reg32
!= 1
6164 && !op
.bitfield
.reg64
!= 1
6165 && !operand_type_equal (&op
, ®xmm
)
6166 && !operand_type_equal (&op
, ®ymm
)
6167 && !operand_type_equal (&op
, ®zmm
)
6168 && !operand_type_equal (&op
, ®mask
)))
6170 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6176 /* One of the register operands will be encoded in the i.tm.reg
6177 field, the other in the combined i.tm.mode and i.tm.regmem
6178 fields. If no form of this instruction supports a memory
6179 destination operand, then we assume the source operand may
6180 sometimes be a memory operand and so we need to store the
6181 destination in the i.rm.reg field. */
6182 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6183 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6185 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6186 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6187 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6189 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6191 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6193 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6198 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6199 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6200 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6202 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6204 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6206 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6209 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6211 if (!i
.types
[0].bitfield
.control
6212 && !i
.types
[1].bitfield
.control
)
6214 i
.rex
&= ~(REX_R
| REX_B
);
6215 add_prefix (LOCK_PREFIX_OPCODE
);
6219 { /* If it's not 2 reg operands... */
6224 unsigned int fake_zero_displacement
= 0;
6227 for (op
= 0; op
< i
.operands
; op
++)
6228 if (operand_type_check (i
.types
[op
], anymem
))
6230 gas_assert (op
< i
.operands
);
6232 if (i
.tm
.opcode_modifier
.vecsib
)
6234 if (i
.index_reg
->reg_num
== RegEiz
6235 || i
.index_reg
->reg_num
== RegRiz
)
6238 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6241 i
.sib
.base
= NO_BASE_REGISTER
;
6242 i
.sib
.scale
= i
.log2_scale_factor
;
6243 /* No Vec_Disp8 if there is no base. */
6244 i
.types
[op
].bitfield
.vec_disp8
= 0;
6245 i
.types
[op
].bitfield
.disp8
= 0;
6246 i
.types
[op
].bitfield
.disp16
= 0;
6247 i
.types
[op
].bitfield
.disp64
= 0;
6248 if (flag_code
!= CODE_64BIT
)
6250 /* Must be 32 bit */
6251 i
.types
[op
].bitfield
.disp32
= 1;
6252 i
.types
[op
].bitfield
.disp32s
= 0;
6256 i
.types
[op
].bitfield
.disp32
= 0;
6257 i
.types
[op
].bitfield
.disp32s
= 1;
6260 i
.sib
.index
= i
.index_reg
->reg_num
;
6261 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6263 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6269 if (i
.base_reg
== 0)
6272 if (!i
.disp_operands
)
6274 fake_zero_displacement
= 1;
6275 /* Instructions with VSIB byte need 32bit displacement
6276 if there is no base register. */
6277 if (i
.tm
.opcode_modifier
.vecsib
)
6278 i
.types
[op
].bitfield
.disp32
= 1;
6280 if (i
.index_reg
== 0)
6282 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6283 /* Operand is just <disp> */
6284 if (flag_code
== CODE_64BIT
)
6286 /* 64bit mode overwrites the 32bit absolute
6287 addressing by RIP relative addressing and
6288 absolute addressing is encoded by one of the
6289 redundant SIB forms. */
6290 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6291 i
.sib
.base
= NO_BASE_REGISTER
;
6292 i
.sib
.index
= NO_INDEX_REGISTER
;
6293 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6294 ? disp32s
: disp32
);
6296 else if ((flag_code
== CODE_16BIT
)
6297 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6299 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6300 i
.types
[op
] = disp16
;
6304 i
.rm
.regmem
= NO_BASE_REGISTER
;
6305 i
.types
[op
] = disp32
;
6308 else if (!i
.tm
.opcode_modifier
.vecsib
)
6310 /* !i.base_reg && i.index_reg */
6311 if (i
.index_reg
->reg_num
== RegEiz
6312 || i
.index_reg
->reg_num
== RegRiz
)
6313 i
.sib
.index
= NO_INDEX_REGISTER
;
6315 i
.sib
.index
= i
.index_reg
->reg_num
;
6316 i
.sib
.base
= NO_BASE_REGISTER
;
6317 i
.sib
.scale
= i
.log2_scale_factor
;
6318 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6319 /* No Vec_Disp8 if there is no base. */
6320 i
.types
[op
].bitfield
.vec_disp8
= 0;
6321 i
.types
[op
].bitfield
.disp8
= 0;
6322 i
.types
[op
].bitfield
.disp16
= 0;
6323 i
.types
[op
].bitfield
.disp64
= 0;
6324 if (flag_code
!= CODE_64BIT
)
6326 /* Must be 32 bit */
6327 i
.types
[op
].bitfield
.disp32
= 1;
6328 i
.types
[op
].bitfield
.disp32s
= 0;
6332 i
.types
[op
].bitfield
.disp32
= 0;
6333 i
.types
[op
].bitfield
.disp32s
= 1;
6335 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6339 /* RIP addressing for 64bit mode. */
6340 else if (i
.base_reg
->reg_num
== RegRip
||
6341 i
.base_reg
->reg_num
== RegEip
)
6343 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6344 i
.rm
.regmem
= NO_BASE_REGISTER
;
6345 i
.types
[op
].bitfield
.disp8
= 0;
6346 i
.types
[op
].bitfield
.disp16
= 0;
6347 i
.types
[op
].bitfield
.disp32
= 0;
6348 i
.types
[op
].bitfield
.disp32s
= 1;
6349 i
.types
[op
].bitfield
.disp64
= 0;
6350 i
.types
[op
].bitfield
.vec_disp8
= 0;
6351 i
.flags
[op
] |= Operand_PCrel
;
6352 if (! i
.disp_operands
)
6353 fake_zero_displacement
= 1;
6355 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6357 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6358 switch (i
.base_reg
->reg_num
)
6361 if (i
.index_reg
== 0)
6363 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6364 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6368 if (i
.index_reg
== 0)
6371 if (operand_type_check (i
.types
[op
], disp
) == 0)
6373 /* fake (%bp) into 0(%bp) */
6374 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6375 i
.types
[op
].bitfield
.vec_disp8
= 1;
6377 i
.types
[op
].bitfield
.disp8
= 1;
6378 fake_zero_displacement
= 1;
6381 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6382 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6384 default: /* (%si) -> 4 or (%di) -> 5 */
6385 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6387 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6389 else /* i.base_reg and 32/64 bit mode */
6391 if (flag_code
== CODE_64BIT
6392 && operand_type_check (i
.types
[op
], disp
))
6394 i386_operand_type temp
;
6395 operand_type_set (&temp
, 0);
6396 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6397 temp
.bitfield
.vec_disp8
6398 = i
.types
[op
].bitfield
.vec_disp8
;
6400 if (i
.prefix
[ADDR_PREFIX
] == 0)
6401 i
.types
[op
].bitfield
.disp32s
= 1;
6403 i
.types
[op
].bitfield
.disp32
= 1;
6406 if (!i
.tm
.opcode_modifier
.vecsib
)
6407 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6408 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6410 i
.sib
.base
= i
.base_reg
->reg_num
;
6411 /* x86-64 ignores REX prefix bit here to avoid decoder
6413 if (!(i
.base_reg
->reg_flags
& RegRex
)
6414 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6415 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6417 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6419 fake_zero_displacement
= 1;
6420 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6421 i
.types
[op
].bitfield
.vec_disp8
= 1;
6423 i
.types
[op
].bitfield
.disp8
= 1;
6425 i
.sib
.scale
= i
.log2_scale_factor
;
6426 if (i
.index_reg
== 0)
6428 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6429 /* <disp>(%esp) becomes two byte modrm with no index
6430 register. We've already stored the code for esp
6431 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6432 Any base register besides %esp will not use the
6433 extra modrm byte. */
6434 i
.sib
.index
= NO_INDEX_REGISTER
;
6436 else if (!i
.tm
.opcode_modifier
.vecsib
)
6438 if (i
.index_reg
->reg_num
== RegEiz
6439 || i
.index_reg
->reg_num
== RegRiz
)
6440 i
.sib
.index
= NO_INDEX_REGISTER
;
6442 i
.sib
.index
= i
.index_reg
->reg_num
;
6443 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6444 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6449 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6450 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6454 if (!fake_zero_displacement
6458 fake_zero_displacement
= 1;
6459 if (i
.disp_encoding
== disp_encoding_8bit
)
6460 i
.types
[op
].bitfield
.disp8
= 1;
6462 i
.types
[op
].bitfield
.disp32
= 1;
6464 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6468 if (fake_zero_displacement
)
6470 /* Fakes a zero displacement assuming that i.types[op]
6471 holds the correct displacement size. */
6474 gas_assert (i
.op
[op
].disps
== 0);
6475 exp
= &disp_expressions
[i
.disp_operands
++];
6476 i
.op
[op
].disps
= exp
;
6477 exp
->X_op
= O_constant
;
6478 exp
->X_add_number
= 0;
6479 exp
->X_add_symbol
= (symbolS
*) 0;
6480 exp
->X_op_symbol
= (symbolS
*) 0;
6488 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6490 if (operand_type_check (i
.types
[0], imm
))
6491 i
.vex
.register_specifier
= NULL
;
6494 /* VEX.vvvv encodes one of the sources when the first
6495 operand is not an immediate. */
6496 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6497 i
.vex
.register_specifier
= i
.op
[0].regs
;
6499 i
.vex
.register_specifier
= i
.op
[1].regs
;
6502 /* Destination is a XMM register encoded in the ModRM.reg
6504 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6505 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6508 /* ModRM.rm and VEX.B encodes the other source. */
6509 if (!i
.mem_operands
)
6513 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6514 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6516 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6518 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6522 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6524 i
.vex
.register_specifier
= i
.op
[2].regs
;
6525 if (!i
.mem_operands
)
6528 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6529 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6533 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6534 (if any) based on i.tm.extension_opcode. Again, we must be
6535 careful to make sure that segment/control/debug/test/MMX
6536 registers are coded into the i.rm.reg field. */
6537 else if (i
.reg_operands
)
6540 unsigned int vex_reg
= ~0;
6542 for (op
= 0; op
< i
.operands
; op
++)
6543 if (i
.types
[op
].bitfield
.reg8
6544 || i
.types
[op
].bitfield
.reg16
6545 || i
.types
[op
].bitfield
.reg32
6546 || i
.types
[op
].bitfield
.reg64
6547 || i
.types
[op
].bitfield
.regmmx
6548 || i
.types
[op
].bitfield
.regxmm
6549 || i
.types
[op
].bitfield
.regymm
6550 || i
.types
[op
].bitfield
.regbnd
6551 || i
.types
[op
].bitfield
.regzmm
6552 || i
.types
[op
].bitfield
.regmask
6553 || i
.types
[op
].bitfield
.sreg2
6554 || i
.types
[op
].bitfield
.sreg3
6555 || i
.types
[op
].bitfield
.control
6556 || i
.types
[op
].bitfield
.debug
6557 || i
.types
[op
].bitfield
.test
)
6562 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6564 /* For instructions with VexNDS, the register-only
6565 source operand is encoded in VEX prefix. */
6566 gas_assert (mem
!= (unsigned int) ~0);
6571 gas_assert (op
< i
.operands
);
6575 /* Check register-only source operand when two source
6576 operands are swapped. */
6577 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6578 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6582 gas_assert (mem
== (vex_reg
+ 1)
6583 && op
< i
.operands
);
6588 gas_assert (vex_reg
< i
.operands
);
6592 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6594 /* For instructions with VexNDD, the register destination
6595 is encoded in VEX prefix. */
6596 if (i
.mem_operands
== 0)
6598 /* There is no memory operand. */
6599 gas_assert ((op
+ 2) == i
.operands
);
6604 /* There are only 2 operands. */
6605 gas_assert (op
< 2 && i
.operands
== 2);
6610 gas_assert (op
< i
.operands
);
6612 if (vex_reg
!= (unsigned int) ~0)
6614 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6616 if (type
->bitfield
.reg32
!= 1
6617 && type
->bitfield
.reg64
!= 1
6618 && !operand_type_equal (type
, ®xmm
)
6619 && !operand_type_equal (type
, ®ymm
)
6620 && !operand_type_equal (type
, ®zmm
)
6621 && !operand_type_equal (type
, ®mask
))
6624 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6627 /* Don't set OP operand twice. */
6630 /* If there is an extension opcode to put here, the
6631 register number must be put into the regmem field. */
6632 if (i
.tm
.extension_opcode
!= None
)
6634 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6635 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6637 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6642 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6643 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6645 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6650 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6651 must set it to 3 to indicate this is a register operand
6652 in the regmem field. */
6653 if (!i
.mem_operands
)
6657 /* Fill in i.rm.reg field with extension opcode (if any). */
6658 if (i
.tm
.extension_opcode
!= None
)
6659 i
.rm
.reg
= i
.tm
.extension_opcode
;
6665 output_branch (void)
6671 relax_substateT subtype
;
6675 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6676 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6679 if (i
.prefix
[DATA_PREFIX
] != 0)
6685 /* Pentium4 branch hints. */
6686 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6687 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6692 if (i
.prefix
[REX_PREFIX
] != 0)
6698 /* BND prefixed jump. */
6699 if (i
.prefix
[BND_PREFIX
] != 0)
6701 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6705 if (i
.prefixes
!= 0 && !intel_syntax
)
6706 as_warn (_("skipping prefixes on this instruction"));
6708 /* It's always a symbol; End frag & setup for relax.
6709 Make sure there is enough room in this frag for the largest
6710 instruction we may generate in md_convert_frag. This is 2
6711 bytes for the opcode and room for the prefix and largest
6713 frag_grow (prefix
+ 2 + 4);
6714 /* Prefix and 1 opcode byte go in fr_fix. */
6715 p
= frag_more (prefix
+ 1);
6716 if (i
.prefix
[DATA_PREFIX
] != 0)
6717 *p
++ = DATA_PREFIX_OPCODE
;
6718 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6719 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6720 *p
++ = i
.prefix
[SEG_PREFIX
];
6721 if (i
.prefix
[REX_PREFIX
] != 0)
6722 *p
++ = i
.prefix
[REX_PREFIX
];
6723 *p
= i
.tm
.base_opcode
;
6725 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6726 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6727 else if (cpu_arch_flags
.bitfield
.cpui386
)
6728 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6730 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6733 sym
= i
.op
[0].disps
->X_add_symbol
;
6734 off
= i
.op
[0].disps
->X_add_number
;
6736 if (i
.op
[0].disps
->X_op
!= O_constant
6737 && i
.op
[0].disps
->X_op
!= O_symbol
)
6739 /* Handle complex expressions. */
6740 sym
= make_expr_symbol (i
.op
[0].disps
);
6744 /* 1 possible extra opcode + 4 byte displacement go in var part.
6745 Pass reloc in fr_var. */
6746 frag_var (rs_machine_dependent
, 5,
6748 || i
.reloc
[0] != NO_RELOC
6749 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6751 : BFD_RELOC_X86_64_PC32_BND
),
6752 subtype
, sym
, off
, p
);
6762 if (i
.tm
.opcode_modifier
.jumpbyte
)
6764 /* This is a loop or jecxz type instruction. */
6766 if (i
.prefix
[ADDR_PREFIX
] != 0)
6768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6771 /* Pentium4 branch hints. */
6772 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6773 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6775 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6784 if (flag_code
== CODE_16BIT
)
6787 if (i
.prefix
[DATA_PREFIX
] != 0)
6789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6799 if (i
.prefix
[REX_PREFIX
] != 0)
6801 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6805 /* BND prefixed jump. */
6806 if (i
.prefix
[BND_PREFIX
] != 0)
6808 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6812 if (i
.prefixes
!= 0 && !intel_syntax
)
6813 as_warn (_("skipping prefixes on this instruction"));
6815 p
= frag_more (i
.tm
.opcode_length
+ size
);
6816 switch (i
.tm
.opcode_length
)
6819 *p
++ = i
.tm
.base_opcode
>> 8;
6821 *p
++ = i
.tm
.base_opcode
;
6827 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6828 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6829 (i
.bnd_prefix
!= NULL
6833 /* All jumps handled here are signed, but don't use a signed limit
6834 check for 32 and 16 bit jumps as we want to allow wrap around at
6835 4G and 64k respectively. */
6837 fixP
->fx_signed
= 1;
6841 output_interseg_jump (void)
6849 if (flag_code
== CODE_16BIT
)
6853 if (i
.prefix
[DATA_PREFIX
] != 0)
6859 if (i
.prefix
[REX_PREFIX
] != 0)
6869 if (i
.prefixes
!= 0 && !intel_syntax
)
6870 as_warn (_("skipping prefixes on this instruction"));
6872 /* 1 opcode; 2 segment; offset */
6873 p
= frag_more (prefix
+ 1 + 2 + size
);
6875 if (i
.prefix
[DATA_PREFIX
] != 0)
6876 *p
++ = DATA_PREFIX_OPCODE
;
6878 if (i
.prefix
[REX_PREFIX
] != 0)
6879 *p
++ = i
.prefix
[REX_PREFIX
];
6881 *p
++ = i
.tm
.base_opcode
;
6882 if (i
.op
[1].imms
->X_op
== O_constant
)
6884 offsetT n
= i
.op
[1].imms
->X_add_number
;
6887 && !fits_in_unsigned_word (n
)
6888 && !fits_in_signed_word (n
))
6890 as_bad (_("16-bit jump out of range"));
6893 md_number_to_chars (p
, n
, size
);
6896 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6897 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6898 if (i
.op
[0].imms
->X_op
!= O_constant
)
6899 as_bad (_("can't handle non absolute segment in `%s'"),
6901 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6907 fragS
*insn_start_frag
;
6908 offsetT insn_start_off
;
6910 /* Tie dwarf2 debug info to the address at the start of the insn.
6911 We can't do this after the insn has been output as the current
6912 frag may have been closed off. eg. by frag_var. */
6913 dwarf2_emit_insn (0);
6915 insn_start_frag
= frag_now
;
6916 insn_start_off
= frag_now_fix ();
6919 if (i
.tm
.opcode_modifier
.jump
)
6921 else if (i
.tm
.opcode_modifier
.jumpbyte
6922 || i
.tm
.opcode_modifier
.jumpdword
)
6924 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6925 output_interseg_jump ();
6928 /* Output normal instructions here. */
6932 unsigned int prefix
;
6934 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6935 don't need the explicit prefix. */
6936 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6938 switch (i
.tm
.opcode_length
)
6941 if (i
.tm
.base_opcode
& 0xff000000)
6943 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6948 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6950 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6951 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6954 if (prefix
!= REPE_PREFIX_OPCODE
6955 || (i
.prefix
[REP_PREFIX
]
6956 != REPE_PREFIX_OPCODE
))
6957 add_prefix (prefix
);
6960 add_prefix (prefix
);
6969 /* The prefix bytes. */
6970 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6972 FRAG_APPEND_1_CHAR (*q
);
6976 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6981 /* REX byte is encoded in VEX prefix. */
6985 FRAG_APPEND_1_CHAR (*q
);
6988 /* There should be no other prefixes for instructions
6993 /* For EVEX instructions i.vrex should become 0 after
6994 build_evex_prefix. For VEX instructions upper 16 registers
6995 aren't available, so VREX should be 0. */
6998 /* Now the VEX prefix. */
6999 p
= frag_more (i
.vex
.length
);
7000 for (j
= 0; j
< i
.vex
.length
; j
++)
7001 p
[j
] = i
.vex
.bytes
[j
];
7004 /* Now the opcode; be careful about word order here! */
7005 if (i
.tm
.opcode_length
== 1)
7007 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7011 switch (i
.tm
.opcode_length
)
7015 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7016 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7020 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7030 /* Put out high byte first: can't use md_number_to_chars! */
7031 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7032 *p
= i
.tm
.base_opcode
& 0xff;
7035 /* Now the modrm byte and sib byte (if present). */
7036 if (i
.tm
.opcode_modifier
.modrm
)
7038 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7041 /* If i.rm.regmem == ESP (4)
7042 && i.rm.mode != (Register mode)
7044 ==> need second modrm byte. */
7045 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7047 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7048 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7050 | i
.sib
.scale
<< 6));
7053 if (i
.disp_operands
)
7054 output_disp (insn_start_frag
, insn_start_off
);
7057 output_imm (insn_start_frag
, insn_start_off
);
7063 pi ("" /*line*/, &i
);
7065 #endif /* DEBUG386 */
7068 /* Return the size of the displacement operand N. */
7071 disp_size (unsigned int n
)
7075 /* Vec_Disp8 has to be 8bit. */
7076 if (i
.types
[n
].bitfield
.vec_disp8
)
7078 else if (i
.types
[n
].bitfield
.disp64
)
7080 else if (i
.types
[n
].bitfield
.disp8
)
7082 else if (i
.types
[n
].bitfield
.disp16
)
7087 /* Return the size of the immediate operand N. */
7090 imm_size (unsigned int n
)
7093 if (i
.types
[n
].bitfield
.imm64
)
7095 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7097 else if (i
.types
[n
].bitfield
.imm16
)
7103 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7108 for (n
= 0; n
< i
.operands
; n
++)
7110 if (i
.types
[n
].bitfield
.vec_disp8
7111 || operand_type_check (i
.types
[n
], disp
))
7113 if (i
.op
[n
].disps
->X_op
== O_constant
)
7115 int size
= disp_size (n
);
7116 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7118 if (i
.types
[n
].bitfield
.vec_disp8
)
7120 val
= offset_in_range (val
, size
);
7121 p
= frag_more (size
);
7122 md_number_to_chars (p
, val
, size
);
7126 enum bfd_reloc_code_real reloc_type
;
7127 int size
= disp_size (n
);
7128 int sign
= i
.types
[n
].bitfield
.disp32s
;
7129 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7131 /* We can't have 8 bit displacement here. */
7132 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7134 /* The PC relative address is computed relative
7135 to the instruction boundary, so in case immediate
7136 fields follows, we need to adjust the value. */
7137 if (pcrel
&& i
.imm_operands
)
7142 for (n1
= 0; n1
< i
.operands
; n1
++)
7143 if (operand_type_check (i
.types
[n1
], imm
))
7145 /* Only one immediate is allowed for PC
7146 relative address. */
7147 gas_assert (sz
== 0);
7149 i
.op
[n
].disps
->X_add_number
-= sz
;
7151 /* We should find the immediate. */
7152 gas_assert (sz
!= 0);
7155 p
= frag_more (size
);
7156 reloc_type
= reloc (size
, pcrel
, sign
,
7157 (i
.bnd_prefix
!= NULL
7161 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7162 && (((reloc_type
== BFD_RELOC_32
7163 || reloc_type
== BFD_RELOC_X86_64_32S
7164 || (reloc_type
== BFD_RELOC_64
7166 && (i
.op
[n
].disps
->X_op
== O_symbol
7167 || (i
.op
[n
].disps
->X_op
== O_add
7168 && ((symbol_get_value_expression
7169 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7171 || reloc_type
== BFD_RELOC_32_PCREL
))
7175 if (insn_start_frag
== frag_now
)
7176 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7181 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7182 for (fr
= insn_start_frag
->fr_next
;
7183 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7185 add
+= p
- frag_now
->fr_literal
;
7190 reloc_type
= BFD_RELOC_386_GOTPC
;
7191 i
.op
[n
].imms
->X_add_number
+= add
;
7193 else if (reloc_type
== BFD_RELOC_64
)
7194 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7196 /* Don't do the adjustment for x86-64, as there
7197 the pcrel addressing is relative to the _next_
7198 insn, and that is taken care of in other code. */
7199 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7201 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7202 i
.op
[n
].disps
, pcrel
, reloc_type
);
7209 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7214 for (n
= 0; n
< i
.operands
; n
++)
7216 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7217 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7220 if (operand_type_check (i
.types
[n
], imm
))
7222 if (i
.op
[n
].imms
->X_op
== O_constant
)
7224 int size
= imm_size (n
);
7227 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7229 p
= frag_more (size
);
7230 md_number_to_chars (p
, val
, size
);
7234 /* Not absolute_section.
7235 Need a 32-bit fixup (don't support 8bit
7236 non-absolute imms). Try to support other
7238 enum bfd_reloc_code_real reloc_type
;
7239 int size
= imm_size (n
);
7242 if (i
.types
[n
].bitfield
.imm32s
7243 && (i
.suffix
== QWORD_MNEM_SUFFIX
7244 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7249 p
= frag_more (size
);
7250 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7252 /* This is tough to explain. We end up with this one if we
7253 * have operands that look like
7254 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7255 * obtain the absolute address of the GOT, and it is strongly
7256 * preferable from a performance point of view to avoid using
7257 * a runtime relocation for this. The actual sequence of
7258 * instructions often look something like:
7263 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7265 * The call and pop essentially return the absolute address
7266 * of the label .L66 and store it in %ebx. The linker itself
7267 * will ultimately change the first operand of the addl so
7268 * that %ebx points to the GOT, but to keep things simple, the
7269 * .o file must have this operand set so that it generates not
7270 * the absolute address of .L66, but the absolute address of
7271 * itself. This allows the linker itself simply treat a GOTPC
7272 * relocation as asking for a pcrel offset to the GOT to be
7273 * added in, and the addend of the relocation is stored in the
7274 * operand field for the instruction itself.
7276 * Our job here is to fix the operand so that it would add
7277 * the correct offset so that %ebx would point to itself. The
7278 * thing that is tricky is that .-.L66 will point to the
7279 * beginning of the instruction, so we need to further modify
7280 * the operand so that it will point to itself. There are
7281 * other cases where you have something like:
7283 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7285 * and here no correction would be required. Internally in
7286 * the assembler we treat operands of this form as not being
7287 * pcrel since the '.' is explicitly mentioned, and I wonder
7288 * whether it would simplify matters to do it this way. Who
7289 * knows. In earlier versions of the PIC patches, the
7290 * pcrel_adjust field was used to store the correction, but
7291 * since the expression is not pcrel, I felt it would be
7292 * confusing to do it this way. */
7294 if ((reloc_type
== BFD_RELOC_32
7295 || reloc_type
== BFD_RELOC_X86_64_32S
7296 || reloc_type
== BFD_RELOC_64
)
7298 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7299 && (i
.op
[n
].imms
->X_op
== O_symbol
7300 || (i
.op
[n
].imms
->X_op
== O_add
7301 && ((symbol_get_value_expression
7302 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7307 if (insn_start_frag
== frag_now
)
7308 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7313 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7314 for (fr
= insn_start_frag
->fr_next
;
7315 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7317 add
+= p
- frag_now
->fr_literal
;
7321 reloc_type
= BFD_RELOC_386_GOTPC
;
7323 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7325 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7326 i
.op
[n
].imms
->X_add_number
+= add
;
7328 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7329 i
.op
[n
].imms
, 0, reloc_type
);
7335 /* x86_cons_fix_new is called via the expression parsing code when a
7336 reloc is needed. We use this hook to get the correct .got reloc. */
7337 static int cons_sign
= -1;
7340 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7341 expressionS
*exp
, bfd_reloc_code_real_type r
)
7343 r
= reloc (len
, 0, cons_sign
, 0, r
);
7346 if (exp
->X_op
== O_secrel
)
7348 exp
->X_op
= O_symbol
;
7349 r
= BFD_RELOC_32_SECREL
;
7353 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7356 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7357 purpose of the `.dc.a' internal pseudo-op. */
7360 x86_address_bytes (void)
7362 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7364 return stdoutput
->arch_info
->bits_per_address
/ 8;
7367 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7369 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7371 /* Parse operands of the form
7372 <symbol>@GOTOFF+<nnn>
7373 and similar .plt or .got references.
7375 If we find one, set up the correct relocation in RELOC and copy the
7376 input string, minus the `@GOTOFF' into a malloc'd buffer for
7377 parsing by the calling routine. Return this buffer, and if ADJUST
7378 is non-null set it to the length of the string we removed from the
7379 input line. Otherwise return NULL. */
7381 lex_got (enum bfd_reloc_code_real
*rel
,
7383 i386_operand_type
*types
,
7386 /* Some of the relocations depend on the size of what field is to
7387 be relocated. But in our callers i386_immediate and i386_displacement
7388 we don't yet know the operand size (this will be set by insn
7389 matching). Hence we record the word32 relocation here,
7390 and adjust the reloc according to the real size in reloc(). */
7391 static const struct {
7394 const enum bfd_reloc_code_real rel
[2];
7395 const i386_operand_type types64
;
7397 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7398 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7400 OPERAND_TYPE_IMM32_64
},
7402 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7403 BFD_RELOC_X86_64_PLTOFF64
},
7404 OPERAND_TYPE_IMM64
},
7405 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7406 BFD_RELOC_X86_64_PLT32
},
7407 OPERAND_TYPE_IMM32_32S_DISP32
},
7408 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7409 BFD_RELOC_X86_64_GOTPLT64
},
7410 OPERAND_TYPE_IMM64_DISP64
},
7411 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7412 BFD_RELOC_X86_64_GOTOFF64
},
7413 OPERAND_TYPE_IMM64_DISP64
},
7414 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7415 BFD_RELOC_X86_64_GOTPCREL
},
7416 OPERAND_TYPE_IMM32_32S_DISP32
},
7417 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7418 BFD_RELOC_X86_64_TLSGD
},
7419 OPERAND_TYPE_IMM32_32S_DISP32
},
7420 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7421 _dummy_first_bfd_reloc_code_real
},
7422 OPERAND_TYPE_NONE
},
7423 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7424 BFD_RELOC_X86_64_TLSLD
},
7425 OPERAND_TYPE_IMM32_32S_DISP32
},
7426 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7427 BFD_RELOC_X86_64_GOTTPOFF
},
7428 OPERAND_TYPE_IMM32_32S_DISP32
},
7429 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7430 BFD_RELOC_X86_64_TPOFF32
},
7431 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7432 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7433 _dummy_first_bfd_reloc_code_real
},
7434 OPERAND_TYPE_NONE
},
7435 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7436 BFD_RELOC_X86_64_DTPOFF32
},
7437 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7438 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7439 _dummy_first_bfd_reloc_code_real
},
7440 OPERAND_TYPE_NONE
},
7441 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7442 _dummy_first_bfd_reloc_code_real
},
7443 OPERAND_TYPE_NONE
},
7444 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7445 BFD_RELOC_X86_64_GOT32
},
7446 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7447 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7448 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7449 OPERAND_TYPE_IMM32_32S_DISP32
},
7450 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7451 BFD_RELOC_X86_64_TLSDESC_CALL
},
7452 OPERAND_TYPE_IMM32_32S_DISP32
},
7457 #if defined (OBJ_MAYBE_ELF)
7462 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7463 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7466 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7468 int len
= gotrel
[j
].len
;
7469 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7471 if (gotrel
[j
].rel
[object_64bit
] != 0)
7474 char *tmpbuf
, *past_reloc
;
7476 *rel
= gotrel
[j
].rel
[object_64bit
];
7480 if (flag_code
!= CODE_64BIT
)
7482 types
->bitfield
.imm32
= 1;
7483 types
->bitfield
.disp32
= 1;
7486 *types
= gotrel
[j
].types64
;
7489 if (j
!= 0 && GOT_symbol
== NULL
)
7490 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7492 /* The length of the first part of our input line. */
7493 first
= cp
- input_line_pointer
;
7495 /* The second part goes from after the reloc token until
7496 (and including) an end_of_line char or comma. */
7497 past_reloc
= cp
+ 1 + len
;
7499 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7501 second
= cp
+ 1 - past_reloc
;
7503 /* Allocate and copy string. The trailing NUL shouldn't
7504 be necessary, but be safe. */
7505 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7506 memcpy (tmpbuf
, input_line_pointer
, first
);
7507 if (second
!= 0 && *past_reloc
!= ' ')
7508 /* Replace the relocation token with ' ', so that
7509 errors like foo@GOTOFF1 will be detected. */
7510 tmpbuf
[first
++] = ' ';
7512 /* Increment length by 1 if the relocation token is
7517 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7518 tmpbuf
[first
+ second
] = '\0';
7519 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7520 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7524 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7525 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7530 /* Might be a symbol version string. Don't as_bad here. */
7539 /* Parse operands of the form
7540 <symbol>@SECREL32+<nnn>
7542 If we find one, set up the correct relocation in RELOC and copy the
7543 input string, minus the `@SECREL32' into a malloc'd buffer for
7544 parsing by the calling routine. Return this buffer, and if ADJUST
7545 is non-null set it to the length of the string we removed from the
7546 input line. Otherwise return NULL.
7548 This function is copied from the ELF version above adjusted for PE targets. */
7551 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7552 int *adjust ATTRIBUTE_UNUSED
,
7553 i386_operand_type
*types
,
7554 int bnd_prefix ATTRIBUTE_UNUSED
)
7560 const enum bfd_reloc_code_real rel
[2];
7561 const i386_operand_type types64
;
7565 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7566 BFD_RELOC_32_SECREL
},
7567 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7573 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7574 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7577 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7579 int len
= gotrel
[j
].len
;
7581 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7583 if (gotrel
[j
].rel
[object_64bit
] != 0)
7586 char *tmpbuf
, *past_reloc
;
7588 *rel
= gotrel
[j
].rel
[object_64bit
];
7594 if (flag_code
!= CODE_64BIT
)
7596 types
->bitfield
.imm32
= 1;
7597 types
->bitfield
.disp32
= 1;
7600 *types
= gotrel
[j
].types64
;
7603 /* The length of the first part of our input line. */
7604 first
= cp
- input_line_pointer
;
7606 /* The second part goes from after the reloc token until
7607 (and including) an end_of_line char or comma. */
7608 past_reloc
= cp
+ 1 + len
;
7610 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7612 second
= cp
+ 1 - past_reloc
;
7614 /* Allocate and copy string. The trailing NUL shouldn't
7615 be necessary, but be safe. */
7616 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7617 memcpy (tmpbuf
, input_line_pointer
, first
);
7618 if (second
!= 0 && *past_reloc
!= ' ')
7619 /* Replace the relocation token with ' ', so that
7620 errors like foo@SECLREL321 will be detected. */
7621 tmpbuf
[first
++] = ' ';
7622 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7623 tmpbuf
[first
+ second
] = '\0';
7627 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7628 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7633 /* Might be a symbol version string. Don't as_bad here. */
7639 bfd_reloc_code_real_type
7640 x86_cons (expressionS
*exp
, int size
)
7642 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7644 intel_syntax
= -intel_syntax
;
7647 if (size
== 4 || (object_64bit
&& size
== 8))
7649 /* Handle @GOTOFF and the like in an expression. */
7651 char *gotfree_input_line
;
7654 save
= input_line_pointer
;
7655 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7656 if (gotfree_input_line
)
7657 input_line_pointer
= gotfree_input_line
;
7661 if (gotfree_input_line
)
7663 /* expression () has merrily parsed up to the end of line,
7664 or a comma - in the wrong buffer. Transfer how far
7665 input_line_pointer has moved to the right buffer. */
7666 input_line_pointer
= (save
7667 + (input_line_pointer
- gotfree_input_line
)
7669 free (gotfree_input_line
);
7670 if (exp
->X_op
== O_constant
7671 || exp
->X_op
== O_absent
7672 || exp
->X_op
== O_illegal
7673 || exp
->X_op
== O_register
7674 || exp
->X_op
== O_big
)
7676 char c
= *input_line_pointer
;
7677 *input_line_pointer
= 0;
7678 as_bad (_("missing or invalid expression `%s'"), save
);
7679 *input_line_pointer
= c
;
7686 intel_syntax
= -intel_syntax
;
7689 i386_intel_simplify (exp
);
7695 signed_cons (int size
)
7697 if (flag_code
== CODE_64BIT
)
7705 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7712 if (exp
.X_op
== O_symbol
)
7713 exp
.X_op
= O_secrel
;
7715 emit_expr (&exp
, 4);
7717 while (*input_line_pointer
++ == ',');
7719 input_line_pointer
--;
7720 demand_empty_rest_of_line ();
7724 /* Handle Vector operations. */
7727 check_VecOperations (char *op_string
, char *op_end
)
7729 const reg_entry
*mask
;
7734 && (op_end
== NULL
|| op_string
< op_end
))
7737 if (*op_string
== '{')
7741 /* Check broadcasts. */
7742 if (strncmp (op_string
, "1to", 3) == 0)
7747 goto duplicated_vec_op
;
7750 if (*op_string
== '8')
7751 bcst_type
= BROADCAST_1TO8
;
7752 else if (*op_string
== '1'
7753 && *(op_string
+1) == '6')
7755 bcst_type
= BROADCAST_1TO16
;
7760 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7765 broadcast_op
.type
= bcst_type
;
7766 broadcast_op
.operand
= this_operand
;
7767 i
.broadcast
= &broadcast_op
;
7769 /* Check masking operation. */
7770 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7772 /* k0 can't be used for write mask. */
7773 if (mask
->reg_num
== 0)
7775 as_bad (_("`%s' can't be used for write mask"),
7782 mask_op
.mask
= mask
;
7783 mask_op
.zeroing
= 0;
7784 mask_op
.operand
= this_operand
;
7790 goto duplicated_vec_op
;
7792 i
.mask
->mask
= mask
;
7794 /* Only "{z}" is allowed here. No need to check
7795 zeroing mask explicitly. */
7796 if (i
.mask
->operand
!= this_operand
)
7798 as_bad (_("invalid write mask `%s'"), saved
);
7805 /* Check zeroing-flag for masking operation. */
7806 else if (*op_string
== 'z')
7810 mask_op
.mask
= NULL
;
7811 mask_op
.zeroing
= 1;
7812 mask_op
.operand
= this_operand
;
7817 if (i
.mask
->zeroing
)
7820 as_bad (_("duplicated `%s'"), saved
);
7824 i
.mask
->zeroing
= 1;
7826 /* Only "{%k}" is allowed here. No need to check mask
7827 register explicitly. */
7828 if (i
.mask
->operand
!= this_operand
)
7830 as_bad (_("invalid zeroing-masking `%s'"),
7839 goto unknown_vec_op
;
7841 if (*op_string
!= '}')
7843 as_bad (_("missing `}' in `%s'"), saved
);
7850 /* We don't know this one. */
7851 as_bad (_("unknown vector operation: `%s'"), saved
);
7859 i386_immediate (char *imm_start
)
7861 char *save_input_line_pointer
;
7862 char *gotfree_input_line
;
7865 i386_operand_type types
;
7867 operand_type_set (&types
, ~0);
7869 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7871 as_bad (_("at most %d immediate operands are allowed"),
7872 MAX_IMMEDIATE_OPERANDS
);
7876 exp
= &im_expressions
[i
.imm_operands
++];
7877 i
.op
[this_operand
].imms
= exp
;
7879 if (is_space_char (*imm_start
))
7882 save_input_line_pointer
= input_line_pointer
;
7883 input_line_pointer
= imm_start
;
7885 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7886 (i
.bnd_prefix
!= NULL
7887 || add_bnd_prefix
));
7888 if (gotfree_input_line
)
7889 input_line_pointer
= gotfree_input_line
;
7891 exp_seg
= expression (exp
);
7895 /* Handle vector operations. */
7896 if (*input_line_pointer
== '{')
7898 input_line_pointer
= check_VecOperations (input_line_pointer
,
7900 if (input_line_pointer
== NULL
)
7904 if (*input_line_pointer
)
7905 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7907 input_line_pointer
= save_input_line_pointer
;
7908 if (gotfree_input_line
)
7910 free (gotfree_input_line
);
7912 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7913 exp
->X_op
= O_illegal
;
7916 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7920 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7921 i386_operand_type types
, const char *imm_start
)
7923 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7926 as_bad (_("missing or invalid immediate expression `%s'"),
7930 else if (exp
->X_op
== O_constant
)
7932 /* Size it properly later. */
7933 i
.types
[this_operand
].bitfield
.imm64
= 1;
7934 /* If not 64bit, sign extend val. */
7935 if (flag_code
!= CODE_64BIT
7936 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7938 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7940 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7941 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7942 && exp_seg
!= absolute_section
7943 && exp_seg
!= text_section
7944 && exp_seg
!= data_section
7945 && exp_seg
!= bss_section
7946 && exp_seg
!= undefined_section
7947 && !bfd_is_com_section (exp_seg
))
7949 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7953 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7956 as_bad (_("illegal immediate register operand %s"), imm_start
);
7961 /* This is an address. The size of the address will be
7962 determined later, depending on destination register,
7963 suffix, or the default for the section. */
7964 i
.types
[this_operand
].bitfield
.imm8
= 1;
7965 i
.types
[this_operand
].bitfield
.imm16
= 1;
7966 i
.types
[this_operand
].bitfield
.imm32
= 1;
7967 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7968 i
.types
[this_operand
].bitfield
.imm64
= 1;
7969 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7977 i386_scale (char *scale
)
7980 char *save
= input_line_pointer
;
7982 input_line_pointer
= scale
;
7983 val
= get_absolute_expression ();
7988 i
.log2_scale_factor
= 0;
7991 i
.log2_scale_factor
= 1;
7994 i
.log2_scale_factor
= 2;
7997 i
.log2_scale_factor
= 3;
8001 char sep
= *input_line_pointer
;
8003 *input_line_pointer
= '\0';
8004 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8006 *input_line_pointer
= sep
;
8007 input_line_pointer
= save
;
8011 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8013 as_warn (_("scale factor of %d without an index register"),
8014 1 << i
.log2_scale_factor
);
8015 i
.log2_scale_factor
= 0;
8017 scale
= input_line_pointer
;
8018 input_line_pointer
= save
;
8023 i386_displacement (char *disp_start
, char *disp_end
)
8027 char *save_input_line_pointer
;
8028 char *gotfree_input_line
;
8030 i386_operand_type bigdisp
, types
= anydisp
;
8033 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8035 as_bad (_("at most %d displacement operands are allowed"),
8036 MAX_MEMORY_OPERANDS
);
8040 operand_type_set (&bigdisp
, 0);
8041 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8042 || (!current_templates
->start
->opcode_modifier
.jump
8043 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8045 bigdisp
.bitfield
.disp32
= 1;
8046 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8047 if (flag_code
== CODE_64BIT
)
8051 bigdisp
.bitfield
.disp32s
= 1;
8052 bigdisp
.bitfield
.disp64
= 1;
8055 else if ((flag_code
== CODE_16BIT
) ^ override
)
8057 bigdisp
.bitfield
.disp32
= 0;
8058 bigdisp
.bitfield
.disp16
= 1;
8063 /* For PC-relative branches, the width of the displacement
8064 is dependent upon data size, not address size. */
8065 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8066 if (flag_code
== CODE_64BIT
)
8068 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8069 bigdisp
.bitfield
.disp16
= 1;
8072 bigdisp
.bitfield
.disp32
= 1;
8073 bigdisp
.bitfield
.disp32s
= 1;
8079 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8081 : LONG_MNEM_SUFFIX
));
8082 bigdisp
.bitfield
.disp32
= 1;
8083 if ((flag_code
== CODE_16BIT
) ^ override
)
8085 bigdisp
.bitfield
.disp32
= 0;
8086 bigdisp
.bitfield
.disp16
= 1;
8090 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8093 exp
= &disp_expressions
[i
.disp_operands
];
8094 i
.op
[this_operand
].disps
= exp
;
8096 save_input_line_pointer
= input_line_pointer
;
8097 input_line_pointer
= disp_start
;
8098 END_STRING_AND_SAVE (disp_end
);
8100 #ifndef GCC_ASM_O_HACK
8101 #define GCC_ASM_O_HACK 0
8104 END_STRING_AND_SAVE (disp_end
+ 1);
8105 if (i
.types
[this_operand
].bitfield
.baseIndex
8106 && displacement_string_end
[-1] == '+')
8108 /* This hack is to avoid a warning when using the "o"
8109 constraint within gcc asm statements.
8112 #define _set_tssldt_desc(n,addr,limit,type) \
8113 __asm__ __volatile__ ( \
8115 "movw %w1,2+%0\n\t" \
8117 "movb %b1,4+%0\n\t" \
8118 "movb %4,5+%0\n\t" \
8119 "movb $0,6+%0\n\t" \
8120 "movb %h1,7+%0\n\t" \
8122 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8124 This works great except that the output assembler ends
8125 up looking a bit weird if it turns out that there is
8126 no offset. You end up producing code that looks like:
8139 So here we provide the missing zero. */
8141 *displacement_string_end
= '0';
8144 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8145 (i
.bnd_prefix
!= NULL
8146 || add_bnd_prefix
));
8147 if (gotfree_input_line
)
8148 input_line_pointer
= gotfree_input_line
;
8150 exp_seg
= expression (exp
);
8153 if (*input_line_pointer
)
8154 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8156 RESTORE_END_STRING (disp_end
+ 1);
8158 input_line_pointer
= save_input_line_pointer
;
8159 if (gotfree_input_line
)
8161 free (gotfree_input_line
);
8163 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8164 exp
->X_op
= O_illegal
;
8167 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8169 RESTORE_END_STRING (disp_end
);
8175 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8176 i386_operand_type types
, const char *disp_start
)
8178 i386_operand_type bigdisp
;
8181 /* We do this to make sure that the section symbol is in
8182 the symbol table. We will ultimately change the relocation
8183 to be relative to the beginning of the section. */
8184 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8185 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8186 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8188 if (exp
->X_op
!= O_symbol
)
8191 if (S_IS_LOCAL (exp
->X_add_symbol
)
8192 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8193 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8194 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8195 exp
->X_op
= O_subtract
;
8196 exp
->X_op_symbol
= GOT_symbol
;
8197 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8198 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8199 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8200 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8202 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8205 else if (exp
->X_op
== O_absent
8206 || exp
->X_op
== O_illegal
8207 || exp
->X_op
== O_big
)
8210 as_bad (_("missing or invalid displacement expression `%s'"),
8215 else if (flag_code
== CODE_64BIT
8216 && !i
.prefix
[ADDR_PREFIX
]
8217 && exp
->X_op
== O_constant
)
8219 /* Since displacement is signed extended to 64bit, don't allow
8220 disp32 and turn off disp32s if they are out of range. */
8221 i
.types
[this_operand
].bitfield
.disp32
= 0;
8222 if (!fits_in_signed_long (exp
->X_add_number
))
8224 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8225 if (i
.types
[this_operand
].bitfield
.baseindex
)
8227 as_bad (_("0x%lx out range of signed 32bit displacement"),
8228 (long) exp
->X_add_number
);
8234 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8235 else if (exp
->X_op
!= O_constant
8236 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8237 && exp_seg
!= absolute_section
8238 && exp_seg
!= text_section
8239 && exp_seg
!= data_section
8240 && exp_seg
!= bss_section
8241 && exp_seg
!= undefined_section
8242 && !bfd_is_com_section (exp_seg
))
8244 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8249 /* Check if this is a displacement only operand. */
8250 bigdisp
= i
.types
[this_operand
];
8251 bigdisp
.bitfield
.disp8
= 0;
8252 bigdisp
.bitfield
.disp16
= 0;
8253 bigdisp
.bitfield
.disp32
= 0;
8254 bigdisp
.bitfield
.disp32s
= 0;
8255 bigdisp
.bitfield
.disp64
= 0;
8256 if (operand_type_all_zero (&bigdisp
))
8257 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8263 /* Make sure the memory operand we've been dealt is valid.
8264 Return 1 on success, 0 on a failure. */
8267 i386_index_check (const char *operand_string
)
8269 const char *kind
= "base/index";
8270 enum flag_code addr_mode
;
8272 if (i
.prefix
[ADDR_PREFIX
])
8273 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8276 addr_mode
= flag_code
;
8278 #if INFER_ADDR_PREFIX
8279 if (i
.mem_operands
== 0)
8281 /* Infer address prefix from the first memory operand. */
8282 const reg_entry
*addr_reg
= i
.base_reg
;
8284 if (addr_reg
== NULL
)
8285 addr_reg
= i
.index_reg
;
8289 if (addr_reg
->reg_num
== RegEip
8290 || addr_reg
->reg_num
== RegEiz
8291 || addr_reg
->reg_type
.bitfield
.reg32
)
8292 addr_mode
= CODE_32BIT
;
8293 else if (flag_code
!= CODE_64BIT
8294 && addr_reg
->reg_type
.bitfield
.reg16
)
8295 addr_mode
= CODE_16BIT
;
8297 if (addr_mode
!= flag_code
)
8299 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8301 /* Change the size of any displacement too. At most one
8302 of Disp16 or Disp32 is set.
8303 FIXME. There doesn't seem to be any real need for
8304 separate Disp16 and Disp32 flags. The same goes for
8305 Imm16 and Imm32. Removing them would probably clean
8306 up the code quite a lot. */
8307 if (flag_code
!= CODE_64BIT
8308 && (i
.types
[this_operand
].bitfield
.disp16
8309 || i
.types
[this_operand
].bitfield
.disp32
))
8310 i
.types
[this_operand
]
8311 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8318 if (current_templates
->start
->opcode_modifier
.isstring
8319 && !current_templates
->start
->opcode_modifier
.immext
8320 && (current_templates
->end
[-1].opcode_modifier
.isstring
8323 /* Memory operands of string insns are special in that they only allow
8324 a single register (rDI, rSI, or rBX) as their memory address. */
8325 const reg_entry
*expected_reg
;
8326 static const char *di_si
[][2] =
8332 static const char *bx
[] = { "ebx", "bx", "rbx" };
8334 kind
= "string address";
8336 if (current_templates
->start
->opcode_modifier
.w
)
8338 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8340 if (!type
.bitfield
.baseindex
8341 || ((!i
.mem_operands
!= !intel_syntax
)
8342 && current_templates
->end
[-1].operand_types
[1]
8343 .bitfield
.baseindex
))
8344 type
= current_templates
->end
[-1].operand_types
[1];
8345 expected_reg
= hash_find (reg_hash
,
8346 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8350 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8352 if (i
.base_reg
!= expected_reg
8354 || operand_type_check (i
.types
[this_operand
], disp
))
8356 /* The second memory operand must have the same size as
8360 && !((addr_mode
== CODE_64BIT
8361 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8362 || (addr_mode
== CODE_32BIT
8363 ? i
.base_reg
->reg_type
.bitfield
.reg32
8364 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8367 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8369 intel_syntax
? '[' : '(',
8371 expected_reg
->reg_name
,
8372 intel_syntax
? ']' : ')');
8379 as_bad (_("`%s' is not a valid %s expression"),
8380 operand_string
, kind
);
8385 if (addr_mode
!= CODE_16BIT
)
8387 /* 32-bit/64-bit checks. */
8389 && (addr_mode
== CODE_64BIT
8390 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8391 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8393 || (i
.base_reg
->reg_num
8394 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8396 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8397 && !i
.index_reg
->reg_type
.bitfield
.regymm
8398 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8399 && ((addr_mode
== CODE_64BIT
8400 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8401 || i
.index_reg
->reg_num
== RegRiz
)
8402 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8403 || i
.index_reg
->reg_num
== RegEiz
))
8404 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8409 /* 16-bit checks. */
8411 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8412 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8414 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8415 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8417 && i
.base_reg
->reg_num
< 6
8418 && i
.index_reg
->reg_num
>= 6
8419 && i
.log2_scale_factor
== 0))))
8426 /* Handle vector immediates. */
8429 RC_SAE_immediate (const char *imm_start
)
8431 unsigned int match_found
, j
;
8432 const char *pstr
= imm_start
;
8440 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8442 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8446 rc_op
.type
= RC_NamesTable
[j
].type
;
8447 rc_op
.operand
= this_operand
;
8448 i
.rounding
= &rc_op
;
8452 as_bad (_("duplicated `%s'"), imm_start
);
8455 pstr
+= RC_NamesTable
[j
].len
;
8465 as_bad (_("Missing '}': '%s'"), imm_start
);
8468 /* RC/SAE immediate string should contain nothing more. */;
8471 as_bad (_("Junk after '}': '%s'"), imm_start
);
8475 exp
= &im_expressions
[i
.imm_operands
++];
8476 i
.op
[this_operand
].imms
= exp
;
8478 exp
->X_op
= O_constant
;
8479 exp
->X_add_number
= 0;
8480 exp
->X_add_symbol
= (symbolS
*) 0;
8481 exp
->X_op_symbol
= (symbolS
*) 0;
8483 i
.types
[this_operand
].bitfield
.imm8
= 1;
8487 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8491 i386_att_operand (char *operand_string
)
8495 char *op_string
= operand_string
;
8497 if (is_space_char (*op_string
))
8500 /* We check for an absolute prefix (differentiating,
8501 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8502 if (*op_string
== ABSOLUTE_PREFIX
)
8505 if (is_space_char (*op_string
))
8507 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8510 /* Check if operand is a register. */
8511 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8513 i386_operand_type temp
;
8515 /* Check for a segment override by searching for ':' after a
8516 segment register. */
8518 if (is_space_char (*op_string
))
8520 if (*op_string
== ':'
8521 && (r
->reg_type
.bitfield
.sreg2
8522 || r
->reg_type
.bitfield
.sreg3
))
8527 i
.seg
[i
.mem_operands
] = &es
;
8530 i
.seg
[i
.mem_operands
] = &cs
;
8533 i
.seg
[i
.mem_operands
] = &ss
;
8536 i
.seg
[i
.mem_operands
] = &ds
;
8539 i
.seg
[i
.mem_operands
] = &fs
;
8542 i
.seg
[i
.mem_operands
] = &gs
;
8546 /* Skip the ':' and whitespace. */
8548 if (is_space_char (*op_string
))
8551 if (!is_digit_char (*op_string
)
8552 && !is_identifier_char (*op_string
)
8553 && *op_string
!= '('
8554 && *op_string
!= ABSOLUTE_PREFIX
)
8556 as_bad (_("bad memory operand `%s'"), op_string
);
8559 /* Handle case of %es:*foo. */
8560 if (*op_string
== ABSOLUTE_PREFIX
)
8563 if (is_space_char (*op_string
))
8565 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8567 goto do_memory_reference
;
8570 /* Handle vector operations. */
8571 if (*op_string
== '{')
8573 op_string
= check_VecOperations (op_string
, NULL
);
8574 if (op_string
== NULL
)
8580 as_bad (_("junk `%s' after register"), op_string
);
8584 temp
.bitfield
.baseindex
= 0;
8585 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8587 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8588 i
.op
[this_operand
].regs
= r
;
8591 else if (*op_string
== REGISTER_PREFIX
)
8593 as_bad (_("bad register name `%s'"), op_string
);
8596 else if (*op_string
== IMMEDIATE_PREFIX
)
8599 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8601 as_bad (_("immediate operand illegal with absolute jump"));
8604 if (!i386_immediate (op_string
))
8607 else if (RC_SAE_immediate (operand_string
))
8609 /* If it is a RC or SAE immediate, do nothing. */
8612 else if (is_digit_char (*op_string
)
8613 || is_identifier_char (*op_string
)
8614 || *op_string
== '(')
8616 /* This is a memory reference of some sort. */
8619 /* Start and end of displacement string expression (if found). */
8620 char *displacement_string_start
;
8621 char *displacement_string_end
;
8624 do_memory_reference
:
8625 if ((i
.mem_operands
== 1
8626 && !current_templates
->start
->opcode_modifier
.isstring
)
8627 || i
.mem_operands
== 2)
8629 as_bad (_("too many memory references for `%s'"),
8630 current_templates
->start
->name
);
8634 /* Check for base index form. We detect the base index form by
8635 looking for an ')' at the end of the operand, searching
8636 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8638 base_string
= op_string
+ strlen (op_string
);
8640 /* Handle vector operations. */
8641 vop_start
= strchr (op_string
, '{');
8642 if (vop_start
&& vop_start
< base_string
)
8644 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8646 base_string
= vop_start
;
8650 if (is_space_char (*base_string
))
8653 /* If we only have a displacement, set-up for it to be parsed later. */
8654 displacement_string_start
= op_string
;
8655 displacement_string_end
= base_string
+ 1;
8657 if (*base_string
== ')')
8660 unsigned int parens_balanced
= 1;
8661 /* We've already checked that the number of left & right ()'s are
8662 equal, so this loop will not be infinite. */
8666 if (*base_string
== ')')
8668 if (*base_string
== '(')
8671 while (parens_balanced
);
8673 temp_string
= base_string
;
8675 /* Skip past '(' and whitespace. */
8677 if (is_space_char (*base_string
))
8680 if (*base_string
== ','
8681 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8684 displacement_string_end
= temp_string
;
8686 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8690 base_string
= end_op
;
8691 if (is_space_char (*base_string
))
8695 /* There may be an index reg or scale factor here. */
8696 if (*base_string
== ',')
8699 if (is_space_char (*base_string
))
8702 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8705 base_string
= end_op
;
8706 if (is_space_char (*base_string
))
8708 if (*base_string
== ',')
8711 if (is_space_char (*base_string
))
8714 else if (*base_string
!= ')')
8716 as_bad (_("expecting `,' or `)' "
8717 "after index register in `%s'"),
8722 else if (*base_string
== REGISTER_PREFIX
)
8724 end_op
= strchr (base_string
, ',');
8727 as_bad (_("bad register name `%s'"), base_string
);
8731 /* Check for scale factor. */
8732 if (*base_string
!= ')')
8734 char *end_scale
= i386_scale (base_string
);
8739 base_string
= end_scale
;
8740 if (is_space_char (*base_string
))
8742 if (*base_string
!= ')')
8744 as_bad (_("expecting `)' "
8745 "after scale factor in `%s'"),
8750 else if (!i
.index_reg
)
8752 as_bad (_("expecting index register or scale factor "
8753 "after `,'; got '%c'"),
8758 else if (*base_string
!= ')')
8760 as_bad (_("expecting `,' or `)' "
8761 "after base register in `%s'"),
8766 else if (*base_string
== REGISTER_PREFIX
)
8768 end_op
= strchr (base_string
, ',');
8771 as_bad (_("bad register name `%s'"), base_string
);
8776 /* If there's an expression beginning the operand, parse it,
8777 assuming displacement_string_start and
8778 displacement_string_end are meaningful. */
8779 if (displacement_string_start
!= displacement_string_end
)
8781 if (!i386_displacement (displacement_string_start
,
8782 displacement_string_end
))
8786 /* Special case for (%dx) while doing input/output op. */
8788 && operand_type_equal (&i
.base_reg
->reg_type
,
8789 ®16_inoutportreg
)
8791 && i
.log2_scale_factor
== 0
8792 && i
.seg
[i
.mem_operands
] == 0
8793 && !operand_type_check (i
.types
[this_operand
], disp
))
8795 i
.types
[this_operand
] = inoutportreg
;
8799 if (i386_index_check (operand_string
) == 0)
8801 i
.types
[this_operand
].bitfield
.mem
= 1;
8806 /* It's not a memory operand; argh! */
8807 as_bad (_("invalid char %s beginning operand %d `%s'"),
8808 output_invalid (*op_string
),
8813 return 1; /* Normal return. */
8816 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8817 that an rs_machine_dependent frag may reach. */
8820 i386_frag_max_var (fragS
*frag
)
8822 /* The only relaxable frags are for jumps.
8823 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8824 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8825 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8828 /* md_estimate_size_before_relax()
8830 Called just before relax() for rs_machine_dependent frags. The x86
8831 assembler uses these frags to handle variable size jump
8834 Any symbol that is now undefined will not become defined.
8835 Return the correct fr_subtype in the frag.
8836 Return the initial "guess for variable size of frag" to caller.
8837 The guess is actually the growth beyond the fixed part. Whatever
8838 we do to grow the fixed or variable part contributes to our
8842 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8844 /* We've already got fragP->fr_subtype right; all we have to do is
8845 check for un-relaxable symbols. On an ELF system, we can't relax
8846 an externally visible symbol, because it may be overridden by a
8848 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8851 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8852 || S_IS_WEAK (fragP
->fr_symbol
)
8853 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8854 & BSF_GNU_INDIRECT_FUNCTION
))))
8856 #if defined (OBJ_COFF) && defined (TE_PE)
8857 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8858 && S_IS_WEAK (fragP
->fr_symbol
))
8862 /* Symbol is undefined in this segment, or we need to keep a
8863 reloc so that weak symbols can be overridden. */
8864 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8865 enum bfd_reloc_code_real reloc_type
;
8866 unsigned char *opcode
;
8869 if (fragP
->fr_var
!= NO_RELOC
)
8870 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8872 reloc_type
= BFD_RELOC_16_PCREL
;
8874 reloc_type
= BFD_RELOC_32_PCREL
;
8876 old_fr_fix
= fragP
->fr_fix
;
8877 opcode
= (unsigned char *) fragP
->fr_opcode
;
8879 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8882 /* Make jmp (0xeb) a (d)word displacement jump. */
8884 fragP
->fr_fix
+= size
;
8885 fix_new (fragP
, old_fr_fix
, size
,
8887 fragP
->fr_offset
, 1,
8893 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8895 /* Negate the condition, and branch past an
8896 unconditional jump. */
8899 /* Insert an unconditional jump. */
8901 /* We added two extra opcode bytes, and have a two byte
8903 fragP
->fr_fix
+= 2 + 2;
8904 fix_new (fragP
, old_fr_fix
+ 2, 2,
8906 fragP
->fr_offset
, 1,
8913 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8918 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8920 fragP
->fr_offset
, 1,
8922 fixP
->fx_signed
= 1;
8926 /* This changes the byte-displacement jump 0x7N
8927 to the (d)word-displacement jump 0x0f,0x8N. */
8928 opcode
[1] = opcode
[0] + 0x10;
8929 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8930 /* We've added an opcode byte. */
8931 fragP
->fr_fix
+= 1 + size
;
8932 fix_new (fragP
, old_fr_fix
+ 1, size
,
8934 fragP
->fr_offset
, 1,
8939 BAD_CASE (fragP
->fr_subtype
);
8943 return fragP
->fr_fix
- old_fr_fix
;
8946 /* Guess size depending on current relax state. Initially the relax
8947 state will correspond to a short jump and we return 1, because
8948 the variable part of the frag (the branch offset) is one byte
8949 long. However, we can relax a section more than once and in that
8950 case we must either set fr_subtype back to the unrelaxed state,
8951 or return the value for the appropriate branch. */
8952 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8955 /* Called after relax() is finished.
8957 In: Address of frag.
8958 fr_type == rs_machine_dependent.
8959 fr_subtype is what the address relaxed to.
8961 Out: Any fixSs and constants are set up.
8962 Caller will turn frag into a ".space 0". */
8965 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8968 unsigned char *opcode
;
8969 unsigned char *where_to_put_displacement
= NULL
;
8970 offsetT target_address
;
8971 offsetT opcode_address
;
8972 unsigned int extension
= 0;
8973 offsetT displacement_from_opcode_start
;
8975 opcode
= (unsigned char *) fragP
->fr_opcode
;
8977 /* Address we want to reach in file space. */
8978 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8980 /* Address opcode resides at in file space. */
8981 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8983 /* Displacement from opcode start to fill into instruction. */
8984 displacement_from_opcode_start
= target_address
- opcode_address
;
8986 if ((fragP
->fr_subtype
& BIG
) == 0)
8988 /* Don't have to change opcode. */
8989 extension
= 1; /* 1 opcode + 1 displacement */
8990 where_to_put_displacement
= &opcode
[1];
8994 if (no_cond_jump_promotion
8995 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8996 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8997 _("long jump required"));
8999 switch (fragP
->fr_subtype
)
9001 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9002 extension
= 4; /* 1 opcode + 4 displacement */
9004 where_to_put_displacement
= &opcode
[1];
9007 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9008 extension
= 2; /* 1 opcode + 2 displacement */
9010 where_to_put_displacement
= &opcode
[1];
9013 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9014 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9015 extension
= 5; /* 2 opcode + 4 displacement */
9016 opcode
[1] = opcode
[0] + 0x10;
9017 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9018 where_to_put_displacement
= &opcode
[2];
9021 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9022 extension
= 3; /* 2 opcode + 2 displacement */
9023 opcode
[1] = opcode
[0] + 0x10;
9024 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9025 where_to_put_displacement
= &opcode
[2];
9028 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9033 where_to_put_displacement
= &opcode
[3];
9037 BAD_CASE (fragP
->fr_subtype
);
9042 /* If size if less then four we are sure that the operand fits,
9043 but if it's 4, then it could be that the displacement is larger
9045 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9047 && ((addressT
) (displacement_from_opcode_start
- extension
9048 + ((addressT
) 1 << 31))
9049 > (((addressT
) 2 << 31) - 1)))
9051 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9052 _("jump target out of range"));
9053 /* Make us emit 0. */
9054 displacement_from_opcode_start
= extension
;
9056 /* Now put displacement after opcode. */
9057 md_number_to_chars ((char *) where_to_put_displacement
,
9058 (valueT
) (displacement_from_opcode_start
- extension
),
9059 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9060 fragP
->fr_fix
+= extension
;
9063 /* Apply a fixup (fixP) to segment data, once it has been determined
9064 by our caller that we have all the info we need to fix it up.
9066 Parameter valP is the pointer to the value of the bits.
9068 On the 386, immediates, displacements, and data pointers are all in
9069 the same (little-endian) format, so we don't need to care about which
9073 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9075 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9076 valueT value
= *valP
;
9078 #if !defined (TE_Mach)
9081 switch (fixP
->fx_r_type
)
9087 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9090 case BFD_RELOC_X86_64_32S
:
9091 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9094 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9097 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9102 if (fixP
->fx_addsy
!= NULL
9103 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9104 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9105 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9106 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9107 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9108 && !use_rela_relocations
)
9110 /* This is a hack. There should be a better way to handle this.
9111 This covers for the fact that bfd_install_relocation will
9112 subtract the current location (for partial_inplace, PC relative
9113 relocations); see more below. */
9117 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9120 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9122 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9125 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9128 || (symbol_section_p (fixP
->fx_addsy
)
9129 && sym_seg
!= absolute_section
))
9130 && !generic_force_reloc (fixP
))
9132 /* Yes, we add the values in twice. This is because
9133 bfd_install_relocation subtracts them out again. I think
9134 bfd_install_relocation is broken, but I don't dare change
9136 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9140 #if defined (OBJ_COFF) && defined (TE_PE)
9141 /* For some reason, the PE format does not store a
9142 section address offset for a PC relative symbol. */
9143 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9144 || S_IS_WEAK (fixP
->fx_addsy
))
9145 value
+= md_pcrel_from (fixP
);
9148 #if defined (OBJ_COFF) && defined (TE_PE)
9149 if (fixP
->fx_addsy
!= NULL
9150 && S_IS_WEAK (fixP
->fx_addsy
)
9151 /* PR 16858: Do not modify weak function references. */
9152 && ! fixP
->fx_pcrel
)
9154 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9158 /* Fix a few things - the dynamic linker expects certain values here,
9159 and we must not disappoint it. */
9160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9161 if (IS_ELF
&& fixP
->fx_addsy
)
9162 switch (fixP
->fx_r_type
)
9164 case BFD_RELOC_386_PLT32
:
9165 case BFD_RELOC_X86_64_PLT32
:
9166 case BFD_RELOC_X86_64_PLT32_BND
:
9167 /* Make the jump instruction point to the address of the operand. At
9168 runtime we merely add the offset to the actual PLT entry. */
9172 case BFD_RELOC_386_TLS_GD
:
9173 case BFD_RELOC_386_TLS_LDM
:
9174 case BFD_RELOC_386_TLS_IE_32
:
9175 case BFD_RELOC_386_TLS_IE
:
9176 case BFD_RELOC_386_TLS_GOTIE
:
9177 case BFD_RELOC_386_TLS_GOTDESC
:
9178 case BFD_RELOC_X86_64_TLSGD
:
9179 case BFD_RELOC_X86_64_TLSLD
:
9180 case BFD_RELOC_X86_64_GOTTPOFF
:
9181 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9182 value
= 0; /* Fully resolved at runtime. No addend. */
9184 case BFD_RELOC_386_TLS_LE
:
9185 case BFD_RELOC_386_TLS_LDO_32
:
9186 case BFD_RELOC_386_TLS_LE_32
:
9187 case BFD_RELOC_X86_64_DTPOFF32
:
9188 case BFD_RELOC_X86_64_DTPOFF64
:
9189 case BFD_RELOC_X86_64_TPOFF32
:
9190 case BFD_RELOC_X86_64_TPOFF64
:
9191 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9194 case BFD_RELOC_386_TLS_DESC_CALL
:
9195 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9196 value
= 0; /* Fully resolved at runtime. No addend. */
9197 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9201 case BFD_RELOC_386_GOT32
:
9202 case BFD_RELOC_X86_64_GOT32
:
9203 value
= 0; /* Fully resolved at runtime. No addend. */
9206 case BFD_RELOC_VTABLE_INHERIT
:
9207 case BFD_RELOC_VTABLE_ENTRY
:
9214 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9216 #endif /* !defined (TE_Mach) */
9218 /* Are we finished with this relocation now? */
9219 if (fixP
->fx_addsy
== NULL
)
9221 #if defined (OBJ_COFF) && defined (TE_PE)
9222 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9225 /* Remember value for tc_gen_reloc. */
9226 fixP
->fx_addnumber
= value
;
9227 /* Clear out the frag for now. */
9231 else if (use_rela_relocations
)
9233 fixP
->fx_no_overflow
= 1;
9234 /* Remember value for tc_gen_reloc. */
9235 fixP
->fx_addnumber
= value
;
9239 md_number_to_chars (p
, value
, fixP
->fx_size
);
9243 md_atof (int type
, char *litP
, int *sizeP
)
9245 /* This outputs the LITTLENUMs in REVERSE order;
9246 in accord with the bigendian 386. */
9247 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9250 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9253 output_invalid (int c
)
9256 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9259 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9260 "(0x%x)", (unsigned char) c
);
9261 return output_invalid_buf
;
9264 /* REG_STRING starts *before* REGISTER_PREFIX. */
9266 static const reg_entry
*
9267 parse_real_register (char *reg_string
, char **end_op
)
9269 char *s
= reg_string
;
9271 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9274 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9275 if (*s
== REGISTER_PREFIX
)
9278 if (is_space_char (*s
))
9282 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9284 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9285 return (const reg_entry
*) NULL
;
9289 /* For naked regs, make sure that we are not dealing with an identifier.
9290 This prevents confusing an identifier like `eax_var' with register
9292 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9293 return (const reg_entry
*) NULL
;
9297 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9299 /* Handle floating point regs, allowing spaces in the (i) part. */
9300 if (r
== i386_regtab
/* %st is first entry of table */)
9302 if (is_space_char (*s
))
9307 if (is_space_char (*s
))
9309 if (*s
>= '0' && *s
<= '7')
9313 if (is_space_char (*s
))
9318 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9323 /* We have "%st(" then garbage. */
9324 return (const reg_entry
*) NULL
;
9328 if (r
== NULL
|| allow_pseudo_reg
)
9331 if (operand_type_all_zero (&r
->reg_type
))
9332 return (const reg_entry
*) NULL
;
9334 if ((r
->reg_type
.bitfield
.reg32
9335 || r
->reg_type
.bitfield
.sreg3
9336 || r
->reg_type
.bitfield
.control
9337 || r
->reg_type
.bitfield
.debug
9338 || r
->reg_type
.bitfield
.test
)
9339 && !cpu_arch_flags
.bitfield
.cpui386
)
9340 return (const reg_entry
*) NULL
;
9342 if (r
->reg_type
.bitfield
.floatreg
9343 && !cpu_arch_flags
.bitfield
.cpu8087
9344 && !cpu_arch_flags
.bitfield
.cpu287
9345 && !cpu_arch_flags
.bitfield
.cpu387
)
9346 return (const reg_entry
*) NULL
;
9348 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9349 return (const reg_entry
*) NULL
;
9351 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9352 return (const reg_entry
*) NULL
;
9354 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9355 return (const reg_entry
*) NULL
;
9357 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9358 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9359 return (const reg_entry
*) NULL
;
9361 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9362 if (!allow_index_reg
9363 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9364 return (const reg_entry
*) NULL
;
9366 /* Upper 16 vector register is only available with VREX in 64bit
9368 if ((r
->reg_flags
& RegVRex
))
9370 if (!cpu_arch_flags
.bitfield
.cpuvrex
9371 || flag_code
!= CODE_64BIT
)
9372 return (const reg_entry
*) NULL
;
9377 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9378 || r
->reg_type
.bitfield
.reg64
)
9379 && (!cpu_arch_flags
.bitfield
.cpulm
9380 || !operand_type_equal (&r
->reg_type
, &control
))
9381 && flag_code
!= CODE_64BIT
)
9382 return (const reg_entry
*) NULL
;
9384 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9385 return (const reg_entry
*) NULL
;
9390 /* REG_STRING starts *before* REGISTER_PREFIX. */
9392 static const reg_entry
*
9393 parse_register (char *reg_string
, char **end_op
)
9397 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9398 r
= parse_real_register (reg_string
, end_op
);
9403 char *save
= input_line_pointer
;
9407 input_line_pointer
= reg_string
;
9408 c
= get_symbol_end ();
9409 symbolP
= symbol_find (reg_string
);
9410 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9412 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9414 know (e
->X_op
== O_register
);
9415 know (e
->X_add_number
>= 0
9416 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9417 r
= i386_regtab
+ e
->X_add_number
;
9418 *end_op
= input_line_pointer
;
9420 *input_line_pointer
= c
;
9421 input_line_pointer
= save
;
9427 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9430 char *end
= input_line_pointer
;
9433 r
= parse_register (name
, &input_line_pointer
);
9434 if (r
&& end
<= input_line_pointer
)
9436 *nextcharP
= *input_line_pointer
;
9437 *input_line_pointer
= 0;
9438 e
->X_op
= O_register
;
9439 e
->X_add_number
= r
- i386_regtab
;
9442 input_line_pointer
= end
;
9444 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9448 md_operand (expressionS
*e
)
9453 switch (*input_line_pointer
)
9455 case REGISTER_PREFIX
:
9456 r
= parse_real_register (input_line_pointer
, &end
);
9459 e
->X_op
= O_register
;
9460 e
->X_add_number
= r
- i386_regtab
;
9461 input_line_pointer
= end
;
9466 gas_assert (intel_syntax
);
9467 end
= input_line_pointer
++;
9469 if (*input_line_pointer
== ']')
9471 ++input_line_pointer
;
9472 e
->X_op_symbol
= make_expr_symbol (e
);
9473 e
->X_add_symbol
= NULL
;
9474 e
->X_add_number
= 0;
9480 input_line_pointer
= end
;
9487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9488 const char *md_shortopts
= "kVQ:sqn";
9490 const char *md_shortopts
= "qn";
9493 #define OPTION_32 (OPTION_MD_BASE + 0)
9494 #define OPTION_64 (OPTION_MD_BASE + 1)
9495 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9496 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9497 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9498 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9499 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9500 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9501 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9502 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9503 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9504 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9505 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9506 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9507 #define OPTION_X32 (OPTION_MD_BASE + 14)
9508 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9509 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9510 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9511 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9513 struct option md_longopts
[] =
9515 {"32", no_argument
, NULL
, OPTION_32
},
9516 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9517 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9518 {"64", no_argument
, NULL
, OPTION_64
},
9520 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9521 {"x32", no_argument
, NULL
, OPTION_X32
},
9523 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9524 {"march", required_argument
, NULL
, OPTION_MARCH
},
9525 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9526 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9527 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9528 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9529 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9530 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9531 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9532 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9533 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9534 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9535 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9536 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9537 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9538 # if defined (TE_PE) || defined (TE_PEP)
9539 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9541 {NULL
, no_argument
, NULL
, 0}
9543 size_t md_longopts_size
= sizeof (md_longopts
);
9546 md_parse_option (int c
, char *arg
)
9554 optimize_align_code
= 0;
9561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9562 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9563 should be emitted or not. FIXME: Not implemented. */
9567 /* -V: SVR4 argument to print version ID. */
9569 print_version_id ();
9572 /* -k: Ignore for FreeBSD compatibility. */
9577 /* -s: On i386 Solaris, this tells the native assembler to use
9578 .stab instead of .stab.excl. We always use .stab anyhow. */
9581 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9585 const char **list
, **l
;
9587 list
= bfd_target_list ();
9588 for (l
= list
; *l
!= NULL
; l
++)
9589 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9590 || strcmp (*l
, "coff-x86-64") == 0
9591 || strcmp (*l
, "pe-x86-64") == 0
9592 || strcmp (*l
, "pei-x86-64") == 0
9593 || strcmp (*l
, "mach-o-x86-64") == 0)
9595 default_arch
= "x86_64";
9599 as_fatal (_("no compiled in support for x86_64"));
9605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9609 const char **list
, **l
;
9611 list
= bfd_target_list ();
9612 for (l
= list
; *l
!= NULL
; l
++)
9613 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9615 default_arch
= "x86_64:32";
9619 as_fatal (_("no compiled in support for 32bit x86_64"));
9623 as_fatal (_("32bit x86_64 is only supported for ELF"));
9628 default_arch
= "i386";
9632 #ifdef SVR4_COMMENT_CHARS
9637 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9639 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9643 i386_comment_chars
= n
;
9649 arch
= xstrdup (arg
);
9653 as_fatal (_("invalid -march= option: `%s'"), arg
);
9654 next
= strchr (arch
, '+');
9657 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9659 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9662 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9665 cpu_arch_name
= cpu_arch
[j
].name
;
9666 cpu_sub_arch_name
= NULL
;
9667 cpu_arch_flags
= cpu_arch
[j
].flags
;
9668 cpu_arch_isa
= cpu_arch
[j
].type
;
9669 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9670 if (!cpu_arch_tune_set
)
9672 cpu_arch_tune
= cpu_arch_isa
;
9673 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9677 else if (*cpu_arch
[j
].name
== '.'
9678 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9680 /* ISA entension. */
9681 i386_cpu_flags flags
;
9683 if (!cpu_arch
[j
].negated
)
9684 flags
= cpu_flags_or (cpu_arch_flags
,
9687 flags
= cpu_flags_and_not (cpu_arch_flags
,
9689 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9691 if (cpu_sub_arch_name
)
9693 char *name
= cpu_sub_arch_name
;
9694 cpu_sub_arch_name
= concat (name
,
9696 (const char *) NULL
);
9700 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9701 cpu_arch_flags
= flags
;
9702 cpu_arch_isa_flags
= flags
;
9708 if (j
>= ARRAY_SIZE (cpu_arch
))
9709 as_fatal (_("invalid -march= option: `%s'"), arg
);
9713 while (next
!= NULL
);
9718 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9719 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9721 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9723 cpu_arch_tune_set
= 1;
9724 cpu_arch_tune
= cpu_arch
[j
].type
;
9725 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9729 if (j
>= ARRAY_SIZE (cpu_arch
))
9730 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9733 case OPTION_MMNEMONIC
:
9734 if (strcasecmp (arg
, "att") == 0)
9736 else if (strcasecmp (arg
, "intel") == 0)
9739 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9742 case OPTION_MSYNTAX
:
9743 if (strcasecmp (arg
, "att") == 0)
9745 else if (strcasecmp (arg
, "intel") == 0)
9748 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9751 case OPTION_MINDEX_REG
:
9752 allow_index_reg
= 1;
9755 case OPTION_MNAKED_REG
:
9756 allow_naked_reg
= 1;
9759 case OPTION_MOLD_GCC
:
9763 case OPTION_MSSE2AVX
:
9767 case OPTION_MSSE_CHECK
:
9768 if (strcasecmp (arg
, "error") == 0)
9769 sse_check
= check_error
;
9770 else if (strcasecmp (arg
, "warning") == 0)
9771 sse_check
= check_warning
;
9772 else if (strcasecmp (arg
, "none") == 0)
9773 sse_check
= check_none
;
9775 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9778 case OPTION_MOPERAND_CHECK
:
9779 if (strcasecmp (arg
, "error") == 0)
9780 operand_check
= check_error
;
9781 else if (strcasecmp (arg
, "warning") == 0)
9782 operand_check
= check_warning
;
9783 else if (strcasecmp (arg
, "none") == 0)
9784 operand_check
= check_none
;
9786 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9789 case OPTION_MAVXSCALAR
:
9790 if (strcasecmp (arg
, "128") == 0)
9792 else if (strcasecmp (arg
, "256") == 0)
9795 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9798 case OPTION_MADD_BND_PREFIX
:
9802 case OPTION_MEVEXLIG
:
9803 if (strcmp (arg
, "128") == 0)
9805 else if (strcmp (arg
, "256") == 0)
9807 else if (strcmp (arg
, "512") == 0)
9810 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9813 case OPTION_MEVEXWIG
:
9814 if (strcmp (arg
, "0") == 0)
9816 else if (strcmp (arg
, "1") == 0)
9819 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9822 # if defined (TE_PE) || defined (TE_PEP)
9823 case OPTION_MBIG_OBJ
:
9834 #define MESSAGE_TEMPLATE \
9838 show_arch (FILE *stream
, int ext
, int check
)
9840 static char message
[] = MESSAGE_TEMPLATE
;
9841 char *start
= message
+ 27;
9843 int size
= sizeof (MESSAGE_TEMPLATE
);
9850 left
= size
- (start
- message
);
9851 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9853 /* Should it be skipped? */
9854 if (cpu_arch
[j
].skip
)
9857 name
= cpu_arch
[j
].name
;
9858 len
= cpu_arch
[j
].len
;
9861 /* It is an extension. Skip if we aren't asked to show it. */
9872 /* It is an processor. Skip if we show only extension. */
9875 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9877 /* It is an impossible processor - skip. */
9881 /* Reserve 2 spaces for ", " or ",\0" */
9884 /* Check if there is any room. */
9892 p
= mempcpy (p
, name
, len
);
9896 /* Output the current message now and start a new one. */
9899 fprintf (stream
, "%s\n", message
);
9901 left
= size
- (start
- message
) - len
- 2;
9903 gas_assert (left
>= 0);
9905 p
= mempcpy (p
, name
, len
);
9910 fprintf (stream
, "%s\n", message
);
9914 md_show_usage (FILE *stream
)
9916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9917 fprintf (stream
, _("\
9919 -V print assembler version number\n\
9922 fprintf (stream
, _("\
9923 -n Do not optimize code alignment\n\
9924 -q quieten some warnings\n"));
9925 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9926 fprintf (stream
, _("\
9929 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9930 || defined (TE_PE) || defined (TE_PEP))
9931 fprintf (stream
, _("\
9932 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9934 #ifdef SVR4_COMMENT_CHARS
9935 fprintf (stream
, _("\
9936 --divide do not treat `/' as a comment character\n"));
9938 fprintf (stream
, _("\
9939 --divide ignored\n"));
9941 fprintf (stream
, _("\
9942 -march=CPU[,+EXTENSION...]\n\
9943 generate code for CPU and EXTENSION, CPU is one of:\n"));
9944 show_arch (stream
, 0, 1);
9945 fprintf (stream
, _("\
9946 EXTENSION is combination of:\n"));
9947 show_arch (stream
, 1, 0);
9948 fprintf (stream
, _("\
9949 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9950 show_arch (stream
, 0, 0);
9951 fprintf (stream
, _("\
9952 -msse2avx encode SSE instructions with VEX prefix\n"));
9953 fprintf (stream
, _("\
9954 -msse-check=[none|error|warning]\n\
9955 check SSE instructions\n"));
9956 fprintf (stream
, _("\
9957 -moperand-check=[none|error|warning]\n\
9958 check operand combinations for validity\n"));
9959 fprintf (stream
, _("\
9960 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9962 fprintf (stream
, _("\
9963 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9965 fprintf (stream
, _("\
9966 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9967 for EVEX.W bit ignored instructions\n"));
9968 fprintf (stream
, _("\
9969 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9970 fprintf (stream
, _("\
9971 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9972 fprintf (stream
, _("\
9973 -mindex-reg support pseudo index registers\n"));
9974 fprintf (stream
, _("\
9975 -mnaked-reg don't require `%%' prefix for registers\n"));
9976 fprintf (stream
, _("\
9977 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9978 fprintf (stream
, _("\
9979 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9980 # if defined (TE_PE) || defined (TE_PEP)
9981 fprintf (stream
, _("\
9982 -mbig-obj generate big object files\n"));
9986 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9987 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9988 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9990 /* Pick the target format to use. */
9993 i386_target_format (void)
9995 if (!strncmp (default_arch
, "x86_64", 6))
9997 update_code_flag (CODE_64BIT
, 1);
9998 if (default_arch
[6] == '\0')
9999 x86_elf_abi
= X86_64_ABI
;
10001 x86_elf_abi
= X86_64_X32_ABI
;
10003 else if (!strcmp (default_arch
, "i386"))
10004 update_code_flag (CODE_32BIT
, 1);
10006 as_fatal (_("unknown architecture"));
10008 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10009 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10010 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10011 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10013 switch (OUTPUT_FLAVOR
)
10015 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10016 case bfd_target_aout_flavour
:
10017 return AOUT_TARGET_FORMAT
;
10019 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10020 # if defined (TE_PE) || defined (TE_PEP)
10021 case bfd_target_coff_flavour
:
10022 if (flag_code
== CODE_64BIT
)
10023 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10026 # elif defined (TE_GO32)
10027 case bfd_target_coff_flavour
:
10028 return "coff-go32";
10030 case bfd_target_coff_flavour
:
10031 return "coff-i386";
10034 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10035 case bfd_target_elf_flavour
:
10037 const char *format
;
10039 switch (x86_elf_abi
)
10042 format
= ELF_TARGET_FORMAT
;
10045 use_rela_relocations
= 1;
10047 format
= ELF_TARGET_FORMAT64
;
10049 case X86_64_X32_ABI
:
10050 use_rela_relocations
= 1;
10052 disallow_64bit_reloc
= 1;
10053 format
= ELF_TARGET_FORMAT32
;
10056 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10058 if (x86_elf_abi
!= X86_64_ABI
)
10059 as_fatal (_("Intel L1OM is 64bit only"));
10060 return ELF_TARGET_L1OM_FORMAT
;
10062 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10064 if (x86_elf_abi
!= X86_64_ABI
)
10065 as_fatal (_("Intel K1OM is 64bit only"));
10066 return ELF_TARGET_K1OM_FORMAT
;
10072 #if defined (OBJ_MACH_O)
10073 case bfd_target_mach_o_flavour
:
10074 if (flag_code
== CODE_64BIT
)
10076 use_rela_relocations
= 1;
10078 return "mach-o-x86-64";
10081 return "mach-o-i386";
10089 #endif /* OBJ_MAYBE_ more than one */
10091 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10093 i386_elf_emit_arch_note (void)
10095 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10098 asection
*seg
= now_seg
;
10099 subsegT subseg
= now_subseg
;
10100 Elf_Internal_Note i_note
;
10101 Elf_External_Note e_note
;
10102 asection
*note_secp
;
10105 /* Create the .note section. */
10106 note_secp
= subseg_new (".note", 0);
10107 bfd_set_section_flags (stdoutput
,
10109 SEC_HAS_CONTENTS
| SEC_READONLY
);
10111 /* Process the arch string. */
10112 len
= strlen (cpu_arch_name
);
10114 i_note
.namesz
= len
+ 1;
10116 i_note
.type
= NT_ARCH
;
10117 p
= frag_more (sizeof (e_note
.namesz
));
10118 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10119 p
= frag_more (sizeof (e_note
.descsz
));
10120 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10121 p
= frag_more (sizeof (e_note
.type
));
10122 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10123 p
= frag_more (len
+ 1);
10124 strcpy (p
, cpu_arch_name
);
10126 frag_align (2, 0, 0);
10128 subseg_set (seg
, subseg
);
10134 md_undefined_symbol (char *name
)
10136 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10137 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10138 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10139 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10143 if (symbol_find (name
))
10144 as_bad (_("GOT already in symbol table"));
10145 GOT_symbol
= symbol_new (name
, undefined_section
,
10146 (valueT
) 0, &zero_address_frag
);
10153 /* Round up a section size to the appropriate boundary. */
10156 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10158 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10159 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10161 /* For a.out, force the section size to be aligned. If we don't do
10162 this, BFD will align it for us, but it will not write out the
10163 final bytes of the section. This may be a bug in BFD, but it is
10164 easier to fix it here since that is how the other a.out targets
10168 align
= bfd_get_section_alignment (stdoutput
, segment
);
10169 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10176 /* On the i386, PC-relative offsets are relative to the start of the
10177 next instruction. That is, the address of the offset, plus its
10178 size, since the offset is always the last part of the insn. */
10181 md_pcrel_from (fixS
*fixP
)
10183 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10189 s_bss (int ignore ATTRIBUTE_UNUSED
)
10193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10195 obj_elf_section_change_hook ();
10197 temp
= get_absolute_expression ();
10198 subseg_set (bss_section
, (subsegT
) temp
);
10199 demand_empty_rest_of_line ();
10205 i386_validate_fix (fixS
*fixp
)
10207 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10209 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10213 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10218 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10220 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10222 fixp
->fx_subsy
= 0;
10227 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10230 bfd_reloc_code_real_type code
;
10232 switch (fixp
->fx_r_type
)
10234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10235 case BFD_RELOC_SIZE32
:
10236 case BFD_RELOC_SIZE64
:
10237 if (S_IS_DEFINED (fixp
->fx_addsy
)
10238 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10240 /* Resolve size relocation against local symbol to size of
10241 the symbol plus addend. */
10242 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10243 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10244 && !fits_in_unsigned_long (value
))
10245 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10246 _("symbol size computation overflow"));
10247 fixp
->fx_addsy
= NULL
;
10248 fixp
->fx_subsy
= NULL
;
10249 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10254 case BFD_RELOC_X86_64_PLT32
:
10255 case BFD_RELOC_X86_64_PLT32_BND
:
10256 case BFD_RELOC_X86_64_GOT32
:
10257 case BFD_RELOC_X86_64_GOTPCREL
:
10258 case BFD_RELOC_386_PLT32
:
10259 case BFD_RELOC_386_GOT32
:
10260 case BFD_RELOC_386_GOTOFF
:
10261 case BFD_RELOC_386_GOTPC
:
10262 case BFD_RELOC_386_TLS_GD
:
10263 case BFD_RELOC_386_TLS_LDM
:
10264 case BFD_RELOC_386_TLS_LDO_32
:
10265 case BFD_RELOC_386_TLS_IE_32
:
10266 case BFD_RELOC_386_TLS_IE
:
10267 case BFD_RELOC_386_TLS_GOTIE
:
10268 case BFD_RELOC_386_TLS_LE_32
:
10269 case BFD_RELOC_386_TLS_LE
:
10270 case BFD_RELOC_386_TLS_GOTDESC
:
10271 case BFD_RELOC_386_TLS_DESC_CALL
:
10272 case BFD_RELOC_X86_64_TLSGD
:
10273 case BFD_RELOC_X86_64_TLSLD
:
10274 case BFD_RELOC_X86_64_DTPOFF32
:
10275 case BFD_RELOC_X86_64_DTPOFF64
:
10276 case BFD_RELOC_X86_64_GOTTPOFF
:
10277 case BFD_RELOC_X86_64_TPOFF32
:
10278 case BFD_RELOC_X86_64_TPOFF64
:
10279 case BFD_RELOC_X86_64_GOTOFF64
:
10280 case BFD_RELOC_X86_64_GOTPC32
:
10281 case BFD_RELOC_X86_64_GOT64
:
10282 case BFD_RELOC_X86_64_GOTPCREL64
:
10283 case BFD_RELOC_X86_64_GOTPC64
:
10284 case BFD_RELOC_X86_64_GOTPLT64
:
10285 case BFD_RELOC_X86_64_PLTOFF64
:
10286 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10287 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10288 case BFD_RELOC_RVA
:
10289 case BFD_RELOC_VTABLE_ENTRY
:
10290 case BFD_RELOC_VTABLE_INHERIT
:
10292 case BFD_RELOC_32_SECREL
:
10294 code
= fixp
->fx_r_type
;
10296 case BFD_RELOC_X86_64_32S
:
10297 if (!fixp
->fx_pcrel
)
10299 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10300 code
= fixp
->fx_r_type
;
10304 if (fixp
->fx_pcrel
)
10306 switch (fixp
->fx_size
)
10309 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10310 _("can not do %d byte pc-relative relocation"),
10312 code
= BFD_RELOC_32_PCREL
;
10314 case 1: code
= BFD_RELOC_8_PCREL
; break;
10315 case 2: code
= BFD_RELOC_16_PCREL
; break;
10317 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10318 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10321 case 8: code
= BFD_RELOC_64_PCREL
; break;
10327 switch (fixp
->fx_size
)
10330 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10331 _("can not do %d byte relocation"),
10333 code
= BFD_RELOC_32
;
10335 case 1: code
= BFD_RELOC_8
; break;
10336 case 2: code
= BFD_RELOC_16
; break;
10337 case 4: code
= BFD_RELOC_32
; break;
10339 case 8: code
= BFD_RELOC_64
; break;
10346 if ((code
== BFD_RELOC_32
10347 || code
== BFD_RELOC_32_PCREL
10348 || code
== BFD_RELOC_X86_64_32S
)
10350 && fixp
->fx_addsy
== GOT_symbol
)
10353 code
= BFD_RELOC_386_GOTPC
;
10355 code
= BFD_RELOC_X86_64_GOTPC32
;
10357 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10359 && fixp
->fx_addsy
== GOT_symbol
)
10361 code
= BFD_RELOC_X86_64_GOTPC64
;
10364 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10365 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10366 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10368 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10370 if (!use_rela_relocations
)
10372 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10373 vtable entry to be used in the relocation's section offset. */
10374 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10375 rel
->address
= fixp
->fx_offset
;
10376 #if defined (OBJ_COFF) && defined (TE_PE)
10377 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10378 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10383 /* Use the rela in 64bit mode. */
10386 if (disallow_64bit_reloc
)
10389 case BFD_RELOC_X86_64_DTPOFF64
:
10390 case BFD_RELOC_X86_64_TPOFF64
:
10391 case BFD_RELOC_64_PCREL
:
10392 case BFD_RELOC_X86_64_GOTOFF64
:
10393 case BFD_RELOC_X86_64_GOT64
:
10394 case BFD_RELOC_X86_64_GOTPCREL64
:
10395 case BFD_RELOC_X86_64_GOTPC64
:
10396 case BFD_RELOC_X86_64_GOTPLT64
:
10397 case BFD_RELOC_X86_64_PLTOFF64
:
10398 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10399 _("cannot represent relocation type %s in x32 mode"),
10400 bfd_get_reloc_code_name (code
));
10406 if (!fixp
->fx_pcrel
)
10407 rel
->addend
= fixp
->fx_offset
;
10411 case BFD_RELOC_X86_64_PLT32
:
10412 case BFD_RELOC_X86_64_PLT32_BND
:
10413 case BFD_RELOC_X86_64_GOT32
:
10414 case BFD_RELOC_X86_64_GOTPCREL
:
10415 case BFD_RELOC_X86_64_TLSGD
:
10416 case BFD_RELOC_X86_64_TLSLD
:
10417 case BFD_RELOC_X86_64_GOTTPOFF
:
10418 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10419 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10420 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10423 rel
->addend
= (section
->vma
10425 + fixp
->fx_addnumber
10426 + md_pcrel_from (fixp
));
10431 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10432 if (rel
->howto
== NULL
)
10434 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10435 _("cannot represent relocation type %s"),
10436 bfd_get_reloc_code_name (code
));
10437 /* Set howto to a garbage value so that we can keep going. */
10438 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10439 gas_assert (rel
->howto
!= NULL
);
10445 #include "tc-i386-intel.c"
10448 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10450 int saved_naked_reg
;
10451 char saved_register_dot
;
10453 saved_naked_reg
= allow_naked_reg
;
10454 allow_naked_reg
= 1;
10455 saved_register_dot
= register_chars
['.'];
10456 register_chars
['.'] = '.';
10457 allow_pseudo_reg
= 1;
10458 expression_and_evaluate (exp
);
10459 allow_pseudo_reg
= 0;
10460 register_chars
['.'] = saved_register_dot
;
10461 allow_naked_reg
= saved_naked_reg
;
10463 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10465 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10467 exp
->X_op
= O_constant
;
10468 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10469 .dw2_regnum
[flag_code
>> 1];
10472 exp
->X_op
= O_illegal
;
10477 tc_x86_frame_initial_instructions (void)
10479 static unsigned int sp_regno
[2];
10481 if (!sp_regno
[flag_code
>> 1])
10483 char *saved_input
= input_line_pointer
;
10484 char sp
[][4] = {"esp", "rsp"};
10487 input_line_pointer
= sp
[flag_code
>> 1];
10488 tc_x86_parse_to_dw2regnum (&exp
);
10489 gas_assert (exp
.X_op
== O_constant
);
10490 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10491 input_line_pointer
= saved_input
;
10494 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10495 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10499 x86_dwarf2_addr_size (void)
10501 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10502 if (x86_elf_abi
== X86_64_X32_ABI
)
10505 return bfd_arch_bits_per_address (stdoutput
) / 8;
10509 i386_elf_section_type (const char *str
, size_t len
)
10511 if (flag_code
== CODE_64BIT
10512 && len
== sizeof ("unwind") - 1
10513 && strncmp (str
, "unwind", 6) == 0)
10514 return SHT_X86_64_UNWIND
;
10521 i386_solaris_fix_up_eh_frame (segT sec
)
10523 if (flag_code
== CODE_64BIT
)
10524 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10530 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10534 exp
.X_op
= O_secrel
;
10535 exp
.X_add_symbol
= symbol
;
10536 exp
.X_add_number
= 0;
10537 emit_expr (&exp
, size
);
10541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10542 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10545 x86_64_section_letter (int letter
, char **ptr_msg
)
10547 if (flag_code
== CODE_64BIT
)
10550 return SHF_X86_64_LARGE
;
10552 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10555 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10560 x86_64_section_word (char *str
, size_t len
)
10562 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10563 return SHF_X86_64_LARGE
;
10569 handle_large_common (int small ATTRIBUTE_UNUSED
)
10571 if (flag_code
!= CODE_64BIT
)
10573 s_comm_internal (0, elf_common_parse
);
10574 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10578 static segT lbss_section
;
10579 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10580 asection
*saved_bss_section
= bss_section
;
10582 if (lbss_section
== NULL
)
10584 flagword applicable
;
10585 segT seg
= now_seg
;
10586 subsegT subseg
= now_subseg
;
10588 /* The .lbss section is for local .largecomm symbols. */
10589 lbss_section
= subseg_new (".lbss", 0);
10590 applicable
= bfd_applicable_section_flags (stdoutput
);
10591 bfd_set_section_flags (stdoutput
, lbss_section
,
10592 applicable
& SEC_ALLOC
);
10593 seg_info (lbss_section
)->bss
= 1;
10595 subseg_set (seg
, subseg
);
10598 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10599 bss_section
= lbss_section
;
10601 s_comm_internal (0, elf_common_parse
);
10603 elf_com_section_ptr
= saved_com_section_ptr
;
10604 bss_section
= saved_bss_section
;
10607 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */