1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO
,
172 /* x86 arch names, types and features */
175 const char *name
; /* arch name */
176 enum processor_type type
; /* arch type */
177 i386_cpu_flags flags
; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_sse_check (int);
187 static void set_cpu_arch (int);
189 static void pe_directive_secrel (int);
191 static void signed_cons (int);
192 static char *output_invalid (int c
);
193 static int i386_att_operand (char *);
194 static int i386_intel_operand (char *, int);
195 static const reg_entry
*parse_register (char *, char **);
196 static char *parse_insn (char *, char *);
197 static char *parse_operands (char *, const char *);
198 static void swap_operands (void);
199 static void swap_2_operands (int, int);
200 static void optimize_imm (void);
201 static void optimize_disp (void);
202 static int match_template (void);
203 static int check_string (void);
204 static int process_suffix (void);
205 static int check_byte_reg (void);
206 static int check_long_reg (void);
207 static int check_qword_reg (void);
208 static int check_word_reg (void);
209 static int finalize_imm (void);
210 static void process_drex (void);
211 static int process_operands (void);
212 static const seg_entry
*build_modrm_byte (void);
213 static void output_insn (void);
214 static void output_imm (fragS
*, offsetT
);
215 static void output_disp (fragS
*, offsetT
);
217 static void s_bss (int);
219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
223 static const char *default_arch
= DEFAULT_ARCH
;
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes
[3];
231 /* Destination or source register specifier. */
232 const reg_entry
*register_specifier
;
235 /* 'md_assemble ()' gathers together information and puts it into a
242 const reg_entry
*regs
;
247 /* TM holds the template for the insn were currently assembling. */
250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
254 /* OPERANDS gives the number of given operands. */
255 unsigned int operands
;
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
260 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
262 /* TYPES [i] is the type (see above #defines) which tells us how to
263 use OP[i] for the corresponding operand. */
264 i386_operand_type types
[MAX_OPERANDS
];
266 /* Displacement expression, immediate expression, or register for each
268 union i386_op op
[MAX_OPERANDS
];
270 /* Flags for operands. */
271 unsigned int flags
[MAX_OPERANDS
];
272 #define Operand_PCrel 1
274 /* Relocation type for operand */
275 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry
*base_reg
;
280 const reg_entry
*index_reg
;
281 unsigned int log2_scale_factor
;
283 /* SEG gives the seg_entries of this insn. They are zero unless
284 explicit segment overrides are given. */
285 const seg_entry
*seg
[2];
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes
;
290 unsigned char prefix
[MAX_PREFIXES
];
292 /* RM and SIB are the modrm byte and the sib byte where the
293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
303 typedef struct _i386_insn i386_insn
;
305 /* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
307 const char extra_symbol_chars
[] = "*%-(["
316 #if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
318 && !defined (TE_GNU) \
319 && !defined (TE_LINUX) \
320 && !defined (TE_NETWARE) \
321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
323 /* This array holds the chars that always start a comment. If the
324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326 const char *i386_comment_chars
= "#/";
327 #define SVR4_COMMENT_CHARS 1
328 #define PREFIX_SEPARATOR '\\'
331 const char *i386_comment_chars
= "#";
332 #define PREFIX_SEPARATOR '/'
335 /* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
339 first line of the input file. This is because the compiler outputs
340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
342 '/' isn't otherwise defined. */
343 const char line_comment_chars
[] = "#/";
345 const char line_separator_chars
[] = ";";
347 /* Chars that can be used to separate mant from exp in floating point
349 const char EXP_CHARS
[] = "eE";
351 /* Chars that mean this number is a floating point constant
354 const char FLT_CHARS
[] = "fFdDxX";
356 /* Tables for lexical analysis. */
357 static char mnemonic_chars
[256];
358 static char register_chars
[256];
359 static char operand_chars
[256];
360 static char identifier_chars
[256];
361 static char digit_chars
[256];
363 /* Lexical macros. */
364 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365 #define is_operand_char(x) (operand_chars[(unsigned char) x])
366 #define is_register_char(x) (register_chars[(unsigned char) x])
367 #define is_space_char(x) ((x) == ' ')
368 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369 #define is_digit_char(x) (digit_chars[(unsigned char) x])
371 /* All non-digit non-letter characters that may occur in an operand. */
372 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
374 /* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
377 assembler instruction). */
378 static char save_stack
[32];
379 static char *save_stack_p
;
380 #define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382 #define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
385 /* The instruction we're assembling. */
388 /* Possible templates for current insn. */
389 static const templates
*current_templates
;
391 /* Per instruction expressionS buffers: max displacements & immediates. */
392 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
393 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
395 /* Current operand we are working on. */
396 static int this_operand
;
398 /* We support four different modes. FLAG_CODE variable is used to distinguish
406 static enum flag_code flag_code
;
407 static unsigned int object_64bit
;
408 static int use_rela_relocations
= 0;
410 /* The names used to print error messages. */
411 static const char *flag_code_names
[] =
418 /* 1 for intel syntax,
420 static int intel_syntax
= 0;
422 /* 1 for intel mnemonic,
423 0 if att mnemonic. */
424 static int intel_mnemonic
= !SYSV386_COMPAT
;
426 /* 1 if support old (<= 2.8.1) versions of gcc. */
427 static int old_gcc
= OLDGCC_COMPAT
;
429 /* 1 if pseudo registers are permitted. */
430 static int allow_pseudo_reg
= 0;
432 /* 1 if register prefix % not required. */
433 static int allow_naked_reg
= 0;
435 /* 1 if pseudo index register, eiz/riz, is allowed . */
436 static int allow_index_reg
= 0;
446 /* Register prefix used for error message. */
447 static const char *register_prefix
= "%";
449 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452 static char stackop_size
= '\0';
454 /* Non-zero to optimize code alignment. */
455 int optimize_align_code
= 1;
457 /* Non-zero to quieten some warnings. */
458 static int quiet_warnings
= 0;
461 static const char *cpu_arch_name
= NULL
;
462 static char *cpu_sub_arch_name
= NULL
;
464 /* CPU feature flags. */
465 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
467 /* If we have selected a cpu we are generating instructions for. */
468 static int cpu_arch_tune_set
= 0;
470 /* Cpu we are generating instructions for. */
471 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
473 /* CPU feature flags of cpu we are generating instructions for. */
474 static i386_cpu_flags cpu_arch_tune_flags
;
476 /* CPU instruction set architecture used. */
477 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
479 /* CPU feature flags of instruction set architecture used. */
480 static i386_cpu_flags cpu_arch_isa_flags
;
482 /* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484 static unsigned int no_cond_jump_promotion
= 0;
486 /* Encode SSE instructions with VEX prefix. */
487 static unsigned int sse2avx
;
489 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
490 static symbolS
*GOT_symbol
;
492 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
493 unsigned int x86_dwarf2_return_column
;
495 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496 int x86_cie_data_alignment
;
498 /* Interface to relax_segment.
499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
504 #define UNCOND_JUMP 0
506 #define COND_JUMP86 2
511 #define SMALL16 (SMALL | CODE16)
513 #define BIG16 (BIG | CODE16)
517 #define INLINE __inline__
523 #define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525 #define TYPE_FROM_RELAX_STATE(s) \
527 #define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
530 /* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
538 const relax_typeS md_relax_table
[] =
541 1) most positive reach of this state,
542 2) most negative reach of this state,
543 3) how many bytes this mode will have in the variable part of the frag
544 4) which index into the table to try if we can't fit into this one. */
546 /* UNCOND_JUMP states. */
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
562 /* word conditionals add 3 bytes to frag:
563 1 extra opcode byte, 2 displacement bytes. */
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
577 static const arch_entry cpu_arch
[] =
579 { "generic32", PROCESSOR_GENERIC32
,
580 CPU_GENERIC32_FLAGS
},
581 { "generic64", PROCESSOR_GENERIC64
,
582 CPU_GENERIC64_FLAGS
},
583 { "i8086", PROCESSOR_UNKNOWN
,
585 { "i186", PROCESSOR_UNKNOWN
,
587 { "i286", PROCESSOR_UNKNOWN
,
589 { "i386", PROCESSOR_I386
,
591 { "i486", PROCESSOR_I486
,
593 { "i586", PROCESSOR_PENTIUM
,
595 { "i686", PROCESSOR_PENTIUMPRO
,
597 { "pentium", PROCESSOR_PENTIUM
,
599 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
601 { "pentiumii", PROCESSOR_PENTIUMPRO
,
603 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
605 { "pentium4", PROCESSOR_PENTIUM4
,
607 { "prescott", PROCESSOR_NOCONA
,
609 { "nocona", PROCESSOR_NOCONA
,
611 { "yonah", PROCESSOR_CORE
,
613 { "core", PROCESSOR_CORE
,
615 { "merom", PROCESSOR_CORE2
,
617 { "core2", PROCESSOR_CORE2
,
619 { "k6", PROCESSOR_K6
,
621 { "k6_2", PROCESSOR_K6
,
623 { "athlon", PROCESSOR_ATHLON
,
625 { "sledgehammer", PROCESSOR_K8
,
627 { "opteron", PROCESSOR_K8
,
629 { "k8", PROCESSOR_K8
,
631 { "amdfam10", PROCESSOR_AMDFAM10
,
632 CPU_AMDFAM10_FLAGS
},
633 { ".mmx", PROCESSOR_UNKNOWN
,
635 { ".sse", PROCESSOR_UNKNOWN
,
637 { ".sse2", PROCESSOR_UNKNOWN
,
639 { ".sse3", PROCESSOR_UNKNOWN
,
641 { ".ssse3", PROCESSOR_UNKNOWN
,
643 { ".sse4.1", PROCESSOR_UNKNOWN
,
645 { ".sse4.2", PROCESSOR_UNKNOWN
,
647 { ".sse4", PROCESSOR_UNKNOWN
,
649 { ".avx", PROCESSOR_UNKNOWN
,
651 { ".vmx", PROCESSOR_UNKNOWN
,
653 { ".smx", PROCESSOR_UNKNOWN
,
655 { ".xsave", PROCESSOR_UNKNOWN
,
657 { ".aes", PROCESSOR_UNKNOWN
,
659 { ".pclmul", PROCESSOR_UNKNOWN
,
661 { ".clmul", PROCESSOR_UNKNOWN
,
663 { ".fma", PROCESSOR_UNKNOWN
,
665 { ".movbe", PROCESSOR_UNKNOWN
,
667 { ".ept", PROCESSOR_UNKNOWN
,
669 { ".3dnow", PROCESSOR_UNKNOWN
,
671 { ".3dnowa", PROCESSOR_UNKNOWN
,
673 { ".padlock", PROCESSOR_UNKNOWN
,
675 { ".pacifica", PROCESSOR_UNKNOWN
,
677 { ".svme", PROCESSOR_UNKNOWN
,
679 { ".sse4a", PROCESSOR_UNKNOWN
,
681 { ".abm", PROCESSOR_UNKNOWN
,
683 { ".sse5", PROCESSOR_UNKNOWN
,
687 const pseudo_typeS md_pseudo_table
[] =
689 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes
, 0},
692 {"align", s_align_ptwo
, 0},
694 {"arch", set_cpu_arch
, 0},
698 {"ffloat", float_cons
, 'f'},
699 {"dfloat", float_cons
, 'd'},
700 {"tfloat", float_cons
, 'x'},
702 {"slong", signed_cons
, 4},
703 {"noopt", s_ignore
, 0},
704 {"optim", s_ignore
, 0},
705 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
706 {"code16", set_code_flag
, CODE_16BIT
},
707 {"code32", set_code_flag
, CODE_32BIT
},
708 {"code64", set_code_flag
, CODE_64BIT
},
709 {"intel_syntax", set_intel_syntax
, 1},
710 {"att_syntax", set_intel_syntax
, 0},
711 {"intel_mnemonic", set_intel_mnemonic
, 1},
712 {"att_mnemonic", set_intel_mnemonic
, 0},
713 {"allow_index_reg", set_allow_index_reg
, 1},
714 {"disallow_index_reg", set_allow_index_reg
, 0},
715 {"sse_check", set_sse_check
, 0},
716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common
, 0},
719 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
720 {"loc", dwarf2_directive_loc
, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
724 {"secrel32", pe_directive_secrel
, 0},
729 /* For interface with expression (). */
730 extern char *input_line_pointer
;
732 /* Hash table for instruction mnemonic lookup. */
733 static struct hash_control
*op_hash
;
735 /* Hash table for register lookup. */
736 static struct hash_control
*reg_hash
;
739 i386_align_code (fragS
*fragP
, int count
)
741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
744 static const char f32_1
[] =
746 static const char f32_2
[] =
747 {0x66,0x90}; /* xchg %ax,%ax */
748 static const char f32_3
[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4
[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5
[] =
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6
[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7
[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8
[] =
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9
[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10
[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11
[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12
[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13
[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14
[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
780 static const char f16_3
[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
782 static const char f16_4
[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5
[] =
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6
[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7
[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8
[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
796 static const char jump_31
[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
801 static const char *const f32_patt
[] = {
802 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
803 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
805 static const char *const f16_patt
[] = {
806 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
809 static const char alt_3
[] =
811 /* nopl 0(%[re]ax) */
812 static const char alt_4
[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5
[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6
[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7
[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8
[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9
[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10
[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11
[] =
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12
[] =
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13
[] =
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15
[] =
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11
[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12
[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
889 static const char alt_short_13
[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
894 static const char alt_short_14
[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15
[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt
[] = {
903 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
904 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
905 alt_short_14
, alt_short_15
907 static const char *const alt_long_patt
[] = {
908 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
909 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
910 alt_long_14
, alt_long_15
913 /* Only align for at least a positive non-zero boundary. */
914 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
935 if (flag_code
== CODE_16BIT
)
939 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
941 /* Adjust jump offset. */
942 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
945 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
946 f16_patt
[count
- 1], count
);
950 const char *const *patt
= NULL
;
952 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune
)
957 case PROCESSOR_UNKNOWN
:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
960 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
961 patt
= alt_long_patt
;
965 case PROCESSOR_PENTIUMPRO
:
966 case PROCESSOR_PENTIUM4
:
967 case PROCESSOR_NOCONA
:
969 case PROCESSOR_CORE2
:
970 case PROCESSOR_GENERIC64
:
971 patt
= alt_long_patt
;
974 case PROCESSOR_ATHLON
:
976 case PROCESSOR_AMDFAM10
:
977 patt
= alt_short_patt
;
981 case PROCESSOR_PENTIUM
:
982 case PROCESSOR_GENERIC32
:
989 switch (cpu_arch_tune
)
991 case PROCESSOR_UNKNOWN
:
992 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
993 PROCESSOR_UNKNOWN. */
999 case PROCESSOR_PENTIUM
:
1001 case PROCESSOR_ATHLON
:
1003 case PROCESSOR_AMDFAM10
:
1004 case PROCESSOR_GENERIC32
:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1007 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1008 patt
= alt_short_patt
;
1012 case PROCESSOR_PENTIUMPRO
:
1013 case PROCESSOR_PENTIUM4
:
1014 case PROCESSOR_NOCONA
:
1015 case PROCESSOR_CORE
:
1016 case PROCESSOR_CORE2
:
1017 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1018 patt
= alt_long_patt
;
1022 case PROCESSOR_GENERIC64
:
1023 patt
= alt_long_patt
;
1028 if (patt
== f32_patt
)
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1034 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1035 patt
[count
- 1], count
);
1038 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1040 /* Adjust jump offset. */
1041 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding
= count
;
1050 while (padding
> 15)
1053 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1058 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1059 patt
[padding
- 1], padding
);
1062 fragP
->fr_var
= count
;
1066 operand_type_all_zero (const union i386_operand_type
*x
)
1068 switch (ARRAY_SIZE(x
->array
))
1077 return !x
->array
[0];
1084 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1086 switch (ARRAY_SIZE(x
->array
))
1101 operand_type_equal (const union i386_operand_type
*x
,
1102 const union i386_operand_type
*y
)
1104 switch (ARRAY_SIZE(x
->array
))
1107 if (x
->array
[2] != y
->array
[2])
1110 if (x
->array
[1] != y
->array
[1])
1113 return x
->array
[0] == y
->array
[0];
1121 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1123 switch (ARRAY_SIZE(x
->array
))
1132 return !x
->array
[0];
1139 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1141 switch (ARRAY_SIZE(x
->array
))
1156 cpu_flags_equal (const union i386_cpu_flags
*x
,
1157 const union i386_cpu_flags
*y
)
1159 switch (ARRAY_SIZE(x
->array
))
1162 if (x
->array
[2] != y
->array
[2])
1165 if (x
->array
[1] != y
->array
[1])
1168 return x
->array
[0] == y
->array
[0];
1176 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1178 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1179 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1182 static INLINE i386_cpu_flags
1183 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1185 switch (ARRAY_SIZE (x
.array
))
1188 x
.array
[2] &= y
.array
[2];
1190 x
.array
[1] &= y
.array
[1];
1192 x
.array
[0] &= y
.array
[0];
1200 static INLINE i386_cpu_flags
1201 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1203 switch (ARRAY_SIZE (x
.array
))
1206 x
.array
[2] |= y
.array
[2];
1208 x
.array
[1] |= y
.array
[1];
1210 x
.array
[0] |= y
.array
[0];
1218 #define CPU_FLAGS_ARCH_MATCH 0x1
1219 #define CPU_FLAGS_64BIT_MATCH 0x2
1220 #define CPU_FLAGS_AES_MATCH 0x4
1221 #define CPU_FLAGS_AVX_MATCH 0x8
1223 #define CPU_FLAGS_32BIT_MATCH \
1224 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1225 #define CPU_FLAGS_PERFECT_MATCH \
1226 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1228 /* Return CPU flags match bits. */
1231 cpu_flags_match (const template *t
)
1233 i386_cpu_flags x
= t
->cpu_flags
;
1234 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1236 x
.bitfield
.cpu64
= 0;
1237 x
.bitfield
.cpuno64
= 0;
1239 if (cpu_flags_all_zero (&x
))
1241 /* This instruction is available on all archs. */
1242 match
|= CPU_FLAGS_32BIT_MATCH
;
1246 /* This instruction is available only on some archs. */
1247 i386_cpu_flags cpu
= cpu_arch_flags
;
1249 cpu
.bitfield
.cpu64
= 0;
1250 cpu
.bitfield
.cpuno64
= 0;
1251 cpu
= cpu_flags_and (x
, cpu
);
1252 if (!cpu_flags_all_zero (&cpu
))
1254 if (x
.bitfield
.cpuavx
)
1256 /* We only need to check AES/SSE2AVX with AVX. */
1257 if (cpu
.bitfield
.cpuavx
)
1259 /* Check SSE2AVX. */
1260 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1262 match
|= (CPU_FLAGS_ARCH_MATCH
1263 | CPU_FLAGS_AVX_MATCH
);
1265 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1266 match
|= CPU_FLAGS_AES_MATCH
;
1270 match
|= CPU_FLAGS_ARCH_MATCH
;
1273 match
|= CPU_FLAGS_32BIT_MATCH
;
1279 static INLINE i386_operand_type
1280 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1282 switch (ARRAY_SIZE (x
.array
))
1285 x
.array
[2] &= y
.array
[2];
1287 x
.array
[1] &= y
.array
[1];
1289 x
.array
[0] &= y
.array
[0];
1297 static INLINE i386_operand_type
1298 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1300 switch (ARRAY_SIZE (x
.array
))
1303 x
.array
[2] |= y
.array
[2];
1305 x
.array
[1] |= y
.array
[1];
1307 x
.array
[0] |= y
.array
[0];
1315 static INLINE i386_operand_type
1316 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1318 switch (ARRAY_SIZE (x
.array
))
1321 x
.array
[2] ^= y
.array
[2];
1323 x
.array
[1] ^= y
.array
[1];
1325 x
.array
[0] ^= y
.array
[0];
1333 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1334 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1335 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1336 static const i386_operand_type inoutportreg
1337 = OPERAND_TYPE_INOUTPORTREG
;
1338 static const i386_operand_type reg16_inoutportreg
1339 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1340 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1341 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1342 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1343 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1344 static const i386_operand_type anydisp
1345 = OPERAND_TYPE_ANYDISP
;
1346 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1347 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1348 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1349 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1350 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1351 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1352 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1353 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1354 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1355 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1356 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1357 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1368 operand_type_check (i386_operand_type t
, enum operand_type c
)
1373 return (t
.bitfield
.reg8
1376 || t
.bitfield
.reg64
);
1379 return (t
.bitfield
.imm8
1383 || t
.bitfield
.imm32s
1384 || t
.bitfield
.imm64
);
1387 return (t
.bitfield
.disp8
1388 || t
.bitfield
.disp16
1389 || t
.bitfield
.disp32
1390 || t
.bitfield
.disp32s
1391 || t
.bitfield
.disp64
);
1394 return (t
.bitfield
.disp8
1395 || t
.bitfield
.disp16
1396 || t
.bitfield
.disp32
1397 || t
.bitfield
.disp32s
1398 || t
.bitfield
.disp64
1399 || t
.bitfield
.baseindex
);
1408 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1409 operand J for instruction template T. */
1412 match_reg_size (const template *t
, unsigned int j
)
1414 return !((i
.types
[j
].bitfield
.byte
1415 && !t
->operand_types
[j
].bitfield
.byte
)
1416 || (i
.types
[j
].bitfield
.word
1417 && !t
->operand_types
[j
].bitfield
.word
)
1418 || (i
.types
[j
].bitfield
.dword
1419 && !t
->operand_types
[j
].bitfield
.dword
)
1420 || (i
.types
[j
].bitfield
.qword
1421 && !t
->operand_types
[j
].bitfield
.qword
));
1424 /* Return 1 if there is no conflict in any size on operand J for
1425 instruction template T. */
1428 match_mem_size (const template *t
, unsigned int j
)
1430 return (match_reg_size (t
, j
)
1431 && !((i
.types
[j
].bitfield
.unspecified
1432 && !t
->operand_types
[j
].bitfield
.unspecified
)
1433 || (i
.types
[j
].bitfield
.fword
1434 && !t
->operand_types
[j
].bitfield
.fword
)
1435 || (i
.types
[j
].bitfield
.tbyte
1436 && !t
->operand_types
[j
].bitfield
.tbyte
)
1437 || (i
.types
[j
].bitfield
.xmmword
1438 && !t
->operand_types
[j
].bitfield
.xmmword
)
1439 || (i
.types
[j
].bitfield
.ymmword
1440 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1443 /* Return 1 if there is no size conflict on any operands for
1444 instruction template T. */
1447 operand_size_match (const template *t
)
1452 /* Don't check jump instructions. */
1453 if (t
->opcode_modifier
.jump
1454 || t
->opcode_modifier
.jumpbyte
1455 || t
->opcode_modifier
.jumpdword
1456 || t
->opcode_modifier
.jumpintersegment
)
1459 /* Check memory and accumulator operand size. */
1460 for (j
= 0; j
< i
.operands
; j
++)
1462 if (t
->operand_types
[j
].bitfield
.anysize
)
1465 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1471 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1479 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1482 /* Check reverse. */
1483 assert (i
.operands
== 2);
1486 for (j
= 0; j
< 2; j
++)
1488 if (t
->operand_types
[j
].bitfield
.acc
1489 && !match_reg_size (t
, j
? 0 : 1))
1495 if (i
.types
[j
].bitfield
.mem
1496 && !match_mem_size (t
, j
? 0 : 1))
1507 operand_type_match (i386_operand_type overlap
,
1508 i386_operand_type given
)
1510 i386_operand_type temp
= overlap
;
1512 temp
.bitfield
.jumpabsolute
= 0;
1513 temp
.bitfield
.unspecified
= 0;
1514 temp
.bitfield
.byte
= 0;
1515 temp
.bitfield
.word
= 0;
1516 temp
.bitfield
.dword
= 0;
1517 temp
.bitfield
.fword
= 0;
1518 temp
.bitfield
.qword
= 0;
1519 temp
.bitfield
.tbyte
= 0;
1520 temp
.bitfield
.xmmword
= 0;
1521 temp
.bitfield
.ymmword
= 0;
1522 if (operand_type_all_zero (&temp
))
1525 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1526 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1529 /* If given types g0 and g1 are registers they must be of the same type
1530 unless the expected operand type register overlap is null.
1531 Note that Acc in a template matches every size of reg. */
1534 operand_type_register_match (i386_operand_type m0
,
1535 i386_operand_type g0
,
1536 i386_operand_type t0
,
1537 i386_operand_type m1
,
1538 i386_operand_type g1
,
1539 i386_operand_type t1
)
1541 if (!operand_type_check (g0
, reg
))
1544 if (!operand_type_check (g1
, reg
))
1547 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1548 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1549 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1550 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1553 if (m0
.bitfield
.acc
)
1555 t0
.bitfield
.reg8
= 1;
1556 t0
.bitfield
.reg16
= 1;
1557 t0
.bitfield
.reg32
= 1;
1558 t0
.bitfield
.reg64
= 1;
1561 if (m1
.bitfield
.acc
)
1563 t1
.bitfield
.reg8
= 1;
1564 t1
.bitfield
.reg16
= 1;
1565 t1
.bitfield
.reg32
= 1;
1566 t1
.bitfield
.reg64
= 1;
1569 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1570 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1571 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1572 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1575 static INLINE
unsigned int
1576 mode_from_disp_size (i386_operand_type t
)
1578 if (t
.bitfield
.disp8
)
1580 else if (t
.bitfield
.disp16
1581 || t
.bitfield
.disp32
1582 || t
.bitfield
.disp32s
)
1589 fits_in_signed_byte (offsetT num
)
1591 return (num
>= -128) && (num
<= 127);
1595 fits_in_unsigned_byte (offsetT num
)
1597 return (num
& 0xff) == num
;
1601 fits_in_unsigned_word (offsetT num
)
1603 return (num
& 0xffff) == num
;
1607 fits_in_signed_word (offsetT num
)
1609 return (-32768 <= num
) && (num
<= 32767);
1613 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1618 return (!(((offsetT
) -1 << 31) & num
)
1619 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1621 } /* fits_in_signed_long() */
1624 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1629 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1631 } /* fits_in_unsigned_long() */
1634 fits_in_imm4 (offsetT num
)
1636 return (num
& 0xf) == num
;
1639 static i386_operand_type
1640 smallest_imm_type (offsetT num
)
1642 i386_operand_type t
;
1644 operand_type_set (&t
, 0);
1645 t
.bitfield
.imm64
= 1;
1647 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1649 /* This code is disabled on the 486 because all the Imm1 forms
1650 in the opcode table are slower on the i486. They're the
1651 versions with the implicitly specified single-position
1652 displacement, which has another syntax if you really want to
1654 t
.bitfield
.imm1
= 1;
1655 t
.bitfield
.imm8
= 1;
1656 t
.bitfield
.imm8s
= 1;
1657 t
.bitfield
.imm16
= 1;
1658 t
.bitfield
.imm32
= 1;
1659 t
.bitfield
.imm32s
= 1;
1661 else if (fits_in_signed_byte (num
))
1663 t
.bitfield
.imm8
= 1;
1664 t
.bitfield
.imm8s
= 1;
1665 t
.bitfield
.imm16
= 1;
1666 t
.bitfield
.imm32
= 1;
1667 t
.bitfield
.imm32s
= 1;
1669 else if (fits_in_unsigned_byte (num
))
1671 t
.bitfield
.imm8
= 1;
1672 t
.bitfield
.imm16
= 1;
1673 t
.bitfield
.imm32
= 1;
1674 t
.bitfield
.imm32s
= 1;
1676 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1678 t
.bitfield
.imm16
= 1;
1679 t
.bitfield
.imm32
= 1;
1680 t
.bitfield
.imm32s
= 1;
1682 else if (fits_in_signed_long (num
))
1684 t
.bitfield
.imm32
= 1;
1685 t
.bitfield
.imm32s
= 1;
1687 else if (fits_in_unsigned_long (num
))
1688 t
.bitfield
.imm32
= 1;
1694 offset_in_range (offsetT val
, int size
)
1700 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1701 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1702 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1704 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1709 /* If BFD64, sign extend val. */
1710 if (!use_rela_relocations
)
1711 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1712 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1714 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1716 char buf1
[40], buf2
[40];
1718 sprint_value (buf1
, val
);
1719 sprint_value (buf2
, val
& mask
);
1720 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1725 /* Returns 0 if attempting to add a prefix where one from the same
1726 class already exists, 1 if non rep/repne added, 2 if rep/repne
1729 add_prefix (unsigned int prefix
)
1734 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1735 && flag_code
== CODE_64BIT
)
1737 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1738 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1739 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1750 case CS_PREFIX_OPCODE
:
1751 case DS_PREFIX_OPCODE
:
1752 case ES_PREFIX_OPCODE
:
1753 case FS_PREFIX_OPCODE
:
1754 case GS_PREFIX_OPCODE
:
1755 case SS_PREFIX_OPCODE
:
1759 case REPNE_PREFIX_OPCODE
:
1760 case REPE_PREFIX_OPCODE
:
1763 case LOCK_PREFIX_OPCODE
:
1771 case ADDR_PREFIX_OPCODE
:
1775 case DATA_PREFIX_OPCODE
:
1779 if (i
.prefix
[q
] != 0)
1787 i
.prefix
[q
] |= prefix
;
1790 as_bad (_("same type of prefix used twice"));
1796 set_code_flag (int value
)
1799 if (flag_code
== CODE_64BIT
)
1801 cpu_arch_flags
.bitfield
.cpu64
= 1;
1802 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1806 cpu_arch_flags
.bitfield
.cpu64
= 0;
1807 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1809 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1811 as_bad (_("64bit mode not supported on this CPU."));
1813 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1815 as_bad (_("32bit mode not supported on this CPU."));
1817 stackop_size
= '\0';
1821 set_16bit_gcc_code_flag (int new_code_flag
)
1823 flag_code
= new_code_flag
;
1824 if (flag_code
!= CODE_16BIT
)
1826 cpu_arch_flags
.bitfield
.cpu64
= 0;
1827 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1828 stackop_size
= LONG_MNEM_SUFFIX
;
1832 set_intel_syntax (int syntax_flag
)
1834 /* Find out if register prefixing is specified. */
1835 int ask_naked_reg
= 0;
1838 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1840 char *string
= input_line_pointer
;
1841 int e
= get_symbol_end ();
1843 if (strcmp (string
, "prefix") == 0)
1845 else if (strcmp (string
, "noprefix") == 0)
1848 as_bad (_("bad argument to syntax directive."));
1849 *input_line_pointer
= e
;
1851 demand_empty_rest_of_line ();
1853 intel_syntax
= syntax_flag
;
1855 if (ask_naked_reg
== 0)
1856 allow_naked_reg
= (intel_syntax
1857 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1859 allow_naked_reg
= (ask_naked_reg
< 0);
1861 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1862 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1863 register_prefix
= allow_naked_reg
? "" : "%";
1867 set_intel_mnemonic (int mnemonic_flag
)
1869 intel_mnemonic
= mnemonic_flag
;
1873 set_allow_index_reg (int flag
)
1875 allow_index_reg
= flag
;
1879 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1883 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1885 char *string
= input_line_pointer
;
1886 int e
= get_symbol_end ();
1888 if (strcmp (string
, "none") == 0)
1889 sse_check
= sse_check_none
;
1890 else if (strcmp (string
, "warning") == 0)
1891 sse_check
= sse_check_warning
;
1892 else if (strcmp (string
, "error") == 0)
1893 sse_check
= sse_check_error
;
1895 as_bad (_("bad argument to sse_check directive."));
1896 *input_line_pointer
= e
;
1899 as_bad (_("missing argument for sse_check directive"));
1901 demand_empty_rest_of_line ();
1905 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1909 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1911 char *string
= input_line_pointer
;
1912 int e
= get_symbol_end ();
1914 i386_cpu_flags flags
;
1916 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1918 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1922 cpu_arch_name
= cpu_arch
[i
].name
;
1923 cpu_sub_arch_name
= NULL
;
1924 cpu_arch_flags
= cpu_arch
[i
].flags
;
1925 if (flag_code
== CODE_64BIT
)
1927 cpu_arch_flags
.bitfield
.cpu64
= 1;
1928 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1932 cpu_arch_flags
.bitfield
.cpu64
= 0;
1933 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1935 cpu_arch_isa
= cpu_arch
[i
].type
;
1936 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1937 if (!cpu_arch_tune_set
)
1939 cpu_arch_tune
= cpu_arch_isa
;
1940 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1945 flags
= cpu_flags_or (cpu_arch_flags
,
1947 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1949 if (cpu_sub_arch_name
)
1951 char *name
= cpu_sub_arch_name
;
1952 cpu_sub_arch_name
= concat (name
,
1954 (const char *) NULL
);
1958 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1959 cpu_arch_flags
= flags
;
1961 *input_line_pointer
= e
;
1962 demand_empty_rest_of_line ();
1966 if (i
>= ARRAY_SIZE (cpu_arch
))
1967 as_bad (_("no such architecture: `%s'"), string
);
1969 *input_line_pointer
= e
;
1972 as_bad (_("missing cpu architecture"));
1974 no_cond_jump_promotion
= 0;
1975 if (*input_line_pointer
== ','
1976 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1978 char *string
= ++input_line_pointer
;
1979 int e
= get_symbol_end ();
1981 if (strcmp (string
, "nojumps") == 0)
1982 no_cond_jump_promotion
= 1;
1983 else if (strcmp (string
, "jumps") == 0)
1986 as_bad (_("no such architecture modifier: `%s'"), string
);
1988 *input_line_pointer
= e
;
1991 demand_empty_rest_of_line ();
1997 if (!strcmp (default_arch
, "x86_64"))
1998 return bfd_mach_x86_64
;
1999 else if (!strcmp (default_arch
, "i386"))
2000 return bfd_mach_i386_i386
;
2002 as_fatal (_("Unknown architecture"));
2008 const char *hash_err
;
2010 /* Initialize op_hash hash table. */
2011 op_hash
= hash_new ();
2014 const template *optab
;
2015 templates
*core_optab
;
2017 /* Setup for loop. */
2019 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2020 core_optab
->start
= optab
;
2025 if (optab
->name
== NULL
2026 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2028 /* different name --> ship out current template list;
2029 add to hash table; & begin anew. */
2030 core_optab
->end
= optab
;
2031 hash_err
= hash_insert (op_hash
,
2033 (void *) core_optab
);
2036 as_fatal (_("Internal Error: Can't hash %s: %s"),
2040 if (optab
->name
== NULL
)
2042 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2043 core_optab
->start
= optab
;
2048 /* Initialize reg_hash hash table. */
2049 reg_hash
= hash_new ();
2051 const reg_entry
*regtab
;
2052 unsigned int regtab_size
= i386_regtab_size
;
2054 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2056 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2058 as_fatal (_("Internal Error: Can't hash %s: %s"),
2064 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2069 for (c
= 0; c
< 256; c
++)
2074 mnemonic_chars
[c
] = c
;
2075 register_chars
[c
] = c
;
2076 operand_chars
[c
] = c
;
2078 else if (ISLOWER (c
))
2080 mnemonic_chars
[c
] = c
;
2081 register_chars
[c
] = c
;
2082 operand_chars
[c
] = c
;
2084 else if (ISUPPER (c
))
2086 mnemonic_chars
[c
] = TOLOWER (c
);
2087 register_chars
[c
] = mnemonic_chars
[c
];
2088 operand_chars
[c
] = c
;
2091 if (ISALPHA (c
) || ISDIGIT (c
))
2092 identifier_chars
[c
] = c
;
2095 identifier_chars
[c
] = c
;
2096 operand_chars
[c
] = c
;
2101 identifier_chars
['@'] = '@';
2104 identifier_chars
['?'] = '?';
2105 operand_chars
['?'] = '?';
2107 digit_chars
['-'] = '-';
2108 mnemonic_chars
['_'] = '_';
2109 mnemonic_chars
['-'] = '-';
2110 mnemonic_chars
['.'] = '.';
2111 identifier_chars
['_'] = '_';
2112 identifier_chars
['.'] = '.';
2114 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2115 operand_chars
[(unsigned char) *p
] = *p
;
2118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2121 record_alignment (text_section
, 2);
2122 record_alignment (data_section
, 2);
2123 record_alignment (bss_section
, 2);
2127 if (flag_code
== CODE_64BIT
)
2129 x86_dwarf2_return_column
= 16;
2130 x86_cie_data_alignment
= -8;
2134 x86_dwarf2_return_column
= 8;
2135 x86_cie_data_alignment
= -4;
2140 i386_print_statistics (FILE *file
)
2142 hash_print_statistics (file
, "i386 opcode", op_hash
);
2143 hash_print_statistics (file
, "i386 register", reg_hash
);
2148 /* Debugging routines for md_assemble. */
2149 static void pte (template *);
2150 static void pt (i386_operand_type
);
2151 static void pe (expressionS
*);
2152 static void ps (symbolS
*);
2155 pi (char *line
, i386_insn
*x
)
2159 fprintf (stdout
, "%s: template ", line
);
2161 fprintf (stdout
, " address: base %s index %s scale %x\n",
2162 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2163 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2164 x
->log2_scale_factor
);
2165 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2166 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2167 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2168 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2169 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2170 (x
->rex
& REX_W
) != 0,
2171 (x
->rex
& REX_R
) != 0,
2172 (x
->rex
& REX_X
) != 0,
2173 (x
->rex
& REX_B
) != 0);
2174 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2175 x
->drex
.reg
, x
->drex
.rex
);
2176 for (i
= 0; i
< x
->operands
; i
++)
2178 fprintf (stdout
, " #%d: ", i
+ 1);
2180 fprintf (stdout
, "\n");
2181 if (x
->types
[i
].bitfield
.reg8
2182 || x
->types
[i
].bitfield
.reg16
2183 || x
->types
[i
].bitfield
.reg32
2184 || x
->types
[i
].bitfield
.reg64
2185 || x
->types
[i
].bitfield
.regmmx
2186 || x
->types
[i
].bitfield
.regxmm
2187 || x
->types
[i
].bitfield
.regymm
2188 || x
->types
[i
].bitfield
.sreg2
2189 || x
->types
[i
].bitfield
.sreg3
2190 || x
->types
[i
].bitfield
.control
2191 || x
->types
[i
].bitfield
.debug
2192 || x
->types
[i
].bitfield
.test
)
2193 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2194 if (operand_type_check (x
->types
[i
], imm
))
2196 if (operand_type_check (x
->types
[i
], disp
))
2197 pe (x
->op
[i
].disps
);
2205 fprintf (stdout
, " %d operands ", t
->operands
);
2206 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2207 if (t
->extension_opcode
!= None
)
2208 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2209 if (t
->opcode_modifier
.d
)
2210 fprintf (stdout
, "D");
2211 if (t
->opcode_modifier
.w
)
2212 fprintf (stdout
, "W");
2213 fprintf (stdout
, "\n");
2214 for (i
= 0; i
< t
->operands
; i
++)
2216 fprintf (stdout
, " #%d type ", i
+ 1);
2217 pt (t
->operand_types
[i
]);
2218 fprintf (stdout
, "\n");
2225 fprintf (stdout
, " operation %d\n", e
->X_op
);
2226 fprintf (stdout
, " add_number %ld (%lx)\n",
2227 (long) e
->X_add_number
, (long) e
->X_add_number
);
2228 if (e
->X_add_symbol
)
2230 fprintf (stdout
, " add_symbol ");
2231 ps (e
->X_add_symbol
);
2232 fprintf (stdout
, "\n");
2236 fprintf (stdout
, " op_symbol ");
2237 ps (e
->X_op_symbol
);
2238 fprintf (stdout
, "\n");
2245 fprintf (stdout
, "%s type %s%s",
2247 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2248 segment_name (S_GET_SEGMENT (s
)));
2251 static struct type_name
2253 i386_operand_type mask
;
2256 const type_names
[] =
2258 { OPERAND_TYPE_REG8
, "r8" },
2259 { OPERAND_TYPE_REG16
, "r16" },
2260 { OPERAND_TYPE_REG32
, "r32" },
2261 { OPERAND_TYPE_REG64
, "r64" },
2262 { OPERAND_TYPE_IMM8
, "i8" },
2263 { OPERAND_TYPE_IMM8
, "i8s" },
2264 { OPERAND_TYPE_IMM16
, "i16" },
2265 { OPERAND_TYPE_IMM32
, "i32" },
2266 { OPERAND_TYPE_IMM32S
, "i32s" },
2267 { OPERAND_TYPE_IMM64
, "i64" },
2268 { OPERAND_TYPE_IMM1
, "i1" },
2269 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2270 { OPERAND_TYPE_DISP8
, "d8" },
2271 { OPERAND_TYPE_DISP16
, "d16" },
2272 { OPERAND_TYPE_DISP32
, "d32" },
2273 { OPERAND_TYPE_DISP32S
, "d32s" },
2274 { OPERAND_TYPE_DISP64
, "d64" },
2275 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2276 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2277 { OPERAND_TYPE_CONTROL
, "control reg" },
2278 { OPERAND_TYPE_TEST
, "test reg" },
2279 { OPERAND_TYPE_DEBUG
, "debug reg" },
2280 { OPERAND_TYPE_FLOATREG
, "FReg" },
2281 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2282 { OPERAND_TYPE_SREG2
, "SReg2" },
2283 { OPERAND_TYPE_SREG3
, "SReg3" },
2284 { OPERAND_TYPE_ACC
, "Acc" },
2285 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2286 { OPERAND_TYPE_REGMMX
, "rMMX" },
2287 { OPERAND_TYPE_REGXMM
, "rXMM" },
2288 { OPERAND_TYPE_ESSEG
, "es" },
2289 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2293 pt (i386_operand_type t
)
2296 i386_operand_type a
;
2298 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2300 a
= operand_type_and (t
, type_names
[j
].mask
);
2301 if (!UINTS_ALL_ZERO (a
))
2302 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2307 #endif /* DEBUG386 */
2309 static bfd_reloc_code_real_type
2310 reloc (unsigned int size
,
2313 bfd_reloc_code_real_type other
)
2315 if (other
!= NO_RELOC
)
2317 reloc_howto_type
*reloc
;
2322 case BFD_RELOC_X86_64_GOT32
:
2323 return BFD_RELOC_X86_64_GOT64
;
2325 case BFD_RELOC_X86_64_PLTOFF64
:
2326 return BFD_RELOC_X86_64_PLTOFF64
;
2328 case BFD_RELOC_X86_64_GOTPC32
:
2329 other
= BFD_RELOC_X86_64_GOTPC64
;
2331 case BFD_RELOC_X86_64_GOTPCREL
:
2332 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2334 case BFD_RELOC_X86_64_TPOFF32
:
2335 other
= BFD_RELOC_X86_64_TPOFF64
;
2337 case BFD_RELOC_X86_64_DTPOFF32
:
2338 other
= BFD_RELOC_X86_64_DTPOFF64
;
2344 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2345 if (size
== 4 && flag_code
!= CODE_64BIT
)
2348 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2350 as_bad (_("unknown relocation (%u)"), other
);
2351 else if (size
!= bfd_get_reloc_size (reloc
))
2352 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2353 bfd_get_reloc_size (reloc
),
2355 else if (pcrel
&& !reloc
->pc_relative
)
2356 as_bad (_("non-pc-relative relocation for pc-relative field"));
2357 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2359 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2361 as_bad (_("relocated field and relocation type differ in signedness"));
2370 as_bad (_("there are no unsigned pc-relative relocations"));
2373 case 1: return BFD_RELOC_8_PCREL
;
2374 case 2: return BFD_RELOC_16_PCREL
;
2375 case 4: return BFD_RELOC_32_PCREL
;
2376 case 8: return BFD_RELOC_64_PCREL
;
2378 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2385 case 4: return BFD_RELOC_X86_64_32S
;
2390 case 1: return BFD_RELOC_8
;
2391 case 2: return BFD_RELOC_16
;
2392 case 4: return BFD_RELOC_32
;
2393 case 8: return BFD_RELOC_64
;
2395 as_bad (_("cannot do %s %u byte relocation"),
2396 sign
> 0 ? "signed" : "unsigned", size
);
2400 return BFD_RELOC_NONE
;
2403 /* Here we decide which fixups can be adjusted to make them relative to
2404 the beginning of the section instead of the symbol. Basically we need
2405 to make sure that the dynamic relocations are done correctly, so in
2406 some cases we force the original symbol to be used. */
2409 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2415 /* Don't adjust pc-relative references to merge sections in 64-bit
2417 if (use_rela_relocations
2418 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2422 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2423 and changed later by validate_fix. */
2424 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2425 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2428 /* adjust_reloc_syms doesn't know about the GOT. */
2429 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2430 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2431 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2432 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2433 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2434 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2435 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2436 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2437 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2438 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2439 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2440 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2441 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2442 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2443 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2444 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2445 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2446 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2447 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2448 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2449 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2455 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2456 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2463 intel_float_operand (const char *mnemonic
)
2465 /* Note that the value returned is meaningful only for opcodes with (memory)
2466 operands, hence the code here is free to improperly handle opcodes that
2467 have no operands (for better performance and smaller code). */
2469 if (mnemonic
[0] != 'f')
2470 return 0; /* non-math */
2472 switch (mnemonic
[1])
2474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2475 the fs segment override prefix not currently handled because no
2476 call path can make opcodes without operands get here */
2478 return 2 /* integer op */;
2480 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2481 return 3; /* fldcw/fldenv */
2484 if (mnemonic
[2] != 'o' /* fnop */)
2485 return 3; /* non-waiting control op */
2488 if (mnemonic
[2] == 's')
2489 return 3; /* frstor/frstpm */
2492 if (mnemonic
[2] == 'a')
2493 return 3; /* fsave */
2494 if (mnemonic
[2] == 't')
2496 switch (mnemonic
[3])
2498 case 'c': /* fstcw */
2499 case 'd': /* fstdw */
2500 case 'e': /* fstenv */
2501 case 's': /* fsts[gw] */
2507 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2508 return 0; /* fxsave/fxrstor are not really math ops */
2515 /* Build the VEX prefix. */
2518 build_vex_prefix (void)
2520 unsigned int register_specifier
;
2521 unsigned int implied_prefix
;
2522 unsigned int vector_length
;
2524 /* Check register specifier. */
2525 if (i
.vex
.register_specifier
)
2527 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2528 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2529 register_specifier
+= 8;
2530 register_specifier
= ~register_specifier
& 0xf;
2533 register_specifier
= 0xf;
2535 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2537 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2542 case DATA_PREFIX_OPCODE
:
2545 case REPE_PREFIX_OPCODE
:
2548 case REPNE_PREFIX_OPCODE
:
2555 /* Use 2-byte VEX prefix if possible. */
2556 if (i
.tm
.opcode_modifier
.vex0f
2557 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2559 /* 2-byte VEX prefix. */
2563 i
.vex
.bytes
[0] = 0xc5;
2565 /* Check the REX.R bit. */
2566 r
= (i
.rex
& REX_R
) ? 0 : 1;
2567 i
.vex
.bytes
[1] = (r
<< 7
2568 | register_specifier
<< 3
2569 | vector_length
<< 2
2574 /* 3-byte VEX prefix. */
2577 if (i
.tm
.opcode_modifier
.vex0f
)
2579 else if (i
.tm
.opcode_modifier
.vex0f38
)
2581 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2587 i
.vex
.bytes
[0] = 0xc4;
2589 /* The high 3 bits of the second VEX byte are 1's compliment
2590 of RXB bits from REX. */
2591 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2593 /* Check the REX.W bit. */
2594 w
= (i
.rex
& REX_W
) ? 1 : 0;
2595 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2600 if (i
.tm
.opcode_modifier
.vexw1
)
2604 i
.vex
.bytes
[2] = (w
<< 7
2605 | register_specifier
<< 3
2606 | vector_length
<< 2
2612 process_immext (void)
2616 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2618 /* SSE3 Instructions have the fixed operands with an opcode
2619 suffix which is coded in the same place as an 8-bit immediate
2620 field would be. Here we check those operands and remove them
2624 for (x
= 0; x
< i
.operands
; x
++)
2625 if (i
.op
[x
].regs
->reg_num
!= x
)
2626 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2627 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2633 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2634 which is coded in the same place as an 8-bit immediate field
2635 would be. Here we fake an 8-bit immediate operand from the
2636 opcode suffix stored in tm.extension_opcode.
2638 SSE5 and AVX instructions also use this encoding, for some of
2639 3 argument instructions. */
2641 assert (i
.imm_operands
== 0
2643 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2645 || (i
.tm
.opcode_modifier
.vex
2646 && i
.operands
<= 4)));
2648 exp
= &im_expressions
[i
.imm_operands
++];
2649 i
.op
[i
.operands
].imms
= exp
;
2650 i
.types
[i
.operands
] = imm8
;
2652 exp
->X_op
= O_constant
;
2653 exp
->X_add_number
= i
.tm
.extension_opcode
;
2654 i
.tm
.extension_opcode
= None
;
2657 /* This is the guts of the machine-dependent assembler. LINE points to a
2658 machine dependent instruction. This function is supposed to emit
2659 the frags/bytes it assembles to. */
2662 md_assemble (char *line
)
2665 char mnemonic
[MAX_MNEM_SIZE
];
2667 /* Initialize globals. */
2668 memset (&i
, '\0', sizeof (i
));
2669 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2670 i
.reloc
[j
] = NO_RELOC
;
2671 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2672 memset (im_expressions
, '\0', sizeof (im_expressions
));
2673 save_stack_p
= save_stack
;
2675 /* First parse an instruction mnemonic & call i386_operand for the operands.
2676 We assume that the scrubber has arranged it so that line[0] is the valid
2677 start of a (possibly prefixed) mnemonic. */
2679 line
= parse_insn (line
, mnemonic
);
2683 line
= parse_operands (line
, mnemonic
);
2687 /* Now we've parsed the mnemonic into a set of templates, and have the
2688 operands at hand. */
2690 /* All intel opcodes have reversed operands except for "bound" and
2691 "enter". We also don't reverse intersegment "jmp" and "call"
2692 instructions with 2 immediate operands so that the immediate segment
2693 precedes the offset, as it does when in AT&T mode. */
2696 && (strcmp (mnemonic
, "bound") != 0)
2697 && (strcmp (mnemonic
, "invlpga") != 0)
2698 && !(operand_type_check (i
.types
[0], imm
)
2699 && operand_type_check (i
.types
[1], imm
)))
2702 /* The order of the immediates should be reversed
2703 for 2 immediates extrq and insertq instructions */
2704 if (i
.imm_operands
== 2
2705 && (strcmp (mnemonic
, "extrq") == 0
2706 || strcmp (mnemonic
, "insertq") == 0))
2707 swap_2_operands (0, 1);
2712 /* Don't optimize displacement for movabs since it only takes 64bit
2715 && (flag_code
!= CODE_64BIT
2716 || strcmp (mnemonic
, "movabs") != 0))
2719 /* Next, we find a template that matches the given insn,
2720 making sure the overlap of the given operands types is consistent
2721 with the template operand types. */
2723 if (!match_template ())
2726 if (sse_check
!= sse_check_none
2727 && !i
.tm
.opcode_modifier
.noavx
2728 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2729 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2730 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2731 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2732 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2733 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2735 (sse_check
== sse_check_warning
2737 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2740 /* Zap movzx and movsx suffix. The suffix has been set from
2741 "word ptr" or "byte ptr" on the source operand in Intel syntax
2742 or extracted from mnemonic in AT&T syntax. But we'll use
2743 the destination register to choose the suffix for encoding. */
2744 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2746 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2747 there is no suffix, the default will be byte extension. */
2748 if (i
.reg_operands
!= 2
2751 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2756 if (i
.tm
.opcode_modifier
.fwait
)
2757 if (!add_prefix (FWAIT_OPCODE
))
2760 /* Check string instruction segment overrides. */
2761 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2763 if (!check_string ())
2765 i
.disp_operands
= 0;
2768 if (!process_suffix ())
2771 /* Make still unresolved immediate matches conform to size of immediate
2772 given in i.suffix. */
2773 if (!finalize_imm ())
2776 if (i
.types
[0].bitfield
.imm1
)
2777 i
.imm_operands
= 0; /* kludge for shift insns. */
2779 for (j
= 0; j
< 3; j
++)
2780 if (i
.types
[j
].bitfield
.inoutportreg
2781 || i
.types
[j
].bitfield
.shiftcount
2782 || i
.types
[j
].bitfield
.acc
2783 || i
.types
[j
].bitfield
.floatacc
)
2786 /* ImmExt should be processed after SSE2AVX. */
2787 if (!i
.tm
.opcode_modifier
.sse2avx
2788 && i
.tm
.opcode_modifier
.immext
)
2791 /* For insns with operands there are more diddles to do to the opcode. */
2794 if (!process_operands ())
2797 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2799 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2800 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2803 if (i
.tm
.opcode_modifier
.vex
)
2804 build_vex_prefix ();
2806 /* Handle conversion of 'int $3' --> special int3 insn. */
2807 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2809 i
.tm
.base_opcode
= INT3_OPCODE
;
2813 if ((i
.tm
.opcode_modifier
.jump
2814 || i
.tm
.opcode_modifier
.jumpbyte
2815 || i
.tm
.opcode_modifier
.jumpdword
)
2816 && i
.op
[0].disps
->X_op
== O_constant
)
2818 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2819 the absolute address given by the constant. Since ix86 jumps and
2820 calls are pc relative, we need to generate a reloc. */
2821 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2822 i
.op
[0].disps
->X_op
= O_symbol
;
2825 if (i
.tm
.opcode_modifier
.rex64
)
2828 /* For 8 bit registers we need an empty rex prefix. Also if the
2829 instruction already has a prefix, we need to convert old
2830 registers to new ones. */
2832 if ((i
.types
[0].bitfield
.reg8
2833 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2834 || (i
.types
[1].bitfield
.reg8
2835 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2836 || ((i
.types
[0].bitfield
.reg8
2837 || i
.types
[1].bitfield
.reg8
)
2842 i
.rex
|= REX_OPCODE
;
2843 for (x
= 0; x
< 2; x
++)
2845 /* Look for 8 bit operand that uses old registers. */
2846 if (i
.types
[x
].bitfield
.reg8
2847 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2849 /* In case it is "hi" register, give up. */
2850 if (i
.op
[x
].regs
->reg_num
> 3)
2851 as_bad (_("can't encode register '%s%s' in an "
2852 "instruction requiring REX prefix."),
2853 register_prefix
, i
.op
[x
].regs
->reg_name
);
2855 /* Otherwise it is equivalent to the extended register.
2856 Since the encoding doesn't change this is merely
2857 cosmetic cleanup for debug output. */
2859 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2864 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2866 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2871 else if (i
.rex
!= 0)
2872 add_prefix (REX_OPCODE
| i
.rex
);
2874 /* We are ready to output the insn. */
2879 parse_insn (char *line
, char *mnemonic
)
2882 char *token_start
= l
;
2887 /* Non-zero if we found a prefix only acceptable with string insns. */
2888 const char *expecting_string_instruction
= NULL
;
2893 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2896 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2898 as_bad (_("no such instruction: `%s'"), token_start
);
2903 if (!is_space_char (*l
)
2904 && *l
!= END_OF_INSN
2906 || (*l
!= PREFIX_SEPARATOR
2909 as_bad (_("invalid character %s in mnemonic"),
2910 output_invalid (*l
));
2913 if (token_start
== l
)
2915 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2916 as_bad (_("expecting prefix; got nothing"));
2918 as_bad (_("expecting mnemonic; got nothing"));
2922 /* Look up instruction (or prefix) via hash table. */
2923 current_templates
= hash_find (op_hash
, mnemonic
);
2925 if (*l
!= END_OF_INSN
2926 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2927 && current_templates
2928 && current_templates
->start
->opcode_modifier
.isprefix
)
2930 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2932 as_bad ((flag_code
!= CODE_64BIT
2933 ? _("`%s' is only supported in 64-bit mode")
2934 : _("`%s' is not supported in 64-bit mode")),
2935 current_templates
->start
->name
);
2938 /* If we are in 16-bit mode, do not allow addr16 or data16.
2939 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2940 if ((current_templates
->start
->opcode_modifier
.size16
2941 || current_templates
->start
->opcode_modifier
.size32
)
2942 && flag_code
!= CODE_64BIT
2943 && (current_templates
->start
->opcode_modifier
.size32
2944 ^ (flag_code
== CODE_16BIT
)))
2946 as_bad (_("redundant %s prefix"),
2947 current_templates
->start
->name
);
2950 /* Add prefix, checking for repeated prefixes. */
2951 switch (add_prefix (current_templates
->start
->base_opcode
))
2956 expecting_string_instruction
= current_templates
->start
->name
;
2959 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2966 if (!current_templates
)
2968 /* See if we can get a match by trimming off a suffix. */
2971 case WORD_MNEM_SUFFIX
:
2972 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2973 i
.suffix
= SHORT_MNEM_SUFFIX
;
2975 case BYTE_MNEM_SUFFIX
:
2976 case QWORD_MNEM_SUFFIX
:
2977 i
.suffix
= mnem_p
[-1];
2979 current_templates
= hash_find (op_hash
, mnemonic
);
2981 case SHORT_MNEM_SUFFIX
:
2982 case LONG_MNEM_SUFFIX
:
2985 i
.suffix
= mnem_p
[-1];
2987 current_templates
= hash_find (op_hash
, mnemonic
);
2995 if (intel_float_operand (mnemonic
) == 1)
2996 i
.suffix
= SHORT_MNEM_SUFFIX
;
2998 i
.suffix
= LONG_MNEM_SUFFIX
;
3000 current_templates
= hash_find (op_hash
, mnemonic
);
3004 if (!current_templates
)
3006 as_bad (_("no such instruction: `%s'"), token_start
);
3011 if (current_templates
->start
->opcode_modifier
.jump
3012 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3014 /* Check for a branch hint. We allow ",pt" and ",pn" for
3015 predict taken and predict not taken respectively.
3016 I'm not sure that branch hints actually do anything on loop
3017 and jcxz insns (JumpByte) for current Pentium4 chips. They
3018 may work in the future and it doesn't hurt to accept them
3020 if (l
[0] == ',' && l
[1] == 'p')
3024 if (!add_prefix (DS_PREFIX_OPCODE
))
3028 else if (l
[2] == 'n')
3030 if (!add_prefix (CS_PREFIX_OPCODE
))
3036 /* Any other comma loses. */
3039 as_bad (_("invalid character %s in mnemonic"),
3040 output_invalid (*l
));
3044 /* Check if instruction is supported on specified architecture. */
3046 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3048 supported
|= cpu_flags_match (t
);
3049 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3053 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3055 as_bad (flag_code
== CODE_64BIT
3056 ? _("`%s' is not supported in 64-bit mode")
3057 : _("`%s' is only supported in 64-bit mode"),
3058 current_templates
->start
->name
);
3061 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3063 as_bad (_("`%s' is not supported on `%s%s'"),
3064 current_templates
->start
->name
, cpu_arch_name
,
3065 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3070 if (!cpu_arch_flags
.bitfield
.cpui386
3071 && (flag_code
!= CODE_16BIT
))
3073 as_warn (_("use .code16 to ensure correct addressing mode"));
3076 /* Check for rep/repne without a string instruction. */
3077 if (expecting_string_instruction
)
3079 static templates override
;
3081 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3082 if (t
->opcode_modifier
.isstring
)
3084 if (t
>= current_templates
->end
)
3086 as_bad (_("expecting string instruction after `%s'"),
3087 expecting_string_instruction
);
3090 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3091 if (!t
->opcode_modifier
.isstring
)
3094 current_templates
= &override
;
3101 parse_operands (char *l
, const char *mnemonic
)
3105 /* 1 if operand is pending after ','. */
3106 unsigned int expecting_operand
= 0;
3108 /* Non-zero if operand parens not balanced. */
3109 unsigned int paren_not_balanced
;
3111 while (*l
!= END_OF_INSN
)
3113 /* Skip optional white space before operand. */
3114 if (is_space_char (*l
))
3116 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3118 as_bad (_("invalid character %s before operand %d"),
3119 output_invalid (*l
),
3123 token_start
= l
; /* after white space */
3124 paren_not_balanced
= 0;
3125 while (paren_not_balanced
|| *l
!= ',')
3127 if (*l
== END_OF_INSN
)
3129 if (paren_not_balanced
)
3132 as_bad (_("unbalanced parenthesis in operand %d."),
3135 as_bad (_("unbalanced brackets in operand %d."),
3140 break; /* we are done */
3142 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3144 as_bad (_("invalid character %s in operand %d"),
3145 output_invalid (*l
),
3152 ++paren_not_balanced
;
3154 --paren_not_balanced
;
3159 ++paren_not_balanced
;
3161 --paren_not_balanced
;
3165 if (l
!= token_start
)
3166 { /* Yes, we've read in another operand. */
3167 unsigned int operand_ok
;
3168 this_operand
= i
.operands
++;
3169 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3170 if (i
.operands
> MAX_OPERANDS
)
3172 as_bad (_("spurious operands; (%d operands/instruction max)"),
3176 /* Now parse operand adding info to 'i' as we go along. */
3177 END_STRING_AND_SAVE (l
);
3181 i386_intel_operand (token_start
,
3182 intel_float_operand (mnemonic
));
3184 operand_ok
= i386_att_operand (token_start
);
3186 RESTORE_END_STRING (l
);
3192 if (expecting_operand
)
3194 expecting_operand_after_comma
:
3195 as_bad (_("expecting operand after ','; got nothing"));
3200 as_bad (_("expecting operand before ','; got nothing"));
3205 /* Now *l must be either ',' or END_OF_INSN. */
3208 if (*++l
== END_OF_INSN
)
3210 /* Just skip it, if it's \n complain. */
3211 goto expecting_operand_after_comma
;
3213 expecting_operand
= 1;
3220 swap_2_operands (int xchg1
, int xchg2
)
3222 union i386_op temp_op
;
3223 i386_operand_type temp_type
;
3224 enum bfd_reloc_code_real temp_reloc
;
3226 temp_type
= i
.types
[xchg2
];
3227 i
.types
[xchg2
] = i
.types
[xchg1
];
3228 i
.types
[xchg1
] = temp_type
;
3229 temp_op
= i
.op
[xchg2
];
3230 i
.op
[xchg2
] = i
.op
[xchg1
];
3231 i
.op
[xchg1
] = temp_op
;
3232 temp_reloc
= i
.reloc
[xchg2
];
3233 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3234 i
.reloc
[xchg1
] = temp_reloc
;
3238 swap_operands (void)
3244 swap_2_operands (1, i
.operands
- 2);
3247 swap_2_operands (0, i
.operands
- 1);
3253 if (i
.mem_operands
== 2)
3255 const seg_entry
*temp_seg
;
3256 temp_seg
= i
.seg
[0];
3257 i
.seg
[0] = i
.seg
[1];
3258 i
.seg
[1] = temp_seg
;
3262 /* Try to ensure constant immediates are represented in the smallest
3267 char guess_suffix
= 0;
3271 guess_suffix
= i
.suffix
;
3272 else if (i
.reg_operands
)
3274 /* Figure out a suffix from the last register operand specified.
3275 We can't do this properly yet, ie. excluding InOutPortReg,
3276 but the following works for instructions with immediates.
3277 In any case, we can't set i.suffix yet. */
3278 for (op
= i
.operands
; --op
>= 0;)
3279 if (i
.types
[op
].bitfield
.reg8
)
3281 guess_suffix
= BYTE_MNEM_SUFFIX
;
3284 else if (i
.types
[op
].bitfield
.reg16
)
3286 guess_suffix
= WORD_MNEM_SUFFIX
;
3289 else if (i
.types
[op
].bitfield
.reg32
)
3291 guess_suffix
= LONG_MNEM_SUFFIX
;
3294 else if (i
.types
[op
].bitfield
.reg64
)
3296 guess_suffix
= QWORD_MNEM_SUFFIX
;
3300 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3301 guess_suffix
= WORD_MNEM_SUFFIX
;
3303 for (op
= i
.operands
; --op
>= 0;)
3304 if (operand_type_check (i
.types
[op
], imm
))
3306 switch (i
.op
[op
].imms
->X_op
)
3309 /* If a suffix is given, this operand may be shortened. */
3310 switch (guess_suffix
)
3312 case LONG_MNEM_SUFFIX
:
3313 i
.types
[op
].bitfield
.imm32
= 1;
3314 i
.types
[op
].bitfield
.imm64
= 1;
3316 case WORD_MNEM_SUFFIX
:
3317 i
.types
[op
].bitfield
.imm16
= 1;
3318 i
.types
[op
].bitfield
.imm32
= 1;
3319 i
.types
[op
].bitfield
.imm32s
= 1;
3320 i
.types
[op
].bitfield
.imm64
= 1;
3322 case BYTE_MNEM_SUFFIX
:
3323 i
.types
[op
].bitfield
.imm8
= 1;
3324 i
.types
[op
].bitfield
.imm8s
= 1;
3325 i
.types
[op
].bitfield
.imm16
= 1;
3326 i
.types
[op
].bitfield
.imm32
= 1;
3327 i
.types
[op
].bitfield
.imm32s
= 1;
3328 i
.types
[op
].bitfield
.imm64
= 1;
3332 /* If this operand is at most 16 bits, convert it
3333 to a signed 16 bit number before trying to see
3334 whether it will fit in an even smaller size.
3335 This allows a 16-bit operand such as $0xffe0 to
3336 be recognised as within Imm8S range. */
3337 if ((i
.types
[op
].bitfield
.imm16
)
3338 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3340 i
.op
[op
].imms
->X_add_number
=
3341 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3343 if ((i
.types
[op
].bitfield
.imm32
)
3344 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3347 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3348 ^ ((offsetT
) 1 << 31))
3349 - ((offsetT
) 1 << 31));
3352 = operand_type_or (i
.types
[op
],
3353 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3355 /* We must avoid matching of Imm32 templates when 64bit
3356 only immediate is available. */
3357 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3358 i
.types
[op
].bitfield
.imm32
= 0;
3365 /* Symbols and expressions. */
3367 /* Convert symbolic operand to proper sizes for matching, but don't
3368 prevent matching a set of insns that only supports sizes other
3369 than those matching the insn suffix. */
3371 i386_operand_type mask
, allowed
;
3374 operand_type_set (&mask
, 0);
3375 operand_type_set (&allowed
, 0);
3377 for (t
= current_templates
->start
;
3378 t
< current_templates
->end
;
3380 allowed
= operand_type_or (allowed
,
3381 t
->operand_types
[op
]);
3382 switch (guess_suffix
)
3384 case QWORD_MNEM_SUFFIX
:
3385 mask
.bitfield
.imm64
= 1;
3386 mask
.bitfield
.imm32s
= 1;
3388 case LONG_MNEM_SUFFIX
:
3389 mask
.bitfield
.imm32
= 1;
3391 case WORD_MNEM_SUFFIX
:
3392 mask
.bitfield
.imm16
= 1;
3394 case BYTE_MNEM_SUFFIX
:
3395 mask
.bitfield
.imm8
= 1;
3400 allowed
= operand_type_and (mask
, allowed
);
3401 if (!operand_type_all_zero (&allowed
))
3402 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3409 /* Try to use the smallest displacement type too. */
3411 optimize_disp (void)
3415 for (op
= i
.operands
; --op
>= 0;)
3416 if (operand_type_check (i
.types
[op
], disp
))
3418 if (i
.op
[op
].disps
->X_op
== O_constant
)
3420 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3422 if (i
.types
[op
].bitfield
.disp16
3423 && (disp
& ~(offsetT
) 0xffff) == 0)
3425 /* If this operand is at most 16 bits, convert
3426 to a signed 16 bit number and don't use 64bit
3428 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3429 i
.types
[op
].bitfield
.disp64
= 0;
3431 if (i
.types
[op
].bitfield
.disp32
3432 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3434 /* If this operand is at most 32 bits, convert
3435 to a signed 32 bit number and don't use 64bit
3437 disp
&= (((offsetT
) 2 << 31) - 1);
3438 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3439 i
.types
[op
].bitfield
.disp64
= 0;
3441 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3443 i
.types
[op
].bitfield
.disp8
= 0;
3444 i
.types
[op
].bitfield
.disp16
= 0;
3445 i
.types
[op
].bitfield
.disp32
= 0;
3446 i
.types
[op
].bitfield
.disp32s
= 0;
3447 i
.types
[op
].bitfield
.disp64
= 0;
3451 else if (flag_code
== CODE_64BIT
)
3453 if (fits_in_signed_long (disp
))
3455 i
.types
[op
].bitfield
.disp64
= 0;
3456 i
.types
[op
].bitfield
.disp32s
= 1;
3458 if (fits_in_unsigned_long (disp
))
3459 i
.types
[op
].bitfield
.disp32
= 1;
3461 if ((i
.types
[op
].bitfield
.disp32
3462 || i
.types
[op
].bitfield
.disp32s
3463 || i
.types
[op
].bitfield
.disp16
)
3464 && fits_in_signed_byte (disp
))
3465 i
.types
[op
].bitfield
.disp8
= 1;
3467 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3468 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3470 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3471 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3472 i
.types
[op
].bitfield
.disp8
= 0;
3473 i
.types
[op
].bitfield
.disp16
= 0;
3474 i
.types
[op
].bitfield
.disp32
= 0;
3475 i
.types
[op
].bitfield
.disp32s
= 0;
3476 i
.types
[op
].bitfield
.disp64
= 0;
3479 /* We only support 64bit displacement on constants. */
3480 i
.types
[op
].bitfield
.disp64
= 0;
3484 /* Check if operands are valid for the instrucrtion. Update VEX
3488 VEX_check_operands (const template *t
)
3490 if (!t
->opcode_modifier
.vex
)
3493 /* Only check VEX_Imm4, which must be the first operand. */
3494 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3496 if (i
.op
[0].imms
->X_op
!= O_constant
3497 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3500 /* Turn off Imm8 so that update_imm won't complain. */
3501 i
.types
[0] = vex_imm4
;
3508 match_template (void)
3510 /* Points to template once we've found it. */
3512 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3513 i386_operand_type overlap4
;
3514 unsigned int found_reverse_match
;
3515 i386_opcode_modifier suffix_check
;
3516 i386_operand_type operand_types
[MAX_OPERANDS
];
3517 int addr_prefix_disp
;
3519 unsigned int found_cpu_match
;
3520 unsigned int check_register
;
3522 #if MAX_OPERANDS != 5
3523 # error "MAX_OPERANDS must be 5."
3526 found_reverse_match
= 0;
3527 addr_prefix_disp
= -1;
3529 memset (&suffix_check
, 0, sizeof (suffix_check
));
3530 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3531 suffix_check
.no_bsuf
= 1;
3532 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3533 suffix_check
.no_wsuf
= 1;
3534 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3535 suffix_check
.no_ssuf
= 1;
3536 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3537 suffix_check
.no_lsuf
= 1;
3538 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3539 suffix_check
.no_qsuf
= 1;
3540 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3541 suffix_check
.no_ldsuf
= 1;
3543 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3545 addr_prefix_disp
= -1;
3547 /* Must have right number of operands. */
3548 if (i
.operands
!= t
->operands
)
3551 /* Check processor support. */
3552 found_cpu_match
= (cpu_flags_match (t
)
3553 == CPU_FLAGS_PERFECT_MATCH
);
3554 if (!found_cpu_match
)
3557 /* Check old gcc support. */
3558 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3561 /* Check AT&T mnemonic. */
3562 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3565 /* Check AT&T syntax Intel syntax. */
3566 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3567 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3570 /* Check the suffix, except for some instructions in intel mode. */
3571 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3572 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3573 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3574 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3575 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3576 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3577 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3580 if (!operand_size_match (t
))
3583 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3584 operand_types
[j
] = t
->operand_types
[j
];
3586 /* In general, don't allow 64-bit operands in 32-bit mode. */
3587 if (i
.suffix
== QWORD_MNEM_SUFFIX
3588 && flag_code
!= CODE_64BIT
3590 ? (!t
->opcode_modifier
.ignoresize
3591 && !intel_float_operand (t
->name
))
3592 : intel_float_operand (t
->name
) != 2)
3593 && ((!operand_types
[0].bitfield
.regmmx
3594 && !operand_types
[0].bitfield
.regxmm
3595 && !operand_types
[0].bitfield
.regymm
)
3596 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3597 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3598 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3599 && (t
->base_opcode
!= 0x0fc7
3600 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3603 /* In general, don't allow 32-bit operands on pre-386. */
3604 else if (i
.suffix
== LONG_MNEM_SUFFIX
3605 && !cpu_arch_flags
.bitfield
.cpui386
3607 ? (!t
->opcode_modifier
.ignoresize
3608 && !intel_float_operand (t
->name
))
3609 : intel_float_operand (t
->name
) != 2)
3610 && ((!operand_types
[0].bitfield
.regmmx
3611 && !operand_types
[0].bitfield
.regxmm
)
3612 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3613 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3616 /* Do not verify operands when there are none. */
3620 /* We've found a match; break out of loop. */
3624 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3625 into Disp32/Disp16/Disp32 operand. */
3626 if (i
.prefix
[ADDR_PREFIX
] != 0)
3628 /* There should be only one Disp operand. */
3632 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3634 if (operand_types
[j
].bitfield
.disp16
)
3636 addr_prefix_disp
= j
;
3637 operand_types
[j
].bitfield
.disp32
= 1;
3638 operand_types
[j
].bitfield
.disp16
= 0;
3644 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3646 if (operand_types
[j
].bitfield
.disp32
)
3648 addr_prefix_disp
= j
;
3649 operand_types
[j
].bitfield
.disp32
= 0;
3650 operand_types
[j
].bitfield
.disp16
= 1;
3656 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3658 if (operand_types
[j
].bitfield
.disp64
)
3660 addr_prefix_disp
= j
;
3661 operand_types
[j
].bitfield
.disp64
= 0;
3662 operand_types
[j
].bitfield
.disp32
= 1;
3670 /* We check register size only if size of operands can be
3671 encoded the canonical way. */
3672 check_register
= t
->opcode_modifier
.w
;
3673 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3674 switch (t
->operands
)
3677 if (!operand_type_match (overlap0
, i
.types
[0]))
3681 /* xchg %eax, %eax is a special case. It is an aliase for nop
3682 only in 32bit mode and we can use opcode 0x90. In 64bit
3683 mode, we can't use 0x90 for xchg %eax, %eax since it should
3684 zero-extend %eax to %rax. */
3685 if (flag_code
== CODE_64BIT
3686 && t
->base_opcode
== 0x90
3687 && operand_type_equal (&i
.types
[0], &acc32
)
3688 && operand_type_equal (&i
.types
[1], &acc32
))
3693 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3694 if (!operand_type_match (overlap0
, i
.types
[0])
3695 || !operand_type_match (overlap1
, i
.types
[1])
3697 && !operand_type_register_match (overlap0
, i
.types
[0],
3699 overlap1
, i
.types
[1],
3702 /* Check if other direction is valid ... */
3703 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3706 /* Try reversing direction of operands. */
3707 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3708 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3709 if (!operand_type_match (overlap0
, i
.types
[0])
3710 || !operand_type_match (overlap1
, i
.types
[1])
3712 && !operand_type_register_match (overlap0
,
3719 /* Does not match either direction. */
3722 /* found_reverse_match holds which of D or FloatDR
3724 if (t
->opcode_modifier
.d
)
3725 found_reverse_match
= Opcode_D
;
3726 else if (t
->opcode_modifier
.floatd
)
3727 found_reverse_match
= Opcode_FloatD
;
3729 found_reverse_match
= 0;
3730 if (t
->opcode_modifier
.floatr
)
3731 found_reverse_match
|= Opcode_FloatR
;
3735 /* Found a forward 2 operand match here. */
3736 switch (t
->operands
)
3739 overlap4
= operand_type_and (i
.types
[4],
3742 overlap3
= operand_type_and (i
.types
[3],
3745 overlap2
= operand_type_and (i
.types
[2],
3750 switch (t
->operands
)
3753 if (!operand_type_match (overlap4
, i
.types
[4])
3754 || !operand_type_register_match (overlap3
,
3762 if (!operand_type_match (overlap3
, i
.types
[3])
3764 && !operand_type_register_match (overlap2
,
3772 /* Here we make use of the fact that there are no
3773 reverse match 3 operand instructions, and all 3
3774 operand instructions only need to be checked for
3775 register consistency between operands 2 and 3. */
3776 if (!operand_type_match (overlap2
, i
.types
[2])
3778 && !operand_type_register_match (overlap1
,
3788 /* Found either forward/reverse 2, 3 or 4 operand match here:
3789 slip through to break. */
3791 if (!found_cpu_match
)
3793 found_reverse_match
= 0;
3797 /* Check if VEX operands are valid. */
3798 if (VEX_check_operands (t
))
3801 /* We've found a match; break out of loop. */
3805 if (t
== current_templates
->end
)
3807 /* We found no match. */
3809 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3810 current_templates
->start
->name
);
3812 as_bad (_("suffix or operands invalid for `%s'"),
3813 current_templates
->start
->name
);
3817 if (!quiet_warnings
)
3820 && (i
.types
[0].bitfield
.jumpabsolute
3821 != operand_types
[0].bitfield
.jumpabsolute
))
3823 as_warn (_("indirect %s without `*'"), t
->name
);
3826 if (t
->opcode_modifier
.isprefix
3827 && t
->opcode_modifier
.ignoresize
)
3829 /* Warn them that a data or address size prefix doesn't
3830 affect assembly of the next line of code. */
3831 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3835 /* Copy the template we found. */
3838 if (addr_prefix_disp
!= -1)
3839 i
.tm
.operand_types
[addr_prefix_disp
]
3840 = operand_types
[addr_prefix_disp
];
3842 if (found_reverse_match
)
3844 /* If we found a reverse match we must alter the opcode
3845 direction bit. found_reverse_match holds bits to change
3846 (different for int & float insns). */
3848 i
.tm
.base_opcode
^= found_reverse_match
;
3850 i
.tm
.operand_types
[0] = operand_types
[1];
3851 i
.tm
.operand_types
[1] = operand_types
[0];
3860 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3861 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3863 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3865 as_bad (_("`%s' operand %d must use `%ses' segment"),
3871 /* There's only ever one segment override allowed per instruction.
3872 This instruction possibly has a legal segment override on the
3873 second operand, so copy the segment to where non-string
3874 instructions store it, allowing common code. */
3875 i
.seg
[0] = i
.seg
[1];
3877 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3879 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3881 as_bad (_("`%s' operand %d must use `%ses' segment"),
3892 process_suffix (void)
3894 /* If matched instruction specifies an explicit instruction mnemonic
3896 if (i
.tm
.opcode_modifier
.size16
)
3897 i
.suffix
= WORD_MNEM_SUFFIX
;
3898 else if (i
.tm
.opcode_modifier
.size32
)
3899 i
.suffix
= LONG_MNEM_SUFFIX
;
3900 else if (i
.tm
.opcode_modifier
.size64
)
3901 i
.suffix
= QWORD_MNEM_SUFFIX
;
3902 else if (i
.reg_operands
)
3904 /* If there's no instruction mnemonic suffix we try to invent one
3905 based on register operands. */
3908 /* We take i.suffix from the last register operand specified,
3909 Destination register type is more significant than source
3910 register type. crc32 in SSE4.2 prefers source register
3912 if (i
.tm
.base_opcode
== 0xf20f38f1)
3914 if (i
.types
[0].bitfield
.reg16
)
3915 i
.suffix
= WORD_MNEM_SUFFIX
;
3916 else if (i
.types
[0].bitfield
.reg32
)
3917 i
.suffix
= LONG_MNEM_SUFFIX
;
3918 else if (i
.types
[0].bitfield
.reg64
)
3919 i
.suffix
= QWORD_MNEM_SUFFIX
;
3921 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3923 if (i
.types
[0].bitfield
.reg8
)
3924 i
.suffix
= BYTE_MNEM_SUFFIX
;
3931 if (i
.tm
.base_opcode
== 0xf20f38f1
3932 || i
.tm
.base_opcode
== 0xf20f38f0)
3934 /* We have to know the operand size for crc32. */
3935 as_bad (_("ambiguous memory operand size for `%s`"),
3940 for (op
= i
.operands
; --op
>= 0;)
3941 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3943 if (i
.types
[op
].bitfield
.reg8
)
3945 i
.suffix
= BYTE_MNEM_SUFFIX
;
3948 else if (i
.types
[op
].bitfield
.reg16
)
3950 i
.suffix
= WORD_MNEM_SUFFIX
;
3953 else if (i
.types
[op
].bitfield
.reg32
)
3955 i
.suffix
= LONG_MNEM_SUFFIX
;
3958 else if (i
.types
[op
].bitfield
.reg64
)
3960 i
.suffix
= QWORD_MNEM_SUFFIX
;
3966 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3968 if (!check_byte_reg ())
3971 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3973 if (!check_long_reg ())
3976 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3979 && i
.tm
.opcode_modifier
.ignoresize
3980 && i
.tm
.opcode_modifier
.no_qsuf
)
3982 else if (!check_qword_reg ())
3985 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3987 if (!check_word_reg ())
3990 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
3991 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
3993 /* Skip if the instruction has x/y suffix. match_template
3994 should check if it is a valid suffix. */
3996 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3997 /* Do nothing if the instruction is going to ignore the prefix. */
4002 else if (i
.tm
.opcode_modifier
.defaultsize
4004 /* exclude fldenv/frstor/fsave/fstenv */
4005 && i
.tm
.opcode_modifier
.no_ssuf
)
4007 i
.suffix
= stackop_size
;
4009 else if (intel_syntax
4011 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4012 || i
.tm
.opcode_modifier
.jumpbyte
4013 || i
.tm
.opcode_modifier
.jumpintersegment
4014 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4015 && i
.tm
.extension_opcode
<= 3)))
4020 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4022 i
.suffix
= QWORD_MNEM_SUFFIX
;
4026 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4027 i
.suffix
= LONG_MNEM_SUFFIX
;
4030 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4031 i
.suffix
= WORD_MNEM_SUFFIX
;
4040 if (i
.tm
.opcode_modifier
.w
)
4042 as_bad (_("no instruction mnemonic suffix given and "
4043 "no register operands; can't size instruction"));
4049 unsigned int suffixes
;
4051 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4052 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4054 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4056 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4058 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4060 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4063 /* There are more than suffix matches. */
4064 if (i
.tm
.opcode_modifier
.w
4065 || ((suffixes
& (suffixes
- 1))
4066 && !i
.tm
.opcode_modifier
.defaultsize
4067 && !i
.tm
.opcode_modifier
.ignoresize
))
4069 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4075 /* Change the opcode based on the operand size given by i.suffix;
4076 We don't need to change things for byte insns. */
4079 && i
.suffix
!= BYTE_MNEM_SUFFIX
4080 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4081 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4083 /* It's not a byte, select word/dword operation. */
4084 if (i
.tm
.opcode_modifier
.w
)
4086 if (i
.tm
.opcode_modifier
.shortform
)
4087 i
.tm
.base_opcode
|= 8;
4089 i
.tm
.base_opcode
|= 1;
4092 /* Now select between word & dword operations via the operand
4093 size prefix, except for instructions that will ignore this
4095 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4097 /* The address size override prefix changes the size of the
4099 if ((flag_code
== CODE_32BIT
4100 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4101 || (flag_code
!= CODE_32BIT
4102 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4103 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4106 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4107 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4108 && !i
.tm
.opcode_modifier
.ignoresize
4109 && !i
.tm
.opcode_modifier
.floatmf
4110 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4111 || (flag_code
== CODE_64BIT
4112 && i
.tm
.opcode_modifier
.jumpbyte
)))
4114 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4116 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4117 prefix
= ADDR_PREFIX_OPCODE
;
4119 if (!add_prefix (prefix
))
4123 /* Set mode64 for an operand. */
4124 if (i
.suffix
== QWORD_MNEM_SUFFIX
4125 && flag_code
== CODE_64BIT
4126 && !i
.tm
.opcode_modifier
.norex64
)
4128 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4129 need rex64. cmpxchg8b is also a special case. */
4130 if (! (i
.operands
== 2
4131 && i
.tm
.base_opcode
== 0x90
4132 && i
.tm
.extension_opcode
== None
4133 && operand_type_equal (&i
.types
[0], &acc64
)
4134 && operand_type_equal (&i
.types
[1], &acc64
))
4135 && ! (i
.operands
== 1
4136 && i
.tm
.base_opcode
== 0xfc7
4137 && i
.tm
.extension_opcode
== 1
4138 && !operand_type_check (i
.types
[0], reg
)
4139 && operand_type_check (i
.types
[0], anymem
)))
4143 /* Size floating point instruction. */
4144 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4145 if (i
.tm
.opcode_modifier
.floatmf
)
4146 i
.tm
.base_opcode
^= 4;
4153 check_byte_reg (void)
4157 for (op
= i
.operands
; --op
>= 0;)
4159 /* If this is an eight bit register, it's OK. If it's the 16 or
4160 32 bit version of an eight bit register, we will just use the
4161 low portion, and that's OK too. */
4162 if (i
.types
[op
].bitfield
.reg8
)
4165 /* Don't generate this warning if not needed. */
4166 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4169 /* crc32 doesn't generate this warning. */
4170 if (i
.tm
.base_opcode
== 0xf20f38f0)
4173 if ((i
.types
[op
].bitfield
.reg16
4174 || i
.types
[op
].bitfield
.reg32
4175 || i
.types
[op
].bitfield
.reg64
)
4176 && i
.op
[op
].regs
->reg_num
< 4)
4178 /* Prohibit these changes in the 64bit mode, since the
4179 lowering is more complicated. */
4180 if (flag_code
== CODE_64BIT
4181 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4183 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4184 register_prefix
, i
.op
[op
].regs
->reg_name
,
4188 #if REGISTER_WARNINGS
4190 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4191 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4193 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4194 ? REGNAM_AL
- REGNAM_AX
4195 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4197 i
.op
[op
].regs
->reg_name
,
4202 /* Any other register is bad. */
4203 if (i
.types
[op
].bitfield
.reg16
4204 || i
.types
[op
].bitfield
.reg32
4205 || i
.types
[op
].bitfield
.reg64
4206 || i
.types
[op
].bitfield
.regmmx
4207 || i
.types
[op
].bitfield
.regxmm
4208 || i
.types
[op
].bitfield
.regymm
4209 || i
.types
[op
].bitfield
.sreg2
4210 || i
.types
[op
].bitfield
.sreg3
4211 || i
.types
[op
].bitfield
.control
4212 || i
.types
[op
].bitfield
.debug
4213 || i
.types
[op
].bitfield
.test
4214 || i
.types
[op
].bitfield
.floatreg
4215 || i
.types
[op
].bitfield
.floatacc
)
4217 as_bad (_("`%s%s' not allowed with `%s%c'"),
4219 i
.op
[op
].regs
->reg_name
,
4229 check_long_reg (void)
4233 for (op
= i
.operands
; --op
>= 0;)
4234 /* Reject eight bit registers, except where the template requires
4235 them. (eg. movzb) */
4236 if (i
.types
[op
].bitfield
.reg8
4237 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4238 || i
.tm
.operand_types
[op
].bitfield
.reg32
4239 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4241 as_bad (_("`%s%s' not allowed with `%s%c'"),
4243 i
.op
[op
].regs
->reg_name
,
4248 /* Warn if the e prefix on a general reg is missing. */
4249 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4250 && i
.types
[op
].bitfield
.reg16
4251 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4252 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4254 /* Prohibit these changes in the 64bit mode, since the
4255 lowering is more complicated. */
4256 if (flag_code
== CODE_64BIT
)
4258 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4259 register_prefix
, i
.op
[op
].regs
->reg_name
,
4263 #if REGISTER_WARNINGS
4265 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4267 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4269 i
.op
[op
].regs
->reg_name
,
4273 /* Warn if the r prefix on a general reg is missing. */
4274 else if (i
.types
[op
].bitfield
.reg64
4275 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4276 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4279 && i
.tm
.opcode_modifier
.toqword
4280 && !i
.types
[0].bitfield
.regxmm
)
4282 /* Convert to QWORD. We want REX byte. */
4283 i
.suffix
= QWORD_MNEM_SUFFIX
;
4287 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4288 register_prefix
, i
.op
[op
].regs
->reg_name
,
4297 check_qword_reg (void)
4301 for (op
= i
.operands
; --op
>= 0; )
4302 /* Reject eight bit registers, except where the template requires
4303 them. (eg. movzb) */
4304 if (i
.types
[op
].bitfield
.reg8
4305 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4306 || i
.tm
.operand_types
[op
].bitfield
.reg32
4307 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4309 as_bad (_("`%s%s' not allowed with `%s%c'"),
4311 i
.op
[op
].regs
->reg_name
,
4316 /* Warn if the e prefix on a general reg is missing. */
4317 else if ((i
.types
[op
].bitfield
.reg16
4318 || i
.types
[op
].bitfield
.reg32
)
4319 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4320 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4322 /* Prohibit these changes in the 64bit mode, since the
4323 lowering is more complicated. */
4325 && i
.tm
.opcode_modifier
.todword
4326 && !i
.types
[0].bitfield
.regxmm
)
4328 /* Convert to DWORD. We don't want REX byte. */
4329 i
.suffix
= LONG_MNEM_SUFFIX
;
4333 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4334 register_prefix
, i
.op
[op
].regs
->reg_name
,
4343 check_word_reg (void)
4346 for (op
= i
.operands
; --op
>= 0;)
4347 /* Reject eight bit registers, except where the template requires
4348 them. (eg. movzb) */
4349 if (i
.types
[op
].bitfield
.reg8
4350 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4351 || i
.tm
.operand_types
[op
].bitfield
.reg32
4352 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4354 as_bad (_("`%s%s' not allowed with `%s%c'"),
4356 i
.op
[op
].regs
->reg_name
,
4361 /* Warn if the e prefix on a general reg is present. */
4362 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4363 && i
.types
[op
].bitfield
.reg32
4364 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4365 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4367 /* Prohibit these changes in the 64bit mode, since the
4368 lowering is more complicated. */
4369 if (flag_code
== CODE_64BIT
)
4371 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4372 register_prefix
, i
.op
[op
].regs
->reg_name
,
4377 #if REGISTER_WARNINGS
4378 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4380 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4382 i
.op
[op
].regs
->reg_name
,
4390 update_imm (unsigned int j
)
4392 i386_operand_type overlap
;
4394 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4395 if ((overlap
.bitfield
.imm8
4396 || overlap
.bitfield
.imm8s
4397 || overlap
.bitfield
.imm16
4398 || overlap
.bitfield
.imm32
4399 || overlap
.bitfield
.imm32s
4400 || overlap
.bitfield
.imm64
)
4401 && !operand_type_equal (&overlap
, &imm8
)
4402 && !operand_type_equal (&overlap
, &imm8s
)
4403 && !operand_type_equal (&overlap
, &imm16
)
4404 && !operand_type_equal (&overlap
, &imm32
)
4405 && !operand_type_equal (&overlap
, &imm32s
)
4406 && !operand_type_equal (&overlap
, &imm64
))
4410 i386_operand_type temp
;
4412 operand_type_set (&temp
, 0);
4413 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4415 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4416 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4418 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4419 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4420 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4422 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4423 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4426 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4429 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4430 || operand_type_equal (&overlap
, &imm16_32
)
4431 || operand_type_equal (&overlap
, &imm16_32s
))
4433 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4438 if (!operand_type_equal (&overlap
, &imm8
)
4439 && !operand_type_equal (&overlap
, &imm8s
)
4440 && !operand_type_equal (&overlap
, &imm16
)
4441 && !operand_type_equal (&overlap
, &imm32
)
4442 && !operand_type_equal (&overlap
, &imm32s
)
4443 && !operand_type_equal (&overlap
, &imm64
))
4445 as_bad (_("no instruction mnemonic suffix given; "
4446 "can't determine immediate size"));
4450 i
.types
[j
] = overlap
;
4460 for (j
= 0; j
< 2; j
++)
4461 if (update_imm (j
) == 0)
4464 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4465 assert (operand_type_check (i
.types
[2], imm
) == 0);
4473 i
.drex
.modrm_reg
= 0;
4474 i
.drex
.modrm_regmem
= 0;
4476 /* SSE5 4 operand instructions must have the destination the same as
4477 one of the inputs. Figure out the destination register and cache
4478 it away in the drex field, and remember which fields to use for
4480 if (i
.tm
.opcode_modifier
.drex
4481 && i
.tm
.opcode_modifier
.drexv
4484 i
.tm
.extension_opcode
= None
;
4486 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4487 if (i
.types
[0].bitfield
.regxmm
!= 0
4488 && i
.types
[1].bitfield
.regxmm
!= 0
4489 && i
.types
[2].bitfield
.regxmm
!= 0
4490 && i
.types
[3].bitfield
.regxmm
!= 0
4491 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4492 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4494 /* Clear the arguments that are stored in drex. */
4495 operand_type_set (&i
.types
[0], 0);
4496 operand_type_set (&i
.types
[3], 0);
4497 i
.reg_operands
-= 2;
4499 /* There are two different ways to encode a 4 operand
4500 instruction with all registers that uses OC1 set to
4501 0 or 1. Favor setting OC1 to 0 since this mimics the
4502 actions of other SSE5 assemblers. Use modrm encoding 2
4503 for register/register. Include the high order bit that
4504 is normally stored in the REX byte in the register
4506 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4507 i
.drex
.modrm_reg
= 2;
4508 i
.drex
.modrm_regmem
= 1;
4509 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4510 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4513 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4514 else if (i
.types
[0].bitfield
.regxmm
!= 0
4515 && i
.types
[1].bitfield
.regxmm
!= 0
4516 && (i
.types
[2].bitfield
.regxmm
4517 || operand_type_check (i
.types
[2], anymem
))
4518 && i
.types
[3].bitfield
.regxmm
!= 0
4519 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4520 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4522 /* clear the arguments that are stored in drex */
4523 operand_type_set (&i
.types
[0], 0);
4524 operand_type_set (&i
.types
[3], 0);
4525 i
.reg_operands
-= 2;
4527 /* Specify the modrm encoding for memory addressing. Include
4528 the high order bit that is normally stored in the REX byte
4529 in the register field. */
4530 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4531 i
.drex
.modrm_reg
= 1;
4532 i
.drex
.modrm_regmem
= 2;
4533 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4534 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4537 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4538 else if (i
.types
[0].bitfield
.regxmm
!= 0
4539 && operand_type_check (i
.types
[1], anymem
) != 0
4540 && i
.types
[2].bitfield
.regxmm
!= 0
4541 && i
.types
[3].bitfield
.regxmm
!= 0
4542 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4543 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4545 /* Clear the arguments that are stored in drex. */
4546 operand_type_set (&i
.types
[0], 0);
4547 operand_type_set (&i
.types
[3], 0);
4548 i
.reg_operands
-= 2;
4550 /* Specify the modrm encoding for memory addressing. Include
4551 the high order bit that is normally stored in the REX byte
4552 in the register field. */
4553 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4554 i
.drex
.modrm_reg
= 2;
4555 i
.drex
.modrm_regmem
= 1;
4556 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4557 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4560 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4561 else if (i
.types
[0].bitfield
.regxmm
!= 0
4562 && i
.types
[1].bitfield
.regxmm
!= 0
4563 && i
.types
[2].bitfield
.regxmm
!= 0
4564 && i
.types
[3].bitfield
.regxmm
!= 0
4565 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4566 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4568 /* clear the arguments that are stored in drex */
4569 operand_type_set (&i
.types
[2], 0);
4570 operand_type_set (&i
.types
[3], 0);
4571 i
.reg_operands
-= 2;
4573 /* There are two different ways to encode a 4 operand
4574 instruction with all registers that uses OC1 set to
4575 0 or 1. Favor setting OC1 to 0 since this mimics the
4576 actions of other SSE5 assemblers. Use modrm encoding
4577 2 for register/register. Include the high order bit that
4578 is normally stored in the REX byte in the register
4580 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4581 i
.drex
.modrm_reg
= 1;
4582 i
.drex
.modrm_regmem
= 0;
4584 /* Remember the register, including the upper bits */
4585 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4586 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4589 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4590 else if (i
.types
[0].bitfield
.regxmm
!= 0
4591 && (i
.types
[1].bitfield
.regxmm
4592 || operand_type_check (i
.types
[1], anymem
))
4593 && i
.types
[2].bitfield
.regxmm
!= 0
4594 && i
.types
[3].bitfield
.regxmm
!= 0
4595 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4596 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4598 /* Clear the arguments that are stored in drex. */
4599 operand_type_set (&i
.types
[2], 0);
4600 operand_type_set (&i
.types
[3], 0);
4601 i
.reg_operands
-= 2;
4603 /* Specify the modrm encoding and remember the register
4604 including the bits normally stored in the REX byte. */
4605 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4606 i
.drex
.modrm_reg
= 0;
4607 i
.drex
.modrm_regmem
= 1;
4608 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4609 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4612 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4613 else if (operand_type_check (i
.types
[0], anymem
) != 0
4614 && i
.types
[1].bitfield
.regxmm
!= 0
4615 && i
.types
[2].bitfield
.regxmm
!= 0
4616 && i
.types
[3].bitfield
.regxmm
!= 0
4617 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4618 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4620 /* clear the arguments that are stored in drex */
4621 operand_type_set (&i
.types
[2], 0);
4622 operand_type_set (&i
.types
[3], 0);
4623 i
.reg_operands
-= 2;
4625 /* Specify the modrm encoding and remember the register
4626 including the bits normally stored in the REX byte. */
4627 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4628 i
.drex
.modrm_reg
= 1;
4629 i
.drex
.modrm_regmem
= 0;
4630 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4631 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4635 as_bad (_("Incorrect operands for the '%s' instruction"),
4639 /* SSE5 instructions with the DREX byte where the only memory operand
4640 is in the 2nd argument, and the first and last xmm register must
4641 match, and is encoded in the DREX byte. */
4642 else if (i
.tm
.opcode_modifier
.drex
4643 && !i
.tm
.opcode_modifier
.drexv
4646 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4647 if (i
.types
[0].bitfield
.regxmm
!= 0
4648 && (i
.types
[1].bitfield
.regxmm
4649 || operand_type_check(i
.types
[1], anymem
))
4650 && i
.types
[2].bitfield
.regxmm
!= 0
4651 && i
.types
[3].bitfield
.regxmm
!= 0
4652 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4653 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4655 /* clear the arguments that are stored in drex */
4656 operand_type_set (&i
.types
[0], 0);
4657 operand_type_set (&i
.types
[3], 0);
4658 i
.reg_operands
-= 2;
4660 /* Specify the modrm encoding and remember the register
4661 including the high bit normally stored in the REX
4663 i
.drex
.modrm_reg
= 2;
4664 i
.drex
.modrm_regmem
= 1;
4665 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4666 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4670 as_bad (_("Incorrect operands for the '%s' instruction"),
4674 /* SSE5 3 operand instructions that the result is a register, being
4675 either operand can be a memory operand, using OC0 to note which
4676 one is the memory. */
4677 else if (i
.tm
.opcode_modifier
.drex
4678 && i
.tm
.opcode_modifier
.drexv
4681 i
.tm
.extension_opcode
= None
;
4683 /* Case 1: 3 operand insn, src1 = register. */
4684 if (i
.types
[0].bitfield
.regxmm
!= 0
4685 && i
.types
[1].bitfield
.regxmm
!= 0
4686 && i
.types
[2].bitfield
.regxmm
!= 0)
4688 /* Clear the arguments that are stored in drex. */
4689 operand_type_set (&i
.types
[2], 0);
4692 /* Specify the modrm encoding and remember the register
4693 including the high bit normally stored in the REX byte. */
4694 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4695 i
.drex
.modrm_reg
= 1;
4696 i
.drex
.modrm_regmem
= 0;
4697 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4698 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4701 /* Case 2: 3 operand insn, src1 = memory. */
4702 else if (operand_type_check (i
.types
[0], anymem
) != 0
4703 && i
.types
[1].bitfield
.regxmm
!= 0
4704 && i
.types
[2].bitfield
.regxmm
!= 0)
4706 /* Clear the arguments that are stored in drex. */
4707 operand_type_set (&i
.types
[2], 0);
4710 /* Specify the modrm encoding and remember the register
4711 including the high bit normally stored in the REX
4713 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4714 i
.drex
.modrm_reg
= 1;
4715 i
.drex
.modrm_regmem
= 0;
4716 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4717 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4720 /* Case 3: 3 operand insn, src2 = memory. */
4721 else if (i
.types
[0].bitfield
.regxmm
!= 0
4722 && operand_type_check (i
.types
[1], anymem
) != 0
4723 && i
.types
[2].bitfield
.regxmm
!= 0)
4725 /* Clear the arguments that are stored in drex. */
4726 operand_type_set (&i
.types
[2], 0);
4729 /* Specify the modrm encoding and remember the register
4730 including the high bit normally stored in the REX byte. */
4731 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4732 i
.drex
.modrm_reg
= 0;
4733 i
.drex
.modrm_regmem
= 1;
4734 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4735 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4739 as_bad (_("Incorrect operands for the '%s' instruction"),
4743 /* SSE5 4 operand instructions that are the comparison instructions
4744 where the first operand is the immediate value of the comparison
4746 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4748 /* Case 1: 4 operand insn, src1 = reg/memory. */
4749 if (operand_type_check (i
.types
[0], imm
) != 0
4750 && (i
.types
[1].bitfield
.regxmm
4751 || operand_type_check (i
.types
[1], anymem
))
4752 && i
.types
[2].bitfield
.regxmm
!= 0
4753 && i
.types
[3].bitfield
.regxmm
!= 0)
4755 /* clear the arguments that are stored in drex */
4756 operand_type_set (&i
.types
[3], 0);
4759 /* Specify the modrm encoding and remember the register
4760 including the high bit normally stored in the REX byte. */
4761 i
.drex
.modrm_reg
= 2;
4762 i
.drex
.modrm_regmem
= 1;
4763 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4764 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4767 /* Case 2: 3 operand insn with ImmExt that places the
4768 opcode_extension as an immediate argument. This is used for
4769 all of the varients of comparison that supplies the appropriate
4770 value as part of the instruction. */
4771 else if ((i
.types
[0].bitfield
.regxmm
4772 || operand_type_check (i
.types
[0], anymem
))
4773 && i
.types
[1].bitfield
.regxmm
!= 0
4774 && i
.types
[2].bitfield
.regxmm
!= 0
4775 && operand_type_check (i
.types
[3], imm
) != 0)
4777 /* clear the arguments that are stored in drex */
4778 operand_type_set (&i
.types
[2], 0);
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX byte. */
4783 i
.drex
.modrm_reg
= 1;
4784 i
.drex
.modrm_regmem
= 0;
4785 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4786 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4790 as_bad (_("Incorrect operands for the '%s' instruction"),
4794 else if (i
.tm
.opcode_modifier
.drex
4795 || i
.tm
.opcode_modifier
.drexv
4796 || i
.tm
.opcode_modifier
.drexc
)
4797 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4801 bad_implicit_operand (int xmm
)
4803 const char *reg
= xmm
? "xmm0" : "ymm0";
4805 as_bad (_("the last operand of `%s' must be `%s%s'"),
4806 i
.tm
.name
, register_prefix
, reg
);
4808 as_bad (_("the first operand of `%s' must be `%s%s'"),
4809 i
.tm
.name
, register_prefix
, reg
);
4814 process_operands (void)
4816 /* Default segment register this instruction will use for memory
4817 accesses. 0 means unknown. This is only for optimizing out
4818 unnecessary segment overrides. */
4819 const seg_entry
*default_seg
= 0;
4821 /* Handle all of the DREX munging that SSE5 needs. */
4822 if (i
.tm
.opcode_modifier
.drex
4823 || i
.tm
.opcode_modifier
.drexv
4824 || i
.tm
.opcode_modifier
.drexc
)
4827 if (i
.tm
.opcode_modifier
.sse2avx
4828 && (i
.tm
.opcode_modifier
.vexnds
4829 || i
.tm
.opcode_modifier
.vexndd
))
4831 unsigned int dup
= i
.operands
;
4832 unsigned int dest
= dup
- 1;
4835 /* The destination must be an xmm register. */
4836 assert (i
.reg_operands
4837 && MAX_OPERANDS
> dup
4838 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4840 if (i
.tm
.opcode_modifier
.firstxmm0
)
4842 /* The first operand is implicit and must be xmm0. */
4843 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4844 if (i
.op
[0].regs
->reg_num
!= 0)
4845 return bad_implicit_operand (1);
4847 if (i
.tm
.opcode_modifier
.vex3sources
)
4849 /* Keep xmm0 for instructions with VEX prefix and 3
4855 /* We remove the first xmm0 and keep the number of
4856 operands unchanged, which in fact duplicates the
4858 for (j
= 1; j
< i
.operands
; j
++)
4860 i
.op
[j
- 1] = i
.op
[j
];
4861 i
.types
[j
- 1] = i
.types
[j
];
4862 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4866 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4868 assert ((MAX_OPERANDS
- 1) > dup
4869 && i
.tm
.opcode_modifier
.vex3sources
);
4871 /* Add the implicit xmm0 for instructions with VEX prefix
4873 for (j
= i
.operands
; j
> 0; j
--)
4875 i
.op
[j
] = i
.op
[j
- 1];
4876 i
.types
[j
] = i
.types
[j
- 1];
4877 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4880 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4881 i
.types
[0] = regxmm
;
4882 i
.tm
.operand_types
[0] = regxmm
;
4885 i
.reg_operands
+= 2;
4890 i
.op
[dup
] = i
.op
[dest
];
4891 i
.types
[dup
] = i
.types
[dest
];
4892 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4901 i
.op
[dup
] = i
.op
[dest
];
4902 i
.types
[dup
] = i
.types
[dest
];
4903 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4906 if (i
.tm
.opcode_modifier
.immext
)
4909 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4913 /* The first operand is implicit and must be xmm0/ymm0. */
4914 assert (i
.reg_operands
4915 && (operand_type_equal (&i
.types
[0], ®xmm
)
4916 || operand_type_equal (&i
.types
[0], ®ymm
)));
4917 if (i
.op
[0].regs
->reg_num
!= 0)
4918 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4920 for (j
= 1; j
< i
.operands
; j
++)
4922 i
.op
[j
- 1] = i
.op
[j
];
4923 i
.types
[j
- 1] = i
.types
[j
];
4925 /* We need to adjust fields in i.tm since they are used by
4926 build_modrm_byte. */
4927 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4934 else if (i
.tm
.opcode_modifier
.regkludge
)
4936 /* The imul $imm, %reg instruction is converted into
4937 imul $imm, %reg, %reg, and the clr %reg instruction
4938 is converted into xor %reg, %reg. */
4940 unsigned int first_reg_op
;
4942 if (operand_type_check (i
.types
[0], reg
))
4946 /* Pretend we saw the extra register operand. */
4947 assert (i
.reg_operands
== 1
4948 && i
.op
[first_reg_op
+ 1].regs
== 0);
4949 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4950 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4955 if (i
.tm
.opcode_modifier
.shortform
)
4957 if (i
.types
[0].bitfield
.sreg2
4958 || i
.types
[0].bitfield
.sreg3
)
4960 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4961 && i
.op
[0].regs
->reg_num
== 1)
4963 as_bad (_("you can't `pop %scs'"), register_prefix
);
4966 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4967 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4972 /* The register or float register operand is in operand
4976 if (i
.types
[0].bitfield
.floatreg
4977 || operand_type_check (i
.types
[0], reg
))
4981 /* Register goes in low 3 bits of opcode. */
4982 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4983 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4985 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4987 /* Warn about some common errors, but press on regardless.
4988 The first case can be generated by gcc (<= 2.8.1). */
4989 if (i
.operands
== 2)
4991 /* Reversed arguments on faddp, fsubp, etc. */
4992 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4993 register_prefix
, i
.op
[1].regs
->reg_name
,
4994 register_prefix
, i
.op
[0].regs
->reg_name
);
4998 /* Extraneous `l' suffix on fp insn. */
4999 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5000 register_prefix
, i
.op
[0].regs
->reg_name
);
5005 else if (i
.tm
.opcode_modifier
.modrm
)
5007 /* The opcode is completed (modulo i.tm.extension_opcode which
5008 must be put into the modrm byte). Now, we make the modrm and
5009 index base bytes based on all the info we've collected. */
5011 default_seg
= build_modrm_byte ();
5013 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5017 else if (i
.tm
.opcode_modifier
.isstring
)
5019 /* For the string instructions that allow a segment override
5020 on one of their operands, the default segment is ds. */
5024 if (i
.tm
.base_opcode
== 0x8d /* lea */
5027 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5029 /* If a segment was explicitly specified, and the specified segment
5030 is not the default, use an opcode prefix to select it. If we
5031 never figured out what the default segment is, then default_seg
5032 will be zero at this point, and the specified segment prefix will
5034 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5036 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5042 static const seg_entry
*
5043 build_modrm_byte (void)
5045 const seg_entry
*default_seg
= 0;
5046 unsigned int source
, dest
;
5049 /* The first operand of instructions with VEX prefix and 3 sources
5050 must be VEX_Imm4. */
5051 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5054 unsigned int nds
, reg
;
5056 if (i
.tm
.opcode_modifier
.veximmext
5057 && i
.tm
.opcode_modifier
.immext
)
5059 dest
= i
.operands
- 2;
5063 dest
= i
.operands
- 1;
5066 /* There are 2 kinds of instructions:
5067 1. 5 operands: one immediate operand and 4 register
5068 operands or 3 register operands plus 1 memory operand.
5069 It must have VexNDS and VexW0 or VexW1. The destination
5070 must be either XMM or YMM register.
5071 2. 4 operands: 4 register operands or 3 register operands
5072 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5073 if (!((i
.reg_operands
== 4
5074 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5075 && i
.tm
.opcode_modifier
.vexnds
5076 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5077 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5079 && i
.imm_operands
== 1
5080 && i
.types
[0].bitfield
.vex_imm4
5081 && (i
.tm
.opcode_modifier
.vexw0
5082 || i
.tm
.opcode_modifier
.vexw1
))
5084 && (i
.imm_operands
== 0
5085 || (i
.imm_operands
== 1
5086 && i
.tm
.opcode_modifier
.immext
))
5087 && i
.tm
.opcode_modifier
.veximmext
))))
5090 if (i
.imm_operands
== 0)
5092 /* When there is no immediate operand, generate an 8bit
5093 immediate operand to encode the first operand. */
5094 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5095 i
.op
[i
.operands
].imms
= exp
;
5096 i
.types
[i
.operands
] = imm8
;
5098 /* If VexW1 is set, the first operand is the source and
5099 the second operand is encoded in the immediate operand. */
5100 if (i
.tm
.opcode_modifier
.vexw1
)
5111 /* FMA swaps REG and NDS. */
5112 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5120 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5121 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5123 exp
->X_op
= O_constant
;
5125 = ((i
.op
[reg
].regs
->reg_num
5126 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5132 if (i
.tm
.opcode_modifier
.vexw0
)
5134 /* If VexW0 is set, the third operand is the source and
5135 the second operand is encoded in the immediate
5142 /* VexW1 is set, the second operand is the source and
5143 the third operand is encoded in the immediate
5149 if (i
.tm
.opcode_modifier
.immext
)
5151 /* When ImmExt is set, the immdiate byte is the last
5153 imm
= i
.operands
- 1;
5161 /* Turn on Imm8 so that output_imm will generate it. */
5162 i
.types
[imm
].bitfield
.imm8
= 1;
5165 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5166 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5168 i
.op
[imm
].imms
->X_add_number
5169 |= ((i
.op
[reg
].regs
->reg_num
5170 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5173 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5174 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5175 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5181 /* SSE5 4 operand instructions are encoded in such a way that one of
5182 the inputs must match the destination register. Process_drex hides
5183 the 3rd argument in the drex field, so that by the time we get
5184 here, it looks to GAS as if this is a 2 operand instruction. */
5185 if ((i
.tm
.opcode_modifier
.drex
5186 || i
.tm
.opcode_modifier
.drexv
5187 || i
.tm
.opcode_modifier
.drexc
)
5188 && i
.reg_operands
== 2)
5190 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5191 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5193 i
.rm
.reg
= reg
->reg_num
;
5194 i
.rm
.regmem
= regmem
->reg_num
;
5196 if ((reg
->reg_flags
& RegRex
) != 0)
5198 if ((regmem
->reg_flags
& RegRex
) != 0)
5202 /* i.reg_operands MUST be the number of real register operands;
5203 implicit registers do not count. If there are 3 register
5204 operands, it must be a instruction with VexNDS. For a
5205 instruction with VexNDD, the destination register is encoded
5206 in VEX prefix. If there are 4 register operands, it must be
5207 a instruction with VEX prefix and 3 sources. */
5208 else if (i
.mem_operands
== 0
5209 && ((i
.reg_operands
== 2
5210 && !i
.tm
.opcode_modifier
.vexndd
)
5211 || (i
.reg_operands
== 3
5212 && i
.tm
.opcode_modifier
.vexnds
)
5213 || (i
.reg_operands
== 4 && vex_3_sources
)))
5221 /* When there are 3 operands, one of them may be immediate,
5222 which may be the first or the last operand. Otherwise,
5223 the first operand must be shift count register (cl) or it
5224 is an instruction with VexNDS. */
5225 assert (i
.imm_operands
== 1
5226 || (i
.imm_operands
== 0
5227 && (i
.tm
.opcode_modifier
.vexnds
5228 || i
.types
[0].bitfield
.shiftcount
)));
5229 if (operand_type_check (i
.types
[0], imm
)
5230 || i
.types
[0].bitfield
.shiftcount
)
5236 /* When there are 4 operands, the first two must be 8bit
5237 immediate operands. The source operand will be the 3rd
5240 For instructions with VexNDS, if the first operand
5241 an imm8, the source operand is the 2nd one. If the last
5242 operand is imm8, the source operand is the first one. */
5243 assert ((i
.imm_operands
== 2
5244 && i
.types
[0].bitfield
.imm8
5245 && i
.types
[1].bitfield
.imm8
)
5246 || (i
.tm
.opcode_modifier
.vexnds
5247 && i
.imm_operands
== 1
5248 && (i
.types
[0].bitfield
.imm8
5249 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5250 if (i
.tm
.opcode_modifier
.vexnds
)
5252 if (i
.types
[0].bitfield
.imm8
)
5270 if (i
.tm
.opcode_modifier
.vexnds
)
5272 /* For instructions with VexNDS, the register-only
5273 source operand must be XMM or YMM register. It is
5274 encoded in VEX prefix. */
5275 if ((dest
+ 1) >= i
.operands
5276 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5278 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5281 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5287 /* One of the register operands will be encoded in the i.tm.reg
5288 field, the other in the combined i.tm.mode and i.tm.regmem
5289 fields. If no form of this instruction supports a memory
5290 destination operand, then we assume the source operand may
5291 sometimes be a memory operand and so we need to store the
5292 destination in the i.rm.reg field. */
5293 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5294 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5296 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5297 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5298 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5300 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5305 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5306 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5307 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5309 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5312 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5314 if (!i
.types
[0].bitfield
.control
5315 && !i
.types
[1].bitfield
.control
)
5317 i
.rex
&= ~(REX_R
| REX_B
);
5318 add_prefix (LOCK_PREFIX_OPCODE
);
5322 { /* If it's not 2 reg operands... */
5327 unsigned int fake_zero_displacement
= 0;
5330 /* This has been precalculated for SSE5 instructions
5331 that have a DREX field earlier in process_drex. */
5332 if (i
.tm
.opcode_modifier
.drex
5333 || i
.tm
.opcode_modifier
.drexv
5334 || i
.tm
.opcode_modifier
.drexc
)
5335 op
= i
.drex
.modrm_regmem
;
5338 for (op
= 0; op
< i
.operands
; op
++)
5339 if (operand_type_check (i
.types
[op
], anymem
))
5341 assert (op
< i
.operands
);
5346 if (i
.base_reg
== 0)
5349 if (!i
.disp_operands
)
5350 fake_zero_displacement
= 1;
5351 if (i
.index_reg
== 0)
5353 /* Operand is just <disp> */
5354 if (flag_code
== CODE_64BIT
)
5356 /* 64bit mode overwrites the 32bit absolute
5357 addressing by RIP relative addressing and
5358 absolute addressing is encoded by one of the
5359 redundant SIB forms. */
5360 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5361 i
.sib
.base
= NO_BASE_REGISTER
;
5362 i
.sib
.index
= NO_INDEX_REGISTER
;
5363 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5364 ? disp32s
: disp32
);
5366 else if ((flag_code
== CODE_16BIT
)
5367 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5369 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5370 i
.types
[op
] = disp16
;
5374 i
.rm
.regmem
= NO_BASE_REGISTER
;
5375 i
.types
[op
] = disp32
;
5378 else /* !i.base_reg && i.index_reg */
5380 if (i
.index_reg
->reg_num
== RegEiz
5381 || i
.index_reg
->reg_num
== RegRiz
)
5382 i
.sib
.index
= NO_INDEX_REGISTER
;
5384 i
.sib
.index
= i
.index_reg
->reg_num
;
5385 i
.sib
.base
= NO_BASE_REGISTER
;
5386 i
.sib
.scale
= i
.log2_scale_factor
;
5387 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5388 i
.types
[op
].bitfield
.disp8
= 0;
5389 i
.types
[op
].bitfield
.disp16
= 0;
5390 i
.types
[op
].bitfield
.disp64
= 0;
5391 if (flag_code
!= CODE_64BIT
)
5393 /* Must be 32 bit */
5394 i
.types
[op
].bitfield
.disp32
= 1;
5395 i
.types
[op
].bitfield
.disp32s
= 0;
5399 i
.types
[op
].bitfield
.disp32
= 0;
5400 i
.types
[op
].bitfield
.disp32s
= 1;
5402 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5406 /* RIP addressing for 64bit mode. */
5407 else if (i
.base_reg
->reg_num
== RegRip
||
5408 i
.base_reg
->reg_num
== RegEip
)
5410 i
.rm
.regmem
= NO_BASE_REGISTER
;
5411 i
.types
[op
].bitfield
.disp8
= 0;
5412 i
.types
[op
].bitfield
.disp16
= 0;
5413 i
.types
[op
].bitfield
.disp32
= 0;
5414 i
.types
[op
].bitfield
.disp32s
= 1;
5415 i
.types
[op
].bitfield
.disp64
= 0;
5416 i
.flags
[op
] |= Operand_PCrel
;
5417 if (! i
.disp_operands
)
5418 fake_zero_displacement
= 1;
5420 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5422 switch (i
.base_reg
->reg_num
)
5425 if (i
.index_reg
== 0)
5427 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5428 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5432 if (i
.index_reg
== 0)
5435 if (operand_type_check (i
.types
[op
], disp
) == 0)
5437 /* fake (%bp) into 0(%bp) */
5438 i
.types
[op
].bitfield
.disp8
= 1;
5439 fake_zero_displacement
= 1;
5442 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5443 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5445 default: /* (%si) -> 4 or (%di) -> 5 */
5446 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5448 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5450 else /* i.base_reg and 32/64 bit mode */
5452 if (flag_code
== CODE_64BIT
5453 && operand_type_check (i
.types
[op
], disp
))
5455 i386_operand_type temp
;
5456 operand_type_set (&temp
, 0);
5457 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5459 if (i
.prefix
[ADDR_PREFIX
] == 0)
5460 i
.types
[op
].bitfield
.disp32s
= 1;
5462 i
.types
[op
].bitfield
.disp32
= 1;
5465 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5466 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5468 i
.sib
.base
= i
.base_reg
->reg_num
;
5469 /* x86-64 ignores REX prefix bit here to avoid decoder
5471 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5474 if (i
.disp_operands
== 0)
5476 fake_zero_displacement
= 1;
5477 i
.types
[op
].bitfield
.disp8
= 1;
5480 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5484 i
.sib
.scale
= i
.log2_scale_factor
;
5485 if (i
.index_reg
== 0)
5487 /* <disp>(%esp) becomes two byte modrm with no index
5488 register. We've already stored the code for esp
5489 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5490 Any base register besides %esp will not use the
5491 extra modrm byte. */
5492 i
.sib
.index
= NO_INDEX_REGISTER
;
5496 if (i
.index_reg
->reg_num
== RegEiz
5497 || i
.index_reg
->reg_num
== RegRiz
)
5498 i
.sib
.index
= NO_INDEX_REGISTER
;
5500 i
.sib
.index
= i
.index_reg
->reg_num
;
5501 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5502 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5507 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5508 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5511 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5514 if (fake_zero_displacement
)
5516 /* Fakes a zero displacement assuming that i.types[op]
5517 holds the correct displacement size. */
5520 assert (i
.op
[op
].disps
== 0);
5521 exp
= &disp_expressions
[i
.disp_operands
++];
5522 i
.op
[op
].disps
= exp
;
5523 exp
->X_op
= O_constant
;
5524 exp
->X_add_number
= 0;
5525 exp
->X_add_symbol
= (symbolS
*) 0;
5526 exp
->X_op_symbol
= (symbolS
*) 0;
5534 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5535 (if any) based on i.tm.extension_opcode. Again, we must be
5536 careful to make sure that segment/control/debug/test/MMX
5537 registers are coded into the i.rm.reg field. */
5542 /* This has been precalculated for SSE5 instructions
5543 that have a DREX field earlier in process_drex. */
5544 if (i
.tm
.opcode_modifier
.drex
5545 || i
.tm
.opcode_modifier
.drexv
5546 || i
.tm
.opcode_modifier
.drexc
)
5548 op
= i
.drex
.modrm_reg
;
5549 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5550 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5555 unsigned int vex_reg
= ~0;
5557 for (op
= 0; op
< i
.operands
; op
++)
5558 if (i
.types
[op
].bitfield
.reg8
5559 || i
.types
[op
].bitfield
.reg16
5560 || i
.types
[op
].bitfield
.reg32
5561 || i
.types
[op
].bitfield
.reg64
5562 || i
.types
[op
].bitfield
.regmmx
5563 || i
.types
[op
].bitfield
.regxmm
5564 || i
.types
[op
].bitfield
.regymm
5565 || i
.types
[op
].bitfield
.sreg2
5566 || i
.types
[op
].bitfield
.sreg3
5567 || i
.types
[op
].bitfield
.control
5568 || i
.types
[op
].bitfield
.debug
5569 || i
.types
[op
].bitfield
.test
)
5574 else if (i
.tm
.opcode_modifier
.vexnds
)
5576 /* For instructions with VexNDS, the register-only
5577 source operand is encoded in VEX prefix. */
5578 assert (mem
!= (unsigned int) ~0);
5583 assert (op
< i
.operands
);
5588 assert (vex_reg
< i
.operands
);
5591 else if (i
.tm
.opcode_modifier
.vexndd
)
5593 /* For instructions with VexNDD, there should be
5594 no memory operand and the register destination
5595 is encoded in VEX prefix. */
5596 assert (i
.mem_operands
== 0
5597 && (op
+ 2) == i
.operands
);
5601 assert (op
< i
.operands
);
5603 if (vex_reg
!= (unsigned int) ~0)
5605 assert (i
.reg_operands
== 2);
5607 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5609 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5612 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5615 /* If there is an extension opcode to put here, the
5616 register number must be put into the regmem field. */
5617 if (i
.tm
.extension_opcode
!= None
)
5619 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5620 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5625 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5626 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5631 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5632 must set it to 3 to indicate this is a register operand
5633 in the regmem field. */
5634 if (!i
.mem_operands
)
5638 /* Fill in i.rm.reg field with extension opcode (if any). */
5639 if (i
.tm
.extension_opcode
!= None
5640 && !(i
.tm
.opcode_modifier
.drex
5641 || i
.tm
.opcode_modifier
.drexv
5642 || i
.tm
.opcode_modifier
.drexc
))
5643 i
.rm
.reg
= i
.tm
.extension_opcode
;
5649 output_branch (void)
5654 relax_substateT subtype
;
5659 if (flag_code
== CODE_16BIT
)
5663 if (i
.prefix
[DATA_PREFIX
] != 0)
5669 /* Pentium4 branch hints. */
5670 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5671 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5676 if (i
.prefix
[REX_PREFIX
] != 0)
5682 if (i
.prefixes
!= 0 && !intel_syntax
)
5683 as_warn (_("skipping prefixes on this instruction"));
5685 /* It's always a symbol; End frag & setup for relax.
5686 Make sure there is enough room in this frag for the largest
5687 instruction we may generate in md_convert_frag. This is 2
5688 bytes for the opcode and room for the prefix and largest
5690 frag_grow (prefix
+ 2 + 4);
5691 /* Prefix and 1 opcode byte go in fr_fix. */
5692 p
= frag_more (prefix
+ 1);
5693 if (i
.prefix
[DATA_PREFIX
] != 0)
5694 *p
++ = DATA_PREFIX_OPCODE
;
5695 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5696 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5697 *p
++ = i
.prefix
[SEG_PREFIX
];
5698 if (i
.prefix
[REX_PREFIX
] != 0)
5699 *p
++ = i
.prefix
[REX_PREFIX
];
5700 *p
= i
.tm
.base_opcode
;
5702 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5703 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5704 else if (cpu_arch_flags
.bitfield
.cpui386
)
5705 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5707 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5710 sym
= i
.op
[0].disps
->X_add_symbol
;
5711 off
= i
.op
[0].disps
->X_add_number
;
5713 if (i
.op
[0].disps
->X_op
!= O_constant
5714 && i
.op
[0].disps
->X_op
!= O_symbol
)
5716 /* Handle complex expressions. */
5717 sym
= make_expr_symbol (i
.op
[0].disps
);
5721 /* 1 possible extra opcode + 4 byte displacement go in var part.
5722 Pass reloc in fr_var. */
5723 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5733 if (i
.tm
.opcode_modifier
.jumpbyte
)
5735 /* This is a loop or jecxz type instruction. */
5737 if (i
.prefix
[ADDR_PREFIX
] != 0)
5739 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5742 /* Pentium4 branch hints. */
5743 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5744 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5746 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5755 if (flag_code
== CODE_16BIT
)
5758 if (i
.prefix
[DATA_PREFIX
] != 0)
5760 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5770 if (i
.prefix
[REX_PREFIX
] != 0)
5772 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5776 if (i
.prefixes
!= 0 && !intel_syntax
)
5777 as_warn (_("skipping prefixes on this instruction"));
5779 p
= frag_more (1 + size
);
5780 *p
++ = i
.tm
.base_opcode
;
5782 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5783 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5785 /* All jumps handled here are signed, but don't use a signed limit
5786 check for 32 and 16 bit jumps as we want to allow wrap around at
5787 4G and 64k respectively. */
5789 fixP
->fx_signed
= 1;
5793 output_interseg_jump (void)
5801 if (flag_code
== CODE_16BIT
)
5805 if (i
.prefix
[DATA_PREFIX
] != 0)
5811 if (i
.prefix
[REX_PREFIX
] != 0)
5821 if (i
.prefixes
!= 0 && !intel_syntax
)
5822 as_warn (_("skipping prefixes on this instruction"));
5824 /* 1 opcode; 2 segment; offset */
5825 p
= frag_more (prefix
+ 1 + 2 + size
);
5827 if (i
.prefix
[DATA_PREFIX
] != 0)
5828 *p
++ = DATA_PREFIX_OPCODE
;
5830 if (i
.prefix
[REX_PREFIX
] != 0)
5831 *p
++ = i
.prefix
[REX_PREFIX
];
5833 *p
++ = i
.tm
.base_opcode
;
5834 if (i
.op
[1].imms
->X_op
== O_constant
)
5836 offsetT n
= i
.op
[1].imms
->X_add_number
;
5839 && !fits_in_unsigned_word (n
)
5840 && !fits_in_signed_word (n
))
5842 as_bad (_("16-bit jump out of range"));
5845 md_number_to_chars (p
, n
, size
);
5848 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5849 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5850 if (i
.op
[0].imms
->X_op
!= O_constant
)
5851 as_bad (_("can't handle non absolute segment in `%s'"),
5853 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5859 fragS
*insn_start_frag
;
5860 offsetT insn_start_off
;
5862 /* Tie dwarf2 debug info to the address at the start of the insn.
5863 We can't do this after the insn has been output as the current
5864 frag may have been closed off. eg. by frag_var. */
5865 dwarf2_emit_insn (0);
5867 insn_start_frag
= frag_now
;
5868 insn_start_off
= frag_now_fix ();
5871 if (i
.tm
.opcode_modifier
.jump
)
5873 else if (i
.tm
.opcode_modifier
.jumpbyte
5874 || i
.tm
.opcode_modifier
.jumpdword
)
5876 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5877 output_interseg_jump ();
5880 /* Output normal instructions here. */
5884 unsigned int prefix
;
5886 /* Since the VEX prefix contains the implicit prefix, we don't
5887 need the explicit prefix. */
5888 if (!i
.tm
.opcode_modifier
.vex
)
5890 switch (i
.tm
.opcode_length
)
5893 if (i
.tm
.base_opcode
& 0xff000000)
5895 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5900 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5902 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5903 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5906 if (prefix
!= REPE_PREFIX_OPCODE
5907 || (i
.prefix
[LOCKREP_PREFIX
]
5908 != REPE_PREFIX_OPCODE
))
5909 add_prefix (prefix
);
5912 add_prefix (prefix
);
5921 /* The prefix bytes. */
5922 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5924 FRAG_APPEND_1_CHAR (*q
);
5927 if (i
.tm
.opcode_modifier
.vex
)
5929 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5934 /* REX byte is encoded in VEX prefix. */
5938 FRAG_APPEND_1_CHAR (*q
);
5941 /* There should be no other prefixes for instructions
5946 /* Now the VEX prefix. */
5947 p
= frag_more (i
.vex
.length
);
5948 for (j
= 0; j
< i
.vex
.length
; j
++)
5949 p
[j
] = i
.vex
.bytes
[j
];
5952 /* Now the opcode; be careful about word order here! */
5953 if (i
.tm
.opcode_length
== 1)
5955 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5959 switch (i
.tm
.opcode_length
)
5963 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5973 /* Put out high byte first: can't use md_number_to_chars! */
5974 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5975 *p
= i
.tm
.base_opcode
& 0xff;
5977 /* On SSE5, encode the OC1 bit in the DREX field if this
5978 encoding has multiple formats. */
5979 if (i
.tm
.opcode_modifier
.drex
5980 && i
.tm
.opcode_modifier
.drexv
5981 && DREX_OC1 (i
.tm
.extension_opcode
))
5982 *p
|= DREX_OC1_MASK
;
5985 /* Now the modrm byte and sib byte (if present). */
5986 if (i
.tm
.opcode_modifier
.modrm
)
5988 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5991 /* If i.rm.regmem == ESP (4)
5992 && i.rm.mode != (Register mode)
5994 ==> need second modrm byte. */
5995 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5997 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5998 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6000 | i
.sib
.scale
<< 6));
6003 /* Write the DREX byte if needed. */
6004 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6007 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6009 /* Encode the OC0 bit if this encoding has multiple
6011 if ((i
.tm
.opcode_modifier
.drex
6012 || i
.tm
.opcode_modifier
.drexv
)
6013 && DREX_OC0 (i
.tm
.extension_opcode
))
6014 *p
|= DREX_OC0_MASK
;
6017 if (i
.disp_operands
)
6018 output_disp (insn_start_frag
, insn_start_off
);
6021 output_imm (insn_start_frag
, insn_start_off
);
6027 pi ("" /*line*/, &i
);
6029 #endif /* DEBUG386 */
6032 /* Return the size of the displacement operand N. */
6035 disp_size (unsigned int n
)
6038 if (i
.types
[n
].bitfield
.disp64
)
6040 else if (i
.types
[n
].bitfield
.disp8
)
6042 else if (i
.types
[n
].bitfield
.disp16
)
6047 /* Return the size of the immediate operand N. */
6050 imm_size (unsigned int n
)
6053 if (i
.types
[n
].bitfield
.imm64
)
6055 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6057 else if (i
.types
[n
].bitfield
.imm16
)
6063 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6068 for (n
= 0; n
< i
.operands
; n
++)
6070 if (operand_type_check (i
.types
[n
], disp
))
6072 if (i
.op
[n
].disps
->X_op
== O_constant
)
6074 int size
= disp_size (n
);
6077 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6079 p
= frag_more (size
);
6080 md_number_to_chars (p
, val
, size
);
6084 enum bfd_reloc_code_real reloc_type
;
6085 int size
= disp_size (n
);
6086 int sign
= i
.types
[n
].bitfield
.disp32s
;
6087 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6089 /* We can't have 8 bit displacement here. */
6090 assert (!i
.types
[n
].bitfield
.disp8
);
6092 /* The PC relative address is computed relative
6093 to the instruction boundary, so in case immediate
6094 fields follows, we need to adjust the value. */
6095 if (pcrel
&& i
.imm_operands
)
6100 for (n1
= 0; n1
< i
.operands
; n1
++)
6101 if (operand_type_check (i
.types
[n1
], imm
))
6103 /* Only one immediate is allowed for PC
6104 relative address. */
6107 i
.op
[n
].disps
->X_add_number
-= sz
;
6109 /* We should find the immediate. */
6113 p
= frag_more (size
);
6114 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6116 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6117 && (((reloc_type
== BFD_RELOC_32
6118 || reloc_type
== BFD_RELOC_X86_64_32S
6119 || (reloc_type
== BFD_RELOC_64
6121 && (i
.op
[n
].disps
->X_op
== O_symbol
6122 || (i
.op
[n
].disps
->X_op
== O_add
6123 && ((symbol_get_value_expression
6124 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6126 || reloc_type
== BFD_RELOC_32_PCREL
))
6130 if (insn_start_frag
== frag_now
)
6131 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6136 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6137 for (fr
= insn_start_frag
->fr_next
;
6138 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6140 add
+= p
- frag_now
->fr_literal
;
6145 reloc_type
= BFD_RELOC_386_GOTPC
;
6146 i
.op
[n
].imms
->X_add_number
+= add
;
6148 else if (reloc_type
== BFD_RELOC_64
)
6149 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6151 /* Don't do the adjustment for x86-64, as there
6152 the pcrel addressing is relative to the _next_
6153 insn, and that is taken care of in other code. */
6154 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6156 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6157 i
.op
[n
].disps
, pcrel
, reloc_type
);
6164 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6169 for (n
= 0; n
< i
.operands
; n
++)
6171 if (operand_type_check (i
.types
[n
], imm
))
6173 if (i
.op
[n
].imms
->X_op
== O_constant
)
6175 int size
= imm_size (n
);
6178 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6180 p
= frag_more (size
);
6181 md_number_to_chars (p
, val
, size
);
6185 /* Not absolute_section.
6186 Need a 32-bit fixup (don't support 8bit
6187 non-absolute imms). Try to support other
6189 enum bfd_reloc_code_real reloc_type
;
6190 int size
= imm_size (n
);
6193 if (i
.types
[n
].bitfield
.imm32s
6194 && (i
.suffix
== QWORD_MNEM_SUFFIX
6195 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6200 p
= frag_more (size
);
6201 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6203 /* This is tough to explain. We end up with this one if we
6204 * have operands that look like
6205 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6206 * obtain the absolute address of the GOT, and it is strongly
6207 * preferable from a performance point of view to avoid using
6208 * a runtime relocation for this. The actual sequence of
6209 * instructions often look something like:
6214 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6216 * The call and pop essentially return the absolute address
6217 * of the label .L66 and store it in %ebx. The linker itself
6218 * will ultimately change the first operand of the addl so
6219 * that %ebx points to the GOT, but to keep things simple, the
6220 * .o file must have this operand set so that it generates not
6221 * the absolute address of .L66, but the absolute address of
6222 * itself. This allows the linker itself simply treat a GOTPC
6223 * relocation as asking for a pcrel offset to the GOT to be
6224 * added in, and the addend of the relocation is stored in the
6225 * operand field for the instruction itself.
6227 * Our job here is to fix the operand so that it would add
6228 * the correct offset so that %ebx would point to itself. The
6229 * thing that is tricky is that .-.L66 will point to the
6230 * beginning of the instruction, so we need to further modify
6231 * the operand so that it will point to itself. There are
6232 * other cases where you have something like:
6234 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6236 * and here no correction would be required. Internally in
6237 * the assembler we treat operands of this form as not being
6238 * pcrel since the '.' is explicitly mentioned, and I wonder
6239 * whether it would simplify matters to do it this way. Who
6240 * knows. In earlier versions of the PIC patches, the
6241 * pcrel_adjust field was used to store the correction, but
6242 * since the expression is not pcrel, I felt it would be
6243 * confusing to do it this way. */
6245 if ((reloc_type
== BFD_RELOC_32
6246 || reloc_type
== BFD_RELOC_X86_64_32S
6247 || reloc_type
== BFD_RELOC_64
)
6249 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6250 && (i
.op
[n
].imms
->X_op
== O_symbol
6251 || (i
.op
[n
].imms
->X_op
== O_add
6252 && ((symbol_get_value_expression
6253 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6258 if (insn_start_frag
== frag_now
)
6259 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6264 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6265 for (fr
= insn_start_frag
->fr_next
;
6266 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6268 add
+= p
- frag_now
->fr_literal
;
6272 reloc_type
= BFD_RELOC_386_GOTPC
;
6274 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6276 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6277 i
.op
[n
].imms
->X_add_number
+= add
;
6279 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6280 i
.op
[n
].imms
, 0, reloc_type
);
6286 /* x86_cons_fix_new is called via the expression parsing code when a
6287 reloc is needed. We use this hook to get the correct .got reloc. */
6288 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6289 static int cons_sign
= -1;
6292 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6295 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6297 got_reloc
= NO_RELOC
;
6300 if (exp
->X_op
== O_secrel
)
6302 exp
->X_op
= O_symbol
;
6303 r
= BFD_RELOC_32_SECREL
;
6307 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6310 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6311 # define lex_got(reloc, adjust, types) NULL
6313 /* Parse operands of the form
6314 <symbol>@GOTOFF+<nnn>
6315 and similar .plt or .got references.
6317 If we find one, set up the correct relocation in RELOC and copy the
6318 input string, minus the `@GOTOFF' into a malloc'd buffer for
6319 parsing by the calling routine. Return this buffer, and if ADJUST
6320 is non-null set it to the length of the string we removed from the
6321 input line. Otherwise return NULL. */
6323 lex_got (enum bfd_reloc_code_real
*reloc
,
6325 i386_operand_type
*types
)
6327 /* Some of the relocations depend on the size of what field is to
6328 be relocated. But in our callers i386_immediate and i386_displacement
6329 we don't yet know the operand size (this will be set by insn
6330 matching). Hence we record the word32 relocation here,
6331 and adjust the reloc according to the real size in reloc(). */
6332 static const struct {
6334 const enum bfd_reloc_code_real rel
[2];
6335 const i386_operand_type types64
;
6338 BFD_RELOC_X86_64_PLTOFF64
},
6339 OPERAND_TYPE_IMM64
},
6340 { "PLT", { BFD_RELOC_386_PLT32
,
6341 BFD_RELOC_X86_64_PLT32
},
6342 OPERAND_TYPE_IMM32_32S_DISP32
},
6344 BFD_RELOC_X86_64_GOTPLT64
},
6345 OPERAND_TYPE_IMM64_DISP64
},
6346 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6347 BFD_RELOC_X86_64_GOTOFF64
},
6348 OPERAND_TYPE_IMM64_DISP64
},
6350 BFD_RELOC_X86_64_GOTPCREL
},
6351 OPERAND_TYPE_IMM32_32S_DISP32
},
6352 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6353 BFD_RELOC_X86_64_TLSGD
},
6354 OPERAND_TYPE_IMM32_32S_DISP32
},
6355 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6357 OPERAND_TYPE_NONE
},
6359 BFD_RELOC_X86_64_TLSLD
},
6360 OPERAND_TYPE_IMM32_32S_DISP32
},
6361 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6362 BFD_RELOC_X86_64_GOTTPOFF
},
6363 OPERAND_TYPE_IMM32_32S_DISP32
},
6364 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6365 BFD_RELOC_X86_64_TPOFF32
},
6366 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6367 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6369 OPERAND_TYPE_NONE
},
6370 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6371 BFD_RELOC_X86_64_DTPOFF32
},
6373 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6374 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6376 OPERAND_TYPE_NONE
},
6377 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6379 OPERAND_TYPE_NONE
},
6380 { "GOT", { BFD_RELOC_386_GOT32
,
6381 BFD_RELOC_X86_64_GOT32
},
6382 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6383 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6384 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6385 OPERAND_TYPE_IMM32_32S_DISP32
},
6386 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6387 BFD_RELOC_X86_64_TLSDESC_CALL
},
6388 OPERAND_TYPE_IMM32_32S_DISP32
},
6396 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6397 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6400 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6404 len
= strlen (gotrel
[j
].str
);
6405 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6407 if (gotrel
[j
].rel
[object_64bit
] != 0)
6410 char *tmpbuf
, *past_reloc
;
6412 *reloc
= gotrel
[j
].rel
[object_64bit
];
6418 if (flag_code
!= CODE_64BIT
)
6420 types
->bitfield
.imm32
= 1;
6421 types
->bitfield
.disp32
= 1;
6424 *types
= gotrel
[j
].types64
;
6427 if (GOT_symbol
== NULL
)
6428 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6430 /* The length of the first part of our input line. */
6431 first
= cp
- input_line_pointer
;
6433 /* The second part goes from after the reloc token until
6434 (and including) an end_of_line char or comma. */
6435 past_reloc
= cp
+ 1 + len
;
6437 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6439 second
= cp
+ 1 - past_reloc
;
6441 /* Allocate and copy string. The trailing NUL shouldn't
6442 be necessary, but be safe. */
6443 tmpbuf
= xmalloc (first
+ second
+ 2);
6444 memcpy (tmpbuf
, input_line_pointer
, first
);
6445 if (second
!= 0 && *past_reloc
!= ' ')
6446 /* Replace the relocation token with ' ', so that
6447 errors like foo@GOTOFF1 will be detected. */
6448 tmpbuf
[first
++] = ' ';
6449 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6450 tmpbuf
[first
+ second
] = '\0';
6454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6455 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6460 /* Might be a symbol version string. Don't as_bad here. */
6465 x86_cons (expressionS
*exp
, int size
)
6467 if (size
== 4 || (object_64bit
&& size
== 8))
6469 /* Handle @GOTOFF and the like in an expression. */
6471 char *gotfree_input_line
;
6474 save
= input_line_pointer
;
6475 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6476 if (gotfree_input_line
)
6477 input_line_pointer
= gotfree_input_line
;
6481 if (gotfree_input_line
)
6483 /* expression () has merrily parsed up to the end of line,
6484 or a comma - in the wrong buffer. Transfer how far
6485 input_line_pointer has moved to the right buffer. */
6486 input_line_pointer
= (save
6487 + (input_line_pointer
- gotfree_input_line
)
6489 free (gotfree_input_line
);
6490 if (exp
->X_op
== O_constant
6491 || exp
->X_op
== O_absent
6492 || exp
->X_op
== O_illegal
6493 || exp
->X_op
== O_register
6494 || exp
->X_op
== O_big
)
6496 char c
= *input_line_pointer
;
6497 *input_line_pointer
= 0;
6498 as_bad (_("missing or invalid expression `%s'"), save
);
6499 *input_line_pointer
= c
;
6508 static void signed_cons (int size
)
6510 if (flag_code
== CODE_64BIT
)
6518 pe_directive_secrel (dummy
)
6519 int dummy ATTRIBUTE_UNUSED
;
6526 if (exp
.X_op
== O_symbol
)
6527 exp
.X_op
= O_secrel
;
6529 emit_expr (&exp
, 4);
6531 while (*input_line_pointer
++ == ',');
6533 input_line_pointer
--;
6534 demand_empty_rest_of_line ();
6539 i386_immediate (char *imm_start
)
6541 char *save_input_line_pointer
;
6542 char *gotfree_input_line
;
6545 i386_operand_type types
;
6547 operand_type_set (&types
, ~0);
6549 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6551 as_bad (_("at most %d immediate operands are allowed"),
6552 MAX_IMMEDIATE_OPERANDS
);
6556 exp
= &im_expressions
[i
.imm_operands
++];
6557 i
.op
[this_operand
].imms
= exp
;
6559 if (is_space_char (*imm_start
))
6562 save_input_line_pointer
= input_line_pointer
;
6563 input_line_pointer
= imm_start
;
6565 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6566 if (gotfree_input_line
)
6567 input_line_pointer
= gotfree_input_line
;
6569 exp_seg
= expression (exp
);
6572 if (*input_line_pointer
)
6573 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6575 input_line_pointer
= save_input_line_pointer
;
6576 if (gotfree_input_line
)
6577 free (gotfree_input_line
);
6579 if (exp
->X_op
== O_absent
6580 || exp
->X_op
== O_illegal
6581 || exp
->X_op
== O_big
6582 || (gotfree_input_line
6583 && (exp
->X_op
== O_constant
6584 || exp
->X_op
== O_register
)))
6586 as_bad (_("missing or invalid immediate expression `%s'"),
6590 else if (exp
->X_op
== O_constant
)
6592 /* Size it properly later. */
6593 i
.types
[this_operand
].bitfield
.imm64
= 1;
6594 /* If BFD64, sign extend val. */
6595 if (!use_rela_relocations
6596 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6598 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6600 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6601 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6602 && exp_seg
!= absolute_section
6603 && exp_seg
!= text_section
6604 && exp_seg
!= data_section
6605 && exp_seg
!= bss_section
6606 && exp_seg
!= undefined_section
6607 && !bfd_is_com_section (exp_seg
))
6609 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6613 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6615 as_bad (_("illegal immediate register operand %s"), imm_start
);
6620 /* This is an address. The size of the address will be
6621 determined later, depending on destination register,
6622 suffix, or the default for the section. */
6623 i
.types
[this_operand
].bitfield
.imm8
= 1;
6624 i
.types
[this_operand
].bitfield
.imm16
= 1;
6625 i
.types
[this_operand
].bitfield
.imm32
= 1;
6626 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6627 i
.types
[this_operand
].bitfield
.imm64
= 1;
6628 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6636 i386_scale (char *scale
)
6639 char *save
= input_line_pointer
;
6641 input_line_pointer
= scale
;
6642 val
= get_absolute_expression ();
6647 i
.log2_scale_factor
= 0;
6650 i
.log2_scale_factor
= 1;
6653 i
.log2_scale_factor
= 2;
6656 i
.log2_scale_factor
= 3;
6660 char sep
= *input_line_pointer
;
6662 *input_line_pointer
= '\0';
6663 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6665 *input_line_pointer
= sep
;
6666 input_line_pointer
= save
;
6670 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6672 as_warn (_("scale factor of %d without an index register"),
6673 1 << i
.log2_scale_factor
);
6674 i
.log2_scale_factor
= 0;
6676 scale
= input_line_pointer
;
6677 input_line_pointer
= save
;
6682 i386_displacement (char *disp_start
, char *disp_end
)
6686 char *save_input_line_pointer
;
6687 char *gotfree_input_line
;
6689 i386_operand_type bigdisp
, types
= anydisp
;
6692 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6694 as_bad (_("at most %d displacement operands are allowed"),
6695 MAX_MEMORY_OPERANDS
);
6699 operand_type_set (&bigdisp
, 0);
6700 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6701 || (!current_templates
->start
->opcode_modifier
.jump
6702 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6704 bigdisp
.bitfield
.disp32
= 1;
6705 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6706 if (flag_code
== CODE_64BIT
)
6710 bigdisp
.bitfield
.disp32s
= 1;
6711 bigdisp
.bitfield
.disp64
= 1;
6714 else if ((flag_code
== CODE_16BIT
) ^ override
)
6716 bigdisp
.bitfield
.disp32
= 0;
6717 bigdisp
.bitfield
.disp16
= 1;
6722 /* For PC-relative branches, the width of the displacement
6723 is dependent upon data size, not address size. */
6724 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6725 if (flag_code
== CODE_64BIT
)
6727 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6728 bigdisp
.bitfield
.disp16
= 1;
6731 bigdisp
.bitfield
.disp32
= 1;
6732 bigdisp
.bitfield
.disp32s
= 1;
6738 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6740 : LONG_MNEM_SUFFIX
));
6741 bigdisp
.bitfield
.disp32
= 1;
6742 if ((flag_code
== CODE_16BIT
) ^ override
)
6744 bigdisp
.bitfield
.disp32
= 0;
6745 bigdisp
.bitfield
.disp16
= 1;
6749 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6752 exp
= &disp_expressions
[i
.disp_operands
];
6753 i
.op
[this_operand
].disps
= exp
;
6755 save_input_line_pointer
= input_line_pointer
;
6756 input_line_pointer
= disp_start
;
6757 END_STRING_AND_SAVE (disp_end
);
6759 #ifndef GCC_ASM_O_HACK
6760 #define GCC_ASM_O_HACK 0
6763 END_STRING_AND_SAVE (disp_end
+ 1);
6764 if (i
.types
[this_operand
].bitfield
.baseIndex
6765 && displacement_string_end
[-1] == '+')
6767 /* This hack is to avoid a warning when using the "o"
6768 constraint within gcc asm statements.
6771 #define _set_tssldt_desc(n,addr,limit,type) \
6772 __asm__ __volatile__ ( \
6774 "movw %w1,2+%0\n\t" \
6776 "movb %b1,4+%0\n\t" \
6777 "movb %4,5+%0\n\t" \
6778 "movb $0,6+%0\n\t" \
6779 "movb %h1,7+%0\n\t" \
6781 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6783 This works great except that the output assembler ends
6784 up looking a bit weird if it turns out that there is
6785 no offset. You end up producing code that looks like:
6798 So here we provide the missing zero. */
6800 *displacement_string_end
= '0';
6803 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6804 if (gotfree_input_line
)
6805 input_line_pointer
= gotfree_input_line
;
6807 exp_seg
= expression (exp
);
6810 if (*input_line_pointer
)
6811 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6813 RESTORE_END_STRING (disp_end
+ 1);
6815 input_line_pointer
= save_input_line_pointer
;
6816 if (gotfree_input_line
)
6817 free (gotfree_input_line
);
6820 /* We do this to make sure that the section symbol is in
6821 the symbol table. We will ultimately change the relocation
6822 to be relative to the beginning of the section. */
6823 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6824 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6825 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6827 if (exp
->X_op
!= O_symbol
)
6830 if (S_IS_LOCAL (exp
->X_add_symbol
)
6831 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6832 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6833 exp
->X_op
= O_subtract
;
6834 exp
->X_op_symbol
= GOT_symbol
;
6835 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6836 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6837 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6838 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6840 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6843 else if (exp
->X_op
== O_absent
6844 || exp
->X_op
== O_illegal
6845 || exp
->X_op
== O_big
6846 || (gotfree_input_line
6847 && (exp
->X_op
== O_constant
6848 || exp
->X_op
== O_register
)))
6851 as_bad (_("missing or invalid displacement expression `%s'"),
6856 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6857 else if (exp
->X_op
!= O_constant
6858 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6859 && exp_seg
!= absolute_section
6860 && exp_seg
!= text_section
6861 && exp_seg
!= data_section
6862 && exp_seg
!= bss_section
6863 && exp_seg
!= undefined_section
6864 && !bfd_is_com_section (exp_seg
))
6866 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6871 RESTORE_END_STRING (disp_end
);
6873 /* Check if this is a displacement only operand. */
6874 bigdisp
= i
.types
[this_operand
];
6875 bigdisp
.bitfield
.disp8
= 0;
6876 bigdisp
.bitfield
.disp16
= 0;
6877 bigdisp
.bitfield
.disp32
= 0;
6878 bigdisp
.bitfield
.disp32s
= 0;
6879 bigdisp
.bitfield
.disp64
= 0;
6880 if (operand_type_all_zero (&bigdisp
))
6881 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6887 /* Make sure the memory operand we've been dealt is valid.
6888 Return 1 on success, 0 on a failure. */
6891 i386_index_check (const char *operand_string
)
6894 const char *kind
= "base/index";
6895 #if INFER_ADDR_PREFIX
6901 if (current_templates
->start
->opcode_modifier
.isstring
6902 && !current_templates
->start
->opcode_modifier
.immext
6903 && (current_templates
->end
[-1].opcode_modifier
.isstring
6906 /* Memory operands of string insns are special in that they only allow
6907 a single register (rDI, rSI, or rBX) as their memory address. */
6908 unsigned int expected
;
6910 kind
= "string address";
6912 if (current_templates
->start
->opcode_modifier
.w
)
6914 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6916 if (!type
.bitfield
.baseindex
6917 || ((!i
.mem_operands
!= !intel_syntax
)
6918 && current_templates
->end
[-1].operand_types
[1]
6919 .bitfield
.baseindex
))
6920 type
= current_templates
->end
[-1].operand_types
[1];
6921 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6924 expected
= 3 /* rBX */;
6926 if (!i
.base_reg
|| i
.index_reg
6927 || operand_type_check (i
.types
[this_operand
], disp
))
6929 else if (!(flag_code
== CODE_64BIT
6930 ? i
.prefix
[ADDR_PREFIX
]
6931 ? i
.base_reg
->reg_type
.bitfield
.reg32
6932 : i
.base_reg
->reg_type
.bitfield
.reg64
6933 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6934 ? i
.base_reg
->reg_type
.bitfield
.reg32
6935 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6937 else if (i
.base_reg
->reg_num
!= expected
)
6944 for (j
= 0; j
< i386_regtab_size
; ++j
)
6945 if ((flag_code
== CODE_64BIT
6946 ? i
.prefix
[ADDR_PREFIX
]
6947 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6948 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6949 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6950 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6951 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6952 && i386_regtab
[j
].reg_num
== expected
)
6954 assert (j
< i386_regtab_size
);
6955 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6957 intel_syntax
? '[' : '(',
6959 i386_regtab
[j
].reg_name
,
6960 intel_syntax
? ']' : ')');
6964 else if (flag_code
== CODE_64BIT
)
6967 && ((i
.prefix
[ADDR_PREFIX
] == 0
6968 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6969 || (i
.prefix
[ADDR_PREFIX
]
6970 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6972 || i
.base_reg
->reg_num
!=
6973 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6975 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6976 || (i
.prefix
[ADDR_PREFIX
] == 0
6977 && i
.index_reg
->reg_num
!= RegRiz
6978 && !i
.index_reg
->reg_type
.bitfield
.reg64
6980 || (i
.prefix
[ADDR_PREFIX
]
6981 && i
.index_reg
->reg_num
!= RegEiz
6982 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6987 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6991 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6992 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6994 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6995 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6997 && i
.base_reg
->reg_num
< 6
6998 && i
.index_reg
->reg_num
>= 6
6999 && i
.log2_scale_factor
== 0))))
7006 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7008 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7009 && i
.index_reg
->reg_num
!= RegEiz
)
7010 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7016 #if INFER_ADDR_PREFIX
7017 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7019 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7021 /* Change the size of any displacement too. At most one of
7022 Disp16 or Disp32 is set.
7023 FIXME. There doesn't seem to be any real need for separate
7024 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7025 Removing them would probably clean up the code quite a lot. */
7026 if (flag_code
!= CODE_64BIT
7027 && (i
.types
[this_operand
].bitfield
.disp16
7028 || i
.types
[this_operand
].bitfield
.disp32
))
7029 i
.types
[this_operand
]
7030 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7035 as_bad (_("`%s' is not a valid %s expression"),
7040 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7042 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7043 ? flag_code
== CODE_32BIT
7052 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7056 i386_att_operand (char *operand_string
)
7060 char *op_string
= operand_string
;
7062 if (is_space_char (*op_string
))
7065 /* We check for an absolute prefix (differentiating,
7066 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7067 if (*op_string
== ABSOLUTE_PREFIX
)
7070 if (is_space_char (*op_string
))
7072 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7075 /* Check if operand is a register. */
7076 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7078 i386_operand_type temp
;
7080 /* Check for a segment override by searching for ':' after a
7081 segment register. */
7083 if (is_space_char (*op_string
))
7085 if (*op_string
== ':'
7086 && (r
->reg_type
.bitfield
.sreg2
7087 || r
->reg_type
.bitfield
.sreg3
))
7092 i
.seg
[i
.mem_operands
] = &es
;
7095 i
.seg
[i
.mem_operands
] = &cs
;
7098 i
.seg
[i
.mem_operands
] = &ss
;
7101 i
.seg
[i
.mem_operands
] = &ds
;
7104 i
.seg
[i
.mem_operands
] = &fs
;
7107 i
.seg
[i
.mem_operands
] = &gs
;
7111 /* Skip the ':' and whitespace. */
7113 if (is_space_char (*op_string
))
7116 if (!is_digit_char (*op_string
)
7117 && !is_identifier_char (*op_string
)
7118 && *op_string
!= '('
7119 && *op_string
!= ABSOLUTE_PREFIX
)
7121 as_bad (_("bad memory operand `%s'"), op_string
);
7124 /* Handle case of %es:*foo. */
7125 if (*op_string
== ABSOLUTE_PREFIX
)
7128 if (is_space_char (*op_string
))
7130 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7132 goto do_memory_reference
;
7136 as_bad (_("junk `%s' after register"), op_string
);
7140 temp
.bitfield
.baseindex
= 0;
7141 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7143 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7144 i
.op
[this_operand
].regs
= r
;
7147 else if (*op_string
== REGISTER_PREFIX
)
7149 as_bad (_("bad register name `%s'"), op_string
);
7152 else if (*op_string
== IMMEDIATE_PREFIX
)
7155 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7157 as_bad (_("immediate operand illegal with absolute jump"));
7160 if (!i386_immediate (op_string
))
7163 else if (is_digit_char (*op_string
)
7164 || is_identifier_char (*op_string
)
7165 || *op_string
== '(')
7167 /* This is a memory reference of some sort. */
7170 /* Start and end of displacement string expression (if found). */
7171 char *displacement_string_start
;
7172 char *displacement_string_end
;
7174 do_memory_reference
:
7175 if ((i
.mem_operands
== 1
7176 && !current_templates
->start
->opcode_modifier
.isstring
)
7177 || i
.mem_operands
== 2)
7179 as_bad (_("too many memory references for `%s'"),
7180 current_templates
->start
->name
);
7184 /* Check for base index form. We detect the base index form by
7185 looking for an ')' at the end of the operand, searching
7186 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7188 base_string
= op_string
+ strlen (op_string
);
7191 if (is_space_char (*base_string
))
7194 /* If we only have a displacement, set-up for it to be parsed later. */
7195 displacement_string_start
= op_string
;
7196 displacement_string_end
= base_string
+ 1;
7198 if (*base_string
== ')')
7201 unsigned int parens_balanced
= 1;
7202 /* We've already checked that the number of left & right ()'s are
7203 equal, so this loop will not be infinite. */
7207 if (*base_string
== ')')
7209 if (*base_string
== '(')
7212 while (parens_balanced
);
7214 temp_string
= base_string
;
7216 /* Skip past '(' and whitespace. */
7218 if (is_space_char (*base_string
))
7221 if (*base_string
== ','
7222 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7225 displacement_string_end
= temp_string
;
7227 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7231 base_string
= end_op
;
7232 if (is_space_char (*base_string
))
7236 /* There may be an index reg or scale factor here. */
7237 if (*base_string
== ',')
7240 if (is_space_char (*base_string
))
7243 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7246 base_string
= end_op
;
7247 if (is_space_char (*base_string
))
7249 if (*base_string
== ',')
7252 if (is_space_char (*base_string
))
7255 else if (*base_string
!= ')')
7257 as_bad (_("expecting `,' or `)' "
7258 "after index register in `%s'"),
7263 else if (*base_string
== REGISTER_PREFIX
)
7265 as_bad (_("bad register name `%s'"), base_string
);
7269 /* Check for scale factor. */
7270 if (*base_string
!= ')')
7272 char *end_scale
= i386_scale (base_string
);
7277 base_string
= end_scale
;
7278 if (is_space_char (*base_string
))
7280 if (*base_string
!= ')')
7282 as_bad (_("expecting `)' "
7283 "after scale factor in `%s'"),
7288 else if (!i
.index_reg
)
7290 as_bad (_("expecting index register or scale factor "
7291 "after `,'; got '%c'"),
7296 else if (*base_string
!= ')')
7298 as_bad (_("expecting `,' or `)' "
7299 "after base register in `%s'"),
7304 else if (*base_string
== REGISTER_PREFIX
)
7306 as_bad (_("bad register name `%s'"), base_string
);
7311 /* If there's an expression beginning the operand, parse it,
7312 assuming displacement_string_start and
7313 displacement_string_end are meaningful. */
7314 if (displacement_string_start
!= displacement_string_end
)
7316 if (!i386_displacement (displacement_string_start
,
7317 displacement_string_end
))
7321 /* Special case for (%dx) while doing input/output op. */
7323 && operand_type_equal (&i
.base_reg
->reg_type
,
7324 ®16_inoutportreg
)
7326 && i
.log2_scale_factor
== 0
7327 && i
.seg
[i
.mem_operands
] == 0
7328 && !operand_type_check (i
.types
[this_operand
], disp
))
7330 i
.types
[this_operand
] = inoutportreg
;
7334 if (i386_index_check (operand_string
) == 0)
7336 i
.types
[this_operand
].bitfield
.mem
= 1;
7341 /* It's not a memory operand; argh! */
7342 as_bad (_("invalid char %s beginning operand %d `%s'"),
7343 output_invalid (*op_string
),
7348 return 1; /* Normal return. */
7351 /* md_estimate_size_before_relax()
7353 Called just before relax() for rs_machine_dependent frags. The x86
7354 assembler uses these frags to handle variable size jump
7357 Any symbol that is now undefined will not become defined.
7358 Return the correct fr_subtype in the frag.
7359 Return the initial "guess for variable size of frag" to caller.
7360 The guess is actually the growth beyond the fixed part. Whatever
7361 we do to grow the fixed or variable part contributes to our
7365 md_estimate_size_before_relax (fragP
, segment
)
7369 /* We've already got fragP->fr_subtype right; all we have to do is
7370 check for un-relaxable symbols. On an ELF system, we can't relax
7371 an externally visible symbol, because it may be overridden by a
7373 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7376 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7377 || S_IS_WEAK (fragP
->fr_symbol
)))
7381 /* Symbol is undefined in this segment, or we need to keep a
7382 reloc so that weak symbols can be overridden. */
7383 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7384 enum bfd_reloc_code_real reloc_type
;
7385 unsigned char *opcode
;
7388 if (fragP
->fr_var
!= NO_RELOC
)
7389 reloc_type
= fragP
->fr_var
;
7391 reloc_type
= BFD_RELOC_16_PCREL
;
7393 reloc_type
= BFD_RELOC_32_PCREL
;
7395 old_fr_fix
= fragP
->fr_fix
;
7396 opcode
= (unsigned char *) fragP
->fr_opcode
;
7398 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7401 /* Make jmp (0xeb) a (d)word displacement jump. */
7403 fragP
->fr_fix
+= size
;
7404 fix_new (fragP
, old_fr_fix
, size
,
7406 fragP
->fr_offset
, 1,
7412 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7414 /* Negate the condition, and branch past an
7415 unconditional jump. */
7418 /* Insert an unconditional jump. */
7420 /* We added two extra opcode bytes, and have a two byte
7422 fragP
->fr_fix
+= 2 + 2;
7423 fix_new (fragP
, old_fr_fix
+ 2, 2,
7425 fragP
->fr_offset
, 1,
7432 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7437 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7439 fragP
->fr_offset
, 1,
7441 fixP
->fx_signed
= 1;
7445 /* This changes the byte-displacement jump 0x7N
7446 to the (d)word-displacement jump 0x0f,0x8N. */
7447 opcode
[1] = opcode
[0] + 0x10;
7448 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7449 /* We've added an opcode byte. */
7450 fragP
->fr_fix
+= 1 + size
;
7451 fix_new (fragP
, old_fr_fix
+ 1, size
,
7453 fragP
->fr_offset
, 1,
7458 BAD_CASE (fragP
->fr_subtype
);
7462 return fragP
->fr_fix
- old_fr_fix
;
7465 /* Guess size depending on current relax state. Initially the relax
7466 state will correspond to a short jump and we return 1, because
7467 the variable part of the frag (the branch offset) is one byte
7468 long. However, we can relax a section more than once and in that
7469 case we must either set fr_subtype back to the unrelaxed state,
7470 or return the value for the appropriate branch. */
7471 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7474 /* Called after relax() is finished.
7476 In: Address of frag.
7477 fr_type == rs_machine_dependent.
7478 fr_subtype is what the address relaxed to.
7480 Out: Any fixSs and constants are set up.
7481 Caller will turn frag into a ".space 0". */
7484 md_convert_frag (abfd
, sec
, fragP
)
7485 bfd
*abfd ATTRIBUTE_UNUSED
;
7486 segT sec ATTRIBUTE_UNUSED
;
7489 unsigned char *opcode
;
7490 unsigned char *where_to_put_displacement
= NULL
;
7491 offsetT target_address
;
7492 offsetT opcode_address
;
7493 unsigned int extension
= 0;
7494 offsetT displacement_from_opcode_start
;
7496 opcode
= (unsigned char *) fragP
->fr_opcode
;
7498 /* Address we want to reach in file space. */
7499 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7501 /* Address opcode resides at in file space. */
7502 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7504 /* Displacement from opcode start to fill into instruction. */
7505 displacement_from_opcode_start
= target_address
- opcode_address
;
7507 if ((fragP
->fr_subtype
& BIG
) == 0)
7509 /* Don't have to change opcode. */
7510 extension
= 1; /* 1 opcode + 1 displacement */
7511 where_to_put_displacement
= &opcode
[1];
7515 if (no_cond_jump_promotion
7516 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7517 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7518 _("long jump required"));
7520 switch (fragP
->fr_subtype
)
7522 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7523 extension
= 4; /* 1 opcode + 4 displacement */
7525 where_to_put_displacement
= &opcode
[1];
7528 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7529 extension
= 2; /* 1 opcode + 2 displacement */
7531 where_to_put_displacement
= &opcode
[1];
7534 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7535 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7536 extension
= 5; /* 2 opcode + 4 displacement */
7537 opcode
[1] = opcode
[0] + 0x10;
7538 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7539 where_to_put_displacement
= &opcode
[2];
7542 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7543 extension
= 3; /* 2 opcode + 2 displacement */
7544 opcode
[1] = opcode
[0] + 0x10;
7545 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7546 where_to_put_displacement
= &opcode
[2];
7549 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7554 where_to_put_displacement
= &opcode
[3];
7558 BAD_CASE (fragP
->fr_subtype
);
7563 /* If size if less then four we are sure that the operand fits,
7564 but if it's 4, then it could be that the displacement is larger
7566 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7568 && ((addressT
) (displacement_from_opcode_start
- extension
7569 + ((addressT
) 1 << 31))
7570 > (((addressT
) 2 << 31) - 1)))
7572 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7573 _("jump target out of range"));
7574 /* Make us emit 0. */
7575 displacement_from_opcode_start
= extension
;
7577 /* Now put displacement after opcode. */
7578 md_number_to_chars ((char *) where_to_put_displacement
,
7579 (valueT
) (displacement_from_opcode_start
- extension
),
7580 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7581 fragP
->fr_fix
+= extension
;
7584 /* Apply a fixup (fixS) to segment data, once it has been determined
7585 by our caller that we have all the info we need to fix it up.
7587 On the 386, immediates, displacements, and data pointers are all in
7588 the same (little-endian) format, so we don't need to care about which
7592 md_apply_fix (fixP
, valP
, seg
)
7593 /* The fix we're to put in. */
7595 /* Pointer to the value of the bits. */
7597 /* Segment fix is from. */
7598 segT seg ATTRIBUTE_UNUSED
;
7600 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7601 valueT value
= *valP
;
7603 #if !defined (TE_Mach)
7606 switch (fixP
->fx_r_type
)
7612 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7615 case BFD_RELOC_X86_64_32S
:
7616 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7619 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7622 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7627 if (fixP
->fx_addsy
!= NULL
7628 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7629 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7630 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7631 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7632 && !use_rela_relocations
)
7634 /* This is a hack. There should be a better way to handle this.
7635 This covers for the fact that bfd_install_relocation will
7636 subtract the current location (for partial_inplace, PC relative
7637 relocations); see more below. */
7641 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7644 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7646 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7649 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7652 || (symbol_section_p (fixP
->fx_addsy
)
7653 && sym_seg
!= absolute_section
))
7654 && !generic_force_reloc (fixP
))
7656 /* Yes, we add the values in twice. This is because
7657 bfd_install_relocation subtracts them out again. I think
7658 bfd_install_relocation is broken, but I don't dare change
7660 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7664 #if defined (OBJ_COFF) && defined (TE_PE)
7665 /* For some reason, the PE format does not store a
7666 section address offset for a PC relative symbol. */
7667 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7668 || S_IS_WEAK (fixP
->fx_addsy
))
7669 value
+= md_pcrel_from (fixP
);
7673 /* Fix a few things - the dynamic linker expects certain values here,
7674 and we must not disappoint it. */
7675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7676 if (IS_ELF
&& fixP
->fx_addsy
)
7677 switch (fixP
->fx_r_type
)
7679 case BFD_RELOC_386_PLT32
:
7680 case BFD_RELOC_X86_64_PLT32
:
7681 /* Make the jump instruction point to the address of the operand. At
7682 runtime we merely add the offset to the actual PLT entry. */
7686 case BFD_RELOC_386_TLS_GD
:
7687 case BFD_RELOC_386_TLS_LDM
:
7688 case BFD_RELOC_386_TLS_IE_32
:
7689 case BFD_RELOC_386_TLS_IE
:
7690 case BFD_RELOC_386_TLS_GOTIE
:
7691 case BFD_RELOC_386_TLS_GOTDESC
:
7692 case BFD_RELOC_X86_64_TLSGD
:
7693 case BFD_RELOC_X86_64_TLSLD
:
7694 case BFD_RELOC_X86_64_GOTTPOFF
:
7695 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7696 value
= 0; /* Fully resolved at runtime. No addend. */
7698 case BFD_RELOC_386_TLS_LE
:
7699 case BFD_RELOC_386_TLS_LDO_32
:
7700 case BFD_RELOC_386_TLS_LE_32
:
7701 case BFD_RELOC_X86_64_DTPOFF32
:
7702 case BFD_RELOC_X86_64_DTPOFF64
:
7703 case BFD_RELOC_X86_64_TPOFF32
:
7704 case BFD_RELOC_X86_64_TPOFF64
:
7705 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7708 case BFD_RELOC_386_TLS_DESC_CALL
:
7709 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7710 value
= 0; /* Fully resolved at runtime. No addend. */
7711 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7715 case BFD_RELOC_386_GOT32
:
7716 case BFD_RELOC_X86_64_GOT32
:
7717 value
= 0; /* Fully resolved at runtime. No addend. */
7720 case BFD_RELOC_VTABLE_INHERIT
:
7721 case BFD_RELOC_VTABLE_ENTRY
:
7728 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7730 #endif /* !defined (TE_Mach) */
7732 /* Are we finished with this relocation now? */
7733 if (fixP
->fx_addsy
== NULL
)
7735 else if (use_rela_relocations
)
7737 fixP
->fx_no_overflow
= 1;
7738 /* Remember value for tc_gen_reloc. */
7739 fixP
->fx_addnumber
= value
;
7743 md_number_to_chars (p
, value
, fixP
->fx_size
);
7747 md_atof (int type
, char *litP
, int *sizeP
)
7749 /* This outputs the LITTLENUMs in REVERSE order;
7750 in accord with the bigendian 386. */
7751 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7754 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7757 output_invalid (int c
)
7760 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7763 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7764 "(0x%x)", (unsigned char) c
);
7765 return output_invalid_buf
;
7768 /* REG_STRING starts *before* REGISTER_PREFIX. */
7770 static const reg_entry
*
7771 parse_real_register (char *reg_string
, char **end_op
)
7773 char *s
= reg_string
;
7775 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7778 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7779 if (*s
== REGISTER_PREFIX
)
7782 if (is_space_char (*s
))
7786 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7788 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7789 return (const reg_entry
*) NULL
;
7793 /* For naked regs, make sure that we are not dealing with an identifier.
7794 This prevents confusing an identifier like `eax_var' with register
7796 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7797 return (const reg_entry
*) NULL
;
7801 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7803 /* Handle floating point regs, allowing spaces in the (i) part. */
7804 if (r
== i386_regtab
/* %st is first entry of table */)
7806 if (is_space_char (*s
))
7811 if (is_space_char (*s
))
7813 if (*s
>= '0' && *s
<= '7')
7817 if (is_space_char (*s
))
7822 r
= hash_find (reg_hash
, "st(0)");
7827 /* We have "%st(" then garbage. */
7828 return (const reg_entry
*) NULL
;
7832 if (r
== NULL
|| allow_pseudo_reg
)
7835 if (operand_type_all_zero (&r
->reg_type
))
7836 return (const reg_entry
*) NULL
;
7838 if ((r
->reg_type
.bitfield
.reg32
7839 || r
->reg_type
.bitfield
.sreg3
7840 || r
->reg_type
.bitfield
.control
7841 || r
->reg_type
.bitfield
.debug
7842 || r
->reg_type
.bitfield
.test
)
7843 && !cpu_arch_flags
.bitfield
.cpui386
)
7844 return (const reg_entry
*) NULL
;
7846 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7847 return (const reg_entry
*) NULL
;
7849 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7850 return (const reg_entry
*) NULL
;
7852 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7853 return (const reg_entry
*) NULL
;
7855 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7856 if (!allow_index_reg
7857 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7858 return (const reg_entry
*) NULL
;
7860 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7861 || r
->reg_type
.bitfield
.reg64
)
7862 && (!cpu_arch_flags
.bitfield
.cpulm
7863 || !operand_type_equal (&r
->reg_type
, &control
))
7864 && flag_code
!= CODE_64BIT
)
7865 return (const reg_entry
*) NULL
;
7867 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7868 return (const reg_entry
*) NULL
;
7873 /* REG_STRING starts *before* REGISTER_PREFIX. */
7875 static const reg_entry
*
7876 parse_register (char *reg_string
, char **end_op
)
7880 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7881 r
= parse_real_register (reg_string
, end_op
);
7886 char *save
= input_line_pointer
;
7890 input_line_pointer
= reg_string
;
7891 c
= get_symbol_end ();
7892 symbolP
= symbol_find (reg_string
);
7893 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7895 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7897 know (e
->X_op
== O_register
);
7898 know (e
->X_add_number
>= 0
7899 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7900 r
= i386_regtab
+ e
->X_add_number
;
7901 *end_op
= input_line_pointer
;
7903 *input_line_pointer
= c
;
7904 input_line_pointer
= save
;
7910 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7913 char *end
= input_line_pointer
;
7916 r
= parse_register (name
, &input_line_pointer
);
7917 if (r
&& end
<= input_line_pointer
)
7919 *nextcharP
= *input_line_pointer
;
7920 *input_line_pointer
= 0;
7921 e
->X_op
= O_register
;
7922 e
->X_add_number
= r
- i386_regtab
;
7925 input_line_pointer
= end
;
7931 md_operand (expressionS
*e
)
7933 if (*input_line_pointer
== REGISTER_PREFIX
)
7936 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7940 e
->X_op
= O_register
;
7941 e
->X_add_number
= r
- i386_regtab
;
7942 input_line_pointer
= end
;
7948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7949 const char *md_shortopts
= "kVQ:sqn";
7951 const char *md_shortopts
= "qn";
7954 #define OPTION_32 (OPTION_MD_BASE + 0)
7955 #define OPTION_64 (OPTION_MD_BASE + 1)
7956 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7957 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7958 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7959 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7960 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7961 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7962 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7963 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7964 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7965 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7967 struct option md_longopts
[] =
7969 {"32", no_argument
, NULL
, OPTION_32
},
7970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7971 {"64", no_argument
, NULL
, OPTION_64
},
7973 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7974 {"march", required_argument
, NULL
, OPTION_MARCH
},
7975 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7976 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7977 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7978 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7979 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7980 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7981 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7982 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7983 {NULL
, no_argument
, NULL
, 0}
7985 size_t md_longopts_size
= sizeof (md_longopts
);
7988 md_parse_option (int c
, char *arg
)
7996 optimize_align_code
= 0;
8003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8004 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8005 should be emitted or not. FIXME: Not implemented. */
8009 /* -V: SVR4 argument to print version ID. */
8011 print_version_id ();
8014 /* -k: Ignore for FreeBSD compatibility. */
8019 /* -s: On i386 Solaris, this tells the native assembler to use
8020 .stab instead of .stab.excl. We always use .stab anyhow. */
8023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8026 const char **list
, **l
;
8028 list
= bfd_target_list ();
8029 for (l
= list
; *l
!= NULL
; l
++)
8030 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8031 || strcmp (*l
, "coff-x86-64") == 0
8032 || strcmp (*l
, "pe-x86-64") == 0
8033 || strcmp (*l
, "pei-x86-64") == 0)
8035 default_arch
= "x86_64";
8039 as_fatal (_("No compiled in support for x86_64"));
8046 default_arch
= "i386";
8050 #ifdef SVR4_COMMENT_CHARS
8055 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8057 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8061 i386_comment_chars
= n
;
8067 arch
= xstrdup (arg
);
8071 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8072 next
= strchr (arch
, '+');
8075 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8077 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8080 cpu_arch_name
= cpu_arch
[i
].name
;
8081 cpu_sub_arch_name
= NULL
;
8082 cpu_arch_flags
= cpu_arch
[i
].flags
;
8083 cpu_arch_isa
= cpu_arch
[i
].type
;
8084 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8085 if (!cpu_arch_tune_set
)
8087 cpu_arch_tune
= cpu_arch_isa
;
8088 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8092 else if (*cpu_arch
[i
].name
== '.'
8093 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8095 /* ISA entension. */
8096 i386_cpu_flags flags
;
8097 flags
= cpu_flags_or (cpu_arch_flags
,
8099 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8101 if (cpu_sub_arch_name
)
8103 char *name
= cpu_sub_arch_name
;
8104 cpu_sub_arch_name
= concat (name
,
8106 (const char *) NULL
);
8110 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8111 cpu_arch_flags
= flags
;
8117 if (i
>= ARRAY_SIZE (cpu_arch
))
8118 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8122 while (next
!= NULL
);
8127 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8128 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8130 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8132 cpu_arch_tune_set
= 1;
8133 cpu_arch_tune
= cpu_arch
[i
].type
;
8134 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8138 if (i
>= ARRAY_SIZE (cpu_arch
))
8139 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8142 case OPTION_MMNEMONIC
:
8143 if (strcasecmp (arg
, "att") == 0)
8145 else if (strcasecmp (arg
, "intel") == 0)
8148 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8151 case OPTION_MSYNTAX
:
8152 if (strcasecmp (arg
, "att") == 0)
8154 else if (strcasecmp (arg
, "intel") == 0)
8157 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8160 case OPTION_MINDEX_REG
:
8161 allow_index_reg
= 1;
8164 case OPTION_MNAKED_REG
:
8165 allow_naked_reg
= 1;
8168 case OPTION_MOLD_GCC
:
8172 case OPTION_MSSE2AVX
:
8176 case OPTION_MSSE_CHECK
:
8177 if (strcasecmp (arg
, "error") == 0)
8178 sse_check
= sse_check_error
;
8179 else if (strcasecmp (arg
, "warning") == 0)
8180 sse_check
= sse_check_warning
;
8181 else if (strcasecmp (arg
, "none") == 0)
8182 sse_check
= sse_check_none
;
8184 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8194 md_show_usage (stream
)
8197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8198 fprintf (stream
, _("\
8200 -V print assembler version number\n\
8203 fprintf (stream
, _("\
8204 -n Do not optimize code alignment\n\
8205 -q quieten some warnings\n"));
8206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8207 fprintf (stream
, _("\
8210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8211 fprintf (stream
, _("\
8212 --32/--64 generate 32bit/64bit code\n"));
8214 #ifdef SVR4_COMMENT_CHARS
8215 fprintf (stream
, _("\
8216 --divide do not treat `/' as a comment character\n"));
8218 fprintf (stream
, _("\
8219 --divide ignored\n"));
8221 fprintf (stream
, _("\
8222 -march=CPU[,+EXTENSION...]\n\
8223 generate code for CPU and EXTENSION, CPU is one of:\n\
8224 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8225 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8226 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8227 generic32, generic64\n\
8228 EXTENSION is combination of:\n\
8229 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8230 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8231 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8232 fprintf (stream
, _("\
8233 -mtune=CPU optimize for CPU, CPU is one of:\n\
8234 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8235 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8236 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8237 generic32, generic64\n"));
8238 fprintf (stream
, _("\
8239 -msse2avx encode SSE instructions with VEX prefix\n"));
8240 fprintf (stream
, _("\
8241 -msse-check=[none|error|warning]\n\
8242 check SSE instructions\n"));
8243 fprintf (stream
, _("\
8244 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8245 fprintf (stream
, _("\
8246 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8247 fprintf (stream
, _("\
8248 -mindex-reg support pseudo index registers\n"));
8249 fprintf (stream
, _("\
8250 -mnaked-reg don't require `%%' prefix for registers\n"));
8251 fprintf (stream
, _("\
8252 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8255 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8256 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8258 /* Pick the target format to use. */
8261 i386_target_format (void)
8263 if (!strcmp (default_arch
, "x86_64"))
8265 set_code_flag (CODE_64BIT
);
8266 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8268 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8269 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8270 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8271 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8272 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8273 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8274 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8275 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8276 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8277 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8279 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8281 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8282 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8283 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8284 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8285 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8286 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8287 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8288 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8289 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8290 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8293 else if (!strcmp (default_arch
, "i386"))
8295 set_code_flag (CODE_32BIT
);
8296 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8298 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8299 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8300 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8302 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8304 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8305 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8306 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8310 as_fatal (_("Unknown architecture"));
8311 switch (OUTPUT_FLAVOR
)
8314 case bfd_target_coff_flavour
:
8315 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8318 #ifdef OBJ_MAYBE_AOUT
8319 case bfd_target_aout_flavour
:
8320 return AOUT_TARGET_FORMAT
;
8322 #ifdef OBJ_MAYBE_COFF
8323 case bfd_target_coff_flavour
:
8326 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8327 case bfd_target_elf_flavour
:
8329 if (flag_code
== CODE_64BIT
)
8332 use_rela_relocations
= 1;
8334 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8343 #endif /* OBJ_MAYBE_ more than one */
8345 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8347 i386_elf_emit_arch_note (void)
8349 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8352 asection
*seg
= now_seg
;
8353 subsegT subseg
= now_subseg
;
8354 Elf_Internal_Note i_note
;
8355 Elf_External_Note e_note
;
8356 asection
*note_secp
;
8359 /* Create the .note section. */
8360 note_secp
= subseg_new (".note", 0);
8361 bfd_set_section_flags (stdoutput
,
8363 SEC_HAS_CONTENTS
| SEC_READONLY
);
8365 /* Process the arch string. */
8366 len
= strlen (cpu_arch_name
);
8368 i_note
.namesz
= len
+ 1;
8370 i_note
.type
= NT_ARCH
;
8371 p
= frag_more (sizeof (e_note
.namesz
));
8372 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8373 p
= frag_more (sizeof (e_note
.descsz
));
8374 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8375 p
= frag_more (sizeof (e_note
.type
));
8376 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8377 p
= frag_more (len
+ 1);
8378 strcpy (p
, cpu_arch_name
);
8380 frag_align (2, 0, 0);
8382 subseg_set (seg
, subseg
);
8388 md_undefined_symbol (name
)
8391 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8392 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8393 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8394 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8398 if (symbol_find (name
))
8399 as_bad (_("GOT already in symbol table"));
8400 GOT_symbol
= symbol_new (name
, undefined_section
,
8401 (valueT
) 0, &zero_address_frag
);
8408 /* Round up a section size to the appropriate boundary. */
8411 md_section_align (segment
, size
)
8412 segT segment ATTRIBUTE_UNUSED
;
8415 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8416 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8418 /* For a.out, force the section size to be aligned. If we don't do
8419 this, BFD will align it for us, but it will not write out the
8420 final bytes of the section. This may be a bug in BFD, but it is
8421 easier to fix it here since that is how the other a.out targets
8425 align
= bfd_get_section_alignment (stdoutput
, segment
);
8426 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8433 /* On the i386, PC-relative offsets are relative to the start of the
8434 next instruction. That is, the address of the offset, plus its
8435 size, since the offset is always the last part of the insn. */
8438 md_pcrel_from (fixS
*fixP
)
8440 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8446 s_bss (int ignore ATTRIBUTE_UNUSED
)
8450 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8452 obj_elf_section_change_hook ();
8454 temp
= get_absolute_expression ();
8455 subseg_set (bss_section
, (subsegT
) temp
);
8456 demand_empty_rest_of_line ();
8462 i386_validate_fix (fixS
*fixp
)
8464 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8466 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8470 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8475 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8477 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8484 tc_gen_reloc (section
, fixp
)
8485 asection
*section ATTRIBUTE_UNUSED
;
8489 bfd_reloc_code_real_type code
;
8491 switch (fixp
->fx_r_type
)
8493 case BFD_RELOC_X86_64_PLT32
:
8494 case BFD_RELOC_X86_64_GOT32
:
8495 case BFD_RELOC_X86_64_GOTPCREL
:
8496 case BFD_RELOC_386_PLT32
:
8497 case BFD_RELOC_386_GOT32
:
8498 case BFD_RELOC_386_GOTOFF
:
8499 case BFD_RELOC_386_GOTPC
:
8500 case BFD_RELOC_386_TLS_GD
:
8501 case BFD_RELOC_386_TLS_LDM
:
8502 case BFD_RELOC_386_TLS_LDO_32
:
8503 case BFD_RELOC_386_TLS_IE_32
:
8504 case BFD_RELOC_386_TLS_IE
:
8505 case BFD_RELOC_386_TLS_GOTIE
:
8506 case BFD_RELOC_386_TLS_LE_32
:
8507 case BFD_RELOC_386_TLS_LE
:
8508 case BFD_RELOC_386_TLS_GOTDESC
:
8509 case BFD_RELOC_386_TLS_DESC_CALL
:
8510 case BFD_RELOC_X86_64_TLSGD
:
8511 case BFD_RELOC_X86_64_TLSLD
:
8512 case BFD_RELOC_X86_64_DTPOFF32
:
8513 case BFD_RELOC_X86_64_DTPOFF64
:
8514 case BFD_RELOC_X86_64_GOTTPOFF
:
8515 case BFD_RELOC_X86_64_TPOFF32
:
8516 case BFD_RELOC_X86_64_TPOFF64
:
8517 case BFD_RELOC_X86_64_GOTOFF64
:
8518 case BFD_RELOC_X86_64_GOTPC32
:
8519 case BFD_RELOC_X86_64_GOT64
:
8520 case BFD_RELOC_X86_64_GOTPCREL64
:
8521 case BFD_RELOC_X86_64_GOTPC64
:
8522 case BFD_RELOC_X86_64_GOTPLT64
:
8523 case BFD_RELOC_X86_64_PLTOFF64
:
8524 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8525 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8527 case BFD_RELOC_VTABLE_ENTRY
:
8528 case BFD_RELOC_VTABLE_INHERIT
:
8530 case BFD_RELOC_32_SECREL
:
8532 code
= fixp
->fx_r_type
;
8534 case BFD_RELOC_X86_64_32S
:
8535 if (!fixp
->fx_pcrel
)
8537 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8538 code
= fixp
->fx_r_type
;
8544 switch (fixp
->fx_size
)
8547 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8548 _("can not do %d byte pc-relative relocation"),
8550 code
= BFD_RELOC_32_PCREL
;
8552 case 1: code
= BFD_RELOC_8_PCREL
; break;
8553 case 2: code
= BFD_RELOC_16_PCREL
; break;
8554 case 4: code
= BFD_RELOC_32_PCREL
; break;
8556 case 8: code
= BFD_RELOC_64_PCREL
; break;
8562 switch (fixp
->fx_size
)
8565 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8566 _("can not do %d byte relocation"),
8568 code
= BFD_RELOC_32
;
8570 case 1: code
= BFD_RELOC_8
; break;
8571 case 2: code
= BFD_RELOC_16
; break;
8572 case 4: code
= BFD_RELOC_32
; break;
8574 case 8: code
= BFD_RELOC_64
; break;
8581 if ((code
== BFD_RELOC_32
8582 || code
== BFD_RELOC_32_PCREL
8583 || code
== BFD_RELOC_X86_64_32S
)
8585 && fixp
->fx_addsy
== GOT_symbol
)
8588 code
= BFD_RELOC_386_GOTPC
;
8590 code
= BFD_RELOC_X86_64_GOTPC32
;
8592 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8594 && fixp
->fx_addsy
== GOT_symbol
)
8596 code
= BFD_RELOC_X86_64_GOTPC64
;
8599 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8600 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8601 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8603 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8605 if (!use_rela_relocations
)
8607 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8608 vtable entry to be used in the relocation's section offset. */
8609 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8610 rel
->address
= fixp
->fx_offset
;
8614 /* Use the rela in 64bit mode. */
8617 if (!fixp
->fx_pcrel
)
8618 rel
->addend
= fixp
->fx_offset
;
8622 case BFD_RELOC_X86_64_PLT32
:
8623 case BFD_RELOC_X86_64_GOT32
:
8624 case BFD_RELOC_X86_64_GOTPCREL
:
8625 case BFD_RELOC_X86_64_TLSGD
:
8626 case BFD_RELOC_X86_64_TLSLD
:
8627 case BFD_RELOC_X86_64_GOTTPOFF
:
8628 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8629 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8630 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8633 rel
->addend
= (section
->vma
8635 + fixp
->fx_addnumber
8636 + md_pcrel_from (fixp
));
8641 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8642 if (rel
->howto
== NULL
)
8644 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8645 _("cannot represent relocation type %s"),
8646 bfd_get_reloc_code_name (code
));
8647 /* Set howto to a garbage value so that we can keep going. */
8648 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8649 assert (rel
->howto
!= NULL
);
8656 /* Parse operands using Intel syntax. This implements a recursive descent
8657 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8660 FIXME: We do not recognize the full operand grammar defined in the MASM
8661 documentation. In particular, all the structure/union and
8662 high-level macro operands are missing.
8664 Uppercase words are terminals, lower case words are non-terminals.
8665 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8666 bars '|' denote choices. Most grammar productions are implemented in
8667 functions called 'intel_<production>'.
8669 Initial production is 'expr'.
8675 binOp & | AND | \| | OR | ^ | XOR
8677 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8679 constant digits [[ radixOverride ]]
8681 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8719 => expr expr cmpOp e04
8722 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8723 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8725 hexdigit a | b | c | d | e | f
8726 | A | B | C | D | E | F
8732 mulOp * | / | % | MOD | << | SHL | >> | SHR
8736 register specialRegister
8740 segmentRegister CS | DS | ES | FS | GS | SS
8742 specialRegister CR0 | CR2 | CR3 | CR4
8743 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8744 | TR3 | TR4 | TR5 | TR6 | TR7
8746 We simplify the grammar in obvious places (e.g., register parsing is
8747 done by calling parse_register) and eliminate immediate left recursion
8748 to implement a recursive-descent parser.
8752 expr' cmpOp e04 expr'
8804 /* Parsing structure for the intel syntax parser. Used to implement the
8805 semantic actions for the operand grammar. */
8806 struct intel_parser_s
8808 char *op_string
; /* The string being parsed. */
8809 int got_a_float
; /* Whether the operand is a float. */
8810 int op_modifier
; /* Operand modifier. */
8811 int is_mem
; /* 1 if operand is memory reference. */
8812 int in_offset
; /* >=1 if parsing operand of offset. */
8813 int in_bracket
; /* >=1 if parsing operand in brackets. */
8814 const reg_entry
*reg
; /* Last register reference found. */
8815 char *disp
; /* Displacement string being built. */
8816 char *next_operand
; /* Resume point when splitting operands. */
8819 static struct intel_parser_s intel_parser
;
8821 /* Token structure for parsing intel syntax. */
8824 int code
; /* Token code. */
8825 const reg_entry
*reg
; /* Register entry for register tokens. */
8826 char *str
; /* String representation. */
8829 static struct intel_token cur_token
, prev_token
;
8831 /* Token codes for the intel parser. Since T_SHORT is already used
8832 by COFF, undefine it first to prevent a warning. */
8850 #define T_YMMWORD 16
8852 /* Prototypes for intel parser functions. */
8853 static int intel_match_token (int);
8854 static void intel_putback_token (void);
8855 static void intel_get_token (void);
8856 static int intel_expr (void);
8857 static int intel_e04 (void);
8858 static int intel_e05 (void);
8859 static int intel_e06 (void);
8860 static int intel_e09 (void);
8861 static int intel_e10 (void);
8862 static int intel_e11 (void);
8865 i386_intel_operand (char *operand_string
, int got_a_float
)
8869 const reg_entry
*final_base
= i
.base_reg
;
8870 const reg_entry
*final_index
= i
.index_reg
;
8872 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8873 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8877 /* Initialize token holders. */
8878 cur_token
.code
= prev_token
.code
= T_NIL
;
8879 cur_token
.reg
= prev_token
.reg
= NULL
;
8880 cur_token
.str
= prev_token
.str
= NULL
;
8882 /* Initialize parser structure. */
8883 intel_parser
.got_a_float
= got_a_float
;
8884 intel_parser
.op_modifier
= 0;
8885 intel_parser
.is_mem
= 0;
8886 intel_parser
.in_offset
= 0;
8887 intel_parser
.in_bracket
= 0;
8888 intel_parser
.reg
= NULL
;
8889 intel_parser
.disp
[0] = '\0';
8890 intel_parser
.next_operand
= NULL
;
8895 /* Read the first token and start the parser. */
8897 ret
= intel_expr ();
8902 if (cur_token
.code
!= T_NIL
)
8904 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8905 current_templates
->start
->name
, cur_token
.str
);
8908 /* If we found a memory reference, hand it over to i386_displacement
8909 to fill in the rest of the operand fields. */
8910 else if (intel_parser
.is_mem
)
8912 if ((i
.mem_operands
== 1
8913 && !current_templates
->start
->opcode_modifier
.isstring
)
8914 || i
.mem_operands
== 2)
8916 as_bad (_("too many memory references for '%s'"),
8917 current_templates
->start
->name
);
8922 char *s
= intel_parser
.disp
;
8924 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8925 /* See the comments in intel_bracket_expr. */
8926 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8928 /* Add the displacement expression. */
8930 ret
= i386_displacement (s
, s
+ strlen (s
));
8933 /* Swap base and index in 16-bit memory operands like
8934 [si+bx]. Since i386_index_check is also used in AT&T
8935 mode we have to do that here. */
8938 && i
.base_reg
->reg_type
.bitfield
.reg16
8939 && i
.index_reg
->reg_type
.bitfield
.reg16
8940 && i
.base_reg
->reg_num
>= 6
8941 && i
.index_reg
->reg_num
< 6)
8943 const reg_entry
*base
= i
.index_reg
;
8945 i
.index_reg
= i
.base_reg
;
8948 ret
= i386_index_check (operand_string
);
8952 i
.types
[this_operand
].bitfield
.mem
= 1;
8958 /* Constant and OFFSET expressions are handled by i386_immediate. */
8959 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8960 || intel_parser
.reg
== NULL
)
8962 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8964 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8965 as_warn (_("Segment override ignored"));
8966 i
.seg
[i
.mem_operands
] = NULL
;
8968 ret
= i386_immediate (intel_parser
.disp
);
8971 if (!final_base
&& !final_index
)
8973 final_base
= i
.base_reg
;
8974 final_index
= i
.index_reg
;
8977 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8979 if (!ret
|| !intel_parser
.next_operand
)
8981 intel_parser
.op_string
= intel_parser
.next_operand
;
8982 this_operand
= i
.operands
++;
8983 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8987 free (intel_parser
.disp
);
8989 if (final_base
|| final_index
)
8991 i
.base_reg
= final_base
;
8992 i
.index_reg
= final_index
;
8998 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9002 expr' cmpOp e04 expr'
9007 /* XXX Implement the comparison operators. */
9008 return intel_e04 ();
9025 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9026 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9028 if (cur_token
.code
== '+')
9030 else if (cur_token
.code
== '-')
9031 nregs
= NUM_ADDRESS_REGS
;
9035 strcat (intel_parser
.disp
, cur_token
.str
);
9036 intel_match_token (cur_token
.code
);
9047 int nregs
= ~NUM_ADDRESS_REGS
;
9054 if (cur_token
.code
== '&'
9055 || cur_token
.code
== '|'
9056 || cur_token
.code
== '^')
9060 str
[0] = cur_token
.code
;
9062 strcat (intel_parser
.disp
, str
);
9067 intel_match_token (cur_token
.code
);
9072 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9073 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9084 int nregs
= ~NUM_ADDRESS_REGS
;
9091 if (cur_token
.code
== '*'
9092 || cur_token
.code
== '/'
9093 || cur_token
.code
== '%')
9097 str
[0] = cur_token
.code
;
9099 strcat (intel_parser
.disp
, str
);
9101 else if (cur_token
.code
== T_SHL
)
9102 strcat (intel_parser
.disp
, "<<");
9103 else if (cur_token
.code
== T_SHR
)
9104 strcat (intel_parser
.disp
, ">>");
9108 intel_match_token (cur_token
.code
);
9113 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9114 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9132 int nregs
= ~NUM_ADDRESS_REGS
;
9137 /* Don't consume constants here. */
9138 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9140 /* Need to look one token ahead - if the next token
9141 is a constant, the current token is its sign. */
9144 intel_match_token (cur_token
.code
);
9145 next_code
= cur_token
.code
;
9146 intel_putback_token ();
9147 if (next_code
== T_CONST
)
9151 /* e09 OFFSET e09 */
9152 if (cur_token
.code
== T_OFFSET
)
9155 ++intel_parser
.in_offset
;
9159 else if (cur_token
.code
== T_SHORT
)
9160 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9163 else if (cur_token
.code
== '+')
9164 strcat (intel_parser
.disp
, "+");
9169 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9175 str
[0] = cur_token
.code
;
9177 strcat (intel_parser
.disp
, str
);
9184 intel_match_token (cur_token
.code
);
9192 /* e09' PTR e10 e09' */
9193 if (cur_token
.code
== T_PTR
)
9197 if (prev_token
.code
== T_BYTE
)
9199 suffix
= BYTE_MNEM_SUFFIX
;
9200 i
.types
[this_operand
].bitfield
.byte
= 1;
9203 else if (prev_token
.code
== T_WORD
)
9205 if ((current_templates
->start
->name
[0] == 'l'
9206 && current_templates
->start
->name
[2] == 's'
9207 && current_templates
->start
->name
[3] == 0)
9208 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9209 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9210 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9211 suffix
= SHORT_MNEM_SUFFIX
;
9213 suffix
= WORD_MNEM_SUFFIX
;
9214 i
.types
[this_operand
].bitfield
.word
= 1;
9217 else if (prev_token
.code
== T_DWORD
)
9219 if ((current_templates
->start
->name
[0] == 'l'
9220 && current_templates
->start
->name
[2] == 's'
9221 && current_templates
->start
->name
[3] == 0)
9222 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9223 suffix
= WORD_MNEM_SUFFIX
;
9224 else if (flag_code
== CODE_16BIT
9225 && (current_templates
->start
->opcode_modifier
.jump
9226 || current_templates
->start
->opcode_modifier
.jumpdword
))
9227 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9228 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9229 suffix
= SHORT_MNEM_SUFFIX
;
9231 suffix
= LONG_MNEM_SUFFIX
;
9232 i
.types
[this_operand
].bitfield
.dword
= 1;
9235 else if (prev_token
.code
== T_FWORD
)
9237 if (current_templates
->start
->name
[0] == 'l'
9238 && current_templates
->start
->name
[2] == 's'
9239 && current_templates
->start
->name
[3] == 0)
9240 suffix
= LONG_MNEM_SUFFIX
;
9241 else if (!intel_parser
.got_a_float
)
9243 if (flag_code
== CODE_16BIT
)
9244 add_prefix (DATA_PREFIX_OPCODE
);
9245 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9248 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9249 i
.types
[this_operand
].bitfield
.fword
= 1;
9252 else if (prev_token
.code
== T_QWORD
)
9254 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9255 || intel_parser
.got_a_float
== 1) /* "f..." */
9256 suffix
= LONG_MNEM_SUFFIX
;
9258 suffix
= QWORD_MNEM_SUFFIX
;
9259 i
.types
[this_operand
].bitfield
.qword
= 1;
9262 else if (prev_token
.code
== T_TBYTE
)
9264 if (intel_parser
.got_a_float
== 1)
9265 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9267 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9270 else if (prev_token
.code
== T_XMMWORD
)
9272 suffix
= XMMWORD_MNEM_SUFFIX
;
9273 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9276 else if (prev_token
.code
== T_YMMWORD
)
9278 suffix
= YMMWORD_MNEM_SUFFIX
;
9279 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9284 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9288 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9290 /* Operands for jump/call using 'ptr' notation denote absolute
9292 if (current_templates
->start
->opcode_modifier
.jump
9293 || current_templates
->start
->opcode_modifier
.jumpdword
)
9294 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9296 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9300 else if (i
.suffix
!= suffix
)
9302 as_bad (_("Conflicting operand modifiers"));
9308 /* e09' : e10 e09' */
9309 else if (cur_token
.code
== ':')
9311 if (prev_token
.code
!= T_REG
)
9313 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9314 segment/group identifier (which we don't have), using comma
9315 as the operand separator there is even less consistent, since
9316 there all branches only have a single operand. */
9317 if (this_operand
!= 0
9318 || intel_parser
.in_offset
9319 || intel_parser
.in_bracket
9320 || (!current_templates
->start
->opcode_modifier
.jump
9321 && !current_templates
->start
->opcode_modifier
.jumpdword
9322 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9323 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9324 return intel_match_token (T_NIL
);
9325 /* Remember the start of the 2nd operand and terminate 1st
9327 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9328 another expression), but it gets at least the simplest case
9329 (a plain number or symbol on the left side) right. */
9330 intel_parser
.next_operand
= intel_parser
.op_string
;
9331 *--intel_parser
.op_string
= '\0';
9332 return intel_match_token (':');
9340 intel_match_token (cur_token
.code
);
9346 --intel_parser
.in_offset
;
9349 if (NUM_ADDRESS_REGS
> nregs
)
9351 as_bad (_("Invalid operand to `OFFSET'"));
9354 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9357 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9358 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9363 intel_bracket_expr (void)
9365 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9366 const char *start
= intel_parser
.op_string
;
9369 if (i
.op
[this_operand
].regs
)
9370 return intel_match_token (T_NIL
);
9372 intel_match_token ('[');
9374 /* Mark as a memory operand only if it's not already known to be an
9375 offset expression. If it's an offset expression, we need to keep
9377 if (!intel_parser
.in_offset
)
9379 ++intel_parser
.in_bracket
;
9381 /* Operands for jump/call inside brackets denote absolute addresses. */
9382 if (current_templates
->start
->opcode_modifier
.jump
9383 || current_templates
->start
->opcode_modifier
.jumpdword
)
9384 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9386 /* Unfortunately gas always diverged from MASM in a respect that can't
9387 be easily fixed without risking to break code sequences likely to be
9388 encountered (the testsuite even check for this): MASM doesn't consider
9389 an expression inside brackets unconditionally as a memory reference.
9390 When that is e.g. a constant, an offset expression, or the sum of the
9391 two, this is still taken as a constant load. gas, however, always
9392 treated these as memory references. As a compromise, we'll try to make
9393 offset expressions inside brackets work the MASM way (since that's
9394 less likely to be found in real world code), but make constants alone
9395 continue to work the traditional gas way. In either case, issue a
9397 intel_parser
.op_modifier
&= ~was_offset
;
9400 strcat (intel_parser
.disp
, "[");
9402 /* Add a '+' to the displacement string if necessary. */
9403 if (*intel_parser
.disp
!= '\0'
9404 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9405 strcat (intel_parser
.disp
, "+");
9408 && (len
= intel_parser
.op_string
- start
- 1,
9409 intel_match_token (']')))
9411 /* Preserve brackets when the operand is an offset expression. */
9412 if (intel_parser
.in_offset
)
9413 strcat (intel_parser
.disp
, "]");
9416 --intel_parser
.in_bracket
;
9417 if (i
.base_reg
|| i
.index_reg
)
9418 intel_parser
.is_mem
= 1;
9419 if (!intel_parser
.is_mem
)
9421 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9422 /* Defer the warning until all of the operand was parsed. */
9423 intel_parser
.is_mem
= -1;
9424 else if (!quiet_warnings
)
9425 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9426 len
, start
, len
, start
);
9429 intel_parser
.op_modifier
|= was_offset
;
9446 while (cur_token
.code
== '[')
9448 if (!intel_bracket_expr ())
9474 switch (cur_token
.code
)
9478 intel_match_token ('(');
9479 strcat (intel_parser
.disp
, "(");
9481 if (intel_expr () && intel_match_token (')'))
9483 strcat (intel_parser
.disp
, ")");
9490 return intel_bracket_expr ();
9495 strcat (intel_parser
.disp
, cur_token
.str
);
9496 intel_match_token (cur_token
.code
);
9498 /* Mark as a memory operand only if it's not already known to be an
9499 offset expression. */
9500 if (!intel_parser
.in_offset
)
9501 intel_parser
.is_mem
= 1;
9508 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9510 intel_match_token (T_REG
);
9512 /* Check for segment change. */
9513 if (cur_token
.code
== ':')
9515 if (!reg
->reg_type
.bitfield
.sreg2
9516 && !reg
->reg_type
.bitfield
.sreg3
)
9518 as_bad (_("`%s' is not a valid segment register"),
9522 else if (i
.mem_operands
>= 2)
9523 as_warn (_("Segment override ignored"));
9524 else if (i
.seg
[i
.mem_operands
])
9525 as_warn (_("Extra segment override ignored"));
9528 if (!intel_parser
.in_offset
)
9529 intel_parser
.is_mem
= 1;
9530 switch (reg
->reg_num
)
9533 i
.seg
[i
.mem_operands
] = &es
;
9536 i
.seg
[i
.mem_operands
] = &cs
;
9539 i
.seg
[i
.mem_operands
] = &ss
;
9542 i
.seg
[i
.mem_operands
] = &ds
;
9545 i
.seg
[i
.mem_operands
] = &fs
;
9548 i
.seg
[i
.mem_operands
] = &gs
;
9554 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9556 as_bad (_("cannot use `FLAT' here"));
9560 /* Not a segment register. Check for register scaling. */
9561 else if (cur_token
.code
== '*')
9563 if (!intel_parser
.in_bracket
)
9565 as_bad (_("Register scaling only allowed in memory operands"));
9569 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9570 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9571 else if (i
.index_reg
)
9572 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9574 /* What follows must be a valid scale. */
9575 intel_match_token ('*');
9577 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9579 /* Set the scale after setting the register (otherwise,
9580 i386_scale will complain) */
9581 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9583 char *str
, sign
= cur_token
.code
;
9584 intel_match_token (cur_token
.code
);
9585 if (cur_token
.code
!= T_CONST
)
9587 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9591 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9592 strcpy (str
+ 1, cur_token
.str
);
9594 if (!i386_scale (str
))
9598 else if (!i386_scale (cur_token
.str
))
9600 intel_match_token (cur_token
.code
);
9603 /* No scaling. If this is a memory operand, the register is either a
9604 base register (first occurrence) or an index register (second
9606 else if (intel_parser
.in_bracket
)
9611 else if (!i
.index_reg
)
9615 as_bad (_("Too many register references in memory operand"));
9619 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9622 /* It's neither base nor index. */
9623 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9625 i386_operand_type temp
= reg
->reg_type
;
9626 temp
.bitfield
.baseindex
= 0;
9627 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9629 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9630 i
.op
[this_operand
].regs
= reg
;
9635 as_bad (_("Invalid use of register"));
9639 /* Since registers are not part of the displacement string (except
9640 when we're parsing offset operands), we may need to remove any
9641 preceding '+' from the displacement string. */
9642 if (*intel_parser
.disp
!= '\0'
9643 && !intel_parser
.in_offset
)
9645 char *s
= intel_parser
.disp
;
9646 s
+= strlen (s
) - 1;
9671 intel_match_token (cur_token
.code
);
9673 if (cur_token
.code
== T_PTR
)
9676 /* It must have been an identifier. */
9677 intel_putback_token ();
9678 cur_token
.code
= T_ID
;
9684 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9688 /* The identifier represents a memory reference only if it's not
9689 preceded by an offset modifier and if it's not an equate. */
9690 symbolP
= symbol_find(cur_token
.str
);
9691 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9692 intel_parser
.is_mem
= 1;
9700 char *save_str
, sign
= 0;
9702 /* Allow constants that start with `+' or `-'. */
9703 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9705 sign
= cur_token
.code
;
9706 intel_match_token (cur_token
.code
);
9707 if (cur_token
.code
!= T_CONST
)
9709 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9715 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9716 strcpy (save_str
+ !!sign
, cur_token
.str
);
9720 /* Get the next token to check for register scaling. */
9721 intel_match_token (cur_token
.code
);
9723 /* Check if this constant is a scaling factor for an
9725 if (cur_token
.code
== '*')
9727 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9729 const reg_entry
*reg
= cur_token
.reg
;
9731 if (!intel_parser
.in_bracket
)
9733 as_bad (_("Register scaling only allowed "
9734 "in memory operands"));
9738 /* Disallow things like [1*si].
9739 sp and esp are invalid as index. */
9740 if (reg
->reg_type
.bitfield
.reg16
)
9741 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9742 else if (i
.index_reg
)
9743 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9745 /* The constant is followed by `* reg', so it must be
9748 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9750 /* Set the scale after setting the register (otherwise,
9751 i386_scale will complain) */
9752 if (!i386_scale (save_str
))
9754 intel_match_token (T_REG
);
9756 /* Since registers are not part of the displacement
9757 string, we may need to remove any preceding '+' from
9758 the displacement string. */
9759 if (*intel_parser
.disp
!= '\0')
9761 char *s
= intel_parser
.disp
;
9762 s
+= strlen (s
) - 1;
9772 /* The constant was not used for register scaling. Since we have
9773 already consumed the token following `*' we now need to put it
9774 back in the stream. */
9775 intel_putback_token ();
9778 /* Add the constant to the displacement string. */
9779 strcat (intel_parser
.disp
, save_str
);
9786 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9790 /* Match the given token against cur_token. If they match, read the next
9791 token from the operand string. */
9793 intel_match_token (int code
)
9795 if (cur_token
.code
== code
)
9802 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9807 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9809 intel_get_token (void)
9812 const reg_entry
*reg
;
9813 struct intel_token new_token
;
9815 new_token
.code
= T_NIL
;
9816 new_token
.reg
= NULL
;
9817 new_token
.str
= NULL
;
9819 /* Free the memory allocated to the previous token and move
9820 cur_token to prev_token. */
9822 free (prev_token
.str
);
9824 prev_token
= cur_token
;
9826 /* Skip whitespace. */
9827 while (is_space_char (*intel_parser
.op_string
))
9828 intel_parser
.op_string
++;
9830 /* Return an empty token if we find nothing else on the line. */
9831 if (*intel_parser
.op_string
== '\0')
9833 cur_token
= new_token
;
9837 /* The new token cannot be larger than the remainder of the operand
9839 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9840 new_token
.str
[0] = '\0';
9842 if (strchr ("0123456789", *intel_parser
.op_string
))
9844 char *p
= new_token
.str
;
9845 char *q
= intel_parser
.op_string
;
9846 new_token
.code
= T_CONST
;
9848 /* Allow any kind of identifier char to encompass floating point and
9849 hexadecimal numbers. */
9850 while (is_identifier_char (*q
))
9854 /* Recognize special symbol names [0-9][bf]. */
9855 if (strlen (intel_parser
.op_string
) == 2
9856 && (intel_parser
.op_string
[1] == 'b'
9857 || intel_parser
.op_string
[1] == 'f'))
9858 new_token
.code
= T_ID
;
9861 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9863 size_t len
= end_op
- intel_parser
.op_string
;
9865 new_token
.code
= T_REG
;
9866 new_token
.reg
= reg
;
9868 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9869 new_token
.str
[len
] = '\0';
9872 else if (is_identifier_char (*intel_parser
.op_string
))
9874 char *p
= new_token
.str
;
9875 char *q
= intel_parser
.op_string
;
9877 /* A '.' or '$' followed by an identifier char is an identifier.
9878 Otherwise, it's operator '.' followed by an expression. */
9879 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9881 new_token
.code
= '.';
9882 new_token
.str
[0] = '.';
9883 new_token
.str
[1] = '\0';
9887 while (is_identifier_char (*q
) || *q
== '@')
9891 if (strcasecmp (new_token
.str
, "NOT") == 0)
9892 new_token
.code
= '~';
9894 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9895 new_token
.code
= '%';
9897 else if (strcasecmp (new_token
.str
, "AND") == 0)
9898 new_token
.code
= '&';
9900 else if (strcasecmp (new_token
.str
, "OR") == 0)
9901 new_token
.code
= '|';
9903 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9904 new_token
.code
= '^';
9906 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9907 new_token
.code
= T_SHL
;
9909 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9910 new_token
.code
= T_SHR
;
9912 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9913 new_token
.code
= T_BYTE
;
9915 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9916 new_token
.code
= T_WORD
;
9918 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9919 new_token
.code
= T_DWORD
;
9921 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9922 new_token
.code
= T_FWORD
;
9924 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9925 new_token
.code
= T_QWORD
;
9927 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9928 /* XXX remove (gcc still uses it) */
9929 || strcasecmp (new_token
.str
, "XWORD") == 0)
9930 new_token
.code
= T_TBYTE
;
9932 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9933 || strcasecmp (new_token
.str
, "OWORD") == 0)
9934 new_token
.code
= T_XMMWORD
;
9936 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9937 new_token
.code
= T_YMMWORD
;
9939 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9940 new_token
.code
= T_PTR
;
9942 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9943 new_token
.code
= T_SHORT
;
9945 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9947 new_token
.code
= T_OFFSET
;
9949 /* ??? This is not mentioned in the MASM grammar but gcc
9950 makes use of it with -mintel-syntax. OFFSET may be
9951 followed by FLAT: */
9952 if (strncasecmp (q
, " FLAT:", 6) == 0)
9953 strcat (new_token
.str
, " FLAT:");
9957 new_token
.code
= T_ID
;
9961 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9963 new_token
.code
= *intel_parser
.op_string
;
9964 new_token
.str
[0] = *intel_parser
.op_string
;
9965 new_token
.str
[1] = '\0';
9968 else if (strchr ("<>", *intel_parser
.op_string
)
9969 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9971 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9972 new_token
.str
[0] = *intel_parser
.op_string
;
9973 new_token
.str
[1] = *intel_parser
.op_string
;
9974 new_token
.str
[2] = '\0';
9978 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9980 intel_parser
.op_string
+= strlen (new_token
.str
);
9981 cur_token
= new_token
;
9984 /* Put cur_token back into the token stream and make cur_token point to
9987 intel_putback_token (void)
9989 if (cur_token
.code
!= T_NIL
)
9991 intel_parser
.op_string
-= strlen (cur_token
.str
);
9992 free (cur_token
.str
);
9994 cur_token
= prev_token
;
9996 /* Forget prev_token. */
9997 prev_token
.code
= T_NIL
;
9998 prev_token
.reg
= NULL
;
9999 prev_token
.str
= NULL
;
10003 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10005 int saved_naked_reg
;
10006 char saved_register_dot
;
10008 saved_naked_reg
= allow_naked_reg
;
10009 allow_naked_reg
= 1;
10010 saved_register_dot
= register_chars
['.'];
10011 register_chars
['.'] = '.';
10012 allow_pseudo_reg
= 1;
10013 expression_and_evaluate (exp
);
10014 allow_pseudo_reg
= 0;
10015 register_chars
['.'] = saved_register_dot
;
10016 allow_naked_reg
= saved_naked_reg
;
10018 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10020 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10022 exp
->X_op
= O_constant
;
10023 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10024 .dw2_regnum
[flag_code
>> 1];
10027 exp
->X_op
= O_illegal
;
10032 tc_x86_frame_initial_instructions (void)
10034 static unsigned int sp_regno
[2];
10036 if (!sp_regno
[flag_code
>> 1])
10038 char *saved_input
= input_line_pointer
;
10039 char sp
[][4] = {"esp", "rsp"};
10042 input_line_pointer
= sp
[flag_code
>> 1];
10043 tc_x86_parse_to_dw2regnum (&exp
);
10044 assert (exp
.X_op
== O_constant
);
10045 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10046 input_line_pointer
= saved_input
;
10049 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10050 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10054 i386_elf_section_type (const char *str
, size_t len
)
10056 if (flag_code
== CODE_64BIT
10057 && len
== sizeof ("unwind") - 1
10058 && strncmp (str
, "unwind", 6) == 0)
10059 return SHT_X86_64_UNWIND
;
10066 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10070 expr
.X_op
= O_secrel
;
10071 expr
.X_add_symbol
= symbol
;
10072 expr
.X_add_number
= 0;
10073 emit_expr (&expr
, size
);
10077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10081 x86_64_section_letter (int letter
, char **ptr_msg
)
10083 if (flag_code
== CODE_64BIT
)
10086 return SHF_X86_64_LARGE
;
10088 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10091 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10096 x86_64_section_word (char *str
, size_t len
)
10098 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10099 return SHF_X86_64_LARGE
;
10105 handle_large_common (int small ATTRIBUTE_UNUSED
)
10107 if (flag_code
!= CODE_64BIT
)
10109 s_comm_internal (0, elf_common_parse
);
10110 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10114 static segT lbss_section
;
10115 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10116 asection
*saved_bss_section
= bss_section
;
10118 if (lbss_section
== NULL
)
10120 flagword applicable
;
10121 segT seg
= now_seg
;
10122 subsegT subseg
= now_subseg
;
10124 /* The .lbss section is for local .largecomm symbols. */
10125 lbss_section
= subseg_new (".lbss", 0);
10126 applicable
= bfd_applicable_section_flags (stdoutput
);
10127 bfd_set_section_flags (stdoutput
, lbss_section
,
10128 applicable
& SEC_ALLOC
);
10129 seg_info (lbss_section
)->bss
= 1;
10131 subseg_set (seg
, subseg
);
10134 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10135 bss_section
= lbss_section
;
10137 s_comm_internal (0, elf_common_parse
);
10139 elf_com_section_ptr
= saved_com_section_ptr
;
10140 bss_section
= saved_bss_section
;
10143 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */