gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright (C) 1989, 1992 Free Software Foundation.
   3
   4    This file is part of GAS, the GNU Assembler.
   5
   6    GAS is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    GAS is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to
  18    the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  19
  20 #define TC_I386 1
  21
  22 #define AOUT_MACHTYPE 100
  23 #define REVERSE_SORT_RELOCS
  24
  25 #define NO_LISTING
  26
  27 #define tc_aout_pre_write_hook(x)       {;} /* not used */
  28 #define tc_crawl_symbol_chain(a)        {;} /* not used */
  29 #define tc_headers_hook(a)              {;} /* not used */
  30
  31 #define MAX_OPERANDS 3          /* max operands per insn */
  32 #define MAX_PREFIXES 4          /* max prefixes per opcode */
  33 #define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */
  34 #define MAX_MEMORY_OPERANDS 2   /* max memory ref per insn
  35                                  * lcall uses 2
  36                                  */
  37 /* we define the syntax here (modulo base,index,scale syntax) */
  38 #define REGISTER_PREFIX '%'
  39 #define IMMEDIATE_PREFIX '$'
  40 #define ABSOLUTE_PREFIX '*'
  41 #define PREFIX_SEPERATOR '/'
  42
  43 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
  44
  45 /* register numbers */
  46 #define EBP_REG_NUM 5
  47 #define ESP_REG_NUM 4
  48
  49 /* modrm_byte.regmem for twobyte escape */
  50 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
  51 /* index_base_byte.index for no index register addressing */
  52 #define NO_INDEX_REGISTER ESP_REG_NUM
  53 /* index_base_byte.base for no base register addressing */
  54 #define NO_BASE_REGISTER EBP_REG_NUM
  55
  56  /* these are the att as opcode suffixes, making movl --> mov, for example */
  57 #define DWORD_OPCODE_SUFFIX 'l'
  58 #define WORD_OPCODE_SUFFIX  'w'
  59 #define BYTE_OPCODE_SUFFIX  'b'
  60
  61     /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
  62 #define REGMEM_FIELD_HAS_REG 0x3                /* always = 0x3 */
  63 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
  64
  65 #define END_OF_INSN '\0'
  66
  67 /*
  68   When an operand is read in it is classified by its type.  This type includes
  69   all the possible ways an operand can be used.  Thus, '%eax' is both 'register
  70   # 0' and 'The Accumulator'.  In our language this is expressed by OR'ing
  71   'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
  72   Operands are classified so that we can match given operand types with
  73   the opcode table in i386-opcode.h.
  74   */
  75 #define Unknown 0x0
  76 /* register */
  77 #define Reg8    0x1             /* 8 bit reg */
  78 #define Reg16   0x2             /* 16 bit reg */
  79 #define Reg32   0x4             /* 32 bit reg */
  80 #define Reg     (Reg8|Reg16|Reg32)    /* gen'l register */
  81 #define WordReg (Reg16|Reg32)   /* for push/pop operands */
  82 /* immediate */
  83 #define Imm8    0x8             /* 8 bit immediate */
  84 #define Imm8S   0x10            /* 8 bit immediate sign extended */
  85 #define Imm16   0x20            /* 16 bit immediate */
  86 #define Imm32   0x40            /* 32 bit immediate */
  87 #define Imm1    0x80            /* 1 bit immediate */
  88 #define ImmUnknown Imm32        /* for unknown expressions */
  89 #define Imm     (Imm8|Imm8S|Imm16|Imm32)    /* gen'l immediate */
  90 /* memory */
  91 #define Disp8   0x200           /* 8 bit displacement (for jumps) */
  92 #define Disp16  0x400           /* 16 bit displacement */
  93 #define Disp32  0x800           /* 32 bit displacement */
  94 #define Disp    (Disp8|Disp16|Disp32) /* General displacement */
  95 #define DispUnknown Disp32      /* for unknown size displacements */
  96 #define Mem8    0x1000
  97 #define Mem16   0x2000
  98 #define Mem32   0x4000
  99 #define BaseIndex 0x8000
 100 #define Mem     (Disp|Mem8|Mem16|Mem32|BaseIndex) /* General memory */
 101 #define WordMem   (Mem16|Mem32|Disp|BaseIndex)
 102 #define ByteMem   (Mem8|Disp|BaseIndex)
 103 /* specials */
 104 #define InOutPortReg 0x10000    /* register to hold in/out port addr = dx */
 105 #define ShiftCount 0x20000      /* register to hold shift cound = cl */
 106 #define Control 0x40000         /* Control register */
 107 #define Debug   0x80000         /* Debug register */
 108 #define Test    0x100000                /* Test register */
 109 #define FloatReg 0x200000       /* Float register */
 110 #define FloatAcc 0x400000       /* Float stack top %st(0) */
 111 #define SReg2   0x800000                /* 2 bit segment register */
 112 #define SReg3   0x1000000               /* 3 bit segment register */
 113 #define Acc     0x2000000               /* Accumulator %al or %ax or %eax */
 114 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 115 #define JumpAbsolute 0x4000000
 116 #define Abs8  0x08000000
 117 #define Abs16 0x10000000
 118 #define Abs32 0x20000000
 119 #define Abs (Abs8|Abs16|Abs32)
 120
 121 #define Byte (Reg8|Imm8|Imm8S)
 122 #define Word (Reg16|Imm16)
 123 #define DWord (Reg32|Imm32)
 124
 125 #define SMALLEST_DISP_TYPE(num) \
 126     fits_in_signed_byte(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32)
 127
 128 typedef struct {
 129         /* instruction name sans width suffix ("mov" for movl insns) */
 130         char *name;
 131
 132         /* how many operands */
 133         unsigned int operands;
 134
 135         /* base_opcode is the fundamental opcode byte with a optional prefix(es). */
 136         unsigned int base_opcode;
 137
 138         /* extension_opcode is the 3 bit extension for group <n> insns.
 139            If this template has no extension opcode (the usual case) use None */
 140         unsigned char extension_opcode;
 141 #define None 0xff /* If no extension_opcode is possible. */
 142
 143         /* the bits in opcode_modifier are used to generate the final opcode from
 144            the base_opcode.  These bits also are used to detect alternate forms of
 145            the same instruction */
 146         unsigned int opcode_modifier;
 147
 148         /* opcode_modifier bits: */
 149 #define W        0x1    /* set if operands are words or dwords */
 150 #define D        0x2    /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
 151         /* direction flag for floating insns:  MUST BE 0x400 */
 152 #define FloatD 0x400
 153         /* shorthand */
 154 #define DW (D|W)
 155 #define ShortForm 0x10          /* register is in low 3 bits of opcode */
 156 #define ShortFormW 0x20         /* ShortForm and W bit is 0x8 */
 157 #define Seg2ShortForm 0x40      /* encoding of load segment reg insns */
 158 #define Seg3ShortForm 0x80      /* fs/gs segment register insns. */
 159 #define Jump 0x100              /* special case for jump insns. */
 160 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 161         /* 0x400 CANNOT BE USED since it's already used by FloatD above */
 162 #define DONT_USE 0x400
 163 #define NoModrm 0x800
 164 #define Modrm 0x1000
 165 #define imulKludge 0x2000
 166 #define JumpByte 0x4000
 167 #define JumpDword 0x8000
 168 #define ReverseRegRegmem 0x10000
 169
 170         /* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
 171            instuction comes in byte, word, and dword sizes and is encoded into
 172            machine code in the canonical way. */
 173 #define COMES_IN_ALL_SIZES (W)
 174
 175         /* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
 176            source and destination operands can be reversed by setting either
 177            the D (for integer insns) or the FloatD (for floating insns) bit
 178            in base_opcode. */
 179 #define COMES_IN_BOTH_DIRECTIONS (D|FloatD)
 180
 181         /* operand_types[i] describes the type of operand i.  This is made
 182            by OR'ing together all of the possible type masks.  (e.g.
 183            'operand_types[i] = Reg|Imm' specifies that operand i can be
 184            either a register or an immediate operand */
 185         unsigned int operand_types[3];
 186 } template;
 187
 188 /*
 189   'templates' is for grouping together 'template' structures for opcodes
 190   of the same name.  This is only used for storing the insns in the grand
 191   ole hash table of insns.
 192   The templates themselves start at START and range up to (but not including)
 193   END.
 194   */
 195 typedef struct {
 196         template *start;
 197         template *end;
 198 } templates;
 199
 200 /* these are for register name --> number & type hash lookup */
 201 typedef struct {
 202         char *reg_name;
 203         unsigned int reg_type;
 204         unsigned int reg_num;
 205 } reg_entry;
 206
 207 typedef struct {
 208         char *seg_name;
 209         unsigned int seg_prefix;
 210 } seg_entry;
 211
 212 /* these are for prefix name --> prefix code hash lookup */
 213 typedef struct {
 214         char *prefix_name;
 215         unsigned char prefix_code;
 216 } prefix_entry;
 217
 218 /* 386 operand encoding bytes:  see 386 book for details of this. */
 219 typedef struct {
 220         unsigned regmem:3;           /* codes register or memory operand */
 221         unsigned reg:3;      /* codes register operand (or extended opcode) */
 222         unsigned mode:2;             /* how to interpret regmem & reg */
 223 } modrm_byte;
 224
 225 /* 386 opcode byte to code indirect addressing. */
 226 typedef struct {
 227         unsigned base:3;
 228         unsigned index:3;
 229         unsigned scale:2;
 230 } base_index_byte;
 231
 232 /* end of tc-i386.h */