1 /* tc-i860.c -- Assembler for the Intel i860 architecture.
2 Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 Brought back from the dead and completely reworked
6 by Jason Eckhardt <jle@cygnus.com>.
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License along
21 with GAS; see the file COPYING. If not, write to the Free Software
22 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "safe-ctype.h"
29 #include "opcode/i860.h"
33 /* The opcode hash table. */
34 static struct hash_control
*op_hash
= NULL
;
36 /* These characters always start a comment. */
37 const char comment_chars
[] = "#!/";
39 /* These characters start a comment at the beginning of a line. */
40 const char line_comment_chars
[] = "#/";
42 const char line_separator_chars
[] = ";";
44 /* Characters that can be used to separate the mantissa from the exponent
45 in floating point numbers. */
46 const char EXP_CHARS
[] = "eE";
48 /* Characters that indicate this number is a floating point constant.
49 As in 0f12.456 or 0d1.2345e12. */
50 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
52 /* Register prefix (depends on syntax). */
53 static char reg_prefix
;
61 enum expand_type expand
;
65 bfd_reloc_code_real_type reloc
;
71 /* The current fixup count. */
74 static char *expr_end
;
76 /* Indicates error if a pseudo operation was expanded after a branch. */
77 static char last_expand
;
79 /* If true, then warn if any pseudo operations were expanded. */
80 static int target_warn_expand
= 0;
82 /* If true, then XP support is enabled. */
83 static int target_xp
= 0;
85 /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */
86 static int target_intel_syntax
= 0;
90 static void i860_process_insn (char *);
91 static void s_dual (int);
92 static void s_enddual (int);
93 static void s_atmp (int);
94 static int i860_get_expression (char *);
95 static bfd_reloc_code_real_type
obtain_reloc_for_imm16 (fixS
*, long *);
97 static void print_insn (struct i860_it
*);
100 const pseudo_typeS md_pseudo_table
[] =
103 {"align", s_align_bytes
, 0},
106 {"enddual", s_enddual
, 0},
111 /* Dual-instruction mode handling. */
114 DUAL_OFF
= 0, DUAL_ON
, DUAL_DDOT
, DUAL_ONDDOT
,
116 static enum dual dual_mode
= DUAL_OFF
;
118 /* Handle ".dual" directive. */
120 s_dual (int ignore ATTRIBUTE_UNUSED
)
122 if (target_intel_syntax
)
125 as_bad (_("Directive .dual available only with -mintel-syntax option"));
128 /* Handle ".enddual" directive. */
130 s_enddual (int ignore ATTRIBUTE_UNUSED
)
132 if (target_intel_syntax
)
133 dual_mode
= DUAL_OFF
;
135 as_bad (_("Directive .enddual available only with -mintel-syntax option"));
138 /* Temporary register used when expanding assembler pseudo operations. */
139 static int atmp
= 31;
142 s_atmp (int ignore ATTRIBUTE_UNUSED
)
146 if (! target_intel_syntax
)
148 as_bad (_("Directive .atmp available only with -mintel-syntax option"));
149 demand_empty_rest_of_line ();
153 if (strncmp (input_line_pointer
, "sp", 2) == 0)
155 input_line_pointer
+= 2;
158 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
160 input_line_pointer
+= 2;
163 else if (strncmp (input_line_pointer
, "r", 1) == 0)
165 input_line_pointer
+= 1;
166 temp
= get_absolute_expression ();
167 if (temp
>= 0 && temp
<= 31)
170 as_bad (_("Unknown temporary pseudo register"));
174 as_bad (_("Unknown temporary pseudo register"));
176 demand_empty_rest_of_line ();
179 /* This function is called once, at assembler startup time. It should
180 set up all the tables and data structures that the MD part of the
181 assembler will need. */
185 const char *retval
= NULL
;
189 op_hash
= hash_new ();
191 while (i860_opcodes
[i
].name
!= NULL
)
193 const char *name
= i860_opcodes
[i
].name
;
194 retval
= hash_insert (op_hash
, name
, (PTR
)&i860_opcodes
[i
]);
197 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
198 i860_opcodes
[i
].name
, retval
);
203 if (i860_opcodes
[i
].match
& i860_opcodes
[i
].lose
)
206 _("internal error: losing opcode: `%s' \"%s\"\n"),
207 i860_opcodes
[i
].name
, i860_opcodes
[i
].args
);
212 while (i860_opcodes
[i
].name
!= NULL
213 && strcmp (i860_opcodes
[i
].name
, name
) == 0);
217 as_fatal (_("Defective assembler. No assembly attempted."));
219 /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */
220 reg_prefix
= target_intel_syntax
? 0 : '%';
223 /* This is the core of the machine-dependent assembler. STR points to a
224 machine dependent instruction. This function emits the frags/bytes
227 md_assemble (char *str
)
232 struct i860_it pseudo
[3];
237 /* Assemble the instruction. */
238 i860_process_insn (str
);
240 /* Check for expandable flag to produce pseudo-instructions. This
241 is an undesirable feature that should be avoided. */
242 if (the_insn
.expand
!= 0 && the_insn
.expand
!= XP_ONLY
243 && ! (the_insn
.fi
[0].fup
& (OP_SEL_HA
| OP_SEL_H
| OP_SEL_L
| OP_SEL_GOT
244 | OP_SEL_GOTOFF
| OP_SEL_PLT
)))
246 for (i
= 0; i
< 3; i
++)
247 pseudo
[i
] = the_insn
;
250 switch (the_insn
.expand
)
258 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
259 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
260 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
261 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
264 /* Emit "or l%const,r0,ireg_dest". */
265 pseudo
[0].opcode
= (the_insn
.opcode
& 0x001f0000) | 0xe4000000;
266 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
268 /* Emit "orh h%const,ireg_dest,ireg_dest". */
269 pseudo
[1].opcode
= (the_insn
.opcode
& 0x03ffffff) | 0xec000000
270 | ((the_insn
.opcode
& 0x001f0000) << 5);
271 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
277 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
278 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
279 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
280 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
283 /* Emit "orh ha%addr_expr,r0,r31". */
284 pseudo
[0].opcode
= 0xec000000 | (atmp
<< 16);
285 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_HA
);
287 /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup
288 information from the original instruction. */
289 pseudo
[1].opcode
= (the_insn
.opcode
& ~0x03e00000) | (atmp
<< 21);
290 pseudo
[1].fi
[0].fup
= the_insn
.fi
[0].fup
| OP_SEL_L
;
296 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
297 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
298 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 16)
299 && the_insn
.fi
[0].exp
.X_add_number
>= 0))
302 /* Emit "$(opcode)h h%const,ireg_src2,r31". */
303 pseudo
[0].opcode
= (the_insn
.opcode
& 0xf3e0ffff) | 0x0c000000
305 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
307 /* Emit "$(opcode) l%const,r31,ireg_dest". */
308 pseudo
[1].opcode
= (the_insn
.opcode
& 0xf01f0000) | 0x04000000
310 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
316 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
317 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
318 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 16)
319 && the_insn
.fi
[0].exp
.X_add_number
>= 0))
322 /* Emit "andnot h%const,ireg_src2,r31". */
323 pseudo
[0].opcode
= (the_insn
.opcode
& 0x03e0ffff) | 0xd4000000
325 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
326 pseudo
[0].fi
[0].exp
.X_add_number
=
327 -1 - the_insn
.fi
[0].exp
.X_add_number
;
329 /* Emit "andnot l%const,r31,ireg_dest". */
330 pseudo
[1].opcode
= (the_insn
.opcode
& 0x001f0000) | 0xd4000000
332 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
333 pseudo
[1].fi
[0].exp
.X_add_number
=
334 -1 - the_insn
.fi
[0].exp
.X_add_number
;
340 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
341 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
342 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
343 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
346 /* Emit "orh h%const,r0,r31". */
347 pseudo
[0].opcode
= 0xec000000 | (atmp
<< 16);
348 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
350 /* Emit "or l%const,r31,r31". */
351 pseudo
[1].opcode
= 0xe4000000 | (atmp
<< 21) | (atmp
<< 16);
352 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
354 /* Emit "r31,ireg_src2,ireg_dest". */
355 pseudo
[2].opcode
= (the_insn
.opcode
& ~0x0400ffff) | (atmp
<< 11);
356 pseudo
[2].fi
[0].fup
= OP_IMM_S16
;
362 as_fatal (_("failed sanity check."));
365 the_insn
= pseudo
[0];
367 /* Warn if an opcode is expanded after a delayed branch. */
368 if (num_opcodes
> 1 && last_expand
== 1)
369 as_warn (_("Expanded opcode after delayed branch: `%s'"), str
);
371 /* Warn if an opcode is expanded in dual mode. */
372 if (num_opcodes
> 1 && dual_mode
!= DUAL_OFF
)
373 as_warn (_("Expanded opcode in dual mode: `%s'"), str
);
375 /* Notify if any expansions happen. */
376 if (target_warn_expand
&& num_opcodes
> 1)
377 as_warn (_("An instruction was expanded (%s)"), str
);
385 /* Output the opcode. Note that the i860 always reads instructions
386 as little-endian data. */
387 destp
= frag_more (4);
388 number_to_chars_littleendian (destp
, the_insn
.opcode
, 4);
390 /* Check for expanded opcode after branch or in dual mode. */
391 last_expand
= the_insn
.fi
[0].pcrel
;
393 /* Output the symbol-dependent stuff. Only btne and bte will ever
394 loop more than once here, since only they (possibly) have more
396 for (tmp
= 0; tmp
< fc
; tmp
++)
398 if (the_insn
.fi
[tmp
].fup
!= OP_NONE
)
401 fix
= fix_new_exp (frag_now
,
402 destp
- frag_now
->fr_literal
,
404 &the_insn
.fi
[tmp
].exp
,
405 the_insn
.fi
[tmp
].pcrel
,
406 the_insn
.fi
[tmp
].reloc
);
408 /* Despite the odd name, this is a scratch field. We use
409 it to encode operand type information. */
410 fix
->fx_addnumber
= the_insn
.fi
[tmp
].fup
;
413 the_insn
= pseudo
[++i
];
415 while (--num_opcodes
> 0);
419 /* Assemble the instruction pointed to by STR. */
421 i860_process_insn (char *str
)
426 struct i860_opcode
*insn
;
428 unsigned long opcode
;
433 #if 1 /* For compiler warnings. */
440 for (s
= str
; ISLOWER (*s
) || *s
== '.' || *s
== '3'
441 || *s
== '2' || *s
== '1'; ++s
)
459 as_fatal (_("Unknown opcode: `%s'"), str
);
462 /* Check for dual mode ("d.") opcode prefix. */
463 if (strncmp (str
, "d.", 2) == 0)
465 if (dual_mode
== DUAL_ON
)
466 dual_mode
= DUAL_ONDDOT
;
468 dual_mode
= DUAL_DDOT
;
472 if ((insn
= (struct i860_opcode
*) hash_find (op_hash
, str
)) == NULL
)
474 if (dual_mode
== DUAL_DDOT
|| dual_mode
== DUAL_ONDDOT
)
476 as_bad (_("Unknown opcode: `%s'"), str
);
487 opcode
= insn
->match
;
488 memset (&the_insn
, '\0', sizeof (the_insn
));
490 for (t
= 0; t
< MAX_FIXUPS
; t
++)
492 the_insn
.fi
[t
].reloc
= BFD_RELOC_NONE
;
493 the_insn
.fi
[t
].pcrel
= 0;
494 the_insn
.fi
[t
].fup
= OP_NONE
;
497 /* Build the opcode, checking as we go that the operands match. */
498 for (args
= insn
->args
; ; ++args
)
512 /* These must match exactly. */
522 /* Must be at least one digit. */
532 /* Next operand must be a register. */
536 /* Check for register prefix if necessary. */
537 if (reg_prefix
&& *s
!= reg_prefix
)
564 /* Any register r0..r31. */
567 if (!ISDIGIT (c
= *s
++))
573 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
581 /* Not this opcode. */
586 /* Obtained the register, now place it in the opcode. */
590 opcode
|= mask
<< 11;
594 opcode
|= mask
<< 21;
598 opcode
|= mask
<< 16;
604 /* Next operand is a floating point register. */
608 /* Check for register prefix if necessary. */
609 if (reg_prefix
&& *s
!= reg_prefix
)
614 if (*s
++ == 'f' && ISDIGIT (*s
))
619 mask
= 10 * (mask
- '0') + (*s
++ - '0');
632 opcode
|= mask
<< 11;
636 opcode
|= mask
<< 21;
640 opcode
|= mask
<< 16;
641 if ((opcode
& (1 << 10)) && mask
!= 0
642 && (mask
== ((opcode
>> 11) & 0x1f)))
643 as_warn (_("Pipelined instruction: fsrc1 = fdest"));
649 /* Next operand must be a control register. */
651 /* Check for register prefix if necessary. */
652 if (reg_prefix
&& *s
!= reg_prefix
)
657 if (strncmp (s
, "fir", 3) == 0)
663 if (strncmp (s
, "psr", 3) == 0)
669 if (strncmp (s
, "dirbase", 7) == 0)
675 if (strncmp (s
, "db", 2) == 0)
681 if (strncmp (s
, "fsr", 3) == 0)
687 if (strncmp (s
, "epsr", 4) == 0)
693 /* The remaining control registers are XP only. */
694 if (target_xp
&& strncmp (s
, "bear", 4) == 0)
700 if (target_xp
&& strncmp (s
, "ccr", 3) == 0)
706 if (target_xp
&& strncmp (s
, "p0", 2) == 0)
712 if (target_xp
&& strncmp (s
, "p1", 2) == 0)
718 if (target_xp
&& strncmp (s
, "p2", 2) == 0)
724 if (target_xp
&& strncmp (s
, "p3", 2) == 0)
732 /* 5-bit immediate in src1. */
734 if (! i860_get_expression (s
))
737 the_insn
.fi
[fc
].fup
|= OP_IMM_U5
;
743 /* 26-bit immediate, relative branch (lbroff). */
745 the_insn
.fi
[fc
].pcrel
= 1;
746 the_insn
.fi
[fc
].fup
|= OP_IMM_BR26
;
749 /* 16-bit split immediate, relative branch (sbroff). */
751 the_insn
.fi
[fc
].pcrel
= 1;
752 the_insn
.fi
[fc
].fup
|= OP_IMM_BR16
;
755 /* 16-bit split immediate. */
757 the_insn
.fi
[fc
].fup
|= OP_IMM_SPLIT16
;
760 /* 16-bit split immediate, byte aligned (st.b). */
762 the_insn
.fi
[fc
].fup
|= OP_IMM_SPLIT16
;
765 /* 16-bit split immediate, half-word aligned (st.s). */
767 the_insn
.fi
[fc
].fup
|= (OP_IMM_SPLIT16
| OP_ENCODE1
| OP_ALIGN2
);
770 /* 16-bit split immediate, word aligned (st.l). */
772 the_insn
.fi
[fc
].fup
|= (OP_IMM_SPLIT16
| OP_ENCODE1
| OP_ALIGN4
);
775 /* 16-bit immediate. */
777 the_insn
.fi
[fc
].fup
|= OP_IMM_S16
;
780 /* 16-bit immediate, byte aligned (ld.b). */
782 the_insn
.fi
[fc
].fup
|= OP_IMM_S16
;
785 /* 16-bit immediate, half-word aligned (ld.s). */
787 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE1
| OP_ALIGN2
);
790 /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */
792 if (insn
->name
[0] == 'l')
793 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE1
| OP_ALIGN4
);
795 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE2
| OP_ALIGN4
);
798 /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */
800 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE3
| OP_ALIGN8
);
803 /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */
805 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE3
| OP_ALIGN16
);
809 /* Handle the immediate for either the Intel syntax or
810 SVR4 syntax. The Intel syntax is "ha%immediate"
811 whereas SVR4 syntax is "[immediate]@ha". */
813 if (target_intel_syntax
== 0)
815 /* AT&T/SVR4 syntax. */
819 /* Note that if i860_get_expression() fails, we will still
820 have created U entries in the symbol table for the
821 'symbols' in the input string. Try not to create U
822 symbols for registers, etc. */
823 if (! i860_get_expression (s
))
828 if (strncmp (s
, "@ha", 3) == 0)
830 the_insn
.fi
[fc
].fup
|= OP_SEL_HA
;
833 else if (strncmp (s
, "@h", 2) == 0)
835 the_insn
.fi
[fc
].fup
|= OP_SEL_H
;
838 else if (strncmp (s
, "@l", 2) == 0)
840 the_insn
.fi
[fc
].fup
|= OP_SEL_L
;
843 else if (strncmp (s
, "@gotoff", 7) == 0
844 || strncmp (s
, "@GOTOFF", 7) == 0)
846 as_bad (_("Assembler does not yet support PIC"));
847 the_insn
.fi
[fc
].fup
|= OP_SEL_GOTOFF
;
850 else if (strncmp (s
, "@got", 4) == 0
851 || strncmp (s
, "@GOT", 4) == 0)
853 as_bad (_("Assembler does not yet support PIC"));
854 the_insn
.fi
[fc
].fup
|= OP_SEL_GOT
;
857 else if (strncmp (s
, "@plt", 4) == 0
858 || strncmp (s
, "@PLT", 4) == 0)
860 as_bad (_("Assembler does not yet support PIC"));
861 the_insn
.fi
[fc
].fup
|= OP_SEL_PLT
;
865 the_insn
.expand
= insn
->expand
;
875 if (strncmp (s
, "ha%", 3) == 0)
877 the_insn
.fi
[fc
].fup
|= OP_SEL_HA
;
880 else if (strncmp (s
, "h%", 2) == 0)
882 the_insn
.fi
[fc
].fup
|= OP_SEL_H
;
885 else if (strncmp (s
, "l%", 2) == 0)
887 the_insn
.fi
[fc
].fup
|= OP_SEL_L
;
890 the_insn
.expand
= insn
->expand
;
892 /* Note that if i860_get_expression() fails, we will still
893 have created U entries in the symbol table for the
894 'symbols' in the input string. Try not to create U
895 symbols for registers, etc. */
896 if (! i860_get_expression (s
))
907 as_fatal (_("failed sanity check."));
914 /* Args don't match. */
915 if (insn
[1].name
!= NULL
916 && ! strcmp (insn
->name
, insn
[1].name
))
924 as_bad (_("Illegal operands for %s"), insn
->name
);
931 /* Set the dual bit on this instruction if necessary. */
932 if (dual_mode
!= DUAL_OFF
)
934 if ((opcode
& 0xfc000000) == 0x48000000 || opcode
== 0xb0000000)
937 if (dual_mode
== DUAL_DDOT
)
938 dual_mode
= DUAL_OFF
;
939 else if (dual_mode
== DUAL_ONDDOT
)
942 else if (dual_mode
== DUAL_DDOT
|| dual_mode
== DUAL_ONDDOT
)
943 as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn
->name
);
946 the_insn
.opcode
= opcode
;
948 /* Only recognize XP instructions when the user has requested it. */
949 if (insn
->expand
== XP_ONLY
&& ! target_xp
)
950 as_bad (_("Unknown opcode: `%s'"), insn
->name
);
954 i860_get_expression (char *str
)
959 save_in
= input_line_pointer
;
960 input_line_pointer
= str
;
961 seg
= expression (&the_insn
.fi
[fc
].exp
);
962 if (seg
!= absolute_section
963 && seg
!= undefined_section
964 && ! SEG_NORMAL (seg
))
966 the_insn
.error
= _("bad segment");
967 expr_end
= input_line_pointer
;
968 input_line_pointer
= save_in
;
971 expr_end
= input_line_pointer
;
972 input_line_pointer
= save_in
;
976 /* Turn a string in input_line_pointer into a floating point constant of
977 type TYPE, and store the appropriate bytes in *LITP. The number of
978 LITTLENUMS emitted is stored in *SIZEP. An error message is returned,
981 /* Equal to MAX_PRECISION in atof-ieee.c. */
982 #define MAX_LITTLENUMS 6
985 md_atof (int type
, char *litP
, int *sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
989 LITTLENUM_TYPE
*wordP
;
1020 return _("Bad call to MD_ATOF()");
1022 t
= atof_ieee (input_line_pointer
, type
, words
);
1024 input_line_pointer
= t
;
1025 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1026 for (wordP
= words
; prec
--;)
1028 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
1029 litP
+= sizeof (LITTLENUM_TYPE
);
1034 /* Write out in current endian mode. */
1036 md_number_to_chars (char *buf
, valueT val
, int n
)
1038 if (target_big_endian
)
1039 number_to_chars_bigendian (buf
, val
, n
);
1041 number_to_chars_littleendian (buf
, val
, n
);
1044 /* This should never be called for i860. */
1046 md_estimate_size_before_relax (register fragS
*fragP ATTRIBUTE_UNUSED
,
1047 segT segtype ATTRIBUTE_UNUSED
)
1049 as_fatal (_("i860_estimate_size_before_relax\n"));
1054 print_insn (struct i860_it
*insn
)
1057 fprintf (stderr
, "ERROR: %s\n", insn
->error
);
1059 fprintf (stderr
, "opcode = 0x%08lx\t", insn
->opcode
);
1060 fprintf (stderr
, "expand = 0x%x\t", insn
->expand
);
1061 fprintf (stderr
, "reloc = %s\t\n",
1062 bfd_get_reloc_code_name (insn
->reloc
));
1063 fprintf (stderr
, "exp = {\n");
1064 fprintf (stderr
, "\t\tX_add_symbol = %s\n",
1065 insn
->exp
.X_add_symbol
?
1066 (S_GET_NAME (insn
->exp
.X_add_symbol
) ?
1067 S_GET_NAME (insn
->exp
.X_add_symbol
) : "???") : "0");
1068 fprintf (stderr
, "\t\tX_op_symbol = %s\n",
1069 insn
->exp
.X_op_symbol
?
1070 (S_GET_NAME (insn
->exp
.X_op_symbol
) ?
1071 S_GET_NAME (insn
->exp
.X_op_symbol
) : "???") : "0");
1072 fprintf (stderr
, "\t\tX_add_number = %lx\n",
1073 insn
->exp
.X_add_number
);
1074 fprintf (stderr
, "}\n");
1076 #endif /* DEBUG_I860 */
1080 const char *md_shortopts
= "VQ:";
1082 const char *md_shortopts
= "";
1085 #define OPTION_EB (OPTION_MD_BASE + 0)
1086 #define OPTION_EL (OPTION_MD_BASE + 1)
1087 #define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2)
1088 #define OPTION_XP (OPTION_MD_BASE + 3)
1089 #define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4)
1091 struct option md_longopts
[] = {
1092 { "EB", no_argument
, NULL
, OPTION_EB
},
1093 { "EL", no_argument
, NULL
, OPTION_EL
},
1094 { "mwarn-expand", no_argument
, NULL
, OPTION_WARN_EXPAND
},
1095 { "mxp", no_argument
, NULL
, OPTION_XP
},
1096 { "mintel-syntax",no_argument
, NULL
, OPTION_INTEL_SYNTAX
},
1097 { NULL
, no_argument
, NULL
, 0 }
1099 size_t md_longopts_size
= sizeof (md_longopts
);
1102 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
1107 target_big_endian
= 1;
1111 target_big_endian
= 0;
1114 case OPTION_WARN_EXPAND
:
1115 target_warn_expand
= 1;
1122 case OPTION_INTEL_SYNTAX
:
1123 target_intel_syntax
= 1;
1127 /* SVR4 argument compatibility (-V): print version ID. */
1129 print_version_id ();
1132 /* SVR4 argument compatibility (-Qy, -Qn): controls whether
1133 a .comment section should be emitted or not (ignored). */
1146 md_show_usage (FILE *stream
)
1148 fprintf (stream
, _("\
1149 -EL generate code for little endian mode (default)\n\
1150 -EB generate code for big endian mode\n\
1151 -mwarn-expand warn if pseudo operations are expanded\n\
1152 -mxp enable i860XP support (disabled by default)\n\
1153 -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n"));
1155 /* SVR4 compatibility flags. */
1156 fprintf (stream
, _("\
1157 -V print assembler version number\n\
1158 -Qy, -Qn ignored\n"));
1163 /* We have no need to default values of symbols. */
1165 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1170 /* The i860 denotes auto-increment with '++'. */
1172 md_operand (expressionS
*exp
)
1176 for (s
= input_line_pointer
; *s
; s
++)
1178 if (s
[0] == '+' && s
[1] == '+')
1180 input_line_pointer
+= 2;
1181 exp
->X_op
= O_register
;
1187 /* Round up a section size to the appropriate boundary. */
1189 md_section_align (segT segment ATTRIBUTE_UNUSED
,
1190 valueT size ATTRIBUTE_UNUSED
)
1192 /* Byte alignment is fine. */
1196 /* On the i860, a PC-relative offset is relative to the address of the
1197 of the offset plus its size. */
1199 md_pcrel_from (fixS
*fixP
)
1201 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1204 /* Determine the relocation needed for non PC-relative 16-bit immediates.
1205 Also adjust the given immediate as necessary. Finally, check that
1206 all constraints (such as alignment) are satisfied. */
1207 static bfd_reloc_code_real_type
1208 obtain_reloc_for_imm16 (fixS
*fix
, long *val
)
1210 valueT fup
= fix
->fx_addnumber
;
1211 bfd_reloc_code_real_type reloc
;
1216 /* Check alignment restrictions. */
1217 if ((fup
& OP_ALIGN2
) && (*val
& 0x1))
1218 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1219 _("This immediate requires 0 MOD 2 alignment"));
1220 else if ((fup
& OP_ALIGN4
) && (*val
& 0x3))
1221 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1222 _("This immediate requires 0 MOD 4 alignment"));
1223 else if ((fup
& OP_ALIGN8
) && (*val
& 0x7))
1224 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1225 _("This immediate requires 0 MOD 8 alignment"));
1226 else if ((fup
& OP_ALIGN16
) && (*val
& 0xf))
1227 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1228 _("This immediate requires 0 MOD 16 alignment"));
1230 if (fup
& OP_SEL_HA
)
1232 *val
= (*val
>> 16) + (*val
& 0x8000 ? 1 : 0);
1233 reloc
= BFD_RELOC_860_HIGHADJ
;
1235 else if (fup
& OP_SEL_H
)
1238 reloc
= BFD_RELOC_860_HIGH
;
1240 else if (fup
& OP_SEL_L
)
1243 if (fup
& OP_IMM_SPLIT16
)
1245 if (fup
& OP_ENCODE1
)
1248 reloc
= BFD_RELOC_860_SPLIT1
;
1250 else if (fup
& OP_ENCODE2
)
1253 reloc
= BFD_RELOC_860_SPLIT2
;
1258 reloc
= BFD_RELOC_860_SPLIT0
;
1263 if (fup
& OP_ENCODE1
)
1266 reloc
= BFD_RELOC_860_LOW1
;
1268 else if (fup
& OP_ENCODE2
)
1271 reloc
= BFD_RELOC_860_LOW2
;
1273 else if (fup
& OP_ENCODE3
)
1276 reloc
= BFD_RELOC_860_LOW3
;
1281 reloc
= BFD_RELOC_860_LOW0
;
1285 /* Preserve size encode bits. */
1286 *val
&= ~((1 << num_encode
) - 1);
1290 /* No selector. What reloc do we generate (???)? */
1291 reloc
= BFD_RELOC_32
;
1297 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
1298 has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
1299 we will have to generate a reloc entry. */
1302 md_apply_fix3 (fixS
*fix
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1309 buf
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
1311 /* Recall that earlier we stored the opcode little-endian. */
1312 insn
= bfd_getl32 (buf
);
1314 /* We stored a fix-up in this oddly-named scratch field. */
1315 fup
= fix
->fx_addnumber
;
1317 /* Determine the necessary relocations as well as inserting an
1318 immediate into the instruction. */
1319 if (fup
& OP_IMM_U5
)
1322 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1323 _("5-bit immediate too large"));
1325 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1326 _("5-bit field must be absolute"));
1328 insn
|= (val
& 0x1f) << 11;
1329 bfd_putl32 (insn
, buf
);
1330 fix
->fx_r_type
= BFD_RELOC_NONE
;
1333 else if (fup
& OP_IMM_S16
)
1335 fix
->fx_r_type
= obtain_reloc_for_imm16 (fix
, &val
);
1337 /* Insert the immediate. */
1342 insn
|= val
& 0xffff;
1343 bfd_putl32 (insn
, buf
);
1344 fix
->fx_r_type
= BFD_RELOC_NONE
;
1348 else if (fup
& OP_IMM_U16
)
1351 else if (fup
& OP_IMM_SPLIT16
)
1353 fix
->fx_r_type
= obtain_reloc_for_imm16 (fix
, &val
);
1355 /* Insert the immediate. */
1360 insn
|= val
& 0x7ff;
1361 insn
|= (val
& 0xf800) << 5;
1362 bfd_putl32 (insn
, buf
);
1363 fix
->fx_r_type
= BFD_RELOC_NONE
;
1367 else if (fup
& OP_IMM_BR16
)
1370 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1371 _("A branch offset requires 0 MOD 4 alignment"));
1375 /* Insert the immediate. */
1379 fix
->fx_r_type
= BFD_RELOC_860_PC16
;
1383 insn
|= (val
& 0x7ff);
1384 insn
|= ((val
& 0xf800) << 5);
1385 bfd_putl32 (insn
, buf
);
1386 fix
->fx_r_type
= BFD_RELOC_NONE
;
1390 else if (fup
& OP_IMM_BR26
)
1393 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1394 _("A branch offset requires 0 MOD 4 alignment"));
1398 /* Insert the immediate. */
1401 fix
->fx_r_type
= BFD_RELOC_860_PC26
;
1406 insn
|= (val
& 0x3ffffff);
1407 bfd_putl32 (insn
, buf
);
1408 fix
->fx_r_type
= BFD_RELOC_NONE
;
1412 else if (fup
!= OP_NONE
)
1414 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1415 _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup
);
1420 /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000"
1421 reach here (???). */
1424 fix
->fx_r_type
= BFD_RELOC_32
;
1429 insn
|= (val
& 0xffffffff);
1430 bfd_putl32 (insn
, buf
);
1431 fix
->fx_r_type
= BFD_RELOC_NONE
;
1437 /* Generate a machine dependent reloc from a fixup. */
1439 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
1444 reloc
= xmalloc (sizeof (*reloc
));
1445 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1446 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1447 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1448 reloc
->addend
= fixp
->fx_offset
;
1449 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1453 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1454 "Cannot represent %s relocation in object file",
1455 bfd_get_reloc_code_name (fixp
->fx_r_type
));