gas/config/tc-i860.c

   1 /* tc-i860.c -- Assembler for the Intel i860 architecture.
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4
   5    Brought back from the dead and completely reworked
   6    by Jason Eckhardt <jle@cygnus.com>.
   7
   8    This file is part of GAS, the GNU Assembler.
   9
  10    GAS is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2, or (at your option)
  13    any later version.
  14
  15    GAS is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with GAS; see the file COPYING.  If not, write to the Free Software
  22    Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include "as.h"
  27 #include "safe-ctype.h"
  28 #include "subsegs.h"
  29 #include "opcode/i860.h"
  30 #include "elf/i860.h"
  31
  32
  33 /* The opcode hash table.  */
  34 static struct hash_control *op_hash = NULL;
  35
  36 /* These characters always start a comment.  */
  37 const char comment_chars[] = "#!/";
  38
  39 /* These characters start a comment at the beginning of a line.  */
  40 const char line_comment_chars[] = "#/";
  41
  42 const char line_separator_chars[] = ";";
  43
  44 /* Characters that can be used to separate the mantissa from the exponent
  45    in floating point numbers.  */
  46 const char EXP_CHARS[] = "eE";
  47
  48 /* Characters that indicate this number is a floating point constant.
  49    As in 0f12.456 or 0d1.2345e12.  */
  50 const char FLT_CHARS[] = "rRsSfFdDxXpP";
  51
  52 /* Register prefix (depends on syntax).  */
  53 static char reg_prefix;
  54
  55 #define MAX_FIXUPS 2
  56
  57 struct i860_it
  58 {
  59   char *error;
  60   unsigned long opcode;
  61   enum expand_type expand;
  62   struct i860_fi
  63   {
  64     expressionS exp;
  65     bfd_reloc_code_real_type reloc;
  66     int pcrel;
  67     valueT fup;
  68   } fi[MAX_FIXUPS];
  69 } the_insn;
  70
  71 /* The current fixup count.  */
  72 static int fc;
  73
  74 static char *expr_end;
  75
  76 /* Indicates error if a pseudo operation was expanded after a branch.  */
  77 static char last_expand;
  78
  79 /* If true, then warn if any pseudo operations were expanded.  */
  80 static int target_warn_expand = 0;
  81
  82 /* If true, then XP support is enabled.  */
  83 static int target_xp = 0;
  84
  85 /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax).  */
  86 static int target_intel_syntax = 0;
  87
  88
  89 /* Prototypes.  */
  90 static void i860_process_insn (char *);
  91 static void s_dual (int);
  92 static void s_enddual (int);
  93 static void s_atmp (int);
  94 static int i860_get_expression (char *);
  95 static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
  96 #ifdef DEBUG_I860
  97 static void print_insn (struct i860_it *);
  98 #endif
  99
 100 const pseudo_typeS md_pseudo_table[] =
 101 {
 102 #ifdef OBJ_ELF
 103   {"align",   s_align_bytes, 0},
 104 #endif
 105   {"dual",    s_dual,        0},
 106   {"enddual", s_enddual,     0},
 107   {"atmp",    s_atmp,        0},
 108   {NULL,      0,             0},
 109 };
 110
 111 /* Dual-instruction mode handling.  */
 112 enum dual
 113 {
 114   DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT,
 115 };
 116 static enum dual dual_mode = DUAL_OFF;
 117
 118 /* Handle ".dual" directive.  */
 119 static void
 120 s_dual (int ignore ATTRIBUTE_UNUSED)
 121 {
 122   dual_mode = DUAL_ON;
 123 }
 124
 125 /* Handle ".enddual" directive.  */
 126 static void
 127 s_enddual (int ignore ATTRIBUTE_UNUSED)
 128 {
 129   dual_mode = DUAL_OFF;
 130 }
 131
 132 /* Temporary register used when expanding assembler pseudo operations.  */
 133 static int atmp = 31;
 134
 135 static void
 136 s_atmp (int ignore ATTRIBUTE_UNUSED)
 137 {
 138   register int temp;
 139   if (strncmp (input_line_pointer, "sp", 2) == 0)
 140     {
 141       input_line_pointer += 2;
 142       atmp = 2;
 143     }
 144   else if (strncmp (input_line_pointer, "fp", 2) == 0)
 145     {
 146       input_line_pointer += 2;
 147       atmp = 3;
 148     }
 149   else if (strncmp (input_line_pointer, "r", 1) == 0)
 150     {
 151       input_line_pointer += 1;
 152       temp = get_absolute_expression ();
 153       if (temp >= 0 && temp <= 31)
 154         atmp = temp;
 155       else
 156         as_bad (_("Unknown temporary pseudo register"));
 157     }
 158   else
 159     {
 160       as_bad (_("Unknown temporary pseudo register"));
 161     }
 162   demand_empty_rest_of_line ();
 163 }
 164
 165 /* This function is called once, at assembler startup time.  It should
 166    set up all the tables and data structures that the MD part of the
 167    assembler will need.  */
 168 void
 169 md_begin (void)
 170 {
 171   const char *retval = NULL;
 172   int lose = 0;
 173   unsigned int i = 0;
 174
 175   op_hash = hash_new ();
 176
 177   while (i860_opcodes[i].name != NULL)
 178     {
 179       const char *name = i860_opcodes[i].name;
 180       retval = hash_insert (op_hash, name, (PTR)&i860_opcodes[i]);
 181       if (retval != NULL)
 182         {
 183           fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
 184                    i860_opcodes[i].name, retval);
 185           lose = 1;
 186         }
 187       do
 188         {
 189           if (i860_opcodes[i].match & i860_opcodes[i].lose)
 190             {
 191               fprintf (stderr,
 192                        _("internal error: losing opcode: `%s' \"%s\"\n"),
 193                        i860_opcodes[i].name, i860_opcodes[i].args);
 194               lose = 1;
 195             }
 196           ++i;
 197         }
 198       while (i860_opcodes[i].name != NULL
 199              && strcmp (i860_opcodes[i].name, name) == 0);
 200     }
 201
 202   if (lose)
 203     as_fatal (_("Defective assembler.  No assembly attempted."));
 204
 205   /* Set the register prefix for either Intel or AT&T/SVR4 syntax.  */
 206   reg_prefix = target_intel_syntax ? 0 : '%';
 207 }
 208
 209 /* This is the core of the machine-dependent assembler.  STR points to a
 210    machine dependent instruction.  This function emits the frags/bytes
 211    it assembles to.  */
 212 void
 213 md_assemble (char *str)
 214 {
 215   char *destp;
 216   int num_opcodes = 1;
 217   int i;
 218   struct i860_it pseudo[3];
 219
 220   assert (str);
 221   fc = 0;
 222
 223   /* Assemble the instruction.  */
 224   i860_process_insn (str);
 225
 226   /* Check for expandable flag to produce pseudo-instructions.  This
 227      is an undesirable feature that should be avoided.  */
 228   if (the_insn.expand != 0 && the_insn.expand != XP_ONLY
 229       && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
 230                             | OP_SEL_GOTOFF | OP_SEL_PLT)))
 231     {
 232       for (i = 0; i < 3; i++)
 233         pseudo[i] = the_insn;
 234
 235       fc = 1;
 236       switch (the_insn.expand)
 237         {
 238
 239         case E_DELAY:
 240           num_opcodes = 1;
 241           break;
 242
 243         case E_MOV:
 244           if (the_insn.fi[0].exp.X_add_symbol == NULL
 245               && the_insn.fi[0].exp.X_op_symbol == NULL
 246               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 247                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 248             break;
 249
 250           /* Emit "or l%const,r0,ireg_dest".  */
 251           pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000;
 252           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 253
 254           /* Emit "orh h%const,ireg_dest,ireg_dest".  */
 255           pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000
 256                               | ((the_insn.opcode & 0x001f0000) << 5);
 257           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 258
 259           num_opcodes = 2;
 260           break;
 261
 262         case E_ADDR:
 263           if (the_insn.fi[0].exp.X_add_symbol == NULL
 264               && the_insn.fi[0].exp.X_op_symbol == NULL
 265               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 266                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 267             break;
 268
 269           /* Emit "orh ha%addr_expr,r0,r31".  */
 270           pseudo[0].opcode = 0xec000000 | (atmp << 16);
 271           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA);
 272
 273           /* Emit "l%addr_expr(r31),ireg_dest".  We pick up the fixup
 274              information from the original instruction.   */
 275           pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21);
 276           pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L;
 277
 278           num_opcodes = 2;
 279           break;
 280
 281         case E_U32:
 282           if (the_insn.fi[0].exp.X_add_symbol == NULL
 283               && the_insn.fi[0].exp.X_op_symbol == NULL
 284               && (the_insn.fi[0].exp.X_add_number < (1 << 16)
 285                   && the_insn.fi[0].exp.X_add_number >= 0))
 286             break;
 287
 288           /* Emit "$(opcode)h h%const,ireg_src2,r31".  */
 289           pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000
 290                               | (atmp << 16);
 291           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 292
 293           /* Emit "$(opcode) l%const,r31,ireg_dest".  */
 294           pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000
 295                               | (atmp << 21);
 296           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 297
 298           num_opcodes = 2;
 299           break;
 300
 301         case E_AND:
 302           if (the_insn.fi[0].exp.X_add_symbol == NULL
 303               && the_insn.fi[0].exp.X_op_symbol == NULL
 304               && (the_insn.fi[0].exp.X_add_number < (1 << 16)
 305                   && the_insn.fi[0].exp.X_add_number >= 0))
 306             break;
 307
 308           /* Emit "andnot h%const,ireg_src2,r31".  */
 309           pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000
 310                               | (atmp << 16);
 311           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 312           pseudo[0].fi[0].exp.X_add_number =
 313             -1 - the_insn.fi[0].exp.X_add_number;
 314
 315           /* Emit "andnot l%const,r31,ireg_dest".  */
 316           pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000
 317                               | (atmp << 21);
 318           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 319           pseudo[1].fi[0].exp.X_add_number =
 320             -1 - the_insn.fi[0].exp.X_add_number;
 321
 322           num_opcodes = 2;
 323           break;
 324
 325         case E_S32:
 326           if (the_insn.fi[0].exp.X_add_symbol == NULL
 327               && the_insn.fi[0].exp.X_op_symbol == NULL
 328               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 329                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 330             break;
 331
 332           /* Emit "orh h%const,r0,r31".  */
 333           pseudo[0].opcode = 0xec000000 | (atmp << 16);
 334           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 335
 336           /* Emit "or l%const,r31,r31".  */
 337           pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16);
 338           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 339
 340           /* Emit "r31,ireg_src2,ireg_dest".  */
 341           pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11);
 342           pseudo[2].fi[0].fup = OP_IMM_S16;
 343
 344           num_opcodes = 3;
 345           break;
 346
 347         default:
 348           as_fatal (_("failed sanity check."));
 349         }
 350
 351       the_insn = pseudo[0];
 352
 353       /* Warn if an opcode is expanded after a delayed branch.  */
 354       if (num_opcodes > 1 && last_expand == 1)
 355         as_warn (_("Expanded opcode after delayed branch: `%s'"), str);
 356
 357       /* Warn if an opcode is expanded in dual mode.  */
 358       if (num_opcodes > 1 && dual_mode != DUAL_OFF)
 359         as_warn (_("Expanded opcode in dual mode: `%s'"), str);
 360
 361       /* Notify if any expansions happen.  */
 362       if (target_warn_expand && num_opcodes > 1)
 363         as_warn (_("An instruction was expanded (%s)"), str);
 364     }
 365
 366   i = 0;
 367   do
 368     {
 369       int tmp;
 370
 371       /* Output the opcode.  Note that the i860 always reads instructions
 372          as little-endian data.  */
 373       destp = frag_more (4);
 374       number_to_chars_littleendian (destp, the_insn.opcode, 4);
 375
 376       /* Check for expanded opcode after branch or in dual mode.  */
 377       last_expand = the_insn.fi[0].pcrel;
 378
 379       /* Output the symbol-dependent stuff.  Only btne and bte will ever
 380          loop more than once here, since only they (possibly) have more
 381          than one fixup.  */
 382       for (tmp = 0; tmp < fc; tmp++)
 383         {
 384           if (the_insn.fi[tmp].fup != OP_NONE)
 385             {
 386               fixS *fix;
 387               fix = fix_new_exp (frag_now,
 388                                  destp - frag_now->fr_literal,
 389                                  4,
 390                                  &the_insn.fi[tmp].exp,
 391                                  the_insn.fi[tmp].pcrel,
 392                                  the_insn.fi[tmp].reloc);
 393
 394              /* Despite the odd name, this is a scratch field.  We use
 395                 it to encode operand type information.  */
 396              fix->fx_addnumber = the_insn.fi[tmp].fup;
 397            }
 398         }
 399       the_insn = pseudo[++i];
 400     }
 401   while (--num_opcodes > 0);
 402
 403 }
 404
 405 /* Assemble the instruction pointed to by STR.  */
 406 static void
 407 i860_process_insn (char *str)
 408 {
 409   char *s;
 410   const char *args;
 411   char c;
 412   struct i860_opcode *insn;
 413   char *args_start;
 414   unsigned long opcode;
 415   unsigned int mask;
 416   int match = 0;
 417   int comma = 0;
 418
 419 #if 1 /* For compiler warnings.  */
 420   args = 0;
 421   insn = 0;
 422   args_start = 0;
 423   opcode = 0;
 424 #endif
 425
 426   for (s = str; ISLOWER (*s) || *s == '.' || *s == '3'
 427        || *s == '2' || *s == '1'; ++s)
 428     ;
 429
 430   switch (*s)
 431     {
 432     case '\0':
 433       break;
 434
 435     case ',':
 436       comma = 1;
 437
 438       /*FALLTHROUGH*/
 439
 440     case ' ':
 441       *s++ = '\0';
 442       break;
 443
 444     default:
 445       as_fatal (_("Unknown opcode: `%s'"), str);
 446     }
 447
 448   /* Check for dual mode ("d.") opcode prefix.  */
 449   if (strncmp (str, "d.", 2) == 0)
 450     {
 451       if (dual_mode == DUAL_ON)
 452         dual_mode = DUAL_ONDDOT;
 453       else
 454         dual_mode = DUAL_DDOT;
 455       str += 2;
 456     }
 457
 458   if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL)
 459     {
 460       if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT)
 461         str -= 2;
 462       as_bad (_("Unknown opcode: `%s'"), str);
 463       return;
 464     }
 465
 466   if (comma)
 467     *--s = ',';
 468
 469   args_start = s;
 470   for (;;)
 471     {
 472       int t;
 473       opcode = insn->match;
 474       memset (&the_insn, '\0', sizeof (the_insn));
 475       fc = 0;
 476       for (t = 0; t < MAX_FIXUPS; t++)
 477         {
 478           the_insn.fi[t].reloc = BFD_RELOC_NONE;
 479           the_insn.fi[t].pcrel = 0;
 480           the_insn.fi[t].fup = OP_NONE;
 481         }
 482
 483       /* Build the opcode, checking as we go that the operands match.  */
 484       for (args = insn->args; ; ++args)
 485         {
 486           if (fc > MAX_FIXUPS)
 487             abort ();
 488
 489           switch (*args)
 490             {
 491
 492             /* End of args.  */
 493             case '\0':
 494               if (*s == '\0')
 495                 match = 1;
 496               break;
 497
 498             /* These must match exactly.  */
 499             case '+':
 500             case '(':
 501             case ')':
 502             case ',':
 503             case ' ':
 504               if (*s++ == *args)
 505                 continue;
 506               break;
 507
 508             /* Must be at least one digit.  */
 509             case '#':
 510               if (ISDIGIT (*s++))
 511                 {
 512                   while (ISDIGIT (*s))
 513                     ++s;
 514                   continue;
 515                 }
 516               break;
 517
 518             /* Next operand must be a register.  */
 519             case '1':
 520             case '2':
 521             case 'd':
 522               /* Check for register prefix if necessary.  */
 523               if (reg_prefix && *s != reg_prefix)
 524                 goto error;
 525               else if (reg_prefix)
 526                 s++;
 527
 528               switch (*s)
 529                 {
 530                 /* Frame pointer.  */
 531                 case 'f':
 532                   s++;
 533                   if (*s++ == 'p')
 534                     {
 535                       mask = 0x3;
 536                       break;
 537                     }
 538                   goto error;
 539
 540                 /* Stack pointer.  */
 541                 case 's':
 542                   s++;
 543                   if (*s++ == 'p')
 544                     {
 545                       mask = 0x2;
 546                       break;
 547                     }
 548                   goto error;
 549
 550                 /* Any register r0..r31.  */
 551                 case 'r':
 552                   s++;
 553                   if (!ISDIGIT (c = *s++))
 554                     {
 555                       goto error;
 556                     }
 557                   if (ISDIGIT (*s))
 558                     {
 559                       if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
 560                         goto error;
 561                     }
 562                   else
 563                     c -= '0';
 564                   mask = c;
 565                   break;
 566
 567                 /* Not this opcode.  */
 568                 default:
 569                   goto error;
 570                 }
 571
 572               /* Obtained the register, now place it in the opcode.  */
 573               switch (*args)
 574                 {
 575                 case '1':
 576                   opcode |= mask << 11;
 577                   continue;
 578
 579                 case '2':
 580                   opcode |= mask << 21;
 581                   continue;
 582
 583                 case 'd':
 584                   opcode |= mask << 16;
 585                   continue;
 586
 587                 }
 588               break;
 589
 590             /* Next operand is a floating point register.  */
 591             case 'e':
 592             case 'f':
 593             case 'g':
 594               /* Check for register prefix if necessary.  */
 595               if (reg_prefix && *s != reg_prefix)
 596                 goto error;
 597               else if (reg_prefix)
 598                 s++;
 599
 600               if (*s++ == 'f' && ISDIGIT (*s))
 601                 {
 602                   mask = *s++;
 603                   if (ISDIGIT (*s))
 604                     {
 605                       mask = 10 * (mask - '0') + (*s++ - '0');
 606                       if (mask >= 32)
 607                         {
 608                           break;
 609                         }
 610                     }
 611                   else
 612                     mask -= '0';
 613
 614                   switch (*args)
 615                     {
 616
 617                     case 'e':
 618                       opcode |= mask << 11;
 619                       continue;
 620
 621                     case 'f':
 622                       opcode |= mask << 21;
 623                       continue;
 624
 625                     case 'g':
 626                       opcode |= mask << 16;
 627                       if (dual_mode != DUAL_OFF)
 628                         opcode |= (1 << 9);
 629                       if (dual_mode == DUAL_DDOT)
 630                         dual_mode = DUAL_OFF;
 631                       if (dual_mode == DUAL_ONDDOT)
 632                         dual_mode = DUAL_ON;
 633                       if ((opcode & (1 << 10)) && mask != 0
 634                           && (mask == ((opcode >> 11) & 0x1f)))
 635                         as_warn (_("Pipelined instruction: fsrc1 = fdest"));
 636                       continue;
 637                     }
 638                 }
 639               break;
 640
 641             /* Next operand must be a control register.  */
 642             case 'c':
 643               /* Check for register prefix if necessary.  */
 644               if (reg_prefix && *s != reg_prefix)
 645                 goto error;
 646               else if (reg_prefix)
 647                 s++;
 648
 649               if (strncmp (s, "fir", 3) == 0)
 650                 {
 651                   opcode |= 0x0 << 21;
 652                   s += 3;
 653                   continue;
 654                 }
 655               if (strncmp (s, "psr", 3) == 0)
 656                 {
 657                   opcode |= 0x1 << 21;
 658                   s += 3;
 659                   continue;
 660                 }
 661               if (strncmp (s, "dirbase", 7) == 0)
 662                 {
 663                   opcode |= 0x2 << 21;
 664                   s += 7;
 665                   continue;
 666                 }
 667               if (strncmp (s, "db", 2) == 0)
 668                 {
 669                   opcode |= 0x3 << 21;
 670                   s += 2;
 671                   continue;
 672                 }
 673               if (strncmp (s, "fsr", 3) == 0)
 674                 {
 675                   opcode |= 0x4 << 21;
 676                   s += 3;
 677                   continue;
 678                 }
 679               if (strncmp (s, "epsr", 4) == 0)
 680                 {
 681                   opcode |= 0x5 << 21;
 682                   s += 4;
 683                   continue;
 684                 }
 685               /* The remaining control registers are XP only.  */
 686               if (target_xp && strncmp (s, "bear", 4) == 0)
 687                 {
 688                   opcode |= 0x6 << 21;
 689                   s += 4;
 690                   continue;
 691                 }
 692               if (target_xp && strncmp (s, "ccr", 3) == 0)
 693                 {
 694                   opcode |= 0x7 << 21;
 695                   s += 3;
 696                   continue;
 697                 }
 698               if (target_xp && strncmp (s, "p0", 2) == 0)
 699                 {
 700                   opcode |= 0x8 << 21;
 701                   s += 2;
 702                   continue;
 703                 }
 704               if (target_xp && strncmp (s, "p1", 2) == 0)
 705                 {
 706                   opcode |= 0x9 << 21;
 707                   s += 2;
 708                   continue;
 709                 }
 710               if (target_xp && strncmp (s, "p2", 2) == 0)
 711                 {
 712                   opcode |= 0xa << 21;
 713                   s += 2;
 714                   continue;
 715                 }
 716               if (target_xp && strncmp (s, "p3", 2) == 0)
 717                 {
 718                   opcode |= 0xb << 21;
 719                   s += 2;
 720                   continue;
 721                 }
 722               break;
 723
 724             /* 5-bit immediate in src1.  */
 725             case '5':
 726               if (! i860_get_expression (s))
 727                 {
 728                   s = expr_end;
 729                   the_insn.fi[fc].fup |= OP_IMM_U5;
 730                   fc++;
 731                   continue;
 732                 }
 733               break;
 734
 735             /* 26-bit immediate, relative branch (lbroff).  */
 736             case 'l':
 737               the_insn.fi[fc].pcrel = 1;
 738               the_insn.fi[fc].fup |= OP_IMM_BR26;
 739               goto immediate;
 740
 741             /* 16-bit split immediate, relative branch (sbroff).  */
 742             case 'r':
 743               the_insn.fi[fc].pcrel = 1;
 744               the_insn.fi[fc].fup |= OP_IMM_BR16;
 745               goto immediate;
 746
 747             /* 16-bit split immediate.  */
 748             case 's':
 749               the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
 750               goto immediate;
 751
 752             /* 16-bit split immediate, byte aligned (st.b).  */
 753             case 'S':
 754               the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
 755               goto immediate;
 756
 757             /* 16-bit split immediate, half-word aligned (st.s).  */
 758             case 'T':
 759               the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2);
 760               goto immediate;
 761
 762             /* 16-bit split immediate, word aligned (st.l).  */
 763             case 'U':
 764               the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4);
 765               goto immediate;
 766
 767             /* 16-bit immediate.  */
 768             case 'i':
 769               the_insn.fi[fc].fup |= OP_IMM_S16;
 770               goto immediate;
 771
 772             /* 16-bit immediate, byte aligned (ld.b).  */
 773             case 'I':
 774               the_insn.fi[fc].fup |= OP_IMM_S16;
 775               goto immediate;
 776
 777             /* 16-bit immediate, half-word aligned (ld.s).  */
 778             case 'J':
 779               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2);
 780               goto immediate;
 781
 782             /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l).  */
 783             case 'K':
 784               if (insn->name[0] == 'l')
 785                 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4);
 786               else
 787                 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4);
 788               goto immediate;
 789
 790             /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d).  */
 791             case 'L':
 792               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8);
 793               goto immediate;
 794
 795             /* 16-bit immediate, quad-word aligned (fld.q, fst.q).  */
 796             case 'M':
 797               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16);
 798
 799               /*FALLTHROUGH*/
 800
 801               /* Handle the immediate for either the Intel syntax or
 802                  SVR4 syntax. The Intel syntax is "ha%immediate"
 803                  whereas SVR4 syntax is "[immediate]@ha".  */
 804             immediate:
 805               if (target_intel_syntax == 0)
 806                 {
 807                   /* AT&T/SVR4 syntax.  */
 808                   if (*s == ' ')
 809                     s++;
 810
 811                   /* Note that if i860_get_expression() fails, we will still
 812                      have created U entries in the symbol table for the
 813                      'symbols' in the input string.  Try not to create U
 814                      symbols for registers, etc.  */
 815                   if (! i860_get_expression (s))
 816                     s = expr_end;
 817                   else
 818                     goto error;
 819
 820                   if (strncmp (s, "@ha", 3) == 0)
 821                     {
 822                       the_insn.fi[fc].fup |= OP_SEL_HA;
 823                       s += 3;
 824                     }
 825                   else if (strncmp (s, "@h", 2) == 0)
 826                     {
 827                       the_insn.fi[fc].fup |= OP_SEL_H;
 828                       s += 2;
 829                     }
 830                   else if (strncmp (s, "@l", 2) == 0)
 831                     {
 832                       the_insn.fi[fc].fup |= OP_SEL_L;
 833                       s += 2;
 834                     }
 835                   else if (strncmp (s, "@gotoff", 7) == 0
 836                            || strncmp (s, "@GOTOFF", 7) == 0)
 837                     {
 838                       as_bad (_("Assembler does not yet support PIC"));
 839                       the_insn.fi[fc].fup |= OP_SEL_GOTOFF;
 840                       s += 7;
 841                     }
 842                   else if (strncmp (s, "@got", 4) == 0
 843                            || strncmp (s, "@GOT", 4) == 0)
 844                     {
 845                       as_bad (_("Assembler does not yet support PIC"));
 846                       the_insn.fi[fc].fup |= OP_SEL_GOT;
 847                       s += 4;
 848                     }
 849                   else if (strncmp (s, "@plt", 4) == 0
 850                            || strncmp (s, "@PLT", 4) == 0)
 851                     {
 852                       as_bad (_("Assembler does not yet support PIC"));
 853                       the_insn.fi[fc].fup |= OP_SEL_PLT;
 854                       s += 4;
 855                     }
 856
 857                   the_insn.expand = insn->expand;
 858                   fc++;
 859
 860                   continue;
 861                 }
 862               else
 863                 {
 864                   /* Intel syntax.  */
 865                   if (*s == ' ')
 866                     s++;
 867                   if (strncmp (s, "ha%", 3) == 0)
 868                     {
 869                       the_insn.fi[fc].fup |= OP_SEL_HA;
 870                       s += 3;
 871                     }
 872                   else if (strncmp (s, "h%", 2) == 0)
 873                     {
 874                       the_insn.fi[fc].fup |= OP_SEL_H;
 875                       s += 2;
 876                     }
 877                   else if (strncmp (s, "l%", 2) == 0)
 878                     {
 879                       the_insn.fi[fc].fup |= OP_SEL_L;
 880                       s += 2;
 881                     }
 882                   the_insn.expand = insn->expand;
 883
 884                   /* Note that if i860_get_expression() fails, we will still
 885                      have created U entries in the symbol table for the
 886                      'symbols' in the input string.  Try not to create U
 887                      symbols for registers, etc.  */
 888                   if (! i860_get_expression (s))
 889                     s = expr_end;
 890                   else
 891                     goto error;
 892
 893                   fc++;
 894                   continue;
 895                 }
 896               break;
 897
 898             default:
 899               as_fatal (_("failed sanity check."));
 900             }
 901           break;
 902         }
 903     error:
 904       if (match == 0)
 905         {
 906           /* Args don't match.  */
 907           if (insn[1].name != NULL
 908               && ! strcmp (insn->name, insn[1].name))
 909             {
 910               ++insn;
 911               s = args_start;
 912               continue;
 913             }
 914           else
 915             {
 916               as_bad (_("Illegal operands for %s"), insn->name);
 917               return;
 918             }
 919         }
 920       break;
 921     }
 922
 923   the_insn.opcode = opcode;
 924
 925   /* Only recognize XP instructions when the user has requested it.  */
 926   if (insn->expand == XP_ONLY && ! target_xp)
 927     as_bad (_("Unknown opcode: `%s'"), insn->name);
 928 }
 929
 930 static int
 931 i860_get_expression (char *str)
 932 {
 933   char *save_in;
 934   segT seg;
 935
 936   save_in = input_line_pointer;
 937   input_line_pointer = str;
 938   seg = expression (&the_insn.fi[fc].exp);
 939   if (seg != absolute_section
 940       && seg != undefined_section
 941       && ! SEG_NORMAL (seg))
 942     {
 943       the_insn.error = _("bad segment");
 944       expr_end = input_line_pointer;
 945       input_line_pointer = save_in;
 946       return 1;
 947     }
 948   expr_end = input_line_pointer;
 949   input_line_pointer = save_in;
 950   return 0;
 951 }
 952
 953 /* Turn a string in input_line_pointer into a floating point constant of
 954    type TYPE, and store the appropriate bytes in *LITP.  The number of
 955    LITTLENUMS emitted is stored in *SIZEP.  An error message is returned,
 956    or NULL on OK.  */
 957
 958 /* Equal to MAX_PRECISION in atof-ieee.c.  */
 959 #define MAX_LITTLENUMS 6
 960
 961 char *
 962 md_atof (int type, char *litP, int *sizeP)
 963 {
 964   int prec;
 965   LITTLENUM_TYPE words[MAX_LITTLENUMS];
 966   LITTLENUM_TYPE *wordP;
 967   char *t;
 968
 969   switch (type)
 970     {
 971     case 'f':
 972     case 'F':
 973     case 's':
 974     case 'S':
 975       prec = 2;
 976       break;
 977
 978     case 'd':
 979     case 'D':
 980     case 'r':
 981     case 'R':
 982       prec = 4;
 983       break;
 984
 985     case 'x':
 986     case 'X':
 987       prec = 6;
 988       break;
 989
 990     case 'p':
 991     case 'P':
 992       prec = 6;
 993       break;
 994
 995     default:
 996       *sizeP = 0;
 997       return _("Bad call to MD_ATOF()");
 998     }
 999   t = atof_ieee (input_line_pointer, type, words);
1000   if (t)
1001     input_line_pointer = t;
1002   *sizeP = prec * sizeof (LITTLENUM_TYPE);
1003   for (wordP = words; prec--;)
1004     {
1005       md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
1006       litP += sizeof (LITTLENUM_TYPE);
1007     }
1008   return 0;
1009 }
1010
1011 /* Write out in current endian mode.  */
1012 void
1013 md_number_to_chars (char *buf, valueT val, int n)
1014 {
1015   if (target_big_endian)
1016     number_to_chars_bigendian (buf, val, n);
1017   else
1018     number_to_chars_littleendian (buf, val, n);
1019 }
1020
1021 /* This should never be called for i860.  */
1022 int
1023 md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED,
1024                                segT segtype ATTRIBUTE_UNUSED)
1025 {
1026   as_fatal (_("i860_estimate_size_before_relax\n"));
1027 }
1028
1029 #ifdef DEBUG_I860
1030 static void
1031 print_insn (struct i860_it *insn)
1032 {
1033   if (insn->error)
1034     fprintf (stderr, "ERROR: %s\n", insn->error);
1035
1036   fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode);
1037   fprintf (stderr, "expand = 0x%x\t", insn->expand);
1038   fprintf (stderr, "reloc = %s\t\n",
1039            bfd_get_reloc_code_name (insn->reloc));
1040   fprintf (stderr, "exp =  {\n");
1041   fprintf (stderr, "\t\tX_add_symbol = %s\n",
1042            insn->exp.X_add_symbol ?
1043            (S_GET_NAME (insn->exp.X_add_symbol) ?
1044             S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0");
1045   fprintf (stderr, "\t\tX_op_symbol = %s\n",
1046            insn->exp.X_op_symbol ?
1047            (S_GET_NAME (insn->exp.X_op_symbol) ?
1048             S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0");
1049   fprintf (stderr, "\t\tX_add_number = %lx\n",
1050            insn->exp.X_add_number);
1051   fprintf (stderr, "}\n");
1052 }
1053 #endif /* DEBUG_I860 */
1054
1055 \f
1056 #ifdef OBJ_ELF
1057 const char *md_shortopts = "VQ:";
1058 #else
1059 const char *md_shortopts = "";
1060 #endif
1061
1062 #define OPTION_EB               (OPTION_MD_BASE + 0)
1063 #define OPTION_EL               (OPTION_MD_BASE + 1)
1064 #define OPTION_WARN_EXPAND      (OPTION_MD_BASE + 2)
1065 #define OPTION_XP               (OPTION_MD_BASE + 3)
1066 #define OPTION_INTEL_SYNTAX     (OPTION_MD_BASE + 4)
1067
1068 struct option md_longopts[] = {
1069   { "EB",           no_argument, NULL, OPTION_EB },
1070   { "EL",           no_argument, NULL, OPTION_EL },
1071   { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
1072   { "mxp",          no_argument, NULL, OPTION_XP },
1073   { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX },
1074   { NULL,           no_argument, NULL, 0 }
1075 };
1076 size_t md_longopts_size = sizeof (md_longopts);
1077
1078 int
1079 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
1080 {
1081   switch (c)
1082     {
1083     case OPTION_EB:
1084       target_big_endian = 1;
1085       break;
1086
1087     case OPTION_EL:
1088       target_big_endian = 0;
1089       break;
1090
1091     case OPTION_WARN_EXPAND:
1092       target_warn_expand = 1;
1093       break;
1094
1095     case OPTION_XP:
1096       target_xp = 1;
1097       break;
1098
1099     case OPTION_INTEL_SYNTAX:
1100       target_intel_syntax = 1;
1101       break;
1102
1103 #ifdef OBJ_ELF
1104     /* SVR4 argument compatibility (-V): print version ID.  */
1105     case 'V':
1106       print_version_id ();
1107       break;
1108
1109     /* SVR4 argument compatibility (-Qy, -Qn): controls whether
1110        a .comment section should be emitted or not (ignored).  */
1111     case 'Q':
1112       break;
1113 #endif
1114
1115     default:
1116       return 0;
1117     }
1118
1119   return 1;
1120 }
1121
1122 void
1123 md_show_usage (FILE *stream)
1124 {
1125   fprintf (stream, _("\
1126   -EL                     generate code for little endian mode (default)\n\
1127   -EB                     generate code for big endian mode\n\
1128   -mwarn-expand           warn if pseudo operations are expanded\n\
1129   -mxp                    enable i860XP support (disabled by default)\n\
1130   -mintel-syntax          enable Intel syntax (default to AT&T/SVR4)\n"));
1131 #ifdef OBJ_ELF
1132   /* SVR4 compatibility flags.  */
1133   fprintf (stream, _("\
1134   -V                      print assembler version number\n\
1135   -Qy, -Qn                ignored\n"));
1136 #endif
1137 }
1138
1139 \f
1140 /* We have no need to default values of symbols.  */
1141 symbolS *
1142 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1143 {
1144   return 0;
1145 }
1146
1147 /* The i860 denotes auto-increment with '++'.  */
1148 void
1149 md_operand (expressionS *exp)
1150 {
1151   char *s;
1152
1153   for (s = input_line_pointer; *s; s++)
1154     {
1155       if (s[0] == '+' && s[1] == '+')
1156         {
1157           input_line_pointer += 2;
1158           exp->X_op = O_register;
1159           break;
1160         }
1161     }
1162 }
1163
1164 /* Round up a section size to the appropriate boundary.  */
1165 valueT
1166 md_section_align (segT segment ATTRIBUTE_UNUSED,
1167                   valueT size ATTRIBUTE_UNUSED)
1168 {
1169   /* Byte alignment is fine.  */
1170   return size;
1171 }
1172
1173 /* On the i860, a PC-relative offset is relative to the address of the
1174    of the offset plus its size.  */
1175 long
1176 md_pcrel_from (fixS *fixP)
1177 {
1178   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
1179 }
1180
1181 /* Determine the relocation needed for non PC-relative 16-bit immediates.
1182    Also adjust the given immediate as necessary.  Finally, check that
1183    all constraints (such as alignment) are satisfied.   */
1184 static bfd_reloc_code_real_type
1185 obtain_reloc_for_imm16 (fixS *fix, long *val)
1186 {
1187   valueT fup = fix->fx_addnumber;
1188   bfd_reloc_code_real_type reloc;
1189
1190   if (fix->fx_pcrel)
1191     abort ();
1192
1193   /* Check alignment restrictions.  */
1194   if ((fup & OP_ALIGN2) && (*val & 0x1))
1195     as_bad_where (fix->fx_file, fix->fx_line,
1196                   _("This immediate requires 0 MOD 2 alignment"));
1197   else if ((fup & OP_ALIGN4) && (*val & 0x3))
1198     as_bad_where (fix->fx_file, fix->fx_line,
1199                   _("This immediate requires 0 MOD 4 alignment"));
1200   else if ((fup & OP_ALIGN8) && (*val & 0x7))
1201     as_bad_where (fix->fx_file, fix->fx_line,
1202                   _("This immediate requires 0 MOD 8 alignment"));
1203   else if ((fup & OP_ALIGN16) && (*val & 0xf))
1204     as_bad_where (fix->fx_file, fix->fx_line,
1205                   _("This immediate requires 0 MOD 16 alignment"));
1206
1207   if (fup & OP_SEL_HA)
1208     {
1209       *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0);
1210       reloc = BFD_RELOC_860_HIGHADJ;
1211     }
1212   else if (fup & OP_SEL_H)
1213     {
1214       *val >>= 16;
1215       reloc = BFD_RELOC_860_HIGH;
1216     }
1217   else if (fup & OP_SEL_L)
1218     {
1219       int num_encode;
1220       if (fup & OP_IMM_SPLIT16)
1221         {
1222           if (fup & OP_ENCODE1)
1223             {
1224               num_encode = 1;
1225               reloc = BFD_RELOC_860_SPLIT1;
1226             }
1227           else if (fup & OP_ENCODE2)
1228             {
1229               num_encode = 2;
1230               reloc = BFD_RELOC_860_SPLIT2;
1231             }
1232           else
1233             {
1234               num_encode = 0;
1235               reloc = BFD_RELOC_860_SPLIT0;
1236             }
1237         }
1238       else
1239         {
1240           if (fup & OP_ENCODE1)
1241             {
1242               num_encode = 1;
1243               reloc = BFD_RELOC_860_LOW1;
1244             }
1245           else if (fup & OP_ENCODE2)
1246             {
1247               num_encode = 2;
1248               reloc = BFD_RELOC_860_LOW2;
1249             }
1250           else if (fup & OP_ENCODE3)
1251             {
1252               num_encode = 3;
1253               reloc = BFD_RELOC_860_LOW3;
1254             }
1255           else
1256             {
1257               num_encode = 0;
1258               reloc = BFD_RELOC_860_LOW0;
1259             }
1260         }
1261
1262       /* Preserve size encode bits.  */
1263       *val &= ~((1 << num_encode) - 1);
1264     }
1265   else
1266     {
1267       /* No selector.  What reloc do we generate (???)?  */
1268       reloc = BFD_RELOC_32;
1269     }
1270
1271   return reloc;
1272 }
1273
1274 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
1275    has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
1276    we will have to generate a reloc entry.  */
1277
1278 void
1279 md_apply_fix3 (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1280 {
1281   char *buf;
1282   long val = *valP;
1283   unsigned long insn;
1284   valueT fup;
1285
1286   buf = fix->fx_frag->fr_literal + fix->fx_where;
1287
1288   /* Recall that earlier we stored the opcode little-endian.  */
1289   insn = bfd_getl32 (buf);
1290
1291   /* We stored a fix-up in this oddly-named scratch field.  */
1292   fup = fix->fx_addnumber;
1293
1294   /* Determine the necessary relocations as well as inserting an
1295      immediate into the instruction.   */
1296   if (fup & OP_IMM_U5)
1297     {
1298       if (val & ~0x1f)
1299         as_bad_where (fix->fx_file, fix->fx_line,
1300                       _("5-bit immediate too large"));
1301       if (fix->fx_addsy)
1302         as_bad_where (fix->fx_file, fix->fx_line,
1303                       _("5-bit field must be absolute"));
1304
1305       insn |= (val & 0x1f) << 11;
1306       bfd_putl32 (insn, buf);
1307       fix->fx_r_type = BFD_RELOC_NONE;
1308       fix->fx_done = 1;
1309     }
1310   else if (fup & OP_IMM_S16)
1311     {
1312       fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1313
1314       /* Insert the immediate.  */
1315       if (fix->fx_addsy)
1316         fix->fx_done = 0;
1317       else
1318         {
1319           insn |= val & 0xffff;
1320           bfd_putl32 (insn, buf);
1321           fix->fx_r_type = BFD_RELOC_NONE;
1322           fix->fx_done = 1;
1323         }
1324     }
1325   else if (fup & OP_IMM_U16)
1326     abort ();
1327
1328   else if (fup & OP_IMM_SPLIT16)
1329     {
1330       fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1331
1332       /* Insert the immediate.  */
1333       if (fix->fx_addsy)
1334         fix->fx_done = 0;
1335       else
1336         {
1337           insn |= val & 0x7ff;
1338           insn |= (val & 0xf800) << 5;
1339           bfd_putl32 (insn, buf);
1340           fix->fx_r_type = BFD_RELOC_NONE;
1341           fix->fx_done = 1;
1342         }
1343     }
1344   else if (fup & OP_IMM_BR16)
1345     {
1346       if (val & 0x3)
1347         as_bad_where (fix->fx_file, fix->fx_line,
1348                       _("A branch offset requires 0 MOD 4 alignment"));
1349
1350       val = val >> 2;
1351
1352       /* Insert the immediate.  */
1353       if (fix->fx_addsy)
1354         {
1355           fix->fx_done = 0;
1356           fix->fx_r_type = BFD_RELOC_860_PC16;
1357         }
1358       else
1359         {
1360           insn |= (val & 0x7ff);
1361           insn |= ((val & 0xf800) << 5);
1362           bfd_putl32 (insn, buf);
1363           fix->fx_r_type = BFD_RELOC_NONE;
1364           fix->fx_done = 1;
1365         }
1366     }
1367   else if (fup & OP_IMM_BR26)
1368     {
1369       if (val & 0x3)
1370         as_bad_where (fix->fx_file, fix->fx_line,
1371                       _("A branch offset requires 0 MOD 4 alignment"));
1372
1373       val >>= 2;
1374
1375       /* Insert the immediate.  */
1376       if (fix->fx_addsy)
1377         {
1378           fix->fx_r_type = BFD_RELOC_860_PC26;
1379           fix->fx_done = 0;
1380         }
1381       else
1382         {
1383           insn |= (val & 0x3ffffff);
1384           bfd_putl32 (insn, buf);
1385           fix->fx_r_type = BFD_RELOC_NONE;
1386           fix->fx_done = 1;
1387         }
1388     }
1389   else if (fup != OP_NONE)
1390     {
1391       as_bad_where (fix->fx_file, fix->fx_line,
1392                     _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup);
1393       abort ();
1394     }
1395   else
1396     {
1397       /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000"
1398          reach here (???).  */
1399       if (fix->fx_addsy)
1400         {
1401           fix->fx_r_type = BFD_RELOC_32;
1402           fix->fx_done = 0;
1403         }
1404       else
1405         {
1406           insn |= (val & 0xffffffff);
1407           bfd_putl32 (insn, buf);
1408           fix->fx_r_type = BFD_RELOC_NONE;
1409           fix->fx_done = 1;
1410         }
1411     }
1412 }
1413
1414 /* Generate a machine dependent reloc from a fixup.  */
1415 arelent*
1416 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
1417               fixS *fixp)
1418 {
1419   arelent *reloc;
1420
1421   reloc = xmalloc (sizeof (*reloc));
1422   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1423   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1424   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1425   reloc->addend = fixp->fx_offset;
1426   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1427
1428   if (! reloc->howto)
1429     {
1430       as_bad_where (fixp->fx_file, fixp->fx_line,
1431                     "Cannot represent %s relocation in object file",
1432                     bfd_get_reloc_code_name (fixp->fx_r_type));
1433     }
1434   return reloc;
1435 }