1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 ***************************************************************************** */
34 /* There are 4 different lengths of (potentially) symbol-based displacements
35 * in the 80960 instruction set, each of which could require address fix-ups
36 * and (in the case of external symbols) emission of relocation directives:
39 * This is a standard length for the base assembler and requires no
43 * This is a non-standard length, but the base assembler has a hook for
44 * bit field address fixups: the fixS structure can point to a descriptor
45 * of the field, in which case our md_number_to_field() routine gets called
48 * I made the hook a little cleaner by having fix_new() (in the base
49 * assembler) return a pointer to the fixS in question. And I made it a
50 * little simpler by storing the field size (in this case 13) instead of
51 * of a pointer to another structure: 80960 displacements are ALWAYS
52 * stored in the low-order bits of a 4-byte word.
54 * Since the target of a COBR cannot be external, no relocation directives
55 * for this size displacement have to be generated. But the base assembler
56 * had to be modified to issue error messages if the symbol did turn out
60 * Fixups are handled as for the 13-bit case (except that 24 is stored
63 * The relocation directive generated is the same as that for the 32-bit
64 * displacement, except that it's PC-relative (the 32-bit displacement
65 * never is). The i80960 version of the linker needs a mod to
66 * distinguish and handle the 24-bit case.
69 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
70 * is based on a symbol, because it could be relocated at link time.
71 * The only time we use the 12-bit format is if an absolute value of
72 * less than 4096 is specified, in which case we need neither a fixup nor
73 * a relocation directive.
83 #include "opcode/i960.h"
85 extern char *input_line_pointer
;
86 extern struct hash_control
*po_hash
;
87 extern char *next_object_file_charP
;
90 int md_reloc_size
= sizeof(struct reloc
);
92 int md_reloc_size
= sizeof(struct relocation_info
);
95 /***************************
96 * Local i80960 routines *
97 ************************** */
99 static void brcnt_emit(); /* Emit branch-prediction instrumentation code */
100 static char * brlab_next(); /* Return next branch local label */
101 void brtab_emit(); /* Emit br-predict instrumentation table */
102 static void cobr_fmt(); /* Generate COBR instruction */
103 static void ctrl_fmt(); /* Generate CTRL instruction */
104 static char * emit(); /* Emit (internally) binary */
105 static int get_args(); /* Break arguments out of comma-separated list */
106 static void get_cdisp(); /* Handle COBR or CTRL displacement */
107 static char * get_ispec(); /* Find index specification string */
108 static int get_regnum(); /* Translate text to register number */
109 static int i_scan(); /* Lexical scan of instruction source */
110 static void mem_fmt(); /* Generate MEMA or MEMB instruction */
111 static void mema_to_memb(); /* Convert MEMA instruction to MEMB format */
112 static segT
parse_expr(); /* Parse an expression */
113 static int parse_ldconst();/* Parse and replace a 'ldconst' pseudo-op */
114 static void parse_memop(); /* Parse a memory operand */
115 static void parse_po(); /* Parse machine-dependent pseudo-op */
116 static void parse_regop(); /* Parse a register operand */
117 static void reg_fmt(); /* Generate a REG format instruction */
118 void reloc_callj(); /* Relocate a 'callj' instruction */
119 static void relax_cobr(); /* "De-optimize" cobr into compare/branch */
120 static void s_leafproc(); /* Process '.leafproc' pseudo-op */
121 static void s_sysproc(); /* Process '.sysproc' pseudo-op */
122 static int shift_ok(); /* Will a 'shlo' substiture for a 'ldconst'? */
123 static void syntax(); /* Give syntax error */
124 static int targ_has_sfr(); /* Target chip supports spec-func register? */
125 static int targ_has_iclass();/* Target chip supports instruction set? */
126 /* static void unlink_sym(); */ /* Remove a symbol from the symbol list */
128 /* See md_parse_option() for meanings of these options */
129 static char norelax
= 0; /* True if -norelax switch seen */
130 static char instrument_branches
= 0; /* True if -b switch seen */
132 /* Characters that always start a comment.
133 * If the pre-processor is disabled, these aren't very useful.
135 char comment_chars
[] = "#";
137 /* Characters that only start a comment at the beginning of
138 * a line. If the line seems to have the form '# 123 filename'
139 * .line and .file directives will appear in the pre-processed output.
141 * Note that input_file.c hand checks for '#' at the beginning of the
142 * first line of the input file. This is because the compiler outputs
143 * #NO_APP at the beginning of its output.
146 /* Also note that comments started like this one will always work. */
148 char line_comment_chars
[] = "";
150 /* Chars that can be used to separate mant from exp in floating point nums */
151 char EXP_CHARS
[] = "eE";
153 /* Chars that mean this number is a floating point constant,
154 * as in 0f12.456 or 0d1.2345e12
156 char FLT_CHARS
[] = "fFdDtT";
159 /* Table used by base assembler to relax addresses based on varying length
160 * instructions. The fields are:
161 * 1) most positive reach of this state,
162 * 2) most negative reach of this state,
163 * 3) how many bytes this mode will add to the size of the current frag
164 * 4) which index into the table to try if we can't fit into this one.
166 * For i80960, the only application is the (de-)optimization of cobr
167 * instructions into separate compare and branch instructions when a 13-bit
168 * displacement won't hack it.
172 {0, 0, 0,0}, /* State 0 => no more relaxation possible */
173 {4088, -4096, 0,2}, /* State 1: conditional branch (cobr) */
174 {0x800000-8,-0x800000,4,0}, /* State 2: compare (reg) & branch (ctrl) */
178 /* These are the machine dependent pseudo-ops.
180 * This table describes all the machine specific pseudo-ops the assembler
181 * has to support. The fields are:
182 * pseudo-op name without dot
183 * function to call to execute this pseudo-op
184 * integer arg to pass to the function
190 md_pseudo_table
[] = {
192 { "bss", s_lcomm
, 1 },
193 { "extended", float_cons
, 't' },
194 { "leafproc", parse_po
, S_LEAFPROC
},
195 { "sysproc", parse_po
, S_SYSPROC
},
198 { "quad", big_cons
, 16 },
203 /* Macros to extract info from an 'expressionS' structure 'e' */
204 #define adds(e) e.X_add_symbol
205 #define subs(e) e.X_subtract_symbol
206 #define offs(e) e.X_add_number
207 #define segs(e) e.X_seg
210 /* Branch-prediction bits for CTRL/COBR format opcodes */
211 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
212 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
213 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
216 /* Some instruction opcodes that we need explicitly */
217 #define BE 0x12000000
218 #define BG 0x11000000
219 #define BGE 0x13000000
220 #define BL 0x14000000
221 #define BLE 0x16000000
222 #define BNE 0x15000000
223 #define BNO 0x10000000
224 #define BO 0x17000000
225 #define CHKBIT 0x5a002700
226 #define CMPI 0x5a002080
227 #define CMPO 0x5a002000
230 #define BAL 0x0b000000
231 #define CALL 0x09000000
232 #define CALLS 0x66003800
233 #define RET 0x0a000000
236 /* These masks are used to build up a set of MEMB mode bits. */
239 #define MEMB_BIT 0x1000
243 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */
244 #define MEMA_ABASE 0x2000
246 /* Info from which a MEMA or MEMB format instruction can be generated */
248 long opcode
; /* (First) 32 bits of instruction */
249 int disp
; /* 0-(none), 12- or, 32-bit displacement needed */
250 char *e
; /* The expression in the source instruction from
251 * which the displacement should be determined
256 /* The two pieces of info we need to generate a register operand */
258 int mode
; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
259 int special
; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
260 int n
; /* Register number or literal value */
264 /* Number and assembler mnemonic for all registers that can appear in operands */
269 { "pfp", 0 }, { "sp", 1 }, { "rip", 2 }, { "r3", 3 },
270 { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
271 { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
272 { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
273 { "g0", 16 }, { "g1", 17 }, { "g2", 18 }, { "g3", 19 },
274 { "g4", 20 }, { "g5", 21 }, { "g6", 22 }, { "g7", 23 },
275 { "g8", 24 }, { "g9", 25 }, { "g10", 26 }, { "g11", 27 },
276 { "g12", 28 }, { "g13", 29 }, { "g14", 30 }, { "fp", 31 },
278 /* Numbers for special-function registers are for assembler internal
279 * use only: they are scaled back to range [0-31] for binary output.
283 { "sf0", 32 }, { "sf1", 33 }, { "sf2", 34 }, { "sf3", 35 },
284 { "sf4", 36 }, { "sf5", 37 }, { "sf6", 38 }, { "sf7", 39 },
285 { "sf8", 40 }, { "sf9", 41 }, { "sf10",42 }, { "sf11",43 },
286 { "sf12",44 }, { "sf13",45 }, { "sf14",46 }, { "sf15",47 },
287 { "sf16",48 }, { "sf17",49 }, { "sf18",50 }, { "sf19",51 },
288 { "sf20",52 }, { "sf21",53 }, { "sf22",54 }, { "sf23",55 },
289 { "sf24",56 }, { "sf25",57 }, { "sf26",58 }, { "sf27",59 },
290 { "sf28",60 }, { "sf29",61 }, { "sf30",62 }, { "sf31",63 },
292 /* Numbers for floating point registers are for assembler internal use
293 * only: they are scaled back to [0-3] for binary output.
297 { "fp0", 64 }, { "fp1", 65 }, { "fp2", 66 }, { "fp3", 67 },
299 { NULL
, 0 }, /* END OF LIST */
302 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
303 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
304 #define IS_FP_REG(n) ((n) >= FP0)
306 /* Number and assembler mnemonic for all registers that can appear as 'abase'
307 * (indirect addressing) registers.
313 { "(pfp)", 0 }, { "(sp)", 1 }, { "(rip)", 2 }, { "(r3)", 3 },
314 { "(r4)", 4 }, { "(r5)", 5 }, { "(r6)", 6 }, { "(r7)", 7 },
315 { "(r8)", 8 }, { "(r9)", 9 }, { "(r10)", 10 }, { "(r11)", 11 },
316 { "(r12)", 12 }, { "(r13)", 13 }, { "(r14)", 14 }, { "(r15)", 15 },
317 { "(g0)", 16 }, { "(g1)", 17 }, { "(g2)", 18 }, { "(g3)", 19 },
318 { "(g4)", 20 }, { "(g5)", 21 }, { "(g6)", 22 }, { "(g7)", 23 },
319 { "(g8)", 24 }, { "(g9)", 25 }, { "(g10)", 26 }, { "(g11)", 27 },
320 { "(g12)", 28 }, { "(g13)", 29 }, { "(g14)", 30 }, { "(fp)", 31 },
323 /* for assembler internal use only: this number never appears in binary
328 { NULL
, 0 }, /* END OF LIST */
333 static struct hash_control
*op_hash
= NULL
; /* Opcode mnemonics */
334 static struct hash_control
*reg_hash
= NULL
; /* Register name hash table */
335 static struct hash_control
*areg_hash
= NULL
; /* Abase register hash table */
338 /* Architecture for which we are assembling */
339 #define ARCH_ANY 0 /* Default: no architecture checking done */
344 int architecture
= ARCH_ANY
; /* Architecture requested on invocation line */
345 int iclasses_seen
= 0; /* OR of instruction classes (I_* constants)
346 * for which we've actually assembled
351 /* BRANCH-PREDICTION INSTRUMENTATION
353 * The following supports generation of branch-prediction instrumentation
354 * (turned on by -b switch). The instrumentation collects counts
355 * of branches taken/not-taken for later input to a utility that will
356 * set the branch prediction bits of the instructions in accordance with
357 * the behavior observed. (Note that the KX series does not have
360 * The instrumentation consists of:
362 * (1) before and after each conditional branch, a call to an external
363 * routine that increments and steps over an inline counter. The
364 * counter itself, initialized to 0, immediately follows the call
365 * instruction. For each branch, the counter following the branch
366 * is the number of times the branch was not taken, and the difference
367 * between the counters is the number of times it was taken. An
368 * example of an instrumented conditional branch:
372 * LBRANCH23: be label
376 * (2) a table of pointers to the instrumented branches, so that an
377 * external postprocessing routine can locate all of the counters.
378 * the table begins with a 2-word header: a pointer to the next in
379 * a linked list of such tables (initialized to 0); and a count
380 * of the number of entries in the table (exclusive of the header.
382 * Note that input source code is expected to already contain calls
383 * an external routine that will link the branch local table into a
384 * list of such tables.
387 static int br_cnt
= 0; /* Number of branches instrumented so far.
388 * Also used to generate unique local labels
389 * for each instrumented branch
392 #define BR_LABEL_BASE "LBRANCH"
393 /* Basename of local labels on instrumented
394 * branches, to avoid conflict with compiler-
395 * generated local labels.
398 #define BR_CNT_FUNC "__inc_branch"
399 /* Name of the external routine that will
400 * increment (and step over) an inline counter.
403 #define BR_TAB_NAME "__BRANCH_TABLE__"
404 /* Name of the table of pointers to branches.
405 * A local (i.e., non-external) symbol.
408 /*****************************************************************************
409 * md_begin: One-time initialization.
411 * Set up hash tables.
413 **************************************************************************** */
417 int i
; /* Loop counter */
418 const struct i960_opcode
*oP
; /* Pointer into opcode table */
419 char *retval
; /* Value returned by hash functions */
421 if (((op_hash
= hash_new()) == 0)
422 || ((reg_hash
= hash_new()) == 0)
423 || ((areg_hash
= hash_new()) == 0)) {
424 as_fatal("virtual memory exceeded");
427 retval
= ""; /* For some reason, the base assembler uses an empty
428 * string for "no error message", instead of a NULL
432 for (oP
=i960_opcodes
; oP
->name
&& !*retval
; oP
++) {
433 retval
= hash_insert(op_hash
, oP
->name
, oP
);
436 for (i
=0; regnames
[i
].reg_name
&& !*retval
; i
++) {
437 retval
= hash_insert(reg_hash
, regnames
[i
].reg_name
,
438 ®names
[i
].reg_num
);
441 for (i
=0; aregs
[i
].areg_name
&& !*retval
; i
++){
442 retval
= hash_insert(areg_hash
, aregs
[i
].areg_name
,
447 as_fatal("Hashing returned \"%s\".", retval
);
451 /*****************************************************************************
452 * md_end: One-time final cleanup
456 **************************************************************************** */
462 /*****************************************************************************
463 * md_assemble: Assemble an instruction
465 * Assumptions about the passed-in text:
466 * - all comments, labels removed
467 * - text is an instruction
468 * - all white space compressed to single blanks
469 * - all character constants have been replaced with decimal
471 **************************************************************************** */
474 char *textP
; /* Source text of instruction */
476 char *args
[4]; /* Parsed instruction text, containing NO whitespace:
477 * arg[0]->opcode mnemonic
478 * arg[1-3]->operands, with char constants
479 * replaced by decimal numbers
481 int n_ops
; /* Number of instruction operands */
483 struct i960_opcode
*oP
;
484 /* Pointer to instruction description */
486 /* TRUE iff opcode mnemonic included branch-prediction
487 * suffix (".f" or ".t")
489 long bp_bits
; /* Setting of branch-prediction bit(s) to be OR'd
490 * into instruction opcode of CTRL/COBR format
493 int n
; /* Offset of last character in opcode mnemonic */
495 static const char bp_error_msg
[] = "branch prediction invalid on this opcode";
498 /* Parse instruction into opcode and operands */
499 memset(args
, '\0', sizeof(args
));
500 n_ops
= i_scan(textP
, args
);
502 return; /* Error message already issued */
505 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
506 if (!strcmp(args
[0],"ldconst")){
507 n_ops
= parse_ldconst(args
);
513 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
514 n
= strlen(args
[0]) - 1;
517 if (args
[0][n
-1] == '.' && (args
[0][n
] == 't' || args
[0][n
] == 'f')){
518 /* We could check here to see if the target architecture
519 * supports branch prediction, but why bother? The bit
520 * will just be ignored by processors that don't use it.
523 bp_bits
= (args
[0][n
] == 't') ? BP_TAKEN
: BP_NOT_TAKEN
;
524 args
[0][n
-1] = '\0'; /* Strip suffix from opcode mnemonic */
527 /* Look up opcode mnemonic in table and check number of operands.
528 * Check that opcode is legal for the target architecture.
529 * If all looks good, assemble instruction.
531 oP
= (struct i960_opcode
*) hash_find(op_hash
, args
[0]);
532 if (!oP
|| !targ_has_iclass(oP
->iclass
)) {
533 as_bad("invalid opcode, \"%s\".", args
[0]);
535 } else if (n_ops
!= oP
->num_ops
) {
536 as_bad("improper number of operands. expecting %d, got %d", oP
->num_ops
, n_ops
);
542 ctrl_fmt(args
[1], oP
->opcode
| bp_bits
, oP
->num_ops
);
543 if (oP
->format
== FBRA
){
544 /* Now generate a 'bno' to same arg */
545 ctrl_fmt(args
[1], BNO
| bp_bits
, 1);
550 cobr_fmt(args
, oP
->opcode
| bp_bits
, oP
);
554 as_warn(bp_error_msg
);
565 as_warn(bp_error_msg
);
571 as_warn(bp_error_msg
);
573 /* Output opcode & set up "fixup" (relocation);
574 * flag relocation as 'callj' type.
576 know(oP
->num_ops
== 1);
577 get_cdisp(args
[1], "CTRL", oP
->opcode
, 24, 0, 1);
580 BAD_CASE(oP
->format
);
584 } /* md_assemble() */
586 /*****************************************************************************
587 * md_number_to_chars: convert a number to target byte order
589 **************************************************************************** */
591 md_number_to_chars(buf
, value
, n
)
592 char *buf
; /* Put output here */
593 long value
; /* The integer to be converted */
594 int n
; /* Number of bytes to output (significant bytes
603 /* XXX line number probably botched for this warning message. */
604 if (value
!= 0 && value
!= -1){
605 as_bad("Displacement too long for instruction field length.");
609 } /* md_number_to_chars() */
611 /*****************************************************************************
612 * md_chars_to_number: convert from target byte order to host byte order.
614 **************************************************************************** */
616 md_chars_to_number(val
, n
)
617 unsigned char *val
; /* Value in target byte order */
618 int n
; /* Number of bytes in the input */
622 for (retval
=0; n
--;){
630 #define MAX_LITTLENUMS 6
631 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
633 /*****************************************************************************
634 * md_atof: convert ascii to floating point
636 * Turn a string at input_line_pointer into a floating point constant of type
637 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
638 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
639 * to an empty message if OK.
641 * Note we call the i386 floating point routine, rather than complicating
642 * things with more files or symbolic links.
644 **************************************************************************** */
645 char * md_atof(type
, litP
, sizeP
)
650 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
651 LITTLENUM_TYPE
*wordP
;
670 type
= 'x'; /* That's what atof_ieee() understands */
675 return "Bad call to md_atof()";
678 t
= atof_ieee(input_line_pointer
, type
, words
);
680 input_line_pointer
= t
;
683 *sizeP
= prec
* LNUM_SIZE
;
685 /* Output the LITTLENUMs in REVERSE order in accord with i80960
686 * word-order. (Dunno why atof_ieee doesn't do it in the right
687 * order in the first place -- probably because it's a hack of
691 for(wordP
= words
+ prec
- 1; prec
--;){
692 md_number_to_chars(litP
, (long) (*wordP
--), LNUM_SIZE
);
693 litP
+= sizeof(LITTLENUM_TYPE
);
696 return ""; /* Someone should teach Dean about null pointers */
700 /*****************************************************************************
703 **************************************************************************** */
705 md_number_to_imm(buf
, val
, n
)
710 md_number_to_chars(buf
, val
, n
);
714 /*****************************************************************************
717 **************************************************************************** */
719 md_number_to_disp(buf
, val
, n
)
724 md_number_to_chars(buf
, val
, n
);
727 /*****************************************************************************
728 * md_number_to_field:
730 * Stick a value (an address fixup) into a bit field of
731 * previously-generated instruction.
733 **************************************************************************** */
735 md_number_to_field(instrP
, val
, bfixP
)
736 char *instrP
; /* Pointer to instruction to be fixed */
737 long val
; /* Address fixup value */
738 bit_fixS
*bfixP
; /* Description of bit field to be fixed up */
740 int numbits
; /* Length of bit field to be fixed */
741 long instr
; /* 32-bit instruction to be fixed-up */
742 long sign
; /* 0 or -1, according to sign bit of 'val' */
744 /* Convert instruction back to host byte order
746 instr
= md_chars_to_number(instrP
, 4);
748 /* Surprise! -- we stored the number of bits
749 * to be modified rather than a pointer to a structure.
751 numbits
= (int)bfixP
;
753 /* This is a no-op, stuck here by reloc_callj() */
757 know ((numbits
==13) || (numbits
==24));
759 /* Propagate sign bit of 'val' for the given number of bits.
760 * Result should be all 0 or all 1
762 sign
= val
>> ((int)numbits
- 1);
763 if (((val
< 0) && (sign
!= -1))
764 || ((val
> 0) && (sign
!= 0))){
765 as_bad("Fixup of %d too large for field width of %d",
768 /* Put bit field into instruction and write back in target
771 val
&= ~(-1 << (int)numbits
); /* Clear unused sign bits */
773 md_number_to_chars(instrP
, instr
, 4);
775 } /* md_number_to_field() */
778 /*****************************************************************************
780 * Invocation line includes a switch not recognized by the base assembler.
781 * See if it's a processor-specific option. For the 960, these are:
784 * Conditional branch instructions that require displacements
785 * greater than 13 bits (or that have external targets) should
786 * generate errors. The default is to replace each such
787 * instruction with the corresponding compare (or chkbit) and
788 * branch instructions. Note that the Intel "j" cobr directives
789 * are ALWAYS "de-optimized" in this way when necessary,
790 * regardless of the setting of this option.
793 * Add code to collect information about branches taken, for
794 * later optimization of branch prediction bits by a separate
795 * tool. COBR and CNTL format instructions have branch
796 * prediction bits (in the CX architecture); if "BR" represents
797 * an instruction in one of these classes, the following rep-
798 * resents the code generated by the assembler:
800 * call <increment routine>
801 * .word 0 # pre-counter
803 * call <increment routine>
804 * .word 0 # post-counter
806 * A table of all such "Labels" is also generated.
809 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
810 * Select the 80960 architecture. Instructions or features not
811 * supported by the selected architecture cause fatal errors.
812 * The default is to generate code for any instruction or feature
813 * that is supported by SOME version of the 960 (even if this
814 * means mixing architectures!).
816 **************************************************************************** */
818 md_parse_option(argP
, cntP
, vecP
)
824 struct tabentry
{ char *flag
; int arch
; };
825 static struct tabentry arch_tab
[] = {
828 "SA", ARCH_KA
, /* Synonym for KA */
829 "SB", ARCH_KB
, /* Synonym for KB */
830 "KC", ARCH_MC
, /* Synonym for MC */
837 if (!strcmp(*argP
,"norelax")){
840 } else if (**argP
== 'b'){
841 instrument_branches
= 1;
843 } else if (**argP
== 'A'){
846 for (tp
= arch_tab
; tp
->flag
!= NULL
; tp
++){
847 if (!strcmp(p
,tp
->flag
)){
852 if (tp
->flag
== NULL
){
853 as_bad("unknown architecture: %s", p
);
855 architecture
= tp
->arch
;
862 **argP
= '\0'; /* Done parsing this switch */
866 /*****************************************************************************
868 * Called by base assembler after address relaxation is finished: modify
869 * variable fragments according to how much relaxation was done.
871 * If the fragment substate is still 1, a 13-bit displacement was enough
872 * to reach the symbol in question. Set up an address fixup, but otherwise
873 * leave the cobr instruction alone.
875 * If the fragment substate is 2, a 13-bit displacement was not enough.
876 * Replace the cobr with a two instructions (a compare and a branch).
878 **************************************************************************** */
880 md_convert_frag(headers
, fragP
)
881 object_headers
*headers
;
884 fixS
*fixP
; /* Structure describing needed address fix */
886 switch (fragP
->fr_subtype
){
888 /* LEAVE SINGLE COBR INSTRUCTION */
889 fixP
= fix_new(fragP
,
890 fragP
->fr_opcode
-fragP
->fr_literal
,
898 fixP
->fx_bit_fixP
= (bit_fixS
*) 13; /* size of bit field */
901 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
905 BAD_CASE(fragP
->fr_subtype
);
910 /*****************************************************************************
911 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
913 * Called by base assembler just before address relaxation.
914 * Return the amount by which the fragment will grow.
916 * Any symbol that is now undefined will not become defined; cobr's
917 * based on undefined symbols will have to be replaced with a compare
918 * instruction and a branch instruction, and the code fragment will grow
921 **************************************************************************** */
923 md_estimate_size_before_relax(fragP
, segment_type
)
924 register fragS
*fragP
;
925 register segT segment_type
;
927 /* If symbol is undefined in this segment, go to "relaxed" state
928 * (compare and branch instructions instead of cobr) right now.
930 if (S_GET_SEGMENT(fragP
->fr_symbol
) != segment_type
) {
935 } /* md_estimate_size_before_relax() */
938 /*****************************************************************************
940 * This routine exists in order to overcome machine byte-order problems
941 * when dealing with bit-field entries in the relocation_info struct.
943 * But relocation info will be used on the host machine only (only
944 * executable code is actually downloaded to the i80960). Therefore,
945 * we leave it in host byte order.
947 **************************************************************************** */
948 void md_ri_to_chars(where
, ri
)
950 struct relocation_info
*ri
;
952 *((struct relocation_info
*) where
) = *ri
; /* structure assignment */
953 } /* md_ri_to_chars() */
955 #ifndef WORKING_DOT_WORD
957 int md_short_jump_size
= 0;
958 int md_long_jump_size
= 0;
960 void md_create_short_jump(ptr
, from_addr
, to_addr
, frag
, to_symbol
)
967 as_fatal("failed sanity check.");
971 md_create_long_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
973 long from_addr
, to_addr
;
977 as_fatal("failed sanity check.");
981 /*************************************************************
983 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
985 ************************************************************ */
989 /*****************************************************************************
990 * brcnt_emit: Emit code to increment inline branch counter.
992 * See the comments above the declaration of 'br_cnt' for details on
993 * branch-prediction instrumentation.
994 **************************************************************************** */
998 ctrl_fmt(BR_CNT_FUNC
,CALL
,1);/* Emit call to "increment" routine */
999 emit(0); /* Emit inline counter to be incremented */
1002 /*****************************************************************************
1003 * brlab_next: generate the next branch local label
1005 * See the comments above the declaration of 'br_cnt' for details on
1006 * branch-prediction instrumentation.
1007 **************************************************************************** */
1011 static char buf
[20];
1013 sprintf(buf
, "%s%d", BR_LABEL_BASE
, br_cnt
++);
1017 /*****************************************************************************
1018 * brtab_emit: generate the fetch-prediction branch table.
1020 * See the comments above the declaration of 'br_cnt' for details on
1021 * branch-prediction instrumentation.
1023 * The code emitted here would be functionally equivalent to the following
1024 * example assembler source.
1029 * .word 0 # link to next table
1030 * .word 3 # length of table
1031 * .word LBRANCH0 # 1st entry in table proper
1034 ***************************************************************************** */
1040 char *p
; /* Where the binary was output to */
1041 fixS
*fixP
; /*->description of deferred address fixup */
1043 if (!instrument_branches
){
1047 subseg_new(SEG_DATA
,0); /* .data */
1048 frag_align(2,0); /* .align 2 */
1049 record_alignment(now_seg
,2);
1050 colon(BR_TAB_NAME
); /* BR_TAB_NAME: */
1051 emit(0); /* .word 0 #link to next table */
1052 emit(br_cnt
); /* .word n #length of table */
1054 for (i
=0; i
<br_cnt
; i
++){
1055 sprintf(buf
, "%s%d", BR_LABEL_BASE
, i
);
1057 fixP
= fix_new(frag_now
,
1058 p
- frag_now
->fr_literal
,
1065 fixP
->fx_im_disp
= 2; /* 32-bit displacement fix */
1069 /*****************************************************************************
1070 * cobr_fmt: generate a COBR-format instruction
1072 **************************************************************************** */
1075 cobr_fmt(arg
, opcode
, oP
)
1076 char *arg
[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1077 long opcode
; /* Opcode, with branch-prediction bits already set
1080 struct i960_opcode
*oP
;
1081 /*->description of instruction */
1083 long instr
; /* 32-bit instruction */
1084 struct regop regop
; /* Description of register operand */
1085 int n
; /* Number of operands */
1086 int var_frag
; /* 1 if varying length code fragment should
1087 * be emitted; 0 if an address fix
1088 * should be emitted.
1095 /* First operand (if any) of a COBR is always a register
1096 * operand. Parse it.
1098 parse_regop(®op
, arg
[1], oP
->operand
[0]);
1099 instr
|= (regop
.n
<< 19) | (regop
.mode
<< 13);
1102 /* Second operand (if any) of a COBR is always a register
1103 * operand. Parse it.
1105 parse_regop(®op
, arg
[2], oP
->operand
[1]);
1106 instr
|= (regop
.n
<< 14) | regop
.special
;
1114 if (instrument_branches
){
1116 colon(brlab_next());
1119 /* A third operand to a COBR is always a displacement.
1120 * Parse it; if it's relaxable (a cobr "j" directive, or any
1121 * cobr other than bbs/bbc when the "-norelax" option is not in
1122 * use) set up a variable code fragment; otherwise set up an
1125 var_frag
= !norelax
|| (oP
->format
== COJ
); /* TRUE or FALSE */
1126 get_cdisp(arg
[3], "COBR", instr
, 13, var_frag
, 0);
1128 if (instrument_branches
){
1135 /*****************************************************************************
1136 * ctrl_fmt: generate a CTRL-format instruction
1138 **************************************************************************** */
1141 ctrl_fmt(targP
, opcode
, num_ops
)
1142 char *targP
; /* Pointer to text of lone operand (if any) */
1143 long opcode
; /* Template of instruction */
1144 int num_ops
; /* Number of operands */
1146 int instrument
; /* TRUE iff we should add instrumentation to track
1147 * how often the branch is taken
1152 emit(opcode
); /* Output opcode */
1155 instrument
= instrument_branches
&& (opcode
!=CALL
)
1156 && (opcode
!=B
) && (opcode
!=RET
) && (opcode
!=BAL
);
1160 colon(brlab_next());
1163 /* The operand MUST be an ip-relative displacment. Parse it
1164 * and set up address fix for the instruction we just output.
1166 get_cdisp(targP
, "CTRL", opcode
, 24, 0, 0);
1176 /*****************************************************************************
1177 * emit: output instruction binary
1179 * Output instruction binary, in target byte order, 4 bytes at a time.
1180 * Return pointer to where it was placed.
1182 **************************************************************************** */
1186 long instr
; /* Word to be output, host byte order */
1188 char *toP
; /* Where to output it */
1190 toP
= frag_more(4); /* Allocate storage */
1191 md_number_to_chars(toP
, instr
, 4); /* Convert to target byte order */
1196 /*****************************************************************************
1197 * get_args: break individual arguments out of comma-separated list
1199 * Input assumptions:
1200 * - all comments and labels have been removed
1201 * - all strings of whitespace have been collapsed to a single blank.
1202 * - all character constants ('x') have been replaced with decimal
1205 * args[0] is untouched. args[1] points to first operand, etc. All args:
1206 * - are NULL-terminated
1207 * - contain no whitespace
1210 * Number of operands (0,1,2, or 3) or -1 on error.
1212 **************************************************************************** */
1213 static int get_args(p
, args
)
1214 register char *p
; /* Pointer to comma-separated operands; MUCKED BY US */
1215 char *args
[]; /* Output arg: pointers to operands placed in args[1-3].
1216 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1219 register int n
; /* Number of operands */
1225 /* Skip lead white space */
1237 /* Squeze blanks out by moving non-blanks toward start of string.
1238 * Isolate operands, whenever comma is found.
1246 } else if (*p
== ','){
1248 /* Start of operand */
1250 as_bad("too many operands");
1253 *to
++ = '\0'; /* Terminate argument */
1254 args
[++n
] = to
; /* Start next argument */
1266 /*****************************************************************************
1267 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1269 * Parse displacement for a COBR or CTRL instruction.
1271 * If successful, output the instruction opcode and set up for it,
1272 * depending on the arg 'var_frag', either:
1273 * o an address fixup to be done when all symbol values are known, or
1274 * o a varying length code fragment, with address fixup info. This
1275 * will be done for cobr instructions that may have to be relaxed
1276 * in to compare/branch instructions (8 bytes) if the final address
1277 * displacement is greater than 13 bits.
1279 **************************************************************************** */
1282 get_cdisp(dispP
, ifmtP
, instr
, numbits
, var_frag
, callj
)
1283 char *dispP
; /*->displacement as specified in source instruction */
1284 char *ifmtP
; /*->"COBR" or "CTRL" (for use in error message) */
1285 long instr
; /* Instruction needing the displacement */
1286 int numbits
; /* # bits of displacement (13 for COBR, 24 for CTRL) */
1287 int var_frag
; /* 1 if varying length code fragment should be emitted;
1288 * 0 if an address fix should be emitted.
1290 int callj
; /* 1 if callj relocation should be done; else 0 */
1292 expressionS e
; /* Parsed expression */
1293 fixS
*fixP
; /* Structure describing needed address fix */
1294 char *outP
; /* Where instruction binary is output to */
1298 switch (parse_expr(dispP
,&e
)) {
1301 as_bad("expression syntax error");
1307 outP
= frag_more(8); /* Allocate worst-case storage */
1308 md_number_to_chars(outP
, instr
, 4);
1309 frag_variant(rs_machine_dependent
, 4, 4, 1,
1310 adds(e
), offs(e
), outP
, 0, 0);
1312 /* Set up a new fix structure, so address can be updated
1313 * when all symbol values are known.
1316 fixP
= fix_new(frag_now
,
1317 outP
- frag_now
->fr_literal
,
1325 fixP
->fx_callj
= callj
;
1327 /* We want to modify a bit field when the address is
1328 * known. But we don't need all the garbage in the
1329 * bit_fix structure. So we're going to lie and store
1330 * the number of bits affected instead of a pointer.
1332 fixP
->fx_bit_fixP
= (bit_fixS
*) numbits
;
1338 as_bad("attempt to branch into different segment");
1342 as_bad("target of %s instruction must be a label", ifmtP
);
1348 /*****************************************************************************
1349 * get_ispec: parse a memory operand for an index specification
1351 * Here, an "index specification" is taken to be anything surrounded
1352 * by square brackets and NOT followed by anything else.
1354 * If it's found, detach it from the input string, remove the surrounding
1355 * square brackets, and return a pointer to it. Otherwise, return NULL.
1357 **************************************************************************** */
1361 char *textP
; /*->memory operand from source instruction, no white space */
1363 char *start
; /*->start of index specification */
1364 char *end
; /*->end of index specification */
1366 /* Find opening square bracket, if any
1368 start
= strchr(textP
, '[');
1372 /* Eliminate '[', detach from rest of operand */
1375 end
= strchr(start
, ']');
1378 as_bad("unmatched '['");
1381 /* Eliminate ']' and make sure it was the last thing
1385 if (*(end
+1) != '\0'){
1386 as_bad("garbage after index spec ignored");
1393 /*****************************************************************************
1396 * Look up a (suspected) register name in the register table and return the
1397 * associated register number (or -1 if not found).
1399 **************************************************************************** */
1403 char *regname
; /* Suspected register name */
1407 rP
= (int *) hash_find(reg_hash
, regname
);
1408 return (rP
== NULL
) ? -1 : *rP
;
1412 /*****************************************************************************
1413 * i_scan: perform lexical scan of ascii assembler instruction.
1415 * Input assumptions:
1416 * - input string is an i80960 instruction (not a pseudo-op)
1417 * - all comments and labels have been removed
1418 * - all strings of whitespace have been collapsed to a single blank.
1421 * args[0] points to opcode, other entries point to operands. All strings:
1422 * - are NULL-terminated
1423 * - contain no whitespace
1424 * - have character constants ('x') replaced with a decimal number
1427 * Number of operands (0,1,2, or 3) or -1 on error.
1429 **************************************************************************** */
1430 static int i_scan(iP
, args
)
1431 register char *iP
; /* Pointer to ascii instruction; MUCKED BY US. */
1432 char *args
[]; /* Output arg: pointers to opcode and operands placed
1433 * here. MUST ACCOMMODATE 4 ENTRIES.
1437 /* Isolate opcode */
1440 } /* Skip lead space, if any */
1442 for (; *iP
!= ' '; iP
++) {
1444 /* There are no operands */
1445 if (args
[0] == iP
) {
1446 /* We never moved: there was no opcode either! */
1447 as_bad("missing opcode");
1453 *iP
++ = '\0'; /* Terminate opcode */
1454 return(get_args(iP
, args
));
1458 /*****************************************************************************
1459 * mem_fmt: generate a MEMA- or MEMB-format instruction
1461 **************************************************************************** */
1462 static void mem_fmt(args
, oP
)
1463 char *args
[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1464 struct i960_opcode
*oP
; /* Pointer to description of instruction */
1466 int i
; /* Loop counter */
1467 struct regop regop
; /* Description of register operand */
1468 char opdesc
; /* Operand descriptor byte */
1469 memS instr
; /* Description of binary to be output */
1470 char *outP
; /* Where the binary was output to */
1471 expressionS expr
; /* Parsed expression */
1472 fixS
*fixP
; /*->description of deferred address fixup */
1474 memset(&instr
, '\0', sizeof(memS
));
1475 instr
.opcode
= oP
->opcode
;
1477 /* Process operands. */
1478 for (i
= 1; i
<= oP
->num_ops
; i
++){
1479 opdesc
= oP
->operand
[i
-1];
1482 parse_memop(&instr
, args
[i
], oP
->format
);
1484 parse_regop(®op
, args
[i
], opdesc
);
1485 instr
.opcode
|= regop
.n
<< 19;
1490 outP
= emit(instr
.opcode
);
1492 if (instr
.disp
== 0){
1496 /* Parse and process the displacement */
1497 switch (parse_expr(instr
.e
,&expr
)){
1500 as_bad("expression syntax error");
1504 if (instr
.disp
== 32){
1505 (void) emit(offs(expr
)); /* Output displacement */
1507 /* 12-bit displacement */
1508 if (offs(expr
) & ~0xfff){
1509 /* Won't fit in 12 bits: convert already-output
1510 * instruction to MEMB format, output
1514 (void) emit(offs(expr
));
1516 /* WILL fit in 12 bits: OR into opcode and
1517 * overwrite the binary we already put out
1519 instr
.opcode
|= offs(expr
);
1520 md_number_to_chars(outP
, instr
.opcode
, 4);
1525 case SEG_DIFFERENCE
:
1530 if (instr
.disp
== 12){
1531 /* Displacement is dependent on a symbol, whose value
1532 * may change at link time. We HAVE to reserve 32 bits.
1533 * Convert already-output opcode to MEMB format.
1538 /* Output 0 displacement and set up address fixup for when
1539 * this symbol's value becomes known.
1541 outP
= emit((long) 0);
1542 fixP
= fix_new(frag_now
,
1543 outP
- frag_now
->fr_literal
,
1550 fixP
->fx_im_disp
= 2; /* 32-bit displacement fix */
1554 BAD_CASE(segs(expr
));
1560 /*****************************************************************************
1561 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1563 * There are 2 possible MEMA formats:
1564 * - displacement only
1565 * - displacement + abase
1567 * They are distinguished by the setting of the MEMA_ABASE bit.
1569 **************************************************************************** */
1570 static void mema_to_memb(opcodeP
)
1571 char *opcodeP
; /* Where to find the opcode, in target byte order */
1573 long opcode
; /* Opcode in host byte order */
1574 long mode
; /* Mode bits for MEMB instruction */
1576 opcode
= md_chars_to_number(opcodeP
, 4);
1577 know(!(opcode
& MEMB_BIT
));
1579 mode
= MEMB_BIT
| D_BIT
;
1580 if (opcode
& MEMA_ABASE
){
1584 opcode
&= 0xffffc000; /* Clear MEMA offset and mode bits */
1585 opcode
|= mode
; /* Set MEMB mode bits */
1587 md_number_to_chars(opcodeP
, opcode
, 4);
1588 } /* mema_to_memb() */
1591 /*****************************************************************************
1592 * parse_expr: parse an expression
1594 * Use base assembler's expression parser to parse an expression.
1595 * It, unfortunately, runs off a global which we have to save/restore
1596 * in order to make it work for us.
1598 * An empty expression string is treated as an absolute 0.
1600 * Return "segment" to which the expression evaluates.
1601 * Return SEG_GOOF regardless of expression evaluation if entire input
1602 * string is not consumed in the evaluation -- tolerate no dangling junk!
1604 **************************************************************************** */
1607 parse_expr(textP
, expP
)
1608 char *textP
; /* Text of expression to be parsed */
1609 expressionS
*expP
; /* Where to put the results of parsing */
1611 char *save_in
; /* Save global here */
1612 segT seg
; /* Segment to which expression evaluates */
1617 if (*textP
== '\0') {
1618 /* Treat empty string as absolute 0 */
1619 expP
->X_add_symbol
= expP
->X_subtract_symbol
= NULL
;
1620 expP
->X_add_number
= 0;
1621 seg
= expP
->X_seg
= SEG_ABSOLUTE
;
1624 save_in
= input_line_pointer
; /* Save global */
1625 input_line_pointer
= textP
; /* Make parser work for us */
1627 seg
= expression(expP
);
1628 if (input_line_pointer
- textP
!= strlen(textP
)) {
1629 /* Did not consume all of the input */
1632 symP
= expP
->X_add_symbol
;
1633 if (symP
&& (hash_find(reg_hash
, S_GET_NAME(symP
)))) {
1634 /* Register name in an expression */
1638 input_line_pointer
= save_in
; /* Restore global */
1644 /*****************************************************************************
1646 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1647 * i80960 instruction.
1649 * Assumes the input consists of:
1650 * arg[0] opcode mnemonic ('ldconst')
1651 * arg[1] first operand (constant)
1652 * arg[2] name of register to be loaded
1654 * Replaces opcode and/or operands as appropriate.
1656 * Returns the new number of arguments, or -1 on failure.
1658 **************************************************************************** */
1662 char *arg
[]; /* See above */
1664 int n
; /* Constant to be loaded */
1665 int shift
; /* Shift count for "shlo" instruction */
1666 static char buf
[5]; /* Literal for first operand */
1667 static char buf2
[5]; /* Literal for second operand */
1668 expressionS e
; /* Parsed expression */
1671 arg
[3] = NULL
; /* So we can tell at the end if it got used or not */
1673 switch(parse_expr(arg
[1],&e
)){
1679 case SEG_DIFFERENCE
:
1680 /* We're dependent on one or more symbols -- use "lda" */
1685 /* Try the following mappings:
1686 * ldconst 0,<reg> ->mov 0,<reg>
1687 * ldconst 31,<reg> ->mov 31,<reg>
1688 * ldconst 32,<reg> ->addo 1,31,<reg>
1689 * ldconst 62,<reg> ->addo 31,31,<reg>
1690 * ldconst 64,<reg> ->shlo 8,3,<reg>
1691 * ldconst -1,<reg> ->subo 1,0,<reg>
1692 * ldconst -31,<reg>->subo 31,0,<reg>
1694 * anthing else becomes:
1698 if ((0 <= n
) && (n
<= 31)){
1701 } else if ((-31 <= n
) && (n
<= -1)){
1704 sprintf(buf
, "%d", -n
);
1708 } else if ((32 <= n
) && (n
<= 62)){
1712 sprintf(buf
, "%d", n
-31);
1715 } else if ((shift
= shift_ok(n
)) != 0){
1718 sprintf(buf
, "%d", shift
);
1720 sprintf(buf2
, "%d", n
>> shift
);
1729 as_bad("invalid constant");
1733 return (arg
[3] == 0) ? 2: 3;
1736 /*****************************************************************************
1737 * parse_memop: parse a memory operand
1739 * This routine is based on the observation that the 4 mode bits of the
1740 * MEMB format, taken individually, have fairly consistent meaning:
1742 * M3 (bit 13): 1 if displacement is present (D_BIT)
1743 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1744 * M1 (bit 11): 1 if index is present (I_BIT)
1745 * M0 (bit 10): 1 if abase is present (A_BIT)
1747 * So we parse the memory operand and set bits in the mode as we find
1748 * things. Then at the end, if we go to MEMB format, we need only set
1749 * the MEMB bit (M2) and our mode is built for us.
1751 * Unfortunately, I said "fairly consistent". The exceptions:
1754 * 0100 Would seem illegal, but means "abase-only".
1756 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
1757 * Must be converted to 0100.
1759 * 0110 Would seem to mean "index-only", but is reserved.
1760 * We turn on the D bit and provide a 0 displacement.
1762 * The other thing to observe is that we parse from the right, peeling
1763 * things * off as we go: first any index spec, then any abase, then
1766 **************************************************************************** */
1769 parse_memop(memP
, argP
, optype
)
1770 memS
*memP
; /* Where to put the results */
1771 char *argP
; /* Text of the operand to be parsed */
1772 int optype
; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1774 char *indexP
; /* Pointer to index specification with "[]" removed */
1775 char *p
; /* Temp char pointer */
1776 char iprel_flag
;/* True if this is an IP-relative operand */
1777 int regnum
; /* Register number */
1778 int scale
; /* Scale factor: 1,2,4,8, or 16. Later converted
1779 * to internal format (0,1,2,3,4 respectively).
1781 int mode
; /* MEMB mode bits */
1782 int *intP
; /* Pointer to register number */
1784 /* The following table contains the default scale factors for each
1785 * type of memory instruction. It is accessed using (optype-MEM1)
1786 * as an index -- thus it assumes the 'optype' constants are assigned
1787 * consecutive values, in the order they appear in this table
1789 static int def_scale
[] = {
1794 -1, /* MEM12 -- no valid default */
1799 iprel_flag
= mode
= 0;
1801 /* Any index present? */
1802 indexP
= get_ispec(argP
);
1804 p
= strchr(indexP
, '*');
1806 /* No explicit scale -- use default for this
1809 scale
= def_scale
[ optype
- MEM1
];
1811 *p
++ = '\0'; /* Eliminate '*' */
1813 /* Now indexP->a '\0'-terminated register name,
1814 * and p->a scale factor.
1817 if (!strcmp(p
,"16")){
1819 } else if (strchr("1248",*p
) && (p
[1] == '\0')){
1826 regnum
= get_regnum(indexP
); /* Get index reg. # */
1827 if (!IS_RG_REG(regnum
)){
1828 as_bad("invalid index register");
1832 /* Convert scale to its binary encoding */
1834 case 1: scale
= 0 << 7; break;
1835 case 2: scale
= 1 << 7; break;
1836 case 4: scale
= 2 << 7; break;
1837 case 8: scale
= 3 << 7; break;
1838 case 16: scale
= 4 << 7; break;
1839 default: as_bad("invalid scale factor"); return;
1842 memP
->opcode
|= scale
| regnum
; /* Set index bits in opcode */
1843 mode
|= I_BIT
; /* Found a valid index spec */
1846 /* Any abase (Register Indirect) specification present? */
1847 if ((p
= strrchr(argP
,'(')) != NULL
) {
1848 /* "(" is there -- does it start a legal abase spec?
1849 * (If not it could be part of a displacement expression.)
1851 intP
= (int *) hash_find(areg_hash
, p
);
1853 /* Got an abase here */
1855 *p
= '\0'; /* discard register spec */
1856 if (regnum
== IPREL
){
1857 /* We have to specialcase ip-rel mode */
1860 memP
->opcode
|= regnum
<< 14;
1866 /* Any expression present? */
1872 /* Special-case ip-relative addressing */
1877 memP
->opcode
|= 5 << 10; /* IP-relative mode */
1883 /* Handle all other modes */
1886 /* Go with MEMA instruction format for now (grow to MEMB later
1887 * if 12 bits is not enough for the displacement).
1888 * MEMA format has a single mode bit: set it to indicate
1889 * that abase is present.
1891 memP
->opcode
|= MEMA_ABASE
;
1896 /* Go with MEMA instruction format for now (grow to MEMB later
1897 * if 12 bits is not enough for the displacement).
1903 /* For some reason, the bit string for this mode is not
1904 * consistent: it should be 0 (exclusive of the MEMB bit),
1905 * so we set it "by hand" here.
1907 memP
->opcode
|= MEMB_BIT
;
1911 /* set MEMB bit in mode, and OR in mode bits */
1912 memP
->opcode
|= mode
| MEMB_BIT
;
1916 /* Treat missing displacement as displacement of 0 */
1918 /***********************
1919 * Fall into next case *
1920 ********************** */
1921 case D_BIT
| A_BIT
| I_BIT
:
1923 /* set MEMB bit in mode, and OR in mode bits */
1924 memP
->opcode
|= mode
| MEMB_BIT
;
1934 /*****************************************************************************
1935 * parse_po: parse machine-dependent pseudo-op
1937 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
1938 * up the rest of the input line, breaks out the individual arguments,
1939 * and dispatches them to the correct handler.
1940 **************************************************************************** */
1944 int po_num
; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
1946 char *args
[4]; /* Pointers operands, with no embedded whitespace.
1948 * arg[1-3]->operands
1950 int n_ops
; /* Number of operands */
1951 char *p
; /* Pointer to beginning of unparsed argument string */
1952 char eol
; /* Character that indicated end of line */
1954 extern char is_end_of_line
[];
1956 /* Advance input pointer to end of line. */
1957 p
= input_line_pointer
;
1958 while (!is_end_of_line
[ *input_line_pointer
]){
1959 input_line_pointer
++;
1961 eol
= *input_line_pointer
; /* Save end-of-line char */
1962 *input_line_pointer
= '\0'; /* Terminate argument list */
1964 /* Parse out operands */
1965 n_ops
= get_args(p
, args
);
1970 /* Dispatch to correct handler */
1972 case S_SYSPROC
: s_sysproc(n_ops
, args
); break;
1973 case S_LEAFPROC
: s_leafproc(n_ops
, args
); break;
1974 default: BAD_CASE(po_num
); break;
1977 /* Restore eol, so line numbers get updated correctly. Base assembler
1978 * assumes we leave input pointer pointing at char following the eol.
1980 *input_line_pointer
++ = eol
;
1983 /*****************************************************************************
1984 * parse_regop: parse a register operand.
1986 * In case of illegal operand, issue a message and return some valid
1987 * information so instruction processing can continue.
1988 **************************************************************************** */
1991 parse_regop(regopP
, optext
, opdesc
)
1992 struct regop
*regopP
; /* Where to put description of register operand */
1993 char *optext
; /* Text of operand */
1994 char opdesc
; /* Descriptor byte: what's legal for this operand */
1996 int n
; /* Register number */
1997 expressionS e
; /* Parsed expression */
1999 /* See if operand is a register */
2000 n
= get_regnum(optext
);
2003 /* global or local register */
2004 if (!REG_ALIGN(opdesc
,n
)){
2005 as_bad("unaligned register");
2009 regopP
->special
= 0;
2011 } else if (IS_FP_REG(n
) && FP_OK(opdesc
)){
2012 /* Floating point register, and it's allowed */
2013 regopP
->n
= n
- FP0
;
2015 regopP
->special
= 0;
2017 } else if (IS_SF_REG(n
) && SFR_OK(opdesc
)){
2018 /* Special-function register, and it's allowed */
2019 regopP
->n
= n
- SF0
;
2021 regopP
->special
= 1;
2022 if (!targ_has_sfr(regopP
->n
)){
2023 as_bad("no such sfr in this architecture");
2027 } else if (LIT_OK(opdesc
)){
2029 * How about a literal?
2032 regopP
->special
= 0;
2033 if (FP_OK(opdesc
)){ /* floating point literal acceptable */
2034 /* Skip over 0f, 0d, or 0e prefix */
2035 if ( (optext
[0] == '0')
2036 && (optext
[1] >= 'd')
2037 && (optext
[1] <= 'f') ){
2041 if (!strcmp(optext
,"0.0") || !strcmp(optext
,"0") ){
2045 if (!strcmp(optext
,"1.0") || !strcmp(optext
,"1") ){
2050 } else { /* fixed point literal acceptable */
2051 if ((parse_expr(optext
,&e
) != SEG_ABSOLUTE
)
2052 || (offs(e
) < 0) || (offs(e
) > 31)){
2053 as_bad("illegal literal");
2056 regopP
->n
= offs(e
);
2061 /* Nothing worked */
2063 regopP
->mode
= 0; /* Register r0 is always a good one */
2065 regopP
->special
= 0;
2066 } /* parse_regop() */
2068 /*****************************************************************************
2069 * reg_fmt: generate a REG-format instruction
2071 **************************************************************************** */
2072 static void reg_fmt(args
, oP
)
2073 char *args
[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2074 struct i960_opcode
*oP
; /* Pointer to description of instruction */
2076 long instr
; /* Binary to be output */
2077 struct regop regop
; /* Description of register operand */
2078 int n_ops
; /* Number of operands */
2082 n_ops
= oP
->num_ops
;
2085 parse_regop(®op
, args
[1], oP
->operand
[0]);
2087 if ((n_ops
== 1) && !(instr
& M3
)){
2088 /* 1-operand instruction in which the dst field should
2089 * be used (instead of src1).
2093 regop
.mode
= regop
.special
;
2098 /* regop.n goes in bit 0, needs no shifting */
2100 regop
.special
<<= 5;
2102 instr
|= regop
.n
| regop
.mode
| regop
.special
;
2106 parse_regop(®op
, args
[2], oP
->operand
[1]);
2108 if ((n_ops
== 2) && !(instr
& M3
)){
2109 /* 2-operand instruction in which the dst field should
2110 * be used instead of src2).
2114 regop
.mode
= regop
.special
;
2121 regop
.special
<<= 6;
2123 instr
|= regop
.n
| regop
.mode
| regop
.special
;
2126 parse_regop(®op
, args
[3], oP
->operand
[2]);
2128 regop
.mode
= regop
.special
;
2130 instr
|= (regop
.n
<<= 19) | (regop
.mode
<<= 13);
2136 /*****************************************************************************
2138 * Replace cobr instruction in a code fragment with equivalent branch and
2139 * compare instructions, so it can reach beyond a 13-bit displacement.
2140 * Set up an address fix/relocation for the new branch instruction.
2142 **************************************************************************** */
2144 /* This "conditional jump" table maps cobr instructions into equivalent
2145 * compare and branch opcodes.
2151 } coj
[] = { /* COBR OPCODE: */
2152 CHKBIT
, BNO
, /* 0x30 - bbc */
2153 CMPO
, BG
, /* 0x31 - cmpobg */
2154 CMPO
, BE
, /* 0x32 - cmpobe */
2155 CMPO
, BGE
, /* 0x33 - cmpobge */
2156 CMPO
, BL
, /* 0x34 - cmpobl */
2157 CMPO
, BNE
, /* 0x35 - cmpobne */
2158 CMPO
, BLE
, /* 0x36 - cmpoble */
2159 CHKBIT
, BO
, /* 0x37 - bbs */
2160 CMPI
, BNO
, /* 0x38 - cmpibno */
2161 CMPI
, BG
, /* 0x39 - cmpibg */
2162 CMPI
, BE
, /* 0x3a - cmpibe */
2163 CMPI
, BGE
, /* 0x3b - cmpibge */
2164 CMPI
, BL
, /* 0x3c - cmpibl */
2165 CMPI
, BNE
, /* 0x3d - cmpibne */
2166 CMPI
, BLE
, /* 0x3e - cmpible */
2167 CMPI
, BO
, /* 0x3f - cmpibo */
2173 register fragS
*fragP
; /* fragP->fr_opcode is assumed to point to
2174 * the cobr instruction, which comes at the
2175 * end of the code fragment.
2178 int opcode
, src1
, src2
, m1
, s2
;
2179 /* Bit fields from cobr instruction */
2180 long bp_bits
; /* Branch prediction bits from cobr instruction */
2181 long instr
; /* A single i960 instruction */
2182 char *iP
; /*->instruction to be replaced */
2183 fixS
*fixP
; /* Relocation that can be done at assembly time */
2185 /* PICK UP & PARSE COBR INSTRUCTION */
2186 iP
= fragP
->fr_opcode
;
2187 instr
= md_chars_to_number(iP
, 4);
2188 opcode
= ((instr
>> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2189 src1
= (instr
>> 19) & 0x1f;
2190 m1
= (instr
>> 13) & 1;
2192 src2
= (instr
>> 14) & 0x1f;
2193 bp_bits
= instr
& BP_MASK
;
2195 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2196 instr
= coj
[opcode
].compare
2197 | src1
| (m1
<< 11) | (s2
<< 6) | (src2
<< 14);
2198 md_number_to_chars(iP
, instr
, 4);
2200 /* OUTPUT BRANCH INSTRUCTION */
2201 md_number_to_chars(iP
+4, coj
[opcode
].branch
| bp_bits
, 4);
2203 /* SET UP ADDRESS FIXUP/RELOCATION */
2204 fixP
= fix_new(fragP
,
2205 iP
+4 - fragP
->fr_literal
,
2213 fixP
->fx_bit_fixP
= (bit_fixS
*) 24; /* Store size of bit field */
2220 /*****************************************************************************
2221 * reloc_callj: Relocate a 'callj' instruction
2223 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2224 * assembler calls it when it decides it can relocate an address at
2225 * assembly time instead of emitting a relocation directive.
2227 * Check to see if the relocation involves a 'callj' instruction to a:
2228 * sysproc: Replace the default 'call' instruction with a 'calls'
2229 * leafproc: Replace the default 'call' instruction with a 'bal'.
2230 * other proc: Do nothing.
2232 * See b.out.h for details on the 'n_other' field in a symbol structure.
2235 * Assumes the caller has already figured out, in the case of a leafproc,
2236 * to use the 'bal' entry point, and has substituted that symbol into the
2237 * passed fixup structure.
2239 **************************************************************************** */
2240 void reloc_callj(fixP
)
2241 fixS
*fixP
; /* Relocation that can be done at assembly time */
2243 char *where
; /*->the binary for the instruction being relocated */
2245 if (!fixP
->fx_callj
) {
2247 } /* This wasn't a callj instruction in the first place */
2249 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2251 if (TC_S_IS_SYSPROC(fixP
->fx_addsy
)) {
2252 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2253 * System procedure number is (other-1).
2255 md_number_to_chars(where
, CALLS
|TC_S_GET_SYSPROC(fixP
->fx_addsy
), 4);
2257 /* Nothing else needs to be done for this instruction.
2258 * Make sure 'md_number_to_field()' will perform a no-op.
2260 fixP
->fx_bit_fixP
= (bit_fixS
*) 1;
2262 } else if (TC_S_IS_CALLNAME(fixP
->fx_addsy
)) {
2263 /* Should not happen: see block comment above */
2264 as_fatal("Trying to 'bal' to %s", S_GET_NAME(fixP
->fx_addsy
));
2266 } else if (TC_S_IS_BALNAME(fixP
->fx_addsy
)) {
2267 /* Replace 'call' with 'bal'; both instructions have
2268 * the same format, so calling code should complete
2269 * relocation as if nothing happened here.
2271 md_number_to_chars(where
, BAL
, 4);
2272 } else if (TC_S_IS_BADPROC(fixP
->fx_addsy
)) {
2273 as_bad("Looks like a proc, but can't tell what kind.\n");
2274 } /* switch on proc type */
2276 /* else Symbol is neither a sysproc nor a leafproc */
2279 } /* reloc_callj() */
2282 /*****************************************************************************
2283 * s_leafproc: process .leafproc pseudo-op
2285 * .leafproc takes two arguments, the second one is optional:
2286 * arg[1]: name of 'call' entry point to leaf procedure
2287 * arg[2]: name of 'bal' entry point to leaf procedure
2289 * If the two arguments are identical, or if the second one is missing,
2290 * the first argument is taken to be the 'bal' entry point.
2292 * If there are 2 distinct arguments, we must make sure that the 'bal'
2293 * entry point immediately follows the 'call' entry point in the linked
2296 **************************************************************************** */
2297 static void s_leafproc(n_ops
, args
)
2298 int n_ops
; /* Number of operands */
2299 char *args
[]; /* args[1]->1st operand, args[2]->2nd operand */
2301 symbolS
*callP
; /* Pointer to leafproc 'call' entry point symbol */
2302 symbolS
*balP
; /* Pointer to leafproc 'bal' entry point symbol */
2304 if ((n_ops
!= 1) && (n_ops
!= 2)) {
2305 as_bad("should have 1 or 2 operands");
2307 } /* Check number of arguments */
2309 /* Find or create symbol for 'call' entry point. */
2310 callP
= symbol_find_or_make(args
[1]);
2312 if (TC_S_IS_CALLNAME(callP
)) {
2313 as_warn("Redefining leafproc %s", S_GET_NAME(callP
));
2316 /* If that was the only argument, use it as the 'bal' entry point.
2317 * Otherwise, mark it as the 'call' entry point and find or create
2318 * another symbol for the 'bal' entry point.
2320 if ((n_ops
== 1) || !strcmp(args
[1],args
[2])) {
2321 TC_S_FORCE_TO_BALNAME(callP
);
2324 TC_S_FORCE_TO_CALLNAME(callP
);
2326 balP
= symbol_find_or_make(args
[2]);
2327 if (TC_S_IS_CALLNAME(balP
)) {
2328 as_warn("Redefining leafproc %s", S_GET_NAME(balP
));
2330 TC_S_FORCE_TO_BALNAME(balP
);
2332 tc_set_bal_of_call(callP
, balP
);
2333 } /* if only one arg, or the args are the same */
2336 } /* s_leafproc() */
2340 * s_sysproc: process .sysproc pseudo-op
2342 * .sysproc takes two arguments:
2343 * arg[1]: name of entry point to system procedure
2344 * arg[2]: 'entry_num' (index) of system procedure in the range
2347 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2348 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2349 * by adding 1 to it. It must be unbiased before it is used.
2351 static void s_sysproc(n_ops
, args
)
2352 int n_ops
; /* Number of operands */
2353 char *args
[]; /* args[1]->1st operand, args[2]->2nd operand */
2359 as_bad("should have two operands");
2361 } /* bad arg count */
2363 /* Parse "entry_num" argument and check it for validity. */
2364 if ((parse_expr(args
[2],&exp
) != SEG_ABSOLUTE
)
2366 || (offs(exp
) > 31)) {
2367 as_bad("'entry_num' must be absolute number in [0,31]");
2371 /* Find/make symbol and stick entry number (biased by +1) into it */
2372 symP
= symbol_find_or_make(args
[1]);
2374 if (TC_S_IS_SYSPROC(symP
)) {
2375 as_warn("Redefining entrynum for sysproc %s", S_GET_NAME(symP
));
2378 TC_S_SET_SYSPROC(symP
, offs(exp
)); /* encode entry number */
2379 TC_S_FORCE_TO_SYSPROC(symP
);
2385 /*****************************************************************************
2387 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2388 * This means that some number X < 32 can be shifted left to produce the
2389 * constant of interest.
2391 * Return the shift count, or 0 if we can't do it.
2392 * Caller calculates X by shifting original constant right 'shift' places.
2394 **************************************************************************** */
2398 int n
; /* The constant of interest */
2400 int shift
; /* The shift count */
2403 /* Can't do it for negative numbers */
2407 /* Shift 'n' right until a 1 is about to be lost */
2408 for (shift
= 0; (n
& 1) == 0; shift
++){
2419 /*****************************************************************************
2420 * syntax: issue syntax error
2422 **************************************************************************** */
2423 static void syntax() {
2424 as_bad("syntax error");
2428 /*****************************************************************************
2430 * Return TRUE iff the target architecture supports the specified
2431 * special-function register (sfr).
2433 **************************************************************************** */
2437 int n
; /* Number (0-31) of sfr */
2439 switch (architecture
){
2446 return ((0<=n
) && (n
<=2));
2451 /*****************************************************************************
2453 * Return TRUE iff the target architecture supports the indicated
2454 * class of instructions.
2456 **************************************************************************** */
2460 int ic
; /* Instruction class; one of:
2461 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2464 iclasses_seen
|= ic
;
2465 switch (architecture
){
2466 case ARCH_KA
: return ic
& (I_BASE
| I_KX
);
2467 case ARCH_KB
: return ic
& (I_BASE
| I_KX
| I_FP
| I_DEC
);
2468 case ARCH_MC
: return ic
& (I_BASE
| I_KX
| I_FP
| I_DEC
| I_MIL
);
2469 case ARCH_CA
: return ic
& (I_BASE
| I_CX
| I_CASIM
);
2471 if ((iclasses_seen
& (I_KX
|I_FP
|I_DEC
|I_MIL
))
2472 && (iclasses_seen
& I_CX
)){
2473 as_warn("architecture of opcode conflicts with that of earlier instruction(s)");
2474 iclasses_seen
&= ~ic
;
2481 /* Parse an operand that is machine-specific.
2482 We just return without modifying the expression if we have nothing
2487 md_operand (expressionP
)
2488 expressionS
*expressionP
;
2492 /* We have no need to default values of symbols. */
2495 symbolS
*md_undefined_symbol(name
)
2499 } /* md_undefined_symbol() */
2501 /* Exactly what point is a PC-relative offset relative TO?
2502 On the i960, they're relative to the address of the instruction,
2503 which we have set up as the address of the fixup too. */
2505 md_pcrel_from (fixP
)
2508 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2512 md_apply_fix(fixP
, val
)
2516 char *place
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2518 if (!fixP
->fx_bit_fixP
) {
2520 switch (fixP
->fx_im_disp
) {
2522 fixP
->fx_addnumber
= val
;
2523 md_number_to_imm(place
, val
, fixP
->fx_size
, fixP
);
2526 md_number_to_disp(place
,
2527 fixP
->fx_pcrel
? val
+ fixP
->fx_pcrel_adjust
: val
,
2530 case 2: /* fix requested for .long .word etc */
2531 md_number_to_chars(place
, val
, fixP
->fx_size
);
2534 as_fatal("Internal error in md_apply_fix() in file \"%s\"", __FILE__
);
2535 } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */
2537 md_number_to_field(place
, val
, fixP
->fx_bit_fixP
);
2541 } /* md_apply_fix() */
2543 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2544 void tc_bout_fix_to_chars(where
, fixP
, segment_address_in_file
)
2547 relax_addressT segment_address_in_file
;
2549 static unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
2550 struct relocation_info ri
;
2553 /* JF this is for paranoia */
2554 memset((char *)&ri
, '\0', sizeof(ri
));
2556 know((symbolP
= fixP
->fx_addsy
) != 0);
2558 /* These two 'cuz of NS32K */
2559 ri
.r_callj
= fixP
->fx_callj
;
2561 ri
.r_length
= nbytes_r_length
[fixP
->fx_size
];
2562 ri
.r_pcrel
= fixP
->fx_pcrel
;
2563 ri
.r_address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
;
2565 if (!S_IS_DEFINED(symbolP
)) {
2567 ri
.r_index
= symbolP
->sy_number
;
2570 ri
.r_index
= S_GET_TYPE(symbolP
);
2573 /* Output the relocation information in machine-dependent form. */
2574 md_ri_to_chars(where
, &ri
);
2577 } /* tc_bout_fix_to_chars() */
2579 #endif /* OBJ_AOUT or OBJ_BOUT */
2581 /* Align an address by rounding it up to the specified boundary.
2583 long md_section_align(seg
, addr
)
2585 long addr
; /* Address to be rounded up */
2587 return((addr
+ (1 << section_alignment
[(int) seg
]) - 1) & (-1 << section_alignment
[(int) seg
]));
2588 } /* md_section_align() */
2591 void tc_headers_hook(headers
)
2592 object_headers
*headers
;
2594 /* FIXME: remove this line */ /* unsigned short arch_flag = 0; */
2596 if (iclasses_seen
== I_BASE
){
2597 headers
->filehdr
.f_flags
|= F_I960CORE
;
2598 } else if (iclasses_seen
& I_CX
){
2599 headers
->filehdr
.f_flags
|= F_I960CA
;
2600 } else if (iclasses_seen
& I_MIL
){
2601 headers
->filehdr
.f_flags
|= F_I960MC
;
2602 } else if (iclasses_seen
& (I_DEC
|I_FP
)){
2603 headers
->filehdr
.f_flags
|= F_I960KB
;
2605 headers
->filehdr
.f_flags
|= F_I960KA
;
2606 } /* set arch flag */
2608 if (flagseen
['R']) {
2609 headers
->filehdr
.f_magic
= I960RWMAGIC
;
2610 headers
->aouthdr
.magic
= OMAGIC
;
2612 headers
->filehdr
.f_magic
= I960ROMAGIC
;
2613 headers
->aouthdr
.magic
= NMAGIC
;
2614 } /* set magic numbers */
2617 } /* tc_headers_hook() */
2618 #endif /* OBJ_COFF */
2621 * Things going on here:
2623 * For bout, We need to assure a couple of simplifying
2624 * assumptions about leafprocs for the linker: the leafproc
2625 * entry symbols will be defined in the same assembly in
2626 * which they're declared with the '.leafproc' directive;
2627 * and if a leafproc has both 'call' and 'bal' entry points
2628 * they are both global or both local.
2630 * For coff, the call symbol has a second aux entry that
2631 * contains the bal entry point. The bal symbol becomes a
2634 * For coff representation, the call symbol has a second aux entry that
2635 * contains the bal entry point. The bal symbol becomes a label.
2639 void tc_crawl_symbol_chain(headers
)
2640 object_headers
*headers
;
2644 for (symbolP
= symbol_rootP
; symbolP
; symbolP
= symbol_next(symbolP
)) {
2646 if (TC_S_IS_SYSPROC(symbolP
)) {
2647 /* second aux entry already contains the sysproc number */
2648 S_SET_NUMBER_AUXILIARY(symbolP
, 2);
2649 S_SET_STORAGE_CLASS(symbolP
, C_SCALL
);
2650 S_SET_DATA_TYPE(symbolP
, S_GET_DATA_TYPE(symbolP
) | (DT_FCN
<< N_BTSHFT
));
2652 } /* rewrite sysproc */
2653 #endif /* OBJ_COFF */
2655 if (!TC_S_IS_BALNAME(symbolP
) && !TC_S_IS_CALLNAME(symbolP
)) {
2657 } /* Not a leafproc symbol */
2659 if (!S_IS_DEFINED(symbolP
)) {
2660 as_bad("leafproc symbol '%s' undefined", S_GET_NAME(symbolP
));
2661 } /* undefined leaf */
2663 if (TC_S_IS_CALLNAME(symbolP
)) {
2664 symbolS
*balP
= tc_get_bal_of_call(symbolP
);
2665 if (S_IS_EXTERNAL(symbolP
) != S_IS_EXTERNAL(balP
)) {
2666 S_SET_EXTERNAL(symbolP
);
2667 S_SET_EXTERNAL(balP
);
2668 as_warn("Warning: making leafproc entries %s and %s both global\n",
2669 S_GET_NAME(symbolP
), S_GET_NAME(balP
));
2670 } /* externality mismatch */
2672 } /* walk the symbol chain */
2675 } /* tc_crawl_symbol_chain() */
2678 * For aout or bout, the bal immediately follows the call.
2680 * For coff, we cheat and store a pointer to the bal symbol
2681 * in the second aux entry of the call.
2684 void tc_set_bal_of_call(callP
, balP
)
2688 know(TC_S_IS_CALLNAME(callP
));
2689 know(TC_S_IS_BALNAME(balP
));
2693 callP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
= (int) balP
;
2694 S_SET_NUMBER_AUXILIARY(callP
,2);
2696 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2698 /* If the 'bal' entry doesn't immediately follow the 'call'
2699 * symbol, unlink it from the symbol list and re-insert it.
2701 if (symbol_next(callP
) != balP
) {
2702 symbol_remove(balP
, &symbol_rootP
, &symbol_lastP
);
2703 symbol_append(balP
, callP
, &symbol_rootP
, &symbol_lastP
);
2704 } /* if not in order */
2707 (as yet unwritten
.);
2708 #endif /* switch on OBJ_FORMAT */
2711 } /* tc_set_bal_of_call() */
2713 char *_tc_get_bal_of_call(callP
)
2718 know(TC_S_IS_CALLNAME(callP
));
2721 retval
= (symbolS
*) (callP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
);
2722 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2723 retval
= symbol_next(callP
);
2725 (as yet unwritten
.);
2726 #endif /* switch on OBJ_FORMAT */
2728 know(TC_S_IS_BALNAME(retval
));
2729 return((char *) retval
);
2730 } /* _tc_get_bal_of_call() */
2732 void tc_coff_symbol_emit_hook(symbolP
)
2735 if (TC_S_IS_CALLNAME(symbolP
)) {
2737 symbolS
*balP
= tc_get_bal_of_call(symbolP
);
2739 /* second aux entry contains the bal entry point */
2740 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
2741 symbolP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
= S_GET_VALUE(balP
);
2742 S_SET_STORAGE_CLASS(symbolP
, (!SF_GET_LOCAL(symbolP
) ? C_LEAFEXT
: C_LEAFSTAT
));
2743 S_SET_DATA_TYPE(symbolP
, S_GET_DATA_TYPE(symbolP
) | (DT_FCN
<< N_BTSHFT
));
2744 /* fix up the bal symbol */
2745 S_SET_STORAGE_CLASS(balP
, C_LABEL
);
2746 #endif /* OBJ_COFF */
2747 } /* only on calls */
2750 } /* tc_coff_symbol_emit_hook() */
2759 /* end of tc-i960.c */