1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER
33 * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO
34 * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <==
36 ***************************************************************************** */
38 /* There are 4 different lengths of (potentially) symbol-based displacements
39 * in the 80960 instruction set, each of which could require address fix-ups
40 * and (in the case of external symbols) emission of relocation directives:
43 * This is a standard length for the base assembler and requires no
47 * This is a non-standard length, but the base assembler has a hook for
48 * bit field address fixups: the fixS structure can point to a descriptor
49 * of the field, in which case our md_number_to_field() routine gets called
52 * I made the hook a little cleaner by having fix_new() (in the base
53 * assembler) return a pointer to the fixS in question. And I made it a
54 * little simpler by storing the field size (in this case 13) instead of
55 * of a pointer to another structure: 80960 displacements are ALWAYS
56 * stored in the low-order bits of a 4-byte word.
58 * Since the target of a COBR cannot be external, no relocation directives
59 * for this size displacement have to be generated. But the base assembler
60 * had to be modified to issue error messages if the symbol did turn out
64 * Fixups are handled as for the 13-bit case (except that 24 is stored
67 * The relocation directive generated is the same as that for the 32-bit
68 * displacement, except that it's PC-relative (the 32-bit displacement
69 * never is). The i80960 version of the linker needs a mod to
70 * distinguish and handle the 24-bit case.
73 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
74 * is based on a symbol, because it could be relocated at link time.
75 * The only time we use the 12-bit format is if an absolute value of
76 * less than 4096 is specified, in which case we need neither a fixup nor
77 * a relocation directive.
88 #include "opcode/i960.h"
90 extern char *input_line_pointer
;
91 extern struct hash_control
*po_hash
;
92 extern char *next_object_file_charP
;
95 int md_reloc_size
= sizeof (struct reloc
);
97 int md_reloc_size
= sizeof (struct relocation_info
);
100 /***************************
101 * Local i80960 routines *
102 ************************** */
104 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
105 static char *brlab_next (); /* Return next branch local label */
106 void brtab_emit (); /* Emit br-predict instrumentation table */
107 static void cobr_fmt (); /* Generate COBR instruction */
108 static void ctrl_fmt (); /* Generate CTRL instruction */
109 static char *emit (); /* Emit (internally) binary */
110 static int get_args (); /* Break arguments out of comma-separated list */
111 static void get_cdisp (); /* Handle COBR or CTRL displacement */
112 static char *get_ispec (); /* Find index specification string */
113 static int get_regnum (); /* Translate text to register number */
114 static int i_scan (); /* Lexical scan of instruction source */
115 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
116 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
117 static segT
parse_expr (); /* Parse an expression */
118 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
119 static void parse_memop (); /* Parse a memory operand */
120 static void parse_po (); /* Parse machine-dependent pseudo-op */
121 static void parse_regop (); /* Parse a register operand */
122 static void reg_fmt (); /* Generate a REG format instruction */
123 void reloc_callj (); /* Relocate a 'callj' instruction */
124 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
125 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
126 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
127 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
128 static void syntax (); /* Give syntax error */
129 static int targ_has_sfr (); /* Target chip supports spec-func register? */
130 static int targ_has_iclass (); /* Target chip supports instruction set? */
131 /* static void unlink_sym(); *//* Remove a symbol from the symbol list */
133 /* See md_parse_option() for meanings of these options */
134 static char norelax
; /* True if -norelax switch seen */
135 static char instrument_branches
;/* True if -b switch seen */
137 /* Characters that always start a comment.
138 * If the pre-processor is disabled, these aren't very useful.
140 const char comment_chars
[] = "#";
142 /* Characters that only start a comment at the beginning of
143 * a line. If the line seems to have the form '# 123 filename'
144 * .line and .file directives will appear in the pre-processed output.
146 * Note that input_file.c hand checks for '#' at the beginning of the
147 * first line of the input file. This is because the compiler outputs
148 * #NO_APP at the beginning of its output.
151 /* Also note that comments started like this one will always work. */
153 const char line_comment_chars
[] = "";
155 const char line_separator_chars
[] = "";
157 /* Chars that can be used to separate mant from exp in floating point nums */
158 const char EXP_CHARS
[] = "eE";
160 /* Chars that mean this number is a floating point constant,
161 * as in 0f12.456 or 0d1.2345e12
163 const char FLT_CHARS
[] = "fFdDtT";
166 /* Table used by base assembler to relax addresses based on varying length
167 * instructions. The fields are:
168 * 1) most positive reach of this state,
169 * 2) most negative reach of this state,
170 * 3) how many bytes this mode will add to the size of the current frag
171 * 4) which index into the table to try if we can't fit into this one.
173 * For i80960, the only application is the (de-)optimization of cobr
174 * instructions into separate compare and branch instructions when a 13-bit
175 * displacement won't hack it.
180 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
181 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
182 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
186 /* These are the machine dependent pseudo-ops.
188 * This table describes all the machine specific pseudo-ops the assembler
189 * has to support. The fields are:
190 * pseudo-op name without dot
191 * function to call to execute this pseudo-op
192 * integer arg to pass to the function
197 const pseudo_typeS md_pseudo_table
[] =
200 {"extended", float_cons
, 't'},
201 {"leafproc", parse_po
, S_LEAFPROC
},
202 {"sysproc", parse_po
, S_SYSPROC
},
205 {"quad", big_cons
, 16},
210 /* Macros to extract info from an 'expressionS' structure 'e' */
211 #define adds(e) e.X_add_symbol
212 #define subs(e) e.X_subtract_symbol
213 #define offs(e) e.X_add_number
214 #define segs(e) e.X_seg
217 /* Branch-prediction bits for CTRL/COBR format opcodes */
218 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
219 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
220 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
223 /* Some instruction opcodes that we need explicitly */
224 #define BE 0x12000000
225 #define BG 0x11000000
226 #define BGE 0x13000000
227 #define BL 0x14000000
228 #define BLE 0x16000000
229 #define BNE 0x15000000
230 #define BNO 0x10000000
231 #define BO 0x17000000
232 #define CHKBIT 0x5a002700
233 #define CMPI 0x5a002080
234 #define CMPO 0x5a002000
237 #define BAL 0x0b000000
238 #define CALL 0x09000000
239 #define CALLS 0x66003800
240 #define RET 0x0a000000
243 /* These masks are used to build up a set of MEMB mode bits. */
246 #define MEMB_BIT 0x1000
250 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */
251 #define MEMA_ABASE 0x2000
253 /* Info from which a MEMA or MEMB format instruction can be generated */
256 long opcode
; /* (First) 32 bits of instruction */
257 int disp
; /* 0-(none), 12- or, 32-bit displacement needed */
258 char *e
; /* The expression in the source instruction from
259 * which the displacement should be determined
266 /* The two pieces of info we need to generate a register operand */
269 int mode
; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
270 int special
; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
271 int n
; /* Register number or literal value */
275 /* Number and assembler mnemonic for all registers that can appear in operands */
317 /* Numbers for special-function registers are for assembler internal
318 use only: they are scaled back to range [0-31] for binary output. */
354 /* Numbers for floating point registers are for assembler internal use
355 * only: they are scaled back to [0-3] for binary output.
364 { NULL
, 0 }, /* END OF LIST */
367 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
368 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
369 #define IS_FP_REG(n) ((n) >= FP0)
371 /* Number and assembler mnemonic for all registers that can appear as 'abase'
372 * (indirect addressing) registers.
416 /* For assembler internal use only: this number never appears in binary
420 { NULL
, 0 }, /* END OF LIST */
425 static struct hash_control
*op_hash
= NULL
; /* Opcode mnemonics */
426 static struct hash_control
*reg_hash
= NULL
; /* Register name hash table */
427 static struct hash_control
*areg_hash
= NULL
; /* Abase register hash table */
430 /* Architecture for which we are assembling */
431 #define ARCH_ANY 0 /* Default: no architecture checking done */
436 int architecture
= ARCH_ANY
; /* Architecture requested on invocation line */
437 int iclasses_seen
= 0; /* OR of instruction classes (I_* constants)
438 * for which we've actually assembled
443 /* BRANCH-PREDICTION INSTRUMENTATION
445 * The following supports generation of branch-prediction instrumentation
446 * (turned on by -b switch). The instrumentation collects counts
447 * of branches taken/not-taken for later input to a utility that will
448 * set the branch prediction bits of the instructions in accordance with
449 * the behavior observed. (Note that the KX series does not have
452 * The instrumentation consists of:
454 * (1) before and after each conditional branch, a call to an external
455 * routine that increments and steps over an inline counter. The
456 * counter itself, initialized to 0, immediately follows the call
457 * instruction. For each branch, the counter following the branch
458 * is the number of times the branch was not taken, and the difference
459 * between the counters is the number of times it was taken. An
460 * example of an instrumented conditional branch:
464 * LBRANCH23: be label
468 * (2) a table of pointers to the instrumented branches, so that an
469 * external postprocessing routine can locate all of the counters.
470 * the table begins with a 2-word header: a pointer to the next in
471 * a linked list of such tables (initialized to 0); and a count
472 * of the number of entries in the table (exclusive of the header.
474 * Note that input source code is expected to already contain calls
475 * an external routine that will link the branch local table into a
476 * list of such tables.
479 static int br_cnt
= 0; /* Number of branches instrumented so far.
480 * Also used to generate unique local labels
481 * for each instrumented branch
484 #define BR_LABEL_BASE "LBRANCH"
485 /* Basename of local labels on instrumented
486 * branches, to avoid conflict with compiler-
487 * generated local labels.
490 #define BR_CNT_FUNC "__inc_branch"
491 /* Name of the external routine that will
492 * increment (and step over) an inline counter.
495 #define BR_TAB_NAME "__BRANCH_TABLE__"
496 /* Name of the table of pointers to branches.
497 * A local (i.e., non-external) symbol.
500 /*****************************************************************************
501 * md_begin: One-time initialization.
503 * Set up hash tables.
505 **************************************************************************** */
509 int i
; /* Loop counter */
510 const struct i960_opcode
*oP
; /* Pointer into opcode table */
511 char *retval
; /* Value returned by hash functions */
513 if (((op_hash
= hash_new ()) == 0)
514 || ((reg_hash
= hash_new ()) == 0)
515 || ((areg_hash
= hash_new ()) == 0))
517 as_fatal ("virtual memory exceeded");
520 retval
= ""; /* For some reason, the base assembler uses an empty
521 * string for "no error message", instead of a NULL
525 for (oP
= i960_opcodes
; oP
->name
&& !*retval
; oP
++)
527 retval
= hash_insert (op_hash
, oP
->name
, oP
);
530 for (i
= 0; regnames
[i
].reg_name
&& !*retval
; i
++)
532 retval
= hash_insert (reg_hash
, regnames
[i
].reg_name
,
533 ®names
[i
].reg_num
);
536 for (i
= 0; aregs
[i
].areg_name
&& !*retval
; i
++)
538 retval
= hash_insert (areg_hash
, aregs
[i
].areg_name
,
544 as_fatal ("Hashing returned \"%s\".", retval
);
548 /*****************************************************************************
549 * md_end: One-time final cleanup
553 **************************************************************************** */
559 /*****************************************************************************
560 * md_assemble: Assemble an instruction
562 * Assumptions about the passed-in text:
563 * - all comments, labels removed
564 * - text is an instruction
565 * - all white space compressed to single blanks
566 * - all character constants have been replaced with decimal
568 **************************************************************************** */
571 char *textP
; /* Source text of instruction */
573 char *args
[4]; /* Parsed instruction text, containing NO whitespace:
574 * arg[0]->opcode mnemonic
575 * arg[1-3]->operands, with char constants
576 * replaced by decimal numbers
578 int n_ops
; /* Number of instruction operands */
580 struct i960_opcode
*oP
;
581 /* Pointer to instruction description */
583 /* TRUE iff opcode mnemonic included branch-prediction
584 * suffix (".f" or ".t")
586 long bp_bits
; /* Setting of branch-prediction bit(s) to be OR'd
587 * into instruction opcode of CTRL/COBR format
590 int n
; /* Offset of last character in opcode mnemonic */
592 static const char bp_error_msg
[] = "branch prediction invalid on this opcode";
595 /* Parse instruction into opcode and operands */
596 memset (args
, '\0', sizeof (args
));
597 n_ops
= i_scan (textP
, args
);
600 return; /* Error message already issued */
603 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
604 if (!strcmp (args
[0], "ldconst"))
606 n_ops
= parse_ldconst (args
);
615 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
616 n
= strlen (args
[0]) - 1;
619 if (args
[0][n
- 1] == '.' && (args
[0][n
] == 't' || args
[0][n
] == 'f'))
621 /* We could check here to see if the target architecture
622 * supports branch prediction, but why bother? The bit
623 * will just be ignored by processors that don't use it.
626 bp_bits
= (args
[0][n
] == 't') ? BP_TAKEN
: BP_NOT_TAKEN
;
627 args
[0][n
- 1] = '\0'; /* Strip suffix from opcode mnemonic */
630 /* Look up opcode mnemonic in table and check number of operands.
631 * Check that opcode is legal for the target architecture.
632 * If all looks good, assemble instruction.
634 oP
= (struct i960_opcode
*) hash_find (op_hash
, args
[0]);
635 if (!oP
|| !targ_has_iclass (oP
->iclass
))
637 as_bad ("invalid opcode, \"%s\".", args
[0]);
640 else if (n_ops
!= oP
->num_ops
)
642 as_bad ("improper number of operands. expecting %d, got %d", oP
->num_ops
, n_ops
);
651 ctrl_fmt (args
[1], oP
->opcode
| bp_bits
, oP
->num_ops
);
652 if (oP
->format
== FBRA
)
654 /* Now generate a 'bno' to same arg */
655 ctrl_fmt (args
[1], BNO
| bp_bits
, 1);
660 cobr_fmt (args
, oP
->opcode
| bp_bits
, oP
);
665 as_warn (bp_error_msg
);
670 if (args
[0][0] == 'c' && args
[0][1] == 'a')
674 as_warn (bp_error_msg
);
676 mem_fmt (args
, oP
, 1);
686 as_warn (bp_error_msg
);
688 mem_fmt (args
, oP
, 0);
693 as_warn (bp_error_msg
);
695 /* Output opcode & set up "fixup" (relocation);
696 * flag relocation as 'callj' type.
698 know (oP
->num_ops
== 1);
699 get_cdisp (args
[1], "CTRL", oP
->opcode
, 24, 0, 1);
702 BAD_CASE (oP
->format
);
706 } /* md_assemble() */
708 /*****************************************************************************
709 * md_number_to_chars: convert a number to target byte order
711 **************************************************************************** */
713 md_number_to_chars (buf
, value
, n
)
714 char *buf
; /* Put output here */
715 long value
; /* The integer to be converted */
716 int n
; /* Number of bytes to output (significant bytes
726 /* XXX line number probably botched for this warning message. */
727 if (value
!= 0 && value
!= -1)
729 as_bad ("Displacement too long for instruction field length.");
733 } /* md_number_to_chars() */
735 /*****************************************************************************
736 * md_chars_to_number: convert from target byte order to host byte order.
738 **************************************************************************** */
740 md_chars_to_number (val
, n
)
741 unsigned char *val
; /* Value in target byte order */
742 int n
; /* Number of bytes in the input */
746 for (retval
= 0; n
--;)
755 #define MAX_LITTLENUMS 6
756 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
758 /*****************************************************************************
759 * md_atof: convert ascii to floating point
761 * Turn a string at input_line_pointer into a floating point constant of type
762 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
763 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
764 * to an empty message if OK.
766 * Note we call the i386 floating point routine, rather than complicating
767 * things with more files or symbolic links.
769 **************************************************************************** */
771 md_atof (type
, litP
, sizeP
)
776 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
777 LITTLENUM_TYPE
*wordP
;
797 type
= 'x'; /* That's what atof_ieee() understands */
802 return "Bad call to md_atof()";
805 t
= atof_ieee (input_line_pointer
, type
, words
);
808 input_line_pointer
= t
;
811 *sizeP
= prec
* LNUM_SIZE
;
813 /* Output the LITTLENUMs in REVERSE order in accord with i80960
814 * word-order. (Dunno why atof_ieee doesn't do it in the right
815 * order in the first place -- probably because it's a hack of
819 for (wordP
= words
+ prec
- 1; prec
--;)
821 md_number_to_chars (litP
, (long) (*wordP
--), LNUM_SIZE
);
822 litP
+= sizeof (LITTLENUM_TYPE
);
825 return ""; /* Someone should teach Dean about null pointers */
829 /*****************************************************************************
832 **************************************************************************** */
834 md_number_to_imm (buf
, val
, n
)
839 md_number_to_chars (buf
, val
, n
);
843 /*****************************************************************************
846 **************************************************************************** */
848 md_number_to_disp (buf
, val
, n
)
853 md_number_to_chars (buf
, val
, n
);
856 /*****************************************************************************
857 * md_number_to_field:
859 * Stick a value (an address fixup) into a bit field of
860 * previously-generated instruction.
862 **************************************************************************** */
864 md_number_to_field (instrP
, val
, bfixP
)
865 char *instrP
; /* Pointer to instruction to be fixed */
866 long val
; /* Address fixup value */
867 bit_fixS
*bfixP
; /* Description of bit field to be fixed up */
869 int numbits
; /* Length of bit field to be fixed */
870 long instr
; /* 32-bit instruction to be fixed-up */
871 long sign
; /* 0 or -1, according to sign bit of 'val' */
873 /* Convert instruction back to host byte order
875 instr
= md_chars_to_number (instrP
, 4);
877 /* Surprise! -- we stored the number of bits
878 * to be modified rather than a pointer to a structure.
880 numbits
= (int) bfixP
;
883 /* This is a no-op, stuck here by reloc_callj() */
887 know ((numbits
== 13) || (numbits
== 24));
889 /* Propagate sign bit of 'val' for the given number of bits.
890 * Result should be all 0 or all 1
892 sign
= val
>> ((int) numbits
- 1);
893 if (((val
< 0) && (sign
!= -1))
894 || ((val
> 0) && (sign
!= 0)))
896 as_bad ("Fixup of %d too large for field width of %d",
901 /* Put bit field into instruction and write back in target
904 val
&= ~(-1 << (int) numbits
); /* Clear unused sign bits */
906 md_number_to_chars (instrP
, instr
, 4);
908 } /* md_number_to_field() */
911 /*****************************************************************************
913 * Invocation line includes a switch not recognized by the base assembler.
914 * See if it's a processor-specific option. For the 960, these are:
917 * Conditional branch instructions that require displacements
918 * greater than 13 bits (or that have external targets) should
919 * generate errors. The default is to replace each such
920 * instruction with the corresponding compare (or chkbit) and
921 * branch instructions. Note that the Intel "j" cobr directives
922 * are ALWAYS "de-optimized" in this way when necessary,
923 * regardless of the setting of this option.
926 * Add code to collect information about branches taken, for
927 * later optimization of branch prediction bits by a separate
928 * tool. COBR and CNTL format instructions have branch
929 * prediction bits (in the CX architecture); if "BR" represents
930 * an instruction in one of these classes, the following rep-
931 * resents the code generated by the assembler:
933 * call <increment routine>
934 * .word 0 # pre-counter
936 * call <increment routine>
937 * .word 0 # post-counter
939 * A table of all such "Labels" is also generated.
942 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
943 * Select the 80960 architecture. Instructions or features not
944 * supported by the selected architecture cause fatal errors.
945 * The default is to generate code for any instruction or feature
946 * that is supported by SOME version of the 960 (even if this
947 * means mixing architectures!).
949 **************************************************************************** */
951 md_parse_option (argP
, cntP
, vecP
)
962 static struct tabentry arch_tab
[] =
966 "SA", ARCH_KA
, /* Synonym for KA */
967 "SB", ARCH_KB
, /* Synonym for KB */
968 "KC", ARCH_MC
, /* Synonym for MC */
974 if (!strcmp (*argP
, "linkrelax"))
979 else if (!strcmp (*argP
, "norelax"))
984 else if (**argP
== 'b')
986 instrument_branches
= 1;
989 else if (**argP
== 'A')
993 for (tp
= arch_tab
; tp
->flag
!= NULL
; tp
++)
995 if (!strcmp (p
, tp
->flag
))
1001 if (tp
->flag
== NULL
)
1003 as_bad ("unknown architecture: %s", p
);
1007 architecture
= tp
->arch
;
1012 /* Unknown option */
1016 **argP
= '\0'; /* Done parsing this switch */
1020 /*****************************************************************************
1022 * Called by base assembler after address relaxation is finished: modify
1023 * variable fragments according to how much relaxation was done.
1025 * If the fragment substate is still 1, a 13-bit displacement was enough
1026 * to reach the symbol in question. Set up an address fixup, but otherwise
1027 * leave the cobr instruction alone.
1029 * If the fragment substate is 2, a 13-bit displacement was not enough.
1030 * Replace the cobr with a two instructions (a compare and a branch).
1032 **************************************************************************** */
1034 md_convert_frag (headers
, fragP
)
1035 object_headers
*headers
;
1038 fixS
*fixP
; /* Structure describing needed address fix */
1040 switch (fragP
->fr_subtype
)
1043 /* LEAVE SINGLE COBR INSTRUCTION */
1044 fixP
= fix_new (fragP
,
1045 fragP
->fr_opcode
- fragP
->fr_literal
,
1053 fixP
->fx_bit_fixP
= (bit_fixS
*) 13; /* size of bit field */
1056 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1060 BAD_CASE (fragP
->fr_subtype
);
1065 /*****************************************************************************
1066 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
1068 * Called by base assembler just before address relaxation.
1069 * Return the amount by which the fragment will grow.
1071 * Any symbol that is now undefined will not become defined; cobr's
1072 * based on undefined symbols will have to be replaced with a compare
1073 * instruction and a branch instruction, and the code fragment will grow
1076 **************************************************************************** */
1078 md_estimate_size_before_relax (fragP
, segment_type
)
1079 register fragS
*fragP
;
1080 register segT segment_type
;
1082 /* If symbol is undefined in this segment, go to "relaxed" state
1083 * (compare and branch instructions instead of cobr) right now.
1085 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment_type
)
1091 } /* md_estimate_size_before_relax() */
1094 /*****************************************************************************
1096 * This routine exists in order to overcome machine byte-order problems
1097 * when dealing with bit-field entries in the relocation_info struct.
1099 * But relocation info will be used on the host machine only (only
1100 * executable code is actually downloaded to the i80960). Therefore,
1101 * we leave it in host byte order.
1103 * The above comment is no longer true. This routine now really
1104 * does do the reordering (Ian Taylor 28 Aug 92).
1106 **************************************************************************** */
1108 md_ri_to_chars (where
, ri
)
1110 struct relocation_info
*ri
;
1112 md_number_to_chars (where
, ri
->r_address
,
1113 sizeof (ri
->r_address
));
1114 where
[4] = ri
->r_index
& 0x0ff;
1115 where
[5] = (ri
->r_index
>> 8) & 0x0ff;
1116 where
[6] = (ri
->r_index
>> 16) & 0x0ff;
1117 where
[7] = ((ri
->r_pcrel
<< 0)
1118 | (ri
->r_length
<< 1)
1119 | (ri
->r_extern
<< 3)
1122 | (ri
->r_callj
<< 6));
1123 } /* md_ri_to_chars() */
1125 #ifndef WORKING_DOT_WORD
1127 int md_short_jump_size
= 0;
1128 int md_long_jump_size
= 0;
1131 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
1138 as_fatal ("failed sanity check.");
1142 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
1144 long from_addr
, to_addr
;
1148 as_fatal ("failed sanity check.");
1153 /*************************************************************
1155 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
1157 ************************************************************ */
1161 /*****************************************************************************
1162 * brcnt_emit: Emit code to increment inline branch counter.
1164 * See the comments above the declaration of 'br_cnt' for details on
1165 * branch-prediction instrumentation.
1166 **************************************************************************** */
1170 ctrl_fmt (BR_CNT_FUNC
, CALL
, 1); /* Emit call to "increment" routine */
1171 emit (0); /* Emit inline counter to be incremented */
1174 /*****************************************************************************
1175 * brlab_next: generate the next branch local label
1177 * See the comments above the declaration of 'br_cnt' for details on
1178 * branch-prediction instrumentation.
1179 **************************************************************************** */
1183 static char buf
[20];
1185 sprintf (buf
, "%s%d", BR_LABEL_BASE
, br_cnt
++);
1189 /*****************************************************************************
1190 * brtab_emit: generate the fetch-prediction branch table.
1192 * See the comments above the declaration of 'br_cnt' for details on
1193 * branch-prediction instrumentation.
1195 * The code emitted here would be functionally equivalent to the following
1196 * example assembler source.
1201 * .word 0 # link to next table
1202 * .word 3 # length of table
1203 * .word LBRANCH0 # 1st entry in table proper
1206 ***************************************************************************** */
1212 char *p
; /* Where the binary was output to */
1213 fixS
*fixP
; /*->description of deferred address fixup */
1215 if (!instrument_branches
)
1220 subseg_new (SEG_DATA
, 0); /* .data */
1221 frag_align (2, 0); /* .align 2 */
1222 record_alignment (now_seg
, 2);
1223 colon (BR_TAB_NAME
); /* BR_TAB_NAME: */
1224 emit (0); /* .word 0 #link to next table */
1225 emit (br_cnt
); /* .word n #length of table */
1227 for (i
= 0; i
< br_cnt
; i
++)
1229 sprintf (buf
, "%s%d", BR_LABEL_BASE
, i
);
1231 fixP
= fix_new (frag_now
,
1232 p
- frag_now
->fr_literal
,
1239 fixP
->fx_im_disp
= 2; /* 32-bit displacement fix */
1243 /*****************************************************************************
1244 * cobr_fmt: generate a COBR-format instruction
1246 **************************************************************************** */
1249 cobr_fmt (arg
, opcode
, oP
)
1250 char *arg
[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1251 long opcode
; /* Opcode, with branch-prediction bits already set
1254 struct i960_opcode
*oP
;
1255 /*->description of instruction */
1257 long instr
; /* 32-bit instruction */
1258 struct regop regop
; /* Description of register operand */
1259 int n
; /* Number of operands */
1260 int var_frag
; /* 1 if varying length code fragment should
1261 * be emitted; 0 if an address fix
1262 * should be emitted.
1270 /* First operand (if any) of a COBR is always a register
1271 * operand. Parse it.
1273 parse_regop (®op
, arg
[1], oP
->operand
[0]);
1274 instr
|= (regop
.n
<< 19) | (regop
.mode
<< 13);
1278 /* Second operand (if any) of a COBR is always a register
1279 * operand. Parse it.
1281 parse_regop (®op
, arg
[2], oP
->operand
[1]);
1282 instr
|= (regop
.n
<< 14) | regop
.special
;
1293 if (instrument_branches
)
1296 colon (brlab_next ());
1299 /* A third operand to a COBR is always a displacement.
1300 * Parse it; if it's relaxable (a cobr "j" directive, or any
1301 * cobr other than bbs/bbc when the "-norelax" option is not in
1302 * use) set up a variable code fragment; otherwise set up an
1305 var_frag
= !norelax
|| (oP
->format
== COJ
); /* TRUE or FALSE */
1306 get_cdisp (arg
[3], "COBR", instr
, 13, var_frag
, 0);
1308 if (instrument_branches
)
1316 /*****************************************************************************
1317 * ctrl_fmt: generate a CTRL-format instruction
1319 **************************************************************************** */
1322 ctrl_fmt (targP
, opcode
, num_ops
)
1323 char *targP
; /* Pointer to text of lone operand (if any) */
1324 long opcode
; /* Template of instruction */
1325 int num_ops
; /* Number of operands */
1327 int instrument
; /* TRUE iff we should add instrumentation to track
1328 * how often the branch is taken
1334 emit (opcode
); /* Output opcode */
1339 instrument
= instrument_branches
&& (opcode
!= CALL
)
1340 && (opcode
!= B
) && (opcode
!= RET
) && (opcode
!= BAL
);
1345 colon (brlab_next ());
1348 /* The operand MUST be an ip-relative displacment. Parse it
1349 * and set up address fix for the instruction we just output.
1351 get_cdisp (targP
, "CTRL", opcode
, 24, 0, 0);
1362 /*****************************************************************************
1363 * emit: output instruction binary
1365 * Output instruction binary, in target byte order, 4 bytes at a time.
1366 * Return pointer to where it was placed.
1368 **************************************************************************** */
1372 long instr
; /* Word to be output, host byte order */
1374 char *toP
; /* Where to output it */
1376 toP
= frag_more (4); /* Allocate storage */
1377 md_number_to_chars (toP
, instr
, 4); /* Convert to target byte order */
1382 /*****************************************************************************
1383 * get_args: break individual arguments out of comma-separated list
1385 * Input assumptions:
1386 * - all comments and labels have been removed
1387 * - all strings of whitespace have been collapsed to a single blank.
1388 * - all character constants ('x') have been replaced with decimal
1391 * args[0] is untouched. args[1] points to first operand, etc. All args:
1392 * - are NULL-terminated
1393 * - contain no whitespace
1396 * Number of operands (0,1,2, or 3) or -1 on error.
1398 **************************************************************************** */
1401 register char *p
; /* Pointer to comma-separated operands; MUCKED BY US */
1402 char *args
[]; /* Output arg: pointers to operands placed in args[1-3].
1403 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1406 register int n
; /* Number of operands */
1412 /* Skip lead white space */
1426 /* Squeze blanks out by moving non-blanks toward start of string.
1427 * Isolate operands, whenever comma is found.
1441 /* Start of operand */
1444 as_bad ("too many operands");
1447 *to
++ = '\0'; /* Terminate argument */
1448 args
[++n
] = to
; /* Start next argument */
1462 /*****************************************************************************
1463 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1465 * Parse displacement for a COBR or CTRL instruction.
1467 * If successful, output the instruction opcode and set up for it,
1468 * depending on the arg 'var_frag', either:
1469 * o an address fixup to be done when all symbol values are known, or
1470 * o a varying length code fragment, with address fixup info. This
1471 * will be done for cobr instructions that may have to be relaxed
1472 * in to compare/branch instructions (8 bytes) if the final address
1473 * displacement is greater than 13 bits.
1475 **************************************************************************** */
1478 get_cdisp (dispP
, ifmtP
, instr
, numbits
, var_frag
, callj
)
1479 char *dispP
; /*->displacement as specified in source instruction */
1480 char *ifmtP
; /*->"COBR" or "CTRL" (for use in error message) */
1481 long instr
; /* Instruction needing the displacement */
1482 int numbits
; /* # bits of displacement (13 for COBR, 24 for CTRL) */
1483 int var_frag
; /* 1 if varying length code fragment should be emitted;
1484 * 0 if an address fix should be emitted.
1486 int callj
; /* 1 if callj relocation should be done; else 0 */
1488 expressionS e
; /* Parsed expression */
1489 fixS
*fixP
; /* Structure describing needed address fix */
1490 char *outP
; /* Where instruction binary is output to */
1494 switch (parse_expr (dispP
, &e
))
1498 as_bad ("expression syntax error");
1505 outP
= frag_more (8); /* Allocate worst-case storage */
1506 md_number_to_chars (outP
, instr
, 4);
1507 frag_variant (rs_machine_dependent
, 4, 4, 1,
1508 adds (e
), offs (e
), outP
, 0, 0);
1512 /* Set up a new fix structure, so address can be updated
1513 * when all symbol values are known.
1515 outP
= emit (instr
);
1516 fixP
= fix_new (frag_now
,
1517 outP
- frag_now
->fr_literal
,
1525 fixP
->fx_callj
= callj
;
1527 /* We want to modify a bit field when the address is
1528 * known. But we don't need all the garbage in the
1529 * bit_fix structure. So we're going to lie and store
1530 * the number of bits affected instead of a pointer.
1532 fixP
->fx_bit_fixP
= (bit_fixS
*) numbits
;
1538 as_bad ("attempt to branch into different segment");
1542 as_bad ("target of %s instruction must be a label", ifmtP
);
1548 /*****************************************************************************
1549 * get_ispec: parse a memory operand for an index specification
1551 * Here, an "index specification" is taken to be anything surrounded
1552 * by square brackets and NOT followed by anything else.
1554 * If it's found, detach it from the input string, remove the surrounding
1555 * square brackets, and return a pointer to it. Otherwise, return NULL.
1557 **************************************************************************** */
1561 char *textP
; /*->memory operand from source instruction, no white space */
1563 char *start
; /*->start of index specification */
1564 char *end
; /*->end of index specification */
1566 /* Find opening square bracket, if any
1568 start
= strchr (textP
, '[');
1573 /* Eliminate '[', detach from rest of operand */
1576 end
= strchr (start
, ']');
1580 as_bad ("unmatched '['");
1585 /* Eliminate ']' and make sure it was the last thing
1589 if (*(end
+ 1) != '\0')
1591 as_bad ("garbage after index spec ignored");
1598 /*****************************************************************************
1601 * Look up a (suspected) register name in the register table and return the
1602 * associated register number (or -1 if not found).
1604 **************************************************************************** */
1607 get_regnum (regname
)
1608 char *regname
; /* Suspected register name */
1612 rP
= (int *) hash_find (reg_hash
, regname
);
1613 return (rP
== NULL
) ? -1 : *rP
;
1617 /*****************************************************************************
1618 * i_scan: perform lexical scan of ascii assembler instruction.
1620 * Input assumptions:
1621 * - input string is an i80960 instruction (not a pseudo-op)
1622 * - all comments and labels have been removed
1623 * - all strings of whitespace have been collapsed to a single blank.
1626 * args[0] points to opcode, other entries point to operands. All strings:
1627 * - are NULL-terminated
1628 * - contain no whitespace
1629 * - have character constants ('x') replaced with a decimal number
1632 * Number of operands (0,1,2, or 3) or -1 on error.
1634 **************************************************************************** */
1637 register char *iP
; /* Pointer to ascii instruction; MUCKED BY US. */
1638 char *args
[]; /* Output arg: pointers to opcode and operands placed
1639 * here. MUST ACCOMMODATE 4 ENTRIES.
1643 /* Isolate opcode */
1647 } /* Skip lead space, if any */
1649 for (; *iP
!= ' '; iP
++)
1653 /* There are no operands */
1656 /* We never moved: there was no opcode either! */
1657 as_bad ("missing opcode");
1663 *iP
++ = '\0'; /* Terminate opcode */
1664 return (get_args (iP
, args
));
1668 /*****************************************************************************
1669 * mem_fmt: generate a MEMA- or MEMB-format instruction
1671 **************************************************************************** */
1673 mem_fmt (args
, oP
, callx
)
1674 char *args
[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1675 struct i960_opcode
*oP
; /* Pointer to description of instruction */
1676 int callx
; /* Is this a callx opcode */
1678 int i
; /* Loop counter */
1679 struct regop regop
; /* Description of register operand */
1680 char opdesc
; /* Operand descriptor byte */
1681 memS instr
; /* Description of binary to be output */
1682 char *outP
; /* Where the binary was output to */
1683 expressionS expr
; /* Parsed expression */
1684 fixS
*fixP
; /*->description of deferred address fixup */
1686 memset (&instr
, '\0', sizeof (memS
));
1687 instr
.opcode
= oP
->opcode
;
1689 /* Process operands. */
1690 for (i
= 1; i
<= oP
->num_ops
; i
++)
1692 opdesc
= oP
->operand
[i
- 1];
1696 parse_memop (&instr
, args
[i
], oP
->format
);
1700 parse_regop (®op
, args
[i
], opdesc
);
1701 instr
.opcode
|= regop
.n
<< 19;
1706 outP
= emit (instr
.opcode
);
1708 if (instr
.disp
== 0)
1713 /* Parse and process the displacement */
1714 switch (parse_expr (instr
.e
, &expr
))
1718 as_bad ("expression syntax error");
1722 if (instr
.disp
== 32)
1724 (void) emit (offs (expr
)); /* Output displacement */
1728 /* 12-bit displacement */
1729 if (offs (expr
) & ~0xfff)
1731 /* Won't fit in 12 bits: convert already-output
1732 * instruction to MEMB format, output
1735 mema_to_memb (outP
);
1736 (void) emit (offs (expr
));
1740 /* WILL fit in 12 bits: OR into opcode and
1741 * overwrite the binary we already put out
1743 instr
.opcode
|= offs (expr
);
1744 md_number_to_chars (outP
, instr
.opcode
, 4);
1749 case SEG_DIFFERENCE
:
1754 if (instr
.disp
== 12)
1756 /* Displacement is dependent on a symbol, whose value
1757 * may change at link time. We HAVE to reserve 32 bits.
1758 * Convert already-output opcode to MEMB format.
1760 mema_to_memb (outP
);
1763 /* Output 0 displacement and set up address fixup for when
1764 * this symbol's value becomes known.
1766 outP
= emit ((long) 0);
1767 fixP
= fix_new (frag_now
,
1768 outP
- frag_now
->fr_literal
,
1775 fixP
->fx_im_disp
= 2; /* 32-bit displacement fix */
1776 fixP
->fx_bsr
= callx
; /*SAC LD RELAX HACK *//* Mark reloc as being in i stream */
1780 BAD_CASE (segs (expr
));
1786 /*****************************************************************************
1787 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1789 * There are 2 possible MEMA formats:
1790 * - displacement only
1791 * - displacement + abase
1793 * They are distinguished by the setting of the MEMA_ABASE bit.
1795 **************************************************************************** */
1797 mema_to_memb (opcodeP
)
1798 char *opcodeP
; /* Where to find the opcode, in target byte order */
1800 long opcode
; /* Opcode in host byte order */
1801 long mode
; /* Mode bits for MEMB instruction */
1803 opcode
= md_chars_to_number (opcodeP
, 4);
1804 know (!(opcode
& MEMB_BIT
));
1806 mode
= MEMB_BIT
| D_BIT
;
1807 if (opcode
& MEMA_ABASE
)
1812 opcode
&= 0xffffc000; /* Clear MEMA offset and mode bits */
1813 opcode
|= mode
; /* Set MEMB mode bits */
1815 md_number_to_chars (opcodeP
, opcode
, 4);
1816 } /* mema_to_memb() */
1819 /*****************************************************************************
1820 * parse_expr: parse an expression
1822 * Use base assembler's expression parser to parse an expression.
1823 * It, unfortunately, runs off a global which we have to save/restore
1824 * in order to make it work for us.
1826 * An empty expression string is treated as an absolute 0.
1828 * Return "segment" to which the expression evaluates.
1829 * Return SEG_GOOF regardless of expression evaluation if entire input
1830 * string is not consumed in the evaluation -- tolerate no dangling junk!
1832 **************************************************************************** */
1835 parse_expr (textP
, expP
)
1836 char *textP
; /* Text of expression to be parsed */
1837 expressionS
*expP
; /* Where to put the results of parsing */
1839 char *save_in
; /* Save global here */
1840 segT seg
; /* Segment to which expression evaluates */
1847 /* Treat empty string as absolute 0 */
1848 expP
->X_add_symbol
= expP
->X_subtract_symbol
= NULL
;
1849 expP
->X_add_number
= 0;
1850 seg
= expP
->X_seg
= SEG_ABSOLUTE
;
1855 save_in
= input_line_pointer
; /* Save global */
1856 input_line_pointer
= textP
; /* Make parser work for us */
1858 seg
= expression (expP
);
1859 if (input_line_pointer
- textP
!= strlen (textP
))
1861 /* Did not consume all of the input */
1864 symP
= expP
->X_add_symbol
;
1865 if (symP
&& (hash_find (reg_hash
, S_GET_NAME (symP
))))
1867 /* Register name in an expression */
1871 input_line_pointer
= save_in
; /* Restore global */
1877 /*****************************************************************************
1879 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1880 * i80960 instruction.
1882 * Assumes the input consists of:
1883 * arg[0] opcode mnemonic ('ldconst')
1884 * arg[1] first operand (constant)
1885 * arg[2] name of register to be loaded
1887 * Replaces opcode and/or operands as appropriate.
1889 * Returns the new number of arguments, or -1 on failure.
1891 **************************************************************************** */
1895 char *arg
[]; /* See above */
1897 int n
; /* Constant to be loaded */
1898 int shift
; /* Shift count for "shlo" instruction */
1899 static char buf
[5]; /* Literal for first operand */
1900 static char buf2
[5]; /* Literal for second operand */
1901 expressionS e
; /* Parsed expression */
1904 arg
[3] = NULL
; /* So we can tell at the end if it got used or not */
1906 switch (parse_expr (arg
[1], &e
))
1913 case SEG_DIFFERENCE
:
1914 /* We're dependent on one or more symbols -- use "lda" */
1919 /* Try the following mappings:
1920 * ldconst 0,<reg> ->mov 0,<reg>
1921 * ldconst 31,<reg> ->mov 31,<reg>
1922 * ldconst 32,<reg> ->addo 1,31,<reg>
1923 * ldconst 62,<reg> ->addo 31,31,<reg>
1924 * ldconst 64,<reg> ->shlo 8,3,<reg>
1925 * ldconst -1,<reg> ->subo 1,0,<reg>
1926 * ldconst -31,<reg>->subo 31,0,<reg>
1928 * anthing else becomes:
1932 if ((0 <= n
) && (n
<= 31))
1937 else if ((-31 <= n
) && (n
<= -1))
1941 sprintf (buf
, "%d", -n
);
1946 else if ((32 <= n
) && (n
<= 62))
1951 sprintf (buf
, "%d", n
- 31);
1955 else if ((shift
= shift_ok (n
)) != 0)
1959 sprintf (buf
, "%d", shift
);
1961 sprintf (buf2
, "%d", n
>> shift
);
1972 as_bad ("invalid constant");
1976 return (arg
[3] == 0) ? 2 : 3;
1979 /*****************************************************************************
1980 * parse_memop: parse a memory operand
1982 * This routine is based on the observation that the 4 mode bits of the
1983 * MEMB format, taken individually, have fairly consistent meaning:
1985 * M3 (bit 13): 1 if displacement is present (D_BIT)
1986 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1987 * M1 (bit 11): 1 if index is present (I_BIT)
1988 * M0 (bit 10): 1 if abase is present (A_BIT)
1990 * So we parse the memory operand and set bits in the mode as we find
1991 * things. Then at the end, if we go to MEMB format, we need only set
1992 * the MEMB bit (M2) and our mode is built for us.
1994 * Unfortunately, I said "fairly consistent". The exceptions:
1997 * 0100 Would seem illegal, but means "abase-only".
1999 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
2000 * Must be converted to 0100.
2002 * 0110 Would seem to mean "index-only", but is reserved.
2003 * We turn on the D bit and provide a 0 displacement.
2005 * The other thing to observe is that we parse from the right, peeling
2006 * things * off as we go: first any index spec, then any abase, then
2009 **************************************************************************** */
2012 parse_memop (memP
, argP
, optype
)
2013 memS
*memP
; /* Where to put the results */
2014 char *argP
; /* Text of the operand to be parsed */
2015 int optype
; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
2017 char *indexP
; /* Pointer to index specification with "[]" removed */
2018 char *p
; /* Temp char pointer */
2019 char iprel_flag
; /* True if this is an IP-relative operand */
2020 int regnum
; /* Register number */
2021 int scale
; /* Scale factor: 1,2,4,8, or 16. Later converted
2022 * to internal format (0,1,2,3,4 respectively).
2024 int mode
; /* MEMB mode bits */
2025 int *intP
; /* Pointer to register number */
2027 /* The following table contains the default scale factors for each
2028 * type of memory instruction. It is accessed using (optype-MEM1)
2029 * as an index -- thus it assumes the 'optype' constants are assigned
2030 * consecutive values, in the order they appear in this table
2032 static int def_scale
[] =
2038 -1, /* MEM12 -- no valid default */
2043 iprel_flag
= mode
= 0;
2045 /* Any index present? */
2046 indexP
= get_ispec (argP
);
2049 p
= strchr (indexP
, '*');
2052 /* No explicit scale -- use default for this
2055 scale
= def_scale
[optype
- MEM1
];
2059 *p
++ = '\0'; /* Eliminate '*' */
2061 /* Now indexP->a '\0'-terminated register name,
2062 * and p->a scale factor.
2065 if (!strcmp (p
, "16"))
2069 else if (strchr ("1248", *p
) && (p
[1] == '\0'))
2079 regnum
= get_regnum (indexP
); /* Get index reg. # */
2080 if (!IS_RG_REG (regnum
))
2082 as_bad ("invalid index register");
2086 /* Convert scale to its binary encoding */
2105 as_bad ("invalid scale factor");
2109 memP
->opcode
|= scale
| regnum
; /* Set index bits in opcode */
2110 mode
|= I_BIT
; /* Found a valid index spec */
2113 /* Any abase (Register Indirect) specification present? */
2114 if ((p
= strrchr (argP
, '(')) != NULL
)
2116 /* "(" is there -- does it start a legal abase spec?
2117 * (If not it could be part of a displacement expression.)
2119 intP
= (int *) hash_find (areg_hash
, p
);
2122 /* Got an abase here */
2124 *p
= '\0'; /* discard register spec */
2125 if (regnum
== IPREL
)
2127 /* We have to specialcase ip-rel mode */
2132 memP
->opcode
|= regnum
<< 14;
2138 /* Any expression present? */
2145 /* Special-case ip-relative addressing */
2154 memP
->opcode
|= 5 << 10; /* IP-relative mode */
2160 /* Handle all other modes */
2164 /* Go with MEMA instruction format for now (grow to MEMB later
2165 * if 12 bits is not enough for the displacement).
2166 * MEMA format has a single mode bit: set it to indicate
2167 * that abase is present.
2169 memP
->opcode
|= MEMA_ABASE
;
2174 /* Go with MEMA instruction format for now (grow to MEMB later
2175 * if 12 bits is not enough for the displacement).
2181 /* For some reason, the bit string for this mode is not
2182 * consistent: it should be 0 (exclusive of the MEMB bit),
2183 * so we set it "by hand" here.
2185 memP
->opcode
|= MEMB_BIT
;
2189 /* set MEMB bit in mode, and OR in mode bits */
2190 memP
->opcode
|= mode
| MEMB_BIT
;
2194 /* Treat missing displacement as displacement of 0 */
2196 /***********************
2197 * Fall into next case *
2198 ********************** */
2199 case D_BIT
| A_BIT
| I_BIT
:
2201 /* set MEMB bit in mode, and OR in mode bits */
2202 memP
->opcode
|= mode
| MEMB_BIT
;
2212 /*****************************************************************************
2213 * parse_po: parse machine-dependent pseudo-op
2215 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
2216 * up the rest of the input line, breaks out the individual arguments,
2217 * and dispatches them to the correct handler.
2218 **************************************************************************** */
2222 int po_num
; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2224 char *args
[4]; /* Pointers operands, with no embedded whitespace.
2226 * arg[1-3]->operands
2228 int n_ops
; /* Number of operands */
2229 char *p
; /* Pointer to beginning of unparsed argument string */
2230 char eol
; /* Character that indicated end of line */
2232 extern char is_end_of_line
[];
2234 /* Advance input pointer to end of line. */
2235 p
= input_line_pointer
;
2236 while (!is_end_of_line
[*input_line_pointer
])
2238 input_line_pointer
++;
2240 eol
= *input_line_pointer
; /* Save end-of-line char */
2241 *input_line_pointer
= '\0'; /* Terminate argument list */
2243 /* Parse out operands */
2244 n_ops
= get_args (p
, args
);
2250 /* Dispatch to correct handler */
2254 s_sysproc (n_ops
, args
);
2257 s_leafproc (n_ops
, args
);
2264 /* Restore eol, so line numbers get updated correctly. Base assembler
2265 * assumes we leave input pointer pointing at char following the eol.
2267 *input_line_pointer
++ = eol
;
2270 /*****************************************************************************
2271 * parse_regop: parse a register operand.
2273 * In case of illegal operand, issue a message and return some valid
2274 * information so instruction processing can continue.
2275 **************************************************************************** */
2278 parse_regop (regopP
, optext
, opdesc
)
2279 struct regop
*regopP
; /* Where to put description of register operand */
2280 char *optext
; /* Text of operand */
2281 char opdesc
; /* Descriptor byte: what's legal for this operand */
2283 int n
; /* Register number */
2284 expressionS e
; /* Parsed expression */
2286 /* See if operand is a register */
2287 n
= get_regnum (optext
);
2292 /* global or local register */
2293 if (!REG_ALIGN (opdesc
, n
))
2295 as_bad ("unaligned register");
2299 regopP
->special
= 0;
2302 else if (IS_FP_REG (n
) && FP_OK (opdesc
))
2304 /* Floating point register, and it's allowed */
2305 regopP
->n
= n
- FP0
;
2307 regopP
->special
= 0;
2310 else if (IS_SF_REG (n
) && SFR_OK (opdesc
))
2312 /* Special-function register, and it's allowed */
2313 regopP
->n
= n
- SF0
;
2315 regopP
->special
= 1;
2316 if (!targ_has_sfr (regopP
->n
))
2318 as_bad ("no such sfr in this architecture");
2323 else if (LIT_OK (opdesc
))
2326 * How about a literal?
2329 regopP
->special
= 0;
2331 { /* floating point literal acceptable */
2332 /* Skip over 0f, 0d, or 0e prefix */
2333 if ((optext
[0] == '0')
2334 && (optext
[1] >= 'd')
2335 && (optext
[1] <= 'f'))
2340 if (!strcmp (optext
, "0.0") || !strcmp (optext
, "0"))
2345 if (!strcmp (optext
, "1.0") || !strcmp (optext
, "1"))
2353 { /* fixed point literal acceptable */
2354 if ((parse_expr (optext
, &e
) != SEG_ABSOLUTE
)
2355 || (offs (e
) < 0) || (offs (e
) > 31))
2357 as_bad ("illegal literal");
2360 regopP
->n
= offs (e
);
2365 /* Nothing worked */
2367 regopP
->mode
= 0; /* Register r0 is always a good one */
2369 regopP
->special
= 0;
2370 } /* parse_regop() */
2372 /*****************************************************************************
2373 * reg_fmt: generate a REG-format instruction
2375 **************************************************************************** */
2378 char *args
[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2379 struct i960_opcode
*oP
; /* Pointer to description of instruction */
2381 long instr
; /* Binary to be output */
2382 struct regop regop
; /* Description of register operand */
2383 int n_ops
; /* Number of operands */
2387 n_ops
= oP
->num_ops
;
2391 parse_regop (®op
, args
[1], oP
->operand
[0]);
2393 if ((n_ops
== 1) && !(instr
& M3
))
2395 /* 1-operand instruction in which the dst field should
2396 * be used (instead of src1).
2401 regop
.mode
= regop
.special
;
2408 /* regop.n goes in bit 0, needs no shifting */
2410 regop
.special
<<= 5;
2412 instr
|= regop
.n
| regop
.mode
| regop
.special
;
2417 parse_regop (®op
, args
[2], oP
->operand
[1]);
2419 if ((n_ops
== 2) && !(instr
& M3
))
2421 /* 2-operand instruction in which the dst field should
2422 * be used instead of src2).
2427 regop
.mode
= regop
.special
;
2436 regop
.special
<<= 6;
2438 instr
|= regop
.n
| regop
.mode
| regop
.special
;
2442 parse_regop (®op
, args
[3], oP
->operand
[2]);
2445 regop
.mode
= regop
.special
;
2447 instr
|= (regop
.n
<<= 19) | (regop
.mode
<<= 13);
2453 /*****************************************************************************
2455 * Replace cobr instruction in a code fragment with equivalent branch and
2456 * compare instructions, so it can reach beyond a 13-bit displacement.
2457 * Set up an address fix/relocation for the new branch instruction.
2459 **************************************************************************** */
2461 /* This "conditional jump" table maps cobr instructions into equivalent
2462 * compare and branch opcodes.
2472 { /* COBR OPCODE: */
2473 CHKBIT
, BNO
, /* 0x30 - bbc */
2474 CMPO
, BG
, /* 0x31 - cmpobg */
2475 CMPO
, BE
, /* 0x32 - cmpobe */
2476 CMPO
, BGE
, /* 0x33 - cmpobge */
2477 CMPO
, BL
, /* 0x34 - cmpobl */
2478 CMPO
, BNE
, /* 0x35 - cmpobne */
2479 CMPO
, BLE
, /* 0x36 - cmpoble */
2480 CHKBIT
, BO
, /* 0x37 - bbs */
2481 CMPI
, BNO
, /* 0x38 - cmpibno */
2482 CMPI
, BG
, /* 0x39 - cmpibg */
2483 CMPI
, BE
, /* 0x3a - cmpibe */
2484 CMPI
, BGE
, /* 0x3b - cmpibge */
2485 CMPI
, BL
, /* 0x3c - cmpibl */
2486 CMPI
, BNE
, /* 0x3d - cmpibne */
2487 CMPI
, BLE
, /* 0x3e - cmpible */
2488 CMPI
, BO
, /* 0x3f - cmpibo */
2494 register fragS
*fragP
; /* fragP->fr_opcode is assumed to point to
2495 * the cobr instruction, which comes at the
2496 * end of the code fragment.
2499 int opcode
, src1
, src2
, m1
, s2
;
2500 /* Bit fields from cobr instruction */
2501 long bp_bits
; /* Branch prediction bits from cobr instruction */
2502 long instr
; /* A single i960 instruction */
2503 char *iP
; /*->instruction to be replaced */
2504 fixS
*fixP
; /* Relocation that can be done at assembly time */
2506 /* PICK UP & PARSE COBR INSTRUCTION */
2507 iP
= fragP
->fr_opcode
;
2508 instr
= md_chars_to_number (iP
, 4);
2509 opcode
= ((instr
>> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2510 src1
= (instr
>> 19) & 0x1f;
2511 m1
= (instr
>> 13) & 1;
2513 src2
= (instr
>> 14) & 0x1f;
2514 bp_bits
= instr
& BP_MASK
;
2516 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2517 instr
= coj
[opcode
].compare
2518 | src1
| (m1
<< 11) | (s2
<< 6) | (src2
<< 14);
2519 md_number_to_chars (iP
, instr
, 4);
2521 /* OUTPUT BRANCH INSTRUCTION */
2522 md_number_to_chars (iP
+ 4, coj
[opcode
].branch
| bp_bits
, 4);
2524 /* SET UP ADDRESS FIXUP/RELOCATION */
2525 fixP
= fix_new (fragP
,
2526 iP
+ 4 - fragP
->fr_literal
,
2534 fixP
->fx_bit_fixP
= (bit_fixS
*) 24; /* Store size of bit field */
2541 /*****************************************************************************
2542 * reloc_callj: Relocate a 'callj' instruction
2544 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2545 * assembler calls it when it decides it can relocate an address at
2546 * assembly time instead of emitting a relocation directive.
2548 * Check to see if the relocation involves a 'callj' instruction to a:
2549 * sysproc: Replace the default 'call' instruction with a 'calls'
2550 * leafproc: Replace the default 'call' instruction with a 'bal'.
2551 * other proc: Do nothing.
2553 * See b.out.h for details on the 'n_other' field in a symbol structure.
2556 * Assumes the caller has already figured out, in the case of a leafproc,
2557 * to use the 'bal' entry point, and has substituted that symbol into the
2558 * passed fixup structure.
2560 **************************************************************************** */
2563 fixS
*fixP
; /* Relocation that can be done at assembly time */
2565 char *where
; /*->the binary for the instruction being relocated */
2567 if (!fixP
->fx_callj
)
2570 } /* This wasn't a callj instruction in the first place */
2572 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2574 if (TC_S_IS_SYSPROC (fixP
->fx_addsy
))
2576 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2577 * System procedure number is (other-1).
2579 md_number_to_chars (where
, CALLS
| TC_S_GET_SYSPROC (fixP
->fx_addsy
), 4);
2581 /* Nothing else needs to be done for this instruction.
2582 * Make sure 'md_number_to_field()' will perform a no-op.
2584 fixP
->fx_bit_fixP
= (bit_fixS
*) 1;
2587 else if (TC_S_IS_CALLNAME (fixP
->fx_addsy
))
2589 /* Should not happen: see block comment above */
2590 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP
->fx_addsy
));
2593 else if (TC_S_IS_BALNAME (fixP
->fx_addsy
))
2595 /* Replace 'call' with 'bal'; both instructions have
2596 * the same format, so calling code should complete
2597 * relocation as if nothing happened here.
2599 md_number_to_chars (where
, BAL
, 4);
2601 else if (TC_S_IS_BADPROC (fixP
->fx_addsy
))
2603 as_bad ("Looks like a proc, but can't tell what kind.\n");
2604 } /* switch on proc type */
2606 /* else Symbol is neither a sysproc nor a leafproc */
2609 } /* reloc_callj() */
2612 /*****************************************************************************
2613 * s_leafproc: process .leafproc pseudo-op
2615 * .leafproc takes two arguments, the second one is optional:
2616 * arg[1]: name of 'call' entry point to leaf procedure
2617 * arg[2]: name of 'bal' entry point to leaf procedure
2619 * If the two arguments are identical, or if the second one is missing,
2620 * the first argument is taken to be the 'bal' entry point.
2622 * If there are 2 distinct arguments, we must make sure that the 'bal'
2623 * entry point immediately follows the 'call' entry point in the linked
2626 **************************************************************************** */
2628 s_leafproc (n_ops
, args
)
2629 int n_ops
; /* Number of operands */
2630 char *args
[]; /* args[1]->1st operand, args[2]->2nd operand */
2632 symbolS
*callP
; /* Pointer to leafproc 'call' entry point symbol */
2633 symbolS
*balP
; /* Pointer to leafproc 'bal' entry point symbol */
2635 if ((n_ops
!= 1) && (n_ops
!= 2))
2637 as_bad ("should have 1 or 2 operands");
2639 } /* Check number of arguments */
2641 /* Find or create symbol for 'call' entry point. */
2642 callP
= symbol_find_or_make (args
[1]);
2644 if (TC_S_IS_CALLNAME (callP
))
2646 as_warn ("Redefining leafproc %s", S_GET_NAME (callP
));
2649 /* If that was the only argument, use it as the 'bal' entry point.
2650 * Otherwise, mark it as the 'call' entry point and find or create
2651 * another symbol for the 'bal' entry point.
2653 if ((n_ops
== 1) || !strcmp (args
[1], args
[2]))
2655 TC_S_FORCE_TO_BALNAME (callP
);
2660 TC_S_FORCE_TO_CALLNAME (callP
);
2662 balP
= symbol_find_or_make (args
[2]);
2663 if (TC_S_IS_CALLNAME (balP
))
2665 as_warn ("Redefining leafproc %s", S_GET_NAME (balP
));
2667 TC_S_FORCE_TO_BALNAME (balP
);
2669 tc_set_bal_of_call (callP
, balP
);
2670 } /* if only one arg, or the args are the same */
2673 } /* s_leafproc() */
2677 * s_sysproc: process .sysproc pseudo-op
2679 * .sysproc takes two arguments:
2680 * arg[1]: name of entry point to system procedure
2681 * arg[2]: 'entry_num' (index) of system procedure in the range
2684 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2685 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2686 * by adding 1 to it. It must be unbiased before it is used.
2689 s_sysproc (n_ops
, args
)
2690 int n_ops
; /* Number of operands */
2691 char *args
[]; /* args[1]->1st operand, args[2]->2nd operand */
2698 as_bad ("should have two operands");
2700 } /* bad arg count */
2702 /* Parse "entry_num" argument and check it for validity. */
2703 if ((parse_expr (args
[2], &exp
) != SEG_ABSOLUTE
)
2705 || (offs (exp
) > 31))
2707 as_bad ("'entry_num' must be absolute number in [0,31]");
2711 /* Find/make symbol and stick entry number (biased by +1) into it */
2712 symP
= symbol_find_or_make (args
[1]);
2714 if (TC_S_IS_SYSPROC (symP
))
2716 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP
));
2719 TC_S_SET_SYSPROC (symP
, offs (exp
)); /* encode entry number */
2720 TC_S_FORCE_TO_SYSPROC (symP
);
2726 /*****************************************************************************
2728 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2729 * This means that some number X < 32 can be shifted left to produce the
2730 * constant of interest.
2732 * Return the shift count, or 0 if we can't do it.
2733 * Caller calculates X by shifting original constant right 'shift' places.
2735 **************************************************************************** */
2739 int n
; /* The constant of interest */
2741 int shift
; /* The shift count */
2745 /* Can't do it for negative numbers */
2749 /* Shift 'n' right until a 1 is about to be lost */
2750 for (shift
= 0; (n
& 1) == 0; shift
++)
2763 /*****************************************************************************
2764 * syntax: issue syntax error
2766 **************************************************************************** */
2770 as_bad ("syntax error");
2774 /*****************************************************************************
2776 * Return TRUE iff the target architecture supports the specified
2777 * special-function register (sfr).
2779 **************************************************************************** */
2783 int n
; /* Number (0-31) of sfr */
2785 switch (architecture
)
2793 return ((0 <= n
) && (n
<= 2));
2798 /*****************************************************************************
2800 * Return TRUE iff the target architecture supports the indicated
2801 * class of instructions.
2803 **************************************************************************** */
2806 targ_has_iclass (ic
)
2807 int ic
; /* Instruction class; one of:
2808 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2811 iclasses_seen
|= ic
;
2812 switch (architecture
)
2815 return ic
& (I_BASE
| I_KX
);
2817 return ic
& (I_BASE
| I_KX
| I_FP
| I_DEC
);
2819 return ic
& (I_BASE
| I_KX
| I_FP
| I_DEC
| I_MIL
);
2821 return ic
& (I_BASE
| I_CX
| I_CASIM
);
2823 if ((iclasses_seen
& (I_KX
| I_FP
| I_DEC
| I_MIL
))
2824 && (iclasses_seen
& I_CX
))
2826 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2827 iclasses_seen
&= ~ic
;
2834 /* Parse an operand that is machine-specific.
2835 We just return without modifying the expression if we have nothing
2840 md_operand (expressionP
)
2841 expressionS
*expressionP
;
2845 /* We have no need to default values of symbols. */
2849 md_undefined_symbol (name
)
2853 } /* md_undefined_symbol() */
2855 /* Exactly what point is a PC-relative offset relative TO?
2856 On the i960, they're relative to the address of the instruction,
2857 which we have set up as the address of the fixup too. */
2859 md_pcrel_from (fixP
)
2862 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2866 md_apply_fix (fixP
, val
)
2870 char *place
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2872 if (!fixP
->fx_bit_fixP
)
2875 switch (fixP
->fx_im_disp
)
2878 fixP
->fx_addnumber
= val
;
2879 md_number_to_imm (place
, val
, fixP
->fx_size
, fixP
);
2882 md_number_to_disp (place
,
2883 fixP
->fx_pcrel
? val
+ fixP
->fx_pcrel_adjust
: val
,
2886 case 2: /* fix requested for .long .word etc */
2887 md_number_to_chars (place
, val
, fixP
->fx_size
);
2890 as_fatal ("Internal error in md_apply_fix() in file \"%s\"", __FILE__
);
2891 } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */
2895 md_number_to_field (place
, val
, fixP
->fx_bit_fixP
);
2899 } /* md_apply_fix() */
2901 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2903 tc_bout_fix_to_chars (where
, fixP
, segment_address_in_file
)
2906 relax_addressT segment_address_in_file
;
2908 static unsigned char nbytes_r_length
[] =
2910 struct relocation_info ri
;
2913 /* JF this is for paranoia */
2914 memset ((char *) &ri
, '\0', sizeof (ri
));
2915 symbolP
= fixP
->fx_addsy
;
2916 know (symbolP
!= 0 || fixP
->fx_r_type
!= NO_RELOC
);
2917 ri
.r_bsr
= fixP
->fx_bsr
; /*SAC LD RELAX HACK */
2918 /* These two 'cuz of NS32K */
2919 ri
.r_callj
= fixP
->fx_callj
;
2920 if (fixP
->fx_bit_fixP
)
2926 ri
.r_length
= nbytes_r_length
[fixP
->fx_size
];
2928 ri
.r_pcrel
= fixP
->fx_pcrel
;
2929 ri
.r_address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
;
2931 if (fixP
->fx_r_type
!= NO_RELOC
)
2933 switch (fixP
->fx_r_type
)
2938 ri
.r_length
= fixP
->fx_size
- 1;
2952 else if (linkrelax
|| !S_IS_DEFINED (symbolP
))
2955 ri
.r_index
= symbolP
->sy_number
;
2960 ri
.r_index
= S_GET_TYPE (symbolP
);
2963 /* Output the relocation information in machine-dependent form. */
2964 md_ri_to_chars (where
, &ri
);
2967 } /* tc_bout_fix_to_chars() */
2969 #endif /* OBJ_AOUT or OBJ_BOUT */
2971 /* Align an address by rounding it up to the specified boundary.
2974 md_section_align (seg
, addr
)
2976 long addr
; /* Address to be rounded up */
2978 return ((addr
+ (1 << section_alignment
[(int) seg
]) - 1) & (-1 << section_alignment
[(int) seg
]));
2979 } /* md_section_align() */
2983 tc_headers_hook (headers
)
2984 object_headers
*headers
;
2986 /* FIXME: remove this line *//* unsigned short arch_flag = 0; */
2988 if (iclasses_seen
== I_BASE
)
2990 headers
->filehdr
.f_flags
|= F_I960CORE
;
2992 else if (iclasses_seen
& I_CX
)
2994 headers
->filehdr
.f_flags
|= F_I960CA
;
2996 else if (iclasses_seen
& I_MIL
)
2998 headers
->filehdr
.f_flags
|= F_I960MC
;
3000 else if (iclasses_seen
& (I_DEC
| I_FP
))
3002 headers
->filehdr
.f_flags
|= F_I960KB
;
3006 headers
->filehdr
.f_flags
|= F_I960KA
;
3007 } /* set arch flag */
3011 headers
->filehdr
.f_magic
= I960RWMAGIC
;
3012 headers
->aouthdr
.magic
= OMAGIC
;
3016 headers
->filehdr
.f_magic
= I960ROMAGIC
;
3017 headers
->aouthdr
.magic
= NMAGIC
;
3018 } /* set magic numbers */
3021 } /* tc_headers_hook() */
3023 #endif /* OBJ_COFF */
3026 * Things going on here:
3028 * For bout, We need to assure a couple of simplifying
3029 * assumptions about leafprocs for the linker: the leafproc
3030 * entry symbols will be defined in the same assembly in
3031 * which they're declared with the '.leafproc' directive;
3032 * and if a leafproc has both 'call' and 'bal' entry points
3033 * they are both global or both local.
3035 * For coff, the call symbol has a second aux entry that
3036 * contains the bal entry point. The bal symbol becomes a
3039 * For coff representation, the call symbol has a second aux entry that
3040 * contains the bal entry point. The bal symbol becomes a label.
3045 tc_crawl_symbol_chain (headers
)
3046 object_headers
*headers
;
3050 for (symbolP
= symbol_rootP
; symbolP
; symbolP
= symbol_next (symbolP
))
3053 if (TC_S_IS_SYSPROC (symbolP
))
3055 /* second aux entry already contains the sysproc number */
3056 S_SET_NUMBER_AUXILIARY (symbolP
, 2);
3057 S_SET_STORAGE_CLASS (symbolP
, C_SCALL
);
3058 S_SET_DATA_TYPE (symbolP
, S_GET_DATA_TYPE (symbolP
) | (DT_FCN
<< N_BTSHFT
));
3060 } /* rewrite sysproc */
3061 #endif /* OBJ_COFF */
3063 if (!TC_S_IS_BALNAME (symbolP
) && !TC_S_IS_CALLNAME (symbolP
))
3066 } /* Not a leafproc symbol */
3068 if (!S_IS_DEFINED (symbolP
))
3070 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP
));
3071 } /* undefined leaf */
3073 if (TC_S_IS_CALLNAME (symbolP
))
3075 symbolS
*balP
= tc_get_bal_of_call (symbolP
);
3076 if (S_IS_EXTERNAL (symbolP
) != S_IS_EXTERNAL (balP
))
3078 S_SET_EXTERNAL (symbolP
);
3079 S_SET_EXTERNAL (balP
);
3080 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3081 S_GET_NAME (symbolP
), S_GET_NAME (balP
));
3082 } /* externality mismatch */
3084 } /* walk the symbol chain */
3087 } /* tc_crawl_symbol_chain() */
3090 * For aout or bout, the bal immediately follows the call.
3092 * For coff, we cheat and store a pointer to the bal symbol
3093 * in the second aux entry of the call.
3105 tc_set_bal_of_call (callP
, balP
)
3109 know (TC_S_IS_CALLNAME (callP
));
3110 know (TC_S_IS_BALNAME (balP
));
3114 callP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
= (int) balP
;
3115 S_SET_NUMBER_AUXILIARY (callP
, 2);
3117 #else /* ! OBJ_COFF */
3120 /* If the 'bal' entry doesn't immediately follow the 'call'
3121 * symbol, unlink it from the symbol list and re-insert it.
3123 if (symbol_next (callP
) != balP
)
3125 symbol_remove (balP
, &symbol_rootP
, &symbol_lastP
);
3126 symbol_append (balP
, callP
, &symbol_rootP
, &symbol_lastP
);
3127 } /* if not in order */
3129 #else /* ! OBJ_ABOUT */
3130 (as yet unwritten
.);
3131 #endif /* ! OBJ_ABOUT */
3132 #endif /* ! OBJ_COFF */
3135 } /* tc_set_bal_of_call() */
3138 _tc_get_bal_of_call (callP
)
3143 know (TC_S_IS_CALLNAME (callP
));
3146 retval
= (symbolS
*) (callP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
);
3149 retval
= symbol_next (callP
);
3151 (as yet unwritten
.);
3152 #endif /* ! OBJ_ABOUT */
3153 #endif /* ! OBJ_COFF */
3155 know (TC_S_IS_BALNAME (retval
));
3156 return ((char *) retval
);
3157 } /* _tc_get_bal_of_call() */
3160 tc_coff_symbol_emit_hook (symbolP
)
3163 if (TC_S_IS_CALLNAME (symbolP
))
3166 symbolS
*balP
= tc_get_bal_of_call (symbolP
);
3168 /* second aux entry contains the bal entry point */
3169 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
3170 symbolP
->sy_symbol
.ost_auxent
[1].x_bal
.x_balntry
= S_GET_VALUE (balP
);
3171 S_SET_STORAGE_CLASS (symbolP
, (!SF_GET_LOCAL (symbolP
) ? C_LEAFEXT
: C_LEAFSTAT
));
3172 S_SET_DATA_TYPE (symbolP
, S_GET_DATA_TYPE (symbolP
) | (DT_FCN
<< N_BTSHFT
));
3173 /* fix up the bal symbol */
3174 S_SET_STORAGE_CLASS (balP
, C_LABEL
);
3175 #endif /* OBJ_COFF */
3176 } /* only on calls */
3179 } /* tc_coff_symbol_emit_hook() */
3182 i960_handle_align (fragp
)
3186 segT old_seg
= now_seg
, this_seg
;
3187 int old_subseg
= now_subseg
;
3189 extern struct frag
*text_last_frag
, *data_last_frag
;
3194 /* The text section "ends" with another alignment reloc, to which we
3195 aren't adding padding. */
3196 if (fragp
->fr_next
== text_last_frag
3197 || fragp
->fr_next
== data_last_frag
)
3202 /* alignment directive */
3203 fixp
= fix_new (fragp
, fragp
->fr_fix
, fragp
->fr_offset
, 0, 0, 0, 0,
3204 (int) fragp
->fr_type
);
3214 /* end of tc-i960.c */