1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "m:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct label_fix
*tag_fixups
;
223 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
226 unsigned int src_line
;
227 struct dwarf2_line_info debug_line
;
235 struct dynreg
*next
; /* next dynamic register */
237 unsigned short base
; /* the base register number */
238 unsigned short num_regs
; /* # of registers in this set */
240 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
242 flagword flags
; /* ELF-header flags */
245 unsigned hint
:1; /* is this hint currently valid? */
246 bfd_vma offset
; /* mem.offset offset */
247 bfd_vma base
; /* mem.offset base */
250 int path
; /* number of alt. entry points seen */
251 const char **entry_labels
; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths
; /* size currently allocated for
255 /* Support for hardware errata workarounds. */
257 /* Record data about the last three insn groups. */
260 /* B-step workaround.
261 For each predicate register, this is set if the corresponding insn
262 group conditionally sets this register with one of the affected
265 /* B-step workaround.
266 For each general register, this is set if the corresponding insn
267 a) is conditional one one of the predicate registers for which
268 P_REG_SET is 1 in the corresponding entry of the previous group,
269 b) sets this general register with one of the affected
271 int g_reg_set_conditionally
[128];
277 /* application registers: */
283 #define AR_BSPSTORE 18
298 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
299 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
300 {"ar.rsc", 16}, {"ar.bsp", 17},
301 {"ar.bspstore", 18}, {"ar.rnat", 19},
302 {"ar.fcr", 21}, {"ar.eflag", 24},
303 {"ar.csd", 25}, {"ar.ssd", 26},
304 {"ar.cflg", 27}, {"ar.fsr", 28},
305 {"ar.fir", 29}, {"ar.fdr", 30},
306 {"ar.ccv", 32}, {"ar.unat", 36},
307 {"ar.fpsr", 40}, {"ar.itc", 44},
308 {"ar.pfs", 64}, {"ar.lc", 65},
329 /* control registers: */
371 static const struct const_desc
378 /* PSR constant masks: */
381 {"psr.be", ((valueT
) 1) << 1},
382 {"psr.up", ((valueT
) 1) << 2},
383 {"psr.ac", ((valueT
) 1) << 3},
384 {"psr.mfl", ((valueT
) 1) << 4},
385 {"psr.mfh", ((valueT
) 1) << 5},
387 {"psr.ic", ((valueT
) 1) << 13},
388 {"psr.i", ((valueT
) 1) << 14},
389 {"psr.pk", ((valueT
) 1) << 15},
391 {"psr.dt", ((valueT
) 1) << 17},
392 {"psr.dfl", ((valueT
) 1) << 18},
393 {"psr.dfh", ((valueT
) 1) << 19},
394 {"psr.sp", ((valueT
) 1) << 20},
395 {"psr.pp", ((valueT
) 1) << 21},
396 {"psr.di", ((valueT
) 1) << 22},
397 {"psr.si", ((valueT
) 1) << 23},
398 {"psr.db", ((valueT
) 1) << 24},
399 {"psr.lp", ((valueT
) 1) << 25},
400 {"psr.tb", ((valueT
) 1) << 26},
401 {"psr.rt", ((valueT
) 1) << 27},
402 /* 28-31: reserved */
403 /* 32-33: cpl (current privilege level) */
404 {"psr.is", ((valueT
) 1) << 34},
405 {"psr.mc", ((valueT
) 1) << 35},
406 {"psr.it", ((valueT
) 1) << 36},
407 {"psr.id", ((valueT
) 1) << 37},
408 {"psr.da", ((valueT
) 1) << 38},
409 {"psr.dd", ((valueT
) 1) << 39},
410 {"psr.ss", ((valueT
) 1) << 40},
411 /* 41-42: ri (restart instruction) */
412 {"psr.ed", ((valueT
) 1) << 43},
413 {"psr.bn", ((valueT
) 1) << 44},
416 /* indirect register-sets/memory: */
425 { "CPUID", IND_CPUID
},
426 { "cpuid", IND_CPUID
},
438 /* Pseudo functions used to indicate relocation types (these functions
439 start with an at sign (@). */
461 /* reloc pseudo functions (these must come first!): */
462 { "fptr", PSEUDO_FUNC_RELOC
},
463 { "gprel", PSEUDO_FUNC_RELOC
},
464 { "ltoff", PSEUDO_FUNC_RELOC
},
465 { "pcrel", PSEUDO_FUNC_RELOC
},
466 { "pltoff", PSEUDO_FUNC_RELOC
},
467 { "secrel", PSEUDO_FUNC_RELOC
},
468 { "segrel", PSEUDO_FUNC_RELOC
},
469 { "ltv", PSEUDO_FUNC_RELOC
},
470 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
472 /* mbtype4 constants: */
473 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
474 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
475 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
476 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
477 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
479 /* fclass constants: */
480 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
481 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
482 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
483 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
484 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
485 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
486 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
487 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
488 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
490 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
492 /* unwind-related constants: */
493 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
494 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
495 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
497 /* unwind-related registers: */
498 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
501 /* 41-bit nop opcodes (one per unit): */
502 static const bfd_vma nop
[IA64_NUM_UNITS
] =
504 0x0000000000LL
, /* NIL => break 0 */
505 0x0008000000LL
, /* I-unit nop */
506 0x0008000000LL
, /* M-unit nop */
507 0x4000000000LL
, /* B-unit nop */
508 0x0008000000LL
, /* F-unit nop */
509 0x0008000000LL
, /* L-"unit" nop */
510 0x0008000000LL
, /* X-unit nop */
513 /* Can't be `const' as it's passed to input routines (which have the
514 habit of setting temporary sentinels. */
515 static char special_section_name
[][20] =
517 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
518 {".IA_64.unwind"}, {".IA_64.unwind_info"}
521 /* The best template for a particular sequence of up to three
523 #define N IA64_NUM_TYPES
524 static unsigned char best_template
[N
][N
][N
];
527 /* Resource dependencies currently in effect */
529 int depind
; /* dependency index */
530 const struct ia64_dependency
*dependency
; /* actual dependency */
531 unsigned specific
:1, /* is this a specific bit/regno? */
532 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
533 int index
; /* specific regno/bit within dependency */
534 int note
; /* optional qualifying note (0 if none) */
538 int insn_srlz
; /* current insn serialization state */
539 int data_srlz
; /* current data serialization state */
540 int qp_regno
; /* qualifying predicate for this usage */
541 char *file
; /* what file marked this dependency */
542 int line
; /* what line marked this dependency */
543 struct mem_offset mem_offset
; /* optional memory offset hint */
544 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
545 int path
; /* corresponding code entry index */
547 static int regdepslen
= 0;
548 static int regdepstotlen
= 0;
549 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
550 static const char *dv_sem
[] = { "none", "implied", "impliedf",
551 "data", "instr", "specific", "stop", "other" };
552 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
554 /* Current state of PR mutexation */
555 static struct qpmutex
{
558 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
559 static int qp_mutexeslen
= 0;
560 static int qp_mutexestotlen
= 0;
561 static valueT qp_safe_across_calls
= 0;
563 /* Current state of PR implications */
564 static struct qp_imply
{
567 unsigned p2_branched
:1;
569 } *qp_implies
= NULL
;
570 static int qp_implieslen
= 0;
571 static int qp_impliestotlen
= 0;
573 /* Keep track of static GR values so that indirect register usage can
574 sometimes be tracked. */
579 } gr_values
[128] = {{ 1, 0 }};
581 /* These are the routines required to output the various types of
584 /* A slot_number is a frag address plus the slot index (0-2). We use the
585 frag address here so that if there is a section switch in the middle of
586 a function, then instructions emitted to a different section are not
587 counted. Since there may be more than one frag for a function, this
588 means we also need to keep track of which frag this address belongs to
589 so we can compute inter-frag distances. This also nicely solves the
590 problem with nops emitted for align directives, which can't easily be
591 counted, but can easily be derived from frag sizes. */
593 typedef struct unw_rec_list
{
595 unsigned long slot_number
;
597 struct unw_rec_list
*next
;
600 #define SLOT_NUM_NOT_SET -1
604 unsigned long next_slot_number
;
605 fragS
*next_slot_frag
;
607 /* Maintain a list of unwind entries for the current function. */
611 /* Any unwind entires that should be attached to the current slot
612 that an insn is being constructed for. */
613 unw_rec_list
*current_entry
;
615 /* These are used to create the unwind table entry for this function. */
618 symbolS
*info
; /* pointer to unwind info */
619 symbolS
*personality_routine
;
621 /* TRUE if processing unwind directives in a prologue region. */
626 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
628 /* Forward delarations: */
629 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
630 static void set_section
PARAMS ((char *name
));
631 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
632 unsigned int, unsigned int));
633 static void dot_radix
PARAMS ((int));
634 static void dot_special_section
PARAMS ((int));
635 static void dot_proc
PARAMS ((int));
636 static void dot_fframe
PARAMS ((int));
637 static void dot_vframe
PARAMS ((int));
638 static void dot_vframesp
PARAMS ((int));
639 static void dot_vframepsp
PARAMS ((int));
640 static void dot_save
PARAMS ((int));
641 static void dot_restore
PARAMS ((int));
642 static void dot_restorereg
PARAMS ((int));
643 static void dot_restorereg_p
PARAMS ((int));
644 static void dot_handlerdata
PARAMS ((int));
645 static void dot_unwentry
PARAMS ((int));
646 static void dot_altrp
PARAMS ((int));
647 static void dot_savemem
PARAMS ((int));
648 static void dot_saveg
PARAMS ((int));
649 static void dot_savef
PARAMS ((int));
650 static void dot_saveb
PARAMS ((int));
651 static void dot_savegf
PARAMS ((int));
652 static void dot_spill
PARAMS ((int));
653 static void dot_spillreg
PARAMS ((int));
654 static void dot_spillmem
PARAMS ((int));
655 static void dot_spillreg_p
PARAMS ((int));
656 static void dot_spillmem_p
PARAMS ((int));
657 static void dot_label_state
PARAMS ((int));
658 static void dot_copy_state
PARAMS ((int));
659 static void dot_unwabi
PARAMS ((int));
660 static void dot_personality
PARAMS ((int));
661 static void dot_body
PARAMS ((int));
662 static void dot_prologue
PARAMS ((int));
663 static void dot_endp
PARAMS ((int));
664 static void dot_template
PARAMS ((int));
665 static void dot_regstk
PARAMS ((int));
666 static void dot_rot
PARAMS ((int));
667 static void dot_byteorder
PARAMS ((int));
668 static void dot_psr
PARAMS ((int));
669 static void dot_alias
PARAMS ((int));
670 static void dot_ln
PARAMS ((int));
671 static char *parse_section_name
PARAMS ((void));
672 static void dot_xdata
PARAMS ((int));
673 static void stmt_float_cons
PARAMS ((int));
674 static void stmt_cons_ua
PARAMS ((int));
675 static void dot_xfloat_cons
PARAMS ((int));
676 static void dot_xstringer
PARAMS ((int));
677 static void dot_xdata_ua
PARAMS ((int));
678 static void dot_xfloat_cons_ua
PARAMS ((int));
679 static void print_prmask
PARAMS ((valueT mask
));
680 static void dot_pred_rel
PARAMS ((int));
681 static void dot_reg_val
PARAMS ((int));
682 static void dot_dv_mode
PARAMS ((int));
683 static void dot_entry
PARAMS ((int));
684 static void dot_mem_offset
PARAMS ((int));
685 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
686 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
687 static void declare_register_set
PARAMS ((const char *, int, int));
688 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
689 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
690 int index
, expressionS
*e
));
691 static int parse_operand
PARAMS ((expressionS
*e
));
692 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
693 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
694 static void emit_one_bundle
PARAMS ((void));
695 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
696 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
697 bfd_reloc_code_real_type r_type
));
698 static void insn_group_break
PARAMS ((int, int, int));
699 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
700 struct rsrc
*, int depind
, int path
));
701 static void add_qp_mutex
PARAMS((valueT mask
));
702 static void add_qp_imply
PARAMS((int p1
, int p2
));
703 static void clear_qp_branch_flag
PARAMS((valueT mask
));
704 static void clear_qp_mutex
PARAMS((valueT mask
));
705 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
706 static void clear_register_values
PARAMS ((void));
707 static void print_dependency
PARAMS ((const char *action
, int depind
));
708 static void instruction_serialization
PARAMS ((void));
709 static void data_serialization
PARAMS ((void));
710 static void remove_marked_resource
PARAMS ((struct rsrc
*));
711 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
712 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
713 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
714 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
715 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
716 struct ia64_opcode
*, int, struct rsrc
[], int, int));
717 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
718 static void check_dependencies
PARAMS((struct ia64_opcode
*));
719 static void mark_resources
PARAMS((struct ia64_opcode
*));
720 static void update_dependencies
PARAMS((struct ia64_opcode
*));
721 static void note_register_values
PARAMS((struct ia64_opcode
*));
722 static int qp_mutex
PARAMS ((int, int, int));
723 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
724 static void output_vbyte_mem
PARAMS ((int, char *, char *));
725 static void count_output
PARAMS ((int, char *, char *));
726 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
727 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
728 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
729 static void output_P1_format
PARAMS ((vbyte_func
, int));
730 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
731 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
732 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
733 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
734 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
735 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
736 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
737 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
738 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
739 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
740 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
741 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
742 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
743 static char format_ab_reg
PARAMS ((int, int));
744 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
746 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
747 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
749 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
750 static void free_list_records
PARAMS ((unw_rec_list
*));
751 static unw_rec_list
*output_prologue
PARAMS ((void));
752 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
753 static unw_rec_list
*output_body
PARAMS ((void));
754 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
755 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
756 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
757 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
758 static unw_rec_list
*output_rp_when
PARAMS ((void));
759 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
761 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
763 static unw_rec_list
*output_pfs_when
PARAMS ((void));
764 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
765 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
767 static unw_rec_list
*output_preds_when
PARAMS ((void));
768 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
769 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
771 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
772 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
773 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
774 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
775 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
776 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
777 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
778 static unw_rec_list
*output_unat_when
PARAMS ((void));
779 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
780 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
781 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
782 static unw_rec_list
*output_lc_when
PARAMS ((void));
783 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
784 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
785 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
786 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
787 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
788 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
790 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
791 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
792 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
793 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
794 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
795 static unw_rec_list
*output_bsp_when
PARAMS ((void));
796 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
797 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
798 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
799 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
800 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
801 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
802 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
803 static unw_rec_list
*output_rnat_when
PARAMS ((void));
804 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
805 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
806 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
808 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
809 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
810 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
811 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
812 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
813 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
815 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
817 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
819 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
820 unsigned int, unsigned int));
821 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
822 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
823 static int calc_record_size
PARAMS ((unw_rec_list
*));
824 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
825 static int count_bits
PARAMS ((unsigned long));
826 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
827 unsigned long, fragS
*));
828 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
829 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
830 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
831 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
832 static int generate_unwind_image
PARAMS ((void));
834 /* Determine if application register REGNUM resides in the integer
835 unit (as opposed to the memory unit). */
837 ar_is_in_integer_unit (reg
)
842 return (reg
== 64 /* pfs */
843 || reg
== 65 /* lc */
844 || reg
== 66 /* ec */
845 /* ??? ias accepts and puts these in the integer unit. */
846 || (reg
>= 112 && reg
<= 127));
849 /* Switch to section NAME and create section if necessary. It's
850 rather ugly that we have to manipulate input_line_pointer but I
851 don't see any other way to accomplish the same thing without
852 changing obj-elf.c (which may be the Right Thing, in the end). */
857 char *saved_input_line_pointer
;
859 saved_input_line_pointer
= input_line_pointer
;
860 input_line_pointer
= name
;
862 input_line_pointer
= saved_input_line_pointer
;
865 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
868 ia64_elf_section_flags (flags
, attr
, type
)
872 if (attr
& SHF_IA_64_SHORT
)
873 flags
|= SEC_SMALL_DATA
;
878 set_regstack (ins
, locs
, outs
, rots
)
879 unsigned int ins
, locs
, outs
, rots
;
884 sof
= ins
+ locs
+ outs
;
887 as_bad ("Size of frame exceeds maximum of 96 registers");
892 as_warn ("Size of rotating registers exceeds frame size");
895 md
.in
.base
= REG_GR
+ 32;
896 md
.loc
.base
= md
.in
.base
+ ins
;
897 md
.out
.base
= md
.loc
.base
+ locs
;
899 md
.in
.num_regs
= ins
;
900 md
.loc
.num_regs
= locs
;
901 md
.out
.num_regs
= outs
;
902 md
.rot
.num_regs
= rots
;
909 struct label_fix
*lfix
;
911 subsegT saved_subseg
;
913 if (!md
.last_text_seg
)
917 saved_subseg
= now_subseg
;
919 subseg_set (md
.last_text_seg
, 0);
921 while (md
.num_slots_in_use
> 0)
922 emit_one_bundle (); /* force out queued instructions */
924 /* In case there are labels following the last instruction, resolve
926 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
928 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
929 symbol_set_frag (lfix
->sym
, frag_now
);
931 CURR_SLOT
.label_fixups
= 0;
932 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
934 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
935 symbol_set_frag (lfix
->sym
, frag_now
);
937 CURR_SLOT
.tag_fixups
= 0;
939 subseg_set (saved_seg
, saved_subseg
);
941 if (md
.qp
.X_op
== O_register
)
942 as_bad ("qualifying predicate not followed by instruction");
946 ia64_do_align (nbytes
)
949 char *saved_input_line_pointer
= input_line_pointer
;
951 input_line_pointer
= "";
952 s_align_bytes (nbytes
);
953 input_line_pointer
= saved_input_line_pointer
;
957 ia64_cons_align (nbytes
)
962 char *saved_input_line_pointer
= input_line_pointer
;
963 input_line_pointer
= "";
964 s_align_bytes (nbytes
);
965 input_line_pointer
= saved_input_line_pointer
;
969 /* Output COUNT bytes to a memory location. */
970 static unsigned char *vbyte_mem_ptr
= NULL
;
973 output_vbyte_mem (count
, ptr
, comment
)
979 if (vbyte_mem_ptr
== NULL
)
984 for (x
= 0; x
< count
; x
++)
985 *(vbyte_mem_ptr
++) = ptr
[x
];
988 /* Count the number of bytes required for records. */
989 static int vbyte_count
= 0;
991 count_output (count
, ptr
, comment
)
996 vbyte_count
+= count
;
1000 output_R1_format (f
, rtype
, rlen
)
1002 unw_record_type rtype
;
1009 output_R3_format (f
, rtype
, rlen
);
1015 else if (rtype
!= prologue
)
1016 as_bad ("record type is not valid");
1018 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1019 (*f
) (1, &byte
, NULL
);
1023 output_R2_format (f
, mask
, grsave
, rlen
)
1030 mask
= (mask
& 0x0f);
1031 grsave
= (grsave
& 0x7f);
1033 bytes
[0] = (UNW_R2
| (mask
>> 1));
1034 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1035 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1036 (*f
) (count
, bytes
, NULL
);
1040 output_R3_format (f
, rtype
, rlen
)
1042 unw_record_type rtype
;
1049 output_R1_format (f
, rtype
, rlen
);
1055 else if (rtype
!= prologue
)
1056 as_bad ("record type is not valid");
1057 bytes
[0] = (UNW_R3
| r
);
1058 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1059 (*f
) (count
+ 1, bytes
, NULL
);
1063 output_P1_format (f
, brmask
)
1068 byte
= UNW_P1
| (brmask
& 0x1f);
1069 (*f
) (1, &byte
, NULL
);
1073 output_P2_format (f
, brmask
, gr
)
1079 brmask
= (brmask
& 0x1f);
1080 bytes
[0] = UNW_P2
| (brmask
>> 1);
1081 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1082 (*f
) (2, bytes
, NULL
);
1086 output_P3_format (f
, rtype
, reg
)
1088 unw_record_type rtype
;
1133 as_bad ("Invalid record type for P3 format.");
1135 bytes
[0] = (UNW_P3
| (r
>> 1));
1136 bytes
[1] = (((r
& 1) << 7) | reg
);
1137 (*f
) (2, bytes
, NULL
);
1141 output_P4_format (f
, imask
, imask_size
)
1143 unsigned char *imask
;
1144 unsigned long imask_size
;
1147 (*f
) (imask_size
, imask
, NULL
);
1151 output_P5_format (f
, grmask
, frmask
)
1154 unsigned long frmask
;
1157 grmask
= (grmask
& 0x0f);
1160 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1161 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1162 bytes
[3] = (frmask
& 0x000000ff);
1163 (*f
) (4, bytes
, NULL
);
1167 output_P6_format (f
, rtype
, rmask
)
1169 unw_record_type rtype
;
1175 if (rtype
== gr_mem
)
1177 else if (rtype
!= fr_mem
)
1178 as_bad ("Invalid record type for format P6");
1179 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1180 (*f
) (1, &byte
, NULL
);
1184 output_P7_format (f
, rtype
, w1
, w2
)
1186 unw_record_type rtype
;
1193 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1198 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1248 bytes
[0] = (UNW_P7
| r
);
1249 (*f
) (count
, bytes
, NULL
);
1253 output_P8_format (f
, rtype
, t
)
1255 unw_record_type rtype
;
1294 case bspstore_psprel
:
1297 case bspstore_sprel
:
1309 case priunat_when_gr
:
1312 case priunat_psprel
:
1318 case priunat_when_mem
:
1325 count
+= output_leb128 (bytes
+ 2, t
, 0);
1326 (*f
) (count
, bytes
, NULL
);
1330 output_P9_format (f
, grmask
, gr
)
1337 bytes
[1] = (grmask
& 0x0f);
1338 bytes
[2] = (gr
& 0x7f);
1339 (*f
) (3, bytes
, NULL
);
1343 output_P10_format (f
, abi
, context
)
1350 bytes
[1] = (abi
& 0xff);
1351 bytes
[2] = (context
& 0xff);
1352 (*f
) (3, bytes
, NULL
);
1356 output_B1_format (f
, rtype
, label
)
1358 unw_record_type rtype
;
1359 unsigned long label
;
1365 output_B4_format (f
, rtype
, label
);
1368 if (rtype
== copy_state
)
1370 else if (rtype
!= label_state
)
1371 as_bad ("Invalid record type for format B1");
1373 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1374 (*f
) (1, &byte
, NULL
);
1378 output_B2_format (f
, ecount
, t
)
1380 unsigned long ecount
;
1387 output_B3_format (f
, ecount
, t
);
1390 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1391 count
+= output_leb128 (bytes
+ 1, t
, 0);
1392 (*f
) (count
, bytes
, NULL
);
1396 output_B3_format (f
, ecount
, t
)
1398 unsigned long ecount
;
1405 output_B2_format (f
, ecount
, t
);
1409 count
+= output_leb128 (bytes
+ 1, t
, 0);
1410 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1411 (*f
) (count
, bytes
, NULL
);
1415 output_B4_format (f
, rtype
, label
)
1417 unw_record_type rtype
;
1418 unsigned long label
;
1425 output_B1_format (f
, rtype
, label
);
1429 if (rtype
== copy_state
)
1431 else if (rtype
!= label_state
)
1432 as_bad ("Invalid record type for format B1");
1434 bytes
[0] = (UNW_B4
| (r
<< 3));
1435 count
+= output_leb128 (bytes
+ 1, label
, 0);
1436 (*f
) (count
, bytes
, NULL
);
1440 format_ab_reg (ab
, reg
)
1447 ret
= (ab
<< 5) | reg
;
1452 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1454 unw_record_type rtype
;
1464 if (rtype
== spill_sprel
)
1466 else if (rtype
!= spill_psprel
)
1467 as_bad ("Invalid record type for format X1");
1468 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1469 count
+= output_leb128 (bytes
+ 2, t
, 0);
1470 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1471 (*f
) (count
, bytes
, NULL
);
1475 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1484 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1485 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1486 count
+= output_leb128 (bytes
+ 3, t
, 0);
1487 (*f
) (count
, bytes
, NULL
);
1491 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1493 unw_record_type rtype
;
1504 if (rtype
== spill_sprel_p
)
1506 else if (rtype
!= spill_psprel_p
)
1507 as_bad ("Invalid record type for format X3");
1508 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1509 bytes
[2] = format_ab_reg (ab
, reg
);
1510 count
+= output_leb128 (bytes
+ 3, t
, 0);
1511 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1512 (*f
) (count
, bytes
, NULL
);
1516 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1526 bytes
[1] = (qp
& 0x3f);
1527 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1528 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1529 count
+= output_leb128 (bytes
+ 4, t
, 0);
1530 (*f
) (count
, bytes
, NULL
);
1533 /* This function allocates a record list structure, and initializes fields. */
1535 static unw_rec_list
*
1536 alloc_record (unw_record_type t
)
1539 ptr
= xmalloc (sizeof (*ptr
));
1541 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1546 /* This function frees an entire list of record structures. */
1549 free_list_records (unw_rec_list
*first
)
1552 for (ptr
= first
; ptr
!= NULL
;)
1554 unw_rec_list
*tmp
= ptr
;
1556 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1557 && tmp
->r
.record
.r
.mask
.i
)
1558 free (tmp
->r
.record
.r
.mask
.i
);
1565 static unw_rec_list
*
1568 unw_rec_list
*ptr
= alloc_record (prologue
);
1569 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1573 static unw_rec_list
*
1574 output_prologue_gr (saved_mask
, reg
)
1575 unsigned int saved_mask
;
1578 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1579 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1580 ptr
->r
.record
.r
.grmask
= saved_mask
;
1581 ptr
->r
.record
.r
.grsave
= reg
;
1585 static unw_rec_list
*
1588 unw_rec_list
*ptr
= alloc_record (body
);
1592 static unw_rec_list
*
1593 output_mem_stack_f (size
)
1596 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1597 ptr
->r
.record
.p
.size
= size
;
1601 static unw_rec_list
*
1602 output_mem_stack_v ()
1604 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1608 static unw_rec_list
*
1612 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1613 ptr
->r
.record
.p
.gr
= gr
;
1617 static unw_rec_list
*
1618 output_psp_sprel (offset
)
1619 unsigned int offset
;
1621 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1622 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1626 static unw_rec_list
*
1629 unw_rec_list
*ptr
= alloc_record (rp_when
);
1633 static unw_rec_list
*
1637 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1638 ptr
->r
.record
.p
.gr
= gr
;
1642 static unw_rec_list
*
1646 unw_rec_list
*ptr
= alloc_record (rp_br
);
1647 ptr
->r
.record
.p
.br
= br
;
1651 static unw_rec_list
*
1652 output_rp_psprel (offset
)
1653 unsigned int offset
;
1655 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1656 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1660 static unw_rec_list
*
1661 output_rp_sprel (offset
)
1662 unsigned int offset
;
1664 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1665 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1669 static unw_rec_list
*
1672 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1676 static unw_rec_list
*
1680 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1681 ptr
->r
.record
.p
.gr
= gr
;
1685 static unw_rec_list
*
1686 output_pfs_psprel (offset
)
1687 unsigned int offset
;
1689 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1690 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1694 static unw_rec_list
*
1695 output_pfs_sprel (offset
)
1696 unsigned int offset
;
1698 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1699 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1703 static unw_rec_list
*
1704 output_preds_when ()
1706 unw_rec_list
*ptr
= alloc_record (preds_when
);
1710 static unw_rec_list
*
1711 output_preds_gr (gr
)
1714 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1715 ptr
->r
.record
.p
.gr
= gr
;
1719 static unw_rec_list
*
1720 output_preds_psprel (offset
)
1721 unsigned int offset
;
1723 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1724 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1728 static unw_rec_list
*
1729 output_preds_sprel (offset
)
1730 unsigned int offset
;
1732 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1733 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1737 static unw_rec_list
*
1738 output_fr_mem (mask
)
1741 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1742 ptr
->r
.record
.p
.rmask
= mask
;
1746 static unw_rec_list
*
1747 output_frgr_mem (gr_mask
, fr_mask
)
1748 unsigned int gr_mask
;
1749 unsigned int fr_mask
;
1751 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1752 ptr
->r
.record
.p
.grmask
= gr_mask
;
1753 ptr
->r
.record
.p
.frmask
= fr_mask
;
1757 static unw_rec_list
*
1758 output_gr_gr (mask
, reg
)
1762 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1763 ptr
->r
.record
.p
.grmask
= mask
;
1764 ptr
->r
.record
.p
.gr
= reg
;
1768 static unw_rec_list
*
1769 output_gr_mem (mask
)
1772 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1773 ptr
->r
.record
.p
.rmask
= mask
;
1777 static unw_rec_list
*
1778 output_br_mem (unsigned int mask
)
1780 unw_rec_list
*ptr
= alloc_record (br_mem
);
1781 ptr
->r
.record
.p
.brmask
= mask
;
1785 static unw_rec_list
*
1786 output_br_gr (save_mask
, reg
)
1787 unsigned int save_mask
;
1790 unw_rec_list
*ptr
= alloc_record (br_gr
);
1791 ptr
->r
.record
.p
.brmask
= save_mask
;
1792 ptr
->r
.record
.p
.gr
= reg
;
1796 static unw_rec_list
*
1797 output_spill_base (offset
)
1798 unsigned int offset
;
1800 unw_rec_list
*ptr
= alloc_record (spill_base
);
1801 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1805 static unw_rec_list
*
1808 unw_rec_list
*ptr
= alloc_record (unat_when
);
1812 static unw_rec_list
*
1816 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1817 ptr
->r
.record
.p
.gr
= gr
;
1821 static unw_rec_list
*
1822 output_unat_psprel (offset
)
1823 unsigned int offset
;
1825 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1826 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1830 static unw_rec_list
*
1831 output_unat_sprel (offset
)
1832 unsigned int offset
;
1834 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1835 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1839 static unw_rec_list
*
1842 unw_rec_list
*ptr
= alloc_record (lc_when
);
1846 static unw_rec_list
*
1850 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1851 ptr
->r
.record
.p
.gr
= gr
;
1855 static unw_rec_list
*
1856 output_lc_psprel (offset
)
1857 unsigned int offset
;
1859 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1860 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1864 static unw_rec_list
*
1865 output_lc_sprel (offset
)
1866 unsigned int offset
;
1868 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1869 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1873 static unw_rec_list
*
1876 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1880 static unw_rec_list
*
1884 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1885 ptr
->r
.record
.p
.gr
= gr
;
1889 static unw_rec_list
*
1890 output_fpsr_psprel (offset
)
1891 unsigned int offset
;
1893 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1894 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1898 static unw_rec_list
*
1899 output_fpsr_sprel (offset
)
1900 unsigned int offset
;
1902 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1903 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1907 static unw_rec_list
*
1908 output_priunat_when_gr ()
1910 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1914 static unw_rec_list
*
1915 output_priunat_when_mem ()
1917 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1921 static unw_rec_list
*
1922 output_priunat_gr (gr
)
1925 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1926 ptr
->r
.record
.p
.gr
= gr
;
1930 static unw_rec_list
*
1931 output_priunat_psprel (offset
)
1932 unsigned int offset
;
1934 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1935 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1939 static unw_rec_list
*
1940 output_priunat_sprel (offset
)
1941 unsigned int offset
;
1943 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1944 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1948 static unw_rec_list
*
1951 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1955 static unw_rec_list
*
1959 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1960 ptr
->r
.record
.p
.gr
= gr
;
1964 static unw_rec_list
*
1965 output_bsp_psprel (offset
)
1966 unsigned int offset
;
1968 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1969 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1973 static unw_rec_list
*
1974 output_bsp_sprel (offset
)
1975 unsigned int offset
;
1977 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1978 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1982 static unw_rec_list
*
1983 output_bspstore_when ()
1985 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
1989 static unw_rec_list
*
1990 output_bspstore_gr (gr
)
1993 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
1994 ptr
->r
.record
.p
.gr
= gr
;
1998 static unw_rec_list
*
1999 output_bspstore_psprel (offset
)
2000 unsigned int offset
;
2002 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2003 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2007 static unw_rec_list
*
2008 output_bspstore_sprel (offset
)
2009 unsigned int offset
;
2011 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2012 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2016 static unw_rec_list
*
2019 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2023 static unw_rec_list
*
2027 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2028 ptr
->r
.record
.p
.gr
= gr
;
2032 static unw_rec_list
*
2033 output_rnat_psprel (offset
)
2034 unsigned int offset
;
2036 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2037 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2041 static unw_rec_list
*
2042 output_rnat_sprel (offset
)
2043 unsigned int offset
;
2045 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2046 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2050 static unw_rec_list
*
2051 output_unwabi (abi
, context
)
2053 unsigned long context
;
2055 unw_rec_list
*ptr
= alloc_record (unwabi
);
2056 ptr
->r
.record
.p
.abi
= abi
;
2057 ptr
->r
.record
.p
.context
= context
;
2061 static unw_rec_list
*
2062 output_epilogue (unsigned long ecount
)
2064 unw_rec_list
*ptr
= alloc_record (epilogue
);
2065 ptr
->r
.record
.b
.ecount
= ecount
;
2069 static unw_rec_list
*
2070 output_label_state (unsigned long label
)
2072 unw_rec_list
*ptr
= alloc_record (label_state
);
2073 ptr
->r
.record
.b
.label
= label
;
2077 static unw_rec_list
*
2078 output_copy_state (unsigned long label
)
2080 unw_rec_list
*ptr
= alloc_record (copy_state
);
2081 ptr
->r
.record
.b
.label
= label
;
2085 static unw_rec_list
*
2086 output_spill_psprel (ab
, reg
, offset
)
2089 unsigned int offset
;
2091 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2092 ptr
->r
.record
.x
.ab
= ab
;
2093 ptr
->r
.record
.x
.reg
= reg
;
2094 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2098 static unw_rec_list
*
2099 output_spill_sprel (ab
, reg
, offset
)
2102 unsigned int offset
;
2104 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2105 ptr
->r
.record
.x
.ab
= ab
;
2106 ptr
->r
.record
.x
.reg
= reg
;
2107 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2111 static unw_rec_list
*
2112 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2115 unsigned int offset
;
2116 unsigned int predicate
;
2118 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2119 ptr
->r
.record
.x
.ab
= ab
;
2120 ptr
->r
.record
.x
.reg
= reg
;
2121 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2122 ptr
->r
.record
.x
.qp
= predicate
;
2126 static unw_rec_list
*
2127 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2130 unsigned int offset
;
2131 unsigned int predicate
;
2133 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2134 ptr
->r
.record
.x
.ab
= ab
;
2135 ptr
->r
.record
.x
.reg
= reg
;
2136 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2137 ptr
->r
.record
.x
.qp
= predicate
;
2141 static unw_rec_list
*
2142 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2145 unsigned int targ_reg
;
2148 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2149 ptr
->r
.record
.x
.ab
= ab
;
2150 ptr
->r
.record
.x
.reg
= reg
;
2151 ptr
->r
.record
.x
.treg
= targ_reg
;
2152 ptr
->r
.record
.x
.xy
= xy
;
2156 static unw_rec_list
*
2157 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2160 unsigned int targ_reg
;
2162 unsigned int predicate
;
2164 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2165 ptr
->r
.record
.x
.ab
= ab
;
2166 ptr
->r
.record
.x
.reg
= reg
;
2167 ptr
->r
.record
.x
.treg
= targ_reg
;
2168 ptr
->r
.record
.x
.xy
= xy
;
2169 ptr
->r
.record
.x
.qp
= predicate
;
2173 /* Given a unw_rec_list process the correct format with the
2174 specified function. */
2177 process_one_record (ptr
, f
)
2181 unsigned long fr_mask
, gr_mask
;
2183 switch (ptr
->r
.type
)
2189 /* These are taken care of by prologue/prologue_gr. */
2194 if (ptr
->r
.type
== prologue_gr
)
2195 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2196 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2198 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2200 /* Output descriptor(s) for union of register spills (if any). */
2201 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2202 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2205 if ((fr_mask
& ~0xfUL
) == 0)
2206 output_P6_format (f
, fr_mem
, fr_mask
);
2209 output_P5_format (f
, gr_mask
, fr_mask
);
2214 output_P6_format (f
, gr_mem
, gr_mask
);
2215 if (ptr
->r
.record
.r
.mask
.br_mem
)
2216 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2218 /* output imask descriptor if necessary: */
2219 if (ptr
->r
.record
.r
.mask
.i
)
2220 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2221 ptr
->r
.record
.r
.imask_size
);
2225 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2229 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2230 ptr
->r
.record
.p
.size
);
2243 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2246 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2249 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2257 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2266 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2276 case bspstore_sprel
:
2278 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2281 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2284 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2287 as_bad ("spill_mask record unimplemented.");
2289 case priunat_when_gr
:
2290 case priunat_when_mem
:
2294 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2296 case priunat_psprel
:
2298 case bspstore_psprel
:
2300 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2303 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2306 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2310 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2313 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2314 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2315 ptr
->r
.record
.x
.pspoff
);
2318 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2319 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2320 ptr
->r
.record
.x
.spoff
);
2323 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2324 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2325 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2327 case spill_psprel_p
:
2328 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2329 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2330 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2333 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2334 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2335 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2338 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2339 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2340 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2344 as_bad ("record_type_not_valid");
2349 /* Given a unw_rec_list list, process all the records with
2350 the specified function. */
2352 process_unw_records (list
, f
)
2357 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2358 process_one_record (ptr
, f
);
2361 /* Determine the size of a record list in bytes. */
2363 calc_record_size (list
)
2367 process_unw_records (list
, count_output
);
2371 /* Update IMASK bitmask to reflect the fact that one or more registers
2372 of type TYPE are saved starting at instruction with index T. If N
2373 bits are set in REGMASK, it is assumed that instructions T through
2374 T+N-1 save these registers.
2378 1: instruction saves next fp reg
2379 2: instruction saves next general reg
2380 3: instruction saves next branch reg */
2382 set_imask (region
, regmask
, t
, type
)
2383 unw_rec_list
*region
;
2384 unsigned long regmask
;
2388 unsigned char *imask
;
2389 unsigned long imask_size
;
2393 imask
= region
->r
.record
.r
.mask
.i
;
2394 imask_size
= region
->r
.record
.r
.imask_size
;
2397 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2398 imask
= xmalloc (imask_size
);
2399 memset (imask
, 0, imask_size
);
2401 region
->r
.record
.r
.imask_size
= imask_size
;
2402 region
->r
.record
.r
.mask
.i
= imask
;
2406 pos
= 2 * (3 - t
% 4);
2409 if (i
>= imask_size
)
2411 as_bad ("Ignoring attempt to spill beyond end of region");
2415 imask
[i
] |= (type
& 0x3) << pos
;
2417 regmask
&= (regmask
- 1);
2428 count_bits (unsigned long mask
)
2440 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2441 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2442 containing FIRST_ADDR. */
2445 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2446 unsigned long slot_addr
;
2448 unsigned long first_addr
;
2451 unsigned long index
= 0;
2453 /* First time we are called, the initial address and frag are invalid. */
2454 if (first_addr
== 0)
2457 /* If the two addresses are in different frags, then we need to add in
2458 the remaining size of this frag, and then the entire size of intermediate
2460 while (slot_frag
!= first_frag
)
2462 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2464 /* Add in the full size of the frag converted to instruction slots. */
2465 index
+= 3 * (first_frag
->fr_fix
>> 4);
2466 /* Subtract away the initial part before first_addr. */
2467 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2468 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2470 /* Move to the beginning of the next frag. */
2471 first_frag
= first_frag
->fr_next
;
2472 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2475 /* Add in the used part of the last frag. */
2476 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2477 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2481 /* Given a complete record list, process any records which have
2482 unresolved fields, (ie length counts for a prologue). After
2483 this has been run, all neccessary information should be available
2484 within each record to generate an image. */
2487 fixup_unw_records (list
)
2490 unw_rec_list
*ptr
, *region
= 0;
2491 unsigned long first_addr
= 0, rlen
= 0, t
;
2492 fragS
*first_frag
= 0;
2494 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2496 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2497 as_bad (" Insn slot not set in unwind record.");
2498 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2499 first_addr
, first_frag
);
2500 switch (ptr
->r
.type
)
2507 int size
, dir_len
= 0;
2508 unsigned long last_addr
;
2511 first_addr
= ptr
->slot_number
;
2512 first_frag
= ptr
->slot_frag
;
2513 ptr
->slot_number
= 0;
2514 /* Find either the next body/prologue start, or the end of
2515 the list, and determine the size of the region. */
2516 last_addr
= unwind
.next_slot_number
;
2517 last_frag
= unwind
.next_slot_frag
;
2518 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2519 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2520 || last
->r
.type
== body
)
2522 last_addr
= last
->slot_number
;
2523 last_frag
= last
->slot_frag
;
2526 else if (!last
->next
)
2528 /* In the absence of an explicit .body directive,
2529 the prologue ends after the last instruction
2530 covered by an unwind directive. */
2531 if (ptr
->r
.type
!= body
)
2533 last_addr
= last
->slot_number
;
2534 last_frag
= last
->slot_frag
;
2535 switch (last
->r
.type
)
2538 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2539 + count_bits (last
->r
.record
.p
.grmask
));
2543 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2547 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2550 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2559 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2561 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2566 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2577 case priunat_when_gr
:
2578 case priunat_when_mem
:
2582 ptr
->r
.record
.p
.t
= t
;
2590 case spill_psprel_p
:
2591 ptr
->r
.record
.x
.t
= t
;
2597 as_bad ("frgr_mem record before region record!\n");
2600 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2601 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2602 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2603 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2608 as_bad ("fr_mem record before region record!\n");
2611 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2612 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2617 as_bad ("gr_mem record before region record!\n");
2620 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2621 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2626 as_bad ("br_mem record before region record!\n");
2629 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2630 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2636 as_bad ("gr_gr record before region record!\n");
2639 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2644 as_bad ("br_gr record before region record!\n");
2647 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2656 /* Generate an unwind image from a record list. Returns the number of
2657 bytes in the resulting image. The memory image itselof is returned
2658 in the 'ptr' parameter. */
2660 output_unw_records (list
, ptr
)
2664 int size
, x
, extra
= 0;
2667 fixup_unw_records (list
);
2668 size
= calc_record_size (list
);
2670 /* pad to 8 byte boundry. */
2674 /* Add 8 for the header + 8 more bytes for the personality offset. */
2675 mem
= xmalloc (size
+ extra
+ 16);
2677 vbyte_mem_ptr
= mem
+ 8;
2678 /* Clear the padding area and personality. */
2679 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2680 /* Initialize the header area. */
2681 md_number_to_chars (mem
, (((bfd_vma
) 1 << 48) /* version */
2682 | (unwind
.personality_routine
2683 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2685 | ((size
+ extra
) / 8)), /* length (dwords) */
2688 process_unw_records (list
, output_vbyte_mem
);
2691 return size
+ extra
+ 16;
2695 convert_expr_to_ab_reg (e
, ab
, regp
)
2702 if (e
->X_op
!= O_register
)
2705 reg
= e
->X_add_number
;
2706 if (reg
>= REG_GR
+ 4 && reg
<= REG_GR
+ 7)
2709 *regp
= reg
- REG_GR
;
2711 else if ((reg
>= REG_FR
+ 2 && reg
<= REG_FR
+ 5)
2712 || (reg
>= REG_FR
+ 16 && reg
<= REG_FR
+ 31))
2715 *regp
= reg
- REG_FR
;
2717 else if (reg
>= REG_BR
+ 1 && reg
<= REG_BR
+ 5)
2720 *regp
= reg
- REG_BR
;
2727 case REG_PR
: *regp
= 0; break;
2728 case REG_PSP
: *regp
= 1; break;
2729 case REG_PRIUNAT
: *regp
= 2; break;
2730 case REG_BR
+ 0: *regp
= 3; break;
2731 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2732 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2733 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2734 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2735 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2736 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2737 case REG_AR
+ AR_LC
: *regp
= 10; break;
2747 convert_expr_to_xy_reg (e
, xy
, regp
)
2754 if (e
->X_op
!= O_register
)
2757 reg
= e
->X_add_number
;
2759 if (reg
>= REG_GR
&& reg
<= REG_GR
+ 127)
2762 *regp
= reg
- REG_GR
;
2764 else if (reg
>= REG_FR
&& reg
<= REG_FR
+ 127)
2767 *regp
= reg
- REG_FR
;
2769 else if (reg
>= REG_BR
&& reg
<= REG_BR
+ 7)
2772 *regp
= reg
- REG_BR
;
2786 radix
= *input_line_pointer
++;
2788 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2790 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2791 ignore_rest_of_line ();
2796 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2798 dot_special_section (which
)
2801 set_section ((char *) special_section_name
[which
]);
2805 add_unwind_entry (ptr
)
2809 unwind
.tail
->next
= ptr
;
2814 /* The current entry can in fact be a chain of unwind entries. */
2815 if (unwind
.current_entry
== NULL
)
2816 unwind
.current_entry
= ptr
;
2827 if (e
.X_op
!= O_constant
)
2828 as_bad ("Operand to .fframe must be a constant");
2830 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2841 reg
= e
.X_add_number
- REG_GR
;
2842 if (e
.X_op
== O_register
&& reg
< 128)
2844 add_unwind_entry (output_mem_stack_v ());
2845 if (! (unwind
.prologue_mask
& 2))
2846 add_unwind_entry (output_psp_gr (reg
));
2849 as_bad ("First operand to .vframe must be a general register");
2853 dot_vframesp (dummy
)
2859 if (e
.X_op
== O_constant
)
2861 add_unwind_entry (output_mem_stack_v ());
2862 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2865 as_bad ("First operand to .vframesp must be a general register");
2869 dot_vframepsp (dummy
)
2875 if (e
.X_op
== O_constant
)
2877 add_unwind_entry (output_mem_stack_v ());
2878 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2881 as_bad ("First operand to .vframepsp must be a general register");
2892 sep
= parse_operand (&e1
);
2894 as_bad ("No second operand to .save");
2895 sep
= parse_operand (&e2
);
2897 reg1
= e1
.X_add_number
;
2898 reg2
= e2
.X_add_number
- REG_GR
;
2900 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2901 if (e1
.X_op
== O_register
)
2903 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
2907 case REG_AR
+ AR_BSP
:
2908 add_unwind_entry (output_bsp_when ());
2909 add_unwind_entry (output_bsp_gr (reg2
));
2911 case REG_AR
+ AR_BSPSTORE
:
2912 add_unwind_entry (output_bspstore_when ());
2913 add_unwind_entry (output_bspstore_gr (reg2
));
2915 case REG_AR
+ AR_RNAT
:
2916 add_unwind_entry (output_rnat_when ());
2917 add_unwind_entry (output_rnat_gr (reg2
));
2919 case REG_AR
+ AR_UNAT
:
2920 add_unwind_entry (output_unat_when ());
2921 add_unwind_entry (output_unat_gr (reg2
));
2923 case REG_AR
+ AR_FPSR
:
2924 add_unwind_entry (output_fpsr_when ());
2925 add_unwind_entry (output_fpsr_gr (reg2
));
2927 case REG_AR
+ AR_PFS
:
2928 add_unwind_entry (output_pfs_when ());
2929 if (! (unwind
.prologue_mask
& 4))
2930 add_unwind_entry (output_pfs_gr (reg2
));
2932 case REG_AR
+ AR_LC
:
2933 add_unwind_entry (output_lc_when ());
2934 add_unwind_entry (output_lc_gr (reg2
));
2937 add_unwind_entry (output_rp_when ());
2938 if (! (unwind
.prologue_mask
& 8))
2939 add_unwind_entry (output_rp_gr (reg2
));
2942 add_unwind_entry (output_preds_when ());
2943 if (! (unwind
.prologue_mask
& 1))
2944 add_unwind_entry (output_preds_gr (reg2
));
2947 add_unwind_entry (output_priunat_when_gr ());
2948 add_unwind_entry (output_priunat_gr (reg2
));
2951 as_bad ("First operand not a valid register");
2955 as_bad (" Second operand not a valid register");
2958 as_bad ("First operand not a register");
2966 unsigned long ecount
= 0;
2969 sep
= parse_operand (&e1
);
2970 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2972 as_bad ("First operand to .restore must be stack pointer (sp)");
2978 parse_operand (&e2
);
2979 if (e1
.X_op
!= O_constant
)
2981 as_bad ("Second operand to .restore must be constant");
2986 add_unwind_entry (output_epilogue (ecount
));
2990 dot_restorereg (dummy
)
2993 unsigned int ab
, reg
;
2998 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3000 as_bad ("First operand to .restorereg must be a preserved register");
3003 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3007 dot_restorereg_p (dummy
)
3010 unsigned int qp
, ab
, reg
;
3014 sep
= parse_operand (&e1
);
3017 as_bad ("No second operand to .restorereg.p");
3021 parse_operand (&e2
);
3023 qp
= e1
.X_add_number
- REG_P
;
3024 if (e1
.X_op
!= O_register
|| qp
> 63)
3026 as_bad ("First operand to .restorereg.p must be a predicate");
3030 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3032 as_bad ("Second operand to .restorereg.p must be a preserved register");
3035 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3039 generate_unwind_image ()
3042 unsigned char *unw_rec
;
3044 /* Force out pending instructions, to make sure all unwind records have
3045 a valid slot_number field. */
3046 ia64_flush_insns ();
3048 /* Generate the unwind record. */
3049 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3051 as_bad ("Unwind record is not a multiple of 8 bytes.");
3053 /* If there are unwind records, switch sections, and output the info. */
3056 unsigned char *where
;
3058 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
3060 /* Set expression which points to start of unwind descriptor area. */
3061 unwind
.info
= expr_build_dot ();
3063 where
= (unsigned char *) frag_more (size
);
3065 /* Issue a label for this address, and keep track of it to put it
3066 in the unwind section. */
3068 /* Copy the information from the unwind record into this section. The
3069 data is already in the correct byte order. */
3070 memcpy (where
, unw_rec
, size
);
3071 /* Add the personality address to the image. */
3072 if (unwind
.personality_routine
!= 0)
3074 exp
.X_op
= O_symbol
;
3075 exp
.X_add_symbol
= unwind
.personality_routine
;
3076 exp
.X_add_number
= 0;
3077 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3078 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3079 unwind
.personality_routine
= 0;
3081 obj_elf_previous (0);
3084 free_list_records (unwind
.list
);
3085 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3091 dot_handlerdata (dummy
)
3094 generate_unwind_image ();
3095 demand_empty_rest_of_line ();
3099 dot_unwentry (dummy
)
3102 demand_empty_rest_of_line ();
3113 reg
= e
.X_add_number
- REG_BR
;
3114 if (e
.X_op
== O_register
&& reg
< 8)
3115 add_unwind_entry (output_rp_br (reg
));
3117 as_bad ("First operand not a valid branch register");
3121 dot_savemem (psprel
)
3128 sep
= parse_operand (&e1
);
3130 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3131 sep
= parse_operand (&e2
);
3133 reg1
= e1
.X_add_number
;
3134 val
= e2
.X_add_number
;
3136 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3137 if (e1
.X_op
== O_register
)
3139 if (e2
.X_op
== O_constant
)
3143 case REG_AR
+ AR_BSP
:
3144 add_unwind_entry (output_bsp_when ());
3145 add_unwind_entry ((psprel
3147 : output_bsp_sprel
) (val
));
3149 case REG_AR
+ AR_BSPSTORE
:
3150 add_unwind_entry (output_bspstore_when ());
3151 add_unwind_entry ((psprel
3152 ? output_bspstore_psprel
3153 : output_bspstore_sprel
) (val
));
3155 case REG_AR
+ AR_RNAT
:
3156 add_unwind_entry (output_rnat_when ());
3157 add_unwind_entry ((psprel
3158 ? output_rnat_psprel
3159 : output_rnat_sprel
) (val
));
3161 case REG_AR
+ AR_UNAT
:
3162 add_unwind_entry (output_unat_when ());
3163 add_unwind_entry ((psprel
3164 ? output_unat_psprel
3165 : output_unat_sprel
) (val
));
3167 case REG_AR
+ AR_FPSR
:
3168 add_unwind_entry (output_fpsr_when ());
3169 add_unwind_entry ((psprel
3170 ? output_fpsr_psprel
3171 : output_fpsr_sprel
) (val
));
3173 case REG_AR
+ AR_PFS
:
3174 add_unwind_entry (output_pfs_when ());
3175 add_unwind_entry ((psprel
3177 : output_pfs_sprel
) (val
));
3179 case REG_AR
+ AR_LC
:
3180 add_unwind_entry (output_lc_when ());
3181 add_unwind_entry ((psprel
3183 : output_lc_sprel
) (val
));
3186 add_unwind_entry (output_rp_when ());
3187 add_unwind_entry ((psprel
3189 : output_rp_sprel
) (val
));
3192 add_unwind_entry (output_preds_when ());
3193 add_unwind_entry ((psprel
3194 ? output_preds_psprel
3195 : output_preds_sprel
) (val
));
3198 add_unwind_entry (output_priunat_when_mem ());
3199 add_unwind_entry ((psprel
3200 ? output_priunat_psprel
3201 : output_priunat_sprel
) (val
));
3204 as_bad ("First operand not a valid register");
3208 as_bad (" Second operand not a valid constant");
3211 as_bad ("First operand not a register");
3220 sep
= parse_operand (&e1
);
3222 parse_operand (&e2
);
3224 if (e1
.X_op
!= O_constant
)
3225 as_bad ("First operand to .save.g must be a constant.");
3228 int grmask
= e1
.X_add_number
;
3230 add_unwind_entry (output_gr_mem (grmask
));
3233 int reg
= e2
.X_add_number
- REG_GR
;
3234 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3235 add_unwind_entry (output_gr_gr (grmask
, reg
));
3237 as_bad ("Second operand is an invalid register.");
3248 sep
= parse_operand (&e1
);
3250 if (e1
.X_op
!= O_constant
)
3251 as_bad ("Operand to .save.f must be a constant.");
3253 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3265 sep
= parse_operand (&e1
);
3266 if (e1
.X_op
!= O_constant
)
3268 as_bad ("First operand to .save.b must be a constant.");
3271 brmask
= e1
.X_add_number
;
3275 sep
= parse_operand (&e2
);
3276 reg
= e2
.X_add_number
- REG_GR
;
3277 if (e2
.X_op
!= O_register
|| reg
> 127)
3279 as_bad ("Second operand to .save.b must be a general register.");
3282 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3285 add_unwind_entry (output_br_mem (brmask
));
3287 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3288 ignore_rest_of_line ();
3297 sep
= parse_operand (&e1
);
3299 parse_operand (&e2
);
3301 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3302 as_bad ("Both operands of .save.gf must be constants.");
3305 int grmask
= e1
.X_add_number
;
3306 int frmask
= e2
.X_add_number
;
3307 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3318 sep
= parse_operand (&e
);
3319 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3320 ignore_rest_of_line ();
3322 if (e
.X_op
!= O_constant
)
3323 as_bad ("Operand to .spill must be a constant");
3325 add_unwind_entry (output_spill_base (e
.X_add_number
));
3329 dot_spillreg (dummy
)
3332 int sep
, ab
, xy
, reg
, treg
;
3335 sep
= parse_operand (&e1
);
3338 as_bad ("No second operand to .spillreg");
3342 parse_operand (&e2
);
3344 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3346 as_bad ("First operand to .spillreg must be a preserved register");
3350 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3352 as_bad ("Second operand to .spillreg must be a register");
3356 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3360 dot_spillmem (psprel
)
3366 sep
= parse_operand (&e1
);
3369 as_bad ("Second operand missing");
3373 parse_operand (&e2
);
3375 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3377 as_bad ("First operand to .spill%s must be a preserved register",
3378 psprel
? "psp" : "sp");
3382 if (e2
.X_op
!= O_constant
)
3384 as_bad ("Second operand to .spill%s must be a constant",
3385 psprel
? "psp" : "sp");
3390 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3392 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3396 dot_spillreg_p (dummy
)
3399 int sep
, ab
, xy
, reg
, treg
;
3400 expressionS e1
, e2
, e3
;
3403 sep
= parse_operand (&e1
);
3406 as_bad ("No second and third operand to .spillreg.p");
3410 sep
= parse_operand (&e2
);
3413 as_bad ("No third operand to .spillreg.p");
3417 parse_operand (&e3
);
3419 qp
= e1
.X_add_number
- REG_P
;
3421 if (e1
.X_op
!= O_register
|| qp
> 63)
3423 as_bad ("First operand to .spillreg.p must be a predicate");
3427 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3429 as_bad ("Second operand to .spillreg.p must be a preserved register");
3433 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3435 as_bad ("Third operand to .spillreg.p must be a register");
3439 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3443 dot_spillmem_p (psprel
)
3446 expressionS e1
, e2
, e3
;
3450 sep
= parse_operand (&e1
);
3453 as_bad ("Second operand missing");
3457 parse_operand (&e2
);
3460 as_bad ("Second operand missing");
3464 parse_operand (&e3
);
3466 qp
= e1
.X_add_number
- REG_P
;
3467 if (e1
.X_op
!= O_register
|| qp
> 63)
3469 as_bad ("First operand to .spill%s_p must be a predicate",
3470 psprel
? "psp" : "sp");
3474 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3476 as_bad ("Second operand to .spill%s_p must be a preserved register",
3477 psprel
? "psp" : "sp");
3481 if (e3
.X_op
!= O_constant
)
3483 as_bad ("Third operand to .spill%s_p must be a constant",
3484 psprel
? "psp" : "sp");
3489 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3491 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3495 dot_label_state (dummy
)
3501 if (e
.X_op
!= O_constant
)
3503 as_bad ("Operand to .label_state must be a constant");
3506 add_unwind_entry (output_label_state (e
.X_add_number
));
3510 dot_copy_state (dummy
)
3516 if (e
.X_op
!= O_constant
)
3518 as_bad ("Operand to .copy_state must be a constant");
3521 add_unwind_entry (output_copy_state (e
.X_add_number
));
3531 sep
= parse_operand (&e1
);
3534 as_bad ("Second operand to .unwabi missing");
3537 sep
= parse_operand (&e2
);
3538 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3539 ignore_rest_of_line ();
3541 if (e1
.X_op
!= O_constant
)
3543 as_bad ("First operand to .unwabi must be a constant");
3547 if (e2
.X_op
!= O_constant
)
3549 as_bad ("Second operand to .unwabi must be a constant");
3553 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3557 dot_personality (dummy
)
3562 name
= input_line_pointer
;
3563 c
= get_symbol_end ();
3564 p
= input_line_pointer
;
3565 unwind
.personality_routine
= symbol_find_or_make (name
);
3568 demand_empty_rest_of_line ();
3578 unwind
.proc_start
= expr_build_dot ();
3579 /* Parse names of main and alternate entry points and mark them as
3580 function symbols: */
3584 name
= input_line_pointer
;
3585 c
= get_symbol_end ();
3586 p
= input_line_pointer
;
3587 sym
= symbol_find_or_make (name
);
3588 if (unwind
.proc_start
== 0)
3590 unwind
.proc_start
= sym
;
3592 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3595 if (*input_line_pointer
!= ',')
3597 ++input_line_pointer
;
3599 demand_empty_rest_of_line ();
3602 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3603 unwind
.personality_routine
= 0;
3610 unwind
.prologue
= 0;
3611 unwind
.prologue_mask
= 0;
3613 add_unwind_entry (output_body ());
3614 demand_empty_rest_of_line ();
3618 dot_prologue (dummy
)
3622 int mask
= 0, grsave
;
3624 if (!is_it_end_of_statement ())
3627 sep
= parse_operand (&e1
);
3629 as_bad ("No second operand to .prologue");
3630 sep
= parse_operand (&e2
);
3631 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3632 ignore_rest_of_line ();
3634 if (e1
.X_op
== O_constant
)
3636 mask
= e1
.X_add_number
;
3638 if (e2
.X_op
== O_constant
)
3639 grsave
= e2
.X_add_number
;
3640 else if (e2
.X_op
== O_register
3641 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3644 as_bad ("Second operand not a constant or general register");
3646 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3649 as_bad ("First operand not a constant");
3652 add_unwind_entry (output_prologue ());
3654 unwind
.prologue
= 1;
3655 unwind
.prologue_mask
= mask
;
3664 int bytes_per_address
;
3667 subsegT saved_subseg
;
3669 saved_seg
= now_seg
;
3670 saved_subseg
= now_subseg
;
3673 demand_empty_rest_of_line ();
3675 insn_group_break (1, 0, 0);
3677 /* If there was a .handlerdata, we haven't generated an image yet. */
3678 if (unwind
.info
== 0)
3680 generate_unwind_image ();
3683 subseg_set (md
.last_text_seg
, 0);
3684 unwind
.proc_end
= expr_build_dot ();
3686 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3687 ptr
= frag_more (24);
3688 where
= frag_now_fix () - 24;
3689 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3691 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3692 e
.X_op
= O_pseudo_fixup
;
3693 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3695 e
.X_add_symbol
= unwind
.proc_start
;
3696 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3698 e
.X_op
= O_pseudo_fixup
;
3699 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3701 e
.X_add_symbol
= unwind
.proc_end
;
3702 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
, bytes_per_address
, &e
);
3704 if (unwind
.info
!= 0)
3706 e
.X_op
= O_pseudo_fixup
;
3707 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3709 e
.X_add_symbol
= unwind
.info
;
3710 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2), bytes_per_address
, &e
);
3713 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0, bytes_per_address
);
3715 subseg_set (saved_seg
, saved_subseg
);
3716 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3720 dot_template (template)
3723 CURR_SLOT
.user_template
= template;
3730 int ins
, locs
, outs
, rots
;
3732 if (is_it_end_of_statement ())
3733 ins
= locs
= outs
= rots
= 0;
3736 ins
= get_absolute_expression ();
3737 if (*input_line_pointer
++ != ',')
3739 locs
= get_absolute_expression ();
3740 if (*input_line_pointer
++ != ',')
3742 outs
= get_absolute_expression ();
3743 if (*input_line_pointer
++ != ',')
3745 rots
= get_absolute_expression ();
3747 set_regstack (ins
, locs
, outs
, rots
);
3751 as_bad ("Comma expected");
3752 ignore_rest_of_line ();
3759 unsigned num_regs
, num_alloced
= 0;
3760 struct dynreg
**drpp
, *dr
;
3761 int ch
, base_reg
= 0;
3767 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3768 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3769 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3773 /* First, remove existing names from hash table. */
3774 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3776 hash_delete (md
.dynreg_hash
, dr
->name
);
3780 drpp
= &md
.dynreg
[type
];
3783 start
= input_line_pointer
;
3784 ch
= get_symbol_end ();
3785 *input_line_pointer
= ch
;
3786 len
= (input_line_pointer
- start
);
3789 if (*input_line_pointer
!= '[')
3791 as_bad ("Expected '['");
3794 ++input_line_pointer
; /* skip '[' */
3796 num_regs
= get_absolute_expression ();
3798 if (*input_line_pointer
++ != ']')
3800 as_bad ("Expected ']'");
3805 num_alloced
+= num_regs
;
3809 if (num_alloced
> md
.rot
.num_regs
)
3811 as_bad ("Used more than the declared %d rotating registers",
3817 if (num_alloced
> 96)
3819 as_bad ("Used more than the available 96 rotating registers");
3824 if (num_alloced
> 48)
3826 as_bad ("Used more than the available 48 rotating registers");
3835 name
= obstack_alloc (¬es
, len
+ 1);
3836 memcpy (name
, start
, len
);
3841 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3842 memset (*drpp
, 0, sizeof (*dr
));
3847 dr
->num_regs
= num_regs
;
3848 dr
->base
= base_reg
;
3850 base_reg
+= num_regs
;
3852 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3854 as_bad ("Attempt to redefine register set `%s'", name
);
3858 if (*input_line_pointer
!= ',')
3860 ++input_line_pointer
; /* skip comma */
3863 demand_empty_rest_of_line ();
3867 ignore_rest_of_line ();
3871 dot_byteorder (byteorder
)
3874 target_big_endian
= byteorder
;
3886 option
= input_line_pointer
;
3887 ch
= get_symbol_end ();
3888 if (strcmp (option
, "lsb") == 0)
3889 md
.flags
&= ~EF_IA_64_BE
;
3890 else if (strcmp (option
, "msb") == 0)
3891 md
.flags
|= EF_IA_64_BE
;
3892 else if (strcmp (option
, "abi32") == 0)
3893 md
.flags
&= ~EF_IA_64_ABI64
;
3894 else if (strcmp (option
, "abi64") == 0)
3895 md
.flags
|= EF_IA_64_ABI64
;
3897 as_bad ("Unknown psr option `%s'", option
);
3898 *input_line_pointer
= ch
;
3901 if (*input_line_pointer
!= ',')
3904 ++input_line_pointer
;
3907 demand_empty_rest_of_line ();
3914 as_bad (".alias not implemented yet");
3921 new_logical_line (0, get_absolute_expression ());
3922 demand_empty_rest_of_line ();
3926 parse_section_name ()
3932 if (*input_line_pointer
!= '"')
3934 as_bad ("Missing section name");
3935 ignore_rest_of_line ();
3938 name
= demand_copy_C_string (&len
);
3941 ignore_rest_of_line ();
3945 if (*input_line_pointer
!= ',')
3947 as_bad ("Comma expected after section name");
3948 ignore_rest_of_line ();
3951 ++input_line_pointer
; /* skip comma */
3959 char *name
= parse_section_name ();
3965 obj_elf_previous (0);
3968 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3971 stmt_float_cons (kind
)
3978 case 'd': size
= 8; break;
3979 case 'x': size
= 10; break;
3986 ia64_do_align (size
);
3994 int saved_auto_align
= md
.auto_align
;
3998 md
.auto_align
= saved_auto_align
;
4002 dot_xfloat_cons (kind
)
4005 char *name
= parse_section_name ();
4010 stmt_float_cons (kind
);
4011 obj_elf_previous (0);
4015 dot_xstringer (zero
)
4018 char *name
= parse_section_name ();
4024 obj_elf_previous (0);
4031 int saved_auto_align
= md
.auto_align
;
4032 char *name
= parse_section_name ();
4039 md
.auto_align
= saved_auto_align
;
4040 obj_elf_previous (0);
4044 dot_xfloat_cons_ua (kind
)
4047 int saved_auto_align
= md
.auto_align
;
4048 char *name
= parse_section_name ();
4054 stmt_float_cons (kind
);
4055 md
.auto_align
= saved_auto_align
;
4056 obj_elf_previous (0);
4059 /* .reg.val <regname>,value */
4068 if (reg
.X_op
!= O_register
)
4070 as_bad (_("Register name expected"));
4071 ignore_rest_of_line ();
4073 else if (*input_line_pointer
++ != ',')
4075 as_bad (_("Comma expected"));
4076 ignore_rest_of_line ();
4080 valueT value
= get_absolute_expression ();
4081 int regno
= reg
.X_add_number
;
4082 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4083 as_warn (_("Register value annotation ignored"));
4086 gr_values
[regno
- REG_GR
].known
= 1;
4087 gr_values
[regno
- REG_GR
].value
= value
;
4088 gr_values
[regno
- REG_GR
].path
= md
.path
;
4091 demand_empty_rest_of_line ();
4094 /* select dv checking mode
4099 A stop is inserted when changing modes
4106 if (md
.manual_bundling
)
4107 as_warn (_("Directive invalid within a bundle"));
4109 if (type
== 'E' || type
== 'A')
4110 md
.mode_explicitly_set
= 0;
4112 md
.mode_explicitly_set
= 1;
4119 if (md
.explicit_mode
)
4120 insn_group_break (1, 0, 0);
4121 md
.explicit_mode
= 0;
4125 if (!md
.explicit_mode
)
4126 insn_group_break (1, 0, 0);
4127 md
.explicit_mode
= 1;
4131 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4132 insn_group_break (1, 0, 0);
4133 md
.explicit_mode
= md
.default_explicit_mode
;
4134 md
.mode_explicitly_set
= 0;
4145 for (regno
= 0; regno
< 64; regno
++)
4147 if (mask
& ((valueT
) 1 << regno
))
4149 fprintf (stderr
, "%s p%d", comma
, regno
);
4156 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4157 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4158 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4159 .pred.safe_across_calls p1 [, p2 [,...]]
4168 int p1
= -1, p2
= -1;
4172 if (*input_line_pointer
!= '"')
4174 as_bad (_("Missing predicate relation type"));
4175 ignore_rest_of_line ();
4181 char *form
= demand_copy_C_string (&len
);
4182 if (strcmp (form
, "mutex") == 0)
4184 else if (strcmp (form
, "clear") == 0)
4186 else if (strcmp (form
, "imply") == 0)
4190 as_bad (_("Unrecognized predicate relation type"));
4191 ignore_rest_of_line ();
4195 if (*input_line_pointer
== ',')
4196 ++input_line_pointer
;
4206 if (toupper (*input_line_pointer
) != 'P'
4207 || (regno
= atoi (++input_line_pointer
)) < 0
4210 as_bad (_("Predicate register expected"));
4211 ignore_rest_of_line ();
4214 while (isdigit (*input_line_pointer
))
4215 ++input_line_pointer
;
4222 as_warn (_("Duplicate predicate register ignored"));
4225 /* See if it's a range. */
4226 if (*input_line_pointer
== '-')
4229 ++input_line_pointer
;
4231 if (toupper (*input_line_pointer
) != 'P'
4232 || (regno
= atoi (++input_line_pointer
)) < 0
4235 as_bad (_("Predicate register expected"));
4236 ignore_rest_of_line ();
4239 while (isdigit (*input_line_pointer
))
4240 ++input_line_pointer
;
4244 as_bad (_("Bad register range"));
4245 ignore_rest_of_line ();
4256 if (*input_line_pointer
!= ',')
4258 ++input_line_pointer
;
4267 clear_qp_mutex (mask
);
4268 clear_qp_implies (mask
, (valueT
) 0);
4271 if (count
!= 2 || p1
== -1 || p2
== -1)
4272 as_bad (_("Predicate source and target required"));
4273 else if (p1
== 0 || p2
== 0)
4274 as_bad (_("Use of p0 is not valid in this context"));
4276 add_qp_imply (p1
, p2
);
4281 as_bad (_("At least two PR arguments expected"));
4286 as_bad (_("Use of p0 is not valid in this context"));
4289 add_qp_mutex (mask
);
4292 /* note that we don't override any existing relations */
4295 as_bad (_("At least one PR argument expected"));
4300 fprintf (stderr
, "Safe across calls: ");
4301 print_prmask (mask
);
4302 fprintf (stderr
, "\n");
4304 qp_safe_across_calls
= mask
;
4307 demand_empty_rest_of_line ();
4310 /* .entry label [, label [, ...]]
4311 Hint to DV code that the given labels are to be considered entry points.
4312 Otherwise, only global labels are considered entry points. */
4325 name
= input_line_pointer
;
4326 c
= get_symbol_end ();
4327 symbolP
= symbol_find_or_make (name
);
4329 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4331 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4334 *input_line_pointer
= c
;
4336 c
= *input_line_pointer
;
4339 input_line_pointer
++;
4341 if (*input_line_pointer
== '\n')
4347 demand_empty_rest_of_line ();
4350 /* .mem.offset offset, base
4351 "base" is used to distinguish between offsets from a different base. */
4354 dot_mem_offset (dummy
)
4357 md
.mem_offset
.hint
= 1;
4358 md
.mem_offset
.offset
= get_absolute_expression ();
4359 if (*input_line_pointer
!= ',')
4361 as_bad (_("Comma expected"));
4362 ignore_rest_of_line ();
4365 ++input_line_pointer
;
4366 md
.mem_offset
.base
= get_absolute_expression ();
4367 demand_empty_rest_of_line ();
4370 /* ia64-specific pseudo-ops: */
4371 const pseudo_typeS md_pseudo_table
[] =
4373 { "radix", dot_radix
, 0 },
4374 { "lcomm", s_lcomm_bytes
, 1 },
4375 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4376 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4377 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4378 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4379 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4380 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4381 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4382 { "proc", dot_proc
, 0 },
4383 { "body", dot_body
, 0 },
4384 { "prologue", dot_prologue
, 0 },
4385 { "endp", dot_endp
},
4386 { "file", dwarf2_directive_file
},
4387 { "loc", dwarf2_directive_loc
},
4389 { "fframe", dot_fframe
},
4390 { "vframe", dot_vframe
},
4391 { "vframesp", dot_vframesp
},
4392 { "vframepsp", dot_vframepsp
},
4393 { "save", dot_save
},
4394 { "restore", dot_restore
},
4395 { "restorereg", dot_restorereg
},
4396 { "restorereg.p", dot_restorereg_p
},
4397 { "handlerdata", dot_handlerdata
},
4398 { "unwentry", dot_unwentry
},
4399 { "altrp", dot_altrp
},
4400 { "savesp", dot_savemem
, 0 },
4401 { "savepsp", dot_savemem
, 1 },
4402 { "save.g", dot_saveg
},
4403 { "save.f", dot_savef
},
4404 { "save.b", dot_saveb
},
4405 { "save.gf", dot_savegf
},
4406 { "spill", dot_spill
},
4407 { "spillreg", dot_spillreg
},
4408 { "spillsp", dot_spillmem
, 0 },
4409 { "spillpsp", dot_spillmem
, 1 },
4410 { "spillreg.p", dot_spillreg_p
},
4411 { "spillsp.p", dot_spillmem_p
, 0 },
4412 { "spillpsp.p", dot_spillmem_p
, 1 },
4413 { "label_state", dot_label_state
},
4414 { "copy_state", dot_copy_state
},
4415 { "unwabi", dot_unwabi
},
4416 { "personality", dot_personality
},
4418 { "estate", dot_estate
},
4420 { "mii", dot_template
, 0x0 },
4421 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4422 { "mlx", dot_template
, 0x2 },
4423 { "mmi", dot_template
, 0x4 },
4424 { "mfi", dot_template
, 0x6 },
4425 { "mmf", dot_template
, 0x7 },
4426 { "mib", dot_template
, 0x8 },
4427 { "mbb", dot_template
, 0x9 },
4428 { "bbb", dot_template
, 0xb },
4429 { "mmb", dot_template
, 0xc },
4430 { "mfb", dot_template
, 0xe },
4432 { "lb", dot_scope
, 0 },
4433 { "le", dot_scope
, 1 },
4435 { "align", s_align_bytes
, 0 },
4436 { "regstk", dot_regstk
, 0 },
4437 { "rotr", dot_rot
, DYNREG_GR
},
4438 { "rotf", dot_rot
, DYNREG_FR
},
4439 { "rotp", dot_rot
, DYNREG_PR
},
4440 { "lsb", dot_byteorder
, 0 },
4441 { "msb", dot_byteorder
, 1 },
4442 { "psr", dot_psr
, 0 },
4443 { "alias", dot_alias
, 0 },
4444 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4446 { "xdata1", dot_xdata
, 1 },
4447 { "xdata2", dot_xdata
, 2 },
4448 { "xdata4", dot_xdata
, 4 },
4449 { "xdata8", dot_xdata
, 8 },
4450 { "xreal4", dot_xfloat_cons
, 'f' },
4451 { "xreal8", dot_xfloat_cons
, 'd' },
4452 { "xreal10", dot_xfloat_cons
, 'x' },
4453 { "xstring", dot_xstringer
, 0 },
4454 { "xstringz", dot_xstringer
, 1 },
4456 /* unaligned versions: */
4457 { "xdata2.ua", dot_xdata_ua
, 2 },
4458 { "xdata4.ua", dot_xdata_ua
, 4 },
4459 { "xdata8.ua", dot_xdata_ua
, 8 },
4460 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4461 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4462 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4464 /* annotations/DV checking support */
4465 { "entry", dot_entry
, 0 },
4466 { "mem.offset", dot_mem_offset
},
4467 { "pred.rel", dot_pred_rel
, 0 },
4468 { "pred.rel.clear", dot_pred_rel
, 'c' },
4469 { "pred.rel.imply", dot_pred_rel
, 'i' },
4470 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4471 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4472 { "reg.val", dot_reg_val
},
4473 { "auto", dot_dv_mode
, 'a' },
4474 { "explicit", dot_dv_mode
, 'e' },
4475 { "default", dot_dv_mode
, 'd' },
4480 static const struct pseudo_opcode
4483 void (*handler
) (int);
4488 /* these are more like pseudo-ops, but don't start with a dot */
4489 { "data1", cons
, 1 },
4490 { "data2", cons
, 2 },
4491 { "data4", cons
, 4 },
4492 { "data8", cons
, 8 },
4493 { "real4", stmt_float_cons
, 'f' },
4494 { "real8", stmt_float_cons
, 'd' },
4495 { "real10", stmt_float_cons
, 'x' },
4496 { "string", stringer
, 0 },
4497 { "stringz", stringer
, 1 },
4499 /* unaligned versions: */
4500 { "data2.ua", stmt_cons_ua
, 2 },
4501 { "data4.ua", stmt_cons_ua
, 4 },
4502 { "data8.ua", stmt_cons_ua
, 8 },
4503 { "real4.ua", float_cons
, 'f' },
4504 { "real8.ua", float_cons
, 'd' },
4505 { "real10.ua", float_cons
, 'x' },
4508 /* Declare a register by creating a symbol for it and entering it in
4509 the symbol table. */
4512 declare_register (name
, regnum
)
4519 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4521 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4523 as_fatal ("Inserting \"%s\" into register table failed: %s",
4530 declare_register_set (prefix
, num_regs
, base_regnum
)
4538 for (i
= 0; i
< num_regs
; ++i
)
4540 sprintf (name
, "%s%u", prefix
, i
);
4541 declare_register (name
, base_regnum
+ i
);
4546 operand_width (opnd
)
4547 enum ia64_opnd opnd
;
4549 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4550 unsigned int bits
= 0;
4554 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4555 bits
+= odesc
->field
[i
].bits
;
4561 operand_match (idesc
, index
, e
)
4562 const struct ia64_opcode
*idesc
;
4566 enum ia64_opnd opnd
= idesc
->operands
[index
];
4567 int bits
, relocatable
= 0;
4568 struct insn_fix
*fix
;
4575 case IA64_OPND_AR_CCV
:
4576 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4580 case IA64_OPND_AR_PFS
:
4581 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4586 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4591 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4596 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4600 case IA64_OPND_PR_ROT
:
4601 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4606 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4610 case IA64_OPND_PSR_L
:
4611 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4615 case IA64_OPND_PSR_UM
:
4616 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4621 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4626 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4631 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4635 /* register operands: */
4638 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4639 && e
->X_add_number
< REG_AR
+ 128)
4645 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4646 && e
->X_add_number
< REG_BR
+ 8)
4651 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4652 && e
->X_add_number
< REG_CR
+ 128)
4660 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4661 && e
->X_add_number
< REG_FR
+ 128)
4667 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4668 && e
->X_add_number
< REG_P
+ 64)
4675 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4676 && e
->X_add_number
< REG_GR
+ 128)
4680 case IA64_OPND_R3_2
:
4681 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4682 && e
->X_add_number
< REG_GR
+ 4)
4686 /* indirect operands: */
4687 case IA64_OPND_CPUID_R3
:
4688 case IA64_OPND_DBR_R3
:
4689 case IA64_OPND_DTR_R3
:
4690 case IA64_OPND_ITR_R3
:
4691 case IA64_OPND_IBR_R3
:
4692 case IA64_OPND_MSR_R3
:
4693 case IA64_OPND_PKR_R3
:
4694 case IA64_OPND_PMC_R3
:
4695 case IA64_OPND_PMD_R3
:
4696 case IA64_OPND_RR_R3
:
4697 if (e
->X_op
== O_index
&& e
->X_op_symbol
4698 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4699 == opnd
- IA64_OPND_CPUID_R3
))
4704 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4708 /* immediate operands: */
4709 case IA64_OPND_CNT2a
:
4710 case IA64_OPND_LEN4
:
4711 case IA64_OPND_LEN6
:
4712 bits
= operand_width (idesc
->operands
[index
]);
4713 if (e
->X_op
== O_constant
4714 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4718 case IA64_OPND_CNT2b
:
4719 if (e
->X_op
== O_constant
4720 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4724 case IA64_OPND_CNT2c
:
4725 val
= e
->X_add_number
;
4726 if (e
->X_op
== O_constant
4727 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4732 /* SOR must be an integer multiple of 8 */
4733 if (e
->X_add_number
& 0x7)
4737 if (e
->X_op
== O_constant
&&
4738 (bfd_vma
) e
->X_add_number
<= 96)
4742 case IA64_OPND_IMMU62
:
4743 if (e
->X_op
== O_constant
)
4745 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4750 /* FIXME -- need 62-bit relocation type */
4751 as_bad (_("62-bit relocation not yet implemented"));
4755 case IA64_OPND_IMMU64
:
4756 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4757 || e
->X_op
== O_subtract
)
4759 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4760 fix
->code
= BFD_RELOC_IA64_IMM64
;
4761 if (e
->X_op
!= O_subtract
)
4763 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4764 if (e
->X_op
== O_pseudo_fixup
)
4768 fix
->opnd
= idesc
->operands
[index
];
4771 ++CURR_SLOT
.num_fixups
;
4774 else if (e
->X_op
== O_constant
)
4778 case IA64_OPND_CCNT5
:
4779 case IA64_OPND_CNT5
:
4780 case IA64_OPND_CNT6
:
4781 case IA64_OPND_CPOS6a
:
4782 case IA64_OPND_CPOS6b
:
4783 case IA64_OPND_CPOS6c
:
4784 case IA64_OPND_IMMU2
:
4785 case IA64_OPND_IMMU7a
:
4786 case IA64_OPND_IMMU7b
:
4787 case IA64_OPND_IMMU21
:
4788 case IA64_OPND_IMMU24
:
4789 case IA64_OPND_MBTYPE4
:
4790 case IA64_OPND_MHTYPE8
:
4791 case IA64_OPND_POS6
:
4792 bits
= operand_width (idesc
->operands
[index
]);
4793 if (e
->X_op
== O_constant
4794 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4798 case IA64_OPND_IMMU9
:
4799 bits
= operand_width (idesc
->operands
[index
]);
4800 if (e
->X_op
== O_constant
4801 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4803 int lobits
= e
->X_add_number
& 0x3;
4804 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4805 e
->X_add_number
|= (bfd_vma
) 0x3;
4810 case IA64_OPND_IMM44
:
4811 /* least 16 bits must be zero */
4812 if ((e
->X_add_number
& 0xffff) != 0)
4813 as_warn (_("lower 16 bits of mask ignored"));
4815 if (e
->X_op
== O_constant
4816 && ((e
->X_add_number
>= 0
4817 && e
->X_add_number
< ((bfd_vma
) 1 << 44))
4818 || (e
->X_add_number
< 0
4819 && -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4822 if (e
->X_add_number
>= 0
4823 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4825 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4831 case IA64_OPND_IMM17
:
4832 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4833 if (e
->X_op
== O_constant
4834 && ((e
->X_add_number
>= 0
4835 && e
->X_add_number
< ((bfd_vma
) 1 << 17))
4836 || (e
->X_add_number
< 0
4837 && -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4840 if (e
->X_add_number
>= 0
4841 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4843 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
4849 case IA64_OPND_IMM14
:
4850 case IA64_OPND_IMM22
:
4852 case IA64_OPND_IMM1
:
4853 case IA64_OPND_IMM8
:
4854 case IA64_OPND_IMM8U4
:
4855 case IA64_OPND_IMM8M1
:
4856 case IA64_OPND_IMM8M1U4
:
4857 case IA64_OPND_IMM8M1U8
:
4858 case IA64_OPND_IMM9a
:
4859 case IA64_OPND_IMM9b
:
4860 bits
= operand_width (idesc
->operands
[index
]);
4861 if (relocatable
&& (e
->X_op
== O_symbol
4862 || e
->X_op
== O_subtract
4863 || e
->X_op
== O_pseudo_fixup
))
4865 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4867 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4868 fix
->code
= BFD_RELOC_IA64_IMM14
;
4870 fix
->code
= BFD_RELOC_IA64_IMM22
;
4872 if (e
->X_op
!= O_subtract
)
4874 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4875 if (e
->X_op
== O_pseudo_fixup
)
4879 fix
->opnd
= idesc
->operands
[index
];
4882 ++CURR_SLOT
.num_fixups
;
4885 else if (e
->X_op
!= O_constant
4886 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4889 if (opnd
== IA64_OPND_IMM8M1U4
)
4891 /* Zero is not valid for unsigned compares that take an adjusted
4892 constant immediate range. */
4893 if (e
->X_add_number
== 0)
4896 /* Sign-extend 32-bit unsigned numbers, so that the following range
4897 checks will work. */
4898 val
= e
->X_add_number
;
4899 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4900 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4901 val
= ((val
<< 32) >> 32);
4903 /* Check for 0x100000000. This is valid because
4904 0x100000000-1 is the same as ((uint32_t) -1). */
4905 if (val
== ((bfd_signed_vma
) 1 << 32))
4910 else if (opnd
== IA64_OPND_IMM8M1U8
)
4912 /* Zero is not valid for unsigned compares that take an adjusted
4913 constant immediate range. */
4914 if (e
->X_add_number
== 0)
4917 /* Check for 0x10000000000000000. */
4918 if (e
->X_op
== O_big
)
4920 if (generic_bignum
[0] == 0
4921 && generic_bignum
[1] == 0
4922 && generic_bignum
[2] == 0
4923 && generic_bignum
[3] == 0
4924 && generic_bignum
[4] == 1)
4930 val
= e
->X_add_number
- 1;
4932 else if (opnd
== IA64_OPND_IMM8M1
)
4933 val
= e
->X_add_number
- 1;
4934 else if (opnd
== IA64_OPND_IMM8U4
)
4936 /* Sign-extend 32-bit unsigned numbers, so that the following range
4937 checks will work. */
4938 val
= e
->X_add_number
;
4939 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4940 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4941 val
= ((val
<< 32) >> 32);
4944 val
= e
->X_add_number
;
4946 if ((val
>= 0 && val
< ((bfd_vma
) 1 << (bits
- 1)))
4947 || (val
< 0 && -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4951 case IA64_OPND_INC3
:
4952 /* +/- 1, 4, 8, 16 */
4953 val
= e
->X_add_number
;
4956 if (e
->X_op
== O_constant
4957 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4961 case IA64_OPND_TGT25
:
4962 case IA64_OPND_TGT25b
:
4963 case IA64_OPND_TGT25c
:
4964 case IA64_OPND_TGT64
:
4965 if (e
->X_op
== O_symbol
)
4967 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4968 if (opnd
== IA64_OPND_TGT25
)
4969 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4970 else if (opnd
== IA64_OPND_TGT25b
)
4971 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4972 else if (opnd
== IA64_OPND_TGT25c
)
4973 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4974 else if (opnd
== IA64_OPND_TGT64
)
4975 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
4979 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4980 fix
->opnd
= idesc
->operands
[index
];
4983 ++CURR_SLOT
.num_fixups
;
4986 case IA64_OPND_TAG13
:
4987 case IA64_OPND_TAG13b
:
4994 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4995 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
4996 fix
->opnd
= idesc
->operands
[index
];
4999 ++CURR_SLOT
.num_fixups
;
5019 memset (e
, 0, sizeof (*e
));
5022 if (*input_line_pointer
!= '}')
5024 sep
= *input_line_pointer
++;
5028 if (!md
.manual_bundling
)
5029 as_warn ("Found '}' when manual bundling is off");
5031 CURR_SLOT
.manual_bundling_off
= 1;
5032 md
.manual_bundling
= 0;
5038 /* Returns the next entry in the opcode table that matches the one in
5039 IDESC, and frees the entry in IDESC. If no matching entry is
5040 found, NULL is returned instead. */
5042 static struct ia64_opcode
*
5043 get_next_opcode (struct ia64_opcode
*idesc
)
5045 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5046 ia64_free_opcode (idesc
);
5050 /* Parse the operands for the opcode and find the opcode variant that
5051 matches the specified operands, or NULL if no match is possible. */
5053 static struct ia64_opcode
*
5054 parse_operands (idesc
)
5055 struct ia64_opcode
*idesc
;
5057 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5059 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5061 char *first_arg
= 0, *end
, *saved_input_pointer
;
5064 assert (strlen (idesc
->name
) <= 128);
5066 strcpy (mnemonic
, idesc
->name
);
5067 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5069 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5070 can't parse the first operand until we have parsed the
5071 remaining operands of the "alloc" instruction. */
5073 first_arg
= input_line_pointer
;
5074 end
= strchr (input_line_pointer
, '=');
5077 as_bad ("Expected separator `='");
5080 input_line_pointer
= end
+ 1;
5085 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5087 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5088 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5093 if (sep
!= '=' && sep
!= ',')
5098 if (num_outputs
> 0)
5099 as_bad ("Duplicate equal sign (=) in instruction");
5101 num_outputs
= i
+ 1;
5106 as_bad ("Illegal operand separator `%c'", sep
);
5110 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5112 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5113 know (strcmp (idesc
->name
, "alloc") == 0);
5114 if (num_operands
== 5 /* first_arg not included in this count! */
5115 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5116 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5117 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5118 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5120 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5121 CURR_SLOT
.opnd
[3].X_add_number
,
5122 CURR_SLOT
.opnd
[4].X_add_number
,
5123 CURR_SLOT
.opnd
[5].X_add_number
);
5125 /* now we can parse the first arg: */
5126 saved_input_pointer
= input_line_pointer
;
5127 input_line_pointer
= first_arg
;
5128 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5130 --num_outputs
; /* force error */
5131 input_line_pointer
= saved_input_pointer
;
5133 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5134 CURR_SLOT
.opnd
[3].X_add_number
5135 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5136 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5140 highest_unmatched_operand
= 0;
5141 expected_operand
= idesc
->operands
[0];
5142 for (; idesc
; idesc
= get_next_opcode (idesc
))
5144 if (num_outputs
!= idesc
->num_outputs
)
5145 continue; /* mismatch in # of outputs */
5147 CURR_SLOT
.num_fixups
= 0;
5148 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5149 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5152 if (i
!= num_operands
)
5154 if (i
> highest_unmatched_operand
)
5156 highest_unmatched_operand
= i
;
5157 expected_operand
= idesc
->operands
[i
];
5162 if (num_operands
< NELEMS (idesc
->operands
)
5163 && idesc
->operands
[num_operands
])
5164 continue; /* mismatch in number of arguments */
5170 if (expected_operand
)
5171 as_bad ("Operand %u of `%s' should be %s",
5172 highest_unmatched_operand
+ 1, mnemonic
,
5173 elf64_ia64_operands
[expected_operand
].desc
);
5175 as_bad ("Operand mismatch");
5181 /* Keep track of state necessary to determine whether a NOP is necessary
5182 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5183 detect a case where additional NOPs may be necessary. */
5185 errata_nop_necessary_p (slot
, insn_unit
)
5187 enum ia64_unit insn_unit
;
5190 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5191 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5192 struct ia64_opcode
*idesc
= slot
->idesc
;
5194 /* Test whether this could be the first insn in a problematic sequence. */
5195 if (insn_unit
== IA64_UNIT_F
)
5197 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5198 if (idesc
->operands
[i
] == IA64_OPND_P1
5199 || idesc
->operands
[i
] == IA64_OPND_P2
)
5201 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5204 this_group
->p_reg_set
[regno
] = 1;
5208 /* Test whether this could be the second insn in a problematic sequence. */
5209 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5210 && prev_group
->p_reg_set
[slot
->qp_regno
])
5212 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5213 if (idesc
->operands
[i
] == IA64_OPND_R1
5214 || idesc
->operands
[i
] == IA64_OPND_R2
5215 || idesc
->operands
[i
] == IA64_OPND_R3
)
5217 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5220 if (strncmp (idesc
->name
, "add", 3) != 0
5221 && strncmp (idesc
->name
, "sub", 3) != 0
5222 && strncmp (idesc
->name
, "shladd", 6) != 0
5223 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5224 this_group
->g_reg_set_conditionally
[regno
] = 1;
5228 /* Test whether this could be the third insn in a problematic sequence. */
5229 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5231 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5232 idesc
->operands
[i
] == IA64_OPND_R3
5233 /* For mov indirect. */
5234 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5235 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5236 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5237 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5238 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5239 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5240 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5241 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5243 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5244 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5245 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5246 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5248 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5251 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5253 if (strcmp (idesc
->name
, "fc") != 0
5254 && strcmp (idesc
->name
, "tak") != 0
5255 && strcmp (idesc
->name
, "thash") != 0
5256 && strcmp (idesc
->name
, "tpa") != 0
5257 && strcmp (idesc
->name
, "ttag") != 0
5258 && strncmp (idesc
->name
, "ptr", 3) != 0
5259 && strncmp (idesc
->name
, "ptc", 3) != 0
5260 && strncmp (idesc
->name
, "probe", 5) != 0)
5263 if (prev_group
->g_reg_set_conditionally
[regno
])
5271 build_insn (slot
, insnp
)
5275 const struct ia64_operand
*odesc
, *o2desc
;
5276 struct ia64_opcode
*idesc
= slot
->idesc
;
5277 bfd_signed_vma insn
, val
;
5281 insn
= idesc
->opcode
| slot
->qp_regno
;
5283 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5285 if (slot
->opnd
[i
].X_op
== O_register
5286 || slot
->opnd
[i
].X_op
== O_constant
5287 || slot
->opnd
[i
].X_op
== O_index
)
5288 val
= slot
->opnd
[i
].X_add_number
;
5289 else if (slot
->opnd
[i
].X_op
== O_big
)
5291 /* This must be the value 0x10000000000000000. */
5292 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5298 switch (idesc
->operands
[i
])
5300 case IA64_OPND_IMMU64
:
5301 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5302 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5303 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5304 | (((val
>> 63) & 0x1) << 36));
5307 case IA64_OPND_IMMU62
:
5308 val
&= 0x3fffffffffffffffULL
;
5309 if (val
!= slot
->opnd
[i
].X_add_number
)
5310 as_warn (_("Value truncated to 62 bits"));
5311 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5312 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5315 case IA64_OPND_TGT64
:
5317 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5318 insn
|= ((((val
>> 59) & 0x1) << 36)
5319 | (((val
>> 0) & 0xfffff) << 13));
5350 case IA64_OPND_R3_2
:
5351 case IA64_OPND_CPUID_R3
:
5352 case IA64_OPND_DBR_R3
:
5353 case IA64_OPND_DTR_R3
:
5354 case IA64_OPND_ITR_R3
:
5355 case IA64_OPND_IBR_R3
:
5357 case IA64_OPND_MSR_R3
:
5358 case IA64_OPND_PKR_R3
:
5359 case IA64_OPND_PMC_R3
:
5360 case IA64_OPND_PMD_R3
:
5361 case IA64_OPND_RR_R3
:
5369 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5370 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5372 as_bad_where (slot
->src_file
, slot
->src_line
,
5373 "Bad operand value: %s", err
);
5374 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5376 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5377 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5379 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5380 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5382 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5383 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5384 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5386 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5387 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5397 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5398 unsigned int manual_bundling
= 0;
5399 enum ia64_unit required_unit
, insn_unit
= 0;
5400 enum ia64_insn_type type
[3], insn_type
;
5401 unsigned int template, orig_template
;
5402 bfd_vma insn
[3] = { -1, -1, -1 };
5403 struct ia64_opcode
*idesc
;
5404 int end_of_insn_group
= 0, user_template
= -1;
5405 int n
, i
, j
, first
, curr
;
5406 unw_rec_list
*ptr
, *prev
;
5407 bfd_vma t0
= 0, t1
= 0;
5408 struct label_fix
*lfix
;
5409 struct insn_fix
*ifix
;
5414 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5415 know (first
>= 0 & first
< NUM_SLOTS
);
5416 n
= MIN (3, md
.num_slots_in_use
);
5418 /* Determine template: user user_template if specified, best match
5421 if (md
.slot
[first
].user_template
>= 0)
5422 user_template
= template = md
.slot
[first
].user_template
;
5425 /* Auto select appropriate template. */
5426 memset (type
, 0, sizeof (type
));
5428 for (i
= 0; i
< n
; ++i
)
5430 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5432 type
[i
] = md
.slot
[curr
].idesc
->type
;
5433 curr
= (curr
+ 1) % NUM_SLOTS
;
5435 template = best_template
[type
[0]][type
[1]][type
[2]];
5438 /* initialize instructions with appropriate nops: */
5439 for (i
= 0; i
< 3; ++i
)
5440 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5444 /* now fill in slots with as many insns as possible: */
5446 idesc
= md
.slot
[curr
].idesc
;
5447 end_of_insn_group
= 0;
5448 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5450 /* Set the slot number for prologue/body records now as those
5451 refer to the current point, not the point after the
5452 instruction has been issued: */
5453 /* Don't try to delete prologue/body records here, as that will cause
5454 them to also be deleted from the master list of unwind records. */
5455 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5456 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5457 || ptr
->r
.type
== body
)
5459 ptr
->slot_number
= (unsigned long) f
+ i
;
5460 ptr
->slot_frag
= frag_now
;
5463 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5465 if (manual_bundling
&& i
!= 2)
5466 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5467 "`%s' must be last in bundle", idesc
->name
);
5471 if (idesc
->flags
& IA64_OPCODE_LAST
)
5473 int required_slot
, required_template
;
5475 /* If we need a stop bit after an M slot, our only choice is
5476 template 5 (M;;MI). If we need a stop bit after a B
5477 slot, our only choice is to place it at the end of the
5478 bundle, because the only available templates are MIB,
5479 MBB, BBB, MMB, and MFB. We don't handle anything other
5480 than M and B slots because these are the only kind of
5481 instructions that can have the IA64_OPCODE_LAST bit set. */
5482 required_template
= template;
5483 switch (idesc
->type
)
5487 required_template
= 5;
5495 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5496 "Internal error: don't know how to force %s to end"
5497 "of instruction group", idesc
->name
);
5501 if (manual_bundling
&& i
!= required_slot
)
5502 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5503 "`%s' must be last in instruction group",
5505 if (required_slot
< i
)
5506 /* Can't fit this instruction. */
5510 if (required_template
!= template)
5512 /* If we switch the template, we need to reset the NOPs
5513 after slot i. The slot-types of the instructions ahead
5514 of i never change, so we don't need to worry about
5515 changing NOPs in front of this slot. */
5516 for (j
= i
; j
< 3; ++j
)
5517 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5519 template = required_template
;
5521 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5523 if (manual_bundling_on
)
5524 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5525 "Label must be first in a bundle");
5526 /* This insn must go into the first slot of a bundle. */
5530 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5531 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5533 if (manual_bundling_on
)
5536 manual_bundling
= 1;
5538 break; /* need to start a new bundle */
5541 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5543 /* We need an instruction group boundary in the middle of a
5544 bundle. See if we can switch to an other template with
5545 an appropriate boundary. */
5547 orig_template
= template;
5548 if (i
== 1 && (user_template
== 4
5549 || (user_template
< 0
5550 && (ia64_templ_desc
[template].exec_unit
[0]
5554 end_of_insn_group
= 0;
5556 else if (i
== 2 && (user_template
== 0
5557 || (user_template
< 0
5558 && (ia64_templ_desc
[template].exec_unit
[1]
5560 /* This test makes sure we don't switch the template if
5561 the next instruction is one that needs to be first in
5562 an instruction group. Since all those instructions are
5563 in the M group, there is no way such an instruction can
5564 fit in this bundle even if we switch the template. The
5565 reason we have to check for this is that otherwise we
5566 may end up generating "MI;;I M.." which has the deadly
5567 effect that the second M instruction is no longer the
5568 first in the bundle! --davidm 99/12/16 */
5569 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5572 end_of_insn_group
= 0;
5574 else if (curr
!= first
)
5575 /* can't fit this insn */
5578 if (template != orig_template
)
5579 /* if we switch the template, we need to reset the NOPs
5580 after slot i. The slot-types of the instructions ahead
5581 of i never change, so we don't need to worry about
5582 changing NOPs in front of this slot. */
5583 for (j
= i
; j
< 3; ++j
)
5584 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5586 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5588 /* resolve dynamic opcodes such as "break" and "nop": */
5589 if (idesc
->type
== IA64_TYPE_DYN
)
5591 if ((strcmp (idesc
->name
, "nop") == 0)
5592 || (strcmp (idesc
->name
, "break") == 0))
5593 insn_unit
= required_unit
;
5594 else if (strcmp (idesc
->name
, "chk.s") == 0)
5596 insn_unit
= IA64_UNIT_M
;
5597 if (required_unit
== IA64_UNIT_I
)
5598 insn_unit
= IA64_UNIT_I
;
5601 as_fatal ("emit_one_bundle: unexpected dynamic op");
5603 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5604 ia64_free_opcode (idesc
);
5605 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5607 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5612 insn_type
= idesc
->type
;
5613 insn_unit
= IA64_UNIT_NIL
;
5617 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5618 insn_unit
= required_unit
;
5620 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5621 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5622 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5623 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5624 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5629 if (insn_unit
!= required_unit
)
5631 if (required_unit
== IA64_UNIT_L
5632 && insn_unit
== IA64_UNIT_I
5633 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5635 /* we got ourselves an MLX template but the current
5636 instruction isn't an X-unit, or an I-unit instruction
5637 that can go into the X slot of an MLX template. Duh. */
5638 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5640 as_bad_where (md
.slot
[curr
].src_file
,
5641 md
.slot
[curr
].src_line
,
5642 "`%s' can't go in X slot of "
5643 "MLX template", idesc
->name
);
5644 /* drop this insn so we don't livelock: */
5645 --md
.num_slots_in_use
;
5649 continue; /* try next slot */
5652 if (debug_type
== DEBUG_DWARF2
)
5656 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
5657 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5660 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
5661 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5663 build_insn (md
.slot
+ curr
, insn
+ i
);
5665 /* Set slot counts for non prologue/body unwind records. */
5666 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5667 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5668 && ptr
->r
.type
!= body
)
5670 ptr
->slot_number
= (unsigned long) f
+ i
;
5671 ptr
->slot_frag
= frag_now
;
5673 md
.slot
[curr
].unwind_record
= NULL
;
5675 if (required_unit
== IA64_UNIT_L
)
5678 /* skip one slot for long/X-unit instructions */
5681 --md
.num_slots_in_use
;
5683 /* now is a good time to fix up the labels for this insn: */
5684 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5686 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5687 symbol_set_frag (lfix
->sym
, frag_now
);
5689 /* and fix up the tags also. */
5690 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
5692 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
5693 symbol_set_frag (lfix
->sym
, frag_now
);
5696 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5698 ifix
= md
.slot
[curr
].fixup
+ j
;
5699 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 4,
5700 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5701 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5702 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5703 fix
->fx_file
= md
.slot
[curr
].src_file
;
5704 fix
->fx_line
= md
.slot
[curr
].src_line
;
5707 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5709 if (end_of_insn_group
)
5711 md
.group_idx
= (md
.group_idx
+ 1) % 3;
5712 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
5716 ia64_free_opcode (md
.slot
[curr
].idesc
);
5717 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5718 md
.slot
[curr
].user_template
= -1;
5720 if (manual_bundling_off
)
5722 manual_bundling
= 0;
5725 curr
= (curr
+ 1) % NUM_SLOTS
;
5726 idesc
= md
.slot
[curr
].idesc
;
5728 if (manual_bundling
)
5730 if (md
.num_slots_in_use
> 0)
5731 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5732 "`%s' does not fit into %s template",
5733 idesc
->name
, ia64_templ_desc
[template].name
);
5735 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5736 "Missing '}' at end of file");
5738 know (md
.num_slots_in_use
< NUM_SLOTS
);
5740 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5741 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5743 number_to_chars_littleendian (f
+ 0, t0
, 8);
5744 number_to_chars_littleendian (f
+ 8, t1
, 8);
5746 unwind
.next_slot_number
= (unsigned long) f
+ 16;
5747 unwind
.next_slot_frag
= frag_now
;
5751 md_parse_option (c
, arg
)
5757 /* Switches from the Intel assembler. */
5759 if (strcmp (arg
, "ilp64") == 0
5760 || strcmp (arg
, "lp64") == 0
5761 || strcmp (arg
, "p64") == 0)
5763 md
.flags
|= EF_IA_64_ABI64
;
5765 else if (strcmp (arg
, "ilp32") == 0)
5767 md
.flags
&= ~EF_IA_64_ABI64
;
5769 else if (strcmp (arg
, "le") == 0)
5771 md
.flags
&= ~EF_IA_64_BE
;
5773 else if (strcmp (arg
, "be") == 0)
5775 md
.flags
|= EF_IA_64_BE
;
5782 if (strcmp (arg
, "so") == 0)
5784 /* Suppress signon message. */
5786 else if (strcmp (arg
, "pi") == 0)
5788 /* Reject privileged instructions. FIXME */
5790 else if (strcmp (arg
, "us") == 0)
5792 /* Allow union of signed and unsigned range. FIXME */
5794 else if (strcmp (arg
, "close_fcalls") == 0)
5796 /* Do not resolve global function calls. */
5803 /* temp[="prefix"] Insert temporary labels into the object file
5804 symbol table prefixed by "prefix".
5805 Default prefix is ":temp:".
5810 /* ??? Conflicts with gas' listing option. */
5811 /* indirect=<tgt> Assume unannotated indirect branches behavior
5812 according to <tgt> --
5813 exit: branch out from the current context (default)
5814 labels: all labels in context may be branch targets
5819 /* -X conflicts with an ignored option, use -x instead */
5821 if (!arg
|| strcmp (arg
, "explicit") == 0)
5823 /* set default mode to explicit */
5824 md
.default_explicit_mode
= 1;
5827 else if (strcmp (arg
, "auto") == 0)
5829 md
.default_explicit_mode
= 0;
5831 else if (strcmp (arg
, "debug") == 0)
5835 else if (strcmp (arg
, "debugx") == 0)
5837 md
.default_explicit_mode
= 1;
5842 as_bad (_("Unrecognized option '-x%s'"), arg
);
5847 /* nops Print nops statistics. */
5850 /* GNU specific switches for gcc. */
5851 case OPTION_MCONSTANT_GP
:
5852 md
.flags
|= EF_IA_64_CONS_GP
;
5855 case OPTION_MAUTO_PIC
:
5856 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
5867 md_show_usage (stream
)
5872 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
5873 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
5874 -x | -xexplicit turn on dependency violation checking (default)\n\
5875 -xauto automagically remove dependency violations\n\
5876 -xdebug debug dependency violation checker\n"),
5880 /* Return true if TYPE fits in TEMPL at SLOT. */
5883 match (int templ
, int type
, int slot
)
5885 enum ia64_unit unit
;
5888 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5891 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5893 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5895 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5896 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5897 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5898 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5899 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5900 default: result
= 0; break;
5905 /* Add a bit of extra goodness if a nop of type F or B would fit
5906 in TEMPL at SLOT. */
5909 extra_goodness (int templ
, int slot
)
5911 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
5913 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
5918 /* This function is called once, at assembler startup time. It sets
5919 up all the tables, etc. that the MD part of the assembler will need
5920 that can be determined before arguments are parsed. */
5924 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
5929 md
.explicit_mode
= md
.default_explicit_mode
;
5931 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5933 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
5934 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5935 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5936 &zero_address_frag
);
5938 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5939 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5940 &zero_address_frag
);
5942 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5943 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5944 &zero_address_frag
);
5946 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5947 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5948 &zero_address_frag
);
5950 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5951 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5952 &zero_address_frag
);
5954 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5955 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5956 &zero_address_frag
);
5958 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5959 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5960 &zero_address_frag
);
5962 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5963 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5964 &zero_address_frag
);
5966 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5967 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5968 &zero_address_frag
);
5970 /* Compute the table of best templates. We compute goodness as a
5971 base 4 value, in which each match counts for 3, each F counts
5972 for 2, each B counts for 1. This should maximize the number of
5973 F and B nops in the chosen bundles, which is good because these
5974 pipelines are least likely to be overcommitted. */
5975 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
5976 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
5977 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
5980 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
5983 if (match (t
, i
, 0))
5985 if (match (t
, j
, 1))
5987 if (match (t
, k
, 2))
5988 goodness
= 3 + 3 + 3;
5990 goodness
= 3 + 3 + extra_goodness (t
, 2);
5992 else if (match (t
, j
, 2))
5993 goodness
= 3 + 3 + extra_goodness (t
, 1);
5997 goodness
+= extra_goodness (t
, 1);
5998 goodness
+= extra_goodness (t
, 2);
6001 else if (match (t
, i
, 1))
6003 if (match (t
, j
, 2))
6006 goodness
= 3 + extra_goodness (t
, 2);
6008 else if (match (t
, i
, 2))
6009 goodness
= 3 + extra_goodness (t
, 1);
6011 if (goodness
> best
)
6014 best_template
[i
][j
][k
] = t
;
6019 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6020 md
.slot
[i
].user_template
= -1;
6022 md
.pseudo_hash
= hash_new ();
6023 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6025 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6026 (void *) (pseudo_opcode
+ i
));
6028 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6029 pseudo_opcode
[i
].name
, err
);
6032 md
.reg_hash
= hash_new ();
6033 md
.dynreg_hash
= hash_new ();
6034 md
.const_hash
= hash_new ();
6035 md
.entry_hash
= hash_new ();
6037 /* general registers: */
6040 for (i
= 0; i
< total
; ++i
)
6042 sprintf (name
, "r%d", i
- REG_GR
);
6043 md
.regsym
[i
] = declare_register (name
, i
);
6046 /* floating point registers: */
6048 for (; i
< total
; ++i
)
6050 sprintf (name
, "f%d", i
- REG_FR
);
6051 md
.regsym
[i
] = declare_register (name
, i
);
6054 /* application registers: */
6057 for (; i
< total
; ++i
)
6059 sprintf (name
, "ar%d", i
- REG_AR
);
6060 md
.regsym
[i
] = declare_register (name
, i
);
6063 /* control registers: */
6066 for (; i
< total
; ++i
)
6068 sprintf (name
, "cr%d", i
- REG_CR
);
6069 md
.regsym
[i
] = declare_register (name
, i
);
6072 /* predicate registers: */
6074 for (; i
< total
; ++i
)
6076 sprintf (name
, "p%d", i
- REG_P
);
6077 md
.regsym
[i
] = declare_register (name
, i
);
6080 /* branch registers: */
6082 for (; i
< total
; ++i
)
6084 sprintf (name
, "b%d", i
- REG_BR
);
6085 md
.regsym
[i
] = declare_register (name
, i
);
6088 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6089 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6090 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6091 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6092 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6093 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6094 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6096 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6098 regnum
= indirect_reg
[i
].regnum
;
6099 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6102 /* define synonyms for application registers: */
6103 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6104 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6105 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6107 /* define synonyms for control registers: */
6108 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6109 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6110 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6112 declare_register ("gp", REG_GR
+ 1);
6113 declare_register ("sp", REG_GR
+ 12);
6114 declare_register ("rp", REG_BR
+ 0);
6116 /* pseudo-registers used to specify unwind info: */
6117 declare_register ("psp", REG_PSP
);
6119 declare_register_set ("ret", 4, REG_GR
+ 8);
6120 declare_register_set ("farg", 8, REG_FR
+ 8);
6121 declare_register_set ("fret", 8, REG_FR
+ 8);
6123 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6125 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6126 (PTR
) (const_bits
+ i
));
6128 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6132 /* Set the architecture and machine depending on defaults and command line
6134 if (md
.flags
& EF_IA_64_ABI64
)
6135 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6137 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6140 as_warn (_("Could not set architecture and machine"));
6142 md
.mem_offset
.hint
= 0;
6145 md
.entry_labels
= NULL
;
6148 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6149 because that is called after md_parse_option which is where we do the
6150 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6151 default endianness. */
6154 ia64_init (argc
, argv
)
6158 md
.flags
= EF_IA_64_ABI64
;
6159 if (TARGET_BYTES_BIG_ENDIAN
)
6160 md
.flags
|= EF_IA_64_BE
;
6163 /* Return a string for the target object file format. */
6166 ia64_target_format ()
6168 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6170 if (md
.flags
& EF_IA_64_BE
)
6172 if (md
.flags
& EF_IA_64_ABI64
)
6173 return "elf64-ia64-big";
6175 return "elf32-ia64-big";
6179 if (md
.flags
& EF_IA_64_ABI64
)
6180 return "elf64-ia64-little";
6182 return "elf32-ia64-little";
6186 return "unknown-format";
6190 ia64_end_of_source ()
6192 /* terminate insn group upon reaching end of file: */
6193 insn_group_break (1, 0, 0);
6195 /* emits slots we haven't written yet: */
6196 ia64_flush_insns ();
6198 bfd_set_private_flags (stdoutput
, md
.flags
);
6200 if (debug_type
== DEBUG_DWARF2
)
6203 md
.mem_offset
.hint
= 0;
6209 if (md
.qp
.X_op
== O_register
)
6210 as_bad ("qualifying predicate not followed by instruction");
6211 md
.qp
.X_op
= O_absent
;
6213 if (ignore_input ())
6216 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6218 if (md
.detect_dv
&& !md
.explicit_mode
)
6219 as_warn (_("Explicit stops are ignored in auto mode"));
6221 insn_group_break (1, 0, 0);
6225 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6227 static int defining_tag
= 0;
6230 ia64_unrecognized_line (ch
)
6236 expression (&md
.qp
);
6237 if (*input_line_pointer
++ != ')')
6239 as_bad ("Expected ')'");
6242 if (md
.qp
.X_op
!= O_register
)
6244 as_bad ("Qualifying predicate expected");
6247 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6249 as_bad ("Predicate register expected");
6255 if (md
.manual_bundling
)
6256 as_warn ("Found '{' when manual bundling is already turned on");
6258 CURR_SLOT
.manual_bundling_on
= 1;
6259 md
.manual_bundling
= 1;
6261 /* Bundling is only acceptable in explicit mode
6262 or when in default automatic mode. */
6263 if (md
.detect_dv
&& !md
.explicit_mode
)
6265 if (!md
.mode_explicitly_set
6266 && !md
.default_explicit_mode
)
6269 as_warn (_("Found '{' after explicit switch to automatic mode"));
6274 if (!md
.manual_bundling
)
6275 as_warn ("Found '}' when manual bundling is off");
6277 PREV_SLOT
.manual_bundling_off
= 1;
6278 md
.manual_bundling
= 0;
6280 /* switch back to automatic mode, if applicable */
6283 && !md
.mode_explicitly_set
6284 && !md
.default_explicit_mode
)
6287 /* Allow '{' to follow on the same line. We also allow ";;", but that
6288 happens automatically because ';' is an end of line marker. */
6290 if (input_line_pointer
[0] == '{')
6292 input_line_pointer
++;
6293 return ia64_unrecognized_line ('{');
6296 demand_empty_rest_of_line ();
6305 if (md
.qp
.X_op
== O_register
)
6307 as_bad ("Tag must come before qualifying predicate.");
6310 s
= input_line_pointer
;
6311 c
= get_symbol_end ();
6314 /* Put ':' back for error messages' sake. */
6315 *input_line_pointer
++ = ':';
6316 as_bad ("Expected ':'");
6322 /* Put ':' back for error messages' sake. */
6323 *input_line_pointer
++ = ':';
6324 if (*input_line_pointer
++ != ']')
6326 as_bad ("Expected ']'");
6331 as_bad ("Tag name expected");
6341 /* Not a valid line. */
6346 ia64_frob_label (sym
)
6349 struct label_fix
*fix
;
6351 /* Tags need special handling since they are not bundle breaks like
6355 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6357 fix
->next
= CURR_SLOT
.tag_fixups
;
6358 CURR_SLOT
.tag_fixups
= fix
;
6363 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6365 md
.last_text_seg
= now_seg
;
6366 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6368 fix
->next
= CURR_SLOT
.label_fixups
;
6369 CURR_SLOT
.label_fixups
= fix
;
6371 /* Keep track of how many code entry points we've seen. */
6372 if (md
.path
== md
.maxpaths
)
6375 md
.entry_labels
= (const char **)
6376 xrealloc ((void *) md
.entry_labels
,
6377 md
.maxpaths
* sizeof (char *));
6379 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6384 ia64_flush_pending_output ()
6386 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6388 /* ??? This causes many unnecessary stop bits to be emitted.
6389 Unfortunately, it isn't clear if it is safe to remove this. */
6390 insn_group_break (1, 0, 0);
6391 ia64_flush_insns ();
6395 /* Do ia64-specific expression optimization. All that's done here is
6396 to transform index expressions that are either due to the indexing
6397 of rotating registers or due to the indexing of indirect register
6400 ia64_optimize_expr (l
, op
, r
)
6409 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6411 num_regs
= (l
->X_add_number
>> 16);
6412 if ((unsigned) r
->X_add_number
>= num_regs
)
6415 as_bad ("No current frame");
6417 as_bad ("Index out of range 0..%u", num_regs
- 1);
6418 r
->X_add_number
= 0;
6420 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6423 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6425 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6426 || l
->X_add_number
== IND_MEM
)
6428 as_bad ("Indirect register set name expected");
6429 l
->X_add_number
= IND_CPUID
;
6432 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6433 l
->X_add_number
= r
->X_add_number
;
6441 ia64_parse_name (name
, e
)
6445 struct const_desc
*cdesc
;
6446 struct dynreg
*dr
= 0;
6447 unsigned int regnum
;
6451 /* first see if NAME is a known register name: */
6452 sym
= hash_find (md
.reg_hash
, name
);
6455 e
->X_op
= O_register
;
6456 e
->X_add_number
= S_GET_VALUE (sym
);
6460 cdesc
= hash_find (md
.const_hash
, name
);
6463 e
->X_op
= O_constant
;
6464 e
->X_add_number
= cdesc
->value
;
6468 /* check for inN, locN, or outN: */
6472 if (name
[1] == 'n' && isdigit (name
[2]))
6480 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6488 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6501 /* The name is inN, locN, or outN; parse the register number. */
6502 regnum
= strtoul (name
, &end
, 10);
6503 if (end
> name
&& *end
== '\0')
6505 if ((unsigned) regnum
>= dr
->num_regs
)
6508 as_bad ("No current frame");
6510 as_bad ("Register number out of range 0..%u",
6514 e
->X_op
= O_register
;
6515 e
->X_add_number
= dr
->base
+ regnum
;
6520 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6522 /* We've got ourselves the name of a rotating register set.
6523 Store the base register number in the low 16 bits of
6524 X_add_number and the size of the register set in the top 16
6526 e
->X_op
= O_register
;
6527 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6533 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6536 ia64_canonicalize_symbol_name (name
)
6539 size_t len
= strlen (name
);
6540 if (len
> 1 && name
[len
- 1] == '#')
6541 name
[len
- 1] = '\0';
6546 is_conditional_branch (idesc
)
6547 struct ia64_opcode
*idesc
;
6549 return (strncmp (idesc
->name
, "br", 2) == 0
6550 && (strcmp (idesc
->name
, "br") == 0
6551 || strncmp (idesc
->name
, "br.cond", 7) == 0
6552 || strncmp (idesc
->name
, "br.call", 7) == 0
6553 || strncmp (idesc
->name
, "br.ret", 6) == 0
6554 || strcmp (idesc
->name
, "brl") == 0
6555 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6556 || strncmp (idesc
->name
, "brl.call", 7) == 0
6557 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6560 /* Return whether the given opcode is a taken branch. If there's any doubt,
6564 is_taken_branch (idesc
)
6565 struct ia64_opcode
*idesc
;
6567 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6568 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6571 /* Return whether the given opcode is an interruption or rfi. If there's any
6572 doubt, returns zero. */
6575 is_interruption_or_rfi (idesc
)
6576 struct ia64_opcode
*idesc
;
6578 if (strcmp (idesc
->name
, "rfi") == 0)
6583 /* Returns the index of the given dependency in the opcode's list of chks, or
6584 -1 if there is no dependency. */
6587 depends_on (depind
, idesc
)
6589 struct ia64_opcode
*idesc
;
6592 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6593 for (i
= 0; i
< dep
->nchks
; i
++)
6595 if (depind
== DEP (dep
->chks
[i
]))
6601 /* Determine a set of specific resources used for a particular resource
6602 class. Returns the number of specific resources identified For those
6603 cases which are not determinable statically, the resource returned is
6606 Meanings of value in 'NOTE':
6607 1) only read/write when the register number is explicitly encoded in the
6609 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6610 accesses CFM when qualifying predicate is in the rotating region.
6611 3) general register value is used to specify an indirect register; not
6612 determinable statically.
6613 4) only read the given resource when bits 7:0 of the indirect index
6614 register value does not match the register number of the resource; not
6615 determinable statically.
6616 5) all rules are implementation specific.
6617 6) only when both the index specified by the reader and the index specified
6618 by the writer have the same value in bits 63:61; not determinable
6620 7) only access the specified resource when the corresponding mask bit is
6622 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6623 only read when these insns reference FR2-31
6624 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6625 written when these insns write FR32-127
6626 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6628 11) The target predicates are written independently of PR[qp], but source
6629 registers are only read if PR[qp] is true. Since the state of PR[qp]
6630 cannot statically be determined, all source registers are marked used.
6631 12) This insn only reads the specified predicate register when that
6632 register is the PR[qp].
6633 13) This reference to ld-c only applies to teh GR whose value is loaded
6634 with data returned from memory, not the post-incremented address register.
6635 14) The RSE resource includes the implementation-specific RSE internal
6636 state resources. At least one (and possibly more) of these resources are
6637 read by each instruction listed in IC:rse-readers. At least one (and
6638 possibly more) of these resources are written by each insn listed in
6640 15+16) Represents reserved instructions, which the assembler does not
6643 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6644 this code; there are no dependency violations based on memory access.
6647 #define MAX_SPECS 256
6652 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6653 const struct ia64_dependency
*dep
;
6654 struct ia64_opcode
*idesc
;
6655 int type
; /* is this a DV chk or a DV reg? */
6656 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6657 int note
; /* resource note for this insn's usage */
6658 int path
; /* which execution path to examine */
6665 if (dep
->mode
== IA64_DV_WAW
6666 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6667 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6670 /* template for any resources we identify */
6671 tmpl
.dependency
= dep
;
6673 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6674 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6675 tmpl
.link_to_qp_branch
= 1;
6676 tmpl
.mem_offset
.hint
= 0;
6679 tmpl
.cmp_type
= CMP_NONE
;
6682 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6683 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6684 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6686 /* we don't need to track these */
6687 if (dep
->semantics
== IA64_DVS_NONE
)
6690 switch (dep
->specifier
)
6695 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6697 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6698 if (regno
>= 0 && regno
<= 7)
6700 specs
[count
] = tmpl
;
6701 specs
[count
++].index
= regno
;
6707 for (i
= 0; i
< 8; i
++)
6709 specs
[count
] = tmpl
;
6710 specs
[count
++].index
= i
;
6719 case IA64_RS_AR_UNAT
:
6720 /* This is a mov =AR or mov AR= instruction. */
6721 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6723 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6724 if (regno
== AR_UNAT
)
6726 specs
[count
++] = tmpl
;
6731 /* This is a spill/fill, or other instruction that modifies the
6734 /* Unless we can determine the specific bits used, mark the whole
6735 thing; bits 8:3 of the memory address indicate the bit used in
6736 UNAT. The .mem.offset hint may be used to eliminate a small
6737 subset of conflicts. */
6738 specs
[count
] = tmpl
;
6739 if (md
.mem_offset
.hint
)
6742 fprintf (stderr
, " Using hint for spill/fill\n");
6743 /* The index isn't actually used, just set it to something
6744 approximating the bit index. */
6745 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6746 specs
[count
].mem_offset
.hint
= 1;
6747 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6748 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6752 specs
[count
++].specific
= 0;
6760 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6762 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6763 if ((regno
>= 8 && regno
<= 15)
6764 || (regno
>= 20 && regno
<= 23)
6765 || (regno
>= 31 && regno
<= 39)
6766 || (regno
>= 41 && regno
<= 47)
6767 || (regno
>= 67 && regno
<= 111))
6769 specs
[count
] = tmpl
;
6770 specs
[count
++].index
= regno
;
6783 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6785 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6786 if ((regno
>= 48 && regno
<= 63)
6787 || (regno
>= 112 && regno
<= 127))
6789 specs
[count
] = tmpl
;
6790 specs
[count
++].index
= regno
;
6796 for (i
= 48; i
< 64; i
++)
6798 specs
[count
] = tmpl
;
6799 specs
[count
++].index
= i
;
6801 for (i
= 112; i
< 128; i
++)
6803 specs
[count
] = tmpl
;
6804 specs
[count
++].index
= i
;
6822 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6823 if (idesc
->operands
[i
] == IA64_OPND_B1
6824 || idesc
->operands
[i
] == IA64_OPND_B2
)
6826 specs
[count
] = tmpl
;
6827 specs
[count
++].index
=
6828 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6833 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
6834 if (idesc
->operands
[i
] == IA64_OPND_B1
6835 || idesc
->operands
[i
] == IA64_OPND_B2
)
6837 specs
[count
] = tmpl
;
6838 specs
[count
++].index
=
6839 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6845 case IA64_RS_CPUID
: /* four or more registers */
6848 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6850 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6851 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6854 specs
[count
] = tmpl
;
6855 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6859 specs
[count
] = tmpl
;
6860 specs
[count
++].specific
= 0;
6870 case IA64_RS_DBR
: /* four or more registers */
6873 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6875 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6876 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6879 specs
[count
] = tmpl
;
6880 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6884 specs
[count
] = tmpl
;
6885 specs
[count
++].specific
= 0;
6889 else if (note
== 0 && !rsrc_write
)
6891 specs
[count
] = tmpl
;
6892 specs
[count
++].specific
= 0;
6900 case IA64_RS_IBR
: /* four or more registers */
6903 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6905 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6906 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6909 specs
[count
] = tmpl
;
6910 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6914 specs
[count
] = tmpl
;
6915 specs
[count
++].specific
= 0;
6928 /* These are implementation specific. Force all references to
6929 conflict with all other references. */
6930 specs
[count
] = tmpl
;
6931 specs
[count
++].specific
= 0;
6939 case IA64_RS_PKR
: /* 16 or more registers */
6940 if (note
== 3 || note
== 4)
6942 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6944 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6945 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6950 specs
[count
] = tmpl
;
6951 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6954 for (i
= 0; i
< NELEMS (gr_values
); i
++)
6956 /* Uses all registers *except* the one in R3. */
6957 if (i
!= (gr_values
[regno
].value
& 0xFF))
6959 specs
[count
] = tmpl
;
6960 specs
[count
++].index
= i
;
6966 specs
[count
] = tmpl
;
6967 specs
[count
++].specific
= 0;
6974 specs
[count
] = tmpl
;
6975 specs
[count
++].specific
= 0;
6979 case IA64_RS_PMC
: /* four or more registers */
6982 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
6983 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
6986 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
6988 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
6989 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6992 specs
[count
] = tmpl
;
6993 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6997 specs
[count
] = tmpl
;
6998 specs
[count
++].specific
= 0;
7008 case IA64_RS_PMD
: /* four or more registers */
7011 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7013 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7014 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7017 specs
[count
] = tmpl
;
7018 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7022 specs
[count
] = tmpl
;
7023 specs
[count
++].specific
= 0;
7033 case IA64_RS_RR
: /* eight registers */
7036 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7038 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7039 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7042 specs
[count
] = tmpl
;
7043 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7047 specs
[count
] = tmpl
;
7048 specs
[count
++].specific
= 0;
7052 else if (note
== 0 && !rsrc_write
)
7054 specs
[count
] = tmpl
;
7055 specs
[count
++].specific
= 0;
7063 case IA64_RS_CR_IRR
:
7066 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7067 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7069 && idesc
->operands
[1] == IA64_OPND_CR3
7072 for (i
= 0; i
< 4; i
++)
7074 specs
[count
] = tmpl
;
7075 specs
[count
++].index
= CR_IRR0
+ i
;
7081 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7082 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7084 && regno
<= CR_IRR3
)
7086 specs
[count
] = tmpl
;
7087 specs
[count
++].index
= regno
;
7096 case IA64_RS_CR_LRR
:
7103 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7104 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7105 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7107 specs
[count
] = tmpl
;
7108 specs
[count
++].index
= regno
;
7116 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7118 specs
[count
] = tmpl
;
7119 specs
[count
++].index
=
7120 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7135 else if (rsrc_write
)
7137 if (dep
->specifier
== IA64_RS_FRb
7138 && idesc
->operands
[0] == IA64_OPND_F1
)
7140 specs
[count
] = tmpl
;
7141 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7146 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7148 if (idesc
->operands
[i
] == IA64_OPND_F2
7149 || idesc
->operands
[i
] == IA64_OPND_F3
7150 || idesc
->operands
[i
] == IA64_OPND_F4
)
7152 specs
[count
] = tmpl
;
7153 specs
[count
++].index
=
7154 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7163 /* This reference applies only to the GR whose value is loaded with
7164 data returned from memory. */
7165 specs
[count
] = tmpl
;
7166 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7172 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7173 if (idesc
->operands
[i
] == IA64_OPND_R1
7174 || idesc
->operands
[i
] == IA64_OPND_R2
7175 || idesc
->operands
[i
] == IA64_OPND_R3
)
7177 specs
[count
] = tmpl
;
7178 specs
[count
++].index
=
7179 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7181 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7182 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7183 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7185 specs
[count
] = tmpl
;
7186 specs
[count
++].index
=
7187 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7192 /* Look for anything that reads a GR. */
7193 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7195 if (idesc
->operands
[i
] == IA64_OPND_MR3
7196 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7197 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7198 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7199 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7200 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7201 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7202 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7203 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7204 || ((i
>= idesc
->num_outputs
)
7205 && (idesc
->operands
[i
] == IA64_OPND_R1
7206 || idesc
->operands
[i
] == IA64_OPND_R2
7207 || idesc
->operands
[i
] == IA64_OPND_R3
7208 /* addl source register. */
7209 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7211 specs
[count
] = tmpl
;
7212 specs
[count
++].index
=
7213 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7224 /* This is the same as IA64_RS_PRr, except that the register range is
7225 from 1 - 15, and there are no rotating register reads/writes here. */
7229 for (i
= 1; i
< 16; i
++)
7231 specs
[count
] = tmpl
;
7232 specs
[count
++].index
= i
;
7238 /* Mark only those registers indicated by the mask. */
7241 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7242 for (i
= 1; i
< 16; i
++)
7243 if (mask
& ((valueT
) 1 << i
))
7245 specs
[count
] = tmpl
;
7246 specs
[count
++].index
= i
;
7254 else if (note
== 11) /* note 11 implies note 1 as well */
7258 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7260 if (idesc
->operands
[i
] == IA64_OPND_P1
7261 || idesc
->operands
[i
] == IA64_OPND_P2
)
7263 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7264 if (regno
>= 1 && regno
< 16)
7266 specs
[count
] = tmpl
;
7267 specs
[count
++].index
= regno
;
7277 else if (note
== 12)
7279 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7281 specs
[count
] = tmpl
;
7282 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7289 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7290 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7291 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7292 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7294 if ((idesc
->operands
[0] == IA64_OPND_P1
7295 || idesc
->operands
[0] == IA64_OPND_P2
)
7296 && p1
>= 1 && p1
< 16)
7298 specs
[count
] = tmpl
;
7299 specs
[count
].cmp_type
=
7300 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7301 specs
[count
++].index
= p1
;
7303 if ((idesc
->operands
[1] == IA64_OPND_P1
7304 || idesc
->operands
[1] == IA64_OPND_P2
)
7305 && p2
>= 1 && p2
< 16)
7307 specs
[count
] = tmpl
;
7308 specs
[count
].cmp_type
=
7309 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7310 specs
[count
++].index
= p2
;
7315 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7317 specs
[count
] = tmpl
;
7318 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7320 if (idesc
->operands
[1] == IA64_OPND_PR
)
7322 for (i
= 1; i
< 16; i
++)
7324 specs
[count
] = tmpl
;
7325 specs
[count
++].index
= i
;
7336 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7337 simplified cases of this. */
7341 for (i
= 16; i
< 63; i
++)
7343 specs
[count
] = tmpl
;
7344 specs
[count
++].index
= i
;
7350 /* Mark only those registers indicated by the mask. */
7352 && idesc
->operands
[0] == IA64_OPND_PR
)
7354 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7355 if (mask
& ((valueT
) 1<<16))
7356 for (i
= 16; i
< 63; i
++)
7358 specs
[count
] = tmpl
;
7359 specs
[count
++].index
= i
;
7363 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7365 for (i
= 16; i
< 63; i
++)
7367 specs
[count
] = tmpl
;
7368 specs
[count
++].index
= i
;
7376 else if (note
== 11) /* note 11 implies note 1 as well */
7380 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7382 if (idesc
->operands
[i
] == IA64_OPND_P1
7383 || idesc
->operands
[i
] == IA64_OPND_P2
)
7385 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7386 if (regno
>= 16 && regno
< 63)
7388 specs
[count
] = tmpl
;
7389 specs
[count
++].index
= regno
;
7399 else if (note
== 12)
7401 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7403 specs
[count
] = tmpl
;
7404 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7411 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7412 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7413 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7414 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7416 if ((idesc
->operands
[0] == IA64_OPND_P1
7417 || idesc
->operands
[0] == IA64_OPND_P2
)
7418 && p1
>= 16 && p1
< 63)
7420 specs
[count
] = tmpl
;
7421 specs
[count
].cmp_type
=
7422 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7423 specs
[count
++].index
= p1
;
7425 if ((idesc
->operands
[1] == IA64_OPND_P1
7426 || idesc
->operands
[1] == IA64_OPND_P2
)
7427 && p2
>= 16 && p2
< 63)
7429 specs
[count
] = tmpl
;
7430 specs
[count
].cmp_type
=
7431 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7432 specs
[count
++].index
= p2
;
7437 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7439 specs
[count
] = tmpl
;
7440 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7442 if (idesc
->operands
[1] == IA64_OPND_PR
)
7444 for (i
= 16; i
< 63; i
++)
7446 specs
[count
] = tmpl
;
7447 specs
[count
++].index
= i
;
7459 /* Verify that the instruction is using the PSR bit indicated in
7463 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7465 if (dep
->regindex
< 6)
7467 specs
[count
++] = tmpl
;
7470 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7472 if (dep
->regindex
< 32
7473 || dep
->regindex
== 35
7474 || dep
->regindex
== 36
7475 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7477 specs
[count
++] = tmpl
;
7480 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7482 if (dep
->regindex
< 32
7483 || dep
->regindex
== 35
7484 || dep
->regindex
== 36
7485 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7487 specs
[count
++] = tmpl
;
7492 /* Several PSR bits have very specific dependencies. */
7493 switch (dep
->regindex
)
7496 specs
[count
++] = tmpl
;
7501 specs
[count
++] = tmpl
;
7505 /* Only certain CR accesses use PSR.ic */
7506 if (idesc
->operands
[0] == IA64_OPND_CR3
7507 || idesc
->operands
[1] == IA64_OPND_CR3
)
7510 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7513 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7528 specs
[count
++] = tmpl
;
7537 specs
[count
++] = tmpl
;
7541 /* Only some AR accesses use cpl */
7542 if (idesc
->operands
[0] == IA64_OPND_AR3
7543 || idesc
->operands
[1] == IA64_OPND_AR3
)
7546 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7549 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7556 && regno
<= AR_K7
))))
7558 specs
[count
++] = tmpl
;
7563 specs
[count
++] = tmpl
;
7573 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7575 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7581 if (mask
& ((valueT
) 1 << dep
->regindex
))
7583 specs
[count
++] = tmpl
;
7588 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7589 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7590 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7591 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7593 if (idesc
->operands
[i
] == IA64_OPND_F1
7594 || idesc
->operands
[i
] == IA64_OPND_F2
7595 || idesc
->operands
[i
] == IA64_OPND_F3
7596 || idesc
->operands
[i
] == IA64_OPND_F4
)
7598 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7599 if (reg
>= min
&& reg
<= max
)
7601 specs
[count
++] = tmpl
;
7608 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7609 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7610 /* mfh is read on writes to FR32-127; mfl is read on writes to
7612 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7614 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7616 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7617 if (reg
>= min
&& reg
<= max
)
7619 specs
[count
++] = tmpl
;
7624 else if (note
== 10)
7626 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7628 if (idesc
->operands
[i
] == IA64_OPND_R1
7629 || idesc
->operands
[i
] == IA64_OPND_R2
7630 || idesc
->operands
[i
] == IA64_OPND_R3
)
7632 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7633 if (regno
>= 16 && regno
<= 31)
7635 specs
[count
++] = tmpl
;
7646 case IA64_RS_AR_FPSR
:
7647 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7649 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7650 if (regno
== AR_FPSR
)
7652 specs
[count
++] = tmpl
;
7657 specs
[count
++] = tmpl
;
7662 /* Handle all AR[REG] resources */
7663 if (note
== 0 || note
== 1)
7665 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7666 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7667 && regno
== dep
->regindex
)
7669 specs
[count
++] = tmpl
;
7671 /* other AR[REG] resources may be affected by AR accesses */
7672 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7675 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7676 switch (dep
->regindex
)
7682 if (regno
== AR_BSPSTORE
)
7684 specs
[count
++] = tmpl
;
7688 (regno
== AR_BSPSTORE
7689 || regno
== AR_RNAT
))
7691 specs
[count
++] = tmpl
;
7696 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7699 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7700 switch (dep
->regindex
)
7705 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7707 specs
[count
++] = tmpl
;
7714 specs
[count
++] = tmpl
;
7724 /* Handle all CR[REG] resources */
7725 if (note
== 0 || note
== 1)
7727 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7729 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7730 if (regno
== dep
->regindex
)
7732 specs
[count
++] = tmpl
;
7734 else if (!rsrc_write
)
7736 /* Reads from CR[IVR] affect other resources. */
7737 if (regno
== CR_IVR
)
7739 if ((dep
->regindex
>= CR_IRR0
7740 && dep
->regindex
<= CR_IRR3
)
7741 || dep
->regindex
== CR_TPR
)
7743 specs
[count
++] = tmpl
;
7750 specs
[count
++] = tmpl
;
7759 case IA64_RS_INSERVICE
:
7760 /* look for write of EOI (67) or read of IVR (65) */
7761 if ((idesc
->operands
[0] == IA64_OPND_CR3
7762 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7763 || (idesc
->operands
[1] == IA64_OPND_CR3
7764 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7766 specs
[count
++] = tmpl
;
7773 specs
[count
++] = tmpl
;
7784 specs
[count
++] = tmpl
;
7788 /* Check if any of the registers accessed are in the rotating region.
7789 mov to/from pr accesses CFM only when qp_regno is in the rotating
7791 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7793 if (idesc
->operands
[i
] == IA64_OPND_R1
7794 || idesc
->operands
[i
] == IA64_OPND_R2
7795 || idesc
->operands
[i
] == IA64_OPND_R3
)
7797 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7798 /* Assumes that md.rot.num_regs is always valid */
7799 if (md
.rot
.num_regs
> 0
7801 && num
< 31 + md
.rot
.num_regs
)
7803 specs
[count
] = tmpl
;
7804 specs
[count
++].specific
= 0;
7807 else if (idesc
->operands
[i
] == IA64_OPND_F1
7808 || idesc
->operands
[i
] == IA64_OPND_F2
7809 || idesc
->operands
[i
] == IA64_OPND_F3
7810 || idesc
->operands
[i
] == IA64_OPND_F4
)
7812 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7815 specs
[count
] = tmpl
;
7816 specs
[count
++].specific
= 0;
7819 else if (idesc
->operands
[i
] == IA64_OPND_P1
7820 || idesc
->operands
[i
] == IA64_OPND_P2
)
7822 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7825 specs
[count
] = tmpl
;
7826 specs
[count
++].specific
= 0;
7830 if (CURR_SLOT
.qp_regno
> 15)
7832 specs
[count
] = tmpl
;
7833 specs
[count
++].specific
= 0;
7838 /* This is the same as IA64_RS_PRr, except simplified to account for
7839 the fact that there is only one register. */
7843 specs
[count
++] = tmpl
;
7848 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7849 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7850 if (mask
& ((valueT
) 1 << 63))
7851 specs
[count
++] = tmpl
;
7853 else if (note
== 11)
7855 if ((idesc
->operands
[0] == IA64_OPND_P1
7856 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7857 || (idesc
->operands
[1] == IA64_OPND_P2
7858 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7860 specs
[count
++] = tmpl
;
7863 else if (note
== 12)
7865 if (CURR_SLOT
.qp_regno
== 63)
7867 specs
[count
++] = tmpl
;
7874 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7875 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7876 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7877 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7880 && (idesc
->operands
[0] == IA64_OPND_P1
7881 || idesc
->operands
[0] == IA64_OPND_P2
))
7883 specs
[count
] = tmpl
;
7884 specs
[count
++].cmp_type
=
7885 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7888 && (idesc
->operands
[1] == IA64_OPND_P1
7889 || idesc
->operands
[1] == IA64_OPND_P2
))
7891 specs
[count
] = tmpl
;
7892 specs
[count
++].cmp_type
=
7893 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7898 if (CURR_SLOT
.qp_regno
== 63)
7900 specs
[count
++] = tmpl
;
7911 /* FIXME we can identify some individual RSE written resources, but RSE
7912 read resources have not yet been completely identified, so for now
7913 treat RSE as a single resource */
7914 if (strncmp (idesc
->name
, "mov", 3) == 0)
7918 if (idesc
->operands
[0] == IA64_OPND_AR3
7919 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7921 specs
[count
] = tmpl
;
7922 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7927 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7929 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7930 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7932 specs
[count
++] = tmpl
;
7935 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7937 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7938 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7939 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7941 specs
[count
++] = tmpl
;
7948 specs
[count
++] = tmpl
;
7953 /* FIXME -- do any of these need to be non-specific? */
7954 specs
[count
++] = tmpl
;
7958 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7965 /* Clear branch flags on marked resources. This breaks the link between the
7966 QP of the marking instruction and a subsequent branch on the same QP. */
7969 clear_qp_branch_flag (mask
)
7973 for (i
= 0; i
< regdepslen
; i
++)
7975 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
7976 if ((bit
& mask
) != 0)
7978 regdeps
[i
].link_to_qp_branch
= 0;
7983 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7985 Any changes to a PR clears the mutex relations which include that PR. */
7988 clear_qp_mutex (mask
)
7994 while (i
< qp_mutexeslen
)
7996 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8000 fprintf (stderr
, " Clearing mutex relation");
8001 print_prmask (qp_mutexes
[i
].prmask
);
8002 fprintf (stderr
, "\n");
8004 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8011 /* Clear implies relations which contain PRs in the given masks.
8012 P1_MASK indicates the source of the implies relation, while P2_MASK
8013 indicates the implied PR. */
8016 clear_qp_implies (p1_mask
, p2_mask
)
8023 while (i
< qp_implieslen
)
8025 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8026 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8029 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8030 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8031 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8038 /* Add the PRs specified to the list of implied relations. */
8041 add_qp_imply (p1
, p2
)
8048 /* p0 is not meaningful here. */
8049 if (p1
== 0 || p2
== 0)
8055 /* If it exists already, ignore it. */
8056 for (i
= 0; i
< qp_implieslen
; i
++)
8058 if (qp_implies
[i
].p1
== p1
8059 && qp_implies
[i
].p2
== p2
8060 && qp_implies
[i
].path
== md
.path
8061 && !qp_implies
[i
].p2_branched
)
8065 if (qp_implieslen
== qp_impliestotlen
)
8067 qp_impliestotlen
+= 20;
8068 qp_implies
= (struct qp_imply
*)
8069 xrealloc ((void *) qp_implies
,
8070 qp_impliestotlen
* sizeof (struct qp_imply
));
8073 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8074 qp_implies
[qp_implieslen
].p1
= p1
;
8075 qp_implies
[qp_implieslen
].p2
= p2
;
8076 qp_implies
[qp_implieslen
].path
= md
.path
;
8077 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8079 /* Add in the implied transitive relations; for everything that p2 implies,
8080 make p1 imply that, too; for everything that implies p1, make it imply p2
8082 for (i
= 0; i
< qp_implieslen
; i
++)
8084 if (qp_implies
[i
].p1
== p2
)
8085 add_qp_imply (p1
, qp_implies
[i
].p2
);
8086 if (qp_implies
[i
].p2
== p1
)
8087 add_qp_imply (qp_implies
[i
].p1
, p2
);
8089 /* Add in mutex relations implied by this implies relation; for each mutex
8090 relation containing p2, duplicate it and replace p2 with p1. */
8091 bit
= (valueT
) 1 << p1
;
8092 mask
= (valueT
) 1 << p2
;
8093 for (i
= 0; i
< qp_mutexeslen
; i
++)
8095 if (qp_mutexes
[i
].prmask
& mask
)
8096 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8100 /* Add the PRs specified in the mask to the mutex list; this means that only
8101 one of the PRs can be true at any time. PR0 should never be included in
8111 if (qp_mutexeslen
== qp_mutexestotlen
)
8113 qp_mutexestotlen
+= 20;
8114 qp_mutexes
= (struct qpmutex
*)
8115 xrealloc ((void *) qp_mutexes
,
8116 qp_mutexestotlen
* sizeof (struct qpmutex
));
8120 fprintf (stderr
, " Registering mutex on");
8121 print_prmask (mask
);
8122 fprintf (stderr
, "\n");
8124 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8125 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8129 clear_register_values ()
8133 fprintf (stderr
, " Clearing register values\n");
8134 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8135 gr_values
[i
].known
= 0;
8138 /* Keep track of register values/changes which affect DV tracking.
8140 optimization note: should add a flag to classes of insns where otherwise we
8141 have to examine a group of strings to identify them. */
8144 note_register_values (idesc
)
8145 struct ia64_opcode
*idesc
;
8147 valueT qp_changemask
= 0;
8150 /* Invalidate values for registers being written to. */
8151 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8153 if (idesc
->operands
[i
] == IA64_OPND_R1
8154 || idesc
->operands
[i
] == IA64_OPND_R2
8155 || idesc
->operands
[i
] == IA64_OPND_R3
)
8157 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8158 if (regno
> 0 && regno
< NELEMS (gr_values
))
8159 gr_values
[regno
].known
= 0;
8161 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8163 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8164 if (regno
> 0 && regno
< 4)
8165 gr_values
[regno
].known
= 0;
8167 else if (idesc
->operands
[i
] == IA64_OPND_P1
8168 || idesc
->operands
[i
] == IA64_OPND_P2
)
8170 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8171 qp_changemask
|= (valueT
) 1 << regno
;
8173 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8175 if (idesc
->operands
[2] & (valueT
) 0x10000)
8176 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8178 qp_changemask
= idesc
->operands
[2];
8181 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8183 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8184 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8186 qp_changemask
= idesc
->operands
[1];
8187 qp_changemask
&= ~(valueT
) 0xFFFF;
8192 /* Always clear qp branch flags on any PR change. */
8193 /* FIXME there may be exceptions for certain compares. */
8194 clear_qp_branch_flag (qp_changemask
);
8196 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8197 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8199 qp_changemask
|= ~(valueT
) 0xFFFF;
8200 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8202 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8203 gr_values
[i
].known
= 0;
8205 clear_qp_mutex (qp_changemask
);
8206 clear_qp_implies (qp_changemask
, qp_changemask
);
8208 /* After a call, all register values are undefined, except those marked
8210 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8211 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8213 /* FIXME keep GR values which are marked as "safe_across_calls" */
8214 clear_register_values ();
8215 clear_qp_mutex (~qp_safe_across_calls
);
8216 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8217 clear_qp_branch_flag (~qp_safe_across_calls
);
8219 else if (is_interruption_or_rfi (idesc
)
8220 || is_taken_branch (idesc
))
8222 clear_register_values ();
8223 clear_qp_mutex (~(valueT
) 0);
8224 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8226 /* Look for mutex and implies relations. */
8227 else if ((idesc
->operands
[0] == IA64_OPND_P1
8228 || idesc
->operands
[0] == IA64_OPND_P2
)
8229 && (idesc
->operands
[1] == IA64_OPND_P1
8230 || idesc
->operands
[1] == IA64_OPND_P2
))
8232 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8233 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8234 valueT p1mask
= (valueT
) 1 << p1
;
8235 valueT p2mask
= (valueT
) 1 << p2
;
8237 /* If one of the PRs is PR0, we can't really do anything. */
8238 if (p1
== 0 || p2
== 0)
8241 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8243 /* In general, clear mutexes and implies which include P1 or P2,
8244 with the following exceptions. */
8245 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8247 add_qp_mutex (p1mask
| p2mask
);
8248 clear_qp_implies (p2mask
, p1mask
);
8250 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8252 add_qp_mutex (p1mask
| p2mask
);
8253 clear_qp_implies (p1mask
, p2mask
);
8255 else if (strstr (idesc
->name
, ".and") != NULL
)
8257 clear_qp_implies (0, p1mask
| p2mask
);
8259 else if (strstr (idesc
->name
, ".or") != NULL
)
8261 clear_qp_mutex (p1mask
| p2mask
);
8262 clear_qp_implies (p1mask
| p2mask
, 0);
8266 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8267 if (strstr (idesc
->name
, ".unc") != NULL
)
8269 add_qp_mutex (p1mask
| p2mask
);
8270 if (CURR_SLOT
.qp_regno
!= 0)
8272 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8273 CURR_SLOT
.qp_regno
);
8274 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8275 CURR_SLOT
.qp_regno
);
8278 else if (CURR_SLOT
.qp_regno
== 0)
8280 add_qp_mutex (p1mask
| p2mask
);
8284 clear_qp_mutex (p1mask
| p2mask
);
8288 /* Look for mov imm insns into GRs. */
8289 else if (idesc
->operands
[0] == IA64_OPND_R1
8290 && (idesc
->operands
[1] == IA64_OPND_IMM22
8291 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8292 && (strcmp (idesc
->name
, "mov") == 0
8293 || strcmp (idesc
->name
, "movl") == 0))
8295 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8296 if (regno
> 0 && regno
< NELEMS (gr_values
))
8298 gr_values
[regno
].known
= 1;
8299 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8300 gr_values
[regno
].path
= md
.path
;
8302 fprintf (stderr
, " Know gr%d = 0x%llx\n",
8303 regno
, gr_values
[regno
].value
);
8308 clear_qp_mutex (qp_changemask
);
8309 clear_qp_implies (qp_changemask
, qp_changemask
);
8313 /* Return whether the given predicate registers are currently mutex. */
8316 qp_mutex (p1
, p2
, path
)
8326 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8327 for (i
= 0; i
< qp_mutexeslen
; i
++)
8329 if (qp_mutexes
[i
].path
>= path
8330 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8337 /* Return whether the given resource is in the given insn's list of chks
8338 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8342 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8344 struct ia64_opcode
*idesc
;
8349 struct rsrc specs
[MAX_SPECS
];
8352 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8353 we don't need to check. One exception is note 11, which indicates that
8354 target predicates are written regardless of PR[qp]. */
8355 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8359 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8362 /* UNAT checking is a bit more specific than other resources */
8363 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8364 && specs
[count
].mem_offset
.hint
8365 && rs
->mem_offset
.hint
)
8367 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8369 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8370 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8377 /* Skip apparent PR write conflicts where both writes are an AND or both
8378 writes are an OR. */
8379 if (rs
->dependency
->specifier
== IA64_RS_PR
8380 || rs
->dependency
->specifier
== IA64_RS_PRr
8381 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8383 if (specs
[count
].cmp_type
!= CMP_NONE
8384 && specs
[count
].cmp_type
== rs
->cmp_type
)
8387 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8388 dv_mode
[rs
->dependency
->mode
],
8389 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8390 specs
[count
].index
: 63);
8395 " %s on parallel compare conflict %s vs %s on PR%d\n",
8396 dv_mode
[rs
->dependency
->mode
],
8397 dv_cmp_type
[rs
->cmp_type
],
8398 dv_cmp_type
[specs
[count
].cmp_type
],
8399 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8400 specs
[count
].index
: 63);
8404 /* If either resource is not specific, conservatively assume a conflict
8406 if (!specs
[count
].specific
|| !rs
->specific
)
8408 else if (specs
[count
].index
== rs
->index
)
8413 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8419 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8420 insert a stop to create the break. Update all resource dependencies
8421 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8422 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8423 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8427 insn_group_break (insert_stop
, qp_regno
, save_current
)
8434 if (insert_stop
&& md
.num_slots_in_use
> 0)
8435 PREV_SLOT
.end_of_insn_group
= 1;
8439 fprintf (stderr
, " Insn group break%s",
8440 (insert_stop
? " (w/stop)" : ""));
8442 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8443 fprintf (stderr
, "\n");
8447 while (i
< regdepslen
)
8449 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8452 && regdeps
[i
].qp_regno
!= qp_regno
)
8459 && CURR_SLOT
.src_file
== regdeps
[i
].file
8460 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8466 /* clear dependencies which are automatically cleared by a stop, or
8467 those that have reached the appropriate state of insn serialization */
8468 if (dep
->semantics
== IA64_DVS_IMPLIED
8469 || dep
->semantics
== IA64_DVS_IMPLIEDF
8470 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8472 print_dependency ("Removing", i
);
8473 regdeps
[i
] = regdeps
[--regdepslen
];
8477 if (dep
->semantics
== IA64_DVS_DATA
8478 || dep
->semantics
== IA64_DVS_INSTR
8479 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8481 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8482 regdeps
[i
].insn_srlz
= STATE_STOP
;
8483 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8484 regdeps
[i
].data_srlz
= STATE_STOP
;
8491 /* Add the given resource usage spec to the list of active dependencies. */
8494 mark_resource (idesc
, dep
, spec
, depind
, path
)
8495 struct ia64_opcode
*idesc
;
8496 const struct ia64_dependency
*dep
;
8501 if (regdepslen
== regdepstotlen
)
8503 regdepstotlen
+= 20;
8504 regdeps
= (struct rsrc
*)
8505 xrealloc ((void *) regdeps
,
8506 regdepstotlen
* sizeof(struct rsrc
));
8509 regdeps
[regdepslen
] = *spec
;
8510 regdeps
[regdepslen
].depind
= depind
;
8511 regdeps
[regdepslen
].path
= path
;
8512 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8513 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8515 print_dependency ("Adding", regdepslen
);
8521 print_dependency (action
, depind
)
8527 fprintf (stderr
, " %s %s '%s'",
8528 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8529 (regdeps
[depind
].dependency
)->name
);
8530 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8531 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8532 if (regdeps
[depind
].mem_offset
.hint
)
8533 fprintf (stderr
, " 0x%llx+0x%llx",
8534 regdeps
[depind
].mem_offset
.base
,
8535 regdeps
[depind
].mem_offset
.offset
);
8536 fprintf (stderr
, "\n");
8541 instruction_serialization ()
8545 fprintf (stderr
, " Instruction serialization\n");
8546 for (i
= 0; i
< regdepslen
; i
++)
8547 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8548 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8552 data_serialization ()
8556 fprintf (stderr
, " Data serialization\n");
8557 while (i
< regdepslen
)
8559 if (regdeps
[i
].data_srlz
== STATE_STOP
8560 /* Note: as of 991210, all "other" dependencies are cleared by a
8561 data serialization. This might change with new tables */
8562 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8564 print_dependency ("Removing", i
);
8565 regdeps
[i
] = regdeps
[--regdepslen
];
8572 /* Insert stops and serializations as needed to avoid DVs. */
8575 remove_marked_resource (rs
)
8578 switch (rs
->dependency
->semantics
)
8580 case IA64_DVS_SPECIFIC
:
8582 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8583 /* ...fall through... */
8584 case IA64_DVS_INSTR
:
8586 fprintf (stderr
, "Inserting instr serialization\n");
8587 if (rs
->insn_srlz
< STATE_STOP
)
8588 insn_group_break (1, 0, 0);
8589 if (rs
->insn_srlz
< STATE_SRLZ
)
8591 int oldqp
= CURR_SLOT
.qp_regno
;
8592 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8593 /* Manually jam a srlz.i insn into the stream */
8594 CURR_SLOT
.qp_regno
= 0;
8595 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8596 instruction_serialization ();
8597 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8598 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8600 CURR_SLOT
.qp_regno
= oldqp
;
8601 CURR_SLOT
.idesc
= oldidesc
;
8603 insn_group_break (1, 0, 0);
8605 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8606 "other" types of DV are eliminated
8607 by a data serialization */
8610 fprintf (stderr
, "Inserting data serialization\n");
8611 if (rs
->data_srlz
< STATE_STOP
)
8612 insn_group_break (1, 0, 0);
8614 int oldqp
= CURR_SLOT
.qp_regno
;
8615 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8616 /* Manually jam a srlz.d insn into the stream */
8617 CURR_SLOT
.qp_regno
= 0;
8618 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8619 data_serialization ();
8620 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8621 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8623 CURR_SLOT
.qp_regno
= oldqp
;
8624 CURR_SLOT
.idesc
= oldidesc
;
8627 case IA64_DVS_IMPLIED
:
8628 case IA64_DVS_IMPLIEDF
:
8630 fprintf (stderr
, "Inserting stop\n");
8631 insn_group_break (1, 0, 0);
8638 /* Check the resources used by the given opcode against the current dependency
8641 The check is run once for each execution path encountered. In this case,
8642 a unique execution path is the sequence of instructions following a code
8643 entry point, e.g. the following has three execution paths, one starting
8644 at L0, one at L1, and one at L2.
8653 check_dependencies (idesc
)
8654 struct ia64_opcode
*idesc
;
8656 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8660 /* Note that the number of marked resources may change within the
8661 loop if in auto mode. */
8663 while (i
< regdepslen
)
8665 struct rsrc
*rs
= ®deps
[i
];
8666 const struct ia64_dependency
*dep
= rs
->dependency
;
8671 if (dep
->semantics
== IA64_DVS_NONE
8672 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8678 note
= NOTE (opdeps
->chks
[chkind
]);
8680 /* Check this resource against each execution path seen thus far. */
8681 for (path
= 0; path
<= md
.path
; path
++)
8685 /* If the dependency wasn't on the path being checked, ignore it. */
8686 if (rs
->path
< path
)
8689 /* If the QP for this insn implies a QP which has branched, don't
8690 bother checking. Ed. NOTE: I don't think this check is terribly
8691 useful; what's the point of generating code which will only be
8692 reached if its QP is zero?
8693 This code was specifically inserted to handle the following code,
8694 based on notes from Intel's DV checking code, where p1 implies p2.
8700 if (CURR_SLOT
.qp_regno
!= 0)
8704 for (implies
= 0; implies
< qp_implieslen
; implies
++)
8706 if (qp_implies
[implies
].path
>= path
8707 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8708 && qp_implies
[implies
].p2_branched
)
8718 if ((matchtype
= resources_match (rs
, idesc
, note
,
8719 CURR_SLOT
.qp_regno
, path
)) != 0)
8722 char pathmsg
[256] = "";
8723 char indexmsg
[256] = "";
8724 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8727 sprintf (pathmsg
, " when entry is at label '%s'",
8728 md
.entry_labels
[path
- 1]);
8729 if (rs
->specific
&& rs
->index
!= 0)
8730 sprintf (indexmsg
, ", specific resource number is %d",
8732 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8734 (certain
? "violates" : "may violate"),
8735 dv_mode
[dep
->mode
], dep
->name
,
8736 dv_sem
[dep
->semantics
],
8739 if (md
.explicit_mode
)
8741 as_warn ("%s", msg
);
8743 as_warn (_("Only the first path encountering the conflict "
8745 as_warn_where (rs
->file
, rs
->line
,
8746 _("This is the location of the "
8747 "conflicting usage"));
8748 /* Don't bother checking other paths, to avoid duplicating
8755 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8757 remove_marked_resource (rs
);
8759 /* since the set of dependencies has changed, start over */
8760 /* FIXME -- since we're removing dvs as we go, we
8761 probably don't really need to start over... */
8774 /* Register new dependencies based on the given opcode. */
8777 mark_resources (idesc
)
8778 struct ia64_opcode
*idesc
;
8781 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8782 int add_only_qp_reads
= 0;
8784 /* A conditional branch only uses its resources if it is taken; if it is
8785 taken, we stop following that path. The other branch types effectively
8786 *always* write their resources. If it's not taken, register only QP
8788 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8790 add_only_qp_reads
= 1;
8794 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8796 for (i
= 0; i
< opdeps
->nregs
; i
++)
8798 const struct ia64_dependency
*dep
;
8799 struct rsrc specs
[MAX_SPECS
];
8804 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8805 note
= NOTE (opdeps
->regs
[i
]);
8807 if (add_only_qp_reads
8808 && !(dep
->mode
== IA64_DV_WAR
8809 && (dep
->specifier
== IA64_RS_PR
8810 || dep
->specifier
== IA64_RS_PRr
8811 || dep
->specifier
== IA64_RS_PR63
)))
8814 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8817 if (md
.debug_dv
&& !count
)
8818 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8819 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8824 mark_resource (idesc
, dep
, &specs
[count
],
8825 DEP (opdeps
->regs
[i
]), md
.path
);
8828 /* The execution path may affect register values, which may in turn
8829 affect which indirect-access resources are accessed. */
8830 switch (dep
->specifier
)
8842 for (path
= 0; path
< md
.path
; path
++)
8844 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8846 mark_resource (idesc
, dep
, &specs
[count
],
8847 DEP (opdeps
->regs
[i
]), path
);
8854 /* Remove dependencies when they no longer apply. */
8857 update_dependencies (idesc
)
8858 struct ia64_opcode
*idesc
;
8862 if (strcmp (idesc
->name
, "srlz.i") == 0)
8864 instruction_serialization ();
8866 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8868 data_serialization ();
8870 else if (is_interruption_or_rfi (idesc
)
8871 || is_taken_branch (idesc
))
8873 /* Although technically the taken branch doesn't clear dependencies
8874 which require a srlz.[id], we don't follow the branch; the next
8875 instruction is assumed to start with a clean slate. */
8879 else if (is_conditional_branch (idesc
)
8880 && CURR_SLOT
.qp_regno
!= 0)
8882 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8884 for (i
= 0; i
< qp_implieslen
; i
++)
8886 /* If the conditional branch's predicate is implied by the predicate
8887 in an existing dependency, remove that dependency. */
8888 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8891 /* Note that this implied predicate takes a branch so that if
8892 a later insn generates a DV but its predicate implies this
8893 one, we can avoid the false DV warning. */
8894 qp_implies
[i
].p2_branched
= 1;
8895 while (depind
< regdepslen
)
8897 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8899 print_dependency ("Removing", depind
);
8900 regdeps
[depind
] = regdeps
[--regdepslen
];
8907 /* Any marked resources which have this same predicate should be
8908 cleared, provided that the QP hasn't been modified between the
8909 marking instruction and the branch. */
8912 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8917 while (i
< regdepslen
)
8919 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8920 && regdeps
[i
].link_to_qp_branch
8921 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8922 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8924 /* Treat like a taken branch */
8925 print_dependency ("Removing", i
);
8926 regdeps
[i
] = regdeps
[--regdepslen
];
8935 /* Examine the current instruction for dependency violations. */
8939 struct ia64_opcode
*idesc
;
8943 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8944 idesc
->name
, CURR_SLOT
.src_line
,
8945 idesc
->dependencies
->nchks
,
8946 idesc
->dependencies
->nregs
);
8949 /* Look through the list of currently marked resources; if the current
8950 instruction has the dependency in its chks list which uses that resource,
8951 check against the specific resources used. */
8952 check_dependencies (idesc
);
8954 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8955 then add them to the list of marked resources. */
8956 mark_resources (idesc
);
8958 /* There are several types of dependency semantics, and each has its own
8959 requirements for being cleared
8961 Instruction serialization (insns separated by interruption, rfi, or
8962 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8964 Data serialization (instruction serialization, or writer + srlz.d +
8965 reader, where writer and srlz.d are in separate groups) clears
8966 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8967 always be the case).
8969 Instruction group break (groups separated by stop, taken branch,
8970 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8972 update_dependencies (idesc
);
8974 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8975 warning. Keep track of as many as possible that are useful. */
8976 note_register_values (idesc
);
8978 /* We don't need or want this anymore. */
8979 md
.mem_offset
.hint
= 0;
8984 /* Translate one line of assembly. Pseudo ops and labels do not show
8990 char *saved_input_line_pointer
, *mnemonic
;
8991 const struct pseudo_opcode
*pdesc
;
8992 struct ia64_opcode
*idesc
;
8993 unsigned char qp_regno
;
8997 saved_input_line_pointer
= input_line_pointer
;
8998 input_line_pointer
= str
;
9000 /* extract the opcode (mnemonic): */
9002 mnemonic
= input_line_pointer
;
9003 ch
= get_symbol_end ();
9004 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9007 *input_line_pointer
= ch
;
9008 (*pdesc
->handler
) (pdesc
->arg
);
9012 /* Find the instruction descriptor matching the arguments. */
9014 idesc
= ia64_find_opcode (mnemonic
);
9015 *input_line_pointer
= ch
;
9018 as_bad ("Unknown opcode `%s'", mnemonic
);
9022 idesc
= parse_operands (idesc
);
9026 /* Handle the dynamic ops we can handle now: */
9027 if (idesc
->type
== IA64_TYPE_DYN
)
9029 if (strcmp (idesc
->name
, "add") == 0)
9031 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9032 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9036 ia64_free_opcode (idesc
);
9037 idesc
= ia64_find_opcode (mnemonic
);
9039 know (!idesc
->next
);
9042 else if (strcmp (idesc
->name
, "mov") == 0)
9044 enum ia64_opnd opnd1
, opnd2
;
9047 opnd1
= idesc
->operands
[0];
9048 opnd2
= idesc
->operands
[1];
9049 if (opnd1
== IA64_OPND_AR3
)
9051 else if (opnd2
== IA64_OPND_AR3
)
9055 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9056 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9060 ia64_free_opcode (idesc
);
9061 idesc
= ia64_find_opcode (mnemonic
);
9062 while (idesc
!= NULL
9063 && (idesc
->operands
[0] != opnd1
9064 || idesc
->operands
[1] != opnd2
))
9065 idesc
= get_next_opcode (idesc
);
9070 if (md
.qp
.X_op
== O_register
)
9072 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9073 md
.qp
.X_op
= O_absent
;
9076 flags
= idesc
->flags
;
9078 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9079 insn_group_break (1, 0, 0);
9081 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9083 as_bad ("`%s' cannot be predicated", idesc
->name
);
9087 /* Build the instruction. */
9088 CURR_SLOT
.qp_regno
= qp_regno
;
9089 CURR_SLOT
.idesc
= idesc
;
9090 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9091 if (debug_type
== DEBUG_DWARF2
)
9092 dwarf2_where (&CURR_SLOT
.debug_line
);
9094 /* Add unwind entry, if there is one. */
9095 if (unwind
.current_entry
)
9097 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9098 unwind
.current_entry
= NULL
;
9101 /* Check for dependency violations. */
9105 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9106 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9109 if ((flags
& IA64_OPCODE_LAST
) != 0)
9110 insn_group_break (1, 0, 0);
9112 md
.last_text_seg
= now_seg
;
9115 input_line_pointer
= saved_input_line_pointer
;
9118 /* Called when symbol NAME cannot be found in the symbol table.
9119 Should be used for dynamic valued symbols only. */
9122 md_undefined_symbol (name
)
9128 /* Called for any expression that can not be recognized. When the
9129 function is called, `input_line_pointer' will point to the start of
9136 enum pseudo_type pseudo_type
;
9141 switch (*input_line_pointer
)
9144 /* Find what relocation pseudo-function we're dealing with. */
9146 ch
= *++input_line_pointer
;
9147 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9148 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9150 len
= strlen (pseudo_func
[i
].name
);
9151 if (strncmp (pseudo_func
[i
].name
+ 1,
9152 input_line_pointer
+ 1, len
- 1) == 0
9153 && !is_part_of_name (input_line_pointer
[len
]))
9155 input_line_pointer
+= len
;
9156 pseudo_type
= pseudo_func
[i
].type
;
9160 switch (pseudo_type
)
9162 case PSEUDO_FUNC_RELOC
:
9164 if (*input_line_pointer
!= '(')
9166 as_bad ("Expected '('");
9170 ++input_line_pointer
;
9172 if (*input_line_pointer
++ != ')')
9174 as_bad ("Missing ')'");
9177 if (e
->X_op
!= O_symbol
)
9179 if (e
->X_op
!= O_pseudo_fixup
)
9181 as_bad ("Not a symbolic expression");
9184 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9185 && i
== FUNC_LT_RELATIVE
)
9186 i
= FUNC_LT_FPTR_RELATIVE
;
9189 as_bad ("Illegal combination of relocation functions");
9193 /* Make sure gas doesn't get rid of local symbols that are used
9195 e
->X_op
= O_pseudo_fixup
;
9196 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9199 case PSEUDO_FUNC_CONST
:
9200 e
->X_op
= O_constant
;
9201 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9204 case PSEUDO_FUNC_REG
:
9205 e
->X_op
= O_register
;
9206 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9210 name
= input_line_pointer
- 1;
9212 as_bad ("Unknown pseudo function `%s'", name
);
9218 ++input_line_pointer
;
9220 if (*input_line_pointer
!= ']')
9222 as_bad ("Closing bracket misssing");
9227 if (e
->X_op
!= O_register
)
9228 as_bad ("Register expected as index");
9230 ++input_line_pointer
;
9241 ignore_rest_of_line ();
9244 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9245 a section symbol plus some offset. For relocs involving @fptr(),
9246 directives we don't want such adjustments since we need to have the
9247 original symbol's name in the reloc. */
9249 ia64_fix_adjustable (fix
)
9252 /* Prevent all adjustments to global symbols */
9253 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9256 switch (fix
->fx_r_type
)
9258 case BFD_RELOC_IA64_FPTR64I
:
9259 case BFD_RELOC_IA64_FPTR32MSB
:
9260 case BFD_RELOC_IA64_FPTR32LSB
:
9261 case BFD_RELOC_IA64_FPTR64MSB
:
9262 case BFD_RELOC_IA64_FPTR64LSB
:
9263 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9264 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9274 ia64_force_relocation (fix
)
9277 switch (fix
->fx_r_type
)
9279 case BFD_RELOC_IA64_FPTR64I
:
9280 case BFD_RELOC_IA64_FPTR32MSB
:
9281 case BFD_RELOC_IA64_FPTR32LSB
:
9282 case BFD_RELOC_IA64_FPTR64MSB
:
9283 case BFD_RELOC_IA64_FPTR64LSB
:
9285 case BFD_RELOC_IA64_LTOFF22
:
9286 case BFD_RELOC_IA64_LTOFF64I
:
9287 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9288 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9289 case BFD_RELOC_IA64_PLTOFF22
:
9290 case BFD_RELOC_IA64_PLTOFF64I
:
9291 case BFD_RELOC_IA64_PLTOFF64MSB
:
9292 case BFD_RELOC_IA64_PLTOFF64LSB
:
9301 /* Decide from what point a pc-relative relocation is relative to,
9302 relative to the pc-relative fixup. Er, relatively speaking. */
9304 ia64_pcrel_from_section (fix
, sec
)
9308 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9310 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9316 /* This is called whenever some data item (not an instruction) needs a
9317 fixup. We pick the right reloc code depending on the byteorder
9318 currently in effect. */
9320 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9326 bfd_reloc_code_real_type code
;
9331 /* There are no reloc for 8 and 16 bit quantities, but we allow
9332 them here since they will work fine as long as the expression
9333 is fully defined at the end of the pass over the source file. */
9334 case 1: code
= BFD_RELOC_8
; break;
9335 case 2: code
= BFD_RELOC_16
; break;
9337 if (target_big_endian
)
9338 code
= BFD_RELOC_IA64_DIR32MSB
;
9340 code
= BFD_RELOC_IA64_DIR32LSB
;
9344 if (target_big_endian
)
9345 code
= BFD_RELOC_IA64_DIR64MSB
;
9347 code
= BFD_RELOC_IA64_DIR64LSB
;
9351 as_bad ("Unsupported fixup size %d", nbytes
);
9352 ignore_rest_of_line ();
9355 if (exp
->X_op
== O_pseudo_fixup
)
9358 exp
->X_op
= O_symbol
;
9359 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9361 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9362 /* We need to store the byte order in effect in case we're going
9363 to fix an 8 or 16 bit relocation (for which there no real
9364 relocs available). See md_apply_fix(). */
9365 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9368 /* Return the actual relocation we wish to associate with the pseudo
9369 reloc described by SYM and R_TYPE. SYM should be one of the
9370 symbols in the pseudo_func array, or NULL. */
9372 static bfd_reloc_code_real_type
9373 ia64_gen_real_reloc_type (sym
, r_type
)
9375 bfd_reloc_code_real_type r_type
;
9377 bfd_reloc_code_real_type
new = 0;
9384 switch (S_GET_VALUE (sym
))
9386 case FUNC_FPTR_RELATIVE
:
9389 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9390 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9391 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9392 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9393 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9398 case FUNC_GP_RELATIVE
:
9401 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9402 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9403 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9404 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9405 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9406 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9411 case FUNC_LT_RELATIVE
:
9414 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9415 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9420 case FUNC_PC_RELATIVE
:
9423 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9424 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9425 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9426 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9427 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9428 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9433 case FUNC_PLT_RELATIVE
:
9436 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9437 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9438 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9439 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9444 case FUNC_SEC_RELATIVE
:
9447 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9448 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9449 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9450 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9455 case FUNC_SEG_RELATIVE
:
9458 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9459 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9460 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9461 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9466 case FUNC_LTV_RELATIVE
:
9469 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9470 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9471 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9472 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9477 case FUNC_LT_FPTR_RELATIVE
:
9480 case BFD_RELOC_IA64_IMM22
:
9481 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9482 case BFD_RELOC_IA64_IMM64
:
9483 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9491 /* Hmmmm. Should this ever occur? */
9498 /* Here is where generate the appropriate reloc for pseudo relocation
9501 ia64_validate_fix (fix
)
9504 switch (fix
->fx_r_type
)
9506 case BFD_RELOC_IA64_FPTR64I
:
9507 case BFD_RELOC_IA64_FPTR32MSB
:
9508 case BFD_RELOC_IA64_FPTR64LSB
:
9509 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9510 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9511 if (fix
->fx_offset
!= 0)
9512 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9513 "No addend allowed in @fptr() relocation");
9523 fix_insn (fix
, odesc
, value
)
9525 const struct ia64_operand
*odesc
;
9528 bfd_vma insn
[3], t0
, t1
, control_bits
;
9533 slot
= fix
->fx_where
& 0x3;
9534 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9536 /* Bundles are always in little-endian byte order */
9537 t0
= bfd_getl64 (fixpos
);
9538 t1
= bfd_getl64 (fixpos
+ 8);
9539 control_bits
= t0
& 0x1f;
9540 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9541 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9542 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9545 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9547 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9548 insn
[2] |= (((value
& 0x7f) << 13)
9549 | (((value
>> 7) & 0x1ff) << 27)
9550 | (((value
>> 16) & 0x1f) << 22)
9551 | (((value
>> 21) & 0x1) << 21)
9552 | (((value
>> 63) & 0x1) << 36));
9554 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9556 if (value
& ~0x3fffffffffffffffULL
)
9557 err
= "integer operand out of range";
9558 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9559 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9561 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9564 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9565 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9566 | (((value
>> 0) & 0xfffff) << 13));
9569 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9572 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9574 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9575 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9576 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
9577 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
9580 /* Attempt to simplify or even eliminate a fixup. The return value is
9581 ignored; perhaps it was once meaningful, but now it is historical.
9582 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9584 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9587 md_apply_fix3 (fix
, valuep
, seg
)
9593 valueT value
= *valuep
;
9596 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9600 switch (fix
->fx_r_type
)
9602 case BFD_RELOC_IA64_DIR32MSB
:
9603 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9607 case BFD_RELOC_IA64_DIR32LSB
:
9608 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9612 case BFD_RELOC_IA64_DIR64MSB
:
9613 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9617 case BFD_RELOC_IA64_DIR64LSB
:
9618 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9628 switch (fix
->fx_r_type
)
9631 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9632 "%s must have a constant value",
9633 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9640 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9641 work. There should be a better way to handle this. */
9643 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9645 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9647 if (fix
->tc_fix_data
.bigendian
)
9648 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9650 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9656 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9663 /* Generate the BFD reloc to be stuck in the object file from the
9664 fixup used internally in the assembler. */
9667 tc_gen_reloc (sec
, fixp
)
9673 reloc
= xmalloc (sizeof (*reloc
));
9674 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9675 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9676 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9677 reloc
->addend
= fixp
->fx_offset
;
9678 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9682 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9683 "Cannot represent %s relocation in object file",
9684 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9689 /* Turn a string in input_line_pointer into a floating point constant
9690 of type TYPE, and store the appropriate bytes in *LIT. The number
9691 of LITTLENUMS emitted is stored in *SIZE. An error message is
9692 returned, or NULL on OK. */
9694 #define MAX_LITTLENUMS 5
9697 md_atof (type
, lit
, size
)
9702 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9703 LITTLENUM_TYPE
*word
;
9733 return "Bad call to MD_ATOF()";
9735 t
= atof_ieee (input_line_pointer
, type
, words
);
9737 input_line_pointer
= t
;
9738 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9740 for (word
= words
+ prec
- 1; prec
--;)
9742 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9743 lit
+= sizeof (LITTLENUM_TYPE
);
9748 /* Round up a section's size to the appropriate boundary. */
9750 md_section_align (seg
, size
)
9754 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9755 valueT mask
= ((valueT
) 1 << align
) - 1;
9757 return (size
+ mask
) & ~mask
;
9760 /* Handle ia64 specific semantics of the align directive. */
9763 ia64_md_do_align (n
, fill
, len
, max
)
9769 /* Fill any pending bundle with nops. */
9770 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
9771 ia64_flush_insns ();
9773 /* When we align code in a text section, emit a bundle of 3 nops instead of
9774 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9775 N is log base 2 of the requested alignment. */
9777 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
9780 /* Use mfi bundle of nops with no stop bits. */
9781 static const unsigned char be_nop
[]
9782 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9783 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9784 static const unsigned char le_nop
[]
9785 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9786 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9788 /* Make sure we are on a 16-byte boundary, in case someone has been
9789 putting data into a text section. */
9790 frag_align (4, 0, 0);
9792 if (target_big_endian
)
9793 frag_align_pattern (n
, be_nop
, 16, max
);
9795 frag_align_pattern (n
, le_nop
, 16, max
);