1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "M:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
225 unsigned int src_line
;
226 struct dwarf2_line_info debug_line
;
234 struct dynreg
*next
; /* next dynamic register */
236 unsigned short base
; /* the base register number */
237 unsigned short num_regs
; /* # of registers in this set */
239 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
241 flagword flags
; /* ELF-header flags */
244 unsigned hint
:1; /* is this hint currently valid? */
245 bfd_vma offset
; /* mem.offset offset */
246 bfd_vma base
; /* mem.offset base */
249 int path
; /* number of alt. entry points seen */
250 const char **entry_labels
; /* labels of all alternate paths in
251 the current DV-checking block. */
252 int maxpaths
; /* size currently allocated for
257 /* application registers: */
263 #define AR_BSPSTORE 18
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
309 /* control registers: */
351 static const struct const_desc
358 /* PSR constant masks: */
361 {"psr.be", ((valueT
) 1) << 1},
362 {"psr.up", ((valueT
) 1) << 2},
363 {"psr.ac", ((valueT
) 1) << 3},
364 {"psr.mfl", ((valueT
) 1) << 4},
365 {"psr.mfh", ((valueT
) 1) << 5},
367 {"psr.ic", ((valueT
) 1) << 13},
368 {"psr.i", ((valueT
) 1) << 14},
369 {"psr.pk", ((valueT
) 1) << 15},
371 {"psr.dt", ((valueT
) 1) << 17},
372 {"psr.dfl", ((valueT
) 1) << 18},
373 {"psr.dfh", ((valueT
) 1) << 19},
374 {"psr.sp", ((valueT
) 1) << 20},
375 {"psr.pp", ((valueT
) 1) << 21},
376 {"psr.di", ((valueT
) 1) << 22},
377 {"psr.si", ((valueT
) 1) << 23},
378 {"psr.db", ((valueT
) 1) << 24},
379 {"psr.lp", ((valueT
) 1) << 25},
380 {"psr.tb", ((valueT
) 1) << 26},
381 {"psr.rt", ((valueT
) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT
) 1) << 34},
385 {"psr.mc", ((valueT
) 1) << 35},
386 {"psr.it", ((valueT
) 1) << 36},
387 {"psr.id", ((valueT
) 1) << 37},
388 {"psr.da", ((valueT
) 1) << 38},
389 {"psr.dd", ((valueT
) 1) << 39},
390 {"psr.ss", ((valueT
) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT
) 1) << 43},
393 {"psr.bn", ((valueT
) 1) << 44},
396 /* indirect register-sets/memory: */
405 { "CPUID", IND_CPUID
},
406 { "cpuid", IND_CPUID
},
418 /* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC
},
443 { "gprel", PSEUDO_FUNC_RELOC
},
444 { "ltoff", PSEUDO_FUNC_RELOC
},
445 { "pcrel", PSEUDO_FUNC_RELOC
},
446 { "pltoff", PSEUDO_FUNC_RELOC
},
447 { "secrel", PSEUDO_FUNC_RELOC
},
448 { "segrel", PSEUDO_FUNC_RELOC
},
449 { "ltv", PSEUDO_FUNC_RELOC
},
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
459 /* fclass constants: */
460 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
461 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
470 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
481 /* 41-bit nop opcodes (one per unit): */
482 static const bfd_vma nop
[IA64_NUM_UNITS
] =
484 0x0000000000LL
, /* NIL => break 0 */
485 0x0008000000LL
, /* I-unit nop */
486 0x0008000000LL
, /* M-unit nop */
487 0x4000000000LL
, /* B-unit nop */
488 0x0008000000LL
, /* F-unit nop */
489 0x0008000000LL
, /* L-"unit" nop */
490 0x0008000000LL
, /* X-unit nop */
493 /* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495 static char special_section_name
[][20] =
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
501 /* The best template for a particular sequence of up to three
503 #define N IA64_NUM_TYPES
504 static unsigned char best_template
[N
][N
][N
];
507 /* Resource dependencies currently in effect */
509 int depind
; /* dependency index */
510 const struct ia64_dependency
*dependency
; /* actual dependency */
511 unsigned specific
:1, /* is this a specific bit/regno? */
512 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
513 int index
; /* specific regno/bit within dependency */
514 int note
; /* optional qualifying note (0 if none) */
518 int insn_srlz
; /* current insn serialization state */
519 int data_srlz
; /* current data serialization state */
520 int qp_regno
; /* qualifying predicate for this usage */
521 char *file
; /* what file marked this dependency */
522 int line
; /* what line marked this dependency */
523 struct mem_offset mem_offset
; /* optional memory offset hint */
524 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
525 int path
; /* corresponding code entry index */
527 static int regdepslen
= 0;
528 static int regdepstotlen
= 0;
529 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
530 static const char *dv_sem
[] = { "none", "implied", "impliedf",
531 "data", "instr", "specific", "stop", "other" };
532 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
534 /* Current state of PR mutexation */
535 static struct qpmutex
{
538 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
539 static int qp_mutexeslen
= 0;
540 static int qp_mutexestotlen
= 0;
541 static valueT qp_safe_across_calls
= 0;
543 /* Current state of PR implications */
544 static struct qp_imply
{
547 unsigned p2_branched
:1;
549 } *qp_implies
= NULL
;
550 static int qp_implieslen
= 0;
551 static int qp_impliestotlen
= 0;
553 /* Keep track of static GR values so that indirect register usage can
554 sometimes be tracked. */
559 } gr_values
[128] = {{ 1, 0 }};
561 /* These are the routines required to output the various types of
564 typedef struct unw_rec_list
{
566 unsigned long slot_number
;
567 struct unw_rec_list
*next
;
570 #define SLOT_NUM_NOT_SET -1
574 unsigned long next_slot_number
;
576 /* Maintain a list of unwind entries for the current function. */
580 /* Any unwind entires that should be attached to the current slot
581 that an insn is being constructed for. */
582 unw_rec_list
*current_entry
;
584 /* These are used to create the unwind table entry for this function. */
587 symbolS
*info
; /* pointer to unwind info */
588 symbolS
*personality_routine
;
590 /* TRUE if processing unwind directives in a prologue region. */
595 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
597 /* Forward delarations: */
598 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
599 static void set_section
PARAMS ((char *name
));
600 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
601 unsigned int, unsigned int));
602 static void dot_radix
PARAMS ((int));
603 static void dot_special_section
PARAMS ((int));
604 static void dot_proc
PARAMS ((int));
605 static void dot_fframe
PARAMS ((int));
606 static void dot_vframe
PARAMS ((int));
607 static void dot_vframesp
PARAMS ((int));
608 static void dot_vframepsp
PARAMS ((int));
609 static void dot_save
PARAMS ((int));
610 static void dot_restore
PARAMS ((int));
611 static void dot_restorereg
PARAMS ((int));
612 static void dot_restorereg_p
PARAMS ((int));
613 static void dot_handlerdata
PARAMS ((int));
614 static void dot_unwentry
PARAMS ((int));
615 static void dot_altrp
PARAMS ((int));
616 static void dot_savemem
PARAMS ((int));
617 static void dot_saveg
PARAMS ((int));
618 static void dot_savef
PARAMS ((int));
619 static void dot_saveb
PARAMS ((int));
620 static void dot_savegf
PARAMS ((int));
621 static void dot_spill
PARAMS ((int));
622 static void dot_spillreg
PARAMS ((int));
623 static void dot_spillmem
PARAMS ((int));
624 static void dot_spillreg_p
PARAMS ((int));
625 static void dot_spillmem_p
PARAMS ((int));
626 static void dot_label_state
PARAMS ((int));
627 static void dot_copy_state
PARAMS ((int));
628 static void dot_unwabi
PARAMS ((int));
629 static void dot_personality
PARAMS ((int));
630 static void dot_body
PARAMS ((int));
631 static void dot_prologue
PARAMS ((int));
632 static void dot_endp
PARAMS ((int));
633 static void dot_template
PARAMS ((int));
634 static void dot_regstk
PARAMS ((int));
635 static void dot_rot
PARAMS ((int));
636 static void dot_byteorder
PARAMS ((int));
637 static void dot_psr
PARAMS ((int));
638 static void dot_alias
PARAMS ((int));
639 static void dot_ln
PARAMS ((int));
640 static char *parse_section_name
PARAMS ((void));
641 static void dot_xdata
PARAMS ((int));
642 static void stmt_float_cons
PARAMS ((int));
643 static void stmt_cons_ua
PARAMS ((int));
644 static void dot_xfloat_cons
PARAMS ((int));
645 static void dot_xstringer
PARAMS ((int));
646 static void dot_xdata_ua
PARAMS ((int));
647 static void dot_xfloat_cons_ua
PARAMS ((int));
648 static void print_prmask
PARAMS ((valueT mask
));
649 static void dot_pred_rel
PARAMS ((int));
650 static void dot_reg_val
PARAMS ((int));
651 static void dot_dv_mode
PARAMS ((int));
652 static void dot_entry
PARAMS ((int));
653 static void dot_mem_offset
PARAMS ((int));
654 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
655 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
656 static void declare_register_set
PARAMS ((const char *, int, int));
657 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
658 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
659 int index
, expressionS
*e
));
660 static int parse_operand
PARAMS ((expressionS
*e
));
661 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
662 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
663 static void emit_one_bundle
PARAMS ((void));
664 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
665 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
666 bfd_reloc_code_real_type r_type
));
667 static void insn_group_break
PARAMS ((int, int, int));
668 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
669 struct rsrc
*, int depind
, int path
));
670 static void add_qp_mutex
PARAMS((valueT mask
));
671 static void add_qp_imply
PARAMS((int p1
, int p2
));
672 static void clear_qp_branch_flag
PARAMS((valueT mask
));
673 static void clear_qp_mutex
PARAMS((valueT mask
));
674 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
675 static void clear_register_values
PARAMS ((void));
676 static void print_dependency
PARAMS ((const char *action
, int depind
));
677 static void instruction_serialization
PARAMS ((void));
678 static void data_serialization
PARAMS ((void));
679 static void remove_marked_resource
PARAMS ((struct rsrc
*));
680 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
681 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
682 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
683 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
684 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
685 struct ia64_opcode
*, int, struct rsrc
[], int, int));
686 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
687 static void check_dependencies
PARAMS((struct ia64_opcode
*));
688 static void mark_resources
PARAMS((struct ia64_opcode
*));
689 static void update_dependencies
PARAMS((struct ia64_opcode
*));
690 static void note_register_values
PARAMS((struct ia64_opcode
*));
691 static int qp_mutex
PARAMS ((int, int, int));
692 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
693 static void output_vbyte_mem
PARAMS ((int, char *, char *));
694 static void count_output
PARAMS ((int, char *, char *));
695 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
696 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
697 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
698 static void output_P1_format
PARAMS ((vbyte_func
, int));
699 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
700 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
701 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
702 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
703 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
704 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
705 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
706 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
707 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
708 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
709 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
710 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
711 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
712 static char format_ab_reg
PARAMS ((int, int));
713 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
715 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
716 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
718 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
719 static void free_list_records
PARAMS ((unw_rec_list
*));
720 static unw_rec_list
*output_prologue
PARAMS ((void));
721 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
722 static unw_rec_list
*output_body
PARAMS ((void));
723 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
724 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
725 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
726 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
727 static unw_rec_list
*output_rp_when
PARAMS ((void));
728 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
729 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
730 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
731 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
732 static unw_rec_list
*output_pfs_when
PARAMS ((void));
733 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
734 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
735 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
736 static unw_rec_list
*output_preds_when
PARAMS ((void));
737 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
738 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
739 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
740 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
741 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
742 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
743 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
744 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
745 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
746 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
747 static unw_rec_list
*output_unat_when
PARAMS ((void));
748 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
749 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
750 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
751 static unw_rec_list
*output_lc_when
PARAMS ((void));
752 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
753 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
754 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
755 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
756 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
757 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
758 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
759 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
760 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
761 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
762 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
763 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
764 static unw_rec_list
*output_bsp_when
PARAMS ((void));
765 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
766 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
767 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
768 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
769 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
770 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
771 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
772 static unw_rec_list
*output_rnat_when
PARAMS ((void));
773 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
774 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
775 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
776 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
777 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
778 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
779 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
780 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
781 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
782 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
784 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
786 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
788 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
789 unsigned int, unsigned int));
790 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
791 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
792 static int calc_record_size
PARAMS ((unw_rec_list
*));
793 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
794 static int count_bits
PARAMS ((unsigned long));
795 static unsigned long slot_index
PARAMS ((unsigned long, unsigned long));
796 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
797 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
798 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
799 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
800 static int generate_unwind_image
PARAMS ((void));
802 /* Determine if application register REGNUM resides in the integer
803 unit (as opposed to the memory unit). */
805 ar_is_in_integer_unit (reg
)
810 return (reg
== 64 /* pfs */
811 || reg
== 65 /* lc */
812 || reg
== 66 /* ec */
813 /* ??? ias accepts and puts these in the integer unit. */
814 || (reg
>= 112 && reg
<= 127));
817 /* Switch to section NAME and create section if necessary. It's
818 rather ugly that we have to manipulate input_line_pointer but I
819 don't see any other way to accomplish the same thing without
820 changing obj-elf.c (which may be the Right Thing, in the end). */
825 char *saved_input_line_pointer
;
827 saved_input_line_pointer
= input_line_pointer
;
828 input_line_pointer
= name
;
830 input_line_pointer
= saved_input_line_pointer
;
833 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
836 ia64_elf_section_flags (flags
, attr
, type
)
840 if (attr
& SHF_IA_64_SHORT
)
841 flags
|= SEC_SMALL_DATA
;
846 set_regstack (ins
, locs
, outs
, rots
)
847 unsigned int ins
, locs
, outs
, rots
;
852 sof
= ins
+ locs
+ outs
;
855 as_bad ("Size of frame exceeds maximum of 96 registers");
860 as_warn ("Size of rotating registers exceeds frame size");
863 md
.in
.base
= REG_GR
+ 32;
864 md
.loc
.base
= md
.in
.base
+ ins
;
865 md
.out
.base
= md
.loc
.base
+ locs
;
867 md
.in
.num_regs
= ins
;
868 md
.loc
.num_regs
= locs
;
869 md
.out
.num_regs
= outs
;
870 md
.rot
.num_regs
= rots
;
877 struct label_fix
*lfix
;
879 subsegT saved_subseg
;
881 if (!md
.last_text_seg
)
885 saved_subseg
= now_subseg
;
887 subseg_set (md
.last_text_seg
, 0);
889 while (md
.num_slots_in_use
> 0)
890 emit_one_bundle (); /* force out queued instructions */
892 /* In case there are labels following the last instruction, resolve
894 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
896 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
897 symbol_set_frag (lfix
->sym
, frag_now
);
899 CURR_SLOT
.label_fixups
= 0;
901 subseg_set (saved_seg
, saved_subseg
);
905 ia64_do_align (nbytes
)
908 char *saved_input_line_pointer
= input_line_pointer
;
910 input_line_pointer
= "";
911 s_align_bytes (nbytes
);
912 input_line_pointer
= saved_input_line_pointer
;
916 ia64_cons_align (nbytes
)
921 char *saved_input_line_pointer
= input_line_pointer
;
922 input_line_pointer
= "";
923 s_align_bytes (nbytes
);
924 input_line_pointer
= saved_input_line_pointer
;
928 /* Output COUNT bytes to a memory location. */
929 static unsigned char *vbyte_mem_ptr
= NULL
;
932 output_vbyte_mem (count
, ptr
, comment
)
938 if (vbyte_mem_ptr
== NULL
)
943 for (x
= 0; x
< count
; x
++)
944 *(vbyte_mem_ptr
++) = ptr
[x
];
947 /* Count the number of bytes required for records. */
948 static int vbyte_count
= 0;
950 count_output (count
, ptr
, comment
)
955 vbyte_count
+= count
;
959 output_R1_format (f
, rtype
, rlen
)
961 unw_record_type rtype
;
968 output_R3_format (f
, rtype
, rlen
);
974 else if (rtype
!= prologue
)
975 as_bad ("record type is not valid");
977 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
978 (*f
) (1, &byte
, NULL
);
982 output_R2_format (f
, mask
, grsave
, rlen
)
989 mask
= (mask
& 0x0f);
990 grsave
= (grsave
& 0x7f);
992 bytes
[0] = (UNW_R2
| (mask
>> 1));
993 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
994 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
995 (*f
) (count
, bytes
, NULL
);
999 output_R3_format (f
, rtype
, rlen
)
1001 unw_record_type rtype
;
1008 output_R1_format (f
, rtype
, rlen
);
1014 else if (rtype
!= prologue
)
1015 as_bad ("record type is not valid");
1016 bytes
[0] = (UNW_R3
| r
);
1017 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1018 (*f
) (count
+ 1, bytes
, NULL
);
1022 output_P1_format (f
, brmask
)
1027 byte
= UNW_P1
| (brmask
& 0x1f);
1028 (*f
) (1, &byte
, NULL
);
1032 output_P2_format (f
, brmask
, gr
)
1038 brmask
= (brmask
& 0x1f);
1039 bytes
[0] = UNW_P2
| (brmask
>> 1);
1040 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1041 (*f
) (2, bytes
, NULL
);
1045 output_P3_format (f
, rtype
, reg
)
1047 unw_record_type rtype
;
1092 as_bad ("Invalid record type for P3 format.");
1094 bytes
[0] = (UNW_P3
| (r
>> 1));
1095 bytes
[1] = (((r
& 1) << 7) | reg
);
1096 (*f
) (2, bytes
, NULL
);
1100 output_P4_format (f
, imask
, imask_size
)
1102 unsigned char *imask
;
1103 unsigned long imask_size
;
1106 (*f
) (imask_size
, imask
, NULL
);
1110 output_P5_format (f
, grmask
, frmask
)
1113 unsigned long frmask
;
1116 grmask
= (grmask
& 0x0f);
1119 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1120 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1121 bytes
[3] = (frmask
& 0x000000ff);
1122 (*f
) (4, bytes
, NULL
);
1126 output_P6_format (f
, rtype
, rmask
)
1128 unw_record_type rtype
;
1134 if (rtype
== gr_mem
)
1136 else if (rtype
!= fr_mem
)
1137 as_bad ("Invalid record type for format P6");
1138 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1139 (*f
) (1, &byte
, NULL
);
1143 output_P7_format (f
, rtype
, w1
, w2
)
1145 unw_record_type rtype
;
1152 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1157 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1207 bytes
[0] = (UNW_P7
| r
);
1208 (*f
) (count
, bytes
, NULL
);
1212 output_P8_format (f
, rtype
, t
)
1214 unw_record_type rtype
;
1253 case bspstore_psprel
:
1256 case bspstore_sprel
:
1268 case priunat_when_gr
:
1271 case priunat_psprel
:
1277 case priunat_when_mem
:
1284 count
+= output_leb128 (bytes
+ 2, t
, 0);
1285 (*f
) (count
, bytes
, NULL
);
1289 output_P9_format (f
, grmask
, gr
)
1296 bytes
[1] = (grmask
& 0x0f);
1297 bytes
[2] = (gr
& 0x7f);
1298 (*f
) (3, bytes
, NULL
);
1302 output_P10_format (f
, abi
, context
)
1309 bytes
[1] = (abi
& 0xff);
1310 bytes
[2] = (context
& 0xff);
1311 (*f
) (3, bytes
, NULL
);
1315 output_B1_format (f
, rtype
, label
)
1317 unw_record_type rtype
;
1318 unsigned long label
;
1324 output_B4_format (f
, rtype
, label
);
1327 if (rtype
== copy_state
)
1329 else if (rtype
!= label_state
)
1330 as_bad ("Invalid record type for format B1");
1332 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1333 (*f
) (1, &byte
, NULL
);
1337 output_B2_format (f
, ecount
, t
)
1339 unsigned long ecount
;
1346 output_B3_format (f
, ecount
, t
);
1349 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1350 count
+= output_leb128 (bytes
+ 1, t
, 0);
1351 (*f
) (count
, bytes
, NULL
);
1355 output_B3_format (f
, ecount
, t
)
1357 unsigned long ecount
;
1364 output_B2_format (f
, ecount
, t
);
1368 count
+= output_leb128 (bytes
+ 1, t
, 0);
1369 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1370 (*f
) (count
, bytes
, NULL
);
1374 output_B4_format (f
, rtype
, label
)
1376 unw_record_type rtype
;
1377 unsigned long label
;
1384 output_B1_format (f
, rtype
, label
);
1388 if (rtype
== copy_state
)
1390 else if (rtype
!= label_state
)
1391 as_bad ("Invalid record type for format B1");
1393 bytes
[0] = (UNW_B4
| (r
<< 3));
1394 count
+= output_leb128 (bytes
+ 1, label
, 0);
1395 (*f
) (count
, bytes
, NULL
);
1399 format_ab_reg (ab
, reg
)
1406 ret
= (ab
<< 5) | reg
;
1411 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1413 unw_record_type rtype
;
1423 if (rtype
== spill_sprel
)
1425 else if (rtype
!= spill_psprel
)
1426 as_bad ("Invalid record type for format X1");
1427 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1428 count
+= output_leb128 (bytes
+ 2, t
, 0);
1429 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1430 (*f
) (count
, bytes
, NULL
);
1434 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1443 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1444 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1445 count
+= output_leb128 (bytes
+ 3, t
, 0);
1446 (*f
) (count
, bytes
, NULL
);
1450 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1452 unw_record_type rtype
;
1463 if (rtype
== spill_sprel_p
)
1465 else if (rtype
!= spill_psprel_p
)
1466 as_bad ("Invalid record type for format X3");
1467 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1468 bytes
[2] = format_ab_reg (ab
, reg
);
1469 count
+= output_leb128 (bytes
+ 3, t
, 0);
1470 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1471 (*f
) (count
, bytes
, NULL
);
1475 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1485 bytes
[1] = (qp
& 0x3f);
1486 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1487 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1488 count
+= output_leb128 (bytes
+ 4, t
, 0);
1489 (*f
) (count
, bytes
, NULL
);
1492 /* This function allocates a record list structure, and initializes fields. */
1494 static unw_rec_list
*
1495 alloc_record (unw_record_type t
)
1498 ptr
= xmalloc (sizeof (*ptr
));
1500 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1505 /* This function frees an entire list of record structures. */
1508 free_list_records (unw_rec_list
*first
)
1511 for (ptr
= first
; ptr
!= NULL
;)
1513 unw_rec_list
*tmp
= ptr
;
1515 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1516 && tmp
->r
.record
.r
.mask
.i
)
1517 free (tmp
->r
.record
.r
.mask
.i
);
1524 static unw_rec_list
*
1527 unw_rec_list
*ptr
= alloc_record (prologue
);
1528 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1532 static unw_rec_list
*
1533 output_prologue_gr (saved_mask
, reg
)
1534 unsigned int saved_mask
;
1537 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1538 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1539 ptr
->r
.record
.r
.grmask
= saved_mask
;
1540 ptr
->r
.record
.r
.grsave
= reg
;
1544 static unw_rec_list
*
1547 unw_rec_list
*ptr
= alloc_record (body
);
1551 static unw_rec_list
*
1552 output_mem_stack_f (size
)
1555 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1556 ptr
->r
.record
.p
.size
= size
;
1560 static unw_rec_list
*
1561 output_mem_stack_v ()
1563 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1567 static unw_rec_list
*
1571 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1572 ptr
->r
.record
.p
.gr
= gr
;
1576 static unw_rec_list
*
1577 output_psp_sprel (offset
)
1578 unsigned int offset
;
1580 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1581 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1585 static unw_rec_list
*
1588 unw_rec_list
*ptr
= alloc_record (rp_when
);
1592 static unw_rec_list
*
1596 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1597 ptr
->r
.record
.p
.gr
= gr
;
1601 static unw_rec_list
*
1605 unw_rec_list
*ptr
= alloc_record (rp_br
);
1606 ptr
->r
.record
.p
.br
= br
;
1610 static unw_rec_list
*
1611 output_rp_psprel (offset
)
1612 unsigned int offset
;
1614 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1615 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1619 static unw_rec_list
*
1620 output_rp_sprel (offset
)
1621 unsigned int offset
;
1623 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1624 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1628 static unw_rec_list
*
1631 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1635 static unw_rec_list
*
1639 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1640 ptr
->r
.record
.p
.gr
= gr
;
1644 static unw_rec_list
*
1645 output_pfs_psprel (offset
)
1646 unsigned int offset
;
1648 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1649 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1653 static unw_rec_list
*
1654 output_pfs_sprel (offset
)
1655 unsigned int offset
;
1657 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1658 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1662 static unw_rec_list
*
1663 output_preds_when ()
1665 unw_rec_list
*ptr
= alloc_record (preds_when
);
1669 static unw_rec_list
*
1670 output_preds_gr (gr
)
1673 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1674 ptr
->r
.record
.p
.gr
= gr
;
1678 static unw_rec_list
*
1679 output_preds_psprel (offset
)
1680 unsigned int offset
;
1682 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1683 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1687 static unw_rec_list
*
1688 output_preds_sprel (offset
)
1689 unsigned int offset
;
1691 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1692 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1696 static unw_rec_list
*
1697 output_fr_mem (mask
)
1700 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1701 ptr
->r
.record
.p
.rmask
= mask
;
1705 static unw_rec_list
*
1706 output_frgr_mem (gr_mask
, fr_mask
)
1707 unsigned int gr_mask
;
1708 unsigned int fr_mask
;
1710 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1711 ptr
->r
.record
.p
.grmask
= gr_mask
;
1712 ptr
->r
.record
.p
.frmask
= fr_mask
;
1716 static unw_rec_list
*
1717 output_gr_gr (mask
, reg
)
1721 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1722 ptr
->r
.record
.p
.grmask
= mask
;
1723 ptr
->r
.record
.p
.gr
= reg
;
1727 static unw_rec_list
*
1728 output_gr_mem (mask
)
1731 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1732 ptr
->r
.record
.p
.rmask
= mask
;
1736 static unw_rec_list
*
1737 output_br_mem (unsigned int mask
)
1739 unw_rec_list
*ptr
= alloc_record (br_mem
);
1740 ptr
->r
.record
.p
.brmask
= mask
;
1744 static unw_rec_list
*
1745 output_br_gr (save_mask
, reg
)
1746 unsigned int save_mask
;
1749 unw_rec_list
*ptr
= alloc_record (br_gr
);
1750 ptr
->r
.record
.p
.brmask
= save_mask
;
1751 ptr
->r
.record
.p
.gr
= reg
;
1755 static unw_rec_list
*
1756 output_spill_base (offset
)
1757 unsigned int offset
;
1759 unw_rec_list
*ptr
= alloc_record (spill_base
);
1760 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1764 static unw_rec_list
*
1767 unw_rec_list
*ptr
= alloc_record (unat_when
);
1771 static unw_rec_list
*
1775 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1776 ptr
->r
.record
.p
.gr
= gr
;
1780 static unw_rec_list
*
1781 output_unat_psprel (offset
)
1782 unsigned int offset
;
1784 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1785 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1789 static unw_rec_list
*
1790 output_unat_sprel (offset
)
1791 unsigned int offset
;
1793 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1794 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1798 static unw_rec_list
*
1801 unw_rec_list
*ptr
= alloc_record (lc_when
);
1805 static unw_rec_list
*
1809 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1810 ptr
->r
.record
.p
.gr
= gr
;
1814 static unw_rec_list
*
1815 output_lc_psprel (offset
)
1816 unsigned int offset
;
1818 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1819 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1823 static unw_rec_list
*
1824 output_lc_sprel (offset
)
1825 unsigned int offset
;
1827 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1828 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1832 static unw_rec_list
*
1835 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1839 static unw_rec_list
*
1843 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1844 ptr
->r
.record
.p
.gr
= gr
;
1848 static unw_rec_list
*
1849 output_fpsr_psprel (offset
)
1850 unsigned int offset
;
1852 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1853 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1857 static unw_rec_list
*
1858 output_fpsr_sprel (offset
)
1859 unsigned int offset
;
1861 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1862 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1866 static unw_rec_list
*
1867 output_priunat_when_gr ()
1869 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1873 static unw_rec_list
*
1874 output_priunat_when_mem ()
1876 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1880 static unw_rec_list
*
1881 output_priunat_gr (gr
)
1884 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1885 ptr
->r
.record
.p
.gr
= gr
;
1889 static unw_rec_list
*
1890 output_priunat_psprel (offset
)
1891 unsigned int offset
;
1893 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1894 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1898 static unw_rec_list
*
1899 output_priunat_sprel (offset
)
1900 unsigned int offset
;
1902 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1903 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1907 static unw_rec_list
*
1910 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1914 static unw_rec_list
*
1918 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1919 ptr
->r
.record
.p
.gr
= gr
;
1923 static unw_rec_list
*
1924 output_bsp_psprel (offset
)
1925 unsigned int offset
;
1927 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1928 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1932 static unw_rec_list
*
1933 output_bsp_sprel (offset
)
1934 unsigned int offset
;
1936 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1937 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1941 static unw_rec_list
*
1942 output_bspstore_when ()
1944 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
1948 static unw_rec_list
*
1949 output_bspstore_gr (gr
)
1952 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
1953 ptr
->r
.record
.p
.gr
= gr
;
1957 static unw_rec_list
*
1958 output_bspstore_psprel (offset
)
1959 unsigned int offset
;
1961 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
1962 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1966 static unw_rec_list
*
1967 output_bspstore_sprel (offset
)
1968 unsigned int offset
;
1970 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
1971 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1975 static unw_rec_list
*
1978 unw_rec_list
*ptr
= alloc_record (rnat_when
);
1982 static unw_rec_list
*
1986 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
1987 ptr
->r
.record
.p
.gr
= gr
;
1991 static unw_rec_list
*
1992 output_rnat_psprel (offset
)
1993 unsigned int offset
;
1995 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
1996 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2000 static unw_rec_list
*
2001 output_rnat_sprel (offset
)
2002 unsigned int offset
;
2004 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2005 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2009 static unw_rec_list
*
2010 output_unwabi (abi
, context
)
2012 unsigned long context
;
2014 unw_rec_list
*ptr
= alloc_record (unwabi
);
2015 ptr
->r
.record
.p
.abi
= abi
;
2016 ptr
->r
.record
.p
.context
= context
;
2020 static unw_rec_list
*
2021 output_epilogue (unsigned long ecount
)
2023 unw_rec_list
*ptr
= alloc_record (epilogue
);
2024 ptr
->r
.record
.b
.ecount
= ecount
;
2028 static unw_rec_list
*
2029 output_label_state (unsigned long label
)
2031 unw_rec_list
*ptr
= alloc_record (label_state
);
2032 ptr
->r
.record
.b
.label
= label
;
2036 static unw_rec_list
*
2037 output_copy_state (unsigned long label
)
2039 unw_rec_list
*ptr
= alloc_record (copy_state
);
2040 ptr
->r
.record
.b
.label
= label
;
2044 static unw_rec_list
*
2045 output_spill_psprel (ab
, reg
, offset
)
2048 unsigned int offset
;
2050 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2051 ptr
->r
.record
.x
.ab
= ab
;
2052 ptr
->r
.record
.x
.reg
= reg
;
2053 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2057 static unw_rec_list
*
2058 output_spill_sprel (ab
, reg
, offset
)
2061 unsigned int offset
;
2063 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2064 ptr
->r
.record
.x
.ab
= ab
;
2065 ptr
->r
.record
.x
.reg
= reg
;
2066 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2070 static unw_rec_list
*
2071 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2074 unsigned int offset
;
2075 unsigned int predicate
;
2077 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2078 ptr
->r
.record
.x
.ab
= ab
;
2079 ptr
->r
.record
.x
.reg
= reg
;
2080 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2081 ptr
->r
.record
.x
.qp
= predicate
;
2085 static unw_rec_list
*
2086 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2089 unsigned int offset
;
2090 unsigned int predicate
;
2092 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2093 ptr
->r
.record
.x
.ab
= ab
;
2094 ptr
->r
.record
.x
.reg
= reg
;
2095 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2096 ptr
->r
.record
.x
.qp
= predicate
;
2100 static unw_rec_list
*
2101 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2104 unsigned int targ_reg
;
2107 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2108 ptr
->r
.record
.x
.ab
= ab
;
2109 ptr
->r
.record
.x
.reg
= reg
;
2110 ptr
->r
.record
.x
.treg
= targ_reg
;
2111 ptr
->r
.record
.x
.xy
= xy
;
2115 static unw_rec_list
*
2116 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2119 unsigned int targ_reg
;
2121 unsigned int predicate
;
2123 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2124 ptr
->r
.record
.x
.ab
= ab
;
2125 ptr
->r
.record
.x
.reg
= reg
;
2126 ptr
->r
.record
.x
.treg
= targ_reg
;
2127 ptr
->r
.record
.x
.xy
= xy
;
2128 ptr
->r
.record
.x
.qp
= predicate
;
2132 /* Given a unw_rec_list process the correct format with the
2133 specified function. */
2136 process_one_record (ptr
, f
)
2140 unsigned long fr_mask
, gr_mask
;
2142 switch (ptr
->r
.type
)
2148 /* These are taken care of by prologue/prologue_gr. */
2153 if (ptr
->r
.type
== prologue_gr
)
2154 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2155 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2157 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2159 /* Output descriptor(s) for union of register spills (if any). */
2160 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2161 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2164 if ((fr_mask
& ~0xfUL
) == 0)
2165 output_P6_format (f
, fr_mem
, fr_mask
);
2168 output_P5_format (f
, gr_mask
, fr_mask
);
2173 output_P6_format (f
, gr_mem
, gr_mask
);
2174 if (ptr
->r
.record
.r
.mask
.br_mem
)
2175 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2177 /* output imask descriptor if necessary: */
2178 if (ptr
->r
.record
.r
.mask
.i
)
2179 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2180 ptr
->r
.record
.r
.imask_size
);
2184 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2188 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2189 ptr
->r
.record
.p
.size
);
2202 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2205 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2208 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2216 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2225 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2235 case bspstore_sprel
:
2237 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2240 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2243 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2246 as_bad ("spill_mask record unimplemented.");
2248 case priunat_when_gr
:
2249 case priunat_when_mem
:
2253 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2255 case priunat_psprel
:
2257 case bspstore_psprel
:
2259 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2262 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2265 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2269 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2272 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2273 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2274 ptr
->r
.record
.x
.pspoff
);
2277 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2278 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2279 ptr
->r
.record
.x
.spoff
);
2282 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2283 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2284 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2286 case spill_psprel_p
:
2287 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2288 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2289 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2292 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2293 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2294 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2297 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2298 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2299 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2303 as_bad ("record_type_not_valid");
2308 /* Given a unw_rec_list list, process all the records with
2309 the specified function. */
2311 process_unw_records (list
, f
)
2316 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2317 process_one_record (ptr
, f
);
2320 /* Determine the size of a record list in bytes. */
2322 calc_record_size (list
)
2326 process_unw_records (list
, count_output
);
2330 /* Update IMASK bitmask to reflect the fact that one or more registers
2331 of type TYPE are saved starting at instruction with index T. If N
2332 bits are set in REGMASK, it is assumed that instructions T through
2333 T+N-1 save these registers.
2337 1: instruction saves next fp reg
2338 2: instruction saves next general reg
2339 3: instruction saves next branch reg */
2341 set_imask (region
, regmask
, t
, type
)
2342 unw_rec_list
*region
;
2343 unsigned long regmask
;
2347 unsigned char *imask
;
2348 unsigned long imask_size
;
2352 imask
= region
->r
.record
.r
.mask
.i
;
2353 imask_size
= region
->r
.record
.r
.imask_size
;
2356 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2357 imask
= xmalloc (imask_size
);
2358 memset (imask
, 0, imask_size
);
2360 region
->r
.record
.r
.imask_size
= imask_size
;
2361 region
->r
.record
.r
.mask
.i
= imask
;
2365 pos
= 2 * (3 - t
% 4);
2368 if (i
>= imask_size
)
2370 as_bad ("Ignoring attempt to spill beyond end of region");
2374 imask
[i
] |= (type
& 0x3) << pos
;
2376 regmask
&= (regmask
- 1);
2387 count_bits (unsigned long mask
)
2400 slot_index (unsigned long slot_addr
, unsigned long first_addr
)
2402 return (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2403 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2406 /* Given a complete record list, process any records which have
2407 unresolved fields, (ie length counts for a prologue). After
2408 this has been run, all neccessary information should be available
2409 within each record to generate an image. */
2412 fixup_unw_records (list
)
2415 unw_rec_list
*ptr
, *region
= 0;
2416 unsigned long first_addr
= 0, rlen
= 0, t
;
2418 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2420 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2421 as_bad (" Insn slot not set in unwind record.");
2422 t
= slot_index (ptr
->slot_number
, first_addr
);
2423 switch (ptr
->r
.type
)
2430 int size
, dir_len
= 0;
2431 unsigned long last_addr
;
2433 first_addr
= ptr
->slot_number
;
2434 ptr
->slot_number
= 0;
2435 /* Find either the next body/prologue start, or the end of
2436 the list, and determine the size of the region. */
2437 last_addr
= unwind
.next_slot_number
;
2438 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2439 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2440 || last
->r
.type
== body
)
2442 last_addr
= last
->slot_number
;
2445 else if (!last
->next
)
2447 /* In the absence of an explicit .body directive,
2448 the prologue ends after the last instruction
2449 covered by an unwind directive. */
2450 if (ptr
->r
.type
!= body
)
2452 last_addr
= last
->slot_number
;
2453 switch (last
->r
.type
)
2456 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2457 + count_bits (last
->r
.record
.p
.grmask
));
2461 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2465 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2468 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2477 size
= slot_index (last_addr
, first_addr
) + dir_len
;
2478 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2483 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2494 case priunat_when_gr
:
2495 case priunat_when_mem
:
2499 ptr
->r
.record
.p
.t
= t
;
2507 case spill_psprel_p
:
2508 ptr
->r
.record
.x
.t
= t
;
2514 as_bad ("frgr_mem record before region record!\n");
2517 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2518 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2519 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2520 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2525 as_bad ("fr_mem record before region record!\n");
2528 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2529 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2534 as_bad ("gr_mem record before region record!\n");
2537 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2538 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2543 as_bad ("br_mem record before region record!\n");
2546 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2547 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2553 as_bad ("gr_gr record before region record!\n");
2556 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2561 as_bad ("br_gr record before region record!\n");
2564 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2573 /* Generate an unwind image from a record list. Returns the number of
2574 bytes in the resulting image. The memory image itselof is returned
2575 in the 'ptr' parameter. */
2577 output_unw_records (list
, ptr
)
2581 int size
, x
, extra
= 0;
2584 fixup_unw_records (list
);
2585 size
= calc_record_size (list
);
2587 /* pad to 8 byte boundry. */
2591 /* Add 8 for the header + 8 more bytes for the personality offset. */
2592 mem
= xmalloc (size
+ extra
+ 16);
2594 vbyte_mem_ptr
= mem
+ 8;
2595 /* Clear the padding area and personality. */
2596 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2597 /* Initialize the header area. */
2598 md_number_to_chars (mem
, (((bfd_vma
) 1 << 48) /* version */
2599 | (unwind
.personality_routine
2600 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2602 | ((size
+ extra
) / 8)), /* length (dwords) */
2605 process_unw_records (list
, output_vbyte_mem
);
2608 return size
+ extra
+ 16;
2612 convert_expr_to_ab_reg (e
, ab
, regp
)
2619 if (e
->X_op
!= O_register
)
2622 reg
= e
->X_add_number
;
2623 if (reg
>= REG_GR
+ 4 && reg
<= REG_GR
+ 7)
2626 *regp
= reg
- REG_GR
;
2628 else if ((reg
>= REG_FR
+ 2 && reg
<= REG_FR
+ 5)
2629 || (reg
>= REG_FR
+ 16 && reg
<= REG_FR
+ 31))
2632 *regp
= reg
- REG_FR
;
2634 else if (reg
>= REG_BR
+ 1 && reg
<= REG_BR
+ 5)
2637 *regp
= reg
- REG_BR
;
2644 case REG_PR
: *regp
= 0; break;
2645 case REG_PSP
: *regp
= 1; break;
2646 case REG_PRIUNAT
: *regp
= 2; break;
2647 case REG_BR
+ 0: *regp
= 3; break;
2648 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2649 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2650 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2651 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2652 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2653 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2654 case REG_AR
+ AR_LC
: *regp
= 10; break;
2664 convert_expr_to_xy_reg (e
, xy
, regp
)
2671 if (e
->X_op
!= O_register
)
2674 reg
= e
->X_add_number
;
2676 if (reg
>= REG_GR
&& reg
<= REG_GR
+ 127)
2679 *regp
= reg
- REG_GR
;
2681 else if (reg
>= REG_FR
&& reg
<= REG_FR
+ 127)
2684 *regp
= reg
- REG_FR
;
2686 else if (reg
>= REG_BR
&& reg
<= REG_BR
+ 7)
2689 *regp
= reg
- REG_BR
;
2703 radix
= *input_line_pointer
++;
2705 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2707 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2708 ignore_rest_of_line ();
2713 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2715 dot_special_section (which
)
2718 set_section ((char *) special_section_name
[which
]);
2722 add_unwind_entry (ptr
)
2726 unwind
.tail
->next
= ptr
;
2731 /* The current entry can in fact be a chain of unwind entries. */
2732 if (unwind
.current_entry
== NULL
)
2733 unwind
.current_entry
= ptr
;
2744 if (e
.X_op
!= O_constant
)
2745 as_bad ("Operand to .fframe must be a constant");
2747 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2758 reg
= e
.X_add_number
- REG_GR
;
2759 if (e
.X_op
== O_register
&& reg
< 128)
2761 add_unwind_entry (output_mem_stack_v ());
2762 if (! (unwind
.prologue_mask
& 2))
2763 add_unwind_entry (output_psp_gr (reg
));
2766 as_bad ("First operand to .vframe must be a general register");
2770 dot_vframesp (dummy
)
2776 if (e
.X_op
== O_constant
)
2778 add_unwind_entry (output_mem_stack_v ());
2779 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2782 as_bad ("First operand to .vframesp must be a general register");
2786 dot_vframepsp (dummy
)
2792 if (e
.X_op
== O_constant
)
2794 add_unwind_entry (output_mem_stack_v ());
2795 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2798 as_bad ("First operand to .vframepsp must be a general register");
2809 sep
= parse_operand (&e1
);
2811 as_bad ("No second operand to .save");
2812 sep
= parse_operand (&e2
);
2814 reg1
= e1
.X_add_number
;
2815 reg2
= e2
.X_add_number
- REG_GR
;
2817 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2818 if (e1
.X_op
== O_register
)
2820 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
2824 case REG_AR
+ AR_BSP
:
2825 add_unwind_entry (output_bsp_when ());
2826 add_unwind_entry (output_bsp_gr (reg2
));
2828 case REG_AR
+ AR_BSPSTORE
:
2829 add_unwind_entry (output_bspstore_when ());
2830 add_unwind_entry (output_bspstore_gr (reg2
));
2832 case REG_AR
+ AR_RNAT
:
2833 add_unwind_entry (output_rnat_when ());
2834 add_unwind_entry (output_rnat_gr (reg2
));
2836 case REG_AR
+ AR_UNAT
:
2837 add_unwind_entry (output_unat_when ());
2838 add_unwind_entry (output_unat_gr (reg2
));
2840 case REG_AR
+ AR_FPSR
:
2841 add_unwind_entry (output_fpsr_when ());
2842 add_unwind_entry (output_fpsr_gr (reg2
));
2844 case REG_AR
+ AR_PFS
:
2845 add_unwind_entry (output_pfs_when ());
2846 if (! (unwind
.prologue_mask
& 4))
2847 add_unwind_entry (output_pfs_gr (reg2
));
2849 case REG_AR
+ AR_LC
:
2850 add_unwind_entry (output_lc_when ());
2851 add_unwind_entry (output_lc_gr (reg2
));
2854 add_unwind_entry (output_rp_when ());
2855 if (! (unwind
.prologue_mask
& 8))
2856 add_unwind_entry (output_rp_gr (reg2
));
2859 add_unwind_entry (output_preds_when ());
2860 if (! (unwind
.prologue_mask
& 1))
2861 add_unwind_entry (output_preds_gr (reg2
));
2864 add_unwind_entry (output_priunat_when_gr ());
2865 add_unwind_entry (output_priunat_gr (reg2
));
2868 as_bad ("First operand not a valid register");
2872 as_bad (" Second operand not a valid register");
2875 as_bad ("First operand not a register");
2883 unsigned long ecount
= 0;
2886 sep
= parse_operand (&e1
);
2887 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2889 as_bad ("First operand to .restore must be stack pointer (sp)");
2895 parse_operand (&e2
);
2896 if (e1
.X_op
!= O_constant
)
2898 as_bad ("Second operand to .restore must be constant");
2903 add_unwind_entry (output_epilogue (ecount
));
2907 dot_restorereg (dummy
)
2910 unsigned int ab
, reg
;
2915 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
2917 as_bad ("First operand to .restorereg must be a preserved register");
2920 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
2924 dot_restorereg_p (dummy
)
2927 unsigned int qp
, ab
, reg
;
2931 sep
= parse_operand (&e1
);
2934 as_bad ("No second operand to .restorereg.p");
2938 parse_operand (&e2
);
2940 qp
= e1
.X_add_number
- REG_P
;
2941 if (e1
.X_op
!= O_register
|| qp
> 63)
2943 as_bad ("First operand to .restorereg.p must be a predicate");
2947 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
2949 as_bad ("Second operand to .restorereg.p must be a preserved register");
2952 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
2956 generate_unwind_image ()
2959 unsigned char *unw_rec
;
2961 /* Force out pending instructions, to make sure all unwind records have
2962 a valid slot_number field. */
2963 ia64_flush_insns ();
2965 /* Generate the unwind record. */
2966 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
2968 as_bad ("Unwind record is not a multiple of 8 bytes.");
2970 /* If there are unwind records, switch sections, and output the info. */
2973 unsigned char *where
;
2975 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
2977 /* Set expression which points to start of unwind descriptor area. */
2978 unwind
.info
= expr_build_dot ();
2980 where
= (unsigned char *) frag_more (size
);
2982 /* Issue a label for this address, and keep track of it to put it
2983 in the unwind section. */
2985 /* Copy the information from the unwind record into this section. The
2986 data is already in the correct byte order. */
2987 memcpy (where
, unw_rec
, size
);
2988 /* Add the personality address to the image. */
2989 if (unwind
.personality_routine
!= 0)
2991 exp
.X_op
= O_symbol
;
2992 exp
.X_add_symbol
= unwind
.personality_routine
;
2993 exp
.X_add_number
= 0;
2994 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
2995 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
2996 unwind
.personality_routine
= 0;
2998 obj_elf_previous (0);
3001 free_list_records (unwind
.list
);
3002 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3008 dot_handlerdata (dummy
)
3011 generate_unwind_image ();
3012 demand_empty_rest_of_line ();
3016 dot_unwentry (dummy
)
3019 demand_empty_rest_of_line ();
3030 reg
= e
.X_add_number
- REG_BR
;
3031 if (e
.X_op
== O_register
&& reg
< 8)
3032 add_unwind_entry (output_rp_br (reg
));
3034 as_bad ("First operand not a valid branch register");
3038 dot_savemem (psprel
)
3045 sep
= parse_operand (&e1
);
3047 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3048 sep
= parse_operand (&e2
);
3050 reg1
= e1
.X_add_number
;
3051 val
= e2
.X_add_number
;
3053 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3054 if (e1
.X_op
== O_register
)
3056 if (e2
.X_op
== O_constant
)
3060 case REG_AR
+ AR_BSP
:
3061 add_unwind_entry (output_bsp_when ());
3062 add_unwind_entry ((psprel
3064 : output_bsp_sprel
) (val
));
3066 case REG_AR
+ AR_BSPSTORE
:
3067 add_unwind_entry (output_bspstore_when ());
3068 add_unwind_entry ((psprel
3069 ? output_bspstore_psprel
3070 : output_bspstore_sprel
) (val
));
3072 case REG_AR
+ AR_RNAT
:
3073 add_unwind_entry (output_rnat_when ());
3074 add_unwind_entry ((psprel
3075 ? output_rnat_psprel
3076 : output_rnat_sprel
) (val
));
3078 case REG_AR
+ AR_UNAT
:
3079 add_unwind_entry (output_unat_when ());
3080 add_unwind_entry ((psprel
3081 ? output_unat_psprel
3082 : output_unat_sprel
) (val
));
3084 case REG_AR
+ AR_FPSR
:
3085 add_unwind_entry (output_fpsr_when ());
3086 add_unwind_entry ((psprel
3087 ? output_fpsr_psprel
3088 : output_fpsr_sprel
) (val
));
3090 case REG_AR
+ AR_PFS
:
3091 add_unwind_entry (output_pfs_when ());
3092 add_unwind_entry ((psprel
3094 : output_pfs_sprel
) (val
));
3096 case REG_AR
+ AR_LC
:
3097 add_unwind_entry (output_lc_when ());
3098 add_unwind_entry ((psprel
3100 : output_lc_sprel
) (val
));
3103 add_unwind_entry (output_rp_when ());
3104 add_unwind_entry ((psprel
3106 : output_rp_sprel
) (val
));
3109 add_unwind_entry (output_preds_when ());
3110 add_unwind_entry ((psprel
3111 ? output_preds_psprel
3112 : output_preds_sprel
) (val
));
3115 add_unwind_entry (output_priunat_when_mem ());
3116 add_unwind_entry ((psprel
3117 ? output_priunat_psprel
3118 : output_priunat_sprel
) (val
));
3121 as_bad ("First operand not a valid register");
3125 as_bad (" Second operand not a valid constant");
3128 as_bad ("First operand not a register");
3137 sep
= parse_operand (&e1
);
3139 parse_operand (&e2
);
3141 if (e1
.X_op
!= O_constant
)
3142 as_bad ("First operand to .save.g must be a constant.");
3145 int grmask
= e1
.X_add_number
;
3147 add_unwind_entry (output_gr_mem (grmask
));
3150 int reg
= e2
.X_add_number
- REG_GR
;
3151 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3152 add_unwind_entry (output_gr_gr (grmask
, reg
));
3154 as_bad ("Second operand is an invalid register.");
3165 sep
= parse_operand (&e1
);
3167 if (e1
.X_op
!= O_constant
)
3168 as_bad ("Operand to .save.f must be a constant.");
3170 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3182 sep
= parse_operand (&e1
);
3183 if (e1
.X_op
!= O_constant
)
3185 as_bad ("First operand to .save.b must be a constant.");
3188 brmask
= e1
.X_add_number
;
3192 sep
= parse_operand (&e2
);
3193 reg
= e2
.X_add_number
- REG_GR
;
3194 if (e2
.X_op
!= O_register
|| reg
> 127)
3196 as_bad ("Second operand to .save.b must be a general register.");
3199 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3202 add_unwind_entry (output_br_mem (brmask
));
3204 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3205 ignore_rest_of_line ();
3214 sep
= parse_operand (&e1
);
3216 parse_operand (&e2
);
3218 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3219 as_bad ("Both operands of .save.gf must be constants.");
3222 int grmask
= e1
.X_add_number
;
3223 int frmask
= e2
.X_add_number
;
3224 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3235 sep
= parse_operand (&e
);
3236 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3237 ignore_rest_of_line ();
3239 if (e
.X_op
!= O_constant
)
3240 as_bad ("Operand to .spill must be a constant");
3242 add_unwind_entry (output_spill_base (e
.X_add_number
));
3246 dot_spillreg (dummy
)
3249 int sep
, ab
, xy
, reg
, treg
;
3252 sep
= parse_operand (&e1
);
3255 as_bad ("No second operand to .spillreg");
3259 parse_operand (&e2
);
3261 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3263 as_bad ("First operand to .spillreg must be a preserved register");
3267 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3269 as_bad ("Second operand to .spillreg must be a register");
3273 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3277 dot_spillmem (psprel
)
3283 sep
= parse_operand (&e1
);
3286 as_bad ("Second operand missing");
3290 parse_operand (&e2
);
3292 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3294 as_bad ("First operand to .spill%s must be a preserved register",
3295 psprel
? "psp" : "sp");
3299 if (e2
.X_op
!= O_constant
)
3301 as_bad ("Second operand to .spill%s must be a constant",
3302 psprel
? "psp" : "sp");
3307 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3309 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3313 dot_spillreg_p (dummy
)
3316 int sep
, ab
, xy
, reg
, treg
;
3317 expressionS e1
, e2
, e3
;
3320 sep
= parse_operand (&e1
);
3323 as_bad ("No second and third operand to .spillreg.p");
3327 sep
= parse_operand (&e2
);
3330 as_bad ("No third operand to .spillreg.p");
3334 parse_operand (&e3
);
3336 qp
= e1
.X_add_number
- REG_P
;
3338 if (e1
.X_op
!= O_register
|| qp
> 63)
3340 as_bad ("First operand to .spillreg.p must be a predicate");
3344 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3346 as_bad ("Second operand to .spillreg.p must be a preserved register");
3350 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3352 as_bad ("Third operand to .spillreg.p must be a register");
3356 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3360 dot_spillmem_p (psprel
)
3363 expressionS e1
, e2
, e3
;
3367 sep
= parse_operand (&e1
);
3370 as_bad ("Second operand missing");
3374 parse_operand (&e2
);
3377 as_bad ("Second operand missing");
3381 parse_operand (&e3
);
3383 qp
= e1
.X_add_number
- REG_P
;
3384 if (e1
.X_op
!= O_register
|| qp
> 63)
3386 as_bad ("First operand to .spill%s_p must be a predicate",
3387 psprel
? "psp" : "sp");
3391 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3393 as_bad ("Second operand to .spill%s_p must be a preserved register",
3394 psprel
? "psp" : "sp");
3398 if (e3
.X_op
!= O_constant
)
3400 as_bad ("Third operand to .spill%s_p must be a constant",
3401 psprel
? "psp" : "sp");
3406 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3408 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3412 dot_label_state (dummy
)
3418 if (e
.X_op
!= O_constant
)
3420 as_bad ("Operand to .label_state must be a constant");
3423 add_unwind_entry (output_label_state (e
.X_add_number
));
3427 dot_copy_state (dummy
)
3433 if (e
.X_op
!= O_constant
)
3435 as_bad ("Operand to .copy_state must be a constant");
3438 add_unwind_entry (output_copy_state (e
.X_add_number
));
3448 sep
= parse_operand (&e1
);
3451 as_bad ("Second operand to .unwabi missing");
3454 sep
= parse_operand (&e2
);
3455 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3456 ignore_rest_of_line ();
3458 if (e1
.X_op
!= O_constant
)
3460 as_bad ("First operand to .unwabi must be a constant");
3464 if (e2
.X_op
!= O_constant
)
3466 as_bad ("Second operand to .unwabi must be a constant");
3470 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3474 dot_personality (dummy
)
3479 name
= input_line_pointer
;
3480 c
= get_symbol_end ();
3481 p
= input_line_pointer
;
3482 unwind
.personality_routine
= symbol_find_or_make (name
);
3485 demand_empty_rest_of_line ();
3495 unwind
.proc_start
= expr_build_dot ();
3496 /* Parse names of main and alternate entry points and mark them as
3497 function symbols: */
3501 name
= input_line_pointer
;
3502 c
= get_symbol_end ();
3503 p
= input_line_pointer
;
3504 sym
= symbol_find_or_make (name
);
3505 if (unwind
.proc_start
== 0)
3507 unwind
.proc_start
= sym
;
3509 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3512 if (*input_line_pointer
!= ',')
3514 ++input_line_pointer
;
3516 demand_empty_rest_of_line ();
3519 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3520 unwind
.personality_routine
= 0;
3527 unwind
.prologue
= 0;
3528 unwind
.prologue_mask
= 0;
3530 add_unwind_entry (output_body ());
3531 demand_empty_rest_of_line ();
3535 dot_prologue (dummy
)
3539 int mask
= 0, grsave
;
3541 if (!is_it_end_of_statement ())
3544 sep
= parse_operand (&e1
);
3546 as_bad ("No second operand to .prologue");
3547 sep
= parse_operand (&e2
);
3548 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3549 ignore_rest_of_line ();
3551 if (e1
.X_op
== O_constant
)
3553 mask
= e1
.X_add_number
;
3555 if (e2
.X_op
== O_constant
)
3556 grsave
= e2
.X_add_number
;
3557 else if (e2
.X_op
== O_register
3558 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3561 as_bad ("Second operand not a constant or general register");
3563 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3566 as_bad ("First operand not a constant");
3569 add_unwind_entry (output_prologue ());
3571 unwind
.prologue
= 1;
3572 unwind
.prologue_mask
= mask
;
3583 subsegT saved_subseg
;
3585 saved_seg
= now_seg
;
3586 saved_subseg
= now_subseg
;
3589 demand_empty_rest_of_line ();
3591 insn_group_break (1, 0, 0);
3593 /* If there was a .handlerdata, we haven't generated an image yet. */
3594 if (unwind
.info
== 0)
3596 generate_unwind_image ();
3599 subseg_set (md
.last_text_seg
, 0);
3600 unwind
.proc_end
= expr_build_dot ();
3602 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3603 ptr
= frag_more (24);
3604 where
= frag_now_fix () - 24;
3606 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3607 e
.X_op
= O_pseudo_fixup
;
3608 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3610 e
.X_add_symbol
= unwind
.proc_start
;
3611 ia64_cons_fix_new (frag_now
, where
, 8, &e
);
3613 e
.X_op
= O_pseudo_fixup
;
3614 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3616 e
.X_add_symbol
= unwind
.proc_end
;
3617 ia64_cons_fix_new (frag_now
, where
+ 8, 8, &e
);
3619 if (unwind
.info
!= 0)
3621 e
.X_op
= O_pseudo_fixup
;
3622 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3624 e
.X_add_symbol
= unwind
.info
;
3625 ia64_cons_fix_new (frag_now
, where
+ 16, 8, &e
);
3628 md_number_to_chars (ptr
+ 16, 0, 8);
3630 subseg_set (saved_seg
, saved_subseg
);
3631 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3635 dot_template (template)
3638 CURR_SLOT
.user_template
= template;
3645 int ins
, locs
, outs
, rots
;
3647 if (is_it_end_of_statement ())
3648 ins
= locs
= outs
= rots
= 0;
3651 ins
= get_absolute_expression ();
3652 if (*input_line_pointer
++ != ',')
3654 locs
= get_absolute_expression ();
3655 if (*input_line_pointer
++ != ',')
3657 outs
= get_absolute_expression ();
3658 if (*input_line_pointer
++ != ',')
3660 rots
= get_absolute_expression ();
3662 set_regstack (ins
, locs
, outs
, rots
);
3666 as_bad ("Comma expected");
3667 ignore_rest_of_line ();
3674 unsigned num_regs
, num_alloced
= 0;
3675 struct dynreg
**drpp
, *dr
;
3676 int ch
, base_reg
= 0;
3682 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3683 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3684 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3688 /* First, remove existing names from hash table. */
3689 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3691 hash_delete (md
.dynreg_hash
, dr
->name
);
3695 drpp
= &md
.dynreg
[type
];
3698 start
= input_line_pointer
;
3699 ch
= get_symbol_end ();
3700 *input_line_pointer
= ch
;
3701 len
= (input_line_pointer
- start
);
3704 if (*input_line_pointer
!= '[')
3706 as_bad ("Expected '['");
3709 ++input_line_pointer
; /* skip '[' */
3711 num_regs
= get_absolute_expression ();
3713 if (*input_line_pointer
++ != ']')
3715 as_bad ("Expected ']'");
3720 num_alloced
+= num_regs
;
3724 if (num_alloced
> md
.rot
.num_regs
)
3726 as_bad ("Used more than the declared %d rotating registers",
3732 if (num_alloced
> 96)
3734 as_bad ("Used more than the available 96 rotating registers");
3739 if (num_alloced
> 48)
3741 as_bad ("Used more than the available 48 rotating registers");
3750 name
= obstack_alloc (¬es
, len
+ 1);
3751 memcpy (name
, start
, len
);
3756 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3757 memset (*drpp
, 0, sizeof (*dr
));
3762 dr
->num_regs
= num_regs
;
3763 dr
->base
= base_reg
;
3765 base_reg
+= num_regs
;
3767 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3769 as_bad ("Attempt to redefine register set `%s'", name
);
3773 if (*input_line_pointer
!= ',')
3775 ++input_line_pointer
; /* skip comma */
3778 demand_empty_rest_of_line ();
3782 ignore_rest_of_line ();
3786 dot_byteorder (byteorder
)
3789 target_big_endian
= byteorder
;
3801 option
= input_line_pointer
;
3802 ch
= get_symbol_end ();
3803 if (strcmp (option
, "lsb") == 0)
3804 md
.flags
&= ~EF_IA_64_BE
;
3805 else if (strcmp (option
, "msb") == 0)
3806 md
.flags
|= EF_IA_64_BE
;
3807 else if (strcmp (option
, "abi32") == 0)
3808 md
.flags
&= ~EF_IA_64_ABI64
;
3809 else if (strcmp (option
, "abi64") == 0)
3810 md
.flags
|= EF_IA_64_ABI64
;
3812 as_bad ("Unknown psr option `%s'", option
);
3813 *input_line_pointer
= ch
;
3816 if (*input_line_pointer
!= ',')
3819 ++input_line_pointer
;
3822 demand_empty_rest_of_line ();
3829 as_bad (".alias not implemented yet");
3836 new_logical_line (0, get_absolute_expression ());
3837 demand_empty_rest_of_line ();
3841 parse_section_name ()
3847 if (*input_line_pointer
!= '"')
3849 as_bad ("Missing section name");
3850 ignore_rest_of_line ();
3853 name
= demand_copy_C_string (&len
);
3856 ignore_rest_of_line ();
3860 if (*input_line_pointer
!= ',')
3862 as_bad ("Comma expected after section name");
3863 ignore_rest_of_line ();
3866 ++input_line_pointer
; /* skip comma */
3874 char *name
= parse_section_name ();
3880 obj_elf_previous (0);
3883 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3886 stmt_float_cons (kind
)
3893 case 'd': size
= 8; break;
3894 case 'x': size
= 10; break;
3901 ia64_do_align (size
);
3909 int saved_auto_align
= md
.auto_align
;
3913 md
.auto_align
= saved_auto_align
;
3917 dot_xfloat_cons (kind
)
3920 char *name
= parse_section_name ();
3925 stmt_float_cons (kind
);
3926 obj_elf_previous (0);
3930 dot_xstringer (zero
)
3933 char *name
= parse_section_name ();
3939 obj_elf_previous (0);
3946 int saved_auto_align
= md
.auto_align
;
3947 char *name
= parse_section_name ();
3954 md
.auto_align
= saved_auto_align
;
3955 obj_elf_previous (0);
3959 dot_xfloat_cons_ua (kind
)
3962 int saved_auto_align
= md
.auto_align
;
3963 char *name
= parse_section_name ();
3969 stmt_float_cons (kind
);
3970 md
.auto_align
= saved_auto_align
;
3971 obj_elf_previous (0);
3974 /* .reg.val <regname>,value */
3983 if (reg
.X_op
!= O_register
)
3985 as_bad (_("Register name expected"));
3986 ignore_rest_of_line ();
3988 else if (*input_line_pointer
++ != ',')
3990 as_bad (_("Comma expected"));
3991 ignore_rest_of_line ();
3995 valueT value
= get_absolute_expression ();
3996 int regno
= reg
.X_add_number
;
3997 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
3998 as_warn (_("Register value annotation ignored"));
4001 gr_values
[regno
- REG_GR
].known
= 1;
4002 gr_values
[regno
- REG_GR
].value
= value
;
4003 gr_values
[regno
- REG_GR
].path
= md
.path
;
4006 demand_empty_rest_of_line ();
4009 /* select dv checking mode
4014 A stop is inserted when changing modes
4021 if (md
.manual_bundling
)
4022 as_warn (_("Directive invalid within a bundle"));
4024 if (type
== 'E' || type
== 'A')
4025 md
.mode_explicitly_set
= 0;
4027 md
.mode_explicitly_set
= 1;
4034 if (md
.explicit_mode
)
4035 insn_group_break (1, 0, 0);
4036 md
.explicit_mode
= 0;
4040 if (!md
.explicit_mode
)
4041 insn_group_break (1, 0, 0);
4042 md
.explicit_mode
= 1;
4046 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4047 insn_group_break (1, 0, 0);
4048 md
.explicit_mode
= md
.default_explicit_mode
;
4049 md
.mode_explicitly_set
= 0;
4060 for (regno
= 0; regno
< 64; regno
++)
4062 if (mask
& ((valueT
) 1 << regno
))
4064 fprintf (stderr
, "%s p%d", comma
, regno
);
4071 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4072 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4073 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4074 .pred.safe_across_calls p1 [, p2 [,...]]
4083 int p1
= -1, p2
= -1;
4087 if (*input_line_pointer
!= '"')
4089 as_bad (_("Missing predicate relation type"));
4090 ignore_rest_of_line ();
4096 char *form
= demand_copy_C_string (&len
);
4097 if (strcmp (form
, "mutex") == 0)
4099 else if (strcmp (form
, "clear") == 0)
4101 else if (strcmp (form
, "imply") == 0)
4105 as_bad (_("Unrecognized predicate relation type"));
4106 ignore_rest_of_line ();
4110 if (*input_line_pointer
== ',')
4111 ++input_line_pointer
;
4121 if (toupper (*input_line_pointer
) != 'P'
4122 || (regno
= atoi (++input_line_pointer
)) < 0
4125 as_bad (_("Predicate register expected"));
4126 ignore_rest_of_line ();
4129 while (isdigit (*input_line_pointer
))
4130 ++input_line_pointer
;
4137 as_warn (_("Duplicate predicate register ignored"));
4140 /* See if it's a range. */
4141 if (*input_line_pointer
== '-')
4144 ++input_line_pointer
;
4146 if (toupper (*input_line_pointer
) != 'P'
4147 || (regno
= atoi (++input_line_pointer
)) < 0
4150 as_bad (_("Predicate register expected"));
4151 ignore_rest_of_line ();
4154 while (isdigit (*input_line_pointer
))
4155 ++input_line_pointer
;
4159 as_bad (_("Bad register range"));
4160 ignore_rest_of_line ();
4171 if (*input_line_pointer
!= ',')
4173 ++input_line_pointer
;
4182 clear_qp_mutex (mask
);
4183 clear_qp_implies (mask
, (valueT
) 0);
4186 if (count
!= 2 || p1
== -1 || p2
== -1)
4187 as_bad (_("Predicate source and target required"));
4188 else if (p1
== 0 || p2
== 0)
4189 as_bad (_("Use of p0 is not valid in this context"));
4191 add_qp_imply (p1
, p2
);
4196 as_bad (_("At least two PR arguments expected"));
4201 as_bad (_("Use of p0 is not valid in this context"));
4204 add_qp_mutex (mask
);
4207 /* note that we don't override any existing relations */
4210 as_bad (_("At least one PR argument expected"));
4215 fprintf (stderr
, "Safe across calls: ");
4216 print_prmask (mask
);
4217 fprintf (stderr
, "\n");
4219 qp_safe_across_calls
= mask
;
4222 demand_empty_rest_of_line ();
4225 /* .entry label [, label [, ...]]
4226 Hint to DV code that the given labels are to be considered entry points.
4227 Otherwise, only global labels are considered entry points. */
4240 name
= input_line_pointer
;
4241 c
= get_symbol_end ();
4242 symbolP
= symbol_find_or_make (name
);
4244 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4246 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4249 *input_line_pointer
= c
;
4251 c
= *input_line_pointer
;
4254 input_line_pointer
++;
4256 if (*input_line_pointer
== '\n')
4262 demand_empty_rest_of_line ();
4265 /* .mem.offset offset, base
4266 "base" is used to distinguish between offsets from a different base. */
4269 dot_mem_offset (dummy
)
4272 md
.mem_offset
.hint
= 1;
4273 md
.mem_offset
.offset
= get_absolute_expression ();
4274 if (*input_line_pointer
!= ',')
4276 as_bad (_("Comma expected"));
4277 ignore_rest_of_line ();
4280 ++input_line_pointer
;
4281 md
.mem_offset
.base
= get_absolute_expression ();
4282 demand_empty_rest_of_line ();
4285 /* ia64-specific pseudo-ops: */
4286 const pseudo_typeS md_pseudo_table
[] =
4288 { "radix", dot_radix
, 0 },
4289 { "lcomm", s_lcomm_bytes
, 1 },
4290 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4291 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4292 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4293 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4294 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4295 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4296 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4297 { "proc", dot_proc
, 0 },
4298 { "body", dot_body
, 0 },
4299 { "prologue", dot_prologue
, 0 },
4300 { "endp", dot_endp
},
4301 { "file", dwarf2_directive_file
},
4302 { "loc", dwarf2_directive_loc
},
4304 { "fframe", dot_fframe
},
4305 { "vframe", dot_vframe
},
4306 { "vframesp", dot_vframesp
},
4307 { "vframepsp", dot_vframepsp
},
4308 { "save", dot_save
},
4309 { "restore", dot_restore
},
4310 { "restorereg", dot_restorereg
},
4311 { "restorereg.p", dot_restorereg_p
},
4312 { "handlerdata", dot_handlerdata
},
4313 { "unwentry", dot_unwentry
},
4314 { "altrp", dot_altrp
},
4315 { "savesp", dot_savemem
, 0 },
4316 { "savepsp", dot_savemem
, 1 },
4317 { "save.g", dot_saveg
},
4318 { "save.f", dot_savef
},
4319 { "save.b", dot_saveb
},
4320 { "save.gf", dot_savegf
},
4321 { "spill", dot_spill
},
4322 { "spillreg", dot_spillreg
},
4323 { "spillsp", dot_spillmem
, 0 },
4324 { "spillpsp", dot_spillmem
, 1 },
4325 { "spillreg.p", dot_spillreg_p
},
4326 { "spillsp.p", dot_spillmem_p
, 0 },
4327 { "spillpsp.p", dot_spillmem_p
, 1 },
4328 { "label_state", dot_label_state
},
4329 { "copy_state", dot_copy_state
},
4330 { "unwabi", dot_unwabi
},
4331 { "personality", dot_personality
},
4333 { "estate", dot_estate
},
4335 { "mii", dot_template
, 0x0 },
4336 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4337 { "mlx", dot_template
, 0x2 },
4338 { "mmi", dot_template
, 0x4 },
4339 { "mfi", dot_template
, 0x6 },
4340 { "mmf", dot_template
, 0x7 },
4341 { "mib", dot_template
, 0x8 },
4342 { "mbb", dot_template
, 0x9 },
4343 { "bbb", dot_template
, 0xb },
4344 { "mmb", dot_template
, 0xc },
4345 { "mfb", dot_template
, 0xe },
4347 { "lb", dot_scope
, 0 },
4348 { "le", dot_scope
, 1 },
4350 { "align", s_align_bytes
, 0 },
4351 { "regstk", dot_regstk
, 0 },
4352 { "rotr", dot_rot
, DYNREG_GR
},
4353 { "rotf", dot_rot
, DYNREG_FR
},
4354 { "rotp", dot_rot
, DYNREG_PR
},
4355 { "lsb", dot_byteorder
, 0 },
4356 { "msb", dot_byteorder
, 1 },
4357 { "psr", dot_psr
, 0 },
4358 { "alias", dot_alias
, 0 },
4359 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4361 { "xdata1", dot_xdata
, 1 },
4362 { "xdata2", dot_xdata
, 2 },
4363 { "xdata4", dot_xdata
, 4 },
4364 { "xdata8", dot_xdata
, 8 },
4365 { "xreal4", dot_xfloat_cons
, 'f' },
4366 { "xreal8", dot_xfloat_cons
, 'd' },
4367 { "xreal10", dot_xfloat_cons
, 'x' },
4368 { "xstring", dot_xstringer
, 0 },
4369 { "xstringz", dot_xstringer
, 1 },
4371 /* unaligned versions: */
4372 { "xdata2.ua", dot_xdata_ua
, 2 },
4373 { "xdata4.ua", dot_xdata_ua
, 4 },
4374 { "xdata8.ua", dot_xdata_ua
, 8 },
4375 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4376 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4377 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4379 /* annotations/DV checking support */
4380 { "entry", dot_entry
, 0 },
4381 { "mem.offset", dot_mem_offset
},
4382 { "pred.rel", dot_pred_rel
, 0 },
4383 { "pred.rel.clear", dot_pred_rel
, 'c' },
4384 { "pred.rel.imply", dot_pred_rel
, 'i' },
4385 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4386 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4387 { "reg.val", dot_reg_val
},
4388 { "auto", dot_dv_mode
, 'a' },
4389 { "explicit", dot_dv_mode
, 'e' },
4390 { "default", dot_dv_mode
, 'd' },
4395 static const struct pseudo_opcode
4398 void (*handler
) (int);
4403 /* these are more like pseudo-ops, but don't start with a dot */
4404 { "data1", cons
, 1 },
4405 { "data2", cons
, 2 },
4406 { "data4", cons
, 4 },
4407 { "data8", cons
, 8 },
4408 { "real4", stmt_float_cons
, 'f' },
4409 { "real8", stmt_float_cons
, 'd' },
4410 { "real10", stmt_float_cons
, 'x' },
4411 { "string", stringer
, 0 },
4412 { "stringz", stringer
, 1 },
4414 /* unaligned versions: */
4415 { "data2.ua", stmt_cons_ua
, 2 },
4416 { "data4.ua", stmt_cons_ua
, 4 },
4417 { "data8.ua", stmt_cons_ua
, 8 },
4418 { "real4.ua", float_cons
, 'f' },
4419 { "real8.ua", float_cons
, 'd' },
4420 { "real10.ua", float_cons
, 'x' },
4423 /* Declare a register by creating a symbol for it and entering it in
4424 the symbol table. */
4427 declare_register (name
, regnum
)
4434 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4436 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4438 as_fatal ("Inserting \"%s\" into register table failed: %s",
4445 declare_register_set (prefix
, num_regs
, base_regnum
)
4453 for (i
= 0; i
< num_regs
; ++i
)
4455 sprintf (name
, "%s%u", prefix
, i
);
4456 declare_register (name
, base_regnum
+ i
);
4461 operand_width (opnd
)
4462 enum ia64_opnd opnd
;
4464 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4465 unsigned int bits
= 0;
4469 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4470 bits
+= odesc
->field
[i
].bits
;
4476 operand_match (idesc
, index
, e
)
4477 const struct ia64_opcode
*idesc
;
4481 enum ia64_opnd opnd
= idesc
->operands
[index
];
4482 int bits
, relocatable
= 0;
4483 struct insn_fix
*fix
;
4490 case IA64_OPND_AR_CCV
:
4491 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4495 case IA64_OPND_AR_PFS
:
4496 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4501 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4506 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4511 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4515 case IA64_OPND_PR_ROT
:
4516 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4521 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4525 case IA64_OPND_PSR_L
:
4526 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4530 case IA64_OPND_PSR_UM
:
4531 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4536 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4541 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4546 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4550 /* register operands: */
4553 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4554 && e
->X_add_number
< REG_AR
+ 128)
4560 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4561 && e
->X_add_number
< REG_BR
+ 8)
4566 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4567 && e
->X_add_number
< REG_CR
+ 128)
4575 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4576 && e
->X_add_number
< REG_FR
+ 128)
4582 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4583 && e
->X_add_number
< REG_P
+ 64)
4590 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4591 && e
->X_add_number
< REG_GR
+ 128)
4595 case IA64_OPND_R3_2
:
4596 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4597 && e
->X_add_number
< REG_GR
+ 4)
4601 /* indirect operands: */
4602 case IA64_OPND_CPUID_R3
:
4603 case IA64_OPND_DBR_R3
:
4604 case IA64_OPND_DTR_R3
:
4605 case IA64_OPND_ITR_R3
:
4606 case IA64_OPND_IBR_R3
:
4607 case IA64_OPND_MSR_R3
:
4608 case IA64_OPND_PKR_R3
:
4609 case IA64_OPND_PMC_R3
:
4610 case IA64_OPND_PMD_R3
:
4611 case IA64_OPND_RR_R3
:
4612 if (e
->X_op
== O_index
&& e
->X_op_symbol
4613 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4614 == opnd
- IA64_OPND_CPUID_R3
))
4619 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4623 /* immediate operands: */
4624 case IA64_OPND_CNT2a
:
4625 case IA64_OPND_LEN4
:
4626 case IA64_OPND_LEN6
:
4627 bits
= operand_width (idesc
->operands
[index
]);
4628 if (e
->X_op
== O_constant
4629 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4633 case IA64_OPND_CNT2b
:
4634 if (e
->X_op
== O_constant
4635 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4639 case IA64_OPND_CNT2c
:
4640 val
= e
->X_add_number
;
4641 if (e
->X_op
== O_constant
4642 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4647 /* SOR must be an integer multiple of 8 */
4648 if (e
->X_add_number
& 0x7)
4652 if (e
->X_op
== O_constant
&&
4653 (bfd_vma
) e
->X_add_number
<= 96)
4657 case IA64_OPND_IMMU62
:
4658 if (e
->X_op
== O_constant
)
4660 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4665 /* FIXME -- need 62-bit relocation type */
4666 as_bad (_("62-bit relocation not yet implemented"));
4670 case IA64_OPND_IMMU64
:
4671 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4672 || e
->X_op
== O_subtract
)
4674 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4675 fix
->code
= BFD_RELOC_IA64_IMM64
;
4676 if (e
->X_op
!= O_subtract
)
4678 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4679 if (e
->X_op
== O_pseudo_fixup
)
4683 fix
->opnd
= idesc
->operands
[index
];
4686 ++CURR_SLOT
.num_fixups
;
4689 else if (e
->X_op
== O_constant
)
4693 case IA64_OPND_CCNT5
:
4694 case IA64_OPND_CNT5
:
4695 case IA64_OPND_CNT6
:
4696 case IA64_OPND_CPOS6a
:
4697 case IA64_OPND_CPOS6b
:
4698 case IA64_OPND_CPOS6c
:
4699 case IA64_OPND_IMMU2
:
4700 case IA64_OPND_IMMU7a
:
4701 case IA64_OPND_IMMU7b
:
4702 case IA64_OPND_IMMU21
:
4703 case IA64_OPND_IMMU24
:
4704 case IA64_OPND_MBTYPE4
:
4705 case IA64_OPND_MHTYPE8
:
4706 case IA64_OPND_POS6
:
4707 bits
= operand_width (idesc
->operands
[index
]);
4708 if (e
->X_op
== O_constant
4709 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4713 case IA64_OPND_IMMU9
:
4714 bits
= operand_width (idesc
->operands
[index
]);
4715 if (e
->X_op
== O_constant
4716 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4718 int lobits
= e
->X_add_number
& 0x3;
4719 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4720 e
->X_add_number
|= (bfd_vma
) 0x3;
4725 case IA64_OPND_IMM44
:
4726 /* least 16 bits must be zero */
4727 if ((e
->X_add_number
& 0xffff) != 0)
4728 as_warn (_("lower 16 bits of mask ignored"));
4730 if (e
->X_op
== O_constant
4731 && ((e
->X_add_number
>= 0
4732 && e
->X_add_number
< ((bfd_vma
) 1 << 44))
4733 || (e
->X_add_number
< 0
4734 && -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4737 if (e
->X_add_number
>= 0
4738 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4740 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4746 case IA64_OPND_IMM17
:
4747 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4748 if (e
->X_op
== O_constant
4749 && ((e
->X_add_number
>= 0
4750 && e
->X_add_number
< ((bfd_vma
) 1 << 17))
4751 || (e
->X_add_number
< 0
4752 && -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4755 if (e
->X_add_number
>= 0
4756 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4758 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
4764 case IA64_OPND_IMM14
:
4765 case IA64_OPND_IMM22
:
4767 case IA64_OPND_IMM1
:
4768 case IA64_OPND_IMM8
:
4769 case IA64_OPND_IMM8U4
:
4770 case IA64_OPND_IMM8M1
:
4771 case IA64_OPND_IMM8M1U4
:
4772 case IA64_OPND_IMM8M1U8
:
4773 case IA64_OPND_IMM9a
:
4774 case IA64_OPND_IMM9b
:
4775 bits
= operand_width (idesc
->operands
[index
]);
4776 if (relocatable
&& (e
->X_op
== O_symbol
4777 || e
->X_op
== O_subtract
4778 || e
->X_op
== O_pseudo_fixup
))
4780 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4782 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4783 fix
->code
= BFD_RELOC_IA64_IMM14
;
4785 fix
->code
= BFD_RELOC_IA64_IMM22
;
4787 if (e
->X_op
!= O_subtract
)
4789 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4790 if (e
->X_op
== O_pseudo_fixup
)
4794 fix
->opnd
= idesc
->operands
[index
];
4797 ++CURR_SLOT
.num_fixups
;
4800 else if (e
->X_op
!= O_constant
4801 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4804 if (opnd
== IA64_OPND_IMM8M1U4
)
4806 /* Zero is not valid for unsigned compares that take an adjusted
4807 constant immediate range. */
4808 if (e
->X_add_number
== 0)
4811 /* Sign-extend 32-bit unsigned numbers, so that the following range
4812 checks will work. */
4813 val
= e
->X_add_number
;
4814 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4815 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4816 val
= ((val
<< 32) >> 32);
4818 /* Check for 0x100000000. This is valid because
4819 0x100000000-1 is the same as ((uint32_t) -1). */
4820 if (val
== ((bfd_signed_vma
) 1 << 32))
4825 else if (opnd
== IA64_OPND_IMM8M1U8
)
4827 /* Zero is not valid for unsigned compares that take an adjusted
4828 constant immediate range. */
4829 if (e
->X_add_number
== 0)
4832 /* Check for 0x10000000000000000. */
4833 if (e
->X_op
== O_big
)
4835 if (generic_bignum
[0] == 0
4836 && generic_bignum
[1] == 0
4837 && generic_bignum
[2] == 0
4838 && generic_bignum
[3] == 0
4839 && generic_bignum
[4] == 1)
4845 val
= e
->X_add_number
- 1;
4847 else if (opnd
== IA64_OPND_IMM8M1
)
4848 val
= e
->X_add_number
- 1;
4849 else if (opnd
== IA64_OPND_IMM8U4
)
4851 /* Sign-extend 32-bit unsigned numbers, so that the following range
4852 checks will work. */
4853 val
= e
->X_add_number
;
4854 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4855 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4856 val
= ((val
<< 32) >> 32);
4859 val
= e
->X_add_number
;
4861 if ((val
>= 0 && val
< ((bfd_vma
) 1 << (bits
- 1)))
4862 || (val
< 0 && -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4866 case IA64_OPND_INC3
:
4867 /* +/- 1, 4, 8, 16 */
4868 val
= e
->X_add_number
;
4871 if (e
->X_op
== O_constant
4872 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4876 case IA64_OPND_TGT25
:
4877 case IA64_OPND_TGT25b
:
4878 case IA64_OPND_TGT25c
:
4879 case IA64_OPND_TGT64
:
4880 if (e
->X_op
== O_symbol
)
4882 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4883 if (opnd
== IA64_OPND_TGT25
)
4884 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4885 else if (opnd
== IA64_OPND_TGT25b
)
4886 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4887 else if (opnd
== IA64_OPND_TGT25c
)
4888 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4889 else if (opnd
== IA64_OPND_TGT64
)
4890 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
4894 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4895 fix
->opnd
= idesc
->operands
[index
];
4898 ++CURR_SLOT
.num_fixups
;
4901 case IA64_OPND_TAG13
:
4902 case IA64_OPND_TAG13b
:
4909 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4910 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
4911 fix
->opnd
= idesc
->operands
[index
];
4914 ++CURR_SLOT
.num_fixups
;
4934 memset (e
, 0, sizeof (*e
));
4937 if (*input_line_pointer
!= '}')
4939 sep
= *input_line_pointer
++;
4943 if (!md
.manual_bundling
)
4944 as_warn ("Found '}' when manual bundling is off");
4946 CURR_SLOT
.manual_bundling_off
= 1;
4947 md
.manual_bundling
= 0;
4953 /* Returns the next entry in the opcode table that matches the one in
4954 IDESC, and frees the entry in IDESC. If no matching entry is
4955 found, NULL is returned instead. */
4957 static struct ia64_opcode
*
4958 get_next_opcode (struct ia64_opcode
*idesc
)
4960 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
4961 ia64_free_opcode (idesc
);
4965 /* Parse the operands for the opcode and find the opcode variant that
4966 matches the specified operands, or NULL if no match is possible. */
4968 static struct ia64_opcode
*
4969 parse_operands (idesc
)
4970 struct ia64_opcode
*idesc
;
4972 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
4974 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
4976 char *first_arg
= 0, *end
, *saved_input_pointer
;
4979 assert (strlen (idesc
->name
) <= 128);
4981 strcpy (mnemonic
, idesc
->name
);
4982 if (idesc
->operands
[2] == IA64_OPND_SOF
)
4984 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4985 can't parse the first operand until we have parsed the
4986 remaining operands of the "alloc" instruction. */
4988 first_arg
= input_line_pointer
;
4989 end
= strchr (input_line_pointer
, '=');
4992 as_bad ("Expected separator `='");
4995 input_line_pointer
= end
+ 1;
5000 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5002 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5003 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5008 if (sep
!= '=' && sep
!= ',')
5013 if (num_outputs
> 0)
5014 as_bad ("Duplicate equal sign (=) in instruction");
5016 num_outputs
= i
+ 1;
5021 as_bad ("Illegal operand separator `%c'", sep
);
5025 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5027 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5028 know (strcmp (idesc
->name
, "alloc") == 0);
5029 if (num_operands
== 5 /* first_arg not included in this count! */
5030 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5031 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5032 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5033 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5035 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5036 CURR_SLOT
.opnd
[3].X_add_number
,
5037 CURR_SLOT
.opnd
[4].X_add_number
,
5038 CURR_SLOT
.opnd
[5].X_add_number
);
5040 /* now we can parse the first arg: */
5041 saved_input_pointer
= input_line_pointer
;
5042 input_line_pointer
= first_arg
;
5043 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5045 --num_outputs
; /* force error */
5046 input_line_pointer
= saved_input_pointer
;
5048 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5049 CURR_SLOT
.opnd
[3].X_add_number
5050 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5051 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5055 highest_unmatched_operand
= 0;
5056 expected_operand
= idesc
->operands
[0];
5057 for (; idesc
; idesc
= get_next_opcode (idesc
))
5059 if (num_outputs
!= idesc
->num_outputs
)
5060 continue; /* mismatch in # of outputs */
5062 CURR_SLOT
.num_fixups
= 0;
5063 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5064 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5067 if (i
!= num_operands
)
5069 if (i
> highest_unmatched_operand
)
5071 highest_unmatched_operand
= i
;
5072 expected_operand
= idesc
->operands
[i
];
5077 if (num_operands
< NELEMS (idesc
->operands
)
5078 && idesc
->operands
[num_operands
])
5079 continue; /* mismatch in number of arguments */
5085 if (expected_operand
)
5086 as_bad ("Operand %u of `%s' should be %s",
5087 highest_unmatched_operand
+ 1, mnemonic
,
5088 elf64_ia64_operands
[expected_operand
].desc
);
5090 as_bad ("Operand mismatch");
5097 build_insn (slot
, insnp
)
5101 const struct ia64_operand
*odesc
, *o2desc
;
5102 struct ia64_opcode
*idesc
= slot
->idesc
;
5103 bfd_signed_vma insn
, val
;
5107 insn
= idesc
->opcode
| slot
->qp_regno
;
5109 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5111 if (slot
->opnd
[i
].X_op
== O_register
5112 || slot
->opnd
[i
].X_op
== O_constant
5113 || slot
->opnd
[i
].X_op
== O_index
)
5114 val
= slot
->opnd
[i
].X_add_number
;
5115 else if (slot
->opnd
[i
].X_op
== O_big
)
5117 /* This must be the value 0x10000000000000000. */
5118 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5124 switch (idesc
->operands
[i
])
5126 case IA64_OPND_IMMU64
:
5127 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5128 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5129 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5130 | (((val
>> 63) & 0x1) << 36));
5133 case IA64_OPND_IMMU62
:
5134 val
&= 0x3fffffffffffffffULL
;
5135 if (val
!= slot
->opnd
[i
].X_add_number
)
5136 as_warn (_("Value truncated to 62 bits"));
5137 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5138 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5141 case IA64_OPND_TGT64
:
5143 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5144 insn
|= ((((val
>> 59) & 0x1) << 36)
5145 | (((val
>> 0) & 0xfffff) << 13));
5176 case IA64_OPND_R3_2
:
5177 case IA64_OPND_CPUID_R3
:
5178 case IA64_OPND_DBR_R3
:
5179 case IA64_OPND_DTR_R3
:
5180 case IA64_OPND_ITR_R3
:
5181 case IA64_OPND_IBR_R3
:
5183 case IA64_OPND_MSR_R3
:
5184 case IA64_OPND_PKR_R3
:
5185 case IA64_OPND_PMC_R3
:
5186 case IA64_OPND_PMD_R3
:
5187 case IA64_OPND_RR_R3
:
5195 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5196 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5198 as_bad_where (slot
->src_file
, slot
->src_line
,
5199 "Bad operand value: %s", err
);
5200 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5202 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5203 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5205 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5206 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5208 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5209 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5210 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5212 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5213 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5223 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5224 unsigned int manual_bundling
= 0;
5225 enum ia64_unit required_unit
, insn_unit
= 0;
5226 enum ia64_insn_type type
[3], insn_type
;
5227 unsigned int template, orig_template
;
5228 bfd_vma insn
[3] = { -1, -1, -1 };
5229 struct ia64_opcode
*idesc
;
5230 int end_of_insn_group
= 0, user_template
= -1;
5231 int n
, i
, j
, first
, curr
;
5232 unw_rec_list
*ptr
, *prev
;
5233 bfd_vma t0
= 0, t1
= 0;
5234 struct label_fix
*lfix
;
5235 struct insn_fix
*ifix
;
5240 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5241 know (first
>= 0 & first
< NUM_SLOTS
);
5242 n
= MIN (3, md
.num_slots_in_use
);
5244 /* Determine template: user user_template if specified, best match
5247 if (md
.slot
[first
].user_template
>= 0)
5248 user_template
= template = md
.slot
[first
].user_template
;
5251 /* Auto select appropriate template. */
5252 memset (type
, 0, sizeof (type
));
5254 for (i
= 0; i
< n
; ++i
)
5256 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5258 type
[i
] = md
.slot
[curr
].idesc
->type
;
5259 curr
= (curr
+ 1) % NUM_SLOTS
;
5261 template = best_template
[type
[0]][type
[1]][type
[2]];
5264 /* initialize instructions with appropriate nops: */
5265 for (i
= 0; i
< 3; ++i
)
5266 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5270 /* now fill in slots with as many insns as possible: */
5272 idesc
= md
.slot
[curr
].idesc
;
5273 end_of_insn_group
= 0;
5274 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5276 /* Set the slot number for prologue/body records now as those
5277 refer to the current point, not the point after the
5278 instruction has been issued: */
5279 /* Don't try to delete prologue/body records here, as that will cause
5280 them to also be deleted from the master list of unwind records. */
5281 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5282 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5283 || ptr
->r
.type
== body
)
5284 ptr
->slot_number
= (unsigned long) f
+ i
;
5286 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5288 if (manual_bundling
&& i
!= 2)
5289 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5290 "`%s' must be last in bundle", idesc
->name
);
5294 if (idesc
->flags
& IA64_OPCODE_LAST
)
5296 int required_slot
, required_template
;
5298 /* If we need a stop bit after an M slot, our only choice is
5299 template 5 (M;;MI). If we need a stop bit after a B
5300 slot, our only choice is to place it at the end of the
5301 bundle, because the only available templates are MIB,
5302 MBB, BBB, MMB, and MFB. We don't handle anything other
5303 than M and B slots because these are the only kind of
5304 instructions that can have the IA64_OPCODE_LAST bit set. */
5305 required_template
= template;
5306 switch (idesc
->type
)
5310 required_template
= 5;
5318 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5319 "Internal error: don't know how to force %s to end"
5320 "of instruction group", idesc
->name
);
5324 if (manual_bundling
&& i
!= required_slot
)
5325 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5326 "`%s' must be last in instruction group",
5328 if (required_slot
< i
)
5329 /* Can't fit this instruction. */
5333 if (required_template
!= template)
5335 /* If we switch the template, we need to reset the NOPs
5336 after slot i. The slot-types of the instructions ahead
5337 of i never change, so we don't need to worry about
5338 changing NOPs in front of this slot. */
5339 for (j
= i
; j
< 3; ++j
)
5340 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5342 template = required_template
;
5344 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5346 if (manual_bundling_on
)
5347 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5348 "Label must be first in a bundle");
5349 /* This insn must go into the first slot of a bundle. */
5353 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5354 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5356 if (manual_bundling_on
)
5359 manual_bundling
= 1;
5361 break; /* need to start a new bundle */
5364 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5366 /* We need an instruction group boundary in the middle of a
5367 bundle. See if we can switch to an other template with
5368 an appropriate boundary. */
5370 orig_template
= template;
5371 if (i
== 1 && (user_template
== 4
5372 || (user_template
< 0
5373 && (ia64_templ_desc
[template].exec_unit
[0]
5377 end_of_insn_group
= 0;
5379 else if (i
== 2 && (user_template
== 0
5380 || (user_template
< 0
5381 && (ia64_templ_desc
[template].exec_unit
[1]
5383 /* This test makes sure we don't switch the template if
5384 the next instruction is one that needs to be first in
5385 an instruction group. Since all those instructions are
5386 in the M group, there is no way such an instruction can
5387 fit in this bundle even if we switch the template. The
5388 reason we have to check for this is that otherwise we
5389 may end up generating "MI;;I M.." which has the deadly
5390 effect that the second M instruction is no longer the
5391 first in the bundle! --davidm 99/12/16 */
5392 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5395 end_of_insn_group
= 0;
5397 else if (curr
!= first
)
5398 /* can't fit this insn */
5401 if (template != orig_template
)
5402 /* if we switch the template, we need to reset the NOPs
5403 after slot i. The slot-types of the instructions ahead
5404 of i never change, so we don't need to worry about
5405 changing NOPs in front of this slot. */
5406 for (j
= i
; j
< 3; ++j
)
5407 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5409 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5411 /* resolve dynamic opcodes such as "break" and "nop": */
5412 if (idesc
->type
== IA64_TYPE_DYN
)
5414 if ((strcmp (idesc
->name
, "nop") == 0)
5415 || (strcmp (idesc
->name
, "break") == 0))
5416 insn_unit
= required_unit
;
5417 else if (strcmp (idesc
->name
, "chk.s") == 0)
5419 insn_unit
= IA64_UNIT_M
;
5420 if (required_unit
== IA64_UNIT_I
)
5421 insn_unit
= IA64_UNIT_I
;
5424 as_fatal ("emit_one_bundle: unexpected dynamic op");
5426 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5427 ia64_free_opcode (idesc
);
5428 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5430 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5435 insn_type
= idesc
->type
;
5436 insn_unit
= IA64_UNIT_NIL
;
5440 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5441 insn_unit
= required_unit
;
5443 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5444 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5445 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5446 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5447 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5452 if (insn_unit
!= required_unit
)
5454 if (required_unit
== IA64_UNIT_L
5455 && insn_unit
== IA64_UNIT_I
5456 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5458 /* we got ourselves an MLX template but the current
5459 instruction isn't an X-unit, or an I-unit instruction
5460 that can go into the X slot of an MLX template. Duh. */
5461 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5463 as_bad_where (md
.slot
[curr
].src_file
,
5464 md
.slot
[curr
].src_line
,
5465 "`%s' can't go in X slot of "
5466 "MLX template", idesc
->name
);
5467 /* drop this insn so we don't livelock: */
5468 --md
.num_slots_in_use
;
5472 continue; /* try next slot */
5475 if (debug_type
== DEBUG_DWARF2
)
5479 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + 1 * i
;
5480 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5483 build_insn (md
.slot
+ curr
, insn
+ i
);
5485 /* Set slot counts for non prologue/body unwind records. */
5486 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5487 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5488 && ptr
->r
.type
!= body
)
5489 ptr
->slot_number
= (unsigned long) f
+ i
;
5490 md
.slot
[curr
].unwind_record
= NULL
;
5491 unwind
.next_slot_number
= (unsigned long) f
+ i
+ ((i
== 2)?(0x10-2):1);
5493 if (required_unit
== IA64_UNIT_L
)
5496 /* skip one slot for long/X-unit instructions */
5499 --md
.num_slots_in_use
;
5501 /* now is a good time to fix up the labels for this insn: */
5502 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5504 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5505 symbol_set_frag (lfix
->sym
, frag_now
);
5508 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5510 ifix
= md
.slot
[curr
].fixup
+ j
;
5511 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 4,
5512 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5513 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5514 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5515 fix
->fx_file
= md
.slot
[curr
].src_file
;
5516 fix
->fx_line
= md
.slot
[curr
].src_line
;
5519 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5522 ia64_free_opcode (md
.slot
[curr
].idesc
);
5523 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5524 md
.slot
[curr
].user_template
= -1;
5526 if (manual_bundling_off
)
5528 manual_bundling
= 0;
5531 curr
= (curr
+ 1) % NUM_SLOTS
;
5532 idesc
= md
.slot
[curr
].idesc
;
5534 if (manual_bundling
)
5536 if (md
.num_slots_in_use
> 0)
5537 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5538 "`%s' does not fit into %s template",
5539 idesc
->name
, ia64_templ_desc
[template].name
);
5541 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5542 "Missing '}' at end of file");
5544 know (md
.num_slots_in_use
< NUM_SLOTS
);
5546 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5547 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5549 md_number_to_chars (f
+ 0, t0
, 8);
5550 md_number_to_chars (f
+ 8, t1
, 8);
5554 md_parse_option (c
, arg
)
5560 /* Switches from the Intel assembler. */
5562 if (strcmp (arg
, "ilp64") == 0
5563 || strcmp (arg
, "lp64") == 0
5564 || strcmp (arg
, "p64") == 0)
5566 md
.flags
|= EF_IA_64_ABI64
;
5568 else if (strcmp (arg
, "ilp32") == 0)
5570 md
.flags
&= ~EF_IA_64_ABI64
;
5572 else if (strcmp (arg
, "le") == 0)
5574 md
.flags
&= ~EF_IA_64_BE
;
5576 else if (strcmp (arg
, "be") == 0)
5578 md
.flags
|= EF_IA_64_BE
;
5585 if (strcmp (arg
, "so") == 0)
5587 /* Suppress signon message. */
5589 else if (strcmp (arg
, "pi") == 0)
5591 /* Reject privileged instructions. FIXME */
5593 else if (strcmp (arg
, "us") == 0)
5595 /* Allow union of signed and unsigned range. FIXME */
5597 else if (strcmp (arg
, "close_fcalls") == 0)
5599 /* Do not resolve global function calls. */
5606 /* temp[="prefix"] Insert temporary labels into the object file
5607 symbol table prefixed by "prefix".
5608 Default prefix is ":temp:".
5613 /* ??? Conflicts with gas' listing option. */
5614 /* indirect=<tgt> Assume unannotated indirect branches behavior
5615 according to <tgt> --
5616 exit: branch out from the current context (default)
5617 labels: all labels in context may be branch targets
5622 /* -X conflicts with an ignored option, use -x instead */
5624 if (!arg
|| strcmp (arg
, "explicit") == 0)
5626 /* set default mode to explicit */
5627 md
.default_explicit_mode
= 1;
5630 else if (strcmp (arg
, "auto") == 0)
5632 md
.default_explicit_mode
= 0;
5634 else if (strcmp (arg
, "debug") == 0)
5638 else if (strcmp (arg
, "debugx") == 0)
5640 md
.default_explicit_mode
= 1;
5645 as_bad (_("Unrecognized option '-x%s'"), arg
);
5650 /* nops Print nops statistics. */
5653 /* GNU specific switches for gcc. */
5654 case OPTION_MCONSTANT_GP
:
5655 md
.flags
|= EF_IA_64_CONS_GP
;
5658 case OPTION_MAUTO_PIC
:
5659 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
5670 md_show_usage (stream
)
5675 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5676 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5677 -x | -xexplicit turn on dependency violation checking (default)\n\
5678 -xauto automagically remove dependency violations\n\
5679 -xdebug debug dependency violation checker\n"),
5683 /* Return true if TYPE fits in TEMPL at SLOT. */
5686 match (int templ
, int type
, int slot
)
5688 enum ia64_unit unit
;
5691 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5694 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5696 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5698 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5699 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5700 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5701 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5702 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5703 default: result
= 0; break;
5708 /* Add a bit of extra goodness if a nop of type F or B would fit
5709 in TEMPL at SLOT. */
5712 extra_goodness (int templ
, int slot
)
5714 if (match (templ
, IA64_TYPE_F
, slot
))
5716 if (match (templ
, IA64_TYPE_B
, slot
))
5721 /* This function is called once, at assembler startup time. It sets
5722 up all the tables, etc. that the MD part of the assembler will need
5723 that can be determined before arguments are parsed. */
5727 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
;
5732 md
.explicit_mode
= md
.default_explicit_mode
;
5734 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5736 target_big_endian
= 0;
5737 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5738 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5739 &zero_address_frag
);
5741 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5742 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5743 &zero_address_frag
);
5745 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5746 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5747 &zero_address_frag
);
5749 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5750 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5751 &zero_address_frag
);
5753 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5754 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5755 &zero_address_frag
);
5757 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5758 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5759 &zero_address_frag
);
5761 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5762 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5763 &zero_address_frag
);
5765 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5766 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5767 &zero_address_frag
);
5769 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5770 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5771 &zero_address_frag
);
5773 /* Compute the table of best templates. We compute goodness as a
5774 base 4 value, in which each match counts for 3, each F counts
5775 for 2, each B counts for 1. This should maximize the number of
5776 F and B nops in the chosen bundles, which is good because these
5777 pipelines are least likely to be overcommitted. */
5778 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
5779 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
5780 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
5783 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
5786 if (match (t
, i
, 0))
5788 if (match (t
, j
, 1))
5790 if (match (t
, k
, 2))
5791 goodness
= 3 + 3 + 3;
5793 goodness
= 3 + 3 + extra_goodness (t
, 2);
5795 else if (match (t
, j
, 2))
5796 goodness
= 3 + 3 + extra_goodness (t
, 1);
5800 goodness
+= extra_goodness (t
, 1);
5801 goodness
+= extra_goodness (t
, 2);
5804 else if (match (t
, i
, 1))
5806 if (match (t
, j
, 2))
5809 goodness
= 3 + extra_goodness (t
, 2);
5811 else if (match (t
, i
, 2))
5812 goodness
= 3 + extra_goodness (t
, 1);
5814 if (goodness
> best
)
5817 best_template
[i
][j
][k
] = t
;
5822 for (i
= 0; i
< NUM_SLOTS
; ++i
)
5823 md
.slot
[i
].user_template
= -1;
5825 md
.pseudo_hash
= hash_new ();
5826 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
5828 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
5829 (void *) (pseudo_opcode
+ i
));
5831 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5832 pseudo_opcode
[i
].name
, err
);
5835 md
.reg_hash
= hash_new ();
5836 md
.dynreg_hash
= hash_new ();
5837 md
.const_hash
= hash_new ();
5838 md
.entry_hash
= hash_new ();
5840 /* general registers: */
5843 for (i
= 0; i
< total
; ++i
)
5845 sprintf (name
, "r%d", i
- REG_GR
);
5846 md
.regsym
[i
] = declare_register (name
, i
);
5849 /* floating point registers: */
5851 for (; i
< total
; ++i
)
5853 sprintf (name
, "f%d", i
- REG_FR
);
5854 md
.regsym
[i
] = declare_register (name
, i
);
5857 /* application registers: */
5860 for (; i
< total
; ++i
)
5862 sprintf (name
, "ar%d", i
- REG_AR
);
5863 md
.regsym
[i
] = declare_register (name
, i
);
5866 /* control registers: */
5869 for (; i
< total
; ++i
)
5871 sprintf (name
, "cr%d", i
- REG_CR
);
5872 md
.regsym
[i
] = declare_register (name
, i
);
5875 /* predicate registers: */
5877 for (; i
< total
; ++i
)
5879 sprintf (name
, "p%d", i
- REG_P
);
5880 md
.regsym
[i
] = declare_register (name
, i
);
5883 /* branch registers: */
5885 for (; i
< total
; ++i
)
5887 sprintf (name
, "b%d", i
- REG_BR
);
5888 md
.regsym
[i
] = declare_register (name
, i
);
5891 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
5892 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
5893 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
5894 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
5895 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
5896 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
5897 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
5899 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
5901 regnum
= indirect_reg
[i
].regnum
;
5902 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
5905 /* define synonyms for application registers: */
5906 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
5907 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
5908 REG_AR
+ ar
[i
- REG_AR
].regnum
);
5910 /* define synonyms for control registers: */
5911 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
5912 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
5913 REG_CR
+ cr
[i
- REG_CR
].regnum
);
5915 declare_register ("gp", REG_GR
+ 1);
5916 declare_register ("sp", REG_GR
+ 12);
5917 declare_register ("rp", REG_BR
+ 0);
5919 /* pseudo-registers used to specify unwind info: */
5920 declare_register ("psp", REG_PSP
);
5922 declare_register_set ("ret", 4, REG_GR
+ 8);
5923 declare_register_set ("farg", 8, REG_FR
+ 8);
5924 declare_register_set ("fret", 8, REG_FR
+ 8);
5926 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
5928 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
5929 (PTR
) (const_bits
+ i
));
5931 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5935 /* Default to 64-bit mode. */
5936 /* ??? This overrides the -M options, but they aren't working anyways. */
5937 md
.flags
|= EF_IA_64_ABI64
;
5939 md
.mem_offset
.hint
= 0;
5942 md
.entry_labels
= NULL
;
5946 ia64_end_of_source ()
5948 /* terminate insn group upon reaching end of file: */
5949 insn_group_break (1, 0, 0);
5951 /* emits slots we haven't written yet: */
5952 ia64_flush_insns ();
5954 bfd_set_private_flags (stdoutput
, md
.flags
);
5956 if (debug_type
== DEBUG_DWARF2
)
5959 md
.mem_offset
.hint
= 0;
5965 md
.qp
.X_op
= O_absent
;
5967 if (ignore_input ())
5970 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
5972 if (md
.detect_dv
&& !md
.explicit_mode
)
5973 as_warn (_("Explicit stops are ignored in auto mode"));
5975 insn_group_break (1, 0, 0);
5980 ia64_unrecognized_line (ch
)
5986 expression (&md
.qp
);
5987 if (*input_line_pointer
++ != ')')
5989 as_bad ("Expected ')'");
5992 if (md
.qp
.X_op
!= O_register
)
5994 as_bad ("Qualifying predicate expected");
5997 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
5999 as_bad ("Predicate register expected");
6005 if (md
.manual_bundling
)
6006 as_warn ("Found '{' when manual bundling is already turned on");
6008 CURR_SLOT
.manual_bundling_on
= 1;
6009 md
.manual_bundling
= 1;
6011 /* Bundling is only acceptable in explicit mode
6012 or when in default automatic mode. */
6013 if (md
.detect_dv
&& !md
.explicit_mode
)
6015 if (!md
.mode_explicitly_set
6016 && !md
.default_explicit_mode
)
6019 as_warn (_("Found '{' after explicit switch to automatic mode"));
6024 if (!md
.manual_bundling
)
6025 as_warn ("Found '}' when manual bundling is off");
6027 PREV_SLOT
.manual_bundling_off
= 1;
6028 md
.manual_bundling
= 0;
6030 /* switch back to automatic mode, if applicable */
6033 && !md
.mode_explicitly_set
6034 && !md
.default_explicit_mode
)
6037 /* Allow '{' to follow on the same line. We also allow ";;", but that
6038 happens automatically because ';' is an end of line marker. */
6040 if (input_line_pointer
[0] == '{')
6042 input_line_pointer
++;
6043 return ia64_unrecognized_line ('{');
6046 demand_empty_rest_of_line ();
6053 /* Not a valid line. */
6058 ia64_frob_label (sym
)
6061 struct label_fix
*fix
;
6063 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6065 md
.last_text_seg
= now_seg
;
6066 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6068 fix
->next
= CURR_SLOT
.label_fixups
;
6069 CURR_SLOT
.label_fixups
= fix
;
6071 /* Keep track of how many code entry points we've seen. */
6072 if (md
.path
== md
.maxpaths
)
6075 md
.entry_labels
= (const char **)
6076 xrealloc ((void *) md
.entry_labels
,
6077 md
.maxpaths
* sizeof (char *));
6079 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6084 ia64_flush_pending_output ()
6086 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6088 /* ??? This causes many unnecessary stop bits to be emitted.
6089 Unfortunately, it isn't clear if it is safe to remove this. */
6090 insn_group_break (1, 0, 0);
6091 ia64_flush_insns ();
6095 /* Do ia64-specific expression optimization. All that's done here is
6096 to transform index expressions that are either due to the indexing
6097 of rotating registers or due to the indexing of indirect register
6100 ia64_optimize_expr (l
, op
, r
)
6109 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6111 num_regs
= (l
->X_add_number
>> 16);
6112 if ((unsigned) r
->X_add_number
>= num_regs
)
6115 as_bad ("No current frame");
6117 as_bad ("Index out of range 0..%u", num_regs
- 1);
6118 r
->X_add_number
= 0;
6120 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6123 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6125 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6126 || l
->X_add_number
== IND_MEM
)
6128 as_bad ("Indirect register set name expected");
6129 l
->X_add_number
= IND_CPUID
;
6132 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6133 l
->X_add_number
= r
->X_add_number
;
6141 ia64_parse_name (name
, e
)
6145 struct const_desc
*cdesc
;
6146 struct dynreg
*dr
= 0;
6147 unsigned int regnum
;
6151 /* first see if NAME is a known register name: */
6152 sym
= hash_find (md
.reg_hash
, name
);
6155 e
->X_op
= O_register
;
6156 e
->X_add_number
= S_GET_VALUE (sym
);
6160 cdesc
= hash_find (md
.const_hash
, name
);
6163 e
->X_op
= O_constant
;
6164 e
->X_add_number
= cdesc
->value
;
6168 /* check for inN, locN, or outN: */
6172 if (name
[1] == 'n' && isdigit (name
[2]))
6180 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6188 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6201 /* The name is inN, locN, or outN; parse the register number. */
6202 regnum
= strtoul (name
, &end
, 10);
6203 if (end
> name
&& *end
== '\0')
6205 if ((unsigned) regnum
>= dr
->num_regs
)
6208 as_bad ("No current frame");
6210 as_bad ("Register number out of range 0..%u",
6214 e
->X_op
= O_register
;
6215 e
->X_add_number
= dr
->base
+ regnum
;
6220 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6222 /* We've got ourselves the name of a rotating register set.
6223 Store the base register number in the low 16 bits of
6224 X_add_number and the size of the register set in the top 16
6226 e
->X_op
= O_register
;
6227 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6233 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6236 ia64_canonicalize_symbol_name (name
)
6239 size_t len
= strlen (name
);
6240 if (len
> 1 && name
[len
- 1] == '#')
6241 name
[len
- 1] = '\0';
6246 is_conditional_branch (idesc
)
6247 struct ia64_opcode
*idesc
;
6249 return (strncmp (idesc
->name
, "br", 2) == 0
6250 && (strcmp (idesc
->name
, "br") == 0
6251 || strncmp (idesc
->name
, "br.cond", 7) == 0
6252 || strncmp (idesc
->name
, "br.call", 7) == 0
6253 || strncmp (idesc
->name
, "br.ret", 6) == 0
6254 || strcmp (idesc
->name
, "brl") == 0
6255 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6256 || strncmp (idesc
->name
, "brl.call", 7) == 0
6257 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6260 /* Return whether the given opcode is a taken branch. If there's any doubt,
6264 is_taken_branch (idesc
)
6265 struct ia64_opcode
*idesc
;
6267 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6268 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6271 /* Return whether the given opcode is an interruption or rfi. If there's any
6272 doubt, returns zero. */
6275 is_interruption_or_rfi (idesc
)
6276 struct ia64_opcode
*idesc
;
6278 if (strcmp (idesc
->name
, "rfi") == 0)
6283 /* Returns the index of the given dependency in the opcode's list of chks, or
6284 -1 if there is no dependency. */
6287 depends_on (depind
, idesc
)
6289 struct ia64_opcode
*idesc
;
6292 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6293 for (i
= 0; i
< dep
->nchks
; i
++)
6295 if (depind
== DEP (dep
->chks
[i
]))
6301 /* Determine a set of specific resources used for a particular resource
6302 class. Returns the number of specific resources identified For those
6303 cases which are not determinable statically, the resource returned is
6306 Meanings of value in 'NOTE':
6307 1) only read/write when the register number is explicitly encoded in the
6309 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6310 accesses CFM when qualifying predicate is in the rotating region.
6311 3) general register value is used to specify an indirect register; not
6312 determinable statically.
6313 4) only read the given resource when bits 7:0 of the indirect index
6314 register value does not match the register number of the resource; not
6315 determinable statically.
6316 5) all rules are implementation specific.
6317 6) only when both the index specified by the reader and the index specified
6318 by the writer have the same value in bits 63:61; not determinable
6320 7) only access the specified resource when the corresponding mask bit is
6322 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6323 only read when these insns reference FR2-31
6324 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6325 written when these insns write FR32-127
6326 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6328 11) The target predicates are written independently of PR[qp], but source
6329 registers are only read if PR[qp] is true. Since the state of PR[qp]
6330 cannot statically be determined, all source registers are marked used.
6331 12) This insn only reads the specified predicate register when that
6332 register is the PR[qp].
6333 13) This reference to ld-c only applies to teh GR whose value is loaded
6334 with data returned from memory, not the post-incremented address register.
6335 14) The RSE resource includes the implementation-specific RSE internal
6336 state resources. At least one (and possibly more) of these resources are
6337 read by each instruction listed in IC:rse-readers. At least one (and
6338 possibly more) of these resources are written by each insn listed in
6340 15+16) Represents reserved instructions, which the assembler does not
6343 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6344 this code; there are no dependency violations based on memory access.
6347 #define MAX_SPECS 256
6352 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6353 const struct ia64_dependency
*dep
;
6354 struct ia64_opcode
*idesc
;
6355 int type
; /* is this a DV chk or a DV reg? */
6356 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6357 int note
; /* resource note for this insn's usage */
6358 int path
; /* which execution path to examine */
6365 if (dep
->mode
== IA64_DV_WAW
6366 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6367 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6370 /* template for any resources we identify */
6371 tmpl
.dependency
= dep
;
6373 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6374 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6375 tmpl
.link_to_qp_branch
= 1;
6376 tmpl
.mem_offset
.hint
= 0;
6379 tmpl
.cmp_type
= CMP_NONE
;
6382 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6383 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6384 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6386 /* we don't need to track these */
6387 if (dep
->semantics
== IA64_DVS_NONE
)
6390 switch (dep
->specifier
)
6395 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6397 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6398 if (regno
>= 0 && regno
<= 7)
6400 specs
[count
] = tmpl
;
6401 specs
[count
++].index
= regno
;
6407 for (i
= 0; i
< 8; i
++)
6409 specs
[count
] = tmpl
;
6410 specs
[count
++].index
= i
;
6419 case IA64_RS_AR_UNAT
:
6420 /* This is a mov =AR or mov AR= instruction. */
6421 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6423 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6424 if (regno
== AR_UNAT
)
6426 specs
[count
++] = tmpl
;
6431 /* This is a spill/fill, or other instruction that modifies the
6434 /* Unless we can determine the specific bits used, mark the whole
6435 thing; bits 8:3 of the memory address indicate the bit used in
6436 UNAT. The .mem.offset hint may be used to eliminate a small
6437 subset of conflicts. */
6438 specs
[count
] = tmpl
;
6439 if (md
.mem_offset
.hint
)
6442 fprintf (stderr
, " Using hint for spill/fill\n");
6443 /* The index isn't actually used, just set it to something
6444 approximating the bit index. */
6445 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6446 specs
[count
].mem_offset
.hint
= 1;
6447 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6448 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6452 specs
[count
++].specific
= 0;
6460 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6462 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6463 if ((regno
>= 8 && regno
<= 15)
6464 || (regno
>= 20 && regno
<= 23)
6465 || (regno
>= 31 && regno
<= 39)
6466 || (regno
>= 41 && regno
<= 47)
6467 || (regno
>= 67 && regno
<= 111))
6469 specs
[count
] = tmpl
;
6470 specs
[count
++].index
= regno
;
6483 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6485 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6486 if ((regno
>= 48 && regno
<= 63)
6487 || (regno
>= 112 && regno
<= 127))
6489 specs
[count
] = tmpl
;
6490 specs
[count
++].index
= regno
;
6496 for (i
= 48; i
< 64; i
++)
6498 specs
[count
] = tmpl
;
6499 specs
[count
++].index
= i
;
6501 for (i
= 112; i
< 128; i
++)
6503 specs
[count
] = tmpl
;
6504 specs
[count
++].index
= i
;
6522 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6523 if (idesc
->operands
[i
] == IA64_OPND_B1
6524 || idesc
->operands
[i
] == IA64_OPND_B2
)
6526 specs
[count
] = tmpl
;
6527 specs
[count
++].index
=
6528 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6533 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
6534 if (idesc
->operands
[i
] == IA64_OPND_B1
6535 || idesc
->operands
[i
] == IA64_OPND_B2
)
6537 specs
[count
] = tmpl
;
6538 specs
[count
++].index
=
6539 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6545 case IA64_RS_CPUID
: /* four or more registers */
6548 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6550 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6551 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6554 specs
[count
] = tmpl
;
6555 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6559 specs
[count
] = tmpl
;
6560 specs
[count
++].specific
= 0;
6570 case IA64_RS_DBR
: /* four or more registers */
6573 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6575 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6576 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6579 specs
[count
] = tmpl
;
6580 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6584 specs
[count
] = tmpl
;
6585 specs
[count
++].specific
= 0;
6589 else if (note
== 0 && !rsrc_write
)
6591 specs
[count
] = tmpl
;
6592 specs
[count
++].specific
= 0;
6600 case IA64_RS_IBR
: /* four or more registers */
6603 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6605 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6606 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6609 specs
[count
] = tmpl
;
6610 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6614 specs
[count
] = tmpl
;
6615 specs
[count
++].specific
= 0;
6628 /* These are implementation specific. Force all references to
6629 conflict with all other references. */
6630 specs
[count
] = tmpl
;
6631 specs
[count
++].specific
= 0;
6639 case IA64_RS_PKR
: /* 16 or more registers */
6640 if (note
== 3 || note
== 4)
6642 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6644 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6645 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6650 specs
[count
] = tmpl
;
6651 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6654 for (i
= 0; i
< NELEMS (gr_values
); i
++)
6656 /* Uses all registers *except* the one in R3. */
6657 if (i
!= (gr_values
[regno
].value
& 0xFF))
6659 specs
[count
] = tmpl
;
6660 specs
[count
++].index
= i
;
6666 specs
[count
] = tmpl
;
6667 specs
[count
++].specific
= 0;
6674 specs
[count
] = tmpl
;
6675 specs
[count
++].specific
= 0;
6679 case IA64_RS_PMC
: /* four or more registers */
6682 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
6683 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
6686 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
6688 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
6689 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6692 specs
[count
] = tmpl
;
6693 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6697 specs
[count
] = tmpl
;
6698 specs
[count
++].specific
= 0;
6708 case IA64_RS_PMD
: /* four or more registers */
6711 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
6713 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6714 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6717 specs
[count
] = tmpl
;
6718 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6722 specs
[count
] = tmpl
;
6723 specs
[count
++].specific
= 0;
6733 case IA64_RS_RR
: /* eight registers */
6736 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
6738 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6739 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6742 specs
[count
] = tmpl
;
6743 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
6747 specs
[count
] = tmpl
;
6748 specs
[count
++].specific
= 0;
6752 else if (note
== 0 && !rsrc_write
)
6754 specs
[count
] = tmpl
;
6755 specs
[count
++].specific
= 0;
6763 case IA64_RS_CR_IRR
:
6766 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6767 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
6769 && idesc
->operands
[1] == IA64_OPND_CR3
6772 for (i
= 0; i
< 4; i
++)
6774 specs
[count
] = tmpl
;
6775 specs
[count
++].index
= CR_IRR0
+ i
;
6781 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6782 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6784 && regno
<= CR_IRR3
)
6786 specs
[count
] = tmpl
;
6787 specs
[count
++].index
= regno
;
6796 case IA64_RS_CR_LRR
:
6803 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6804 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6805 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
6807 specs
[count
] = tmpl
;
6808 specs
[count
++].index
= regno
;
6816 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
6818 specs
[count
] = tmpl
;
6819 specs
[count
++].index
=
6820 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6835 else if (rsrc_write
)
6837 if (dep
->specifier
== IA64_RS_FRb
6838 && idesc
->operands
[0] == IA64_OPND_F1
)
6840 specs
[count
] = tmpl
;
6841 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
6846 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
6848 if (idesc
->operands
[i
] == IA64_OPND_F2
6849 || idesc
->operands
[i
] == IA64_OPND_F3
6850 || idesc
->operands
[i
] == IA64_OPND_F4
)
6852 specs
[count
] = tmpl
;
6853 specs
[count
++].index
=
6854 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
6863 /* This reference applies only to the GR whose value is loaded with
6864 data returned from memory. */
6865 specs
[count
] = tmpl
;
6866 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
6872 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6873 if (idesc
->operands
[i
] == IA64_OPND_R1
6874 || idesc
->operands
[i
] == IA64_OPND_R2
6875 || idesc
->operands
[i
] == IA64_OPND_R3
)
6877 specs
[count
] = tmpl
;
6878 specs
[count
++].index
=
6879 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6881 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
6882 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
6883 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
6885 specs
[count
] = tmpl
;
6886 specs
[count
++].index
=
6887 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6892 /* Look for anything that reads a GR. */
6893 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
6895 if (idesc
->operands
[i
] == IA64_OPND_MR3
6896 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
6897 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
6898 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
6899 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
6900 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
6901 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
6902 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
6903 || idesc
->operands
[i
] == IA64_OPND_RR_R3
6904 || ((i
>= idesc
->num_outputs
)
6905 && (idesc
->operands
[i
] == IA64_OPND_R1
6906 || idesc
->operands
[i
] == IA64_OPND_R2
6907 || idesc
->operands
[i
] == IA64_OPND_R3
6908 /* addl source register. */
6909 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
6911 specs
[count
] = tmpl
;
6912 specs
[count
++].index
=
6913 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6924 /* This is the same as IA64_RS_PRr, except that the register range is
6925 from 1 - 15, and there are no rotating register reads/writes here. */
6929 for (i
= 1; i
< 16; i
++)
6931 specs
[count
] = tmpl
;
6932 specs
[count
++].index
= i
;
6938 /* Mark only those registers indicated by the mask. */
6941 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
6942 for (i
= 1; i
< 16; i
++)
6943 if (mask
& ((valueT
) 1 << i
))
6945 specs
[count
] = tmpl
;
6946 specs
[count
++].index
= i
;
6954 else if (note
== 11) /* note 11 implies note 1 as well */
6958 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6960 if (idesc
->operands
[i
] == IA64_OPND_P1
6961 || idesc
->operands
[i
] == IA64_OPND_P2
)
6963 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
6964 if (regno
>= 1 && regno
< 16)
6966 specs
[count
] = tmpl
;
6967 specs
[count
++].index
= regno
;
6977 else if (note
== 12)
6979 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
6981 specs
[count
] = tmpl
;
6982 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6989 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
6990 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
6991 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
6992 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
6994 if ((idesc
->operands
[0] == IA64_OPND_P1
6995 || idesc
->operands
[0] == IA64_OPND_P2
)
6996 && p1
>= 1 && p1
< 16)
6998 specs
[count
] = tmpl
;
6999 specs
[count
].cmp_type
=
7000 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7001 specs
[count
++].index
= p1
;
7003 if ((idesc
->operands
[1] == IA64_OPND_P1
7004 || idesc
->operands
[1] == IA64_OPND_P2
)
7005 && p2
>= 1 && p2
< 16)
7007 specs
[count
] = tmpl
;
7008 specs
[count
].cmp_type
=
7009 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7010 specs
[count
++].index
= p2
;
7015 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7017 specs
[count
] = tmpl
;
7018 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7020 if (idesc
->operands
[1] == IA64_OPND_PR
)
7022 for (i
= 1; i
< 16; i
++)
7024 specs
[count
] = tmpl
;
7025 specs
[count
++].index
= i
;
7036 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7037 simplified cases of this. */
7041 for (i
= 16; i
< 63; i
++)
7043 specs
[count
] = tmpl
;
7044 specs
[count
++].index
= i
;
7050 /* Mark only those registers indicated by the mask. */
7052 && idesc
->operands
[0] == IA64_OPND_PR
)
7054 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7055 if (mask
& ((valueT
) 1<<16))
7056 for (i
= 16; i
< 63; i
++)
7058 specs
[count
] = tmpl
;
7059 specs
[count
++].index
= i
;
7063 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7065 for (i
= 16; i
< 63; i
++)
7067 specs
[count
] = tmpl
;
7068 specs
[count
++].index
= i
;
7076 else if (note
== 11) /* note 11 implies note 1 as well */
7080 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7082 if (idesc
->operands
[i
] == IA64_OPND_P1
7083 || idesc
->operands
[i
] == IA64_OPND_P2
)
7085 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7086 if (regno
>= 16 && regno
< 63)
7088 specs
[count
] = tmpl
;
7089 specs
[count
++].index
= regno
;
7099 else if (note
== 12)
7101 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7103 specs
[count
] = tmpl
;
7104 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7111 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7112 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7113 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7114 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7116 if ((idesc
->operands
[0] == IA64_OPND_P1
7117 || idesc
->operands
[0] == IA64_OPND_P2
)
7118 && p1
>= 16 && p1
< 63)
7120 specs
[count
] = tmpl
;
7121 specs
[count
].cmp_type
=
7122 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7123 specs
[count
++].index
= p1
;
7125 if ((idesc
->operands
[1] == IA64_OPND_P1
7126 || idesc
->operands
[1] == IA64_OPND_P2
)
7127 && p2
>= 16 && p2
< 63)
7129 specs
[count
] = tmpl
;
7130 specs
[count
].cmp_type
=
7131 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7132 specs
[count
++].index
= p2
;
7137 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7139 specs
[count
] = tmpl
;
7140 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7142 if (idesc
->operands
[1] == IA64_OPND_PR
)
7144 for (i
= 16; i
< 63; i
++)
7146 specs
[count
] = tmpl
;
7147 specs
[count
++].index
= i
;
7159 /* Verify that the instruction is using the PSR bit indicated in
7163 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7165 if (dep
->regindex
< 6)
7167 specs
[count
++] = tmpl
;
7170 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7172 if (dep
->regindex
< 32
7173 || dep
->regindex
== 35
7174 || dep
->regindex
== 36
7175 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7177 specs
[count
++] = tmpl
;
7180 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7182 if (dep
->regindex
< 32
7183 || dep
->regindex
== 35
7184 || dep
->regindex
== 36
7185 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7187 specs
[count
++] = tmpl
;
7192 /* Several PSR bits have very specific dependencies. */
7193 switch (dep
->regindex
)
7196 specs
[count
++] = tmpl
;
7201 specs
[count
++] = tmpl
;
7205 /* Only certain CR accesses use PSR.ic */
7206 if (idesc
->operands
[0] == IA64_OPND_CR3
7207 || idesc
->operands
[1] == IA64_OPND_CR3
)
7210 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7213 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7228 specs
[count
++] = tmpl
;
7237 specs
[count
++] = tmpl
;
7241 /* Only some AR accesses use cpl */
7242 if (idesc
->operands
[0] == IA64_OPND_AR3
7243 || idesc
->operands
[1] == IA64_OPND_AR3
)
7246 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7249 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7256 && regno
<= AR_K7
))))
7258 specs
[count
++] = tmpl
;
7263 specs
[count
++] = tmpl
;
7273 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7275 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7281 if (mask
& ((valueT
) 1 << dep
->regindex
))
7283 specs
[count
++] = tmpl
;
7288 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7289 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7290 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7291 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7293 if (idesc
->operands
[i
] == IA64_OPND_F1
7294 || idesc
->operands
[i
] == IA64_OPND_F2
7295 || idesc
->operands
[i
] == IA64_OPND_F3
7296 || idesc
->operands
[i
] == IA64_OPND_F4
)
7298 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7299 if (reg
>= min
&& reg
<= max
)
7301 specs
[count
++] = tmpl
;
7308 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7309 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7310 /* mfh is read on writes to FR32-127; mfl is read on writes to
7312 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7314 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7316 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7317 if (reg
>= min
&& reg
<= max
)
7319 specs
[count
++] = tmpl
;
7324 else if (note
== 10)
7326 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7328 if (idesc
->operands
[i
] == IA64_OPND_R1
7329 || idesc
->operands
[i
] == IA64_OPND_R2
7330 || idesc
->operands
[i
] == IA64_OPND_R3
)
7332 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7333 if (regno
>= 16 && regno
<= 31)
7335 specs
[count
++] = tmpl
;
7346 case IA64_RS_AR_FPSR
:
7347 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7349 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7350 if (regno
== AR_FPSR
)
7352 specs
[count
++] = tmpl
;
7357 specs
[count
++] = tmpl
;
7362 /* Handle all AR[REG] resources */
7363 if (note
== 0 || note
== 1)
7365 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7366 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7367 && regno
== dep
->regindex
)
7369 specs
[count
++] = tmpl
;
7371 /* other AR[REG] resources may be affected by AR accesses */
7372 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7375 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7376 switch (dep
->regindex
)
7382 if (regno
== AR_BSPSTORE
)
7384 specs
[count
++] = tmpl
;
7388 (regno
== AR_BSPSTORE
7389 || regno
== AR_RNAT
))
7391 specs
[count
++] = tmpl
;
7396 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7399 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7400 switch (dep
->regindex
)
7405 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7407 specs
[count
++] = tmpl
;
7414 specs
[count
++] = tmpl
;
7424 /* Handle all CR[REG] resources */
7425 if (note
== 0 || note
== 1)
7427 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7429 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7430 if (regno
== dep
->regindex
)
7432 specs
[count
++] = tmpl
;
7434 else if (!rsrc_write
)
7436 /* Reads from CR[IVR] affect other resources. */
7437 if (regno
== CR_IVR
)
7439 if ((dep
->regindex
>= CR_IRR0
7440 && dep
->regindex
<= CR_IRR3
)
7441 || dep
->regindex
== CR_TPR
)
7443 specs
[count
++] = tmpl
;
7450 specs
[count
++] = tmpl
;
7459 case IA64_RS_INSERVICE
:
7460 /* look for write of EOI (67) or read of IVR (65) */
7461 if ((idesc
->operands
[0] == IA64_OPND_CR3
7462 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7463 || (idesc
->operands
[1] == IA64_OPND_CR3
7464 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7466 specs
[count
++] = tmpl
;
7473 specs
[count
++] = tmpl
;
7484 specs
[count
++] = tmpl
;
7488 /* Check if any of the registers accessed are in the rotating region.
7489 mov to/from pr accesses CFM only when qp_regno is in the rotating
7491 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7493 if (idesc
->operands
[i
] == IA64_OPND_R1
7494 || idesc
->operands
[i
] == IA64_OPND_R2
7495 || idesc
->operands
[i
] == IA64_OPND_R3
)
7497 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7498 /* Assumes that md.rot.num_regs is always valid */
7499 if (md
.rot
.num_regs
> 0
7501 && num
< 31 + md
.rot
.num_regs
)
7503 specs
[count
] = tmpl
;
7504 specs
[count
++].specific
= 0;
7507 else if (idesc
->operands
[i
] == IA64_OPND_F1
7508 || idesc
->operands
[i
] == IA64_OPND_F2
7509 || idesc
->operands
[i
] == IA64_OPND_F3
7510 || idesc
->operands
[i
] == IA64_OPND_F4
)
7512 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7515 specs
[count
] = tmpl
;
7516 specs
[count
++].specific
= 0;
7519 else if (idesc
->operands
[i
] == IA64_OPND_P1
7520 || idesc
->operands
[i
] == IA64_OPND_P2
)
7522 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7525 specs
[count
] = tmpl
;
7526 specs
[count
++].specific
= 0;
7530 if (CURR_SLOT
.qp_regno
> 15)
7532 specs
[count
] = tmpl
;
7533 specs
[count
++].specific
= 0;
7538 /* This is the same as IA64_RS_PRr, except simplified to account for
7539 the fact that there is only one register. */
7543 specs
[count
++] = tmpl
;
7548 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7549 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7550 if (mask
& ((valueT
) 1 << 63))
7551 specs
[count
++] = tmpl
;
7553 else if (note
== 11)
7555 if ((idesc
->operands
[0] == IA64_OPND_P1
7556 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7557 || (idesc
->operands
[1] == IA64_OPND_P2
7558 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7560 specs
[count
++] = tmpl
;
7563 else if (note
== 12)
7565 if (CURR_SLOT
.qp_regno
== 63)
7567 specs
[count
++] = tmpl
;
7574 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7575 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7576 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7577 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7580 && (idesc
->operands
[0] == IA64_OPND_P1
7581 || idesc
->operands
[0] == IA64_OPND_P2
))
7583 specs
[count
] = tmpl
;
7584 specs
[count
++].cmp_type
=
7585 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7588 && (idesc
->operands
[1] == IA64_OPND_P1
7589 || idesc
->operands
[1] == IA64_OPND_P2
))
7591 specs
[count
] = tmpl
;
7592 specs
[count
++].cmp_type
=
7593 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7598 if (CURR_SLOT
.qp_regno
== 63)
7600 specs
[count
++] = tmpl
;
7611 /* FIXME we can identify some individual RSE written resources, but RSE
7612 read resources have not yet been completely identified, so for now
7613 treat RSE as a single resource */
7614 if (strncmp (idesc
->name
, "mov", 3) == 0)
7618 if (idesc
->operands
[0] == IA64_OPND_AR3
7619 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7621 specs
[count
] = tmpl
;
7622 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7627 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7629 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7630 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7632 specs
[count
++] = tmpl
;
7635 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7637 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7638 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7639 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7641 specs
[count
++] = tmpl
;
7648 specs
[count
++] = tmpl
;
7653 /* FIXME -- do any of these need to be non-specific? */
7654 specs
[count
++] = tmpl
;
7658 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7665 /* Clear branch flags on marked resources. This breaks the link between the
7666 QP of the marking instruction and a subsequent branch on the same QP. */
7669 clear_qp_branch_flag (mask
)
7673 for (i
= 0; i
< regdepslen
; i
++)
7675 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
7676 if ((bit
& mask
) != 0)
7678 regdeps
[i
].link_to_qp_branch
= 0;
7683 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7685 Any changes to a PR clears the mutex relations which include that PR. */
7688 clear_qp_mutex (mask
)
7694 while (i
< qp_mutexeslen
)
7696 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
7700 fprintf (stderr
, " Clearing mutex relation");
7701 print_prmask (qp_mutexes
[i
].prmask
);
7702 fprintf (stderr
, "\n");
7704 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
7711 /* Clear implies relations which contain PRs in the given masks.
7712 P1_MASK indicates the source of the implies relation, while P2_MASK
7713 indicates the implied PR. */
7716 clear_qp_implies (p1_mask
, p2_mask
)
7723 while (i
< qp_implieslen
)
7725 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
7726 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
7729 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
7730 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
7731 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
7738 /* Add the PRs specified to the list of implied relations. */
7741 add_qp_imply (p1
, p2
)
7748 /* p0 is not meaningful here. */
7749 if (p1
== 0 || p2
== 0)
7755 /* If it exists already, ignore it. */
7756 for (i
= 0; i
< qp_implieslen
; i
++)
7758 if (qp_implies
[i
].p1
== p1
7759 && qp_implies
[i
].p2
== p2
7760 && qp_implies
[i
].path
== md
.path
7761 && !qp_implies
[i
].p2_branched
)
7765 if (qp_implieslen
== qp_impliestotlen
)
7767 qp_impliestotlen
+= 20;
7768 qp_implies
= (struct qp_imply
*)
7769 xrealloc ((void *) qp_implies
,
7770 qp_impliestotlen
* sizeof (struct qp_imply
));
7773 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
7774 qp_implies
[qp_implieslen
].p1
= p1
;
7775 qp_implies
[qp_implieslen
].p2
= p2
;
7776 qp_implies
[qp_implieslen
].path
= md
.path
;
7777 qp_implies
[qp_implieslen
++].p2_branched
= 0;
7779 /* Add in the implied transitive relations; for everything that p2 implies,
7780 make p1 imply that, too; for everything that implies p1, make it imply p2
7782 for (i
= 0; i
< qp_implieslen
; i
++)
7784 if (qp_implies
[i
].p1
== p2
)
7785 add_qp_imply (p1
, qp_implies
[i
].p2
);
7786 if (qp_implies
[i
].p2
== p1
)
7787 add_qp_imply (qp_implies
[i
].p1
, p2
);
7789 /* Add in mutex relations implied by this implies relation; for each mutex
7790 relation containing p2, duplicate it and replace p2 with p1. */
7791 bit
= (valueT
) 1 << p1
;
7792 mask
= (valueT
) 1 << p2
;
7793 for (i
= 0; i
< qp_mutexeslen
; i
++)
7795 if (qp_mutexes
[i
].prmask
& mask
)
7796 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
7800 /* Add the PRs specified in the mask to the mutex list; this means that only
7801 one of the PRs can be true at any time. PR0 should never be included in
7811 if (qp_mutexeslen
== qp_mutexestotlen
)
7813 qp_mutexestotlen
+= 20;
7814 qp_mutexes
= (struct qpmutex
*)
7815 xrealloc ((void *) qp_mutexes
,
7816 qp_mutexestotlen
* sizeof (struct qpmutex
));
7820 fprintf (stderr
, " Registering mutex on");
7821 print_prmask (mask
);
7822 fprintf (stderr
, "\n");
7824 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
7825 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
7829 clear_register_values ()
7833 fprintf (stderr
, " Clearing register values\n");
7834 for (i
= 1; i
< NELEMS (gr_values
); i
++)
7835 gr_values
[i
].known
= 0;
7838 /* Keep track of register values/changes which affect DV tracking.
7840 optimization note: should add a flag to classes of insns where otherwise we
7841 have to examine a group of strings to identify them. */
7844 note_register_values (idesc
)
7845 struct ia64_opcode
*idesc
;
7847 valueT qp_changemask
= 0;
7850 /* Invalidate values for registers being written to. */
7851 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7853 if (idesc
->operands
[i
] == IA64_OPND_R1
7854 || idesc
->operands
[i
] == IA64_OPND_R2
7855 || idesc
->operands
[i
] == IA64_OPND_R3
)
7857 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7858 if (regno
> 0 && regno
< NELEMS (gr_values
))
7859 gr_values
[regno
].known
= 0;
7861 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
7863 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7864 if (regno
> 0 && regno
< 4)
7865 gr_values
[regno
].known
= 0;
7867 else if (idesc
->operands
[i
] == IA64_OPND_P1
7868 || idesc
->operands
[i
] == IA64_OPND_P2
)
7870 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7871 qp_changemask
|= (valueT
) 1 << regno
;
7873 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
7875 if (idesc
->operands
[2] & (valueT
) 0x10000)
7876 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
7878 qp_changemask
= idesc
->operands
[2];
7881 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
7883 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
7884 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
7886 qp_changemask
= idesc
->operands
[1];
7887 qp_changemask
&= ~(valueT
) 0xFFFF;
7892 /* Always clear qp branch flags on any PR change. */
7893 /* FIXME there may be exceptions for certain compares. */
7894 clear_qp_branch_flag (qp_changemask
);
7896 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
7897 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
7899 qp_changemask
|= ~(valueT
) 0xFFFF;
7900 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
7902 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
7903 gr_values
[i
].known
= 0;
7905 clear_qp_mutex (qp_changemask
);
7906 clear_qp_implies (qp_changemask
, qp_changemask
);
7908 /* After a call, all register values are undefined, except those marked
7910 else if (strncmp (idesc
->name
, "br.call", 6) == 0
7911 || strncmp (idesc
->name
, "brl.call", 7) == 0)
7913 // FIXME keep GR values which are marked as "safe_across_calls"
7914 clear_register_values ();
7915 clear_qp_mutex (~qp_safe_across_calls
);
7916 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
7917 clear_qp_branch_flag (~qp_safe_across_calls
);
7919 else if (is_interruption_or_rfi (idesc
)
7920 || is_taken_branch (idesc
))
7922 clear_register_values ();
7923 clear_qp_mutex (~(valueT
) 0);
7924 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
7926 /* Look for mutex and implies relations. */
7927 else if ((idesc
->operands
[0] == IA64_OPND_P1
7928 || idesc
->operands
[0] == IA64_OPND_P2
)
7929 && (idesc
->operands
[1] == IA64_OPND_P1
7930 || idesc
->operands
[1] == IA64_OPND_P2
))
7932 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7933 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7934 valueT p1mask
= (valueT
) 1 << p1
;
7935 valueT p2mask
= (valueT
) 1 << p2
;
7937 /* If one of the PRs is PR0, we can't really do anything. */
7938 if (p1
== 0 || p2
== 0)
7941 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
7943 /* In general, clear mutexes and implies which include P1 or P2,
7944 with the following exceptions. */
7945 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
7947 add_qp_mutex (p1mask
| p2mask
);
7948 clear_qp_implies (p2mask
, p1mask
);
7950 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
7952 add_qp_mutex (p1mask
| p2mask
);
7953 clear_qp_implies (p1mask
, p2mask
);
7955 else if (strstr (idesc
->name
, ".and") != NULL
)
7957 clear_qp_implies (0, p1mask
| p2mask
);
7959 else if (strstr (idesc
->name
, ".or") != NULL
)
7961 clear_qp_mutex (p1mask
| p2mask
);
7962 clear_qp_implies (p1mask
| p2mask
, 0);
7966 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
7967 if (strstr (idesc
->name
, ".unc") != NULL
)
7969 add_qp_mutex (p1mask
| p2mask
);
7970 if (CURR_SLOT
.qp_regno
!= 0)
7972 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
7973 CURR_SLOT
.qp_regno
);
7974 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
7975 CURR_SLOT
.qp_regno
);
7978 else if (CURR_SLOT
.qp_regno
== 0)
7980 add_qp_mutex (p1mask
| p2mask
);
7984 clear_qp_mutex (p1mask
| p2mask
);
7988 /* Look for mov imm insns into GRs. */
7989 else if (idesc
->operands
[0] == IA64_OPND_R1
7990 && (idesc
->operands
[1] == IA64_OPND_IMM22
7991 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
7992 && (strcmp (idesc
->name
, "mov") == 0
7993 || strcmp (idesc
->name
, "movl") == 0))
7995 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7996 if (regno
> 0 && regno
< NELEMS (gr_values
))
7998 gr_values
[regno
].known
= 1;
7999 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8000 gr_values
[regno
].path
= md
.path
;
8002 fprintf (stderr
, " Know gr%d = 0x%llx\n",
8003 regno
, gr_values
[regno
].value
);
8008 clear_qp_mutex (qp_changemask
);
8009 clear_qp_implies (qp_changemask
, qp_changemask
);
8013 /* Return whether the given predicate registers are currently mutex. */
8016 qp_mutex (p1
, p2
, path
)
8026 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8027 for (i
= 0; i
< qp_mutexeslen
; i
++)
8029 if (qp_mutexes
[i
].path
>= path
8030 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8037 /* Return whether the given resource is in the given insn's list of chks
8038 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8042 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8044 struct ia64_opcode
*idesc
;
8049 struct rsrc specs
[MAX_SPECS
];
8052 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8053 we don't need to check. One exception is note 11, which indicates that
8054 target predicates are written regardless of PR[qp]. */
8055 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8059 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8062 /* UNAT checking is a bit more specific than other resources */
8063 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8064 && specs
[count
].mem_offset
.hint
8065 && rs
->mem_offset
.hint
)
8067 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8069 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8070 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8077 /* Skip apparent PR write conflicts where both writes are an AND or both
8078 writes are an OR. */
8079 if (rs
->dependency
->specifier
== IA64_RS_PR
8080 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8082 if (specs
[count
].cmp_type
!= CMP_NONE
8083 && specs
[count
].cmp_type
== rs
->cmp_type
)
8086 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8087 dv_mode
[rs
->dependency
->mode
],
8088 rs
->dependency
->specifier
== IA64_RS_PR
?
8089 specs
[count
].index
: 63);
8094 " %s on parallel compare conflict %s vs %s on PR%d\n",
8095 dv_mode
[rs
->dependency
->mode
],
8096 dv_cmp_type
[rs
->cmp_type
],
8097 dv_cmp_type
[specs
[count
].cmp_type
],
8098 rs
->dependency
->specifier
== IA64_RS_PR
?
8099 specs
[count
].index
: 63);
8103 /* If either resource is not specific, conservatively assume a conflict
8105 if (!specs
[count
].specific
|| !rs
->specific
)
8107 else if (specs
[count
].index
== rs
->index
)
8112 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8118 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8119 insert a stop to create the break. Update all resource dependencies
8120 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8121 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8122 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8126 insn_group_break (insert_stop
, qp_regno
, save_current
)
8133 if (insert_stop
&& md
.num_slots_in_use
> 0)
8134 PREV_SLOT
.end_of_insn_group
= 1;
8138 fprintf (stderr
, " Insn group break%s",
8139 (insert_stop
? " (w/stop)" : ""));
8141 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8142 fprintf (stderr
, "\n");
8146 while (i
< regdepslen
)
8148 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8151 && regdeps
[i
].qp_regno
!= qp_regno
)
8158 && CURR_SLOT
.src_file
== regdeps
[i
].file
8159 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8165 /* clear dependencies which are automatically cleared by a stop, or
8166 those that have reached the appropriate state of insn serialization */
8167 if (dep
->semantics
== IA64_DVS_IMPLIED
8168 || dep
->semantics
== IA64_DVS_IMPLIEDF
8169 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8171 print_dependency ("Removing", i
);
8172 regdeps
[i
] = regdeps
[--regdepslen
];
8176 if (dep
->semantics
== IA64_DVS_DATA
8177 || dep
->semantics
== IA64_DVS_INSTR
8178 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8180 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8181 regdeps
[i
].insn_srlz
= STATE_STOP
;
8182 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8183 regdeps
[i
].data_srlz
= STATE_STOP
;
8190 /* Add the given resource usage spec to the list of active dependencies. */
8193 mark_resource (idesc
, dep
, spec
, depind
, path
)
8194 struct ia64_opcode
*idesc
;
8195 const struct ia64_dependency
*dep
;
8200 if (regdepslen
== regdepstotlen
)
8202 regdepstotlen
+= 20;
8203 regdeps
= (struct rsrc
*)
8204 xrealloc ((void *) regdeps
,
8205 regdepstotlen
* sizeof(struct rsrc
));
8208 regdeps
[regdepslen
] = *spec
;
8209 regdeps
[regdepslen
].depind
= depind
;
8210 regdeps
[regdepslen
].path
= path
;
8211 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8212 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8214 print_dependency ("Adding", regdepslen
);
8220 print_dependency (action
, depind
)
8226 fprintf (stderr
, " %s %s '%s'",
8227 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8228 (regdeps
[depind
].dependency
)->name
);
8229 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8230 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8231 if (regdeps
[depind
].mem_offset
.hint
)
8232 fprintf (stderr
, " 0x%llx+0x%llx",
8233 regdeps
[depind
].mem_offset
.base
,
8234 regdeps
[depind
].mem_offset
.offset
);
8235 fprintf (stderr
, "\n");
8240 instruction_serialization ()
8244 fprintf (stderr
, " Instruction serialization\n");
8245 for (i
= 0; i
< regdepslen
; i
++)
8246 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8247 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8251 data_serialization ()
8255 fprintf (stderr
, " Data serialization\n");
8256 while (i
< regdepslen
)
8258 if (regdeps
[i
].data_srlz
== STATE_STOP
8259 /* Note: as of 991210, all "other" dependencies are cleared by a
8260 data serialization. This might change with new tables */
8261 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8263 print_dependency ("Removing", i
);
8264 regdeps
[i
] = regdeps
[--regdepslen
];
8271 /* Insert stops and serializations as needed to avoid DVs. */
8274 remove_marked_resource (rs
)
8277 switch (rs
->dependency
->semantics
)
8279 case IA64_DVS_SPECIFIC
:
8281 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8282 /* ...fall through... */
8283 case IA64_DVS_INSTR
:
8285 fprintf (stderr
, "Inserting instr serialization\n");
8286 if (rs
->insn_srlz
< STATE_STOP
)
8287 insn_group_break (1, 0, 0);
8288 if (rs
->insn_srlz
< STATE_SRLZ
)
8290 int oldqp
= CURR_SLOT
.qp_regno
;
8291 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8292 /* Manually jam a srlz.i insn into the stream */
8293 CURR_SLOT
.qp_regno
= 0;
8294 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8295 instruction_serialization ();
8296 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8297 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8299 CURR_SLOT
.qp_regno
= oldqp
;
8300 CURR_SLOT
.idesc
= oldidesc
;
8302 insn_group_break (1, 0, 0);
8304 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8305 "other" types of DV are eliminated
8306 by a data serialization */
8309 fprintf (stderr
, "Inserting data serialization\n");
8310 if (rs
->data_srlz
< STATE_STOP
)
8311 insn_group_break (1, 0, 0);
8313 int oldqp
= CURR_SLOT
.qp_regno
;
8314 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8315 /* Manually jam a srlz.d insn into the stream */
8316 CURR_SLOT
.qp_regno
= 0;
8317 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8318 data_serialization ();
8319 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8320 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8322 CURR_SLOT
.qp_regno
= oldqp
;
8323 CURR_SLOT
.idesc
= oldidesc
;
8326 case IA64_DVS_IMPLIED
:
8327 case IA64_DVS_IMPLIEDF
:
8329 fprintf (stderr
, "Inserting stop\n");
8330 insn_group_break (1, 0, 0);
8337 /* Check the resources used by the given opcode against the current dependency
8340 The check is run once for each execution path encountered. In this case,
8341 a unique execution path is the sequence of instructions following a code
8342 entry point, e.g. the following has three execution paths, one starting
8343 at L0, one at L1, and one at L2.
8352 check_dependencies (idesc
)
8353 struct ia64_opcode
*idesc
;
8355 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8359 /* Note that the number of marked resources may change within the
8360 loop if in auto mode. */
8362 while (i
< regdepslen
)
8364 struct rsrc
*rs
= ®deps
[i
];
8365 const struct ia64_dependency
*dep
= rs
->dependency
;
8370 if (dep
->semantics
== IA64_DVS_NONE
8371 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8377 note
= NOTE (opdeps
->chks
[chkind
]);
8379 /* Check this resource against each execution path seen thus far. */
8380 for (path
= 0; path
<= md
.path
; path
++)
8384 /* If the dependency wasn't on the path being checked, ignore it. */
8385 if (rs
->path
< path
)
8388 /* If the QP for this insn implies a QP which has branched, don't
8389 bother checking. Ed. NOTE: I don't think this check is terribly
8390 useful; what's the point of generating code which will only be
8391 reached if its QP is zero?
8392 This code was specifically inserted to handle the following code,
8393 based on notes from Intel's DV checking code, where p1 implies p2.
8399 if (CURR_SLOT
.qp_regno
!= 0)
8403 for (implies
= 0; implies
< qp_implieslen
; implies
++)
8405 if (qp_implies
[implies
].path
>= path
8406 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8407 && qp_implies
[implies
].p2_branched
)
8417 if ((matchtype
= resources_match (rs
, idesc
, note
,
8418 CURR_SLOT
.qp_regno
, path
)) != 0)
8421 char pathmsg
[256] = "";
8422 char indexmsg
[256] = "";
8423 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8426 sprintf (pathmsg
, " when entry is at label '%s'",
8427 md
.entry_labels
[path
- 1]);
8428 if (rs
->specific
&& rs
->index
!= 0)
8429 sprintf (indexmsg
, ", specific resource number is %d",
8431 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8433 (certain
? "violates" : "may violate"),
8434 dv_mode
[dep
->mode
], dep
->name
,
8435 dv_sem
[dep
->semantics
],
8438 if (md
.explicit_mode
)
8440 as_warn ("%s", msg
);
8442 as_warn (_("Only the first path encountering the conflict "
8444 as_warn_where (rs
->file
, rs
->line
,
8445 _("This is the location of the "
8446 "conflicting usage"));
8447 /* Don't bother checking other paths, to avoid duplicating
8454 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8456 remove_marked_resource (rs
);
8458 /* since the set of dependencies has changed, start over */
8459 /* FIXME -- since we're removing dvs as we go, we
8460 probably don't really need to start over... */
8473 /* Register new dependencies based on the given opcode. */
8476 mark_resources (idesc
)
8477 struct ia64_opcode
*idesc
;
8480 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8481 int add_only_qp_reads
= 0;
8483 /* A conditional branch only uses its resources if it is taken; if it is
8484 taken, we stop following that path. The other branch types effectively
8485 *always* write their resources. If it's not taken, register only QP
8487 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8489 add_only_qp_reads
= 1;
8493 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8495 for (i
= 0; i
< opdeps
->nregs
; i
++)
8497 const struct ia64_dependency
*dep
;
8498 struct rsrc specs
[MAX_SPECS
];
8503 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8504 note
= NOTE (opdeps
->regs
[i
]);
8506 if (add_only_qp_reads
8507 && !(dep
->mode
== IA64_DV_WAR
8508 && (dep
->specifier
== IA64_RS_PR
8509 || dep
->specifier
== IA64_RS_PRr
8510 || dep
->specifier
== IA64_RS_PR63
)))
8513 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8516 if (md
.debug_dv
&& !count
)
8517 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8518 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8523 mark_resource (idesc
, dep
, &specs
[count
],
8524 DEP (opdeps
->regs
[i
]), md
.path
);
8527 /* The execution path may affect register values, which may in turn
8528 affect which indirect-access resources are accessed. */
8529 switch (dep
->specifier
)
8541 for (path
= 0; path
< md
.path
; path
++)
8543 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8545 mark_resource (idesc
, dep
, &specs
[count
],
8546 DEP (opdeps
->regs
[i
]), path
);
8553 /* Remove dependencies when they no longer apply. */
8556 update_dependencies (idesc
)
8557 struct ia64_opcode
*idesc
;
8561 if (strcmp (idesc
->name
, "srlz.i") == 0)
8563 instruction_serialization ();
8565 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8567 data_serialization ();
8569 else if (is_interruption_or_rfi (idesc
)
8570 || is_taken_branch (idesc
))
8572 /* Although technically the taken branch doesn't clear dependencies
8573 which require a srlz.[id], we don't follow the branch; the next
8574 instruction is assumed to start with a clean slate. */
8578 else if (is_conditional_branch (idesc
)
8579 && CURR_SLOT
.qp_regno
!= 0)
8581 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8583 for (i
= 0; i
< qp_implieslen
; i
++)
8585 /* If the conditional branch's predicate is implied by the predicate
8586 in an existing dependency, remove that dependency. */
8587 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8590 /* Note that this implied predicate takes a branch so that if
8591 a later insn generates a DV but its predicate implies this
8592 one, we can avoid the false DV warning. */
8593 qp_implies
[i
].p2_branched
= 1;
8594 while (depind
< regdepslen
)
8596 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8598 print_dependency ("Removing", depind
);
8599 regdeps
[depind
] = regdeps
[--regdepslen
];
8606 /* Any marked resources which have this same predicate should be
8607 cleared, provided that the QP hasn't been modified between the
8608 marking instruction and the branch. */
8611 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8616 while (i
< regdepslen
)
8618 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8619 && regdeps
[i
].link_to_qp_branch
8620 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8621 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8623 /* Treat like a taken branch */
8624 print_dependency ("Removing", i
);
8625 regdeps
[i
] = regdeps
[--regdepslen
];
8634 /* Examine the current instruction for dependency violations. */
8638 struct ia64_opcode
*idesc
;
8642 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8643 idesc
->name
, CURR_SLOT
.src_line
,
8644 idesc
->dependencies
->nchks
,
8645 idesc
->dependencies
->nregs
);
8648 /* Look through the list of currently marked resources; if the current
8649 instruction has the dependency in its chks list which uses that resource,
8650 check against the specific resources used. */
8651 check_dependencies (idesc
);
8653 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8654 then add them to the list of marked resources. */
8655 mark_resources (idesc
);
8657 /* There are several types of dependency semantics, and each has its own
8658 requirements for being cleared
8660 Instruction serialization (insns separated by interruption, rfi, or
8661 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8663 Data serialization (instruction serialization, or writer + srlz.d +
8664 reader, where writer and srlz.d are in separate groups) clears
8665 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8666 always be the case).
8668 Instruction group break (groups separated by stop, taken branch,
8669 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8671 update_dependencies (idesc
);
8673 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8674 warning. Keep track of as many as possible that are useful. */
8675 note_register_values (idesc
);
8677 /* We don't need or want this anymore. */
8678 md
.mem_offset
.hint
= 0;
8683 /* Translate one line of assembly. Pseudo ops and labels do not show
8689 char *saved_input_line_pointer
, *mnemonic
;
8690 const struct pseudo_opcode
*pdesc
;
8691 struct ia64_opcode
*idesc
;
8692 unsigned char qp_regno
;
8696 saved_input_line_pointer
= input_line_pointer
;
8697 input_line_pointer
= str
;
8699 /* extract the opcode (mnemonic): */
8701 mnemonic
= input_line_pointer
;
8702 ch
= get_symbol_end ();
8703 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
8706 *input_line_pointer
= ch
;
8707 (*pdesc
->handler
) (pdesc
->arg
);
8711 /* Find the instruction descriptor matching the arguments. */
8713 idesc
= ia64_find_opcode (mnemonic
);
8714 *input_line_pointer
= ch
;
8717 as_bad ("Unknown opcode `%s'", mnemonic
);
8721 idesc
= parse_operands (idesc
);
8725 /* Handle the dynamic ops we can handle now: */
8726 if (idesc
->type
== IA64_TYPE_DYN
)
8728 if (strcmp (idesc
->name
, "add") == 0)
8730 if (CURR_SLOT
.opnd
[2].X_op
== O_register
8731 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
8735 ia64_free_opcode (idesc
);
8736 idesc
= ia64_find_opcode (mnemonic
);
8738 know (!idesc
->next
);
8741 else if (strcmp (idesc
->name
, "mov") == 0)
8743 enum ia64_opnd opnd1
, opnd2
;
8746 opnd1
= idesc
->operands
[0];
8747 opnd2
= idesc
->operands
[1];
8748 if (opnd1
== IA64_OPND_AR3
)
8750 else if (opnd2
== IA64_OPND_AR3
)
8754 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
8755 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
8759 ia64_free_opcode (idesc
);
8760 idesc
= ia64_find_opcode (mnemonic
);
8761 while (idesc
!= NULL
8762 && (idesc
->operands
[0] != opnd1
8763 || idesc
->operands
[1] != opnd2
))
8764 idesc
= get_next_opcode (idesc
);
8769 if (md
.qp
.X_op
== O_register
)
8770 qp_regno
= md
.qp
.X_add_number
- REG_P
;
8772 flags
= idesc
->flags
;
8774 if ((flags
& IA64_OPCODE_FIRST
) != 0)
8775 insn_group_break (1, 0, 0);
8777 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
8779 as_bad ("`%s' cannot be predicated", idesc
->name
);
8783 /* Build the instruction. */
8784 CURR_SLOT
.qp_regno
= qp_regno
;
8785 CURR_SLOT
.idesc
= idesc
;
8786 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
8787 if (debug_type
== DEBUG_DWARF2
)
8788 dwarf2_where (&CURR_SLOT
.debug_line
);
8790 /* Add unwind entry, if there is one. */
8791 if (unwind
.current_entry
)
8793 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
8794 unwind
.current_entry
= NULL
;
8797 /* Check for dependency violations. */
8801 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8802 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8805 if ((flags
& IA64_OPCODE_LAST
) != 0)
8806 insn_group_break (1, 0, 0);
8808 md
.last_text_seg
= now_seg
;
8811 input_line_pointer
= saved_input_line_pointer
;
8814 /* Called when symbol NAME cannot be found in the symbol table.
8815 Should be used for dynamic valued symbols only. */
8818 md_undefined_symbol (name
)
8824 /* Called for any expression that can not be recognized. When the
8825 function is called, `input_line_pointer' will point to the start of
8832 enum pseudo_type pseudo_type
;
8837 switch (*input_line_pointer
)
8840 /* Find what relocation pseudo-function we're dealing with. */
8842 ch
= *++input_line_pointer
;
8843 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
8844 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
8846 len
= strlen (pseudo_func
[i
].name
);
8847 if (strncmp (pseudo_func
[i
].name
+ 1,
8848 input_line_pointer
+ 1, len
- 1) == 0
8849 && !is_part_of_name (input_line_pointer
[len
]))
8851 input_line_pointer
+= len
;
8852 pseudo_type
= pseudo_func
[i
].type
;
8856 switch (pseudo_type
)
8858 case PSEUDO_FUNC_RELOC
:
8860 if (*input_line_pointer
!= '(')
8862 as_bad ("Expected '('");
8866 ++input_line_pointer
;
8868 if (*input_line_pointer
++ != ')')
8870 as_bad ("Missing ')'");
8873 if (e
->X_op
!= O_symbol
)
8875 if (e
->X_op
!= O_pseudo_fixup
)
8877 as_bad ("Not a symbolic expression");
8880 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
8881 && i
== FUNC_LT_RELATIVE
)
8882 i
= FUNC_LT_FPTR_RELATIVE
;
8885 as_bad ("Illegal combination of relocation functions");
8889 /* Make sure gas doesn't get rid of local symbols that are used
8891 e
->X_op
= O_pseudo_fixup
;
8892 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
8895 case PSEUDO_FUNC_CONST
:
8896 e
->X_op
= O_constant
;
8897 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8900 case PSEUDO_FUNC_REG
:
8901 e
->X_op
= O_register
;
8902 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8906 name
= input_line_pointer
- 1;
8908 as_bad ("Unknown pseudo function `%s'", name
);
8914 ++input_line_pointer
;
8916 if (*input_line_pointer
!= ']')
8918 as_bad ("Closing bracket misssing");
8923 if (e
->X_op
!= O_register
)
8924 as_bad ("Register expected as index");
8926 ++input_line_pointer
;
8937 ignore_rest_of_line ();
8940 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8941 a section symbol plus some offset. For relocs involving @fptr(),
8942 directives we don't want such adjustments since we need to have the
8943 original symbol's name in the reloc. */
8945 ia64_fix_adjustable (fix
)
8948 /* Prevent all adjustments to global symbols */
8949 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
8952 switch (fix
->fx_r_type
)
8954 case BFD_RELOC_IA64_FPTR64I
:
8955 case BFD_RELOC_IA64_FPTR32MSB
:
8956 case BFD_RELOC_IA64_FPTR32LSB
:
8957 case BFD_RELOC_IA64_FPTR64MSB
:
8958 case BFD_RELOC_IA64_FPTR64LSB
:
8959 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8960 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8970 ia64_force_relocation (fix
)
8973 switch (fix
->fx_r_type
)
8975 case BFD_RELOC_IA64_FPTR64I
:
8976 case BFD_RELOC_IA64_FPTR32MSB
:
8977 case BFD_RELOC_IA64_FPTR32LSB
:
8978 case BFD_RELOC_IA64_FPTR64MSB
:
8979 case BFD_RELOC_IA64_FPTR64LSB
:
8981 case BFD_RELOC_IA64_LTOFF22
:
8982 case BFD_RELOC_IA64_LTOFF64I
:
8983 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8984 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8985 case BFD_RELOC_IA64_PLTOFF22
:
8986 case BFD_RELOC_IA64_PLTOFF64I
:
8987 case BFD_RELOC_IA64_PLTOFF64MSB
:
8988 case BFD_RELOC_IA64_PLTOFF64LSB
:
8997 /* Decide from what point a pc-relative relocation is relative to,
8998 relative to the pc-relative fixup. Er, relatively speaking. */
9000 ia64_pcrel_from_section (fix
, sec
)
9004 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9006 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9012 /* This is called whenever some data item (not an instruction) needs a
9013 fixup. We pick the right reloc code depending on the byteorder
9014 currently in effect. */
9016 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9022 bfd_reloc_code_real_type code
;
9027 /* There are no reloc for 8 and 16 bit quantities, but we allow
9028 them here since they will work fine as long as the expression
9029 is fully defined at the end of the pass over the source file. */
9030 case 1: code
= BFD_RELOC_8
; break;
9031 case 2: code
= BFD_RELOC_16
; break;
9033 if (target_big_endian
)
9034 code
= BFD_RELOC_IA64_DIR32MSB
;
9036 code
= BFD_RELOC_IA64_DIR32LSB
;
9040 if (target_big_endian
)
9041 code
= BFD_RELOC_IA64_DIR64MSB
;
9043 code
= BFD_RELOC_IA64_DIR64LSB
;
9047 as_bad ("Unsupported fixup size %d", nbytes
);
9048 ignore_rest_of_line ();
9051 if (exp
->X_op
== O_pseudo_fixup
)
9054 exp
->X_op
= O_symbol
;
9055 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9057 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9058 /* We need to store the byte order in effect in case we're going
9059 to fix an 8 or 16 bit relocation (for which there no real
9060 relocs available). See md_apply_fix(). */
9061 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9064 /* Return the actual relocation we wish to associate with the pseudo
9065 reloc described by SYM and R_TYPE. SYM should be one of the
9066 symbols in the pseudo_func array, or NULL. */
9068 static bfd_reloc_code_real_type
9069 ia64_gen_real_reloc_type (sym
, r_type
)
9071 bfd_reloc_code_real_type r_type
;
9073 bfd_reloc_code_real_type
new = 0;
9080 switch (S_GET_VALUE (sym
))
9082 case FUNC_FPTR_RELATIVE
:
9085 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9086 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9087 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9088 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9089 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9094 case FUNC_GP_RELATIVE
:
9097 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9098 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9099 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9100 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9101 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9102 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9107 case FUNC_LT_RELATIVE
:
9110 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9111 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9116 case FUNC_PC_RELATIVE
:
9119 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9120 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9121 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9122 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9123 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9124 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9129 case FUNC_PLT_RELATIVE
:
9132 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9133 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9134 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9135 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9140 case FUNC_SEC_RELATIVE
:
9143 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9144 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9145 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9146 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9151 case FUNC_SEG_RELATIVE
:
9154 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9155 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9156 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9157 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9162 case FUNC_LTV_RELATIVE
:
9165 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9166 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9167 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9168 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9173 case FUNC_LT_FPTR_RELATIVE
:
9176 case BFD_RELOC_IA64_IMM22
:
9177 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9178 case BFD_RELOC_IA64_IMM64
:
9179 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9187 /* Hmmmm. Should this ever occur? */
9194 /* Here is where generate the appropriate reloc for pseudo relocation
9197 ia64_validate_fix (fix
)
9200 switch (fix
->fx_r_type
)
9202 case BFD_RELOC_IA64_FPTR64I
:
9203 case BFD_RELOC_IA64_FPTR32MSB
:
9204 case BFD_RELOC_IA64_FPTR64LSB
:
9205 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9206 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9207 if (fix
->fx_offset
!= 0)
9208 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9209 "No addend allowed in @fptr() relocation");
9219 fix_insn (fix
, odesc
, value
)
9221 const struct ia64_operand
*odesc
;
9224 bfd_vma insn
[3], t0
, t1
, control_bits
;
9229 slot
= fix
->fx_where
& 0x3;
9230 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9232 /* Bundles are always in little-endian byte order */
9233 t0
= bfd_getl64 (fixpos
);
9234 t1
= bfd_getl64 (fixpos
+ 8);
9235 control_bits
= t0
& 0x1f;
9236 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9237 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9238 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9241 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9243 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9244 insn
[2] |= (((value
& 0x7f) << 13)
9245 | (((value
>> 7) & 0x1ff) << 27)
9246 | (((value
>> 16) & 0x1f) << 22)
9247 | (((value
>> 21) & 0x1) << 21)
9248 | (((value
>> 63) & 0x1) << 36));
9250 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9252 if (value
& ~0x3fffffffffffffffULL
)
9253 err
= "integer operand out of range";
9254 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9255 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9257 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9260 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9261 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9262 | (((value
>> 0) & 0xfffff) << 13));
9265 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9268 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9270 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9271 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9272 md_number_to_chars (fixpos
+ 0, t0
, 8);
9273 md_number_to_chars (fixpos
+ 8, t1
, 8);
9276 /* Attempt to simplify or even eliminate a fixup. The return value is
9277 ignored; perhaps it was once meaningful, but now it is historical.
9278 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9280 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9283 md_apply_fix3 (fix
, valuep
, seg
)
9289 valueT value
= *valuep
;
9292 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9296 switch (fix
->fx_r_type
)
9298 case BFD_RELOC_IA64_DIR32MSB
:
9299 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9303 case BFD_RELOC_IA64_DIR32LSB
:
9304 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9308 case BFD_RELOC_IA64_DIR64MSB
:
9309 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9313 case BFD_RELOC_IA64_DIR64LSB
:
9314 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9324 switch (fix
->fx_r_type
)
9327 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9328 "%s must have a constant value",
9329 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9336 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9337 work. There should be a better way to handle this. */
9339 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9341 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9343 if (fix
->tc_fix_data
.bigendian
)
9344 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9346 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9352 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9359 /* Generate the BFD reloc to be stuck in the object file from the
9360 fixup used internally in the assembler. */
9363 tc_gen_reloc (sec
, fixp
)
9369 reloc
= xmalloc (sizeof (*reloc
));
9370 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9371 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9372 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9373 reloc
->addend
= fixp
->fx_offset
;
9374 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9378 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9379 "Cannot represent %s relocation in object file",
9380 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9385 /* Turn a string in input_line_pointer into a floating point constant
9386 of type TYPE, and store the appropriate bytes in *LIT. The number
9387 of LITTLENUMS emitted is stored in *SIZE. An error message is
9388 returned, or NULL on OK. */
9390 #define MAX_LITTLENUMS 5
9393 md_atof (type
, lit
, size
)
9398 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9399 LITTLENUM_TYPE
*word
;
9429 return "Bad call to MD_ATOF()";
9431 t
= atof_ieee (input_line_pointer
, type
, words
);
9433 input_line_pointer
= t
;
9434 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9436 for (word
= words
+ prec
- 1; prec
--;)
9438 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9439 lit
+= sizeof (LITTLENUM_TYPE
);
9444 /* Round up a section's size to the appropriate boundary. */
9446 md_section_align (seg
, size
)
9450 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9451 valueT mask
= ((valueT
) 1 << align
) - 1;
9453 return (size
+ mask
) & ~mask
;
9456 /* Handle ia64 specific semantics of the align directive. */
9459 ia64_md_do_align (n
, fill
, len
, max
)
9465 /* Fill any pending bundle with nops. */
9466 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
9467 ia64_flush_insns ();
9469 /* When we align code in a text section, emit a bundle of 3 nops instead of
9470 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9471 N is log base 2 of the requested alignment. */
9473 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
9476 /* Use mfi bundle of nops with no stop bits. */
9477 static const unsigned char be_nop
[]
9478 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9479 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9480 static const unsigned char le_nop
[]
9481 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9482 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9484 /* Make sure we are on a 16-byte boundary, in case someone has been
9485 putting data into a text section. */
9486 frag_align (4, 0, 0);
9488 if (target_big_endian
)
9489 frag_align_pattern (n
, be_nop
, 16, max
);
9491 frag_align_pattern (n
, le_nop
, 16, max
);