1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS
= 0,
68 SPECIAL_SECTION_SDATA
,
69 SPECIAL_SECTION_RODATA
,
70 SPECIAL_SECTION_COMMENT
,
71 SPECIAL_SECTION_UNWIND
,
72 SPECIAL_SECTION_UNWIND_INFO
,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY
,
75 SPECIAL_SECTION_FINI_ARRAY
,
92 FUNC_LT_FPTR_RELATIVE
,
102 REG_FR
= (REG_GR
+ 128),
103 REG_AR
= (REG_FR
+ 128),
104 REG_CR
= (REG_AR
+ 128),
105 REG_P
= (REG_CR
+ 128),
106 REG_BR
= (REG_P
+ 64),
107 REG_IP
= (REG_BR
+ 8),
114 /* The following are pseudo-registers for use by gas only. */
126 /* The following pseudo-registers are used for unwind directives only: */
134 DYNREG_GR
= 0, /* dynamic general purpose register */
135 DYNREG_FR
, /* dynamic floating point register */
136 DYNREG_PR
, /* dynamic predicate register */
140 enum operand_match_result
143 OPERAND_OUT_OF_RANGE
,
147 /* On the ia64, we can't know the address of a text label until the
148 instructions are packed into a bundle. To handle this, we keep
149 track of the list of labels that appear in front of each
153 struct label_fix
*next
;
157 extern int target_big_endian
;
159 void (*ia64_number_to_chars
) PARAMS ((char *, valueT
, int));
161 static void ia64_float_to_chars_bigendian
162 PARAMS ((char *, LITTLENUM_TYPE
*, int));
163 static void ia64_float_to_chars_littleendian
164 PARAMS ((char *, LITTLENUM_TYPE
*, int));
165 static void (*ia64_float_to_chars
)
166 PARAMS ((char *, LITTLENUM_TYPE
*, int));
168 /* Characters which always start a comment. */
169 const char comment_chars
[] = "";
171 /* Characters which start a comment at the beginning of a line. */
172 const char line_comment_chars
[] = "#";
174 /* Characters which may be used to separate multiple commands on a
176 const char line_separator_chars
[] = ";";
178 /* Characters which are used to indicate an exponent in a floating
180 const char EXP_CHARS
[] = "eE";
182 /* Characters which mean that a number is a floating point constant,
184 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
186 /* ia64-specific option processing: */
188 const char *md_shortopts
= "m:N:x::";
190 struct option md_longopts
[] =
192 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
193 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
194 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
195 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
198 size_t md_longopts_size
= sizeof (md_longopts
);
202 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
203 struct hash_control
*reg_hash
; /* register name hash table */
204 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
205 struct hash_control
*const_hash
; /* constant hash table */
206 struct hash_control
*entry_hash
; /* code entry hint hash table */
208 symbolS
*regsym
[REG_NUM
];
210 /* If X_op is != O_absent, the registername for the instruction's
211 qualifying predicate. If NULL, p0 is assumed for instructions
212 that are predicatable. */
219 explicit_mode
: 1, /* which mode we're in */
220 default_explicit_mode
: 1, /* which mode is the default */
221 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
223 keep_pending_output
: 1;
225 /* Each bundle consists of up to three instructions. We keep
226 track of four most recent instructions so we can correctly set
227 the end_of_insn_group for the last instruction in a bundle. */
229 int num_slots_in_use
;
233 end_of_insn_group
: 1,
234 manual_bundling_on
: 1,
235 manual_bundling_off
: 1;
236 signed char user_template
; /* user-selected template, if any */
237 unsigned char qp_regno
; /* qualifying predicate */
238 /* This duplicates a good fraction of "struct fix" but we
239 can't use a "struct fix" instead since we can't call
240 fix_new_exp() until we know the address of the instruction. */
244 bfd_reloc_code_real_type code
;
245 enum ia64_opnd opnd
; /* type of operand in need of fix */
246 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
247 expressionS expr
; /* the value to be inserted */
249 fixup
[2]; /* at most two fixups per insn */
250 struct ia64_opcode
*idesc
;
251 struct label_fix
*label_fixups
;
252 struct label_fix
*tag_fixups
;
253 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
256 unsigned int src_line
;
257 struct dwarf2_line_info debug_line
;
265 struct dynreg
*next
; /* next dynamic register */
267 unsigned short base
; /* the base register number */
268 unsigned short num_regs
; /* # of registers in this set */
270 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
272 flagword flags
; /* ELF-header flags */
275 unsigned hint
:1; /* is this hint currently valid? */
276 bfd_vma offset
; /* mem.offset offset */
277 bfd_vma base
; /* mem.offset base */
280 int path
; /* number of alt. entry points seen */
281 const char **entry_labels
; /* labels of all alternate paths in
282 the current DV-checking block. */
283 int maxpaths
; /* size currently allocated for
285 /* Support for hardware errata workarounds. */
287 /* Record data about the last three insn groups. */
290 /* B-step workaround.
291 For each predicate register, this is set if the corresponding insn
292 group conditionally sets this register with one of the affected
295 /* B-step workaround.
296 For each general register, this is set if the corresponding insn
297 a) is conditional one one of the predicate registers for which
298 P_REG_SET is 1 in the corresponding entry of the previous group,
299 b) sets this general register with one of the affected
301 int g_reg_set_conditionally
[128];
305 int pointer_size
; /* size in bytes of a pointer */
306 int pointer_size_shift
; /* shift size of a pointer for alignment */
310 /* application registers: */
316 #define AR_BSPSTORE 18
331 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
332 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
333 {"ar.rsc", 16}, {"ar.bsp", 17},
334 {"ar.bspstore", 18}, {"ar.rnat", 19},
335 {"ar.fcr", 21}, {"ar.eflag", 24},
336 {"ar.csd", 25}, {"ar.ssd", 26},
337 {"ar.cflg", 27}, {"ar.fsr", 28},
338 {"ar.fir", 29}, {"ar.fdr", 30},
339 {"ar.ccv", 32}, {"ar.unat", 36},
340 {"ar.fpsr", 40}, {"ar.itc", 44},
341 {"ar.pfs", 64}, {"ar.lc", 65},
362 /* control registers: */
404 static const struct const_desc
411 /* PSR constant masks: */
414 {"psr.be", ((valueT
) 1) << 1},
415 {"psr.up", ((valueT
) 1) << 2},
416 {"psr.ac", ((valueT
) 1) << 3},
417 {"psr.mfl", ((valueT
) 1) << 4},
418 {"psr.mfh", ((valueT
) 1) << 5},
420 {"psr.ic", ((valueT
) 1) << 13},
421 {"psr.i", ((valueT
) 1) << 14},
422 {"psr.pk", ((valueT
) 1) << 15},
424 {"psr.dt", ((valueT
) 1) << 17},
425 {"psr.dfl", ((valueT
) 1) << 18},
426 {"psr.dfh", ((valueT
) 1) << 19},
427 {"psr.sp", ((valueT
) 1) << 20},
428 {"psr.pp", ((valueT
) 1) << 21},
429 {"psr.di", ((valueT
) 1) << 22},
430 {"psr.si", ((valueT
) 1) << 23},
431 {"psr.db", ((valueT
) 1) << 24},
432 {"psr.lp", ((valueT
) 1) << 25},
433 {"psr.tb", ((valueT
) 1) << 26},
434 {"psr.rt", ((valueT
) 1) << 27},
435 /* 28-31: reserved */
436 /* 32-33: cpl (current privilege level) */
437 {"psr.is", ((valueT
) 1) << 34},
438 {"psr.mc", ((valueT
) 1) << 35},
439 {"psr.it", ((valueT
) 1) << 36},
440 {"psr.id", ((valueT
) 1) << 37},
441 {"psr.da", ((valueT
) 1) << 38},
442 {"psr.dd", ((valueT
) 1) << 39},
443 {"psr.ss", ((valueT
) 1) << 40},
444 /* 41-42: ri (restart instruction) */
445 {"psr.ed", ((valueT
) 1) << 43},
446 {"psr.bn", ((valueT
) 1) << 44},
449 /* indirect register-sets/memory: */
458 { "CPUID", IND_CPUID
},
459 { "cpuid", IND_CPUID
},
471 /* Pseudo functions used to indicate relocation types (these functions
472 start with an at sign (@). */
494 /* reloc pseudo functions (these must come first!): */
495 { "dtpmod", PSEUDO_FUNC_RELOC
, { 0 } },
496 { "dtprel", PSEUDO_FUNC_RELOC
, { 0 } },
497 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
498 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
499 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
500 { "ltoffx", PSEUDO_FUNC_RELOC
, { 0 } },
501 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
502 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
503 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
504 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
505 { "tprel", PSEUDO_FUNC_RELOC
, { 0 } },
506 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
507 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
508 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */
509 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */
510 { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */
511 { "iplt", PSEUDO_FUNC_RELOC
, { 0 } },
513 /* mbtype4 constants: */
514 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
515 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
516 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
517 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
518 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
520 /* fclass constants: */
521 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
522 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
523 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
524 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
525 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
526 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
527 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
528 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
529 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
531 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
533 /* hint constants: */
534 { "pause", PSEUDO_FUNC_CONST
, { 0x0 } },
536 /* unwind-related constants: */
537 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
538 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
539 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
541 /* unwind-related registers: */
542 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
545 /* 41-bit nop opcodes (one per unit): */
546 static const bfd_vma nop
[IA64_NUM_UNITS
] =
548 0x0000000000LL
, /* NIL => break 0 */
549 0x0008000000LL
, /* I-unit nop */
550 0x0008000000LL
, /* M-unit nop */
551 0x4000000000LL
, /* B-unit nop */
552 0x0008000000LL
, /* F-unit nop */
553 0x0008000000LL
, /* L-"unit" nop */
554 0x0008000000LL
, /* X-unit nop */
557 /* Can't be `const' as it's passed to input routines (which have the
558 habit of setting temporary sentinels. */
559 static char special_section_name
[][20] =
561 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
562 {".IA_64.unwind"}, {".IA_64.unwind_info"},
563 {".init_array"}, {".fini_array"}
566 static char *special_linkonce_name
[] =
568 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
571 /* The best template for a particular sequence of up to three
573 #define N IA64_NUM_TYPES
574 static unsigned char best_template
[N
][N
][N
];
577 /* Resource dependencies currently in effect */
579 int depind
; /* dependency index */
580 const struct ia64_dependency
*dependency
; /* actual dependency */
581 unsigned specific
:1, /* is this a specific bit/regno? */
582 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
583 int index
; /* specific regno/bit within dependency */
584 int note
; /* optional qualifying note (0 if none) */
588 int insn_srlz
; /* current insn serialization state */
589 int data_srlz
; /* current data serialization state */
590 int qp_regno
; /* qualifying predicate for this usage */
591 char *file
; /* what file marked this dependency */
592 unsigned int line
; /* what line marked this dependency */
593 struct mem_offset mem_offset
; /* optional memory offset hint */
594 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
595 int path
; /* corresponding code entry index */
597 static int regdepslen
= 0;
598 static int regdepstotlen
= 0;
599 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
600 static const char *dv_sem
[] = { "none", "implied", "impliedf",
601 "data", "instr", "specific", "stop", "other" };
602 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
604 /* Current state of PR mutexation */
605 static struct qpmutex
{
608 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
609 static int qp_mutexeslen
= 0;
610 static int qp_mutexestotlen
= 0;
611 static valueT qp_safe_across_calls
= 0;
613 /* Current state of PR implications */
614 static struct qp_imply
{
617 unsigned p2_branched
:1;
619 } *qp_implies
= NULL
;
620 static int qp_implieslen
= 0;
621 static int qp_impliestotlen
= 0;
623 /* Keep track of static GR values so that indirect register usage can
624 sometimes be tracked. */
629 } gr_values
[128] = {{ 1, 0, 0 }};
631 /* These are the routines required to output the various types of
634 /* A slot_number is a frag address plus the slot index (0-2). We use the
635 frag address here so that if there is a section switch in the middle of
636 a function, then instructions emitted to a different section are not
637 counted. Since there may be more than one frag for a function, this
638 means we also need to keep track of which frag this address belongs to
639 so we can compute inter-frag distances. This also nicely solves the
640 problem with nops emitted for align directives, which can't easily be
641 counted, but can easily be derived from frag sizes. */
643 typedef struct unw_rec_list
{
645 unsigned long slot_number
;
647 struct unw_rec_list
*next
;
650 #define SLOT_NUM_NOT_SET (unsigned)-1
652 /* Linked list of saved prologue counts. A very poor
653 implementation of a map from label numbers to prologue counts. */
654 typedef struct label_prologue_count
656 struct label_prologue_count
*next
;
657 unsigned long label_number
;
658 unsigned int prologue_count
;
659 } label_prologue_count
;
663 unsigned long next_slot_number
;
664 fragS
*next_slot_frag
;
666 /* Maintain a list of unwind entries for the current function. */
670 /* Any unwind entires that should be attached to the current slot
671 that an insn is being constructed for. */
672 unw_rec_list
*current_entry
;
674 /* These are used to create the unwind table entry for this function. */
677 symbolS
*info
; /* pointer to unwind info */
678 symbolS
*personality_routine
;
680 subsegT saved_text_subseg
;
681 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
683 /* TRUE if processing unwind directives in a prologue region. */
686 unsigned int prologue_count
; /* number of .prologues seen so far */
687 /* Prologue counts at previous .label_state directives. */
688 struct label_prologue_count
* saved_prologue_counts
;
691 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
693 /* Forward delarations: */
694 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
695 static void set_section
PARAMS ((char *name
));
696 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
697 unsigned int, unsigned int));
698 static void dot_radix
PARAMS ((int));
699 static void dot_special_section
PARAMS ((int));
700 static void dot_proc
PARAMS ((int));
701 static void dot_fframe
PARAMS ((int));
702 static void dot_vframe
PARAMS ((int));
703 static void dot_vframesp
PARAMS ((int));
704 static void dot_vframepsp
PARAMS ((int));
705 static void dot_save
PARAMS ((int));
706 static void dot_restore
PARAMS ((int));
707 static void dot_restorereg
PARAMS ((int));
708 static void dot_restorereg_p
PARAMS ((int));
709 static void dot_handlerdata
PARAMS ((int));
710 static void dot_unwentry
PARAMS ((int));
711 static void dot_altrp
PARAMS ((int));
712 static void dot_savemem
PARAMS ((int));
713 static void dot_saveg
PARAMS ((int));
714 static void dot_savef
PARAMS ((int));
715 static void dot_saveb
PARAMS ((int));
716 static void dot_savegf
PARAMS ((int));
717 static void dot_spill
PARAMS ((int));
718 static void dot_spillreg
PARAMS ((int));
719 static void dot_spillmem
PARAMS ((int));
720 static void dot_spillreg_p
PARAMS ((int));
721 static void dot_spillmem_p
PARAMS ((int));
722 static void dot_label_state
PARAMS ((int));
723 static void dot_copy_state
PARAMS ((int));
724 static void dot_unwabi
PARAMS ((int));
725 static void dot_personality
PARAMS ((int));
726 static void dot_body
PARAMS ((int));
727 static void dot_prologue
PARAMS ((int));
728 static void dot_endp
PARAMS ((int));
729 static void dot_template
PARAMS ((int));
730 static void dot_regstk
PARAMS ((int));
731 static void dot_rot
PARAMS ((int));
732 static void dot_byteorder
PARAMS ((int));
733 static void dot_psr
PARAMS ((int));
734 static void dot_alias
PARAMS ((int));
735 static void dot_ln
PARAMS ((int));
736 static char *parse_section_name
PARAMS ((void));
737 static void dot_xdata
PARAMS ((int));
738 static void stmt_float_cons
PARAMS ((int));
739 static void stmt_cons_ua
PARAMS ((int));
740 static void dot_xfloat_cons
PARAMS ((int));
741 static void dot_xstringer
PARAMS ((int));
742 static void dot_xdata_ua
PARAMS ((int));
743 static void dot_xfloat_cons_ua
PARAMS ((int));
744 static void print_prmask
PARAMS ((valueT mask
));
745 static void dot_pred_rel
PARAMS ((int));
746 static void dot_reg_val
PARAMS ((int));
747 static void dot_dv_mode
PARAMS ((int));
748 static void dot_entry
PARAMS ((int));
749 static void dot_mem_offset
PARAMS ((int));
750 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
751 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
752 static void declare_register_set
PARAMS ((const char *, int, int));
753 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
754 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
757 static int parse_operand
PARAMS ((expressionS
*e
));
758 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
759 static int errata_nop_necessary_p
PARAMS ((struct slot
*, enum ia64_unit
));
760 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
761 static void emit_one_bundle
PARAMS ((void));
762 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
763 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
764 bfd_reloc_code_real_type r_type
));
765 static void insn_group_break
PARAMS ((int, int, int));
766 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
767 struct rsrc
*, int depind
, int path
));
768 static void add_qp_mutex
PARAMS((valueT mask
));
769 static void add_qp_imply
PARAMS((int p1
, int p2
));
770 static void clear_qp_branch_flag
PARAMS((valueT mask
));
771 static void clear_qp_mutex
PARAMS((valueT mask
));
772 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
773 static int has_suffix_p
PARAMS((const char *, const char *));
774 static void clear_register_values
PARAMS ((void));
775 static void print_dependency
PARAMS ((const char *action
, int depind
));
776 static void instruction_serialization
PARAMS ((void));
777 static void data_serialization
PARAMS ((void));
778 static void remove_marked_resource
PARAMS ((struct rsrc
*));
779 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
780 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
781 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
782 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
783 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
784 struct ia64_opcode
*, int, struct rsrc
[], int, int));
785 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
786 static void check_dependencies
PARAMS((struct ia64_opcode
*));
787 static void mark_resources
PARAMS((struct ia64_opcode
*));
788 static void update_dependencies
PARAMS((struct ia64_opcode
*));
789 static void note_register_values
PARAMS((struct ia64_opcode
*));
790 static int qp_mutex
PARAMS ((int, int, int));
791 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
792 static void output_vbyte_mem
PARAMS ((int, char *, char *));
793 static void count_output
PARAMS ((int, char *, char *));
794 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
795 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
796 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
797 static void output_P1_format
PARAMS ((vbyte_func
, int));
798 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
799 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
800 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
801 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
802 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
803 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
804 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
805 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
806 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
807 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
808 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
809 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
810 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
811 static char format_ab_reg
PARAMS ((int, int));
812 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
814 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
815 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
817 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
818 static void free_list_records
PARAMS ((unw_rec_list
*));
819 static unw_rec_list
*output_prologue
PARAMS ((void));
820 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
821 static unw_rec_list
*output_body
PARAMS ((void));
822 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
823 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
824 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
825 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
826 static unw_rec_list
*output_rp_when
PARAMS ((void));
827 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
828 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
829 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
830 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
831 static unw_rec_list
*output_pfs_when
PARAMS ((void));
832 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
833 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
834 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
835 static unw_rec_list
*output_preds_when
PARAMS ((void));
836 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
837 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
838 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
839 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
840 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
841 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
842 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
843 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
844 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
845 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
846 static unw_rec_list
*output_unat_when
PARAMS ((void));
847 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
848 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
849 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
850 static unw_rec_list
*output_lc_when
PARAMS ((void));
851 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
852 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
853 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
854 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
855 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
856 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
857 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
858 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
859 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
860 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
861 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
862 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
863 static unw_rec_list
*output_bsp_when
PARAMS ((void));
864 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
865 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
866 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
867 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
868 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
869 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
870 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
871 static unw_rec_list
*output_rnat_when
PARAMS ((void));
872 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
873 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
874 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
875 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
876 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
877 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
878 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
879 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
880 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
881 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
883 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
885 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
887 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
888 unsigned int, unsigned int));
889 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
890 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
891 static int calc_record_size
PARAMS ((unw_rec_list
*));
892 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
893 static int count_bits
PARAMS ((unsigned long));
894 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
895 unsigned long, fragS
*));
896 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
897 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
898 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
899 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
900 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
901 static int generate_unwind_image
PARAMS ((const char *));
902 static unsigned int get_saved_prologue_count
PARAMS ((unsigned long));
903 static void save_prologue_count
PARAMS ((unsigned long, unsigned int));
904 static void free_saved_prologue_counts
PARAMS ((void));
906 /* Build the unwind section name by appending the (possibly stripped)
907 text section NAME to the unwind PREFIX. The resulting string
908 pointer is assigned to RESULT. The string is allocated on the
909 stack, so this must be a macro... */
910 #define make_unw_section_name(special, text_name, result) \
912 const char *_prefix = special_section_name[special]; \
913 const char *_suffix = text_name; \
914 size_t _prefix_len, _suffix_len; \
916 if (strncmp (text_name, ".gnu.linkonce.t.", \
917 sizeof (".gnu.linkonce.t.") - 1) == 0) \
919 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
920 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
922 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
923 _result = alloca (_prefix_len + _suffix_len + 1); \
924 memcpy (_result, _prefix, _prefix_len); \
925 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
926 _result[_prefix_len + _suffix_len] = '\0'; \
931 /* Determine if application register REGNUM resides in the integer
932 unit (as opposed to the memory unit). */
934 ar_is_in_integer_unit (reg
)
939 return (reg
== 64 /* pfs */
940 || reg
== 65 /* lc */
941 || reg
== 66 /* ec */
942 /* ??? ias accepts and puts these in the integer unit. */
943 || (reg
>= 112 && reg
<= 127));
946 /* Switch to section NAME and create section if necessary. It's
947 rather ugly that we have to manipulate input_line_pointer but I
948 don't see any other way to accomplish the same thing without
949 changing obj-elf.c (which may be the Right Thing, in the end). */
954 char *saved_input_line_pointer
;
956 saved_input_line_pointer
= input_line_pointer
;
957 input_line_pointer
= name
;
959 input_line_pointer
= saved_input_line_pointer
;
962 /* Map 's' to SHF_IA_64_SHORT. */
965 ia64_elf_section_letter (letter
, ptr_msg
)
970 return SHF_IA_64_SHORT
;
971 else if (letter
== 'o')
972 return SHF_LINK_ORDER
;
974 *ptr_msg
= _("Bad .section directive: want a,o,s,w,x,M,S,G,T in string");
978 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
981 ia64_elf_section_flags (flags
, attr
, type
)
983 int attr
, type ATTRIBUTE_UNUSED
;
985 if (attr
& SHF_IA_64_SHORT
)
986 flags
|= SEC_SMALL_DATA
;
991 ia64_elf_section_type (str
, len
)
995 #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
997 if (STREQ (ELF_STRING_ia64_unwind_info
))
1000 if (STREQ (ELF_STRING_ia64_unwind_info_once
))
1001 return SHT_PROGBITS
;
1003 if (STREQ (ELF_STRING_ia64_unwind
))
1004 return SHT_IA_64_UNWIND
;
1006 if (STREQ (ELF_STRING_ia64_unwind_once
))
1007 return SHT_IA_64_UNWIND
;
1009 if (STREQ ("unwind"))
1010 return SHT_IA_64_UNWIND
;
1012 if (STREQ ("init_array"))
1013 return SHT_INIT_ARRAY
;
1015 if (STREQ ("fini_array"))
1016 return SHT_FINI_ARRAY
;
1023 set_regstack (ins
, locs
, outs
, rots
)
1024 unsigned int ins
, locs
, outs
, rots
;
1026 /* Size of frame. */
1029 sof
= ins
+ locs
+ outs
;
1032 as_bad ("Size of frame exceeds maximum of 96 registers");
1037 as_warn ("Size of rotating registers exceeds frame size");
1040 md
.in
.base
= REG_GR
+ 32;
1041 md
.loc
.base
= md
.in
.base
+ ins
;
1042 md
.out
.base
= md
.loc
.base
+ locs
;
1044 md
.in
.num_regs
= ins
;
1045 md
.loc
.num_regs
= locs
;
1046 md
.out
.num_regs
= outs
;
1047 md
.rot
.num_regs
= rots
;
1054 struct label_fix
*lfix
;
1056 subsegT saved_subseg
;
1059 if (!md
.last_text_seg
)
1062 saved_seg
= now_seg
;
1063 saved_subseg
= now_subseg
;
1065 subseg_set (md
.last_text_seg
, 0);
1067 while (md
.num_slots_in_use
> 0)
1068 emit_one_bundle (); /* force out queued instructions */
1070 /* In case there are labels following the last instruction, resolve
1072 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1074 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1075 symbol_set_frag (lfix
->sym
, frag_now
);
1077 CURR_SLOT
.label_fixups
= 0;
1078 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1080 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1081 symbol_set_frag (lfix
->sym
, frag_now
);
1083 CURR_SLOT
.tag_fixups
= 0;
1085 /* In case there are unwind directives following the last instruction,
1086 resolve those now. We only handle body and prologue directives here.
1087 Give an error for others. */
1088 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1090 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1091 || ptr
->r
.type
== body
)
1093 ptr
->slot_number
= (unsigned long) frag_more (0);
1094 ptr
->slot_frag
= frag_now
;
1097 as_bad (_("Unwind directive not followed by an instruction."));
1099 unwind
.current_entry
= NULL
;
1101 subseg_set (saved_seg
, saved_subseg
);
1103 if (md
.qp
.X_op
== O_register
)
1104 as_bad ("qualifying predicate not followed by instruction");
1108 ia64_do_align (nbytes
)
1111 char *saved_input_line_pointer
= input_line_pointer
;
1113 input_line_pointer
= "";
1114 s_align_bytes (nbytes
);
1115 input_line_pointer
= saved_input_line_pointer
;
1119 ia64_cons_align (nbytes
)
1124 char *saved_input_line_pointer
= input_line_pointer
;
1125 input_line_pointer
= "";
1126 s_align_bytes (nbytes
);
1127 input_line_pointer
= saved_input_line_pointer
;
1131 /* Output COUNT bytes to a memory location. */
1132 static unsigned char *vbyte_mem_ptr
= NULL
;
1135 output_vbyte_mem (count
, ptr
, comment
)
1138 char *comment ATTRIBUTE_UNUSED
;
1141 if (vbyte_mem_ptr
== NULL
)
1146 for (x
= 0; x
< count
; x
++)
1147 *(vbyte_mem_ptr
++) = ptr
[x
];
1150 /* Count the number of bytes required for records. */
1151 static int vbyte_count
= 0;
1153 count_output (count
, ptr
, comment
)
1155 char *ptr ATTRIBUTE_UNUSED
;
1156 char *comment ATTRIBUTE_UNUSED
;
1158 vbyte_count
+= count
;
1162 output_R1_format (f
, rtype
, rlen
)
1164 unw_record_type rtype
;
1171 output_R3_format (f
, rtype
, rlen
);
1177 else if (rtype
!= prologue
)
1178 as_bad ("record type is not valid");
1180 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1181 (*f
) (1, &byte
, NULL
);
1185 output_R2_format (f
, mask
, grsave
, rlen
)
1192 mask
= (mask
& 0x0f);
1193 grsave
= (grsave
& 0x7f);
1195 bytes
[0] = (UNW_R2
| (mask
>> 1));
1196 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1197 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1198 (*f
) (count
, bytes
, NULL
);
1202 output_R3_format (f
, rtype
, rlen
)
1204 unw_record_type rtype
;
1211 output_R1_format (f
, rtype
, rlen
);
1217 else if (rtype
!= prologue
)
1218 as_bad ("record type is not valid");
1219 bytes
[0] = (UNW_R3
| r
);
1220 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1221 (*f
) (count
+ 1, bytes
, NULL
);
1225 output_P1_format (f
, brmask
)
1230 byte
= UNW_P1
| (brmask
& 0x1f);
1231 (*f
) (1, &byte
, NULL
);
1235 output_P2_format (f
, brmask
, gr
)
1241 brmask
= (brmask
& 0x1f);
1242 bytes
[0] = UNW_P2
| (brmask
>> 1);
1243 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1244 (*f
) (2, bytes
, NULL
);
1248 output_P3_format (f
, rtype
, reg
)
1250 unw_record_type rtype
;
1295 as_bad ("Invalid record type for P3 format.");
1297 bytes
[0] = (UNW_P3
| (r
>> 1));
1298 bytes
[1] = (((r
& 1) << 7) | reg
);
1299 (*f
) (2, bytes
, NULL
);
1303 output_P4_format (f
, imask
, imask_size
)
1305 unsigned char *imask
;
1306 unsigned long imask_size
;
1309 (*f
) (imask_size
, imask
, NULL
);
1313 output_P5_format (f
, grmask
, frmask
)
1316 unsigned long frmask
;
1319 grmask
= (grmask
& 0x0f);
1322 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1323 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1324 bytes
[3] = (frmask
& 0x000000ff);
1325 (*f
) (4, bytes
, NULL
);
1329 output_P6_format (f
, rtype
, rmask
)
1331 unw_record_type rtype
;
1337 if (rtype
== gr_mem
)
1339 else if (rtype
!= fr_mem
)
1340 as_bad ("Invalid record type for format P6");
1341 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1342 (*f
) (1, &byte
, NULL
);
1346 output_P7_format (f
, rtype
, w1
, w2
)
1348 unw_record_type rtype
;
1355 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1360 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1410 bytes
[0] = (UNW_P7
| r
);
1411 (*f
) (count
, bytes
, NULL
);
1415 output_P8_format (f
, rtype
, t
)
1417 unw_record_type rtype
;
1456 case bspstore_psprel
:
1459 case bspstore_sprel
:
1471 case priunat_when_gr
:
1474 case priunat_psprel
:
1480 case priunat_when_mem
:
1487 count
+= output_leb128 (bytes
+ 2, t
, 0);
1488 (*f
) (count
, bytes
, NULL
);
1492 output_P9_format (f
, grmask
, gr
)
1499 bytes
[1] = (grmask
& 0x0f);
1500 bytes
[2] = (gr
& 0x7f);
1501 (*f
) (3, bytes
, NULL
);
1505 output_P10_format (f
, abi
, context
)
1512 bytes
[1] = (abi
& 0xff);
1513 bytes
[2] = (context
& 0xff);
1514 (*f
) (3, bytes
, NULL
);
1518 output_B1_format (f
, rtype
, label
)
1520 unw_record_type rtype
;
1521 unsigned long label
;
1527 output_B4_format (f
, rtype
, label
);
1530 if (rtype
== copy_state
)
1532 else if (rtype
!= label_state
)
1533 as_bad ("Invalid record type for format B1");
1535 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1536 (*f
) (1, &byte
, NULL
);
1540 output_B2_format (f
, ecount
, t
)
1542 unsigned long ecount
;
1549 output_B3_format (f
, ecount
, t
);
1552 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1553 count
+= output_leb128 (bytes
+ 1, t
, 0);
1554 (*f
) (count
, bytes
, NULL
);
1558 output_B3_format (f
, ecount
, t
)
1560 unsigned long ecount
;
1567 output_B2_format (f
, ecount
, t
);
1571 count
+= output_leb128 (bytes
+ 1, t
, 0);
1572 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1573 (*f
) (count
, bytes
, NULL
);
1577 output_B4_format (f
, rtype
, label
)
1579 unw_record_type rtype
;
1580 unsigned long label
;
1587 output_B1_format (f
, rtype
, label
);
1591 if (rtype
== copy_state
)
1593 else if (rtype
!= label_state
)
1594 as_bad ("Invalid record type for format B1");
1596 bytes
[0] = (UNW_B4
| (r
<< 3));
1597 count
+= output_leb128 (bytes
+ 1, label
, 0);
1598 (*f
) (count
, bytes
, NULL
);
1602 format_ab_reg (ab
, reg
)
1609 ret
= (ab
<< 5) | reg
;
1614 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1616 unw_record_type rtype
;
1626 if (rtype
== spill_sprel
)
1628 else if (rtype
!= spill_psprel
)
1629 as_bad ("Invalid record type for format X1");
1630 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1631 count
+= output_leb128 (bytes
+ 2, t
, 0);
1632 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1633 (*f
) (count
, bytes
, NULL
);
1637 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1646 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1647 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1648 count
+= output_leb128 (bytes
+ 3, t
, 0);
1649 (*f
) (count
, bytes
, NULL
);
1653 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1655 unw_record_type rtype
;
1666 if (rtype
== spill_sprel_p
)
1668 else if (rtype
!= spill_psprel_p
)
1669 as_bad ("Invalid record type for format X3");
1670 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1671 bytes
[2] = format_ab_reg (ab
, reg
);
1672 count
+= output_leb128 (bytes
+ 3, t
, 0);
1673 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1674 (*f
) (count
, bytes
, NULL
);
1678 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1688 bytes
[1] = (qp
& 0x3f);
1689 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1690 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1691 count
+= output_leb128 (bytes
+ 4, t
, 0);
1692 (*f
) (count
, bytes
, NULL
);
1695 /* This function allocates a record list structure, and initializes fields. */
1697 static unw_rec_list
*
1698 alloc_record (unw_record_type t
)
1701 ptr
= xmalloc (sizeof (*ptr
));
1703 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1708 /* This function frees an entire list of record structures. */
1711 free_list_records (unw_rec_list
*first
)
1714 for (ptr
= first
; ptr
!= NULL
;)
1716 unw_rec_list
*tmp
= ptr
;
1718 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1719 && tmp
->r
.record
.r
.mask
.i
)
1720 free (tmp
->r
.record
.r
.mask
.i
);
1727 static unw_rec_list
*
1730 unw_rec_list
*ptr
= alloc_record (prologue
);
1731 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1735 static unw_rec_list
*
1736 output_prologue_gr (saved_mask
, reg
)
1737 unsigned int saved_mask
;
1740 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1741 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1742 ptr
->r
.record
.r
.grmask
= saved_mask
;
1743 ptr
->r
.record
.r
.grsave
= reg
;
1747 static unw_rec_list
*
1750 unw_rec_list
*ptr
= alloc_record (body
);
1754 static unw_rec_list
*
1755 output_mem_stack_f (size
)
1758 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1759 ptr
->r
.record
.p
.size
= size
;
1763 static unw_rec_list
*
1764 output_mem_stack_v ()
1766 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1770 static unw_rec_list
*
1774 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1775 ptr
->r
.record
.p
.gr
= gr
;
1779 static unw_rec_list
*
1780 output_psp_sprel (offset
)
1781 unsigned int offset
;
1783 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1784 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1788 static unw_rec_list
*
1791 unw_rec_list
*ptr
= alloc_record (rp_when
);
1795 static unw_rec_list
*
1799 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1800 ptr
->r
.record
.p
.gr
= gr
;
1804 static unw_rec_list
*
1808 unw_rec_list
*ptr
= alloc_record (rp_br
);
1809 ptr
->r
.record
.p
.br
= br
;
1813 static unw_rec_list
*
1814 output_rp_psprel (offset
)
1815 unsigned int offset
;
1817 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1818 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1822 static unw_rec_list
*
1823 output_rp_sprel (offset
)
1824 unsigned int offset
;
1826 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1827 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1831 static unw_rec_list
*
1834 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1838 static unw_rec_list
*
1842 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1843 ptr
->r
.record
.p
.gr
= gr
;
1847 static unw_rec_list
*
1848 output_pfs_psprel (offset
)
1849 unsigned int offset
;
1851 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1852 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1856 static unw_rec_list
*
1857 output_pfs_sprel (offset
)
1858 unsigned int offset
;
1860 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1861 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1865 static unw_rec_list
*
1866 output_preds_when ()
1868 unw_rec_list
*ptr
= alloc_record (preds_when
);
1872 static unw_rec_list
*
1873 output_preds_gr (gr
)
1876 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1877 ptr
->r
.record
.p
.gr
= gr
;
1881 static unw_rec_list
*
1882 output_preds_psprel (offset
)
1883 unsigned int offset
;
1885 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1886 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1890 static unw_rec_list
*
1891 output_preds_sprel (offset
)
1892 unsigned int offset
;
1894 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1895 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1899 static unw_rec_list
*
1900 output_fr_mem (mask
)
1903 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1904 ptr
->r
.record
.p
.rmask
= mask
;
1908 static unw_rec_list
*
1909 output_frgr_mem (gr_mask
, fr_mask
)
1910 unsigned int gr_mask
;
1911 unsigned int fr_mask
;
1913 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1914 ptr
->r
.record
.p
.grmask
= gr_mask
;
1915 ptr
->r
.record
.p
.frmask
= fr_mask
;
1919 static unw_rec_list
*
1920 output_gr_gr (mask
, reg
)
1924 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1925 ptr
->r
.record
.p
.grmask
= mask
;
1926 ptr
->r
.record
.p
.gr
= reg
;
1930 static unw_rec_list
*
1931 output_gr_mem (mask
)
1934 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1935 ptr
->r
.record
.p
.rmask
= mask
;
1939 static unw_rec_list
*
1940 output_br_mem (unsigned int mask
)
1942 unw_rec_list
*ptr
= alloc_record (br_mem
);
1943 ptr
->r
.record
.p
.brmask
= mask
;
1947 static unw_rec_list
*
1948 output_br_gr (save_mask
, reg
)
1949 unsigned int save_mask
;
1952 unw_rec_list
*ptr
= alloc_record (br_gr
);
1953 ptr
->r
.record
.p
.brmask
= save_mask
;
1954 ptr
->r
.record
.p
.gr
= reg
;
1958 static unw_rec_list
*
1959 output_spill_base (offset
)
1960 unsigned int offset
;
1962 unw_rec_list
*ptr
= alloc_record (spill_base
);
1963 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1967 static unw_rec_list
*
1970 unw_rec_list
*ptr
= alloc_record (unat_when
);
1974 static unw_rec_list
*
1978 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1979 ptr
->r
.record
.p
.gr
= gr
;
1983 static unw_rec_list
*
1984 output_unat_psprel (offset
)
1985 unsigned int offset
;
1987 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1988 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1992 static unw_rec_list
*
1993 output_unat_sprel (offset
)
1994 unsigned int offset
;
1996 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1997 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2001 static unw_rec_list
*
2004 unw_rec_list
*ptr
= alloc_record (lc_when
);
2008 static unw_rec_list
*
2012 unw_rec_list
*ptr
= alloc_record (lc_gr
);
2013 ptr
->r
.record
.p
.gr
= gr
;
2017 static unw_rec_list
*
2018 output_lc_psprel (offset
)
2019 unsigned int offset
;
2021 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
2022 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2026 static unw_rec_list
*
2027 output_lc_sprel (offset
)
2028 unsigned int offset
;
2030 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
2031 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2035 static unw_rec_list
*
2038 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
2042 static unw_rec_list
*
2046 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
2047 ptr
->r
.record
.p
.gr
= gr
;
2051 static unw_rec_list
*
2052 output_fpsr_psprel (offset
)
2053 unsigned int offset
;
2055 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
2056 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2060 static unw_rec_list
*
2061 output_fpsr_sprel (offset
)
2062 unsigned int offset
;
2064 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
2065 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2069 static unw_rec_list
*
2070 output_priunat_when_gr ()
2072 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2076 static unw_rec_list
*
2077 output_priunat_when_mem ()
2079 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2083 static unw_rec_list
*
2084 output_priunat_gr (gr
)
2087 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2088 ptr
->r
.record
.p
.gr
= gr
;
2092 static unw_rec_list
*
2093 output_priunat_psprel (offset
)
2094 unsigned int offset
;
2096 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2097 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2101 static unw_rec_list
*
2102 output_priunat_sprel (offset
)
2103 unsigned int offset
;
2105 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2106 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2110 static unw_rec_list
*
2113 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2117 static unw_rec_list
*
2121 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2122 ptr
->r
.record
.p
.gr
= gr
;
2126 static unw_rec_list
*
2127 output_bsp_psprel (offset
)
2128 unsigned int offset
;
2130 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2131 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2135 static unw_rec_list
*
2136 output_bsp_sprel (offset
)
2137 unsigned int offset
;
2139 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2140 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2144 static unw_rec_list
*
2145 output_bspstore_when ()
2147 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2151 static unw_rec_list
*
2152 output_bspstore_gr (gr
)
2155 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2156 ptr
->r
.record
.p
.gr
= gr
;
2160 static unw_rec_list
*
2161 output_bspstore_psprel (offset
)
2162 unsigned int offset
;
2164 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2165 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2169 static unw_rec_list
*
2170 output_bspstore_sprel (offset
)
2171 unsigned int offset
;
2173 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2174 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2178 static unw_rec_list
*
2181 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2185 static unw_rec_list
*
2189 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2190 ptr
->r
.record
.p
.gr
= gr
;
2194 static unw_rec_list
*
2195 output_rnat_psprel (offset
)
2196 unsigned int offset
;
2198 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2199 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2203 static unw_rec_list
*
2204 output_rnat_sprel (offset
)
2205 unsigned int offset
;
2207 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2208 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2212 static unw_rec_list
*
2213 output_unwabi (abi
, context
)
2215 unsigned long context
;
2217 unw_rec_list
*ptr
= alloc_record (unwabi
);
2218 ptr
->r
.record
.p
.abi
= abi
;
2219 ptr
->r
.record
.p
.context
= context
;
2223 static unw_rec_list
*
2224 output_epilogue (unsigned long ecount
)
2226 unw_rec_list
*ptr
= alloc_record (epilogue
);
2227 ptr
->r
.record
.b
.ecount
= ecount
;
2231 static unw_rec_list
*
2232 output_label_state (unsigned long label
)
2234 unw_rec_list
*ptr
= alloc_record (label_state
);
2235 ptr
->r
.record
.b
.label
= label
;
2239 static unw_rec_list
*
2240 output_copy_state (unsigned long label
)
2242 unw_rec_list
*ptr
= alloc_record (copy_state
);
2243 ptr
->r
.record
.b
.label
= label
;
2247 static unw_rec_list
*
2248 output_spill_psprel (ab
, reg
, offset
)
2251 unsigned int offset
;
2253 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2254 ptr
->r
.record
.x
.ab
= ab
;
2255 ptr
->r
.record
.x
.reg
= reg
;
2256 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2260 static unw_rec_list
*
2261 output_spill_sprel (ab
, reg
, offset
)
2264 unsigned int offset
;
2266 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2267 ptr
->r
.record
.x
.ab
= ab
;
2268 ptr
->r
.record
.x
.reg
= reg
;
2269 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2273 static unw_rec_list
*
2274 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2277 unsigned int offset
;
2278 unsigned int predicate
;
2280 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2281 ptr
->r
.record
.x
.ab
= ab
;
2282 ptr
->r
.record
.x
.reg
= reg
;
2283 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2284 ptr
->r
.record
.x
.qp
= predicate
;
2288 static unw_rec_list
*
2289 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2292 unsigned int offset
;
2293 unsigned int predicate
;
2295 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2296 ptr
->r
.record
.x
.ab
= ab
;
2297 ptr
->r
.record
.x
.reg
= reg
;
2298 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2299 ptr
->r
.record
.x
.qp
= predicate
;
2303 static unw_rec_list
*
2304 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2307 unsigned int targ_reg
;
2310 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2311 ptr
->r
.record
.x
.ab
= ab
;
2312 ptr
->r
.record
.x
.reg
= reg
;
2313 ptr
->r
.record
.x
.treg
= targ_reg
;
2314 ptr
->r
.record
.x
.xy
= xy
;
2318 static unw_rec_list
*
2319 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2322 unsigned int targ_reg
;
2324 unsigned int predicate
;
2326 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2327 ptr
->r
.record
.x
.ab
= ab
;
2328 ptr
->r
.record
.x
.reg
= reg
;
2329 ptr
->r
.record
.x
.treg
= targ_reg
;
2330 ptr
->r
.record
.x
.xy
= xy
;
2331 ptr
->r
.record
.x
.qp
= predicate
;
2335 /* Given a unw_rec_list process the correct format with the
2336 specified function. */
2339 process_one_record (ptr
, f
)
2343 unsigned long fr_mask
, gr_mask
;
2345 switch (ptr
->r
.type
)
2351 /* These are taken care of by prologue/prologue_gr. */
2356 if (ptr
->r
.type
== prologue_gr
)
2357 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2358 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2360 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2362 /* Output descriptor(s) for union of register spills (if any). */
2363 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2364 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2367 if ((fr_mask
& ~0xfUL
) == 0)
2368 output_P6_format (f
, fr_mem
, fr_mask
);
2371 output_P5_format (f
, gr_mask
, fr_mask
);
2376 output_P6_format (f
, gr_mem
, gr_mask
);
2377 if (ptr
->r
.record
.r
.mask
.br_mem
)
2378 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2380 /* output imask descriptor if necessary: */
2381 if (ptr
->r
.record
.r
.mask
.i
)
2382 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2383 ptr
->r
.record
.r
.imask_size
);
2387 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2391 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2392 ptr
->r
.record
.p
.size
);
2405 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2408 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2411 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2419 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2428 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2438 case bspstore_sprel
:
2440 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2443 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2446 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2449 as_bad ("spill_mask record unimplemented.");
2451 case priunat_when_gr
:
2452 case priunat_when_mem
:
2456 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2458 case priunat_psprel
:
2460 case bspstore_psprel
:
2462 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2465 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2468 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2472 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2475 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2476 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2477 ptr
->r
.record
.x
.pspoff
);
2480 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2481 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2482 ptr
->r
.record
.x
.spoff
);
2485 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2486 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2487 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2489 case spill_psprel_p
:
2490 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2491 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2492 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2495 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2496 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2497 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2500 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2501 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2502 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2506 as_bad ("record_type_not_valid");
2511 /* Given a unw_rec_list list, process all the records with
2512 the specified function. */
2514 process_unw_records (list
, f
)
2519 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2520 process_one_record (ptr
, f
);
2523 /* Determine the size of a record list in bytes. */
2525 calc_record_size (list
)
2529 process_unw_records (list
, count_output
);
2533 /* Update IMASK bitmask to reflect the fact that one or more registers
2534 of type TYPE are saved starting at instruction with index T. If N
2535 bits are set in REGMASK, it is assumed that instructions T through
2536 T+N-1 save these registers.
2540 1: instruction saves next fp reg
2541 2: instruction saves next general reg
2542 3: instruction saves next branch reg */
2544 set_imask (region
, regmask
, t
, type
)
2545 unw_rec_list
*region
;
2546 unsigned long regmask
;
2550 unsigned char *imask
;
2551 unsigned long imask_size
;
2555 imask
= region
->r
.record
.r
.mask
.i
;
2556 imask_size
= region
->r
.record
.r
.imask_size
;
2559 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2560 imask
= xmalloc (imask_size
);
2561 memset (imask
, 0, imask_size
);
2563 region
->r
.record
.r
.imask_size
= imask_size
;
2564 region
->r
.record
.r
.mask
.i
= imask
;
2568 pos
= 2 * (3 - t
% 4);
2571 if (i
>= imask_size
)
2573 as_bad ("Ignoring attempt to spill beyond end of region");
2577 imask
[i
] |= (type
& 0x3) << pos
;
2579 regmask
&= (regmask
- 1);
2590 count_bits (unsigned long mask
)
2602 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2603 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2604 containing FIRST_ADDR. */
2607 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2608 unsigned long slot_addr
;
2610 unsigned long first_addr
;
2613 unsigned long index
= 0;
2615 /* First time we are called, the initial address and frag are invalid. */
2616 if (first_addr
== 0)
2619 /* If the two addresses are in different frags, then we need to add in
2620 the remaining size of this frag, and then the entire size of intermediate
2622 while (slot_frag
!= first_frag
)
2624 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2626 /* Add in the full size of the frag converted to instruction slots. */
2627 index
+= 3 * (first_frag
->fr_fix
>> 4);
2628 /* Subtract away the initial part before first_addr. */
2629 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2630 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2632 /* Move to the beginning of the next frag. */
2633 first_frag
= first_frag
->fr_next
;
2634 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2637 /* Add in the used part of the last frag. */
2638 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2639 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2643 /* Optimize unwind record directives. */
2645 static unw_rec_list
*
2646 optimize_unw_records (list
)
2652 /* If the only unwind record is ".prologue" or ".prologue" followed
2653 by ".body", then we can optimize the unwind directives away. */
2654 if (list
->r
.type
== prologue
2655 && (list
->next
== NULL
2656 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2662 /* Given a complete record list, process any records which have
2663 unresolved fields, (ie length counts for a prologue). After
2664 this has been run, all neccessary information should be available
2665 within each record to generate an image. */
2668 fixup_unw_records (list
)
2671 unw_rec_list
*ptr
, *region
= 0;
2672 unsigned long first_addr
= 0, rlen
= 0, t
;
2673 fragS
*first_frag
= 0;
2675 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2677 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2678 as_bad (" Insn slot not set in unwind record.");
2679 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2680 first_addr
, first_frag
);
2681 switch (ptr
->r
.type
)
2688 int size
, dir_len
= 0;
2689 unsigned long last_addr
;
2692 first_addr
= ptr
->slot_number
;
2693 first_frag
= ptr
->slot_frag
;
2694 ptr
->slot_number
= 0;
2695 /* Find either the next body/prologue start, or the end of
2696 the list, and determine the size of the region. */
2697 last_addr
= unwind
.next_slot_number
;
2698 last_frag
= unwind
.next_slot_frag
;
2699 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2700 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2701 || last
->r
.type
== body
)
2703 last_addr
= last
->slot_number
;
2704 last_frag
= last
->slot_frag
;
2707 else if (!last
->next
)
2709 /* In the absence of an explicit .body directive,
2710 the prologue ends after the last instruction
2711 covered by an unwind directive. */
2712 if (ptr
->r
.type
!= body
)
2714 last_addr
= last
->slot_number
;
2715 last_frag
= last
->slot_frag
;
2716 switch (last
->r
.type
)
2719 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2720 + count_bits (last
->r
.record
.p
.grmask
));
2724 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2728 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2731 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2740 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2742 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2743 if (ptr
->r
.type
== body
)
2744 /* End of region. */
2751 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2762 case priunat_when_gr
:
2763 case priunat_when_mem
:
2767 ptr
->r
.record
.p
.t
= t
;
2775 case spill_psprel_p
:
2776 ptr
->r
.record
.x
.t
= t
;
2782 as_bad ("frgr_mem record before region record!\n");
2785 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2786 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2787 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2788 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2793 as_bad ("fr_mem record before region record!\n");
2796 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2797 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2802 as_bad ("gr_mem record before region record!\n");
2805 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2806 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2811 as_bad ("br_mem record before region record!\n");
2814 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2815 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2821 as_bad ("gr_gr record before region record!\n");
2824 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2829 as_bad ("br_gr record before region record!\n");
2832 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2841 /* Helper routine for output_unw_records. Emits the header for the unwind
2845 setup_unwind_header (int size
, unsigned char **mem
)
2850 /* pad to pointer-size boundry. */
2851 x
= size
% md
.pointer_size
;
2853 extra
= md
.pointer_size
- x
;
2855 /* Add 8 for the header + a pointer for the
2856 personality offset. */
2857 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2859 /* Clear the padding area and personality. */
2860 memset (*mem
+ 8 + size
, 0, extra
+ md
.pointer_size
);
2862 /* Initialize the header area. */
2863 if (unwind
.personality_routine
)
2865 if (md
.flags
& EF_IA_64_ABI64
)
2866 flag_value
= (bfd_vma
) 3 << 32;
2868 /* 32-bit unwind info block. */
2869 flag_value
= (bfd_vma
) 0x1003 << 32;
2874 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* Version. */
2875 | flag_value
/* U & E handler flags. */
2876 | ((size
+ extra
) / md
.pointer_size
)), /* Length. */
2882 /* Generate an unwind image from a record list. Returns the number of
2883 bytes in the resulting image. The memory image itselof is returned
2884 in the 'ptr' parameter. */
2886 output_unw_records (list
, ptr
)
2895 list
= optimize_unw_records (list
);
2896 fixup_unw_records (list
);
2897 size
= calc_record_size (list
);
2899 if (size
> 0 || unwind
.force_unwind_entry
)
2901 unwind
.force_unwind_entry
= 0;
2902 extra
= setup_unwind_header (size
, &mem
);
2904 vbyte_mem_ptr
= mem
+ 8;
2905 process_unw_records (list
, output_vbyte_mem
);
2909 size
+= extra
+ 8 + md
.pointer_size
;
2915 convert_expr_to_ab_reg (e
, ab
, regp
)
2922 if (e
->X_op
!= O_register
)
2925 reg
= e
->X_add_number
;
2926 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2929 *regp
= reg
- REG_GR
;
2931 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2932 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2935 *regp
= reg
- REG_FR
;
2937 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2940 *regp
= reg
- REG_BR
;
2947 case REG_PR
: *regp
= 0; break;
2948 case REG_PSP
: *regp
= 1; break;
2949 case REG_PRIUNAT
: *regp
= 2; break;
2950 case REG_BR
+ 0: *regp
= 3; break;
2951 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2952 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2953 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2954 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2955 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2956 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2957 case REG_AR
+ AR_LC
: *regp
= 10; break;
2967 convert_expr_to_xy_reg (e
, xy
, regp
)
2974 if (e
->X_op
!= O_register
)
2977 reg
= e
->X_add_number
;
2979 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2982 *regp
= reg
- REG_GR
;
2984 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2987 *regp
= reg
- REG_FR
;
2989 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2992 *regp
= reg
- REG_BR
;
3001 int dummy ATTRIBUTE_UNUSED
;
3006 radix
= *input_line_pointer
++;
3008 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
3010 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
3011 ignore_rest_of_line ();
3016 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
3018 dot_special_section (which
)
3021 set_section ((char *) special_section_name
[which
]);
3025 add_unwind_entry (ptr
)
3029 unwind
.tail
->next
= ptr
;
3034 /* The current entry can in fact be a chain of unwind entries. */
3035 if (unwind
.current_entry
== NULL
)
3036 unwind
.current_entry
= ptr
;
3041 int dummy ATTRIBUTE_UNUSED
;
3047 if (e
.X_op
!= O_constant
)
3048 as_bad ("Operand to .fframe must be a constant");
3050 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
3055 int dummy ATTRIBUTE_UNUSED
;
3061 reg
= e
.X_add_number
- REG_GR
;
3062 if (e
.X_op
== O_register
&& reg
< 128)
3064 add_unwind_entry (output_mem_stack_v ());
3065 if (! (unwind
.prologue_mask
& 2))
3066 add_unwind_entry (output_psp_gr (reg
));
3069 as_bad ("First operand to .vframe must be a general register");
3073 dot_vframesp (dummy
)
3074 int dummy ATTRIBUTE_UNUSED
;
3079 if (e
.X_op
== O_constant
)
3081 add_unwind_entry (output_mem_stack_v ());
3082 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3085 as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
3089 dot_vframepsp (dummy
)
3090 int dummy ATTRIBUTE_UNUSED
;
3095 if (e
.X_op
== O_constant
)
3097 add_unwind_entry (output_mem_stack_v ());
3098 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3101 as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)");
3106 int dummy ATTRIBUTE_UNUSED
;
3112 sep
= parse_operand (&e1
);
3114 as_bad ("No second operand to .save");
3115 sep
= parse_operand (&e2
);
3117 reg1
= e1
.X_add_number
;
3118 reg2
= e2
.X_add_number
- REG_GR
;
3120 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3121 if (e1
.X_op
== O_register
)
3123 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3127 case REG_AR
+ AR_BSP
:
3128 add_unwind_entry (output_bsp_when ());
3129 add_unwind_entry (output_bsp_gr (reg2
));
3131 case REG_AR
+ AR_BSPSTORE
:
3132 add_unwind_entry (output_bspstore_when ());
3133 add_unwind_entry (output_bspstore_gr (reg2
));
3135 case REG_AR
+ AR_RNAT
:
3136 add_unwind_entry (output_rnat_when ());
3137 add_unwind_entry (output_rnat_gr (reg2
));
3139 case REG_AR
+ AR_UNAT
:
3140 add_unwind_entry (output_unat_when ());
3141 add_unwind_entry (output_unat_gr (reg2
));
3143 case REG_AR
+ AR_FPSR
:
3144 add_unwind_entry (output_fpsr_when ());
3145 add_unwind_entry (output_fpsr_gr (reg2
));
3147 case REG_AR
+ AR_PFS
:
3148 add_unwind_entry (output_pfs_when ());
3149 if (! (unwind
.prologue_mask
& 4))
3150 add_unwind_entry (output_pfs_gr (reg2
));
3152 case REG_AR
+ AR_LC
:
3153 add_unwind_entry (output_lc_when ());
3154 add_unwind_entry (output_lc_gr (reg2
));
3157 add_unwind_entry (output_rp_when ());
3158 if (! (unwind
.prologue_mask
& 8))
3159 add_unwind_entry (output_rp_gr (reg2
));
3162 add_unwind_entry (output_preds_when ());
3163 if (! (unwind
.prologue_mask
& 1))
3164 add_unwind_entry (output_preds_gr (reg2
));
3167 add_unwind_entry (output_priunat_when_gr ());
3168 add_unwind_entry (output_priunat_gr (reg2
));
3171 as_bad ("First operand not a valid register");
3175 as_bad (" Second operand not a valid register");
3178 as_bad ("First operand not a register");
3183 int dummy ATTRIBUTE_UNUSED
;
3186 unsigned long ecount
; /* # of _additional_ regions to pop */
3189 sep
= parse_operand (&e1
);
3190 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3192 as_bad ("First operand to .restore must be stack pointer (sp)");
3198 parse_operand (&e2
);
3199 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3201 as_bad ("Second operand to .restore must be a constant >= 0");
3204 ecount
= e2
.X_add_number
;
3207 ecount
= unwind
.prologue_count
- 1;
3209 if (ecount
>= unwind
.prologue_count
)
3211 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3212 ecount
+ 1, unwind
.prologue_count
);
3216 add_unwind_entry (output_epilogue (ecount
));
3218 if (ecount
< unwind
.prologue_count
)
3219 unwind
.prologue_count
-= ecount
+ 1;
3221 unwind
.prologue_count
= 0;
3225 dot_restorereg (dummy
)
3226 int dummy ATTRIBUTE_UNUSED
;
3228 unsigned int ab
, reg
;
3233 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3235 as_bad ("First operand to .restorereg must be a preserved register");
3238 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3242 dot_restorereg_p (dummy
)
3243 int dummy ATTRIBUTE_UNUSED
;
3245 unsigned int qp
, ab
, reg
;
3249 sep
= parse_operand (&e1
);
3252 as_bad ("No second operand to .restorereg.p");
3256 parse_operand (&e2
);
3258 qp
= e1
.X_add_number
- REG_P
;
3259 if (e1
.X_op
!= O_register
|| qp
> 63)
3261 as_bad ("First operand to .restorereg.p must be a predicate");
3265 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3267 as_bad ("Second operand to .restorereg.p must be a preserved register");
3270 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3274 generate_unwind_image (text_name
)
3275 const char *text_name
;
3280 /* Force out pending instructions, to make sure all unwind records have
3281 a valid slot_number field. */
3282 ia64_flush_insns ();
3284 /* Generate the unwind record. */
3285 size
= output_unw_records (unwind
.list
, &unw_rec
);
3286 if (size
% md
.pointer_size
!= 0)
3287 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3289 /* If there are unwind records, switch sections, and output the info. */
3292 unsigned char *where
;
3295 bfd_reloc_code_real_type reloc
;
3297 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3298 set_section (sec_name
);
3299 bfd_set_section_flags (stdoutput
, now_seg
,
3300 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3302 /* Make sure the section has 4 byte alignment for ILP32 and
3303 8 byte alignment for LP64. */
3304 frag_align (md
.pointer_size_shift
, 0, 0);
3305 record_alignment (now_seg
, md
.pointer_size_shift
);
3307 /* Set expression which points to start of unwind descriptor area. */
3308 unwind
.info
= expr_build_dot ();
3310 where
= (unsigned char *) frag_more (size
);
3312 /* Issue a label for this address, and keep track of it to put it
3313 in the unwind section. */
3315 /* Copy the information from the unwind record into this section. The
3316 data is already in the correct byte order. */
3317 memcpy (where
, unw_rec
, size
);
3319 /* Add the personality address to the image. */
3320 if (unwind
.personality_routine
!= 0)
3322 exp
.X_op
= O_symbol
;
3323 exp
.X_add_symbol
= unwind
.personality_routine
;
3324 exp
.X_add_number
= 0;
3326 if (md
.flags
& EF_IA_64_BE
)
3328 if (md
.flags
& EF_IA_64_ABI64
)
3329 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64MSB
;
3331 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32MSB
;
3335 if (md
.flags
& EF_IA_64_ABI64
)
3336 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64LSB
;
3338 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32LSB
;
3341 fix_new_exp (frag_now
, frag_now_fix () - md
.pointer_size
,
3342 md
.pointer_size
, &exp
, 0, reloc
);
3343 unwind
.personality_routine
= 0;
3347 free_list_records (unwind
.list
);
3348 free_saved_prologue_counts ();
3349 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3355 dot_handlerdata (dummy
)
3356 int dummy ATTRIBUTE_UNUSED
;
3358 const char *text_name
= segment_name (now_seg
);
3360 /* If text section name starts with ".text" (which it should),
3361 strip this prefix off. */
3362 if (strcmp (text_name
, ".text") == 0)
3365 unwind
.force_unwind_entry
= 1;
3367 /* Remember which segment we're in so we can switch back after .endp */
3368 unwind
.saved_text_seg
= now_seg
;
3369 unwind
.saved_text_subseg
= now_subseg
;
3371 /* Generate unwind info into unwind-info section and then leave that
3372 section as the currently active one so dataXX directives go into
3373 the language specific data area of the unwind info block. */
3374 generate_unwind_image (text_name
);
3375 demand_empty_rest_of_line ();
3379 dot_unwentry (dummy
)
3380 int dummy ATTRIBUTE_UNUSED
;
3382 unwind
.force_unwind_entry
= 1;
3383 demand_empty_rest_of_line ();
3388 int dummy ATTRIBUTE_UNUSED
;
3394 reg
= e
.X_add_number
- REG_BR
;
3395 if (e
.X_op
== O_register
&& reg
< 8)
3396 add_unwind_entry (output_rp_br (reg
));
3398 as_bad ("First operand not a valid branch register");
3402 dot_savemem (psprel
)
3409 sep
= parse_operand (&e1
);
3411 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3412 sep
= parse_operand (&e2
);
3414 reg1
= e1
.X_add_number
;
3415 val
= e2
.X_add_number
;
3417 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3418 if (e1
.X_op
== O_register
)
3420 if (e2
.X_op
== O_constant
)
3424 case REG_AR
+ AR_BSP
:
3425 add_unwind_entry (output_bsp_when ());
3426 add_unwind_entry ((psprel
3428 : output_bsp_sprel
) (val
));
3430 case REG_AR
+ AR_BSPSTORE
:
3431 add_unwind_entry (output_bspstore_when ());
3432 add_unwind_entry ((psprel
3433 ? output_bspstore_psprel
3434 : output_bspstore_sprel
) (val
));
3436 case REG_AR
+ AR_RNAT
:
3437 add_unwind_entry (output_rnat_when ());
3438 add_unwind_entry ((psprel
3439 ? output_rnat_psprel
3440 : output_rnat_sprel
) (val
));
3442 case REG_AR
+ AR_UNAT
:
3443 add_unwind_entry (output_unat_when ());
3444 add_unwind_entry ((psprel
3445 ? output_unat_psprel
3446 : output_unat_sprel
) (val
));
3448 case REG_AR
+ AR_FPSR
:
3449 add_unwind_entry (output_fpsr_when ());
3450 add_unwind_entry ((psprel
3451 ? output_fpsr_psprel
3452 : output_fpsr_sprel
) (val
));
3454 case REG_AR
+ AR_PFS
:
3455 add_unwind_entry (output_pfs_when ());
3456 add_unwind_entry ((psprel
3458 : output_pfs_sprel
) (val
));
3460 case REG_AR
+ AR_LC
:
3461 add_unwind_entry (output_lc_when ());
3462 add_unwind_entry ((psprel
3464 : output_lc_sprel
) (val
));
3467 add_unwind_entry (output_rp_when ());
3468 add_unwind_entry ((psprel
3470 : output_rp_sprel
) (val
));
3473 add_unwind_entry (output_preds_when ());
3474 add_unwind_entry ((psprel
3475 ? output_preds_psprel
3476 : output_preds_sprel
) (val
));
3479 add_unwind_entry (output_priunat_when_mem ());
3480 add_unwind_entry ((psprel
3481 ? output_priunat_psprel
3482 : output_priunat_sprel
) (val
));
3485 as_bad ("First operand not a valid register");
3489 as_bad (" Second operand not a valid constant");
3492 as_bad ("First operand not a register");
3497 int dummy ATTRIBUTE_UNUSED
;
3501 sep
= parse_operand (&e1
);
3503 parse_operand (&e2
);
3505 if (e1
.X_op
!= O_constant
)
3506 as_bad ("First operand to .save.g must be a constant.");
3509 int grmask
= e1
.X_add_number
;
3511 add_unwind_entry (output_gr_mem (grmask
));
3514 int reg
= e2
.X_add_number
- REG_GR
;
3515 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3516 add_unwind_entry (output_gr_gr (grmask
, reg
));
3518 as_bad ("Second operand is an invalid register.");
3525 int dummy ATTRIBUTE_UNUSED
;
3529 sep
= parse_operand (&e1
);
3531 if (e1
.X_op
!= O_constant
)
3532 as_bad ("Operand to .save.f must be a constant.");
3534 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3539 int dummy ATTRIBUTE_UNUSED
;
3546 sep
= parse_operand (&e1
);
3547 if (e1
.X_op
!= O_constant
)
3549 as_bad ("First operand to .save.b must be a constant.");
3552 brmask
= e1
.X_add_number
;
3556 sep
= parse_operand (&e2
);
3557 reg
= e2
.X_add_number
- REG_GR
;
3558 if (e2
.X_op
!= O_register
|| reg
> 127)
3560 as_bad ("Second operand to .save.b must be a general register.");
3563 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3566 add_unwind_entry (output_br_mem (brmask
));
3568 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3569 ignore_rest_of_line ();
3574 int dummy ATTRIBUTE_UNUSED
;
3578 sep
= parse_operand (&e1
);
3580 parse_operand (&e2
);
3582 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3583 as_bad ("Both operands of .save.gf must be constants.");
3586 int grmask
= e1
.X_add_number
;
3587 int frmask
= e2
.X_add_number
;
3588 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3594 int dummy ATTRIBUTE_UNUSED
;
3599 sep
= parse_operand (&e
);
3600 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3601 ignore_rest_of_line ();
3603 if (e
.X_op
!= O_constant
)
3604 as_bad ("Operand to .spill must be a constant");
3606 add_unwind_entry (output_spill_base (e
.X_add_number
));
3610 dot_spillreg (dummy
)
3611 int dummy ATTRIBUTE_UNUSED
;
3613 int sep
, ab
, xy
, reg
, treg
;
3616 sep
= parse_operand (&e1
);
3619 as_bad ("No second operand to .spillreg");
3623 parse_operand (&e2
);
3625 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3627 as_bad ("First operand to .spillreg must be a preserved register");
3631 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3633 as_bad ("Second operand to .spillreg must be a register");
3637 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3641 dot_spillmem (psprel
)
3647 sep
= parse_operand (&e1
);
3650 as_bad ("Second operand missing");
3654 parse_operand (&e2
);
3656 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3658 as_bad ("First operand to .spill%s must be a preserved register",
3659 psprel
? "psp" : "sp");
3663 if (e2
.X_op
!= O_constant
)
3665 as_bad ("Second operand to .spill%s must be a constant",
3666 psprel
? "psp" : "sp");
3671 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3673 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3677 dot_spillreg_p (dummy
)
3678 int dummy ATTRIBUTE_UNUSED
;
3680 int sep
, ab
, xy
, reg
, treg
;
3681 expressionS e1
, e2
, e3
;
3684 sep
= parse_operand (&e1
);
3687 as_bad ("No second and third operand to .spillreg.p");
3691 sep
= parse_operand (&e2
);
3694 as_bad ("No third operand to .spillreg.p");
3698 parse_operand (&e3
);
3700 qp
= e1
.X_add_number
- REG_P
;
3702 if (e1
.X_op
!= O_register
|| qp
> 63)
3704 as_bad ("First operand to .spillreg.p must be a predicate");
3708 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3710 as_bad ("Second operand to .spillreg.p must be a preserved register");
3714 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3716 as_bad ("Third operand to .spillreg.p must be a register");
3720 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3724 dot_spillmem_p (psprel
)
3727 expressionS e1
, e2
, e3
;
3731 sep
= parse_operand (&e1
);
3734 as_bad ("Second operand missing");
3738 parse_operand (&e2
);
3741 as_bad ("Second operand missing");
3745 parse_operand (&e3
);
3747 qp
= e1
.X_add_number
- REG_P
;
3748 if (e1
.X_op
!= O_register
|| qp
> 63)
3750 as_bad ("First operand to .spill%s_p must be a predicate",
3751 psprel
? "psp" : "sp");
3755 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3757 as_bad ("Second operand to .spill%s_p must be a preserved register",
3758 psprel
? "psp" : "sp");
3762 if (e3
.X_op
!= O_constant
)
3764 as_bad ("Third operand to .spill%s_p must be a constant",
3765 psprel
? "psp" : "sp");
3770 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3772 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3776 get_saved_prologue_count (lbl
)
3779 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3781 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3785 return lpc
->prologue_count
;
3787 as_bad ("Missing .label_state %ld", lbl
);
3792 save_prologue_count (lbl
, count
)
3796 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3798 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3802 lpc
->prologue_count
= count
;
3805 label_prologue_count
*new_lpc
= xmalloc (sizeof (* new_lpc
));
3807 new_lpc
->next
= unwind
.saved_prologue_counts
;
3808 new_lpc
->label_number
= lbl
;
3809 new_lpc
->prologue_count
= count
;
3810 unwind
.saved_prologue_counts
= new_lpc
;
3815 free_saved_prologue_counts ()
3817 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3818 label_prologue_count
*next
;
3827 unwind
.saved_prologue_counts
= NULL
;
3831 dot_label_state (dummy
)
3832 int dummy ATTRIBUTE_UNUSED
;
3837 if (e
.X_op
!= O_constant
)
3839 as_bad ("Operand to .label_state must be a constant");
3842 add_unwind_entry (output_label_state (e
.X_add_number
));
3843 save_prologue_count (e
.X_add_number
, unwind
.prologue_count
);
3847 dot_copy_state (dummy
)
3848 int dummy ATTRIBUTE_UNUSED
;
3853 if (e
.X_op
!= O_constant
)
3855 as_bad ("Operand to .copy_state must be a constant");
3858 add_unwind_entry (output_copy_state (e
.X_add_number
));
3859 unwind
.prologue_count
= get_saved_prologue_count (e
.X_add_number
);
3864 int dummy ATTRIBUTE_UNUSED
;
3869 sep
= parse_operand (&e1
);
3872 as_bad ("Second operand to .unwabi missing");
3875 sep
= parse_operand (&e2
);
3876 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3877 ignore_rest_of_line ();
3879 if (e1
.X_op
!= O_constant
)
3881 as_bad ("First operand to .unwabi must be a constant");
3885 if (e2
.X_op
!= O_constant
)
3887 as_bad ("Second operand to .unwabi must be a constant");
3891 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3895 dot_personality (dummy
)
3896 int dummy ATTRIBUTE_UNUSED
;
3900 name
= input_line_pointer
;
3901 c
= get_symbol_end ();
3902 p
= input_line_pointer
;
3903 unwind
.personality_routine
= symbol_find_or_make (name
);
3904 unwind
.force_unwind_entry
= 1;
3907 demand_empty_rest_of_line ();
3912 int dummy ATTRIBUTE_UNUSED
;
3917 unwind
.proc_start
= expr_build_dot ();
3918 /* Parse names of main and alternate entry points and mark them as
3919 function symbols: */
3923 name
= input_line_pointer
;
3924 c
= get_symbol_end ();
3925 p
= input_line_pointer
;
3926 sym
= symbol_find_or_make (name
);
3927 if (unwind
.proc_start
== 0)
3929 unwind
.proc_start
= sym
;
3931 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3934 if (*input_line_pointer
!= ',')
3936 ++input_line_pointer
;
3938 demand_empty_rest_of_line ();
3941 unwind
.prologue_count
= 0;
3942 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3943 unwind
.personality_routine
= 0;
3948 int dummy ATTRIBUTE_UNUSED
;
3950 unwind
.prologue
= 0;
3951 unwind
.prologue_mask
= 0;
3953 add_unwind_entry (output_body ());
3954 demand_empty_rest_of_line ();
3958 dot_prologue (dummy
)
3959 int dummy ATTRIBUTE_UNUSED
;
3962 int mask
= 0, grsave
= 0;
3964 if (!is_it_end_of_statement ())
3967 sep
= parse_operand (&e1
);
3969 as_bad ("No second operand to .prologue");
3970 sep
= parse_operand (&e2
);
3971 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3972 ignore_rest_of_line ();
3974 if (e1
.X_op
== O_constant
)
3976 mask
= e1
.X_add_number
;
3978 if (e2
.X_op
== O_constant
)
3979 grsave
= e2
.X_add_number
;
3980 else if (e2
.X_op
== O_register
3981 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3984 as_bad ("Second operand not a constant or general register");
3986 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3989 as_bad ("First operand not a constant");
3992 add_unwind_entry (output_prologue ());
3994 unwind
.prologue
= 1;
3995 unwind
.prologue_mask
= mask
;
3996 ++unwind
.prologue_count
;
4001 int dummy ATTRIBUTE_UNUSED
;
4005 int bytes_per_address
;
4008 subsegT saved_subseg
;
4009 const char *sec_name
, *text_name
;
4013 if (unwind
.saved_text_seg
)
4015 saved_seg
= unwind
.saved_text_seg
;
4016 saved_subseg
= unwind
.saved_text_subseg
;
4017 unwind
.saved_text_seg
= NULL
;
4021 saved_seg
= now_seg
;
4022 saved_subseg
= now_subseg
;
4026 Use a slightly ugly scheme to derive the unwind section names from
4027 the text section name:
4029 text sect. unwind table sect.
4030 name: name: comments:
4031 ---------- ----------------- --------------------------------
4033 .text.foo .IA_64.unwind.text.foo
4034 .foo .IA_64.unwind.foo
4036 .gnu.linkonce.ia64unw.foo
4037 _info .IA_64.unwind_info gas issues error message (ditto)
4038 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4040 This mapping is done so that:
4042 (a) An object file with unwind info only in .text will use
4043 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4044 This follows the letter of the ABI and also ensures backwards
4045 compatibility with older toolchains.
4047 (b) An object file with unwind info in multiple text sections
4048 will use separate unwind sections for each text section.
4049 This allows us to properly set the "sh_info" and "sh_link"
4050 fields in SHT_IA_64_UNWIND as required by the ABI and also
4051 lets GNU ld support programs with multiple segments
4052 containing unwind info (as might be the case for certain
4053 embedded applications).
4055 (c) An error is issued if there would be a name clash.
4057 text_name
= segment_name (saved_seg
);
4058 if (strncmp (text_name
, "_info", 5) == 0)
4060 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4062 ignore_rest_of_line ();
4065 if (strcmp (text_name
, ".text") == 0)
4068 insn_group_break (1, 0, 0);
4070 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4072 generate_unwind_image (text_name
);
4074 if (unwind
.info
|| unwind
.force_unwind_entry
)
4076 subseg_set (md
.last_text_seg
, 0);
4077 unwind
.proc_end
= expr_build_dot ();
4079 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
4080 set_section ((char *) sec_name
);
4081 bfd_set_section_flags (stdoutput
, now_seg
,
4082 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
4084 /* Make sure that section has 4 byte alignment for ILP32 and
4085 8 byte alignment for LP64. */
4086 record_alignment (now_seg
, md
.pointer_size_shift
);
4088 /* Need space for 3 pointers for procedure start, procedure end,
4090 ptr
= frag_more (3 * md
.pointer_size
);
4091 where
= frag_now_fix () - (3 * md
.pointer_size
);
4092 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
4094 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
4095 e
.X_op
= O_pseudo_fixup
;
4096 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4098 e
.X_add_symbol
= unwind
.proc_start
;
4099 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
4101 e
.X_op
= O_pseudo_fixup
;
4102 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4104 e
.X_add_symbol
= unwind
.proc_end
;
4105 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
4106 bytes_per_address
, &e
);
4110 e
.X_op
= O_pseudo_fixup
;
4111 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4113 e
.X_add_symbol
= unwind
.info
;
4114 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
4115 bytes_per_address
, &e
);
4118 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
4122 subseg_set (saved_seg
, saved_subseg
);
4124 /* Parse names of main and alternate entry points and set symbol sizes. */
4128 name
= input_line_pointer
;
4129 c
= get_symbol_end ();
4130 p
= input_line_pointer
;
4131 sym
= symbol_find (name
);
4132 if (sym
&& unwind
.proc_start
4133 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
4134 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
4136 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
4137 fragS
*frag
= symbol_get_frag (sym
);
4139 /* Check whether the function label is at or beyond last
4141 while (fr
&& fr
!= frag
)
4145 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
4146 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
4149 symbol_get_obj (sym
)->size
=
4150 (expressionS
*) xmalloc (sizeof (expressionS
));
4151 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
4152 symbol_get_obj (sym
)->size
->X_add_symbol
4153 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
4154 frag_now_fix (), frag_now
);
4155 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
4156 symbol_get_obj (sym
)->size
->X_add_number
= 0;
4162 if (*input_line_pointer
!= ',')
4164 ++input_line_pointer
;
4166 demand_empty_rest_of_line ();
4167 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4171 dot_template (template)
4174 CURR_SLOT
.user_template
= template;
4179 int dummy ATTRIBUTE_UNUSED
;
4181 int ins
, locs
, outs
, rots
;
4183 if (is_it_end_of_statement ())
4184 ins
= locs
= outs
= rots
= 0;
4187 ins
= get_absolute_expression ();
4188 if (*input_line_pointer
++ != ',')
4190 locs
= get_absolute_expression ();
4191 if (*input_line_pointer
++ != ',')
4193 outs
= get_absolute_expression ();
4194 if (*input_line_pointer
++ != ',')
4196 rots
= get_absolute_expression ();
4198 set_regstack (ins
, locs
, outs
, rots
);
4202 as_bad ("Comma expected");
4203 ignore_rest_of_line ();
4210 unsigned num_regs
, num_alloced
= 0;
4211 struct dynreg
**drpp
, *dr
;
4212 int ch
, base_reg
= 0;
4218 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4219 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4220 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4224 /* First, remove existing names from hash table. */
4225 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4227 hash_delete (md
.dynreg_hash
, dr
->name
);
4231 drpp
= &md
.dynreg
[type
];
4234 start
= input_line_pointer
;
4235 ch
= get_symbol_end ();
4236 *input_line_pointer
= ch
;
4237 len
= (input_line_pointer
- start
);
4240 if (*input_line_pointer
!= '[')
4242 as_bad ("Expected '['");
4245 ++input_line_pointer
; /* skip '[' */
4247 num_regs
= get_absolute_expression ();
4249 if (*input_line_pointer
++ != ']')
4251 as_bad ("Expected ']'");
4256 num_alloced
+= num_regs
;
4260 if (num_alloced
> md
.rot
.num_regs
)
4262 as_bad ("Used more than the declared %d rotating registers",
4268 if (num_alloced
> 96)
4270 as_bad ("Used more than the available 96 rotating registers");
4275 if (num_alloced
> 48)
4277 as_bad ("Used more than the available 48 rotating registers");
4286 name
= obstack_alloc (¬es
, len
+ 1);
4287 memcpy (name
, start
, len
);
4292 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4293 memset (*drpp
, 0, sizeof (*dr
));
4298 dr
->num_regs
= num_regs
;
4299 dr
->base
= base_reg
;
4301 base_reg
+= num_regs
;
4303 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4305 as_bad ("Attempt to redefine register set `%s'", name
);
4309 if (*input_line_pointer
!= ',')
4311 ++input_line_pointer
; /* skip comma */
4314 demand_empty_rest_of_line ();
4318 ignore_rest_of_line ();
4322 dot_byteorder (byteorder
)
4325 segment_info_type
*seginfo
= seg_info (now_seg
);
4327 if (byteorder
== -1)
4329 if (seginfo
->tc_segment_info_data
.endian
== 0)
4330 seginfo
->tc_segment_info_data
.endian
4331 = TARGET_BYTES_BIG_ENDIAN
? 1 : 2;
4332 byteorder
= seginfo
->tc_segment_info_data
.endian
== 1;
4335 seginfo
->tc_segment_info_data
.endian
= byteorder
? 1 : 2;
4337 if (target_big_endian
!= byteorder
)
4339 target_big_endian
= byteorder
;
4340 if (target_big_endian
)
4342 ia64_number_to_chars
= number_to_chars_bigendian
;
4343 ia64_float_to_chars
= ia64_float_to_chars_bigendian
;
4347 ia64_number_to_chars
= number_to_chars_littleendian
;
4348 ia64_float_to_chars
= ia64_float_to_chars_littleendian
;
4355 int dummy ATTRIBUTE_UNUSED
;
4362 option
= input_line_pointer
;
4363 ch
= get_symbol_end ();
4364 if (strcmp (option
, "lsb") == 0)
4365 md
.flags
&= ~EF_IA_64_BE
;
4366 else if (strcmp (option
, "msb") == 0)
4367 md
.flags
|= EF_IA_64_BE
;
4368 else if (strcmp (option
, "abi32") == 0)
4369 md
.flags
&= ~EF_IA_64_ABI64
;
4370 else if (strcmp (option
, "abi64") == 0)
4371 md
.flags
|= EF_IA_64_ABI64
;
4373 as_bad ("Unknown psr option `%s'", option
);
4374 *input_line_pointer
= ch
;
4377 if (*input_line_pointer
!= ',')
4380 ++input_line_pointer
;
4383 demand_empty_rest_of_line ();
4388 int dummy ATTRIBUTE_UNUSED
;
4390 as_bad (".alias not implemented yet");
4395 int dummy ATTRIBUTE_UNUSED
;
4397 new_logical_line (0, get_absolute_expression ());
4398 demand_empty_rest_of_line ();
4402 parse_section_name ()
4408 if (*input_line_pointer
!= '"')
4410 as_bad ("Missing section name");
4411 ignore_rest_of_line ();
4414 name
= demand_copy_C_string (&len
);
4417 ignore_rest_of_line ();
4421 if (*input_line_pointer
!= ',')
4423 as_bad ("Comma expected after section name");
4424 ignore_rest_of_line ();
4427 ++input_line_pointer
; /* skip comma */
4435 char *name
= parse_section_name ();
4439 md
.keep_pending_output
= 1;
4442 obj_elf_previous (0);
4443 md
.keep_pending_output
= 0;
4446 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4449 stmt_float_cons (kind
)
4470 ia64_do_align (alignment
);
4478 int saved_auto_align
= md
.auto_align
;
4482 md
.auto_align
= saved_auto_align
;
4486 dot_xfloat_cons (kind
)
4489 char *name
= parse_section_name ();
4493 md
.keep_pending_output
= 1;
4495 stmt_float_cons (kind
);
4496 obj_elf_previous (0);
4497 md
.keep_pending_output
= 0;
4501 dot_xstringer (zero
)
4504 char *name
= parse_section_name ();
4508 md
.keep_pending_output
= 1;
4511 obj_elf_previous (0);
4512 md
.keep_pending_output
= 0;
4519 int saved_auto_align
= md
.auto_align
;
4520 char *name
= parse_section_name ();
4524 md
.keep_pending_output
= 1;
4528 md
.auto_align
= saved_auto_align
;
4529 obj_elf_previous (0);
4530 md
.keep_pending_output
= 0;
4534 dot_xfloat_cons_ua (kind
)
4537 int saved_auto_align
= md
.auto_align
;
4538 char *name
= parse_section_name ();
4542 md
.keep_pending_output
= 1;
4545 stmt_float_cons (kind
);
4546 md
.auto_align
= saved_auto_align
;
4547 obj_elf_previous (0);
4548 md
.keep_pending_output
= 0;
4551 /* .reg.val <regname>,value */
4555 int dummy ATTRIBUTE_UNUSED
;
4560 if (reg
.X_op
!= O_register
)
4562 as_bad (_("Register name expected"));
4563 ignore_rest_of_line ();
4565 else if (*input_line_pointer
++ != ',')
4567 as_bad (_("Comma expected"));
4568 ignore_rest_of_line ();
4572 valueT value
= get_absolute_expression ();
4573 int regno
= reg
.X_add_number
;
4574 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4575 as_warn (_("Register value annotation ignored"));
4578 gr_values
[regno
- REG_GR
].known
= 1;
4579 gr_values
[regno
- REG_GR
].value
= value
;
4580 gr_values
[regno
- REG_GR
].path
= md
.path
;
4583 demand_empty_rest_of_line ();
4586 /* select dv checking mode
4591 A stop is inserted when changing modes
4598 if (md
.manual_bundling
)
4599 as_warn (_("Directive invalid within a bundle"));
4601 if (type
== 'E' || type
== 'A')
4602 md
.mode_explicitly_set
= 0;
4604 md
.mode_explicitly_set
= 1;
4611 if (md
.explicit_mode
)
4612 insn_group_break (1, 0, 0);
4613 md
.explicit_mode
= 0;
4617 if (!md
.explicit_mode
)
4618 insn_group_break (1, 0, 0);
4619 md
.explicit_mode
= 1;
4623 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4624 insn_group_break (1, 0, 0);
4625 md
.explicit_mode
= md
.default_explicit_mode
;
4626 md
.mode_explicitly_set
= 0;
4637 for (regno
= 0; regno
< 64; regno
++)
4639 if (mask
& ((valueT
) 1 << regno
))
4641 fprintf (stderr
, "%s p%d", comma
, regno
);
4648 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4649 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4650 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4651 .pred.safe_across_calls p1 [, p2 [,...]]
4660 int p1
= -1, p2
= -1;
4664 if (*input_line_pointer
!= '"')
4666 as_bad (_("Missing predicate relation type"));
4667 ignore_rest_of_line ();
4673 char *form
= demand_copy_C_string (&len
);
4674 if (strcmp (form
, "mutex") == 0)
4676 else if (strcmp (form
, "clear") == 0)
4678 else if (strcmp (form
, "imply") == 0)
4682 as_bad (_("Unrecognized predicate relation type"));
4683 ignore_rest_of_line ();
4687 if (*input_line_pointer
== ',')
4688 ++input_line_pointer
;
4698 if (TOUPPER (*input_line_pointer
) != 'P'
4699 || (regno
= atoi (++input_line_pointer
)) < 0
4702 as_bad (_("Predicate register expected"));
4703 ignore_rest_of_line ();
4706 while (ISDIGIT (*input_line_pointer
))
4707 ++input_line_pointer
;
4714 as_warn (_("Duplicate predicate register ignored"));
4717 /* See if it's a range. */
4718 if (*input_line_pointer
== '-')
4721 ++input_line_pointer
;
4723 if (TOUPPER (*input_line_pointer
) != 'P'
4724 || (regno
= atoi (++input_line_pointer
)) < 0
4727 as_bad (_("Predicate register expected"));
4728 ignore_rest_of_line ();
4731 while (ISDIGIT (*input_line_pointer
))
4732 ++input_line_pointer
;
4736 as_bad (_("Bad register range"));
4737 ignore_rest_of_line ();
4748 if (*input_line_pointer
!= ',')
4750 ++input_line_pointer
;
4759 clear_qp_mutex (mask
);
4760 clear_qp_implies (mask
, (valueT
) 0);
4763 if (count
!= 2 || p1
== -1 || p2
== -1)
4764 as_bad (_("Predicate source and target required"));
4765 else if (p1
== 0 || p2
== 0)
4766 as_bad (_("Use of p0 is not valid in this context"));
4768 add_qp_imply (p1
, p2
);
4773 as_bad (_("At least two PR arguments expected"));
4778 as_bad (_("Use of p0 is not valid in this context"));
4781 add_qp_mutex (mask
);
4784 /* note that we don't override any existing relations */
4787 as_bad (_("At least one PR argument expected"));
4792 fprintf (stderr
, "Safe across calls: ");
4793 print_prmask (mask
);
4794 fprintf (stderr
, "\n");
4796 qp_safe_across_calls
= mask
;
4799 demand_empty_rest_of_line ();
4802 /* .entry label [, label [, ...]]
4803 Hint to DV code that the given labels are to be considered entry points.
4804 Otherwise, only global labels are considered entry points. */
4808 int dummy ATTRIBUTE_UNUSED
;
4817 name
= input_line_pointer
;
4818 c
= get_symbol_end ();
4819 symbolP
= symbol_find_or_make (name
);
4821 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4823 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4826 *input_line_pointer
= c
;
4828 c
= *input_line_pointer
;
4831 input_line_pointer
++;
4833 if (*input_line_pointer
== '\n')
4839 demand_empty_rest_of_line ();
4842 /* .mem.offset offset, base
4843 "base" is used to distinguish between offsets from a different base. */
4846 dot_mem_offset (dummy
)
4847 int dummy ATTRIBUTE_UNUSED
;
4849 md
.mem_offset
.hint
= 1;
4850 md
.mem_offset
.offset
= get_absolute_expression ();
4851 if (*input_line_pointer
!= ',')
4853 as_bad (_("Comma expected"));
4854 ignore_rest_of_line ();
4857 ++input_line_pointer
;
4858 md
.mem_offset
.base
= get_absolute_expression ();
4859 demand_empty_rest_of_line ();
4862 /* ia64-specific pseudo-ops: */
4863 const pseudo_typeS md_pseudo_table
[] =
4865 { "radix", dot_radix
, 0 },
4866 { "lcomm", s_lcomm_bytes
, 1 },
4867 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4868 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4869 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4870 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4871 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4872 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4873 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4874 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4875 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4876 { "proc", dot_proc
, 0 },
4877 { "body", dot_body
, 0 },
4878 { "prologue", dot_prologue
, 0 },
4879 { "endp", dot_endp
, 0 },
4880 { "file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0 },
4881 { "loc", dwarf2_directive_loc
, 0 },
4883 { "fframe", dot_fframe
, 0 },
4884 { "vframe", dot_vframe
, 0 },
4885 { "vframesp", dot_vframesp
, 0 },
4886 { "vframepsp", dot_vframepsp
, 0 },
4887 { "save", dot_save
, 0 },
4888 { "restore", dot_restore
, 0 },
4889 { "restorereg", dot_restorereg
, 0 },
4890 { "restorereg.p", dot_restorereg_p
, 0 },
4891 { "handlerdata", dot_handlerdata
, 0 },
4892 { "unwentry", dot_unwentry
, 0 },
4893 { "altrp", dot_altrp
, 0 },
4894 { "savesp", dot_savemem
, 0 },
4895 { "savepsp", dot_savemem
, 1 },
4896 { "save.g", dot_saveg
, 0 },
4897 { "save.f", dot_savef
, 0 },
4898 { "save.b", dot_saveb
, 0 },
4899 { "save.gf", dot_savegf
, 0 },
4900 { "spill", dot_spill
, 0 },
4901 { "spillreg", dot_spillreg
, 0 },
4902 { "spillsp", dot_spillmem
, 0 },
4903 { "spillpsp", dot_spillmem
, 1 },
4904 { "spillreg.p", dot_spillreg_p
, 0 },
4905 { "spillsp.p", dot_spillmem_p
, 0 },
4906 { "spillpsp.p", dot_spillmem_p
, 1 },
4907 { "label_state", dot_label_state
, 0 },
4908 { "copy_state", dot_copy_state
, 0 },
4909 { "unwabi", dot_unwabi
, 0 },
4910 { "personality", dot_personality
, 0 },
4912 { "estate", dot_estate
, 0 },
4914 { "mii", dot_template
, 0x0 },
4915 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4916 { "mlx", dot_template
, 0x2 },
4917 { "mmi", dot_template
, 0x4 },
4918 { "mfi", dot_template
, 0x6 },
4919 { "mmf", dot_template
, 0x7 },
4920 { "mib", dot_template
, 0x8 },
4921 { "mbb", dot_template
, 0x9 },
4922 { "bbb", dot_template
, 0xb },
4923 { "mmb", dot_template
, 0xc },
4924 { "mfb", dot_template
, 0xe },
4926 { "lb", dot_scope
, 0 },
4927 { "le", dot_scope
, 1 },
4929 { "align", s_align_bytes
, 0 },
4930 { "regstk", dot_regstk
, 0 },
4931 { "rotr", dot_rot
, DYNREG_GR
},
4932 { "rotf", dot_rot
, DYNREG_FR
},
4933 { "rotp", dot_rot
, DYNREG_PR
},
4934 { "lsb", dot_byteorder
, 0 },
4935 { "msb", dot_byteorder
, 1 },
4936 { "psr", dot_psr
, 0 },
4937 { "alias", dot_alias
, 0 },
4938 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4940 { "xdata1", dot_xdata
, 1 },
4941 { "xdata2", dot_xdata
, 2 },
4942 { "xdata4", dot_xdata
, 4 },
4943 { "xdata8", dot_xdata
, 8 },
4944 { "xreal4", dot_xfloat_cons
, 'f' },
4945 { "xreal8", dot_xfloat_cons
, 'd' },
4946 { "xreal10", dot_xfloat_cons
, 'x' },
4947 { "xreal16", dot_xfloat_cons
, 'X' },
4948 { "xstring", dot_xstringer
, 0 },
4949 { "xstringz", dot_xstringer
, 1 },
4951 /* unaligned versions: */
4952 { "xdata2.ua", dot_xdata_ua
, 2 },
4953 { "xdata4.ua", dot_xdata_ua
, 4 },
4954 { "xdata8.ua", dot_xdata_ua
, 8 },
4955 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4956 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4957 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4958 { "xreal16.ua", dot_xfloat_cons_ua
, 'X' },
4960 /* annotations/DV checking support */
4961 { "entry", dot_entry
, 0 },
4962 { "mem.offset", dot_mem_offset
, 0 },
4963 { "pred.rel", dot_pred_rel
, 0 },
4964 { "pred.rel.clear", dot_pred_rel
, 'c' },
4965 { "pred.rel.imply", dot_pred_rel
, 'i' },
4966 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4967 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4968 { "reg.val", dot_reg_val
, 0 },
4969 { "auto", dot_dv_mode
, 'a' },
4970 { "explicit", dot_dv_mode
, 'e' },
4971 { "default", dot_dv_mode
, 'd' },
4973 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4974 IA-64 aligns data allocation pseudo-ops by default, so we have to
4975 tell it that these ones are supposed to be unaligned. Long term,
4976 should rewrite so that only IA-64 specific data allocation pseudo-ops
4977 are aligned by default. */
4978 {"2byte", stmt_cons_ua
, 2},
4979 {"4byte", stmt_cons_ua
, 4},
4980 {"8byte", stmt_cons_ua
, 8},
4985 static const struct pseudo_opcode
4988 void (*handler
) (int);
4993 /* these are more like pseudo-ops, but don't start with a dot */
4994 { "data1", cons
, 1 },
4995 { "data2", cons
, 2 },
4996 { "data4", cons
, 4 },
4997 { "data8", cons
, 8 },
4998 { "data16", cons
, 16 },
4999 { "real4", stmt_float_cons
, 'f' },
5000 { "real8", stmt_float_cons
, 'd' },
5001 { "real10", stmt_float_cons
, 'x' },
5002 { "real16", stmt_float_cons
, 'X' },
5003 { "string", stringer
, 0 },
5004 { "stringz", stringer
, 1 },
5006 /* unaligned versions: */
5007 { "data2.ua", stmt_cons_ua
, 2 },
5008 { "data4.ua", stmt_cons_ua
, 4 },
5009 { "data8.ua", stmt_cons_ua
, 8 },
5010 { "data16.ua", stmt_cons_ua
, 16 },
5011 { "real4.ua", float_cons
, 'f' },
5012 { "real8.ua", float_cons
, 'd' },
5013 { "real10.ua", float_cons
, 'x' },
5014 { "real16.ua", float_cons
, 'X' },
5017 /* Declare a register by creating a symbol for it and entering it in
5018 the symbol table. */
5021 declare_register (name
, regnum
)
5028 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
5030 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
5032 as_fatal ("Inserting \"%s\" into register table failed: %s",
5039 declare_register_set (prefix
, num_regs
, base_regnum
)
5047 for (i
= 0; i
< num_regs
; ++i
)
5049 sprintf (name
, "%s%u", prefix
, i
);
5050 declare_register (name
, base_regnum
+ i
);
5055 operand_width (opnd
)
5056 enum ia64_opnd opnd
;
5058 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
5059 unsigned int bits
= 0;
5063 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
5064 bits
+= odesc
->field
[i
].bits
;
5069 static enum operand_match_result
5070 operand_match (idesc
, index
, e
)
5071 const struct ia64_opcode
*idesc
;
5075 enum ia64_opnd opnd
= idesc
->operands
[index
];
5076 int bits
, relocatable
= 0;
5077 struct insn_fix
*fix
;
5084 case IA64_OPND_AR_CCV
:
5085 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
5086 return OPERAND_MATCH
;
5089 case IA64_OPND_AR_CSD
:
5090 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 25)
5091 return OPERAND_MATCH
;
5094 case IA64_OPND_AR_PFS
:
5095 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
5096 return OPERAND_MATCH
;
5100 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
5101 return OPERAND_MATCH
;
5105 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
5106 return OPERAND_MATCH
;
5110 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
5111 return OPERAND_MATCH
;
5114 case IA64_OPND_PR_ROT
:
5115 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
5116 return OPERAND_MATCH
;
5120 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
5121 return OPERAND_MATCH
;
5124 case IA64_OPND_PSR_L
:
5125 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
5126 return OPERAND_MATCH
;
5129 case IA64_OPND_PSR_UM
:
5130 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
5131 return OPERAND_MATCH
;
5135 if (e
->X_op
== O_constant
)
5137 if (e
->X_add_number
== 1)
5138 return OPERAND_MATCH
;
5140 return OPERAND_OUT_OF_RANGE
;
5145 if (e
->X_op
== O_constant
)
5147 if (e
->X_add_number
== 8)
5148 return OPERAND_MATCH
;
5150 return OPERAND_OUT_OF_RANGE
;
5155 if (e
->X_op
== O_constant
)
5157 if (e
->X_add_number
== 16)
5158 return OPERAND_MATCH
;
5160 return OPERAND_OUT_OF_RANGE
;
5164 /* register operands: */
5167 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
5168 && e
->X_add_number
< REG_AR
+ 128)
5169 return OPERAND_MATCH
;
5174 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
5175 && e
->X_add_number
< REG_BR
+ 8)
5176 return OPERAND_MATCH
;
5180 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
5181 && e
->X_add_number
< REG_CR
+ 128)
5182 return OPERAND_MATCH
;
5189 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
5190 && e
->X_add_number
< REG_FR
+ 128)
5191 return OPERAND_MATCH
;
5196 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
5197 && e
->X_add_number
< REG_P
+ 64)
5198 return OPERAND_MATCH
;
5204 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
5205 && e
->X_add_number
< REG_GR
+ 128)
5206 return OPERAND_MATCH
;
5209 case IA64_OPND_R3_2
:
5210 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5212 if (e
->X_add_number
< REG_GR
+ 4)
5213 return OPERAND_MATCH
;
5214 else if (e
->X_add_number
< REG_GR
+ 128)
5215 return OPERAND_OUT_OF_RANGE
;
5219 /* indirect operands: */
5220 case IA64_OPND_CPUID_R3
:
5221 case IA64_OPND_DBR_R3
:
5222 case IA64_OPND_DTR_R3
:
5223 case IA64_OPND_ITR_R3
:
5224 case IA64_OPND_IBR_R3
:
5225 case IA64_OPND_MSR_R3
:
5226 case IA64_OPND_PKR_R3
:
5227 case IA64_OPND_PMC_R3
:
5228 case IA64_OPND_PMD_R3
:
5229 case IA64_OPND_RR_R3
:
5230 if (e
->X_op
== O_index
&& e
->X_op_symbol
5231 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5232 == opnd
- IA64_OPND_CPUID_R3
))
5233 return OPERAND_MATCH
;
5237 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5238 return OPERAND_MATCH
;
5241 /* immediate operands: */
5242 case IA64_OPND_CNT2a
:
5243 case IA64_OPND_LEN4
:
5244 case IA64_OPND_LEN6
:
5245 bits
= operand_width (idesc
->operands
[index
]);
5246 if (e
->X_op
== O_constant
)
5248 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5249 return OPERAND_MATCH
;
5251 return OPERAND_OUT_OF_RANGE
;
5255 case IA64_OPND_CNT2b
:
5256 if (e
->X_op
== O_constant
)
5258 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5259 return OPERAND_MATCH
;
5261 return OPERAND_OUT_OF_RANGE
;
5265 case IA64_OPND_CNT2c
:
5266 val
= e
->X_add_number
;
5267 if (e
->X_op
== O_constant
)
5269 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5270 return OPERAND_MATCH
;
5272 return OPERAND_OUT_OF_RANGE
;
5277 /* SOR must be an integer multiple of 8 */
5278 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5279 return OPERAND_OUT_OF_RANGE
;
5282 if (e
->X_op
== O_constant
)
5284 if ((bfd_vma
) e
->X_add_number
<= 96)
5285 return OPERAND_MATCH
;
5287 return OPERAND_OUT_OF_RANGE
;
5291 case IA64_OPND_IMMU62
:
5292 if (e
->X_op
== O_constant
)
5294 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5295 return OPERAND_MATCH
;
5297 return OPERAND_OUT_OF_RANGE
;
5301 /* FIXME -- need 62-bit relocation type */
5302 as_bad (_("62-bit relocation not yet implemented"));
5306 case IA64_OPND_IMMU64
:
5307 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5308 || e
->X_op
== O_subtract
)
5310 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5311 fix
->code
= BFD_RELOC_IA64_IMM64
;
5312 if (e
->X_op
!= O_subtract
)
5314 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5315 if (e
->X_op
== O_pseudo_fixup
)
5319 fix
->opnd
= idesc
->operands
[index
];
5322 ++CURR_SLOT
.num_fixups
;
5323 return OPERAND_MATCH
;
5325 else if (e
->X_op
== O_constant
)
5326 return OPERAND_MATCH
;
5329 case IA64_OPND_CCNT5
:
5330 case IA64_OPND_CNT5
:
5331 case IA64_OPND_CNT6
:
5332 case IA64_OPND_CPOS6a
:
5333 case IA64_OPND_CPOS6b
:
5334 case IA64_OPND_CPOS6c
:
5335 case IA64_OPND_IMMU2
:
5336 case IA64_OPND_IMMU7a
:
5337 case IA64_OPND_IMMU7b
:
5338 case IA64_OPND_IMMU21
:
5339 case IA64_OPND_IMMU24
:
5340 case IA64_OPND_MBTYPE4
:
5341 case IA64_OPND_MHTYPE8
:
5342 case IA64_OPND_POS6
:
5343 bits
= operand_width (idesc
->operands
[index
]);
5344 if (e
->X_op
== O_constant
)
5346 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5347 return OPERAND_MATCH
;
5349 return OPERAND_OUT_OF_RANGE
;
5353 case IA64_OPND_IMMU9
:
5354 bits
= operand_width (idesc
->operands
[index
]);
5355 if (e
->X_op
== O_constant
)
5357 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5359 int lobits
= e
->X_add_number
& 0x3;
5360 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5361 e
->X_add_number
|= (bfd_vma
) 0x3;
5362 return OPERAND_MATCH
;
5365 return OPERAND_OUT_OF_RANGE
;
5369 case IA64_OPND_IMM44
:
5370 /* least 16 bits must be zero */
5371 if ((e
->X_add_number
& 0xffff) != 0)
5372 /* XXX technically, this is wrong: we should not be issuing warning
5373 messages until we're sure this instruction pattern is going to
5375 as_warn (_("lower 16 bits of mask ignored"));
5377 if (e
->X_op
== O_constant
)
5379 if (((e
->X_add_number
>= 0
5380 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5381 || (e
->X_add_number
< 0
5382 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5385 if (e
->X_add_number
>= 0
5386 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5388 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5390 return OPERAND_MATCH
;
5393 return OPERAND_OUT_OF_RANGE
;
5397 case IA64_OPND_IMM17
:
5398 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5399 if (e
->X_op
== O_constant
)
5401 if (((e
->X_add_number
>= 0
5402 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5403 || (e
->X_add_number
< 0
5404 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5407 if (e
->X_add_number
>= 0
5408 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5410 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5412 return OPERAND_MATCH
;
5415 return OPERAND_OUT_OF_RANGE
;
5419 case IA64_OPND_IMM14
:
5420 case IA64_OPND_IMM22
:
5422 case IA64_OPND_IMM1
:
5423 case IA64_OPND_IMM8
:
5424 case IA64_OPND_IMM8U4
:
5425 case IA64_OPND_IMM8M1
:
5426 case IA64_OPND_IMM8M1U4
:
5427 case IA64_OPND_IMM8M1U8
:
5428 case IA64_OPND_IMM9a
:
5429 case IA64_OPND_IMM9b
:
5430 bits
= operand_width (idesc
->operands
[index
]);
5431 if (relocatable
&& (e
->X_op
== O_symbol
5432 || e
->X_op
== O_subtract
5433 || e
->X_op
== O_pseudo_fixup
))
5435 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5437 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5438 fix
->code
= BFD_RELOC_IA64_IMM14
;
5440 fix
->code
= BFD_RELOC_IA64_IMM22
;
5442 if (e
->X_op
!= O_subtract
)
5444 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5445 if (e
->X_op
== O_pseudo_fixup
)
5449 fix
->opnd
= idesc
->operands
[index
];
5452 ++CURR_SLOT
.num_fixups
;
5453 return OPERAND_MATCH
;
5455 else if (e
->X_op
!= O_constant
5456 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5457 return OPERAND_MISMATCH
;
5459 if (opnd
== IA64_OPND_IMM8M1U4
)
5461 /* Zero is not valid for unsigned compares that take an adjusted
5462 constant immediate range. */
5463 if (e
->X_add_number
== 0)
5464 return OPERAND_OUT_OF_RANGE
;
5466 /* Sign-extend 32-bit unsigned numbers, so that the following range
5467 checks will work. */
5468 val
= e
->X_add_number
;
5469 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5470 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5471 val
= ((val
<< 32) >> 32);
5473 /* Check for 0x100000000. This is valid because
5474 0x100000000-1 is the same as ((uint32_t) -1). */
5475 if (val
== ((bfd_signed_vma
) 1 << 32))
5476 return OPERAND_MATCH
;
5480 else if (opnd
== IA64_OPND_IMM8M1U8
)
5482 /* Zero is not valid for unsigned compares that take an adjusted
5483 constant immediate range. */
5484 if (e
->X_add_number
== 0)
5485 return OPERAND_OUT_OF_RANGE
;
5487 /* Check for 0x10000000000000000. */
5488 if (e
->X_op
== O_big
)
5490 if (generic_bignum
[0] == 0
5491 && generic_bignum
[1] == 0
5492 && generic_bignum
[2] == 0
5493 && generic_bignum
[3] == 0
5494 && generic_bignum
[4] == 1)
5495 return OPERAND_MATCH
;
5497 return OPERAND_OUT_OF_RANGE
;
5500 val
= e
->X_add_number
- 1;
5502 else if (opnd
== IA64_OPND_IMM8M1
)
5503 val
= e
->X_add_number
- 1;
5504 else if (opnd
== IA64_OPND_IMM8U4
)
5506 /* Sign-extend 32-bit unsigned numbers, so that the following range
5507 checks will work. */
5508 val
= e
->X_add_number
;
5509 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5510 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5511 val
= ((val
<< 32) >> 32);
5514 val
= e
->X_add_number
;
5516 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5517 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5518 return OPERAND_MATCH
;
5520 return OPERAND_OUT_OF_RANGE
;
5522 case IA64_OPND_INC3
:
5523 /* +/- 1, 4, 8, 16 */
5524 val
= e
->X_add_number
;
5527 if (e
->X_op
== O_constant
)
5529 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5530 return OPERAND_MATCH
;
5532 return OPERAND_OUT_OF_RANGE
;
5536 case IA64_OPND_TGT25
:
5537 case IA64_OPND_TGT25b
:
5538 case IA64_OPND_TGT25c
:
5539 case IA64_OPND_TGT64
:
5540 if (e
->X_op
== O_symbol
)
5542 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5543 if (opnd
== IA64_OPND_TGT25
)
5544 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5545 else if (opnd
== IA64_OPND_TGT25b
)
5546 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5547 else if (opnd
== IA64_OPND_TGT25c
)
5548 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5549 else if (opnd
== IA64_OPND_TGT64
)
5550 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5554 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5555 fix
->opnd
= idesc
->operands
[index
];
5558 ++CURR_SLOT
.num_fixups
;
5559 return OPERAND_MATCH
;
5561 case IA64_OPND_TAG13
:
5562 case IA64_OPND_TAG13b
:
5566 return OPERAND_MATCH
;
5569 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5570 /* There are no external relocs for TAG13/TAG13b fields, so we
5571 create a dummy reloc. This will not live past md_apply_fix3. */
5572 fix
->code
= BFD_RELOC_UNUSED
;
5573 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5574 fix
->opnd
= idesc
->operands
[index
];
5577 ++CURR_SLOT
.num_fixups
;
5578 return OPERAND_MATCH
;
5585 case IA64_OPND_LDXMOV
:
5586 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5587 fix
->code
= BFD_RELOC_IA64_LDXMOV
;
5588 fix
->opnd
= idesc
->operands
[index
];
5591 ++CURR_SLOT
.num_fixups
;
5592 return OPERAND_MATCH
;
5597 return OPERAND_MISMATCH
;
5606 memset (e
, 0, sizeof (*e
));
5609 if (*input_line_pointer
!= '}')
5611 sep
= *input_line_pointer
++;
5615 if (!md
.manual_bundling
)
5616 as_warn ("Found '}' when manual bundling is off");
5618 CURR_SLOT
.manual_bundling_off
= 1;
5619 md
.manual_bundling
= 0;
5625 /* Returns the next entry in the opcode table that matches the one in
5626 IDESC, and frees the entry in IDESC. If no matching entry is
5627 found, NULL is returned instead. */
5629 static struct ia64_opcode
*
5630 get_next_opcode (struct ia64_opcode
*idesc
)
5632 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5633 ia64_free_opcode (idesc
);
5637 /* Parse the operands for the opcode and find the opcode variant that
5638 matches the specified operands, or NULL if no match is possible. */
5640 static struct ia64_opcode
*
5641 parse_operands (idesc
)
5642 struct ia64_opcode
*idesc
;
5644 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5645 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5646 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5647 enum operand_match_result result
;
5649 char *first_arg
= 0, *end
, *saved_input_pointer
;
5652 assert (strlen (idesc
->name
) <= 128);
5654 strcpy (mnemonic
, idesc
->name
);
5655 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5657 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5658 can't parse the first operand until we have parsed the
5659 remaining operands of the "alloc" instruction. */
5661 first_arg
= input_line_pointer
;
5662 end
= strchr (input_line_pointer
, '=');
5665 as_bad ("Expected separator `='");
5668 input_line_pointer
= end
+ 1;
5673 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5675 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5676 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5681 if (sep
!= '=' && sep
!= ',')
5686 if (num_outputs
> 0)
5687 as_bad ("Duplicate equal sign (=) in instruction");
5689 num_outputs
= i
+ 1;
5694 as_bad ("Illegal operand separator `%c'", sep
);
5698 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5700 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5701 know (strcmp (idesc
->name
, "alloc") == 0);
5702 if (num_operands
== 5 /* first_arg not included in this count! */
5703 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5704 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5705 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5706 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5708 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5709 CURR_SLOT
.opnd
[3].X_add_number
,
5710 CURR_SLOT
.opnd
[4].X_add_number
,
5711 CURR_SLOT
.opnd
[5].X_add_number
);
5713 /* now we can parse the first arg: */
5714 saved_input_pointer
= input_line_pointer
;
5715 input_line_pointer
= first_arg
;
5716 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5718 --num_outputs
; /* force error */
5719 input_line_pointer
= saved_input_pointer
;
5721 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5722 CURR_SLOT
.opnd
[3].X_add_number
5723 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5724 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5728 highest_unmatched_operand
= 0;
5729 curr_out_of_range_pos
= -1;
5731 expected_operand
= idesc
->operands
[0];
5732 for (; idesc
; idesc
= get_next_opcode (idesc
))
5734 if (num_outputs
!= idesc
->num_outputs
)
5735 continue; /* mismatch in # of outputs */
5737 CURR_SLOT
.num_fixups
= 0;
5739 /* Try to match all operands. If we see an out-of-range operand,
5740 then continue trying to match the rest of the operands, since if
5741 the rest match, then this idesc will give the best error message. */
5743 out_of_range_pos
= -1;
5744 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5746 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5747 if (result
!= OPERAND_MATCH
)
5749 if (result
!= OPERAND_OUT_OF_RANGE
)
5751 if (out_of_range_pos
< 0)
5752 /* remember position of the first out-of-range operand: */
5753 out_of_range_pos
= i
;
5757 /* If we did not match all operands, or if at least one operand was
5758 out-of-range, then this idesc does not match. Keep track of which
5759 idesc matched the most operands before failing. If we have two
5760 idescs that failed at the same position, and one had an out-of-range
5761 operand, then prefer the out-of-range operand. Thus if we have
5762 "add r0=0x1000000,r1" we get an error saying the constant is out
5763 of range instead of an error saying that the constant should have been
5766 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5768 if (i
> highest_unmatched_operand
5769 || (i
== highest_unmatched_operand
5770 && out_of_range_pos
> curr_out_of_range_pos
))
5772 highest_unmatched_operand
= i
;
5773 if (out_of_range_pos
>= 0)
5775 expected_operand
= idesc
->operands
[out_of_range_pos
];
5776 error_pos
= out_of_range_pos
;
5780 expected_operand
= idesc
->operands
[i
];
5783 curr_out_of_range_pos
= out_of_range_pos
;
5788 if (num_operands
< NELEMS (idesc
->operands
)
5789 && idesc
->operands
[num_operands
])
5790 continue; /* mismatch in number of arguments */
5796 if (expected_operand
)
5797 as_bad ("Operand %u of `%s' should be %s",
5798 error_pos
+ 1, mnemonic
,
5799 elf64_ia64_operands
[expected_operand
].desc
);
5801 as_bad ("Operand mismatch");
5807 /* Keep track of state necessary to determine whether a NOP is necessary
5808 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5809 detect a case where additional NOPs may be necessary. */
5811 errata_nop_necessary_p (slot
, insn_unit
)
5813 enum ia64_unit insn_unit
;
5816 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5817 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5818 struct ia64_opcode
*idesc
= slot
->idesc
;
5820 /* Test whether this could be the first insn in a problematic sequence. */
5821 if (insn_unit
== IA64_UNIT_F
)
5823 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5824 if (idesc
->operands
[i
] == IA64_OPND_P1
5825 || idesc
->operands
[i
] == IA64_OPND_P2
)
5827 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5828 /* Ignore invalid operands; they generate errors elsewhere. */
5831 this_group
->p_reg_set
[regno
] = 1;
5835 /* Test whether this could be the second insn in a problematic sequence. */
5836 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5837 && prev_group
->p_reg_set
[slot
->qp_regno
])
5839 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5840 if (idesc
->operands
[i
] == IA64_OPND_R1
5841 || idesc
->operands
[i
] == IA64_OPND_R2
5842 || idesc
->operands
[i
] == IA64_OPND_R3
)
5844 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5845 /* Ignore invalid operands; they generate errors elsewhere. */
5848 if (strncmp (idesc
->name
, "add", 3) != 0
5849 && strncmp (idesc
->name
, "sub", 3) != 0
5850 && strncmp (idesc
->name
, "shladd", 6) != 0
5851 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5852 this_group
->g_reg_set_conditionally
[regno
] = 1;
5856 /* Test whether this could be the third insn in a problematic sequence. */
5857 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5859 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5860 idesc
->operands
[i
] == IA64_OPND_R3
5861 /* For mov indirect. */
5862 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5863 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5864 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5865 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5866 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5867 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5868 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5869 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5871 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5872 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5873 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5874 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5876 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5877 /* Ignore invalid operands; they generate errors elsewhere. */
5880 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5882 if (strcmp (idesc
->name
, "fc") != 0
5883 && strcmp (idesc
->name
, "tak") != 0
5884 && strcmp (idesc
->name
, "thash") != 0
5885 && strcmp (idesc
->name
, "tpa") != 0
5886 && strcmp (idesc
->name
, "ttag") != 0
5887 && strncmp (idesc
->name
, "ptr", 3) != 0
5888 && strncmp (idesc
->name
, "ptc", 3) != 0
5889 && strncmp (idesc
->name
, "probe", 5) != 0)
5892 if (prev_group
->g_reg_set_conditionally
[regno
])
5900 build_insn (slot
, insnp
)
5904 const struct ia64_operand
*odesc
, *o2desc
;
5905 struct ia64_opcode
*idesc
= slot
->idesc
;
5906 bfd_signed_vma insn
, val
;
5910 insn
= idesc
->opcode
| slot
->qp_regno
;
5912 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5914 if (slot
->opnd
[i
].X_op
== O_register
5915 || slot
->opnd
[i
].X_op
== O_constant
5916 || slot
->opnd
[i
].X_op
== O_index
)
5917 val
= slot
->opnd
[i
].X_add_number
;
5918 else if (slot
->opnd
[i
].X_op
== O_big
)
5920 /* This must be the value 0x10000000000000000. */
5921 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5927 switch (idesc
->operands
[i
])
5929 case IA64_OPND_IMMU64
:
5930 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5931 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5932 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5933 | (((val
>> 63) & 0x1) << 36));
5936 case IA64_OPND_IMMU62
:
5937 val
&= 0x3fffffffffffffffULL
;
5938 if (val
!= slot
->opnd
[i
].X_add_number
)
5939 as_warn (_("Value truncated to 62 bits"));
5940 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5941 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5944 case IA64_OPND_TGT64
:
5946 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5947 insn
|= ((((val
>> 59) & 0x1) << 36)
5948 | (((val
>> 0) & 0xfffff) << 13));
5979 case IA64_OPND_R3_2
:
5980 case IA64_OPND_CPUID_R3
:
5981 case IA64_OPND_DBR_R3
:
5982 case IA64_OPND_DTR_R3
:
5983 case IA64_OPND_ITR_R3
:
5984 case IA64_OPND_IBR_R3
:
5986 case IA64_OPND_MSR_R3
:
5987 case IA64_OPND_PKR_R3
:
5988 case IA64_OPND_PMC_R3
:
5989 case IA64_OPND_PMD_R3
:
5990 case IA64_OPND_RR_R3
:
5998 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5999 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
6001 as_bad_where (slot
->src_file
, slot
->src_line
,
6002 "Bad operand value: %s", err
);
6003 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
6005 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
6006 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
6008 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
6009 (*o2desc
->insert
) (o2desc
, val
, &insn
);
6011 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
6012 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
6013 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
6015 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
6016 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
6026 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
6027 unsigned int manual_bundling
= 0;
6028 enum ia64_unit required_unit
, insn_unit
= 0;
6029 enum ia64_insn_type type
[3], insn_type
;
6030 unsigned int template, orig_template
;
6031 bfd_vma insn
[3] = { -1, -1, -1 };
6032 struct ia64_opcode
*idesc
;
6033 int end_of_insn_group
= 0, user_template
= -1;
6034 int n
, i
, j
, first
, curr
;
6036 bfd_vma t0
= 0, t1
= 0;
6037 struct label_fix
*lfix
;
6038 struct insn_fix
*ifix
;
6043 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
6044 know (first
>= 0 & first
< NUM_SLOTS
);
6045 n
= MIN (3, md
.num_slots_in_use
);
6047 /* Determine template: user user_template if specified, best match
6050 if (md
.slot
[first
].user_template
>= 0)
6051 user_template
= template = md
.slot
[first
].user_template
;
6054 /* Auto select appropriate template. */
6055 memset (type
, 0, sizeof (type
));
6057 for (i
= 0; i
< n
; ++i
)
6059 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
6061 type
[i
] = md
.slot
[curr
].idesc
->type
;
6062 curr
= (curr
+ 1) % NUM_SLOTS
;
6064 template = best_template
[type
[0]][type
[1]][type
[2]];
6067 /* initialize instructions with appropriate nops: */
6068 for (i
= 0; i
< 3; ++i
)
6069 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
6073 /* now fill in slots with as many insns as possible: */
6075 idesc
= md
.slot
[curr
].idesc
;
6076 end_of_insn_group
= 0;
6077 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
6079 /* Set the slot number for prologue/body records now as those
6080 refer to the current point, not the point after the
6081 instruction has been issued: */
6082 /* Don't try to delete prologue/body records here, as that will cause
6083 them to also be deleted from the master list of unwind records. */
6084 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6085 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
6086 || ptr
->r
.type
== body
)
6088 ptr
->slot_number
= (unsigned long) f
+ i
;
6089 ptr
->slot_frag
= frag_now
;
6092 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
6094 if (manual_bundling
&& i
!= 2)
6095 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6096 "`%s' must be last in bundle", idesc
->name
);
6100 if (idesc
->flags
& IA64_OPCODE_LAST
)
6103 unsigned int required_template
;
6105 /* If we need a stop bit after an M slot, our only choice is
6106 template 5 (M;;MI). If we need a stop bit after a B
6107 slot, our only choice is to place it at the end of the
6108 bundle, because the only available templates are MIB,
6109 MBB, BBB, MMB, and MFB. We don't handle anything other
6110 than M and B slots because these are the only kind of
6111 instructions that can have the IA64_OPCODE_LAST bit set. */
6112 required_template
= template;
6113 switch (idesc
->type
)
6117 required_template
= 5;
6125 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6126 "Internal error: don't know how to force %s to end"
6127 "of instruction group", idesc
->name
);
6131 if (manual_bundling
&& i
!= required_slot
)
6132 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6133 "`%s' must be last in instruction group",
6135 if (required_slot
< i
)
6136 /* Can't fit this instruction. */
6140 if (required_template
!= template)
6142 /* If we switch the template, we need to reset the NOPs
6143 after slot i. The slot-types of the instructions ahead
6144 of i never change, so we don't need to worry about
6145 changing NOPs in front of this slot. */
6146 for (j
= i
; j
< 3; ++j
)
6147 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
6149 template = required_template
;
6151 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
6153 if (manual_bundling_on
)
6154 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6155 "Label must be first in a bundle");
6156 /* This insn must go into the first slot of a bundle. */
6160 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
6161 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
6163 if (manual_bundling_on
)
6166 manual_bundling
= 1;
6168 break; /* need to start a new bundle */
6171 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
6173 /* We need an instruction group boundary in the middle of a
6174 bundle. See if we can switch to an other template with
6175 an appropriate boundary. */
6177 orig_template
= template;
6178 if (i
== 1 && (user_template
== 4
6179 || (user_template
< 0
6180 && (ia64_templ_desc
[template].exec_unit
[0]
6184 end_of_insn_group
= 0;
6186 else if (i
== 2 && (user_template
== 0
6187 || (user_template
< 0
6188 && (ia64_templ_desc
[template].exec_unit
[1]
6190 /* This test makes sure we don't switch the template if
6191 the next instruction is one that needs to be first in
6192 an instruction group. Since all those instructions are
6193 in the M group, there is no way such an instruction can
6194 fit in this bundle even if we switch the template. The
6195 reason we have to check for this is that otherwise we
6196 may end up generating "MI;;I M.." which has the deadly
6197 effect that the second M instruction is no longer the
6198 first in the bundle! --davidm 99/12/16 */
6199 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
6202 end_of_insn_group
= 0;
6204 else if (curr
!= first
)
6205 /* can't fit this insn */
6208 if (template != orig_template
)
6209 /* if we switch the template, we need to reset the NOPs
6210 after slot i. The slot-types of the instructions ahead
6211 of i never change, so we don't need to worry about
6212 changing NOPs in front of this slot. */
6213 for (j
= i
; j
< 3; ++j
)
6214 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
6216 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6218 /* resolve dynamic opcodes such as "break", "hint", and "nop": */
6219 if (idesc
->type
== IA64_TYPE_DYN
)
6221 if ((strcmp (idesc
->name
, "nop") == 0)
6222 || (strcmp (idesc
->name
, "hint") == 0)
6223 || (strcmp (idesc
->name
, "break") == 0))
6224 insn_unit
= required_unit
;
6225 else if (strcmp (idesc
->name
, "chk.s") == 0)
6227 insn_unit
= IA64_UNIT_M
;
6228 if (required_unit
== IA64_UNIT_I
)
6229 insn_unit
= IA64_UNIT_I
;
6232 as_fatal ("emit_one_bundle: unexpected dynamic op");
6234 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6235 ia64_free_opcode (idesc
);
6236 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6238 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6243 insn_type
= idesc
->type
;
6244 insn_unit
= IA64_UNIT_NIL
;
6248 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6249 insn_unit
= required_unit
;
6251 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6252 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6253 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6254 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6255 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6260 if (insn_unit
!= required_unit
)
6262 if (required_unit
== IA64_UNIT_L
6263 && insn_unit
== IA64_UNIT_I
6264 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6266 /* we got ourselves an MLX template but the current
6267 instruction isn't an X-unit, or an I-unit instruction
6268 that can go into the X slot of an MLX template. Duh. */
6269 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6271 as_bad_where (md
.slot
[curr
].src_file
,
6272 md
.slot
[curr
].src_line
,
6273 "`%s' can't go in X slot of "
6274 "MLX template", idesc
->name
);
6275 /* drop this insn so we don't livelock: */
6276 --md
.num_slots_in_use
;
6280 continue; /* try next slot */
6286 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6287 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6290 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6291 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6293 build_insn (md
.slot
+ curr
, insn
+ i
);
6295 /* Set slot counts for non prologue/body unwind records. */
6296 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6297 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6298 && ptr
->r
.type
!= body
)
6300 ptr
->slot_number
= (unsigned long) f
+ i
;
6301 ptr
->slot_frag
= frag_now
;
6303 md
.slot
[curr
].unwind_record
= NULL
;
6305 if (required_unit
== IA64_UNIT_L
)
6308 /* skip one slot for long/X-unit instructions */
6311 --md
.num_slots_in_use
;
6313 /* now is a good time to fix up the labels for this insn: */
6314 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6316 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6317 symbol_set_frag (lfix
->sym
, frag_now
);
6319 /* and fix up the tags also. */
6320 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6322 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6323 symbol_set_frag (lfix
->sym
, frag_now
);
6326 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6328 ifix
= md
.slot
[curr
].fixup
+ j
;
6329 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6330 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6331 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6332 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6333 fix
->fx_file
= md
.slot
[curr
].src_file
;
6334 fix
->fx_line
= md
.slot
[curr
].src_line
;
6337 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6339 if (end_of_insn_group
)
6341 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6342 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6346 ia64_free_opcode (md
.slot
[curr
].idesc
);
6347 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6348 md
.slot
[curr
].user_template
= -1;
6350 if (manual_bundling_off
)
6352 manual_bundling
= 0;
6355 curr
= (curr
+ 1) % NUM_SLOTS
;
6356 idesc
= md
.slot
[curr
].idesc
;
6358 if (manual_bundling
)
6360 if (md
.num_slots_in_use
> 0)
6361 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6362 "`%s' does not fit into %s template",
6363 idesc
->name
, ia64_templ_desc
[template].name
);
6365 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6366 "Missing '}' at end of file");
6368 know (md
.num_slots_in_use
< NUM_SLOTS
);
6370 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6371 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6373 number_to_chars_littleendian (f
+ 0, t0
, 8);
6374 number_to_chars_littleendian (f
+ 8, t1
, 8);
6376 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6377 unwind
.next_slot_frag
= frag_now
;
6381 md_parse_option (c
, arg
)
6388 /* Switches from the Intel assembler. */
6390 if (strcmp (arg
, "ilp64") == 0
6391 || strcmp (arg
, "lp64") == 0
6392 || strcmp (arg
, "p64") == 0)
6394 md
.flags
|= EF_IA_64_ABI64
;
6396 else if (strcmp (arg
, "ilp32") == 0)
6398 md
.flags
&= ~EF_IA_64_ABI64
;
6400 else if (strcmp (arg
, "le") == 0)
6402 md
.flags
&= ~EF_IA_64_BE
;
6404 else if (strcmp (arg
, "be") == 0)
6406 md
.flags
|= EF_IA_64_BE
;
6413 if (strcmp (arg
, "so") == 0)
6415 /* Suppress signon message. */
6417 else if (strcmp (arg
, "pi") == 0)
6419 /* Reject privileged instructions. FIXME */
6421 else if (strcmp (arg
, "us") == 0)
6423 /* Allow union of signed and unsigned range. FIXME */
6425 else if (strcmp (arg
, "close_fcalls") == 0)
6427 /* Do not resolve global function calls. */
6434 /* temp[="prefix"] Insert temporary labels into the object file
6435 symbol table prefixed by "prefix".
6436 Default prefix is ":temp:".
6441 /* indirect=<tgt> Assume unannotated indirect branches behavior
6442 according to <tgt> --
6443 exit: branch out from the current context (default)
6444 labels: all labels in context may be branch targets
6446 if (strncmp (arg
, "indirect=", 9) != 0)
6451 /* -X conflicts with an ignored option, use -x instead */
6453 if (!arg
|| strcmp (arg
, "explicit") == 0)
6455 /* set default mode to explicit */
6456 md
.default_explicit_mode
= 1;
6459 else if (strcmp (arg
, "auto") == 0)
6461 md
.default_explicit_mode
= 0;
6463 else if (strcmp (arg
, "debug") == 0)
6467 else if (strcmp (arg
, "debugx") == 0)
6469 md
.default_explicit_mode
= 1;
6474 as_bad (_("Unrecognized option '-x%s'"), arg
);
6479 /* nops Print nops statistics. */
6482 /* GNU specific switches for gcc. */
6483 case OPTION_MCONSTANT_GP
:
6484 md
.flags
|= EF_IA_64_CONS_GP
;
6487 case OPTION_MAUTO_PIC
:
6488 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6499 md_show_usage (stream
)
6504 --mconstant-gp mark output file as using the constant-GP model\n\
6505 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6506 --mauto-pic mark output file as using the constant-GP model\n\
6507 without function descriptors (sets ELF header flag\n\
6508 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
6509 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6510 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6511 -x | -xexplicit turn on dependency violation checking (default)\n\
6512 -xauto automagically remove dependency violations\n\
6513 -xdebug debug dependency violation checker\n"),
6518 ia64_after_parse_args ()
6520 if (debug_type
== DEBUG_STABS
)
6521 as_fatal (_("--gstabs is not supported for ia64"));
6524 /* Return true if TYPE fits in TEMPL at SLOT. */
6527 match (int templ
, int type
, int slot
)
6529 enum ia64_unit unit
;
6532 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6535 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6537 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6539 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6540 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6541 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6542 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6543 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6544 default: result
= 0; break;
6549 /* Add a bit of extra goodness if a nop of type F or B would fit
6550 in TEMPL at SLOT. */
6553 extra_goodness (int templ
, int slot
)
6555 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6557 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6562 /* This function is called once, at assembler startup time. It sets
6563 up all the tables, etc. that the MD part of the assembler will need
6564 that can be determined before arguments are parsed. */
6568 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6573 md
.explicit_mode
= md
.default_explicit_mode
;
6575 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6577 /* Make sure fucntion pointers get initialized. */
6578 target_big_endian
= -1;
6579 dot_byteorder (TARGET_BYTES_BIG_ENDIAN
);
6581 pseudo_func
[FUNC_DTP_MODULE
].u
.sym
=
6582 symbol_new (".<dtpmod>", undefined_section
, FUNC_DTP_MODULE
,
6583 &zero_address_frag
);
6585 pseudo_func
[FUNC_DTP_RELATIVE
].u
.sym
=
6586 symbol_new (".<dtprel>", undefined_section
, FUNC_DTP_RELATIVE
,
6587 &zero_address_frag
);
6589 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6590 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6591 &zero_address_frag
);
6593 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6594 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6595 &zero_address_frag
);
6597 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6598 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6599 &zero_address_frag
);
6601 pseudo_func
[FUNC_LT_RELATIVE_X
].u
.sym
=
6602 symbol_new (".<ltoffx>", undefined_section
, FUNC_LT_RELATIVE_X
,
6603 &zero_address_frag
);
6605 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6606 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6607 &zero_address_frag
);
6609 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6610 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6611 &zero_address_frag
);
6613 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6614 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6615 &zero_address_frag
);
6617 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6618 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6619 &zero_address_frag
);
6621 pseudo_func
[FUNC_TP_RELATIVE
].u
.sym
=
6622 symbol_new (".<tprel>", undefined_section
, FUNC_TP_RELATIVE
,
6623 &zero_address_frag
);
6625 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6626 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6627 &zero_address_frag
);
6629 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6630 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6631 &zero_address_frag
);
6633 pseudo_func
[FUNC_LT_DTP_MODULE
].u
.sym
=
6634 symbol_new (".<ltoff.dtpmod>", undefined_section
, FUNC_LT_DTP_MODULE
,
6635 &zero_address_frag
);
6637 pseudo_func
[FUNC_LT_DTP_RELATIVE
].u
.sym
=
6638 symbol_new (".<ltoff.dptrel>", undefined_section
, FUNC_LT_DTP_RELATIVE
,
6639 &zero_address_frag
);
6641 pseudo_func
[FUNC_LT_TP_RELATIVE
].u
.sym
=
6642 symbol_new (".<ltoff.tprel>", undefined_section
, FUNC_LT_TP_RELATIVE
,
6643 &zero_address_frag
);
6645 pseudo_func
[FUNC_IPLT_RELOC
].u
.sym
=
6646 symbol_new (".<iplt>", undefined_section
, FUNC_IPLT_RELOC
,
6647 &zero_address_frag
);
6649 /* Compute the table of best templates. We compute goodness as a
6650 base 4 value, in which each match counts for 3, each F counts
6651 for 2, each B counts for 1. This should maximize the number of
6652 F and B nops in the chosen bundles, which is good because these
6653 pipelines are least likely to be overcommitted. */
6654 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6655 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6656 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6659 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6662 if (match (t
, i
, 0))
6664 if (match (t
, j
, 1))
6666 if (match (t
, k
, 2))
6667 goodness
= 3 + 3 + 3;
6669 goodness
= 3 + 3 + extra_goodness (t
, 2);
6671 else if (match (t
, j
, 2))
6672 goodness
= 3 + 3 + extra_goodness (t
, 1);
6676 goodness
+= extra_goodness (t
, 1);
6677 goodness
+= extra_goodness (t
, 2);
6680 else if (match (t
, i
, 1))
6682 if (match (t
, j
, 2))
6685 goodness
= 3 + extra_goodness (t
, 2);
6687 else if (match (t
, i
, 2))
6688 goodness
= 3 + extra_goodness (t
, 1);
6690 if (goodness
> best
)
6693 best_template
[i
][j
][k
] = t
;
6698 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6699 md
.slot
[i
].user_template
= -1;
6701 md
.pseudo_hash
= hash_new ();
6702 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6704 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6705 (void *) (pseudo_opcode
+ i
));
6707 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6708 pseudo_opcode
[i
].name
, err
);
6711 md
.reg_hash
= hash_new ();
6712 md
.dynreg_hash
= hash_new ();
6713 md
.const_hash
= hash_new ();
6714 md
.entry_hash
= hash_new ();
6716 /* general registers: */
6719 for (i
= 0; i
< total
; ++i
)
6721 sprintf (name
, "r%d", i
- REG_GR
);
6722 md
.regsym
[i
] = declare_register (name
, i
);
6725 /* floating point registers: */
6727 for (; i
< total
; ++i
)
6729 sprintf (name
, "f%d", i
- REG_FR
);
6730 md
.regsym
[i
] = declare_register (name
, i
);
6733 /* application registers: */
6736 for (; i
< total
; ++i
)
6738 sprintf (name
, "ar%d", i
- REG_AR
);
6739 md
.regsym
[i
] = declare_register (name
, i
);
6742 /* control registers: */
6745 for (; i
< total
; ++i
)
6747 sprintf (name
, "cr%d", i
- REG_CR
);
6748 md
.regsym
[i
] = declare_register (name
, i
);
6751 /* predicate registers: */
6753 for (; i
< total
; ++i
)
6755 sprintf (name
, "p%d", i
- REG_P
);
6756 md
.regsym
[i
] = declare_register (name
, i
);
6759 /* branch registers: */
6761 for (; i
< total
; ++i
)
6763 sprintf (name
, "b%d", i
- REG_BR
);
6764 md
.regsym
[i
] = declare_register (name
, i
);
6767 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6768 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6769 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6770 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6771 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6772 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6773 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6775 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6777 regnum
= indirect_reg
[i
].regnum
;
6778 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6781 /* define synonyms for application registers: */
6782 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6783 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6784 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6786 /* define synonyms for control registers: */
6787 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6788 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6789 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6791 declare_register ("gp", REG_GR
+ 1);
6792 declare_register ("sp", REG_GR
+ 12);
6793 declare_register ("rp", REG_BR
+ 0);
6795 /* pseudo-registers used to specify unwind info: */
6796 declare_register ("psp", REG_PSP
);
6798 declare_register_set ("ret", 4, REG_GR
+ 8);
6799 declare_register_set ("farg", 8, REG_FR
+ 8);
6800 declare_register_set ("fret", 8, REG_FR
+ 8);
6802 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6804 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6805 (PTR
) (const_bits
+ i
));
6807 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6811 /* Set the architecture and machine depending on defaults and command line
6813 if (md
.flags
& EF_IA_64_ABI64
)
6814 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6816 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6819 as_warn (_("Could not set architecture and machine"));
6821 /* Set the pointer size and pointer shift size depending on md.flags */
6823 if (md
.flags
& EF_IA_64_ABI64
)
6825 md
.pointer_size
= 8; /* pointers are 8 bytes */
6826 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6830 md
.pointer_size
= 4; /* pointers are 4 bytes */
6831 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6834 md
.mem_offset
.hint
= 0;
6837 md
.entry_labels
= NULL
;
6840 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6841 because that is called after md_parse_option which is where we do the
6842 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6843 default endianness. */
6846 ia64_init (argc
, argv
)
6847 int argc ATTRIBUTE_UNUSED
;
6848 char **argv ATTRIBUTE_UNUSED
;
6850 md
.flags
= MD_FLAGS_DEFAULT
;
6853 /* Return a string for the target object file format. */
6856 ia64_target_format ()
6858 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6860 if (md
.flags
& EF_IA_64_BE
)
6862 if (md
.flags
& EF_IA_64_ABI64
)
6863 #if defined(TE_AIX50)
6864 return "elf64-ia64-aix-big";
6865 #elif defined(TE_HPUX)
6866 return "elf64-ia64-hpux-big";
6868 return "elf64-ia64-big";
6871 #if defined(TE_AIX50)
6872 return "elf32-ia64-aix-big";
6873 #elif defined(TE_HPUX)
6874 return "elf32-ia64-hpux-big";
6876 return "elf32-ia64-big";
6881 if (md
.flags
& EF_IA_64_ABI64
)
6883 return "elf64-ia64-aix-little";
6885 return "elf64-ia64-little";
6889 return "elf32-ia64-aix-little";
6891 return "elf32-ia64-little";
6896 return "unknown-format";
6900 ia64_end_of_source ()
6902 /* terminate insn group upon reaching end of file: */
6903 insn_group_break (1, 0, 0);
6905 /* emits slots we haven't written yet: */
6906 ia64_flush_insns ();
6908 bfd_set_private_flags (stdoutput
, md
.flags
);
6910 md
.mem_offset
.hint
= 0;
6916 if (md
.qp
.X_op
== O_register
)
6917 as_bad ("qualifying predicate not followed by instruction");
6918 md
.qp
.X_op
= O_absent
;
6920 if (ignore_input ())
6923 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6925 if (md
.detect_dv
&& !md
.explicit_mode
)
6926 as_warn (_("Explicit stops are ignored in auto mode"));
6928 insn_group_break (1, 0, 0);
6932 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6934 static int defining_tag
= 0;
6937 ia64_unrecognized_line (ch
)
6943 expression (&md
.qp
);
6944 if (*input_line_pointer
++ != ')')
6946 as_bad ("Expected ')'");
6949 if (md
.qp
.X_op
!= O_register
)
6951 as_bad ("Qualifying predicate expected");
6954 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6956 as_bad ("Predicate register expected");
6962 if (md
.manual_bundling
)
6963 as_warn ("Found '{' when manual bundling is already turned on");
6965 CURR_SLOT
.manual_bundling_on
= 1;
6966 md
.manual_bundling
= 1;
6968 /* Bundling is only acceptable in explicit mode
6969 or when in default automatic mode. */
6970 if (md
.detect_dv
&& !md
.explicit_mode
)
6972 if (!md
.mode_explicitly_set
6973 && !md
.default_explicit_mode
)
6976 as_warn (_("Found '{' after explicit switch to automatic mode"));
6981 if (!md
.manual_bundling
)
6982 as_warn ("Found '}' when manual bundling is off");
6984 PREV_SLOT
.manual_bundling_off
= 1;
6985 md
.manual_bundling
= 0;
6987 /* switch back to automatic mode, if applicable */
6990 && !md
.mode_explicitly_set
6991 && !md
.default_explicit_mode
)
6994 /* Allow '{' to follow on the same line. We also allow ";;", but that
6995 happens automatically because ';' is an end of line marker. */
6997 if (input_line_pointer
[0] == '{')
6999 input_line_pointer
++;
7000 return ia64_unrecognized_line ('{');
7003 demand_empty_rest_of_line ();
7013 if (md
.qp
.X_op
== O_register
)
7015 as_bad ("Tag must come before qualifying predicate.");
7019 /* This implements just enough of read_a_source_file in read.c to
7020 recognize labels. */
7021 if (is_name_beginner (*input_line_pointer
))
7023 s
= input_line_pointer
;
7024 c
= get_symbol_end ();
7026 else if (LOCAL_LABELS_FB
7027 && ISDIGIT (*input_line_pointer
))
7030 while (ISDIGIT (*input_line_pointer
))
7031 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
7032 fb_label_instance_inc (temp
);
7033 s
= fb_label_name (temp
, 0);
7034 c
= *input_line_pointer
;
7043 /* Put ':' back for error messages' sake. */
7044 *input_line_pointer
++ = ':';
7045 as_bad ("Expected ':'");
7052 /* Put ':' back for error messages' sake. */
7053 *input_line_pointer
++ = ':';
7054 if (*input_line_pointer
++ != ']')
7056 as_bad ("Expected ']'");
7061 as_bad ("Tag name expected");
7071 /* Not a valid line. */
7076 ia64_frob_label (sym
)
7079 struct label_fix
*fix
;
7081 /* Tags need special handling since they are not bundle breaks like
7085 fix
= obstack_alloc (¬es
, sizeof (*fix
));
7087 fix
->next
= CURR_SLOT
.tag_fixups
;
7088 CURR_SLOT
.tag_fixups
= fix
;
7093 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
7095 md
.last_text_seg
= now_seg
;
7096 fix
= obstack_alloc (¬es
, sizeof (*fix
));
7098 fix
->next
= CURR_SLOT
.label_fixups
;
7099 CURR_SLOT
.label_fixups
= fix
;
7101 /* Keep track of how many code entry points we've seen. */
7102 if (md
.path
== md
.maxpaths
)
7105 md
.entry_labels
= (const char **)
7106 xrealloc ((void *) md
.entry_labels
,
7107 md
.maxpaths
* sizeof (char *));
7109 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
7114 ia64_flush_pending_output ()
7116 if (!md
.keep_pending_output
7117 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
7119 /* ??? This causes many unnecessary stop bits to be emitted.
7120 Unfortunately, it isn't clear if it is safe to remove this. */
7121 insn_group_break (1, 0, 0);
7122 ia64_flush_insns ();
7126 /* Do ia64-specific expression optimization. All that's done here is
7127 to transform index expressions that are either due to the indexing
7128 of rotating registers or due to the indexing of indirect register
7131 ia64_optimize_expr (l
, op
, r
)
7140 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
7142 num_regs
= (l
->X_add_number
>> 16);
7143 if ((unsigned) r
->X_add_number
>= num_regs
)
7146 as_bad ("No current frame");
7148 as_bad ("Index out of range 0..%u", num_regs
- 1);
7149 r
->X_add_number
= 0;
7151 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
7154 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
7156 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
7157 || l
->X_add_number
== IND_MEM
)
7159 as_bad ("Indirect register set name expected");
7160 l
->X_add_number
= IND_CPUID
;
7163 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
7164 l
->X_add_number
= r
->X_add_number
;
7172 ia64_parse_name (name
, e
)
7176 struct const_desc
*cdesc
;
7177 struct dynreg
*dr
= 0;
7178 unsigned int regnum
;
7182 /* first see if NAME is a known register name: */
7183 sym
= hash_find (md
.reg_hash
, name
);
7186 e
->X_op
= O_register
;
7187 e
->X_add_number
= S_GET_VALUE (sym
);
7191 cdesc
= hash_find (md
.const_hash
, name
);
7194 e
->X_op
= O_constant
;
7195 e
->X_add_number
= cdesc
->value
;
7199 /* check for inN, locN, or outN: */
7203 if (name
[1] == 'n' && ISDIGIT (name
[2]))
7211 if (name
[1] == 'o' && name
[2] == 'c' && ISDIGIT (name
[3]))
7219 if (name
[1] == 'u' && name
[2] == 't' && ISDIGIT (name
[3]))
7232 /* The name is inN, locN, or outN; parse the register number. */
7233 regnum
= strtoul (name
, &end
, 10);
7234 if (end
> name
&& *end
== '\0')
7236 if ((unsigned) regnum
>= dr
->num_regs
)
7239 as_bad ("No current frame");
7241 as_bad ("Register number out of range 0..%u",
7245 e
->X_op
= O_register
;
7246 e
->X_add_number
= dr
->base
+ regnum
;
7251 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
7253 /* We've got ourselves the name of a rotating register set.
7254 Store the base register number in the low 16 bits of
7255 X_add_number and the size of the register set in the top 16
7257 e
->X_op
= O_register
;
7258 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
7264 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7267 ia64_canonicalize_symbol_name (name
)
7270 size_t len
= strlen (name
);
7271 if (len
> 1 && name
[len
- 1] == '#')
7272 name
[len
- 1] = '\0';
7276 /* Return true if idesc is a conditional branch instruction. This excludes
7277 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7278 because they always read/write resources regardless of the value of the
7279 qualifying predicate. br.ia must always use p0, and hence is always
7280 taken. Thus this function returns true for branches which can fall
7281 through, and which use no resources if they do fall through. */
7284 is_conditional_branch (idesc
)
7285 struct ia64_opcode
*idesc
;
7287 /* br is a conditional branch. Everything that starts with br. except
7288 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7289 Everything that starts with brl is a conditional branch. */
7290 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7291 && (idesc
->name
[2] == '\0'
7292 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7293 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7294 || idesc
->name
[2] == 'l'
7295 /* br.cond, br.call, br.clr */
7296 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7297 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7298 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7301 /* Return whether the given opcode is a taken branch. If there's any doubt,
7305 is_taken_branch (idesc
)
7306 struct ia64_opcode
*idesc
;
7308 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7309 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7312 /* Return whether the given opcode is an interruption or rfi. If there's any
7313 doubt, returns zero. */
7316 is_interruption_or_rfi (idesc
)
7317 struct ia64_opcode
*idesc
;
7319 if (strcmp (idesc
->name
, "rfi") == 0)
7324 /* Returns the index of the given dependency in the opcode's list of chks, or
7325 -1 if there is no dependency. */
7328 depends_on (depind
, idesc
)
7330 struct ia64_opcode
*idesc
;
7333 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7334 for (i
= 0; i
< dep
->nchks
; i
++)
7336 if (depind
== DEP (dep
->chks
[i
]))
7342 /* Determine a set of specific resources used for a particular resource
7343 class. Returns the number of specific resources identified For those
7344 cases which are not determinable statically, the resource returned is
7347 Meanings of value in 'NOTE':
7348 1) only read/write when the register number is explicitly encoded in the
7350 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7351 accesses CFM when qualifying predicate is in the rotating region.
7352 3) general register value is used to specify an indirect register; not
7353 determinable statically.
7354 4) only read the given resource when bits 7:0 of the indirect index
7355 register value does not match the register number of the resource; not
7356 determinable statically.
7357 5) all rules are implementation specific.
7358 6) only when both the index specified by the reader and the index specified
7359 by the writer have the same value in bits 63:61; not determinable
7361 7) only access the specified resource when the corresponding mask bit is
7363 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7364 only read when these insns reference FR2-31
7365 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7366 written when these insns write FR32-127
7367 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7369 11) The target predicates are written independently of PR[qp], but source
7370 registers are only read if PR[qp] is true. Since the state of PR[qp]
7371 cannot statically be determined, all source registers are marked used.
7372 12) This insn only reads the specified predicate register when that
7373 register is the PR[qp].
7374 13) This reference to ld-c only applies to teh GR whose value is loaded
7375 with data returned from memory, not the post-incremented address register.
7376 14) The RSE resource includes the implementation-specific RSE internal
7377 state resources. At least one (and possibly more) of these resources are
7378 read by each instruction listed in IC:rse-readers. At least one (and
7379 possibly more) of these resources are written by each insn listed in
7381 15+16) Represents reserved instructions, which the assembler does not
7384 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7385 this code; there are no dependency violations based on memory access.
7388 #define MAX_SPECS 256
7393 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7394 const struct ia64_dependency
*dep
;
7395 struct ia64_opcode
*idesc
;
7396 int type
; /* is this a DV chk or a DV reg? */
7397 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7398 int note
; /* resource note for this insn's usage */
7399 int path
; /* which execution path to examine */
7406 if (dep
->mode
== IA64_DV_WAW
7407 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7408 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7411 /* template for any resources we identify */
7412 tmpl
.dependency
= dep
;
7414 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7415 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7416 tmpl
.link_to_qp_branch
= 1;
7417 tmpl
.mem_offset
.hint
= 0;
7420 tmpl
.cmp_type
= CMP_NONE
;
7423 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7424 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7425 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7427 /* we don't need to track these */
7428 if (dep
->semantics
== IA64_DVS_NONE
)
7431 switch (dep
->specifier
)
7436 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7438 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7439 if (regno
>= 0 && regno
<= 7)
7441 specs
[count
] = tmpl
;
7442 specs
[count
++].index
= regno
;
7448 for (i
= 0; i
< 8; i
++)
7450 specs
[count
] = tmpl
;
7451 specs
[count
++].index
= i
;
7460 case IA64_RS_AR_UNAT
:
7461 /* This is a mov =AR or mov AR= instruction. */
7462 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7464 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7465 if (regno
== AR_UNAT
)
7467 specs
[count
++] = tmpl
;
7472 /* This is a spill/fill, or other instruction that modifies the
7475 /* Unless we can determine the specific bits used, mark the whole
7476 thing; bits 8:3 of the memory address indicate the bit used in
7477 UNAT. The .mem.offset hint may be used to eliminate a small
7478 subset of conflicts. */
7479 specs
[count
] = tmpl
;
7480 if (md
.mem_offset
.hint
)
7483 fprintf (stderr
, " Using hint for spill/fill\n");
7484 /* The index isn't actually used, just set it to something
7485 approximating the bit index. */
7486 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7487 specs
[count
].mem_offset
.hint
= 1;
7488 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7489 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7493 specs
[count
++].specific
= 0;
7501 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7503 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7504 if ((regno
>= 8 && regno
<= 15)
7505 || (regno
>= 20 && regno
<= 23)
7506 || (regno
>= 31 && regno
<= 39)
7507 || (regno
>= 41 && regno
<= 47)
7508 || (regno
>= 67 && regno
<= 111))
7510 specs
[count
] = tmpl
;
7511 specs
[count
++].index
= regno
;
7524 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7526 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7527 if ((regno
>= 48 && regno
<= 63)
7528 || (regno
>= 112 && regno
<= 127))
7530 specs
[count
] = tmpl
;
7531 specs
[count
++].index
= regno
;
7537 for (i
= 48; i
< 64; i
++)
7539 specs
[count
] = tmpl
;
7540 specs
[count
++].index
= i
;
7542 for (i
= 112; i
< 128; i
++)
7544 specs
[count
] = tmpl
;
7545 specs
[count
++].index
= i
;
7563 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7564 if (idesc
->operands
[i
] == IA64_OPND_B1
7565 || idesc
->operands
[i
] == IA64_OPND_B2
)
7567 specs
[count
] = tmpl
;
7568 specs
[count
++].index
=
7569 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7574 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7575 if (idesc
->operands
[i
] == IA64_OPND_B1
7576 || idesc
->operands
[i
] == IA64_OPND_B2
)
7578 specs
[count
] = tmpl
;
7579 specs
[count
++].index
=
7580 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7586 case IA64_RS_CPUID
: /* four or more registers */
7589 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7591 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7592 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7595 specs
[count
] = tmpl
;
7596 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7600 specs
[count
] = tmpl
;
7601 specs
[count
++].specific
= 0;
7611 case IA64_RS_DBR
: /* four or more registers */
7614 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7616 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7617 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7620 specs
[count
] = tmpl
;
7621 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7625 specs
[count
] = tmpl
;
7626 specs
[count
++].specific
= 0;
7630 else if (note
== 0 && !rsrc_write
)
7632 specs
[count
] = tmpl
;
7633 specs
[count
++].specific
= 0;
7641 case IA64_RS_IBR
: /* four or more registers */
7644 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7646 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7647 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7650 specs
[count
] = tmpl
;
7651 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7655 specs
[count
] = tmpl
;
7656 specs
[count
++].specific
= 0;
7669 /* These are implementation specific. Force all references to
7670 conflict with all other references. */
7671 specs
[count
] = tmpl
;
7672 specs
[count
++].specific
= 0;
7680 case IA64_RS_PKR
: /* 16 or more registers */
7681 if (note
== 3 || note
== 4)
7683 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7685 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7686 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7691 specs
[count
] = tmpl
;
7692 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7695 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7697 /* Uses all registers *except* the one in R3. */
7698 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7700 specs
[count
] = tmpl
;
7701 specs
[count
++].index
= i
;
7707 specs
[count
] = tmpl
;
7708 specs
[count
++].specific
= 0;
7715 specs
[count
] = tmpl
;
7716 specs
[count
++].specific
= 0;
7720 case IA64_RS_PMC
: /* four or more registers */
7723 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7724 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7727 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7729 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7730 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7733 specs
[count
] = tmpl
;
7734 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7738 specs
[count
] = tmpl
;
7739 specs
[count
++].specific
= 0;
7749 case IA64_RS_PMD
: /* four or more registers */
7752 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7754 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7755 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7758 specs
[count
] = tmpl
;
7759 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7763 specs
[count
] = tmpl
;
7764 specs
[count
++].specific
= 0;
7774 case IA64_RS_RR
: /* eight registers */
7777 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7779 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7780 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7783 specs
[count
] = tmpl
;
7784 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7788 specs
[count
] = tmpl
;
7789 specs
[count
++].specific
= 0;
7793 else if (note
== 0 && !rsrc_write
)
7795 specs
[count
] = tmpl
;
7796 specs
[count
++].specific
= 0;
7804 case IA64_RS_CR_IRR
:
7807 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7808 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7810 && idesc
->operands
[1] == IA64_OPND_CR3
7813 for (i
= 0; i
< 4; i
++)
7815 specs
[count
] = tmpl
;
7816 specs
[count
++].index
= CR_IRR0
+ i
;
7822 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7823 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7825 && regno
<= CR_IRR3
)
7827 specs
[count
] = tmpl
;
7828 specs
[count
++].index
= regno
;
7837 case IA64_RS_CR_LRR
:
7844 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7845 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7846 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7848 specs
[count
] = tmpl
;
7849 specs
[count
++].index
= regno
;
7857 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7859 specs
[count
] = tmpl
;
7860 specs
[count
++].index
=
7861 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7876 else if (rsrc_write
)
7878 if (dep
->specifier
== IA64_RS_FRb
7879 && idesc
->operands
[0] == IA64_OPND_F1
)
7881 specs
[count
] = tmpl
;
7882 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7887 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7889 if (idesc
->operands
[i
] == IA64_OPND_F2
7890 || idesc
->operands
[i
] == IA64_OPND_F3
7891 || idesc
->operands
[i
] == IA64_OPND_F4
)
7893 specs
[count
] = tmpl
;
7894 specs
[count
++].index
=
7895 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7904 /* This reference applies only to the GR whose value is loaded with
7905 data returned from memory. */
7906 specs
[count
] = tmpl
;
7907 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7913 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7914 if (idesc
->operands
[i
] == IA64_OPND_R1
7915 || idesc
->operands
[i
] == IA64_OPND_R2
7916 || idesc
->operands
[i
] == IA64_OPND_R3
)
7918 specs
[count
] = tmpl
;
7919 specs
[count
++].index
=
7920 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7922 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7923 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7924 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7926 specs
[count
] = tmpl
;
7927 specs
[count
++].index
=
7928 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7933 /* Look for anything that reads a GR. */
7934 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7936 if (idesc
->operands
[i
] == IA64_OPND_MR3
7937 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7938 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7939 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7940 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7941 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7942 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7943 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7944 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7945 || ((i
>= idesc
->num_outputs
)
7946 && (idesc
->operands
[i
] == IA64_OPND_R1
7947 || idesc
->operands
[i
] == IA64_OPND_R2
7948 || idesc
->operands
[i
] == IA64_OPND_R3
7949 /* addl source register. */
7950 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7952 specs
[count
] = tmpl
;
7953 specs
[count
++].index
=
7954 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7965 /* This is the same as IA64_RS_PRr, except that the register range is
7966 from 1 - 15, and there are no rotating register reads/writes here. */
7970 for (i
= 1; i
< 16; i
++)
7972 specs
[count
] = tmpl
;
7973 specs
[count
++].index
= i
;
7979 /* Mark only those registers indicated by the mask. */
7982 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7983 for (i
= 1; i
< 16; i
++)
7984 if (mask
& ((valueT
) 1 << i
))
7986 specs
[count
] = tmpl
;
7987 specs
[count
++].index
= i
;
7995 else if (note
== 11) /* note 11 implies note 1 as well */
7999 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8001 if (idesc
->operands
[i
] == IA64_OPND_P1
8002 || idesc
->operands
[i
] == IA64_OPND_P2
)
8004 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8005 if (regno
>= 1 && regno
< 16)
8007 specs
[count
] = tmpl
;
8008 specs
[count
++].index
= regno
;
8018 else if (note
== 12)
8020 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
8022 specs
[count
] = tmpl
;
8023 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8030 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8031 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8032 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8033 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8035 if ((idesc
->operands
[0] == IA64_OPND_P1
8036 || idesc
->operands
[0] == IA64_OPND_P2
)
8037 && p1
>= 1 && p1
< 16)
8039 specs
[count
] = tmpl
;
8040 specs
[count
].cmp_type
=
8041 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8042 specs
[count
++].index
= p1
;
8044 if ((idesc
->operands
[1] == IA64_OPND_P1
8045 || idesc
->operands
[1] == IA64_OPND_P2
)
8046 && p2
>= 1 && p2
< 16)
8048 specs
[count
] = tmpl
;
8049 specs
[count
].cmp_type
=
8050 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8051 specs
[count
++].index
= p2
;
8056 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
8058 specs
[count
] = tmpl
;
8059 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8061 if (idesc
->operands
[1] == IA64_OPND_PR
)
8063 for (i
= 1; i
< 16; i
++)
8065 specs
[count
] = tmpl
;
8066 specs
[count
++].index
= i
;
8077 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
8078 simplified cases of this. */
8082 for (i
= 16; i
< 63; i
++)
8084 specs
[count
] = tmpl
;
8085 specs
[count
++].index
= i
;
8091 /* Mark only those registers indicated by the mask. */
8093 && idesc
->operands
[0] == IA64_OPND_PR
)
8095 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8096 if (mask
& ((valueT
) 1 << 16))
8097 for (i
= 16; i
< 63; i
++)
8099 specs
[count
] = tmpl
;
8100 specs
[count
++].index
= i
;
8104 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
8106 for (i
= 16; i
< 63; i
++)
8108 specs
[count
] = tmpl
;
8109 specs
[count
++].index
= i
;
8117 else if (note
== 11) /* note 11 implies note 1 as well */
8121 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8123 if (idesc
->operands
[i
] == IA64_OPND_P1
8124 || idesc
->operands
[i
] == IA64_OPND_P2
)
8126 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8127 if (regno
>= 16 && regno
< 63)
8129 specs
[count
] = tmpl
;
8130 specs
[count
++].index
= regno
;
8140 else if (note
== 12)
8142 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8144 specs
[count
] = tmpl
;
8145 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8152 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8153 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8154 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8155 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8157 if ((idesc
->operands
[0] == IA64_OPND_P1
8158 || idesc
->operands
[0] == IA64_OPND_P2
)
8159 && p1
>= 16 && p1
< 63)
8161 specs
[count
] = tmpl
;
8162 specs
[count
].cmp_type
=
8163 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8164 specs
[count
++].index
= p1
;
8166 if ((idesc
->operands
[1] == IA64_OPND_P1
8167 || idesc
->operands
[1] == IA64_OPND_P2
)
8168 && p2
>= 16 && p2
< 63)
8170 specs
[count
] = tmpl
;
8171 specs
[count
].cmp_type
=
8172 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8173 specs
[count
++].index
= p2
;
8178 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8180 specs
[count
] = tmpl
;
8181 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8183 if (idesc
->operands
[1] == IA64_OPND_PR
)
8185 for (i
= 16; i
< 63; i
++)
8187 specs
[count
] = tmpl
;
8188 specs
[count
++].index
= i
;
8200 /* Verify that the instruction is using the PSR bit indicated in
8204 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
8206 if (dep
->regindex
< 6)
8208 specs
[count
++] = tmpl
;
8211 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
8213 if (dep
->regindex
< 32
8214 || dep
->regindex
== 35
8215 || dep
->regindex
== 36
8216 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
8218 specs
[count
++] = tmpl
;
8221 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
8223 if (dep
->regindex
< 32
8224 || dep
->regindex
== 35
8225 || dep
->regindex
== 36
8226 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
8228 specs
[count
++] = tmpl
;
8233 /* Several PSR bits have very specific dependencies. */
8234 switch (dep
->regindex
)
8237 specs
[count
++] = tmpl
;
8242 specs
[count
++] = tmpl
;
8246 /* Only certain CR accesses use PSR.ic */
8247 if (idesc
->operands
[0] == IA64_OPND_CR3
8248 || idesc
->operands
[1] == IA64_OPND_CR3
)
8251 ((idesc
->operands
[0] == IA64_OPND_CR3
)
8254 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8269 specs
[count
++] = tmpl
;
8278 specs
[count
++] = tmpl
;
8282 /* Only some AR accesses use cpl */
8283 if (idesc
->operands
[0] == IA64_OPND_AR3
8284 || idesc
->operands
[1] == IA64_OPND_AR3
)
8287 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8290 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8297 && regno
<= AR_K7
))))
8299 specs
[count
++] = tmpl
;
8304 specs
[count
++] = tmpl
;
8314 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8316 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8322 if (mask
& ((valueT
) 1 << dep
->regindex
))
8324 specs
[count
++] = tmpl
;
8329 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8330 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8331 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8332 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8334 if (idesc
->operands
[i
] == IA64_OPND_F1
8335 || idesc
->operands
[i
] == IA64_OPND_F2
8336 || idesc
->operands
[i
] == IA64_OPND_F3
8337 || idesc
->operands
[i
] == IA64_OPND_F4
)
8339 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8340 if (reg
>= min
&& reg
<= max
)
8342 specs
[count
++] = tmpl
;
8349 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8350 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8351 /* mfh is read on writes to FR32-127; mfl is read on writes to
8353 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8355 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8357 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8358 if (reg
>= min
&& reg
<= max
)
8360 specs
[count
++] = tmpl
;
8365 else if (note
== 10)
8367 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8369 if (idesc
->operands
[i
] == IA64_OPND_R1
8370 || idesc
->operands
[i
] == IA64_OPND_R2
8371 || idesc
->operands
[i
] == IA64_OPND_R3
)
8373 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8374 if (regno
>= 16 && regno
<= 31)
8376 specs
[count
++] = tmpl
;
8387 case IA64_RS_AR_FPSR
:
8388 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8390 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8391 if (regno
== AR_FPSR
)
8393 specs
[count
++] = tmpl
;
8398 specs
[count
++] = tmpl
;
8403 /* Handle all AR[REG] resources */
8404 if (note
== 0 || note
== 1)
8406 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8407 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8408 && regno
== dep
->regindex
)
8410 specs
[count
++] = tmpl
;
8412 /* other AR[REG] resources may be affected by AR accesses */
8413 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8416 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8417 switch (dep
->regindex
)
8423 if (regno
== AR_BSPSTORE
)
8425 specs
[count
++] = tmpl
;
8429 (regno
== AR_BSPSTORE
8430 || regno
== AR_RNAT
))
8432 specs
[count
++] = tmpl
;
8437 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8440 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8441 switch (dep
->regindex
)
8446 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8448 specs
[count
++] = tmpl
;
8455 specs
[count
++] = tmpl
;
8465 /* Handle all CR[REG] resources */
8466 if (note
== 0 || note
== 1)
8468 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8470 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8471 if (regno
== dep
->regindex
)
8473 specs
[count
++] = tmpl
;
8475 else if (!rsrc_write
)
8477 /* Reads from CR[IVR] affect other resources. */
8478 if (regno
== CR_IVR
)
8480 if ((dep
->regindex
>= CR_IRR0
8481 && dep
->regindex
<= CR_IRR3
)
8482 || dep
->regindex
== CR_TPR
)
8484 specs
[count
++] = tmpl
;
8491 specs
[count
++] = tmpl
;
8500 case IA64_RS_INSERVICE
:
8501 /* look for write of EOI (67) or read of IVR (65) */
8502 if ((idesc
->operands
[0] == IA64_OPND_CR3
8503 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8504 || (idesc
->operands
[1] == IA64_OPND_CR3
8505 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8507 specs
[count
++] = tmpl
;
8514 specs
[count
++] = tmpl
;
8525 specs
[count
++] = tmpl
;
8529 /* Check if any of the registers accessed are in the rotating region.
8530 mov to/from pr accesses CFM only when qp_regno is in the rotating
8532 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8534 if (idesc
->operands
[i
] == IA64_OPND_R1
8535 || idesc
->operands
[i
] == IA64_OPND_R2
8536 || idesc
->operands
[i
] == IA64_OPND_R3
)
8538 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8539 /* Assumes that md.rot.num_regs is always valid */
8540 if (md
.rot
.num_regs
> 0
8542 && num
< 31 + md
.rot
.num_regs
)
8544 specs
[count
] = tmpl
;
8545 specs
[count
++].specific
= 0;
8548 else if (idesc
->operands
[i
] == IA64_OPND_F1
8549 || idesc
->operands
[i
] == IA64_OPND_F2
8550 || idesc
->operands
[i
] == IA64_OPND_F3
8551 || idesc
->operands
[i
] == IA64_OPND_F4
)
8553 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8556 specs
[count
] = tmpl
;
8557 specs
[count
++].specific
= 0;
8560 else if (idesc
->operands
[i
] == IA64_OPND_P1
8561 || idesc
->operands
[i
] == IA64_OPND_P2
)
8563 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8566 specs
[count
] = tmpl
;
8567 specs
[count
++].specific
= 0;
8571 if (CURR_SLOT
.qp_regno
> 15)
8573 specs
[count
] = tmpl
;
8574 specs
[count
++].specific
= 0;
8579 /* This is the same as IA64_RS_PRr, except simplified to account for
8580 the fact that there is only one register. */
8584 specs
[count
++] = tmpl
;
8589 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8590 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8591 if (mask
& ((valueT
) 1 << 63))
8592 specs
[count
++] = tmpl
;
8594 else if (note
== 11)
8596 if ((idesc
->operands
[0] == IA64_OPND_P1
8597 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8598 || (idesc
->operands
[1] == IA64_OPND_P2
8599 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8601 specs
[count
++] = tmpl
;
8604 else if (note
== 12)
8606 if (CURR_SLOT
.qp_regno
== 63)
8608 specs
[count
++] = tmpl
;
8615 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8616 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8617 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8618 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8621 && (idesc
->operands
[0] == IA64_OPND_P1
8622 || idesc
->operands
[0] == IA64_OPND_P2
))
8624 specs
[count
] = tmpl
;
8625 specs
[count
++].cmp_type
=
8626 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8629 && (idesc
->operands
[1] == IA64_OPND_P1
8630 || idesc
->operands
[1] == IA64_OPND_P2
))
8632 specs
[count
] = tmpl
;
8633 specs
[count
++].cmp_type
=
8634 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8639 if (CURR_SLOT
.qp_regno
== 63)
8641 specs
[count
++] = tmpl
;
8652 /* FIXME we can identify some individual RSE written resources, but RSE
8653 read resources have not yet been completely identified, so for now
8654 treat RSE as a single resource */
8655 if (strncmp (idesc
->name
, "mov", 3) == 0)
8659 if (idesc
->operands
[0] == IA64_OPND_AR3
8660 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8662 specs
[count
] = tmpl
;
8663 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8668 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8670 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8671 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8673 specs
[count
++] = tmpl
;
8676 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8678 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8679 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8680 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8682 specs
[count
++] = tmpl
;
8689 specs
[count
++] = tmpl
;
8694 /* FIXME -- do any of these need to be non-specific? */
8695 specs
[count
++] = tmpl
;
8699 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8706 /* Clear branch flags on marked resources. This breaks the link between the
8707 QP of the marking instruction and a subsequent branch on the same QP. */
8710 clear_qp_branch_flag (mask
)
8714 for (i
= 0; i
< regdepslen
; i
++)
8716 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8717 if ((bit
& mask
) != 0)
8719 regdeps
[i
].link_to_qp_branch
= 0;
8724 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8726 Any changes to a PR clears the mutex relations which include that PR. */
8729 clear_qp_mutex (mask
)
8735 while (i
< qp_mutexeslen
)
8737 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8741 fprintf (stderr
, " Clearing mutex relation");
8742 print_prmask (qp_mutexes
[i
].prmask
);
8743 fprintf (stderr
, "\n");
8745 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8752 /* Clear implies relations which contain PRs in the given masks.
8753 P1_MASK indicates the source of the implies relation, while P2_MASK
8754 indicates the implied PR. */
8757 clear_qp_implies (p1_mask
, p2_mask
)
8764 while (i
< qp_implieslen
)
8766 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8767 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8770 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8771 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8772 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8779 /* Add the PRs specified to the list of implied relations. */
8782 add_qp_imply (p1
, p2
)
8789 /* p0 is not meaningful here. */
8790 if (p1
== 0 || p2
== 0)
8796 /* If it exists already, ignore it. */
8797 for (i
= 0; i
< qp_implieslen
; i
++)
8799 if (qp_implies
[i
].p1
== p1
8800 && qp_implies
[i
].p2
== p2
8801 && qp_implies
[i
].path
== md
.path
8802 && !qp_implies
[i
].p2_branched
)
8806 if (qp_implieslen
== qp_impliestotlen
)
8808 qp_impliestotlen
+= 20;
8809 qp_implies
= (struct qp_imply
*)
8810 xrealloc ((void *) qp_implies
,
8811 qp_impliestotlen
* sizeof (struct qp_imply
));
8814 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8815 qp_implies
[qp_implieslen
].p1
= p1
;
8816 qp_implies
[qp_implieslen
].p2
= p2
;
8817 qp_implies
[qp_implieslen
].path
= md
.path
;
8818 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8820 /* Add in the implied transitive relations; for everything that p2 implies,
8821 make p1 imply that, too; for everything that implies p1, make it imply p2
8823 for (i
= 0; i
< qp_implieslen
; i
++)
8825 if (qp_implies
[i
].p1
== p2
)
8826 add_qp_imply (p1
, qp_implies
[i
].p2
);
8827 if (qp_implies
[i
].p2
== p1
)
8828 add_qp_imply (qp_implies
[i
].p1
, p2
);
8830 /* Add in mutex relations implied by this implies relation; for each mutex
8831 relation containing p2, duplicate it and replace p2 with p1. */
8832 bit
= (valueT
) 1 << p1
;
8833 mask
= (valueT
) 1 << p2
;
8834 for (i
= 0; i
< qp_mutexeslen
; i
++)
8836 if (qp_mutexes
[i
].prmask
& mask
)
8837 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8841 /* Add the PRs specified in the mask to the mutex list; this means that only
8842 one of the PRs can be true at any time. PR0 should never be included in
8852 if (qp_mutexeslen
== qp_mutexestotlen
)
8854 qp_mutexestotlen
+= 20;
8855 qp_mutexes
= (struct qpmutex
*)
8856 xrealloc ((void *) qp_mutexes
,
8857 qp_mutexestotlen
* sizeof (struct qpmutex
));
8861 fprintf (stderr
, " Registering mutex on");
8862 print_prmask (mask
);
8863 fprintf (stderr
, "\n");
8865 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8866 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8870 has_suffix_p (name
, suffix
)
8874 size_t namelen
= strlen (name
);
8875 size_t sufflen
= strlen (suffix
);
8877 if (namelen
<= sufflen
)
8879 return strcmp (name
+ namelen
- sufflen
, suffix
) == 0;
8883 clear_register_values ()
8887 fprintf (stderr
, " Clearing register values\n");
8888 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8889 gr_values
[i
].known
= 0;
8892 /* Keep track of register values/changes which affect DV tracking.
8894 optimization note: should add a flag to classes of insns where otherwise we
8895 have to examine a group of strings to identify them. */
8898 note_register_values (idesc
)
8899 struct ia64_opcode
*idesc
;
8901 valueT qp_changemask
= 0;
8904 /* Invalidate values for registers being written to. */
8905 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8907 if (idesc
->operands
[i
] == IA64_OPND_R1
8908 || idesc
->operands
[i
] == IA64_OPND_R2
8909 || idesc
->operands
[i
] == IA64_OPND_R3
)
8911 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8912 if (regno
> 0 && regno
< NELEMS (gr_values
))
8913 gr_values
[regno
].known
= 0;
8915 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8917 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8918 if (regno
> 0 && regno
< 4)
8919 gr_values
[regno
].known
= 0;
8921 else if (idesc
->operands
[i
] == IA64_OPND_P1
8922 || idesc
->operands
[i
] == IA64_OPND_P2
)
8924 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8925 qp_changemask
|= (valueT
) 1 << regno
;
8927 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8929 if (idesc
->operands
[2] & (valueT
) 0x10000)
8930 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8932 qp_changemask
= idesc
->operands
[2];
8935 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8937 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8938 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8940 qp_changemask
= idesc
->operands
[1];
8941 qp_changemask
&= ~(valueT
) 0xFFFF;
8946 /* Always clear qp branch flags on any PR change. */
8947 /* FIXME there may be exceptions for certain compares. */
8948 clear_qp_branch_flag (qp_changemask
);
8950 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8951 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8953 qp_changemask
|= ~(valueT
) 0xFFFF;
8954 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8956 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8957 gr_values
[i
].known
= 0;
8959 clear_qp_mutex (qp_changemask
);
8960 clear_qp_implies (qp_changemask
, qp_changemask
);
8962 /* After a call, all register values are undefined, except those marked
8964 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8965 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8967 /* FIXME keep GR values which are marked as "safe_across_calls" */
8968 clear_register_values ();
8969 clear_qp_mutex (~qp_safe_across_calls
);
8970 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8971 clear_qp_branch_flag (~qp_safe_across_calls
);
8973 else if (is_interruption_or_rfi (idesc
)
8974 || is_taken_branch (idesc
))
8976 clear_register_values ();
8977 clear_qp_mutex (~(valueT
) 0);
8978 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8980 /* Look for mutex and implies relations. */
8981 else if ((idesc
->operands
[0] == IA64_OPND_P1
8982 || idesc
->operands
[0] == IA64_OPND_P2
)
8983 && (idesc
->operands
[1] == IA64_OPND_P1
8984 || idesc
->operands
[1] == IA64_OPND_P2
))
8986 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8987 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8988 valueT p1mask
= (valueT
) 1 << p1
;
8989 valueT p2mask
= (valueT
) 1 << p2
;
8991 /* If one of the PRs is PR0, we can't really do anything. */
8992 if (p1
== 0 || p2
== 0)
8995 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8997 /* In general, clear mutexes and implies which include P1 or P2,
8998 with the following exceptions. */
8999 else if (has_suffix_p (idesc
->name
, ".or.andcm")
9000 || has_suffix_p (idesc
->name
, ".and.orcm"))
9002 add_qp_mutex (p1mask
| p2mask
);
9003 clear_qp_implies (p2mask
, p1mask
);
9005 else if (has_suffix_p (idesc
->name
, ".andcm")
9006 || has_suffix_p (idesc
->name
, ".and"))
9008 clear_qp_implies (0, p1mask
| p2mask
);
9010 else if (has_suffix_p (idesc
->name
, ".orcm")
9011 || has_suffix_p (idesc
->name
, ".or"))
9013 clear_qp_mutex (p1mask
| p2mask
);
9014 clear_qp_implies (p1mask
| p2mask
, 0);
9018 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
9019 if (has_suffix_p (idesc
->name
, ".unc"))
9021 add_qp_mutex (p1mask
| p2mask
);
9022 if (CURR_SLOT
.qp_regno
!= 0)
9024 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
9025 CURR_SLOT
.qp_regno
);
9026 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
9027 CURR_SLOT
.qp_regno
);
9030 else if (CURR_SLOT
.qp_regno
== 0)
9032 add_qp_mutex (p1mask
| p2mask
);
9036 clear_qp_mutex (p1mask
| p2mask
);
9040 /* Look for mov imm insns into GRs. */
9041 else if (idesc
->operands
[0] == IA64_OPND_R1
9042 && (idesc
->operands
[1] == IA64_OPND_IMM22
9043 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
9044 && (strcmp (idesc
->name
, "mov") == 0
9045 || strcmp (idesc
->name
, "movl") == 0))
9047 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
9048 if (regno
> 0 && regno
< NELEMS (gr_values
))
9050 gr_values
[regno
].known
= 1;
9051 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
9052 gr_values
[regno
].path
= md
.path
;
9055 fprintf (stderr
, " Know gr%d = ", regno
);
9056 fprintf_vma (stderr
, gr_values
[regno
].value
);
9057 fputs ("\n", stderr
);
9063 clear_qp_mutex (qp_changemask
);
9064 clear_qp_implies (qp_changemask
, qp_changemask
);
9068 /* Return whether the given predicate registers are currently mutex. */
9071 qp_mutex (p1
, p2
, path
)
9081 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
9082 for (i
= 0; i
< qp_mutexeslen
; i
++)
9084 if (qp_mutexes
[i
].path
>= path
9085 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
9092 /* Return whether the given resource is in the given insn's list of chks
9093 Return 1 if the conflict is absolutely determined, 2 if it's a potential
9097 resources_match (rs
, idesc
, note
, qp_regno
, path
)
9099 struct ia64_opcode
*idesc
;
9104 struct rsrc specs
[MAX_SPECS
];
9107 /* If the marked resource's qp_regno and the given qp_regno are mutex,
9108 we don't need to check. One exception is note 11, which indicates that
9109 target predicates are written regardless of PR[qp]. */
9110 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
9114 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
9117 /* UNAT checking is a bit more specific than other resources */
9118 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
9119 && specs
[count
].mem_offset
.hint
9120 && rs
->mem_offset
.hint
)
9122 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
9124 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
9125 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
9132 /* Skip apparent PR write conflicts where both writes are an AND or both
9133 writes are an OR. */
9134 if (rs
->dependency
->specifier
== IA64_RS_PR
9135 || rs
->dependency
->specifier
== IA64_RS_PRr
9136 || rs
->dependency
->specifier
== IA64_RS_PR63
)
9138 if (specs
[count
].cmp_type
!= CMP_NONE
9139 && specs
[count
].cmp_type
== rs
->cmp_type
)
9142 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
9143 dv_mode
[rs
->dependency
->mode
],
9144 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9145 specs
[count
].index
: 63);
9150 " %s on parallel compare conflict %s vs %s on PR%d\n",
9151 dv_mode
[rs
->dependency
->mode
],
9152 dv_cmp_type
[rs
->cmp_type
],
9153 dv_cmp_type
[specs
[count
].cmp_type
],
9154 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9155 specs
[count
].index
: 63);
9159 /* If either resource is not specific, conservatively assume a conflict
9161 if (!specs
[count
].specific
|| !rs
->specific
)
9163 else if (specs
[count
].index
== rs
->index
)
9168 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
9174 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9175 insert a stop to create the break. Update all resource dependencies
9176 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9177 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9178 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
9182 insn_group_break (insert_stop
, qp_regno
, save_current
)
9189 if (insert_stop
&& md
.num_slots_in_use
> 0)
9190 PREV_SLOT
.end_of_insn_group
= 1;
9194 fprintf (stderr
, " Insn group break%s",
9195 (insert_stop
? " (w/stop)" : ""));
9197 fprintf (stderr
, " effective for QP=%d", qp_regno
);
9198 fprintf (stderr
, "\n");
9202 while (i
< regdepslen
)
9204 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
9207 && regdeps
[i
].qp_regno
!= qp_regno
)
9214 && CURR_SLOT
.src_file
== regdeps
[i
].file
9215 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
9221 /* clear dependencies which are automatically cleared by a stop, or
9222 those that have reached the appropriate state of insn serialization */
9223 if (dep
->semantics
== IA64_DVS_IMPLIED
9224 || dep
->semantics
== IA64_DVS_IMPLIEDF
9225 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
9227 print_dependency ("Removing", i
);
9228 regdeps
[i
] = regdeps
[--regdepslen
];
9232 if (dep
->semantics
== IA64_DVS_DATA
9233 || dep
->semantics
== IA64_DVS_INSTR
9234 || dep
->semantics
== IA64_DVS_SPECIFIC
)
9236 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
9237 regdeps
[i
].insn_srlz
= STATE_STOP
;
9238 if (regdeps
[i
].data_srlz
== STATE_NONE
)
9239 regdeps
[i
].data_srlz
= STATE_STOP
;
9246 /* Add the given resource usage spec to the list of active dependencies. */
9249 mark_resource (idesc
, dep
, spec
, depind
, path
)
9250 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
9251 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
9256 if (regdepslen
== regdepstotlen
)
9258 regdepstotlen
+= 20;
9259 regdeps
= (struct rsrc
*)
9260 xrealloc ((void *) regdeps
,
9261 regdepstotlen
* sizeof (struct rsrc
));
9264 regdeps
[regdepslen
] = *spec
;
9265 regdeps
[regdepslen
].depind
= depind
;
9266 regdeps
[regdepslen
].path
= path
;
9267 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
9268 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
9270 print_dependency ("Adding", regdepslen
);
9276 print_dependency (action
, depind
)
9282 fprintf (stderr
, " %s %s '%s'",
9283 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9284 (regdeps
[depind
].dependency
)->name
);
9285 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9286 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9287 if (regdeps
[depind
].mem_offset
.hint
)
9289 fputs (" ", stderr
);
9290 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9291 fputs ("+", stderr
);
9292 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9294 fprintf (stderr
, "\n");
9299 instruction_serialization ()
9303 fprintf (stderr
, " Instruction serialization\n");
9304 for (i
= 0; i
< regdepslen
; i
++)
9305 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9306 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9310 data_serialization ()
9314 fprintf (stderr
, " Data serialization\n");
9315 while (i
< regdepslen
)
9317 if (regdeps
[i
].data_srlz
== STATE_STOP
9318 /* Note: as of 991210, all "other" dependencies are cleared by a
9319 data serialization. This might change with new tables */
9320 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9322 print_dependency ("Removing", i
);
9323 regdeps
[i
] = regdeps
[--regdepslen
];
9330 /* Insert stops and serializations as needed to avoid DVs. */
9333 remove_marked_resource (rs
)
9336 switch (rs
->dependency
->semantics
)
9338 case IA64_DVS_SPECIFIC
:
9340 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9341 /* ...fall through... */
9342 case IA64_DVS_INSTR
:
9344 fprintf (stderr
, "Inserting instr serialization\n");
9345 if (rs
->insn_srlz
< STATE_STOP
)
9346 insn_group_break (1, 0, 0);
9347 if (rs
->insn_srlz
< STATE_SRLZ
)
9349 int oldqp
= CURR_SLOT
.qp_regno
;
9350 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9351 /* Manually jam a srlz.i insn into the stream */
9352 CURR_SLOT
.qp_regno
= 0;
9353 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9354 instruction_serialization ();
9355 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9356 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9358 CURR_SLOT
.qp_regno
= oldqp
;
9359 CURR_SLOT
.idesc
= oldidesc
;
9361 insn_group_break (1, 0, 0);
9363 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9364 "other" types of DV are eliminated
9365 by a data serialization */
9368 fprintf (stderr
, "Inserting data serialization\n");
9369 if (rs
->data_srlz
< STATE_STOP
)
9370 insn_group_break (1, 0, 0);
9372 int oldqp
= CURR_SLOT
.qp_regno
;
9373 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9374 /* Manually jam a srlz.d insn into the stream */
9375 CURR_SLOT
.qp_regno
= 0;
9376 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9377 data_serialization ();
9378 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9379 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9381 CURR_SLOT
.qp_regno
= oldqp
;
9382 CURR_SLOT
.idesc
= oldidesc
;
9385 case IA64_DVS_IMPLIED
:
9386 case IA64_DVS_IMPLIEDF
:
9388 fprintf (stderr
, "Inserting stop\n");
9389 insn_group_break (1, 0, 0);
9396 /* Check the resources used by the given opcode against the current dependency
9399 The check is run once for each execution path encountered. In this case,
9400 a unique execution path is the sequence of instructions following a code
9401 entry point, e.g. the following has three execution paths, one starting
9402 at L0, one at L1, and one at L2.
9411 check_dependencies (idesc
)
9412 struct ia64_opcode
*idesc
;
9414 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9418 /* Note that the number of marked resources may change within the
9419 loop if in auto mode. */
9421 while (i
< regdepslen
)
9423 struct rsrc
*rs
= ®deps
[i
];
9424 const struct ia64_dependency
*dep
= rs
->dependency
;
9429 if (dep
->semantics
== IA64_DVS_NONE
9430 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9436 note
= NOTE (opdeps
->chks
[chkind
]);
9438 /* Check this resource against each execution path seen thus far. */
9439 for (path
= 0; path
<= md
.path
; path
++)
9443 /* If the dependency wasn't on the path being checked, ignore it. */
9444 if (rs
->path
< path
)
9447 /* If the QP for this insn implies a QP which has branched, don't
9448 bother checking. Ed. NOTE: I don't think this check is terribly
9449 useful; what's the point of generating code which will only be
9450 reached if its QP is zero?
9451 This code was specifically inserted to handle the following code,
9452 based on notes from Intel's DV checking code, where p1 implies p2.
9458 if (CURR_SLOT
.qp_regno
!= 0)
9462 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9464 if (qp_implies
[implies
].path
>= path
9465 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9466 && qp_implies
[implies
].p2_branched
)
9476 if ((matchtype
= resources_match (rs
, idesc
, note
,
9477 CURR_SLOT
.qp_regno
, path
)) != 0)
9480 char pathmsg
[256] = "";
9481 char indexmsg
[256] = "";
9482 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9485 sprintf (pathmsg
, " when entry is at label '%s'",
9486 md
.entry_labels
[path
- 1]);
9487 if (rs
->specific
&& rs
->index
!= 0)
9488 sprintf (indexmsg
, ", specific resource number is %d",
9490 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9492 (certain
? "violates" : "may violate"),
9493 dv_mode
[dep
->mode
], dep
->name
,
9494 dv_sem
[dep
->semantics
],
9497 if (md
.explicit_mode
)
9499 as_warn ("%s", msg
);
9501 as_warn (_("Only the first path encountering the conflict "
9503 as_warn_where (rs
->file
, rs
->line
,
9504 _("This is the location of the "
9505 "conflicting usage"));
9506 /* Don't bother checking other paths, to avoid duplicating
9513 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9515 remove_marked_resource (rs
);
9517 /* since the set of dependencies has changed, start over */
9518 /* FIXME -- since we're removing dvs as we go, we
9519 probably don't really need to start over... */
9532 /* Register new dependencies based on the given opcode. */
9535 mark_resources (idesc
)
9536 struct ia64_opcode
*idesc
;
9539 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9540 int add_only_qp_reads
= 0;
9542 /* A conditional branch only uses its resources if it is taken; if it is
9543 taken, we stop following that path. The other branch types effectively
9544 *always* write their resources. If it's not taken, register only QP
9546 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9548 add_only_qp_reads
= 1;
9552 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9554 for (i
= 0; i
< opdeps
->nregs
; i
++)
9556 const struct ia64_dependency
*dep
;
9557 struct rsrc specs
[MAX_SPECS
];
9562 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9563 note
= NOTE (opdeps
->regs
[i
]);
9565 if (add_only_qp_reads
9566 && !(dep
->mode
== IA64_DV_WAR
9567 && (dep
->specifier
== IA64_RS_PR
9568 || dep
->specifier
== IA64_RS_PRr
9569 || dep
->specifier
== IA64_RS_PR63
)))
9572 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9575 if (md
.debug_dv
&& !count
)
9576 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9577 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9582 mark_resource (idesc
, dep
, &specs
[count
],
9583 DEP (opdeps
->regs
[i
]), md
.path
);
9586 /* The execution path may affect register values, which may in turn
9587 affect which indirect-access resources are accessed. */
9588 switch (dep
->specifier
)
9600 for (path
= 0; path
< md
.path
; path
++)
9602 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9604 mark_resource (idesc
, dep
, &specs
[count
],
9605 DEP (opdeps
->regs
[i
]), path
);
9612 /* Remove dependencies when they no longer apply. */
9615 update_dependencies (idesc
)
9616 struct ia64_opcode
*idesc
;
9620 if (strcmp (idesc
->name
, "srlz.i") == 0)
9622 instruction_serialization ();
9624 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9626 data_serialization ();
9628 else if (is_interruption_or_rfi (idesc
)
9629 || is_taken_branch (idesc
))
9631 /* Although technically the taken branch doesn't clear dependencies
9632 which require a srlz.[id], we don't follow the branch; the next
9633 instruction is assumed to start with a clean slate. */
9637 else if (is_conditional_branch (idesc
)
9638 && CURR_SLOT
.qp_regno
!= 0)
9640 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9642 for (i
= 0; i
< qp_implieslen
; i
++)
9644 /* If the conditional branch's predicate is implied by the predicate
9645 in an existing dependency, remove that dependency. */
9646 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9649 /* Note that this implied predicate takes a branch so that if
9650 a later insn generates a DV but its predicate implies this
9651 one, we can avoid the false DV warning. */
9652 qp_implies
[i
].p2_branched
= 1;
9653 while (depind
< regdepslen
)
9655 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9657 print_dependency ("Removing", depind
);
9658 regdeps
[depind
] = regdeps
[--regdepslen
];
9665 /* Any marked resources which have this same predicate should be
9666 cleared, provided that the QP hasn't been modified between the
9667 marking instruction and the branch. */
9670 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9675 while (i
< regdepslen
)
9677 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9678 && regdeps
[i
].link_to_qp_branch
9679 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9680 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9682 /* Treat like a taken branch */
9683 print_dependency ("Removing", i
);
9684 regdeps
[i
] = regdeps
[--regdepslen
];
9693 /* Examine the current instruction for dependency violations. */
9697 struct ia64_opcode
*idesc
;
9701 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9702 idesc
->name
, CURR_SLOT
.src_line
,
9703 idesc
->dependencies
->nchks
,
9704 idesc
->dependencies
->nregs
);
9707 /* Look through the list of currently marked resources; if the current
9708 instruction has the dependency in its chks list which uses that resource,
9709 check against the specific resources used. */
9710 check_dependencies (idesc
);
9712 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9713 then add them to the list of marked resources. */
9714 mark_resources (idesc
);
9716 /* There are several types of dependency semantics, and each has its own
9717 requirements for being cleared
9719 Instruction serialization (insns separated by interruption, rfi, or
9720 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9722 Data serialization (instruction serialization, or writer + srlz.d +
9723 reader, where writer and srlz.d are in separate groups) clears
9724 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9725 always be the case).
9727 Instruction group break (groups separated by stop, taken branch,
9728 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9730 update_dependencies (idesc
);
9732 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9733 warning. Keep track of as many as possible that are useful. */
9734 note_register_values (idesc
);
9736 /* We don't need or want this anymore. */
9737 md
.mem_offset
.hint
= 0;
9742 /* Translate one line of assembly. Pseudo ops and labels do not show
9748 char *saved_input_line_pointer
, *mnemonic
;
9749 const struct pseudo_opcode
*pdesc
;
9750 struct ia64_opcode
*idesc
;
9751 unsigned char qp_regno
;
9755 saved_input_line_pointer
= input_line_pointer
;
9756 input_line_pointer
= str
;
9758 /* extract the opcode (mnemonic): */
9760 mnemonic
= input_line_pointer
;
9761 ch
= get_symbol_end ();
9762 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9765 *input_line_pointer
= ch
;
9766 (*pdesc
->handler
) (pdesc
->arg
);
9770 /* Find the instruction descriptor matching the arguments. */
9772 idesc
= ia64_find_opcode (mnemonic
);
9773 *input_line_pointer
= ch
;
9776 as_bad ("Unknown opcode `%s'", mnemonic
);
9780 idesc
= parse_operands (idesc
);
9784 /* Handle the dynamic ops we can handle now: */
9785 if (idesc
->type
== IA64_TYPE_DYN
)
9787 if (strcmp (idesc
->name
, "add") == 0)
9789 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9790 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9794 ia64_free_opcode (idesc
);
9795 idesc
= ia64_find_opcode (mnemonic
);
9797 know (!idesc
->next
);
9800 else if (strcmp (idesc
->name
, "mov") == 0)
9802 enum ia64_opnd opnd1
, opnd2
;
9805 opnd1
= idesc
->operands
[0];
9806 opnd2
= idesc
->operands
[1];
9807 if (opnd1
== IA64_OPND_AR3
)
9809 else if (opnd2
== IA64_OPND_AR3
)
9813 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9814 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9818 ia64_free_opcode (idesc
);
9819 idesc
= ia64_find_opcode (mnemonic
);
9820 while (idesc
!= NULL
9821 && (idesc
->operands
[0] != opnd1
9822 || idesc
->operands
[1] != opnd2
))
9823 idesc
= get_next_opcode (idesc
);
9828 if (md
.qp
.X_op
== O_register
)
9830 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9831 md
.qp
.X_op
= O_absent
;
9834 flags
= idesc
->flags
;
9836 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9837 insn_group_break (1, 0, 0);
9839 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9841 as_bad ("`%s' cannot be predicated", idesc
->name
);
9845 /* Build the instruction. */
9846 CURR_SLOT
.qp_regno
= qp_regno
;
9847 CURR_SLOT
.idesc
= idesc
;
9848 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9849 dwarf2_where (&CURR_SLOT
.debug_line
);
9851 /* Add unwind entry, if there is one. */
9852 if (unwind
.current_entry
)
9854 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9855 unwind
.current_entry
= NULL
;
9858 /* Check for dependency violations. */
9862 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9863 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9866 if ((flags
& IA64_OPCODE_LAST
) != 0)
9867 insn_group_break (1, 0, 0);
9869 md
.last_text_seg
= now_seg
;
9872 input_line_pointer
= saved_input_line_pointer
;
9875 /* Called when symbol NAME cannot be found in the symbol table.
9876 Should be used for dynamic valued symbols only. */
9879 md_undefined_symbol (name
)
9880 char *name ATTRIBUTE_UNUSED
;
9885 /* Called for any expression that can not be recognized. When the
9886 function is called, `input_line_pointer' will point to the start of
9893 enum pseudo_type pseudo_type
;
9898 switch (*input_line_pointer
)
9901 /* Find what relocation pseudo-function we're dealing with. */
9903 ch
= *++input_line_pointer
;
9904 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9905 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9907 len
= strlen (pseudo_func
[i
].name
);
9908 if (strncmp (pseudo_func
[i
].name
+ 1,
9909 input_line_pointer
+ 1, len
- 1) == 0
9910 && !is_part_of_name (input_line_pointer
[len
]))
9912 input_line_pointer
+= len
;
9913 pseudo_type
= pseudo_func
[i
].type
;
9917 switch (pseudo_type
)
9919 case PSEUDO_FUNC_RELOC
:
9921 if (*input_line_pointer
!= '(')
9923 as_bad ("Expected '('");
9927 ++input_line_pointer
;
9929 if (*input_line_pointer
++ != ')')
9931 as_bad ("Missing ')'");
9934 if (e
->X_op
!= O_symbol
)
9936 if (e
->X_op
!= O_pseudo_fixup
)
9938 as_bad ("Not a symbolic expression");
9941 if (i
!= FUNC_LT_RELATIVE
)
9943 as_bad ("Illegal combination of relocation functions");
9946 switch (S_GET_VALUE (e
->X_op_symbol
))
9948 case FUNC_FPTR_RELATIVE
:
9949 i
= FUNC_LT_FPTR_RELATIVE
; break;
9950 case FUNC_DTP_MODULE
:
9951 i
= FUNC_LT_DTP_MODULE
; break;
9952 case FUNC_DTP_RELATIVE
:
9953 i
= FUNC_LT_DTP_RELATIVE
; break;
9954 case FUNC_TP_RELATIVE
:
9955 i
= FUNC_LT_TP_RELATIVE
; break;
9957 as_bad ("Illegal combination of relocation functions");
9961 /* Make sure gas doesn't get rid of local symbols that are used
9963 e
->X_op
= O_pseudo_fixup
;
9964 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9967 case PSEUDO_FUNC_CONST
:
9968 e
->X_op
= O_constant
;
9969 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9972 case PSEUDO_FUNC_REG
:
9973 e
->X_op
= O_register
;
9974 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9978 name
= input_line_pointer
- 1;
9980 as_bad ("Unknown pseudo function `%s'", name
);
9986 ++input_line_pointer
;
9988 if (*input_line_pointer
!= ']')
9990 as_bad ("Closing bracket misssing");
9995 if (e
->X_op
!= O_register
)
9996 as_bad ("Register expected as index");
9998 ++input_line_pointer
;
10009 ignore_rest_of_line ();
10012 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
10013 a section symbol plus some offset. For relocs involving @fptr(),
10014 directives we don't want such adjustments since we need to have the
10015 original symbol's name in the reloc. */
10017 ia64_fix_adjustable (fix
)
10020 /* Prevent all adjustments to global symbols */
10021 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
10024 switch (fix
->fx_r_type
)
10026 case BFD_RELOC_IA64_FPTR64I
:
10027 case BFD_RELOC_IA64_FPTR32MSB
:
10028 case BFD_RELOC_IA64_FPTR32LSB
:
10029 case BFD_RELOC_IA64_FPTR64MSB
:
10030 case BFD_RELOC_IA64_FPTR64LSB
:
10031 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10032 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10042 ia64_force_relocation (fix
)
10045 switch (fix
->fx_r_type
)
10047 case BFD_RELOC_IA64_FPTR64I
:
10048 case BFD_RELOC_IA64_FPTR32MSB
:
10049 case BFD_RELOC_IA64_FPTR32LSB
:
10050 case BFD_RELOC_IA64_FPTR64MSB
:
10051 case BFD_RELOC_IA64_FPTR64LSB
:
10053 case BFD_RELOC_IA64_LTOFF22
:
10054 case BFD_RELOC_IA64_LTOFF64I
:
10055 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10056 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10057 case BFD_RELOC_IA64_PLTOFF22
:
10058 case BFD_RELOC_IA64_PLTOFF64I
:
10059 case BFD_RELOC_IA64_PLTOFF64MSB
:
10060 case BFD_RELOC_IA64_PLTOFF64LSB
:
10062 case BFD_RELOC_IA64_LTOFF22X
:
10063 case BFD_RELOC_IA64_LDXMOV
:
10070 return generic_force_reloc (fix
);
10073 /* Decide from what point a pc-relative relocation is relative to,
10074 relative to the pc-relative fixup. Er, relatively speaking. */
10076 ia64_pcrel_from_section (fix
, sec
)
10080 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
10082 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
10089 /* Used to emit section-relative relocs for the dwarf2 debug data. */
10091 ia64_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10095 expr
.X_op
= O_pseudo_fixup
;
10096 expr
.X_op_symbol
= pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
;
10097 expr
.X_add_number
= 0;
10098 expr
.X_add_symbol
= symbol
;
10099 emit_expr (&expr
, size
);
10102 /* This is called whenever some data item (not an instruction) needs a
10103 fixup. We pick the right reloc code depending on the byteorder
10104 currently in effect. */
10106 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
10112 bfd_reloc_code_real_type code
;
10117 /* There are no reloc for 8 and 16 bit quantities, but we allow
10118 them here since they will work fine as long as the expression
10119 is fully defined at the end of the pass over the source file. */
10120 case 1: code
= BFD_RELOC_8
; break;
10121 case 2: code
= BFD_RELOC_16
; break;
10123 if (target_big_endian
)
10124 code
= BFD_RELOC_IA64_DIR32MSB
;
10126 code
= BFD_RELOC_IA64_DIR32LSB
;
10130 /* In 32-bit mode, data8 could mean function descriptors too. */
10131 if (exp
->X_op
== O_pseudo_fixup
10132 && exp
->X_op_symbol
10133 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
10134 && !(md
.flags
& EF_IA_64_ABI64
))
10136 if (target_big_endian
)
10137 code
= BFD_RELOC_IA64_IPLTMSB
;
10139 code
= BFD_RELOC_IA64_IPLTLSB
;
10140 exp
->X_op
= O_symbol
;
10145 if (target_big_endian
)
10146 code
= BFD_RELOC_IA64_DIR64MSB
;
10148 code
= BFD_RELOC_IA64_DIR64LSB
;
10153 if (exp
->X_op
== O_pseudo_fixup
10154 && exp
->X_op_symbol
10155 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
)
10157 if (target_big_endian
)
10158 code
= BFD_RELOC_IA64_IPLTMSB
;
10160 code
= BFD_RELOC_IA64_IPLTLSB
;
10161 exp
->X_op
= O_symbol
;
10167 as_bad ("Unsupported fixup size %d", nbytes
);
10168 ignore_rest_of_line ();
10172 if (exp
->X_op
== O_pseudo_fixup
)
10174 exp
->X_op
= O_symbol
;
10175 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
10176 /* ??? If code unchanged, unsupported. */
10179 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
10180 /* We need to store the byte order in effect in case we're going
10181 to fix an 8 or 16 bit relocation (for which there no real
10182 relocs available). See md_apply_fix3(). */
10183 fix
->tc_fix_data
.bigendian
= target_big_endian
;
10186 /* Return the actual relocation we wish to associate with the pseudo
10187 reloc described by SYM and R_TYPE. SYM should be one of the
10188 symbols in the pseudo_func array, or NULL. */
10190 static bfd_reloc_code_real_type
10191 ia64_gen_real_reloc_type (sym
, r_type
)
10192 struct symbol
*sym
;
10193 bfd_reloc_code_real_type r_type
;
10195 bfd_reloc_code_real_type
new = 0;
10202 switch (S_GET_VALUE (sym
))
10204 case FUNC_FPTR_RELATIVE
:
10207 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
10208 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
10209 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
10210 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
10211 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
10216 case FUNC_GP_RELATIVE
:
10219 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
10220 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
10221 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
10222 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
10223 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
10224 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
10229 case FUNC_LT_RELATIVE
:
10232 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
10233 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
10238 case FUNC_LT_RELATIVE_X
:
10241 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22X
; break;
10246 case FUNC_PC_RELATIVE
:
10249 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
10250 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
10251 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
10252 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
10253 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
10254 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
10259 case FUNC_PLT_RELATIVE
:
10262 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
10263 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
10264 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
10265 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
10270 case FUNC_SEC_RELATIVE
:
10273 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
10274 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
10275 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
10276 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
10281 case FUNC_SEG_RELATIVE
:
10284 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
10285 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
10286 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
10287 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
10292 case FUNC_LTV_RELATIVE
:
10295 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
10296 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
10297 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
10298 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
10303 case FUNC_LT_FPTR_RELATIVE
:
10306 case BFD_RELOC_IA64_IMM22
:
10307 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
10308 case BFD_RELOC_IA64_IMM64
:
10309 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
10315 case FUNC_TP_RELATIVE
:
10318 case BFD_RELOC_IA64_IMM14
:
10319 new = BFD_RELOC_IA64_TPREL14
; break;
10320 case BFD_RELOC_IA64_IMM22
:
10321 new = BFD_RELOC_IA64_TPREL22
; break;
10322 case BFD_RELOC_IA64_IMM64
:
10323 new = BFD_RELOC_IA64_TPREL64I
; break;
10329 case FUNC_LT_TP_RELATIVE
:
10332 case BFD_RELOC_IA64_IMM22
:
10333 new = BFD_RELOC_IA64_LTOFF_TPREL22
; break;
10339 case FUNC_LT_DTP_MODULE
:
10342 case BFD_RELOC_IA64_IMM22
:
10343 new = BFD_RELOC_IA64_LTOFF_DTPMOD22
; break;
10349 case FUNC_DTP_RELATIVE
:
10352 case BFD_RELOC_IA64_DIR64MSB
:
10353 new = BFD_RELOC_IA64_DTPREL64MSB
; break;
10354 case BFD_RELOC_IA64_DIR64LSB
:
10355 new = BFD_RELOC_IA64_DTPREL64LSB
; break;
10356 case BFD_RELOC_IA64_IMM14
:
10357 new = BFD_RELOC_IA64_DTPREL14
; break;
10358 case BFD_RELOC_IA64_IMM22
:
10359 new = BFD_RELOC_IA64_DTPREL22
; break;
10360 case BFD_RELOC_IA64_IMM64
:
10361 new = BFD_RELOC_IA64_DTPREL64I
; break;
10367 case FUNC_LT_DTP_RELATIVE
:
10370 case BFD_RELOC_IA64_IMM22
:
10371 new = BFD_RELOC_IA64_LTOFF_DTPREL22
; break;
10377 case FUNC_IPLT_RELOC
:
10384 /* Hmmmm. Should this ever occur? */
10391 /* Here is where generate the appropriate reloc for pseudo relocation
10394 ia64_validate_fix (fix
)
10397 switch (fix
->fx_r_type
)
10399 case BFD_RELOC_IA64_FPTR64I
:
10400 case BFD_RELOC_IA64_FPTR32MSB
:
10401 case BFD_RELOC_IA64_FPTR64LSB
:
10402 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10403 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10404 if (fix
->fx_offset
!= 0)
10405 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10406 "No addend allowed in @fptr() relocation");
10416 fix_insn (fix
, odesc
, value
)
10418 const struct ia64_operand
*odesc
;
10421 bfd_vma insn
[3], t0
, t1
, control_bits
;
10426 slot
= fix
->fx_where
& 0x3;
10427 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10429 /* Bundles are always in little-endian byte order */
10430 t0
= bfd_getl64 (fixpos
);
10431 t1
= bfd_getl64 (fixpos
+ 8);
10432 control_bits
= t0
& 0x1f;
10433 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10434 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10435 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10438 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10440 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10441 insn
[2] |= (((value
& 0x7f) << 13)
10442 | (((value
>> 7) & 0x1ff) << 27)
10443 | (((value
>> 16) & 0x1f) << 22)
10444 | (((value
>> 21) & 0x1) << 21)
10445 | (((value
>> 63) & 0x1) << 36));
10447 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10449 if (value
& ~0x3fffffffffffffffULL
)
10450 err
= "integer operand out of range";
10451 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10452 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10454 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10457 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10458 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10459 | (((value
>> 0) & 0xfffff) << 13));
10462 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10465 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10467 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10468 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10469 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10470 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10473 /* Attempt to simplify or even eliminate a fixup. The return value is
10474 ignored; perhaps it was once meaningful, but now it is historical.
10475 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10477 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10481 md_apply_fix3 (fix
, valP
, seg
)
10484 segT seg ATTRIBUTE_UNUSED
;
10487 valueT value
= *valP
;
10489 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10493 switch (fix
->fx_r_type
)
10495 case BFD_RELOC_IA64_DIR32MSB
:
10496 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10499 case BFD_RELOC_IA64_DIR32LSB
:
10500 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10503 case BFD_RELOC_IA64_DIR64MSB
:
10504 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10507 case BFD_RELOC_IA64_DIR64LSB
:
10508 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10517 switch (fix
->fx_r_type
)
10519 case BFD_RELOC_UNUSED
:
10520 /* This must be a TAG13 or TAG13b operand. There are no external
10521 relocs defined for them, so we must give an error. */
10522 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10523 "%s must have a constant value",
10524 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10528 case BFD_RELOC_IA64_TPREL14
:
10529 case BFD_RELOC_IA64_TPREL22
:
10530 case BFD_RELOC_IA64_TPREL64I
:
10531 case BFD_RELOC_IA64_LTOFF_TPREL22
:
10532 case BFD_RELOC_IA64_LTOFF_DTPMOD22
:
10533 case BFD_RELOC_IA64_DTPREL14
:
10534 case BFD_RELOC_IA64_DTPREL22
:
10535 case BFD_RELOC_IA64_DTPREL64I
:
10536 case BFD_RELOC_IA64_LTOFF_DTPREL22
:
10537 S_SET_THREAD_LOCAL (fix
->fx_addsy
);
10544 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10546 if (fix
->tc_fix_data
.bigendian
)
10547 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10549 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10554 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10559 /* Generate the BFD reloc to be stuck in the object file from the
10560 fixup used internally in the assembler. */
10563 tc_gen_reloc (sec
, fixp
)
10564 asection
*sec ATTRIBUTE_UNUSED
;
10569 reloc
= xmalloc (sizeof (*reloc
));
10570 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10571 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10572 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10573 reloc
->addend
= fixp
->fx_offset
;
10574 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10578 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10579 "Cannot represent %s relocation in object file",
10580 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10585 /* Turn a string in input_line_pointer into a floating point constant
10586 of type TYPE, and store the appropriate bytes in *LIT. The number
10587 of LITTLENUMS emitted is stored in *SIZE. An error message is
10588 returned, or NULL on OK. */
10590 #define MAX_LITTLENUMS 5
10593 md_atof (type
, lit
, size
)
10598 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10628 return "Bad call to MD_ATOF()";
10630 t
= atof_ieee (input_line_pointer
, type
, words
);
10632 input_line_pointer
= t
;
10634 (*ia64_float_to_chars
) (lit
, words
, prec
);
10638 /* It is 10 byte floating point with 6 byte padding. */
10639 memset (&lit
[10], 0, 6);
10640 *size
= 8 * sizeof (LITTLENUM_TYPE
);
10643 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10648 /* Handle ia64 specific semantics of the align directive. */
10651 ia64_md_do_align (n
, fill
, len
, max
)
10652 int n ATTRIBUTE_UNUSED
;
10653 const char *fill ATTRIBUTE_UNUSED
;
10654 int len ATTRIBUTE_UNUSED
;
10655 int max ATTRIBUTE_UNUSED
;
10657 if (subseg_text_p (now_seg
))
10658 ia64_flush_insns ();
10661 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10662 of an rs_align_code fragment. */
10665 ia64_handle_align (fragp
)
10668 /* Use mfi bundle of nops with no stop bits. */
10669 static const unsigned char be_nop
[]
10670 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10671 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10672 static const unsigned char le_nop
[]
10673 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10674 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10679 if (fragp
->fr_type
!= rs_align_code
)
10682 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10683 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10685 /* Make sure we are on a 16-byte boundary, in case someone has been
10686 putting data into a text section. */
10689 int fix
= bytes
& 15;
10690 memset (p
, 0, fix
);
10693 fragp
->fr_fix
+= fix
;
10696 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10697 fragp
->fr_var
= 16;
10701 ia64_float_to_chars_bigendian (char *lit
, LITTLENUM_TYPE
*words
,
10706 number_to_chars_bigendian (lit
, (long) (*words
++),
10707 sizeof (LITTLENUM_TYPE
));
10708 lit
+= sizeof (LITTLENUM_TYPE
);
10713 ia64_float_to_chars_littleendian (char *lit
, LITTLENUM_TYPE
*words
,
10718 number_to_chars_littleendian (lit
, (long) (words
[prec
]),
10719 sizeof (LITTLENUM_TYPE
));
10720 lit
+= sizeof (LITTLENUM_TYPE
);
10725 ia64_elf_section_change_hook (void)
10727 dot_byteorder (-1);
10730 /* Check if a label should be made global. */
10732 ia64_check_label (symbolS
*label
)
10734 if (*input_line_pointer
== ':')
10736 S_SET_EXTERNAL (label
);
10737 input_line_pointer
++;