1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 /* IA-64 ABI section pseudo-ops. */
65 SPECIAL_SECTION_BSS
= 0,
67 SPECIAL_SECTION_SDATA
,
68 SPECIAL_SECTION_RODATA
,
69 SPECIAL_SECTION_COMMENT
,
70 SPECIAL_SECTION_UNWIND
,
71 SPECIAL_SECTION_UNWIND_INFO
,
72 /* HPUX specific section pseudo-ops. */
73 SPECIAL_SECTION_INIT_ARRAY
,
74 SPECIAL_SECTION_FINI_ARRAY
,
87 FUNC_LT_FPTR_RELATIVE
,
93 REG_FR
= (REG_GR
+ 128),
94 REG_AR
= (REG_FR
+ 128),
95 REG_CR
= (REG_AR
+ 128),
96 REG_P
= (REG_CR
+ 128),
97 REG_BR
= (REG_P
+ 64),
98 REG_IP
= (REG_BR
+ 8),
105 /* The following are pseudo-registers for use by gas only. */
117 /* The following pseudo-registers are used for unwind directives only: */
125 DYNREG_GR
= 0, /* dynamic general purpose register */
126 DYNREG_FR
, /* dynamic floating point register */
127 DYNREG_PR
, /* dynamic predicate register */
131 enum operand_match_result
134 OPERAND_OUT_OF_RANGE
,
138 /* On the ia64, we can't know the address of a text label until the
139 instructions are packed into a bundle. To handle this, we keep
140 track of the list of labels that appear in front of each
144 struct label_fix
*next
;
148 extern int target_big_endian
;
150 /* Characters which always start a comment. */
151 const char comment_chars
[] = "";
153 /* Characters which start a comment at the beginning of a line. */
154 const char line_comment_chars
[] = "#";
156 /* Characters which may be used to separate multiple commands on a
158 const char line_separator_chars
[] = ";";
160 /* Characters which are used to indicate an exponent in a floating
162 const char EXP_CHARS
[] = "eE";
164 /* Characters which mean that a number is a floating point constant,
166 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
168 /* ia64-specific option processing: */
170 const char *md_shortopts
= "m:N:x::";
172 struct option md_longopts
[] =
174 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
175 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
176 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
177 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
180 size_t md_longopts_size
= sizeof (md_longopts
);
184 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
185 struct hash_control
*reg_hash
; /* register name hash table */
186 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
187 struct hash_control
*const_hash
; /* constant hash table */
188 struct hash_control
*entry_hash
; /* code entry hint hash table */
190 symbolS
*regsym
[REG_NUM
];
192 /* If X_op is != O_absent, the registername for the instruction's
193 qualifying predicate. If NULL, p0 is assumed for instructions
194 that are predicatable. */
201 explicit_mode
: 1, /* which mode we're in */
202 default_explicit_mode
: 1, /* which mode is the default */
203 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
205 keep_pending_output
: 1;
207 /* Each bundle consists of up to three instructions. We keep
208 track of four most recent instructions so we can correctly set
209 the end_of_insn_group for the last instruction in a bundle. */
211 int num_slots_in_use
;
215 end_of_insn_group
: 1,
216 manual_bundling_on
: 1,
217 manual_bundling_off
: 1;
218 signed char user_template
; /* user-selected template, if any */
219 unsigned char qp_regno
; /* qualifying predicate */
220 /* This duplicates a good fraction of "struct fix" but we
221 can't use a "struct fix" instead since we can't call
222 fix_new_exp() until we know the address of the instruction. */
226 bfd_reloc_code_real_type code
;
227 enum ia64_opnd opnd
; /* type of operand in need of fix */
228 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
229 expressionS expr
; /* the value to be inserted */
231 fixup
[2]; /* at most two fixups per insn */
232 struct ia64_opcode
*idesc
;
233 struct label_fix
*label_fixups
;
234 struct label_fix
*tag_fixups
;
235 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
238 unsigned int src_line
;
239 struct dwarf2_line_info debug_line
;
247 struct dynreg
*next
; /* next dynamic register */
249 unsigned short base
; /* the base register number */
250 unsigned short num_regs
; /* # of registers in this set */
252 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
254 flagword flags
; /* ELF-header flags */
257 unsigned hint
:1; /* is this hint currently valid? */
258 bfd_vma offset
; /* mem.offset offset */
259 bfd_vma base
; /* mem.offset base */
262 int path
; /* number of alt. entry points seen */
263 const char **entry_labels
; /* labels of all alternate paths in
264 the current DV-checking block. */
265 int maxpaths
; /* size currently allocated for
267 /* Support for hardware errata workarounds. */
269 /* Record data about the last three insn groups. */
272 /* B-step workaround.
273 For each predicate register, this is set if the corresponding insn
274 group conditionally sets this register with one of the affected
277 /* B-step workaround.
278 For each general register, this is set if the corresponding insn
279 a) is conditional one one of the predicate registers for which
280 P_REG_SET is 1 in the corresponding entry of the previous group,
281 b) sets this general register with one of the affected
283 int g_reg_set_conditionally
[128];
287 int pointer_size
; /* size in bytes of a pointer */
288 int pointer_size_shift
; /* shift size of a pointer for alignment */
292 /* application registers: */
298 #define AR_BSPSTORE 18
313 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
314 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
315 {"ar.rsc", 16}, {"ar.bsp", 17},
316 {"ar.bspstore", 18}, {"ar.rnat", 19},
317 {"ar.fcr", 21}, {"ar.eflag", 24},
318 {"ar.csd", 25}, {"ar.ssd", 26},
319 {"ar.cflg", 27}, {"ar.fsr", 28},
320 {"ar.fir", 29}, {"ar.fdr", 30},
321 {"ar.ccv", 32}, {"ar.unat", 36},
322 {"ar.fpsr", 40}, {"ar.itc", 44},
323 {"ar.pfs", 64}, {"ar.lc", 65},
344 /* control registers: */
386 static const struct const_desc
393 /* PSR constant masks: */
396 {"psr.be", ((valueT
) 1) << 1},
397 {"psr.up", ((valueT
) 1) << 2},
398 {"psr.ac", ((valueT
) 1) << 3},
399 {"psr.mfl", ((valueT
) 1) << 4},
400 {"psr.mfh", ((valueT
) 1) << 5},
402 {"psr.ic", ((valueT
) 1) << 13},
403 {"psr.i", ((valueT
) 1) << 14},
404 {"psr.pk", ((valueT
) 1) << 15},
406 {"psr.dt", ((valueT
) 1) << 17},
407 {"psr.dfl", ((valueT
) 1) << 18},
408 {"psr.dfh", ((valueT
) 1) << 19},
409 {"psr.sp", ((valueT
) 1) << 20},
410 {"psr.pp", ((valueT
) 1) << 21},
411 {"psr.di", ((valueT
) 1) << 22},
412 {"psr.si", ((valueT
) 1) << 23},
413 {"psr.db", ((valueT
) 1) << 24},
414 {"psr.lp", ((valueT
) 1) << 25},
415 {"psr.tb", ((valueT
) 1) << 26},
416 {"psr.rt", ((valueT
) 1) << 27},
417 /* 28-31: reserved */
418 /* 32-33: cpl (current privilege level) */
419 {"psr.is", ((valueT
) 1) << 34},
420 {"psr.mc", ((valueT
) 1) << 35},
421 {"psr.it", ((valueT
) 1) << 36},
422 {"psr.id", ((valueT
) 1) << 37},
423 {"psr.da", ((valueT
) 1) << 38},
424 {"psr.dd", ((valueT
) 1) << 39},
425 {"psr.ss", ((valueT
) 1) << 40},
426 /* 41-42: ri (restart instruction) */
427 {"psr.ed", ((valueT
) 1) << 43},
428 {"psr.bn", ((valueT
) 1) << 44},
431 /* indirect register-sets/memory: */
440 { "CPUID", IND_CPUID
},
441 { "cpuid", IND_CPUID
},
453 /* Pseudo functions used to indicate relocation types (these functions
454 start with an at sign (@). */
476 /* reloc pseudo functions (these must come first!): */
477 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
478 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
479 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
480 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
481 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
482 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
483 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
484 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
485 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
487 /* mbtype4 constants: */
488 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
489 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
490 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
491 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
492 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
494 /* fclass constants: */
495 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
496 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
497 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
498 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
499 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
500 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
501 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
502 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
503 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
505 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
507 /* unwind-related constants: */
508 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
509 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
510 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
512 /* unwind-related registers: */
513 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
516 /* 41-bit nop opcodes (one per unit): */
517 static const bfd_vma nop
[IA64_NUM_UNITS
] =
519 0x0000000000LL
, /* NIL => break 0 */
520 0x0008000000LL
, /* I-unit nop */
521 0x0008000000LL
, /* M-unit nop */
522 0x4000000000LL
, /* B-unit nop */
523 0x0008000000LL
, /* F-unit nop */
524 0x0008000000LL
, /* L-"unit" nop */
525 0x0008000000LL
, /* X-unit nop */
528 /* Can't be `const' as it's passed to input routines (which have the
529 habit of setting temporary sentinels. */
530 static char special_section_name
[][20] =
532 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
533 {".IA_64.unwind"}, {".IA_64.unwind_info"},
534 {".init_array"}, {".fini_array"}
537 static char *special_linkonce_name
[] =
539 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
542 /* The best template for a particular sequence of up to three
544 #define N IA64_NUM_TYPES
545 static unsigned char best_template
[N
][N
][N
];
548 /* Resource dependencies currently in effect */
550 int depind
; /* dependency index */
551 const struct ia64_dependency
*dependency
; /* actual dependency */
552 unsigned specific
:1, /* is this a specific bit/regno? */
553 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
554 int index
; /* specific regno/bit within dependency */
555 int note
; /* optional qualifying note (0 if none) */
559 int insn_srlz
; /* current insn serialization state */
560 int data_srlz
; /* current data serialization state */
561 int qp_regno
; /* qualifying predicate for this usage */
562 char *file
; /* what file marked this dependency */
563 unsigned int line
; /* what line marked this dependency */
564 struct mem_offset mem_offset
; /* optional memory offset hint */
565 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
566 int path
; /* corresponding code entry index */
568 static int regdepslen
= 0;
569 static int regdepstotlen
= 0;
570 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
571 static const char *dv_sem
[] = { "none", "implied", "impliedf",
572 "data", "instr", "specific", "stop", "other" };
573 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
575 /* Current state of PR mutexation */
576 static struct qpmutex
{
579 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
580 static int qp_mutexeslen
= 0;
581 static int qp_mutexestotlen
= 0;
582 static valueT qp_safe_across_calls
= 0;
584 /* Current state of PR implications */
585 static struct qp_imply
{
588 unsigned p2_branched
:1;
590 } *qp_implies
= NULL
;
591 static int qp_implieslen
= 0;
592 static int qp_impliestotlen
= 0;
594 /* Keep track of static GR values so that indirect register usage can
595 sometimes be tracked. */
600 } gr_values
[128] = {{ 1, 0, 0 }};
602 /* These are the routines required to output the various types of
605 /* A slot_number is a frag address plus the slot index (0-2). We use the
606 frag address here so that if there is a section switch in the middle of
607 a function, then instructions emitted to a different section are not
608 counted. Since there may be more than one frag for a function, this
609 means we also need to keep track of which frag this address belongs to
610 so we can compute inter-frag distances. This also nicely solves the
611 problem with nops emitted for align directives, which can't easily be
612 counted, but can easily be derived from frag sizes. */
614 typedef struct unw_rec_list
{
616 unsigned long slot_number
;
618 struct unw_rec_list
*next
;
621 #define SLOT_NUM_NOT_SET (unsigned)-1
625 unsigned long next_slot_number
;
626 fragS
*next_slot_frag
;
628 /* Maintain a list of unwind entries for the current function. */
632 /* Any unwind entires that should be attached to the current slot
633 that an insn is being constructed for. */
634 unw_rec_list
*current_entry
;
636 /* These are used to create the unwind table entry for this function. */
639 symbolS
*info
; /* pointer to unwind info */
640 symbolS
*personality_routine
;
642 subsegT saved_text_subseg
;
643 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
645 /* TRUE if processing unwind directives in a prologue region. */
648 unsigned int prologue_count
; /* number of .prologues seen so far */
651 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
653 /* Forward delarations: */
654 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
655 static void set_section
PARAMS ((char *name
));
656 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
657 unsigned int, unsigned int));
658 static void dot_radix
PARAMS ((int));
659 static void dot_special_section
PARAMS ((int));
660 static void dot_proc
PARAMS ((int));
661 static void dot_fframe
PARAMS ((int));
662 static void dot_vframe
PARAMS ((int));
663 static void dot_vframesp
PARAMS ((int));
664 static void dot_vframepsp
PARAMS ((int));
665 static void dot_save
PARAMS ((int));
666 static void dot_restore
PARAMS ((int));
667 static void dot_restorereg
PARAMS ((int));
668 static void dot_restorereg_p
PARAMS ((int));
669 static void dot_handlerdata
PARAMS ((int));
670 static void dot_unwentry
PARAMS ((int));
671 static void dot_altrp
PARAMS ((int));
672 static void dot_savemem
PARAMS ((int));
673 static void dot_saveg
PARAMS ((int));
674 static void dot_savef
PARAMS ((int));
675 static void dot_saveb
PARAMS ((int));
676 static void dot_savegf
PARAMS ((int));
677 static void dot_spill
PARAMS ((int));
678 static void dot_spillreg
PARAMS ((int));
679 static void dot_spillmem
PARAMS ((int));
680 static void dot_spillreg_p
PARAMS ((int));
681 static void dot_spillmem_p
PARAMS ((int));
682 static void dot_label_state
PARAMS ((int));
683 static void dot_copy_state
PARAMS ((int));
684 static void dot_unwabi
PARAMS ((int));
685 static void dot_personality
PARAMS ((int));
686 static void dot_body
PARAMS ((int));
687 static void dot_prologue
PARAMS ((int));
688 static void dot_endp
PARAMS ((int));
689 static void dot_template
PARAMS ((int));
690 static void dot_regstk
PARAMS ((int));
691 static void dot_rot
PARAMS ((int));
692 static void dot_byteorder
PARAMS ((int));
693 static void dot_psr
PARAMS ((int));
694 static void dot_alias
PARAMS ((int));
695 static void dot_ln
PARAMS ((int));
696 static char *parse_section_name
PARAMS ((void));
697 static void dot_xdata
PARAMS ((int));
698 static void stmt_float_cons
PARAMS ((int));
699 static void stmt_cons_ua
PARAMS ((int));
700 static void dot_xfloat_cons
PARAMS ((int));
701 static void dot_xstringer
PARAMS ((int));
702 static void dot_xdata_ua
PARAMS ((int));
703 static void dot_xfloat_cons_ua
PARAMS ((int));
704 static void print_prmask
PARAMS ((valueT mask
));
705 static void dot_pred_rel
PARAMS ((int));
706 static void dot_reg_val
PARAMS ((int));
707 static void dot_dv_mode
PARAMS ((int));
708 static void dot_entry
PARAMS ((int));
709 static void dot_mem_offset
PARAMS ((int));
710 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
711 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
712 static void declare_register_set
PARAMS ((const char *, int, int));
713 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
714 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
717 static int parse_operand
PARAMS ((expressionS
*e
));
718 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
719 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
720 static void emit_one_bundle
PARAMS ((void));
721 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
722 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
723 bfd_reloc_code_real_type r_type
));
724 static void insn_group_break
PARAMS ((int, int, int));
725 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
726 struct rsrc
*, int depind
, int path
));
727 static void add_qp_mutex
PARAMS((valueT mask
));
728 static void add_qp_imply
PARAMS((int p1
, int p2
));
729 static void clear_qp_branch_flag
PARAMS((valueT mask
));
730 static void clear_qp_mutex
PARAMS((valueT mask
));
731 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
732 static void clear_register_values
PARAMS ((void));
733 static void print_dependency
PARAMS ((const char *action
, int depind
));
734 static void instruction_serialization
PARAMS ((void));
735 static void data_serialization
PARAMS ((void));
736 static void remove_marked_resource
PARAMS ((struct rsrc
*));
737 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
738 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
739 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
740 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
741 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
742 struct ia64_opcode
*, int, struct rsrc
[], int, int));
743 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
744 static void check_dependencies
PARAMS((struct ia64_opcode
*));
745 static void mark_resources
PARAMS((struct ia64_opcode
*));
746 static void update_dependencies
PARAMS((struct ia64_opcode
*));
747 static void note_register_values
PARAMS((struct ia64_opcode
*));
748 static int qp_mutex
PARAMS ((int, int, int));
749 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
750 static void output_vbyte_mem
PARAMS ((int, char *, char *));
751 static void count_output
PARAMS ((int, char *, char *));
752 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
753 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
754 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
755 static void output_P1_format
PARAMS ((vbyte_func
, int));
756 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
757 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
758 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
759 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
760 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
761 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
762 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
763 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
764 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
765 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
766 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
767 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
768 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
769 static char format_ab_reg
PARAMS ((int, int));
770 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
772 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
773 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
775 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
776 static void free_list_records
PARAMS ((unw_rec_list
*));
777 static unw_rec_list
*output_prologue
PARAMS ((void));
778 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
779 static unw_rec_list
*output_body
PARAMS ((void));
780 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
781 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
782 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
783 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
784 static unw_rec_list
*output_rp_when
PARAMS ((void));
785 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
786 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
787 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
788 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_pfs_when
PARAMS ((void));
790 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
791 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
792 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_preds_when
PARAMS ((void));
794 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
795 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
796 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
797 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
798 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
799 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
800 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
801 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
802 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
803 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
804 static unw_rec_list
*output_unat_when
PARAMS ((void));
805 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
806 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
808 static unw_rec_list
*output_lc_when
PARAMS ((void));
809 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
810 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
812 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
813 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
814 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
816 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
817 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
818 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
819 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
820 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
821 static unw_rec_list
*output_bsp_when
PARAMS ((void));
822 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
823 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
825 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
826 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
827 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
829 static unw_rec_list
*output_rnat_when
PARAMS ((void));
830 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
831 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
832 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
833 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
834 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
835 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
836 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
837 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
838 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
839 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
841 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
843 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
845 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
846 unsigned int, unsigned int));
847 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
848 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
849 static int calc_record_size
PARAMS ((unw_rec_list
*));
850 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
851 static int count_bits
PARAMS ((unsigned long));
852 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
853 unsigned long, fragS
*));
854 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
855 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
856 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
857 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
858 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
859 static int generate_unwind_image
PARAMS ((const char *));
861 /* Build the unwind section name by appending the (possibly stripped)
862 text section NAME to the unwind PREFIX. The resulting string
863 pointer is assigned to RESULT. The string is allocated on the
864 stack, so this must be a macro... */
865 #define make_unw_section_name(special, text_name, result) \
867 char *_prefix = special_section_name[special]; \
868 char *_suffix = text_name; \
869 size_t _prefix_len, _suffix_len; \
871 if (strncmp (text_name, ".gnu.linkonce.t.", \
872 sizeof (".gnu.linkonce.t.") - 1) == 0) \
874 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
875 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
877 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
878 _result = alloca (_prefix_len + _suffix_len + 1); \
879 memcpy (_result, _prefix, _prefix_len); \
880 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
881 _result[_prefix_len + _suffix_len] = '\0'; \
886 /* Determine if application register REGNUM resides in the integer
887 unit (as opposed to the memory unit). */
889 ar_is_in_integer_unit (reg
)
894 return (reg
== 64 /* pfs */
895 || reg
== 65 /* lc */
896 || reg
== 66 /* ec */
897 /* ??? ias accepts and puts these in the integer unit. */
898 || (reg
>= 112 && reg
<= 127));
901 /* Switch to section NAME and create section if necessary. It's
902 rather ugly that we have to manipulate input_line_pointer but I
903 don't see any other way to accomplish the same thing without
904 changing obj-elf.c (which may be the Right Thing, in the end). */
909 char *saved_input_line_pointer
;
911 saved_input_line_pointer
= input_line_pointer
;
912 input_line_pointer
= name
;
914 input_line_pointer
= saved_input_line_pointer
;
917 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
920 ia64_elf_section_flags (flags
, attr
, type
)
922 int attr
, type ATTRIBUTE_UNUSED
;
924 if (attr
& SHF_IA_64_SHORT
)
925 flags
|= SEC_SMALL_DATA
;
930 ia64_elf_section_type (str
, len
)
934 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
935 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
938 len
= sizeof (ELF_STRING_ia64_unwind_info_once
) - 1;
939 if (strncmp (str
, ELF_STRING_ia64_unwind_info_once
, len
) == 0)
942 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
943 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
944 return SHT_IA_64_UNWIND
;
946 len
= sizeof (ELF_STRING_ia64_unwind_once
) - 1;
947 if (strncmp (str
, ELF_STRING_ia64_unwind_once
, len
) == 0)
948 return SHT_IA_64_UNWIND
;
954 set_regstack (ins
, locs
, outs
, rots
)
955 unsigned int ins
, locs
, outs
, rots
;
960 sof
= ins
+ locs
+ outs
;
963 as_bad ("Size of frame exceeds maximum of 96 registers");
968 as_warn ("Size of rotating registers exceeds frame size");
971 md
.in
.base
= REG_GR
+ 32;
972 md
.loc
.base
= md
.in
.base
+ ins
;
973 md
.out
.base
= md
.loc
.base
+ locs
;
975 md
.in
.num_regs
= ins
;
976 md
.loc
.num_regs
= locs
;
977 md
.out
.num_regs
= outs
;
978 md
.rot
.num_regs
= rots
;
985 struct label_fix
*lfix
;
987 subsegT saved_subseg
;
990 if (!md
.last_text_seg
)
994 saved_subseg
= now_subseg
;
996 subseg_set (md
.last_text_seg
, 0);
998 while (md
.num_slots_in_use
> 0)
999 emit_one_bundle (); /* force out queued instructions */
1001 /* In case there are labels following the last instruction, resolve
1003 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1005 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1006 symbol_set_frag (lfix
->sym
, frag_now
);
1008 CURR_SLOT
.label_fixups
= 0;
1009 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1011 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1012 symbol_set_frag (lfix
->sym
, frag_now
);
1014 CURR_SLOT
.tag_fixups
= 0;
1016 /* In case there are unwind directives following the last instruction,
1017 resolve those now. We only handle body and prologue directives here.
1018 Give an error for others. */
1019 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1021 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1022 || ptr
->r
.type
== body
)
1024 ptr
->slot_number
= (unsigned long) frag_more (0);
1025 ptr
->slot_frag
= frag_now
;
1028 as_bad (_("Unwind directive not followed by an instruction."));
1030 unwind
.current_entry
= NULL
;
1032 subseg_set (saved_seg
, saved_subseg
);
1034 if (md
.qp
.X_op
== O_register
)
1035 as_bad ("qualifying predicate not followed by instruction");
1039 ia64_do_align (nbytes
)
1042 char *saved_input_line_pointer
= input_line_pointer
;
1044 input_line_pointer
= "";
1045 s_align_bytes (nbytes
);
1046 input_line_pointer
= saved_input_line_pointer
;
1050 ia64_cons_align (nbytes
)
1055 char *saved_input_line_pointer
= input_line_pointer
;
1056 input_line_pointer
= "";
1057 s_align_bytes (nbytes
);
1058 input_line_pointer
= saved_input_line_pointer
;
1062 /* Output COUNT bytes to a memory location. */
1063 static unsigned char *vbyte_mem_ptr
= NULL
;
1066 output_vbyte_mem (count
, ptr
, comment
)
1069 char *comment ATTRIBUTE_UNUSED
;
1072 if (vbyte_mem_ptr
== NULL
)
1077 for (x
= 0; x
< count
; x
++)
1078 *(vbyte_mem_ptr
++) = ptr
[x
];
1081 /* Count the number of bytes required for records. */
1082 static int vbyte_count
= 0;
1084 count_output (count
, ptr
, comment
)
1086 char *ptr ATTRIBUTE_UNUSED
;
1087 char *comment ATTRIBUTE_UNUSED
;
1089 vbyte_count
+= count
;
1093 output_R1_format (f
, rtype
, rlen
)
1095 unw_record_type rtype
;
1102 output_R3_format (f
, rtype
, rlen
);
1108 else if (rtype
!= prologue
)
1109 as_bad ("record type is not valid");
1111 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1112 (*f
) (1, &byte
, NULL
);
1116 output_R2_format (f
, mask
, grsave
, rlen
)
1123 mask
= (mask
& 0x0f);
1124 grsave
= (grsave
& 0x7f);
1126 bytes
[0] = (UNW_R2
| (mask
>> 1));
1127 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1128 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1129 (*f
) (count
, bytes
, NULL
);
1133 output_R3_format (f
, rtype
, rlen
)
1135 unw_record_type rtype
;
1142 output_R1_format (f
, rtype
, rlen
);
1148 else if (rtype
!= prologue
)
1149 as_bad ("record type is not valid");
1150 bytes
[0] = (UNW_R3
| r
);
1151 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1152 (*f
) (count
+ 1, bytes
, NULL
);
1156 output_P1_format (f
, brmask
)
1161 byte
= UNW_P1
| (brmask
& 0x1f);
1162 (*f
) (1, &byte
, NULL
);
1166 output_P2_format (f
, brmask
, gr
)
1172 brmask
= (brmask
& 0x1f);
1173 bytes
[0] = UNW_P2
| (brmask
>> 1);
1174 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1175 (*f
) (2, bytes
, NULL
);
1179 output_P3_format (f
, rtype
, reg
)
1181 unw_record_type rtype
;
1226 as_bad ("Invalid record type for P3 format.");
1228 bytes
[0] = (UNW_P3
| (r
>> 1));
1229 bytes
[1] = (((r
& 1) << 7) | reg
);
1230 (*f
) (2, bytes
, NULL
);
1234 output_P4_format (f
, imask
, imask_size
)
1236 unsigned char *imask
;
1237 unsigned long imask_size
;
1240 (*f
) (imask_size
, imask
, NULL
);
1244 output_P5_format (f
, grmask
, frmask
)
1247 unsigned long frmask
;
1250 grmask
= (grmask
& 0x0f);
1253 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1254 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1255 bytes
[3] = (frmask
& 0x000000ff);
1256 (*f
) (4, bytes
, NULL
);
1260 output_P6_format (f
, rtype
, rmask
)
1262 unw_record_type rtype
;
1268 if (rtype
== gr_mem
)
1270 else if (rtype
!= fr_mem
)
1271 as_bad ("Invalid record type for format P6");
1272 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1273 (*f
) (1, &byte
, NULL
);
1277 output_P7_format (f
, rtype
, w1
, w2
)
1279 unw_record_type rtype
;
1286 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1291 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1341 bytes
[0] = (UNW_P7
| r
);
1342 (*f
) (count
, bytes
, NULL
);
1346 output_P8_format (f
, rtype
, t
)
1348 unw_record_type rtype
;
1387 case bspstore_psprel
:
1390 case bspstore_sprel
:
1402 case priunat_when_gr
:
1405 case priunat_psprel
:
1411 case priunat_when_mem
:
1418 count
+= output_leb128 (bytes
+ 2, t
, 0);
1419 (*f
) (count
, bytes
, NULL
);
1423 output_P9_format (f
, grmask
, gr
)
1430 bytes
[1] = (grmask
& 0x0f);
1431 bytes
[2] = (gr
& 0x7f);
1432 (*f
) (3, bytes
, NULL
);
1436 output_P10_format (f
, abi
, context
)
1443 bytes
[1] = (abi
& 0xff);
1444 bytes
[2] = (context
& 0xff);
1445 (*f
) (3, bytes
, NULL
);
1449 output_B1_format (f
, rtype
, label
)
1451 unw_record_type rtype
;
1452 unsigned long label
;
1458 output_B4_format (f
, rtype
, label
);
1461 if (rtype
== copy_state
)
1463 else if (rtype
!= label_state
)
1464 as_bad ("Invalid record type for format B1");
1466 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1467 (*f
) (1, &byte
, NULL
);
1471 output_B2_format (f
, ecount
, t
)
1473 unsigned long ecount
;
1480 output_B3_format (f
, ecount
, t
);
1483 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1484 count
+= output_leb128 (bytes
+ 1, t
, 0);
1485 (*f
) (count
, bytes
, NULL
);
1489 output_B3_format (f
, ecount
, t
)
1491 unsigned long ecount
;
1498 output_B2_format (f
, ecount
, t
);
1502 count
+= output_leb128 (bytes
+ 1, t
, 0);
1503 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1504 (*f
) (count
, bytes
, NULL
);
1508 output_B4_format (f
, rtype
, label
)
1510 unw_record_type rtype
;
1511 unsigned long label
;
1518 output_B1_format (f
, rtype
, label
);
1522 if (rtype
== copy_state
)
1524 else if (rtype
!= label_state
)
1525 as_bad ("Invalid record type for format B1");
1527 bytes
[0] = (UNW_B4
| (r
<< 3));
1528 count
+= output_leb128 (bytes
+ 1, label
, 0);
1529 (*f
) (count
, bytes
, NULL
);
1533 format_ab_reg (ab
, reg
)
1540 ret
= (ab
<< 5) | reg
;
1545 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1547 unw_record_type rtype
;
1557 if (rtype
== spill_sprel
)
1559 else if (rtype
!= spill_psprel
)
1560 as_bad ("Invalid record type for format X1");
1561 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1562 count
+= output_leb128 (bytes
+ 2, t
, 0);
1563 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1564 (*f
) (count
, bytes
, NULL
);
1568 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1577 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1578 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1579 count
+= output_leb128 (bytes
+ 3, t
, 0);
1580 (*f
) (count
, bytes
, NULL
);
1584 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1586 unw_record_type rtype
;
1597 if (rtype
== spill_sprel_p
)
1599 else if (rtype
!= spill_psprel_p
)
1600 as_bad ("Invalid record type for format X3");
1601 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1602 bytes
[2] = format_ab_reg (ab
, reg
);
1603 count
+= output_leb128 (bytes
+ 3, t
, 0);
1604 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1605 (*f
) (count
, bytes
, NULL
);
1609 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1619 bytes
[1] = (qp
& 0x3f);
1620 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1621 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1622 count
+= output_leb128 (bytes
+ 4, t
, 0);
1623 (*f
) (count
, bytes
, NULL
);
1626 /* This function allocates a record list structure, and initializes fields. */
1628 static unw_rec_list
*
1629 alloc_record (unw_record_type t
)
1632 ptr
= xmalloc (sizeof (*ptr
));
1634 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1639 /* This function frees an entire list of record structures. */
1642 free_list_records (unw_rec_list
*first
)
1645 for (ptr
= first
; ptr
!= NULL
;)
1647 unw_rec_list
*tmp
= ptr
;
1649 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1650 && tmp
->r
.record
.r
.mask
.i
)
1651 free (tmp
->r
.record
.r
.mask
.i
);
1658 static unw_rec_list
*
1661 unw_rec_list
*ptr
= alloc_record (prologue
);
1662 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1666 static unw_rec_list
*
1667 output_prologue_gr (saved_mask
, reg
)
1668 unsigned int saved_mask
;
1671 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1672 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1673 ptr
->r
.record
.r
.grmask
= saved_mask
;
1674 ptr
->r
.record
.r
.grsave
= reg
;
1678 static unw_rec_list
*
1681 unw_rec_list
*ptr
= alloc_record (body
);
1685 static unw_rec_list
*
1686 output_mem_stack_f (size
)
1689 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1690 ptr
->r
.record
.p
.size
= size
;
1694 static unw_rec_list
*
1695 output_mem_stack_v ()
1697 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1701 static unw_rec_list
*
1705 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1706 ptr
->r
.record
.p
.gr
= gr
;
1710 static unw_rec_list
*
1711 output_psp_sprel (offset
)
1712 unsigned int offset
;
1714 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1715 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1719 static unw_rec_list
*
1722 unw_rec_list
*ptr
= alloc_record (rp_when
);
1726 static unw_rec_list
*
1730 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1731 ptr
->r
.record
.p
.gr
= gr
;
1735 static unw_rec_list
*
1739 unw_rec_list
*ptr
= alloc_record (rp_br
);
1740 ptr
->r
.record
.p
.br
= br
;
1744 static unw_rec_list
*
1745 output_rp_psprel (offset
)
1746 unsigned int offset
;
1748 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1749 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1753 static unw_rec_list
*
1754 output_rp_sprel (offset
)
1755 unsigned int offset
;
1757 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1758 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1762 static unw_rec_list
*
1765 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1769 static unw_rec_list
*
1773 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1774 ptr
->r
.record
.p
.gr
= gr
;
1778 static unw_rec_list
*
1779 output_pfs_psprel (offset
)
1780 unsigned int offset
;
1782 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1783 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1787 static unw_rec_list
*
1788 output_pfs_sprel (offset
)
1789 unsigned int offset
;
1791 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1792 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1796 static unw_rec_list
*
1797 output_preds_when ()
1799 unw_rec_list
*ptr
= alloc_record (preds_when
);
1803 static unw_rec_list
*
1804 output_preds_gr (gr
)
1807 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1808 ptr
->r
.record
.p
.gr
= gr
;
1812 static unw_rec_list
*
1813 output_preds_psprel (offset
)
1814 unsigned int offset
;
1816 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1817 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1821 static unw_rec_list
*
1822 output_preds_sprel (offset
)
1823 unsigned int offset
;
1825 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1826 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1830 static unw_rec_list
*
1831 output_fr_mem (mask
)
1834 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1835 ptr
->r
.record
.p
.rmask
= mask
;
1839 static unw_rec_list
*
1840 output_frgr_mem (gr_mask
, fr_mask
)
1841 unsigned int gr_mask
;
1842 unsigned int fr_mask
;
1844 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1845 ptr
->r
.record
.p
.grmask
= gr_mask
;
1846 ptr
->r
.record
.p
.frmask
= fr_mask
;
1850 static unw_rec_list
*
1851 output_gr_gr (mask
, reg
)
1855 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1856 ptr
->r
.record
.p
.grmask
= mask
;
1857 ptr
->r
.record
.p
.gr
= reg
;
1861 static unw_rec_list
*
1862 output_gr_mem (mask
)
1865 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1866 ptr
->r
.record
.p
.rmask
= mask
;
1870 static unw_rec_list
*
1871 output_br_mem (unsigned int mask
)
1873 unw_rec_list
*ptr
= alloc_record (br_mem
);
1874 ptr
->r
.record
.p
.brmask
= mask
;
1878 static unw_rec_list
*
1879 output_br_gr (save_mask
, reg
)
1880 unsigned int save_mask
;
1883 unw_rec_list
*ptr
= alloc_record (br_gr
);
1884 ptr
->r
.record
.p
.brmask
= save_mask
;
1885 ptr
->r
.record
.p
.gr
= reg
;
1889 static unw_rec_list
*
1890 output_spill_base (offset
)
1891 unsigned int offset
;
1893 unw_rec_list
*ptr
= alloc_record (spill_base
);
1894 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1898 static unw_rec_list
*
1901 unw_rec_list
*ptr
= alloc_record (unat_when
);
1905 static unw_rec_list
*
1909 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1910 ptr
->r
.record
.p
.gr
= gr
;
1914 static unw_rec_list
*
1915 output_unat_psprel (offset
)
1916 unsigned int offset
;
1918 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1919 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1923 static unw_rec_list
*
1924 output_unat_sprel (offset
)
1925 unsigned int offset
;
1927 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1928 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1932 static unw_rec_list
*
1935 unw_rec_list
*ptr
= alloc_record (lc_when
);
1939 static unw_rec_list
*
1943 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1944 ptr
->r
.record
.p
.gr
= gr
;
1948 static unw_rec_list
*
1949 output_lc_psprel (offset
)
1950 unsigned int offset
;
1952 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1953 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1957 static unw_rec_list
*
1958 output_lc_sprel (offset
)
1959 unsigned int offset
;
1961 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1962 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1966 static unw_rec_list
*
1969 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1973 static unw_rec_list
*
1977 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1978 ptr
->r
.record
.p
.gr
= gr
;
1982 static unw_rec_list
*
1983 output_fpsr_psprel (offset
)
1984 unsigned int offset
;
1986 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1987 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1991 static unw_rec_list
*
1992 output_fpsr_sprel (offset
)
1993 unsigned int offset
;
1995 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1996 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2000 static unw_rec_list
*
2001 output_priunat_when_gr ()
2003 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2007 static unw_rec_list
*
2008 output_priunat_when_mem ()
2010 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2014 static unw_rec_list
*
2015 output_priunat_gr (gr
)
2018 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2019 ptr
->r
.record
.p
.gr
= gr
;
2023 static unw_rec_list
*
2024 output_priunat_psprel (offset
)
2025 unsigned int offset
;
2027 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2028 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2032 static unw_rec_list
*
2033 output_priunat_sprel (offset
)
2034 unsigned int offset
;
2036 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2037 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2041 static unw_rec_list
*
2044 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2048 static unw_rec_list
*
2052 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2053 ptr
->r
.record
.p
.gr
= gr
;
2057 static unw_rec_list
*
2058 output_bsp_psprel (offset
)
2059 unsigned int offset
;
2061 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2062 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2066 static unw_rec_list
*
2067 output_bsp_sprel (offset
)
2068 unsigned int offset
;
2070 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2071 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2075 static unw_rec_list
*
2076 output_bspstore_when ()
2078 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2082 static unw_rec_list
*
2083 output_bspstore_gr (gr
)
2086 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2087 ptr
->r
.record
.p
.gr
= gr
;
2091 static unw_rec_list
*
2092 output_bspstore_psprel (offset
)
2093 unsigned int offset
;
2095 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2096 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2100 static unw_rec_list
*
2101 output_bspstore_sprel (offset
)
2102 unsigned int offset
;
2104 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2105 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2109 static unw_rec_list
*
2112 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2116 static unw_rec_list
*
2120 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2121 ptr
->r
.record
.p
.gr
= gr
;
2125 static unw_rec_list
*
2126 output_rnat_psprel (offset
)
2127 unsigned int offset
;
2129 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2130 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2134 static unw_rec_list
*
2135 output_rnat_sprel (offset
)
2136 unsigned int offset
;
2138 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2139 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2143 static unw_rec_list
*
2144 output_unwabi (abi
, context
)
2146 unsigned long context
;
2148 unw_rec_list
*ptr
= alloc_record (unwabi
);
2149 ptr
->r
.record
.p
.abi
= abi
;
2150 ptr
->r
.record
.p
.context
= context
;
2154 static unw_rec_list
*
2155 output_epilogue (unsigned long ecount
)
2157 unw_rec_list
*ptr
= alloc_record (epilogue
);
2158 ptr
->r
.record
.b
.ecount
= ecount
;
2162 static unw_rec_list
*
2163 output_label_state (unsigned long label
)
2165 unw_rec_list
*ptr
= alloc_record (label_state
);
2166 ptr
->r
.record
.b
.label
= label
;
2170 static unw_rec_list
*
2171 output_copy_state (unsigned long label
)
2173 unw_rec_list
*ptr
= alloc_record (copy_state
);
2174 ptr
->r
.record
.b
.label
= label
;
2178 static unw_rec_list
*
2179 output_spill_psprel (ab
, reg
, offset
)
2182 unsigned int offset
;
2184 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2185 ptr
->r
.record
.x
.ab
= ab
;
2186 ptr
->r
.record
.x
.reg
= reg
;
2187 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2191 static unw_rec_list
*
2192 output_spill_sprel (ab
, reg
, offset
)
2195 unsigned int offset
;
2197 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2198 ptr
->r
.record
.x
.ab
= ab
;
2199 ptr
->r
.record
.x
.reg
= reg
;
2200 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2204 static unw_rec_list
*
2205 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2208 unsigned int offset
;
2209 unsigned int predicate
;
2211 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2212 ptr
->r
.record
.x
.ab
= ab
;
2213 ptr
->r
.record
.x
.reg
= reg
;
2214 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2215 ptr
->r
.record
.x
.qp
= predicate
;
2219 static unw_rec_list
*
2220 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2223 unsigned int offset
;
2224 unsigned int predicate
;
2226 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2227 ptr
->r
.record
.x
.ab
= ab
;
2228 ptr
->r
.record
.x
.reg
= reg
;
2229 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2230 ptr
->r
.record
.x
.qp
= predicate
;
2234 static unw_rec_list
*
2235 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2238 unsigned int targ_reg
;
2241 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2242 ptr
->r
.record
.x
.ab
= ab
;
2243 ptr
->r
.record
.x
.reg
= reg
;
2244 ptr
->r
.record
.x
.treg
= targ_reg
;
2245 ptr
->r
.record
.x
.xy
= xy
;
2249 static unw_rec_list
*
2250 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2253 unsigned int targ_reg
;
2255 unsigned int predicate
;
2257 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2258 ptr
->r
.record
.x
.ab
= ab
;
2259 ptr
->r
.record
.x
.reg
= reg
;
2260 ptr
->r
.record
.x
.treg
= targ_reg
;
2261 ptr
->r
.record
.x
.xy
= xy
;
2262 ptr
->r
.record
.x
.qp
= predicate
;
2266 /* Given a unw_rec_list process the correct format with the
2267 specified function. */
2270 process_one_record (ptr
, f
)
2274 unsigned long fr_mask
, gr_mask
;
2276 switch (ptr
->r
.type
)
2282 /* These are taken care of by prologue/prologue_gr. */
2287 if (ptr
->r
.type
== prologue_gr
)
2288 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2289 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2291 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2293 /* Output descriptor(s) for union of register spills (if any). */
2294 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2295 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2298 if ((fr_mask
& ~0xfUL
) == 0)
2299 output_P6_format (f
, fr_mem
, fr_mask
);
2302 output_P5_format (f
, gr_mask
, fr_mask
);
2307 output_P6_format (f
, gr_mem
, gr_mask
);
2308 if (ptr
->r
.record
.r
.mask
.br_mem
)
2309 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2311 /* output imask descriptor if necessary: */
2312 if (ptr
->r
.record
.r
.mask
.i
)
2313 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2314 ptr
->r
.record
.r
.imask_size
);
2318 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2322 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2323 ptr
->r
.record
.p
.size
);
2336 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2339 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2342 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2350 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2359 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2369 case bspstore_sprel
:
2371 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2374 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2377 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2380 as_bad ("spill_mask record unimplemented.");
2382 case priunat_when_gr
:
2383 case priunat_when_mem
:
2387 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2389 case priunat_psprel
:
2391 case bspstore_psprel
:
2393 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2396 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2399 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2403 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2406 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2407 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2408 ptr
->r
.record
.x
.pspoff
);
2411 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2412 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2413 ptr
->r
.record
.x
.spoff
);
2416 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2417 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2418 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2420 case spill_psprel_p
:
2421 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2422 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2423 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2426 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2427 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2428 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2431 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2432 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2433 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2437 as_bad ("record_type_not_valid");
2442 /* Given a unw_rec_list list, process all the records with
2443 the specified function. */
2445 process_unw_records (list
, f
)
2450 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2451 process_one_record (ptr
, f
);
2454 /* Determine the size of a record list in bytes. */
2456 calc_record_size (list
)
2460 process_unw_records (list
, count_output
);
2464 /* Update IMASK bitmask to reflect the fact that one or more registers
2465 of type TYPE are saved starting at instruction with index T. If N
2466 bits are set in REGMASK, it is assumed that instructions T through
2467 T+N-1 save these registers.
2471 1: instruction saves next fp reg
2472 2: instruction saves next general reg
2473 3: instruction saves next branch reg */
2475 set_imask (region
, regmask
, t
, type
)
2476 unw_rec_list
*region
;
2477 unsigned long regmask
;
2481 unsigned char *imask
;
2482 unsigned long imask_size
;
2486 imask
= region
->r
.record
.r
.mask
.i
;
2487 imask_size
= region
->r
.record
.r
.imask_size
;
2490 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2491 imask
= xmalloc (imask_size
);
2492 memset (imask
, 0, imask_size
);
2494 region
->r
.record
.r
.imask_size
= imask_size
;
2495 region
->r
.record
.r
.mask
.i
= imask
;
2499 pos
= 2 * (3 - t
% 4);
2502 if (i
>= imask_size
)
2504 as_bad ("Ignoring attempt to spill beyond end of region");
2508 imask
[i
] |= (type
& 0x3) << pos
;
2510 regmask
&= (regmask
- 1);
2521 count_bits (unsigned long mask
)
2533 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2534 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2535 containing FIRST_ADDR. */
2538 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2539 unsigned long slot_addr
;
2541 unsigned long first_addr
;
2544 unsigned long index
= 0;
2546 /* First time we are called, the initial address and frag are invalid. */
2547 if (first_addr
== 0)
2550 /* If the two addresses are in different frags, then we need to add in
2551 the remaining size of this frag, and then the entire size of intermediate
2553 while (slot_frag
!= first_frag
)
2555 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2557 /* Add in the full size of the frag converted to instruction slots. */
2558 index
+= 3 * (first_frag
->fr_fix
>> 4);
2559 /* Subtract away the initial part before first_addr. */
2560 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2561 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2563 /* Move to the beginning of the next frag. */
2564 first_frag
= first_frag
->fr_next
;
2565 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2568 /* Add in the used part of the last frag. */
2569 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2570 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2574 /* Optimize unwind record directives. */
2576 static unw_rec_list
*
2577 optimize_unw_records (list
)
2583 /* If the only unwind record is ".prologue" or ".prologue" followed
2584 by ".body", then we can optimize the unwind directives away. */
2585 if (list
->r
.type
== prologue
2586 && (list
->next
== NULL
2587 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2593 /* Given a complete record list, process any records which have
2594 unresolved fields, (ie length counts for a prologue). After
2595 this has been run, all neccessary information should be available
2596 within each record to generate an image. */
2599 fixup_unw_records (list
)
2602 unw_rec_list
*ptr
, *region
= 0;
2603 unsigned long first_addr
= 0, rlen
= 0, t
;
2604 fragS
*first_frag
= 0;
2606 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2608 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2609 as_bad (" Insn slot not set in unwind record.");
2610 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2611 first_addr
, first_frag
);
2612 switch (ptr
->r
.type
)
2619 int size
, dir_len
= 0;
2620 unsigned long last_addr
;
2623 first_addr
= ptr
->slot_number
;
2624 first_frag
= ptr
->slot_frag
;
2625 ptr
->slot_number
= 0;
2626 /* Find either the next body/prologue start, or the end of
2627 the list, and determine the size of the region. */
2628 last_addr
= unwind
.next_slot_number
;
2629 last_frag
= unwind
.next_slot_frag
;
2630 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2631 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2632 || last
->r
.type
== body
)
2634 last_addr
= last
->slot_number
;
2635 last_frag
= last
->slot_frag
;
2638 else if (!last
->next
)
2640 /* In the absence of an explicit .body directive,
2641 the prologue ends after the last instruction
2642 covered by an unwind directive. */
2643 if (ptr
->r
.type
!= body
)
2645 last_addr
= last
->slot_number
;
2646 last_frag
= last
->slot_frag
;
2647 switch (last
->r
.type
)
2650 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2651 + count_bits (last
->r
.record
.p
.grmask
));
2655 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2659 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2662 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2671 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2673 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2678 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2689 case priunat_when_gr
:
2690 case priunat_when_mem
:
2694 ptr
->r
.record
.p
.t
= t
;
2702 case spill_psprel_p
:
2703 ptr
->r
.record
.x
.t
= t
;
2709 as_bad ("frgr_mem record before region record!\n");
2712 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2713 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2714 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2715 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2720 as_bad ("fr_mem record before region record!\n");
2723 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2724 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2729 as_bad ("gr_mem record before region record!\n");
2732 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2733 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2738 as_bad ("br_mem record before region record!\n");
2741 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2742 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2748 as_bad ("gr_gr record before region record!\n");
2751 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2756 as_bad ("br_gr record before region record!\n");
2759 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2768 /* Helper routine for output_unw_records. Emits the header for the unwind
2772 setup_unwind_header (int size
, unsigned char **mem
)
2776 /* pad to pointer-size boundry. */
2777 x
= size
% md
.pointer_size
;
2779 extra
= md
.pointer_size
- x
;
2781 /* Add 8 for the header + a pointer for the
2782 personality offset. */
2783 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2785 /* Clear the padding area and personality. */
2786 memset (*mem
+ 8 + size
, 0 , extra
+ md
.pointer_size
);
2787 /* Initialize the header area. */
2789 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* version */
2790 | (unwind
.personality_routine
2791 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2793 | ((size
+ extra
) / md
.pointer_size
)), /* length */
2799 /* Generate an unwind image from a record list. Returns the number of
2800 bytes in the resulting image. The memory image itselof is returned
2801 in the 'ptr' parameter. */
2803 output_unw_records (list
, ptr
)
2812 list
= optimize_unw_records (list
);
2813 fixup_unw_records (list
);
2814 size
= calc_record_size (list
);
2816 if (size
> 0 || unwind
.force_unwind_entry
)
2818 unwind
.force_unwind_entry
= 0;
2819 extra
= setup_unwind_header (size
, &mem
);
2821 vbyte_mem_ptr
= mem
+ 8;
2822 process_unw_records (list
, output_vbyte_mem
);
2826 size
+= extra
+ 8 + md
.pointer_size
;
2832 convert_expr_to_ab_reg (e
, ab
, regp
)
2839 if (e
->X_op
!= O_register
)
2842 reg
= e
->X_add_number
;
2843 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2846 *regp
= reg
- REG_GR
;
2848 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2849 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2852 *regp
= reg
- REG_FR
;
2854 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2857 *regp
= reg
- REG_BR
;
2864 case REG_PR
: *regp
= 0; break;
2865 case REG_PSP
: *regp
= 1; break;
2866 case REG_PRIUNAT
: *regp
= 2; break;
2867 case REG_BR
+ 0: *regp
= 3; break;
2868 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2869 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2870 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2871 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2872 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2873 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2874 case REG_AR
+ AR_LC
: *regp
= 10; break;
2884 convert_expr_to_xy_reg (e
, xy
, regp
)
2891 if (e
->X_op
!= O_register
)
2894 reg
= e
->X_add_number
;
2896 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2899 *regp
= reg
- REG_GR
;
2901 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2904 *regp
= reg
- REG_FR
;
2906 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2909 *regp
= reg
- REG_BR
;
2918 int dummy ATTRIBUTE_UNUSED
;
2923 radix
= *input_line_pointer
++;
2925 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2927 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2928 ignore_rest_of_line ();
2933 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2935 dot_special_section (which
)
2938 set_section ((char *) special_section_name
[which
]);
2942 add_unwind_entry (ptr
)
2946 unwind
.tail
->next
= ptr
;
2951 /* The current entry can in fact be a chain of unwind entries. */
2952 if (unwind
.current_entry
== NULL
)
2953 unwind
.current_entry
= ptr
;
2958 int dummy ATTRIBUTE_UNUSED
;
2964 if (e
.X_op
!= O_constant
)
2965 as_bad ("Operand to .fframe must be a constant");
2967 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2972 int dummy ATTRIBUTE_UNUSED
;
2978 reg
= e
.X_add_number
- REG_GR
;
2979 if (e
.X_op
== O_register
&& reg
< 128)
2981 add_unwind_entry (output_mem_stack_v ());
2982 if (! (unwind
.prologue_mask
& 2))
2983 add_unwind_entry (output_psp_gr (reg
));
2986 as_bad ("First operand to .vframe must be a general register");
2990 dot_vframesp (dummy
)
2991 int dummy ATTRIBUTE_UNUSED
;
2996 if (e
.X_op
== O_constant
)
2998 add_unwind_entry (output_mem_stack_v ());
2999 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3002 as_bad ("First operand to .vframesp must be a general register");
3006 dot_vframepsp (dummy
)
3007 int dummy ATTRIBUTE_UNUSED
;
3012 if (e
.X_op
== O_constant
)
3014 add_unwind_entry (output_mem_stack_v ());
3015 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3018 as_bad ("First operand to .vframepsp must be a general register");
3023 int dummy ATTRIBUTE_UNUSED
;
3029 sep
= parse_operand (&e1
);
3031 as_bad ("No second operand to .save");
3032 sep
= parse_operand (&e2
);
3034 reg1
= e1
.X_add_number
;
3035 reg2
= e2
.X_add_number
- REG_GR
;
3037 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3038 if (e1
.X_op
== O_register
)
3040 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3044 case REG_AR
+ AR_BSP
:
3045 add_unwind_entry (output_bsp_when ());
3046 add_unwind_entry (output_bsp_gr (reg2
));
3048 case REG_AR
+ AR_BSPSTORE
:
3049 add_unwind_entry (output_bspstore_when ());
3050 add_unwind_entry (output_bspstore_gr (reg2
));
3052 case REG_AR
+ AR_RNAT
:
3053 add_unwind_entry (output_rnat_when ());
3054 add_unwind_entry (output_rnat_gr (reg2
));
3056 case REG_AR
+ AR_UNAT
:
3057 add_unwind_entry (output_unat_when ());
3058 add_unwind_entry (output_unat_gr (reg2
));
3060 case REG_AR
+ AR_FPSR
:
3061 add_unwind_entry (output_fpsr_when ());
3062 add_unwind_entry (output_fpsr_gr (reg2
));
3064 case REG_AR
+ AR_PFS
:
3065 add_unwind_entry (output_pfs_when ());
3066 if (! (unwind
.prologue_mask
& 4))
3067 add_unwind_entry (output_pfs_gr (reg2
));
3069 case REG_AR
+ AR_LC
:
3070 add_unwind_entry (output_lc_when ());
3071 add_unwind_entry (output_lc_gr (reg2
));
3074 add_unwind_entry (output_rp_when ());
3075 if (! (unwind
.prologue_mask
& 8))
3076 add_unwind_entry (output_rp_gr (reg2
));
3079 add_unwind_entry (output_preds_when ());
3080 if (! (unwind
.prologue_mask
& 1))
3081 add_unwind_entry (output_preds_gr (reg2
));
3084 add_unwind_entry (output_priunat_when_gr ());
3085 add_unwind_entry (output_priunat_gr (reg2
));
3088 as_bad ("First operand not a valid register");
3092 as_bad (" Second operand not a valid register");
3095 as_bad ("First operand not a register");
3100 int dummy ATTRIBUTE_UNUSED
;
3103 unsigned long ecount
; /* # of _additional_ regions to pop */
3106 sep
= parse_operand (&e1
);
3107 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3109 as_bad ("First operand to .restore must be stack pointer (sp)");
3115 parse_operand (&e2
);
3116 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3118 as_bad ("Second operand to .restore must be a constant >= 0");
3121 ecount
= e2
.X_add_number
;
3124 ecount
= unwind
.prologue_count
- 1;
3125 add_unwind_entry (output_epilogue (ecount
));
3127 if (ecount
< unwind
.prologue_count
)
3128 unwind
.prologue_count
-= ecount
+ 1;
3130 unwind
.prologue_count
= 0;
3134 dot_restorereg (dummy
)
3135 int dummy ATTRIBUTE_UNUSED
;
3137 unsigned int ab
, reg
;
3142 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3144 as_bad ("First operand to .restorereg must be a preserved register");
3147 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3151 dot_restorereg_p (dummy
)
3152 int dummy ATTRIBUTE_UNUSED
;
3154 unsigned int qp
, ab
, reg
;
3158 sep
= parse_operand (&e1
);
3161 as_bad ("No second operand to .restorereg.p");
3165 parse_operand (&e2
);
3167 qp
= e1
.X_add_number
- REG_P
;
3168 if (e1
.X_op
!= O_register
|| qp
> 63)
3170 as_bad ("First operand to .restorereg.p must be a predicate");
3174 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3176 as_bad ("Second operand to .restorereg.p must be a preserved register");
3179 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3183 generate_unwind_image (text_name
)
3184 const char *text_name
;
3187 unsigned char *unw_rec
;
3189 /* Force out pending instructions, to make sure all unwind records have
3190 a valid slot_number field. */
3191 ia64_flush_insns ();
3193 /* Generate the unwind record. */
3194 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3195 if (size
% md
.pointer_size
!= 0)
3196 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3198 /* If there are unwind records, switch sections, and output the info. */
3201 unsigned char *where
;
3205 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3206 set_section (sec_name
);
3207 bfd_set_section_flags (stdoutput
, now_seg
,
3208 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3210 /* Make sure the section has 4 byte alignment for ILP32 and
3211 8 byte alignment for LP64. */
3212 frag_align (md
.pointer_size_shift
, 0, 0);
3213 record_alignment (now_seg
, md
.pointer_size_shift
);
3215 /* Set expression which points to start of unwind descriptor area. */
3216 unwind
.info
= expr_build_dot ();
3218 where
= (unsigned char *) frag_more (size
);
3220 /* Issue a label for this address, and keep track of it to put it
3221 in the unwind section. */
3223 /* Copy the information from the unwind record into this section. The
3224 data is already in the correct byte order. */
3225 memcpy (where
, unw_rec
, size
);
3227 /* Add the personality address to the image. */
3228 if (unwind
.personality_routine
!= 0)
3230 exp
.X_op
= O_symbol
;
3231 exp
.X_add_symbol
= unwind
.personality_routine
;
3232 exp
.X_add_number
= 0;
3233 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3234 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3235 unwind
.personality_routine
= 0;
3239 free_list_records (unwind
.list
);
3240 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3246 dot_handlerdata (dummy
)
3247 int dummy ATTRIBUTE_UNUSED
;
3249 const char *text_name
= segment_name (now_seg
);
3251 /* If text section name starts with ".text" (which it should),
3252 strip this prefix off. */
3253 if (strcmp (text_name
, ".text") == 0)
3256 unwind
.force_unwind_entry
= 1;
3258 /* Remember which segment we're in so we can switch back after .endp */
3259 unwind
.saved_text_seg
= now_seg
;
3260 unwind
.saved_text_subseg
= now_subseg
;
3262 /* Generate unwind info into unwind-info section and then leave that
3263 section as the currently active one so dataXX directives go into
3264 the language specific data area of the unwind info block. */
3265 generate_unwind_image (text_name
);
3266 demand_empty_rest_of_line ();
3270 dot_unwentry (dummy
)
3271 int dummy ATTRIBUTE_UNUSED
;
3273 unwind
.force_unwind_entry
= 1;
3274 demand_empty_rest_of_line ();
3279 int dummy ATTRIBUTE_UNUSED
;
3285 reg
= e
.X_add_number
- REG_BR
;
3286 if (e
.X_op
== O_register
&& reg
< 8)
3287 add_unwind_entry (output_rp_br (reg
));
3289 as_bad ("First operand not a valid branch register");
3293 dot_savemem (psprel
)
3300 sep
= parse_operand (&e1
);
3302 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3303 sep
= parse_operand (&e2
);
3305 reg1
= e1
.X_add_number
;
3306 val
= e2
.X_add_number
;
3308 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3309 if (e1
.X_op
== O_register
)
3311 if (e2
.X_op
== O_constant
)
3315 case REG_AR
+ AR_BSP
:
3316 add_unwind_entry (output_bsp_when ());
3317 add_unwind_entry ((psprel
3319 : output_bsp_sprel
) (val
));
3321 case REG_AR
+ AR_BSPSTORE
:
3322 add_unwind_entry (output_bspstore_when ());
3323 add_unwind_entry ((psprel
3324 ? output_bspstore_psprel
3325 : output_bspstore_sprel
) (val
));
3327 case REG_AR
+ AR_RNAT
:
3328 add_unwind_entry (output_rnat_when ());
3329 add_unwind_entry ((psprel
3330 ? output_rnat_psprel
3331 : output_rnat_sprel
) (val
));
3333 case REG_AR
+ AR_UNAT
:
3334 add_unwind_entry (output_unat_when ());
3335 add_unwind_entry ((psprel
3336 ? output_unat_psprel
3337 : output_unat_sprel
) (val
));
3339 case REG_AR
+ AR_FPSR
:
3340 add_unwind_entry (output_fpsr_when ());
3341 add_unwind_entry ((psprel
3342 ? output_fpsr_psprel
3343 : output_fpsr_sprel
) (val
));
3345 case REG_AR
+ AR_PFS
:
3346 add_unwind_entry (output_pfs_when ());
3347 add_unwind_entry ((psprel
3349 : output_pfs_sprel
) (val
));
3351 case REG_AR
+ AR_LC
:
3352 add_unwind_entry (output_lc_when ());
3353 add_unwind_entry ((psprel
3355 : output_lc_sprel
) (val
));
3358 add_unwind_entry (output_rp_when ());
3359 add_unwind_entry ((psprel
3361 : output_rp_sprel
) (val
));
3364 add_unwind_entry (output_preds_when ());
3365 add_unwind_entry ((psprel
3366 ? output_preds_psprel
3367 : output_preds_sprel
) (val
));
3370 add_unwind_entry (output_priunat_when_mem ());
3371 add_unwind_entry ((psprel
3372 ? output_priunat_psprel
3373 : output_priunat_sprel
) (val
));
3376 as_bad ("First operand not a valid register");
3380 as_bad (" Second operand not a valid constant");
3383 as_bad ("First operand not a register");
3388 int dummy ATTRIBUTE_UNUSED
;
3392 sep
= parse_operand (&e1
);
3394 parse_operand (&e2
);
3396 if (e1
.X_op
!= O_constant
)
3397 as_bad ("First operand to .save.g must be a constant.");
3400 int grmask
= e1
.X_add_number
;
3402 add_unwind_entry (output_gr_mem (grmask
));
3405 int reg
= e2
.X_add_number
- REG_GR
;
3406 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3407 add_unwind_entry (output_gr_gr (grmask
, reg
));
3409 as_bad ("Second operand is an invalid register.");
3416 int dummy ATTRIBUTE_UNUSED
;
3420 sep
= parse_operand (&e1
);
3422 if (e1
.X_op
!= O_constant
)
3423 as_bad ("Operand to .save.f must be a constant.");
3425 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3430 int dummy ATTRIBUTE_UNUSED
;
3437 sep
= parse_operand (&e1
);
3438 if (e1
.X_op
!= O_constant
)
3440 as_bad ("First operand to .save.b must be a constant.");
3443 brmask
= e1
.X_add_number
;
3447 sep
= parse_operand (&e2
);
3448 reg
= e2
.X_add_number
- REG_GR
;
3449 if (e2
.X_op
!= O_register
|| reg
> 127)
3451 as_bad ("Second operand to .save.b must be a general register.");
3454 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3457 add_unwind_entry (output_br_mem (brmask
));
3459 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3460 ignore_rest_of_line ();
3465 int dummy ATTRIBUTE_UNUSED
;
3469 sep
= parse_operand (&e1
);
3471 parse_operand (&e2
);
3473 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3474 as_bad ("Both operands of .save.gf must be constants.");
3477 int grmask
= e1
.X_add_number
;
3478 int frmask
= e2
.X_add_number
;
3479 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3485 int dummy ATTRIBUTE_UNUSED
;
3490 sep
= parse_operand (&e
);
3491 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3492 ignore_rest_of_line ();
3494 if (e
.X_op
!= O_constant
)
3495 as_bad ("Operand to .spill must be a constant");
3497 add_unwind_entry (output_spill_base (e
.X_add_number
));
3501 dot_spillreg (dummy
)
3502 int dummy ATTRIBUTE_UNUSED
;
3504 int sep
, ab
, xy
, reg
, treg
;
3507 sep
= parse_operand (&e1
);
3510 as_bad ("No second operand to .spillreg");
3514 parse_operand (&e2
);
3516 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3518 as_bad ("First operand to .spillreg must be a preserved register");
3522 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3524 as_bad ("Second operand to .spillreg must be a register");
3528 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3532 dot_spillmem (psprel
)
3538 sep
= parse_operand (&e1
);
3541 as_bad ("Second operand missing");
3545 parse_operand (&e2
);
3547 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3549 as_bad ("First operand to .spill%s must be a preserved register",
3550 psprel
? "psp" : "sp");
3554 if (e2
.X_op
!= O_constant
)
3556 as_bad ("Second operand to .spill%s must be a constant",
3557 psprel
? "psp" : "sp");
3562 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3564 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3568 dot_spillreg_p (dummy
)
3569 int dummy ATTRIBUTE_UNUSED
;
3571 int sep
, ab
, xy
, reg
, treg
;
3572 expressionS e1
, e2
, e3
;
3575 sep
= parse_operand (&e1
);
3578 as_bad ("No second and third operand to .spillreg.p");
3582 sep
= parse_operand (&e2
);
3585 as_bad ("No third operand to .spillreg.p");
3589 parse_operand (&e3
);
3591 qp
= e1
.X_add_number
- REG_P
;
3593 if (e1
.X_op
!= O_register
|| qp
> 63)
3595 as_bad ("First operand to .spillreg.p must be a predicate");
3599 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3601 as_bad ("Second operand to .spillreg.p must be a preserved register");
3605 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3607 as_bad ("Third operand to .spillreg.p must be a register");
3611 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3615 dot_spillmem_p (psprel
)
3618 expressionS e1
, e2
, e3
;
3622 sep
= parse_operand (&e1
);
3625 as_bad ("Second operand missing");
3629 parse_operand (&e2
);
3632 as_bad ("Second operand missing");
3636 parse_operand (&e3
);
3638 qp
= e1
.X_add_number
- REG_P
;
3639 if (e1
.X_op
!= O_register
|| qp
> 63)
3641 as_bad ("First operand to .spill%s_p must be a predicate",
3642 psprel
? "psp" : "sp");
3646 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3648 as_bad ("Second operand to .spill%s_p must be a preserved register",
3649 psprel
? "psp" : "sp");
3653 if (e3
.X_op
!= O_constant
)
3655 as_bad ("Third operand to .spill%s_p must be a constant",
3656 psprel
? "psp" : "sp");
3661 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3663 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3667 dot_label_state (dummy
)
3668 int dummy ATTRIBUTE_UNUSED
;
3673 if (e
.X_op
!= O_constant
)
3675 as_bad ("Operand to .label_state must be a constant");
3678 add_unwind_entry (output_label_state (e
.X_add_number
));
3682 dot_copy_state (dummy
)
3683 int dummy ATTRIBUTE_UNUSED
;
3688 if (e
.X_op
!= O_constant
)
3690 as_bad ("Operand to .copy_state must be a constant");
3693 add_unwind_entry (output_copy_state (e
.X_add_number
));
3698 int dummy ATTRIBUTE_UNUSED
;
3703 sep
= parse_operand (&e1
);
3706 as_bad ("Second operand to .unwabi missing");
3709 sep
= parse_operand (&e2
);
3710 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3711 ignore_rest_of_line ();
3713 if (e1
.X_op
!= O_constant
)
3715 as_bad ("First operand to .unwabi must be a constant");
3719 if (e2
.X_op
!= O_constant
)
3721 as_bad ("Second operand to .unwabi must be a constant");
3725 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3729 dot_personality (dummy
)
3730 int dummy ATTRIBUTE_UNUSED
;
3734 name
= input_line_pointer
;
3735 c
= get_symbol_end ();
3736 p
= input_line_pointer
;
3737 unwind
.personality_routine
= symbol_find_or_make (name
);
3738 unwind
.force_unwind_entry
= 1;
3741 demand_empty_rest_of_line ();
3746 int dummy ATTRIBUTE_UNUSED
;
3751 unwind
.proc_start
= expr_build_dot ();
3752 /* Parse names of main and alternate entry points and mark them as
3753 function symbols: */
3757 name
= input_line_pointer
;
3758 c
= get_symbol_end ();
3759 p
= input_line_pointer
;
3760 sym
= symbol_find_or_make (name
);
3761 if (unwind
.proc_start
== 0)
3763 unwind
.proc_start
= sym
;
3765 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3768 if (*input_line_pointer
!= ',')
3770 ++input_line_pointer
;
3772 demand_empty_rest_of_line ();
3775 unwind
.prologue_count
= 0;
3776 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3777 unwind
.personality_routine
= 0;
3782 int dummy ATTRIBUTE_UNUSED
;
3784 unwind
.prologue
= 0;
3785 unwind
.prologue_mask
= 0;
3787 add_unwind_entry (output_body ());
3788 demand_empty_rest_of_line ();
3792 dot_prologue (dummy
)
3793 int dummy ATTRIBUTE_UNUSED
;
3796 int mask
= 0, grsave
= 0;
3798 if (!is_it_end_of_statement ())
3801 sep
= parse_operand (&e1
);
3803 as_bad ("No second operand to .prologue");
3804 sep
= parse_operand (&e2
);
3805 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3806 ignore_rest_of_line ();
3808 if (e1
.X_op
== O_constant
)
3810 mask
= e1
.X_add_number
;
3812 if (e2
.X_op
== O_constant
)
3813 grsave
= e2
.X_add_number
;
3814 else if (e2
.X_op
== O_register
3815 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3818 as_bad ("Second operand not a constant or general register");
3820 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3823 as_bad ("First operand not a constant");
3826 add_unwind_entry (output_prologue ());
3828 unwind
.prologue
= 1;
3829 unwind
.prologue_mask
= mask
;
3830 ++unwind
.prologue_count
;
3835 int dummy ATTRIBUTE_UNUSED
;
3839 int bytes_per_address
;
3842 subsegT saved_subseg
;
3843 const char *sec_name
, *text_name
;
3845 if (unwind
.saved_text_seg
)
3847 saved_seg
= unwind
.saved_text_seg
;
3848 saved_subseg
= unwind
.saved_text_subseg
;
3849 unwind
.saved_text_seg
= NULL
;
3853 saved_seg
= now_seg
;
3854 saved_subseg
= now_subseg
;
3858 Use a slightly ugly scheme to derive the unwind section names from
3859 the text section name:
3861 text sect. unwind table sect.
3862 name: name: comments:
3863 ---------- ----------------- --------------------------------
3865 .text.foo .IA_64.unwind.text.foo
3866 .foo .IA_64.unwind.foo
3868 .gnu.linkonce.ia64unw.foo
3869 _info .IA_64.unwind_info gas issues error message (ditto)
3870 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3872 This mapping is done so that:
3874 (a) An object file with unwind info only in .text will use
3875 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3876 This follows the letter of the ABI and also ensures backwards
3877 compatibility with older toolchains.
3879 (b) An object file with unwind info in multiple text sections
3880 will use separate unwind sections for each text section.
3881 This allows us to properly set the "sh_info" and "sh_link"
3882 fields in SHT_IA_64_UNWIND as required by the ABI and also
3883 lets GNU ld support programs with multiple segments
3884 containing unwind info (as might be the case for certain
3885 embedded applications).
3887 (c) An error is issued if there would be a name clash.
3889 text_name
= segment_name (saved_seg
);
3890 if (strncmp (text_name
, "_info", 5) == 0)
3892 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3894 ignore_rest_of_line ();
3897 if (strcmp (text_name
, ".text") == 0)
3901 demand_empty_rest_of_line ();
3903 insn_group_break (1, 0, 0);
3905 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3907 generate_unwind_image (text_name
);
3909 if (unwind
.info
|| unwind
.force_unwind_entry
)
3911 subseg_set (md
.last_text_seg
, 0);
3912 unwind
.proc_end
= expr_build_dot ();
3914 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3915 set_section ((char *) sec_name
);
3916 bfd_set_section_flags (stdoutput
, now_seg
,
3917 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3919 /* Make sure that section has 4 byte alignment for ILP32 and
3920 8 byte alignment for LP64. */
3921 record_alignment (now_seg
, md
.pointer_size_shift
);
3923 /* Need space for 3 pointers for procedure start, procedure end,
3925 ptr
= frag_more (3 * md
.pointer_size
);
3926 where
= frag_now_fix () - (3 * md
.pointer_size
);
3927 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3929 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3930 e
.X_op
= O_pseudo_fixup
;
3931 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3933 e
.X_add_symbol
= unwind
.proc_start
;
3934 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3936 e
.X_op
= O_pseudo_fixup
;
3937 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3939 e
.X_add_symbol
= unwind
.proc_end
;
3940 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3941 bytes_per_address
, &e
);
3945 e
.X_op
= O_pseudo_fixup
;
3946 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3948 e
.X_add_symbol
= unwind
.info
;
3949 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3950 bytes_per_address
, &e
);
3953 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3957 subseg_set (saved_seg
, saved_subseg
);
3958 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3962 dot_template (template)
3965 CURR_SLOT
.user_template
= template;
3970 int dummy ATTRIBUTE_UNUSED
;
3972 int ins
, locs
, outs
, rots
;
3974 if (is_it_end_of_statement ())
3975 ins
= locs
= outs
= rots
= 0;
3978 ins
= get_absolute_expression ();
3979 if (*input_line_pointer
++ != ',')
3981 locs
= get_absolute_expression ();
3982 if (*input_line_pointer
++ != ',')
3984 outs
= get_absolute_expression ();
3985 if (*input_line_pointer
++ != ',')
3987 rots
= get_absolute_expression ();
3989 set_regstack (ins
, locs
, outs
, rots
);
3993 as_bad ("Comma expected");
3994 ignore_rest_of_line ();
4001 unsigned num_regs
, num_alloced
= 0;
4002 struct dynreg
**drpp
, *dr
;
4003 int ch
, base_reg
= 0;
4009 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4010 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4011 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4015 /* First, remove existing names from hash table. */
4016 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4018 hash_delete (md
.dynreg_hash
, dr
->name
);
4022 drpp
= &md
.dynreg
[type
];
4025 start
= input_line_pointer
;
4026 ch
= get_symbol_end ();
4027 *input_line_pointer
= ch
;
4028 len
= (input_line_pointer
- start
);
4031 if (*input_line_pointer
!= '[')
4033 as_bad ("Expected '['");
4036 ++input_line_pointer
; /* skip '[' */
4038 num_regs
= get_absolute_expression ();
4040 if (*input_line_pointer
++ != ']')
4042 as_bad ("Expected ']'");
4047 num_alloced
+= num_regs
;
4051 if (num_alloced
> md
.rot
.num_regs
)
4053 as_bad ("Used more than the declared %d rotating registers",
4059 if (num_alloced
> 96)
4061 as_bad ("Used more than the available 96 rotating registers");
4066 if (num_alloced
> 48)
4068 as_bad ("Used more than the available 48 rotating registers");
4077 name
= obstack_alloc (¬es
, len
+ 1);
4078 memcpy (name
, start
, len
);
4083 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4084 memset (*drpp
, 0, sizeof (*dr
));
4089 dr
->num_regs
= num_regs
;
4090 dr
->base
= base_reg
;
4092 base_reg
+= num_regs
;
4094 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4096 as_bad ("Attempt to redefine register set `%s'", name
);
4100 if (*input_line_pointer
!= ',')
4102 ++input_line_pointer
; /* skip comma */
4105 demand_empty_rest_of_line ();
4109 ignore_rest_of_line ();
4113 dot_byteorder (byteorder
)
4116 target_big_endian
= byteorder
;
4121 int dummy ATTRIBUTE_UNUSED
;
4128 option
= input_line_pointer
;
4129 ch
= get_symbol_end ();
4130 if (strcmp (option
, "lsb") == 0)
4131 md
.flags
&= ~EF_IA_64_BE
;
4132 else if (strcmp (option
, "msb") == 0)
4133 md
.flags
|= EF_IA_64_BE
;
4134 else if (strcmp (option
, "abi32") == 0)
4135 md
.flags
&= ~EF_IA_64_ABI64
;
4136 else if (strcmp (option
, "abi64") == 0)
4137 md
.flags
|= EF_IA_64_ABI64
;
4139 as_bad ("Unknown psr option `%s'", option
);
4140 *input_line_pointer
= ch
;
4143 if (*input_line_pointer
!= ',')
4146 ++input_line_pointer
;
4149 demand_empty_rest_of_line ();
4154 int dummy ATTRIBUTE_UNUSED
;
4156 as_bad (".alias not implemented yet");
4161 int dummy ATTRIBUTE_UNUSED
;
4163 new_logical_line (0, get_absolute_expression ());
4164 demand_empty_rest_of_line ();
4168 parse_section_name ()
4174 if (*input_line_pointer
!= '"')
4176 as_bad ("Missing section name");
4177 ignore_rest_of_line ();
4180 name
= demand_copy_C_string (&len
);
4183 ignore_rest_of_line ();
4187 if (*input_line_pointer
!= ',')
4189 as_bad ("Comma expected after section name");
4190 ignore_rest_of_line ();
4193 ++input_line_pointer
; /* skip comma */
4201 char *name
= parse_section_name ();
4205 md
.keep_pending_output
= 1;
4208 obj_elf_previous (0);
4209 md
.keep_pending_output
= 0;
4212 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4215 stmt_float_cons (kind
)
4222 case 'd': size
= 8; break;
4223 case 'x': size
= 10; break;
4230 ia64_do_align (size
);
4238 int saved_auto_align
= md
.auto_align
;
4242 md
.auto_align
= saved_auto_align
;
4246 dot_xfloat_cons (kind
)
4249 char *name
= parse_section_name ();
4253 md
.keep_pending_output
= 1;
4255 stmt_float_cons (kind
);
4256 obj_elf_previous (0);
4257 md
.keep_pending_output
= 0;
4261 dot_xstringer (zero
)
4264 char *name
= parse_section_name ();
4268 md
.keep_pending_output
= 1;
4271 obj_elf_previous (0);
4272 md
.keep_pending_output
= 0;
4279 int saved_auto_align
= md
.auto_align
;
4280 char *name
= parse_section_name ();
4284 md
.keep_pending_output
= 1;
4288 md
.auto_align
= saved_auto_align
;
4289 obj_elf_previous (0);
4290 md
.keep_pending_output
= 0;
4294 dot_xfloat_cons_ua (kind
)
4297 int saved_auto_align
= md
.auto_align
;
4298 char *name
= parse_section_name ();
4302 md
.keep_pending_output
= 1;
4305 stmt_float_cons (kind
);
4306 md
.auto_align
= saved_auto_align
;
4307 obj_elf_previous (0);
4308 md
.keep_pending_output
= 0;
4311 /* .reg.val <regname>,value */
4315 int dummy ATTRIBUTE_UNUSED
;
4320 if (reg
.X_op
!= O_register
)
4322 as_bad (_("Register name expected"));
4323 ignore_rest_of_line ();
4325 else if (*input_line_pointer
++ != ',')
4327 as_bad (_("Comma expected"));
4328 ignore_rest_of_line ();
4332 valueT value
= get_absolute_expression ();
4333 int regno
= reg
.X_add_number
;
4334 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4335 as_warn (_("Register value annotation ignored"));
4338 gr_values
[regno
- REG_GR
].known
= 1;
4339 gr_values
[regno
- REG_GR
].value
= value
;
4340 gr_values
[regno
- REG_GR
].path
= md
.path
;
4343 demand_empty_rest_of_line ();
4346 /* select dv checking mode
4351 A stop is inserted when changing modes
4358 if (md
.manual_bundling
)
4359 as_warn (_("Directive invalid within a bundle"));
4361 if (type
== 'E' || type
== 'A')
4362 md
.mode_explicitly_set
= 0;
4364 md
.mode_explicitly_set
= 1;
4371 if (md
.explicit_mode
)
4372 insn_group_break (1, 0, 0);
4373 md
.explicit_mode
= 0;
4377 if (!md
.explicit_mode
)
4378 insn_group_break (1, 0, 0);
4379 md
.explicit_mode
= 1;
4383 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4384 insn_group_break (1, 0, 0);
4385 md
.explicit_mode
= md
.default_explicit_mode
;
4386 md
.mode_explicitly_set
= 0;
4397 for (regno
= 0; regno
< 64; regno
++)
4399 if (mask
& ((valueT
) 1 << regno
))
4401 fprintf (stderr
, "%s p%d", comma
, regno
);
4408 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4409 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4410 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4411 .pred.safe_across_calls p1 [, p2 [,...]]
4420 int p1
= -1, p2
= -1;
4424 if (*input_line_pointer
!= '"')
4426 as_bad (_("Missing predicate relation type"));
4427 ignore_rest_of_line ();
4433 char *form
= demand_copy_C_string (&len
);
4434 if (strcmp (form
, "mutex") == 0)
4436 else if (strcmp (form
, "clear") == 0)
4438 else if (strcmp (form
, "imply") == 0)
4442 as_bad (_("Unrecognized predicate relation type"));
4443 ignore_rest_of_line ();
4447 if (*input_line_pointer
== ',')
4448 ++input_line_pointer
;
4458 if (toupper (*input_line_pointer
) != 'P'
4459 || (regno
= atoi (++input_line_pointer
)) < 0
4462 as_bad (_("Predicate register expected"));
4463 ignore_rest_of_line ();
4466 while (isdigit (*input_line_pointer
))
4467 ++input_line_pointer
;
4474 as_warn (_("Duplicate predicate register ignored"));
4477 /* See if it's a range. */
4478 if (*input_line_pointer
== '-')
4481 ++input_line_pointer
;
4483 if (toupper (*input_line_pointer
) != 'P'
4484 || (regno
= atoi (++input_line_pointer
)) < 0
4487 as_bad (_("Predicate register expected"));
4488 ignore_rest_of_line ();
4491 while (isdigit (*input_line_pointer
))
4492 ++input_line_pointer
;
4496 as_bad (_("Bad register range"));
4497 ignore_rest_of_line ();
4508 if (*input_line_pointer
!= ',')
4510 ++input_line_pointer
;
4519 clear_qp_mutex (mask
);
4520 clear_qp_implies (mask
, (valueT
) 0);
4523 if (count
!= 2 || p1
== -1 || p2
== -1)
4524 as_bad (_("Predicate source and target required"));
4525 else if (p1
== 0 || p2
== 0)
4526 as_bad (_("Use of p0 is not valid in this context"));
4528 add_qp_imply (p1
, p2
);
4533 as_bad (_("At least two PR arguments expected"));
4538 as_bad (_("Use of p0 is not valid in this context"));
4541 add_qp_mutex (mask
);
4544 /* note that we don't override any existing relations */
4547 as_bad (_("At least one PR argument expected"));
4552 fprintf (stderr
, "Safe across calls: ");
4553 print_prmask (mask
);
4554 fprintf (stderr
, "\n");
4556 qp_safe_across_calls
= mask
;
4559 demand_empty_rest_of_line ();
4562 /* .entry label [, label [, ...]]
4563 Hint to DV code that the given labels are to be considered entry points.
4564 Otherwise, only global labels are considered entry points. */
4568 int dummy ATTRIBUTE_UNUSED
;
4577 name
= input_line_pointer
;
4578 c
= get_symbol_end ();
4579 symbolP
= symbol_find_or_make (name
);
4581 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4583 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4586 *input_line_pointer
= c
;
4588 c
= *input_line_pointer
;
4591 input_line_pointer
++;
4593 if (*input_line_pointer
== '\n')
4599 demand_empty_rest_of_line ();
4602 /* .mem.offset offset, base
4603 "base" is used to distinguish between offsets from a different base. */
4606 dot_mem_offset (dummy
)
4607 int dummy ATTRIBUTE_UNUSED
;
4609 md
.mem_offset
.hint
= 1;
4610 md
.mem_offset
.offset
= get_absolute_expression ();
4611 if (*input_line_pointer
!= ',')
4613 as_bad (_("Comma expected"));
4614 ignore_rest_of_line ();
4617 ++input_line_pointer
;
4618 md
.mem_offset
.base
= get_absolute_expression ();
4619 demand_empty_rest_of_line ();
4622 /* ia64-specific pseudo-ops: */
4623 const pseudo_typeS md_pseudo_table
[] =
4625 { "radix", dot_radix
, 0 },
4626 { "lcomm", s_lcomm_bytes
, 1 },
4627 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4628 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4629 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4630 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4631 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4632 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4633 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4634 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4635 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4636 { "proc", dot_proc
, 0 },
4637 { "body", dot_body
, 0 },
4638 { "prologue", dot_prologue
, 0 },
4639 { "endp", dot_endp
, 0 },
4640 { "file", dwarf2_directive_file
, 0 },
4641 { "loc", dwarf2_directive_loc
, 0 },
4643 { "fframe", dot_fframe
, 0 },
4644 { "vframe", dot_vframe
, 0 },
4645 { "vframesp", dot_vframesp
, 0 },
4646 { "vframepsp", dot_vframepsp
, 0 },
4647 { "save", dot_save
, 0 },
4648 { "restore", dot_restore
, 0 },
4649 { "restorereg", dot_restorereg
, 0 },
4650 { "restorereg.p", dot_restorereg_p
, 0 },
4651 { "handlerdata", dot_handlerdata
, 0 },
4652 { "unwentry", dot_unwentry
, 0 },
4653 { "altrp", dot_altrp
, 0 },
4654 { "savesp", dot_savemem
, 0 },
4655 { "savepsp", dot_savemem
, 1 },
4656 { "save.g", dot_saveg
, 0 },
4657 { "save.f", dot_savef
, 0 },
4658 { "save.b", dot_saveb
, 0 },
4659 { "save.gf", dot_savegf
, 0 },
4660 { "spill", dot_spill
, 0 },
4661 { "spillreg", dot_spillreg
, 0 },
4662 { "spillsp", dot_spillmem
, 0 },
4663 { "spillpsp", dot_spillmem
, 1 },
4664 { "spillreg.p", dot_spillreg_p
, 0 },
4665 { "spillsp.p", dot_spillmem_p
, 0 },
4666 { "spillpsp.p", dot_spillmem_p
, 1 },
4667 { "label_state", dot_label_state
, 0 },
4668 { "copy_state", dot_copy_state
, 0 },
4669 { "unwabi", dot_unwabi
, 0 },
4670 { "personality", dot_personality
, 0 },
4672 { "estate", dot_estate
, 0 },
4674 { "mii", dot_template
, 0x0 },
4675 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4676 { "mlx", dot_template
, 0x2 },
4677 { "mmi", dot_template
, 0x4 },
4678 { "mfi", dot_template
, 0x6 },
4679 { "mmf", dot_template
, 0x7 },
4680 { "mib", dot_template
, 0x8 },
4681 { "mbb", dot_template
, 0x9 },
4682 { "bbb", dot_template
, 0xb },
4683 { "mmb", dot_template
, 0xc },
4684 { "mfb", dot_template
, 0xe },
4686 { "lb", dot_scope
, 0 },
4687 { "le", dot_scope
, 1 },
4689 { "align", s_align_bytes
, 0 },
4690 { "regstk", dot_regstk
, 0 },
4691 { "rotr", dot_rot
, DYNREG_GR
},
4692 { "rotf", dot_rot
, DYNREG_FR
},
4693 { "rotp", dot_rot
, DYNREG_PR
},
4694 { "lsb", dot_byteorder
, 0 },
4695 { "msb", dot_byteorder
, 1 },
4696 { "psr", dot_psr
, 0 },
4697 { "alias", dot_alias
, 0 },
4698 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4700 { "xdata1", dot_xdata
, 1 },
4701 { "xdata2", dot_xdata
, 2 },
4702 { "xdata4", dot_xdata
, 4 },
4703 { "xdata8", dot_xdata
, 8 },
4704 { "xreal4", dot_xfloat_cons
, 'f' },
4705 { "xreal8", dot_xfloat_cons
, 'd' },
4706 { "xreal10", dot_xfloat_cons
, 'x' },
4707 { "xstring", dot_xstringer
, 0 },
4708 { "xstringz", dot_xstringer
, 1 },
4710 /* unaligned versions: */
4711 { "xdata2.ua", dot_xdata_ua
, 2 },
4712 { "xdata4.ua", dot_xdata_ua
, 4 },
4713 { "xdata8.ua", dot_xdata_ua
, 8 },
4714 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4715 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4716 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4718 /* annotations/DV checking support */
4719 { "entry", dot_entry
, 0 },
4720 { "mem.offset", dot_mem_offset
, 0 },
4721 { "pred.rel", dot_pred_rel
, 0 },
4722 { "pred.rel.clear", dot_pred_rel
, 'c' },
4723 { "pred.rel.imply", dot_pred_rel
, 'i' },
4724 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4725 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4726 { "reg.val", dot_reg_val
, 0 },
4727 { "auto", dot_dv_mode
, 'a' },
4728 { "explicit", dot_dv_mode
, 'e' },
4729 { "default", dot_dv_mode
, 'd' },
4731 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4732 IA-64 aligns data allocation pseudo-ops by default, so we have to
4733 tell it that these ones are supposed to be unaligned. Long term,
4734 should rewrite so that only IA-64 specific data allocation pseudo-ops
4735 are aligned by default. */
4736 {"2byte", stmt_cons_ua
, 2},
4737 {"4byte", stmt_cons_ua
, 4},
4738 {"8byte", stmt_cons_ua
, 8},
4743 static const struct pseudo_opcode
4746 void (*handler
) (int);
4751 /* these are more like pseudo-ops, but don't start with a dot */
4752 { "data1", cons
, 1 },
4753 { "data2", cons
, 2 },
4754 { "data4", cons
, 4 },
4755 { "data8", cons
, 8 },
4756 { "real4", stmt_float_cons
, 'f' },
4757 { "real8", stmt_float_cons
, 'd' },
4758 { "real10", stmt_float_cons
, 'x' },
4759 { "string", stringer
, 0 },
4760 { "stringz", stringer
, 1 },
4762 /* unaligned versions: */
4763 { "data2.ua", stmt_cons_ua
, 2 },
4764 { "data4.ua", stmt_cons_ua
, 4 },
4765 { "data8.ua", stmt_cons_ua
, 8 },
4766 { "real4.ua", float_cons
, 'f' },
4767 { "real8.ua", float_cons
, 'd' },
4768 { "real10.ua", float_cons
, 'x' },
4771 /* Declare a register by creating a symbol for it and entering it in
4772 the symbol table. */
4775 declare_register (name
, regnum
)
4782 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4784 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4786 as_fatal ("Inserting \"%s\" into register table failed: %s",
4793 declare_register_set (prefix
, num_regs
, base_regnum
)
4801 for (i
= 0; i
< num_regs
; ++i
)
4803 sprintf (name
, "%s%u", prefix
, i
);
4804 declare_register (name
, base_regnum
+ i
);
4809 operand_width (opnd
)
4810 enum ia64_opnd opnd
;
4812 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4813 unsigned int bits
= 0;
4817 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4818 bits
+= odesc
->field
[i
].bits
;
4823 static enum operand_match_result
4824 operand_match (idesc
, index
, e
)
4825 const struct ia64_opcode
*idesc
;
4829 enum ia64_opnd opnd
= idesc
->operands
[index
];
4830 int bits
, relocatable
= 0;
4831 struct insn_fix
*fix
;
4838 case IA64_OPND_AR_CCV
:
4839 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4840 return OPERAND_MATCH
;
4843 case IA64_OPND_AR_PFS
:
4844 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4845 return OPERAND_MATCH
;
4849 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4850 return OPERAND_MATCH
;
4854 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4855 return OPERAND_MATCH
;
4859 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4860 return OPERAND_MATCH
;
4863 case IA64_OPND_PR_ROT
:
4864 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4865 return OPERAND_MATCH
;
4869 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4870 return OPERAND_MATCH
;
4873 case IA64_OPND_PSR_L
:
4874 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4875 return OPERAND_MATCH
;
4878 case IA64_OPND_PSR_UM
:
4879 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4880 return OPERAND_MATCH
;
4884 if (e
->X_op
== O_constant
)
4886 if (e
->X_add_number
== 1)
4887 return OPERAND_MATCH
;
4889 return OPERAND_OUT_OF_RANGE
;
4894 if (e
->X_op
== O_constant
)
4896 if (e
->X_add_number
== 8)
4897 return OPERAND_MATCH
;
4899 return OPERAND_OUT_OF_RANGE
;
4904 if (e
->X_op
== O_constant
)
4906 if (e
->X_add_number
== 16)
4907 return OPERAND_MATCH
;
4909 return OPERAND_OUT_OF_RANGE
;
4913 /* register operands: */
4916 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4917 && e
->X_add_number
< REG_AR
+ 128)
4918 return OPERAND_MATCH
;
4923 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4924 && e
->X_add_number
< REG_BR
+ 8)
4925 return OPERAND_MATCH
;
4929 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4930 && e
->X_add_number
< REG_CR
+ 128)
4931 return OPERAND_MATCH
;
4938 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4939 && e
->X_add_number
< REG_FR
+ 128)
4940 return OPERAND_MATCH
;
4945 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4946 && e
->X_add_number
< REG_P
+ 64)
4947 return OPERAND_MATCH
;
4953 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4954 && e
->X_add_number
< REG_GR
+ 128)
4955 return OPERAND_MATCH
;
4958 case IA64_OPND_R3_2
:
4959 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
4961 if (e
->X_add_number
< REG_GR
+ 4)
4962 return OPERAND_MATCH
;
4963 else if (e
->X_add_number
< REG_GR
+ 128)
4964 return OPERAND_OUT_OF_RANGE
;
4968 /* indirect operands: */
4969 case IA64_OPND_CPUID_R3
:
4970 case IA64_OPND_DBR_R3
:
4971 case IA64_OPND_DTR_R3
:
4972 case IA64_OPND_ITR_R3
:
4973 case IA64_OPND_IBR_R3
:
4974 case IA64_OPND_MSR_R3
:
4975 case IA64_OPND_PKR_R3
:
4976 case IA64_OPND_PMC_R3
:
4977 case IA64_OPND_PMD_R3
:
4978 case IA64_OPND_RR_R3
:
4979 if (e
->X_op
== O_index
&& e
->X_op_symbol
4980 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4981 == opnd
- IA64_OPND_CPUID_R3
))
4982 return OPERAND_MATCH
;
4986 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4987 return OPERAND_MATCH
;
4990 /* immediate operands: */
4991 case IA64_OPND_CNT2a
:
4992 case IA64_OPND_LEN4
:
4993 case IA64_OPND_LEN6
:
4994 bits
= operand_width (idesc
->operands
[index
]);
4995 if (e
->X_op
== O_constant
)
4997 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4998 return OPERAND_MATCH
;
5000 return OPERAND_OUT_OF_RANGE
;
5004 case IA64_OPND_CNT2b
:
5005 if (e
->X_op
== O_constant
)
5007 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5008 return OPERAND_MATCH
;
5010 return OPERAND_OUT_OF_RANGE
;
5014 case IA64_OPND_CNT2c
:
5015 val
= e
->X_add_number
;
5016 if (e
->X_op
== O_constant
)
5018 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5019 return OPERAND_MATCH
;
5021 return OPERAND_OUT_OF_RANGE
;
5026 /* SOR must be an integer multiple of 8 */
5027 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5028 return OPERAND_OUT_OF_RANGE
;
5031 if (e
->X_op
== O_constant
)
5033 if ((bfd_vma
) e
->X_add_number
<= 96)
5034 return OPERAND_MATCH
;
5036 return OPERAND_OUT_OF_RANGE
;
5040 case IA64_OPND_IMMU62
:
5041 if (e
->X_op
== O_constant
)
5043 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5044 return OPERAND_MATCH
;
5046 return OPERAND_OUT_OF_RANGE
;
5050 /* FIXME -- need 62-bit relocation type */
5051 as_bad (_("62-bit relocation not yet implemented"));
5055 case IA64_OPND_IMMU64
:
5056 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5057 || e
->X_op
== O_subtract
)
5059 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5060 fix
->code
= BFD_RELOC_IA64_IMM64
;
5061 if (e
->X_op
!= O_subtract
)
5063 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5064 if (e
->X_op
== O_pseudo_fixup
)
5068 fix
->opnd
= idesc
->operands
[index
];
5071 ++CURR_SLOT
.num_fixups
;
5072 return OPERAND_MATCH
;
5074 else if (e
->X_op
== O_constant
)
5075 return OPERAND_MATCH
;
5078 case IA64_OPND_CCNT5
:
5079 case IA64_OPND_CNT5
:
5080 case IA64_OPND_CNT6
:
5081 case IA64_OPND_CPOS6a
:
5082 case IA64_OPND_CPOS6b
:
5083 case IA64_OPND_CPOS6c
:
5084 case IA64_OPND_IMMU2
:
5085 case IA64_OPND_IMMU7a
:
5086 case IA64_OPND_IMMU7b
:
5087 case IA64_OPND_IMMU21
:
5088 case IA64_OPND_IMMU24
:
5089 case IA64_OPND_MBTYPE4
:
5090 case IA64_OPND_MHTYPE8
:
5091 case IA64_OPND_POS6
:
5092 bits
= operand_width (idesc
->operands
[index
]);
5093 if (e
->X_op
== O_constant
)
5095 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5096 return OPERAND_MATCH
;
5098 return OPERAND_OUT_OF_RANGE
;
5102 case IA64_OPND_IMMU9
:
5103 bits
= operand_width (idesc
->operands
[index
]);
5104 if (e
->X_op
== O_constant
)
5106 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5108 int lobits
= e
->X_add_number
& 0x3;
5109 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5110 e
->X_add_number
|= (bfd_vma
) 0x3;
5111 return OPERAND_MATCH
;
5114 return OPERAND_OUT_OF_RANGE
;
5118 case IA64_OPND_IMM44
:
5119 /* least 16 bits must be zero */
5120 if ((e
->X_add_number
& 0xffff) != 0)
5121 /* XXX technically, this is wrong: we should not be issuing warning
5122 messages until we're sure this instruction pattern is going to
5124 as_warn (_("lower 16 bits of mask ignored"));
5126 if (e
->X_op
== O_constant
)
5128 if (((e
->X_add_number
>= 0
5129 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5130 || (e
->X_add_number
< 0
5131 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5134 if (e
->X_add_number
>= 0
5135 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5137 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5139 return OPERAND_MATCH
;
5142 return OPERAND_OUT_OF_RANGE
;
5146 case IA64_OPND_IMM17
:
5147 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5148 if (e
->X_op
== O_constant
)
5150 if (((e
->X_add_number
>= 0
5151 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5152 || (e
->X_add_number
< 0
5153 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5156 if (e
->X_add_number
>= 0
5157 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5159 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5161 return OPERAND_MATCH
;
5164 return OPERAND_OUT_OF_RANGE
;
5168 case IA64_OPND_IMM14
:
5169 case IA64_OPND_IMM22
:
5171 case IA64_OPND_IMM1
:
5172 case IA64_OPND_IMM8
:
5173 case IA64_OPND_IMM8U4
:
5174 case IA64_OPND_IMM8M1
:
5175 case IA64_OPND_IMM8M1U4
:
5176 case IA64_OPND_IMM8M1U8
:
5177 case IA64_OPND_IMM9a
:
5178 case IA64_OPND_IMM9b
:
5179 bits
= operand_width (idesc
->operands
[index
]);
5180 if (relocatable
&& (e
->X_op
== O_symbol
5181 || e
->X_op
== O_subtract
5182 || e
->X_op
== O_pseudo_fixup
))
5184 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5186 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5187 fix
->code
= BFD_RELOC_IA64_IMM14
;
5189 fix
->code
= BFD_RELOC_IA64_IMM22
;
5191 if (e
->X_op
!= O_subtract
)
5193 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5194 if (e
->X_op
== O_pseudo_fixup
)
5198 fix
->opnd
= idesc
->operands
[index
];
5201 ++CURR_SLOT
.num_fixups
;
5202 return OPERAND_MATCH
;
5204 else if (e
->X_op
!= O_constant
5205 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5206 return OPERAND_MISMATCH
;
5208 if (opnd
== IA64_OPND_IMM8M1U4
)
5210 /* Zero is not valid for unsigned compares that take an adjusted
5211 constant immediate range. */
5212 if (e
->X_add_number
== 0)
5213 return OPERAND_OUT_OF_RANGE
;
5215 /* Sign-extend 32-bit unsigned numbers, so that the following range
5216 checks will work. */
5217 val
= e
->X_add_number
;
5218 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5219 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5220 val
= ((val
<< 32) >> 32);
5222 /* Check for 0x100000000. This is valid because
5223 0x100000000-1 is the same as ((uint32_t) -1). */
5224 if (val
== ((bfd_signed_vma
) 1 << 32))
5225 return OPERAND_MATCH
;
5229 else if (opnd
== IA64_OPND_IMM8M1U8
)
5231 /* Zero is not valid for unsigned compares that take an adjusted
5232 constant immediate range. */
5233 if (e
->X_add_number
== 0)
5234 return OPERAND_OUT_OF_RANGE
;
5236 /* Check for 0x10000000000000000. */
5237 if (e
->X_op
== O_big
)
5239 if (generic_bignum
[0] == 0
5240 && generic_bignum
[1] == 0
5241 && generic_bignum
[2] == 0
5242 && generic_bignum
[3] == 0
5243 && generic_bignum
[4] == 1)
5244 return OPERAND_MATCH
;
5246 return OPERAND_OUT_OF_RANGE
;
5249 val
= e
->X_add_number
- 1;
5251 else if (opnd
== IA64_OPND_IMM8M1
)
5252 val
= e
->X_add_number
- 1;
5253 else if (opnd
== IA64_OPND_IMM8U4
)
5255 /* Sign-extend 32-bit unsigned numbers, so that the following range
5256 checks will work. */
5257 val
= e
->X_add_number
;
5258 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5259 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5260 val
= ((val
<< 32) >> 32);
5263 val
= e
->X_add_number
;
5265 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5266 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5267 return OPERAND_MATCH
;
5269 return OPERAND_OUT_OF_RANGE
;
5271 case IA64_OPND_INC3
:
5272 /* +/- 1, 4, 8, 16 */
5273 val
= e
->X_add_number
;
5276 if (e
->X_op
== O_constant
)
5278 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5279 return OPERAND_MATCH
;
5281 return OPERAND_OUT_OF_RANGE
;
5285 case IA64_OPND_TGT25
:
5286 case IA64_OPND_TGT25b
:
5287 case IA64_OPND_TGT25c
:
5288 case IA64_OPND_TGT64
:
5289 if (e
->X_op
== O_symbol
)
5291 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5292 if (opnd
== IA64_OPND_TGT25
)
5293 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5294 else if (opnd
== IA64_OPND_TGT25b
)
5295 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5296 else if (opnd
== IA64_OPND_TGT25c
)
5297 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5298 else if (opnd
== IA64_OPND_TGT64
)
5299 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5303 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5304 fix
->opnd
= idesc
->operands
[index
];
5307 ++CURR_SLOT
.num_fixups
;
5308 return OPERAND_MATCH
;
5310 case IA64_OPND_TAG13
:
5311 case IA64_OPND_TAG13b
:
5315 return OPERAND_MATCH
;
5318 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5319 /* There are no external relocs for TAG13/TAG13b fields, so we
5320 create a dummy reloc. This will not live past md_apply_fix3. */
5321 fix
->code
= BFD_RELOC_UNUSED
;
5322 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5323 fix
->opnd
= idesc
->operands
[index
];
5326 ++CURR_SLOT
.num_fixups
;
5327 return OPERAND_MATCH
;
5337 return OPERAND_MISMATCH
;
5346 memset (e
, 0, sizeof (*e
));
5349 if (*input_line_pointer
!= '}')
5351 sep
= *input_line_pointer
++;
5355 if (!md
.manual_bundling
)
5356 as_warn ("Found '}' when manual bundling is off");
5358 CURR_SLOT
.manual_bundling_off
= 1;
5359 md
.manual_bundling
= 0;
5365 /* Returns the next entry in the opcode table that matches the one in
5366 IDESC, and frees the entry in IDESC. If no matching entry is
5367 found, NULL is returned instead. */
5369 static struct ia64_opcode
*
5370 get_next_opcode (struct ia64_opcode
*idesc
)
5372 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5373 ia64_free_opcode (idesc
);
5377 /* Parse the operands for the opcode and find the opcode variant that
5378 matches the specified operands, or NULL if no match is possible. */
5380 static struct ia64_opcode
*
5381 parse_operands (idesc
)
5382 struct ia64_opcode
*idesc
;
5384 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5385 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5386 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5387 enum operand_match_result result
;
5389 char *first_arg
= 0, *end
, *saved_input_pointer
;
5392 assert (strlen (idesc
->name
) <= 128);
5394 strcpy (mnemonic
, idesc
->name
);
5395 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5397 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5398 can't parse the first operand until we have parsed the
5399 remaining operands of the "alloc" instruction. */
5401 first_arg
= input_line_pointer
;
5402 end
= strchr (input_line_pointer
, '=');
5405 as_bad ("Expected separator `='");
5408 input_line_pointer
= end
+ 1;
5413 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5415 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5416 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5421 if (sep
!= '=' && sep
!= ',')
5426 if (num_outputs
> 0)
5427 as_bad ("Duplicate equal sign (=) in instruction");
5429 num_outputs
= i
+ 1;
5434 as_bad ("Illegal operand separator `%c'", sep
);
5438 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5440 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5441 know (strcmp (idesc
->name
, "alloc") == 0);
5442 if (num_operands
== 5 /* first_arg not included in this count! */
5443 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5444 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5445 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5446 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5448 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5449 CURR_SLOT
.opnd
[3].X_add_number
,
5450 CURR_SLOT
.opnd
[4].X_add_number
,
5451 CURR_SLOT
.opnd
[5].X_add_number
);
5453 /* now we can parse the first arg: */
5454 saved_input_pointer
= input_line_pointer
;
5455 input_line_pointer
= first_arg
;
5456 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5458 --num_outputs
; /* force error */
5459 input_line_pointer
= saved_input_pointer
;
5461 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5462 CURR_SLOT
.opnd
[3].X_add_number
5463 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5464 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5468 highest_unmatched_operand
= 0;
5469 curr_out_of_range_pos
= -1;
5471 expected_operand
= idesc
->operands
[0];
5472 for (; idesc
; idesc
= get_next_opcode (idesc
))
5474 if (num_outputs
!= idesc
->num_outputs
)
5475 continue; /* mismatch in # of outputs */
5477 CURR_SLOT
.num_fixups
= 0;
5479 /* Try to match all operands. If we see an out-of-range operand,
5480 then continue trying to match the rest of the operands, since if
5481 the rest match, then this idesc will give the best error message. */
5483 out_of_range_pos
= -1;
5484 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5486 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5487 if (result
!= OPERAND_MATCH
)
5489 if (result
!= OPERAND_OUT_OF_RANGE
)
5491 if (out_of_range_pos
< 0)
5492 /* remember position of the first out-of-range operand: */
5493 out_of_range_pos
= i
;
5497 /* If we did not match all operands, or if at least one operand was
5498 out-of-range, then this idesc does not match. Keep track of which
5499 idesc matched the most operands before failing. If we have two
5500 idescs that failed at the same position, and one had an out-of-range
5501 operand, then prefer the out-of-range operand. Thus if we have
5502 "add r0=0x1000000,r1" we get an error saying the constant is out
5503 of range instead of an error saying that the constant should have been
5506 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5508 if (i
> highest_unmatched_operand
5509 || (i
== highest_unmatched_operand
5510 && out_of_range_pos
> curr_out_of_range_pos
))
5512 highest_unmatched_operand
= i
;
5513 if (out_of_range_pos
>= 0)
5515 expected_operand
= idesc
->operands
[out_of_range_pos
];
5516 error_pos
= out_of_range_pos
;
5520 expected_operand
= idesc
->operands
[i
];
5523 curr_out_of_range_pos
= out_of_range_pos
;
5528 if (num_operands
< NELEMS (idesc
->operands
)
5529 && idesc
->operands
[num_operands
])
5530 continue; /* mismatch in number of arguments */
5536 if (expected_operand
)
5537 as_bad ("Operand %u of `%s' should be %s",
5538 error_pos
+ 1, mnemonic
,
5539 elf64_ia64_operands
[expected_operand
].desc
);
5541 as_bad ("Operand mismatch");
5547 /* Keep track of state necessary to determine whether a NOP is necessary
5548 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5549 detect a case where additional NOPs may be necessary. */
5551 errata_nop_necessary_p (slot
, insn_unit
)
5553 enum ia64_unit insn_unit
;
5556 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5557 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5558 struct ia64_opcode
*idesc
= slot
->idesc
;
5560 /* Test whether this could be the first insn in a problematic sequence. */
5561 if (insn_unit
== IA64_UNIT_F
)
5563 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5564 if (idesc
->operands
[i
] == IA64_OPND_P1
5565 || idesc
->operands
[i
] == IA64_OPND_P2
)
5567 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5568 /* Ignore invalid operands; they generate errors elsewhere. */
5571 this_group
->p_reg_set
[regno
] = 1;
5575 /* Test whether this could be the second insn in a problematic sequence. */
5576 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5577 && prev_group
->p_reg_set
[slot
->qp_regno
])
5579 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5580 if (idesc
->operands
[i
] == IA64_OPND_R1
5581 || idesc
->operands
[i
] == IA64_OPND_R2
5582 || idesc
->operands
[i
] == IA64_OPND_R3
)
5584 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5585 /* Ignore invalid operands; they generate errors elsewhere. */
5588 if (strncmp (idesc
->name
, "add", 3) != 0
5589 && strncmp (idesc
->name
, "sub", 3) != 0
5590 && strncmp (idesc
->name
, "shladd", 6) != 0
5591 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5592 this_group
->g_reg_set_conditionally
[regno
] = 1;
5596 /* Test whether this could be the third insn in a problematic sequence. */
5597 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5599 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5600 idesc
->operands
[i
] == IA64_OPND_R3
5601 /* For mov indirect. */
5602 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5603 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5604 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5605 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5606 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5607 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5608 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5609 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5611 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5612 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5613 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5614 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5616 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5617 /* Ignore invalid operands; they generate errors elsewhere. */
5620 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5622 if (strcmp (idesc
->name
, "fc") != 0
5623 && strcmp (idesc
->name
, "tak") != 0
5624 && strcmp (idesc
->name
, "thash") != 0
5625 && strcmp (idesc
->name
, "tpa") != 0
5626 && strcmp (idesc
->name
, "ttag") != 0
5627 && strncmp (idesc
->name
, "ptr", 3) != 0
5628 && strncmp (idesc
->name
, "ptc", 3) != 0
5629 && strncmp (idesc
->name
, "probe", 5) != 0)
5632 if (prev_group
->g_reg_set_conditionally
[regno
])
5640 build_insn (slot
, insnp
)
5644 const struct ia64_operand
*odesc
, *o2desc
;
5645 struct ia64_opcode
*idesc
= slot
->idesc
;
5646 bfd_signed_vma insn
, val
;
5650 insn
= idesc
->opcode
| slot
->qp_regno
;
5652 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5654 if (slot
->opnd
[i
].X_op
== O_register
5655 || slot
->opnd
[i
].X_op
== O_constant
5656 || slot
->opnd
[i
].X_op
== O_index
)
5657 val
= slot
->opnd
[i
].X_add_number
;
5658 else if (slot
->opnd
[i
].X_op
== O_big
)
5660 /* This must be the value 0x10000000000000000. */
5661 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5667 switch (idesc
->operands
[i
])
5669 case IA64_OPND_IMMU64
:
5670 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5671 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5672 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5673 | (((val
>> 63) & 0x1) << 36));
5676 case IA64_OPND_IMMU62
:
5677 val
&= 0x3fffffffffffffffULL
;
5678 if (val
!= slot
->opnd
[i
].X_add_number
)
5679 as_warn (_("Value truncated to 62 bits"));
5680 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5681 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5684 case IA64_OPND_TGT64
:
5686 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5687 insn
|= ((((val
>> 59) & 0x1) << 36)
5688 | (((val
>> 0) & 0xfffff) << 13));
5719 case IA64_OPND_R3_2
:
5720 case IA64_OPND_CPUID_R3
:
5721 case IA64_OPND_DBR_R3
:
5722 case IA64_OPND_DTR_R3
:
5723 case IA64_OPND_ITR_R3
:
5724 case IA64_OPND_IBR_R3
:
5726 case IA64_OPND_MSR_R3
:
5727 case IA64_OPND_PKR_R3
:
5728 case IA64_OPND_PMC_R3
:
5729 case IA64_OPND_PMD_R3
:
5730 case IA64_OPND_RR_R3
:
5738 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5739 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5741 as_bad_where (slot
->src_file
, slot
->src_line
,
5742 "Bad operand value: %s", err
);
5743 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5745 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5746 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5748 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5749 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5751 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5752 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5753 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5755 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5756 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5766 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5767 unsigned int manual_bundling
= 0;
5768 enum ia64_unit required_unit
, insn_unit
= 0;
5769 enum ia64_insn_type type
[3], insn_type
;
5770 unsigned int template, orig_template
;
5771 bfd_vma insn
[3] = { -1, -1, -1 };
5772 struct ia64_opcode
*idesc
;
5773 int end_of_insn_group
= 0, user_template
= -1;
5774 int n
, i
, j
, first
, curr
;
5776 bfd_vma t0
= 0, t1
= 0;
5777 struct label_fix
*lfix
;
5778 struct insn_fix
*ifix
;
5783 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5784 know (first
>= 0 & first
< NUM_SLOTS
);
5785 n
= MIN (3, md
.num_slots_in_use
);
5787 /* Determine template: user user_template if specified, best match
5790 if (md
.slot
[first
].user_template
>= 0)
5791 user_template
= template = md
.slot
[first
].user_template
;
5794 /* Auto select appropriate template. */
5795 memset (type
, 0, sizeof (type
));
5797 for (i
= 0; i
< n
; ++i
)
5799 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5801 type
[i
] = md
.slot
[curr
].idesc
->type
;
5802 curr
= (curr
+ 1) % NUM_SLOTS
;
5804 template = best_template
[type
[0]][type
[1]][type
[2]];
5807 /* initialize instructions with appropriate nops: */
5808 for (i
= 0; i
< 3; ++i
)
5809 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5813 /* now fill in slots with as many insns as possible: */
5815 idesc
= md
.slot
[curr
].idesc
;
5816 end_of_insn_group
= 0;
5817 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5819 /* Set the slot number for prologue/body records now as those
5820 refer to the current point, not the point after the
5821 instruction has been issued: */
5822 /* Don't try to delete prologue/body records here, as that will cause
5823 them to also be deleted from the master list of unwind records. */
5824 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5825 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5826 || ptr
->r
.type
== body
)
5828 ptr
->slot_number
= (unsigned long) f
+ i
;
5829 ptr
->slot_frag
= frag_now
;
5832 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5834 if (manual_bundling
&& i
!= 2)
5835 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5836 "`%s' must be last in bundle", idesc
->name
);
5840 if (idesc
->flags
& IA64_OPCODE_LAST
)
5843 unsigned int required_template
;
5845 /* If we need a stop bit after an M slot, our only choice is
5846 template 5 (M;;MI). If we need a stop bit after a B
5847 slot, our only choice is to place it at the end of the
5848 bundle, because the only available templates are MIB,
5849 MBB, BBB, MMB, and MFB. We don't handle anything other
5850 than M and B slots because these are the only kind of
5851 instructions that can have the IA64_OPCODE_LAST bit set. */
5852 required_template
= template;
5853 switch (idesc
->type
)
5857 required_template
= 5;
5865 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5866 "Internal error: don't know how to force %s to end"
5867 "of instruction group", idesc
->name
);
5871 if (manual_bundling
&& i
!= required_slot
)
5872 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5873 "`%s' must be last in instruction group",
5875 if (required_slot
< i
)
5876 /* Can't fit this instruction. */
5880 if (required_template
!= template)
5882 /* If we switch the template, we need to reset the NOPs
5883 after slot i. The slot-types of the instructions ahead
5884 of i never change, so we don't need to worry about
5885 changing NOPs in front of this slot. */
5886 for (j
= i
; j
< 3; ++j
)
5887 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5889 template = required_template
;
5891 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5893 if (manual_bundling_on
)
5894 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5895 "Label must be first in a bundle");
5896 /* This insn must go into the first slot of a bundle. */
5900 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5901 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5903 if (manual_bundling_on
)
5906 manual_bundling
= 1;
5908 break; /* need to start a new bundle */
5911 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5913 /* We need an instruction group boundary in the middle of a
5914 bundle. See if we can switch to an other template with
5915 an appropriate boundary. */
5917 orig_template
= template;
5918 if (i
== 1 && (user_template
== 4
5919 || (user_template
< 0
5920 && (ia64_templ_desc
[template].exec_unit
[0]
5924 end_of_insn_group
= 0;
5926 else if (i
== 2 && (user_template
== 0
5927 || (user_template
< 0
5928 && (ia64_templ_desc
[template].exec_unit
[1]
5930 /* This test makes sure we don't switch the template if
5931 the next instruction is one that needs to be first in
5932 an instruction group. Since all those instructions are
5933 in the M group, there is no way such an instruction can
5934 fit in this bundle even if we switch the template. The
5935 reason we have to check for this is that otherwise we
5936 may end up generating "MI;;I M.." which has the deadly
5937 effect that the second M instruction is no longer the
5938 first in the bundle! --davidm 99/12/16 */
5939 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5942 end_of_insn_group
= 0;
5944 else if (curr
!= first
)
5945 /* can't fit this insn */
5948 if (template != orig_template
)
5949 /* if we switch the template, we need to reset the NOPs
5950 after slot i. The slot-types of the instructions ahead
5951 of i never change, so we don't need to worry about
5952 changing NOPs in front of this slot. */
5953 for (j
= i
; j
< 3; ++j
)
5954 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5956 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5958 /* resolve dynamic opcodes such as "break" and "nop": */
5959 if (idesc
->type
== IA64_TYPE_DYN
)
5961 if ((strcmp (idesc
->name
, "nop") == 0)
5962 || (strcmp (idesc
->name
, "break") == 0))
5963 insn_unit
= required_unit
;
5964 else if (strcmp (idesc
->name
, "chk.s") == 0)
5966 insn_unit
= IA64_UNIT_M
;
5967 if (required_unit
== IA64_UNIT_I
)
5968 insn_unit
= IA64_UNIT_I
;
5971 as_fatal ("emit_one_bundle: unexpected dynamic op");
5973 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5974 ia64_free_opcode (idesc
);
5975 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5977 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5982 insn_type
= idesc
->type
;
5983 insn_unit
= IA64_UNIT_NIL
;
5987 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5988 insn_unit
= required_unit
;
5990 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5991 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5992 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5993 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5994 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5999 if (insn_unit
!= required_unit
)
6001 if (required_unit
== IA64_UNIT_L
6002 && insn_unit
== IA64_UNIT_I
6003 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6005 /* we got ourselves an MLX template but the current
6006 instruction isn't an X-unit, or an I-unit instruction
6007 that can go into the X slot of an MLX template. Duh. */
6008 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6010 as_bad_where (md
.slot
[curr
].src_file
,
6011 md
.slot
[curr
].src_line
,
6012 "`%s' can't go in X slot of "
6013 "MLX template", idesc
->name
);
6014 /* drop this insn so we don't livelock: */
6015 --md
.num_slots_in_use
;
6019 continue; /* try next slot */
6025 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6026 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6029 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6030 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6032 build_insn (md
.slot
+ curr
, insn
+ i
);
6034 /* Set slot counts for non prologue/body unwind records. */
6035 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6036 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6037 && ptr
->r
.type
!= body
)
6039 ptr
->slot_number
= (unsigned long) f
+ i
;
6040 ptr
->slot_frag
= frag_now
;
6042 md
.slot
[curr
].unwind_record
= NULL
;
6044 if (required_unit
== IA64_UNIT_L
)
6047 /* skip one slot for long/X-unit instructions */
6050 --md
.num_slots_in_use
;
6052 /* now is a good time to fix up the labels for this insn: */
6053 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6055 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6056 symbol_set_frag (lfix
->sym
, frag_now
);
6058 /* and fix up the tags also. */
6059 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6061 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6062 symbol_set_frag (lfix
->sym
, frag_now
);
6065 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6067 ifix
= md
.slot
[curr
].fixup
+ j
;
6068 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6069 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6070 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6071 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6072 fix
->fx_file
= md
.slot
[curr
].src_file
;
6073 fix
->fx_line
= md
.slot
[curr
].src_line
;
6076 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6078 if (end_of_insn_group
)
6080 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6081 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6085 ia64_free_opcode (md
.slot
[curr
].idesc
);
6086 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6087 md
.slot
[curr
].user_template
= -1;
6089 if (manual_bundling_off
)
6091 manual_bundling
= 0;
6094 curr
= (curr
+ 1) % NUM_SLOTS
;
6095 idesc
= md
.slot
[curr
].idesc
;
6097 if (manual_bundling
)
6099 if (md
.num_slots_in_use
> 0)
6100 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6101 "`%s' does not fit into %s template",
6102 idesc
->name
, ia64_templ_desc
[template].name
);
6104 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6105 "Missing '}' at end of file");
6107 know (md
.num_slots_in_use
< NUM_SLOTS
);
6109 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6110 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6112 number_to_chars_littleendian (f
+ 0, t0
, 8);
6113 number_to_chars_littleendian (f
+ 8, t1
, 8);
6115 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6116 unwind
.next_slot_frag
= frag_now
;
6120 md_parse_option (c
, arg
)
6127 /* Switches from the Intel assembler. */
6129 if (strcmp (arg
, "ilp64") == 0
6130 || strcmp (arg
, "lp64") == 0
6131 || strcmp (arg
, "p64") == 0)
6133 md
.flags
|= EF_IA_64_ABI64
;
6135 else if (strcmp (arg
, "ilp32") == 0)
6137 md
.flags
&= ~EF_IA_64_ABI64
;
6139 else if (strcmp (arg
, "le") == 0)
6141 md
.flags
&= ~EF_IA_64_BE
;
6143 else if (strcmp (arg
, "be") == 0)
6145 md
.flags
|= EF_IA_64_BE
;
6152 if (strcmp (arg
, "so") == 0)
6154 /* Suppress signon message. */
6156 else if (strcmp (arg
, "pi") == 0)
6158 /* Reject privileged instructions. FIXME */
6160 else if (strcmp (arg
, "us") == 0)
6162 /* Allow union of signed and unsigned range. FIXME */
6164 else if (strcmp (arg
, "close_fcalls") == 0)
6166 /* Do not resolve global function calls. */
6173 /* temp[="prefix"] Insert temporary labels into the object file
6174 symbol table prefixed by "prefix".
6175 Default prefix is ":temp:".
6180 /* indirect=<tgt> Assume unannotated indirect branches behavior
6181 according to <tgt> --
6182 exit: branch out from the current context (default)
6183 labels: all labels in context may be branch targets
6185 if (strncmp (arg
, "indirect=", 9) != 0)
6190 /* -X conflicts with an ignored option, use -x instead */
6192 if (!arg
|| strcmp (arg
, "explicit") == 0)
6194 /* set default mode to explicit */
6195 md
.default_explicit_mode
= 1;
6198 else if (strcmp (arg
, "auto") == 0)
6200 md
.default_explicit_mode
= 0;
6202 else if (strcmp (arg
, "debug") == 0)
6206 else if (strcmp (arg
, "debugx") == 0)
6208 md
.default_explicit_mode
= 1;
6213 as_bad (_("Unrecognized option '-x%s'"), arg
);
6218 /* nops Print nops statistics. */
6221 /* GNU specific switches for gcc. */
6222 case OPTION_MCONSTANT_GP
:
6223 md
.flags
|= EF_IA_64_CONS_GP
;
6226 case OPTION_MAUTO_PIC
:
6227 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6238 md_show_usage (stream
)
6243 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6244 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6245 -x | -xexplicit turn on dependency violation checking (default)\n\
6246 -xauto automagically remove dependency violations\n\
6247 -xdebug debug dependency violation checker\n"),
6251 /* Return true if TYPE fits in TEMPL at SLOT. */
6254 match (int templ
, int type
, int slot
)
6256 enum ia64_unit unit
;
6259 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6262 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6264 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6266 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6267 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6268 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6269 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6270 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6271 default: result
= 0; break;
6276 /* Add a bit of extra goodness if a nop of type F or B would fit
6277 in TEMPL at SLOT. */
6280 extra_goodness (int templ
, int slot
)
6282 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6284 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6289 /* This function is called once, at assembler startup time. It sets
6290 up all the tables, etc. that the MD part of the assembler will need
6291 that can be determined before arguments are parsed. */
6295 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6300 md
.explicit_mode
= md
.default_explicit_mode
;
6302 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6304 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6305 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6306 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6307 &zero_address_frag
);
6309 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6310 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6311 &zero_address_frag
);
6313 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6314 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6315 &zero_address_frag
);
6317 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6318 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6319 &zero_address_frag
);
6321 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6322 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6323 &zero_address_frag
);
6325 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6326 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6327 &zero_address_frag
);
6329 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6330 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6331 &zero_address_frag
);
6333 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6334 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6335 &zero_address_frag
);
6337 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6338 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6339 &zero_address_frag
);
6341 /* Compute the table of best templates. We compute goodness as a
6342 base 4 value, in which each match counts for 3, each F counts
6343 for 2, each B counts for 1. This should maximize the number of
6344 F and B nops in the chosen bundles, which is good because these
6345 pipelines are least likely to be overcommitted. */
6346 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6347 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6348 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6351 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6354 if (match (t
, i
, 0))
6356 if (match (t
, j
, 1))
6358 if (match (t
, k
, 2))
6359 goodness
= 3 + 3 + 3;
6361 goodness
= 3 + 3 + extra_goodness (t
, 2);
6363 else if (match (t
, j
, 2))
6364 goodness
= 3 + 3 + extra_goodness (t
, 1);
6368 goodness
+= extra_goodness (t
, 1);
6369 goodness
+= extra_goodness (t
, 2);
6372 else if (match (t
, i
, 1))
6374 if (match (t
, j
, 2))
6377 goodness
= 3 + extra_goodness (t
, 2);
6379 else if (match (t
, i
, 2))
6380 goodness
= 3 + extra_goodness (t
, 1);
6382 if (goodness
> best
)
6385 best_template
[i
][j
][k
] = t
;
6390 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6391 md
.slot
[i
].user_template
= -1;
6393 md
.pseudo_hash
= hash_new ();
6394 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6396 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6397 (void *) (pseudo_opcode
+ i
));
6399 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6400 pseudo_opcode
[i
].name
, err
);
6403 md
.reg_hash
= hash_new ();
6404 md
.dynreg_hash
= hash_new ();
6405 md
.const_hash
= hash_new ();
6406 md
.entry_hash
= hash_new ();
6408 /* general registers: */
6411 for (i
= 0; i
< total
; ++i
)
6413 sprintf (name
, "r%d", i
- REG_GR
);
6414 md
.regsym
[i
] = declare_register (name
, i
);
6417 /* floating point registers: */
6419 for (; i
< total
; ++i
)
6421 sprintf (name
, "f%d", i
- REG_FR
);
6422 md
.regsym
[i
] = declare_register (name
, i
);
6425 /* application registers: */
6428 for (; i
< total
; ++i
)
6430 sprintf (name
, "ar%d", i
- REG_AR
);
6431 md
.regsym
[i
] = declare_register (name
, i
);
6434 /* control registers: */
6437 for (; i
< total
; ++i
)
6439 sprintf (name
, "cr%d", i
- REG_CR
);
6440 md
.regsym
[i
] = declare_register (name
, i
);
6443 /* predicate registers: */
6445 for (; i
< total
; ++i
)
6447 sprintf (name
, "p%d", i
- REG_P
);
6448 md
.regsym
[i
] = declare_register (name
, i
);
6451 /* branch registers: */
6453 for (; i
< total
; ++i
)
6455 sprintf (name
, "b%d", i
- REG_BR
);
6456 md
.regsym
[i
] = declare_register (name
, i
);
6459 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6460 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6461 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6462 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6463 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6464 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6465 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6467 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6469 regnum
= indirect_reg
[i
].regnum
;
6470 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6473 /* define synonyms for application registers: */
6474 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6475 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6476 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6478 /* define synonyms for control registers: */
6479 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6480 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6481 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6483 declare_register ("gp", REG_GR
+ 1);
6484 declare_register ("sp", REG_GR
+ 12);
6485 declare_register ("rp", REG_BR
+ 0);
6487 /* pseudo-registers used to specify unwind info: */
6488 declare_register ("psp", REG_PSP
);
6490 declare_register_set ("ret", 4, REG_GR
+ 8);
6491 declare_register_set ("farg", 8, REG_FR
+ 8);
6492 declare_register_set ("fret", 8, REG_FR
+ 8);
6494 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6496 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6497 (PTR
) (const_bits
+ i
));
6499 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6503 /* Set the architecture and machine depending on defaults and command line
6505 if (md
.flags
& EF_IA_64_ABI64
)
6506 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6508 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6511 as_warn (_("Could not set architecture and machine"));
6513 /* Set the pointer size and pointer shift size depending on md.flags */
6515 if (md
.flags
& EF_IA_64_ABI64
)
6517 md
.pointer_size
= 8; /* pointers are 8 bytes */
6518 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6522 md
.pointer_size
= 4; /* pointers are 4 bytes */
6523 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6526 md
.mem_offset
.hint
= 0;
6529 md
.entry_labels
= NULL
;
6532 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6533 because that is called after md_parse_option which is where we do the
6534 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6535 default endianness. */
6538 ia64_init (argc
, argv
)
6539 int argc ATTRIBUTE_UNUSED
;
6540 char **argv ATTRIBUTE_UNUSED
;
6542 md
.flags
= EF_IA_64_ABI64
;
6543 if (TARGET_BYTES_BIG_ENDIAN
)
6544 md
.flags
|= EF_IA_64_BE
;
6547 /* Return a string for the target object file format. */
6550 ia64_target_format ()
6552 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6554 if (md
.flags
& EF_IA_64_BE
)
6556 if (md
.flags
& EF_IA_64_ABI64
)
6558 return "elf64-ia64-aix-big";
6560 return "elf64-ia64-big";
6564 return "elf32-ia64-aix-big";
6566 return "elf32-ia64-big";
6571 if (md
.flags
& EF_IA_64_ABI64
)
6573 return "elf64-ia64-aix-little";
6575 return "elf64-ia64-little";
6579 return "elf32-ia64-aix-little";
6581 return "elf32-ia64-little";
6586 return "unknown-format";
6590 ia64_end_of_source ()
6592 /* terminate insn group upon reaching end of file: */
6593 insn_group_break (1, 0, 0);
6595 /* emits slots we haven't written yet: */
6596 ia64_flush_insns ();
6598 bfd_set_private_flags (stdoutput
, md
.flags
);
6600 md
.mem_offset
.hint
= 0;
6606 if (md
.qp
.X_op
== O_register
)
6607 as_bad ("qualifying predicate not followed by instruction");
6608 md
.qp
.X_op
= O_absent
;
6610 if (ignore_input ())
6613 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6615 if (md
.detect_dv
&& !md
.explicit_mode
)
6616 as_warn (_("Explicit stops are ignored in auto mode"));
6618 insn_group_break (1, 0, 0);
6622 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6624 static int defining_tag
= 0;
6627 ia64_unrecognized_line (ch
)
6633 expression (&md
.qp
);
6634 if (*input_line_pointer
++ != ')')
6636 as_bad ("Expected ')'");
6639 if (md
.qp
.X_op
!= O_register
)
6641 as_bad ("Qualifying predicate expected");
6644 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6646 as_bad ("Predicate register expected");
6652 if (md
.manual_bundling
)
6653 as_warn ("Found '{' when manual bundling is already turned on");
6655 CURR_SLOT
.manual_bundling_on
= 1;
6656 md
.manual_bundling
= 1;
6658 /* Bundling is only acceptable in explicit mode
6659 or when in default automatic mode. */
6660 if (md
.detect_dv
&& !md
.explicit_mode
)
6662 if (!md
.mode_explicitly_set
6663 && !md
.default_explicit_mode
)
6666 as_warn (_("Found '{' after explicit switch to automatic mode"));
6671 if (!md
.manual_bundling
)
6672 as_warn ("Found '}' when manual bundling is off");
6674 PREV_SLOT
.manual_bundling_off
= 1;
6675 md
.manual_bundling
= 0;
6677 /* switch back to automatic mode, if applicable */
6680 && !md
.mode_explicitly_set
6681 && !md
.default_explicit_mode
)
6684 /* Allow '{' to follow on the same line. We also allow ";;", but that
6685 happens automatically because ';' is an end of line marker. */
6687 if (input_line_pointer
[0] == '{')
6689 input_line_pointer
++;
6690 return ia64_unrecognized_line ('{');
6693 demand_empty_rest_of_line ();
6703 if (md
.qp
.X_op
== O_register
)
6705 as_bad ("Tag must come before qualifying predicate.");
6709 /* This implements just enough of read_a_source_file in read.c to
6710 recognize labels. */
6711 if (is_name_beginner (*input_line_pointer
))
6713 s
= input_line_pointer
;
6714 c
= get_symbol_end ();
6716 else if (LOCAL_LABELS_FB
6717 && isdigit ((unsigned char) *input_line_pointer
))
6720 while (isdigit ((unsigned char) *input_line_pointer
))
6721 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6722 fb_label_instance_inc (temp
);
6723 s
= fb_label_name (temp
, 0);
6724 c
= *input_line_pointer
;
6733 /* Put ':' back for error messages' sake. */
6734 *input_line_pointer
++ = ':';
6735 as_bad ("Expected ':'");
6742 /* Put ':' back for error messages' sake. */
6743 *input_line_pointer
++ = ':';
6744 if (*input_line_pointer
++ != ']')
6746 as_bad ("Expected ']'");
6751 as_bad ("Tag name expected");
6761 /* Not a valid line. */
6766 ia64_frob_label (sym
)
6769 struct label_fix
*fix
;
6771 /* Tags need special handling since they are not bundle breaks like
6775 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6777 fix
->next
= CURR_SLOT
.tag_fixups
;
6778 CURR_SLOT
.tag_fixups
= fix
;
6783 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6785 md
.last_text_seg
= now_seg
;
6786 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6788 fix
->next
= CURR_SLOT
.label_fixups
;
6789 CURR_SLOT
.label_fixups
= fix
;
6791 /* Keep track of how many code entry points we've seen. */
6792 if (md
.path
== md
.maxpaths
)
6795 md
.entry_labels
= (const char **)
6796 xrealloc ((void *) md
.entry_labels
,
6797 md
.maxpaths
* sizeof (char *));
6799 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6804 ia64_flush_pending_output ()
6806 if (!md
.keep_pending_output
6807 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6809 /* ??? This causes many unnecessary stop bits to be emitted.
6810 Unfortunately, it isn't clear if it is safe to remove this. */
6811 insn_group_break (1, 0, 0);
6812 ia64_flush_insns ();
6816 /* Do ia64-specific expression optimization. All that's done here is
6817 to transform index expressions that are either due to the indexing
6818 of rotating registers or due to the indexing of indirect register
6821 ia64_optimize_expr (l
, op
, r
)
6830 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6832 num_regs
= (l
->X_add_number
>> 16);
6833 if ((unsigned) r
->X_add_number
>= num_regs
)
6836 as_bad ("No current frame");
6838 as_bad ("Index out of range 0..%u", num_regs
- 1);
6839 r
->X_add_number
= 0;
6841 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6844 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6846 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6847 || l
->X_add_number
== IND_MEM
)
6849 as_bad ("Indirect register set name expected");
6850 l
->X_add_number
= IND_CPUID
;
6853 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6854 l
->X_add_number
= r
->X_add_number
;
6862 ia64_parse_name (name
, e
)
6866 struct const_desc
*cdesc
;
6867 struct dynreg
*dr
= 0;
6868 unsigned int regnum
;
6872 /* first see if NAME is a known register name: */
6873 sym
= hash_find (md
.reg_hash
, name
);
6876 e
->X_op
= O_register
;
6877 e
->X_add_number
= S_GET_VALUE (sym
);
6881 cdesc
= hash_find (md
.const_hash
, name
);
6884 e
->X_op
= O_constant
;
6885 e
->X_add_number
= cdesc
->value
;
6889 /* check for inN, locN, or outN: */
6893 if (name
[1] == 'n' && isdigit (name
[2]))
6901 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6909 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6922 /* The name is inN, locN, or outN; parse the register number. */
6923 regnum
= strtoul (name
, &end
, 10);
6924 if (end
> name
&& *end
== '\0')
6926 if ((unsigned) regnum
>= dr
->num_regs
)
6929 as_bad ("No current frame");
6931 as_bad ("Register number out of range 0..%u",
6935 e
->X_op
= O_register
;
6936 e
->X_add_number
= dr
->base
+ regnum
;
6941 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6943 /* We've got ourselves the name of a rotating register set.
6944 Store the base register number in the low 16 bits of
6945 X_add_number and the size of the register set in the top 16
6947 e
->X_op
= O_register
;
6948 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6954 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6957 ia64_canonicalize_symbol_name (name
)
6960 size_t len
= strlen (name
);
6961 if (len
> 1 && name
[len
- 1] == '#')
6962 name
[len
- 1] = '\0';
6966 /* Return true if idesc is a conditional branch instruction. This excludes
6967 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
6968 because they always read/write resources regardless of the value of the
6969 qualifying predicate. br.ia must always use p0, and hence is always
6970 taken. Thus this function returns true for branches which can fall
6971 through, and which use no resources if they do fall through. */
6974 is_conditional_branch (idesc
)
6975 struct ia64_opcode
*idesc
;
6977 /* br is a conditional branch. Everything that starts with br. except
6978 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
6979 Everything that starts with brl is a conditional branch. */
6980 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
6981 && (idesc
->name
[2] == '\0'
6982 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
6983 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
6984 || idesc
->name
[2] == 'l'
6985 /* br.cond, br.call, br.clr */
6986 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
6987 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
6988 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
6991 /* Return whether the given opcode is a taken branch. If there's any doubt,
6995 is_taken_branch (idesc
)
6996 struct ia64_opcode
*idesc
;
6998 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6999 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7002 /* Return whether the given opcode is an interruption or rfi. If there's any
7003 doubt, returns zero. */
7006 is_interruption_or_rfi (idesc
)
7007 struct ia64_opcode
*idesc
;
7009 if (strcmp (idesc
->name
, "rfi") == 0)
7014 /* Returns the index of the given dependency in the opcode's list of chks, or
7015 -1 if there is no dependency. */
7018 depends_on (depind
, idesc
)
7020 struct ia64_opcode
*idesc
;
7023 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7024 for (i
= 0; i
< dep
->nchks
; i
++)
7026 if (depind
== DEP (dep
->chks
[i
]))
7032 /* Determine a set of specific resources used for a particular resource
7033 class. Returns the number of specific resources identified For those
7034 cases which are not determinable statically, the resource returned is
7037 Meanings of value in 'NOTE':
7038 1) only read/write when the register number is explicitly encoded in the
7040 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7041 accesses CFM when qualifying predicate is in the rotating region.
7042 3) general register value is used to specify an indirect register; not
7043 determinable statically.
7044 4) only read the given resource when bits 7:0 of the indirect index
7045 register value does not match the register number of the resource; not
7046 determinable statically.
7047 5) all rules are implementation specific.
7048 6) only when both the index specified by the reader and the index specified
7049 by the writer have the same value in bits 63:61; not determinable
7051 7) only access the specified resource when the corresponding mask bit is
7053 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7054 only read when these insns reference FR2-31
7055 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7056 written when these insns write FR32-127
7057 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7059 11) The target predicates are written independently of PR[qp], but source
7060 registers are only read if PR[qp] is true. Since the state of PR[qp]
7061 cannot statically be determined, all source registers are marked used.
7062 12) This insn only reads the specified predicate register when that
7063 register is the PR[qp].
7064 13) This reference to ld-c only applies to teh GR whose value is loaded
7065 with data returned from memory, not the post-incremented address register.
7066 14) The RSE resource includes the implementation-specific RSE internal
7067 state resources. At least one (and possibly more) of these resources are
7068 read by each instruction listed in IC:rse-readers. At least one (and
7069 possibly more) of these resources are written by each insn listed in
7071 15+16) Represents reserved instructions, which the assembler does not
7074 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7075 this code; there are no dependency violations based on memory access.
7078 #define MAX_SPECS 256
7083 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7084 const struct ia64_dependency
*dep
;
7085 struct ia64_opcode
*idesc
;
7086 int type
; /* is this a DV chk or a DV reg? */
7087 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7088 int note
; /* resource note for this insn's usage */
7089 int path
; /* which execution path to examine */
7096 if (dep
->mode
== IA64_DV_WAW
7097 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7098 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7101 /* template for any resources we identify */
7102 tmpl
.dependency
= dep
;
7104 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7105 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7106 tmpl
.link_to_qp_branch
= 1;
7107 tmpl
.mem_offset
.hint
= 0;
7110 tmpl
.cmp_type
= CMP_NONE
;
7113 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7114 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7115 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7117 /* we don't need to track these */
7118 if (dep
->semantics
== IA64_DVS_NONE
)
7121 switch (dep
->specifier
)
7126 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7128 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7129 if (regno
>= 0 && regno
<= 7)
7131 specs
[count
] = tmpl
;
7132 specs
[count
++].index
= regno
;
7138 for (i
= 0; i
< 8; i
++)
7140 specs
[count
] = tmpl
;
7141 specs
[count
++].index
= i
;
7150 case IA64_RS_AR_UNAT
:
7151 /* This is a mov =AR or mov AR= instruction. */
7152 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7154 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7155 if (regno
== AR_UNAT
)
7157 specs
[count
++] = tmpl
;
7162 /* This is a spill/fill, or other instruction that modifies the
7165 /* Unless we can determine the specific bits used, mark the whole
7166 thing; bits 8:3 of the memory address indicate the bit used in
7167 UNAT. The .mem.offset hint may be used to eliminate a small
7168 subset of conflicts. */
7169 specs
[count
] = tmpl
;
7170 if (md
.mem_offset
.hint
)
7173 fprintf (stderr
, " Using hint for spill/fill\n");
7174 /* The index isn't actually used, just set it to something
7175 approximating the bit index. */
7176 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7177 specs
[count
].mem_offset
.hint
= 1;
7178 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7179 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7183 specs
[count
++].specific
= 0;
7191 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7193 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7194 if ((regno
>= 8 && regno
<= 15)
7195 || (regno
>= 20 && regno
<= 23)
7196 || (regno
>= 31 && regno
<= 39)
7197 || (regno
>= 41 && regno
<= 47)
7198 || (regno
>= 67 && regno
<= 111))
7200 specs
[count
] = tmpl
;
7201 specs
[count
++].index
= regno
;
7214 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7216 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7217 if ((regno
>= 48 && regno
<= 63)
7218 || (regno
>= 112 && regno
<= 127))
7220 specs
[count
] = tmpl
;
7221 specs
[count
++].index
= regno
;
7227 for (i
= 48; i
< 64; i
++)
7229 specs
[count
] = tmpl
;
7230 specs
[count
++].index
= i
;
7232 for (i
= 112; i
< 128; i
++)
7234 specs
[count
] = tmpl
;
7235 specs
[count
++].index
= i
;
7253 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7254 if (idesc
->operands
[i
] == IA64_OPND_B1
7255 || idesc
->operands
[i
] == IA64_OPND_B2
)
7257 specs
[count
] = tmpl
;
7258 specs
[count
++].index
=
7259 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7264 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7265 if (idesc
->operands
[i
] == IA64_OPND_B1
7266 || idesc
->operands
[i
] == IA64_OPND_B2
)
7268 specs
[count
] = tmpl
;
7269 specs
[count
++].index
=
7270 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7276 case IA64_RS_CPUID
: /* four or more registers */
7279 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7281 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7282 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7285 specs
[count
] = tmpl
;
7286 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7290 specs
[count
] = tmpl
;
7291 specs
[count
++].specific
= 0;
7301 case IA64_RS_DBR
: /* four or more registers */
7304 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7306 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7307 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7310 specs
[count
] = tmpl
;
7311 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7315 specs
[count
] = tmpl
;
7316 specs
[count
++].specific
= 0;
7320 else if (note
== 0 && !rsrc_write
)
7322 specs
[count
] = tmpl
;
7323 specs
[count
++].specific
= 0;
7331 case IA64_RS_IBR
: /* four or more registers */
7334 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7336 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7337 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7340 specs
[count
] = tmpl
;
7341 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7345 specs
[count
] = tmpl
;
7346 specs
[count
++].specific
= 0;
7359 /* These are implementation specific. Force all references to
7360 conflict with all other references. */
7361 specs
[count
] = tmpl
;
7362 specs
[count
++].specific
= 0;
7370 case IA64_RS_PKR
: /* 16 or more registers */
7371 if (note
== 3 || note
== 4)
7373 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7375 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7376 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7381 specs
[count
] = tmpl
;
7382 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7385 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7387 /* Uses all registers *except* the one in R3. */
7388 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7390 specs
[count
] = tmpl
;
7391 specs
[count
++].index
= i
;
7397 specs
[count
] = tmpl
;
7398 specs
[count
++].specific
= 0;
7405 specs
[count
] = tmpl
;
7406 specs
[count
++].specific
= 0;
7410 case IA64_RS_PMC
: /* four or more registers */
7413 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7414 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7417 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7419 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7420 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7423 specs
[count
] = tmpl
;
7424 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7428 specs
[count
] = tmpl
;
7429 specs
[count
++].specific
= 0;
7439 case IA64_RS_PMD
: /* four or more registers */
7442 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7444 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7445 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7448 specs
[count
] = tmpl
;
7449 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7453 specs
[count
] = tmpl
;
7454 specs
[count
++].specific
= 0;
7464 case IA64_RS_RR
: /* eight registers */
7467 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7469 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7470 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7473 specs
[count
] = tmpl
;
7474 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7478 specs
[count
] = tmpl
;
7479 specs
[count
++].specific
= 0;
7483 else if (note
== 0 && !rsrc_write
)
7485 specs
[count
] = tmpl
;
7486 specs
[count
++].specific
= 0;
7494 case IA64_RS_CR_IRR
:
7497 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7498 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7500 && idesc
->operands
[1] == IA64_OPND_CR3
7503 for (i
= 0; i
< 4; i
++)
7505 specs
[count
] = tmpl
;
7506 specs
[count
++].index
= CR_IRR0
+ i
;
7512 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7513 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7515 && regno
<= CR_IRR3
)
7517 specs
[count
] = tmpl
;
7518 specs
[count
++].index
= regno
;
7527 case IA64_RS_CR_LRR
:
7534 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7535 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7536 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7538 specs
[count
] = tmpl
;
7539 specs
[count
++].index
= regno
;
7547 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7549 specs
[count
] = tmpl
;
7550 specs
[count
++].index
=
7551 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7566 else if (rsrc_write
)
7568 if (dep
->specifier
== IA64_RS_FRb
7569 && idesc
->operands
[0] == IA64_OPND_F1
)
7571 specs
[count
] = tmpl
;
7572 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7577 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7579 if (idesc
->operands
[i
] == IA64_OPND_F2
7580 || idesc
->operands
[i
] == IA64_OPND_F3
7581 || idesc
->operands
[i
] == IA64_OPND_F4
)
7583 specs
[count
] = tmpl
;
7584 specs
[count
++].index
=
7585 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7594 /* This reference applies only to the GR whose value is loaded with
7595 data returned from memory. */
7596 specs
[count
] = tmpl
;
7597 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7603 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7604 if (idesc
->operands
[i
] == IA64_OPND_R1
7605 || idesc
->operands
[i
] == IA64_OPND_R2
7606 || idesc
->operands
[i
] == IA64_OPND_R3
)
7608 specs
[count
] = tmpl
;
7609 specs
[count
++].index
=
7610 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7612 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7613 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7614 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7616 specs
[count
] = tmpl
;
7617 specs
[count
++].index
=
7618 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7623 /* Look for anything that reads a GR. */
7624 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7626 if (idesc
->operands
[i
] == IA64_OPND_MR3
7627 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7628 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7629 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7630 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7631 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7632 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7633 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7634 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7635 || ((i
>= idesc
->num_outputs
)
7636 && (idesc
->operands
[i
] == IA64_OPND_R1
7637 || idesc
->operands
[i
] == IA64_OPND_R2
7638 || idesc
->operands
[i
] == IA64_OPND_R3
7639 /* addl source register. */
7640 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7642 specs
[count
] = tmpl
;
7643 specs
[count
++].index
=
7644 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7655 /* This is the same as IA64_RS_PRr, except that the register range is
7656 from 1 - 15, and there are no rotating register reads/writes here. */
7660 for (i
= 1; i
< 16; i
++)
7662 specs
[count
] = tmpl
;
7663 specs
[count
++].index
= i
;
7669 /* Mark only those registers indicated by the mask. */
7672 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7673 for (i
= 1; i
< 16; i
++)
7674 if (mask
& ((valueT
) 1 << i
))
7676 specs
[count
] = tmpl
;
7677 specs
[count
++].index
= i
;
7685 else if (note
== 11) /* note 11 implies note 1 as well */
7689 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7691 if (idesc
->operands
[i
] == IA64_OPND_P1
7692 || idesc
->operands
[i
] == IA64_OPND_P2
)
7694 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7695 if (regno
>= 1 && regno
< 16)
7697 specs
[count
] = tmpl
;
7698 specs
[count
++].index
= regno
;
7708 else if (note
== 12)
7710 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7712 specs
[count
] = tmpl
;
7713 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7720 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7721 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7722 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7723 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7725 if ((idesc
->operands
[0] == IA64_OPND_P1
7726 || idesc
->operands
[0] == IA64_OPND_P2
)
7727 && p1
>= 1 && p1
< 16)
7729 specs
[count
] = tmpl
;
7730 specs
[count
].cmp_type
=
7731 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7732 specs
[count
++].index
= p1
;
7734 if ((idesc
->operands
[1] == IA64_OPND_P1
7735 || idesc
->operands
[1] == IA64_OPND_P2
)
7736 && p2
>= 1 && p2
< 16)
7738 specs
[count
] = tmpl
;
7739 specs
[count
].cmp_type
=
7740 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7741 specs
[count
++].index
= p2
;
7746 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7748 specs
[count
] = tmpl
;
7749 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7751 if (idesc
->operands
[1] == IA64_OPND_PR
)
7753 for (i
= 1; i
< 16; i
++)
7755 specs
[count
] = tmpl
;
7756 specs
[count
++].index
= i
;
7767 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7768 simplified cases of this. */
7772 for (i
= 16; i
< 63; i
++)
7774 specs
[count
] = tmpl
;
7775 specs
[count
++].index
= i
;
7781 /* Mark only those registers indicated by the mask. */
7783 && idesc
->operands
[0] == IA64_OPND_PR
)
7785 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7786 if (mask
& ((valueT
) 1<<16))
7787 for (i
= 16; i
< 63; i
++)
7789 specs
[count
] = tmpl
;
7790 specs
[count
++].index
= i
;
7794 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7796 for (i
= 16; i
< 63; i
++)
7798 specs
[count
] = tmpl
;
7799 specs
[count
++].index
= i
;
7807 else if (note
== 11) /* note 11 implies note 1 as well */
7811 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7813 if (idesc
->operands
[i
] == IA64_OPND_P1
7814 || idesc
->operands
[i
] == IA64_OPND_P2
)
7816 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7817 if (regno
>= 16 && regno
< 63)
7819 specs
[count
] = tmpl
;
7820 specs
[count
++].index
= regno
;
7830 else if (note
== 12)
7832 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7834 specs
[count
] = tmpl
;
7835 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7842 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7843 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7844 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7845 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7847 if ((idesc
->operands
[0] == IA64_OPND_P1
7848 || idesc
->operands
[0] == IA64_OPND_P2
)
7849 && p1
>= 16 && p1
< 63)
7851 specs
[count
] = tmpl
;
7852 specs
[count
].cmp_type
=
7853 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7854 specs
[count
++].index
= p1
;
7856 if ((idesc
->operands
[1] == IA64_OPND_P1
7857 || idesc
->operands
[1] == IA64_OPND_P2
)
7858 && p2
>= 16 && p2
< 63)
7860 specs
[count
] = tmpl
;
7861 specs
[count
].cmp_type
=
7862 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7863 specs
[count
++].index
= p2
;
7868 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7870 specs
[count
] = tmpl
;
7871 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7873 if (idesc
->operands
[1] == IA64_OPND_PR
)
7875 for (i
= 16; i
< 63; i
++)
7877 specs
[count
] = tmpl
;
7878 specs
[count
++].index
= i
;
7890 /* Verify that the instruction is using the PSR bit indicated in
7894 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7896 if (dep
->regindex
< 6)
7898 specs
[count
++] = tmpl
;
7901 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7903 if (dep
->regindex
< 32
7904 || dep
->regindex
== 35
7905 || dep
->regindex
== 36
7906 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7908 specs
[count
++] = tmpl
;
7911 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7913 if (dep
->regindex
< 32
7914 || dep
->regindex
== 35
7915 || dep
->regindex
== 36
7916 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7918 specs
[count
++] = tmpl
;
7923 /* Several PSR bits have very specific dependencies. */
7924 switch (dep
->regindex
)
7927 specs
[count
++] = tmpl
;
7932 specs
[count
++] = tmpl
;
7936 /* Only certain CR accesses use PSR.ic */
7937 if (idesc
->operands
[0] == IA64_OPND_CR3
7938 || idesc
->operands
[1] == IA64_OPND_CR3
)
7941 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7944 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7959 specs
[count
++] = tmpl
;
7968 specs
[count
++] = tmpl
;
7972 /* Only some AR accesses use cpl */
7973 if (idesc
->operands
[0] == IA64_OPND_AR3
7974 || idesc
->operands
[1] == IA64_OPND_AR3
)
7977 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7980 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7987 && regno
<= AR_K7
))))
7989 specs
[count
++] = tmpl
;
7994 specs
[count
++] = tmpl
;
8004 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8006 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8012 if (mask
& ((valueT
) 1 << dep
->regindex
))
8014 specs
[count
++] = tmpl
;
8019 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8020 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8021 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8022 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8024 if (idesc
->operands
[i
] == IA64_OPND_F1
8025 || idesc
->operands
[i
] == IA64_OPND_F2
8026 || idesc
->operands
[i
] == IA64_OPND_F3
8027 || idesc
->operands
[i
] == IA64_OPND_F4
)
8029 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8030 if (reg
>= min
&& reg
<= max
)
8032 specs
[count
++] = tmpl
;
8039 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8040 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8041 /* mfh is read on writes to FR32-127; mfl is read on writes to
8043 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8045 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8047 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8048 if (reg
>= min
&& reg
<= max
)
8050 specs
[count
++] = tmpl
;
8055 else if (note
== 10)
8057 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8059 if (idesc
->operands
[i
] == IA64_OPND_R1
8060 || idesc
->operands
[i
] == IA64_OPND_R2
8061 || idesc
->operands
[i
] == IA64_OPND_R3
)
8063 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8064 if (regno
>= 16 && regno
<= 31)
8066 specs
[count
++] = tmpl
;
8077 case IA64_RS_AR_FPSR
:
8078 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8080 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8081 if (regno
== AR_FPSR
)
8083 specs
[count
++] = tmpl
;
8088 specs
[count
++] = tmpl
;
8093 /* Handle all AR[REG] resources */
8094 if (note
== 0 || note
== 1)
8096 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8097 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8098 && regno
== dep
->regindex
)
8100 specs
[count
++] = tmpl
;
8102 /* other AR[REG] resources may be affected by AR accesses */
8103 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8106 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8107 switch (dep
->regindex
)
8113 if (regno
== AR_BSPSTORE
)
8115 specs
[count
++] = tmpl
;
8119 (regno
== AR_BSPSTORE
8120 || regno
== AR_RNAT
))
8122 specs
[count
++] = tmpl
;
8127 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8130 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8131 switch (dep
->regindex
)
8136 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8138 specs
[count
++] = tmpl
;
8145 specs
[count
++] = tmpl
;
8155 /* Handle all CR[REG] resources */
8156 if (note
== 0 || note
== 1)
8158 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8160 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8161 if (regno
== dep
->regindex
)
8163 specs
[count
++] = tmpl
;
8165 else if (!rsrc_write
)
8167 /* Reads from CR[IVR] affect other resources. */
8168 if (regno
== CR_IVR
)
8170 if ((dep
->regindex
>= CR_IRR0
8171 && dep
->regindex
<= CR_IRR3
)
8172 || dep
->regindex
== CR_TPR
)
8174 specs
[count
++] = tmpl
;
8181 specs
[count
++] = tmpl
;
8190 case IA64_RS_INSERVICE
:
8191 /* look for write of EOI (67) or read of IVR (65) */
8192 if ((idesc
->operands
[0] == IA64_OPND_CR3
8193 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8194 || (idesc
->operands
[1] == IA64_OPND_CR3
8195 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8197 specs
[count
++] = tmpl
;
8204 specs
[count
++] = tmpl
;
8215 specs
[count
++] = tmpl
;
8219 /* Check if any of the registers accessed are in the rotating region.
8220 mov to/from pr accesses CFM only when qp_regno is in the rotating
8222 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8224 if (idesc
->operands
[i
] == IA64_OPND_R1
8225 || idesc
->operands
[i
] == IA64_OPND_R2
8226 || idesc
->operands
[i
] == IA64_OPND_R3
)
8228 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8229 /* Assumes that md.rot.num_regs is always valid */
8230 if (md
.rot
.num_regs
> 0
8232 && num
< 31 + md
.rot
.num_regs
)
8234 specs
[count
] = tmpl
;
8235 specs
[count
++].specific
= 0;
8238 else if (idesc
->operands
[i
] == IA64_OPND_F1
8239 || idesc
->operands
[i
] == IA64_OPND_F2
8240 || idesc
->operands
[i
] == IA64_OPND_F3
8241 || idesc
->operands
[i
] == IA64_OPND_F4
)
8243 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8246 specs
[count
] = tmpl
;
8247 specs
[count
++].specific
= 0;
8250 else if (idesc
->operands
[i
] == IA64_OPND_P1
8251 || idesc
->operands
[i
] == IA64_OPND_P2
)
8253 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8256 specs
[count
] = tmpl
;
8257 specs
[count
++].specific
= 0;
8261 if (CURR_SLOT
.qp_regno
> 15)
8263 specs
[count
] = tmpl
;
8264 specs
[count
++].specific
= 0;
8269 /* This is the same as IA64_RS_PRr, except simplified to account for
8270 the fact that there is only one register. */
8274 specs
[count
++] = tmpl
;
8279 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8280 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8281 if (mask
& ((valueT
) 1 << 63))
8282 specs
[count
++] = tmpl
;
8284 else if (note
== 11)
8286 if ((idesc
->operands
[0] == IA64_OPND_P1
8287 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8288 || (idesc
->operands
[1] == IA64_OPND_P2
8289 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8291 specs
[count
++] = tmpl
;
8294 else if (note
== 12)
8296 if (CURR_SLOT
.qp_regno
== 63)
8298 specs
[count
++] = tmpl
;
8305 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8306 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8307 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8308 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8311 && (idesc
->operands
[0] == IA64_OPND_P1
8312 || idesc
->operands
[0] == IA64_OPND_P2
))
8314 specs
[count
] = tmpl
;
8315 specs
[count
++].cmp_type
=
8316 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8319 && (idesc
->operands
[1] == IA64_OPND_P1
8320 || idesc
->operands
[1] == IA64_OPND_P2
))
8322 specs
[count
] = tmpl
;
8323 specs
[count
++].cmp_type
=
8324 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8329 if (CURR_SLOT
.qp_regno
== 63)
8331 specs
[count
++] = tmpl
;
8342 /* FIXME we can identify some individual RSE written resources, but RSE
8343 read resources have not yet been completely identified, so for now
8344 treat RSE as a single resource */
8345 if (strncmp (idesc
->name
, "mov", 3) == 0)
8349 if (idesc
->operands
[0] == IA64_OPND_AR3
8350 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8352 specs
[count
] = tmpl
;
8353 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8358 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8360 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8361 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8363 specs
[count
++] = tmpl
;
8366 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8368 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8369 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8370 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8372 specs
[count
++] = tmpl
;
8379 specs
[count
++] = tmpl
;
8384 /* FIXME -- do any of these need to be non-specific? */
8385 specs
[count
++] = tmpl
;
8389 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8396 /* Clear branch flags on marked resources. This breaks the link between the
8397 QP of the marking instruction and a subsequent branch on the same QP. */
8400 clear_qp_branch_flag (mask
)
8404 for (i
= 0; i
< regdepslen
; i
++)
8406 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8407 if ((bit
& mask
) != 0)
8409 regdeps
[i
].link_to_qp_branch
= 0;
8414 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8416 Any changes to a PR clears the mutex relations which include that PR. */
8419 clear_qp_mutex (mask
)
8425 while (i
< qp_mutexeslen
)
8427 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8431 fprintf (stderr
, " Clearing mutex relation");
8432 print_prmask (qp_mutexes
[i
].prmask
);
8433 fprintf (stderr
, "\n");
8435 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8442 /* Clear implies relations which contain PRs in the given masks.
8443 P1_MASK indicates the source of the implies relation, while P2_MASK
8444 indicates the implied PR. */
8447 clear_qp_implies (p1_mask
, p2_mask
)
8454 while (i
< qp_implieslen
)
8456 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8457 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8460 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8461 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8462 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8469 /* Add the PRs specified to the list of implied relations. */
8472 add_qp_imply (p1
, p2
)
8479 /* p0 is not meaningful here. */
8480 if (p1
== 0 || p2
== 0)
8486 /* If it exists already, ignore it. */
8487 for (i
= 0; i
< qp_implieslen
; i
++)
8489 if (qp_implies
[i
].p1
== p1
8490 && qp_implies
[i
].p2
== p2
8491 && qp_implies
[i
].path
== md
.path
8492 && !qp_implies
[i
].p2_branched
)
8496 if (qp_implieslen
== qp_impliestotlen
)
8498 qp_impliestotlen
+= 20;
8499 qp_implies
= (struct qp_imply
*)
8500 xrealloc ((void *) qp_implies
,
8501 qp_impliestotlen
* sizeof (struct qp_imply
));
8504 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8505 qp_implies
[qp_implieslen
].p1
= p1
;
8506 qp_implies
[qp_implieslen
].p2
= p2
;
8507 qp_implies
[qp_implieslen
].path
= md
.path
;
8508 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8510 /* Add in the implied transitive relations; for everything that p2 implies,
8511 make p1 imply that, too; for everything that implies p1, make it imply p2
8513 for (i
= 0; i
< qp_implieslen
; i
++)
8515 if (qp_implies
[i
].p1
== p2
)
8516 add_qp_imply (p1
, qp_implies
[i
].p2
);
8517 if (qp_implies
[i
].p2
== p1
)
8518 add_qp_imply (qp_implies
[i
].p1
, p2
);
8520 /* Add in mutex relations implied by this implies relation; for each mutex
8521 relation containing p2, duplicate it and replace p2 with p1. */
8522 bit
= (valueT
) 1 << p1
;
8523 mask
= (valueT
) 1 << p2
;
8524 for (i
= 0; i
< qp_mutexeslen
; i
++)
8526 if (qp_mutexes
[i
].prmask
& mask
)
8527 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8531 /* Add the PRs specified in the mask to the mutex list; this means that only
8532 one of the PRs can be true at any time. PR0 should never be included in
8542 if (qp_mutexeslen
== qp_mutexestotlen
)
8544 qp_mutexestotlen
+= 20;
8545 qp_mutexes
= (struct qpmutex
*)
8546 xrealloc ((void *) qp_mutexes
,
8547 qp_mutexestotlen
* sizeof (struct qpmutex
));
8551 fprintf (stderr
, " Registering mutex on");
8552 print_prmask (mask
);
8553 fprintf (stderr
, "\n");
8555 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8556 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8560 clear_register_values ()
8564 fprintf (stderr
, " Clearing register values\n");
8565 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8566 gr_values
[i
].known
= 0;
8569 /* Keep track of register values/changes which affect DV tracking.
8571 optimization note: should add a flag to classes of insns where otherwise we
8572 have to examine a group of strings to identify them. */
8575 note_register_values (idesc
)
8576 struct ia64_opcode
*idesc
;
8578 valueT qp_changemask
= 0;
8581 /* Invalidate values for registers being written to. */
8582 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8584 if (idesc
->operands
[i
] == IA64_OPND_R1
8585 || idesc
->operands
[i
] == IA64_OPND_R2
8586 || idesc
->operands
[i
] == IA64_OPND_R3
)
8588 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8589 if (regno
> 0 && regno
< NELEMS (gr_values
))
8590 gr_values
[regno
].known
= 0;
8592 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8594 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8595 if (regno
> 0 && regno
< 4)
8596 gr_values
[regno
].known
= 0;
8598 else if (idesc
->operands
[i
] == IA64_OPND_P1
8599 || idesc
->operands
[i
] == IA64_OPND_P2
)
8601 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8602 qp_changemask
|= (valueT
) 1 << regno
;
8604 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8606 if (idesc
->operands
[2] & (valueT
) 0x10000)
8607 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8609 qp_changemask
= idesc
->operands
[2];
8612 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8614 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8615 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8617 qp_changemask
= idesc
->operands
[1];
8618 qp_changemask
&= ~(valueT
) 0xFFFF;
8623 /* Always clear qp branch flags on any PR change. */
8624 /* FIXME there may be exceptions for certain compares. */
8625 clear_qp_branch_flag (qp_changemask
);
8627 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8628 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8630 qp_changemask
|= ~(valueT
) 0xFFFF;
8631 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8633 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8634 gr_values
[i
].known
= 0;
8636 clear_qp_mutex (qp_changemask
);
8637 clear_qp_implies (qp_changemask
, qp_changemask
);
8639 /* After a call, all register values are undefined, except those marked
8641 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8642 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8644 /* FIXME keep GR values which are marked as "safe_across_calls" */
8645 clear_register_values ();
8646 clear_qp_mutex (~qp_safe_across_calls
);
8647 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8648 clear_qp_branch_flag (~qp_safe_across_calls
);
8650 else if (is_interruption_or_rfi (idesc
)
8651 || is_taken_branch (idesc
))
8653 clear_register_values ();
8654 clear_qp_mutex (~(valueT
) 0);
8655 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8657 /* Look for mutex and implies relations. */
8658 else if ((idesc
->operands
[0] == IA64_OPND_P1
8659 || idesc
->operands
[0] == IA64_OPND_P2
)
8660 && (idesc
->operands
[1] == IA64_OPND_P1
8661 || idesc
->operands
[1] == IA64_OPND_P2
))
8663 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8664 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8665 valueT p1mask
= (valueT
) 1 << p1
;
8666 valueT p2mask
= (valueT
) 1 << p2
;
8668 /* If one of the PRs is PR0, we can't really do anything. */
8669 if (p1
== 0 || p2
== 0)
8672 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8674 /* In general, clear mutexes and implies which include P1 or P2,
8675 with the following exceptions. */
8676 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8678 add_qp_mutex (p1mask
| p2mask
);
8679 clear_qp_implies (p2mask
, p1mask
);
8681 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8683 add_qp_mutex (p1mask
| p2mask
);
8684 clear_qp_implies (p1mask
, p2mask
);
8686 else if (strstr (idesc
->name
, ".and") != NULL
)
8688 clear_qp_implies (0, p1mask
| p2mask
);
8690 else if (strstr (idesc
->name
, ".or") != NULL
)
8692 clear_qp_mutex (p1mask
| p2mask
);
8693 clear_qp_implies (p1mask
| p2mask
, 0);
8697 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8698 if (strstr (idesc
->name
, ".unc") != NULL
)
8700 add_qp_mutex (p1mask
| p2mask
);
8701 if (CURR_SLOT
.qp_regno
!= 0)
8703 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8704 CURR_SLOT
.qp_regno
);
8705 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8706 CURR_SLOT
.qp_regno
);
8709 else if (CURR_SLOT
.qp_regno
== 0)
8711 add_qp_mutex (p1mask
| p2mask
);
8715 clear_qp_mutex (p1mask
| p2mask
);
8719 /* Look for mov imm insns into GRs. */
8720 else if (idesc
->operands
[0] == IA64_OPND_R1
8721 && (idesc
->operands
[1] == IA64_OPND_IMM22
8722 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8723 && (strcmp (idesc
->name
, "mov") == 0
8724 || strcmp (idesc
->name
, "movl") == 0))
8726 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8727 if (regno
> 0 && regno
< NELEMS (gr_values
))
8729 gr_values
[regno
].known
= 1;
8730 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8731 gr_values
[regno
].path
= md
.path
;
8734 fprintf (stderr
, " Know gr%d = ", regno
);
8735 fprintf_vma (stderr
, gr_values
[regno
].value
);
8736 fputs ("\n", stderr
);
8742 clear_qp_mutex (qp_changemask
);
8743 clear_qp_implies (qp_changemask
, qp_changemask
);
8747 /* Return whether the given predicate registers are currently mutex. */
8750 qp_mutex (p1
, p2
, path
)
8760 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8761 for (i
= 0; i
< qp_mutexeslen
; i
++)
8763 if (qp_mutexes
[i
].path
>= path
8764 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8771 /* Return whether the given resource is in the given insn's list of chks
8772 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8776 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8778 struct ia64_opcode
*idesc
;
8783 struct rsrc specs
[MAX_SPECS
];
8786 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8787 we don't need to check. One exception is note 11, which indicates that
8788 target predicates are written regardless of PR[qp]. */
8789 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8793 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8796 /* UNAT checking is a bit more specific than other resources */
8797 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8798 && specs
[count
].mem_offset
.hint
8799 && rs
->mem_offset
.hint
)
8801 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8803 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8804 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8811 /* Skip apparent PR write conflicts where both writes are an AND or both
8812 writes are an OR. */
8813 if (rs
->dependency
->specifier
== IA64_RS_PR
8814 || rs
->dependency
->specifier
== IA64_RS_PRr
8815 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8817 if (specs
[count
].cmp_type
!= CMP_NONE
8818 && specs
[count
].cmp_type
== rs
->cmp_type
)
8821 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8822 dv_mode
[rs
->dependency
->mode
],
8823 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8824 specs
[count
].index
: 63);
8829 " %s on parallel compare conflict %s vs %s on PR%d\n",
8830 dv_mode
[rs
->dependency
->mode
],
8831 dv_cmp_type
[rs
->cmp_type
],
8832 dv_cmp_type
[specs
[count
].cmp_type
],
8833 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8834 specs
[count
].index
: 63);
8838 /* If either resource is not specific, conservatively assume a conflict
8840 if (!specs
[count
].specific
|| !rs
->specific
)
8842 else if (specs
[count
].index
== rs
->index
)
8847 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8853 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8854 insert a stop to create the break. Update all resource dependencies
8855 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8856 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8857 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8861 insn_group_break (insert_stop
, qp_regno
, save_current
)
8868 if (insert_stop
&& md
.num_slots_in_use
> 0)
8869 PREV_SLOT
.end_of_insn_group
= 1;
8873 fprintf (stderr
, " Insn group break%s",
8874 (insert_stop
? " (w/stop)" : ""));
8876 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8877 fprintf (stderr
, "\n");
8881 while (i
< regdepslen
)
8883 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8886 && regdeps
[i
].qp_regno
!= qp_regno
)
8893 && CURR_SLOT
.src_file
== regdeps
[i
].file
8894 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8900 /* clear dependencies which are automatically cleared by a stop, or
8901 those that have reached the appropriate state of insn serialization */
8902 if (dep
->semantics
== IA64_DVS_IMPLIED
8903 || dep
->semantics
== IA64_DVS_IMPLIEDF
8904 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8906 print_dependency ("Removing", i
);
8907 regdeps
[i
] = regdeps
[--regdepslen
];
8911 if (dep
->semantics
== IA64_DVS_DATA
8912 || dep
->semantics
== IA64_DVS_INSTR
8913 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8915 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8916 regdeps
[i
].insn_srlz
= STATE_STOP
;
8917 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8918 regdeps
[i
].data_srlz
= STATE_STOP
;
8925 /* Add the given resource usage spec to the list of active dependencies. */
8928 mark_resource (idesc
, dep
, spec
, depind
, path
)
8929 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8930 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8935 if (regdepslen
== regdepstotlen
)
8937 regdepstotlen
+= 20;
8938 regdeps
= (struct rsrc
*)
8939 xrealloc ((void *) regdeps
,
8940 regdepstotlen
* sizeof (struct rsrc
));
8943 regdeps
[regdepslen
] = *spec
;
8944 regdeps
[regdepslen
].depind
= depind
;
8945 regdeps
[regdepslen
].path
= path
;
8946 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8947 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8949 print_dependency ("Adding", regdepslen
);
8955 print_dependency (action
, depind
)
8961 fprintf (stderr
, " %s %s '%s'",
8962 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8963 (regdeps
[depind
].dependency
)->name
);
8964 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8965 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8966 if (regdeps
[depind
].mem_offset
.hint
)
8968 fputs (" ", stderr
);
8969 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
8970 fputs ("+", stderr
);
8971 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
8973 fprintf (stderr
, "\n");
8978 instruction_serialization ()
8982 fprintf (stderr
, " Instruction serialization\n");
8983 for (i
= 0; i
< regdepslen
; i
++)
8984 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8985 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8989 data_serialization ()
8993 fprintf (stderr
, " Data serialization\n");
8994 while (i
< regdepslen
)
8996 if (regdeps
[i
].data_srlz
== STATE_STOP
8997 /* Note: as of 991210, all "other" dependencies are cleared by a
8998 data serialization. This might change with new tables */
8999 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9001 print_dependency ("Removing", i
);
9002 regdeps
[i
] = regdeps
[--regdepslen
];
9009 /* Insert stops and serializations as needed to avoid DVs. */
9012 remove_marked_resource (rs
)
9015 switch (rs
->dependency
->semantics
)
9017 case IA64_DVS_SPECIFIC
:
9019 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9020 /* ...fall through... */
9021 case IA64_DVS_INSTR
:
9023 fprintf (stderr
, "Inserting instr serialization\n");
9024 if (rs
->insn_srlz
< STATE_STOP
)
9025 insn_group_break (1, 0, 0);
9026 if (rs
->insn_srlz
< STATE_SRLZ
)
9028 int oldqp
= CURR_SLOT
.qp_regno
;
9029 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9030 /* Manually jam a srlz.i insn into the stream */
9031 CURR_SLOT
.qp_regno
= 0;
9032 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9033 instruction_serialization ();
9034 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9035 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9037 CURR_SLOT
.qp_regno
= oldqp
;
9038 CURR_SLOT
.idesc
= oldidesc
;
9040 insn_group_break (1, 0, 0);
9042 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9043 "other" types of DV are eliminated
9044 by a data serialization */
9047 fprintf (stderr
, "Inserting data serialization\n");
9048 if (rs
->data_srlz
< STATE_STOP
)
9049 insn_group_break (1, 0, 0);
9051 int oldqp
= CURR_SLOT
.qp_regno
;
9052 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9053 /* Manually jam a srlz.d insn into the stream */
9054 CURR_SLOT
.qp_regno
= 0;
9055 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9056 data_serialization ();
9057 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9058 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9060 CURR_SLOT
.qp_regno
= oldqp
;
9061 CURR_SLOT
.idesc
= oldidesc
;
9064 case IA64_DVS_IMPLIED
:
9065 case IA64_DVS_IMPLIEDF
:
9067 fprintf (stderr
, "Inserting stop\n");
9068 insn_group_break (1, 0, 0);
9075 /* Check the resources used by the given opcode against the current dependency
9078 The check is run once for each execution path encountered. In this case,
9079 a unique execution path is the sequence of instructions following a code
9080 entry point, e.g. the following has three execution paths, one starting
9081 at L0, one at L1, and one at L2.
9090 check_dependencies (idesc
)
9091 struct ia64_opcode
*idesc
;
9093 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9097 /* Note that the number of marked resources may change within the
9098 loop if in auto mode. */
9100 while (i
< regdepslen
)
9102 struct rsrc
*rs
= ®deps
[i
];
9103 const struct ia64_dependency
*dep
= rs
->dependency
;
9108 if (dep
->semantics
== IA64_DVS_NONE
9109 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9115 note
= NOTE (opdeps
->chks
[chkind
]);
9117 /* Check this resource against each execution path seen thus far. */
9118 for (path
= 0; path
<= md
.path
; path
++)
9122 /* If the dependency wasn't on the path being checked, ignore it. */
9123 if (rs
->path
< path
)
9126 /* If the QP for this insn implies a QP which has branched, don't
9127 bother checking. Ed. NOTE: I don't think this check is terribly
9128 useful; what's the point of generating code which will only be
9129 reached if its QP is zero?
9130 This code was specifically inserted to handle the following code,
9131 based on notes from Intel's DV checking code, where p1 implies p2.
9137 if (CURR_SLOT
.qp_regno
!= 0)
9141 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9143 if (qp_implies
[implies
].path
>= path
9144 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9145 && qp_implies
[implies
].p2_branched
)
9155 if ((matchtype
= resources_match (rs
, idesc
, note
,
9156 CURR_SLOT
.qp_regno
, path
)) != 0)
9159 char pathmsg
[256] = "";
9160 char indexmsg
[256] = "";
9161 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9164 sprintf (pathmsg
, " when entry is at label '%s'",
9165 md
.entry_labels
[path
- 1]);
9166 if (rs
->specific
&& rs
->index
!= 0)
9167 sprintf (indexmsg
, ", specific resource number is %d",
9169 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9171 (certain
? "violates" : "may violate"),
9172 dv_mode
[dep
->mode
], dep
->name
,
9173 dv_sem
[dep
->semantics
],
9176 if (md
.explicit_mode
)
9178 as_warn ("%s", msg
);
9180 as_warn (_("Only the first path encountering the conflict "
9182 as_warn_where (rs
->file
, rs
->line
,
9183 _("This is the location of the "
9184 "conflicting usage"));
9185 /* Don't bother checking other paths, to avoid duplicating
9192 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9194 remove_marked_resource (rs
);
9196 /* since the set of dependencies has changed, start over */
9197 /* FIXME -- since we're removing dvs as we go, we
9198 probably don't really need to start over... */
9211 /* Register new dependencies based on the given opcode. */
9214 mark_resources (idesc
)
9215 struct ia64_opcode
*idesc
;
9218 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9219 int add_only_qp_reads
= 0;
9221 /* A conditional branch only uses its resources if it is taken; if it is
9222 taken, we stop following that path. The other branch types effectively
9223 *always* write their resources. If it's not taken, register only QP
9225 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9227 add_only_qp_reads
= 1;
9231 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9233 for (i
= 0; i
< opdeps
->nregs
; i
++)
9235 const struct ia64_dependency
*dep
;
9236 struct rsrc specs
[MAX_SPECS
];
9241 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9242 note
= NOTE (opdeps
->regs
[i
]);
9244 if (add_only_qp_reads
9245 && !(dep
->mode
== IA64_DV_WAR
9246 && (dep
->specifier
== IA64_RS_PR
9247 || dep
->specifier
== IA64_RS_PRr
9248 || dep
->specifier
== IA64_RS_PR63
)))
9251 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9254 if (md
.debug_dv
&& !count
)
9255 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9256 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9261 mark_resource (idesc
, dep
, &specs
[count
],
9262 DEP (opdeps
->regs
[i
]), md
.path
);
9265 /* The execution path may affect register values, which may in turn
9266 affect which indirect-access resources are accessed. */
9267 switch (dep
->specifier
)
9279 for (path
= 0; path
< md
.path
; path
++)
9281 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9283 mark_resource (idesc
, dep
, &specs
[count
],
9284 DEP (opdeps
->regs
[i
]), path
);
9291 /* Remove dependencies when they no longer apply. */
9294 update_dependencies (idesc
)
9295 struct ia64_opcode
*idesc
;
9299 if (strcmp (idesc
->name
, "srlz.i") == 0)
9301 instruction_serialization ();
9303 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9305 data_serialization ();
9307 else if (is_interruption_or_rfi (idesc
)
9308 || is_taken_branch (idesc
))
9310 /* Although technically the taken branch doesn't clear dependencies
9311 which require a srlz.[id], we don't follow the branch; the next
9312 instruction is assumed to start with a clean slate. */
9316 else if (is_conditional_branch (idesc
)
9317 && CURR_SLOT
.qp_regno
!= 0)
9319 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9321 for (i
= 0; i
< qp_implieslen
; i
++)
9323 /* If the conditional branch's predicate is implied by the predicate
9324 in an existing dependency, remove that dependency. */
9325 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9328 /* Note that this implied predicate takes a branch so that if
9329 a later insn generates a DV but its predicate implies this
9330 one, we can avoid the false DV warning. */
9331 qp_implies
[i
].p2_branched
= 1;
9332 while (depind
< regdepslen
)
9334 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9336 print_dependency ("Removing", depind
);
9337 regdeps
[depind
] = regdeps
[--regdepslen
];
9344 /* Any marked resources which have this same predicate should be
9345 cleared, provided that the QP hasn't been modified between the
9346 marking instruction and the branch. */
9349 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9354 while (i
< regdepslen
)
9356 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9357 && regdeps
[i
].link_to_qp_branch
9358 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9359 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9361 /* Treat like a taken branch */
9362 print_dependency ("Removing", i
);
9363 regdeps
[i
] = regdeps
[--regdepslen
];
9372 /* Examine the current instruction for dependency violations. */
9376 struct ia64_opcode
*idesc
;
9380 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9381 idesc
->name
, CURR_SLOT
.src_line
,
9382 idesc
->dependencies
->nchks
,
9383 idesc
->dependencies
->nregs
);
9386 /* Look through the list of currently marked resources; if the current
9387 instruction has the dependency in its chks list which uses that resource,
9388 check against the specific resources used. */
9389 check_dependencies (idesc
);
9391 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9392 then add them to the list of marked resources. */
9393 mark_resources (idesc
);
9395 /* There are several types of dependency semantics, and each has its own
9396 requirements for being cleared
9398 Instruction serialization (insns separated by interruption, rfi, or
9399 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9401 Data serialization (instruction serialization, or writer + srlz.d +
9402 reader, where writer and srlz.d are in separate groups) clears
9403 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9404 always be the case).
9406 Instruction group break (groups separated by stop, taken branch,
9407 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9409 update_dependencies (idesc
);
9411 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9412 warning. Keep track of as many as possible that are useful. */
9413 note_register_values (idesc
);
9415 /* We don't need or want this anymore. */
9416 md
.mem_offset
.hint
= 0;
9421 /* Translate one line of assembly. Pseudo ops and labels do not show
9427 char *saved_input_line_pointer
, *mnemonic
;
9428 const struct pseudo_opcode
*pdesc
;
9429 struct ia64_opcode
*idesc
;
9430 unsigned char qp_regno
;
9434 saved_input_line_pointer
= input_line_pointer
;
9435 input_line_pointer
= str
;
9437 /* extract the opcode (mnemonic): */
9439 mnemonic
= input_line_pointer
;
9440 ch
= get_symbol_end ();
9441 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9444 *input_line_pointer
= ch
;
9445 (*pdesc
->handler
) (pdesc
->arg
);
9449 /* Find the instruction descriptor matching the arguments. */
9451 idesc
= ia64_find_opcode (mnemonic
);
9452 *input_line_pointer
= ch
;
9455 as_bad ("Unknown opcode `%s'", mnemonic
);
9459 idesc
= parse_operands (idesc
);
9463 /* Handle the dynamic ops we can handle now: */
9464 if (idesc
->type
== IA64_TYPE_DYN
)
9466 if (strcmp (idesc
->name
, "add") == 0)
9468 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9469 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9473 ia64_free_opcode (idesc
);
9474 idesc
= ia64_find_opcode (mnemonic
);
9476 know (!idesc
->next
);
9479 else if (strcmp (idesc
->name
, "mov") == 0)
9481 enum ia64_opnd opnd1
, opnd2
;
9484 opnd1
= idesc
->operands
[0];
9485 opnd2
= idesc
->operands
[1];
9486 if (opnd1
== IA64_OPND_AR3
)
9488 else if (opnd2
== IA64_OPND_AR3
)
9492 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9493 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9497 ia64_free_opcode (idesc
);
9498 idesc
= ia64_find_opcode (mnemonic
);
9499 while (idesc
!= NULL
9500 && (idesc
->operands
[0] != opnd1
9501 || idesc
->operands
[1] != opnd2
))
9502 idesc
= get_next_opcode (idesc
);
9507 if (md
.qp
.X_op
== O_register
)
9509 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9510 md
.qp
.X_op
= O_absent
;
9513 flags
= idesc
->flags
;
9515 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9516 insn_group_break (1, 0, 0);
9518 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9520 as_bad ("`%s' cannot be predicated", idesc
->name
);
9524 /* Build the instruction. */
9525 CURR_SLOT
.qp_regno
= qp_regno
;
9526 CURR_SLOT
.idesc
= idesc
;
9527 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9528 dwarf2_where (&CURR_SLOT
.debug_line
);
9530 /* Add unwind entry, if there is one. */
9531 if (unwind
.current_entry
)
9533 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9534 unwind
.current_entry
= NULL
;
9537 /* Check for dependency violations. */
9541 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9542 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9545 if ((flags
& IA64_OPCODE_LAST
) != 0)
9546 insn_group_break (1, 0, 0);
9548 md
.last_text_seg
= now_seg
;
9551 input_line_pointer
= saved_input_line_pointer
;
9554 /* Called when symbol NAME cannot be found in the symbol table.
9555 Should be used for dynamic valued symbols only. */
9558 md_undefined_symbol (name
)
9559 char *name ATTRIBUTE_UNUSED
;
9564 /* Called for any expression that can not be recognized. When the
9565 function is called, `input_line_pointer' will point to the start of
9572 enum pseudo_type pseudo_type
;
9577 switch (*input_line_pointer
)
9580 /* Find what relocation pseudo-function we're dealing with. */
9582 ch
= *++input_line_pointer
;
9583 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9584 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9586 len
= strlen (pseudo_func
[i
].name
);
9587 if (strncmp (pseudo_func
[i
].name
+ 1,
9588 input_line_pointer
+ 1, len
- 1) == 0
9589 && !is_part_of_name (input_line_pointer
[len
]))
9591 input_line_pointer
+= len
;
9592 pseudo_type
= pseudo_func
[i
].type
;
9596 switch (pseudo_type
)
9598 case PSEUDO_FUNC_RELOC
:
9600 if (*input_line_pointer
!= '(')
9602 as_bad ("Expected '('");
9606 ++input_line_pointer
;
9608 if (*input_line_pointer
++ != ')')
9610 as_bad ("Missing ')'");
9613 if (e
->X_op
!= O_symbol
)
9615 if (e
->X_op
!= O_pseudo_fixup
)
9617 as_bad ("Not a symbolic expression");
9620 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9621 && i
== FUNC_LT_RELATIVE
)
9622 i
= FUNC_LT_FPTR_RELATIVE
;
9625 as_bad ("Illegal combination of relocation functions");
9629 /* Make sure gas doesn't get rid of local symbols that are used
9631 e
->X_op
= O_pseudo_fixup
;
9632 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9635 case PSEUDO_FUNC_CONST
:
9636 e
->X_op
= O_constant
;
9637 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9640 case PSEUDO_FUNC_REG
:
9641 e
->X_op
= O_register
;
9642 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9646 name
= input_line_pointer
- 1;
9648 as_bad ("Unknown pseudo function `%s'", name
);
9654 ++input_line_pointer
;
9656 if (*input_line_pointer
!= ']')
9658 as_bad ("Closing bracket misssing");
9663 if (e
->X_op
!= O_register
)
9664 as_bad ("Register expected as index");
9666 ++input_line_pointer
;
9677 ignore_rest_of_line ();
9680 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9681 a section symbol plus some offset. For relocs involving @fptr(),
9682 directives we don't want such adjustments since we need to have the
9683 original symbol's name in the reloc. */
9685 ia64_fix_adjustable (fix
)
9688 /* Prevent all adjustments to global symbols */
9689 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9692 switch (fix
->fx_r_type
)
9694 case BFD_RELOC_IA64_FPTR64I
:
9695 case BFD_RELOC_IA64_FPTR32MSB
:
9696 case BFD_RELOC_IA64_FPTR32LSB
:
9697 case BFD_RELOC_IA64_FPTR64MSB
:
9698 case BFD_RELOC_IA64_FPTR64LSB
:
9699 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9700 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9710 ia64_force_relocation (fix
)
9713 switch (fix
->fx_r_type
)
9715 case BFD_RELOC_IA64_FPTR64I
:
9716 case BFD_RELOC_IA64_FPTR32MSB
:
9717 case BFD_RELOC_IA64_FPTR32LSB
:
9718 case BFD_RELOC_IA64_FPTR64MSB
:
9719 case BFD_RELOC_IA64_FPTR64LSB
:
9721 case BFD_RELOC_IA64_LTOFF22
:
9722 case BFD_RELOC_IA64_LTOFF64I
:
9723 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9724 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9725 case BFD_RELOC_IA64_PLTOFF22
:
9726 case BFD_RELOC_IA64_PLTOFF64I
:
9727 case BFD_RELOC_IA64_PLTOFF64MSB
:
9728 case BFD_RELOC_IA64_PLTOFF64LSB
:
9737 /* Decide from what point a pc-relative relocation is relative to,
9738 relative to the pc-relative fixup. Er, relatively speaking. */
9740 ia64_pcrel_from_section (fix
, sec
)
9744 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9746 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9752 /* This is called whenever some data item (not an instruction) needs a
9753 fixup. We pick the right reloc code depending on the byteorder
9754 currently in effect. */
9756 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9762 bfd_reloc_code_real_type code
;
9767 /* There are no reloc for 8 and 16 bit quantities, but we allow
9768 them here since they will work fine as long as the expression
9769 is fully defined at the end of the pass over the source file. */
9770 case 1: code
= BFD_RELOC_8
; break;
9771 case 2: code
= BFD_RELOC_16
; break;
9773 if (target_big_endian
)
9774 code
= BFD_RELOC_IA64_DIR32MSB
;
9776 code
= BFD_RELOC_IA64_DIR32LSB
;
9780 if (target_big_endian
)
9781 code
= BFD_RELOC_IA64_DIR64MSB
;
9783 code
= BFD_RELOC_IA64_DIR64LSB
;
9787 as_bad ("Unsupported fixup size %d", nbytes
);
9788 ignore_rest_of_line ();
9791 if (exp
->X_op
== O_pseudo_fixup
)
9794 exp
->X_op
= O_symbol
;
9795 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9797 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9798 /* We need to store the byte order in effect in case we're going
9799 to fix an 8 or 16 bit relocation (for which there no real
9800 relocs available). See md_apply_fix(). */
9801 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9804 /* Return the actual relocation we wish to associate with the pseudo
9805 reloc described by SYM and R_TYPE. SYM should be one of the
9806 symbols in the pseudo_func array, or NULL. */
9808 static bfd_reloc_code_real_type
9809 ia64_gen_real_reloc_type (sym
, r_type
)
9811 bfd_reloc_code_real_type r_type
;
9813 bfd_reloc_code_real_type
new = 0;
9820 switch (S_GET_VALUE (sym
))
9822 case FUNC_FPTR_RELATIVE
:
9825 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9826 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9827 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9828 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9829 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9834 case FUNC_GP_RELATIVE
:
9837 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9838 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9839 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9840 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9841 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9842 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9847 case FUNC_LT_RELATIVE
:
9850 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9851 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9856 case FUNC_PC_RELATIVE
:
9859 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9860 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9861 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9862 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9863 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9864 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9869 case FUNC_PLT_RELATIVE
:
9872 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9873 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9874 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9875 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9880 case FUNC_SEC_RELATIVE
:
9883 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9884 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9885 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9886 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9891 case FUNC_SEG_RELATIVE
:
9894 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9895 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9896 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9897 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9902 case FUNC_LTV_RELATIVE
:
9905 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9906 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9907 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9908 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9913 case FUNC_LT_FPTR_RELATIVE
:
9916 case BFD_RELOC_IA64_IMM22
:
9917 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9918 case BFD_RELOC_IA64_IMM64
:
9919 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9927 /* Hmmmm. Should this ever occur? */
9934 /* Here is where generate the appropriate reloc for pseudo relocation
9937 ia64_validate_fix (fix
)
9940 switch (fix
->fx_r_type
)
9942 case BFD_RELOC_IA64_FPTR64I
:
9943 case BFD_RELOC_IA64_FPTR32MSB
:
9944 case BFD_RELOC_IA64_FPTR64LSB
:
9945 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9946 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9947 if (fix
->fx_offset
!= 0)
9948 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9949 "No addend allowed in @fptr() relocation");
9959 fix_insn (fix
, odesc
, value
)
9961 const struct ia64_operand
*odesc
;
9964 bfd_vma insn
[3], t0
, t1
, control_bits
;
9969 slot
= fix
->fx_where
& 0x3;
9970 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9972 /* Bundles are always in little-endian byte order */
9973 t0
= bfd_getl64 (fixpos
);
9974 t1
= bfd_getl64 (fixpos
+ 8);
9975 control_bits
= t0
& 0x1f;
9976 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9977 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9978 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9981 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9983 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9984 insn
[2] |= (((value
& 0x7f) << 13)
9985 | (((value
>> 7) & 0x1ff) << 27)
9986 | (((value
>> 16) & 0x1f) << 22)
9987 | (((value
>> 21) & 0x1) << 21)
9988 | (((value
>> 63) & 0x1) << 36));
9990 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9992 if (value
& ~0x3fffffffffffffffULL
)
9993 err
= "integer operand out of range";
9994 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9995 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9997 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10000 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10001 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10002 | (((value
>> 0) & 0xfffff) << 13));
10005 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10008 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10010 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10011 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10012 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10013 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10016 /* Attempt to simplify or even eliminate a fixup. The return value is
10017 ignored; perhaps it was once meaningful, but now it is historical.
10018 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10020 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10023 md_apply_fix3 (fix
, valuep
, seg
)
10026 segT seg ATTRIBUTE_UNUSED
;
10029 valueT value
= *valuep
;
10032 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10036 switch (fix
->fx_r_type
)
10038 case BFD_RELOC_IA64_DIR32MSB
:
10039 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10043 case BFD_RELOC_IA64_DIR32LSB
:
10044 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10048 case BFD_RELOC_IA64_DIR64MSB
:
10049 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10053 case BFD_RELOC_IA64_DIR64LSB
:
10054 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10064 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
10066 /* This must be a TAG13 or TAG13b operand. There are no external
10067 relocs defined for them, so we must give an error. */
10068 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10069 "%s must have a constant value",
10070 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10075 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10076 work. There should be a better way to handle this. */
10078 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10080 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10082 if (fix
->tc_fix_data
.bigendian
)
10083 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10085 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10091 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10098 /* Generate the BFD reloc to be stuck in the object file from the
10099 fixup used internally in the assembler. */
10102 tc_gen_reloc (sec
, fixp
)
10103 asection
*sec ATTRIBUTE_UNUSED
;
10108 reloc
= xmalloc (sizeof (*reloc
));
10109 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10110 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10111 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10112 reloc
->addend
= fixp
->fx_offset
;
10113 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10117 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10118 "Cannot represent %s relocation in object file",
10119 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10124 /* Turn a string in input_line_pointer into a floating point constant
10125 of type TYPE, and store the appropriate bytes in *LIT. The number
10126 of LITTLENUMS emitted is stored in *SIZE. An error message is
10127 returned, or NULL on OK. */
10129 #define MAX_LITTLENUMS 5
10132 md_atof (type
, lit
, size
)
10137 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10138 LITTLENUM_TYPE
*word
;
10168 return "Bad call to MD_ATOF()";
10170 t
= atof_ieee (input_line_pointer
, type
, words
);
10172 input_line_pointer
= t
;
10173 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10175 for (word
= words
+ prec
- 1; prec
--;)
10177 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10178 lit
+= sizeof (LITTLENUM_TYPE
);
10183 /* Round up a section's size to the appropriate boundary. */
10185 md_section_align (seg
, size
)
10189 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10190 valueT mask
= ((valueT
) 1 << align
) - 1;
10192 return (size
+ mask
) & ~mask
;
10195 /* Handle ia64 specific semantics of the align directive. */
10198 ia64_md_do_align (n
, fill
, len
, max
)
10199 int n ATTRIBUTE_UNUSED
;
10200 const char *fill ATTRIBUTE_UNUSED
;
10201 int len ATTRIBUTE_UNUSED
;
10202 int max ATTRIBUTE_UNUSED
;
10204 if (subseg_text_p (now_seg
))
10205 ia64_flush_insns ();
10208 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10209 of an rs_align_code fragment. */
10212 ia64_handle_align (fragp
)
10215 /* Use mfi bundle of nops with no stop bits. */
10216 static const unsigned char be_nop
[]
10217 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10218 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10219 static const unsigned char le_nop
[]
10220 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10221 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10226 if (fragp
->fr_type
!= rs_align_code
)
10229 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10230 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10232 /* Make sure we are on a 16-byte boundary, in case someone has been
10233 putting data into a text section. */
10236 int fix
= bytes
& 15;
10237 memset (p
, 0, fix
);
10240 fragp
->fr_fix
+= fix
;
10243 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10244 fragp
->fr_var
= 16;