1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "M:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
225 unsigned int src_line
;
226 struct dwarf2_line_info debug_line
;
234 struct dynreg
*next
; /* next dynamic register */
236 unsigned short base
; /* the base register number */
237 unsigned short num_regs
; /* # of registers in this set */
239 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
241 flagword flags
; /* ELF-header flags */
244 unsigned hint
:1; /* is this hint currently valid? */
245 bfd_vma offset
; /* mem.offset offset */
246 bfd_vma base
; /* mem.offset base */
249 int path
; /* number of alt. entry points seen */
250 const char **entry_labels
; /* labels of all alternate paths in
251 the current DV-checking block. */
252 int maxpaths
; /* size currently allocated for
257 /* application registers: */
263 #define AR_BSPSTORE 18
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
309 /* control registers: */
351 static const struct const_desc
358 /* PSR constant masks: */
361 {"psr.be", ((valueT
) 1) << 1},
362 {"psr.up", ((valueT
) 1) << 2},
363 {"psr.ac", ((valueT
) 1) << 3},
364 {"psr.mfl", ((valueT
) 1) << 4},
365 {"psr.mfh", ((valueT
) 1) << 5},
367 {"psr.ic", ((valueT
) 1) << 13},
368 {"psr.i", ((valueT
) 1) << 14},
369 {"psr.pk", ((valueT
) 1) << 15},
371 {"psr.dt", ((valueT
) 1) << 17},
372 {"psr.dfl", ((valueT
) 1) << 18},
373 {"psr.dfh", ((valueT
) 1) << 19},
374 {"psr.sp", ((valueT
) 1) << 20},
375 {"psr.pp", ((valueT
) 1) << 21},
376 {"psr.di", ((valueT
) 1) << 22},
377 {"psr.si", ((valueT
) 1) << 23},
378 {"psr.db", ((valueT
) 1) << 24},
379 {"psr.lp", ((valueT
) 1) << 25},
380 {"psr.tb", ((valueT
) 1) << 26},
381 {"psr.rt", ((valueT
) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT
) 1) << 34},
385 {"psr.mc", ((valueT
) 1) << 35},
386 {"psr.it", ((valueT
) 1) << 36},
387 {"psr.id", ((valueT
) 1) << 37},
388 {"psr.da", ((valueT
) 1) << 38},
389 {"psr.dd", ((valueT
) 1) << 39},
390 {"psr.ss", ((valueT
) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT
) 1) << 43},
393 {"psr.bn", ((valueT
) 1) << 44},
396 /* indirect register-sets/memory: */
405 { "CPUID", IND_CPUID
},
406 { "cpuid", IND_CPUID
},
418 /* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC
},
443 { "gprel", PSEUDO_FUNC_RELOC
},
444 { "ltoff", PSEUDO_FUNC_RELOC
},
445 { "pcrel", PSEUDO_FUNC_RELOC
},
446 { "pltoff", PSEUDO_FUNC_RELOC
},
447 { "secrel", PSEUDO_FUNC_RELOC
},
448 { "segrel", PSEUDO_FUNC_RELOC
},
449 { "ltv", PSEUDO_FUNC_RELOC
},
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
459 /* fclass constants: */
460 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
461 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
470 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
481 /* 41-bit nop opcodes (one per unit): */
482 static const bfd_vma nop
[IA64_NUM_UNITS
] =
484 0x0000000000LL
, /* NIL => break 0 */
485 0x0008000000LL
, /* I-unit nop */
486 0x0008000000LL
, /* M-unit nop */
487 0x4000000000LL
, /* B-unit nop */
488 0x0008000000LL
, /* F-unit nop */
489 0x0008000000LL
, /* L-"unit" nop */
490 0x0008000000LL
, /* X-unit nop */
493 /* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495 static char special_section_name
[][20] =
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
501 /* The best template for a particular sequence of up to three
503 #define N IA64_NUM_TYPES
504 static unsigned char best_template
[N
][N
][N
];
507 /* Resource dependencies currently in effect */
509 int depind
; /* dependency index */
510 const struct ia64_dependency
*dependency
; /* actual dependency */
511 unsigned specific
:1, /* is this a specific bit/regno? */
512 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
513 int index
; /* specific regno/bit within dependency */
514 int note
; /* optional qualifying note (0 if none) */
518 int insn_srlz
; /* current insn serialization state */
519 int data_srlz
; /* current data serialization state */
520 int qp_regno
; /* qualifying predicate for this usage */
521 char *file
; /* what file marked this dependency */
522 int line
; /* what line marked this dependency */
523 struct mem_offset mem_offset
; /* optional memory offset hint */
524 int path
; /* corresponding code entry index */
526 static int regdepslen
= 0;
527 static int regdepstotlen
= 0;
528 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
529 static const char *dv_sem
[] = { "none", "implied", "impliedf",
530 "data", "instr", "specific", "other" };
532 /* Current state of PR mutexation */
533 static struct qpmutex
{
536 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
537 static int qp_mutexeslen
= 0;
538 static int qp_mutexestotlen
= 0;
539 static valueT qp_safe_across_calls
= 0;
541 /* Current state of PR implications */
542 static struct qp_imply
{
545 unsigned p2_branched
:1;
547 } *qp_implies
= NULL
;
548 static int qp_implieslen
= 0;
549 static int qp_impliestotlen
= 0;
551 /* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
557 } gr_values
[128] = {{ 1, 0 }};
559 /* These are the routines required to output the various types of
562 typedef struct unw_rec_list
{
564 unsigned long slot_number
;
565 struct unw_rec_list
*next
;
568 #define SLOT_NUM_NOT_SET -1
572 unsigned long next_slot_number
;
574 /* Maintain a list of unwind entries for the current function. */
578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list
*current_entry
;
582 /* These are used to create the unwind table entry for this function. */
585 symbolS
*info
; /* pointer to unwind info */
586 symbolS
*personality_routine
;
588 /* TRUE if processing unwind directives in a prologue region. */
593 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
595 /* Forward delarations: */
596 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
597 static void set_section
PARAMS ((char *name
));
598 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600 static void dot_radix
PARAMS ((int));
601 static void dot_special_section
PARAMS ((int));
602 static void dot_proc
PARAMS ((int));
603 static void dot_fframe
PARAMS ((int));
604 static void dot_vframe
PARAMS ((int));
605 static void dot_vframesp
PARAMS ((int));
606 static void dot_vframepsp
PARAMS ((int));
607 static void dot_save
PARAMS ((int));
608 static void dot_restore
PARAMS ((int));
609 static void dot_restorereg
PARAMS ((int));
610 static void dot_restorereg_p
PARAMS ((int));
611 static void dot_handlerdata
PARAMS ((int));
612 static void dot_unwentry
PARAMS ((int));
613 static void dot_altrp
PARAMS ((int));
614 static void dot_savemem
PARAMS ((int));
615 static void dot_saveg
PARAMS ((int));
616 static void dot_savef
PARAMS ((int));
617 static void dot_saveb
PARAMS ((int));
618 static void dot_savegf
PARAMS ((int));
619 static void dot_spill
PARAMS ((int));
620 static void dot_spillreg
PARAMS ((int));
621 static void dot_spillmem
PARAMS ((int));
622 static void dot_spillreg_p
PARAMS ((int));
623 static void dot_spillmem_p
PARAMS ((int));
624 static void dot_label_state
PARAMS ((int));
625 static void dot_copy_state
PARAMS ((int));
626 static void dot_unwabi
PARAMS ((int));
627 static void dot_personality
PARAMS ((int));
628 static void dot_body
PARAMS ((int));
629 static void dot_prologue
PARAMS ((int));
630 static void dot_endp
PARAMS ((int));
631 static void dot_template
PARAMS ((int));
632 static void dot_regstk
PARAMS ((int));
633 static void dot_rot
PARAMS ((int));
634 static void dot_byteorder
PARAMS ((int));
635 static void dot_psr
PARAMS ((int));
636 static void dot_alias
PARAMS ((int));
637 static void dot_ln
PARAMS ((int));
638 static char *parse_section_name
PARAMS ((void));
639 static void dot_xdata
PARAMS ((int));
640 static void stmt_float_cons
PARAMS ((int));
641 static void stmt_cons_ua
PARAMS ((int));
642 static void dot_xfloat_cons
PARAMS ((int));
643 static void dot_xstringer
PARAMS ((int));
644 static void dot_xdata_ua
PARAMS ((int));
645 static void dot_xfloat_cons_ua
PARAMS ((int));
646 static void print_prmask
PARAMS ((valueT mask
));
647 static void dot_pred_rel
PARAMS ((int));
648 static void dot_reg_val
PARAMS ((int));
649 static void dot_dv_mode
PARAMS ((int));
650 static void dot_entry
PARAMS ((int));
651 static void dot_mem_offset
PARAMS ((int));
652 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
653 static symbolS
* declare_register
PARAMS ((const char *name
, int regnum
));
654 static void declare_register_set
PARAMS ((const char *, int, int));
655 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
656 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
657 int index
, expressionS
*e
));
658 static int parse_operand
PARAMS ((expressionS
*e
));
659 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
660 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
661 static void emit_one_bundle
PARAMS ((void));
662 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
663 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
664 bfd_reloc_code_real_type r_type
));
665 static void insn_group_break
PARAMS ((int, int, int));
666 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
667 struct rsrc
*, int depind
, int path
));
668 static void add_qp_mutex
PARAMS((valueT mask
));
669 static void add_qp_imply
PARAMS((int p1
, int p2
));
670 static void clear_qp_branch_flag
PARAMS((valueT mask
));
671 static void clear_qp_mutex
PARAMS((valueT mask
));
672 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
673 static void clear_register_values
PARAMS ((void));
674 static void print_dependency
PARAMS ((const char *action
, int depind
));
675 static void instruction_serialization
PARAMS ((void));
676 static void data_serialization
PARAMS ((void));
677 static void remove_marked_resource
PARAMS ((struct rsrc
*));
678 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
679 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
680 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
681 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
682 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
683 struct ia64_opcode
*, int, struct rsrc
[], int, int));
684 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
685 static void check_dependencies
PARAMS((struct ia64_opcode
*));
686 static void mark_resources
PARAMS((struct ia64_opcode
*));
687 static void update_dependencies
PARAMS((struct ia64_opcode
*));
688 static void note_register_values
PARAMS((struct ia64_opcode
*));
689 static int qp_mutex
PARAMS ((int, int, int));
690 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
691 static void output_vbyte_mem
PARAMS ((int, char *, char *));
692 static void count_output
PARAMS ((int, char *, char *));
693 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
694 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
695 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
696 static void output_P1_format
PARAMS ((vbyte_func
, int));
697 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
698 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
699 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
700 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
701 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
702 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
703 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
704 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
705 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
706 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
707 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
708 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
709 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
710 static char format_ab_reg
PARAMS ((int, int));
711 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
713 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
714 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
716 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
717 static void free_list_records
PARAMS ((unw_rec_list
*));
718 static unw_rec_list
*output_prologue
PARAMS ((void));
719 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
720 static unw_rec_list
*output_body
PARAMS ((void));
721 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
722 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
723 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
724 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
725 static unw_rec_list
*output_rp_when
PARAMS ((void));
726 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
727 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
728 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
729 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
730 static unw_rec_list
*output_pfs_when
PARAMS ((void));
731 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
732 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
733 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
734 static unw_rec_list
*output_preds_when
PARAMS ((void));
735 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
736 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
737 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
738 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
739 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
740 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
741 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
742 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
743 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
744 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
745 static unw_rec_list
*output_unat_when
PARAMS ((void));
746 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
747 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
748 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
749 static unw_rec_list
*output_lc_when
PARAMS ((void));
750 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
751 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
752 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
753 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
754 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
755 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
756 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
757 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
758 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
759 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
761 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_bsp_when
PARAMS ((void));
763 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
764 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
765 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
767 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
768 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
769 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_rnat_when
PARAMS ((void));
771 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
772 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
773 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
774 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
775 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
776 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
777 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
778 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
779 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
780 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
782 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
784 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
786 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
789 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
790 static int calc_record_size
PARAMS ((unw_rec_list
*));
791 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
792 static int count_bits
PARAMS ((unsigned long));
793 static unsigned long slot_index
PARAMS ((unsigned long, unsigned long));
794 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
795 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
796 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
797 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
798 static int generate_unwind_image
PARAMS ((void));
800 /* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
803 ar_is_in_integer_unit (reg
)
808 return (reg
== 64 /* pfs */
809 || reg
== 65 /* lc */
810 || reg
== 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg
>= 112 && reg
<= 127));
815 /* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
823 char *saved_input_line_pointer
;
825 saved_input_line_pointer
= input_line_pointer
;
826 input_line_pointer
= name
;
828 input_line_pointer
= saved_input_line_pointer
;
831 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
834 ia64_elf_section_flags (flags
, attr
, type
)
838 if (attr
& SHF_IA_64_SHORT
)
839 flags
|= SEC_SMALL_DATA
;
844 set_regstack (ins
, locs
, outs
, rots
)
845 unsigned int ins
, locs
, outs
, rots
;
847 unsigned int sof
; /* size of frame */
849 sof
= ins
+ locs
+ outs
;
852 as_bad ("Size of frame exceeds maximum of 96 registers");
857 as_warn ("Size of rotating registers exceeds frame size");
860 md
.in
.base
= REG_GR
+ 32;
861 md
.loc
.base
= md
.in
.base
+ ins
;
862 md
.out
.base
= md
.loc
.base
+ locs
;
864 md
.in
.num_regs
= ins
;
865 md
.loc
.num_regs
= locs
;
866 md
.out
.num_regs
= outs
;
867 md
.rot
.num_regs
= rots
;
874 struct label_fix
*lfix
;
876 subsegT saved_subseg
;
878 if (!md
.last_text_seg
)
882 saved_subseg
= now_subseg
;
884 subseg_set (md
.last_text_seg
, 0);
886 while (md
.num_slots_in_use
> 0)
887 emit_one_bundle (); /* force out queued instructions */
889 /* In case there are labels following the last instruction, resolve
891 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
893 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
894 symbol_set_frag (lfix
->sym
, frag_now
);
896 CURR_SLOT
.label_fixups
= 0;
898 subseg_set (saved_seg
, saved_subseg
);
902 ia64_do_align (nbytes
)
905 char *saved_input_line_pointer
= input_line_pointer
;
907 input_line_pointer
= "";
908 s_align_bytes (nbytes
);
909 input_line_pointer
= saved_input_line_pointer
;
913 ia64_cons_align (nbytes
)
918 char *saved_input_line_pointer
= input_line_pointer
;
919 input_line_pointer
= "";
920 s_align_bytes (nbytes
);
921 input_line_pointer
= saved_input_line_pointer
;
925 /* Output COUNT bytes to a memory location. */
926 static unsigned char *vbyte_mem_ptr
= NULL
;
929 output_vbyte_mem (count
, ptr
, comment
)
935 if (vbyte_mem_ptr
== NULL
)
940 for (x
= 0; x
< count
; x
++)
941 *(vbyte_mem_ptr
++) = ptr
[x
];
944 /* Count the number of bytes required for records. */
945 static int vbyte_count
= 0;
947 count_output (count
, ptr
, comment
)
952 vbyte_count
+= count
;
956 output_R1_format (f
, rtype
, rlen
)
958 unw_record_type rtype
;
965 output_R3_format (f
, rtype
, rlen
);
971 else if (rtype
!= prologue
)
972 as_bad ("record type is not valid");
974 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
975 (*f
) (1, &byte
, NULL
);
979 output_R2_format (f
, mask
, grsave
, rlen
)
986 mask
= (mask
& 0x0f);
987 grsave
= (grsave
& 0x7f);
989 bytes
[0] = (UNW_R2
| (mask
>> 1));
990 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
991 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
992 (*f
) (count
, bytes
, NULL
);
996 output_R3_format (f
, rtype
, rlen
)
998 unw_record_type rtype
;
1005 output_R1_format (f
, rtype
, rlen
);
1011 else if (rtype
!= prologue
)
1012 as_bad ("record type is not valid");
1013 bytes
[0] = (UNW_R3
| r
);
1014 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1015 (*f
) (count
+ 1, bytes
, NULL
);
1019 output_P1_format (f
, brmask
)
1024 byte
= UNW_P1
| (brmask
& 0x1f);
1025 (*f
) (1, &byte
, NULL
);
1029 output_P2_format (f
, brmask
, gr
)
1035 brmask
= (brmask
& 0x1f);
1036 bytes
[0] = UNW_P2
| (brmask
>> 1);
1037 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1038 (*f
) (2, bytes
, NULL
);
1042 output_P3_format (f
, rtype
, reg
)
1044 unw_record_type rtype
;
1089 as_bad ("Invalid record type for P3 format.");
1091 bytes
[0] = (UNW_P3
| (r
>> 1));
1092 bytes
[1] = (((r
& 1) << 7) | reg
);
1093 (*f
) (2, bytes
, NULL
);
1097 output_P4_format (f
, imask
, imask_size
)
1099 unsigned char *imask
;
1100 unsigned long imask_size
;
1103 (*f
) (imask_size
, imask
, NULL
);
1107 output_P5_format (f
, grmask
, frmask
)
1110 unsigned long frmask
;
1113 grmask
= (grmask
& 0x0f);
1116 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1117 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1118 bytes
[3] = (frmask
& 0x000000ff);
1119 (*f
) (4, bytes
, NULL
);
1123 output_P6_format (f
, rtype
, rmask
)
1125 unw_record_type rtype
;
1131 if (rtype
== gr_mem
)
1133 else if (rtype
!= fr_mem
)
1134 as_bad ("Invalid record type for format P6");
1135 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1136 (*f
) (1, &byte
, NULL
);
1140 output_P7_format (f
, rtype
, w1
, w2
)
1142 unw_record_type rtype
;
1149 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1154 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1204 bytes
[0] = (UNW_P7
| r
);
1205 (*f
) (count
, bytes
, NULL
);
1209 output_P8_format (f
, rtype
, t
)
1211 unw_record_type rtype
;
1250 case bspstore_psprel
:
1253 case bspstore_sprel
:
1265 case priunat_when_gr
:
1268 case priunat_psprel
:
1274 case priunat_when_mem
:
1281 count
+= output_leb128 (bytes
+ 2, t
, 0);
1282 (*f
) (count
, bytes
, NULL
);
1286 output_P9_format (f
, grmask
, gr
)
1293 bytes
[1] = (grmask
& 0x0f);
1294 bytes
[2] = (gr
& 0x7f);
1295 (*f
) (3, bytes
, NULL
);
1299 output_P10_format (f
, abi
, context
)
1306 bytes
[1] = (abi
& 0xff);
1307 bytes
[2] = (context
& 0xff);
1308 (*f
) (3, bytes
, NULL
);
1312 output_B1_format (f
, rtype
, label
)
1314 unw_record_type rtype
;
1315 unsigned long label
;
1321 output_B4_format (f
, rtype
, label
);
1324 if (rtype
== copy_state
)
1326 else if (rtype
!= label_state
)
1327 as_bad ("Invalid record type for format B1");
1329 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1330 (*f
) (1, &byte
, NULL
);
1334 output_B2_format (f
, ecount
, t
)
1336 unsigned long ecount
;
1343 output_B3_format (f
, ecount
, t
);
1346 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1347 count
+= output_leb128 (bytes
+ 1, t
, 0);
1348 (*f
) (count
, bytes
, NULL
);
1352 output_B3_format (f
, ecount
, t
)
1354 unsigned long ecount
;
1361 output_B2_format (f
, ecount
, t
);
1365 count
+= output_leb128 (bytes
+ 1, t
, 0);
1366 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1367 (*f
) (count
, bytes
, NULL
);
1371 output_B4_format (f
, rtype
, label
)
1373 unw_record_type rtype
;
1374 unsigned long label
;
1381 output_B1_format (f
, rtype
, label
);
1385 if (rtype
== copy_state
)
1387 else if (rtype
!= label_state
)
1388 as_bad ("Invalid record type for format B1");
1390 bytes
[0] = (UNW_B4
| (r
<< 3));
1391 count
+= output_leb128 (bytes
+ 1, label
, 0);
1392 (*f
) (count
, bytes
, NULL
);
1396 format_ab_reg (ab
, reg
)
1403 ret
= (ab
<< 5) | reg
;
1408 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1410 unw_record_type rtype
;
1420 if (rtype
== spill_sprel
)
1422 else if (rtype
!= spill_psprel
)
1423 as_bad ("Invalid record type for format X1");
1424 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1425 count
+= output_leb128 (bytes
+ 2, t
, 0);
1426 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1427 (*f
) (count
, bytes
, NULL
);
1431 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1440 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1441 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1442 count
+= output_leb128 (bytes
+ 3, t
, 0);
1443 (*f
) (count
, bytes
, NULL
);
1447 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1449 unw_record_type rtype
;
1460 if (rtype
== spill_sprel_p
)
1462 else if (rtype
!= spill_psprel_p
)
1463 as_bad ("Invalid record type for format X3");
1464 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1465 bytes
[2] = format_ab_reg (ab
, reg
);
1466 count
+= output_leb128 (bytes
+ 3, t
, 0);
1467 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1468 (*f
) (count
, bytes
, NULL
);
1472 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1482 bytes
[1] = (qp
& 0x3f);
1483 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1484 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1485 count
+= output_leb128 (bytes
+ 4, t
, 0);
1486 (*f
) (count
, bytes
, NULL
);
1489 /* This function allocates a record list structure, and initializes fields. */
1490 static unw_rec_list
*
1491 alloc_record (unw_record_type t
)
1494 ptr
= xmalloc (sizeof (*ptr
));
1496 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1501 /* This function frees an entire list of record structures. */
1503 free_list_records (unw_rec_list
*first
)
1506 for (ptr
= first
; ptr
!= NULL
; )
1508 unw_rec_list
*tmp
= ptr
;
1510 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1511 && tmp
->r
.record
.r
.mask
.i
)
1512 free (tmp
->r
.record
.r
.mask
.i
);
1519 static unw_rec_list
*
1522 unw_rec_list
*ptr
= alloc_record (prologue
);
1523 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1527 static unw_rec_list
*
1528 output_prologue_gr (saved_mask
, reg
)
1529 unsigned int saved_mask
;
1532 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1533 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1534 ptr
->r
.record
.r
.grmask
= saved_mask
;
1535 ptr
->r
.record
.r
.grsave
= reg
;
1539 static unw_rec_list
*
1542 unw_rec_list
*ptr
= alloc_record (body
);
1546 static unw_rec_list
*
1547 output_mem_stack_f (size
)
1550 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1551 ptr
->r
.record
.p
.size
= size
;
1555 static unw_rec_list
*
1556 output_mem_stack_v ()
1558 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1562 static unw_rec_list
*
1566 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1567 ptr
->r
.record
.p
.gr
= gr
;
1571 static unw_rec_list
*
1572 output_psp_sprel (offset
)
1573 unsigned int offset
;
1575 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1576 ptr
->r
.record
.p
.spoff
= offset
/4;
1580 static unw_rec_list
*
1583 unw_rec_list
*ptr
= alloc_record (rp_when
);
1587 static unw_rec_list
*
1591 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1592 ptr
->r
.record
.p
.gr
= gr
;
1596 static unw_rec_list
*
1600 unw_rec_list
*ptr
= alloc_record (rp_br
);
1601 ptr
->r
.record
.p
.br
= br
;
1605 static unw_rec_list
*
1606 output_rp_psprel (offset
)
1607 unsigned int offset
;
1609 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1610 ptr
->r
.record
.p
.pspoff
= offset
/4;
1614 static unw_rec_list
*
1615 output_rp_sprel (offset
)
1616 unsigned int offset
;
1618 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1619 ptr
->r
.record
.p
.spoff
= offset
/4;
1623 static unw_rec_list
*
1626 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1630 static unw_rec_list
*
1634 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1635 ptr
->r
.record
.p
.gr
= gr
;
1639 static unw_rec_list
*
1640 output_pfs_psprel (offset
)
1641 unsigned int offset
;
1643 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1644 ptr
->r
.record
.p
.pspoff
= offset
/4;
1648 static unw_rec_list
*
1649 output_pfs_sprel (offset
)
1650 unsigned int offset
;
1652 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1653 ptr
->r
.record
.p
.spoff
= offset
/4;
1657 static unw_rec_list
*
1658 output_preds_when ()
1660 unw_rec_list
*ptr
= alloc_record (preds_when
);
1664 static unw_rec_list
*
1665 output_preds_gr (gr
)
1668 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1669 ptr
->r
.record
.p
.gr
= gr
;
1673 static unw_rec_list
*
1674 output_preds_psprel (offset
)
1675 unsigned int offset
;
1677 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1678 ptr
->r
.record
.p
.pspoff
= offset
/4;
1682 static unw_rec_list
*
1683 output_preds_sprel (offset
)
1684 unsigned int offset
;
1686 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1687 ptr
->r
.record
.p
.spoff
= offset
/4;
1691 static unw_rec_list
*
1692 output_fr_mem (mask
)
1695 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1696 ptr
->r
.record
.p
.rmask
= mask
;
1700 static unw_rec_list
*
1701 output_frgr_mem (gr_mask
, fr_mask
)
1702 unsigned int gr_mask
;
1703 unsigned int fr_mask
;
1705 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1706 ptr
->r
.record
.p
.grmask
= gr_mask
;
1707 ptr
->r
.record
.p
.frmask
= fr_mask
;
1711 static unw_rec_list
*
1712 output_gr_gr (mask
, reg
)
1716 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1717 ptr
->r
.record
.p
.grmask
= mask
;
1718 ptr
->r
.record
.p
.gr
= reg
;
1722 static unw_rec_list
*
1723 output_gr_mem (mask
)
1726 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1727 ptr
->r
.record
.p
.rmask
= mask
;
1731 static unw_rec_list
*
1732 output_br_mem (unsigned int mask
)
1734 unw_rec_list
*ptr
= alloc_record (br_mem
);
1735 ptr
->r
.record
.p
.brmask
= mask
;
1739 static unw_rec_list
*
1740 output_br_gr (save_mask
, reg
)
1741 unsigned int save_mask
;
1744 unw_rec_list
*ptr
= alloc_record (br_gr
);
1745 ptr
->r
.record
.p
.brmask
= save_mask
;
1746 ptr
->r
.record
.p
.gr
= reg
;
1750 static unw_rec_list
*
1751 output_spill_base (offset
)
1752 unsigned int offset
;
1754 unw_rec_list
*ptr
= alloc_record (spill_base
);
1755 ptr
->r
.record
.p
.pspoff
= offset
/4;
1759 static unw_rec_list
*
1762 unw_rec_list
*ptr
= alloc_record (unat_when
);
1766 static unw_rec_list
*
1770 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1771 ptr
->r
.record
.p
.gr
= gr
;
1775 static unw_rec_list
*
1776 output_unat_psprel (offset
)
1777 unsigned int offset
;
1779 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1780 ptr
->r
.record
.p
.pspoff
= offset
/4;
1784 static unw_rec_list
*
1785 output_unat_sprel (offset
)
1786 unsigned int offset
;
1788 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1789 ptr
->r
.record
.p
.spoff
= offset
/4;
1793 static unw_rec_list
*
1796 unw_rec_list
*ptr
= alloc_record (lc_when
);
1800 static unw_rec_list
*
1804 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1805 ptr
->r
.record
.p
.gr
= gr
;
1809 static unw_rec_list
*
1810 output_lc_psprel (offset
)
1811 unsigned int offset
;
1813 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1814 ptr
->r
.record
.p
.pspoff
= offset
/4;
1818 static unw_rec_list
*
1819 output_lc_sprel (offset
)
1820 unsigned int offset
;
1822 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1823 ptr
->r
.record
.p
.spoff
= offset
/4;
1827 static unw_rec_list
*
1830 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1834 static unw_rec_list
*
1838 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1839 ptr
->r
.record
.p
.gr
= gr
;
1843 static unw_rec_list
*
1844 output_fpsr_psprel (offset
)
1845 unsigned int offset
;
1847 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1848 ptr
->r
.record
.p
.pspoff
= offset
/4;
1852 static unw_rec_list
*
1853 output_fpsr_sprel (offset
)
1854 unsigned int offset
;
1856 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1857 ptr
->r
.record
.p
.spoff
= offset
/4;
1861 static unw_rec_list
*
1862 output_priunat_when_gr ()
1864 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1868 static unw_rec_list
*
1869 output_priunat_when_mem ()
1871 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1875 static unw_rec_list
*
1876 output_priunat_gr (gr
)
1879 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1880 ptr
->r
.record
.p
.gr
= gr
;
1884 static unw_rec_list
*
1885 output_priunat_psprel (offset
)
1886 unsigned int offset
;
1888 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1889 ptr
->r
.record
.p
.pspoff
= offset
/4;
1893 static unw_rec_list
*
1894 output_priunat_sprel (offset
)
1895 unsigned int offset
;
1897 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1898 ptr
->r
.record
.p
.spoff
= offset
/4;
1902 static unw_rec_list
*
1905 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1909 static unw_rec_list
*
1913 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1914 ptr
->r
.record
.p
.gr
= gr
;
1918 static unw_rec_list
*
1919 output_bsp_psprel (offset
)
1920 unsigned int offset
;
1922 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1923 ptr
->r
.record
.p
.pspoff
= offset
/4;
1927 static unw_rec_list
*
1928 output_bsp_sprel (offset
)
1929 unsigned int offset
;
1931 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1932 ptr
->r
.record
.p
.spoff
= offset
/4;
1936 static unw_rec_list
*
1937 output_bspstore_when ()
1939 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
1943 static unw_rec_list
*
1944 output_bspstore_gr (gr
)
1947 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
1948 ptr
->r
.record
.p
.gr
= gr
;
1952 static unw_rec_list
*
1953 output_bspstore_psprel (offset
)
1954 unsigned int offset
;
1956 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
1957 ptr
->r
.record
.p
.pspoff
= offset
/4;
1961 static unw_rec_list
*
1962 output_bspstore_sprel (offset
)
1963 unsigned int offset
;
1965 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
1966 ptr
->r
.record
.p
.spoff
= offset
/4;
1970 static unw_rec_list
*
1973 unw_rec_list
*ptr
= alloc_record (rnat_when
);
1977 static unw_rec_list
*
1981 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
1982 ptr
->r
.record
.p
.gr
= gr
;
1986 static unw_rec_list
*
1987 output_rnat_psprel (offset
)
1988 unsigned int offset
;
1990 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
1991 ptr
->r
.record
.p
.pspoff
= offset
/4;
1995 static unw_rec_list
*
1996 output_rnat_sprel (offset
)
1997 unsigned int offset
;
1999 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2000 ptr
->r
.record
.p
.spoff
= offset
/4;
2004 static unw_rec_list
*
2005 output_unwabi (abi
, context
)
2007 unsigned long context
;
2009 unw_rec_list
*ptr
= alloc_record (unwabi
);
2010 ptr
->r
.record
.p
.abi
= abi
;
2011 ptr
->r
.record
.p
.context
= context
;
2015 static unw_rec_list
*
2016 output_epilogue (unsigned long ecount
)
2018 unw_rec_list
*ptr
= alloc_record (epilogue
);
2019 ptr
->r
.record
.b
.ecount
= ecount
;
2023 static unw_rec_list
*
2024 output_label_state (unsigned long label
)
2026 unw_rec_list
*ptr
= alloc_record (label_state
);
2027 ptr
->r
.record
.b
.label
= label
;
2031 static unw_rec_list
*
2032 output_copy_state (unsigned long label
)
2034 unw_rec_list
*ptr
= alloc_record (copy_state
);
2035 ptr
->r
.record
.b
.label
= label
;
2039 static unw_rec_list
*
2040 output_spill_psprel (ab
, reg
, offset
)
2043 unsigned int offset
;
2045 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2046 ptr
->r
.record
.x
.ab
= ab
;
2047 ptr
->r
.record
.x
.reg
= reg
;
2048 ptr
->r
.record
.x
.pspoff
= offset
/4;
2052 static unw_rec_list
*
2053 output_spill_sprel (ab
, reg
, offset
)
2056 unsigned int offset
;
2058 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2059 ptr
->r
.record
.x
.ab
= ab
;
2060 ptr
->r
.record
.x
.reg
= reg
;
2061 ptr
->r
.record
.x
.spoff
= offset
/4;
2065 static unw_rec_list
*
2066 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2069 unsigned int offset
;
2070 unsigned int predicate
;
2072 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2073 ptr
->r
.record
.x
.ab
= ab
;
2074 ptr
->r
.record
.x
.reg
= reg
;
2075 ptr
->r
.record
.x
.pspoff
= offset
/4;
2076 ptr
->r
.record
.x
.qp
= predicate
;
2080 static unw_rec_list
*
2081 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2084 unsigned int offset
;
2085 unsigned int predicate
;
2087 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2088 ptr
->r
.record
.x
.ab
= ab
;
2089 ptr
->r
.record
.x
.reg
= reg
;
2090 ptr
->r
.record
.x
.spoff
= offset
/4;
2091 ptr
->r
.record
.x
.qp
= predicate
;
2095 static unw_rec_list
*
2096 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2099 unsigned int targ_reg
;
2102 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2103 ptr
->r
.record
.x
.ab
= ab
;
2104 ptr
->r
.record
.x
.reg
= reg
;
2105 ptr
->r
.record
.x
.treg
= targ_reg
;
2106 ptr
->r
.record
.x
.xy
= xy
;
2110 static unw_rec_list
*
2111 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2114 unsigned int targ_reg
;
2116 unsigned int predicate
;
2118 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2119 ptr
->r
.record
.x
.ab
= ab
;
2120 ptr
->r
.record
.x
.reg
= reg
;
2121 ptr
->r
.record
.x
.treg
= targ_reg
;
2122 ptr
->r
.record
.x
.xy
= xy
;
2123 ptr
->r
.record
.x
.qp
= predicate
;
2127 /* Given a unw_rec_list process the correct format with the
2128 specified function. */
2130 process_one_record (ptr
, f
)
2134 unsigned long fr_mask
, gr_mask
;
2136 switch (ptr
->r
.type
)
2142 /* these are taken care of by prologue/prologue_gr */
2147 if (ptr
->r
.type
== prologue_gr
)
2148 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2149 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2151 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2153 /* output descriptor(s) for union of register spills (if any): */
2154 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2155 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2158 if ((fr_mask
& ~0xfUL
) == 0)
2159 output_P6_format (f
, fr_mem
, fr_mask
);
2162 output_P5_format (f
, gr_mask
, fr_mask
);
2167 output_P6_format (f
, gr_mem
, gr_mask
);
2168 if (ptr
->r
.record
.r
.mask
.br_mem
)
2169 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2171 /* output imask descriptor if necessary: */
2172 if (ptr
->r
.record
.r
.mask
.i
)
2173 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2174 ptr
->r
.record
.r
.imask_size
);
2178 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2182 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2183 ptr
->r
.record
.p
.size
);
2196 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2199 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2202 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2210 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2219 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2229 case bspstore_sprel
:
2231 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2234 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2237 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2240 as_bad ("spill_mask record unimplemented.");
2242 case priunat_when_gr
:
2243 case priunat_when_mem
:
2247 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2249 case priunat_psprel
:
2251 case bspstore_psprel
:
2253 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2256 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2259 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2263 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2266 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2267 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2268 ptr
->r
.record
.x
.pspoff
);
2271 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2272 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2273 ptr
->r
.record
.x
.spoff
);
2276 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2277 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2278 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2280 case spill_psprel_p
:
2281 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2282 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2283 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2286 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2287 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2288 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2291 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2292 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2293 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2297 as_bad ("record_type_not_valid");
2302 /* Given a unw_rec_list list, process all the records with
2303 the specified function. */
2305 process_unw_records (list
, f
)
2310 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2311 process_one_record (ptr
, f
);
2314 /* Determine the size of a record list in bytes. */
2316 calc_record_size (list
)
2320 process_unw_records (list
, count_output
);
2324 /* Update IMASK bitmask to reflect the fact that one or more registers
2325 of type TYPE are saved starting at instruction with index T. If N
2326 bits are set in REGMASK, it is assumed that instructions T through
2327 T+N-1 save these registers.
2331 1: instruction saves next fp reg
2332 2: instruction saves next general reg
2333 3: instruction saves next branch reg */
2335 set_imask (region
, regmask
, t
, type
)
2336 unw_rec_list
*region
;
2337 unsigned long regmask
;
2341 unsigned char *imask
;
2342 unsigned long imask_size
;
2346 imask
= region
->r
.record
.r
.mask
.i
;
2347 imask_size
= region
->r
.record
.r
.imask_size
;
2350 imask_size
= (region
->r
.record
.r
.rlen
*2 + 7)/8 + 1;
2351 imask
= xmalloc (imask_size
);
2352 memset (imask
, 0, imask_size
);
2354 region
->r
.record
.r
.imask_size
= imask_size
;
2355 region
->r
.record
.r
.mask
.i
= imask
;
2362 if (i
>= imask_size
)
2364 as_bad ("Ignoring attempt to spill beyond end of region");
2368 imask
[i
] |= (type
& 0x3) << pos
;
2370 regmask
&= (regmask
- 1);
2381 count_bits (unsigned long mask
)
2394 slot_index (unsigned long slot_addr
, unsigned long first_addr
)
2396 return (3*((slot_addr
>> 4) - (first_addr
>> 4))
2397 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2400 /* Given a complete record list, process any records which have
2401 unresolved fields, (ie length counts for a prologue). After
2402 this has been run, all neccessary information should be available
2403 within each record to generate an image. */
2405 fixup_unw_records (list
)
2408 unw_rec_list
*ptr
, *region
= 0;
2409 unsigned long first_addr
= 0, rlen
= 0, t
;
2411 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2413 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2414 as_bad (" Insn slot not set in unwind record.");
2415 t
= slot_index (ptr
->slot_number
, first_addr
);
2416 switch (ptr
->r
.type
)
2423 int size
, dir_len
= 0;
2424 unsigned long last_addr
;
2426 first_addr
= ptr
->slot_number
;
2427 ptr
->slot_number
= 0;
2428 /* Find either the next body/prologue start, or the end of
2429 the list, and determine the size of the region. */
2430 last_addr
= unwind
.next_slot_number
;
2431 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2432 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2433 || last
->r
.type
== body
)
2435 last_addr
= last
->slot_number
;
2438 else if (!last
->next
)
2440 /* In the absence of an explicit .body directive,
2441 the prologue ends after the last instruction
2442 covered by an unwind directive. */
2443 if (ptr
->r
.type
!= body
)
2445 last_addr
= last
->slot_number
;
2446 switch (last
->r
.type
)
2449 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2450 + count_bits (last
->r
.record
.p
.grmask
));
2454 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2458 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2461 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2470 size
= slot_index (last_addr
, first_addr
) + dir_len
;
2471 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2476 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2487 case priunat_when_gr
:
2488 case priunat_when_mem
:
2492 ptr
->r
.record
.p
.t
= t
;
2500 case spill_psprel_p
:
2501 ptr
->r
.record
.x
.t
= t
;
2507 as_bad ("frgr_mem record before region record!\n");
2510 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2511 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2512 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2513 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2518 as_bad ("fr_mem record before region record!\n");
2521 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2522 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2527 as_bad ("gr_mem record before region record!\n");
2530 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2531 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2536 as_bad ("br_mem record before region record!\n");
2539 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2540 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2546 as_bad ("gr_gr record before region record!\n");
2549 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2554 as_bad ("br_gr record before region record!\n");
2557 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2566 /* Generate an unwind image from a record list. Returns the number of
2567 bytes in the resulting image. The memory image itselof is returned
2568 in the 'ptr' parameter. */
2570 output_unw_records (list
, ptr
)
2574 int size
, x
, extra
= 0;
2577 fixup_unw_records (list
);
2578 size
= calc_record_size (list
);
2580 /* pad to 8 byte boundry. */
2584 /* Add 8 for the header + 8 more bytes for the personality offset. */
2585 mem
= xmalloc (size
+ extra
+ 16);
2587 vbyte_mem_ptr
= mem
+ 8;
2588 /* Clear the padding area and personality. */
2589 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2590 /* Initialize the header area. */
2591 md_number_to_chars (mem
, (((bfd_vma
) 1 << 48) /* version */
2592 | (unwind
.personality_routine
2593 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2595 | ((size
+ extra
) / 8)), /* length (dwords) */
2598 process_unw_records (list
, output_vbyte_mem
);
2601 return size
+ extra
+ 16;
2605 convert_expr_to_ab_reg (e
, ab
, regp
)
2612 if (e
->X_op
!= O_register
)
2615 reg
= e
->X_add_number
;
2616 if (reg
>= REG_GR
+ 4 && reg
<= REG_GR
+ 7)
2619 *regp
= reg
- REG_GR
;
2621 else if ((reg
>= REG_FR
+ 2 && reg
<= REG_FR
+ 5)
2622 || (reg
>= REG_FR
+ 16 && reg
<= REG_FR
+ 31))
2625 *regp
= reg
- REG_FR
;
2627 else if (reg
>= REG_BR
+ 1 && reg
<= REG_BR
+ 5)
2630 *regp
= reg
- REG_BR
;
2637 case REG_PR
: *regp
= 0; break;
2638 case REG_PSP
: *regp
= 1; break;
2639 case REG_PRIUNAT
: *regp
= 2; break;
2640 case REG_BR
+ 0: *regp
= 3; break;
2641 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2642 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2643 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2644 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2645 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2646 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2647 case REG_AR
+ AR_LC
: *regp
= 10; break;
2657 convert_expr_to_xy_reg (e
, xy
, regp
)
2664 if (e
->X_op
!= O_register
)
2667 reg
= e
->X_add_number
;
2669 if (reg
>= REG_GR
&& reg
<= REG_GR
+ 127)
2672 *regp
= reg
- REG_GR
;
2674 else if (reg
>= REG_FR
&& reg
<= REG_FR
+ 127)
2677 *regp
= reg
- REG_FR
;
2679 else if (reg
>= REG_BR
&& reg
<= REG_BR
+ 7)
2682 *regp
= reg
- REG_BR
;
2696 radix
= *input_line_pointer
++;
2698 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2700 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2701 ignore_rest_of_line ();
2706 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2708 dot_special_section (which
)
2711 set_section ((char *) special_section_name
[which
]);
2715 add_unwind_entry (ptr
)
2719 unwind
.tail
->next
= ptr
;
2724 /* The current entry can in fact be a chain of unwind entries. */
2725 if (unwind
.current_entry
== NULL
)
2726 unwind
.current_entry
= ptr
;
2737 if (e
.X_op
!= O_constant
)
2738 as_bad ("Operand to .fframe must be a constant");
2740 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2751 reg
= e
.X_add_number
- REG_GR
;
2752 if (e
.X_op
== O_register
&& reg
< 128)
2754 add_unwind_entry (output_mem_stack_v ());
2755 if (! (unwind
.prologue_mask
& 2))
2756 add_unwind_entry (output_psp_gr (reg
));
2759 as_bad ("First operand to .vframe must be a general register");
2763 dot_vframesp (dummy
)
2769 if (e
.X_op
== O_constant
)
2771 add_unwind_entry (output_mem_stack_v ());
2772 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2775 as_bad ("First operand to .vframesp must be a general register");
2779 dot_vframepsp (dummy
)
2785 if (e
.X_op
== O_constant
)
2787 add_unwind_entry (output_mem_stack_v ());
2788 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2791 as_bad ("First operand to .vframepsp must be a general register");
2802 sep
= parse_operand (&e1
);
2804 as_bad ("No second operand to .save");
2805 sep
= parse_operand (&e2
);
2807 reg1
= e1
.X_add_number
;
2808 reg2
= e2
.X_add_number
- REG_GR
;
2810 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2811 if (e1
.X_op
== O_register
)
2813 if (e2
.X_op
== O_register
&& reg2
>=0 && reg2
< 128)
2817 case REG_AR
+ AR_BSP
:
2818 add_unwind_entry (output_bsp_when ());
2819 add_unwind_entry (output_bsp_gr (reg2
));
2821 case REG_AR
+ AR_BSPSTORE
:
2822 add_unwind_entry (output_bspstore_when ());
2823 add_unwind_entry (output_bspstore_gr (reg2
));
2825 case REG_AR
+ AR_RNAT
:
2826 add_unwind_entry (output_rnat_when ());
2827 add_unwind_entry (output_rnat_gr (reg2
));
2829 case REG_AR
+AR_UNAT
:
2830 add_unwind_entry (output_unat_when ());
2831 add_unwind_entry (output_unat_gr (reg2
));
2833 case REG_AR
+AR_FPSR
:
2834 add_unwind_entry (output_fpsr_when ());
2835 add_unwind_entry (output_fpsr_gr (reg2
));
2838 add_unwind_entry (output_pfs_when ());
2839 if (! (unwind
.prologue_mask
& 4))
2840 add_unwind_entry (output_pfs_gr (reg2
));
2843 add_unwind_entry (output_lc_when ());
2844 add_unwind_entry (output_lc_gr (reg2
));
2847 add_unwind_entry (output_rp_when ());
2848 if (! (unwind
.prologue_mask
& 8))
2849 add_unwind_entry (output_rp_gr (reg2
));
2852 add_unwind_entry (output_preds_when ());
2853 if (! (unwind
.prologue_mask
& 1))
2854 add_unwind_entry (output_preds_gr (reg2
));
2857 add_unwind_entry (output_priunat_when_gr ());
2858 add_unwind_entry (output_priunat_gr (reg2
));
2861 as_bad ("First operand not a valid register");
2865 as_bad (" Second operand not a valid register");
2868 as_bad ("First operand not a register");
2876 unsigned long ecount
= 0;
2879 sep
= parse_operand (&e1
);
2880 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2882 as_bad ("First operand to .restore must be stack pointer (sp)");
2888 parse_operand (&e2
);
2889 if (e1
.X_op
!= O_constant
)
2891 as_bad ("Second operand to .restore must be constant");
2896 add_unwind_entry (output_epilogue (ecount
));
2900 dot_restorereg (dummy
)
2903 unsigned int ab
, reg
;
2908 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
2910 as_bad ("First operand to .restorereg must be a preserved register");
2913 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
2917 dot_restorereg_p (dummy
)
2920 unsigned int qp
, ab
, reg
;
2924 sep
= parse_operand (&e1
);
2927 as_bad ("No second operand to .restorereg.p");
2931 parse_operand (&e2
);
2933 qp
= e1
.X_add_number
- REG_P
;
2934 if (e1
.X_op
!= O_register
|| qp
> 63)
2936 as_bad ("First operand to .restorereg.p must be a predicate");
2940 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
2942 as_bad ("Second operand to .restorereg.p must be a preserved register");
2945 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
2949 generate_unwind_image ()
2952 unsigned char *unw_rec
;
2954 /* Force out pending instructions, to make sure all unwind records have
2955 a valid slot_number field. */
2956 ia64_flush_insns ();
2958 /* Generate the unwind record. */
2959 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
2961 as_bad ("Unwind record is not a multiple of 8 bytes.");
2963 /* If there are unwind records, switch sections, and output the info. */
2966 unsigned char *where
;
2968 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
2970 /* Set expression which points to start of unwind descriptor area. */
2971 unwind
.info
= expr_build_dot ();
2973 where
= (unsigned char *)frag_more (size
);
2975 /* Issue a label for this address, and keep track of it to put it
2976 in the unwind section. */
2978 /* Copy the information from the unwind record into this section. The
2979 data is already in the correct byte order. */
2980 memcpy (where
, unw_rec
, size
);
2981 /* Add the personality address to the image. */
2982 if (unwind
.personality_routine
!= 0)
2984 exp
.X_op
= O_symbol
;
2985 exp
.X_add_symbol
= unwind
.personality_routine
;
2986 exp
.X_add_number
= 0;
2987 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
2988 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
2989 unwind
.personality_routine
= 0;
2991 obj_elf_previous (0);
2994 free_list_records (unwind
.list
);
2995 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3001 dot_handlerdata (dummy
)
3004 generate_unwind_image ();
3005 demand_empty_rest_of_line ();
3009 dot_unwentry (dummy
)
3012 demand_empty_rest_of_line ();
3023 reg
= e
.X_add_number
- REG_BR
;
3024 if (e
.X_op
== O_register
&& reg
< 8)
3025 add_unwind_entry (output_rp_br (reg
));
3027 as_bad ("First operand not a valid branch register");
3031 dot_savemem (psprel
)
3038 sep
= parse_operand (&e1
);
3040 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3041 sep
= parse_operand (&e2
);
3043 reg1
= e1
.X_add_number
;
3044 val
= e2
.X_add_number
;
3046 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3047 if (e1
.X_op
== O_register
)
3049 if (e2
.X_op
== O_constant
)
3053 case REG_AR
+ AR_BSP
:
3054 add_unwind_entry (output_bsp_when ());
3055 add_unwind_entry ((psprel
3057 : output_bsp_sprel
) (val
));
3059 case REG_AR
+ AR_BSPSTORE
:
3060 add_unwind_entry (output_bspstore_when ());
3061 add_unwind_entry ((psprel
3062 ? output_bspstore_psprel
3063 : output_bspstore_sprel
) (val
));
3065 case REG_AR
+ AR_RNAT
:
3066 add_unwind_entry (output_rnat_when ());
3067 add_unwind_entry ((psprel
3068 ? output_rnat_psprel
3069 : output_rnat_sprel
) (val
));
3071 case REG_AR
+ AR_UNAT
:
3072 add_unwind_entry (output_unat_when ());
3073 add_unwind_entry ((psprel
3074 ? output_unat_psprel
3075 : output_unat_sprel
) (val
));
3077 case REG_AR
+ AR_FPSR
:
3078 add_unwind_entry (output_fpsr_when ());
3079 add_unwind_entry ((psprel
3080 ? output_fpsr_psprel
3081 : output_fpsr_sprel
) (val
));
3083 case REG_AR
+ AR_PFS
:
3084 add_unwind_entry (output_pfs_when ());
3085 add_unwind_entry ((psprel
3087 : output_pfs_sprel
) (val
));
3089 case REG_AR
+ AR_LC
:
3090 add_unwind_entry (output_lc_when ());
3091 add_unwind_entry ((psprel
3093 : output_lc_sprel
) (val
));
3096 add_unwind_entry (output_rp_when ());
3097 add_unwind_entry ((psprel
3099 : output_rp_sprel
) (val
));
3102 add_unwind_entry (output_preds_when ());
3103 add_unwind_entry ((psprel
3104 ? output_preds_psprel
3105 : output_preds_sprel
) (val
));
3108 add_unwind_entry (output_priunat_when_mem ());
3109 add_unwind_entry ((psprel
3110 ? output_priunat_psprel
3111 : output_priunat_sprel
) (val
));
3114 as_bad ("First operand not a valid register");
3118 as_bad (" Second operand not a valid constant");
3121 as_bad ("First operand not a register");
3130 sep
= parse_operand (&e1
);
3132 parse_operand (&e2
);
3134 if (e1
.X_op
!= O_constant
)
3135 as_bad ("First operand to .save.g must be a constant.");
3138 int grmask
= e1
.X_add_number
;
3140 add_unwind_entry (output_gr_mem (grmask
));
3143 int reg
= e2
.X_add_number
- REG_GR
;
3144 if (e2
.X_op
== O_register
&& reg
>=0 && reg
< 128)
3145 add_unwind_entry (output_gr_gr (grmask
, reg
));
3147 as_bad ("Second operand is an invalid register.");
3158 sep
= parse_operand (&e1
);
3160 if (e1
.X_op
!= O_constant
)
3161 as_bad ("Operand to .save.f must be a constant.");
3163 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3175 sep
= parse_operand (&e1
);
3176 if (e1
.X_op
!= O_constant
)
3178 as_bad ("First operand to .save.b must be a constant.");
3181 brmask
= e1
.X_add_number
;
3185 sep
= parse_operand (&e2
);
3186 reg
= e2
.X_add_number
- REG_GR
;
3187 if (e2
.X_op
!= O_register
|| reg
> 127)
3189 as_bad ("Second operand to .save.b must be a general register.");
3192 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3195 add_unwind_entry (output_br_mem (brmask
));
3197 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3198 ignore_rest_of_line ();
3207 sep
= parse_operand (&e1
);
3209 parse_operand (&e2
);
3211 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3212 as_bad ("Both operands of .save.gf must be constants.");
3215 int grmask
= e1
.X_add_number
;
3216 int frmask
= e2
.X_add_number
;
3217 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3228 sep
= parse_operand (&e
);
3229 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3230 ignore_rest_of_line ();
3232 if (e
.X_op
!= O_constant
)
3233 as_bad ("Operand to .spill must be a constant");
3235 add_unwind_entry (output_spill_base (e
.X_add_number
));
3239 dot_spillreg (dummy
)
3242 int sep
, ab
, xy
, reg
, treg
;
3245 sep
= parse_operand (&e1
);
3248 as_bad ("No second operand to .spillreg");
3252 parse_operand (&e2
);
3254 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3256 as_bad ("First operand to .spillreg must be a preserved register");
3260 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3262 as_bad ("Second operand to .spillreg must be a register");
3266 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3270 dot_spillmem (psprel
)
3276 sep
= parse_operand (&e1
);
3279 as_bad ("Second operand missing");
3283 parse_operand (&e2
);
3285 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3287 as_bad ("First operand to .spill%s must be a preserved register",
3288 psprel
? "psp" : "sp");
3292 if (e2
.X_op
!= O_constant
)
3294 as_bad ("Second operand to .spill%s must be a constant",
3295 psprel
? "psp" : "sp");
3300 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3302 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3306 dot_spillreg_p (dummy
)
3309 int sep
, ab
, xy
, reg
, treg
;
3310 expressionS e1
, e2
, e3
;
3313 sep
= parse_operand (&e1
);
3316 as_bad ("No second and third operand to .spillreg.p");
3320 sep
= parse_operand (&e2
);
3323 as_bad ("No third operand to .spillreg.p");
3327 parse_operand (&e3
);
3329 qp
= e1
.X_add_number
- REG_P
;
3331 if (e1
.X_op
!= O_register
|| qp
> 63)
3333 as_bad ("First operand to .spillreg.p must be a predicate");
3337 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3339 as_bad ("Second operand to .spillreg.p must be a preserved register");
3343 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3345 as_bad ("Third operand to .spillreg.p must be a register");
3349 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3353 dot_spillmem_p (psprel
)
3356 expressionS e1
, e2
, e3
;
3360 sep
= parse_operand (&e1
);
3363 as_bad ("Second operand missing");
3367 parse_operand (&e2
);
3370 as_bad ("Second operand missing");
3374 parse_operand (&e3
);
3376 qp
= e1
.X_add_number
- REG_P
;
3377 if (e1
.X_op
!= O_register
|| qp
> 63)
3379 as_bad ("First operand to .spill%s_p must be a predicate",
3380 psprel
? "psp" : "sp");
3384 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3386 as_bad ("Second operand to .spill%s_p must be a preserved register",
3387 psprel
? "psp" : "sp");
3391 if (e3
.X_op
!= O_constant
)
3393 as_bad ("Third operand to .spill%s_p must be a constant",
3394 psprel
? "psp" : "sp");
3399 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3401 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3405 dot_label_state (dummy
)
3411 if (e
.X_op
!= O_constant
)
3413 as_bad ("Operand to .label_state must be a constant");
3416 add_unwind_entry (output_label_state (e
.X_add_number
));
3420 dot_copy_state (dummy
)
3426 if (e
.X_op
!= O_constant
)
3428 as_bad ("Operand to .copy_state must be a constant");
3431 add_unwind_entry (output_copy_state (e
.X_add_number
));
3441 sep
= parse_operand (&e1
);
3444 as_bad ("Second operand to .unwabi missing");
3447 sep
= parse_operand (&e2
);
3448 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3449 ignore_rest_of_line ();
3451 if (e1
.X_op
!= O_constant
)
3453 as_bad ("First operand to .unwabi must be a constant");
3457 if (e2
.X_op
!= O_constant
)
3459 as_bad ("Second operand to .unwabi must be a constant");
3463 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3467 dot_personality (dummy
)
3472 name
= input_line_pointer
;
3473 c
= get_symbol_end ();
3474 p
= input_line_pointer
;
3475 unwind
.personality_routine
= symbol_find_or_make (name
);
3478 demand_empty_rest_of_line ();
3488 unwind
.proc_start
= expr_build_dot ();
3489 /* Parse names of main and alternate entry points and mark them as
3490 function symbols: */
3494 name
= input_line_pointer
;
3495 c
= get_symbol_end ();
3496 p
= input_line_pointer
;
3497 sym
= symbol_find_or_make (name
);
3498 if (unwind
.proc_start
== 0)
3500 unwind
.proc_start
= sym
;
3502 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3505 if (*input_line_pointer
!= ',')
3507 ++input_line_pointer
;
3509 demand_empty_rest_of_line ();
3512 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3513 unwind
.personality_routine
= 0;
3520 unwind
.prologue
= 0;
3521 unwind
.prologue_mask
= 0;
3523 add_unwind_entry (output_body ());
3524 demand_empty_rest_of_line ();
3528 dot_prologue (dummy
)
3532 int mask
= 0, grsave
;
3534 if (!is_it_end_of_statement ())
3537 sep
= parse_operand (&e1
);
3539 as_bad ("No second operand to .prologue");
3540 sep
= parse_operand (&e2
);
3541 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3542 ignore_rest_of_line ();
3544 if (e1
.X_op
== O_constant
)
3546 mask
= e1
.X_add_number
;
3548 if (e2
.X_op
== O_constant
)
3549 grsave
= e2
.X_add_number
;
3550 else if (e2
.X_op
== O_register
3551 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3554 as_bad ("Second operand not a constant or general register");
3556 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3559 as_bad ("First operand not a constant");
3562 add_unwind_entry (output_prologue ());
3564 unwind
.prologue
= 1;
3565 unwind
.prologue_mask
= mask
;
3576 subsegT saved_subseg
;
3578 saved_seg
= now_seg
;
3579 saved_subseg
= now_subseg
;
3582 demand_empty_rest_of_line ();
3584 insn_group_break (1, 0, 0);
3586 /* If there was a .handlerdata, we haven't generated an image yet. */
3587 if (unwind
.info
== 0)
3589 generate_unwind_image ();
3592 subseg_set (md
.last_text_seg
, 0);
3593 unwind
.proc_end
= expr_build_dot ();
3595 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3596 ptr
= frag_more (24);
3597 where
= frag_now_fix () - 24;
3599 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3600 e
.X_op
= O_pseudo_fixup
;
3601 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3603 e
.X_add_symbol
= unwind
.proc_start
;
3604 ia64_cons_fix_new (frag_now
, where
, 8, &e
);
3606 e
.X_op
= O_pseudo_fixup
;
3607 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3609 e
.X_add_symbol
= unwind
.proc_end
;
3610 ia64_cons_fix_new (frag_now
, where
+ 8, 8, &e
);
3612 if (unwind
.info
!= 0)
3614 e
.X_op
= O_pseudo_fixup
;
3615 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3617 e
.X_add_symbol
= unwind
.info
;
3618 ia64_cons_fix_new (frag_now
, where
+ 16, 8, &e
);
3621 md_number_to_chars (ptr
+ 16, 0, 8);
3623 subseg_set (saved_seg
, saved_subseg
);
3624 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3628 dot_template (template)
3631 CURR_SLOT
.user_template
= template;
3638 int ins
, locs
, outs
, rots
;
3640 if (is_it_end_of_statement ())
3641 ins
= locs
= outs
= rots
= 0;
3644 ins
= get_absolute_expression ();
3645 if (*input_line_pointer
++ != ',')
3647 locs
= get_absolute_expression ();
3648 if (*input_line_pointer
++ != ',')
3650 outs
= get_absolute_expression ();
3651 if (*input_line_pointer
++ != ',')
3653 rots
= get_absolute_expression ();
3655 set_regstack (ins
, locs
, outs
, rots
);
3659 as_bad ("Comma expected");
3660 ignore_rest_of_line ();
3667 unsigned num_regs
, num_alloced
= 0;
3668 struct dynreg
**drpp
, *dr
;
3669 int ch
, base_reg
= 0;
3675 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3676 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3677 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3681 /* first, remove existing names from hash table: */
3682 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3684 hash_delete (md
.dynreg_hash
, dr
->name
);
3688 drpp
= &md
.dynreg
[type
];
3691 start
= input_line_pointer
;
3692 ch
= get_symbol_end ();
3693 *input_line_pointer
= ch
;
3694 len
= (input_line_pointer
- start
);
3697 if (*input_line_pointer
!= '[')
3699 as_bad ("Expected '['");
3702 ++input_line_pointer
; /* skip '[' */
3704 num_regs
= get_absolute_expression ();
3706 if (*input_line_pointer
++ != ']')
3708 as_bad ("Expected ']'");
3713 num_alloced
+= num_regs
;
3717 if (num_alloced
> md
.rot
.num_regs
)
3719 as_bad ("Used more than the declared %d rotating registers",
3725 if (num_alloced
> 96)
3727 as_bad ("Used more than the available 96 rotating registers");
3732 if (num_alloced
> 48)
3734 as_bad ("Used more than the available 48 rotating registers");
3743 name
= obstack_alloc (¬es
, len
+ 1);
3744 memcpy (name
, start
, len
);
3749 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3750 memset (*drpp
, 0, sizeof (*dr
));
3755 dr
->num_regs
= num_regs
;
3756 dr
->base
= base_reg
;
3758 base_reg
+= num_regs
;
3760 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3762 as_bad ("Attempt to redefine register set `%s'", name
);
3766 if (*input_line_pointer
!= ',')
3768 ++input_line_pointer
; /* skip comma */
3771 demand_empty_rest_of_line ();
3775 ignore_rest_of_line ();
3779 dot_byteorder (byteorder
)
3782 target_big_endian
= byteorder
;
3794 option
= input_line_pointer
;
3795 ch
= get_symbol_end ();
3796 if (strcmp (option
, "lsb") == 0)
3797 md
.flags
&= ~EF_IA_64_BE
;
3798 else if (strcmp (option
, "msb") == 0)
3799 md
.flags
|= EF_IA_64_BE
;
3800 else if (strcmp (option
, "abi32") == 0)
3801 md
.flags
&= ~EF_IA_64_ABI64
;
3802 else if (strcmp (option
, "abi64") == 0)
3803 md
.flags
|= EF_IA_64_ABI64
;
3805 as_bad ("Unknown psr option `%s'", option
);
3806 *input_line_pointer
= ch
;
3809 if (*input_line_pointer
!= ',')
3812 ++input_line_pointer
;
3815 demand_empty_rest_of_line ();
3822 as_bad (".alias not implemented yet");
3829 new_logical_line (0, get_absolute_expression ());
3830 demand_empty_rest_of_line ();
3834 parse_section_name ()
3840 if (*input_line_pointer
!= '"')
3842 as_bad ("Missing section name");
3843 ignore_rest_of_line ();
3846 name
= demand_copy_C_string (&len
);
3849 ignore_rest_of_line ();
3853 if (*input_line_pointer
!= ',')
3855 as_bad ("Comma expected after section name");
3856 ignore_rest_of_line ();
3859 ++input_line_pointer
; /* skip comma */
3867 char *name
= parse_section_name ();
3873 obj_elf_previous (0);
3876 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3878 stmt_float_cons (kind
)
3885 case 'd': size
= 8; break;
3886 case 'x': size
= 10; break;
3893 ia64_do_align (size
);
3901 int saved_auto_align
= md
.auto_align
;
3905 md
.auto_align
= saved_auto_align
;
3909 dot_xfloat_cons (kind
)
3912 char *name
= parse_section_name ();
3917 stmt_float_cons (kind
);
3918 obj_elf_previous (0);
3922 dot_xstringer (zero
)
3925 char *name
= parse_section_name ();
3931 obj_elf_previous (0);
3938 int saved_auto_align
= md
.auto_align
;
3939 char *name
= parse_section_name ();
3946 md
.auto_align
= saved_auto_align
;
3947 obj_elf_previous (0);
3951 dot_xfloat_cons_ua (kind
)
3954 int saved_auto_align
= md
.auto_align
;
3955 char *name
= parse_section_name ();
3961 stmt_float_cons (kind
);
3962 md
.auto_align
= saved_auto_align
;
3963 obj_elf_previous (0);
3966 /* .reg.val <regname>,value */
3974 if (reg
.X_op
!= O_register
)
3976 as_bad (_("Register name expected"));
3977 ignore_rest_of_line ();
3979 else if (*input_line_pointer
++ != ',')
3981 as_bad (_("Comma expected"));
3982 ignore_rest_of_line ();
3986 valueT value
= get_absolute_expression ();
3987 int regno
= reg
.X_add_number
;
3988 if (regno
< REG_GR
|| regno
> REG_GR
+128)
3989 as_warn (_("Register value annotation ignored"));
3992 gr_values
[regno
-REG_GR
].known
= 1;
3993 gr_values
[regno
-REG_GR
].value
= value
;
3994 gr_values
[regno
-REG_GR
].path
= md
.path
;
3997 demand_empty_rest_of_line ();
4000 /* select dv checking mode
4005 A stop is inserted when changing modes
4011 if (md
.manual_bundling
)
4012 as_warn (_("Directive invalid within a bundle"));
4014 if (type
== 'E' || type
== 'A')
4015 md
.mode_explicitly_set
= 0;
4017 md
.mode_explicitly_set
= 1;
4024 if (md
.explicit_mode
)
4025 insn_group_break (1, 0, 0);
4026 md
.explicit_mode
= 0;
4030 if (!md
.explicit_mode
)
4031 insn_group_break (1, 0, 0);
4032 md
.explicit_mode
= 1;
4036 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4037 insn_group_break (1, 0, 0);
4038 md
.explicit_mode
= md
.default_explicit_mode
;
4039 md
.mode_explicitly_set
= 0;
4050 for (regno
= 0;regno
< 64;regno
++)
4052 if (mask
& ((valueT
) 1<<regno
))
4054 fprintf (stderr
, "%s p%d", comma
, regno
);
4061 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4062 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4063 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4064 .pred.safe_across_calls p1 [, p2 [,...]]
4072 int p1
= -1, p2
= -1;
4076 if (*input_line_pointer
!= '"')
4078 as_bad (_("Missing predicate relation type"));
4079 ignore_rest_of_line ();
4085 char *form
= demand_copy_C_string (&len
);
4086 if (strcmp (form
, "mutex") == 0)
4088 else if (strcmp (form
, "clear") == 0)
4090 else if (strcmp (form
, "imply") == 0)
4094 as_bad (_("Unrecognized predicate relation type"));
4095 ignore_rest_of_line ();
4099 if (*input_line_pointer
== ',')
4100 ++input_line_pointer
;
4110 if (toupper (*input_line_pointer
) != 'P'
4111 || (regno
= atoi (++input_line_pointer
)) < 0
4114 as_bad (_("Predicate register expected"));
4115 ignore_rest_of_line ();
4118 while (isdigit (*input_line_pointer
))
4119 ++input_line_pointer
;
4126 as_warn (_("Duplicate predicate register ignored"));
4127 mask
|= bit
; count
++;
4128 /* see if it's a range */
4129 if (*input_line_pointer
== '-')
4132 ++input_line_pointer
;
4134 if (toupper (*input_line_pointer
) != 'P'
4135 || (regno
= atoi (++input_line_pointer
)) < 0
4138 as_bad (_("Predicate register expected"));
4139 ignore_rest_of_line ();
4142 while (isdigit (*input_line_pointer
))
4143 ++input_line_pointer
;
4147 as_bad (_("Bad register range"));
4148 ignore_rest_of_line ();
4154 mask
|= bit
; count
++;
4158 if (*input_line_pointer
!= ',')
4160 ++input_line_pointer
;
4169 clear_qp_mutex (mask
);
4170 clear_qp_implies (mask
, (valueT
) 0);
4173 if (count
!= 2 || p1
== -1 || p2
== -1)
4174 as_bad (_("Predicate source and target required"));
4175 else if (p1
== 0 || p2
== 0)
4176 as_bad (_("Use of p0 is not valid in this context"));
4178 add_qp_imply (p1
, p2
);
4183 as_bad (_("At least two PR arguments expected"));
4188 as_bad (_("Use of p0 is not valid in this context"));
4191 add_qp_mutex (mask
);
4194 /* note that we don't override any existing relations */
4197 as_bad (_("At least one PR argument expected"));
4202 fprintf (stderr
, "Safe across calls: ");
4203 print_prmask (mask
);
4204 fprintf (stderr
, "\n");
4206 qp_safe_across_calls
= mask
;
4209 demand_empty_rest_of_line ();
4212 /* .entry label [, label [, ...]]
4213 Hint to DV code that the given labels are to be considered entry points.
4214 Otherwise, only global labels are considered entry points.
4227 name
= input_line_pointer
;
4228 c
= get_symbol_end ();
4229 symbolP
= symbol_find_or_make (name
);
4231 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4233 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4236 *input_line_pointer
= c
;
4238 c
= *input_line_pointer
;
4241 input_line_pointer
++;
4243 if (*input_line_pointer
== '\n')
4249 demand_empty_rest_of_line ();
4252 /* .mem.offset offset, base
4253 "base" is used to distinguish between offsets from a different base.
4256 dot_mem_offset (dummy
)
4259 md
.mem_offset
.hint
= 1;
4260 md
.mem_offset
.offset
= get_absolute_expression ();
4261 if (*input_line_pointer
!= ',')
4263 as_bad (_("Comma expected"));
4264 ignore_rest_of_line ();
4267 ++input_line_pointer
;
4268 md
.mem_offset
.base
= get_absolute_expression ();
4269 demand_empty_rest_of_line ();
4272 /* ia64-specific pseudo-ops: */
4273 const pseudo_typeS md_pseudo_table
[] =
4275 { "radix", dot_radix
, 0 },
4276 { "lcomm", s_lcomm_bytes
, 1 },
4277 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4278 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4279 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4280 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4281 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4282 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4283 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4284 { "proc", dot_proc
, 0 },
4285 { "body", dot_body
, 0 },
4286 { "prologue", dot_prologue
, 0 },
4287 { "endp", dot_endp
},
4288 { "file", dwarf2_directive_file
},
4289 { "loc", dwarf2_directive_loc
},
4291 { "fframe", dot_fframe
},
4292 { "vframe", dot_vframe
},
4293 { "vframesp", dot_vframesp
},
4294 { "vframepsp", dot_vframepsp
},
4295 { "save", dot_save
},
4296 { "restore", dot_restore
},
4297 { "restorereg", dot_restorereg
},
4298 { "restorereg.p", dot_restorereg_p
},
4299 { "handlerdata", dot_handlerdata
},
4300 { "unwentry", dot_unwentry
},
4301 { "altrp", dot_altrp
},
4302 { "savesp", dot_savemem
, 0 },
4303 { "savepsp", dot_savemem
, 1 },
4304 { "save.g", dot_saveg
},
4305 { "save.f", dot_savef
},
4306 { "save.b", dot_saveb
},
4307 { "save.gf", dot_savegf
},
4308 { "spill", dot_spill
},
4309 { "spillreg", dot_spillreg
},
4310 { "spillsp", dot_spillmem
, 0 },
4311 { "spillpsp", dot_spillmem
, 1 },
4312 { "spillreg.p", dot_spillreg_p
},
4313 { "spillsp.p", dot_spillmem_p
, 0 },
4314 { "spillpsp.p", dot_spillmem_p
, 1 },
4315 { "label_state", dot_label_state
},
4316 { "copy_state", dot_copy_state
},
4317 { "unwabi", dot_unwabi
},
4318 { "personality", dot_personality
},
4320 { "estate", dot_estate
},
4322 { "mii", dot_template
, 0x0 },
4323 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4324 { "mlx", dot_template
, 0x2 },
4325 { "mmi", dot_template
, 0x4 },
4326 { "mfi", dot_template
, 0x6 },
4327 { "mmf", dot_template
, 0x7 },
4328 { "mib", dot_template
, 0x8 },
4329 { "mbb", dot_template
, 0x9 },
4330 { "bbb", dot_template
, 0xb },
4331 { "mmb", dot_template
, 0xc },
4332 { "mfb", dot_template
, 0xe },
4334 { "lb", dot_scope
, 0 },
4335 { "le", dot_scope
, 1 },
4337 { "align", s_align_bytes
, 0 },
4338 { "regstk", dot_regstk
, 0 },
4339 { "rotr", dot_rot
, DYNREG_GR
},
4340 { "rotf", dot_rot
, DYNREG_FR
},
4341 { "rotp", dot_rot
, DYNREG_PR
},
4342 { "lsb", dot_byteorder
, 0 },
4343 { "msb", dot_byteorder
, 1 },
4344 { "psr", dot_psr
, 0 },
4345 { "alias", dot_alias
, 0 },
4346 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4348 { "xdata1", dot_xdata
, 1 },
4349 { "xdata2", dot_xdata
, 2 },
4350 { "xdata4", dot_xdata
, 4 },
4351 { "xdata8", dot_xdata
, 8 },
4352 { "xreal4", dot_xfloat_cons
, 'f' },
4353 { "xreal8", dot_xfloat_cons
, 'd' },
4354 { "xreal10", dot_xfloat_cons
, 'x' },
4355 { "xstring", dot_xstringer
, 0 },
4356 { "xstringz", dot_xstringer
, 1 },
4358 /* unaligned versions: */
4359 { "xdata2.ua", dot_xdata_ua
, 2 },
4360 { "xdata4.ua", dot_xdata_ua
, 4 },
4361 { "xdata8.ua", dot_xdata_ua
, 8 },
4362 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4363 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4364 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4366 /* annotations/DV checking support */
4367 { "entry", dot_entry
, 0 },
4368 { "mem.offset", dot_mem_offset
},
4369 { "pred.rel", dot_pred_rel
, 0 },
4370 { "pred.rel.clear", dot_pred_rel
, 'c' },
4371 { "pred.rel.imply", dot_pred_rel
, 'i' },
4372 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4373 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4374 { "reg.val", dot_reg_val
},
4375 { "auto", dot_dv_mode
, 'a' },
4376 { "explicit", dot_dv_mode
, 'e' },
4377 { "default", dot_dv_mode
, 'd' },
4382 static const struct pseudo_opcode
4385 void (*handler
) (int);
4390 /* these are more like pseudo-ops, but don't start with a dot */
4391 { "data1", cons
, 1 },
4392 { "data2", cons
, 2 },
4393 { "data4", cons
, 4 },
4394 { "data8", cons
, 8 },
4395 { "real4", stmt_float_cons
, 'f' },
4396 { "real8", stmt_float_cons
, 'd' },
4397 { "real10", stmt_float_cons
, 'x' },
4398 { "string", stringer
, 0 },
4399 { "stringz", stringer
, 1 },
4401 /* unaligned versions: */
4402 { "data2.ua", stmt_cons_ua
, 2 },
4403 { "data4.ua", stmt_cons_ua
, 4 },
4404 { "data8.ua", stmt_cons_ua
, 8 },
4405 { "real4.ua", float_cons
, 'f' },
4406 { "real8.ua", float_cons
, 'd' },
4407 { "real10.ua", float_cons
, 'x' },
4410 /* Declare a register by creating a symbol for it and entering it in
4411 the symbol table. */
4413 declare_register (name
, regnum
)
4420 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4422 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4424 as_fatal ("Inserting \"%s\" into register table failed: %s",
4431 declare_register_set (prefix
, num_regs
, base_regnum
)
4439 for (i
= 0; i
< num_regs
; ++i
)
4441 sprintf (name
, "%s%u", prefix
, i
);
4442 declare_register (name
, base_regnum
+ i
);
4447 operand_width (opnd
)
4448 enum ia64_opnd opnd
;
4450 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4451 unsigned int bits
= 0;
4455 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4456 bits
+= odesc
->field
[i
].bits
;
4462 operand_match (idesc
, index
, e
)
4463 const struct ia64_opcode
*idesc
;
4467 enum ia64_opnd opnd
= idesc
->operands
[index
];
4468 int bits
, relocatable
= 0;
4469 struct insn_fix
*fix
;
4476 case IA64_OPND_AR_CCV
:
4477 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4481 case IA64_OPND_AR_PFS
:
4482 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4487 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4492 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4497 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4501 case IA64_OPND_PR_ROT
:
4502 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4507 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4511 case IA64_OPND_PSR_L
:
4512 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4516 case IA64_OPND_PSR_UM
:
4517 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4522 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4527 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4532 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4536 /* register operands: */
4539 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4540 && e
->X_add_number
< REG_AR
+ 128)
4546 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4547 && e
->X_add_number
< REG_BR
+ 8)
4552 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4553 && e
->X_add_number
< REG_CR
+ 128)
4561 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4562 && e
->X_add_number
< REG_FR
+ 128)
4568 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4569 && e
->X_add_number
< REG_P
+ 64)
4576 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4577 && e
->X_add_number
< REG_GR
+ 128)
4581 case IA64_OPND_R3_2
:
4582 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4583 && e
->X_add_number
< REG_GR
+ 4)
4587 /* indirect operands: */
4588 case IA64_OPND_CPUID_R3
:
4589 case IA64_OPND_DBR_R3
:
4590 case IA64_OPND_DTR_R3
:
4591 case IA64_OPND_ITR_R3
:
4592 case IA64_OPND_IBR_R3
:
4593 case IA64_OPND_MSR_R3
:
4594 case IA64_OPND_PKR_R3
:
4595 case IA64_OPND_PMC_R3
:
4596 case IA64_OPND_PMD_R3
:
4597 case IA64_OPND_RR_R3
:
4598 if (e
->X_op
== O_index
&& e
->X_op_symbol
4599 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4600 == opnd
- IA64_OPND_CPUID_R3
))
4605 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4609 /* immediate operands: */
4610 case IA64_OPND_CNT2a
:
4611 case IA64_OPND_LEN4
:
4612 case IA64_OPND_LEN6
:
4613 bits
= operand_width (idesc
->operands
[index
]);
4614 if (e
->X_op
== O_constant
4615 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4619 case IA64_OPND_CNT2b
:
4620 if (e
->X_op
== O_constant
4621 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4625 case IA64_OPND_CNT2c
:
4626 val
= e
->X_add_number
;
4627 if (e
->X_op
== O_constant
4628 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4633 /* SOR must be an integer multiple of 8 */
4634 if (e
->X_add_number
& 0x7)
4638 if (e
->X_op
== O_constant
&&
4639 (bfd_vma
) e
->X_add_number
<= 96)
4643 case IA64_OPND_IMMU62
:
4644 if (e
->X_op
== O_constant
)
4646 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4651 /* FIXME -- need 62-bit relocation type */
4652 as_bad (_("62-bit relocation not yet implemented"));
4656 case IA64_OPND_IMMU64
:
4657 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4658 || e
->X_op
== O_subtract
)
4660 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4661 fix
->code
= BFD_RELOC_IA64_IMM64
;
4662 if (e
->X_op
!= O_subtract
)
4664 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4665 if (e
->X_op
== O_pseudo_fixup
)
4669 fix
->opnd
= idesc
->operands
[index
];
4672 ++CURR_SLOT
.num_fixups
;
4675 else if (e
->X_op
== O_constant
)
4679 case IA64_OPND_CCNT5
:
4680 case IA64_OPND_CNT5
:
4681 case IA64_OPND_CNT6
:
4682 case IA64_OPND_CPOS6a
:
4683 case IA64_OPND_CPOS6b
:
4684 case IA64_OPND_CPOS6c
:
4685 case IA64_OPND_IMMU2
:
4686 case IA64_OPND_IMMU7a
:
4687 case IA64_OPND_IMMU7b
:
4688 case IA64_OPND_IMMU21
:
4689 case IA64_OPND_IMMU24
:
4690 case IA64_OPND_MBTYPE4
:
4691 case IA64_OPND_MHTYPE8
:
4692 case IA64_OPND_POS6
:
4693 bits
= operand_width (idesc
->operands
[index
]);
4694 if (e
->X_op
== O_constant
4695 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4699 case IA64_OPND_IMMU9
:
4700 bits
= operand_width (idesc
->operands
[index
]);
4701 if (e
->X_op
== O_constant
4702 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4704 int lobits
= e
->X_add_number
& 0x3;
4705 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4706 e
->X_add_number
|= (bfd_vma
) 0x3;
4711 case IA64_OPND_IMM44
:
4712 /* least 16 bits must be zero */
4713 if ((e
->X_add_number
& 0xffff) != 0)
4714 as_warn (_("lower 16 bits of mask ignored"));
4716 if (e
->X_op
== O_constant
4717 && ((e
->X_add_number
>= 0
4718 && e
->X_add_number
< ((bfd_vma
) 1 << 44))
4719 || (e
->X_add_number
< 0
4720 && -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4723 if (e
->X_add_number
>= 0
4724 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4726 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4732 case IA64_OPND_IMM17
:
4733 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4734 if (e
->X_op
== O_constant
4735 && ((e
->X_add_number
>= 0
4736 && e
->X_add_number
< ((bfd_vma
) 1 << 17))
4737 || (e
->X_add_number
< 0
4738 && -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4741 if (e
->X_add_number
>= 0
4742 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4744 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
4750 case IA64_OPND_IMM14
:
4751 case IA64_OPND_IMM22
:
4753 case IA64_OPND_IMM1
:
4754 case IA64_OPND_IMM8
:
4755 case IA64_OPND_IMM8U4
:
4756 case IA64_OPND_IMM8M1
:
4757 case IA64_OPND_IMM8M1U4
:
4758 case IA64_OPND_IMM8M1U8
:
4759 case IA64_OPND_IMM9a
:
4760 case IA64_OPND_IMM9b
:
4761 bits
= operand_width (idesc
->operands
[index
]);
4762 if (relocatable
&& (e
->X_op
== O_symbol
4763 || e
->X_op
== O_subtract
4764 || e
->X_op
== O_pseudo_fixup
))
4766 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4768 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4769 fix
->code
= BFD_RELOC_IA64_IMM14
;
4771 fix
->code
= BFD_RELOC_IA64_IMM22
;
4773 if (e
->X_op
!= O_subtract
)
4775 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4776 if (e
->X_op
== O_pseudo_fixup
)
4780 fix
->opnd
= idesc
->operands
[index
];
4783 ++CURR_SLOT
.num_fixups
;
4786 else if (e
->X_op
!= O_constant
4787 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4790 if (opnd
== IA64_OPND_IMM8M1U4
)
4792 /* Zero is not valid for unsigned compares that take an adjusted
4793 constant immediate range. */
4794 if (e
->X_add_number
== 0)
4797 /* Sign-extend 32-bit unsigned numbers, so that the following range
4798 checks will work. */
4799 val
= e
->X_add_number
;
4800 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4801 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4802 val
= ((val
<< 32) >> 32);
4804 /* Check for 0x100000000. This is valid because
4805 0x100000000-1 is the same as ((uint32_t) -1). */
4806 if (val
== ((bfd_signed_vma
) 1 << 32))
4811 else if (opnd
== IA64_OPND_IMM8M1U8
)
4813 /* Zero is not valid for unsigned compares that take an adjusted
4814 constant immediate range. */
4815 if (e
->X_add_number
== 0)
4818 /* Check for 0x10000000000000000. */
4819 if (e
->X_op
== O_big
)
4821 if (generic_bignum
[0] == 0
4822 && generic_bignum
[1] == 0
4823 && generic_bignum
[2] == 0
4824 && generic_bignum
[3] == 0
4825 && generic_bignum
[4] == 1)
4831 val
= e
->X_add_number
- 1;
4833 else if (opnd
== IA64_OPND_IMM8M1
)
4834 val
= e
->X_add_number
- 1;
4835 else if (opnd
== IA64_OPND_IMM8U4
)
4837 /* Sign-extend 32-bit unsigned numbers, so that the following range
4838 checks will work. */
4839 val
= e
->X_add_number
;
4840 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4841 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4842 val
= ((val
<< 32) >> 32);
4845 val
= e
->X_add_number
;
4847 if ((val
>= 0 && val
< ((bfd_vma
) 1 << (bits
- 1)))
4848 || (val
< 0 && -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4852 case IA64_OPND_INC3
:
4853 /* +/- 1, 4, 8, 16 */
4854 val
= e
->X_add_number
;
4857 if (e
->X_op
== O_constant
4858 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4862 case IA64_OPND_TGT25
:
4863 case IA64_OPND_TGT25b
:
4864 case IA64_OPND_TGT25c
:
4865 case IA64_OPND_TGT64
:
4866 if (e
->X_op
== O_symbol
)
4868 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4869 if (opnd
== IA64_OPND_TGT25
)
4870 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4871 else if (opnd
== IA64_OPND_TGT25b
)
4872 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4873 else if (opnd
== IA64_OPND_TGT25c
)
4874 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4875 else if (opnd
== IA64_OPND_TGT64
)
4876 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
4880 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4881 fix
->opnd
= idesc
->operands
[index
];
4884 ++CURR_SLOT
.num_fixups
;
4887 case IA64_OPND_TAG13
:
4888 case IA64_OPND_TAG13b
:
4895 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4896 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
4897 fix
->opnd
= idesc
->operands
[index
];
4900 ++CURR_SLOT
.num_fixups
;
4920 memset (e
, 0, sizeof (*e
));
4923 if (*input_line_pointer
!= '}')
4925 sep
= *input_line_pointer
++;
4929 if (!md
.manual_bundling
)
4930 as_warn ("Found '}' when manual bundling is off");
4932 CURR_SLOT
.manual_bundling_off
= 1;
4933 md
.manual_bundling
= 0;
4939 /* Returns the next entry in the opcode table that matches the one in
4940 IDESC, and frees the entry in IDESC. If no matching entry is
4941 found, NULL is returned instead. */
4943 static struct ia64_opcode
*
4944 get_next_opcode (struct ia64_opcode
*idesc
)
4946 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
4947 ia64_free_opcode (idesc
);
4951 /* Parse the operands for the opcode and find the opcode variant that
4952 matches the specified operands, or NULL if no match is possible. */
4953 static struct ia64_opcode
*
4954 parse_operands (idesc
)
4955 struct ia64_opcode
*idesc
;
4957 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
4959 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
4961 char *first_arg
= 0, *end
, *saved_input_pointer
;
4964 assert (strlen (idesc
->name
) <= 128);
4966 strcpy (mnemonic
, idesc
->name
);
4967 if (idesc
->operands
[2] == IA64_OPND_SOF
)
4969 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4970 can't parse the first operand until we have parsed the
4971 remaining operands of the "alloc" instruction. */
4973 first_arg
= input_line_pointer
;
4974 end
= strchr (input_line_pointer
, '=');
4977 as_bad ("Expected separator `='");
4980 input_line_pointer
= end
+ 1;
4985 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
4987 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
4988 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
4993 if (sep
!= '=' && sep
!= ',')
4998 if (num_outputs
> 0)
4999 as_bad ("Duplicate equal sign (=) in instruction");
5001 num_outputs
= i
+ 1;
5006 as_bad ("Illegal operand separator `%c'", sep
);
5010 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5012 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5013 know (strcmp (idesc
->name
, "alloc") == 0);
5014 if (num_operands
== 5 /* first_arg not included in this count! */
5015 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5016 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5017 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5018 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5020 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5021 CURR_SLOT
.opnd
[3].X_add_number
,
5022 CURR_SLOT
.opnd
[4].X_add_number
,
5023 CURR_SLOT
.opnd
[5].X_add_number
);
5025 /* now we can parse the first arg: */
5026 saved_input_pointer
= input_line_pointer
;
5027 input_line_pointer
= first_arg
;
5028 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5030 --num_outputs
; /* force error */
5031 input_line_pointer
= saved_input_pointer
;
5033 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5034 CURR_SLOT
.opnd
[3].X_add_number
5035 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5036 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5040 highest_unmatched_operand
= 0;
5041 expected_operand
= idesc
->operands
[0];
5042 for (; idesc
; idesc
= get_next_opcode (idesc
))
5044 if (num_outputs
!= idesc
->num_outputs
)
5045 continue; /* mismatch in # of outputs */
5047 CURR_SLOT
.num_fixups
= 0;
5048 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5049 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5052 if (i
!= num_operands
)
5054 if (i
> highest_unmatched_operand
)
5056 highest_unmatched_operand
= i
;
5057 expected_operand
= idesc
->operands
[i
];
5062 if (num_operands
< NELEMS (idesc
->operands
)
5063 && idesc
->operands
[num_operands
])
5064 continue; /* mismatch in number of arguments */
5070 if (expected_operand
)
5071 as_bad ("Operand %u of `%s' should be %s",
5072 highest_unmatched_operand
+ 1, mnemonic
,
5073 elf64_ia64_operands
[expected_operand
].desc
);
5075 as_bad ("Operand mismatch");
5082 build_insn (slot
, insnp
)
5086 const struct ia64_operand
*odesc
, *o2desc
;
5087 struct ia64_opcode
*idesc
= slot
->idesc
;
5088 bfd_signed_vma insn
, val
;
5092 insn
= idesc
->opcode
| slot
->qp_regno
;
5094 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5096 if (slot
->opnd
[i
].X_op
== O_register
5097 || slot
->opnd
[i
].X_op
== O_constant
5098 || slot
->opnd
[i
].X_op
== O_index
)
5099 val
= slot
->opnd
[i
].X_add_number
;
5100 else if (slot
->opnd
[i
].X_op
== O_big
)
5102 /* This must be the value 0x10000000000000000. */
5103 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5109 switch (idesc
->operands
[i
])
5111 case IA64_OPND_IMMU64
:
5112 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5113 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5114 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5115 | (((val
>> 63) & 0x1) << 36));
5118 case IA64_OPND_IMMU62
:
5119 val
&= 0x3fffffffffffffffULL
;
5120 if (val
!= slot
->opnd
[i
].X_add_number
)
5121 as_warn (_("Value truncated to 62 bits"));
5122 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5123 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5126 case IA64_OPND_TGT64
:
5128 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5129 insn
|= ((((val
>> 59) & 0x1) << 36)
5130 | (((val
>> 0) & 0xfffff) << 13));
5161 case IA64_OPND_R3_2
:
5162 case IA64_OPND_CPUID_R3
:
5163 case IA64_OPND_DBR_R3
:
5164 case IA64_OPND_DTR_R3
:
5165 case IA64_OPND_ITR_R3
:
5166 case IA64_OPND_IBR_R3
:
5168 case IA64_OPND_MSR_R3
:
5169 case IA64_OPND_PKR_R3
:
5170 case IA64_OPND_PMC_R3
:
5171 case IA64_OPND_PMD_R3
:
5172 case IA64_OPND_RR_R3
:
5180 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5181 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5183 as_bad_where (slot
->src_file
, slot
->src_line
,
5184 "Bad operand value: %s", err
);
5185 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5187 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5188 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5190 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5191 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5193 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5194 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5195 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5197 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5198 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5208 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5209 unsigned int manual_bundling
= 0;
5210 enum ia64_unit required_unit
, insn_unit
= 0;
5211 enum ia64_insn_type type
[3], insn_type
;
5212 unsigned int template, orig_template
;
5213 bfd_vma insn
[3] = {-1, -1, -1};
5214 struct ia64_opcode
*idesc
;
5215 int end_of_insn_group
= 0, user_template
= -1;
5216 int n
, i
, j
, first
, curr
;
5217 unw_rec_list
*ptr
, *prev
;
5218 bfd_vma t0
= 0, t1
= 0;
5219 struct label_fix
*lfix
;
5220 struct insn_fix
*ifix
;
5225 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5226 know (first
>= 0 & first
< NUM_SLOTS
);
5227 n
= MIN (3, md
.num_slots_in_use
);
5229 /* Determine template: user user_template if specified, best match
5232 if (md
.slot
[first
].user_template
>= 0)
5233 user_template
= template = md
.slot
[first
].user_template
;
5236 /* auto select appropriate template */
5237 memset (type
, 0, sizeof (type
));
5239 for (i
= 0; i
< n
; ++i
)
5241 type
[i
] = md
.slot
[curr
].idesc
->type
;
5242 curr
= (curr
+ 1) % NUM_SLOTS
;
5244 template = best_template
[type
[0]][type
[1]][type
[2]];
5247 /* initialize instructions with appropriate nops: */
5248 for (i
= 0; i
< 3; ++i
)
5249 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5253 /* now fill in slots with as many insns as possible: */
5255 idesc
= md
.slot
[curr
].idesc
;
5256 end_of_insn_group
= 0;
5257 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5259 /* Set the slot number for prologue/body records now as those
5260 refer to the current point, not the point after the
5261 instruction has been issued: */
5262 /* Don't try to delete prologue/body records here, as that will cause
5263 them to also be deleted from the master list of unwind records. */
5264 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5265 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5266 || ptr
->r
.type
== body
)
5267 ptr
->slot_number
= (unsigned long) f
+ i
;
5269 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5271 if (manual_bundling
&& i
!= 2)
5272 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5273 "`%s' must be last in bundle", idesc
->name
);
5277 if (idesc
->flags
& IA64_OPCODE_LAST
)
5279 int required_slot
, required_template
;
5281 /* If we need a stop bit after an M slot, our only choice is
5282 template 5 (M;;MI). If we need a stop bit after a B
5283 slot, our only choice is to place it at the end of the
5284 bundle, because the only available templates are MIB,
5285 MBB, BBB, MMB, and MFB. We don't handle anything other
5286 than M and B slots because these are the only kind of
5287 instructions that can have the IA64_OPCODE_LAST bit set. */
5288 required_template
= template;
5289 switch (idesc
->type
)
5293 required_template
= 5;
5301 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5302 "Internal error: don't know how to force %s to end"
5303 "of instruction group", idesc
->name
);
5307 if (manual_bundling
&& i
!= required_slot
)
5308 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5309 "`%s' must be last in instruction group",
5311 if (required_slot
< i
)
5312 /* Can't fit this instruction. */
5316 if (required_template
!= template)
5318 /* If we switch the template, we need to reset the NOPs
5319 after slot i. The slot-types of the instructions ahead
5320 of i never change, so we don't need to worry about
5321 changing NOPs in front of this slot. */
5322 for (j
= i
; j
< 3; ++j
)
5323 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5325 template = required_template
;
5327 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5329 if (manual_bundling_on
)
5330 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5331 "Label must be first in a bundle");
5332 /* This insn must go into the first slot of a bundle. */
5336 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5337 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5339 if (manual_bundling_on
)
5342 manual_bundling
= 1;
5344 break; /* need to start a new bundle */
5347 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5349 /* We need an instruction group boundary in the middle of a
5350 bundle. See if we can switch to an other template with
5351 an appropriate boundary. */
5353 orig_template
= template;
5354 if (i
== 1 && (user_template
== 4
5355 || (user_template
< 0
5356 && (ia64_templ_desc
[template].exec_unit
[0]
5360 end_of_insn_group
= 0;
5362 else if (i
== 2 && (user_template
== 0
5363 || (user_template
< 0
5364 && (ia64_templ_desc
[template].exec_unit
[1]
5366 /* This test makes sure we don't switch the template if
5367 the next instruction is one that needs to be first in
5368 an instruction group. Since all those instructions are
5369 in the M group, there is no way such an instruction can
5370 fit in this bundle even if we switch the template. The
5371 reason we have to check for this is that otherwise we
5372 may end up generating "MI;;I M.." which has the deadly
5373 effect that the second M instruction is no longer the
5374 first in the bundle! --davidm 99/12/16 */
5375 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5378 end_of_insn_group
= 0;
5380 else if (curr
!= first
)
5381 /* can't fit this insn */
5384 if (template != orig_template
)
5385 /* if we switch the template, we need to reset the NOPs
5386 after slot i. The slot-types of the instructions ahead
5387 of i never change, so we don't need to worry about
5388 changing NOPs in front of this slot. */
5389 for (j
= i
; j
< 3; ++j
)
5390 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5392 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5394 /* resolve dynamic opcodes such as "break" and "nop": */
5395 if (idesc
->type
== IA64_TYPE_DYN
)
5397 if ((strcmp (idesc
->name
, "nop") == 0)
5398 || (strcmp (idesc
->name
, "break") == 0))
5399 insn_unit
= required_unit
;
5400 else if (strcmp (idesc
->name
, "chk.s") == 0)
5402 insn_unit
= IA64_UNIT_M
;
5403 if (required_unit
== IA64_UNIT_I
)
5404 insn_unit
= IA64_UNIT_I
;
5407 as_fatal ("emit_one_bundle: unexpected dynamic op");
5409 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5410 ia64_free_opcode (idesc
);
5411 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5413 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5418 insn_type
= idesc
->type
;
5419 insn_unit
= IA64_UNIT_NIL
;
5423 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5424 insn_unit
= required_unit
;
5426 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5427 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5428 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5429 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5430 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5435 if (insn_unit
!= required_unit
)
5437 if (required_unit
== IA64_UNIT_L
5438 && insn_unit
== IA64_UNIT_I
5439 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5441 /* we got ourselves an MLX template but the current
5442 instruction isn't an X-unit, or an I-unit instruction
5443 that can go into the X slot of an MLX template. Duh. */
5444 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5446 as_bad_where (md
.slot
[curr
].src_file
,
5447 md
.slot
[curr
].src_line
,
5448 "`%s' can't go in X slot of "
5449 "MLX template", idesc
->name
);
5450 /* drop this insn so we don't livelock: */
5451 --md
.num_slots_in_use
;
5455 continue; /* try next slot */
5458 if (debug_type
== DEBUG_DWARF2
)
5462 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + 1*i
;
5463 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5466 build_insn (md
.slot
+ curr
, insn
+ i
);
5468 /* Set slot counts for non prologue/body unwind records. */
5469 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5470 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5471 && ptr
->r
.type
!= body
)
5472 ptr
->slot_number
= (unsigned long) f
+ i
;
5473 md
.slot
[curr
].unwind_record
= NULL
;
5474 unwind
.next_slot_number
= (unsigned long) f
+ i
+ ((i
== 2)?(0x10-2):1);
5476 if (required_unit
== IA64_UNIT_L
)
5479 /* skip one slot for long/X-unit instructions */
5482 --md
.num_slots_in_use
;
5484 /* now is a good time to fix up the labels for this insn: */
5485 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5487 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5488 symbol_set_frag (lfix
->sym
, frag_now
);
5491 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5493 ifix
= md
.slot
[curr
].fixup
+ j
;
5494 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 4,
5495 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5496 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5497 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5498 fix
->fx_file
= md
.slot
[curr
].src_file
;
5499 fix
->fx_line
= md
.slot
[curr
].src_line
;
5502 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5505 ia64_free_opcode (md
.slot
[curr
].idesc
);
5506 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5507 md
.slot
[curr
].user_template
= -1;
5509 if (manual_bundling_off
)
5511 manual_bundling
= 0;
5514 curr
= (curr
+ 1) % NUM_SLOTS
;
5515 idesc
= md
.slot
[curr
].idesc
;
5517 if (manual_bundling
)
5519 if (md
.num_slots_in_use
> 0)
5520 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5521 "`%s' does not fit into %s template",
5522 idesc
->name
, ia64_templ_desc
[template].name
);
5524 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5525 "Missing '}' at end of file");
5527 know (md
.num_slots_in_use
< NUM_SLOTS
);
5529 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5530 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5532 md_number_to_chars (f
+ 0, t0
, 8);
5533 md_number_to_chars (f
+ 8, t1
, 8);
5537 md_parse_option (c
, arg
)
5543 /* Switches from the Intel assembler. */
5545 if (strcmp (arg
, "ilp64") == 0
5546 || strcmp (arg
, "lp64") == 0
5547 || strcmp (arg
, "p64") == 0)
5549 md
.flags
|= EF_IA_64_ABI64
;
5551 else if (strcmp (arg
, "ilp32") == 0)
5553 md
.flags
&= ~EF_IA_64_ABI64
;
5555 else if (strcmp (arg
, "le") == 0)
5557 md
.flags
&= ~EF_IA_64_BE
;
5559 else if (strcmp (arg
, "be") == 0)
5561 md
.flags
|= EF_IA_64_BE
;
5568 if (strcmp (arg
, "so") == 0)
5570 /* Suppress signon message. */
5572 else if (strcmp (arg
, "pi") == 0)
5574 /* Reject privileged instructions. FIXME */
5576 else if (strcmp (arg
, "us") == 0)
5578 /* Allow union of signed and unsigned range. FIXME */
5580 else if (strcmp (arg
, "close_fcalls") == 0)
5582 /* Do not resolve global function calls. */
5589 /* temp[="prefix"] Insert temporary labels into the object file
5590 symbol table prefixed by "prefix".
5591 Default prefix is ":temp:".
5596 /* ??? Conflicts with gas' listing option. */
5597 /* indirect=<tgt> Assume unannotated indirect branches behavior
5598 according to <tgt> --
5599 exit: branch out from the current context (default)
5600 labels: all labels in context may be branch targets
5605 /* -X conflicts with an ignored option, use -x instead */
5607 if (!arg
|| strcmp (arg
, "explicit") == 0)
5609 /* set default mode to explicit */
5610 md
.default_explicit_mode
= 1;
5613 else if (strcmp (arg
, "auto") == 0)
5615 md
.default_explicit_mode
= 0;
5617 else if (strcmp (arg
, "debug") == 0)
5621 else if (strcmp (arg
, "debugx") == 0)
5623 md
.default_explicit_mode
= 1;
5628 as_bad (_("Unrecognized option '-x%s'"), arg
);
5633 /* nops Print nops statistics. */
5636 /* GNU specific switches for gcc. */
5637 case OPTION_MCONSTANT_GP
:
5638 md
.flags
|= EF_IA_64_CONS_GP
;
5641 case OPTION_MAUTO_PIC
:
5642 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
5653 md_show_usage (stream
)
5658 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5659 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5660 -x | -xexplicit turn on dependency violation checking (default)\n\
5661 -xauto automagically remove dependency violations\n\
5662 -xdebug debug dependency violation checker\n"),
5666 /* Return true if TYPE fits in TEMPL at SLOT. */
5669 match (int templ
, int type
, int slot
)
5671 enum ia64_unit unit
;
5674 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5677 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5679 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5681 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5682 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5683 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5684 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5685 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5686 default: result
= 0; break;
5691 /* Add a bit of extra goodness if a nop of type F or B would fit
5692 in TEMPL at SLOT. */
5695 extra_goodness (int templ
, int slot
)
5697 if (match (templ
, IA64_TYPE_F
, slot
))
5699 if (match (templ
, IA64_TYPE_B
, slot
))
5704 /* This function is called once, at assembler startup time. It sets
5705 up all the tables, etc. that the MD part of the assembler will need
5706 that can be determined before arguments are parsed. */
5710 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
;
5715 md
.explicit_mode
= md
.default_explicit_mode
;
5717 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5719 target_big_endian
= 0;
5720 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5721 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5722 &zero_address_frag
);
5724 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5725 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5726 &zero_address_frag
);
5728 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5729 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5730 &zero_address_frag
);
5732 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5733 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5734 &zero_address_frag
);
5736 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5737 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5738 &zero_address_frag
);
5740 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5741 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5742 &zero_address_frag
);
5744 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5745 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5746 &zero_address_frag
);
5748 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5749 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5750 &zero_address_frag
);
5752 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5753 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5754 &zero_address_frag
);
5756 /* Compute the table of best templates. We compute goodness as a
5757 base 4 value, in which each match counts for 3, each F counts
5758 for 2, each B counts for 1. This should maximize the number of
5759 F and B nops in the chosen bundles, which is good because these
5760 pipelines are least likely to be overcommitted. */
5761 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
5762 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
5763 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
5766 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
5769 if (match (t
, i
, 0))
5771 if (match (t
, j
, 1))
5773 if (match (t
, k
, 2))
5774 goodness
= 3 + 3 + 3;
5776 goodness
= 3 + 3 + extra_goodness (t
, 2);
5778 else if (match (t
, j
, 2))
5779 goodness
= 3 + 3 + extra_goodness (t
, 1);
5783 goodness
+= extra_goodness (t
, 1);
5784 goodness
+= extra_goodness (t
, 2);
5787 else if (match (t
, i
, 1))
5789 if (match (t
, j
, 2))
5792 goodness
= 3 + extra_goodness (t
, 2);
5794 else if (match (t
, i
, 2))
5795 goodness
= 3 + extra_goodness (t
, 1);
5797 if (goodness
> best
)
5800 best_template
[i
][j
][k
] = t
;
5805 for (i
= 0; i
< NUM_SLOTS
; ++i
)
5806 md
.slot
[i
].user_template
= -1;
5808 md
.pseudo_hash
= hash_new ();
5809 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
5811 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
5812 (void *) (pseudo_opcode
+ i
));
5814 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5815 pseudo_opcode
[i
].name
, err
);
5818 md
.reg_hash
= hash_new ();
5819 md
.dynreg_hash
= hash_new ();
5820 md
.const_hash
= hash_new ();
5821 md
.entry_hash
= hash_new ();
5823 /* general registers: */
5826 for (i
= 0; i
< total
; ++i
)
5828 sprintf (name
, "r%d", i
- REG_GR
);
5829 md
.regsym
[i
] = declare_register (name
, i
);
5832 /* floating point registers: */
5834 for (; i
< total
; ++i
)
5836 sprintf (name
, "f%d", i
- REG_FR
);
5837 md
.regsym
[i
] = declare_register (name
, i
);
5840 /* application registers: */
5843 for (; i
< total
; ++i
)
5845 sprintf (name
, "ar%d", i
- REG_AR
);
5846 md
.regsym
[i
] = declare_register (name
, i
);
5849 /* control registers: */
5852 for (; i
< total
; ++i
)
5854 sprintf (name
, "cr%d", i
- REG_CR
);
5855 md
.regsym
[i
] = declare_register (name
, i
);
5858 /* predicate registers: */
5860 for (; i
< total
; ++i
)
5862 sprintf (name
, "p%d", i
- REG_P
);
5863 md
.regsym
[i
] = declare_register (name
, i
);
5866 /* branch registers: */
5868 for (; i
< total
; ++i
)
5870 sprintf (name
, "b%d", i
- REG_BR
);
5871 md
.regsym
[i
] = declare_register (name
, i
);
5874 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
5875 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
5876 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
5877 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
5878 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
5879 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
5880 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
5882 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
5884 regnum
= indirect_reg
[i
].regnum
;
5885 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
5888 /* define synonyms for application registers: */
5889 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
5890 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
5891 REG_AR
+ ar
[i
- REG_AR
].regnum
);
5893 /* define synonyms for control registers: */
5894 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
5895 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
5896 REG_CR
+ cr
[i
- REG_CR
].regnum
);
5898 declare_register ("gp", REG_GR
+ 1);
5899 declare_register ("sp", REG_GR
+ 12);
5900 declare_register ("rp", REG_BR
+ 0);
5902 /* pseudo-registers used to specify unwind info: */
5903 declare_register ("psp", REG_PSP
);
5905 declare_register_set ("ret", 4, REG_GR
+ 8);
5906 declare_register_set ("farg", 8, REG_FR
+ 8);
5907 declare_register_set ("fret", 8, REG_FR
+ 8);
5909 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
5911 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
5912 (PTR
) (const_bits
+ i
));
5914 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5918 /* Default to 64-bit mode. */
5919 /* ??? This overrides the -M options, but they aren't working anyways. */
5920 md
.flags
|= EF_IA_64_ABI64
;
5922 md
.mem_offset
.hint
= 0;
5925 md
.entry_labels
= NULL
;
5929 ia64_end_of_source ()
5931 /* terminate insn group upon reaching end of file: */
5932 insn_group_break (1, 0, 0);
5934 /* emits slots we haven't written yet: */
5935 ia64_flush_insns ();
5937 bfd_set_private_flags (stdoutput
, md
.flags
);
5939 if (debug_type
== DEBUG_DWARF2
)
5942 md
.mem_offset
.hint
= 0;
5948 md
.qp
.X_op
= O_absent
;
5950 if (ignore_input ())
5953 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
5955 if (md
.detect_dv
&& !md
.explicit_mode
)
5956 as_warn (_("Explicit stops are ignored in auto mode"));
5958 insn_group_break (1, 0, 0);
5963 ia64_unrecognized_line (ch
)
5969 expression (&md
.qp
);
5970 if (*input_line_pointer
++ != ')')
5972 as_bad ("Expected ')'");
5975 if (md
.qp
.X_op
!= O_register
)
5977 as_bad ("Qualifying predicate expected");
5980 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
5982 as_bad ("Predicate register expected");
5988 if (md
.manual_bundling
)
5989 as_warn ("Found '{' when manual bundling is already turned on");
5991 CURR_SLOT
.manual_bundling_on
= 1;
5992 md
.manual_bundling
= 1;
5994 /* bundling is only acceptable in explicit mode
5995 or when in default automatic mode */
5996 if (md
.detect_dv
&& !md
.explicit_mode
)
5998 if (!md
.mode_explicitly_set
5999 && !md
.default_explicit_mode
)
6002 as_warn (_("Found '{' after explicit switch to automatic mode"));
6007 if (!md
.manual_bundling
)
6008 as_warn ("Found '}' when manual bundling is off");
6010 PREV_SLOT
.manual_bundling_off
= 1;
6011 md
.manual_bundling
= 0;
6013 /* switch back to automatic mode, if applicable */
6016 && !md
.mode_explicitly_set
6017 && !md
.default_explicit_mode
)
6020 /* Allow '{' to follow on the same line. We also allow ";;", but that
6021 happens automatically because ';' is an end of line marker. */
6023 if (input_line_pointer
[0] == '{')
6025 input_line_pointer
++;
6026 return ia64_unrecognized_line ('{');
6029 demand_empty_rest_of_line ();
6035 return 0; /* not a valid line */
6039 ia64_frob_label (sym
)
6042 struct label_fix
*fix
;
6044 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6046 md
.last_text_seg
= now_seg
;
6047 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6049 fix
->next
= CURR_SLOT
.label_fixups
;
6050 CURR_SLOT
.label_fixups
= fix
;
6052 /* keep track of how many code entry points we've seen */
6053 if (md
.path
== md
.maxpaths
)
6056 md
.entry_labels
= (const char **)
6057 xrealloc ((void *)md
.entry_labels
, md
.maxpaths
* sizeof (char *));
6059 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6064 ia64_flush_pending_output ()
6066 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6068 /* ??? This causes many unnecessary stop bits to be emitted.
6069 Unfortunately, it isn't clear if it is safe to remove this. */
6070 insn_group_break (1, 0, 0);
6071 ia64_flush_insns ();
6075 /* Do ia64-specific expression optimization. All that's done here is
6076 to transform index expressions that are either due to the indexing
6077 of rotating registers or due to the indexing of indirect register
6080 ia64_optimize_expr (l
, op
, r
)
6089 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6091 num_regs
= (l
->X_add_number
>> 16);
6092 if ((unsigned) r
->X_add_number
>= num_regs
)
6095 as_bad ("No current frame");
6097 as_bad ("Index out of range 0..%u", num_regs
- 1);
6098 r
->X_add_number
= 0;
6100 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6103 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6105 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6106 || l
->X_add_number
== IND_MEM
)
6108 as_bad ("Indirect register set name expected");
6109 l
->X_add_number
= IND_CPUID
;
6112 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6113 l
->X_add_number
= r
->X_add_number
;
6121 ia64_parse_name (name
, e
)
6125 struct const_desc
*cdesc
;
6126 struct dynreg
*dr
= 0;
6127 unsigned int regnum
;
6131 /* first see if NAME is a known register name: */
6132 sym
= hash_find (md
.reg_hash
, name
);
6135 e
->X_op
= O_register
;
6136 e
->X_add_number
= S_GET_VALUE (sym
);
6140 cdesc
= hash_find (md
.const_hash
, name
);
6143 e
->X_op
= O_constant
;
6144 e
->X_add_number
= cdesc
->value
;
6148 /* check for inN, locN, or outN: */
6152 if (name
[1] == 'n' && isdigit (name
[2]))
6160 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6168 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6181 /* the name is inN, locN, or outN; parse the register number: */
6182 regnum
= strtoul (name
, &end
, 10);
6183 if (end
> name
&& *end
== '\0')
6185 if ((unsigned) regnum
>= dr
->num_regs
)
6188 as_bad ("No current frame");
6190 as_bad ("Register number out of range 0..%u", dr
->num_regs
-1);
6193 e
->X_op
= O_register
;
6194 e
->X_add_number
= dr
->base
+ regnum
;
6199 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6201 /* We've got ourselves the name of a rotating register set.
6202 Store the base register number in the low 16 bits of
6203 X_add_number and the size of the register set in the top 16
6205 e
->X_op
= O_register
;
6206 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6212 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6215 ia64_canonicalize_symbol_name (name
)
6218 size_t len
= strlen(name
);
6219 if (len
> 1 && name
[len
-1] == '#')
6225 is_conditional_branch (idesc
)
6226 struct ia64_opcode
*idesc
;
6228 return (strncmp (idesc
->name
, "br", 2) == 0
6229 && (strcmp (idesc
->name
, "br") == 0
6230 || strncmp (idesc
->name
, "br.cond", 7) == 0
6231 || strncmp (idesc
->name
, "br.call", 7) == 0
6232 || strncmp (idesc
->name
, "br.ret", 6) == 0
6233 || strcmp (idesc
->name
, "brl") == 0
6234 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6235 || strncmp (idesc
->name
, "brl.call", 7) == 0
6236 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6239 /* Return whether the given opcode is a taken branch. If there's any doubt,
6242 is_taken_branch (idesc
)
6243 struct ia64_opcode
*idesc
;
6245 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6246 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6249 /* Return whether the given opcode is an interruption or rfi. If there's any
6250 doubt, returns zero */
6252 is_interruption_or_rfi (idesc
)
6253 struct ia64_opcode
*idesc
;
6255 if (strcmp (idesc
->name
, "rfi") == 0)
6260 /* Returns the index of the given dependency in the opcode's list of chks, or
6261 -1 if there is no dependency. */
6263 depends_on (depind
, idesc
)
6265 struct ia64_opcode
*idesc
;
6268 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6269 for (i
= 0;i
< dep
->nchks
; i
++)
6271 if (depind
== DEP(dep
->chks
[i
]))
6277 /* Determine a set of specific resources used for a particular resource
6278 class. Returns the number of specific resources identified For those
6279 cases which are not determinable statically, the resource returned is
6282 Meanings of value in 'NOTE':
6283 1) only read/write when the register number is explicitly encoded in the
6285 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6286 accesses CFM when qualifying predicate is in the rotating region.
6287 3) general register value is used to specify an indirect register; not
6288 determinable statically.
6289 4) only read the given resource when bits 7:0 of the indirect index
6290 register value does not match the register number of the resource; not
6291 determinable statically.
6292 5) all rules are implementation specific.
6293 6) only when both the index specified by the reader and the index specified
6294 by the writer have the same value in bits 63:61; not determinable
6296 7) only access the specified resource when the corresponding mask bit is
6298 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6299 only read when these insns reference FR2-31
6300 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6301 written when these insns write FR32-127
6302 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6304 11) The target predicates are written independently of PR[qp], but source
6305 registers are only read if PR[qp] is true. Since the state of PR[qp]
6306 cannot statically be determined, all source registers are marked used.
6307 12) This insn only reads the specified predicate register when that
6308 register is the PR[qp].
6309 13) This reference to ld-c only applies to teh GR whose value is loaded
6310 with data returned from memory, not the post-incremented address register.
6311 14) The RSE resource includes the implementation-specific RSE internal
6312 state resources. At least one (and possibly more) of these resources are
6313 read by each instruction listed in IC:rse-readers. At least one (and
6314 possibly more) of these resources are written by each insn listed in
6316 15+16) Represents reserved instructions, which the assembler does not
6319 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6320 this code; there are no dependency violations based on memory access.
6324 #define MAX_SPECS 256
6329 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6330 const struct ia64_dependency
*dep
;
6331 struct ia64_opcode
*idesc
;
6332 int type
; /* is this a DV chk or a DV reg? */
6333 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6334 int note
; /* resource note for this insn's usage */
6335 int path
; /* which execution path to examine */
6342 if (dep
->mode
== IA64_DV_WAW
6343 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6344 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6347 /* template for any resources we identify */
6348 tmpl
.dependency
= dep
;
6350 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6351 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6352 tmpl
.link_to_qp_branch
= 1;
6353 tmpl
.mem_offset
.hint
= 0;
6358 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6359 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6360 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6362 /* we don't need to track these */
6363 if (dep
->semantics
== IA64_DVS_NONE
)
6366 switch (dep
->specifier
)
6371 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6373 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6374 if (regno
>= 0 && regno
<= 7)
6376 specs
[count
] = tmpl
;
6377 specs
[count
++].index
= regno
;
6385 specs
[count
] = tmpl
;
6386 specs
[count
++].index
= i
;
6395 case IA64_RS_AR_UNAT
:
6396 /* This is a mov =AR or mov AR= instruction. */
6397 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6399 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6400 if (regno
== AR_UNAT
)
6402 specs
[count
++] = tmpl
;
6407 /* This is a spill/fill, or other instruction that modifies the
6410 /* Unless we can determine the specific bits used, mark the whole
6411 thing; bits 8:3 of the memory address indicate the bit used in
6412 UNAT. The .mem.offset hint may be used to eliminate a small
6413 subset of conflicts. */
6414 specs
[count
] = tmpl
;
6415 if (md
.mem_offset
.hint
)
6418 fprintf (stderr
, " Using hint for spill/fill\n");
6419 /* the index isn't actually used, just set it to something
6420 approximating the bit index */
6421 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6422 specs
[count
].mem_offset
.hint
= 1;
6423 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6424 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6428 specs
[count
++].specific
= 0;
6436 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6438 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6439 if ((regno
>= 8 && regno
<= 15)
6440 || (regno
>= 20 && regno
<= 23)
6441 || (regno
>= 31 && regno
<= 39)
6442 || (regno
>= 41 && regno
<= 47)
6443 || (regno
>= 67 && regno
<= 111))
6445 specs
[count
] = tmpl
;
6446 specs
[count
++].index
= regno
;
6459 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6461 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6462 if ((regno
>= 48 && regno
<= 63)
6463 || (regno
>= 112 && regno
<= 127))
6465 specs
[count
] = tmpl
;
6466 specs
[count
++].index
= regno
;
6472 for (i
=48;i
< 64;i
++)
6474 specs
[count
] = tmpl
;
6475 specs
[count
++].index
= i
;
6477 for (i
=112;i
< 128;i
++)
6479 specs
[count
] = tmpl
;
6480 specs
[count
++].index
= i
;
6498 for (i
=0;i
< idesc
->num_outputs
;i
++)
6499 if (idesc
->operands
[i
] == IA64_OPND_B1
6500 || idesc
->operands
[i
] == IA64_OPND_B2
)
6502 specs
[count
] = tmpl
;
6503 specs
[count
++].index
=
6504 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6509 for (i
= idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6510 if (idesc
->operands
[i
] == IA64_OPND_B1
6511 || idesc
->operands
[i
] == IA64_OPND_B2
)
6513 specs
[count
] = tmpl
;
6514 specs
[count
++].index
=
6515 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6521 case IA64_RS_CPUID
: /* four or more registers */
6524 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6526 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6527 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6530 specs
[count
] = tmpl
;
6531 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6535 specs
[count
] = tmpl
;
6536 specs
[count
++].specific
= 0;
6546 case IA64_RS_DBR
: /* four or more registers */
6549 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6551 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6552 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6555 specs
[count
] = tmpl
;
6556 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6560 specs
[count
] = tmpl
;
6561 specs
[count
++].specific
= 0;
6565 else if (note
== 0 && !rsrc_write
)
6567 specs
[count
] = tmpl
;
6568 specs
[count
++].specific
= 0;
6576 case IA64_RS_IBR
: /* four or more registers */
6579 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6581 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6582 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6585 specs
[count
] = tmpl
;
6586 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6590 specs
[count
] = tmpl
;
6591 specs
[count
++].specific
= 0;
6604 /* These are implementation specific. Force all references to
6605 conflict with all other references. */
6606 specs
[count
] = tmpl
;
6607 specs
[count
++].specific
= 0;
6615 case IA64_RS_PKR
: /* 16 or more registers */
6616 if (note
== 3 || note
== 4)
6618 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6620 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6621 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6626 specs
[count
] = tmpl
;
6627 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6629 else for (i
=0;i
< NELEMS(gr_values
);i
++)
6631 /* uses all registers *except* the one in R3 */
6632 if (i
!= (gr_values
[regno
].value
& 0xFF))
6634 specs
[count
] = tmpl
;
6635 specs
[count
++].index
= i
;
6641 specs
[count
] = tmpl
;
6642 specs
[count
++].specific
= 0;
6649 specs
[count
] = tmpl
;
6650 specs
[count
++].specific
= 0;
6654 case IA64_RS_PMC
: /* four or more registers */
6657 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
6658 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
6661 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
6663 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
6664 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6667 specs
[count
] = tmpl
;
6668 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6672 specs
[count
] = tmpl
;
6673 specs
[count
++].specific
= 0;
6683 case IA64_RS_PMD
: /* four or more registers */
6686 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
6688 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6689 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6692 specs
[count
] = tmpl
;
6693 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6697 specs
[count
] = tmpl
;
6698 specs
[count
++].specific
= 0;
6708 case IA64_RS_RR
: /* eight registers */
6711 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
6713 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6714 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6717 specs
[count
] = tmpl
;
6718 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
6722 specs
[count
] = tmpl
;
6723 specs
[count
++].specific
= 0;
6727 else if (note
== 0 && !rsrc_write
)
6729 specs
[count
] = tmpl
;
6730 specs
[count
++].specific
= 0;
6738 case IA64_RS_CR_IRR
:
6741 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6742 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
6744 && idesc
->operands
[1] == IA64_OPND_CR3
6749 specs
[count
] = tmpl
;
6750 specs
[count
++].index
= CR_IRR0
+ i
;
6756 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6757 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6759 && regno
<= CR_IRR3
)
6761 specs
[count
] = tmpl
;
6762 specs
[count
++].index
= regno
;
6771 case IA64_RS_CR_LRR
:
6778 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6779 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6780 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
6782 specs
[count
] = tmpl
;
6783 specs
[count
++].index
= regno
;
6791 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
6793 specs
[count
] = tmpl
;
6794 specs
[count
++].index
=
6795 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6810 else if (rsrc_write
)
6812 if (dep
->specifier
== IA64_RS_FRb
6813 && idesc
->operands
[0] == IA64_OPND_F1
)
6815 specs
[count
] = tmpl
;
6816 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
6821 for (i
=idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6823 if (idesc
->operands
[i
] == IA64_OPND_F2
6824 || idesc
->operands
[i
] == IA64_OPND_F3
6825 || idesc
->operands
[i
] == IA64_OPND_F4
)
6827 specs
[count
] = tmpl
;
6828 specs
[count
++].index
=
6829 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
6838 /* This reference applies only to the GR whose value is loaded with
6839 data returned from memory */
6840 specs
[count
] = tmpl
;
6841 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
6847 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6848 if (idesc
->operands
[i
] == IA64_OPND_R1
6849 || idesc
->operands
[i
] == IA64_OPND_R2
6850 || idesc
->operands
[i
] == IA64_OPND_R3
)
6852 specs
[count
] = tmpl
;
6853 specs
[count
++].index
=
6854 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6856 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
6857 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
6858 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
6860 specs
[count
] = tmpl
;
6861 specs
[count
++].index
=
6862 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6867 /* Look for anything that reads a GR */
6868 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
6870 if (idesc
->operands
[i
] == IA64_OPND_MR3
6871 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
6872 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
6873 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
6874 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
6875 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
6876 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
6877 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
6878 || idesc
->operands
[i
] == IA64_OPND_RR_R3
6879 || ((i
>= idesc
->num_outputs
)
6880 && (idesc
->operands
[i
] == IA64_OPND_R1
6881 || idesc
->operands
[i
] == IA64_OPND_R2
6882 || idesc
->operands
[i
] == IA64_OPND_R3
6883 /* addl source register. */
6884 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
6886 specs
[count
] = tmpl
;
6887 specs
[count
++].index
=
6888 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6902 if (idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6904 for (i
=16;i
< 63;i
++)
6906 specs
[count
] = tmpl
;
6907 specs
[count
++].index
= i
;
6912 for (i
=1;i
< 63;i
++)
6914 specs
[count
] = tmpl
;
6915 specs
[count
++].index
= i
;
6922 /* mark only those registers indicated by the mask */
6924 && idesc
->operands
[0] == IA64_OPND_PR
)
6926 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
6927 if (mask
& ((valueT
) 1<<16))
6928 mask
|= ~(valueT
) 0xffff;
6929 for (i
=1;i
< 63;i
++)
6931 if (mask
& ((valueT
) 1<<i
))
6933 specs
[count
] = tmpl
;
6934 specs
[count
++].index
= i
;
6939 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6941 for (i
=16;i
< 63;i
++)
6943 specs
[count
] = tmpl
;
6944 specs
[count
++].index
= i
;
6952 else if (note
== 11) /* note 11 implies note 1 as well */
6956 for (i
=0;i
< idesc
->num_outputs
;i
++)
6958 if (idesc
->operands
[i
] == IA64_OPND_P1
6959 || idesc
->operands
[i
] == IA64_OPND_P2
)
6961 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
6964 specs
[count
] = tmpl
;
6965 specs
[count
++].index
= regno
;
6975 else if (note
== 12)
6977 if (CURR_SLOT
.qp_regno
!= 0)
6979 specs
[count
] = tmpl
;
6980 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6987 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
6988 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
6989 if ((idesc
->operands
[0] == IA64_OPND_P1
6990 || idesc
->operands
[0] == IA64_OPND_P2
)
6991 && p1
!= 0 && p1
!= 63)
6993 specs
[count
] = tmpl
;
6994 specs
[count
++].index
= p1
;
6996 if ((idesc
->operands
[1] == IA64_OPND_P1
6997 || idesc
->operands
[1] == IA64_OPND_P2
)
6998 && p2
!= 0 && p2
!= 63)
7000 specs
[count
] = tmpl
;
7001 specs
[count
++].index
= p2
;
7006 if (CURR_SLOT
.qp_regno
!= 0)
7008 specs
[count
] = tmpl
;
7009 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7011 if (idesc
->operands
[1] == IA64_OPND_PR
)
7013 for (i
=1;i
< 63;i
++)
7015 specs
[count
] = tmpl
;
7016 specs
[count
++].index
= i
;
7028 /* Verify that the instruction is using the PSR bit indicated in
7032 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7034 if (dep
->regindex
< 6)
7036 specs
[count
++] = tmpl
;
7039 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7041 if (dep
->regindex
< 32
7042 || dep
->regindex
== 35
7043 || dep
->regindex
== 36
7044 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7046 specs
[count
++] = tmpl
;
7049 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7051 if (dep
->regindex
< 32
7052 || dep
->regindex
== 35
7053 || dep
->regindex
== 36
7054 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7056 specs
[count
++] = tmpl
;
7061 /* Several PSR bits have very specific dependencies. */
7062 switch (dep
->regindex
)
7065 specs
[count
++] = tmpl
;
7070 specs
[count
++] = tmpl
;
7074 /* Only certain CR accesses use PSR.ic */
7075 if (idesc
->operands
[0] == IA64_OPND_CR3
7076 || idesc
->operands
[1] == IA64_OPND_CR3
)
7079 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7082 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7097 specs
[count
++] = tmpl
;
7106 specs
[count
++] = tmpl
;
7110 /* Only some AR accesses use cpl */
7111 if (idesc
->operands
[0] == IA64_OPND_AR3
7112 || idesc
->operands
[1] == IA64_OPND_AR3
)
7115 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7118 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7125 && regno
<= AR_K7
))))
7127 specs
[count
++] = tmpl
;
7132 specs
[count
++] = tmpl
;
7142 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7144 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7150 if (mask
& ((valueT
) 1<<dep
->regindex
))
7152 specs
[count
++] = tmpl
;
7157 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7158 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7159 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7160 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7162 if (idesc
->operands
[i
] == IA64_OPND_F1
7163 || idesc
->operands
[i
] == IA64_OPND_F2
7164 || idesc
->operands
[i
] == IA64_OPND_F3
7165 || idesc
->operands
[i
] == IA64_OPND_F4
)
7167 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7168 if (reg
>= min
&& reg
<= max
)
7170 specs
[count
++] = tmpl
;
7177 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7178 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7179 /* mfh is read on writes to FR32-127; mfl is read on writes to
7181 for (i
=0;i
< idesc
->num_outputs
;i
++)
7183 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7185 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7186 if (reg
>= min
&& reg
<= max
)
7188 specs
[count
++] = tmpl
;
7193 else if (note
== 10)
7195 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7197 if (idesc
->operands
[i
] == IA64_OPND_R1
7198 || idesc
->operands
[i
] == IA64_OPND_R2
7199 || idesc
->operands
[i
] == IA64_OPND_R3
)
7201 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7202 if (regno
>= 16 && regno
<= 31)
7204 specs
[count
++] = tmpl
;
7215 case IA64_RS_AR_FPSR
:
7216 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7218 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7219 if (regno
== AR_FPSR
)
7221 specs
[count
++] = tmpl
;
7226 specs
[count
++] = tmpl
;
7231 /* Handle all AR[REG] resources */
7232 if (note
== 0 || note
== 1)
7234 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7235 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7236 && regno
== dep
->regindex
)
7238 specs
[count
++] = tmpl
;
7240 /* other AR[REG] resources may be affected by AR accesses */
7241 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7244 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7245 switch (dep
->regindex
)
7251 if (regno
== AR_BSPSTORE
)
7253 specs
[count
++] = tmpl
;
7257 (regno
== AR_BSPSTORE
7258 || regno
== AR_RNAT
))
7260 specs
[count
++] = tmpl
;
7265 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7268 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7269 switch (dep
->regindex
)
7274 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7276 specs
[count
++] = tmpl
;
7283 specs
[count
++] = tmpl
;
7293 /* Handle all CR[REG] resources */
7294 if (note
== 0 || note
== 1)
7296 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7298 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7299 if (regno
== dep
->regindex
)
7301 specs
[count
++] = tmpl
;
7303 else if (!rsrc_write
)
7305 /* Reads from CR[IVR] affect other resources. */
7306 if (regno
== CR_IVR
)
7308 if ((dep
->regindex
>= CR_IRR0
7309 && dep
->regindex
<= CR_IRR3
)
7310 || dep
->regindex
== CR_TPR
)
7312 specs
[count
++] = tmpl
;
7319 specs
[count
++] = tmpl
;
7328 case IA64_RS_INSERVICE
:
7329 /* look for write of EOI (67) or read of IVR (65) */
7330 if ((idesc
->operands
[0] == IA64_OPND_CR3
7331 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7332 || (idesc
->operands
[1] == IA64_OPND_CR3
7333 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7335 specs
[count
++] = tmpl
;
7342 specs
[count
++] = tmpl
;
7353 specs
[count
++] = tmpl
;
7357 /* Check if any of the registers accessed are in the rotating region.
7358 mov to/from pr accesses CFM only when qp_regno is in the rotating
7360 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7362 if (idesc
->operands
[i
] == IA64_OPND_R1
7363 || idesc
->operands
[i
] == IA64_OPND_R2
7364 || idesc
->operands
[i
] == IA64_OPND_R3
)
7366 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7367 /* Assumes that md.rot.num_regs is always valid */
7368 if (md
.rot
.num_regs
> 0
7370 && num
< 31 + md
.rot
.num_regs
)
7372 specs
[count
] = tmpl
;
7373 specs
[count
++].specific
= 0;
7376 else if (idesc
->operands
[i
] == IA64_OPND_F1
7377 || idesc
->operands
[i
] == IA64_OPND_F2
7378 || idesc
->operands
[i
] == IA64_OPND_F3
7379 || idesc
->operands
[i
] == IA64_OPND_F4
)
7381 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7384 specs
[count
] = tmpl
;
7385 specs
[count
++].specific
= 0;
7388 else if (idesc
->operands
[i
] == IA64_OPND_P1
7389 || idesc
->operands
[i
] == IA64_OPND_P2
)
7391 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7394 specs
[count
] = tmpl
;
7395 specs
[count
++].specific
= 0;
7399 if (CURR_SLOT
.qp_regno
> 15)
7401 specs
[count
] = tmpl
;
7402 specs
[count
++].specific
= 0;
7410 specs
[count
++] = tmpl
;
7412 else if (note
== 11)
7414 if ((idesc
->operands
[0] == IA64_OPND_P1
7415 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7416 || (idesc
->operands
[1] == IA64_OPND_P2
7417 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7419 specs
[count
++] = tmpl
;
7422 else if (note
== 12)
7424 if (CURR_SLOT
.qp_regno
== 63)
7426 specs
[count
++] = tmpl
;
7432 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7433 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7434 if (mask
& ((valueT
) 1<<63))
7436 specs
[count
++] = tmpl
;
7443 for (i
=0;i
< idesc
->num_outputs
;i
++)
7444 if ((idesc
->operands
[i
] == IA64_OPND_P1
7445 || idesc
->operands
[i
] == IA64_OPND_P2
)
7446 && CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
== 63)
7448 specs
[count
++] = tmpl
;
7453 if (CURR_SLOT
.qp_regno
== 63)
7455 specs
[count
++] = tmpl
;
7466 /* FIXME we can identify some individual RSE written resources, but RSE
7467 read resources have not yet been completely identified, so for now
7468 treat RSE as a single resource */
7469 if (strncmp (idesc
->name
, "mov", 3) == 0)
7473 if (idesc
->operands
[0] == IA64_OPND_AR3
7474 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7476 specs
[count
] = tmpl
;
7477 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7482 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7484 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7485 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7487 specs
[count
++] = tmpl
;
7490 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7492 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7493 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7494 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7496 specs
[count
++] = tmpl
;
7503 specs
[count
++] = tmpl
;
7508 /* FIXME -- do any of these need to be non-specific? */
7509 specs
[count
++] = tmpl
;
7513 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7520 /* Clear branch flags on marked resources. This breaks the link between the
7521 QP of the marking instruction and a subsequent branch on the same QP.
7524 clear_qp_branch_flag (mask
)
7528 for (i
= 0;i
< regdepslen
;i
++)
7530 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
7531 if ((bit
& mask
) != 0)
7533 regdeps
[i
].link_to_qp_branch
= 0;
7538 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7540 Any changes to a PR clears the mutex relations which include that PR.
7543 clear_qp_mutex (mask
)
7549 while (i
< qp_mutexeslen
)
7551 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
7555 fprintf (stderr
, " Clearing mutex relation");
7556 print_prmask (qp_mutexes
[i
].prmask
);
7557 fprintf (stderr
, "\n");
7559 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
7566 /* Clear implies relations which contain PRs in the given masks.
7567 P1_MASK indicates the source of the implies relation, while P2_MASK
7568 indicates the implied PR.
7571 clear_qp_implies (p1_mask
, p2_mask
)
7578 while (i
< qp_implieslen
)
7580 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
7581 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
7584 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
7585 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
7586 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
7593 /* add the PRs specified to the list of implied relations */
7595 add_qp_imply (p1
, p2
)
7602 /* p0 is not meaningful here */
7603 if (p1
== 0 || p2
== 0)
7609 /* if it exists already, ignore it */
7610 for (i
=0;i
< qp_implieslen
;i
++)
7612 if (qp_implies
[i
].p1
== p1
7613 && qp_implies
[i
].p2
== p2
7614 && qp_implies
[i
].path
== md
.path
7615 && !qp_implies
[i
].p2_branched
)
7619 if (qp_implieslen
== qp_impliestotlen
)
7621 qp_impliestotlen
+= 20;
7622 qp_implies
= (struct qp_imply
*)
7623 xrealloc ((void *)qp_implies
,
7624 qp_impliestotlen
* sizeof (struct qp_imply
));
7627 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
7628 qp_implies
[qp_implieslen
].p1
= p1
;
7629 qp_implies
[qp_implieslen
].p2
= p2
;
7630 qp_implies
[qp_implieslen
].path
= md
.path
;
7631 qp_implies
[qp_implieslen
++].p2_branched
= 0;
7633 /* Add in the implied transitive relations; for everything that p2 implies,
7634 make p1 imply that, too; for everything that implies p1, make it imply p2
7636 for (i
=0;i
< qp_implieslen
;i
++)
7638 if (qp_implies
[i
].p1
== p2
)
7639 add_qp_imply (p1
, qp_implies
[i
].p2
);
7640 if (qp_implies
[i
].p2
== p1
)
7641 add_qp_imply (qp_implies
[i
].p1
, p2
);
7643 /* Add in mutex relations implied by this implies relation; for each mutex
7644 relation containing p2, duplicate it and replace p2 with p1. */
7645 bit
= (valueT
) 1 << p1
;
7646 mask
= (valueT
) 1 << p2
;
7647 for (i
=0;i
< qp_mutexeslen
;i
++)
7649 if (qp_mutexes
[i
].prmask
& mask
)
7650 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
7654 /* Add the PRs specified in the mask to the mutex list; this means that only
7655 one of the PRs can be true at any time. PR0 should never be included in
7664 if (qp_mutexeslen
== qp_mutexestotlen
)
7666 qp_mutexestotlen
+= 20;
7667 qp_mutexes
= (struct qpmutex
*)
7668 xrealloc ((void *)qp_mutexes
,
7669 qp_mutexestotlen
* sizeof (struct qpmutex
));
7673 fprintf (stderr
, " Registering mutex on");
7674 print_prmask (mask
);
7675 fprintf (stderr
, "\n");
7677 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
7678 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
7682 clear_register_values ()
7686 fprintf (stderr
, " Clearing register values\n");
7687 for (i
=1;i
< NELEMS(gr_values
);i
++)
7688 gr_values
[i
].known
= 0;
7691 /* Keep track of register values/changes which affect DV tracking.
7693 optimization note: should add a flag to classes of insns where otherwise we
7694 have to examine a group of strings to identify them.
7698 note_register_values (idesc
)
7699 struct ia64_opcode
*idesc
;
7701 valueT qp_changemask
= 0;
7704 /* invalidate values for registers being written to */
7705 for (i
=0;i
< idesc
->num_outputs
;i
++)
7707 if (idesc
->operands
[i
] == IA64_OPND_R1
7708 || idesc
->operands
[i
] == IA64_OPND_R2
7709 || idesc
->operands
[i
] == IA64_OPND_R3
)
7711 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7712 if (regno
> 0 && regno
< NELEMS(gr_values
))
7713 gr_values
[regno
].known
= 0;
7715 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
7717 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7718 if (regno
> 0 && regno
< 4)
7719 gr_values
[regno
].known
= 0;
7721 else if (idesc
->operands
[i
] == IA64_OPND_P1
7722 || idesc
->operands
[i
] == IA64_OPND_P2
)
7724 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7725 qp_changemask
|= (valueT
) 1 << regno
;
7727 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
7729 if (idesc
->operands
[2] & (valueT
) 0x10000)
7730 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
7732 qp_changemask
= idesc
->operands
[2];
7735 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
7737 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
7738 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
7740 qp_changemask
= idesc
->operands
[1];
7741 qp_changemask
&= ~(valueT
) 0xFFFF;
7746 /* Always clear qp branch flags on any PR change */
7747 /* FIXME there may be exceptions for certain compares */
7748 clear_qp_branch_flag (qp_changemask
);
7750 /* invalidate rotating registers on insns which affect RRBs in CFM */
7751 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
7753 qp_changemask
|= ~(valueT
) 0xFFFF;
7754 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
7756 for (i
=32;i
< 32+md
.rot
.num_regs
;i
++)
7757 gr_values
[i
].known
= 0;
7759 clear_qp_mutex (qp_changemask
);
7760 clear_qp_implies (qp_changemask
, qp_changemask
);
7762 /* after a call, all register values are undefined, except those marked
7764 else if (strncmp (idesc
->name
, "br.call", 6) == 0
7765 || strncmp (idesc
->name
, "brl.call", 7) == 0)
7767 // FIXME keep GR values which are marked as "safe_across_calls"
7768 clear_register_values ();
7769 clear_qp_mutex (~qp_safe_across_calls
);
7770 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
7771 clear_qp_branch_flag (~qp_safe_across_calls
);
7773 else if (is_interruption_or_rfi (idesc
)
7774 || is_taken_branch (idesc
))
7776 clear_register_values ();
7777 clear_qp_mutex (~(valueT
) 0);
7778 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
7780 /* Look for mutex and implies relations */
7781 else if ((idesc
->operands
[0] == IA64_OPND_P1
7782 || idesc
->operands
[0] == IA64_OPND_P2
)
7783 && (idesc
->operands
[1] == IA64_OPND_P1
7784 || idesc
->operands
[1] == IA64_OPND_P2
))
7786 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7787 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7788 valueT p1mask
= (valueT
) 1 << p1
;
7789 valueT p2mask
= (valueT
) 1 << p2
;
7791 /* if one of the PRs is PR0, we can't really do anything */
7792 if (p1
== 0 || p2
== 0)
7795 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
7797 /* In general, clear mutexes and implies which include P1 or P2,
7798 with the following exceptions */
7799 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
7801 add_qp_mutex (p1mask
| p2mask
);
7802 clear_qp_implies (p2mask
, p1mask
);
7804 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
7806 add_qp_mutex (p1mask
| p2mask
);
7807 clear_qp_implies (p1mask
, p2mask
);
7809 else if (strstr (idesc
->name
, ".and") != NULL
)
7811 clear_qp_implies (0, p1mask
| p2mask
);
7813 else if (strstr (idesc
->name
, ".or") != NULL
)
7815 clear_qp_mutex (p1mask
| p2mask
);
7816 clear_qp_implies (p1mask
| p2mask
, 0);
7820 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
7821 if (strstr (idesc
->name
, ".unc") != NULL
)
7823 add_qp_mutex (p1mask
| p2mask
);
7824 if (CURR_SLOT
.qp_regno
!= 0)
7826 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
7827 CURR_SLOT
.qp_regno
);
7828 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
7829 CURR_SLOT
.qp_regno
);
7832 else if (CURR_SLOT
.qp_regno
== 0)
7834 add_qp_mutex (p1mask
| p2mask
);
7838 clear_qp_mutex (p1mask
| p2mask
);
7842 /* Look for mov imm insns into GRs */
7843 else if (idesc
->operands
[0] == IA64_OPND_R1
7844 && (idesc
->operands
[1] == IA64_OPND_IMM22
7845 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
7846 && (strcmp(idesc
->name
, "mov") == 0
7847 || strcmp(idesc
->name
, "movl") == 0))
7849 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7850 if (regno
> 0 && regno
< NELEMS(gr_values
))
7852 gr_values
[regno
].known
= 1;
7853 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
7854 gr_values
[regno
].path
= md
.path
;
7856 fprintf (stderr
, " Know gr%d = 0x%llx\n",
7857 regno
, gr_values
[regno
].value
);
7862 clear_qp_mutex (qp_changemask
);
7863 clear_qp_implies (qp_changemask
, qp_changemask
);
7867 /* Return whether the given predicate registers are currently mutex */
7869 qp_mutex (p1
, p2
, path
)
7879 mask
= ((valueT
) 1<<p1
) | (valueT
) 1<<p2
;
7880 for (i
=0;i
< qp_mutexeslen
;i
++)
7882 if (qp_mutexes
[i
].path
>= path
7883 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
7890 /* Return whether the given resource is in the given insn's list of chks
7891 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7895 resources_match (rs
, idesc
, note
, qp_regno
, path
)
7897 struct ia64_opcode
*idesc
;
7902 struct rsrc specs
[MAX_SPECS
];
7905 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7906 we don't need to check. One exception is note 11, which indicates that
7907 target predicates are written regardless of PR[qp]. */
7908 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
7912 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
7915 /* UNAT checking is a bit more specific than other resources */
7916 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
7917 && specs
[count
].mem_offset
.hint
7918 && rs
->mem_offset
.hint
)
7920 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
7922 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
7923 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
7930 /* If either resource is not specific, conservatively assume a conflict
7932 if (!specs
[count
].specific
|| !rs
->specific
)
7934 else if (specs
[count
].index
== rs
->index
)
7939 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
7945 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7946 insert a stop to create the break. Update all resource dependencies
7947 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7948 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7949 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7954 insn_group_break (insert_stop
, qp_regno
, save_current
)
7961 if (insert_stop
&& md
.num_slots_in_use
> 0)
7962 PREV_SLOT
.end_of_insn_group
= 1;
7966 fprintf (stderr
, " Insn group break%s",
7967 (insert_stop
? " (w/stop)" : ""));
7969 fprintf (stderr
, " effective for QP=%d", qp_regno
);
7970 fprintf (stderr
, "\n");
7974 while (i
< regdepslen
)
7976 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
7979 && regdeps
[i
].qp_regno
!= qp_regno
)
7986 && CURR_SLOT
.src_file
== regdeps
[i
].file
7987 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
7993 /* clear dependencies which are automatically cleared by a stop, or
7994 those that have reached the appropriate state of insn serialization */
7995 if (dep
->semantics
== IA64_DVS_IMPLIED
7996 || dep
->semantics
== IA64_DVS_IMPLIEDF
7997 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
7999 print_dependency ("Removing", i
);
8000 regdeps
[i
] = regdeps
[--regdepslen
];
8004 if (dep
->semantics
== IA64_DVS_DATA
8005 || dep
->semantics
== IA64_DVS_INSTR
8006 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8008 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8009 regdeps
[i
].insn_srlz
= STATE_STOP
;
8010 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8011 regdeps
[i
].data_srlz
= STATE_STOP
;
8018 /* Add the given resource usage spec to the list of active dependencies */
8020 mark_resource (idesc
, dep
, spec
, depind
, path
)
8021 struct ia64_opcode
*idesc
;
8022 const struct ia64_dependency
*dep
;
8027 if (regdepslen
== regdepstotlen
)
8029 regdepstotlen
+= 20;
8030 regdeps
= (struct rsrc
*)
8031 xrealloc ((void *)regdeps
,
8032 regdepstotlen
* sizeof(struct rsrc
));
8035 regdeps
[regdepslen
] = *spec
;
8036 regdeps
[regdepslen
].depind
= depind
;
8037 regdeps
[regdepslen
].path
= path
;
8038 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8039 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8041 print_dependency ("Adding", regdepslen
);
8047 print_dependency (action
, depind
)
8053 fprintf (stderr
, " %s %s '%s'",
8054 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8055 (regdeps
[depind
].dependency
)->name
);
8056 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8057 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8058 if (regdeps
[depind
].mem_offset
.hint
)
8059 fprintf (stderr
, " 0x%llx+0x%llx",
8060 regdeps
[depind
].mem_offset
.base
,
8061 regdeps
[depind
].mem_offset
.offset
);
8062 fprintf (stderr
, "\n");
8067 instruction_serialization ()
8071 fprintf (stderr
, " Instruction serialization\n");
8072 for (i
=0;i
< regdepslen
;i
++)
8073 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8074 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8078 data_serialization ()
8082 fprintf (stderr
, " Data serialization\n");
8083 while (i
< regdepslen
)
8085 if (regdeps
[i
].data_srlz
== STATE_STOP
8086 /* Note: as of 991210, all "other" dependencies are cleared by a
8087 data serialization. This might change with new tables */
8088 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8090 print_dependency ("Removing", i
);
8091 regdeps
[i
] = regdeps
[--regdepslen
];
8098 /* Insert stops and serializations as needed to avoid DVs */
8100 remove_marked_resource (rs
)
8103 switch (rs
->dependency
->semantics
)
8105 case IA64_DVS_SPECIFIC
:
8107 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8108 /* ...fall through... */
8109 case IA64_DVS_INSTR
:
8111 fprintf (stderr
, "Inserting instr serialization\n");
8112 if (rs
->insn_srlz
< STATE_STOP
)
8113 insn_group_break (1, 0, 0);
8114 if (rs
->insn_srlz
< STATE_SRLZ
)
8116 int oldqp
= CURR_SLOT
.qp_regno
;
8117 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8118 /* Manually jam a srlz.i insn into the stream */
8119 CURR_SLOT
.qp_regno
= 0;
8120 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8121 instruction_serialization ();
8122 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8123 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8125 CURR_SLOT
.qp_regno
= oldqp
;
8126 CURR_SLOT
.idesc
= oldidesc
;
8128 insn_group_break (1, 0, 0);
8130 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8131 "other" types of DV are eliminated
8132 by a data serialization */
8135 fprintf (stderr
, "Inserting data serialization\n");
8136 if (rs
->data_srlz
< STATE_STOP
)
8137 insn_group_break (1, 0, 0);
8139 int oldqp
= CURR_SLOT
.qp_regno
;
8140 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8141 /* Manually jam a srlz.d insn into the stream */
8142 CURR_SLOT
.qp_regno
= 0;
8143 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8144 data_serialization ();
8145 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8146 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8148 CURR_SLOT
.qp_regno
= oldqp
;
8149 CURR_SLOT
.idesc
= oldidesc
;
8152 case IA64_DVS_IMPLIED
:
8153 case IA64_DVS_IMPLIEDF
:
8155 fprintf (stderr
, "Inserting stop\n");
8156 insn_group_break (1, 0, 0);
8163 /* Check the resources used by the given opcode against the current dependency
8166 The check is run once for each execution path encountered. In this case,
8167 a unique execution path is the sequence of instructions following a code
8168 entry point, e.g. the following has three execution paths, one starting
8169 at L0, one at L1, and one at L2.
8177 check_dependencies (idesc
)
8178 struct ia64_opcode
*idesc
;
8180 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8184 /* Note that the number of marked resources may change within the
8185 loop if in auto mode. */
8187 while (i
< regdepslen
)
8189 struct rsrc
*rs
= ®deps
[i
];
8190 const struct ia64_dependency
*dep
= rs
->dependency
;
8195 if (dep
->semantics
== IA64_DVS_NONE
8196 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8201 note
= NOTE(opdeps
->chks
[chkind
]);
8203 /* Check this resource against each execution path seen thus far */
8204 for (path
=0;path
<= md
.path
;path
++)
8208 /* If the dependency wasn't on the path being checked, ignore it */
8209 if (rs
->path
< path
)
8212 /* If the QP for this insn implies a QP which has branched, don't
8213 bother checking. Ed. NOTE: I don't think this check is terribly
8214 useful; what's the point of generating code which will only be
8215 reached if its QP is zero?
8216 This code was specifically inserted to handle the following code,
8217 based on notes from Intel's DV checking code, where p1 implies p2.
8224 if (CURR_SLOT
.qp_regno
!= 0)
8228 for (implies
=0;implies
< qp_implieslen
;implies
++)
8230 if (qp_implies
[implies
].path
>= path
8231 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8232 && qp_implies
[implies
].p2_branched
)
8242 if ((matchtype
= resources_match (rs
, idesc
, note
,
8243 CURR_SLOT
.qp_regno
, path
)) != 0)
8246 char pathmsg
[256] = "";
8247 char indexmsg
[256] = "";
8248 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8251 sprintf (pathmsg
, " when entry is at label '%s'",
8252 md
.entry_labels
[path
-1]);
8253 if (rs
->specific
&& rs
->index
!= 0)
8254 sprintf (indexmsg
, ", specific resource number is %d",
8256 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8258 (certain
? "violates" : "may violate"),
8259 dv_mode
[dep
->mode
], dep
->name
,
8260 dv_sem
[dep
->semantics
],
8263 if (md
.explicit_mode
)
8265 as_warn ("%s", msg
);
8267 as_warn (_("Only the first path encountering the conflict "
8269 as_warn_where (rs
->file
, rs
->line
,
8270 _("This is the location of the "
8271 "conflicting usage"));
8272 /* Don't bother checking other paths, to avoid duplicating
8279 fprintf(stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8281 remove_marked_resource (rs
);
8283 /* since the set of dependencies has changed, start over */
8284 /* FIXME -- since we're removing dvs as we go, we
8285 probably don't really need to start over... */
8298 /* register new dependencies based on the given opcode */
8300 mark_resources (idesc
)
8301 struct ia64_opcode
*idesc
;
8304 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8305 int add_only_qp_reads
= 0;
8307 /* A conditional branch only uses its resources if it is taken; if it is
8308 taken, we stop following that path. The other branch types effectively
8309 *always* write their resources. If it's not taken, register only QP
8311 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8313 add_only_qp_reads
= 1;
8317 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8319 for (i
=0;i
< opdeps
->nregs
;i
++)
8321 const struct ia64_dependency
*dep
;
8322 struct rsrc specs
[MAX_SPECS
];
8327 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8328 note
= NOTE(opdeps
->regs
[i
]);
8330 if (add_only_qp_reads
8331 && !(dep
->mode
== IA64_DV_WAR
8332 && (dep
->specifier
== IA64_RS_PR
8333 || dep
->specifier
== IA64_RS_PR63
)))
8336 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8339 if (md
.debug_dv
&& !count
)
8340 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8341 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8346 mark_resource (idesc
, dep
, &specs
[count
],
8347 DEP(opdeps
->regs
[i
]), md
.path
);
8350 /* The execution path may affect register values, which may in turn
8351 affect which indirect-access resources are accessed. */
8352 switch (dep
->specifier
)
8364 for (path
=0;path
< md
.path
;path
++)
8366 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8368 mark_resource (idesc
, dep
, &specs
[count
],
8369 DEP(opdeps
->regs
[i
]), path
);
8376 /* remove dependencies when they no longer apply */
8378 update_dependencies (idesc
)
8379 struct ia64_opcode
*idesc
;
8383 if (strcmp (idesc
->name
, "srlz.i") == 0)
8385 instruction_serialization ();
8387 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8389 data_serialization ();
8391 else if (is_interruption_or_rfi (idesc
)
8392 || is_taken_branch (idesc
))
8394 /* although technically the taken branch doesn't clear dependencies
8395 which require a srlz.[id], we don't follow the branch; the next
8396 instruction is assumed to start with a clean slate */
8400 else if (is_conditional_branch (idesc
)
8401 && CURR_SLOT
.qp_regno
!= 0)
8403 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8405 for (i
=0;i
< qp_implieslen
;i
++)
8407 /* if the conditional branch's predicate is implied by the predicate
8408 in an existing dependency, remove that dependency */
8409 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8412 /* note that this implied predicate takes a branch so that if
8413 a later insn generates a DV but its predicate implies this
8414 one, we can avoid the false DV warning */
8415 qp_implies
[i
].p2_branched
= 1;
8416 while (depind
< regdepslen
)
8418 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8420 print_dependency ("Removing", depind
);
8421 regdeps
[depind
] = regdeps
[--regdepslen
];
8428 /* Any marked resources which have this same predicate should be
8429 cleared, provided that the QP hasn't been modified between the
8430 marking instruction and the branch.
8434 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8439 while (i
< regdepslen
)
8441 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8442 && regdeps
[i
].link_to_qp_branch
8443 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8444 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8446 /* Treat like a taken branch */
8447 print_dependency ("Removing", i
);
8448 regdeps
[i
] = regdeps
[--regdepslen
];
8457 /* Examine the current instruction for dependency violations. */
8460 struct ia64_opcode
*idesc
;
8464 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8465 idesc
->name
, CURR_SLOT
.src_line
,
8466 idesc
->dependencies
->nchks
,
8467 idesc
->dependencies
->nregs
);
8470 /* Look through the list of currently marked resources; if the current
8471 instruction has the dependency in its chks list which uses that resource,
8472 check against the specific resources used.
8474 check_dependencies (idesc
);
8477 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8478 then add them to the list of marked resources.
8480 mark_resources (idesc
);
8482 /* There are several types of dependency semantics, and each has its own
8483 requirements for being cleared
8485 Instruction serialization (insns separated by interruption, rfi, or
8486 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8488 Data serialization (instruction serialization, or writer + srlz.d +
8489 reader, where writer and srlz.d are in separate groups) clears
8490 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8491 always be the case).
8493 Instruction group break (groups separated by stop, taken branch,
8494 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8496 update_dependencies (idesc
);
8498 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8499 warning. Keep track of as many as possible that are useful. */
8500 note_register_values (idesc
);
8502 /* We don't need or want this anymore. */
8503 md
.mem_offset
.hint
= 0;
8508 /* Translate one line of assembly. Pseudo ops and labels do not show
8514 char *saved_input_line_pointer
, *mnemonic
;
8515 const struct pseudo_opcode
*pdesc
;
8516 struct ia64_opcode
*idesc
;
8517 unsigned char qp_regno
;
8521 saved_input_line_pointer
= input_line_pointer
;
8522 input_line_pointer
= str
;
8524 /* extract the opcode (mnemonic): */
8526 mnemonic
= input_line_pointer
;
8527 ch
= get_symbol_end ();
8528 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
8531 *input_line_pointer
= ch
;
8532 (*pdesc
->handler
) (pdesc
->arg
);
8536 /* find the instruction descriptor matching the arguments: */
8538 idesc
= ia64_find_opcode (mnemonic
);
8539 *input_line_pointer
= ch
;
8542 as_bad ("Unknown opcode `%s'", mnemonic
);
8546 idesc
= parse_operands (idesc
);
8550 /* Handle the dynamic ops we can handle now: */
8551 if (idesc
->type
== IA64_TYPE_DYN
)
8553 if (strcmp (idesc
->name
, "add") == 0)
8555 if (CURR_SLOT
.opnd
[2].X_op
== O_register
8556 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
8560 ia64_free_opcode (idesc
);
8561 idesc
= ia64_find_opcode (mnemonic
);
8563 know (!idesc
->next
);
8566 else if (strcmp (idesc
->name
, "mov") == 0)
8568 enum ia64_opnd opnd1
, opnd2
;
8571 opnd1
= idesc
->operands
[0];
8572 opnd2
= idesc
->operands
[1];
8573 if (opnd1
== IA64_OPND_AR3
)
8575 else if (opnd2
== IA64_OPND_AR3
)
8579 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
8580 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
8584 ia64_free_opcode (idesc
);
8585 idesc
= ia64_find_opcode (mnemonic
);
8586 while (idesc
!= NULL
8587 && (idesc
->operands
[0] != opnd1
8588 || idesc
->operands
[1] != opnd2
))
8589 idesc
= get_next_opcode (idesc
);
8594 if (md
.qp
.X_op
== O_register
)
8595 qp_regno
= md
.qp
.X_add_number
- REG_P
;
8597 flags
= idesc
->flags
;
8599 if ((flags
& IA64_OPCODE_FIRST
) != 0)
8600 insn_group_break (1, 0, 0);
8602 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
8604 as_bad ("`%s' cannot be predicated", idesc
->name
);
8608 /* build the instruction: */
8609 CURR_SLOT
.qp_regno
= qp_regno
;
8610 CURR_SLOT
.idesc
= idesc
;
8611 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
8612 if (debug_type
== DEBUG_DWARF2
)
8613 dwarf2_where (&CURR_SLOT
.debug_line
);
8615 /* Add unwind entry, if there is one. */
8616 if (unwind
.current_entry
)
8618 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
8619 unwind
.current_entry
= NULL
;
8622 /* check for dependency violations */
8626 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8627 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8630 if ((flags
& IA64_OPCODE_LAST
) != 0)
8631 insn_group_break (1, 0, 0);
8633 md
.last_text_seg
= now_seg
;
8636 input_line_pointer
= saved_input_line_pointer
;
8639 /* Called when symbol NAME cannot be found in the symbol table.
8640 Should be used for dynamic valued symbols only. */
8642 md_undefined_symbol (name
)
8648 /* Called for any expression that can not be recognized. When the
8649 function is called, `input_line_pointer' will point to the start of
8655 enum pseudo_type pseudo_type
;
8660 switch (*input_line_pointer
)
8663 /* find what relocation pseudo-function we're dealing with: */
8665 ch
= *++input_line_pointer
;
8666 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
8667 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
8669 len
= strlen (pseudo_func
[i
].name
);
8670 if (strncmp (pseudo_func
[i
].name
+ 1,
8671 input_line_pointer
+ 1, len
- 1) == 0
8672 && !is_part_of_name (input_line_pointer
[len
]))
8674 input_line_pointer
+= len
;
8675 pseudo_type
= pseudo_func
[i
].type
;
8679 switch (pseudo_type
)
8681 case PSEUDO_FUNC_RELOC
:
8683 if (*input_line_pointer
!= '(')
8685 as_bad ("Expected '('");
8688 ++input_line_pointer
; /* skip '(' */
8690 if (*input_line_pointer
++ != ')')
8692 as_bad ("Missing ')'");
8695 if (e
->X_op
!= O_symbol
)
8697 if (e
->X_op
!= O_pseudo_fixup
)
8699 as_bad ("Not a symbolic expression");
8702 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
8703 && i
== FUNC_LT_RELATIVE
)
8704 i
= FUNC_LT_FPTR_RELATIVE
;
8707 as_bad ("Illegal combination of relocation functions");
8711 /* make sure gas doesn't get rid of local symbols that are used
8713 e
->X_op
= O_pseudo_fixup
;
8714 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
8717 case PSEUDO_FUNC_CONST
:
8718 e
->X_op
= O_constant
;
8719 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8722 case PSEUDO_FUNC_REG
:
8723 e
->X_op
= O_register
;
8724 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8728 name
= input_line_pointer
- 1;
8730 as_bad ("Unknown pseudo function `%s'", name
);
8736 ++input_line_pointer
;
8738 if (*input_line_pointer
!= ']')
8740 as_bad ("Closing bracket misssing");
8745 if (e
->X_op
!= O_register
)
8746 as_bad ("Register expected as index");
8748 ++input_line_pointer
;
8759 ignore_rest_of_line ();
8762 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8763 a section symbol plus some offset. For relocs involving @fptr(),
8764 directives we don't want such adjustments since we need to have the
8765 original symbol's name in the reloc. */
8767 ia64_fix_adjustable (fix
)
8770 /* Prevent all adjustments to global symbols */
8771 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
8774 switch (fix
->fx_r_type
)
8776 case BFD_RELOC_IA64_FPTR64I
:
8777 case BFD_RELOC_IA64_FPTR32MSB
:
8778 case BFD_RELOC_IA64_FPTR32LSB
:
8779 case BFD_RELOC_IA64_FPTR64MSB
:
8780 case BFD_RELOC_IA64_FPTR64LSB
:
8781 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8782 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8792 ia64_force_relocation (fix
)
8795 switch (fix
->fx_r_type
)
8797 case BFD_RELOC_IA64_FPTR64I
:
8798 case BFD_RELOC_IA64_FPTR32MSB
:
8799 case BFD_RELOC_IA64_FPTR32LSB
:
8800 case BFD_RELOC_IA64_FPTR64MSB
:
8801 case BFD_RELOC_IA64_FPTR64LSB
:
8803 case BFD_RELOC_IA64_LTOFF22
:
8804 case BFD_RELOC_IA64_LTOFF64I
:
8805 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8806 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8807 case BFD_RELOC_IA64_PLTOFF22
:
8808 case BFD_RELOC_IA64_PLTOFF64I
:
8809 case BFD_RELOC_IA64_PLTOFF64MSB
:
8810 case BFD_RELOC_IA64_PLTOFF64LSB
:
8819 /* Decide from what point a pc-relative relocation is relative to,
8820 relative to the pc-relative fixup. Er, relatively speaking. */
8822 ia64_pcrel_from_section (fix
, sec
)
8826 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
8828 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
8834 /* This is called whenever some data item (not an instruction) needs a
8835 fixup. We pick the right reloc code depending on the byteorder
8836 currently in effect. */
8838 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
8844 bfd_reloc_code_real_type code
;
8849 /* There are no reloc for 8 and 16 bit quantities, but we allow
8850 them here since they will work fine as long as the expression
8851 is fully defined at the end of the pass over the source file. */
8852 case 1: code
= BFD_RELOC_8
; break;
8853 case 2: code
= BFD_RELOC_16
; break;
8855 if (target_big_endian
)
8856 code
= BFD_RELOC_IA64_DIR32MSB
;
8858 code
= BFD_RELOC_IA64_DIR32LSB
;
8862 if (target_big_endian
)
8863 code
= BFD_RELOC_IA64_DIR64MSB
;
8865 code
= BFD_RELOC_IA64_DIR64LSB
;
8869 as_bad ("Unsupported fixup size %d", nbytes
);
8870 ignore_rest_of_line ();
8873 if (exp
->X_op
== O_pseudo_fixup
)
8876 exp
->X_op
= O_symbol
;
8877 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
8879 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
8880 /* We need to store the byte order in effect in case we're going
8881 to fix an 8 or 16 bit relocation (for which there no real
8882 relocs available). See md_apply_fix(). */
8883 fix
->tc_fix_data
.bigendian
= target_big_endian
;
8886 /* Return the actual relocation we wish to associate with the pseudo
8887 reloc described by SYM and R_TYPE. SYM should be one of the
8888 symbols in the pseudo_func array, or NULL. */
8890 static bfd_reloc_code_real_type
8891 ia64_gen_real_reloc_type (sym
, r_type
)
8893 bfd_reloc_code_real_type r_type
;
8895 bfd_reloc_code_real_type
new = 0;
8902 switch (S_GET_VALUE (sym
))
8904 case FUNC_FPTR_RELATIVE
:
8907 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
8908 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
8909 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
8910 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
8911 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
8916 case FUNC_GP_RELATIVE
:
8919 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
8920 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
8921 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
8922 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
8923 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
8924 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
8929 case FUNC_LT_RELATIVE
:
8932 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
8933 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
8938 case FUNC_PC_RELATIVE
:
8941 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
8942 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
8943 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
8944 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
8945 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
8946 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
8951 case FUNC_PLT_RELATIVE
:
8954 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
8955 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
8956 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
8957 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
8962 case FUNC_SEC_RELATIVE
:
8965 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
8966 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
8967 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
8968 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
8973 case FUNC_SEG_RELATIVE
:
8976 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
8977 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
8978 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
8979 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
8984 case FUNC_LTV_RELATIVE
:
8987 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
8988 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
8989 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
8990 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
8995 case FUNC_LT_FPTR_RELATIVE
:
8998 case BFD_RELOC_IA64_IMM22
:
8999 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9000 case BFD_RELOC_IA64_IMM64
:
9001 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9009 /* Hmmmm. Should this ever occur? */
9016 /* Here is where generate the appropriate reloc for pseudo relocation
9019 ia64_validate_fix (fix
)
9022 switch (fix
->fx_r_type
)
9024 case BFD_RELOC_IA64_FPTR64I
:
9025 case BFD_RELOC_IA64_FPTR32MSB
:
9026 case BFD_RELOC_IA64_FPTR64LSB
:
9027 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9028 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9029 if (fix
->fx_offset
!= 0)
9030 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9031 "No addend allowed in @fptr() relocation");
9041 fix_insn (fix
, odesc
, value
)
9043 const struct ia64_operand
*odesc
;
9046 bfd_vma insn
[3], t0
, t1
, control_bits
;
9051 slot
= fix
->fx_where
& 0x3;
9052 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9054 /* Bundles are always in little-endian byte order */
9055 t0
= bfd_getl64 (fixpos
);
9056 t1
= bfd_getl64 (fixpos
+ 8);
9057 control_bits
= t0
& 0x1f;
9058 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9059 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9060 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9063 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9065 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9066 insn
[2] |= (((value
& 0x7f) << 13)
9067 | (((value
>> 7) & 0x1ff) << 27)
9068 | (((value
>> 16) & 0x1f) << 22)
9069 | (((value
>> 21) & 0x1) << 21)
9070 | (((value
>> 63) & 0x1) << 36));
9072 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9074 if (value
& ~0x3fffffffffffffffULL
)
9075 err
= "integer operand out of range";
9076 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9077 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9079 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9082 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9083 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9084 | (((value
>> 0) & 0xfffff) << 13));
9087 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9090 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9092 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9093 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9094 md_number_to_chars (fixpos
+ 0, t0
, 8);
9095 md_number_to_chars (fixpos
+ 8, t1
, 8);
9098 /* Attempt to simplify or even eliminate a fixup. The return value is
9099 ignored; perhaps it was once meaningful, but now it is historical.
9100 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9102 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9105 md_apply_fix3 (fix
, valuep
, seg
)
9111 valueT value
= *valuep
;
9114 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9118 switch (fix
->fx_r_type
)
9120 case BFD_RELOC_IA64_DIR32MSB
:
9121 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9125 case BFD_RELOC_IA64_DIR32LSB
:
9126 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9130 case BFD_RELOC_IA64_DIR64MSB
:
9131 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9135 case BFD_RELOC_IA64_DIR64LSB
:
9136 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9146 switch (fix
->fx_r_type
)
9149 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9150 "%s must have a constant value",
9151 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9158 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9159 work. There should be a better way to handle this. */
9161 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9163 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9165 if (fix
->tc_fix_data
.bigendian
)
9166 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9168 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9174 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9181 /* Generate the BFD reloc to be stuck in the object file from the
9182 fixup used internally in the assembler. */
9184 tc_gen_reloc (sec
, fixp
)
9190 reloc
= xmalloc (sizeof (*reloc
));
9191 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9192 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9193 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9194 reloc
->addend
= fixp
->fx_offset
;
9195 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9199 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9200 "Cannot represent %s relocation in object file",
9201 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9206 /* Turn a string in input_line_pointer into a floating point constant
9207 of type TYPE, and store the appropriate bytes in *LIT. The number
9208 of LITTLENUMS emitted is stored in *SIZE. An error message is
9209 returned, or NULL on OK. */
9211 #define MAX_LITTLENUMS 5
9214 md_atof (type
, lit
, size
)
9219 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9220 LITTLENUM_TYPE
*word
;
9250 return "Bad call to MD_ATOF()";
9252 t
= atof_ieee (input_line_pointer
, type
, words
);
9254 input_line_pointer
= t
;
9255 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9257 for (word
= words
+ prec
- 1; prec
--;)
9259 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9260 lit
+= sizeof (LITTLENUM_TYPE
);
9265 /* Round up a section's size to the appropriate boundary. */
9267 md_section_align (seg
, size
)
9271 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9272 valueT mask
= ((valueT
) 1 << align
) - 1;
9274 return (size
+ mask
) & ~mask
;
9277 /* Handle ia64 specific semantics of the align directive. */
9280 ia64_md_do_align (n
, fill
, len
, max
)
9286 /* Fill any pending bundle with nops. */
9287 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
9288 ia64_flush_insns ();
9290 /* When we align code in a text section, emit a bundle of 3 nops instead of
9291 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9292 N is log base 2 of the requested alignment. */
9294 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
9297 /* Use mfi bundle of nops with no stop bits. */
9298 static const unsigned char be_nop
[]
9299 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9300 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9301 static const unsigned char le_nop
[]
9302 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9303 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9305 /* Make sure we are on a 16-byte boundary, in case someone has been
9306 putting data into a text section. */
9307 frag_align (4, 0, 0);
9309 if (target_big_endian
)
9310 frag_align_pattern (n
, be_nop
, 16, max
);
9312 frag_align_pattern (n
, le_nop
, 16, max
);