1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 /* IA-64 ABI section pseudo-ops. */
65 SPECIAL_SECTION_BSS
= 0,
67 SPECIAL_SECTION_SDATA
,
68 SPECIAL_SECTION_RODATA
,
69 SPECIAL_SECTION_COMMENT
,
70 SPECIAL_SECTION_UNWIND
,
71 SPECIAL_SECTION_UNWIND_INFO
,
72 /* HPUX specific section pseudo-ops. */
73 SPECIAL_SECTION_INIT_ARRAY
,
74 SPECIAL_SECTION_FINI_ARRAY
,
87 FUNC_LT_FPTR_RELATIVE
,
93 REG_FR
= (REG_GR
+ 128),
94 REG_AR
= (REG_FR
+ 128),
95 REG_CR
= (REG_AR
+ 128),
96 REG_P
= (REG_CR
+ 128),
97 REG_BR
= (REG_P
+ 64),
98 REG_IP
= (REG_BR
+ 8),
105 /* The following are pseudo-registers for use by gas only. */
117 /* The following pseudo-registers are used for unwind directives only: */
125 DYNREG_GR
= 0, /* dynamic general purpose register */
126 DYNREG_FR
, /* dynamic floating point register */
127 DYNREG_PR
, /* dynamic predicate register */
131 enum operand_match_result
134 OPERAND_OUT_OF_RANGE
,
138 /* On the ia64, we can't know the address of a text label until the
139 instructions are packed into a bundle. To handle this, we keep
140 track of the list of labels that appear in front of each
144 struct label_fix
*next
;
148 extern int target_big_endian
;
150 /* Characters which always start a comment. */
151 const char comment_chars
[] = "";
153 /* Characters which start a comment at the beginning of a line. */
154 const char line_comment_chars
[] = "#";
156 /* Characters which may be used to separate multiple commands on a
158 const char line_separator_chars
[] = ";";
160 /* Characters which are used to indicate an exponent in a floating
162 const char EXP_CHARS
[] = "eE";
164 /* Characters which mean that a number is a floating point constant,
166 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
168 /* ia64-specific option processing: */
170 const char *md_shortopts
= "m:N:x::";
172 struct option md_longopts
[] =
174 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
175 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
176 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
177 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
180 size_t md_longopts_size
= sizeof (md_longopts
);
184 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
185 struct hash_control
*reg_hash
; /* register name hash table */
186 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
187 struct hash_control
*const_hash
; /* constant hash table */
188 struct hash_control
*entry_hash
; /* code entry hint hash table */
190 symbolS
*regsym
[REG_NUM
];
192 /* If X_op is != O_absent, the registername for the instruction's
193 qualifying predicate. If NULL, p0 is assumed for instructions
194 that are predicatable. */
201 explicit_mode
: 1, /* which mode we're in */
202 default_explicit_mode
: 1, /* which mode is the default */
203 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
205 keep_pending_output
: 1;
207 /* Each bundle consists of up to three instructions. We keep
208 track of four most recent instructions so we can correctly set
209 the end_of_insn_group for the last instruction in a bundle. */
211 int num_slots_in_use
;
215 end_of_insn_group
: 1,
216 manual_bundling_on
: 1,
217 manual_bundling_off
: 1;
218 signed char user_template
; /* user-selected template, if any */
219 unsigned char qp_regno
; /* qualifying predicate */
220 /* This duplicates a good fraction of "struct fix" but we
221 can't use a "struct fix" instead since we can't call
222 fix_new_exp() until we know the address of the instruction. */
226 bfd_reloc_code_real_type code
;
227 enum ia64_opnd opnd
; /* type of operand in need of fix */
228 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
229 expressionS expr
; /* the value to be inserted */
231 fixup
[2]; /* at most two fixups per insn */
232 struct ia64_opcode
*idesc
;
233 struct label_fix
*label_fixups
;
234 struct label_fix
*tag_fixups
;
235 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
238 unsigned int src_line
;
239 struct dwarf2_line_info debug_line
;
247 struct dynreg
*next
; /* next dynamic register */
249 unsigned short base
; /* the base register number */
250 unsigned short num_regs
; /* # of registers in this set */
252 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
254 flagword flags
; /* ELF-header flags */
257 unsigned hint
:1; /* is this hint currently valid? */
258 bfd_vma offset
; /* mem.offset offset */
259 bfd_vma base
; /* mem.offset base */
262 int path
; /* number of alt. entry points seen */
263 const char **entry_labels
; /* labels of all alternate paths in
264 the current DV-checking block. */
265 int maxpaths
; /* size currently allocated for
267 /* Support for hardware errata workarounds. */
269 /* Record data about the last three insn groups. */
272 /* B-step workaround.
273 For each predicate register, this is set if the corresponding insn
274 group conditionally sets this register with one of the affected
277 /* B-step workaround.
278 For each general register, this is set if the corresponding insn
279 a) is conditional one one of the predicate registers for which
280 P_REG_SET is 1 in the corresponding entry of the previous group,
281 b) sets this general register with one of the affected
283 int g_reg_set_conditionally
[128];
287 int pointer_size
; /* size in bytes of a pointer */
288 int pointer_size_shift
; /* shift size of a pointer for alignment */
292 /* application registers: */
298 #define AR_BSPSTORE 18
313 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
314 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
315 {"ar.rsc", 16}, {"ar.bsp", 17},
316 {"ar.bspstore", 18}, {"ar.rnat", 19},
317 {"ar.fcr", 21}, {"ar.eflag", 24},
318 {"ar.csd", 25}, {"ar.ssd", 26},
319 {"ar.cflg", 27}, {"ar.fsr", 28},
320 {"ar.fir", 29}, {"ar.fdr", 30},
321 {"ar.ccv", 32}, {"ar.unat", 36},
322 {"ar.fpsr", 40}, {"ar.itc", 44},
323 {"ar.pfs", 64}, {"ar.lc", 65},
344 /* control registers: */
386 static const struct const_desc
393 /* PSR constant masks: */
396 {"psr.be", ((valueT
) 1) << 1},
397 {"psr.up", ((valueT
) 1) << 2},
398 {"psr.ac", ((valueT
) 1) << 3},
399 {"psr.mfl", ((valueT
) 1) << 4},
400 {"psr.mfh", ((valueT
) 1) << 5},
402 {"psr.ic", ((valueT
) 1) << 13},
403 {"psr.i", ((valueT
) 1) << 14},
404 {"psr.pk", ((valueT
) 1) << 15},
406 {"psr.dt", ((valueT
) 1) << 17},
407 {"psr.dfl", ((valueT
) 1) << 18},
408 {"psr.dfh", ((valueT
) 1) << 19},
409 {"psr.sp", ((valueT
) 1) << 20},
410 {"psr.pp", ((valueT
) 1) << 21},
411 {"psr.di", ((valueT
) 1) << 22},
412 {"psr.si", ((valueT
) 1) << 23},
413 {"psr.db", ((valueT
) 1) << 24},
414 {"psr.lp", ((valueT
) 1) << 25},
415 {"psr.tb", ((valueT
) 1) << 26},
416 {"psr.rt", ((valueT
) 1) << 27},
417 /* 28-31: reserved */
418 /* 32-33: cpl (current privilege level) */
419 {"psr.is", ((valueT
) 1) << 34},
420 {"psr.mc", ((valueT
) 1) << 35},
421 {"psr.it", ((valueT
) 1) << 36},
422 {"psr.id", ((valueT
) 1) << 37},
423 {"psr.da", ((valueT
) 1) << 38},
424 {"psr.dd", ((valueT
) 1) << 39},
425 {"psr.ss", ((valueT
) 1) << 40},
426 /* 41-42: ri (restart instruction) */
427 {"psr.ed", ((valueT
) 1) << 43},
428 {"psr.bn", ((valueT
) 1) << 44},
431 /* indirect register-sets/memory: */
440 { "CPUID", IND_CPUID
},
441 { "cpuid", IND_CPUID
},
453 /* Pseudo functions used to indicate relocation types (these functions
454 start with an at sign (@). */
476 /* reloc pseudo functions (these must come first!): */
477 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
478 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
479 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
480 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
481 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
482 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
483 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
484 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
485 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
487 /* mbtype4 constants: */
488 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
489 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
490 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
491 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
492 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
494 /* fclass constants: */
495 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
496 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
497 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
498 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
499 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
500 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
501 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
502 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
503 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
505 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
507 /* unwind-related constants: */
508 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
509 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
510 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
512 /* unwind-related registers: */
513 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
516 /* 41-bit nop opcodes (one per unit): */
517 static const bfd_vma nop
[IA64_NUM_UNITS
] =
519 0x0000000000LL
, /* NIL => break 0 */
520 0x0008000000LL
, /* I-unit nop */
521 0x0008000000LL
, /* M-unit nop */
522 0x4000000000LL
, /* B-unit nop */
523 0x0008000000LL
, /* F-unit nop */
524 0x0008000000LL
, /* L-"unit" nop */
525 0x0008000000LL
, /* X-unit nop */
528 /* Can't be `const' as it's passed to input routines (which have the
529 habit of setting temporary sentinels. */
530 static char special_section_name
[][20] =
532 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
533 {".IA_64.unwind"}, {".IA_64.unwind_info"},
534 {".init_array"}, {".fini_array"}
537 static char *special_linkonce_name
[] =
539 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
542 /* The best template for a particular sequence of up to three
544 #define N IA64_NUM_TYPES
545 static unsigned char best_template
[N
][N
][N
];
548 /* Resource dependencies currently in effect */
550 int depind
; /* dependency index */
551 const struct ia64_dependency
*dependency
; /* actual dependency */
552 unsigned specific
:1, /* is this a specific bit/regno? */
553 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
554 int index
; /* specific regno/bit within dependency */
555 int note
; /* optional qualifying note (0 if none) */
559 int insn_srlz
; /* current insn serialization state */
560 int data_srlz
; /* current data serialization state */
561 int qp_regno
; /* qualifying predicate for this usage */
562 char *file
; /* what file marked this dependency */
563 unsigned int line
; /* what line marked this dependency */
564 struct mem_offset mem_offset
; /* optional memory offset hint */
565 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
566 int path
; /* corresponding code entry index */
568 static int regdepslen
= 0;
569 static int regdepstotlen
= 0;
570 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
571 static const char *dv_sem
[] = { "none", "implied", "impliedf",
572 "data", "instr", "specific", "stop", "other" };
573 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
575 /* Current state of PR mutexation */
576 static struct qpmutex
{
579 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
580 static int qp_mutexeslen
= 0;
581 static int qp_mutexestotlen
= 0;
582 static valueT qp_safe_across_calls
= 0;
584 /* Current state of PR implications */
585 static struct qp_imply
{
588 unsigned p2_branched
:1;
590 } *qp_implies
= NULL
;
591 static int qp_implieslen
= 0;
592 static int qp_impliestotlen
= 0;
594 /* Keep track of static GR values so that indirect register usage can
595 sometimes be tracked. */
600 } gr_values
[128] = {{ 1, 0, 0 }};
602 /* These are the routines required to output the various types of
605 /* A slot_number is a frag address plus the slot index (0-2). We use the
606 frag address here so that if there is a section switch in the middle of
607 a function, then instructions emitted to a different section are not
608 counted. Since there may be more than one frag for a function, this
609 means we also need to keep track of which frag this address belongs to
610 so we can compute inter-frag distances. This also nicely solves the
611 problem with nops emitted for align directives, which can't easily be
612 counted, but can easily be derived from frag sizes. */
614 typedef struct unw_rec_list
{
616 unsigned long slot_number
;
618 struct unw_rec_list
*next
;
621 #define SLOT_NUM_NOT_SET (unsigned)-1
625 unsigned long next_slot_number
;
626 fragS
*next_slot_frag
;
628 /* Maintain a list of unwind entries for the current function. */
632 /* Any unwind entires that should be attached to the current slot
633 that an insn is being constructed for. */
634 unw_rec_list
*current_entry
;
636 /* These are used to create the unwind table entry for this function. */
639 symbolS
*info
; /* pointer to unwind info */
640 symbolS
*personality_routine
;
642 subsegT saved_text_subseg
;
643 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
645 /* TRUE if processing unwind directives in a prologue region. */
648 unsigned int prologue_count
; /* number of .prologues seen so far */
651 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
653 /* Forward delarations: */
654 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
655 static void set_section
PARAMS ((char *name
));
656 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
657 unsigned int, unsigned int));
658 static void dot_radix
PARAMS ((int));
659 static void dot_special_section
PARAMS ((int));
660 static void dot_proc
PARAMS ((int));
661 static void dot_fframe
PARAMS ((int));
662 static void dot_vframe
PARAMS ((int));
663 static void dot_vframesp
PARAMS ((int));
664 static void dot_vframepsp
PARAMS ((int));
665 static void dot_save
PARAMS ((int));
666 static void dot_restore
PARAMS ((int));
667 static void dot_restorereg
PARAMS ((int));
668 static void dot_restorereg_p
PARAMS ((int));
669 static void dot_handlerdata
PARAMS ((int));
670 static void dot_unwentry
PARAMS ((int));
671 static void dot_altrp
PARAMS ((int));
672 static void dot_savemem
PARAMS ((int));
673 static void dot_saveg
PARAMS ((int));
674 static void dot_savef
PARAMS ((int));
675 static void dot_saveb
PARAMS ((int));
676 static void dot_savegf
PARAMS ((int));
677 static void dot_spill
PARAMS ((int));
678 static void dot_spillreg
PARAMS ((int));
679 static void dot_spillmem
PARAMS ((int));
680 static void dot_spillreg_p
PARAMS ((int));
681 static void dot_spillmem_p
PARAMS ((int));
682 static void dot_label_state
PARAMS ((int));
683 static void dot_copy_state
PARAMS ((int));
684 static void dot_unwabi
PARAMS ((int));
685 static void dot_personality
PARAMS ((int));
686 static void dot_body
PARAMS ((int));
687 static void dot_prologue
PARAMS ((int));
688 static void dot_endp
PARAMS ((int));
689 static void dot_template
PARAMS ((int));
690 static void dot_regstk
PARAMS ((int));
691 static void dot_rot
PARAMS ((int));
692 static void dot_byteorder
PARAMS ((int));
693 static void dot_psr
PARAMS ((int));
694 static void dot_alias
PARAMS ((int));
695 static void dot_ln
PARAMS ((int));
696 static char *parse_section_name
PARAMS ((void));
697 static void dot_xdata
PARAMS ((int));
698 static void stmt_float_cons
PARAMS ((int));
699 static void stmt_cons_ua
PARAMS ((int));
700 static void dot_xfloat_cons
PARAMS ((int));
701 static void dot_xstringer
PARAMS ((int));
702 static void dot_xdata_ua
PARAMS ((int));
703 static void dot_xfloat_cons_ua
PARAMS ((int));
704 static void print_prmask
PARAMS ((valueT mask
));
705 static void dot_pred_rel
PARAMS ((int));
706 static void dot_reg_val
PARAMS ((int));
707 static void dot_dv_mode
PARAMS ((int));
708 static void dot_entry
PARAMS ((int));
709 static void dot_mem_offset
PARAMS ((int));
710 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
711 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
712 static void declare_register_set
PARAMS ((const char *, int, int));
713 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
714 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
717 static int parse_operand
PARAMS ((expressionS
*e
));
718 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
719 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
720 static void emit_one_bundle
PARAMS ((void));
721 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
722 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
723 bfd_reloc_code_real_type r_type
));
724 static void insn_group_break
PARAMS ((int, int, int));
725 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
726 struct rsrc
*, int depind
, int path
));
727 static void add_qp_mutex
PARAMS((valueT mask
));
728 static void add_qp_imply
PARAMS((int p1
, int p2
));
729 static void clear_qp_branch_flag
PARAMS((valueT mask
));
730 static void clear_qp_mutex
PARAMS((valueT mask
));
731 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
732 static void clear_register_values
PARAMS ((void));
733 static void print_dependency
PARAMS ((const char *action
, int depind
));
734 static void instruction_serialization
PARAMS ((void));
735 static void data_serialization
PARAMS ((void));
736 static void remove_marked_resource
PARAMS ((struct rsrc
*));
737 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
738 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
739 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
740 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
741 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
742 struct ia64_opcode
*, int, struct rsrc
[], int, int));
743 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
744 static void check_dependencies
PARAMS((struct ia64_opcode
*));
745 static void mark_resources
PARAMS((struct ia64_opcode
*));
746 static void update_dependencies
PARAMS((struct ia64_opcode
*));
747 static void note_register_values
PARAMS((struct ia64_opcode
*));
748 static int qp_mutex
PARAMS ((int, int, int));
749 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
750 static void output_vbyte_mem
PARAMS ((int, char *, char *));
751 static void count_output
PARAMS ((int, char *, char *));
752 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
753 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
754 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
755 static void output_P1_format
PARAMS ((vbyte_func
, int));
756 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
757 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
758 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
759 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
760 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
761 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
762 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
763 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
764 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
765 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
766 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
767 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
768 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
769 static char format_ab_reg
PARAMS ((int, int));
770 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
772 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
773 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
775 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
776 static void free_list_records
PARAMS ((unw_rec_list
*));
777 static unw_rec_list
*output_prologue
PARAMS ((void));
778 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
779 static unw_rec_list
*output_body
PARAMS ((void));
780 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
781 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
782 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
783 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
784 static unw_rec_list
*output_rp_when
PARAMS ((void));
785 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
786 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
787 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
788 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_pfs_when
PARAMS ((void));
790 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
791 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
792 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_preds_when
PARAMS ((void));
794 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
795 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
796 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
797 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
798 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
799 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
800 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
801 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
802 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
803 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
804 static unw_rec_list
*output_unat_when
PARAMS ((void));
805 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
806 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
808 static unw_rec_list
*output_lc_when
PARAMS ((void));
809 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
810 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
812 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
813 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
814 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
816 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
817 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
818 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
819 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
820 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
821 static unw_rec_list
*output_bsp_when
PARAMS ((void));
822 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
823 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
825 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
826 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
827 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
829 static unw_rec_list
*output_rnat_when
PARAMS ((void));
830 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
831 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
832 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
833 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
834 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
835 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
836 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
837 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
838 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
839 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
841 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
843 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
845 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
846 unsigned int, unsigned int));
847 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
848 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
849 static int calc_record_size
PARAMS ((unw_rec_list
*));
850 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
851 static int count_bits
PARAMS ((unsigned long));
852 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
853 unsigned long, fragS
*));
854 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
855 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
856 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
857 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
858 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
859 static int generate_unwind_image
PARAMS ((const char *));
861 /* Build the unwind section name by appending the (possibly stripped)
862 text section NAME to the unwind PREFIX. The resulting string
863 pointer is assigned to RESULT. The string is allocated on the
864 stack, so this must be a macro... */
865 #define make_unw_section_name(special, text_name, result) \
867 char *_prefix = special_section_name[special]; \
868 char *_suffix = text_name; \
869 size_t _prefix_len, _suffix_len; \
871 if (strncmp (text_name, ".gnu.linkonce.t.", \
872 sizeof (".gnu.linkonce.t.") - 1) == 0) \
874 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
875 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
877 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
878 _result = alloca (_prefix_len + _suffix_len + 1); \
879 memcpy (_result, _prefix, _prefix_len); \
880 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
881 _result[_prefix_len + _suffix_len] = '\0'; \
886 /* Determine if application register REGNUM resides in the integer
887 unit (as opposed to the memory unit). */
889 ar_is_in_integer_unit (reg
)
894 return (reg
== 64 /* pfs */
895 || reg
== 65 /* lc */
896 || reg
== 66 /* ec */
897 /* ??? ias accepts and puts these in the integer unit. */
898 || (reg
>= 112 && reg
<= 127));
901 /* Switch to section NAME and create section if necessary. It's
902 rather ugly that we have to manipulate input_line_pointer but I
903 don't see any other way to accomplish the same thing without
904 changing obj-elf.c (which may be the Right Thing, in the end). */
909 char *saved_input_line_pointer
;
911 saved_input_line_pointer
= input_line_pointer
;
912 input_line_pointer
= name
;
914 input_line_pointer
= saved_input_line_pointer
;
917 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
920 ia64_elf_section_flags (flags
, attr
, type
)
922 int attr
, type ATTRIBUTE_UNUSED
;
924 if (attr
& SHF_IA_64_SHORT
)
925 flags
|= SEC_SMALL_DATA
;
930 ia64_elf_section_type (str
, len
)
934 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
935 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
938 len
= sizeof (ELF_STRING_ia64_unwind_info_once
) - 1;
939 if (strncmp (str
, ELF_STRING_ia64_unwind_info_once
, len
) == 0)
942 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
943 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
944 return SHT_IA_64_UNWIND
;
946 len
= sizeof (ELF_STRING_ia64_unwind_once
) - 1;
947 if (strncmp (str
, ELF_STRING_ia64_unwind_once
, len
) == 0)
948 return SHT_IA_64_UNWIND
;
954 set_regstack (ins
, locs
, outs
, rots
)
955 unsigned int ins
, locs
, outs
, rots
;
960 sof
= ins
+ locs
+ outs
;
963 as_bad ("Size of frame exceeds maximum of 96 registers");
968 as_warn ("Size of rotating registers exceeds frame size");
971 md
.in
.base
= REG_GR
+ 32;
972 md
.loc
.base
= md
.in
.base
+ ins
;
973 md
.out
.base
= md
.loc
.base
+ locs
;
975 md
.in
.num_regs
= ins
;
976 md
.loc
.num_regs
= locs
;
977 md
.out
.num_regs
= outs
;
978 md
.rot
.num_regs
= rots
;
985 struct label_fix
*lfix
;
987 subsegT saved_subseg
;
990 if (!md
.last_text_seg
)
994 saved_subseg
= now_subseg
;
996 subseg_set (md
.last_text_seg
, 0);
998 while (md
.num_slots_in_use
> 0)
999 emit_one_bundle (); /* force out queued instructions */
1001 /* In case there are labels following the last instruction, resolve
1003 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1005 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1006 symbol_set_frag (lfix
->sym
, frag_now
);
1008 CURR_SLOT
.label_fixups
= 0;
1009 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1011 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1012 symbol_set_frag (lfix
->sym
, frag_now
);
1014 CURR_SLOT
.tag_fixups
= 0;
1016 /* In case there are unwind directives following the last instruction,
1017 resolve those now. We only handle body and prologue directives here.
1018 Give an error for others. */
1019 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1021 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1022 || ptr
->r
.type
== body
)
1024 ptr
->slot_number
= (unsigned long) frag_more (0);
1025 ptr
->slot_frag
= frag_now
;
1028 as_bad (_("Unwind directive not followed by an instruction."));
1030 unwind
.current_entry
= NULL
;
1032 subseg_set (saved_seg
, saved_subseg
);
1034 if (md
.qp
.X_op
== O_register
)
1035 as_bad ("qualifying predicate not followed by instruction");
1039 ia64_do_align (nbytes
)
1042 char *saved_input_line_pointer
= input_line_pointer
;
1044 input_line_pointer
= "";
1045 s_align_bytes (nbytes
);
1046 input_line_pointer
= saved_input_line_pointer
;
1050 ia64_cons_align (nbytes
)
1055 char *saved_input_line_pointer
= input_line_pointer
;
1056 input_line_pointer
= "";
1057 s_align_bytes (nbytes
);
1058 input_line_pointer
= saved_input_line_pointer
;
1062 /* Output COUNT bytes to a memory location. */
1063 static unsigned char *vbyte_mem_ptr
= NULL
;
1066 output_vbyte_mem (count
, ptr
, comment
)
1069 char *comment ATTRIBUTE_UNUSED
;
1072 if (vbyte_mem_ptr
== NULL
)
1077 for (x
= 0; x
< count
; x
++)
1078 *(vbyte_mem_ptr
++) = ptr
[x
];
1081 /* Count the number of bytes required for records. */
1082 static int vbyte_count
= 0;
1084 count_output (count
, ptr
, comment
)
1086 char *ptr ATTRIBUTE_UNUSED
;
1087 char *comment ATTRIBUTE_UNUSED
;
1089 vbyte_count
+= count
;
1093 output_R1_format (f
, rtype
, rlen
)
1095 unw_record_type rtype
;
1102 output_R3_format (f
, rtype
, rlen
);
1108 else if (rtype
!= prologue
)
1109 as_bad ("record type is not valid");
1111 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1112 (*f
) (1, &byte
, NULL
);
1116 output_R2_format (f
, mask
, grsave
, rlen
)
1123 mask
= (mask
& 0x0f);
1124 grsave
= (grsave
& 0x7f);
1126 bytes
[0] = (UNW_R2
| (mask
>> 1));
1127 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1128 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1129 (*f
) (count
, bytes
, NULL
);
1133 output_R3_format (f
, rtype
, rlen
)
1135 unw_record_type rtype
;
1142 output_R1_format (f
, rtype
, rlen
);
1148 else if (rtype
!= prologue
)
1149 as_bad ("record type is not valid");
1150 bytes
[0] = (UNW_R3
| r
);
1151 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1152 (*f
) (count
+ 1, bytes
, NULL
);
1156 output_P1_format (f
, brmask
)
1161 byte
= UNW_P1
| (brmask
& 0x1f);
1162 (*f
) (1, &byte
, NULL
);
1166 output_P2_format (f
, brmask
, gr
)
1172 brmask
= (brmask
& 0x1f);
1173 bytes
[0] = UNW_P2
| (brmask
>> 1);
1174 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1175 (*f
) (2, bytes
, NULL
);
1179 output_P3_format (f
, rtype
, reg
)
1181 unw_record_type rtype
;
1226 as_bad ("Invalid record type for P3 format.");
1228 bytes
[0] = (UNW_P3
| (r
>> 1));
1229 bytes
[1] = (((r
& 1) << 7) | reg
);
1230 (*f
) (2, bytes
, NULL
);
1234 output_P4_format (f
, imask
, imask_size
)
1236 unsigned char *imask
;
1237 unsigned long imask_size
;
1240 (*f
) (imask_size
, imask
, NULL
);
1244 output_P5_format (f
, grmask
, frmask
)
1247 unsigned long frmask
;
1250 grmask
= (grmask
& 0x0f);
1253 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1254 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1255 bytes
[3] = (frmask
& 0x000000ff);
1256 (*f
) (4, bytes
, NULL
);
1260 output_P6_format (f
, rtype
, rmask
)
1262 unw_record_type rtype
;
1268 if (rtype
== gr_mem
)
1270 else if (rtype
!= fr_mem
)
1271 as_bad ("Invalid record type for format P6");
1272 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1273 (*f
) (1, &byte
, NULL
);
1277 output_P7_format (f
, rtype
, w1
, w2
)
1279 unw_record_type rtype
;
1286 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1291 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1341 bytes
[0] = (UNW_P7
| r
);
1342 (*f
) (count
, bytes
, NULL
);
1346 output_P8_format (f
, rtype
, t
)
1348 unw_record_type rtype
;
1387 case bspstore_psprel
:
1390 case bspstore_sprel
:
1402 case priunat_when_gr
:
1405 case priunat_psprel
:
1411 case priunat_when_mem
:
1418 count
+= output_leb128 (bytes
+ 2, t
, 0);
1419 (*f
) (count
, bytes
, NULL
);
1423 output_P9_format (f
, grmask
, gr
)
1430 bytes
[1] = (grmask
& 0x0f);
1431 bytes
[2] = (gr
& 0x7f);
1432 (*f
) (3, bytes
, NULL
);
1436 output_P10_format (f
, abi
, context
)
1443 bytes
[1] = (abi
& 0xff);
1444 bytes
[2] = (context
& 0xff);
1445 (*f
) (3, bytes
, NULL
);
1449 output_B1_format (f
, rtype
, label
)
1451 unw_record_type rtype
;
1452 unsigned long label
;
1458 output_B4_format (f
, rtype
, label
);
1461 if (rtype
== copy_state
)
1463 else if (rtype
!= label_state
)
1464 as_bad ("Invalid record type for format B1");
1466 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1467 (*f
) (1, &byte
, NULL
);
1471 output_B2_format (f
, ecount
, t
)
1473 unsigned long ecount
;
1480 output_B3_format (f
, ecount
, t
);
1483 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1484 count
+= output_leb128 (bytes
+ 1, t
, 0);
1485 (*f
) (count
, bytes
, NULL
);
1489 output_B3_format (f
, ecount
, t
)
1491 unsigned long ecount
;
1498 output_B2_format (f
, ecount
, t
);
1502 count
+= output_leb128 (bytes
+ 1, t
, 0);
1503 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1504 (*f
) (count
, bytes
, NULL
);
1508 output_B4_format (f
, rtype
, label
)
1510 unw_record_type rtype
;
1511 unsigned long label
;
1518 output_B1_format (f
, rtype
, label
);
1522 if (rtype
== copy_state
)
1524 else if (rtype
!= label_state
)
1525 as_bad ("Invalid record type for format B1");
1527 bytes
[0] = (UNW_B4
| (r
<< 3));
1528 count
+= output_leb128 (bytes
+ 1, label
, 0);
1529 (*f
) (count
, bytes
, NULL
);
1533 format_ab_reg (ab
, reg
)
1540 ret
= (ab
<< 5) | reg
;
1545 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1547 unw_record_type rtype
;
1557 if (rtype
== spill_sprel
)
1559 else if (rtype
!= spill_psprel
)
1560 as_bad ("Invalid record type for format X1");
1561 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1562 count
+= output_leb128 (bytes
+ 2, t
, 0);
1563 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1564 (*f
) (count
, bytes
, NULL
);
1568 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1577 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1578 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1579 count
+= output_leb128 (bytes
+ 3, t
, 0);
1580 (*f
) (count
, bytes
, NULL
);
1584 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1586 unw_record_type rtype
;
1597 if (rtype
== spill_sprel_p
)
1599 else if (rtype
!= spill_psprel_p
)
1600 as_bad ("Invalid record type for format X3");
1601 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1602 bytes
[2] = format_ab_reg (ab
, reg
);
1603 count
+= output_leb128 (bytes
+ 3, t
, 0);
1604 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1605 (*f
) (count
, bytes
, NULL
);
1609 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1619 bytes
[1] = (qp
& 0x3f);
1620 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1621 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1622 count
+= output_leb128 (bytes
+ 4, t
, 0);
1623 (*f
) (count
, bytes
, NULL
);
1626 /* This function allocates a record list structure, and initializes fields. */
1628 static unw_rec_list
*
1629 alloc_record (unw_record_type t
)
1632 ptr
= xmalloc (sizeof (*ptr
));
1634 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1639 /* This function frees an entire list of record structures. */
1642 free_list_records (unw_rec_list
*first
)
1645 for (ptr
= first
; ptr
!= NULL
;)
1647 unw_rec_list
*tmp
= ptr
;
1649 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1650 && tmp
->r
.record
.r
.mask
.i
)
1651 free (tmp
->r
.record
.r
.mask
.i
);
1658 static unw_rec_list
*
1661 unw_rec_list
*ptr
= alloc_record (prologue
);
1662 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1666 static unw_rec_list
*
1667 output_prologue_gr (saved_mask
, reg
)
1668 unsigned int saved_mask
;
1671 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1672 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1673 ptr
->r
.record
.r
.grmask
= saved_mask
;
1674 ptr
->r
.record
.r
.grsave
= reg
;
1678 static unw_rec_list
*
1681 unw_rec_list
*ptr
= alloc_record (body
);
1685 static unw_rec_list
*
1686 output_mem_stack_f (size
)
1689 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1690 ptr
->r
.record
.p
.size
= size
;
1694 static unw_rec_list
*
1695 output_mem_stack_v ()
1697 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1701 static unw_rec_list
*
1705 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1706 ptr
->r
.record
.p
.gr
= gr
;
1710 static unw_rec_list
*
1711 output_psp_sprel (offset
)
1712 unsigned int offset
;
1714 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1715 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1719 static unw_rec_list
*
1722 unw_rec_list
*ptr
= alloc_record (rp_when
);
1726 static unw_rec_list
*
1730 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1731 ptr
->r
.record
.p
.gr
= gr
;
1735 static unw_rec_list
*
1739 unw_rec_list
*ptr
= alloc_record (rp_br
);
1740 ptr
->r
.record
.p
.br
= br
;
1744 static unw_rec_list
*
1745 output_rp_psprel (offset
)
1746 unsigned int offset
;
1748 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1749 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1753 static unw_rec_list
*
1754 output_rp_sprel (offset
)
1755 unsigned int offset
;
1757 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1758 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1762 static unw_rec_list
*
1765 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1769 static unw_rec_list
*
1773 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1774 ptr
->r
.record
.p
.gr
= gr
;
1778 static unw_rec_list
*
1779 output_pfs_psprel (offset
)
1780 unsigned int offset
;
1782 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1783 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1787 static unw_rec_list
*
1788 output_pfs_sprel (offset
)
1789 unsigned int offset
;
1791 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1792 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1796 static unw_rec_list
*
1797 output_preds_when ()
1799 unw_rec_list
*ptr
= alloc_record (preds_when
);
1803 static unw_rec_list
*
1804 output_preds_gr (gr
)
1807 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1808 ptr
->r
.record
.p
.gr
= gr
;
1812 static unw_rec_list
*
1813 output_preds_psprel (offset
)
1814 unsigned int offset
;
1816 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1817 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1821 static unw_rec_list
*
1822 output_preds_sprel (offset
)
1823 unsigned int offset
;
1825 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1826 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1830 static unw_rec_list
*
1831 output_fr_mem (mask
)
1834 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1835 ptr
->r
.record
.p
.rmask
= mask
;
1839 static unw_rec_list
*
1840 output_frgr_mem (gr_mask
, fr_mask
)
1841 unsigned int gr_mask
;
1842 unsigned int fr_mask
;
1844 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1845 ptr
->r
.record
.p
.grmask
= gr_mask
;
1846 ptr
->r
.record
.p
.frmask
= fr_mask
;
1850 static unw_rec_list
*
1851 output_gr_gr (mask
, reg
)
1855 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1856 ptr
->r
.record
.p
.grmask
= mask
;
1857 ptr
->r
.record
.p
.gr
= reg
;
1861 static unw_rec_list
*
1862 output_gr_mem (mask
)
1865 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1866 ptr
->r
.record
.p
.rmask
= mask
;
1870 static unw_rec_list
*
1871 output_br_mem (unsigned int mask
)
1873 unw_rec_list
*ptr
= alloc_record (br_mem
);
1874 ptr
->r
.record
.p
.brmask
= mask
;
1878 static unw_rec_list
*
1879 output_br_gr (save_mask
, reg
)
1880 unsigned int save_mask
;
1883 unw_rec_list
*ptr
= alloc_record (br_gr
);
1884 ptr
->r
.record
.p
.brmask
= save_mask
;
1885 ptr
->r
.record
.p
.gr
= reg
;
1889 static unw_rec_list
*
1890 output_spill_base (offset
)
1891 unsigned int offset
;
1893 unw_rec_list
*ptr
= alloc_record (spill_base
);
1894 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1898 static unw_rec_list
*
1901 unw_rec_list
*ptr
= alloc_record (unat_when
);
1905 static unw_rec_list
*
1909 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1910 ptr
->r
.record
.p
.gr
= gr
;
1914 static unw_rec_list
*
1915 output_unat_psprel (offset
)
1916 unsigned int offset
;
1918 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1919 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1923 static unw_rec_list
*
1924 output_unat_sprel (offset
)
1925 unsigned int offset
;
1927 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1928 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1932 static unw_rec_list
*
1935 unw_rec_list
*ptr
= alloc_record (lc_when
);
1939 static unw_rec_list
*
1943 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1944 ptr
->r
.record
.p
.gr
= gr
;
1948 static unw_rec_list
*
1949 output_lc_psprel (offset
)
1950 unsigned int offset
;
1952 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1953 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1957 static unw_rec_list
*
1958 output_lc_sprel (offset
)
1959 unsigned int offset
;
1961 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1962 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1966 static unw_rec_list
*
1969 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1973 static unw_rec_list
*
1977 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1978 ptr
->r
.record
.p
.gr
= gr
;
1982 static unw_rec_list
*
1983 output_fpsr_psprel (offset
)
1984 unsigned int offset
;
1986 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1987 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1991 static unw_rec_list
*
1992 output_fpsr_sprel (offset
)
1993 unsigned int offset
;
1995 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1996 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2000 static unw_rec_list
*
2001 output_priunat_when_gr ()
2003 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2007 static unw_rec_list
*
2008 output_priunat_when_mem ()
2010 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2014 static unw_rec_list
*
2015 output_priunat_gr (gr
)
2018 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2019 ptr
->r
.record
.p
.gr
= gr
;
2023 static unw_rec_list
*
2024 output_priunat_psprel (offset
)
2025 unsigned int offset
;
2027 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2028 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2032 static unw_rec_list
*
2033 output_priunat_sprel (offset
)
2034 unsigned int offset
;
2036 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2037 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2041 static unw_rec_list
*
2044 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2048 static unw_rec_list
*
2052 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2053 ptr
->r
.record
.p
.gr
= gr
;
2057 static unw_rec_list
*
2058 output_bsp_psprel (offset
)
2059 unsigned int offset
;
2061 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2062 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2066 static unw_rec_list
*
2067 output_bsp_sprel (offset
)
2068 unsigned int offset
;
2070 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2071 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2075 static unw_rec_list
*
2076 output_bspstore_when ()
2078 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2082 static unw_rec_list
*
2083 output_bspstore_gr (gr
)
2086 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2087 ptr
->r
.record
.p
.gr
= gr
;
2091 static unw_rec_list
*
2092 output_bspstore_psprel (offset
)
2093 unsigned int offset
;
2095 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2096 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2100 static unw_rec_list
*
2101 output_bspstore_sprel (offset
)
2102 unsigned int offset
;
2104 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2105 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2109 static unw_rec_list
*
2112 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2116 static unw_rec_list
*
2120 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2121 ptr
->r
.record
.p
.gr
= gr
;
2125 static unw_rec_list
*
2126 output_rnat_psprel (offset
)
2127 unsigned int offset
;
2129 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2130 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2134 static unw_rec_list
*
2135 output_rnat_sprel (offset
)
2136 unsigned int offset
;
2138 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2139 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2143 static unw_rec_list
*
2144 output_unwabi (abi
, context
)
2146 unsigned long context
;
2148 unw_rec_list
*ptr
= alloc_record (unwabi
);
2149 ptr
->r
.record
.p
.abi
= abi
;
2150 ptr
->r
.record
.p
.context
= context
;
2154 static unw_rec_list
*
2155 output_epilogue (unsigned long ecount
)
2157 unw_rec_list
*ptr
= alloc_record (epilogue
);
2158 ptr
->r
.record
.b
.ecount
= ecount
;
2162 static unw_rec_list
*
2163 output_label_state (unsigned long label
)
2165 unw_rec_list
*ptr
= alloc_record (label_state
);
2166 ptr
->r
.record
.b
.label
= label
;
2170 static unw_rec_list
*
2171 output_copy_state (unsigned long label
)
2173 unw_rec_list
*ptr
= alloc_record (copy_state
);
2174 ptr
->r
.record
.b
.label
= label
;
2178 static unw_rec_list
*
2179 output_spill_psprel (ab
, reg
, offset
)
2182 unsigned int offset
;
2184 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2185 ptr
->r
.record
.x
.ab
= ab
;
2186 ptr
->r
.record
.x
.reg
= reg
;
2187 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2191 static unw_rec_list
*
2192 output_spill_sprel (ab
, reg
, offset
)
2195 unsigned int offset
;
2197 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2198 ptr
->r
.record
.x
.ab
= ab
;
2199 ptr
->r
.record
.x
.reg
= reg
;
2200 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2204 static unw_rec_list
*
2205 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2208 unsigned int offset
;
2209 unsigned int predicate
;
2211 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2212 ptr
->r
.record
.x
.ab
= ab
;
2213 ptr
->r
.record
.x
.reg
= reg
;
2214 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2215 ptr
->r
.record
.x
.qp
= predicate
;
2219 static unw_rec_list
*
2220 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2223 unsigned int offset
;
2224 unsigned int predicate
;
2226 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2227 ptr
->r
.record
.x
.ab
= ab
;
2228 ptr
->r
.record
.x
.reg
= reg
;
2229 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2230 ptr
->r
.record
.x
.qp
= predicate
;
2234 static unw_rec_list
*
2235 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2238 unsigned int targ_reg
;
2241 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2242 ptr
->r
.record
.x
.ab
= ab
;
2243 ptr
->r
.record
.x
.reg
= reg
;
2244 ptr
->r
.record
.x
.treg
= targ_reg
;
2245 ptr
->r
.record
.x
.xy
= xy
;
2249 static unw_rec_list
*
2250 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2253 unsigned int targ_reg
;
2255 unsigned int predicate
;
2257 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2258 ptr
->r
.record
.x
.ab
= ab
;
2259 ptr
->r
.record
.x
.reg
= reg
;
2260 ptr
->r
.record
.x
.treg
= targ_reg
;
2261 ptr
->r
.record
.x
.xy
= xy
;
2262 ptr
->r
.record
.x
.qp
= predicate
;
2266 /* Given a unw_rec_list process the correct format with the
2267 specified function. */
2270 process_one_record (ptr
, f
)
2274 unsigned long fr_mask
, gr_mask
;
2276 switch (ptr
->r
.type
)
2282 /* These are taken care of by prologue/prologue_gr. */
2287 if (ptr
->r
.type
== prologue_gr
)
2288 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2289 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2291 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2293 /* Output descriptor(s) for union of register spills (if any). */
2294 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2295 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2298 if ((fr_mask
& ~0xfUL
) == 0)
2299 output_P6_format (f
, fr_mem
, fr_mask
);
2302 output_P5_format (f
, gr_mask
, fr_mask
);
2307 output_P6_format (f
, gr_mem
, gr_mask
);
2308 if (ptr
->r
.record
.r
.mask
.br_mem
)
2309 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2311 /* output imask descriptor if necessary: */
2312 if (ptr
->r
.record
.r
.mask
.i
)
2313 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2314 ptr
->r
.record
.r
.imask_size
);
2318 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2322 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2323 ptr
->r
.record
.p
.size
);
2336 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2339 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2342 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2350 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2359 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2369 case bspstore_sprel
:
2371 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2374 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2377 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2380 as_bad ("spill_mask record unimplemented.");
2382 case priunat_when_gr
:
2383 case priunat_when_mem
:
2387 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2389 case priunat_psprel
:
2391 case bspstore_psprel
:
2393 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2396 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2399 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2403 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2406 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2407 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2408 ptr
->r
.record
.x
.pspoff
);
2411 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2412 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2413 ptr
->r
.record
.x
.spoff
);
2416 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2417 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2418 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2420 case spill_psprel_p
:
2421 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2422 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2423 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2426 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2427 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2428 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2431 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2432 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2433 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2437 as_bad ("record_type_not_valid");
2442 /* Given a unw_rec_list list, process all the records with
2443 the specified function. */
2445 process_unw_records (list
, f
)
2450 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2451 process_one_record (ptr
, f
);
2454 /* Determine the size of a record list in bytes. */
2456 calc_record_size (list
)
2460 process_unw_records (list
, count_output
);
2464 /* Update IMASK bitmask to reflect the fact that one or more registers
2465 of type TYPE are saved starting at instruction with index T. If N
2466 bits are set in REGMASK, it is assumed that instructions T through
2467 T+N-1 save these registers.
2471 1: instruction saves next fp reg
2472 2: instruction saves next general reg
2473 3: instruction saves next branch reg */
2475 set_imask (region
, regmask
, t
, type
)
2476 unw_rec_list
*region
;
2477 unsigned long regmask
;
2481 unsigned char *imask
;
2482 unsigned long imask_size
;
2486 imask
= region
->r
.record
.r
.mask
.i
;
2487 imask_size
= region
->r
.record
.r
.imask_size
;
2490 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2491 imask
= xmalloc (imask_size
);
2492 memset (imask
, 0, imask_size
);
2494 region
->r
.record
.r
.imask_size
= imask_size
;
2495 region
->r
.record
.r
.mask
.i
= imask
;
2499 pos
= 2 * (3 - t
% 4);
2502 if (i
>= imask_size
)
2504 as_bad ("Ignoring attempt to spill beyond end of region");
2508 imask
[i
] |= (type
& 0x3) << pos
;
2510 regmask
&= (regmask
- 1);
2521 count_bits (unsigned long mask
)
2533 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2534 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2535 containing FIRST_ADDR. */
2538 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2539 unsigned long slot_addr
;
2541 unsigned long first_addr
;
2544 unsigned long index
= 0;
2546 /* First time we are called, the initial address and frag are invalid. */
2547 if (first_addr
== 0)
2550 /* If the two addresses are in different frags, then we need to add in
2551 the remaining size of this frag, and then the entire size of intermediate
2553 while (slot_frag
!= first_frag
)
2555 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2557 /* Add in the full size of the frag converted to instruction slots. */
2558 index
+= 3 * (first_frag
->fr_fix
>> 4);
2559 /* Subtract away the initial part before first_addr. */
2560 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2561 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2563 /* Move to the beginning of the next frag. */
2564 first_frag
= first_frag
->fr_next
;
2565 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2568 /* Add in the used part of the last frag. */
2569 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2570 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2574 /* Optimize unwind record directives. */
2576 static unw_rec_list
*
2577 optimize_unw_records (list
)
2583 /* If the only unwind record is ".prologue" or ".prologue" followed
2584 by ".body", then we can optimize the unwind directives away. */
2585 if (list
->r
.type
== prologue
2586 && (list
->next
== NULL
2587 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2593 /* Given a complete record list, process any records which have
2594 unresolved fields, (ie length counts for a prologue). After
2595 this has been run, all neccessary information should be available
2596 within each record to generate an image. */
2599 fixup_unw_records (list
)
2602 unw_rec_list
*ptr
, *region
= 0;
2603 unsigned long first_addr
= 0, rlen
= 0, t
;
2604 fragS
*first_frag
= 0;
2606 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2608 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2609 as_bad (" Insn slot not set in unwind record.");
2610 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2611 first_addr
, first_frag
);
2612 switch (ptr
->r
.type
)
2619 int size
, dir_len
= 0;
2620 unsigned long last_addr
;
2623 first_addr
= ptr
->slot_number
;
2624 first_frag
= ptr
->slot_frag
;
2625 ptr
->slot_number
= 0;
2626 /* Find either the next body/prologue start, or the end of
2627 the list, and determine the size of the region. */
2628 last_addr
= unwind
.next_slot_number
;
2629 last_frag
= unwind
.next_slot_frag
;
2630 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2631 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2632 || last
->r
.type
== body
)
2634 last_addr
= last
->slot_number
;
2635 last_frag
= last
->slot_frag
;
2638 else if (!last
->next
)
2640 /* In the absence of an explicit .body directive,
2641 the prologue ends after the last instruction
2642 covered by an unwind directive. */
2643 if (ptr
->r
.type
!= body
)
2645 last_addr
= last
->slot_number
;
2646 last_frag
= last
->slot_frag
;
2647 switch (last
->r
.type
)
2650 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2651 + count_bits (last
->r
.record
.p
.grmask
));
2655 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2659 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2662 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2671 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2673 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2678 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2689 case priunat_when_gr
:
2690 case priunat_when_mem
:
2694 ptr
->r
.record
.p
.t
= t
;
2702 case spill_psprel_p
:
2703 ptr
->r
.record
.x
.t
= t
;
2709 as_bad ("frgr_mem record before region record!\n");
2712 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2713 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2714 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2715 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2720 as_bad ("fr_mem record before region record!\n");
2723 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2724 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2729 as_bad ("gr_mem record before region record!\n");
2732 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2733 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2738 as_bad ("br_mem record before region record!\n");
2741 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2742 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2748 as_bad ("gr_gr record before region record!\n");
2751 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2756 as_bad ("br_gr record before region record!\n");
2759 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2768 /* Helper routine for output_unw_records. Emits the header for the unwind
2772 setup_unwind_header (int size
, unsigned char **mem
)
2776 /* pad to pointer-size boundry. */
2777 x
= size
% md
.pointer_size
;
2779 extra
= md
.pointer_size
- x
;
2781 /* Add 8 for the header + a pointer for the
2782 personality offset. */
2783 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2785 /* Clear the padding area and personality. */
2786 memset (*mem
+ 8 + size
, 0 , extra
+ md
.pointer_size
);
2787 /* Initialize the header area. */
2789 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* version */
2790 | (unwind
.personality_routine
2791 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2793 | ((size
+ extra
) / md
.pointer_size
)), /* length */
2799 /* Generate an unwind image from a record list. Returns the number of
2800 bytes in the resulting image. The memory image itselof is returned
2801 in the 'ptr' parameter. */
2803 output_unw_records (list
, ptr
)
2812 list
= optimize_unw_records (list
);
2813 fixup_unw_records (list
);
2814 size
= calc_record_size (list
);
2816 if (size
> 0 || unwind
.force_unwind_entry
)
2818 unwind
.force_unwind_entry
= 0;
2819 extra
= setup_unwind_header (size
, &mem
);
2821 vbyte_mem_ptr
= mem
+ 8;
2822 process_unw_records (list
, output_vbyte_mem
);
2826 size
+= extra
+ 8 + md
.pointer_size
;
2832 convert_expr_to_ab_reg (e
, ab
, regp
)
2839 if (e
->X_op
!= O_register
)
2842 reg
= e
->X_add_number
;
2843 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2846 *regp
= reg
- REG_GR
;
2848 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2849 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2852 *regp
= reg
- REG_FR
;
2854 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2857 *regp
= reg
- REG_BR
;
2864 case REG_PR
: *regp
= 0; break;
2865 case REG_PSP
: *regp
= 1; break;
2866 case REG_PRIUNAT
: *regp
= 2; break;
2867 case REG_BR
+ 0: *regp
= 3; break;
2868 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2869 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2870 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2871 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2872 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2873 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2874 case REG_AR
+ AR_LC
: *regp
= 10; break;
2884 convert_expr_to_xy_reg (e
, xy
, regp
)
2891 if (e
->X_op
!= O_register
)
2894 reg
= e
->X_add_number
;
2896 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2899 *regp
= reg
- REG_GR
;
2901 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2904 *regp
= reg
- REG_FR
;
2906 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2909 *regp
= reg
- REG_BR
;
2918 int dummy ATTRIBUTE_UNUSED
;
2923 radix
= *input_line_pointer
++;
2925 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2927 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2928 ignore_rest_of_line ();
2933 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2935 dot_special_section (which
)
2938 set_section ((char *) special_section_name
[which
]);
2942 add_unwind_entry (ptr
)
2946 unwind
.tail
->next
= ptr
;
2951 /* The current entry can in fact be a chain of unwind entries. */
2952 if (unwind
.current_entry
== NULL
)
2953 unwind
.current_entry
= ptr
;
2958 int dummy ATTRIBUTE_UNUSED
;
2964 if (e
.X_op
!= O_constant
)
2965 as_bad ("Operand to .fframe must be a constant");
2967 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2972 int dummy ATTRIBUTE_UNUSED
;
2978 reg
= e
.X_add_number
- REG_GR
;
2979 if (e
.X_op
== O_register
&& reg
< 128)
2981 add_unwind_entry (output_mem_stack_v ());
2982 if (! (unwind
.prologue_mask
& 2))
2983 add_unwind_entry (output_psp_gr (reg
));
2986 as_bad ("First operand to .vframe must be a general register");
2990 dot_vframesp (dummy
)
2991 int dummy ATTRIBUTE_UNUSED
;
2996 if (e
.X_op
== O_constant
)
2998 add_unwind_entry (output_mem_stack_v ());
2999 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3002 as_bad ("First operand to .vframesp must be a general register");
3006 dot_vframepsp (dummy
)
3007 int dummy ATTRIBUTE_UNUSED
;
3012 if (e
.X_op
== O_constant
)
3014 add_unwind_entry (output_mem_stack_v ());
3015 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3018 as_bad ("First operand to .vframepsp must be a general register");
3023 int dummy ATTRIBUTE_UNUSED
;
3029 sep
= parse_operand (&e1
);
3031 as_bad ("No second operand to .save");
3032 sep
= parse_operand (&e2
);
3034 reg1
= e1
.X_add_number
;
3035 reg2
= e2
.X_add_number
- REG_GR
;
3037 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3038 if (e1
.X_op
== O_register
)
3040 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3044 case REG_AR
+ AR_BSP
:
3045 add_unwind_entry (output_bsp_when ());
3046 add_unwind_entry (output_bsp_gr (reg2
));
3048 case REG_AR
+ AR_BSPSTORE
:
3049 add_unwind_entry (output_bspstore_when ());
3050 add_unwind_entry (output_bspstore_gr (reg2
));
3052 case REG_AR
+ AR_RNAT
:
3053 add_unwind_entry (output_rnat_when ());
3054 add_unwind_entry (output_rnat_gr (reg2
));
3056 case REG_AR
+ AR_UNAT
:
3057 add_unwind_entry (output_unat_when ());
3058 add_unwind_entry (output_unat_gr (reg2
));
3060 case REG_AR
+ AR_FPSR
:
3061 add_unwind_entry (output_fpsr_when ());
3062 add_unwind_entry (output_fpsr_gr (reg2
));
3064 case REG_AR
+ AR_PFS
:
3065 add_unwind_entry (output_pfs_when ());
3066 if (! (unwind
.prologue_mask
& 4))
3067 add_unwind_entry (output_pfs_gr (reg2
));
3069 case REG_AR
+ AR_LC
:
3070 add_unwind_entry (output_lc_when ());
3071 add_unwind_entry (output_lc_gr (reg2
));
3074 add_unwind_entry (output_rp_when ());
3075 if (! (unwind
.prologue_mask
& 8))
3076 add_unwind_entry (output_rp_gr (reg2
));
3079 add_unwind_entry (output_preds_when ());
3080 if (! (unwind
.prologue_mask
& 1))
3081 add_unwind_entry (output_preds_gr (reg2
));
3084 add_unwind_entry (output_priunat_when_gr ());
3085 add_unwind_entry (output_priunat_gr (reg2
));
3088 as_bad ("First operand not a valid register");
3092 as_bad (" Second operand not a valid register");
3095 as_bad ("First operand not a register");
3100 int dummy ATTRIBUTE_UNUSED
;
3103 unsigned long ecount
; /* # of _additional_ regions to pop */
3106 sep
= parse_operand (&e1
);
3107 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3109 as_bad ("First operand to .restore must be stack pointer (sp)");
3115 parse_operand (&e2
);
3116 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3118 as_bad ("Second operand to .restore must be a constant >= 0");
3121 ecount
= e2
.X_add_number
;
3124 ecount
= unwind
.prologue_count
- 1;
3125 add_unwind_entry (output_epilogue (ecount
));
3127 if (ecount
< unwind
.prologue_count
)
3128 unwind
.prologue_count
-= ecount
+ 1;
3130 unwind
.prologue_count
= 0;
3134 dot_restorereg (dummy
)
3135 int dummy ATTRIBUTE_UNUSED
;
3137 unsigned int ab
, reg
;
3142 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3144 as_bad ("First operand to .restorereg must be a preserved register");
3147 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3151 dot_restorereg_p (dummy
)
3152 int dummy ATTRIBUTE_UNUSED
;
3154 unsigned int qp
, ab
, reg
;
3158 sep
= parse_operand (&e1
);
3161 as_bad ("No second operand to .restorereg.p");
3165 parse_operand (&e2
);
3167 qp
= e1
.X_add_number
- REG_P
;
3168 if (e1
.X_op
!= O_register
|| qp
> 63)
3170 as_bad ("First operand to .restorereg.p must be a predicate");
3174 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3176 as_bad ("Second operand to .restorereg.p must be a preserved register");
3179 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3183 generate_unwind_image (text_name
)
3184 const char *text_name
;
3187 unsigned char *unw_rec
;
3189 /* Force out pending instructions, to make sure all unwind records have
3190 a valid slot_number field. */
3191 ia64_flush_insns ();
3193 /* Generate the unwind record. */
3194 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3195 if (size
% md
.pointer_size
!= 0)
3196 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3198 /* If there are unwind records, switch sections, and output the info. */
3201 unsigned char *where
;
3205 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3206 set_section (sec_name
);
3207 bfd_set_section_flags (stdoutput
, now_seg
,
3208 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3210 /* Make sure the section has 4 byte alignment for ILP32 and
3211 8 byte alignment for LP64. */
3212 frag_align (md
.pointer_size_shift
, 0, 0);
3213 record_alignment (now_seg
, md
.pointer_size_shift
);
3215 /* Set expression which points to start of unwind descriptor area. */
3216 unwind
.info
= expr_build_dot ();
3218 where
= (unsigned char *) frag_more (size
);
3220 /* Issue a label for this address, and keep track of it to put it
3221 in the unwind section. */
3223 /* Copy the information from the unwind record into this section. The
3224 data is already in the correct byte order. */
3225 memcpy (where
, unw_rec
, size
);
3227 /* Add the personality address to the image. */
3228 if (unwind
.personality_routine
!= 0)
3230 exp
.X_op
= O_symbol
;
3231 exp
.X_add_symbol
= unwind
.personality_routine
;
3232 exp
.X_add_number
= 0;
3233 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3234 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3235 unwind
.personality_routine
= 0;
3239 free_list_records (unwind
.list
);
3240 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3246 dot_handlerdata (dummy
)
3247 int dummy ATTRIBUTE_UNUSED
;
3249 const char *text_name
= segment_name (now_seg
);
3251 /* If text section name starts with ".text" (which it should),
3252 strip this prefix off. */
3253 if (strcmp (text_name
, ".text") == 0)
3256 unwind
.force_unwind_entry
= 1;
3258 /* Remember which segment we're in so we can switch back after .endp */
3259 unwind
.saved_text_seg
= now_seg
;
3260 unwind
.saved_text_subseg
= now_subseg
;
3262 /* Generate unwind info into unwind-info section and then leave that
3263 section as the currently active one so dataXX directives go into
3264 the language specific data area of the unwind info block. */
3265 generate_unwind_image (text_name
);
3266 demand_empty_rest_of_line ();
3270 dot_unwentry (dummy
)
3271 int dummy ATTRIBUTE_UNUSED
;
3273 unwind
.force_unwind_entry
= 1;
3274 demand_empty_rest_of_line ();
3279 int dummy ATTRIBUTE_UNUSED
;
3285 reg
= e
.X_add_number
- REG_BR
;
3286 if (e
.X_op
== O_register
&& reg
< 8)
3287 add_unwind_entry (output_rp_br (reg
));
3289 as_bad ("First operand not a valid branch register");
3293 dot_savemem (psprel
)
3300 sep
= parse_operand (&e1
);
3302 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3303 sep
= parse_operand (&e2
);
3305 reg1
= e1
.X_add_number
;
3306 val
= e2
.X_add_number
;
3308 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3309 if (e1
.X_op
== O_register
)
3311 if (e2
.X_op
== O_constant
)
3315 case REG_AR
+ AR_BSP
:
3316 add_unwind_entry (output_bsp_when ());
3317 add_unwind_entry ((psprel
3319 : output_bsp_sprel
) (val
));
3321 case REG_AR
+ AR_BSPSTORE
:
3322 add_unwind_entry (output_bspstore_when ());
3323 add_unwind_entry ((psprel
3324 ? output_bspstore_psprel
3325 : output_bspstore_sprel
) (val
));
3327 case REG_AR
+ AR_RNAT
:
3328 add_unwind_entry (output_rnat_when ());
3329 add_unwind_entry ((psprel
3330 ? output_rnat_psprel
3331 : output_rnat_sprel
) (val
));
3333 case REG_AR
+ AR_UNAT
:
3334 add_unwind_entry (output_unat_when ());
3335 add_unwind_entry ((psprel
3336 ? output_unat_psprel
3337 : output_unat_sprel
) (val
));
3339 case REG_AR
+ AR_FPSR
:
3340 add_unwind_entry (output_fpsr_when ());
3341 add_unwind_entry ((psprel
3342 ? output_fpsr_psprel
3343 : output_fpsr_sprel
) (val
));
3345 case REG_AR
+ AR_PFS
:
3346 add_unwind_entry (output_pfs_when ());
3347 add_unwind_entry ((psprel
3349 : output_pfs_sprel
) (val
));
3351 case REG_AR
+ AR_LC
:
3352 add_unwind_entry (output_lc_when ());
3353 add_unwind_entry ((psprel
3355 : output_lc_sprel
) (val
));
3358 add_unwind_entry (output_rp_when ());
3359 add_unwind_entry ((psprel
3361 : output_rp_sprel
) (val
));
3364 add_unwind_entry (output_preds_when ());
3365 add_unwind_entry ((psprel
3366 ? output_preds_psprel
3367 : output_preds_sprel
) (val
));
3370 add_unwind_entry (output_priunat_when_mem ());
3371 add_unwind_entry ((psprel
3372 ? output_priunat_psprel
3373 : output_priunat_sprel
) (val
));
3376 as_bad ("First operand not a valid register");
3380 as_bad (" Second operand not a valid constant");
3383 as_bad ("First operand not a register");
3388 int dummy ATTRIBUTE_UNUSED
;
3392 sep
= parse_operand (&e1
);
3394 parse_operand (&e2
);
3396 if (e1
.X_op
!= O_constant
)
3397 as_bad ("First operand to .save.g must be a constant.");
3400 int grmask
= e1
.X_add_number
;
3402 add_unwind_entry (output_gr_mem (grmask
));
3405 int reg
= e2
.X_add_number
- REG_GR
;
3406 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3407 add_unwind_entry (output_gr_gr (grmask
, reg
));
3409 as_bad ("Second operand is an invalid register.");
3416 int dummy ATTRIBUTE_UNUSED
;
3420 sep
= parse_operand (&e1
);
3422 if (e1
.X_op
!= O_constant
)
3423 as_bad ("Operand to .save.f must be a constant.");
3425 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3430 int dummy ATTRIBUTE_UNUSED
;
3437 sep
= parse_operand (&e1
);
3438 if (e1
.X_op
!= O_constant
)
3440 as_bad ("First operand to .save.b must be a constant.");
3443 brmask
= e1
.X_add_number
;
3447 sep
= parse_operand (&e2
);
3448 reg
= e2
.X_add_number
- REG_GR
;
3449 if (e2
.X_op
!= O_register
|| reg
> 127)
3451 as_bad ("Second operand to .save.b must be a general register.");
3454 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3457 add_unwind_entry (output_br_mem (brmask
));
3459 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3460 ignore_rest_of_line ();
3465 int dummy ATTRIBUTE_UNUSED
;
3469 sep
= parse_operand (&e1
);
3471 parse_operand (&e2
);
3473 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3474 as_bad ("Both operands of .save.gf must be constants.");
3477 int grmask
= e1
.X_add_number
;
3478 int frmask
= e2
.X_add_number
;
3479 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3485 int dummy ATTRIBUTE_UNUSED
;
3490 sep
= parse_operand (&e
);
3491 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3492 ignore_rest_of_line ();
3494 if (e
.X_op
!= O_constant
)
3495 as_bad ("Operand to .spill must be a constant");
3497 add_unwind_entry (output_spill_base (e
.X_add_number
));
3501 dot_spillreg (dummy
)
3502 int dummy ATTRIBUTE_UNUSED
;
3504 int sep
, ab
, xy
, reg
, treg
;
3507 sep
= parse_operand (&e1
);
3510 as_bad ("No second operand to .spillreg");
3514 parse_operand (&e2
);
3516 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3518 as_bad ("First operand to .spillreg must be a preserved register");
3522 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3524 as_bad ("Second operand to .spillreg must be a register");
3528 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3532 dot_spillmem (psprel
)
3538 sep
= parse_operand (&e1
);
3541 as_bad ("Second operand missing");
3545 parse_operand (&e2
);
3547 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3549 as_bad ("First operand to .spill%s must be a preserved register",
3550 psprel
? "psp" : "sp");
3554 if (e2
.X_op
!= O_constant
)
3556 as_bad ("Second operand to .spill%s must be a constant",
3557 psprel
? "psp" : "sp");
3562 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3564 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3568 dot_spillreg_p (dummy
)
3569 int dummy ATTRIBUTE_UNUSED
;
3571 int sep
, ab
, xy
, reg
, treg
;
3572 expressionS e1
, e2
, e3
;
3575 sep
= parse_operand (&e1
);
3578 as_bad ("No second and third operand to .spillreg.p");
3582 sep
= parse_operand (&e2
);
3585 as_bad ("No third operand to .spillreg.p");
3589 parse_operand (&e3
);
3591 qp
= e1
.X_add_number
- REG_P
;
3593 if (e1
.X_op
!= O_register
|| qp
> 63)
3595 as_bad ("First operand to .spillreg.p must be a predicate");
3599 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3601 as_bad ("Second operand to .spillreg.p must be a preserved register");
3605 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3607 as_bad ("Third operand to .spillreg.p must be a register");
3611 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3615 dot_spillmem_p (psprel
)
3618 expressionS e1
, e2
, e3
;
3622 sep
= parse_operand (&e1
);
3625 as_bad ("Second operand missing");
3629 parse_operand (&e2
);
3632 as_bad ("Second operand missing");
3636 parse_operand (&e3
);
3638 qp
= e1
.X_add_number
- REG_P
;
3639 if (e1
.X_op
!= O_register
|| qp
> 63)
3641 as_bad ("First operand to .spill%s_p must be a predicate",
3642 psprel
? "psp" : "sp");
3646 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3648 as_bad ("Second operand to .spill%s_p must be a preserved register",
3649 psprel
? "psp" : "sp");
3653 if (e3
.X_op
!= O_constant
)
3655 as_bad ("Third operand to .spill%s_p must be a constant",
3656 psprel
? "psp" : "sp");
3661 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3663 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3667 dot_label_state (dummy
)
3668 int dummy ATTRIBUTE_UNUSED
;
3673 if (e
.X_op
!= O_constant
)
3675 as_bad ("Operand to .label_state must be a constant");
3678 add_unwind_entry (output_label_state (e
.X_add_number
));
3682 dot_copy_state (dummy
)
3683 int dummy ATTRIBUTE_UNUSED
;
3688 if (e
.X_op
!= O_constant
)
3690 as_bad ("Operand to .copy_state must be a constant");
3693 add_unwind_entry (output_copy_state (e
.X_add_number
));
3698 int dummy ATTRIBUTE_UNUSED
;
3703 sep
= parse_operand (&e1
);
3706 as_bad ("Second operand to .unwabi missing");
3709 sep
= parse_operand (&e2
);
3710 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3711 ignore_rest_of_line ();
3713 if (e1
.X_op
!= O_constant
)
3715 as_bad ("First operand to .unwabi must be a constant");
3719 if (e2
.X_op
!= O_constant
)
3721 as_bad ("Second operand to .unwabi must be a constant");
3725 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3729 dot_personality (dummy
)
3730 int dummy ATTRIBUTE_UNUSED
;
3734 name
= input_line_pointer
;
3735 c
= get_symbol_end ();
3736 p
= input_line_pointer
;
3737 unwind
.personality_routine
= symbol_find_or_make (name
);
3738 unwind
.force_unwind_entry
= 1;
3741 demand_empty_rest_of_line ();
3746 int dummy ATTRIBUTE_UNUSED
;
3751 unwind
.proc_start
= expr_build_dot ();
3752 /* Parse names of main and alternate entry points and mark them as
3753 function symbols: */
3757 name
= input_line_pointer
;
3758 c
= get_symbol_end ();
3759 p
= input_line_pointer
;
3760 sym
= symbol_find_or_make (name
);
3761 if (unwind
.proc_start
== 0)
3763 unwind
.proc_start
= sym
;
3765 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3768 if (*input_line_pointer
!= ',')
3770 ++input_line_pointer
;
3772 demand_empty_rest_of_line ();
3775 unwind
.prologue_count
= 0;
3776 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3777 unwind
.personality_routine
= 0;
3782 int dummy ATTRIBUTE_UNUSED
;
3784 unwind
.prologue
= 0;
3785 unwind
.prologue_mask
= 0;
3787 add_unwind_entry (output_body ());
3788 demand_empty_rest_of_line ();
3792 dot_prologue (dummy
)
3793 int dummy ATTRIBUTE_UNUSED
;
3796 int mask
= 0, grsave
= 0;
3798 if (!is_it_end_of_statement ())
3801 sep
= parse_operand (&e1
);
3803 as_bad ("No second operand to .prologue");
3804 sep
= parse_operand (&e2
);
3805 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3806 ignore_rest_of_line ();
3808 if (e1
.X_op
== O_constant
)
3810 mask
= e1
.X_add_number
;
3812 if (e2
.X_op
== O_constant
)
3813 grsave
= e2
.X_add_number
;
3814 else if (e2
.X_op
== O_register
3815 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3818 as_bad ("Second operand not a constant or general register");
3820 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3823 as_bad ("First operand not a constant");
3826 add_unwind_entry (output_prologue ());
3828 unwind
.prologue
= 1;
3829 unwind
.prologue_mask
= mask
;
3830 ++unwind
.prologue_count
;
3835 int dummy ATTRIBUTE_UNUSED
;
3839 int bytes_per_address
;
3842 subsegT saved_subseg
;
3843 const char *sec_name
, *text_name
;
3847 if (unwind
.saved_text_seg
)
3849 saved_seg
= unwind
.saved_text_seg
;
3850 saved_subseg
= unwind
.saved_text_subseg
;
3851 unwind
.saved_text_seg
= NULL
;
3855 saved_seg
= now_seg
;
3856 saved_subseg
= now_subseg
;
3860 Use a slightly ugly scheme to derive the unwind section names from
3861 the text section name:
3863 text sect. unwind table sect.
3864 name: name: comments:
3865 ---------- ----------------- --------------------------------
3867 .text.foo .IA_64.unwind.text.foo
3868 .foo .IA_64.unwind.foo
3870 .gnu.linkonce.ia64unw.foo
3871 _info .IA_64.unwind_info gas issues error message (ditto)
3872 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3874 This mapping is done so that:
3876 (a) An object file with unwind info only in .text will use
3877 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3878 This follows the letter of the ABI and also ensures backwards
3879 compatibility with older toolchains.
3881 (b) An object file with unwind info in multiple text sections
3882 will use separate unwind sections for each text section.
3883 This allows us to properly set the "sh_info" and "sh_link"
3884 fields in SHT_IA_64_UNWIND as required by the ABI and also
3885 lets GNU ld support programs with multiple segments
3886 containing unwind info (as might be the case for certain
3887 embedded applications).
3889 (c) An error is issued if there would be a name clash.
3891 text_name
= segment_name (saved_seg
);
3892 if (strncmp (text_name
, "_info", 5) == 0)
3894 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3896 ignore_rest_of_line ();
3899 if (strcmp (text_name
, ".text") == 0)
3902 insn_group_break (1, 0, 0);
3904 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3906 generate_unwind_image (text_name
);
3908 if (unwind
.info
|| unwind
.force_unwind_entry
)
3910 subseg_set (md
.last_text_seg
, 0);
3911 unwind
.proc_end
= expr_build_dot ();
3913 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3914 set_section ((char *) sec_name
);
3915 bfd_set_section_flags (stdoutput
, now_seg
,
3916 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3918 /* Make sure that section has 4 byte alignment for ILP32 and
3919 8 byte alignment for LP64. */
3920 record_alignment (now_seg
, md
.pointer_size_shift
);
3922 /* Need space for 3 pointers for procedure start, procedure end,
3924 ptr
= frag_more (3 * md
.pointer_size
);
3925 where
= frag_now_fix () - (3 * md
.pointer_size
);
3926 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3928 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3929 e
.X_op
= O_pseudo_fixup
;
3930 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3932 e
.X_add_symbol
= unwind
.proc_start
;
3933 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3935 e
.X_op
= O_pseudo_fixup
;
3936 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3938 e
.X_add_symbol
= unwind
.proc_end
;
3939 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3940 bytes_per_address
, &e
);
3944 e
.X_op
= O_pseudo_fixup
;
3945 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3947 e
.X_add_symbol
= unwind
.info
;
3948 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3949 bytes_per_address
, &e
);
3952 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3956 subseg_set (saved_seg
, saved_subseg
);
3958 /* Parse names of main and alternate entry points and set symbol sizes. */
3962 name
= input_line_pointer
;
3963 c
= get_symbol_end ();
3964 p
= input_line_pointer
;
3965 sym
= symbol_find (name
);
3966 if (sym
&& unwind
.proc_start
3967 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
3968 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
3970 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
3971 fragS
*frag
= symbol_get_frag (sym
);
3973 /* Check whether the function label is at or beyond last
3975 while (fr
&& fr
!= frag
)
3979 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
3980 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
3983 symbol_get_obj (sym
)->size
=
3984 (expressionS
*) xmalloc (sizeof (expressionS
));
3985 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
3986 symbol_get_obj (sym
)->size
->X_add_symbol
3987 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
3988 frag_now_fix (), frag_now
);
3989 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
3990 symbol_get_obj (sym
)->size
->X_add_number
= 0;
3996 if (*input_line_pointer
!= ',')
3998 ++input_line_pointer
;
4000 demand_empty_rest_of_line ();
4001 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4005 dot_template (template)
4008 CURR_SLOT
.user_template
= template;
4013 int dummy ATTRIBUTE_UNUSED
;
4015 int ins
, locs
, outs
, rots
;
4017 if (is_it_end_of_statement ())
4018 ins
= locs
= outs
= rots
= 0;
4021 ins
= get_absolute_expression ();
4022 if (*input_line_pointer
++ != ',')
4024 locs
= get_absolute_expression ();
4025 if (*input_line_pointer
++ != ',')
4027 outs
= get_absolute_expression ();
4028 if (*input_line_pointer
++ != ',')
4030 rots
= get_absolute_expression ();
4032 set_regstack (ins
, locs
, outs
, rots
);
4036 as_bad ("Comma expected");
4037 ignore_rest_of_line ();
4044 unsigned num_regs
, num_alloced
= 0;
4045 struct dynreg
**drpp
, *dr
;
4046 int ch
, base_reg
= 0;
4052 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4053 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4054 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4058 /* First, remove existing names from hash table. */
4059 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4061 hash_delete (md
.dynreg_hash
, dr
->name
);
4065 drpp
= &md
.dynreg
[type
];
4068 start
= input_line_pointer
;
4069 ch
= get_symbol_end ();
4070 *input_line_pointer
= ch
;
4071 len
= (input_line_pointer
- start
);
4074 if (*input_line_pointer
!= '[')
4076 as_bad ("Expected '['");
4079 ++input_line_pointer
; /* skip '[' */
4081 num_regs
= get_absolute_expression ();
4083 if (*input_line_pointer
++ != ']')
4085 as_bad ("Expected ']'");
4090 num_alloced
+= num_regs
;
4094 if (num_alloced
> md
.rot
.num_regs
)
4096 as_bad ("Used more than the declared %d rotating registers",
4102 if (num_alloced
> 96)
4104 as_bad ("Used more than the available 96 rotating registers");
4109 if (num_alloced
> 48)
4111 as_bad ("Used more than the available 48 rotating registers");
4120 name
= obstack_alloc (¬es
, len
+ 1);
4121 memcpy (name
, start
, len
);
4126 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4127 memset (*drpp
, 0, sizeof (*dr
));
4132 dr
->num_regs
= num_regs
;
4133 dr
->base
= base_reg
;
4135 base_reg
+= num_regs
;
4137 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4139 as_bad ("Attempt to redefine register set `%s'", name
);
4143 if (*input_line_pointer
!= ',')
4145 ++input_line_pointer
; /* skip comma */
4148 demand_empty_rest_of_line ();
4152 ignore_rest_of_line ();
4156 dot_byteorder (byteorder
)
4159 target_big_endian
= byteorder
;
4164 int dummy ATTRIBUTE_UNUSED
;
4171 option
= input_line_pointer
;
4172 ch
= get_symbol_end ();
4173 if (strcmp (option
, "lsb") == 0)
4174 md
.flags
&= ~EF_IA_64_BE
;
4175 else if (strcmp (option
, "msb") == 0)
4176 md
.flags
|= EF_IA_64_BE
;
4177 else if (strcmp (option
, "abi32") == 0)
4178 md
.flags
&= ~EF_IA_64_ABI64
;
4179 else if (strcmp (option
, "abi64") == 0)
4180 md
.flags
|= EF_IA_64_ABI64
;
4182 as_bad ("Unknown psr option `%s'", option
);
4183 *input_line_pointer
= ch
;
4186 if (*input_line_pointer
!= ',')
4189 ++input_line_pointer
;
4192 demand_empty_rest_of_line ();
4197 int dummy ATTRIBUTE_UNUSED
;
4199 as_bad (".alias not implemented yet");
4204 int dummy ATTRIBUTE_UNUSED
;
4206 new_logical_line (0, get_absolute_expression ());
4207 demand_empty_rest_of_line ();
4211 parse_section_name ()
4217 if (*input_line_pointer
!= '"')
4219 as_bad ("Missing section name");
4220 ignore_rest_of_line ();
4223 name
= demand_copy_C_string (&len
);
4226 ignore_rest_of_line ();
4230 if (*input_line_pointer
!= ',')
4232 as_bad ("Comma expected after section name");
4233 ignore_rest_of_line ();
4236 ++input_line_pointer
; /* skip comma */
4244 char *name
= parse_section_name ();
4248 md
.keep_pending_output
= 1;
4251 obj_elf_previous (0);
4252 md
.keep_pending_output
= 0;
4255 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4258 stmt_float_cons (kind
)
4265 case 'd': size
= 8; break;
4266 case 'x': size
= 10; break;
4273 ia64_do_align (size
);
4281 int saved_auto_align
= md
.auto_align
;
4285 md
.auto_align
= saved_auto_align
;
4289 dot_xfloat_cons (kind
)
4292 char *name
= parse_section_name ();
4296 md
.keep_pending_output
= 1;
4298 stmt_float_cons (kind
);
4299 obj_elf_previous (0);
4300 md
.keep_pending_output
= 0;
4304 dot_xstringer (zero
)
4307 char *name
= parse_section_name ();
4311 md
.keep_pending_output
= 1;
4314 obj_elf_previous (0);
4315 md
.keep_pending_output
= 0;
4322 int saved_auto_align
= md
.auto_align
;
4323 char *name
= parse_section_name ();
4327 md
.keep_pending_output
= 1;
4331 md
.auto_align
= saved_auto_align
;
4332 obj_elf_previous (0);
4333 md
.keep_pending_output
= 0;
4337 dot_xfloat_cons_ua (kind
)
4340 int saved_auto_align
= md
.auto_align
;
4341 char *name
= parse_section_name ();
4345 md
.keep_pending_output
= 1;
4348 stmt_float_cons (kind
);
4349 md
.auto_align
= saved_auto_align
;
4350 obj_elf_previous (0);
4351 md
.keep_pending_output
= 0;
4354 /* .reg.val <regname>,value */
4358 int dummy ATTRIBUTE_UNUSED
;
4363 if (reg
.X_op
!= O_register
)
4365 as_bad (_("Register name expected"));
4366 ignore_rest_of_line ();
4368 else if (*input_line_pointer
++ != ',')
4370 as_bad (_("Comma expected"));
4371 ignore_rest_of_line ();
4375 valueT value
= get_absolute_expression ();
4376 int regno
= reg
.X_add_number
;
4377 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4378 as_warn (_("Register value annotation ignored"));
4381 gr_values
[regno
- REG_GR
].known
= 1;
4382 gr_values
[regno
- REG_GR
].value
= value
;
4383 gr_values
[regno
- REG_GR
].path
= md
.path
;
4386 demand_empty_rest_of_line ();
4389 /* select dv checking mode
4394 A stop is inserted when changing modes
4401 if (md
.manual_bundling
)
4402 as_warn (_("Directive invalid within a bundle"));
4404 if (type
== 'E' || type
== 'A')
4405 md
.mode_explicitly_set
= 0;
4407 md
.mode_explicitly_set
= 1;
4414 if (md
.explicit_mode
)
4415 insn_group_break (1, 0, 0);
4416 md
.explicit_mode
= 0;
4420 if (!md
.explicit_mode
)
4421 insn_group_break (1, 0, 0);
4422 md
.explicit_mode
= 1;
4426 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4427 insn_group_break (1, 0, 0);
4428 md
.explicit_mode
= md
.default_explicit_mode
;
4429 md
.mode_explicitly_set
= 0;
4440 for (regno
= 0; regno
< 64; regno
++)
4442 if (mask
& ((valueT
) 1 << regno
))
4444 fprintf (stderr
, "%s p%d", comma
, regno
);
4451 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4452 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4453 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4454 .pred.safe_across_calls p1 [, p2 [,...]]
4463 int p1
= -1, p2
= -1;
4467 if (*input_line_pointer
!= '"')
4469 as_bad (_("Missing predicate relation type"));
4470 ignore_rest_of_line ();
4476 char *form
= demand_copy_C_string (&len
);
4477 if (strcmp (form
, "mutex") == 0)
4479 else if (strcmp (form
, "clear") == 0)
4481 else if (strcmp (form
, "imply") == 0)
4485 as_bad (_("Unrecognized predicate relation type"));
4486 ignore_rest_of_line ();
4490 if (*input_line_pointer
== ',')
4491 ++input_line_pointer
;
4501 if (toupper (*input_line_pointer
) != 'P'
4502 || (regno
= atoi (++input_line_pointer
)) < 0
4505 as_bad (_("Predicate register expected"));
4506 ignore_rest_of_line ();
4509 while (isdigit (*input_line_pointer
))
4510 ++input_line_pointer
;
4517 as_warn (_("Duplicate predicate register ignored"));
4520 /* See if it's a range. */
4521 if (*input_line_pointer
== '-')
4524 ++input_line_pointer
;
4526 if (toupper (*input_line_pointer
) != 'P'
4527 || (regno
= atoi (++input_line_pointer
)) < 0
4530 as_bad (_("Predicate register expected"));
4531 ignore_rest_of_line ();
4534 while (isdigit (*input_line_pointer
))
4535 ++input_line_pointer
;
4539 as_bad (_("Bad register range"));
4540 ignore_rest_of_line ();
4551 if (*input_line_pointer
!= ',')
4553 ++input_line_pointer
;
4562 clear_qp_mutex (mask
);
4563 clear_qp_implies (mask
, (valueT
) 0);
4566 if (count
!= 2 || p1
== -1 || p2
== -1)
4567 as_bad (_("Predicate source and target required"));
4568 else if (p1
== 0 || p2
== 0)
4569 as_bad (_("Use of p0 is not valid in this context"));
4571 add_qp_imply (p1
, p2
);
4576 as_bad (_("At least two PR arguments expected"));
4581 as_bad (_("Use of p0 is not valid in this context"));
4584 add_qp_mutex (mask
);
4587 /* note that we don't override any existing relations */
4590 as_bad (_("At least one PR argument expected"));
4595 fprintf (stderr
, "Safe across calls: ");
4596 print_prmask (mask
);
4597 fprintf (stderr
, "\n");
4599 qp_safe_across_calls
= mask
;
4602 demand_empty_rest_of_line ();
4605 /* .entry label [, label [, ...]]
4606 Hint to DV code that the given labels are to be considered entry points.
4607 Otherwise, only global labels are considered entry points. */
4611 int dummy ATTRIBUTE_UNUSED
;
4620 name
= input_line_pointer
;
4621 c
= get_symbol_end ();
4622 symbolP
= symbol_find_or_make (name
);
4624 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4626 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4629 *input_line_pointer
= c
;
4631 c
= *input_line_pointer
;
4634 input_line_pointer
++;
4636 if (*input_line_pointer
== '\n')
4642 demand_empty_rest_of_line ();
4645 /* .mem.offset offset, base
4646 "base" is used to distinguish between offsets from a different base. */
4649 dot_mem_offset (dummy
)
4650 int dummy ATTRIBUTE_UNUSED
;
4652 md
.mem_offset
.hint
= 1;
4653 md
.mem_offset
.offset
= get_absolute_expression ();
4654 if (*input_line_pointer
!= ',')
4656 as_bad (_("Comma expected"));
4657 ignore_rest_of_line ();
4660 ++input_line_pointer
;
4661 md
.mem_offset
.base
= get_absolute_expression ();
4662 demand_empty_rest_of_line ();
4665 /* ia64-specific pseudo-ops: */
4666 const pseudo_typeS md_pseudo_table
[] =
4668 { "radix", dot_radix
, 0 },
4669 { "lcomm", s_lcomm_bytes
, 1 },
4670 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4671 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4672 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4673 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4674 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4675 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4676 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4677 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4678 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4679 { "proc", dot_proc
, 0 },
4680 { "body", dot_body
, 0 },
4681 { "prologue", dot_prologue
, 0 },
4682 { "endp", dot_endp
, 0 },
4683 { "file", dwarf2_directive_file
, 0 },
4684 { "loc", dwarf2_directive_loc
, 0 },
4686 { "fframe", dot_fframe
, 0 },
4687 { "vframe", dot_vframe
, 0 },
4688 { "vframesp", dot_vframesp
, 0 },
4689 { "vframepsp", dot_vframepsp
, 0 },
4690 { "save", dot_save
, 0 },
4691 { "restore", dot_restore
, 0 },
4692 { "restorereg", dot_restorereg
, 0 },
4693 { "restorereg.p", dot_restorereg_p
, 0 },
4694 { "handlerdata", dot_handlerdata
, 0 },
4695 { "unwentry", dot_unwentry
, 0 },
4696 { "altrp", dot_altrp
, 0 },
4697 { "savesp", dot_savemem
, 0 },
4698 { "savepsp", dot_savemem
, 1 },
4699 { "save.g", dot_saveg
, 0 },
4700 { "save.f", dot_savef
, 0 },
4701 { "save.b", dot_saveb
, 0 },
4702 { "save.gf", dot_savegf
, 0 },
4703 { "spill", dot_spill
, 0 },
4704 { "spillreg", dot_spillreg
, 0 },
4705 { "spillsp", dot_spillmem
, 0 },
4706 { "spillpsp", dot_spillmem
, 1 },
4707 { "spillreg.p", dot_spillreg_p
, 0 },
4708 { "spillsp.p", dot_spillmem_p
, 0 },
4709 { "spillpsp.p", dot_spillmem_p
, 1 },
4710 { "label_state", dot_label_state
, 0 },
4711 { "copy_state", dot_copy_state
, 0 },
4712 { "unwabi", dot_unwabi
, 0 },
4713 { "personality", dot_personality
, 0 },
4715 { "estate", dot_estate
, 0 },
4717 { "mii", dot_template
, 0x0 },
4718 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4719 { "mlx", dot_template
, 0x2 },
4720 { "mmi", dot_template
, 0x4 },
4721 { "mfi", dot_template
, 0x6 },
4722 { "mmf", dot_template
, 0x7 },
4723 { "mib", dot_template
, 0x8 },
4724 { "mbb", dot_template
, 0x9 },
4725 { "bbb", dot_template
, 0xb },
4726 { "mmb", dot_template
, 0xc },
4727 { "mfb", dot_template
, 0xe },
4729 { "lb", dot_scope
, 0 },
4730 { "le", dot_scope
, 1 },
4732 { "align", s_align_bytes
, 0 },
4733 { "regstk", dot_regstk
, 0 },
4734 { "rotr", dot_rot
, DYNREG_GR
},
4735 { "rotf", dot_rot
, DYNREG_FR
},
4736 { "rotp", dot_rot
, DYNREG_PR
},
4737 { "lsb", dot_byteorder
, 0 },
4738 { "msb", dot_byteorder
, 1 },
4739 { "psr", dot_psr
, 0 },
4740 { "alias", dot_alias
, 0 },
4741 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4743 { "xdata1", dot_xdata
, 1 },
4744 { "xdata2", dot_xdata
, 2 },
4745 { "xdata4", dot_xdata
, 4 },
4746 { "xdata8", dot_xdata
, 8 },
4747 { "xreal4", dot_xfloat_cons
, 'f' },
4748 { "xreal8", dot_xfloat_cons
, 'd' },
4749 { "xreal10", dot_xfloat_cons
, 'x' },
4750 { "xstring", dot_xstringer
, 0 },
4751 { "xstringz", dot_xstringer
, 1 },
4753 /* unaligned versions: */
4754 { "xdata2.ua", dot_xdata_ua
, 2 },
4755 { "xdata4.ua", dot_xdata_ua
, 4 },
4756 { "xdata8.ua", dot_xdata_ua
, 8 },
4757 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4758 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4759 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4761 /* annotations/DV checking support */
4762 { "entry", dot_entry
, 0 },
4763 { "mem.offset", dot_mem_offset
, 0 },
4764 { "pred.rel", dot_pred_rel
, 0 },
4765 { "pred.rel.clear", dot_pred_rel
, 'c' },
4766 { "pred.rel.imply", dot_pred_rel
, 'i' },
4767 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4768 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4769 { "reg.val", dot_reg_val
, 0 },
4770 { "auto", dot_dv_mode
, 'a' },
4771 { "explicit", dot_dv_mode
, 'e' },
4772 { "default", dot_dv_mode
, 'd' },
4774 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4775 IA-64 aligns data allocation pseudo-ops by default, so we have to
4776 tell it that these ones are supposed to be unaligned. Long term,
4777 should rewrite so that only IA-64 specific data allocation pseudo-ops
4778 are aligned by default. */
4779 {"2byte", stmt_cons_ua
, 2},
4780 {"4byte", stmt_cons_ua
, 4},
4781 {"8byte", stmt_cons_ua
, 8},
4786 static const struct pseudo_opcode
4789 void (*handler
) (int);
4794 /* these are more like pseudo-ops, but don't start with a dot */
4795 { "data1", cons
, 1 },
4796 { "data2", cons
, 2 },
4797 { "data4", cons
, 4 },
4798 { "data8", cons
, 8 },
4799 { "real4", stmt_float_cons
, 'f' },
4800 { "real8", stmt_float_cons
, 'd' },
4801 { "real10", stmt_float_cons
, 'x' },
4802 { "string", stringer
, 0 },
4803 { "stringz", stringer
, 1 },
4805 /* unaligned versions: */
4806 { "data2.ua", stmt_cons_ua
, 2 },
4807 { "data4.ua", stmt_cons_ua
, 4 },
4808 { "data8.ua", stmt_cons_ua
, 8 },
4809 { "real4.ua", float_cons
, 'f' },
4810 { "real8.ua", float_cons
, 'd' },
4811 { "real10.ua", float_cons
, 'x' },
4814 /* Declare a register by creating a symbol for it and entering it in
4815 the symbol table. */
4818 declare_register (name
, regnum
)
4825 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4827 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4829 as_fatal ("Inserting \"%s\" into register table failed: %s",
4836 declare_register_set (prefix
, num_regs
, base_regnum
)
4844 for (i
= 0; i
< num_regs
; ++i
)
4846 sprintf (name
, "%s%u", prefix
, i
);
4847 declare_register (name
, base_regnum
+ i
);
4852 operand_width (opnd
)
4853 enum ia64_opnd opnd
;
4855 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4856 unsigned int bits
= 0;
4860 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4861 bits
+= odesc
->field
[i
].bits
;
4866 static enum operand_match_result
4867 operand_match (idesc
, index
, e
)
4868 const struct ia64_opcode
*idesc
;
4872 enum ia64_opnd opnd
= idesc
->operands
[index
];
4873 int bits
, relocatable
= 0;
4874 struct insn_fix
*fix
;
4881 case IA64_OPND_AR_CCV
:
4882 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4883 return OPERAND_MATCH
;
4886 case IA64_OPND_AR_PFS
:
4887 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4888 return OPERAND_MATCH
;
4892 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4893 return OPERAND_MATCH
;
4897 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4898 return OPERAND_MATCH
;
4902 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4903 return OPERAND_MATCH
;
4906 case IA64_OPND_PR_ROT
:
4907 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4908 return OPERAND_MATCH
;
4912 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4913 return OPERAND_MATCH
;
4916 case IA64_OPND_PSR_L
:
4917 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4918 return OPERAND_MATCH
;
4921 case IA64_OPND_PSR_UM
:
4922 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4923 return OPERAND_MATCH
;
4927 if (e
->X_op
== O_constant
)
4929 if (e
->X_add_number
== 1)
4930 return OPERAND_MATCH
;
4932 return OPERAND_OUT_OF_RANGE
;
4937 if (e
->X_op
== O_constant
)
4939 if (e
->X_add_number
== 8)
4940 return OPERAND_MATCH
;
4942 return OPERAND_OUT_OF_RANGE
;
4947 if (e
->X_op
== O_constant
)
4949 if (e
->X_add_number
== 16)
4950 return OPERAND_MATCH
;
4952 return OPERAND_OUT_OF_RANGE
;
4956 /* register operands: */
4959 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4960 && e
->X_add_number
< REG_AR
+ 128)
4961 return OPERAND_MATCH
;
4966 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4967 && e
->X_add_number
< REG_BR
+ 8)
4968 return OPERAND_MATCH
;
4972 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4973 && e
->X_add_number
< REG_CR
+ 128)
4974 return OPERAND_MATCH
;
4981 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4982 && e
->X_add_number
< REG_FR
+ 128)
4983 return OPERAND_MATCH
;
4988 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4989 && e
->X_add_number
< REG_P
+ 64)
4990 return OPERAND_MATCH
;
4996 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4997 && e
->X_add_number
< REG_GR
+ 128)
4998 return OPERAND_MATCH
;
5001 case IA64_OPND_R3_2
:
5002 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5004 if (e
->X_add_number
< REG_GR
+ 4)
5005 return OPERAND_MATCH
;
5006 else if (e
->X_add_number
< REG_GR
+ 128)
5007 return OPERAND_OUT_OF_RANGE
;
5011 /* indirect operands: */
5012 case IA64_OPND_CPUID_R3
:
5013 case IA64_OPND_DBR_R3
:
5014 case IA64_OPND_DTR_R3
:
5015 case IA64_OPND_ITR_R3
:
5016 case IA64_OPND_IBR_R3
:
5017 case IA64_OPND_MSR_R3
:
5018 case IA64_OPND_PKR_R3
:
5019 case IA64_OPND_PMC_R3
:
5020 case IA64_OPND_PMD_R3
:
5021 case IA64_OPND_RR_R3
:
5022 if (e
->X_op
== O_index
&& e
->X_op_symbol
5023 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5024 == opnd
- IA64_OPND_CPUID_R3
))
5025 return OPERAND_MATCH
;
5029 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5030 return OPERAND_MATCH
;
5033 /* immediate operands: */
5034 case IA64_OPND_CNT2a
:
5035 case IA64_OPND_LEN4
:
5036 case IA64_OPND_LEN6
:
5037 bits
= operand_width (idesc
->operands
[index
]);
5038 if (e
->X_op
== O_constant
)
5040 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5041 return OPERAND_MATCH
;
5043 return OPERAND_OUT_OF_RANGE
;
5047 case IA64_OPND_CNT2b
:
5048 if (e
->X_op
== O_constant
)
5050 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5051 return OPERAND_MATCH
;
5053 return OPERAND_OUT_OF_RANGE
;
5057 case IA64_OPND_CNT2c
:
5058 val
= e
->X_add_number
;
5059 if (e
->X_op
== O_constant
)
5061 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5062 return OPERAND_MATCH
;
5064 return OPERAND_OUT_OF_RANGE
;
5069 /* SOR must be an integer multiple of 8 */
5070 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5071 return OPERAND_OUT_OF_RANGE
;
5074 if (e
->X_op
== O_constant
)
5076 if ((bfd_vma
) e
->X_add_number
<= 96)
5077 return OPERAND_MATCH
;
5079 return OPERAND_OUT_OF_RANGE
;
5083 case IA64_OPND_IMMU62
:
5084 if (e
->X_op
== O_constant
)
5086 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5087 return OPERAND_MATCH
;
5089 return OPERAND_OUT_OF_RANGE
;
5093 /* FIXME -- need 62-bit relocation type */
5094 as_bad (_("62-bit relocation not yet implemented"));
5098 case IA64_OPND_IMMU64
:
5099 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5100 || e
->X_op
== O_subtract
)
5102 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5103 fix
->code
= BFD_RELOC_IA64_IMM64
;
5104 if (e
->X_op
!= O_subtract
)
5106 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5107 if (e
->X_op
== O_pseudo_fixup
)
5111 fix
->opnd
= idesc
->operands
[index
];
5114 ++CURR_SLOT
.num_fixups
;
5115 return OPERAND_MATCH
;
5117 else if (e
->X_op
== O_constant
)
5118 return OPERAND_MATCH
;
5121 case IA64_OPND_CCNT5
:
5122 case IA64_OPND_CNT5
:
5123 case IA64_OPND_CNT6
:
5124 case IA64_OPND_CPOS6a
:
5125 case IA64_OPND_CPOS6b
:
5126 case IA64_OPND_CPOS6c
:
5127 case IA64_OPND_IMMU2
:
5128 case IA64_OPND_IMMU7a
:
5129 case IA64_OPND_IMMU7b
:
5130 case IA64_OPND_IMMU21
:
5131 case IA64_OPND_IMMU24
:
5132 case IA64_OPND_MBTYPE4
:
5133 case IA64_OPND_MHTYPE8
:
5134 case IA64_OPND_POS6
:
5135 bits
= operand_width (idesc
->operands
[index
]);
5136 if (e
->X_op
== O_constant
)
5138 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5139 return OPERAND_MATCH
;
5141 return OPERAND_OUT_OF_RANGE
;
5145 case IA64_OPND_IMMU9
:
5146 bits
= operand_width (idesc
->operands
[index
]);
5147 if (e
->X_op
== O_constant
)
5149 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5151 int lobits
= e
->X_add_number
& 0x3;
5152 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5153 e
->X_add_number
|= (bfd_vma
) 0x3;
5154 return OPERAND_MATCH
;
5157 return OPERAND_OUT_OF_RANGE
;
5161 case IA64_OPND_IMM44
:
5162 /* least 16 bits must be zero */
5163 if ((e
->X_add_number
& 0xffff) != 0)
5164 /* XXX technically, this is wrong: we should not be issuing warning
5165 messages until we're sure this instruction pattern is going to
5167 as_warn (_("lower 16 bits of mask ignored"));
5169 if (e
->X_op
== O_constant
)
5171 if (((e
->X_add_number
>= 0
5172 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5173 || (e
->X_add_number
< 0
5174 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5177 if (e
->X_add_number
>= 0
5178 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5180 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5182 return OPERAND_MATCH
;
5185 return OPERAND_OUT_OF_RANGE
;
5189 case IA64_OPND_IMM17
:
5190 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5191 if (e
->X_op
== O_constant
)
5193 if (((e
->X_add_number
>= 0
5194 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5195 || (e
->X_add_number
< 0
5196 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5199 if (e
->X_add_number
>= 0
5200 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5202 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5204 return OPERAND_MATCH
;
5207 return OPERAND_OUT_OF_RANGE
;
5211 case IA64_OPND_IMM14
:
5212 case IA64_OPND_IMM22
:
5214 case IA64_OPND_IMM1
:
5215 case IA64_OPND_IMM8
:
5216 case IA64_OPND_IMM8U4
:
5217 case IA64_OPND_IMM8M1
:
5218 case IA64_OPND_IMM8M1U4
:
5219 case IA64_OPND_IMM8M1U8
:
5220 case IA64_OPND_IMM9a
:
5221 case IA64_OPND_IMM9b
:
5222 bits
= operand_width (idesc
->operands
[index
]);
5223 if (relocatable
&& (e
->X_op
== O_symbol
5224 || e
->X_op
== O_subtract
5225 || e
->X_op
== O_pseudo_fixup
))
5227 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5229 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5230 fix
->code
= BFD_RELOC_IA64_IMM14
;
5232 fix
->code
= BFD_RELOC_IA64_IMM22
;
5234 if (e
->X_op
!= O_subtract
)
5236 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5237 if (e
->X_op
== O_pseudo_fixup
)
5241 fix
->opnd
= idesc
->operands
[index
];
5244 ++CURR_SLOT
.num_fixups
;
5245 return OPERAND_MATCH
;
5247 else if (e
->X_op
!= O_constant
5248 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5249 return OPERAND_MISMATCH
;
5251 if (opnd
== IA64_OPND_IMM8M1U4
)
5253 /* Zero is not valid for unsigned compares that take an adjusted
5254 constant immediate range. */
5255 if (e
->X_add_number
== 0)
5256 return OPERAND_OUT_OF_RANGE
;
5258 /* Sign-extend 32-bit unsigned numbers, so that the following range
5259 checks will work. */
5260 val
= e
->X_add_number
;
5261 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5262 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5263 val
= ((val
<< 32) >> 32);
5265 /* Check for 0x100000000. This is valid because
5266 0x100000000-1 is the same as ((uint32_t) -1). */
5267 if (val
== ((bfd_signed_vma
) 1 << 32))
5268 return OPERAND_MATCH
;
5272 else if (opnd
== IA64_OPND_IMM8M1U8
)
5274 /* Zero is not valid for unsigned compares that take an adjusted
5275 constant immediate range. */
5276 if (e
->X_add_number
== 0)
5277 return OPERAND_OUT_OF_RANGE
;
5279 /* Check for 0x10000000000000000. */
5280 if (e
->X_op
== O_big
)
5282 if (generic_bignum
[0] == 0
5283 && generic_bignum
[1] == 0
5284 && generic_bignum
[2] == 0
5285 && generic_bignum
[3] == 0
5286 && generic_bignum
[4] == 1)
5287 return OPERAND_MATCH
;
5289 return OPERAND_OUT_OF_RANGE
;
5292 val
= e
->X_add_number
- 1;
5294 else if (opnd
== IA64_OPND_IMM8M1
)
5295 val
= e
->X_add_number
- 1;
5296 else if (opnd
== IA64_OPND_IMM8U4
)
5298 /* Sign-extend 32-bit unsigned numbers, so that the following range
5299 checks will work. */
5300 val
= e
->X_add_number
;
5301 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5302 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5303 val
= ((val
<< 32) >> 32);
5306 val
= e
->X_add_number
;
5308 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5309 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5310 return OPERAND_MATCH
;
5312 return OPERAND_OUT_OF_RANGE
;
5314 case IA64_OPND_INC3
:
5315 /* +/- 1, 4, 8, 16 */
5316 val
= e
->X_add_number
;
5319 if (e
->X_op
== O_constant
)
5321 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5322 return OPERAND_MATCH
;
5324 return OPERAND_OUT_OF_RANGE
;
5328 case IA64_OPND_TGT25
:
5329 case IA64_OPND_TGT25b
:
5330 case IA64_OPND_TGT25c
:
5331 case IA64_OPND_TGT64
:
5332 if (e
->X_op
== O_symbol
)
5334 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5335 if (opnd
== IA64_OPND_TGT25
)
5336 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5337 else if (opnd
== IA64_OPND_TGT25b
)
5338 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5339 else if (opnd
== IA64_OPND_TGT25c
)
5340 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5341 else if (opnd
== IA64_OPND_TGT64
)
5342 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5346 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5347 fix
->opnd
= idesc
->operands
[index
];
5350 ++CURR_SLOT
.num_fixups
;
5351 return OPERAND_MATCH
;
5353 case IA64_OPND_TAG13
:
5354 case IA64_OPND_TAG13b
:
5358 return OPERAND_MATCH
;
5361 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5362 /* There are no external relocs for TAG13/TAG13b fields, so we
5363 create a dummy reloc. This will not live past md_apply_fix3. */
5364 fix
->code
= BFD_RELOC_UNUSED
;
5365 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5366 fix
->opnd
= idesc
->operands
[index
];
5369 ++CURR_SLOT
.num_fixups
;
5370 return OPERAND_MATCH
;
5380 return OPERAND_MISMATCH
;
5389 memset (e
, 0, sizeof (*e
));
5392 if (*input_line_pointer
!= '}')
5394 sep
= *input_line_pointer
++;
5398 if (!md
.manual_bundling
)
5399 as_warn ("Found '}' when manual bundling is off");
5401 CURR_SLOT
.manual_bundling_off
= 1;
5402 md
.manual_bundling
= 0;
5408 /* Returns the next entry in the opcode table that matches the one in
5409 IDESC, and frees the entry in IDESC. If no matching entry is
5410 found, NULL is returned instead. */
5412 static struct ia64_opcode
*
5413 get_next_opcode (struct ia64_opcode
*idesc
)
5415 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5416 ia64_free_opcode (idesc
);
5420 /* Parse the operands for the opcode and find the opcode variant that
5421 matches the specified operands, or NULL if no match is possible. */
5423 static struct ia64_opcode
*
5424 parse_operands (idesc
)
5425 struct ia64_opcode
*idesc
;
5427 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5428 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5429 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5430 enum operand_match_result result
;
5432 char *first_arg
= 0, *end
, *saved_input_pointer
;
5435 assert (strlen (idesc
->name
) <= 128);
5437 strcpy (mnemonic
, idesc
->name
);
5438 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5440 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5441 can't parse the first operand until we have parsed the
5442 remaining operands of the "alloc" instruction. */
5444 first_arg
= input_line_pointer
;
5445 end
= strchr (input_line_pointer
, '=');
5448 as_bad ("Expected separator `='");
5451 input_line_pointer
= end
+ 1;
5456 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5458 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5459 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5464 if (sep
!= '=' && sep
!= ',')
5469 if (num_outputs
> 0)
5470 as_bad ("Duplicate equal sign (=) in instruction");
5472 num_outputs
= i
+ 1;
5477 as_bad ("Illegal operand separator `%c'", sep
);
5481 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5483 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5484 know (strcmp (idesc
->name
, "alloc") == 0);
5485 if (num_operands
== 5 /* first_arg not included in this count! */
5486 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5487 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5488 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5489 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5491 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5492 CURR_SLOT
.opnd
[3].X_add_number
,
5493 CURR_SLOT
.opnd
[4].X_add_number
,
5494 CURR_SLOT
.opnd
[5].X_add_number
);
5496 /* now we can parse the first arg: */
5497 saved_input_pointer
= input_line_pointer
;
5498 input_line_pointer
= first_arg
;
5499 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5501 --num_outputs
; /* force error */
5502 input_line_pointer
= saved_input_pointer
;
5504 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5505 CURR_SLOT
.opnd
[3].X_add_number
5506 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5507 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5511 highest_unmatched_operand
= 0;
5512 curr_out_of_range_pos
= -1;
5514 expected_operand
= idesc
->operands
[0];
5515 for (; idesc
; idesc
= get_next_opcode (idesc
))
5517 if (num_outputs
!= idesc
->num_outputs
)
5518 continue; /* mismatch in # of outputs */
5520 CURR_SLOT
.num_fixups
= 0;
5522 /* Try to match all operands. If we see an out-of-range operand,
5523 then continue trying to match the rest of the operands, since if
5524 the rest match, then this idesc will give the best error message. */
5526 out_of_range_pos
= -1;
5527 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5529 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5530 if (result
!= OPERAND_MATCH
)
5532 if (result
!= OPERAND_OUT_OF_RANGE
)
5534 if (out_of_range_pos
< 0)
5535 /* remember position of the first out-of-range operand: */
5536 out_of_range_pos
= i
;
5540 /* If we did not match all operands, or if at least one operand was
5541 out-of-range, then this idesc does not match. Keep track of which
5542 idesc matched the most operands before failing. If we have two
5543 idescs that failed at the same position, and one had an out-of-range
5544 operand, then prefer the out-of-range operand. Thus if we have
5545 "add r0=0x1000000,r1" we get an error saying the constant is out
5546 of range instead of an error saying that the constant should have been
5549 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5551 if (i
> highest_unmatched_operand
5552 || (i
== highest_unmatched_operand
5553 && out_of_range_pos
> curr_out_of_range_pos
))
5555 highest_unmatched_operand
= i
;
5556 if (out_of_range_pos
>= 0)
5558 expected_operand
= idesc
->operands
[out_of_range_pos
];
5559 error_pos
= out_of_range_pos
;
5563 expected_operand
= idesc
->operands
[i
];
5566 curr_out_of_range_pos
= out_of_range_pos
;
5571 if (num_operands
< NELEMS (idesc
->operands
)
5572 && idesc
->operands
[num_operands
])
5573 continue; /* mismatch in number of arguments */
5579 if (expected_operand
)
5580 as_bad ("Operand %u of `%s' should be %s",
5581 error_pos
+ 1, mnemonic
,
5582 elf64_ia64_operands
[expected_operand
].desc
);
5584 as_bad ("Operand mismatch");
5590 /* Keep track of state necessary to determine whether a NOP is necessary
5591 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5592 detect a case where additional NOPs may be necessary. */
5594 errata_nop_necessary_p (slot
, insn_unit
)
5596 enum ia64_unit insn_unit
;
5599 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5600 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5601 struct ia64_opcode
*idesc
= slot
->idesc
;
5603 /* Test whether this could be the first insn in a problematic sequence. */
5604 if (insn_unit
== IA64_UNIT_F
)
5606 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5607 if (idesc
->operands
[i
] == IA64_OPND_P1
5608 || idesc
->operands
[i
] == IA64_OPND_P2
)
5610 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5611 /* Ignore invalid operands; they generate errors elsewhere. */
5614 this_group
->p_reg_set
[regno
] = 1;
5618 /* Test whether this could be the second insn in a problematic sequence. */
5619 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5620 && prev_group
->p_reg_set
[slot
->qp_regno
])
5622 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5623 if (idesc
->operands
[i
] == IA64_OPND_R1
5624 || idesc
->operands
[i
] == IA64_OPND_R2
5625 || idesc
->operands
[i
] == IA64_OPND_R3
)
5627 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5628 /* Ignore invalid operands; they generate errors elsewhere. */
5631 if (strncmp (idesc
->name
, "add", 3) != 0
5632 && strncmp (idesc
->name
, "sub", 3) != 0
5633 && strncmp (idesc
->name
, "shladd", 6) != 0
5634 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5635 this_group
->g_reg_set_conditionally
[regno
] = 1;
5639 /* Test whether this could be the third insn in a problematic sequence. */
5640 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5642 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5643 idesc
->operands
[i
] == IA64_OPND_R3
5644 /* For mov indirect. */
5645 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5646 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5647 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5648 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5649 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5650 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5651 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5652 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5654 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5655 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5656 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5657 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5659 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5660 /* Ignore invalid operands; they generate errors elsewhere. */
5663 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5665 if (strcmp (idesc
->name
, "fc") != 0
5666 && strcmp (idesc
->name
, "tak") != 0
5667 && strcmp (idesc
->name
, "thash") != 0
5668 && strcmp (idesc
->name
, "tpa") != 0
5669 && strcmp (idesc
->name
, "ttag") != 0
5670 && strncmp (idesc
->name
, "ptr", 3) != 0
5671 && strncmp (idesc
->name
, "ptc", 3) != 0
5672 && strncmp (idesc
->name
, "probe", 5) != 0)
5675 if (prev_group
->g_reg_set_conditionally
[regno
])
5683 build_insn (slot
, insnp
)
5687 const struct ia64_operand
*odesc
, *o2desc
;
5688 struct ia64_opcode
*idesc
= slot
->idesc
;
5689 bfd_signed_vma insn
, val
;
5693 insn
= idesc
->opcode
| slot
->qp_regno
;
5695 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5697 if (slot
->opnd
[i
].X_op
== O_register
5698 || slot
->opnd
[i
].X_op
== O_constant
5699 || slot
->opnd
[i
].X_op
== O_index
)
5700 val
= slot
->opnd
[i
].X_add_number
;
5701 else if (slot
->opnd
[i
].X_op
== O_big
)
5703 /* This must be the value 0x10000000000000000. */
5704 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5710 switch (idesc
->operands
[i
])
5712 case IA64_OPND_IMMU64
:
5713 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5714 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5715 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5716 | (((val
>> 63) & 0x1) << 36));
5719 case IA64_OPND_IMMU62
:
5720 val
&= 0x3fffffffffffffffULL
;
5721 if (val
!= slot
->opnd
[i
].X_add_number
)
5722 as_warn (_("Value truncated to 62 bits"));
5723 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5724 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5727 case IA64_OPND_TGT64
:
5729 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5730 insn
|= ((((val
>> 59) & 0x1) << 36)
5731 | (((val
>> 0) & 0xfffff) << 13));
5762 case IA64_OPND_R3_2
:
5763 case IA64_OPND_CPUID_R3
:
5764 case IA64_OPND_DBR_R3
:
5765 case IA64_OPND_DTR_R3
:
5766 case IA64_OPND_ITR_R3
:
5767 case IA64_OPND_IBR_R3
:
5769 case IA64_OPND_MSR_R3
:
5770 case IA64_OPND_PKR_R3
:
5771 case IA64_OPND_PMC_R3
:
5772 case IA64_OPND_PMD_R3
:
5773 case IA64_OPND_RR_R3
:
5781 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5782 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5784 as_bad_where (slot
->src_file
, slot
->src_line
,
5785 "Bad operand value: %s", err
);
5786 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5788 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5789 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5791 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5792 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5794 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5795 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5796 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5798 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5799 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5809 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5810 unsigned int manual_bundling
= 0;
5811 enum ia64_unit required_unit
, insn_unit
= 0;
5812 enum ia64_insn_type type
[3], insn_type
;
5813 unsigned int template, orig_template
;
5814 bfd_vma insn
[3] = { -1, -1, -1 };
5815 struct ia64_opcode
*idesc
;
5816 int end_of_insn_group
= 0, user_template
= -1;
5817 int n
, i
, j
, first
, curr
;
5819 bfd_vma t0
= 0, t1
= 0;
5820 struct label_fix
*lfix
;
5821 struct insn_fix
*ifix
;
5826 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5827 know (first
>= 0 & first
< NUM_SLOTS
);
5828 n
= MIN (3, md
.num_slots_in_use
);
5830 /* Determine template: user user_template if specified, best match
5833 if (md
.slot
[first
].user_template
>= 0)
5834 user_template
= template = md
.slot
[first
].user_template
;
5837 /* Auto select appropriate template. */
5838 memset (type
, 0, sizeof (type
));
5840 for (i
= 0; i
< n
; ++i
)
5842 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5844 type
[i
] = md
.slot
[curr
].idesc
->type
;
5845 curr
= (curr
+ 1) % NUM_SLOTS
;
5847 template = best_template
[type
[0]][type
[1]][type
[2]];
5850 /* initialize instructions with appropriate nops: */
5851 for (i
= 0; i
< 3; ++i
)
5852 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5856 /* now fill in slots with as many insns as possible: */
5858 idesc
= md
.slot
[curr
].idesc
;
5859 end_of_insn_group
= 0;
5860 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5862 /* Set the slot number for prologue/body records now as those
5863 refer to the current point, not the point after the
5864 instruction has been issued: */
5865 /* Don't try to delete prologue/body records here, as that will cause
5866 them to also be deleted from the master list of unwind records. */
5867 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5868 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5869 || ptr
->r
.type
== body
)
5871 ptr
->slot_number
= (unsigned long) f
+ i
;
5872 ptr
->slot_frag
= frag_now
;
5875 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5877 if (manual_bundling
&& i
!= 2)
5878 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5879 "`%s' must be last in bundle", idesc
->name
);
5883 if (idesc
->flags
& IA64_OPCODE_LAST
)
5886 unsigned int required_template
;
5888 /* If we need a stop bit after an M slot, our only choice is
5889 template 5 (M;;MI). If we need a stop bit after a B
5890 slot, our only choice is to place it at the end of the
5891 bundle, because the only available templates are MIB,
5892 MBB, BBB, MMB, and MFB. We don't handle anything other
5893 than M and B slots because these are the only kind of
5894 instructions that can have the IA64_OPCODE_LAST bit set. */
5895 required_template
= template;
5896 switch (idesc
->type
)
5900 required_template
= 5;
5908 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5909 "Internal error: don't know how to force %s to end"
5910 "of instruction group", idesc
->name
);
5914 if (manual_bundling
&& i
!= required_slot
)
5915 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5916 "`%s' must be last in instruction group",
5918 if (required_slot
< i
)
5919 /* Can't fit this instruction. */
5923 if (required_template
!= template)
5925 /* If we switch the template, we need to reset the NOPs
5926 after slot i. The slot-types of the instructions ahead
5927 of i never change, so we don't need to worry about
5928 changing NOPs in front of this slot. */
5929 for (j
= i
; j
< 3; ++j
)
5930 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5932 template = required_template
;
5934 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5936 if (manual_bundling_on
)
5937 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5938 "Label must be first in a bundle");
5939 /* This insn must go into the first slot of a bundle. */
5943 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5944 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5946 if (manual_bundling_on
)
5949 manual_bundling
= 1;
5951 break; /* need to start a new bundle */
5954 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5956 /* We need an instruction group boundary in the middle of a
5957 bundle. See if we can switch to an other template with
5958 an appropriate boundary. */
5960 orig_template
= template;
5961 if (i
== 1 && (user_template
== 4
5962 || (user_template
< 0
5963 && (ia64_templ_desc
[template].exec_unit
[0]
5967 end_of_insn_group
= 0;
5969 else if (i
== 2 && (user_template
== 0
5970 || (user_template
< 0
5971 && (ia64_templ_desc
[template].exec_unit
[1]
5973 /* This test makes sure we don't switch the template if
5974 the next instruction is one that needs to be first in
5975 an instruction group. Since all those instructions are
5976 in the M group, there is no way such an instruction can
5977 fit in this bundle even if we switch the template. The
5978 reason we have to check for this is that otherwise we
5979 may end up generating "MI;;I M.." which has the deadly
5980 effect that the second M instruction is no longer the
5981 first in the bundle! --davidm 99/12/16 */
5982 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5985 end_of_insn_group
= 0;
5987 else if (curr
!= first
)
5988 /* can't fit this insn */
5991 if (template != orig_template
)
5992 /* if we switch the template, we need to reset the NOPs
5993 after slot i. The slot-types of the instructions ahead
5994 of i never change, so we don't need to worry about
5995 changing NOPs in front of this slot. */
5996 for (j
= i
; j
< 3; ++j
)
5997 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5999 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6001 /* resolve dynamic opcodes such as "break" and "nop": */
6002 if (idesc
->type
== IA64_TYPE_DYN
)
6004 if ((strcmp (idesc
->name
, "nop") == 0)
6005 || (strcmp (idesc
->name
, "break") == 0))
6006 insn_unit
= required_unit
;
6007 else if (strcmp (idesc
->name
, "chk.s") == 0)
6009 insn_unit
= IA64_UNIT_M
;
6010 if (required_unit
== IA64_UNIT_I
)
6011 insn_unit
= IA64_UNIT_I
;
6014 as_fatal ("emit_one_bundle: unexpected dynamic op");
6016 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6017 ia64_free_opcode (idesc
);
6018 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6020 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6025 insn_type
= idesc
->type
;
6026 insn_unit
= IA64_UNIT_NIL
;
6030 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6031 insn_unit
= required_unit
;
6033 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6034 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6035 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6036 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6037 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6042 if (insn_unit
!= required_unit
)
6044 if (required_unit
== IA64_UNIT_L
6045 && insn_unit
== IA64_UNIT_I
6046 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6048 /* we got ourselves an MLX template but the current
6049 instruction isn't an X-unit, or an I-unit instruction
6050 that can go into the X slot of an MLX template. Duh. */
6051 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6053 as_bad_where (md
.slot
[curr
].src_file
,
6054 md
.slot
[curr
].src_line
,
6055 "`%s' can't go in X slot of "
6056 "MLX template", idesc
->name
);
6057 /* drop this insn so we don't livelock: */
6058 --md
.num_slots_in_use
;
6062 continue; /* try next slot */
6068 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6069 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6072 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6073 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6075 build_insn (md
.slot
+ curr
, insn
+ i
);
6077 /* Set slot counts for non prologue/body unwind records. */
6078 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6079 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6080 && ptr
->r
.type
!= body
)
6082 ptr
->slot_number
= (unsigned long) f
+ i
;
6083 ptr
->slot_frag
= frag_now
;
6085 md
.slot
[curr
].unwind_record
= NULL
;
6087 if (required_unit
== IA64_UNIT_L
)
6090 /* skip one slot for long/X-unit instructions */
6093 --md
.num_slots_in_use
;
6095 /* now is a good time to fix up the labels for this insn: */
6096 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6098 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6099 symbol_set_frag (lfix
->sym
, frag_now
);
6101 /* and fix up the tags also. */
6102 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6104 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6105 symbol_set_frag (lfix
->sym
, frag_now
);
6108 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6110 ifix
= md
.slot
[curr
].fixup
+ j
;
6111 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6112 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6113 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6114 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6115 fix
->fx_file
= md
.slot
[curr
].src_file
;
6116 fix
->fx_line
= md
.slot
[curr
].src_line
;
6119 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6121 if (end_of_insn_group
)
6123 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6124 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6128 ia64_free_opcode (md
.slot
[curr
].idesc
);
6129 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6130 md
.slot
[curr
].user_template
= -1;
6132 if (manual_bundling_off
)
6134 manual_bundling
= 0;
6137 curr
= (curr
+ 1) % NUM_SLOTS
;
6138 idesc
= md
.slot
[curr
].idesc
;
6140 if (manual_bundling
)
6142 if (md
.num_slots_in_use
> 0)
6143 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6144 "`%s' does not fit into %s template",
6145 idesc
->name
, ia64_templ_desc
[template].name
);
6147 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6148 "Missing '}' at end of file");
6150 know (md
.num_slots_in_use
< NUM_SLOTS
);
6152 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6153 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6155 number_to_chars_littleendian (f
+ 0, t0
, 8);
6156 number_to_chars_littleendian (f
+ 8, t1
, 8);
6158 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6159 unwind
.next_slot_frag
= frag_now
;
6163 md_parse_option (c
, arg
)
6170 /* Switches from the Intel assembler. */
6172 if (strcmp (arg
, "ilp64") == 0
6173 || strcmp (arg
, "lp64") == 0
6174 || strcmp (arg
, "p64") == 0)
6176 md
.flags
|= EF_IA_64_ABI64
;
6178 else if (strcmp (arg
, "ilp32") == 0)
6180 md
.flags
&= ~EF_IA_64_ABI64
;
6182 else if (strcmp (arg
, "le") == 0)
6184 md
.flags
&= ~EF_IA_64_BE
;
6186 else if (strcmp (arg
, "be") == 0)
6188 md
.flags
|= EF_IA_64_BE
;
6195 if (strcmp (arg
, "so") == 0)
6197 /* Suppress signon message. */
6199 else if (strcmp (arg
, "pi") == 0)
6201 /* Reject privileged instructions. FIXME */
6203 else if (strcmp (arg
, "us") == 0)
6205 /* Allow union of signed and unsigned range. FIXME */
6207 else if (strcmp (arg
, "close_fcalls") == 0)
6209 /* Do not resolve global function calls. */
6216 /* temp[="prefix"] Insert temporary labels into the object file
6217 symbol table prefixed by "prefix".
6218 Default prefix is ":temp:".
6223 /* indirect=<tgt> Assume unannotated indirect branches behavior
6224 according to <tgt> --
6225 exit: branch out from the current context (default)
6226 labels: all labels in context may be branch targets
6228 if (strncmp (arg
, "indirect=", 9) != 0)
6233 /* -X conflicts with an ignored option, use -x instead */
6235 if (!arg
|| strcmp (arg
, "explicit") == 0)
6237 /* set default mode to explicit */
6238 md
.default_explicit_mode
= 1;
6241 else if (strcmp (arg
, "auto") == 0)
6243 md
.default_explicit_mode
= 0;
6245 else if (strcmp (arg
, "debug") == 0)
6249 else if (strcmp (arg
, "debugx") == 0)
6251 md
.default_explicit_mode
= 1;
6256 as_bad (_("Unrecognized option '-x%s'"), arg
);
6261 /* nops Print nops statistics. */
6264 /* GNU specific switches for gcc. */
6265 case OPTION_MCONSTANT_GP
:
6266 md
.flags
|= EF_IA_64_CONS_GP
;
6269 case OPTION_MAUTO_PIC
:
6270 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6281 md_show_usage (stream
)
6286 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6287 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6288 -x | -xexplicit turn on dependency violation checking (default)\n\
6289 -xauto automagically remove dependency violations\n\
6290 -xdebug debug dependency violation checker\n"),
6294 /* Return true if TYPE fits in TEMPL at SLOT. */
6297 match (int templ
, int type
, int slot
)
6299 enum ia64_unit unit
;
6302 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6305 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6307 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6309 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6310 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6311 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6312 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6313 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6314 default: result
= 0; break;
6319 /* Add a bit of extra goodness if a nop of type F or B would fit
6320 in TEMPL at SLOT. */
6323 extra_goodness (int templ
, int slot
)
6325 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6327 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6332 /* This function is called once, at assembler startup time. It sets
6333 up all the tables, etc. that the MD part of the assembler will need
6334 that can be determined before arguments are parsed. */
6338 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6343 md
.explicit_mode
= md
.default_explicit_mode
;
6345 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6347 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6348 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6349 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6350 &zero_address_frag
);
6352 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6353 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6354 &zero_address_frag
);
6356 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6357 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6358 &zero_address_frag
);
6360 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6361 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6362 &zero_address_frag
);
6364 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6365 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6366 &zero_address_frag
);
6368 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6369 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6370 &zero_address_frag
);
6372 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6373 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6374 &zero_address_frag
);
6376 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6377 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6378 &zero_address_frag
);
6380 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6381 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6382 &zero_address_frag
);
6384 /* Compute the table of best templates. We compute goodness as a
6385 base 4 value, in which each match counts for 3, each F counts
6386 for 2, each B counts for 1. This should maximize the number of
6387 F and B nops in the chosen bundles, which is good because these
6388 pipelines are least likely to be overcommitted. */
6389 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6390 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6391 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6394 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6397 if (match (t
, i
, 0))
6399 if (match (t
, j
, 1))
6401 if (match (t
, k
, 2))
6402 goodness
= 3 + 3 + 3;
6404 goodness
= 3 + 3 + extra_goodness (t
, 2);
6406 else if (match (t
, j
, 2))
6407 goodness
= 3 + 3 + extra_goodness (t
, 1);
6411 goodness
+= extra_goodness (t
, 1);
6412 goodness
+= extra_goodness (t
, 2);
6415 else if (match (t
, i
, 1))
6417 if (match (t
, j
, 2))
6420 goodness
= 3 + extra_goodness (t
, 2);
6422 else if (match (t
, i
, 2))
6423 goodness
= 3 + extra_goodness (t
, 1);
6425 if (goodness
> best
)
6428 best_template
[i
][j
][k
] = t
;
6433 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6434 md
.slot
[i
].user_template
= -1;
6436 md
.pseudo_hash
= hash_new ();
6437 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6439 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6440 (void *) (pseudo_opcode
+ i
));
6442 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6443 pseudo_opcode
[i
].name
, err
);
6446 md
.reg_hash
= hash_new ();
6447 md
.dynreg_hash
= hash_new ();
6448 md
.const_hash
= hash_new ();
6449 md
.entry_hash
= hash_new ();
6451 /* general registers: */
6454 for (i
= 0; i
< total
; ++i
)
6456 sprintf (name
, "r%d", i
- REG_GR
);
6457 md
.regsym
[i
] = declare_register (name
, i
);
6460 /* floating point registers: */
6462 for (; i
< total
; ++i
)
6464 sprintf (name
, "f%d", i
- REG_FR
);
6465 md
.regsym
[i
] = declare_register (name
, i
);
6468 /* application registers: */
6471 for (; i
< total
; ++i
)
6473 sprintf (name
, "ar%d", i
- REG_AR
);
6474 md
.regsym
[i
] = declare_register (name
, i
);
6477 /* control registers: */
6480 for (; i
< total
; ++i
)
6482 sprintf (name
, "cr%d", i
- REG_CR
);
6483 md
.regsym
[i
] = declare_register (name
, i
);
6486 /* predicate registers: */
6488 for (; i
< total
; ++i
)
6490 sprintf (name
, "p%d", i
- REG_P
);
6491 md
.regsym
[i
] = declare_register (name
, i
);
6494 /* branch registers: */
6496 for (; i
< total
; ++i
)
6498 sprintf (name
, "b%d", i
- REG_BR
);
6499 md
.regsym
[i
] = declare_register (name
, i
);
6502 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6503 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6504 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6505 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6506 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6507 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6508 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6510 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6512 regnum
= indirect_reg
[i
].regnum
;
6513 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6516 /* define synonyms for application registers: */
6517 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6518 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6519 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6521 /* define synonyms for control registers: */
6522 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6523 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6524 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6526 declare_register ("gp", REG_GR
+ 1);
6527 declare_register ("sp", REG_GR
+ 12);
6528 declare_register ("rp", REG_BR
+ 0);
6530 /* pseudo-registers used to specify unwind info: */
6531 declare_register ("psp", REG_PSP
);
6533 declare_register_set ("ret", 4, REG_GR
+ 8);
6534 declare_register_set ("farg", 8, REG_FR
+ 8);
6535 declare_register_set ("fret", 8, REG_FR
+ 8);
6537 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6539 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6540 (PTR
) (const_bits
+ i
));
6542 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6546 /* Set the architecture and machine depending on defaults and command line
6548 if (md
.flags
& EF_IA_64_ABI64
)
6549 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6551 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6554 as_warn (_("Could not set architecture and machine"));
6556 /* Set the pointer size and pointer shift size depending on md.flags */
6558 if (md
.flags
& EF_IA_64_ABI64
)
6560 md
.pointer_size
= 8; /* pointers are 8 bytes */
6561 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6565 md
.pointer_size
= 4; /* pointers are 4 bytes */
6566 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6569 md
.mem_offset
.hint
= 0;
6572 md
.entry_labels
= NULL
;
6575 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6576 because that is called after md_parse_option which is where we do the
6577 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6578 default endianness. */
6581 ia64_init (argc
, argv
)
6582 int argc ATTRIBUTE_UNUSED
;
6583 char **argv ATTRIBUTE_UNUSED
;
6585 md
.flags
= EF_IA_64_ABI64
;
6586 if (TARGET_BYTES_BIG_ENDIAN
)
6587 md
.flags
|= EF_IA_64_BE
;
6590 /* Return a string for the target object file format. */
6593 ia64_target_format ()
6595 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6597 if (md
.flags
& EF_IA_64_BE
)
6599 if (md
.flags
& EF_IA_64_ABI64
)
6601 return "elf64-ia64-aix-big";
6603 return "elf64-ia64-big";
6607 return "elf32-ia64-aix-big";
6609 return "elf32-ia64-big";
6614 if (md
.flags
& EF_IA_64_ABI64
)
6616 return "elf64-ia64-aix-little";
6618 return "elf64-ia64-little";
6622 return "elf32-ia64-aix-little";
6624 return "elf32-ia64-little";
6629 return "unknown-format";
6633 ia64_end_of_source ()
6635 /* terminate insn group upon reaching end of file: */
6636 insn_group_break (1, 0, 0);
6638 /* emits slots we haven't written yet: */
6639 ia64_flush_insns ();
6641 bfd_set_private_flags (stdoutput
, md
.flags
);
6643 md
.mem_offset
.hint
= 0;
6649 if (md
.qp
.X_op
== O_register
)
6650 as_bad ("qualifying predicate not followed by instruction");
6651 md
.qp
.X_op
= O_absent
;
6653 if (ignore_input ())
6656 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6658 if (md
.detect_dv
&& !md
.explicit_mode
)
6659 as_warn (_("Explicit stops are ignored in auto mode"));
6661 insn_group_break (1, 0, 0);
6665 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6667 static int defining_tag
= 0;
6670 ia64_unrecognized_line (ch
)
6676 expression (&md
.qp
);
6677 if (*input_line_pointer
++ != ')')
6679 as_bad ("Expected ')'");
6682 if (md
.qp
.X_op
!= O_register
)
6684 as_bad ("Qualifying predicate expected");
6687 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6689 as_bad ("Predicate register expected");
6695 if (md
.manual_bundling
)
6696 as_warn ("Found '{' when manual bundling is already turned on");
6698 CURR_SLOT
.manual_bundling_on
= 1;
6699 md
.manual_bundling
= 1;
6701 /* Bundling is only acceptable in explicit mode
6702 or when in default automatic mode. */
6703 if (md
.detect_dv
&& !md
.explicit_mode
)
6705 if (!md
.mode_explicitly_set
6706 && !md
.default_explicit_mode
)
6709 as_warn (_("Found '{' after explicit switch to automatic mode"));
6714 if (!md
.manual_bundling
)
6715 as_warn ("Found '}' when manual bundling is off");
6717 PREV_SLOT
.manual_bundling_off
= 1;
6718 md
.manual_bundling
= 0;
6720 /* switch back to automatic mode, if applicable */
6723 && !md
.mode_explicitly_set
6724 && !md
.default_explicit_mode
)
6727 /* Allow '{' to follow on the same line. We also allow ";;", but that
6728 happens automatically because ';' is an end of line marker. */
6730 if (input_line_pointer
[0] == '{')
6732 input_line_pointer
++;
6733 return ia64_unrecognized_line ('{');
6736 demand_empty_rest_of_line ();
6746 if (md
.qp
.X_op
== O_register
)
6748 as_bad ("Tag must come before qualifying predicate.");
6752 /* This implements just enough of read_a_source_file in read.c to
6753 recognize labels. */
6754 if (is_name_beginner (*input_line_pointer
))
6756 s
= input_line_pointer
;
6757 c
= get_symbol_end ();
6759 else if (LOCAL_LABELS_FB
6760 && isdigit ((unsigned char) *input_line_pointer
))
6763 while (isdigit ((unsigned char) *input_line_pointer
))
6764 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6765 fb_label_instance_inc (temp
);
6766 s
= fb_label_name (temp
, 0);
6767 c
= *input_line_pointer
;
6776 /* Put ':' back for error messages' sake. */
6777 *input_line_pointer
++ = ':';
6778 as_bad ("Expected ':'");
6785 /* Put ':' back for error messages' sake. */
6786 *input_line_pointer
++ = ':';
6787 if (*input_line_pointer
++ != ']')
6789 as_bad ("Expected ']'");
6794 as_bad ("Tag name expected");
6804 /* Not a valid line. */
6809 ia64_frob_label (sym
)
6812 struct label_fix
*fix
;
6814 /* Tags need special handling since they are not bundle breaks like
6818 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6820 fix
->next
= CURR_SLOT
.tag_fixups
;
6821 CURR_SLOT
.tag_fixups
= fix
;
6826 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6828 md
.last_text_seg
= now_seg
;
6829 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6831 fix
->next
= CURR_SLOT
.label_fixups
;
6832 CURR_SLOT
.label_fixups
= fix
;
6834 /* Keep track of how many code entry points we've seen. */
6835 if (md
.path
== md
.maxpaths
)
6838 md
.entry_labels
= (const char **)
6839 xrealloc ((void *) md
.entry_labels
,
6840 md
.maxpaths
* sizeof (char *));
6842 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6847 ia64_flush_pending_output ()
6849 if (!md
.keep_pending_output
6850 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6852 /* ??? This causes many unnecessary stop bits to be emitted.
6853 Unfortunately, it isn't clear if it is safe to remove this. */
6854 insn_group_break (1, 0, 0);
6855 ia64_flush_insns ();
6859 /* Do ia64-specific expression optimization. All that's done here is
6860 to transform index expressions that are either due to the indexing
6861 of rotating registers or due to the indexing of indirect register
6864 ia64_optimize_expr (l
, op
, r
)
6873 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6875 num_regs
= (l
->X_add_number
>> 16);
6876 if ((unsigned) r
->X_add_number
>= num_regs
)
6879 as_bad ("No current frame");
6881 as_bad ("Index out of range 0..%u", num_regs
- 1);
6882 r
->X_add_number
= 0;
6884 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6887 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6889 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6890 || l
->X_add_number
== IND_MEM
)
6892 as_bad ("Indirect register set name expected");
6893 l
->X_add_number
= IND_CPUID
;
6896 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6897 l
->X_add_number
= r
->X_add_number
;
6905 ia64_parse_name (name
, e
)
6909 struct const_desc
*cdesc
;
6910 struct dynreg
*dr
= 0;
6911 unsigned int regnum
;
6915 /* first see if NAME is a known register name: */
6916 sym
= hash_find (md
.reg_hash
, name
);
6919 e
->X_op
= O_register
;
6920 e
->X_add_number
= S_GET_VALUE (sym
);
6924 cdesc
= hash_find (md
.const_hash
, name
);
6927 e
->X_op
= O_constant
;
6928 e
->X_add_number
= cdesc
->value
;
6932 /* check for inN, locN, or outN: */
6936 if (name
[1] == 'n' && isdigit (name
[2]))
6944 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6952 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6965 /* The name is inN, locN, or outN; parse the register number. */
6966 regnum
= strtoul (name
, &end
, 10);
6967 if (end
> name
&& *end
== '\0')
6969 if ((unsigned) regnum
>= dr
->num_regs
)
6972 as_bad ("No current frame");
6974 as_bad ("Register number out of range 0..%u",
6978 e
->X_op
= O_register
;
6979 e
->X_add_number
= dr
->base
+ regnum
;
6984 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6986 /* We've got ourselves the name of a rotating register set.
6987 Store the base register number in the low 16 bits of
6988 X_add_number and the size of the register set in the top 16
6990 e
->X_op
= O_register
;
6991 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6997 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7000 ia64_canonicalize_symbol_name (name
)
7003 size_t len
= strlen (name
);
7004 if (len
> 1 && name
[len
- 1] == '#')
7005 name
[len
- 1] = '\0';
7009 /* Return true if idesc is a conditional branch instruction. This excludes
7010 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7011 because they always read/write resources regardless of the value of the
7012 qualifying predicate. br.ia must always use p0, and hence is always
7013 taken. Thus this function returns true for branches which can fall
7014 through, and which use no resources if they do fall through. */
7017 is_conditional_branch (idesc
)
7018 struct ia64_opcode
*idesc
;
7020 /* br is a conditional branch. Everything that starts with br. except
7021 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7022 Everything that starts with brl is a conditional branch. */
7023 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7024 && (idesc
->name
[2] == '\0'
7025 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7026 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7027 || idesc
->name
[2] == 'l'
7028 /* br.cond, br.call, br.clr */
7029 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7030 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7031 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7034 /* Return whether the given opcode is a taken branch. If there's any doubt,
7038 is_taken_branch (idesc
)
7039 struct ia64_opcode
*idesc
;
7041 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7042 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7045 /* Return whether the given opcode is an interruption or rfi. If there's any
7046 doubt, returns zero. */
7049 is_interruption_or_rfi (idesc
)
7050 struct ia64_opcode
*idesc
;
7052 if (strcmp (idesc
->name
, "rfi") == 0)
7057 /* Returns the index of the given dependency in the opcode's list of chks, or
7058 -1 if there is no dependency. */
7061 depends_on (depind
, idesc
)
7063 struct ia64_opcode
*idesc
;
7066 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7067 for (i
= 0; i
< dep
->nchks
; i
++)
7069 if (depind
== DEP (dep
->chks
[i
]))
7075 /* Determine a set of specific resources used for a particular resource
7076 class. Returns the number of specific resources identified For those
7077 cases which are not determinable statically, the resource returned is
7080 Meanings of value in 'NOTE':
7081 1) only read/write when the register number is explicitly encoded in the
7083 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7084 accesses CFM when qualifying predicate is in the rotating region.
7085 3) general register value is used to specify an indirect register; not
7086 determinable statically.
7087 4) only read the given resource when bits 7:0 of the indirect index
7088 register value does not match the register number of the resource; not
7089 determinable statically.
7090 5) all rules are implementation specific.
7091 6) only when both the index specified by the reader and the index specified
7092 by the writer have the same value in bits 63:61; not determinable
7094 7) only access the specified resource when the corresponding mask bit is
7096 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7097 only read when these insns reference FR2-31
7098 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7099 written when these insns write FR32-127
7100 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7102 11) The target predicates are written independently of PR[qp], but source
7103 registers are only read if PR[qp] is true. Since the state of PR[qp]
7104 cannot statically be determined, all source registers are marked used.
7105 12) This insn only reads the specified predicate register when that
7106 register is the PR[qp].
7107 13) This reference to ld-c only applies to teh GR whose value is loaded
7108 with data returned from memory, not the post-incremented address register.
7109 14) The RSE resource includes the implementation-specific RSE internal
7110 state resources. At least one (and possibly more) of these resources are
7111 read by each instruction listed in IC:rse-readers. At least one (and
7112 possibly more) of these resources are written by each insn listed in
7114 15+16) Represents reserved instructions, which the assembler does not
7117 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7118 this code; there are no dependency violations based on memory access.
7121 #define MAX_SPECS 256
7126 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7127 const struct ia64_dependency
*dep
;
7128 struct ia64_opcode
*idesc
;
7129 int type
; /* is this a DV chk or a DV reg? */
7130 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7131 int note
; /* resource note for this insn's usage */
7132 int path
; /* which execution path to examine */
7139 if (dep
->mode
== IA64_DV_WAW
7140 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7141 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7144 /* template for any resources we identify */
7145 tmpl
.dependency
= dep
;
7147 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7148 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7149 tmpl
.link_to_qp_branch
= 1;
7150 tmpl
.mem_offset
.hint
= 0;
7153 tmpl
.cmp_type
= CMP_NONE
;
7156 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7157 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7158 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7160 /* we don't need to track these */
7161 if (dep
->semantics
== IA64_DVS_NONE
)
7164 switch (dep
->specifier
)
7169 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7171 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7172 if (regno
>= 0 && regno
<= 7)
7174 specs
[count
] = tmpl
;
7175 specs
[count
++].index
= regno
;
7181 for (i
= 0; i
< 8; i
++)
7183 specs
[count
] = tmpl
;
7184 specs
[count
++].index
= i
;
7193 case IA64_RS_AR_UNAT
:
7194 /* This is a mov =AR or mov AR= instruction. */
7195 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7197 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7198 if (regno
== AR_UNAT
)
7200 specs
[count
++] = tmpl
;
7205 /* This is a spill/fill, or other instruction that modifies the
7208 /* Unless we can determine the specific bits used, mark the whole
7209 thing; bits 8:3 of the memory address indicate the bit used in
7210 UNAT. The .mem.offset hint may be used to eliminate a small
7211 subset of conflicts. */
7212 specs
[count
] = tmpl
;
7213 if (md
.mem_offset
.hint
)
7216 fprintf (stderr
, " Using hint for spill/fill\n");
7217 /* The index isn't actually used, just set it to something
7218 approximating the bit index. */
7219 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7220 specs
[count
].mem_offset
.hint
= 1;
7221 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7222 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7226 specs
[count
++].specific
= 0;
7234 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7236 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7237 if ((regno
>= 8 && regno
<= 15)
7238 || (regno
>= 20 && regno
<= 23)
7239 || (regno
>= 31 && regno
<= 39)
7240 || (regno
>= 41 && regno
<= 47)
7241 || (regno
>= 67 && regno
<= 111))
7243 specs
[count
] = tmpl
;
7244 specs
[count
++].index
= regno
;
7257 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7259 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7260 if ((regno
>= 48 && regno
<= 63)
7261 || (regno
>= 112 && regno
<= 127))
7263 specs
[count
] = tmpl
;
7264 specs
[count
++].index
= regno
;
7270 for (i
= 48; i
< 64; i
++)
7272 specs
[count
] = tmpl
;
7273 specs
[count
++].index
= i
;
7275 for (i
= 112; i
< 128; i
++)
7277 specs
[count
] = tmpl
;
7278 specs
[count
++].index
= i
;
7296 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7297 if (idesc
->operands
[i
] == IA64_OPND_B1
7298 || idesc
->operands
[i
] == IA64_OPND_B2
)
7300 specs
[count
] = tmpl
;
7301 specs
[count
++].index
=
7302 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7307 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7308 if (idesc
->operands
[i
] == IA64_OPND_B1
7309 || idesc
->operands
[i
] == IA64_OPND_B2
)
7311 specs
[count
] = tmpl
;
7312 specs
[count
++].index
=
7313 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7319 case IA64_RS_CPUID
: /* four or more registers */
7322 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7324 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7325 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7328 specs
[count
] = tmpl
;
7329 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7333 specs
[count
] = tmpl
;
7334 specs
[count
++].specific
= 0;
7344 case IA64_RS_DBR
: /* four or more registers */
7347 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7349 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7350 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7353 specs
[count
] = tmpl
;
7354 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7358 specs
[count
] = tmpl
;
7359 specs
[count
++].specific
= 0;
7363 else if (note
== 0 && !rsrc_write
)
7365 specs
[count
] = tmpl
;
7366 specs
[count
++].specific
= 0;
7374 case IA64_RS_IBR
: /* four or more registers */
7377 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7379 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7380 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7383 specs
[count
] = tmpl
;
7384 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7388 specs
[count
] = tmpl
;
7389 specs
[count
++].specific
= 0;
7402 /* These are implementation specific. Force all references to
7403 conflict with all other references. */
7404 specs
[count
] = tmpl
;
7405 specs
[count
++].specific
= 0;
7413 case IA64_RS_PKR
: /* 16 or more registers */
7414 if (note
== 3 || note
== 4)
7416 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7418 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7419 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7424 specs
[count
] = tmpl
;
7425 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7428 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7430 /* Uses all registers *except* the one in R3. */
7431 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7433 specs
[count
] = tmpl
;
7434 specs
[count
++].index
= i
;
7440 specs
[count
] = tmpl
;
7441 specs
[count
++].specific
= 0;
7448 specs
[count
] = tmpl
;
7449 specs
[count
++].specific
= 0;
7453 case IA64_RS_PMC
: /* four or more registers */
7456 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7457 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7460 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7462 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7463 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7466 specs
[count
] = tmpl
;
7467 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7471 specs
[count
] = tmpl
;
7472 specs
[count
++].specific
= 0;
7482 case IA64_RS_PMD
: /* four or more registers */
7485 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7487 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7488 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7491 specs
[count
] = tmpl
;
7492 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7496 specs
[count
] = tmpl
;
7497 specs
[count
++].specific
= 0;
7507 case IA64_RS_RR
: /* eight registers */
7510 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7512 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7513 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7516 specs
[count
] = tmpl
;
7517 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7521 specs
[count
] = tmpl
;
7522 specs
[count
++].specific
= 0;
7526 else if (note
== 0 && !rsrc_write
)
7528 specs
[count
] = tmpl
;
7529 specs
[count
++].specific
= 0;
7537 case IA64_RS_CR_IRR
:
7540 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7541 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7543 && idesc
->operands
[1] == IA64_OPND_CR3
7546 for (i
= 0; i
< 4; i
++)
7548 specs
[count
] = tmpl
;
7549 specs
[count
++].index
= CR_IRR0
+ i
;
7555 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7556 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7558 && regno
<= CR_IRR3
)
7560 specs
[count
] = tmpl
;
7561 specs
[count
++].index
= regno
;
7570 case IA64_RS_CR_LRR
:
7577 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7578 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7579 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7581 specs
[count
] = tmpl
;
7582 specs
[count
++].index
= regno
;
7590 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7592 specs
[count
] = tmpl
;
7593 specs
[count
++].index
=
7594 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7609 else if (rsrc_write
)
7611 if (dep
->specifier
== IA64_RS_FRb
7612 && idesc
->operands
[0] == IA64_OPND_F1
)
7614 specs
[count
] = tmpl
;
7615 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7620 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7622 if (idesc
->operands
[i
] == IA64_OPND_F2
7623 || idesc
->operands
[i
] == IA64_OPND_F3
7624 || idesc
->operands
[i
] == IA64_OPND_F4
)
7626 specs
[count
] = tmpl
;
7627 specs
[count
++].index
=
7628 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7637 /* This reference applies only to the GR whose value is loaded with
7638 data returned from memory. */
7639 specs
[count
] = tmpl
;
7640 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7646 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7647 if (idesc
->operands
[i
] == IA64_OPND_R1
7648 || idesc
->operands
[i
] == IA64_OPND_R2
7649 || idesc
->operands
[i
] == IA64_OPND_R3
)
7651 specs
[count
] = tmpl
;
7652 specs
[count
++].index
=
7653 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7655 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7656 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7657 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7659 specs
[count
] = tmpl
;
7660 specs
[count
++].index
=
7661 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7666 /* Look for anything that reads a GR. */
7667 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7669 if (idesc
->operands
[i
] == IA64_OPND_MR3
7670 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7671 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7672 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7673 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7674 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7675 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7676 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7677 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7678 || ((i
>= idesc
->num_outputs
)
7679 && (idesc
->operands
[i
] == IA64_OPND_R1
7680 || idesc
->operands
[i
] == IA64_OPND_R2
7681 || idesc
->operands
[i
] == IA64_OPND_R3
7682 /* addl source register. */
7683 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7685 specs
[count
] = tmpl
;
7686 specs
[count
++].index
=
7687 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7698 /* This is the same as IA64_RS_PRr, except that the register range is
7699 from 1 - 15, and there are no rotating register reads/writes here. */
7703 for (i
= 1; i
< 16; i
++)
7705 specs
[count
] = tmpl
;
7706 specs
[count
++].index
= i
;
7712 /* Mark only those registers indicated by the mask. */
7715 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7716 for (i
= 1; i
< 16; i
++)
7717 if (mask
& ((valueT
) 1 << i
))
7719 specs
[count
] = tmpl
;
7720 specs
[count
++].index
= i
;
7728 else if (note
== 11) /* note 11 implies note 1 as well */
7732 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7734 if (idesc
->operands
[i
] == IA64_OPND_P1
7735 || idesc
->operands
[i
] == IA64_OPND_P2
)
7737 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7738 if (regno
>= 1 && regno
< 16)
7740 specs
[count
] = tmpl
;
7741 specs
[count
++].index
= regno
;
7751 else if (note
== 12)
7753 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7755 specs
[count
] = tmpl
;
7756 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7763 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7764 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7765 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7766 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7768 if ((idesc
->operands
[0] == IA64_OPND_P1
7769 || idesc
->operands
[0] == IA64_OPND_P2
)
7770 && p1
>= 1 && p1
< 16)
7772 specs
[count
] = tmpl
;
7773 specs
[count
].cmp_type
=
7774 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7775 specs
[count
++].index
= p1
;
7777 if ((idesc
->operands
[1] == IA64_OPND_P1
7778 || idesc
->operands
[1] == IA64_OPND_P2
)
7779 && p2
>= 1 && p2
< 16)
7781 specs
[count
] = tmpl
;
7782 specs
[count
].cmp_type
=
7783 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7784 specs
[count
++].index
= p2
;
7789 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7791 specs
[count
] = tmpl
;
7792 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7794 if (idesc
->operands
[1] == IA64_OPND_PR
)
7796 for (i
= 1; i
< 16; i
++)
7798 specs
[count
] = tmpl
;
7799 specs
[count
++].index
= i
;
7810 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7811 simplified cases of this. */
7815 for (i
= 16; i
< 63; i
++)
7817 specs
[count
] = tmpl
;
7818 specs
[count
++].index
= i
;
7824 /* Mark only those registers indicated by the mask. */
7826 && idesc
->operands
[0] == IA64_OPND_PR
)
7828 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7829 if (mask
& ((valueT
) 1<<16))
7830 for (i
= 16; i
< 63; i
++)
7832 specs
[count
] = tmpl
;
7833 specs
[count
++].index
= i
;
7837 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7839 for (i
= 16; i
< 63; i
++)
7841 specs
[count
] = tmpl
;
7842 specs
[count
++].index
= i
;
7850 else if (note
== 11) /* note 11 implies note 1 as well */
7854 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7856 if (idesc
->operands
[i
] == IA64_OPND_P1
7857 || idesc
->operands
[i
] == IA64_OPND_P2
)
7859 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7860 if (regno
>= 16 && regno
< 63)
7862 specs
[count
] = tmpl
;
7863 specs
[count
++].index
= regno
;
7873 else if (note
== 12)
7875 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7877 specs
[count
] = tmpl
;
7878 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7885 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7886 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7887 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7888 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7890 if ((idesc
->operands
[0] == IA64_OPND_P1
7891 || idesc
->operands
[0] == IA64_OPND_P2
)
7892 && p1
>= 16 && p1
< 63)
7894 specs
[count
] = tmpl
;
7895 specs
[count
].cmp_type
=
7896 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7897 specs
[count
++].index
= p1
;
7899 if ((idesc
->operands
[1] == IA64_OPND_P1
7900 || idesc
->operands
[1] == IA64_OPND_P2
)
7901 && p2
>= 16 && p2
< 63)
7903 specs
[count
] = tmpl
;
7904 specs
[count
].cmp_type
=
7905 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7906 specs
[count
++].index
= p2
;
7911 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7913 specs
[count
] = tmpl
;
7914 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7916 if (idesc
->operands
[1] == IA64_OPND_PR
)
7918 for (i
= 16; i
< 63; i
++)
7920 specs
[count
] = tmpl
;
7921 specs
[count
++].index
= i
;
7933 /* Verify that the instruction is using the PSR bit indicated in
7937 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7939 if (dep
->regindex
< 6)
7941 specs
[count
++] = tmpl
;
7944 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7946 if (dep
->regindex
< 32
7947 || dep
->regindex
== 35
7948 || dep
->regindex
== 36
7949 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7951 specs
[count
++] = tmpl
;
7954 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7956 if (dep
->regindex
< 32
7957 || dep
->regindex
== 35
7958 || dep
->regindex
== 36
7959 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7961 specs
[count
++] = tmpl
;
7966 /* Several PSR bits have very specific dependencies. */
7967 switch (dep
->regindex
)
7970 specs
[count
++] = tmpl
;
7975 specs
[count
++] = tmpl
;
7979 /* Only certain CR accesses use PSR.ic */
7980 if (idesc
->operands
[0] == IA64_OPND_CR3
7981 || idesc
->operands
[1] == IA64_OPND_CR3
)
7984 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7987 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8002 specs
[count
++] = tmpl
;
8011 specs
[count
++] = tmpl
;
8015 /* Only some AR accesses use cpl */
8016 if (idesc
->operands
[0] == IA64_OPND_AR3
8017 || idesc
->operands
[1] == IA64_OPND_AR3
)
8020 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8023 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8030 && regno
<= AR_K7
))))
8032 specs
[count
++] = tmpl
;
8037 specs
[count
++] = tmpl
;
8047 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8049 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8055 if (mask
& ((valueT
) 1 << dep
->regindex
))
8057 specs
[count
++] = tmpl
;
8062 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8063 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8064 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8065 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8067 if (idesc
->operands
[i
] == IA64_OPND_F1
8068 || idesc
->operands
[i
] == IA64_OPND_F2
8069 || idesc
->operands
[i
] == IA64_OPND_F3
8070 || idesc
->operands
[i
] == IA64_OPND_F4
)
8072 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8073 if (reg
>= min
&& reg
<= max
)
8075 specs
[count
++] = tmpl
;
8082 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8083 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8084 /* mfh is read on writes to FR32-127; mfl is read on writes to
8086 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8088 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8090 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8091 if (reg
>= min
&& reg
<= max
)
8093 specs
[count
++] = tmpl
;
8098 else if (note
== 10)
8100 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8102 if (idesc
->operands
[i
] == IA64_OPND_R1
8103 || idesc
->operands
[i
] == IA64_OPND_R2
8104 || idesc
->operands
[i
] == IA64_OPND_R3
)
8106 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8107 if (regno
>= 16 && regno
<= 31)
8109 specs
[count
++] = tmpl
;
8120 case IA64_RS_AR_FPSR
:
8121 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8123 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8124 if (regno
== AR_FPSR
)
8126 specs
[count
++] = tmpl
;
8131 specs
[count
++] = tmpl
;
8136 /* Handle all AR[REG] resources */
8137 if (note
== 0 || note
== 1)
8139 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8140 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8141 && regno
== dep
->regindex
)
8143 specs
[count
++] = tmpl
;
8145 /* other AR[REG] resources may be affected by AR accesses */
8146 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8149 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8150 switch (dep
->regindex
)
8156 if (regno
== AR_BSPSTORE
)
8158 specs
[count
++] = tmpl
;
8162 (regno
== AR_BSPSTORE
8163 || regno
== AR_RNAT
))
8165 specs
[count
++] = tmpl
;
8170 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8173 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8174 switch (dep
->regindex
)
8179 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8181 specs
[count
++] = tmpl
;
8188 specs
[count
++] = tmpl
;
8198 /* Handle all CR[REG] resources */
8199 if (note
== 0 || note
== 1)
8201 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8203 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8204 if (regno
== dep
->regindex
)
8206 specs
[count
++] = tmpl
;
8208 else if (!rsrc_write
)
8210 /* Reads from CR[IVR] affect other resources. */
8211 if (regno
== CR_IVR
)
8213 if ((dep
->regindex
>= CR_IRR0
8214 && dep
->regindex
<= CR_IRR3
)
8215 || dep
->regindex
== CR_TPR
)
8217 specs
[count
++] = tmpl
;
8224 specs
[count
++] = tmpl
;
8233 case IA64_RS_INSERVICE
:
8234 /* look for write of EOI (67) or read of IVR (65) */
8235 if ((idesc
->operands
[0] == IA64_OPND_CR3
8236 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8237 || (idesc
->operands
[1] == IA64_OPND_CR3
8238 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8240 specs
[count
++] = tmpl
;
8247 specs
[count
++] = tmpl
;
8258 specs
[count
++] = tmpl
;
8262 /* Check if any of the registers accessed are in the rotating region.
8263 mov to/from pr accesses CFM only when qp_regno is in the rotating
8265 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8267 if (idesc
->operands
[i
] == IA64_OPND_R1
8268 || idesc
->operands
[i
] == IA64_OPND_R2
8269 || idesc
->operands
[i
] == IA64_OPND_R3
)
8271 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8272 /* Assumes that md.rot.num_regs is always valid */
8273 if (md
.rot
.num_regs
> 0
8275 && num
< 31 + md
.rot
.num_regs
)
8277 specs
[count
] = tmpl
;
8278 specs
[count
++].specific
= 0;
8281 else if (idesc
->operands
[i
] == IA64_OPND_F1
8282 || idesc
->operands
[i
] == IA64_OPND_F2
8283 || idesc
->operands
[i
] == IA64_OPND_F3
8284 || idesc
->operands
[i
] == IA64_OPND_F4
)
8286 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8289 specs
[count
] = tmpl
;
8290 specs
[count
++].specific
= 0;
8293 else if (idesc
->operands
[i
] == IA64_OPND_P1
8294 || idesc
->operands
[i
] == IA64_OPND_P2
)
8296 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8299 specs
[count
] = tmpl
;
8300 specs
[count
++].specific
= 0;
8304 if (CURR_SLOT
.qp_regno
> 15)
8306 specs
[count
] = tmpl
;
8307 specs
[count
++].specific
= 0;
8312 /* This is the same as IA64_RS_PRr, except simplified to account for
8313 the fact that there is only one register. */
8317 specs
[count
++] = tmpl
;
8322 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8323 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8324 if (mask
& ((valueT
) 1 << 63))
8325 specs
[count
++] = tmpl
;
8327 else if (note
== 11)
8329 if ((idesc
->operands
[0] == IA64_OPND_P1
8330 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8331 || (idesc
->operands
[1] == IA64_OPND_P2
8332 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8334 specs
[count
++] = tmpl
;
8337 else if (note
== 12)
8339 if (CURR_SLOT
.qp_regno
== 63)
8341 specs
[count
++] = tmpl
;
8348 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8349 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8350 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8351 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8354 && (idesc
->operands
[0] == IA64_OPND_P1
8355 || idesc
->operands
[0] == IA64_OPND_P2
))
8357 specs
[count
] = tmpl
;
8358 specs
[count
++].cmp_type
=
8359 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8362 && (idesc
->operands
[1] == IA64_OPND_P1
8363 || idesc
->operands
[1] == IA64_OPND_P2
))
8365 specs
[count
] = tmpl
;
8366 specs
[count
++].cmp_type
=
8367 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8372 if (CURR_SLOT
.qp_regno
== 63)
8374 specs
[count
++] = tmpl
;
8385 /* FIXME we can identify some individual RSE written resources, but RSE
8386 read resources have not yet been completely identified, so for now
8387 treat RSE as a single resource */
8388 if (strncmp (idesc
->name
, "mov", 3) == 0)
8392 if (idesc
->operands
[0] == IA64_OPND_AR3
8393 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8395 specs
[count
] = tmpl
;
8396 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8401 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8403 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8404 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8406 specs
[count
++] = tmpl
;
8409 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8411 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8412 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8413 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8415 specs
[count
++] = tmpl
;
8422 specs
[count
++] = tmpl
;
8427 /* FIXME -- do any of these need to be non-specific? */
8428 specs
[count
++] = tmpl
;
8432 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8439 /* Clear branch flags on marked resources. This breaks the link between the
8440 QP of the marking instruction and a subsequent branch on the same QP. */
8443 clear_qp_branch_flag (mask
)
8447 for (i
= 0; i
< regdepslen
; i
++)
8449 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8450 if ((bit
& mask
) != 0)
8452 regdeps
[i
].link_to_qp_branch
= 0;
8457 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8459 Any changes to a PR clears the mutex relations which include that PR. */
8462 clear_qp_mutex (mask
)
8468 while (i
< qp_mutexeslen
)
8470 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8474 fprintf (stderr
, " Clearing mutex relation");
8475 print_prmask (qp_mutexes
[i
].prmask
);
8476 fprintf (stderr
, "\n");
8478 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8485 /* Clear implies relations which contain PRs in the given masks.
8486 P1_MASK indicates the source of the implies relation, while P2_MASK
8487 indicates the implied PR. */
8490 clear_qp_implies (p1_mask
, p2_mask
)
8497 while (i
< qp_implieslen
)
8499 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8500 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8503 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8504 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8505 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8512 /* Add the PRs specified to the list of implied relations. */
8515 add_qp_imply (p1
, p2
)
8522 /* p0 is not meaningful here. */
8523 if (p1
== 0 || p2
== 0)
8529 /* If it exists already, ignore it. */
8530 for (i
= 0; i
< qp_implieslen
; i
++)
8532 if (qp_implies
[i
].p1
== p1
8533 && qp_implies
[i
].p2
== p2
8534 && qp_implies
[i
].path
== md
.path
8535 && !qp_implies
[i
].p2_branched
)
8539 if (qp_implieslen
== qp_impliestotlen
)
8541 qp_impliestotlen
+= 20;
8542 qp_implies
= (struct qp_imply
*)
8543 xrealloc ((void *) qp_implies
,
8544 qp_impliestotlen
* sizeof (struct qp_imply
));
8547 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8548 qp_implies
[qp_implieslen
].p1
= p1
;
8549 qp_implies
[qp_implieslen
].p2
= p2
;
8550 qp_implies
[qp_implieslen
].path
= md
.path
;
8551 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8553 /* Add in the implied transitive relations; for everything that p2 implies,
8554 make p1 imply that, too; for everything that implies p1, make it imply p2
8556 for (i
= 0; i
< qp_implieslen
; i
++)
8558 if (qp_implies
[i
].p1
== p2
)
8559 add_qp_imply (p1
, qp_implies
[i
].p2
);
8560 if (qp_implies
[i
].p2
== p1
)
8561 add_qp_imply (qp_implies
[i
].p1
, p2
);
8563 /* Add in mutex relations implied by this implies relation; for each mutex
8564 relation containing p2, duplicate it and replace p2 with p1. */
8565 bit
= (valueT
) 1 << p1
;
8566 mask
= (valueT
) 1 << p2
;
8567 for (i
= 0; i
< qp_mutexeslen
; i
++)
8569 if (qp_mutexes
[i
].prmask
& mask
)
8570 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8574 /* Add the PRs specified in the mask to the mutex list; this means that only
8575 one of the PRs can be true at any time. PR0 should never be included in
8585 if (qp_mutexeslen
== qp_mutexestotlen
)
8587 qp_mutexestotlen
+= 20;
8588 qp_mutexes
= (struct qpmutex
*)
8589 xrealloc ((void *) qp_mutexes
,
8590 qp_mutexestotlen
* sizeof (struct qpmutex
));
8594 fprintf (stderr
, " Registering mutex on");
8595 print_prmask (mask
);
8596 fprintf (stderr
, "\n");
8598 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8599 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8603 clear_register_values ()
8607 fprintf (stderr
, " Clearing register values\n");
8608 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8609 gr_values
[i
].known
= 0;
8612 /* Keep track of register values/changes which affect DV tracking.
8614 optimization note: should add a flag to classes of insns where otherwise we
8615 have to examine a group of strings to identify them. */
8618 note_register_values (idesc
)
8619 struct ia64_opcode
*idesc
;
8621 valueT qp_changemask
= 0;
8624 /* Invalidate values for registers being written to. */
8625 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8627 if (idesc
->operands
[i
] == IA64_OPND_R1
8628 || idesc
->operands
[i
] == IA64_OPND_R2
8629 || idesc
->operands
[i
] == IA64_OPND_R3
)
8631 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8632 if (regno
> 0 && regno
< NELEMS (gr_values
))
8633 gr_values
[regno
].known
= 0;
8635 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8637 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8638 if (regno
> 0 && regno
< 4)
8639 gr_values
[regno
].known
= 0;
8641 else if (idesc
->operands
[i
] == IA64_OPND_P1
8642 || idesc
->operands
[i
] == IA64_OPND_P2
)
8644 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8645 qp_changemask
|= (valueT
) 1 << regno
;
8647 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8649 if (idesc
->operands
[2] & (valueT
) 0x10000)
8650 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8652 qp_changemask
= idesc
->operands
[2];
8655 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8657 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8658 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8660 qp_changemask
= idesc
->operands
[1];
8661 qp_changemask
&= ~(valueT
) 0xFFFF;
8666 /* Always clear qp branch flags on any PR change. */
8667 /* FIXME there may be exceptions for certain compares. */
8668 clear_qp_branch_flag (qp_changemask
);
8670 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8671 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8673 qp_changemask
|= ~(valueT
) 0xFFFF;
8674 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8676 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8677 gr_values
[i
].known
= 0;
8679 clear_qp_mutex (qp_changemask
);
8680 clear_qp_implies (qp_changemask
, qp_changemask
);
8682 /* After a call, all register values are undefined, except those marked
8684 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8685 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8687 /* FIXME keep GR values which are marked as "safe_across_calls" */
8688 clear_register_values ();
8689 clear_qp_mutex (~qp_safe_across_calls
);
8690 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8691 clear_qp_branch_flag (~qp_safe_across_calls
);
8693 else if (is_interruption_or_rfi (idesc
)
8694 || is_taken_branch (idesc
))
8696 clear_register_values ();
8697 clear_qp_mutex (~(valueT
) 0);
8698 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8700 /* Look for mutex and implies relations. */
8701 else if ((idesc
->operands
[0] == IA64_OPND_P1
8702 || idesc
->operands
[0] == IA64_OPND_P2
)
8703 && (idesc
->operands
[1] == IA64_OPND_P1
8704 || idesc
->operands
[1] == IA64_OPND_P2
))
8706 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8707 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8708 valueT p1mask
= (valueT
) 1 << p1
;
8709 valueT p2mask
= (valueT
) 1 << p2
;
8711 /* If one of the PRs is PR0, we can't really do anything. */
8712 if (p1
== 0 || p2
== 0)
8715 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8717 /* In general, clear mutexes and implies which include P1 or P2,
8718 with the following exceptions. */
8719 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8721 add_qp_mutex (p1mask
| p2mask
);
8722 clear_qp_implies (p2mask
, p1mask
);
8724 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8726 add_qp_mutex (p1mask
| p2mask
);
8727 clear_qp_implies (p1mask
, p2mask
);
8729 else if (strstr (idesc
->name
, ".and") != NULL
)
8731 clear_qp_implies (0, p1mask
| p2mask
);
8733 else if (strstr (idesc
->name
, ".or") != NULL
)
8735 clear_qp_mutex (p1mask
| p2mask
);
8736 clear_qp_implies (p1mask
| p2mask
, 0);
8740 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8741 if (strstr (idesc
->name
, ".unc") != NULL
)
8743 add_qp_mutex (p1mask
| p2mask
);
8744 if (CURR_SLOT
.qp_regno
!= 0)
8746 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8747 CURR_SLOT
.qp_regno
);
8748 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8749 CURR_SLOT
.qp_regno
);
8752 else if (CURR_SLOT
.qp_regno
== 0)
8754 add_qp_mutex (p1mask
| p2mask
);
8758 clear_qp_mutex (p1mask
| p2mask
);
8762 /* Look for mov imm insns into GRs. */
8763 else if (idesc
->operands
[0] == IA64_OPND_R1
8764 && (idesc
->operands
[1] == IA64_OPND_IMM22
8765 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8766 && (strcmp (idesc
->name
, "mov") == 0
8767 || strcmp (idesc
->name
, "movl") == 0))
8769 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8770 if (regno
> 0 && regno
< NELEMS (gr_values
))
8772 gr_values
[regno
].known
= 1;
8773 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8774 gr_values
[regno
].path
= md
.path
;
8777 fprintf (stderr
, " Know gr%d = ", regno
);
8778 fprintf_vma (stderr
, gr_values
[regno
].value
);
8779 fputs ("\n", stderr
);
8785 clear_qp_mutex (qp_changemask
);
8786 clear_qp_implies (qp_changemask
, qp_changemask
);
8790 /* Return whether the given predicate registers are currently mutex. */
8793 qp_mutex (p1
, p2
, path
)
8803 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8804 for (i
= 0; i
< qp_mutexeslen
; i
++)
8806 if (qp_mutexes
[i
].path
>= path
8807 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8814 /* Return whether the given resource is in the given insn's list of chks
8815 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8819 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8821 struct ia64_opcode
*idesc
;
8826 struct rsrc specs
[MAX_SPECS
];
8829 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8830 we don't need to check. One exception is note 11, which indicates that
8831 target predicates are written regardless of PR[qp]. */
8832 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8836 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8839 /* UNAT checking is a bit more specific than other resources */
8840 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8841 && specs
[count
].mem_offset
.hint
8842 && rs
->mem_offset
.hint
)
8844 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8846 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8847 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8854 /* Skip apparent PR write conflicts where both writes are an AND or both
8855 writes are an OR. */
8856 if (rs
->dependency
->specifier
== IA64_RS_PR
8857 || rs
->dependency
->specifier
== IA64_RS_PRr
8858 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8860 if (specs
[count
].cmp_type
!= CMP_NONE
8861 && specs
[count
].cmp_type
== rs
->cmp_type
)
8864 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8865 dv_mode
[rs
->dependency
->mode
],
8866 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8867 specs
[count
].index
: 63);
8872 " %s on parallel compare conflict %s vs %s on PR%d\n",
8873 dv_mode
[rs
->dependency
->mode
],
8874 dv_cmp_type
[rs
->cmp_type
],
8875 dv_cmp_type
[specs
[count
].cmp_type
],
8876 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8877 specs
[count
].index
: 63);
8881 /* If either resource is not specific, conservatively assume a conflict
8883 if (!specs
[count
].specific
|| !rs
->specific
)
8885 else if (specs
[count
].index
== rs
->index
)
8890 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8896 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8897 insert a stop to create the break. Update all resource dependencies
8898 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8899 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8900 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8904 insn_group_break (insert_stop
, qp_regno
, save_current
)
8911 if (insert_stop
&& md
.num_slots_in_use
> 0)
8912 PREV_SLOT
.end_of_insn_group
= 1;
8916 fprintf (stderr
, " Insn group break%s",
8917 (insert_stop
? " (w/stop)" : ""));
8919 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8920 fprintf (stderr
, "\n");
8924 while (i
< regdepslen
)
8926 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8929 && regdeps
[i
].qp_regno
!= qp_regno
)
8936 && CURR_SLOT
.src_file
== regdeps
[i
].file
8937 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8943 /* clear dependencies which are automatically cleared by a stop, or
8944 those that have reached the appropriate state of insn serialization */
8945 if (dep
->semantics
== IA64_DVS_IMPLIED
8946 || dep
->semantics
== IA64_DVS_IMPLIEDF
8947 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8949 print_dependency ("Removing", i
);
8950 regdeps
[i
] = regdeps
[--regdepslen
];
8954 if (dep
->semantics
== IA64_DVS_DATA
8955 || dep
->semantics
== IA64_DVS_INSTR
8956 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8958 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8959 regdeps
[i
].insn_srlz
= STATE_STOP
;
8960 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8961 regdeps
[i
].data_srlz
= STATE_STOP
;
8968 /* Add the given resource usage spec to the list of active dependencies. */
8971 mark_resource (idesc
, dep
, spec
, depind
, path
)
8972 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8973 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8978 if (regdepslen
== regdepstotlen
)
8980 regdepstotlen
+= 20;
8981 regdeps
= (struct rsrc
*)
8982 xrealloc ((void *) regdeps
,
8983 regdepstotlen
* sizeof (struct rsrc
));
8986 regdeps
[regdepslen
] = *spec
;
8987 regdeps
[regdepslen
].depind
= depind
;
8988 regdeps
[regdepslen
].path
= path
;
8989 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8990 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8992 print_dependency ("Adding", regdepslen
);
8998 print_dependency (action
, depind
)
9004 fprintf (stderr
, " %s %s '%s'",
9005 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9006 (regdeps
[depind
].dependency
)->name
);
9007 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9008 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9009 if (regdeps
[depind
].mem_offset
.hint
)
9011 fputs (" ", stderr
);
9012 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9013 fputs ("+", stderr
);
9014 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9016 fprintf (stderr
, "\n");
9021 instruction_serialization ()
9025 fprintf (stderr
, " Instruction serialization\n");
9026 for (i
= 0; i
< regdepslen
; i
++)
9027 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9028 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9032 data_serialization ()
9036 fprintf (stderr
, " Data serialization\n");
9037 while (i
< regdepslen
)
9039 if (regdeps
[i
].data_srlz
== STATE_STOP
9040 /* Note: as of 991210, all "other" dependencies are cleared by a
9041 data serialization. This might change with new tables */
9042 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9044 print_dependency ("Removing", i
);
9045 regdeps
[i
] = regdeps
[--regdepslen
];
9052 /* Insert stops and serializations as needed to avoid DVs. */
9055 remove_marked_resource (rs
)
9058 switch (rs
->dependency
->semantics
)
9060 case IA64_DVS_SPECIFIC
:
9062 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9063 /* ...fall through... */
9064 case IA64_DVS_INSTR
:
9066 fprintf (stderr
, "Inserting instr serialization\n");
9067 if (rs
->insn_srlz
< STATE_STOP
)
9068 insn_group_break (1, 0, 0);
9069 if (rs
->insn_srlz
< STATE_SRLZ
)
9071 int oldqp
= CURR_SLOT
.qp_regno
;
9072 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9073 /* Manually jam a srlz.i insn into the stream */
9074 CURR_SLOT
.qp_regno
= 0;
9075 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9076 instruction_serialization ();
9077 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9078 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9080 CURR_SLOT
.qp_regno
= oldqp
;
9081 CURR_SLOT
.idesc
= oldidesc
;
9083 insn_group_break (1, 0, 0);
9085 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9086 "other" types of DV are eliminated
9087 by a data serialization */
9090 fprintf (stderr
, "Inserting data serialization\n");
9091 if (rs
->data_srlz
< STATE_STOP
)
9092 insn_group_break (1, 0, 0);
9094 int oldqp
= CURR_SLOT
.qp_regno
;
9095 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9096 /* Manually jam a srlz.d insn into the stream */
9097 CURR_SLOT
.qp_regno
= 0;
9098 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9099 data_serialization ();
9100 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9101 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9103 CURR_SLOT
.qp_regno
= oldqp
;
9104 CURR_SLOT
.idesc
= oldidesc
;
9107 case IA64_DVS_IMPLIED
:
9108 case IA64_DVS_IMPLIEDF
:
9110 fprintf (stderr
, "Inserting stop\n");
9111 insn_group_break (1, 0, 0);
9118 /* Check the resources used by the given opcode against the current dependency
9121 The check is run once for each execution path encountered. In this case,
9122 a unique execution path is the sequence of instructions following a code
9123 entry point, e.g. the following has three execution paths, one starting
9124 at L0, one at L1, and one at L2.
9133 check_dependencies (idesc
)
9134 struct ia64_opcode
*idesc
;
9136 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9140 /* Note that the number of marked resources may change within the
9141 loop if in auto mode. */
9143 while (i
< regdepslen
)
9145 struct rsrc
*rs
= ®deps
[i
];
9146 const struct ia64_dependency
*dep
= rs
->dependency
;
9151 if (dep
->semantics
== IA64_DVS_NONE
9152 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9158 note
= NOTE (opdeps
->chks
[chkind
]);
9160 /* Check this resource against each execution path seen thus far. */
9161 for (path
= 0; path
<= md
.path
; path
++)
9165 /* If the dependency wasn't on the path being checked, ignore it. */
9166 if (rs
->path
< path
)
9169 /* If the QP for this insn implies a QP which has branched, don't
9170 bother checking. Ed. NOTE: I don't think this check is terribly
9171 useful; what's the point of generating code which will only be
9172 reached if its QP is zero?
9173 This code was specifically inserted to handle the following code,
9174 based on notes from Intel's DV checking code, where p1 implies p2.
9180 if (CURR_SLOT
.qp_regno
!= 0)
9184 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9186 if (qp_implies
[implies
].path
>= path
9187 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9188 && qp_implies
[implies
].p2_branched
)
9198 if ((matchtype
= resources_match (rs
, idesc
, note
,
9199 CURR_SLOT
.qp_regno
, path
)) != 0)
9202 char pathmsg
[256] = "";
9203 char indexmsg
[256] = "";
9204 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9207 sprintf (pathmsg
, " when entry is at label '%s'",
9208 md
.entry_labels
[path
- 1]);
9209 if (rs
->specific
&& rs
->index
!= 0)
9210 sprintf (indexmsg
, ", specific resource number is %d",
9212 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9214 (certain
? "violates" : "may violate"),
9215 dv_mode
[dep
->mode
], dep
->name
,
9216 dv_sem
[dep
->semantics
],
9219 if (md
.explicit_mode
)
9221 as_warn ("%s", msg
);
9223 as_warn (_("Only the first path encountering the conflict "
9225 as_warn_where (rs
->file
, rs
->line
,
9226 _("This is the location of the "
9227 "conflicting usage"));
9228 /* Don't bother checking other paths, to avoid duplicating
9235 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9237 remove_marked_resource (rs
);
9239 /* since the set of dependencies has changed, start over */
9240 /* FIXME -- since we're removing dvs as we go, we
9241 probably don't really need to start over... */
9254 /* Register new dependencies based on the given opcode. */
9257 mark_resources (idesc
)
9258 struct ia64_opcode
*idesc
;
9261 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9262 int add_only_qp_reads
= 0;
9264 /* A conditional branch only uses its resources if it is taken; if it is
9265 taken, we stop following that path. The other branch types effectively
9266 *always* write their resources. If it's not taken, register only QP
9268 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9270 add_only_qp_reads
= 1;
9274 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9276 for (i
= 0; i
< opdeps
->nregs
; i
++)
9278 const struct ia64_dependency
*dep
;
9279 struct rsrc specs
[MAX_SPECS
];
9284 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9285 note
= NOTE (opdeps
->regs
[i
]);
9287 if (add_only_qp_reads
9288 && !(dep
->mode
== IA64_DV_WAR
9289 && (dep
->specifier
== IA64_RS_PR
9290 || dep
->specifier
== IA64_RS_PRr
9291 || dep
->specifier
== IA64_RS_PR63
)))
9294 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9297 if (md
.debug_dv
&& !count
)
9298 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9299 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9304 mark_resource (idesc
, dep
, &specs
[count
],
9305 DEP (opdeps
->regs
[i
]), md
.path
);
9308 /* The execution path may affect register values, which may in turn
9309 affect which indirect-access resources are accessed. */
9310 switch (dep
->specifier
)
9322 for (path
= 0; path
< md
.path
; path
++)
9324 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9326 mark_resource (idesc
, dep
, &specs
[count
],
9327 DEP (opdeps
->regs
[i
]), path
);
9334 /* Remove dependencies when they no longer apply. */
9337 update_dependencies (idesc
)
9338 struct ia64_opcode
*idesc
;
9342 if (strcmp (idesc
->name
, "srlz.i") == 0)
9344 instruction_serialization ();
9346 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9348 data_serialization ();
9350 else if (is_interruption_or_rfi (idesc
)
9351 || is_taken_branch (idesc
))
9353 /* Although technically the taken branch doesn't clear dependencies
9354 which require a srlz.[id], we don't follow the branch; the next
9355 instruction is assumed to start with a clean slate. */
9359 else if (is_conditional_branch (idesc
)
9360 && CURR_SLOT
.qp_regno
!= 0)
9362 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9364 for (i
= 0; i
< qp_implieslen
; i
++)
9366 /* If the conditional branch's predicate is implied by the predicate
9367 in an existing dependency, remove that dependency. */
9368 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9371 /* Note that this implied predicate takes a branch so that if
9372 a later insn generates a DV but its predicate implies this
9373 one, we can avoid the false DV warning. */
9374 qp_implies
[i
].p2_branched
= 1;
9375 while (depind
< regdepslen
)
9377 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9379 print_dependency ("Removing", depind
);
9380 regdeps
[depind
] = regdeps
[--regdepslen
];
9387 /* Any marked resources which have this same predicate should be
9388 cleared, provided that the QP hasn't been modified between the
9389 marking instruction and the branch. */
9392 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9397 while (i
< regdepslen
)
9399 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9400 && regdeps
[i
].link_to_qp_branch
9401 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9402 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9404 /* Treat like a taken branch */
9405 print_dependency ("Removing", i
);
9406 regdeps
[i
] = regdeps
[--regdepslen
];
9415 /* Examine the current instruction for dependency violations. */
9419 struct ia64_opcode
*idesc
;
9423 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9424 idesc
->name
, CURR_SLOT
.src_line
,
9425 idesc
->dependencies
->nchks
,
9426 idesc
->dependencies
->nregs
);
9429 /* Look through the list of currently marked resources; if the current
9430 instruction has the dependency in its chks list which uses that resource,
9431 check against the specific resources used. */
9432 check_dependencies (idesc
);
9434 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9435 then add them to the list of marked resources. */
9436 mark_resources (idesc
);
9438 /* There are several types of dependency semantics, and each has its own
9439 requirements for being cleared
9441 Instruction serialization (insns separated by interruption, rfi, or
9442 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9444 Data serialization (instruction serialization, or writer + srlz.d +
9445 reader, where writer and srlz.d are in separate groups) clears
9446 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9447 always be the case).
9449 Instruction group break (groups separated by stop, taken branch,
9450 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9452 update_dependencies (idesc
);
9454 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9455 warning. Keep track of as many as possible that are useful. */
9456 note_register_values (idesc
);
9458 /* We don't need or want this anymore. */
9459 md
.mem_offset
.hint
= 0;
9464 /* Translate one line of assembly. Pseudo ops and labels do not show
9470 char *saved_input_line_pointer
, *mnemonic
;
9471 const struct pseudo_opcode
*pdesc
;
9472 struct ia64_opcode
*idesc
;
9473 unsigned char qp_regno
;
9477 saved_input_line_pointer
= input_line_pointer
;
9478 input_line_pointer
= str
;
9480 /* extract the opcode (mnemonic): */
9482 mnemonic
= input_line_pointer
;
9483 ch
= get_symbol_end ();
9484 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9487 *input_line_pointer
= ch
;
9488 (*pdesc
->handler
) (pdesc
->arg
);
9492 /* Find the instruction descriptor matching the arguments. */
9494 idesc
= ia64_find_opcode (mnemonic
);
9495 *input_line_pointer
= ch
;
9498 as_bad ("Unknown opcode `%s'", mnemonic
);
9502 idesc
= parse_operands (idesc
);
9506 /* Handle the dynamic ops we can handle now: */
9507 if (idesc
->type
== IA64_TYPE_DYN
)
9509 if (strcmp (idesc
->name
, "add") == 0)
9511 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9512 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9516 ia64_free_opcode (idesc
);
9517 idesc
= ia64_find_opcode (mnemonic
);
9519 know (!idesc
->next
);
9522 else if (strcmp (idesc
->name
, "mov") == 0)
9524 enum ia64_opnd opnd1
, opnd2
;
9527 opnd1
= idesc
->operands
[0];
9528 opnd2
= idesc
->operands
[1];
9529 if (opnd1
== IA64_OPND_AR3
)
9531 else if (opnd2
== IA64_OPND_AR3
)
9535 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9536 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9540 ia64_free_opcode (idesc
);
9541 idesc
= ia64_find_opcode (mnemonic
);
9542 while (idesc
!= NULL
9543 && (idesc
->operands
[0] != opnd1
9544 || idesc
->operands
[1] != opnd2
))
9545 idesc
= get_next_opcode (idesc
);
9550 if (md
.qp
.X_op
== O_register
)
9552 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9553 md
.qp
.X_op
= O_absent
;
9556 flags
= idesc
->flags
;
9558 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9559 insn_group_break (1, 0, 0);
9561 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9563 as_bad ("`%s' cannot be predicated", idesc
->name
);
9567 /* Build the instruction. */
9568 CURR_SLOT
.qp_regno
= qp_regno
;
9569 CURR_SLOT
.idesc
= idesc
;
9570 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9571 dwarf2_where (&CURR_SLOT
.debug_line
);
9573 /* Add unwind entry, if there is one. */
9574 if (unwind
.current_entry
)
9576 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9577 unwind
.current_entry
= NULL
;
9580 /* Check for dependency violations. */
9584 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9585 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9588 if ((flags
& IA64_OPCODE_LAST
) != 0)
9589 insn_group_break (1, 0, 0);
9591 md
.last_text_seg
= now_seg
;
9594 input_line_pointer
= saved_input_line_pointer
;
9597 /* Called when symbol NAME cannot be found in the symbol table.
9598 Should be used for dynamic valued symbols only. */
9601 md_undefined_symbol (name
)
9602 char *name ATTRIBUTE_UNUSED
;
9607 /* Called for any expression that can not be recognized. When the
9608 function is called, `input_line_pointer' will point to the start of
9615 enum pseudo_type pseudo_type
;
9620 switch (*input_line_pointer
)
9623 /* Find what relocation pseudo-function we're dealing with. */
9625 ch
= *++input_line_pointer
;
9626 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9627 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9629 len
= strlen (pseudo_func
[i
].name
);
9630 if (strncmp (pseudo_func
[i
].name
+ 1,
9631 input_line_pointer
+ 1, len
- 1) == 0
9632 && !is_part_of_name (input_line_pointer
[len
]))
9634 input_line_pointer
+= len
;
9635 pseudo_type
= pseudo_func
[i
].type
;
9639 switch (pseudo_type
)
9641 case PSEUDO_FUNC_RELOC
:
9643 if (*input_line_pointer
!= '(')
9645 as_bad ("Expected '('");
9649 ++input_line_pointer
;
9651 if (*input_line_pointer
++ != ')')
9653 as_bad ("Missing ')'");
9656 if (e
->X_op
!= O_symbol
)
9658 if (e
->X_op
!= O_pseudo_fixup
)
9660 as_bad ("Not a symbolic expression");
9663 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9664 && i
== FUNC_LT_RELATIVE
)
9665 i
= FUNC_LT_FPTR_RELATIVE
;
9668 as_bad ("Illegal combination of relocation functions");
9672 /* Make sure gas doesn't get rid of local symbols that are used
9674 e
->X_op
= O_pseudo_fixup
;
9675 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9678 case PSEUDO_FUNC_CONST
:
9679 e
->X_op
= O_constant
;
9680 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9683 case PSEUDO_FUNC_REG
:
9684 e
->X_op
= O_register
;
9685 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9689 name
= input_line_pointer
- 1;
9691 as_bad ("Unknown pseudo function `%s'", name
);
9697 ++input_line_pointer
;
9699 if (*input_line_pointer
!= ']')
9701 as_bad ("Closing bracket misssing");
9706 if (e
->X_op
!= O_register
)
9707 as_bad ("Register expected as index");
9709 ++input_line_pointer
;
9720 ignore_rest_of_line ();
9723 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9724 a section symbol plus some offset. For relocs involving @fptr(),
9725 directives we don't want such adjustments since we need to have the
9726 original symbol's name in the reloc. */
9728 ia64_fix_adjustable (fix
)
9731 /* Prevent all adjustments to global symbols */
9732 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9735 switch (fix
->fx_r_type
)
9737 case BFD_RELOC_IA64_FPTR64I
:
9738 case BFD_RELOC_IA64_FPTR32MSB
:
9739 case BFD_RELOC_IA64_FPTR32LSB
:
9740 case BFD_RELOC_IA64_FPTR64MSB
:
9741 case BFD_RELOC_IA64_FPTR64LSB
:
9742 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9743 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9753 ia64_force_relocation (fix
)
9756 switch (fix
->fx_r_type
)
9758 case BFD_RELOC_IA64_FPTR64I
:
9759 case BFD_RELOC_IA64_FPTR32MSB
:
9760 case BFD_RELOC_IA64_FPTR32LSB
:
9761 case BFD_RELOC_IA64_FPTR64MSB
:
9762 case BFD_RELOC_IA64_FPTR64LSB
:
9764 case BFD_RELOC_IA64_LTOFF22
:
9765 case BFD_RELOC_IA64_LTOFF64I
:
9766 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9767 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9768 case BFD_RELOC_IA64_PLTOFF22
:
9769 case BFD_RELOC_IA64_PLTOFF64I
:
9770 case BFD_RELOC_IA64_PLTOFF64MSB
:
9771 case BFD_RELOC_IA64_PLTOFF64LSB
:
9780 /* Decide from what point a pc-relative relocation is relative to,
9781 relative to the pc-relative fixup. Er, relatively speaking. */
9783 ia64_pcrel_from_section (fix
, sec
)
9787 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9789 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9795 /* This is called whenever some data item (not an instruction) needs a
9796 fixup. We pick the right reloc code depending on the byteorder
9797 currently in effect. */
9799 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9805 bfd_reloc_code_real_type code
;
9810 /* There are no reloc for 8 and 16 bit quantities, but we allow
9811 them here since they will work fine as long as the expression
9812 is fully defined at the end of the pass over the source file. */
9813 case 1: code
= BFD_RELOC_8
; break;
9814 case 2: code
= BFD_RELOC_16
; break;
9816 if (target_big_endian
)
9817 code
= BFD_RELOC_IA64_DIR32MSB
;
9819 code
= BFD_RELOC_IA64_DIR32LSB
;
9823 if (target_big_endian
)
9824 code
= BFD_RELOC_IA64_DIR64MSB
;
9826 code
= BFD_RELOC_IA64_DIR64LSB
;
9830 as_bad ("Unsupported fixup size %d", nbytes
);
9831 ignore_rest_of_line ();
9834 if (exp
->X_op
== O_pseudo_fixup
)
9837 exp
->X_op
= O_symbol
;
9838 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9840 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9841 /* We need to store the byte order in effect in case we're going
9842 to fix an 8 or 16 bit relocation (for which there no real
9843 relocs available). See md_apply_fix(). */
9844 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9847 /* Return the actual relocation we wish to associate with the pseudo
9848 reloc described by SYM and R_TYPE. SYM should be one of the
9849 symbols in the pseudo_func array, or NULL. */
9851 static bfd_reloc_code_real_type
9852 ia64_gen_real_reloc_type (sym
, r_type
)
9854 bfd_reloc_code_real_type r_type
;
9856 bfd_reloc_code_real_type
new = 0;
9863 switch (S_GET_VALUE (sym
))
9865 case FUNC_FPTR_RELATIVE
:
9868 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9869 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9870 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9871 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9872 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9877 case FUNC_GP_RELATIVE
:
9880 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9881 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9882 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9883 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9884 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9885 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9890 case FUNC_LT_RELATIVE
:
9893 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9894 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9899 case FUNC_PC_RELATIVE
:
9902 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9903 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9904 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9905 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9906 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9907 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9912 case FUNC_PLT_RELATIVE
:
9915 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9916 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9917 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9918 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9923 case FUNC_SEC_RELATIVE
:
9926 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9927 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9928 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9929 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9934 case FUNC_SEG_RELATIVE
:
9937 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9938 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9939 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9940 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9945 case FUNC_LTV_RELATIVE
:
9948 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9949 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9950 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9951 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9956 case FUNC_LT_FPTR_RELATIVE
:
9959 case BFD_RELOC_IA64_IMM22
:
9960 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9961 case BFD_RELOC_IA64_IMM64
:
9962 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9970 /* Hmmmm. Should this ever occur? */
9977 /* Here is where generate the appropriate reloc for pseudo relocation
9980 ia64_validate_fix (fix
)
9983 switch (fix
->fx_r_type
)
9985 case BFD_RELOC_IA64_FPTR64I
:
9986 case BFD_RELOC_IA64_FPTR32MSB
:
9987 case BFD_RELOC_IA64_FPTR64LSB
:
9988 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9989 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9990 if (fix
->fx_offset
!= 0)
9991 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9992 "No addend allowed in @fptr() relocation");
10002 fix_insn (fix
, odesc
, value
)
10004 const struct ia64_operand
*odesc
;
10007 bfd_vma insn
[3], t0
, t1
, control_bits
;
10012 slot
= fix
->fx_where
& 0x3;
10013 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10015 /* Bundles are always in little-endian byte order */
10016 t0
= bfd_getl64 (fixpos
);
10017 t1
= bfd_getl64 (fixpos
+ 8);
10018 control_bits
= t0
& 0x1f;
10019 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10020 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10021 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10024 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10026 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10027 insn
[2] |= (((value
& 0x7f) << 13)
10028 | (((value
>> 7) & 0x1ff) << 27)
10029 | (((value
>> 16) & 0x1f) << 22)
10030 | (((value
>> 21) & 0x1) << 21)
10031 | (((value
>> 63) & 0x1) << 36));
10033 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10035 if (value
& ~0x3fffffffffffffffULL
)
10036 err
= "integer operand out of range";
10037 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10038 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10040 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10043 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10044 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10045 | (((value
>> 0) & 0xfffff) << 13));
10048 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10051 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10053 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10054 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10055 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10056 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10059 /* Attempt to simplify or even eliminate a fixup. The return value is
10060 ignored; perhaps it was once meaningful, but now it is historical.
10061 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10063 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10066 md_apply_fix3 (fix
, valuep
, seg
)
10069 segT seg ATTRIBUTE_UNUSED
;
10072 valueT value
= *valuep
;
10075 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10079 switch (fix
->fx_r_type
)
10081 case BFD_RELOC_IA64_DIR32MSB
:
10082 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10086 case BFD_RELOC_IA64_DIR32LSB
:
10087 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10091 case BFD_RELOC_IA64_DIR64MSB
:
10092 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10096 case BFD_RELOC_IA64_DIR64LSB
:
10097 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10107 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
10109 /* This must be a TAG13 or TAG13b operand. There are no external
10110 relocs defined for them, so we must give an error. */
10111 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10112 "%s must have a constant value",
10113 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10118 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10119 work. There should be a better way to handle this. */
10121 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10123 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10125 if (fix
->tc_fix_data
.bigendian
)
10126 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10128 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10134 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10141 /* Generate the BFD reloc to be stuck in the object file from the
10142 fixup used internally in the assembler. */
10145 tc_gen_reloc (sec
, fixp
)
10146 asection
*sec ATTRIBUTE_UNUSED
;
10151 reloc
= xmalloc (sizeof (*reloc
));
10152 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10153 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10154 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10155 reloc
->addend
= fixp
->fx_offset
;
10156 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10160 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10161 "Cannot represent %s relocation in object file",
10162 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10167 /* Turn a string in input_line_pointer into a floating point constant
10168 of type TYPE, and store the appropriate bytes in *LIT. The number
10169 of LITTLENUMS emitted is stored in *SIZE. An error message is
10170 returned, or NULL on OK. */
10172 #define MAX_LITTLENUMS 5
10175 md_atof (type
, lit
, size
)
10180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10181 LITTLENUM_TYPE
*word
;
10211 return "Bad call to MD_ATOF()";
10213 t
= atof_ieee (input_line_pointer
, type
, words
);
10215 input_line_pointer
= t
;
10216 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10218 for (word
= words
+ prec
- 1; prec
--;)
10220 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10221 lit
+= sizeof (LITTLENUM_TYPE
);
10226 /* Round up a section's size to the appropriate boundary. */
10228 md_section_align (seg
, size
)
10232 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10233 valueT mask
= ((valueT
) 1 << align
) - 1;
10235 return (size
+ mask
) & ~mask
;
10238 /* Handle ia64 specific semantics of the align directive. */
10241 ia64_md_do_align (n
, fill
, len
, max
)
10242 int n ATTRIBUTE_UNUSED
;
10243 const char *fill ATTRIBUTE_UNUSED
;
10244 int len ATTRIBUTE_UNUSED
;
10245 int max ATTRIBUTE_UNUSED
;
10247 if (subseg_text_p (now_seg
))
10248 ia64_flush_insns ();
10251 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10252 of an rs_align_code fragment. */
10255 ia64_handle_align (fragp
)
10258 /* Use mfi bundle of nops with no stop bits. */
10259 static const unsigned char be_nop
[]
10260 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10261 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10262 static const unsigned char le_nop
[]
10263 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10264 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10269 if (fragp
->fr_type
!= rs_align_code
)
10272 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10273 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10275 /* Make sure we are on a 16-byte boundary, in case someone has been
10276 putting data into a text section. */
10279 int fix
= bytes
& 15;
10280 memset (p
, 0, fix
);
10283 fragp
->fr_fix
+= fix
;
10286 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10287 fragp
->fr_var
= 16;