1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS
= 0,
68 SPECIAL_SECTION_SDATA
,
69 SPECIAL_SECTION_RODATA
,
70 SPECIAL_SECTION_COMMENT
,
71 SPECIAL_SECTION_UNWIND
,
72 SPECIAL_SECTION_UNWIND_INFO
,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY
,
75 SPECIAL_SECTION_FINI_ARRAY
,
88 FUNC_LT_FPTR_RELATIVE
,
95 REG_FR
= (REG_GR
+ 128),
96 REG_AR
= (REG_FR
+ 128),
97 REG_CR
= (REG_AR
+ 128),
98 REG_P
= (REG_CR
+ 128),
99 REG_BR
= (REG_P
+ 64),
100 REG_IP
= (REG_BR
+ 8),
107 /* The following are pseudo-registers for use by gas only. */
119 /* The following pseudo-registers are used for unwind directives only: */
127 DYNREG_GR
= 0, /* dynamic general purpose register */
128 DYNREG_FR
, /* dynamic floating point register */
129 DYNREG_PR
, /* dynamic predicate register */
133 enum operand_match_result
136 OPERAND_OUT_OF_RANGE
,
140 /* On the ia64, we can't know the address of a text label until the
141 instructions are packed into a bundle. To handle this, we keep
142 track of the list of labels that appear in front of each
146 struct label_fix
*next
;
150 extern int target_big_endian
;
152 /* Characters which always start a comment. */
153 const char comment_chars
[] = "";
155 /* Characters which start a comment at the beginning of a line. */
156 const char line_comment_chars
[] = "#";
158 /* Characters which may be used to separate multiple commands on a
160 const char line_separator_chars
[] = ";";
162 /* Characters which are used to indicate an exponent in a floating
164 const char EXP_CHARS
[] = "eE";
166 /* Characters which mean that a number is a floating point constant,
168 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
170 /* ia64-specific option processing: */
172 const char *md_shortopts
= "m:N:x::";
174 struct option md_longopts
[] =
176 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
177 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
178 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
179 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
182 size_t md_longopts_size
= sizeof (md_longopts
);
186 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
187 struct hash_control
*reg_hash
; /* register name hash table */
188 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
189 struct hash_control
*const_hash
; /* constant hash table */
190 struct hash_control
*entry_hash
; /* code entry hint hash table */
192 symbolS
*regsym
[REG_NUM
];
194 /* If X_op is != O_absent, the registername for the instruction's
195 qualifying predicate. If NULL, p0 is assumed for instructions
196 that are predicatable. */
203 explicit_mode
: 1, /* which mode we're in */
204 default_explicit_mode
: 1, /* which mode is the default */
205 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
207 keep_pending_output
: 1;
209 /* Each bundle consists of up to three instructions. We keep
210 track of four most recent instructions so we can correctly set
211 the end_of_insn_group for the last instruction in a bundle. */
213 int num_slots_in_use
;
217 end_of_insn_group
: 1,
218 manual_bundling_on
: 1,
219 manual_bundling_off
: 1;
220 signed char user_template
; /* user-selected template, if any */
221 unsigned char qp_regno
; /* qualifying predicate */
222 /* This duplicates a good fraction of "struct fix" but we
223 can't use a "struct fix" instead since we can't call
224 fix_new_exp() until we know the address of the instruction. */
228 bfd_reloc_code_real_type code
;
229 enum ia64_opnd opnd
; /* type of operand in need of fix */
230 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
231 expressionS expr
; /* the value to be inserted */
233 fixup
[2]; /* at most two fixups per insn */
234 struct ia64_opcode
*idesc
;
235 struct label_fix
*label_fixups
;
236 struct label_fix
*tag_fixups
;
237 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
240 unsigned int src_line
;
241 struct dwarf2_line_info debug_line
;
249 struct dynreg
*next
; /* next dynamic register */
251 unsigned short base
; /* the base register number */
252 unsigned short num_regs
; /* # of registers in this set */
254 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
256 flagword flags
; /* ELF-header flags */
259 unsigned hint
:1; /* is this hint currently valid? */
260 bfd_vma offset
; /* mem.offset offset */
261 bfd_vma base
; /* mem.offset base */
264 int path
; /* number of alt. entry points seen */
265 const char **entry_labels
; /* labels of all alternate paths in
266 the current DV-checking block. */
267 int maxpaths
; /* size currently allocated for
269 /* Support for hardware errata workarounds. */
271 /* Record data about the last three insn groups. */
274 /* B-step workaround.
275 For each predicate register, this is set if the corresponding insn
276 group conditionally sets this register with one of the affected
279 /* B-step workaround.
280 For each general register, this is set if the corresponding insn
281 a) is conditional one one of the predicate registers for which
282 P_REG_SET is 1 in the corresponding entry of the previous group,
283 b) sets this general register with one of the affected
285 int g_reg_set_conditionally
[128];
289 int pointer_size
; /* size in bytes of a pointer */
290 int pointer_size_shift
; /* shift size of a pointer for alignment */
294 /* application registers: */
300 #define AR_BSPSTORE 18
315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
317 {"ar.rsc", 16}, {"ar.bsp", 17},
318 {"ar.bspstore", 18}, {"ar.rnat", 19},
319 {"ar.fcr", 21}, {"ar.eflag", 24},
320 {"ar.csd", 25}, {"ar.ssd", 26},
321 {"ar.cflg", 27}, {"ar.fsr", 28},
322 {"ar.fir", 29}, {"ar.fdr", 30},
323 {"ar.ccv", 32}, {"ar.unat", 36},
324 {"ar.fpsr", 40}, {"ar.itc", 44},
325 {"ar.pfs", 64}, {"ar.lc", 65},
346 /* control registers: */
388 static const struct const_desc
395 /* PSR constant masks: */
398 {"psr.be", ((valueT
) 1) << 1},
399 {"psr.up", ((valueT
) 1) << 2},
400 {"psr.ac", ((valueT
) 1) << 3},
401 {"psr.mfl", ((valueT
) 1) << 4},
402 {"psr.mfh", ((valueT
) 1) << 5},
404 {"psr.ic", ((valueT
) 1) << 13},
405 {"psr.i", ((valueT
) 1) << 14},
406 {"psr.pk", ((valueT
) 1) << 15},
408 {"psr.dt", ((valueT
) 1) << 17},
409 {"psr.dfl", ((valueT
) 1) << 18},
410 {"psr.dfh", ((valueT
) 1) << 19},
411 {"psr.sp", ((valueT
) 1) << 20},
412 {"psr.pp", ((valueT
) 1) << 21},
413 {"psr.di", ((valueT
) 1) << 22},
414 {"psr.si", ((valueT
) 1) << 23},
415 {"psr.db", ((valueT
) 1) << 24},
416 {"psr.lp", ((valueT
) 1) << 25},
417 {"psr.tb", ((valueT
) 1) << 26},
418 {"psr.rt", ((valueT
) 1) << 27},
419 /* 28-31: reserved */
420 /* 32-33: cpl (current privilege level) */
421 {"psr.is", ((valueT
) 1) << 34},
422 {"psr.mc", ((valueT
) 1) << 35},
423 {"psr.it", ((valueT
) 1) << 36},
424 {"psr.id", ((valueT
) 1) << 37},
425 {"psr.da", ((valueT
) 1) << 38},
426 {"psr.dd", ((valueT
) 1) << 39},
427 {"psr.ss", ((valueT
) 1) << 40},
428 /* 41-42: ri (restart instruction) */
429 {"psr.ed", ((valueT
) 1) << 43},
430 {"psr.bn", ((valueT
) 1) << 44},
433 /* indirect register-sets/memory: */
442 { "CPUID", IND_CPUID
},
443 { "cpuid", IND_CPUID
},
455 /* Pseudo functions used to indicate relocation types (these functions
456 start with an at sign (@). */
478 /* reloc pseudo functions (these must come first!): */
479 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
480 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
481 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
482 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
483 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
484 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
485 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
486 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
488 { "iplt", PSEUDO_FUNC_RELOC
, { 0 } },
490 /* mbtype4 constants: */
491 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
492 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
493 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
494 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
495 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
497 /* fclass constants: */
498 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
499 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
500 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
501 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
502 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
503 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
504 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
505 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
506 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
508 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
510 /* unwind-related constants: */
511 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
512 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
513 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
515 /* unwind-related registers: */
516 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
519 /* 41-bit nop opcodes (one per unit): */
520 static const bfd_vma nop
[IA64_NUM_UNITS
] =
522 0x0000000000LL
, /* NIL => break 0 */
523 0x0008000000LL
, /* I-unit nop */
524 0x0008000000LL
, /* M-unit nop */
525 0x4000000000LL
, /* B-unit nop */
526 0x0008000000LL
, /* F-unit nop */
527 0x0008000000LL
, /* L-"unit" nop */
528 0x0008000000LL
, /* X-unit nop */
531 /* Can't be `const' as it's passed to input routines (which have the
532 habit of setting temporary sentinels. */
533 static char special_section_name
[][20] =
535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
536 {".IA_64.unwind"}, {".IA_64.unwind_info"},
537 {".init_array"}, {".fini_array"}
540 static char *special_linkonce_name
[] =
542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
545 /* The best template for a particular sequence of up to three
547 #define N IA64_NUM_TYPES
548 static unsigned char best_template
[N
][N
][N
];
551 /* Resource dependencies currently in effect */
553 int depind
; /* dependency index */
554 const struct ia64_dependency
*dependency
; /* actual dependency */
555 unsigned specific
:1, /* is this a specific bit/regno? */
556 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
557 int index
; /* specific regno/bit within dependency */
558 int note
; /* optional qualifying note (0 if none) */
562 int insn_srlz
; /* current insn serialization state */
563 int data_srlz
; /* current data serialization state */
564 int qp_regno
; /* qualifying predicate for this usage */
565 char *file
; /* what file marked this dependency */
566 unsigned int line
; /* what line marked this dependency */
567 struct mem_offset mem_offset
; /* optional memory offset hint */
568 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
569 int path
; /* corresponding code entry index */
571 static int regdepslen
= 0;
572 static int regdepstotlen
= 0;
573 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
574 static const char *dv_sem
[] = { "none", "implied", "impliedf",
575 "data", "instr", "specific", "stop", "other" };
576 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
578 /* Current state of PR mutexation */
579 static struct qpmutex
{
582 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
583 static int qp_mutexeslen
= 0;
584 static int qp_mutexestotlen
= 0;
585 static valueT qp_safe_across_calls
= 0;
587 /* Current state of PR implications */
588 static struct qp_imply
{
591 unsigned p2_branched
:1;
593 } *qp_implies
= NULL
;
594 static int qp_implieslen
= 0;
595 static int qp_impliestotlen
= 0;
597 /* Keep track of static GR values so that indirect register usage can
598 sometimes be tracked. */
603 } gr_values
[128] = {{ 1, 0, 0 }};
605 /* These are the routines required to output the various types of
608 /* A slot_number is a frag address plus the slot index (0-2). We use the
609 frag address here so that if there is a section switch in the middle of
610 a function, then instructions emitted to a different section are not
611 counted. Since there may be more than one frag for a function, this
612 means we also need to keep track of which frag this address belongs to
613 so we can compute inter-frag distances. This also nicely solves the
614 problem with nops emitted for align directives, which can't easily be
615 counted, but can easily be derived from frag sizes. */
617 typedef struct unw_rec_list
{
619 unsigned long slot_number
;
621 struct unw_rec_list
*next
;
624 #define SLOT_NUM_NOT_SET (unsigned)-1
628 unsigned long next_slot_number
;
629 fragS
*next_slot_frag
;
631 /* Maintain a list of unwind entries for the current function. */
635 /* Any unwind entires that should be attached to the current slot
636 that an insn is being constructed for. */
637 unw_rec_list
*current_entry
;
639 /* These are used to create the unwind table entry for this function. */
642 symbolS
*info
; /* pointer to unwind info */
643 symbolS
*personality_routine
;
645 subsegT saved_text_subseg
;
646 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
648 /* TRUE if processing unwind directives in a prologue region. */
651 unsigned int prologue_count
; /* number of .prologues seen so far */
654 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
656 /* Forward delarations: */
657 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
658 static void set_section
PARAMS ((char *name
));
659 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
660 unsigned int, unsigned int));
661 static void dot_radix
PARAMS ((int));
662 static void dot_special_section
PARAMS ((int));
663 static void dot_proc
PARAMS ((int));
664 static void dot_fframe
PARAMS ((int));
665 static void dot_vframe
PARAMS ((int));
666 static void dot_vframesp
PARAMS ((int));
667 static void dot_vframepsp
PARAMS ((int));
668 static void dot_save
PARAMS ((int));
669 static void dot_restore
PARAMS ((int));
670 static void dot_restorereg
PARAMS ((int));
671 static void dot_restorereg_p
PARAMS ((int));
672 static void dot_handlerdata
PARAMS ((int));
673 static void dot_unwentry
PARAMS ((int));
674 static void dot_altrp
PARAMS ((int));
675 static void dot_savemem
PARAMS ((int));
676 static void dot_saveg
PARAMS ((int));
677 static void dot_savef
PARAMS ((int));
678 static void dot_saveb
PARAMS ((int));
679 static void dot_savegf
PARAMS ((int));
680 static void dot_spill
PARAMS ((int));
681 static void dot_spillreg
PARAMS ((int));
682 static void dot_spillmem
PARAMS ((int));
683 static void dot_spillreg_p
PARAMS ((int));
684 static void dot_spillmem_p
PARAMS ((int));
685 static void dot_label_state
PARAMS ((int));
686 static void dot_copy_state
PARAMS ((int));
687 static void dot_unwabi
PARAMS ((int));
688 static void dot_personality
PARAMS ((int));
689 static void dot_body
PARAMS ((int));
690 static void dot_prologue
PARAMS ((int));
691 static void dot_endp
PARAMS ((int));
692 static void dot_template
PARAMS ((int));
693 static void dot_regstk
PARAMS ((int));
694 static void dot_rot
PARAMS ((int));
695 static void dot_byteorder
PARAMS ((int));
696 static void dot_psr
PARAMS ((int));
697 static void dot_alias
PARAMS ((int));
698 static void dot_ln
PARAMS ((int));
699 static char *parse_section_name
PARAMS ((void));
700 static void dot_xdata
PARAMS ((int));
701 static void stmt_float_cons
PARAMS ((int));
702 static void stmt_cons_ua
PARAMS ((int));
703 static void dot_xfloat_cons
PARAMS ((int));
704 static void dot_xstringer
PARAMS ((int));
705 static void dot_xdata_ua
PARAMS ((int));
706 static void dot_xfloat_cons_ua
PARAMS ((int));
707 static void print_prmask
PARAMS ((valueT mask
));
708 static void dot_pred_rel
PARAMS ((int));
709 static void dot_reg_val
PARAMS ((int));
710 static void dot_dv_mode
PARAMS ((int));
711 static void dot_entry
PARAMS ((int));
712 static void dot_mem_offset
PARAMS ((int));
713 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
714 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
715 static void declare_register_set
PARAMS ((const char *, int, int));
716 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
717 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
720 static int parse_operand
PARAMS ((expressionS
*e
));
721 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
722 static int errata_nop_necessary_p
PARAMS ((struct slot
*, enum ia64_unit
));
723 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
724 static void emit_one_bundle
PARAMS ((void));
725 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
726 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
727 bfd_reloc_code_real_type r_type
));
728 static void insn_group_break
PARAMS ((int, int, int));
729 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
730 struct rsrc
*, int depind
, int path
));
731 static void add_qp_mutex
PARAMS((valueT mask
));
732 static void add_qp_imply
PARAMS((int p1
, int p2
));
733 static void clear_qp_branch_flag
PARAMS((valueT mask
));
734 static void clear_qp_mutex
PARAMS((valueT mask
));
735 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
736 static void clear_register_values
PARAMS ((void));
737 static void print_dependency
PARAMS ((const char *action
, int depind
));
738 static void instruction_serialization
PARAMS ((void));
739 static void data_serialization
PARAMS ((void));
740 static void remove_marked_resource
PARAMS ((struct rsrc
*));
741 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
742 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
743 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
744 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
745 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
746 struct ia64_opcode
*, int, struct rsrc
[], int, int));
747 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
748 static void check_dependencies
PARAMS((struct ia64_opcode
*));
749 static void mark_resources
PARAMS((struct ia64_opcode
*));
750 static void update_dependencies
PARAMS((struct ia64_opcode
*));
751 static void note_register_values
PARAMS((struct ia64_opcode
*));
752 static int qp_mutex
PARAMS ((int, int, int));
753 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
754 static void output_vbyte_mem
PARAMS ((int, char *, char *));
755 static void count_output
PARAMS ((int, char *, char *));
756 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
757 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
758 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
759 static void output_P1_format
PARAMS ((vbyte_func
, int));
760 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
761 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
762 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
763 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
764 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
765 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
766 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
767 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
768 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
769 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
770 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
771 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
772 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
773 static char format_ab_reg
PARAMS ((int, int));
774 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
776 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
777 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
779 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
780 static void free_list_records
PARAMS ((unw_rec_list
*));
781 static unw_rec_list
*output_prologue
PARAMS ((void));
782 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
783 static unw_rec_list
*output_body
PARAMS ((void));
784 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
785 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
786 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
787 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
788 static unw_rec_list
*output_rp_when
PARAMS ((void));
789 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
790 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
791 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
792 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_pfs_when
PARAMS ((void));
794 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
795 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
796 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
797 static unw_rec_list
*output_preds_when
PARAMS ((void));
798 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
799 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
800 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
801 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
802 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
803 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
804 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
805 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
806 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
807 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
808 static unw_rec_list
*output_unat_when
PARAMS ((void));
809 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
810 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
812 static unw_rec_list
*output_lc_when
PARAMS ((void));
813 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
814 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
816 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
817 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
818 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
819 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
820 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
821 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
822 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
823 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
825 static unw_rec_list
*output_bsp_when
PARAMS ((void));
826 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
827 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
829 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
830 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
831 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
832 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
833 static unw_rec_list
*output_rnat_when
PARAMS ((void));
834 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
835 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
836 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
837 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
838 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
839 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
840 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
841 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
842 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
843 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
845 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
847 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
849 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
850 unsigned int, unsigned int));
851 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
852 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
853 static int calc_record_size
PARAMS ((unw_rec_list
*));
854 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
855 static int count_bits
PARAMS ((unsigned long));
856 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
857 unsigned long, fragS
*));
858 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
859 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
860 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
861 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
862 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
863 static int generate_unwind_image
PARAMS ((const char *));
865 /* Build the unwind section name by appending the (possibly stripped)
866 text section NAME to the unwind PREFIX. The resulting string
867 pointer is assigned to RESULT. The string is allocated on the
868 stack, so this must be a macro... */
869 #define make_unw_section_name(special, text_name, result) \
871 const char *_prefix = special_section_name[special]; \
872 const char *_suffix = text_name; \
873 size_t _prefix_len, _suffix_len; \
875 if (strncmp (text_name, ".gnu.linkonce.t.", \
876 sizeof (".gnu.linkonce.t.") - 1) == 0) \
878 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
879 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
881 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
882 _result = alloca (_prefix_len + _suffix_len + 1); \
883 memcpy (_result, _prefix, _prefix_len); \
884 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
885 _result[_prefix_len + _suffix_len] = '\0'; \
890 /* Determine if application register REGNUM resides in the integer
891 unit (as opposed to the memory unit). */
893 ar_is_in_integer_unit (reg
)
898 return (reg
== 64 /* pfs */
899 || reg
== 65 /* lc */
900 || reg
== 66 /* ec */
901 /* ??? ias accepts and puts these in the integer unit. */
902 || (reg
>= 112 && reg
<= 127));
905 /* Switch to section NAME and create section if necessary. It's
906 rather ugly that we have to manipulate input_line_pointer but I
907 don't see any other way to accomplish the same thing without
908 changing obj-elf.c (which may be the Right Thing, in the end). */
913 char *saved_input_line_pointer
;
915 saved_input_line_pointer
= input_line_pointer
;
916 input_line_pointer
= name
;
918 input_line_pointer
= saved_input_line_pointer
;
921 /* Map 's' to SHF_IA_64_SHORT. */
924 ia64_elf_section_letter (letter
, ptr_msg
)
929 return SHF_IA_64_SHORT
;
931 *ptr_msg
= _("Bad .section directive: want a,s,w,x,M,S in string");
935 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
938 ia64_elf_section_flags (flags
, attr
, type
)
940 int attr
, type ATTRIBUTE_UNUSED
;
942 if (attr
& SHF_IA_64_SHORT
)
943 flags
|= SEC_SMALL_DATA
;
948 ia64_elf_section_type (str
, len
)
952 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
953 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
956 len
= sizeof (ELF_STRING_ia64_unwind_info_once
) - 1;
957 if (strncmp (str
, ELF_STRING_ia64_unwind_info_once
, len
) == 0)
960 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
961 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
962 return SHT_IA_64_UNWIND
;
964 len
= sizeof (ELF_STRING_ia64_unwind_once
) - 1;
965 if (strncmp (str
, ELF_STRING_ia64_unwind_once
, len
) == 0)
966 return SHT_IA_64_UNWIND
;
972 set_regstack (ins
, locs
, outs
, rots
)
973 unsigned int ins
, locs
, outs
, rots
;
978 sof
= ins
+ locs
+ outs
;
981 as_bad ("Size of frame exceeds maximum of 96 registers");
986 as_warn ("Size of rotating registers exceeds frame size");
989 md
.in
.base
= REG_GR
+ 32;
990 md
.loc
.base
= md
.in
.base
+ ins
;
991 md
.out
.base
= md
.loc
.base
+ locs
;
993 md
.in
.num_regs
= ins
;
994 md
.loc
.num_regs
= locs
;
995 md
.out
.num_regs
= outs
;
996 md
.rot
.num_regs
= rots
;
1003 struct label_fix
*lfix
;
1005 subsegT saved_subseg
;
1008 if (!md
.last_text_seg
)
1011 saved_seg
= now_seg
;
1012 saved_subseg
= now_subseg
;
1014 subseg_set (md
.last_text_seg
, 0);
1016 while (md
.num_slots_in_use
> 0)
1017 emit_one_bundle (); /* force out queued instructions */
1019 /* In case there are labels following the last instruction, resolve
1021 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1023 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1024 symbol_set_frag (lfix
->sym
, frag_now
);
1026 CURR_SLOT
.label_fixups
= 0;
1027 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1029 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1030 symbol_set_frag (lfix
->sym
, frag_now
);
1032 CURR_SLOT
.tag_fixups
= 0;
1034 /* In case there are unwind directives following the last instruction,
1035 resolve those now. We only handle body and prologue directives here.
1036 Give an error for others. */
1037 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1039 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1040 || ptr
->r
.type
== body
)
1042 ptr
->slot_number
= (unsigned long) frag_more (0);
1043 ptr
->slot_frag
= frag_now
;
1046 as_bad (_("Unwind directive not followed by an instruction."));
1048 unwind
.current_entry
= NULL
;
1050 subseg_set (saved_seg
, saved_subseg
);
1052 if (md
.qp
.X_op
== O_register
)
1053 as_bad ("qualifying predicate not followed by instruction");
1057 ia64_do_align (nbytes
)
1060 char *saved_input_line_pointer
= input_line_pointer
;
1062 input_line_pointer
= "";
1063 s_align_bytes (nbytes
);
1064 input_line_pointer
= saved_input_line_pointer
;
1068 ia64_cons_align (nbytes
)
1073 char *saved_input_line_pointer
= input_line_pointer
;
1074 input_line_pointer
= "";
1075 s_align_bytes (nbytes
);
1076 input_line_pointer
= saved_input_line_pointer
;
1080 /* Output COUNT bytes to a memory location. */
1081 static unsigned char *vbyte_mem_ptr
= NULL
;
1084 output_vbyte_mem (count
, ptr
, comment
)
1087 char *comment ATTRIBUTE_UNUSED
;
1090 if (vbyte_mem_ptr
== NULL
)
1095 for (x
= 0; x
< count
; x
++)
1096 *(vbyte_mem_ptr
++) = ptr
[x
];
1099 /* Count the number of bytes required for records. */
1100 static int vbyte_count
= 0;
1102 count_output (count
, ptr
, comment
)
1104 char *ptr ATTRIBUTE_UNUSED
;
1105 char *comment ATTRIBUTE_UNUSED
;
1107 vbyte_count
+= count
;
1111 output_R1_format (f
, rtype
, rlen
)
1113 unw_record_type rtype
;
1120 output_R3_format (f
, rtype
, rlen
);
1126 else if (rtype
!= prologue
)
1127 as_bad ("record type is not valid");
1129 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1130 (*f
) (1, &byte
, NULL
);
1134 output_R2_format (f
, mask
, grsave
, rlen
)
1141 mask
= (mask
& 0x0f);
1142 grsave
= (grsave
& 0x7f);
1144 bytes
[0] = (UNW_R2
| (mask
>> 1));
1145 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1146 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1147 (*f
) (count
, bytes
, NULL
);
1151 output_R3_format (f
, rtype
, rlen
)
1153 unw_record_type rtype
;
1160 output_R1_format (f
, rtype
, rlen
);
1166 else if (rtype
!= prologue
)
1167 as_bad ("record type is not valid");
1168 bytes
[0] = (UNW_R3
| r
);
1169 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1170 (*f
) (count
+ 1, bytes
, NULL
);
1174 output_P1_format (f
, brmask
)
1179 byte
= UNW_P1
| (brmask
& 0x1f);
1180 (*f
) (1, &byte
, NULL
);
1184 output_P2_format (f
, brmask
, gr
)
1190 brmask
= (brmask
& 0x1f);
1191 bytes
[0] = UNW_P2
| (brmask
>> 1);
1192 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1193 (*f
) (2, bytes
, NULL
);
1197 output_P3_format (f
, rtype
, reg
)
1199 unw_record_type rtype
;
1244 as_bad ("Invalid record type for P3 format.");
1246 bytes
[0] = (UNW_P3
| (r
>> 1));
1247 bytes
[1] = (((r
& 1) << 7) | reg
);
1248 (*f
) (2, bytes
, NULL
);
1252 output_P4_format (f
, imask
, imask_size
)
1254 unsigned char *imask
;
1255 unsigned long imask_size
;
1258 (*f
) (imask_size
, imask
, NULL
);
1262 output_P5_format (f
, grmask
, frmask
)
1265 unsigned long frmask
;
1268 grmask
= (grmask
& 0x0f);
1271 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1272 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1273 bytes
[3] = (frmask
& 0x000000ff);
1274 (*f
) (4, bytes
, NULL
);
1278 output_P6_format (f
, rtype
, rmask
)
1280 unw_record_type rtype
;
1286 if (rtype
== gr_mem
)
1288 else if (rtype
!= fr_mem
)
1289 as_bad ("Invalid record type for format P6");
1290 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1291 (*f
) (1, &byte
, NULL
);
1295 output_P7_format (f
, rtype
, w1
, w2
)
1297 unw_record_type rtype
;
1304 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1309 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1359 bytes
[0] = (UNW_P7
| r
);
1360 (*f
) (count
, bytes
, NULL
);
1364 output_P8_format (f
, rtype
, t
)
1366 unw_record_type rtype
;
1405 case bspstore_psprel
:
1408 case bspstore_sprel
:
1420 case priunat_when_gr
:
1423 case priunat_psprel
:
1429 case priunat_when_mem
:
1436 count
+= output_leb128 (bytes
+ 2, t
, 0);
1437 (*f
) (count
, bytes
, NULL
);
1441 output_P9_format (f
, grmask
, gr
)
1448 bytes
[1] = (grmask
& 0x0f);
1449 bytes
[2] = (gr
& 0x7f);
1450 (*f
) (3, bytes
, NULL
);
1454 output_P10_format (f
, abi
, context
)
1461 bytes
[1] = (abi
& 0xff);
1462 bytes
[2] = (context
& 0xff);
1463 (*f
) (3, bytes
, NULL
);
1467 output_B1_format (f
, rtype
, label
)
1469 unw_record_type rtype
;
1470 unsigned long label
;
1476 output_B4_format (f
, rtype
, label
);
1479 if (rtype
== copy_state
)
1481 else if (rtype
!= label_state
)
1482 as_bad ("Invalid record type for format B1");
1484 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1485 (*f
) (1, &byte
, NULL
);
1489 output_B2_format (f
, ecount
, t
)
1491 unsigned long ecount
;
1498 output_B3_format (f
, ecount
, t
);
1501 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1502 count
+= output_leb128 (bytes
+ 1, t
, 0);
1503 (*f
) (count
, bytes
, NULL
);
1507 output_B3_format (f
, ecount
, t
)
1509 unsigned long ecount
;
1516 output_B2_format (f
, ecount
, t
);
1520 count
+= output_leb128 (bytes
+ 1, t
, 0);
1521 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1522 (*f
) (count
, bytes
, NULL
);
1526 output_B4_format (f
, rtype
, label
)
1528 unw_record_type rtype
;
1529 unsigned long label
;
1536 output_B1_format (f
, rtype
, label
);
1540 if (rtype
== copy_state
)
1542 else if (rtype
!= label_state
)
1543 as_bad ("Invalid record type for format B1");
1545 bytes
[0] = (UNW_B4
| (r
<< 3));
1546 count
+= output_leb128 (bytes
+ 1, label
, 0);
1547 (*f
) (count
, bytes
, NULL
);
1551 format_ab_reg (ab
, reg
)
1558 ret
= (ab
<< 5) | reg
;
1563 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1565 unw_record_type rtype
;
1575 if (rtype
== spill_sprel
)
1577 else if (rtype
!= spill_psprel
)
1578 as_bad ("Invalid record type for format X1");
1579 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1580 count
+= output_leb128 (bytes
+ 2, t
, 0);
1581 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1582 (*f
) (count
, bytes
, NULL
);
1586 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1595 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1596 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1597 count
+= output_leb128 (bytes
+ 3, t
, 0);
1598 (*f
) (count
, bytes
, NULL
);
1602 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1604 unw_record_type rtype
;
1615 if (rtype
== spill_sprel_p
)
1617 else if (rtype
!= spill_psprel_p
)
1618 as_bad ("Invalid record type for format X3");
1619 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1620 bytes
[2] = format_ab_reg (ab
, reg
);
1621 count
+= output_leb128 (bytes
+ 3, t
, 0);
1622 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1623 (*f
) (count
, bytes
, NULL
);
1627 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1637 bytes
[1] = (qp
& 0x3f);
1638 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1639 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1640 count
+= output_leb128 (bytes
+ 4, t
, 0);
1641 (*f
) (count
, bytes
, NULL
);
1644 /* This function allocates a record list structure, and initializes fields. */
1646 static unw_rec_list
*
1647 alloc_record (unw_record_type t
)
1650 ptr
= xmalloc (sizeof (*ptr
));
1652 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1657 /* This function frees an entire list of record structures. */
1660 free_list_records (unw_rec_list
*first
)
1663 for (ptr
= first
; ptr
!= NULL
;)
1665 unw_rec_list
*tmp
= ptr
;
1667 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1668 && tmp
->r
.record
.r
.mask
.i
)
1669 free (tmp
->r
.record
.r
.mask
.i
);
1676 static unw_rec_list
*
1679 unw_rec_list
*ptr
= alloc_record (prologue
);
1680 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1684 static unw_rec_list
*
1685 output_prologue_gr (saved_mask
, reg
)
1686 unsigned int saved_mask
;
1689 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1690 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1691 ptr
->r
.record
.r
.grmask
= saved_mask
;
1692 ptr
->r
.record
.r
.grsave
= reg
;
1696 static unw_rec_list
*
1699 unw_rec_list
*ptr
= alloc_record (body
);
1703 static unw_rec_list
*
1704 output_mem_stack_f (size
)
1707 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1708 ptr
->r
.record
.p
.size
= size
;
1712 static unw_rec_list
*
1713 output_mem_stack_v ()
1715 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1719 static unw_rec_list
*
1723 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1724 ptr
->r
.record
.p
.gr
= gr
;
1728 static unw_rec_list
*
1729 output_psp_sprel (offset
)
1730 unsigned int offset
;
1732 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1733 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1737 static unw_rec_list
*
1740 unw_rec_list
*ptr
= alloc_record (rp_when
);
1744 static unw_rec_list
*
1748 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1749 ptr
->r
.record
.p
.gr
= gr
;
1753 static unw_rec_list
*
1757 unw_rec_list
*ptr
= alloc_record (rp_br
);
1758 ptr
->r
.record
.p
.br
= br
;
1762 static unw_rec_list
*
1763 output_rp_psprel (offset
)
1764 unsigned int offset
;
1766 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1767 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1771 static unw_rec_list
*
1772 output_rp_sprel (offset
)
1773 unsigned int offset
;
1775 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1776 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1780 static unw_rec_list
*
1783 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1787 static unw_rec_list
*
1791 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1792 ptr
->r
.record
.p
.gr
= gr
;
1796 static unw_rec_list
*
1797 output_pfs_psprel (offset
)
1798 unsigned int offset
;
1800 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1801 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1805 static unw_rec_list
*
1806 output_pfs_sprel (offset
)
1807 unsigned int offset
;
1809 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1810 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1814 static unw_rec_list
*
1815 output_preds_when ()
1817 unw_rec_list
*ptr
= alloc_record (preds_when
);
1821 static unw_rec_list
*
1822 output_preds_gr (gr
)
1825 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1826 ptr
->r
.record
.p
.gr
= gr
;
1830 static unw_rec_list
*
1831 output_preds_psprel (offset
)
1832 unsigned int offset
;
1834 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1835 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1839 static unw_rec_list
*
1840 output_preds_sprel (offset
)
1841 unsigned int offset
;
1843 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1844 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1848 static unw_rec_list
*
1849 output_fr_mem (mask
)
1852 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1853 ptr
->r
.record
.p
.rmask
= mask
;
1857 static unw_rec_list
*
1858 output_frgr_mem (gr_mask
, fr_mask
)
1859 unsigned int gr_mask
;
1860 unsigned int fr_mask
;
1862 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1863 ptr
->r
.record
.p
.grmask
= gr_mask
;
1864 ptr
->r
.record
.p
.frmask
= fr_mask
;
1868 static unw_rec_list
*
1869 output_gr_gr (mask
, reg
)
1873 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1874 ptr
->r
.record
.p
.grmask
= mask
;
1875 ptr
->r
.record
.p
.gr
= reg
;
1879 static unw_rec_list
*
1880 output_gr_mem (mask
)
1883 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1884 ptr
->r
.record
.p
.rmask
= mask
;
1888 static unw_rec_list
*
1889 output_br_mem (unsigned int mask
)
1891 unw_rec_list
*ptr
= alloc_record (br_mem
);
1892 ptr
->r
.record
.p
.brmask
= mask
;
1896 static unw_rec_list
*
1897 output_br_gr (save_mask
, reg
)
1898 unsigned int save_mask
;
1901 unw_rec_list
*ptr
= alloc_record (br_gr
);
1902 ptr
->r
.record
.p
.brmask
= save_mask
;
1903 ptr
->r
.record
.p
.gr
= reg
;
1907 static unw_rec_list
*
1908 output_spill_base (offset
)
1909 unsigned int offset
;
1911 unw_rec_list
*ptr
= alloc_record (spill_base
);
1912 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1916 static unw_rec_list
*
1919 unw_rec_list
*ptr
= alloc_record (unat_when
);
1923 static unw_rec_list
*
1927 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1928 ptr
->r
.record
.p
.gr
= gr
;
1932 static unw_rec_list
*
1933 output_unat_psprel (offset
)
1934 unsigned int offset
;
1936 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1937 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1941 static unw_rec_list
*
1942 output_unat_sprel (offset
)
1943 unsigned int offset
;
1945 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1946 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1950 static unw_rec_list
*
1953 unw_rec_list
*ptr
= alloc_record (lc_when
);
1957 static unw_rec_list
*
1961 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1962 ptr
->r
.record
.p
.gr
= gr
;
1966 static unw_rec_list
*
1967 output_lc_psprel (offset
)
1968 unsigned int offset
;
1970 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1971 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1975 static unw_rec_list
*
1976 output_lc_sprel (offset
)
1977 unsigned int offset
;
1979 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1980 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1984 static unw_rec_list
*
1987 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1991 static unw_rec_list
*
1995 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1996 ptr
->r
.record
.p
.gr
= gr
;
2000 static unw_rec_list
*
2001 output_fpsr_psprel (offset
)
2002 unsigned int offset
;
2004 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
2005 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2009 static unw_rec_list
*
2010 output_fpsr_sprel (offset
)
2011 unsigned int offset
;
2013 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
2014 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2018 static unw_rec_list
*
2019 output_priunat_when_gr ()
2021 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2025 static unw_rec_list
*
2026 output_priunat_when_mem ()
2028 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2032 static unw_rec_list
*
2033 output_priunat_gr (gr
)
2036 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2037 ptr
->r
.record
.p
.gr
= gr
;
2041 static unw_rec_list
*
2042 output_priunat_psprel (offset
)
2043 unsigned int offset
;
2045 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2046 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2050 static unw_rec_list
*
2051 output_priunat_sprel (offset
)
2052 unsigned int offset
;
2054 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2055 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2059 static unw_rec_list
*
2062 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2066 static unw_rec_list
*
2070 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2071 ptr
->r
.record
.p
.gr
= gr
;
2075 static unw_rec_list
*
2076 output_bsp_psprel (offset
)
2077 unsigned int offset
;
2079 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2080 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2084 static unw_rec_list
*
2085 output_bsp_sprel (offset
)
2086 unsigned int offset
;
2088 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2089 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2093 static unw_rec_list
*
2094 output_bspstore_when ()
2096 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2100 static unw_rec_list
*
2101 output_bspstore_gr (gr
)
2104 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2105 ptr
->r
.record
.p
.gr
= gr
;
2109 static unw_rec_list
*
2110 output_bspstore_psprel (offset
)
2111 unsigned int offset
;
2113 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2114 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2118 static unw_rec_list
*
2119 output_bspstore_sprel (offset
)
2120 unsigned int offset
;
2122 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2123 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2127 static unw_rec_list
*
2130 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2134 static unw_rec_list
*
2138 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2139 ptr
->r
.record
.p
.gr
= gr
;
2143 static unw_rec_list
*
2144 output_rnat_psprel (offset
)
2145 unsigned int offset
;
2147 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2148 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2152 static unw_rec_list
*
2153 output_rnat_sprel (offset
)
2154 unsigned int offset
;
2156 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2157 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2161 static unw_rec_list
*
2162 output_unwabi (abi
, context
)
2164 unsigned long context
;
2166 unw_rec_list
*ptr
= alloc_record (unwabi
);
2167 ptr
->r
.record
.p
.abi
= abi
;
2168 ptr
->r
.record
.p
.context
= context
;
2172 static unw_rec_list
*
2173 output_epilogue (unsigned long ecount
)
2175 unw_rec_list
*ptr
= alloc_record (epilogue
);
2176 ptr
->r
.record
.b
.ecount
= ecount
;
2180 static unw_rec_list
*
2181 output_label_state (unsigned long label
)
2183 unw_rec_list
*ptr
= alloc_record (label_state
);
2184 ptr
->r
.record
.b
.label
= label
;
2188 static unw_rec_list
*
2189 output_copy_state (unsigned long label
)
2191 unw_rec_list
*ptr
= alloc_record (copy_state
);
2192 ptr
->r
.record
.b
.label
= label
;
2196 static unw_rec_list
*
2197 output_spill_psprel (ab
, reg
, offset
)
2200 unsigned int offset
;
2202 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2203 ptr
->r
.record
.x
.ab
= ab
;
2204 ptr
->r
.record
.x
.reg
= reg
;
2205 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2209 static unw_rec_list
*
2210 output_spill_sprel (ab
, reg
, offset
)
2213 unsigned int offset
;
2215 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2216 ptr
->r
.record
.x
.ab
= ab
;
2217 ptr
->r
.record
.x
.reg
= reg
;
2218 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2222 static unw_rec_list
*
2223 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2226 unsigned int offset
;
2227 unsigned int predicate
;
2229 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2230 ptr
->r
.record
.x
.ab
= ab
;
2231 ptr
->r
.record
.x
.reg
= reg
;
2232 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2233 ptr
->r
.record
.x
.qp
= predicate
;
2237 static unw_rec_list
*
2238 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2241 unsigned int offset
;
2242 unsigned int predicate
;
2244 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2245 ptr
->r
.record
.x
.ab
= ab
;
2246 ptr
->r
.record
.x
.reg
= reg
;
2247 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2248 ptr
->r
.record
.x
.qp
= predicate
;
2252 static unw_rec_list
*
2253 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2256 unsigned int targ_reg
;
2259 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2260 ptr
->r
.record
.x
.ab
= ab
;
2261 ptr
->r
.record
.x
.reg
= reg
;
2262 ptr
->r
.record
.x
.treg
= targ_reg
;
2263 ptr
->r
.record
.x
.xy
= xy
;
2267 static unw_rec_list
*
2268 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2271 unsigned int targ_reg
;
2273 unsigned int predicate
;
2275 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2276 ptr
->r
.record
.x
.ab
= ab
;
2277 ptr
->r
.record
.x
.reg
= reg
;
2278 ptr
->r
.record
.x
.treg
= targ_reg
;
2279 ptr
->r
.record
.x
.xy
= xy
;
2280 ptr
->r
.record
.x
.qp
= predicate
;
2284 /* Given a unw_rec_list process the correct format with the
2285 specified function. */
2288 process_one_record (ptr
, f
)
2292 unsigned long fr_mask
, gr_mask
;
2294 switch (ptr
->r
.type
)
2300 /* These are taken care of by prologue/prologue_gr. */
2305 if (ptr
->r
.type
== prologue_gr
)
2306 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2307 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2309 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2311 /* Output descriptor(s) for union of register spills (if any). */
2312 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2313 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2316 if ((fr_mask
& ~0xfUL
) == 0)
2317 output_P6_format (f
, fr_mem
, fr_mask
);
2320 output_P5_format (f
, gr_mask
, fr_mask
);
2325 output_P6_format (f
, gr_mem
, gr_mask
);
2326 if (ptr
->r
.record
.r
.mask
.br_mem
)
2327 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2329 /* output imask descriptor if necessary: */
2330 if (ptr
->r
.record
.r
.mask
.i
)
2331 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2332 ptr
->r
.record
.r
.imask_size
);
2336 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2340 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2341 ptr
->r
.record
.p
.size
);
2354 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2357 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2360 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2368 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2377 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2387 case bspstore_sprel
:
2389 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2392 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2395 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2398 as_bad ("spill_mask record unimplemented.");
2400 case priunat_when_gr
:
2401 case priunat_when_mem
:
2405 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2407 case priunat_psprel
:
2409 case bspstore_psprel
:
2411 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2414 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2417 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2421 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2424 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2425 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2426 ptr
->r
.record
.x
.pspoff
);
2429 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2430 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2431 ptr
->r
.record
.x
.spoff
);
2434 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2435 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2436 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2438 case spill_psprel_p
:
2439 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2440 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2441 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2444 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2445 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2446 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2449 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2450 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2451 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2455 as_bad ("record_type_not_valid");
2460 /* Given a unw_rec_list list, process all the records with
2461 the specified function. */
2463 process_unw_records (list
, f
)
2468 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2469 process_one_record (ptr
, f
);
2472 /* Determine the size of a record list in bytes. */
2474 calc_record_size (list
)
2478 process_unw_records (list
, count_output
);
2482 /* Update IMASK bitmask to reflect the fact that one or more registers
2483 of type TYPE are saved starting at instruction with index T. If N
2484 bits are set in REGMASK, it is assumed that instructions T through
2485 T+N-1 save these registers.
2489 1: instruction saves next fp reg
2490 2: instruction saves next general reg
2491 3: instruction saves next branch reg */
2493 set_imask (region
, regmask
, t
, type
)
2494 unw_rec_list
*region
;
2495 unsigned long regmask
;
2499 unsigned char *imask
;
2500 unsigned long imask_size
;
2504 imask
= region
->r
.record
.r
.mask
.i
;
2505 imask_size
= region
->r
.record
.r
.imask_size
;
2508 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2509 imask
= xmalloc (imask_size
);
2510 memset (imask
, 0, imask_size
);
2512 region
->r
.record
.r
.imask_size
= imask_size
;
2513 region
->r
.record
.r
.mask
.i
= imask
;
2517 pos
= 2 * (3 - t
% 4);
2520 if (i
>= imask_size
)
2522 as_bad ("Ignoring attempt to spill beyond end of region");
2526 imask
[i
] |= (type
& 0x3) << pos
;
2528 regmask
&= (regmask
- 1);
2539 count_bits (unsigned long mask
)
2551 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2552 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2553 containing FIRST_ADDR. */
2556 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2557 unsigned long slot_addr
;
2559 unsigned long first_addr
;
2562 unsigned long index
= 0;
2564 /* First time we are called, the initial address and frag are invalid. */
2565 if (first_addr
== 0)
2568 /* If the two addresses are in different frags, then we need to add in
2569 the remaining size of this frag, and then the entire size of intermediate
2571 while (slot_frag
!= first_frag
)
2573 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2575 /* Add in the full size of the frag converted to instruction slots. */
2576 index
+= 3 * (first_frag
->fr_fix
>> 4);
2577 /* Subtract away the initial part before first_addr. */
2578 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2579 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2581 /* Move to the beginning of the next frag. */
2582 first_frag
= first_frag
->fr_next
;
2583 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2586 /* Add in the used part of the last frag. */
2587 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2588 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2592 /* Optimize unwind record directives. */
2594 static unw_rec_list
*
2595 optimize_unw_records (list
)
2601 /* If the only unwind record is ".prologue" or ".prologue" followed
2602 by ".body", then we can optimize the unwind directives away. */
2603 if (list
->r
.type
== prologue
2604 && (list
->next
== NULL
2605 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2611 /* Given a complete record list, process any records which have
2612 unresolved fields, (ie length counts for a prologue). After
2613 this has been run, all neccessary information should be available
2614 within each record to generate an image. */
2617 fixup_unw_records (list
)
2620 unw_rec_list
*ptr
, *region
= 0;
2621 unsigned long first_addr
= 0, rlen
= 0, t
;
2622 fragS
*first_frag
= 0;
2624 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2626 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2627 as_bad (" Insn slot not set in unwind record.");
2628 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2629 first_addr
, first_frag
);
2630 switch (ptr
->r
.type
)
2637 int size
, dir_len
= 0;
2638 unsigned long last_addr
;
2641 first_addr
= ptr
->slot_number
;
2642 first_frag
= ptr
->slot_frag
;
2643 ptr
->slot_number
= 0;
2644 /* Find either the next body/prologue start, or the end of
2645 the list, and determine the size of the region. */
2646 last_addr
= unwind
.next_slot_number
;
2647 last_frag
= unwind
.next_slot_frag
;
2648 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2649 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2650 || last
->r
.type
== body
)
2652 last_addr
= last
->slot_number
;
2653 last_frag
= last
->slot_frag
;
2656 else if (!last
->next
)
2658 /* In the absence of an explicit .body directive,
2659 the prologue ends after the last instruction
2660 covered by an unwind directive. */
2661 if (ptr
->r
.type
!= body
)
2663 last_addr
= last
->slot_number
;
2664 last_frag
= last
->slot_frag
;
2665 switch (last
->r
.type
)
2668 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2669 + count_bits (last
->r
.record
.p
.grmask
));
2673 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2677 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2680 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2689 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2691 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2696 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2707 case priunat_when_gr
:
2708 case priunat_when_mem
:
2712 ptr
->r
.record
.p
.t
= t
;
2720 case spill_psprel_p
:
2721 ptr
->r
.record
.x
.t
= t
;
2727 as_bad ("frgr_mem record before region record!\n");
2730 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2731 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2732 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2733 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2738 as_bad ("fr_mem record before region record!\n");
2741 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2742 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2747 as_bad ("gr_mem record before region record!\n");
2750 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2751 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2756 as_bad ("br_mem record before region record!\n");
2759 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2760 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2766 as_bad ("gr_gr record before region record!\n");
2769 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2774 as_bad ("br_gr record before region record!\n");
2777 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2786 /* Helper routine for output_unw_records. Emits the header for the unwind
2790 setup_unwind_header (int size
, unsigned char **mem
)
2794 /* pad to pointer-size boundry. */
2795 x
= size
% md
.pointer_size
;
2797 extra
= md
.pointer_size
- x
;
2799 /* Add 8 for the header + a pointer for the
2800 personality offset. */
2801 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2803 /* Clear the padding area and personality. */
2804 memset (*mem
+ 8 + size
, 0 , extra
+ md
.pointer_size
);
2805 /* Initialize the header area. */
2807 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* version */
2808 | (unwind
.personality_routine
2809 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2811 | ((size
+ extra
) / md
.pointer_size
)), /* length */
2817 /* Generate an unwind image from a record list. Returns the number of
2818 bytes in the resulting image. The memory image itselof is returned
2819 in the 'ptr' parameter. */
2821 output_unw_records (list
, ptr
)
2830 list
= optimize_unw_records (list
);
2831 fixup_unw_records (list
);
2832 size
= calc_record_size (list
);
2834 if (size
> 0 || unwind
.force_unwind_entry
)
2836 unwind
.force_unwind_entry
= 0;
2837 extra
= setup_unwind_header (size
, &mem
);
2839 vbyte_mem_ptr
= mem
+ 8;
2840 process_unw_records (list
, output_vbyte_mem
);
2844 size
+= extra
+ 8 + md
.pointer_size
;
2850 convert_expr_to_ab_reg (e
, ab
, regp
)
2857 if (e
->X_op
!= O_register
)
2860 reg
= e
->X_add_number
;
2861 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2864 *regp
= reg
- REG_GR
;
2866 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2867 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2870 *regp
= reg
- REG_FR
;
2872 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2875 *regp
= reg
- REG_BR
;
2882 case REG_PR
: *regp
= 0; break;
2883 case REG_PSP
: *regp
= 1; break;
2884 case REG_PRIUNAT
: *regp
= 2; break;
2885 case REG_BR
+ 0: *regp
= 3; break;
2886 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2887 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2888 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2889 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2890 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2891 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2892 case REG_AR
+ AR_LC
: *regp
= 10; break;
2902 convert_expr_to_xy_reg (e
, xy
, regp
)
2909 if (e
->X_op
!= O_register
)
2912 reg
= e
->X_add_number
;
2914 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2917 *regp
= reg
- REG_GR
;
2919 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2922 *regp
= reg
- REG_FR
;
2924 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2927 *regp
= reg
- REG_BR
;
2936 int dummy ATTRIBUTE_UNUSED
;
2941 radix
= *input_line_pointer
++;
2943 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2945 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2946 ignore_rest_of_line ();
2951 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2953 dot_special_section (which
)
2956 set_section ((char *) special_section_name
[which
]);
2960 add_unwind_entry (ptr
)
2964 unwind
.tail
->next
= ptr
;
2969 /* The current entry can in fact be a chain of unwind entries. */
2970 if (unwind
.current_entry
== NULL
)
2971 unwind
.current_entry
= ptr
;
2976 int dummy ATTRIBUTE_UNUSED
;
2982 if (e
.X_op
!= O_constant
)
2983 as_bad ("Operand to .fframe must be a constant");
2985 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2990 int dummy ATTRIBUTE_UNUSED
;
2996 reg
= e
.X_add_number
- REG_GR
;
2997 if (e
.X_op
== O_register
&& reg
< 128)
2999 add_unwind_entry (output_mem_stack_v ());
3000 if (! (unwind
.prologue_mask
& 2))
3001 add_unwind_entry (output_psp_gr (reg
));
3004 as_bad ("First operand to .vframe must be a general register");
3008 dot_vframesp (dummy
)
3009 int dummy ATTRIBUTE_UNUSED
;
3014 if (e
.X_op
== O_constant
)
3016 add_unwind_entry (output_mem_stack_v ());
3017 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3020 as_bad ("First operand to .vframesp must be a general register");
3024 dot_vframepsp (dummy
)
3025 int dummy ATTRIBUTE_UNUSED
;
3030 if (e
.X_op
== O_constant
)
3032 add_unwind_entry (output_mem_stack_v ());
3033 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3036 as_bad ("First operand to .vframepsp must be a general register");
3041 int dummy ATTRIBUTE_UNUSED
;
3047 sep
= parse_operand (&e1
);
3049 as_bad ("No second operand to .save");
3050 sep
= parse_operand (&e2
);
3052 reg1
= e1
.X_add_number
;
3053 reg2
= e2
.X_add_number
- REG_GR
;
3055 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3056 if (e1
.X_op
== O_register
)
3058 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3062 case REG_AR
+ AR_BSP
:
3063 add_unwind_entry (output_bsp_when ());
3064 add_unwind_entry (output_bsp_gr (reg2
));
3066 case REG_AR
+ AR_BSPSTORE
:
3067 add_unwind_entry (output_bspstore_when ());
3068 add_unwind_entry (output_bspstore_gr (reg2
));
3070 case REG_AR
+ AR_RNAT
:
3071 add_unwind_entry (output_rnat_when ());
3072 add_unwind_entry (output_rnat_gr (reg2
));
3074 case REG_AR
+ AR_UNAT
:
3075 add_unwind_entry (output_unat_when ());
3076 add_unwind_entry (output_unat_gr (reg2
));
3078 case REG_AR
+ AR_FPSR
:
3079 add_unwind_entry (output_fpsr_when ());
3080 add_unwind_entry (output_fpsr_gr (reg2
));
3082 case REG_AR
+ AR_PFS
:
3083 add_unwind_entry (output_pfs_when ());
3084 if (! (unwind
.prologue_mask
& 4))
3085 add_unwind_entry (output_pfs_gr (reg2
));
3087 case REG_AR
+ AR_LC
:
3088 add_unwind_entry (output_lc_when ());
3089 add_unwind_entry (output_lc_gr (reg2
));
3092 add_unwind_entry (output_rp_when ());
3093 if (! (unwind
.prologue_mask
& 8))
3094 add_unwind_entry (output_rp_gr (reg2
));
3097 add_unwind_entry (output_preds_when ());
3098 if (! (unwind
.prologue_mask
& 1))
3099 add_unwind_entry (output_preds_gr (reg2
));
3102 add_unwind_entry (output_priunat_when_gr ());
3103 add_unwind_entry (output_priunat_gr (reg2
));
3106 as_bad ("First operand not a valid register");
3110 as_bad (" Second operand not a valid register");
3113 as_bad ("First operand not a register");
3118 int dummy ATTRIBUTE_UNUSED
;
3121 unsigned long ecount
; /* # of _additional_ regions to pop */
3124 sep
= parse_operand (&e1
);
3125 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3127 as_bad ("First operand to .restore must be stack pointer (sp)");
3133 parse_operand (&e2
);
3134 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3136 as_bad ("Second operand to .restore must be a constant >= 0");
3139 ecount
= e2
.X_add_number
;
3142 ecount
= unwind
.prologue_count
- 1;
3143 add_unwind_entry (output_epilogue (ecount
));
3145 if (ecount
< unwind
.prologue_count
)
3146 unwind
.prologue_count
-= ecount
+ 1;
3148 unwind
.prologue_count
= 0;
3152 dot_restorereg (dummy
)
3153 int dummy ATTRIBUTE_UNUSED
;
3155 unsigned int ab
, reg
;
3160 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3162 as_bad ("First operand to .restorereg must be a preserved register");
3165 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3169 dot_restorereg_p (dummy
)
3170 int dummy ATTRIBUTE_UNUSED
;
3172 unsigned int qp
, ab
, reg
;
3176 sep
= parse_operand (&e1
);
3179 as_bad ("No second operand to .restorereg.p");
3183 parse_operand (&e2
);
3185 qp
= e1
.X_add_number
- REG_P
;
3186 if (e1
.X_op
!= O_register
|| qp
> 63)
3188 as_bad ("First operand to .restorereg.p must be a predicate");
3192 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3194 as_bad ("Second operand to .restorereg.p must be a preserved register");
3197 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3201 generate_unwind_image (text_name
)
3202 const char *text_name
;
3205 unsigned char *unw_rec
;
3207 /* Force out pending instructions, to make sure all unwind records have
3208 a valid slot_number field. */
3209 ia64_flush_insns ();
3211 /* Generate the unwind record. */
3212 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3213 if (size
% md
.pointer_size
!= 0)
3214 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3216 /* If there are unwind records, switch sections, and output the info. */
3219 unsigned char *where
;
3223 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3224 set_section (sec_name
);
3225 bfd_set_section_flags (stdoutput
, now_seg
,
3226 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3228 /* Make sure the section has 4 byte alignment for ILP32 and
3229 8 byte alignment for LP64. */
3230 frag_align (md
.pointer_size_shift
, 0, 0);
3231 record_alignment (now_seg
, md
.pointer_size_shift
);
3233 /* Set expression which points to start of unwind descriptor area. */
3234 unwind
.info
= expr_build_dot ();
3236 where
= (unsigned char *) frag_more (size
);
3238 /* Issue a label for this address, and keep track of it to put it
3239 in the unwind section. */
3241 /* Copy the information from the unwind record into this section. The
3242 data is already in the correct byte order. */
3243 memcpy (where
, unw_rec
, size
);
3245 /* Add the personality address to the image. */
3246 if (unwind
.personality_routine
!= 0)
3248 exp
.X_op
= O_symbol
;
3249 exp
.X_add_symbol
= unwind
.personality_routine
;
3250 exp
.X_add_number
= 0;
3251 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3252 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3253 unwind
.personality_routine
= 0;
3257 free_list_records (unwind
.list
);
3258 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3264 dot_handlerdata (dummy
)
3265 int dummy ATTRIBUTE_UNUSED
;
3267 const char *text_name
= segment_name (now_seg
);
3269 /* If text section name starts with ".text" (which it should),
3270 strip this prefix off. */
3271 if (strcmp (text_name
, ".text") == 0)
3274 unwind
.force_unwind_entry
= 1;
3276 /* Remember which segment we're in so we can switch back after .endp */
3277 unwind
.saved_text_seg
= now_seg
;
3278 unwind
.saved_text_subseg
= now_subseg
;
3280 /* Generate unwind info into unwind-info section and then leave that
3281 section as the currently active one so dataXX directives go into
3282 the language specific data area of the unwind info block. */
3283 generate_unwind_image (text_name
);
3284 demand_empty_rest_of_line ();
3288 dot_unwentry (dummy
)
3289 int dummy ATTRIBUTE_UNUSED
;
3291 unwind
.force_unwind_entry
= 1;
3292 demand_empty_rest_of_line ();
3297 int dummy ATTRIBUTE_UNUSED
;
3303 reg
= e
.X_add_number
- REG_BR
;
3304 if (e
.X_op
== O_register
&& reg
< 8)
3305 add_unwind_entry (output_rp_br (reg
));
3307 as_bad ("First operand not a valid branch register");
3311 dot_savemem (psprel
)
3318 sep
= parse_operand (&e1
);
3320 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3321 sep
= parse_operand (&e2
);
3323 reg1
= e1
.X_add_number
;
3324 val
= e2
.X_add_number
;
3326 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3327 if (e1
.X_op
== O_register
)
3329 if (e2
.X_op
== O_constant
)
3333 case REG_AR
+ AR_BSP
:
3334 add_unwind_entry (output_bsp_when ());
3335 add_unwind_entry ((psprel
3337 : output_bsp_sprel
) (val
));
3339 case REG_AR
+ AR_BSPSTORE
:
3340 add_unwind_entry (output_bspstore_when ());
3341 add_unwind_entry ((psprel
3342 ? output_bspstore_psprel
3343 : output_bspstore_sprel
) (val
));
3345 case REG_AR
+ AR_RNAT
:
3346 add_unwind_entry (output_rnat_when ());
3347 add_unwind_entry ((psprel
3348 ? output_rnat_psprel
3349 : output_rnat_sprel
) (val
));
3351 case REG_AR
+ AR_UNAT
:
3352 add_unwind_entry (output_unat_when ());
3353 add_unwind_entry ((psprel
3354 ? output_unat_psprel
3355 : output_unat_sprel
) (val
));
3357 case REG_AR
+ AR_FPSR
:
3358 add_unwind_entry (output_fpsr_when ());
3359 add_unwind_entry ((psprel
3360 ? output_fpsr_psprel
3361 : output_fpsr_sprel
) (val
));
3363 case REG_AR
+ AR_PFS
:
3364 add_unwind_entry (output_pfs_when ());
3365 add_unwind_entry ((psprel
3367 : output_pfs_sprel
) (val
));
3369 case REG_AR
+ AR_LC
:
3370 add_unwind_entry (output_lc_when ());
3371 add_unwind_entry ((psprel
3373 : output_lc_sprel
) (val
));
3376 add_unwind_entry (output_rp_when ());
3377 add_unwind_entry ((psprel
3379 : output_rp_sprel
) (val
));
3382 add_unwind_entry (output_preds_when ());
3383 add_unwind_entry ((psprel
3384 ? output_preds_psprel
3385 : output_preds_sprel
) (val
));
3388 add_unwind_entry (output_priunat_when_mem ());
3389 add_unwind_entry ((psprel
3390 ? output_priunat_psprel
3391 : output_priunat_sprel
) (val
));
3394 as_bad ("First operand not a valid register");
3398 as_bad (" Second operand not a valid constant");
3401 as_bad ("First operand not a register");
3406 int dummy ATTRIBUTE_UNUSED
;
3410 sep
= parse_operand (&e1
);
3412 parse_operand (&e2
);
3414 if (e1
.X_op
!= O_constant
)
3415 as_bad ("First operand to .save.g must be a constant.");
3418 int grmask
= e1
.X_add_number
;
3420 add_unwind_entry (output_gr_mem (grmask
));
3423 int reg
= e2
.X_add_number
- REG_GR
;
3424 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3425 add_unwind_entry (output_gr_gr (grmask
, reg
));
3427 as_bad ("Second operand is an invalid register.");
3434 int dummy ATTRIBUTE_UNUSED
;
3438 sep
= parse_operand (&e1
);
3440 if (e1
.X_op
!= O_constant
)
3441 as_bad ("Operand to .save.f must be a constant.");
3443 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3448 int dummy ATTRIBUTE_UNUSED
;
3455 sep
= parse_operand (&e1
);
3456 if (e1
.X_op
!= O_constant
)
3458 as_bad ("First operand to .save.b must be a constant.");
3461 brmask
= e1
.X_add_number
;
3465 sep
= parse_operand (&e2
);
3466 reg
= e2
.X_add_number
- REG_GR
;
3467 if (e2
.X_op
!= O_register
|| reg
> 127)
3469 as_bad ("Second operand to .save.b must be a general register.");
3472 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3475 add_unwind_entry (output_br_mem (brmask
));
3477 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3478 ignore_rest_of_line ();
3483 int dummy ATTRIBUTE_UNUSED
;
3487 sep
= parse_operand (&e1
);
3489 parse_operand (&e2
);
3491 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3492 as_bad ("Both operands of .save.gf must be constants.");
3495 int grmask
= e1
.X_add_number
;
3496 int frmask
= e2
.X_add_number
;
3497 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3503 int dummy ATTRIBUTE_UNUSED
;
3508 sep
= parse_operand (&e
);
3509 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3510 ignore_rest_of_line ();
3512 if (e
.X_op
!= O_constant
)
3513 as_bad ("Operand to .spill must be a constant");
3515 add_unwind_entry (output_spill_base (e
.X_add_number
));
3519 dot_spillreg (dummy
)
3520 int dummy ATTRIBUTE_UNUSED
;
3522 int sep
, ab
, xy
, reg
, treg
;
3525 sep
= parse_operand (&e1
);
3528 as_bad ("No second operand to .spillreg");
3532 parse_operand (&e2
);
3534 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3536 as_bad ("First operand to .spillreg must be a preserved register");
3540 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3542 as_bad ("Second operand to .spillreg must be a register");
3546 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3550 dot_spillmem (psprel
)
3556 sep
= parse_operand (&e1
);
3559 as_bad ("Second operand missing");
3563 parse_operand (&e2
);
3565 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3567 as_bad ("First operand to .spill%s must be a preserved register",
3568 psprel
? "psp" : "sp");
3572 if (e2
.X_op
!= O_constant
)
3574 as_bad ("Second operand to .spill%s must be a constant",
3575 psprel
? "psp" : "sp");
3580 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3582 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3586 dot_spillreg_p (dummy
)
3587 int dummy ATTRIBUTE_UNUSED
;
3589 int sep
, ab
, xy
, reg
, treg
;
3590 expressionS e1
, e2
, e3
;
3593 sep
= parse_operand (&e1
);
3596 as_bad ("No second and third operand to .spillreg.p");
3600 sep
= parse_operand (&e2
);
3603 as_bad ("No third operand to .spillreg.p");
3607 parse_operand (&e3
);
3609 qp
= e1
.X_add_number
- REG_P
;
3611 if (e1
.X_op
!= O_register
|| qp
> 63)
3613 as_bad ("First operand to .spillreg.p must be a predicate");
3617 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3619 as_bad ("Second operand to .spillreg.p must be a preserved register");
3623 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3625 as_bad ("Third operand to .spillreg.p must be a register");
3629 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3633 dot_spillmem_p (psprel
)
3636 expressionS e1
, e2
, e3
;
3640 sep
= parse_operand (&e1
);
3643 as_bad ("Second operand missing");
3647 parse_operand (&e2
);
3650 as_bad ("Second operand missing");
3654 parse_operand (&e3
);
3656 qp
= e1
.X_add_number
- REG_P
;
3657 if (e1
.X_op
!= O_register
|| qp
> 63)
3659 as_bad ("First operand to .spill%s_p must be a predicate",
3660 psprel
? "psp" : "sp");
3664 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3666 as_bad ("Second operand to .spill%s_p must be a preserved register",
3667 psprel
? "psp" : "sp");
3671 if (e3
.X_op
!= O_constant
)
3673 as_bad ("Third operand to .spill%s_p must be a constant",
3674 psprel
? "psp" : "sp");
3679 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3681 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3685 dot_label_state (dummy
)
3686 int dummy ATTRIBUTE_UNUSED
;
3691 if (e
.X_op
!= O_constant
)
3693 as_bad ("Operand to .label_state must be a constant");
3696 add_unwind_entry (output_label_state (e
.X_add_number
));
3700 dot_copy_state (dummy
)
3701 int dummy ATTRIBUTE_UNUSED
;
3706 if (e
.X_op
!= O_constant
)
3708 as_bad ("Operand to .copy_state must be a constant");
3711 add_unwind_entry (output_copy_state (e
.X_add_number
));
3716 int dummy ATTRIBUTE_UNUSED
;
3721 sep
= parse_operand (&e1
);
3724 as_bad ("Second operand to .unwabi missing");
3727 sep
= parse_operand (&e2
);
3728 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3729 ignore_rest_of_line ();
3731 if (e1
.X_op
!= O_constant
)
3733 as_bad ("First operand to .unwabi must be a constant");
3737 if (e2
.X_op
!= O_constant
)
3739 as_bad ("Second operand to .unwabi must be a constant");
3743 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3747 dot_personality (dummy
)
3748 int dummy ATTRIBUTE_UNUSED
;
3752 name
= input_line_pointer
;
3753 c
= get_symbol_end ();
3754 p
= input_line_pointer
;
3755 unwind
.personality_routine
= symbol_find_or_make (name
);
3756 unwind
.force_unwind_entry
= 1;
3759 demand_empty_rest_of_line ();
3764 int dummy ATTRIBUTE_UNUSED
;
3769 unwind
.proc_start
= expr_build_dot ();
3770 /* Parse names of main and alternate entry points and mark them as
3771 function symbols: */
3775 name
= input_line_pointer
;
3776 c
= get_symbol_end ();
3777 p
= input_line_pointer
;
3778 sym
= symbol_find_or_make (name
);
3779 if (unwind
.proc_start
== 0)
3781 unwind
.proc_start
= sym
;
3783 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3786 if (*input_line_pointer
!= ',')
3788 ++input_line_pointer
;
3790 demand_empty_rest_of_line ();
3793 unwind
.prologue_count
= 0;
3794 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3795 unwind
.personality_routine
= 0;
3800 int dummy ATTRIBUTE_UNUSED
;
3802 unwind
.prologue
= 0;
3803 unwind
.prologue_mask
= 0;
3805 add_unwind_entry (output_body ());
3806 demand_empty_rest_of_line ();
3810 dot_prologue (dummy
)
3811 int dummy ATTRIBUTE_UNUSED
;
3814 int mask
= 0, grsave
= 0;
3816 if (!is_it_end_of_statement ())
3819 sep
= parse_operand (&e1
);
3821 as_bad ("No second operand to .prologue");
3822 sep
= parse_operand (&e2
);
3823 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3824 ignore_rest_of_line ();
3826 if (e1
.X_op
== O_constant
)
3828 mask
= e1
.X_add_number
;
3830 if (e2
.X_op
== O_constant
)
3831 grsave
= e2
.X_add_number
;
3832 else if (e2
.X_op
== O_register
3833 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3836 as_bad ("Second operand not a constant or general register");
3838 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3841 as_bad ("First operand not a constant");
3844 add_unwind_entry (output_prologue ());
3846 unwind
.prologue
= 1;
3847 unwind
.prologue_mask
= mask
;
3848 ++unwind
.prologue_count
;
3853 int dummy ATTRIBUTE_UNUSED
;
3857 int bytes_per_address
;
3860 subsegT saved_subseg
;
3861 const char *sec_name
, *text_name
;
3865 if (unwind
.saved_text_seg
)
3867 saved_seg
= unwind
.saved_text_seg
;
3868 saved_subseg
= unwind
.saved_text_subseg
;
3869 unwind
.saved_text_seg
= NULL
;
3873 saved_seg
= now_seg
;
3874 saved_subseg
= now_subseg
;
3878 Use a slightly ugly scheme to derive the unwind section names from
3879 the text section name:
3881 text sect. unwind table sect.
3882 name: name: comments:
3883 ---------- ----------------- --------------------------------
3885 .text.foo .IA_64.unwind.text.foo
3886 .foo .IA_64.unwind.foo
3888 .gnu.linkonce.ia64unw.foo
3889 _info .IA_64.unwind_info gas issues error message (ditto)
3890 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3892 This mapping is done so that:
3894 (a) An object file with unwind info only in .text will use
3895 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3896 This follows the letter of the ABI and also ensures backwards
3897 compatibility with older toolchains.
3899 (b) An object file with unwind info in multiple text sections
3900 will use separate unwind sections for each text section.
3901 This allows us to properly set the "sh_info" and "sh_link"
3902 fields in SHT_IA_64_UNWIND as required by the ABI and also
3903 lets GNU ld support programs with multiple segments
3904 containing unwind info (as might be the case for certain
3905 embedded applications).
3907 (c) An error is issued if there would be a name clash.
3909 text_name
= segment_name (saved_seg
);
3910 if (strncmp (text_name
, "_info", 5) == 0)
3912 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3914 ignore_rest_of_line ();
3917 if (strcmp (text_name
, ".text") == 0)
3920 insn_group_break (1, 0, 0);
3922 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3924 generate_unwind_image (text_name
);
3926 if (unwind
.info
|| unwind
.force_unwind_entry
)
3928 subseg_set (md
.last_text_seg
, 0);
3929 unwind
.proc_end
= expr_build_dot ();
3931 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3932 set_section ((char *) sec_name
);
3933 bfd_set_section_flags (stdoutput
, now_seg
,
3934 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3936 /* Make sure that section has 4 byte alignment for ILP32 and
3937 8 byte alignment for LP64. */
3938 record_alignment (now_seg
, md
.pointer_size_shift
);
3940 /* Need space for 3 pointers for procedure start, procedure end,
3942 ptr
= frag_more (3 * md
.pointer_size
);
3943 where
= frag_now_fix () - (3 * md
.pointer_size
);
3944 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3946 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3947 e
.X_op
= O_pseudo_fixup
;
3948 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3950 e
.X_add_symbol
= unwind
.proc_start
;
3951 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3953 e
.X_op
= O_pseudo_fixup
;
3954 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3956 e
.X_add_symbol
= unwind
.proc_end
;
3957 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3958 bytes_per_address
, &e
);
3962 e
.X_op
= O_pseudo_fixup
;
3963 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3965 e
.X_add_symbol
= unwind
.info
;
3966 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3967 bytes_per_address
, &e
);
3970 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3974 subseg_set (saved_seg
, saved_subseg
);
3976 /* Parse names of main and alternate entry points and set symbol sizes. */
3980 name
= input_line_pointer
;
3981 c
= get_symbol_end ();
3982 p
= input_line_pointer
;
3983 sym
= symbol_find (name
);
3984 if (sym
&& unwind
.proc_start
3985 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
3986 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
3988 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
3989 fragS
*frag
= symbol_get_frag (sym
);
3991 /* Check whether the function label is at or beyond last
3993 while (fr
&& fr
!= frag
)
3997 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
3998 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
4001 symbol_get_obj (sym
)->size
=
4002 (expressionS
*) xmalloc (sizeof (expressionS
));
4003 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
4004 symbol_get_obj (sym
)->size
->X_add_symbol
4005 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
4006 frag_now_fix (), frag_now
);
4007 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
4008 symbol_get_obj (sym
)->size
->X_add_number
= 0;
4014 if (*input_line_pointer
!= ',')
4016 ++input_line_pointer
;
4018 demand_empty_rest_of_line ();
4019 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4023 dot_template (template)
4026 CURR_SLOT
.user_template
= template;
4031 int dummy ATTRIBUTE_UNUSED
;
4033 int ins
, locs
, outs
, rots
;
4035 if (is_it_end_of_statement ())
4036 ins
= locs
= outs
= rots
= 0;
4039 ins
= get_absolute_expression ();
4040 if (*input_line_pointer
++ != ',')
4042 locs
= get_absolute_expression ();
4043 if (*input_line_pointer
++ != ',')
4045 outs
= get_absolute_expression ();
4046 if (*input_line_pointer
++ != ',')
4048 rots
= get_absolute_expression ();
4050 set_regstack (ins
, locs
, outs
, rots
);
4054 as_bad ("Comma expected");
4055 ignore_rest_of_line ();
4062 unsigned num_regs
, num_alloced
= 0;
4063 struct dynreg
**drpp
, *dr
;
4064 int ch
, base_reg
= 0;
4070 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4071 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4072 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4076 /* First, remove existing names from hash table. */
4077 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4079 hash_delete (md
.dynreg_hash
, dr
->name
);
4083 drpp
= &md
.dynreg
[type
];
4086 start
= input_line_pointer
;
4087 ch
= get_symbol_end ();
4088 *input_line_pointer
= ch
;
4089 len
= (input_line_pointer
- start
);
4092 if (*input_line_pointer
!= '[')
4094 as_bad ("Expected '['");
4097 ++input_line_pointer
; /* skip '[' */
4099 num_regs
= get_absolute_expression ();
4101 if (*input_line_pointer
++ != ']')
4103 as_bad ("Expected ']'");
4108 num_alloced
+= num_regs
;
4112 if (num_alloced
> md
.rot
.num_regs
)
4114 as_bad ("Used more than the declared %d rotating registers",
4120 if (num_alloced
> 96)
4122 as_bad ("Used more than the available 96 rotating registers");
4127 if (num_alloced
> 48)
4129 as_bad ("Used more than the available 48 rotating registers");
4138 name
= obstack_alloc (¬es
, len
+ 1);
4139 memcpy (name
, start
, len
);
4144 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4145 memset (*drpp
, 0, sizeof (*dr
));
4150 dr
->num_regs
= num_regs
;
4151 dr
->base
= base_reg
;
4153 base_reg
+= num_regs
;
4155 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4157 as_bad ("Attempt to redefine register set `%s'", name
);
4161 if (*input_line_pointer
!= ',')
4163 ++input_line_pointer
; /* skip comma */
4166 demand_empty_rest_of_line ();
4170 ignore_rest_of_line ();
4174 dot_byteorder (byteorder
)
4177 target_big_endian
= byteorder
;
4182 int dummy ATTRIBUTE_UNUSED
;
4189 option
= input_line_pointer
;
4190 ch
= get_symbol_end ();
4191 if (strcmp (option
, "lsb") == 0)
4192 md
.flags
&= ~EF_IA_64_BE
;
4193 else if (strcmp (option
, "msb") == 0)
4194 md
.flags
|= EF_IA_64_BE
;
4195 else if (strcmp (option
, "abi32") == 0)
4196 md
.flags
&= ~EF_IA_64_ABI64
;
4197 else if (strcmp (option
, "abi64") == 0)
4198 md
.flags
|= EF_IA_64_ABI64
;
4200 as_bad ("Unknown psr option `%s'", option
);
4201 *input_line_pointer
= ch
;
4204 if (*input_line_pointer
!= ',')
4207 ++input_line_pointer
;
4210 demand_empty_rest_of_line ();
4215 int dummy ATTRIBUTE_UNUSED
;
4217 as_bad (".alias not implemented yet");
4222 int dummy ATTRIBUTE_UNUSED
;
4224 new_logical_line (0, get_absolute_expression ());
4225 demand_empty_rest_of_line ();
4229 parse_section_name ()
4235 if (*input_line_pointer
!= '"')
4237 as_bad ("Missing section name");
4238 ignore_rest_of_line ();
4241 name
= demand_copy_C_string (&len
);
4244 ignore_rest_of_line ();
4248 if (*input_line_pointer
!= ',')
4250 as_bad ("Comma expected after section name");
4251 ignore_rest_of_line ();
4254 ++input_line_pointer
; /* skip comma */
4262 char *name
= parse_section_name ();
4266 md
.keep_pending_output
= 1;
4269 obj_elf_previous (0);
4270 md
.keep_pending_output
= 0;
4273 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4276 stmt_float_cons (kind
)
4283 case 'd': size
= 8; break;
4284 case 'x': size
= 10; break;
4291 ia64_do_align (size
);
4299 int saved_auto_align
= md
.auto_align
;
4303 md
.auto_align
= saved_auto_align
;
4307 dot_xfloat_cons (kind
)
4310 char *name
= parse_section_name ();
4314 md
.keep_pending_output
= 1;
4316 stmt_float_cons (kind
);
4317 obj_elf_previous (0);
4318 md
.keep_pending_output
= 0;
4322 dot_xstringer (zero
)
4325 char *name
= parse_section_name ();
4329 md
.keep_pending_output
= 1;
4332 obj_elf_previous (0);
4333 md
.keep_pending_output
= 0;
4340 int saved_auto_align
= md
.auto_align
;
4341 char *name
= parse_section_name ();
4345 md
.keep_pending_output
= 1;
4349 md
.auto_align
= saved_auto_align
;
4350 obj_elf_previous (0);
4351 md
.keep_pending_output
= 0;
4355 dot_xfloat_cons_ua (kind
)
4358 int saved_auto_align
= md
.auto_align
;
4359 char *name
= parse_section_name ();
4363 md
.keep_pending_output
= 1;
4366 stmt_float_cons (kind
);
4367 md
.auto_align
= saved_auto_align
;
4368 obj_elf_previous (0);
4369 md
.keep_pending_output
= 0;
4372 /* .reg.val <regname>,value */
4376 int dummy ATTRIBUTE_UNUSED
;
4381 if (reg
.X_op
!= O_register
)
4383 as_bad (_("Register name expected"));
4384 ignore_rest_of_line ();
4386 else if (*input_line_pointer
++ != ',')
4388 as_bad (_("Comma expected"));
4389 ignore_rest_of_line ();
4393 valueT value
= get_absolute_expression ();
4394 int regno
= reg
.X_add_number
;
4395 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4396 as_warn (_("Register value annotation ignored"));
4399 gr_values
[regno
- REG_GR
].known
= 1;
4400 gr_values
[regno
- REG_GR
].value
= value
;
4401 gr_values
[regno
- REG_GR
].path
= md
.path
;
4404 demand_empty_rest_of_line ();
4407 /* select dv checking mode
4412 A stop is inserted when changing modes
4419 if (md
.manual_bundling
)
4420 as_warn (_("Directive invalid within a bundle"));
4422 if (type
== 'E' || type
== 'A')
4423 md
.mode_explicitly_set
= 0;
4425 md
.mode_explicitly_set
= 1;
4432 if (md
.explicit_mode
)
4433 insn_group_break (1, 0, 0);
4434 md
.explicit_mode
= 0;
4438 if (!md
.explicit_mode
)
4439 insn_group_break (1, 0, 0);
4440 md
.explicit_mode
= 1;
4444 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4445 insn_group_break (1, 0, 0);
4446 md
.explicit_mode
= md
.default_explicit_mode
;
4447 md
.mode_explicitly_set
= 0;
4458 for (regno
= 0; regno
< 64; regno
++)
4460 if (mask
& ((valueT
) 1 << regno
))
4462 fprintf (stderr
, "%s p%d", comma
, regno
);
4469 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4470 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4471 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4472 .pred.safe_across_calls p1 [, p2 [,...]]
4481 int p1
= -1, p2
= -1;
4485 if (*input_line_pointer
!= '"')
4487 as_bad (_("Missing predicate relation type"));
4488 ignore_rest_of_line ();
4494 char *form
= demand_copy_C_string (&len
);
4495 if (strcmp (form
, "mutex") == 0)
4497 else if (strcmp (form
, "clear") == 0)
4499 else if (strcmp (form
, "imply") == 0)
4503 as_bad (_("Unrecognized predicate relation type"));
4504 ignore_rest_of_line ();
4508 if (*input_line_pointer
== ',')
4509 ++input_line_pointer
;
4519 if (TOUPPER (*input_line_pointer
) != 'P'
4520 || (regno
= atoi (++input_line_pointer
)) < 0
4523 as_bad (_("Predicate register expected"));
4524 ignore_rest_of_line ();
4527 while (ISDIGIT (*input_line_pointer
))
4528 ++input_line_pointer
;
4535 as_warn (_("Duplicate predicate register ignored"));
4538 /* See if it's a range. */
4539 if (*input_line_pointer
== '-')
4542 ++input_line_pointer
;
4544 if (TOUPPER (*input_line_pointer
) != 'P'
4545 || (regno
= atoi (++input_line_pointer
)) < 0
4548 as_bad (_("Predicate register expected"));
4549 ignore_rest_of_line ();
4552 while (ISDIGIT (*input_line_pointer
))
4553 ++input_line_pointer
;
4557 as_bad (_("Bad register range"));
4558 ignore_rest_of_line ();
4569 if (*input_line_pointer
!= ',')
4571 ++input_line_pointer
;
4580 clear_qp_mutex (mask
);
4581 clear_qp_implies (mask
, (valueT
) 0);
4584 if (count
!= 2 || p1
== -1 || p2
== -1)
4585 as_bad (_("Predicate source and target required"));
4586 else if (p1
== 0 || p2
== 0)
4587 as_bad (_("Use of p0 is not valid in this context"));
4589 add_qp_imply (p1
, p2
);
4594 as_bad (_("At least two PR arguments expected"));
4599 as_bad (_("Use of p0 is not valid in this context"));
4602 add_qp_mutex (mask
);
4605 /* note that we don't override any existing relations */
4608 as_bad (_("At least one PR argument expected"));
4613 fprintf (stderr
, "Safe across calls: ");
4614 print_prmask (mask
);
4615 fprintf (stderr
, "\n");
4617 qp_safe_across_calls
= mask
;
4620 demand_empty_rest_of_line ();
4623 /* .entry label [, label [, ...]]
4624 Hint to DV code that the given labels are to be considered entry points.
4625 Otherwise, only global labels are considered entry points. */
4629 int dummy ATTRIBUTE_UNUSED
;
4638 name
= input_line_pointer
;
4639 c
= get_symbol_end ();
4640 symbolP
= symbol_find_or_make (name
);
4642 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4644 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4647 *input_line_pointer
= c
;
4649 c
= *input_line_pointer
;
4652 input_line_pointer
++;
4654 if (*input_line_pointer
== '\n')
4660 demand_empty_rest_of_line ();
4663 /* .mem.offset offset, base
4664 "base" is used to distinguish between offsets from a different base. */
4667 dot_mem_offset (dummy
)
4668 int dummy ATTRIBUTE_UNUSED
;
4670 md
.mem_offset
.hint
= 1;
4671 md
.mem_offset
.offset
= get_absolute_expression ();
4672 if (*input_line_pointer
!= ',')
4674 as_bad (_("Comma expected"));
4675 ignore_rest_of_line ();
4678 ++input_line_pointer
;
4679 md
.mem_offset
.base
= get_absolute_expression ();
4680 demand_empty_rest_of_line ();
4683 /* ia64-specific pseudo-ops: */
4684 const pseudo_typeS md_pseudo_table
[] =
4686 { "radix", dot_radix
, 0 },
4687 { "lcomm", s_lcomm_bytes
, 1 },
4688 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4689 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4690 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4691 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4692 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4693 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4694 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4695 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4696 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4697 { "proc", dot_proc
, 0 },
4698 { "body", dot_body
, 0 },
4699 { "prologue", dot_prologue
, 0 },
4700 { "endp", dot_endp
, 0 },
4701 { "file", dwarf2_directive_file
, 0 },
4702 { "loc", dwarf2_directive_loc
, 0 },
4704 { "fframe", dot_fframe
, 0 },
4705 { "vframe", dot_vframe
, 0 },
4706 { "vframesp", dot_vframesp
, 0 },
4707 { "vframepsp", dot_vframepsp
, 0 },
4708 { "save", dot_save
, 0 },
4709 { "restore", dot_restore
, 0 },
4710 { "restorereg", dot_restorereg
, 0 },
4711 { "restorereg.p", dot_restorereg_p
, 0 },
4712 { "handlerdata", dot_handlerdata
, 0 },
4713 { "unwentry", dot_unwentry
, 0 },
4714 { "altrp", dot_altrp
, 0 },
4715 { "savesp", dot_savemem
, 0 },
4716 { "savepsp", dot_savemem
, 1 },
4717 { "save.g", dot_saveg
, 0 },
4718 { "save.f", dot_savef
, 0 },
4719 { "save.b", dot_saveb
, 0 },
4720 { "save.gf", dot_savegf
, 0 },
4721 { "spill", dot_spill
, 0 },
4722 { "spillreg", dot_spillreg
, 0 },
4723 { "spillsp", dot_spillmem
, 0 },
4724 { "spillpsp", dot_spillmem
, 1 },
4725 { "spillreg.p", dot_spillreg_p
, 0 },
4726 { "spillsp.p", dot_spillmem_p
, 0 },
4727 { "spillpsp.p", dot_spillmem_p
, 1 },
4728 { "label_state", dot_label_state
, 0 },
4729 { "copy_state", dot_copy_state
, 0 },
4730 { "unwabi", dot_unwabi
, 0 },
4731 { "personality", dot_personality
, 0 },
4733 { "estate", dot_estate
, 0 },
4735 { "mii", dot_template
, 0x0 },
4736 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4737 { "mlx", dot_template
, 0x2 },
4738 { "mmi", dot_template
, 0x4 },
4739 { "mfi", dot_template
, 0x6 },
4740 { "mmf", dot_template
, 0x7 },
4741 { "mib", dot_template
, 0x8 },
4742 { "mbb", dot_template
, 0x9 },
4743 { "bbb", dot_template
, 0xb },
4744 { "mmb", dot_template
, 0xc },
4745 { "mfb", dot_template
, 0xe },
4747 { "lb", dot_scope
, 0 },
4748 { "le", dot_scope
, 1 },
4750 { "align", s_align_bytes
, 0 },
4751 { "regstk", dot_regstk
, 0 },
4752 { "rotr", dot_rot
, DYNREG_GR
},
4753 { "rotf", dot_rot
, DYNREG_FR
},
4754 { "rotp", dot_rot
, DYNREG_PR
},
4755 { "lsb", dot_byteorder
, 0 },
4756 { "msb", dot_byteorder
, 1 },
4757 { "psr", dot_psr
, 0 },
4758 { "alias", dot_alias
, 0 },
4759 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4761 { "xdata1", dot_xdata
, 1 },
4762 { "xdata2", dot_xdata
, 2 },
4763 { "xdata4", dot_xdata
, 4 },
4764 { "xdata8", dot_xdata
, 8 },
4765 { "xreal4", dot_xfloat_cons
, 'f' },
4766 { "xreal8", dot_xfloat_cons
, 'd' },
4767 { "xreal10", dot_xfloat_cons
, 'x' },
4768 { "xstring", dot_xstringer
, 0 },
4769 { "xstringz", dot_xstringer
, 1 },
4771 /* unaligned versions: */
4772 { "xdata2.ua", dot_xdata_ua
, 2 },
4773 { "xdata4.ua", dot_xdata_ua
, 4 },
4774 { "xdata8.ua", dot_xdata_ua
, 8 },
4775 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4776 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4777 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4779 /* annotations/DV checking support */
4780 { "entry", dot_entry
, 0 },
4781 { "mem.offset", dot_mem_offset
, 0 },
4782 { "pred.rel", dot_pred_rel
, 0 },
4783 { "pred.rel.clear", dot_pred_rel
, 'c' },
4784 { "pred.rel.imply", dot_pred_rel
, 'i' },
4785 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4786 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4787 { "reg.val", dot_reg_val
, 0 },
4788 { "auto", dot_dv_mode
, 'a' },
4789 { "explicit", dot_dv_mode
, 'e' },
4790 { "default", dot_dv_mode
, 'd' },
4792 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4793 IA-64 aligns data allocation pseudo-ops by default, so we have to
4794 tell it that these ones are supposed to be unaligned. Long term,
4795 should rewrite so that only IA-64 specific data allocation pseudo-ops
4796 are aligned by default. */
4797 {"2byte", stmt_cons_ua
, 2},
4798 {"4byte", stmt_cons_ua
, 4},
4799 {"8byte", stmt_cons_ua
, 8},
4804 static const struct pseudo_opcode
4807 void (*handler
) (int);
4812 /* these are more like pseudo-ops, but don't start with a dot */
4813 { "data1", cons
, 1 },
4814 { "data2", cons
, 2 },
4815 { "data4", cons
, 4 },
4816 { "data8", cons
, 8 },
4817 { "data16", cons
, 16 },
4818 { "real4", stmt_float_cons
, 'f' },
4819 { "real8", stmt_float_cons
, 'd' },
4820 { "real10", stmt_float_cons
, 'x' },
4821 { "string", stringer
, 0 },
4822 { "stringz", stringer
, 1 },
4824 /* unaligned versions: */
4825 { "data2.ua", stmt_cons_ua
, 2 },
4826 { "data4.ua", stmt_cons_ua
, 4 },
4827 { "data8.ua", stmt_cons_ua
, 8 },
4828 { "data16.ua", stmt_cons_ua
, 16 },
4829 { "real4.ua", float_cons
, 'f' },
4830 { "real8.ua", float_cons
, 'd' },
4831 { "real10.ua", float_cons
, 'x' },
4834 /* Declare a register by creating a symbol for it and entering it in
4835 the symbol table. */
4838 declare_register (name
, regnum
)
4845 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4847 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4849 as_fatal ("Inserting \"%s\" into register table failed: %s",
4856 declare_register_set (prefix
, num_regs
, base_regnum
)
4864 for (i
= 0; i
< num_regs
; ++i
)
4866 sprintf (name
, "%s%u", prefix
, i
);
4867 declare_register (name
, base_regnum
+ i
);
4872 operand_width (opnd
)
4873 enum ia64_opnd opnd
;
4875 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4876 unsigned int bits
= 0;
4880 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4881 bits
+= odesc
->field
[i
].bits
;
4886 static enum operand_match_result
4887 operand_match (idesc
, index
, e
)
4888 const struct ia64_opcode
*idesc
;
4892 enum ia64_opnd opnd
= idesc
->operands
[index
];
4893 int bits
, relocatable
= 0;
4894 struct insn_fix
*fix
;
4901 case IA64_OPND_AR_CCV
:
4902 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4903 return OPERAND_MATCH
;
4906 case IA64_OPND_AR_PFS
:
4907 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4908 return OPERAND_MATCH
;
4912 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4913 return OPERAND_MATCH
;
4917 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4918 return OPERAND_MATCH
;
4922 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4923 return OPERAND_MATCH
;
4926 case IA64_OPND_PR_ROT
:
4927 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4928 return OPERAND_MATCH
;
4932 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4933 return OPERAND_MATCH
;
4936 case IA64_OPND_PSR_L
:
4937 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4938 return OPERAND_MATCH
;
4941 case IA64_OPND_PSR_UM
:
4942 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4943 return OPERAND_MATCH
;
4947 if (e
->X_op
== O_constant
)
4949 if (e
->X_add_number
== 1)
4950 return OPERAND_MATCH
;
4952 return OPERAND_OUT_OF_RANGE
;
4957 if (e
->X_op
== O_constant
)
4959 if (e
->X_add_number
== 8)
4960 return OPERAND_MATCH
;
4962 return OPERAND_OUT_OF_RANGE
;
4967 if (e
->X_op
== O_constant
)
4969 if (e
->X_add_number
== 16)
4970 return OPERAND_MATCH
;
4972 return OPERAND_OUT_OF_RANGE
;
4976 /* register operands: */
4979 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4980 && e
->X_add_number
< REG_AR
+ 128)
4981 return OPERAND_MATCH
;
4986 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4987 && e
->X_add_number
< REG_BR
+ 8)
4988 return OPERAND_MATCH
;
4992 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4993 && e
->X_add_number
< REG_CR
+ 128)
4994 return OPERAND_MATCH
;
5001 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
5002 && e
->X_add_number
< REG_FR
+ 128)
5003 return OPERAND_MATCH
;
5008 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
5009 && e
->X_add_number
< REG_P
+ 64)
5010 return OPERAND_MATCH
;
5016 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
5017 && e
->X_add_number
< REG_GR
+ 128)
5018 return OPERAND_MATCH
;
5021 case IA64_OPND_R3_2
:
5022 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5024 if (e
->X_add_number
< REG_GR
+ 4)
5025 return OPERAND_MATCH
;
5026 else if (e
->X_add_number
< REG_GR
+ 128)
5027 return OPERAND_OUT_OF_RANGE
;
5031 /* indirect operands: */
5032 case IA64_OPND_CPUID_R3
:
5033 case IA64_OPND_DBR_R3
:
5034 case IA64_OPND_DTR_R3
:
5035 case IA64_OPND_ITR_R3
:
5036 case IA64_OPND_IBR_R3
:
5037 case IA64_OPND_MSR_R3
:
5038 case IA64_OPND_PKR_R3
:
5039 case IA64_OPND_PMC_R3
:
5040 case IA64_OPND_PMD_R3
:
5041 case IA64_OPND_RR_R3
:
5042 if (e
->X_op
== O_index
&& e
->X_op_symbol
5043 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5044 == opnd
- IA64_OPND_CPUID_R3
))
5045 return OPERAND_MATCH
;
5049 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5050 return OPERAND_MATCH
;
5053 /* immediate operands: */
5054 case IA64_OPND_CNT2a
:
5055 case IA64_OPND_LEN4
:
5056 case IA64_OPND_LEN6
:
5057 bits
= operand_width (idesc
->operands
[index
]);
5058 if (e
->X_op
== O_constant
)
5060 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5061 return OPERAND_MATCH
;
5063 return OPERAND_OUT_OF_RANGE
;
5067 case IA64_OPND_CNT2b
:
5068 if (e
->X_op
== O_constant
)
5070 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5071 return OPERAND_MATCH
;
5073 return OPERAND_OUT_OF_RANGE
;
5077 case IA64_OPND_CNT2c
:
5078 val
= e
->X_add_number
;
5079 if (e
->X_op
== O_constant
)
5081 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5082 return OPERAND_MATCH
;
5084 return OPERAND_OUT_OF_RANGE
;
5089 /* SOR must be an integer multiple of 8 */
5090 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5091 return OPERAND_OUT_OF_RANGE
;
5094 if (e
->X_op
== O_constant
)
5096 if ((bfd_vma
) e
->X_add_number
<= 96)
5097 return OPERAND_MATCH
;
5099 return OPERAND_OUT_OF_RANGE
;
5103 case IA64_OPND_IMMU62
:
5104 if (e
->X_op
== O_constant
)
5106 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5107 return OPERAND_MATCH
;
5109 return OPERAND_OUT_OF_RANGE
;
5113 /* FIXME -- need 62-bit relocation type */
5114 as_bad (_("62-bit relocation not yet implemented"));
5118 case IA64_OPND_IMMU64
:
5119 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5120 || e
->X_op
== O_subtract
)
5122 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5123 fix
->code
= BFD_RELOC_IA64_IMM64
;
5124 if (e
->X_op
!= O_subtract
)
5126 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5127 if (e
->X_op
== O_pseudo_fixup
)
5131 fix
->opnd
= idesc
->operands
[index
];
5134 ++CURR_SLOT
.num_fixups
;
5135 return OPERAND_MATCH
;
5137 else if (e
->X_op
== O_constant
)
5138 return OPERAND_MATCH
;
5141 case IA64_OPND_CCNT5
:
5142 case IA64_OPND_CNT5
:
5143 case IA64_OPND_CNT6
:
5144 case IA64_OPND_CPOS6a
:
5145 case IA64_OPND_CPOS6b
:
5146 case IA64_OPND_CPOS6c
:
5147 case IA64_OPND_IMMU2
:
5148 case IA64_OPND_IMMU7a
:
5149 case IA64_OPND_IMMU7b
:
5150 case IA64_OPND_IMMU21
:
5151 case IA64_OPND_IMMU24
:
5152 case IA64_OPND_MBTYPE4
:
5153 case IA64_OPND_MHTYPE8
:
5154 case IA64_OPND_POS6
:
5155 bits
= operand_width (idesc
->operands
[index
]);
5156 if (e
->X_op
== O_constant
)
5158 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5159 return OPERAND_MATCH
;
5161 return OPERAND_OUT_OF_RANGE
;
5165 case IA64_OPND_IMMU9
:
5166 bits
= operand_width (idesc
->operands
[index
]);
5167 if (e
->X_op
== O_constant
)
5169 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5171 int lobits
= e
->X_add_number
& 0x3;
5172 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5173 e
->X_add_number
|= (bfd_vma
) 0x3;
5174 return OPERAND_MATCH
;
5177 return OPERAND_OUT_OF_RANGE
;
5181 case IA64_OPND_IMM44
:
5182 /* least 16 bits must be zero */
5183 if ((e
->X_add_number
& 0xffff) != 0)
5184 /* XXX technically, this is wrong: we should not be issuing warning
5185 messages until we're sure this instruction pattern is going to
5187 as_warn (_("lower 16 bits of mask ignored"));
5189 if (e
->X_op
== O_constant
)
5191 if (((e
->X_add_number
>= 0
5192 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5193 || (e
->X_add_number
< 0
5194 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5197 if (e
->X_add_number
>= 0
5198 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5200 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5202 return OPERAND_MATCH
;
5205 return OPERAND_OUT_OF_RANGE
;
5209 case IA64_OPND_IMM17
:
5210 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5211 if (e
->X_op
== O_constant
)
5213 if (((e
->X_add_number
>= 0
5214 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5215 || (e
->X_add_number
< 0
5216 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5219 if (e
->X_add_number
>= 0
5220 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5222 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5224 return OPERAND_MATCH
;
5227 return OPERAND_OUT_OF_RANGE
;
5231 case IA64_OPND_IMM14
:
5232 case IA64_OPND_IMM22
:
5234 case IA64_OPND_IMM1
:
5235 case IA64_OPND_IMM8
:
5236 case IA64_OPND_IMM8U4
:
5237 case IA64_OPND_IMM8M1
:
5238 case IA64_OPND_IMM8M1U4
:
5239 case IA64_OPND_IMM8M1U8
:
5240 case IA64_OPND_IMM9a
:
5241 case IA64_OPND_IMM9b
:
5242 bits
= operand_width (idesc
->operands
[index
]);
5243 if (relocatable
&& (e
->X_op
== O_symbol
5244 || e
->X_op
== O_subtract
5245 || e
->X_op
== O_pseudo_fixup
))
5247 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5249 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5250 fix
->code
= BFD_RELOC_IA64_IMM14
;
5252 fix
->code
= BFD_RELOC_IA64_IMM22
;
5254 if (e
->X_op
!= O_subtract
)
5256 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5257 if (e
->X_op
== O_pseudo_fixup
)
5261 fix
->opnd
= idesc
->operands
[index
];
5264 ++CURR_SLOT
.num_fixups
;
5265 return OPERAND_MATCH
;
5267 else if (e
->X_op
!= O_constant
5268 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5269 return OPERAND_MISMATCH
;
5271 if (opnd
== IA64_OPND_IMM8M1U4
)
5273 /* Zero is not valid for unsigned compares that take an adjusted
5274 constant immediate range. */
5275 if (e
->X_add_number
== 0)
5276 return OPERAND_OUT_OF_RANGE
;
5278 /* Sign-extend 32-bit unsigned numbers, so that the following range
5279 checks will work. */
5280 val
= e
->X_add_number
;
5281 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5282 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5283 val
= ((val
<< 32) >> 32);
5285 /* Check for 0x100000000. This is valid because
5286 0x100000000-1 is the same as ((uint32_t) -1). */
5287 if (val
== ((bfd_signed_vma
) 1 << 32))
5288 return OPERAND_MATCH
;
5292 else if (opnd
== IA64_OPND_IMM8M1U8
)
5294 /* Zero is not valid for unsigned compares that take an adjusted
5295 constant immediate range. */
5296 if (e
->X_add_number
== 0)
5297 return OPERAND_OUT_OF_RANGE
;
5299 /* Check for 0x10000000000000000. */
5300 if (e
->X_op
== O_big
)
5302 if (generic_bignum
[0] == 0
5303 && generic_bignum
[1] == 0
5304 && generic_bignum
[2] == 0
5305 && generic_bignum
[3] == 0
5306 && generic_bignum
[4] == 1)
5307 return OPERAND_MATCH
;
5309 return OPERAND_OUT_OF_RANGE
;
5312 val
= e
->X_add_number
- 1;
5314 else if (opnd
== IA64_OPND_IMM8M1
)
5315 val
= e
->X_add_number
- 1;
5316 else if (opnd
== IA64_OPND_IMM8U4
)
5318 /* Sign-extend 32-bit unsigned numbers, so that the following range
5319 checks will work. */
5320 val
= e
->X_add_number
;
5321 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5322 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5323 val
= ((val
<< 32) >> 32);
5326 val
= e
->X_add_number
;
5328 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5329 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5330 return OPERAND_MATCH
;
5332 return OPERAND_OUT_OF_RANGE
;
5334 case IA64_OPND_INC3
:
5335 /* +/- 1, 4, 8, 16 */
5336 val
= e
->X_add_number
;
5339 if (e
->X_op
== O_constant
)
5341 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5342 return OPERAND_MATCH
;
5344 return OPERAND_OUT_OF_RANGE
;
5348 case IA64_OPND_TGT25
:
5349 case IA64_OPND_TGT25b
:
5350 case IA64_OPND_TGT25c
:
5351 case IA64_OPND_TGT64
:
5352 if (e
->X_op
== O_symbol
)
5354 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5355 if (opnd
== IA64_OPND_TGT25
)
5356 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5357 else if (opnd
== IA64_OPND_TGT25b
)
5358 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5359 else if (opnd
== IA64_OPND_TGT25c
)
5360 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5361 else if (opnd
== IA64_OPND_TGT64
)
5362 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5366 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5367 fix
->opnd
= idesc
->operands
[index
];
5370 ++CURR_SLOT
.num_fixups
;
5371 return OPERAND_MATCH
;
5373 case IA64_OPND_TAG13
:
5374 case IA64_OPND_TAG13b
:
5378 return OPERAND_MATCH
;
5381 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5382 /* There are no external relocs for TAG13/TAG13b fields, so we
5383 create a dummy reloc. This will not live past md_apply_fix3. */
5384 fix
->code
= BFD_RELOC_UNUSED
;
5385 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5386 fix
->opnd
= idesc
->operands
[index
];
5389 ++CURR_SLOT
.num_fixups
;
5390 return OPERAND_MATCH
;
5400 return OPERAND_MISMATCH
;
5409 memset (e
, 0, sizeof (*e
));
5412 if (*input_line_pointer
!= '}')
5414 sep
= *input_line_pointer
++;
5418 if (!md
.manual_bundling
)
5419 as_warn ("Found '}' when manual bundling is off");
5421 CURR_SLOT
.manual_bundling_off
= 1;
5422 md
.manual_bundling
= 0;
5428 /* Returns the next entry in the opcode table that matches the one in
5429 IDESC, and frees the entry in IDESC. If no matching entry is
5430 found, NULL is returned instead. */
5432 static struct ia64_opcode
*
5433 get_next_opcode (struct ia64_opcode
*idesc
)
5435 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5436 ia64_free_opcode (idesc
);
5440 /* Parse the operands for the opcode and find the opcode variant that
5441 matches the specified operands, or NULL if no match is possible. */
5443 static struct ia64_opcode
*
5444 parse_operands (idesc
)
5445 struct ia64_opcode
*idesc
;
5447 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5448 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5449 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5450 enum operand_match_result result
;
5452 char *first_arg
= 0, *end
, *saved_input_pointer
;
5455 assert (strlen (idesc
->name
) <= 128);
5457 strcpy (mnemonic
, idesc
->name
);
5458 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5460 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5461 can't parse the first operand until we have parsed the
5462 remaining operands of the "alloc" instruction. */
5464 first_arg
= input_line_pointer
;
5465 end
= strchr (input_line_pointer
, '=');
5468 as_bad ("Expected separator `='");
5471 input_line_pointer
= end
+ 1;
5476 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5478 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5479 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5484 if (sep
!= '=' && sep
!= ',')
5489 if (num_outputs
> 0)
5490 as_bad ("Duplicate equal sign (=) in instruction");
5492 num_outputs
= i
+ 1;
5497 as_bad ("Illegal operand separator `%c'", sep
);
5501 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5503 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5504 know (strcmp (idesc
->name
, "alloc") == 0);
5505 if (num_operands
== 5 /* first_arg not included in this count! */
5506 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5507 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5508 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5509 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5511 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5512 CURR_SLOT
.opnd
[3].X_add_number
,
5513 CURR_SLOT
.opnd
[4].X_add_number
,
5514 CURR_SLOT
.opnd
[5].X_add_number
);
5516 /* now we can parse the first arg: */
5517 saved_input_pointer
= input_line_pointer
;
5518 input_line_pointer
= first_arg
;
5519 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5521 --num_outputs
; /* force error */
5522 input_line_pointer
= saved_input_pointer
;
5524 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5525 CURR_SLOT
.opnd
[3].X_add_number
5526 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5527 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5531 highest_unmatched_operand
= 0;
5532 curr_out_of_range_pos
= -1;
5534 expected_operand
= idesc
->operands
[0];
5535 for (; idesc
; idesc
= get_next_opcode (idesc
))
5537 if (num_outputs
!= idesc
->num_outputs
)
5538 continue; /* mismatch in # of outputs */
5540 CURR_SLOT
.num_fixups
= 0;
5542 /* Try to match all operands. If we see an out-of-range operand,
5543 then continue trying to match the rest of the operands, since if
5544 the rest match, then this idesc will give the best error message. */
5546 out_of_range_pos
= -1;
5547 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5549 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5550 if (result
!= OPERAND_MATCH
)
5552 if (result
!= OPERAND_OUT_OF_RANGE
)
5554 if (out_of_range_pos
< 0)
5555 /* remember position of the first out-of-range operand: */
5556 out_of_range_pos
= i
;
5560 /* If we did not match all operands, or if at least one operand was
5561 out-of-range, then this idesc does not match. Keep track of which
5562 idesc matched the most operands before failing. If we have two
5563 idescs that failed at the same position, and one had an out-of-range
5564 operand, then prefer the out-of-range operand. Thus if we have
5565 "add r0=0x1000000,r1" we get an error saying the constant is out
5566 of range instead of an error saying that the constant should have been
5569 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5571 if (i
> highest_unmatched_operand
5572 || (i
== highest_unmatched_operand
5573 && out_of_range_pos
> curr_out_of_range_pos
))
5575 highest_unmatched_operand
= i
;
5576 if (out_of_range_pos
>= 0)
5578 expected_operand
= idesc
->operands
[out_of_range_pos
];
5579 error_pos
= out_of_range_pos
;
5583 expected_operand
= idesc
->operands
[i
];
5586 curr_out_of_range_pos
= out_of_range_pos
;
5591 if (num_operands
< NELEMS (idesc
->operands
)
5592 && idesc
->operands
[num_operands
])
5593 continue; /* mismatch in number of arguments */
5599 if (expected_operand
)
5600 as_bad ("Operand %u of `%s' should be %s",
5601 error_pos
+ 1, mnemonic
,
5602 elf64_ia64_operands
[expected_operand
].desc
);
5604 as_bad ("Operand mismatch");
5610 /* Keep track of state necessary to determine whether a NOP is necessary
5611 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5612 detect a case where additional NOPs may be necessary. */
5614 errata_nop_necessary_p (slot
, insn_unit
)
5616 enum ia64_unit insn_unit
;
5619 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5620 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5621 struct ia64_opcode
*idesc
= slot
->idesc
;
5623 /* Test whether this could be the first insn in a problematic sequence. */
5624 if (insn_unit
== IA64_UNIT_F
)
5626 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5627 if (idesc
->operands
[i
] == IA64_OPND_P1
5628 || idesc
->operands
[i
] == IA64_OPND_P2
)
5630 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5631 /* Ignore invalid operands; they generate errors elsewhere. */
5634 this_group
->p_reg_set
[regno
] = 1;
5638 /* Test whether this could be the second insn in a problematic sequence. */
5639 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5640 && prev_group
->p_reg_set
[slot
->qp_regno
])
5642 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5643 if (idesc
->operands
[i
] == IA64_OPND_R1
5644 || idesc
->operands
[i
] == IA64_OPND_R2
5645 || idesc
->operands
[i
] == IA64_OPND_R3
)
5647 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5648 /* Ignore invalid operands; they generate errors elsewhere. */
5651 if (strncmp (idesc
->name
, "add", 3) != 0
5652 && strncmp (idesc
->name
, "sub", 3) != 0
5653 && strncmp (idesc
->name
, "shladd", 6) != 0
5654 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5655 this_group
->g_reg_set_conditionally
[regno
] = 1;
5659 /* Test whether this could be the third insn in a problematic sequence. */
5660 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5662 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5663 idesc
->operands
[i
] == IA64_OPND_R3
5664 /* For mov indirect. */
5665 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5666 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5667 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5668 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5669 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5670 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5671 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5672 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5674 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5675 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5676 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5677 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5679 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5680 /* Ignore invalid operands; they generate errors elsewhere. */
5683 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5685 if (strcmp (idesc
->name
, "fc") != 0
5686 && strcmp (idesc
->name
, "tak") != 0
5687 && strcmp (idesc
->name
, "thash") != 0
5688 && strcmp (idesc
->name
, "tpa") != 0
5689 && strcmp (idesc
->name
, "ttag") != 0
5690 && strncmp (idesc
->name
, "ptr", 3) != 0
5691 && strncmp (idesc
->name
, "ptc", 3) != 0
5692 && strncmp (idesc
->name
, "probe", 5) != 0)
5695 if (prev_group
->g_reg_set_conditionally
[regno
])
5703 build_insn (slot
, insnp
)
5707 const struct ia64_operand
*odesc
, *o2desc
;
5708 struct ia64_opcode
*idesc
= slot
->idesc
;
5709 bfd_signed_vma insn
, val
;
5713 insn
= idesc
->opcode
| slot
->qp_regno
;
5715 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5717 if (slot
->opnd
[i
].X_op
== O_register
5718 || slot
->opnd
[i
].X_op
== O_constant
5719 || slot
->opnd
[i
].X_op
== O_index
)
5720 val
= slot
->opnd
[i
].X_add_number
;
5721 else if (slot
->opnd
[i
].X_op
== O_big
)
5723 /* This must be the value 0x10000000000000000. */
5724 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5730 switch (idesc
->operands
[i
])
5732 case IA64_OPND_IMMU64
:
5733 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5734 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5735 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5736 | (((val
>> 63) & 0x1) << 36));
5739 case IA64_OPND_IMMU62
:
5740 val
&= 0x3fffffffffffffffULL
;
5741 if (val
!= slot
->opnd
[i
].X_add_number
)
5742 as_warn (_("Value truncated to 62 bits"));
5743 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5744 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5747 case IA64_OPND_TGT64
:
5749 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5750 insn
|= ((((val
>> 59) & 0x1) << 36)
5751 | (((val
>> 0) & 0xfffff) << 13));
5782 case IA64_OPND_R3_2
:
5783 case IA64_OPND_CPUID_R3
:
5784 case IA64_OPND_DBR_R3
:
5785 case IA64_OPND_DTR_R3
:
5786 case IA64_OPND_ITR_R3
:
5787 case IA64_OPND_IBR_R3
:
5789 case IA64_OPND_MSR_R3
:
5790 case IA64_OPND_PKR_R3
:
5791 case IA64_OPND_PMC_R3
:
5792 case IA64_OPND_PMD_R3
:
5793 case IA64_OPND_RR_R3
:
5801 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5802 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5804 as_bad_where (slot
->src_file
, slot
->src_line
,
5805 "Bad operand value: %s", err
);
5806 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5808 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5809 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5811 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5812 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5814 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5815 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5816 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5818 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5819 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5829 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5830 unsigned int manual_bundling
= 0;
5831 enum ia64_unit required_unit
, insn_unit
= 0;
5832 enum ia64_insn_type type
[3], insn_type
;
5833 unsigned int template, orig_template
;
5834 bfd_vma insn
[3] = { -1, -1, -1 };
5835 struct ia64_opcode
*idesc
;
5836 int end_of_insn_group
= 0, user_template
= -1;
5837 int n
, i
, j
, first
, curr
;
5839 bfd_vma t0
= 0, t1
= 0;
5840 struct label_fix
*lfix
;
5841 struct insn_fix
*ifix
;
5846 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5847 know (first
>= 0 & first
< NUM_SLOTS
);
5848 n
= MIN (3, md
.num_slots_in_use
);
5850 /* Determine template: user user_template if specified, best match
5853 if (md
.slot
[first
].user_template
>= 0)
5854 user_template
= template = md
.slot
[first
].user_template
;
5857 /* Auto select appropriate template. */
5858 memset (type
, 0, sizeof (type
));
5860 for (i
= 0; i
< n
; ++i
)
5862 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5864 type
[i
] = md
.slot
[curr
].idesc
->type
;
5865 curr
= (curr
+ 1) % NUM_SLOTS
;
5867 template = best_template
[type
[0]][type
[1]][type
[2]];
5870 /* initialize instructions with appropriate nops: */
5871 for (i
= 0; i
< 3; ++i
)
5872 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5876 /* now fill in slots with as many insns as possible: */
5878 idesc
= md
.slot
[curr
].idesc
;
5879 end_of_insn_group
= 0;
5880 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5882 /* Set the slot number for prologue/body records now as those
5883 refer to the current point, not the point after the
5884 instruction has been issued: */
5885 /* Don't try to delete prologue/body records here, as that will cause
5886 them to also be deleted from the master list of unwind records. */
5887 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5888 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5889 || ptr
->r
.type
== body
)
5891 ptr
->slot_number
= (unsigned long) f
+ i
;
5892 ptr
->slot_frag
= frag_now
;
5895 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5897 if (manual_bundling
&& i
!= 2)
5898 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5899 "`%s' must be last in bundle", idesc
->name
);
5903 if (idesc
->flags
& IA64_OPCODE_LAST
)
5906 unsigned int required_template
;
5908 /* If we need a stop bit after an M slot, our only choice is
5909 template 5 (M;;MI). If we need a stop bit after a B
5910 slot, our only choice is to place it at the end of the
5911 bundle, because the only available templates are MIB,
5912 MBB, BBB, MMB, and MFB. We don't handle anything other
5913 than M and B slots because these are the only kind of
5914 instructions that can have the IA64_OPCODE_LAST bit set. */
5915 required_template
= template;
5916 switch (idesc
->type
)
5920 required_template
= 5;
5928 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5929 "Internal error: don't know how to force %s to end"
5930 "of instruction group", idesc
->name
);
5934 if (manual_bundling
&& i
!= required_slot
)
5935 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5936 "`%s' must be last in instruction group",
5938 if (required_slot
< i
)
5939 /* Can't fit this instruction. */
5943 if (required_template
!= template)
5945 /* If we switch the template, we need to reset the NOPs
5946 after slot i. The slot-types of the instructions ahead
5947 of i never change, so we don't need to worry about
5948 changing NOPs in front of this slot. */
5949 for (j
= i
; j
< 3; ++j
)
5950 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5952 template = required_template
;
5954 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5956 if (manual_bundling_on
)
5957 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5958 "Label must be first in a bundle");
5959 /* This insn must go into the first slot of a bundle. */
5963 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5964 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5966 if (manual_bundling_on
)
5969 manual_bundling
= 1;
5971 break; /* need to start a new bundle */
5974 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5976 /* We need an instruction group boundary in the middle of a
5977 bundle. See if we can switch to an other template with
5978 an appropriate boundary. */
5980 orig_template
= template;
5981 if (i
== 1 && (user_template
== 4
5982 || (user_template
< 0
5983 && (ia64_templ_desc
[template].exec_unit
[0]
5987 end_of_insn_group
= 0;
5989 else if (i
== 2 && (user_template
== 0
5990 || (user_template
< 0
5991 && (ia64_templ_desc
[template].exec_unit
[1]
5993 /* This test makes sure we don't switch the template if
5994 the next instruction is one that needs to be first in
5995 an instruction group. Since all those instructions are
5996 in the M group, there is no way such an instruction can
5997 fit in this bundle even if we switch the template. The
5998 reason we have to check for this is that otherwise we
5999 may end up generating "MI;;I M.." which has the deadly
6000 effect that the second M instruction is no longer the
6001 first in the bundle! --davidm 99/12/16 */
6002 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
6005 end_of_insn_group
= 0;
6007 else if (curr
!= first
)
6008 /* can't fit this insn */
6011 if (template != orig_template
)
6012 /* if we switch the template, we need to reset the NOPs
6013 after slot i. The slot-types of the instructions ahead
6014 of i never change, so we don't need to worry about
6015 changing NOPs in front of this slot. */
6016 for (j
= i
; j
< 3; ++j
)
6017 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
6019 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6021 /* resolve dynamic opcodes such as "break" and "nop": */
6022 if (idesc
->type
== IA64_TYPE_DYN
)
6024 if ((strcmp (idesc
->name
, "nop") == 0)
6025 || (strcmp (idesc
->name
, "break") == 0))
6026 insn_unit
= required_unit
;
6027 else if (strcmp (idesc
->name
, "chk.s") == 0)
6029 insn_unit
= IA64_UNIT_M
;
6030 if (required_unit
== IA64_UNIT_I
)
6031 insn_unit
= IA64_UNIT_I
;
6034 as_fatal ("emit_one_bundle: unexpected dynamic op");
6036 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6037 ia64_free_opcode (idesc
);
6038 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6040 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6045 insn_type
= idesc
->type
;
6046 insn_unit
= IA64_UNIT_NIL
;
6050 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6051 insn_unit
= required_unit
;
6053 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6054 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6055 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6056 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6057 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6062 if (insn_unit
!= required_unit
)
6064 if (required_unit
== IA64_UNIT_L
6065 && insn_unit
== IA64_UNIT_I
6066 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6068 /* we got ourselves an MLX template but the current
6069 instruction isn't an X-unit, or an I-unit instruction
6070 that can go into the X slot of an MLX template. Duh. */
6071 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6073 as_bad_where (md
.slot
[curr
].src_file
,
6074 md
.slot
[curr
].src_line
,
6075 "`%s' can't go in X slot of "
6076 "MLX template", idesc
->name
);
6077 /* drop this insn so we don't livelock: */
6078 --md
.num_slots_in_use
;
6082 continue; /* try next slot */
6088 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6089 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6092 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6093 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6095 build_insn (md
.slot
+ curr
, insn
+ i
);
6097 /* Set slot counts for non prologue/body unwind records. */
6098 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6099 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6100 && ptr
->r
.type
!= body
)
6102 ptr
->slot_number
= (unsigned long) f
+ i
;
6103 ptr
->slot_frag
= frag_now
;
6105 md
.slot
[curr
].unwind_record
= NULL
;
6107 if (required_unit
== IA64_UNIT_L
)
6110 /* skip one slot for long/X-unit instructions */
6113 --md
.num_slots_in_use
;
6115 /* now is a good time to fix up the labels for this insn: */
6116 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6118 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6119 symbol_set_frag (lfix
->sym
, frag_now
);
6121 /* and fix up the tags also. */
6122 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6124 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6125 symbol_set_frag (lfix
->sym
, frag_now
);
6128 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6130 ifix
= md
.slot
[curr
].fixup
+ j
;
6131 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6132 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6133 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6134 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6135 fix
->fx_file
= md
.slot
[curr
].src_file
;
6136 fix
->fx_line
= md
.slot
[curr
].src_line
;
6139 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6141 if (end_of_insn_group
)
6143 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6144 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6148 ia64_free_opcode (md
.slot
[curr
].idesc
);
6149 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6150 md
.slot
[curr
].user_template
= -1;
6152 if (manual_bundling_off
)
6154 manual_bundling
= 0;
6157 curr
= (curr
+ 1) % NUM_SLOTS
;
6158 idesc
= md
.slot
[curr
].idesc
;
6160 if (manual_bundling
)
6162 if (md
.num_slots_in_use
> 0)
6163 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6164 "`%s' does not fit into %s template",
6165 idesc
->name
, ia64_templ_desc
[template].name
);
6167 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6168 "Missing '}' at end of file");
6170 know (md
.num_slots_in_use
< NUM_SLOTS
);
6172 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6173 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6175 number_to_chars_littleendian (f
+ 0, t0
, 8);
6176 number_to_chars_littleendian (f
+ 8, t1
, 8);
6178 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6179 unwind
.next_slot_frag
= frag_now
;
6183 md_parse_option (c
, arg
)
6190 /* Switches from the Intel assembler. */
6192 if (strcmp (arg
, "ilp64") == 0
6193 || strcmp (arg
, "lp64") == 0
6194 || strcmp (arg
, "p64") == 0)
6196 md
.flags
|= EF_IA_64_ABI64
;
6198 else if (strcmp (arg
, "ilp32") == 0)
6200 md
.flags
&= ~EF_IA_64_ABI64
;
6202 else if (strcmp (arg
, "le") == 0)
6204 md
.flags
&= ~EF_IA_64_BE
;
6206 else if (strcmp (arg
, "be") == 0)
6208 md
.flags
|= EF_IA_64_BE
;
6215 if (strcmp (arg
, "so") == 0)
6217 /* Suppress signon message. */
6219 else if (strcmp (arg
, "pi") == 0)
6221 /* Reject privileged instructions. FIXME */
6223 else if (strcmp (arg
, "us") == 0)
6225 /* Allow union of signed and unsigned range. FIXME */
6227 else if (strcmp (arg
, "close_fcalls") == 0)
6229 /* Do not resolve global function calls. */
6236 /* temp[="prefix"] Insert temporary labels into the object file
6237 symbol table prefixed by "prefix".
6238 Default prefix is ":temp:".
6243 /* indirect=<tgt> Assume unannotated indirect branches behavior
6244 according to <tgt> --
6245 exit: branch out from the current context (default)
6246 labels: all labels in context may be branch targets
6248 if (strncmp (arg
, "indirect=", 9) != 0)
6253 /* -X conflicts with an ignored option, use -x instead */
6255 if (!arg
|| strcmp (arg
, "explicit") == 0)
6257 /* set default mode to explicit */
6258 md
.default_explicit_mode
= 1;
6261 else if (strcmp (arg
, "auto") == 0)
6263 md
.default_explicit_mode
= 0;
6265 else if (strcmp (arg
, "debug") == 0)
6269 else if (strcmp (arg
, "debugx") == 0)
6271 md
.default_explicit_mode
= 1;
6276 as_bad (_("Unrecognized option '-x%s'"), arg
);
6281 /* nops Print nops statistics. */
6284 /* GNU specific switches for gcc. */
6285 case OPTION_MCONSTANT_GP
:
6286 md
.flags
|= EF_IA_64_CONS_GP
;
6289 case OPTION_MAUTO_PIC
:
6290 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6301 md_show_usage (stream
)
6306 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6307 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6308 -x | -xexplicit turn on dependency violation checking (default)\n\
6309 -xauto automagically remove dependency violations\n\
6310 -xdebug debug dependency violation checker\n"),
6315 ia64_after_parse_args ()
6317 if (debug_type
== DEBUG_STABS
)
6318 as_fatal (_("--gstabs is not supported for ia64"));
6321 /* Return true if TYPE fits in TEMPL at SLOT. */
6324 match (int templ
, int type
, int slot
)
6326 enum ia64_unit unit
;
6329 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6332 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6334 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6336 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6337 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6338 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6339 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6340 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6341 default: result
= 0; break;
6346 /* Add a bit of extra goodness if a nop of type F or B would fit
6347 in TEMPL at SLOT. */
6350 extra_goodness (int templ
, int slot
)
6352 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6354 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6359 /* This function is called once, at assembler startup time. It sets
6360 up all the tables, etc. that the MD part of the assembler will need
6361 that can be determined before arguments are parsed. */
6365 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6370 md
.explicit_mode
= md
.default_explicit_mode
;
6372 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6374 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6375 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6376 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6377 &zero_address_frag
);
6379 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6380 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6381 &zero_address_frag
);
6383 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6384 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6385 &zero_address_frag
);
6387 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6388 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6389 &zero_address_frag
);
6391 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6392 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6393 &zero_address_frag
);
6395 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6396 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6397 &zero_address_frag
);
6399 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6400 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6401 &zero_address_frag
);
6403 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6404 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6405 &zero_address_frag
);
6407 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6408 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6409 &zero_address_frag
);
6411 pseudo_func
[FUNC_IPLT_RELOC
].u
.sym
=
6412 symbol_new (".<iplt>", undefined_section
, FUNC_IPLT_RELOC
,
6413 &zero_address_frag
);
6415 /* Compute the table of best templates. We compute goodness as a
6416 base 4 value, in which each match counts for 3, each F counts
6417 for 2, each B counts for 1. This should maximize the number of
6418 F and B nops in the chosen bundles, which is good because these
6419 pipelines are least likely to be overcommitted. */
6420 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6421 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6422 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6425 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6428 if (match (t
, i
, 0))
6430 if (match (t
, j
, 1))
6432 if (match (t
, k
, 2))
6433 goodness
= 3 + 3 + 3;
6435 goodness
= 3 + 3 + extra_goodness (t
, 2);
6437 else if (match (t
, j
, 2))
6438 goodness
= 3 + 3 + extra_goodness (t
, 1);
6442 goodness
+= extra_goodness (t
, 1);
6443 goodness
+= extra_goodness (t
, 2);
6446 else if (match (t
, i
, 1))
6448 if (match (t
, j
, 2))
6451 goodness
= 3 + extra_goodness (t
, 2);
6453 else if (match (t
, i
, 2))
6454 goodness
= 3 + extra_goodness (t
, 1);
6456 if (goodness
> best
)
6459 best_template
[i
][j
][k
] = t
;
6464 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6465 md
.slot
[i
].user_template
= -1;
6467 md
.pseudo_hash
= hash_new ();
6468 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6470 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6471 (void *) (pseudo_opcode
+ i
));
6473 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6474 pseudo_opcode
[i
].name
, err
);
6477 md
.reg_hash
= hash_new ();
6478 md
.dynreg_hash
= hash_new ();
6479 md
.const_hash
= hash_new ();
6480 md
.entry_hash
= hash_new ();
6482 /* general registers: */
6485 for (i
= 0; i
< total
; ++i
)
6487 sprintf (name
, "r%d", i
- REG_GR
);
6488 md
.regsym
[i
] = declare_register (name
, i
);
6491 /* floating point registers: */
6493 for (; i
< total
; ++i
)
6495 sprintf (name
, "f%d", i
- REG_FR
);
6496 md
.regsym
[i
] = declare_register (name
, i
);
6499 /* application registers: */
6502 for (; i
< total
; ++i
)
6504 sprintf (name
, "ar%d", i
- REG_AR
);
6505 md
.regsym
[i
] = declare_register (name
, i
);
6508 /* control registers: */
6511 for (; i
< total
; ++i
)
6513 sprintf (name
, "cr%d", i
- REG_CR
);
6514 md
.regsym
[i
] = declare_register (name
, i
);
6517 /* predicate registers: */
6519 for (; i
< total
; ++i
)
6521 sprintf (name
, "p%d", i
- REG_P
);
6522 md
.regsym
[i
] = declare_register (name
, i
);
6525 /* branch registers: */
6527 for (; i
< total
; ++i
)
6529 sprintf (name
, "b%d", i
- REG_BR
);
6530 md
.regsym
[i
] = declare_register (name
, i
);
6533 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6534 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6535 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6536 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6537 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6538 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6539 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6541 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6543 regnum
= indirect_reg
[i
].regnum
;
6544 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6547 /* define synonyms for application registers: */
6548 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6549 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6550 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6552 /* define synonyms for control registers: */
6553 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6554 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6555 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6557 declare_register ("gp", REG_GR
+ 1);
6558 declare_register ("sp", REG_GR
+ 12);
6559 declare_register ("rp", REG_BR
+ 0);
6561 /* pseudo-registers used to specify unwind info: */
6562 declare_register ("psp", REG_PSP
);
6564 declare_register_set ("ret", 4, REG_GR
+ 8);
6565 declare_register_set ("farg", 8, REG_FR
+ 8);
6566 declare_register_set ("fret", 8, REG_FR
+ 8);
6568 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6570 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6571 (PTR
) (const_bits
+ i
));
6573 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6577 /* Set the architecture and machine depending on defaults and command line
6579 if (md
.flags
& EF_IA_64_ABI64
)
6580 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6582 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6585 as_warn (_("Could not set architecture and machine"));
6587 /* Set the pointer size and pointer shift size depending on md.flags */
6589 if (md
.flags
& EF_IA_64_ABI64
)
6591 md
.pointer_size
= 8; /* pointers are 8 bytes */
6592 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6596 md
.pointer_size
= 4; /* pointers are 4 bytes */
6597 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6600 md
.mem_offset
.hint
= 0;
6603 md
.entry_labels
= NULL
;
6606 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6607 because that is called after md_parse_option which is where we do the
6608 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6609 default endianness. */
6612 ia64_init (argc
, argv
)
6613 int argc ATTRIBUTE_UNUSED
;
6614 char **argv ATTRIBUTE_UNUSED
;
6616 md
.flags
= EF_IA_64_ABI64
;
6617 if (TARGET_BYTES_BIG_ENDIAN
)
6618 md
.flags
|= EF_IA_64_BE
;
6621 /* Return a string for the target object file format. */
6624 ia64_target_format ()
6626 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6628 if (md
.flags
& EF_IA_64_BE
)
6630 if (md
.flags
& EF_IA_64_ABI64
)
6632 return "elf64-ia64-aix-big";
6634 return "elf64-ia64-big";
6638 return "elf32-ia64-aix-big";
6640 return "elf32-ia64-big";
6645 if (md
.flags
& EF_IA_64_ABI64
)
6647 return "elf64-ia64-aix-little";
6649 return "elf64-ia64-little";
6653 return "elf32-ia64-aix-little";
6655 return "elf32-ia64-little";
6660 return "unknown-format";
6664 ia64_end_of_source ()
6666 /* terminate insn group upon reaching end of file: */
6667 insn_group_break (1, 0, 0);
6669 /* emits slots we haven't written yet: */
6670 ia64_flush_insns ();
6672 bfd_set_private_flags (stdoutput
, md
.flags
);
6674 md
.mem_offset
.hint
= 0;
6680 if (md
.qp
.X_op
== O_register
)
6681 as_bad ("qualifying predicate not followed by instruction");
6682 md
.qp
.X_op
= O_absent
;
6684 if (ignore_input ())
6687 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6689 if (md
.detect_dv
&& !md
.explicit_mode
)
6690 as_warn (_("Explicit stops are ignored in auto mode"));
6692 insn_group_break (1, 0, 0);
6696 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6698 static int defining_tag
= 0;
6701 ia64_unrecognized_line (ch
)
6707 expression (&md
.qp
);
6708 if (*input_line_pointer
++ != ')')
6710 as_bad ("Expected ')'");
6713 if (md
.qp
.X_op
!= O_register
)
6715 as_bad ("Qualifying predicate expected");
6718 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6720 as_bad ("Predicate register expected");
6726 if (md
.manual_bundling
)
6727 as_warn ("Found '{' when manual bundling is already turned on");
6729 CURR_SLOT
.manual_bundling_on
= 1;
6730 md
.manual_bundling
= 1;
6732 /* Bundling is only acceptable in explicit mode
6733 or when in default automatic mode. */
6734 if (md
.detect_dv
&& !md
.explicit_mode
)
6736 if (!md
.mode_explicitly_set
6737 && !md
.default_explicit_mode
)
6740 as_warn (_("Found '{' after explicit switch to automatic mode"));
6745 if (!md
.manual_bundling
)
6746 as_warn ("Found '}' when manual bundling is off");
6748 PREV_SLOT
.manual_bundling_off
= 1;
6749 md
.manual_bundling
= 0;
6751 /* switch back to automatic mode, if applicable */
6754 && !md
.mode_explicitly_set
6755 && !md
.default_explicit_mode
)
6758 /* Allow '{' to follow on the same line. We also allow ";;", but that
6759 happens automatically because ';' is an end of line marker. */
6761 if (input_line_pointer
[0] == '{')
6763 input_line_pointer
++;
6764 return ia64_unrecognized_line ('{');
6767 demand_empty_rest_of_line ();
6777 if (md
.qp
.X_op
== O_register
)
6779 as_bad ("Tag must come before qualifying predicate.");
6783 /* This implements just enough of read_a_source_file in read.c to
6784 recognize labels. */
6785 if (is_name_beginner (*input_line_pointer
))
6787 s
= input_line_pointer
;
6788 c
= get_symbol_end ();
6790 else if (LOCAL_LABELS_FB
6791 && ISDIGIT (*input_line_pointer
))
6794 while (ISDIGIT (*input_line_pointer
))
6795 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6796 fb_label_instance_inc (temp
);
6797 s
= fb_label_name (temp
, 0);
6798 c
= *input_line_pointer
;
6807 /* Put ':' back for error messages' sake. */
6808 *input_line_pointer
++ = ':';
6809 as_bad ("Expected ':'");
6816 /* Put ':' back for error messages' sake. */
6817 *input_line_pointer
++ = ':';
6818 if (*input_line_pointer
++ != ']')
6820 as_bad ("Expected ']'");
6825 as_bad ("Tag name expected");
6835 /* Not a valid line. */
6840 ia64_frob_label (sym
)
6843 struct label_fix
*fix
;
6845 /* Tags need special handling since they are not bundle breaks like
6849 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6851 fix
->next
= CURR_SLOT
.tag_fixups
;
6852 CURR_SLOT
.tag_fixups
= fix
;
6857 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6859 md
.last_text_seg
= now_seg
;
6860 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6862 fix
->next
= CURR_SLOT
.label_fixups
;
6863 CURR_SLOT
.label_fixups
= fix
;
6865 /* Keep track of how many code entry points we've seen. */
6866 if (md
.path
== md
.maxpaths
)
6869 md
.entry_labels
= (const char **)
6870 xrealloc ((void *) md
.entry_labels
,
6871 md
.maxpaths
* sizeof (char *));
6873 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6878 ia64_flush_pending_output ()
6880 if (!md
.keep_pending_output
6881 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6883 /* ??? This causes many unnecessary stop bits to be emitted.
6884 Unfortunately, it isn't clear if it is safe to remove this. */
6885 insn_group_break (1, 0, 0);
6886 ia64_flush_insns ();
6890 /* Do ia64-specific expression optimization. All that's done here is
6891 to transform index expressions that are either due to the indexing
6892 of rotating registers or due to the indexing of indirect register
6895 ia64_optimize_expr (l
, op
, r
)
6904 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6906 num_regs
= (l
->X_add_number
>> 16);
6907 if ((unsigned) r
->X_add_number
>= num_regs
)
6910 as_bad ("No current frame");
6912 as_bad ("Index out of range 0..%u", num_regs
- 1);
6913 r
->X_add_number
= 0;
6915 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6918 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6920 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6921 || l
->X_add_number
== IND_MEM
)
6923 as_bad ("Indirect register set name expected");
6924 l
->X_add_number
= IND_CPUID
;
6927 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6928 l
->X_add_number
= r
->X_add_number
;
6936 ia64_parse_name (name
, e
)
6940 struct const_desc
*cdesc
;
6941 struct dynreg
*dr
= 0;
6942 unsigned int regnum
;
6946 /* first see if NAME is a known register name: */
6947 sym
= hash_find (md
.reg_hash
, name
);
6950 e
->X_op
= O_register
;
6951 e
->X_add_number
= S_GET_VALUE (sym
);
6955 cdesc
= hash_find (md
.const_hash
, name
);
6958 e
->X_op
= O_constant
;
6959 e
->X_add_number
= cdesc
->value
;
6963 /* check for inN, locN, or outN: */
6967 if (name
[1] == 'n' && ISDIGIT (name
[2]))
6975 if (name
[1] == 'o' && name
[2] == 'c' && ISDIGIT (name
[3]))
6983 if (name
[1] == 'u' && name
[2] == 't' && ISDIGIT (name
[3]))
6996 /* The name is inN, locN, or outN; parse the register number. */
6997 regnum
= strtoul (name
, &end
, 10);
6998 if (end
> name
&& *end
== '\0')
7000 if ((unsigned) regnum
>= dr
->num_regs
)
7003 as_bad ("No current frame");
7005 as_bad ("Register number out of range 0..%u",
7009 e
->X_op
= O_register
;
7010 e
->X_add_number
= dr
->base
+ regnum
;
7015 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
7017 /* We've got ourselves the name of a rotating register set.
7018 Store the base register number in the low 16 bits of
7019 X_add_number and the size of the register set in the top 16
7021 e
->X_op
= O_register
;
7022 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
7028 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7031 ia64_canonicalize_symbol_name (name
)
7034 size_t len
= strlen (name
);
7035 if (len
> 1 && name
[len
- 1] == '#')
7036 name
[len
- 1] = '\0';
7040 /* Return true if idesc is a conditional branch instruction. This excludes
7041 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7042 because they always read/write resources regardless of the value of the
7043 qualifying predicate. br.ia must always use p0, and hence is always
7044 taken. Thus this function returns true for branches which can fall
7045 through, and which use no resources if they do fall through. */
7048 is_conditional_branch (idesc
)
7049 struct ia64_opcode
*idesc
;
7051 /* br is a conditional branch. Everything that starts with br. except
7052 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7053 Everything that starts with brl is a conditional branch. */
7054 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7055 && (idesc
->name
[2] == '\0'
7056 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7057 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7058 || idesc
->name
[2] == 'l'
7059 /* br.cond, br.call, br.clr */
7060 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7061 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7062 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7065 /* Return whether the given opcode is a taken branch. If there's any doubt,
7069 is_taken_branch (idesc
)
7070 struct ia64_opcode
*idesc
;
7072 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7073 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7076 /* Return whether the given opcode is an interruption or rfi. If there's any
7077 doubt, returns zero. */
7080 is_interruption_or_rfi (idesc
)
7081 struct ia64_opcode
*idesc
;
7083 if (strcmp (idesc
->name
, "rfi") == 0)
7088 /* Returns the index of the given dependency in the opcode's list of chks, or
7089 -1 if there is no dependency. */
7092 depends_on (depind
, idesc
)
7094 struct ia64_opcode
*idesc
;
7097 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7098 for (i
= 0; i
< dep
->nchks
; i
++)
7100 if (depind
== DEP (dep
->chks
[i
]))
7106 /* Determine a set of specific resources used for a particular resource
7107 class. Returns the number of specific resources identified For those
7108 cases which are not determinable statically, the resource returned is
7111 Meanings of value in 'NOTE':
7112 1) only read/write when the register number is explicitly encoded in the
7114 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7115 accesses CFM when qualifying predicate is in the rotating region.
7116 3) general register value is used to specify an indirect register; not
7117 determinable statically.
7118 4) only read the given resource when bits 7:0 of the indirect index
7119 register value does not match the register number of the resource; not
7120 determinable statically.
7121 5) all rules are implementation specific.
7122 6) only when both the index specified by the reader and the index specified
7123 by the writer have the same value in bits 63:61; not determinable
7125 7) only access the specified resource when the corresponding mask bit is
7127 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7128 only read when these insns reference FR2-31
7129 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7130 written when these insns write FR32-127
7131 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7133 11) The target predicates are written independently of PR[qp], but source
7134 registers are only read if PR[qp] is true. Since the state of PR[qp]
7135 cannot statically be determined, all source registers are marked used.
7136 12) This insn only reads the specified predicate register when that
7137 register is the PR[qp].
7138 13) This reference to ld-c only applies to teh GR whose value is loaded
7139 with data returned from memory, not the post-incremented address register.
7140 14) The RSE resource includes the implementation-specific RSE internal
7141 state resources. At least one (and possibly more) of these resources are
7142 read by each instruction listed in IC:rse-readers. At least one (and
7143 possibly more) of these resources are written by each insn listed in
7145 15+16) Represents reserved instructions, which the assembler does not
7148 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7149 this code; there are no dependency violations based on memory access.
7152 #define MAX_SPECS 256
7157 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7158 const struct ia64_dependency
*dep
;
7159 struct ia64_opcode
*idesc
;
7160 int type
; /* is this a DV chk or a DV reg? */
7161 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7162 int note
; /* resource note for this insn's usage */
7163 int path
; /* which execution path to examine */
7170 if (dep
->mode
== IA64_DV_WAW
7171 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7172 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7175 /* template for any resources we identify */
7176 tmpl
.dependency
= dep
;
7178 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7179 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7180 tmpl
.link_to_qp_branch
= 1;
7181 tmpl
.mem_offset
.hint
= 0;
7184 tmpl
.cmp_type
= CMP_NONE
;
7187 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7188 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7189 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7191 /* we don't need to track these */
7192 if (dep
->semantics
== IA64_DVS_NONE
)
7195 switch (dep
->specifier
)
7200 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7202 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7203 if (regno
>= 0 && regno
<= 7)
7205 specs
[count
] = tmpl
;
7206 specs
[count
++].index
= regno
;
7212 for (i
= 0; i
< 8; i
++)
7214 specs
[count
] = tmpl
;
7215 specs
[count
++].index
= i
;
7224 case IA64_RS_AR_UNAT
:
7225 /* This is a mov =AR or mov AR= instruction. */
7226 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7228 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7229 if (regno
== AR_UNAT
)
7231 specs
[count
++] = tmpl
;
7236 /* This is a spill/fill, or other instruction that modifies the
7239 /* Unless we can determine the specific bits used, mark the whole
7240 thing; bits 8:3 of the memory address indicate the bit used in
7241 UNAT. The .mem.offset hint may be used to eliminate a small
7242 subset of conflicts. */
7243 specs
[count
] = tmpl
;
7244 if (md
.mem_offset
.hint
)
7247 fprintf (stderr
, " Using hint for spill/fill\n");
7248 /* The index isn't actually used, just set it to something
7249 approximating the bit index. */
7250 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7251 specs
[count
].mem_offset
.hint
= 1;
7252 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7253 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7257 specs
[count
++].specific
= 0;
7265 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7267 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7268 if ((regno
>= 8 && regno
<= 15)
7269 || (regno
>= 20 && regno
<= 23)
7270 || (regno
>= 31 && regno
<= 39)
7271 || (regno
>= 41 && regno
<= 47)
7272 || (regno
>= 67 && regno
<= 111))
7274 specs
[count
] = tmpl
;
7275 specs
[count
++].index
= regno
;
7288 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7290 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7291 if ((regno
>= 48 && regno
<= 63)
7292 || (regno
>= 112 && regno
<= 127))
7294 specs
[count
] = tmpl
;
7295 specs
[count
++].index
= regno
;
7301 for (i
= 48; i
< 64; i
++)
7303 specs
[count
] = tmpl
;
7304 specs
[count
++].index
= i
;
7306 for (i
= 112; i
< 128; i
++)
7308 specs
[count
] = tmpl
;
7309 specs
[count
++].index
= i
;
7327 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7328 if (idesc
->operands
[i
] == IA64_OPND_B1
7329 || idesc
->operands
[i
] == IA64_OPND_B2
)
7331 specs
[count
] = tmpl
;
7332 specs
[count
++].index
=
7333 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7338 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7339 if (idesc
->operands
[i
] == IA64_OPND_B1
7340 || idesc
->operands
[i
] == IA64_OPND_B2
)
7342 specs
[count
] = tmpl
;
7343 specs
[count
++].index
=
7344 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7350 case IA64_RS_CPUID
: /* four or more registers */
7353 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7355 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7356 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7359 specs
[count
] = tmpl
;
7360 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7364 specs
[count
] = tmpl
;
7365 specs
[count
++].specific
= 0;
7375 case IA64_RS_DBR
: /* four or more registers */
7378 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7380 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7381 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7384 specs
[count
] = tmpl
;
7385 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7389 specs
[count
] = tmpl
;
7390 specs
[count
++].specific
= 0;
7394 else if (note
== 0 && !rsrc_write
)
7396 specs
[count
] = tmpl
;
7397 specs
[count
++].specific
= 0;
7405 case IA64_RS_IBR
: /* four or more registers */
7408 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7410 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7411 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7414 specs
[count
] = tmpl
;
7415 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7419 specs
[count
] = tmpl
;
7420 specs
[count
++].specific
= 0;
7433 /* These are implementation specific. Force all references to
7434 conflict with all other references. */
7435 specs
[count
] = tmpl
;
7436 specs
[count
++].specific
= 0;
7444 case IA64_RS_PKR
: /* 16 or more registers */
7445 if (note
== 3 || note
== 4)
7447 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7449 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7450 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7455 specs
[count
] = tmpl
;
7456 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7459 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7461 /* Uses all registers *except* the one in R3. */
7462 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7464 specs
[count
] = tmpl
;
7465 specs
[count
++].index
= i
;
7471 specs
[count
] = tmpl
;
7472 specs
[count
++].specific
= 0;
7479 specs
[count
] = tmpl
;
7480 specs
[count
++].specific
= 0;
7484 case IA64_RS_PMC
: /* four or more registers */
7487 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7488 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7491 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7493 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7494 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7497 specs
[count
] = tmpl
;
7498 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7502 specs
[count
] = tmpl
;
7503 specs
[count
++].specific
= 0;
7513 case IA64_RS_PMD
: /* four or more registers */
7516 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7518 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7519 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7522 specs
[count
] = tmpl
;
7523 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7527 specs
[count
] = tmpl
;
7528 specs
[count
++].specific
= 0;
7538 case IA64_RS_RR
: /* eight registers */
7541 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7543 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7544 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7547 specs
[count
] = tmpl
;
7548 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7552 specs
[count
] = tmpl
;
7553 specs
[count
++].specific
= 0;
7557 else if (note
== 0 && !rsrc_write
)
7559 specs
[count
] = tmpl
;
7560 specs
[count
++].specific
= 0;
7568 case IA64_RS_CR_IRR
:
7571 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7572 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7574 && idesc
->operands
[1] == IA64_OPND_CR3
7577 for (i
= 0; i
< 4; i
++)
7579 specs
[count
] = tmpl
;
7580 specs
[count
++].index
= CR_IRR0
+ i
;
7586 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7587 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7589 && regno
<= CR_IRR3
)
7591 specs
[count
] = tmpl
;
7592 specs
[count
++].index
= regno
;
7601 case IA64_RS_CR_LRR
:
7608 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7609 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7610 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7612 specs
[count
] = tmpl
;
7613 specs
[count
++].index
= regno
;
7621 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7623 specs
[count
] = tmpl
;
7624 specs
[count
++].index
=
7625 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7640 else if (rsrc_write
)
7642 if (dep
->specifier
== IA64_RS_FRb
7643 && idesc
->operands
[0] == IA64_OPND_F1
)
7645 specs
[count
] = tmpl
;
7646 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7651 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7653 if (idesc
->operands
[i
] == IA64_OPND_F2
7654 || idesc
->operands
[i
] == IA64_OPND_F3
7655 || idesc
->operands
[i
] == IA64_OPND_F4
)
7657 specs
[count
] = tmpl
;
7658 specs
[count
++].index
=
7659 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7668 /* This reference applies only to the GR whose value is loaded with
7669 data returned from memory. */
7670 specs
[count
] = tmpl
;
7671 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7677 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7678 if (idesc
->operands
[i
] == IA64_OPND_R1
7679 || idesc
->operands
[i
] == IA64_OPND_R2
7680 || idesc
->operands
[i
] == IA64_OPND_R3
)
7682 specs
[count
] = tmpl
;
7683 specs
[count
++].index
=
7684 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7686 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7687 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7688 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7690 specs
[count
] = tmpl
;
7691 specs
[count
++].index
=
7692 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7697 /* Look for anything that reads a GR. */
7698 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7700 if (idesc
->operands
[i
] == IA64_OPND_MR3
7701 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7702 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7703 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7704 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7705 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7706 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7707 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7708 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7709 || ((i
>= idesc
->num_outputs
)
7710 && (idesc
->operands
[i
] == IA64_OPND_R1
7711 || idesc
->operands
[i
] == IA64_OPND_R2
7712 || idesc
->operands
[i
] == IA64_OPND_R3
7713 /* addl source register. */
7714 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7716 specs
[count
] = tmpl
;
7717 specs
[count
++].index
=
7718 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7729 /* This is the same as IA64_RS_PRr, except that the register range is
7730 from 1 - 15, and there are no rotating register reads/writes here. */
7734 for (i
= 1; i
< 16; i
++)
7736 specs
[count
] = tmpl
;
7737 specs
[count
++].index
= i
;
7743 /* Mark only those registers indicated by the mask. */
7746 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7747 for (i
= 1; i
< 16; i
++)
7748 if (mask
& ((valueT
) 1 << i
))
7750 specs
[count
] = tmpl
;
7751 specs
[count
++].index
= i
;
7759 else if (note
== 11) /* note 11 implies note 1 as well */
7763 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7765 if (idesc
->operands
[i
] == IA64_OPND_P1
7766 || idesc
->operands
[i
] == IA64_OPND_P2
)
7768 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7769 if (regno
>= 1 && regno
< 16)
7771 specs
[count
] = tmpl
;
7772 specs
[count
++].index
= regno
;
7782 else if (note
== 12)
7784 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7786 specs
[count
] = tmpl
;
7787 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7794 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7795 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7796 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7797 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7799 if ((idesc
->operands
[0] == IA64_OPND_P1
7800 || idesc
->operands
[0] == IA64_OPND_P2
)
7801 && p1
>= 1 && p1
< 16)
7803 specs
[count
] = tmpl
;
7804 specs
[count
].cmp_type
=
7805 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7806 specs
[count
++].index
= p1
;
7808 if ((idesc
->operands
[1] == IA64_OPND_P1
7809 || idesc
->operands
[1] == IA64_OPND_P2
)
7810 && p2
>= 1 && p2
< 16)
7812 specs
[count
] = tmpl
;
7813 specs
[count
].cmp_type
=
7814 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7815 specs
[count
++].index
= p2
;
7820 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7822 specs
[count
] = tmpl
;
7823 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7825 if (idesc
->operands
[1] == IA64_OPND_PR
)
7827 for (i
= 1; i
< 16; i
++)
7829 specs
[count
] = tmpl
;
7830 specs
[count
++].index
= i
;
7841 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7842 simplified cases of this. */
7846 for (i
= 16; i
< 63; i
++)
7848 specs
[count
] = tmpl
;
7849 specs
[count
++].index
= i
;
7855 /* Mark only those registers indicated by the mask. */
7857 && idesc
->operands
[0] == IA64_OPND_PR
)
7859 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7860 if (mask
& ((valueT
) 1<<16))
7861 for (i
= 16; i
< 63; i
++)
7863 specs
[count
] = tmpl
;
7864 specs
[count
++].index
= i
;
7868 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7870 for (i
= 16; i
< 63; i
++)
7872 specs
[count
] = tmpl
;
7873 specs
[count
++].index
= i
;
7881 else if (note
== 11) /* note 11 implies note 1 as well */
7885 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7887 if (idesc
->operands
[i
] == IA64_OPND_P1
7888 || idesc
->operands
[i
] == IA64_OPND_P2
)
7890 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7891 if (regno
>= 16 && regno
< 63)
7893 specs
[count
] = tmpl
;
7894 specs
[count
++].index
= regno
;
7904 else if (note
== 12)
7906 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7908 specs
[count
] = tmpl
;
7909 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7916 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7917 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7918 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7919 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7921 if ((idesc
->operands
[0] == IA64_OPND_P1
7922 || idesc
->operands
[0] == IA64_OPND_P2
)
7923 && p1
>= 16 && p1
< 63)
7925 specs
[count
] = tmpl
;
7926 specs
[count
].cmp_type
=
7927 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7928 specs
[count
++].index
= p1
;
7930 if ((idesc
->operands
[1] == IA64_OPND_P1
7931 || idesc
->operands
[1] == IA64_OPND_P2
)
7932 && p2
>= 16 && p2
< 63)
7934 specs
[count
] = tmpl
;
7935 specs
[count
].cmp_type
=
7936 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7937 specs
[count
++].index
= p2
;
7942 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7944 specs
[count
] = tmpl
;
7945 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7947 if (idesc
->operands
[1] == IA64_OPND_PR
)
7949 for (i
= 16; i
< 63; i
++)
7951 specs
[count
] = tmpl
;
7952 specs
[count
++].index
= i
;
7964 /* Verify that the instruction is using the PSR bit indicated in
7968 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7970 if (dep
->regindex
< 6)
7972 specs
[count
++] = tmpl
;
7975 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7977 if (dep
->regindex
< 32
7978 || dep
->regindex
== 35
7979 || dep
->regindex
== 36
7980 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7982 specs
[count
++] = tmpl
;
7985 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7987 if (dep
->regindex
< 32
7988 || dep
->regindex
== 35
7989 || dep
->regindex
== 36
7990 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7992 specs
[count
++] = tmpl
;
7997 /* Several PSR bits have very specific dependencies. */
7998 switch (dep
->regindex
)
8001 specs
[count
++] = tmpl
;
8006 specs
[count
++] = tmpl
;
8010 /* Only certain CR accesses use PSR.ic */
8011 if (idesc
->operands
[0] == IA64_OPND_CR3
8012 || idesc
->operands
[1] == IA64_OPND_CR3
)
8015 ((idesc
->operands
[0] == IA64_OPND_CR3
)
8018 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8033 specs
[count
++] = tmpl
;
8042 specs
[count
++] = tmpl
;
8046 /* Only some AR accesses use cpl */
8047 if (idesc
->operands
[0] == IA64_OPND_AR3
8048 || idesc
->operands
[1] == IA64_OPND_AR3
)
8051 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8054 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8061 && regno
<= AR_K7
))))
8063 specs
[count
++] = tmpl
;
8068 specs
[count
++] = tmpl
;
8078 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8080 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8086 if (mask
& ((valueT
) 1 << dep
->regindex
))
8088 specs
[count
++] = tmpl
;
8093 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8094 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8095 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8096 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8098 if (idesc
->operands
[i
] == IA64_OPND_F1
8099 || idesc
->operands
[i
] == IA64_OPND_F2
8100 || idesc
->operands
[i
] == IA64_OPND_F3
8101 || idesc
->operands
[i
] == IA64_OPND_F4
)
8103 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8104 if (reg
>= min
&& reg
<= max
)
8106 specs
[count
++] = tmpl
;
8113 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8114 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8115 /* mfh is read on writes to FR32-127; mfl is read on writes to
8117 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8119 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8121 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8122 if (reg
>= min
&& reg
<= max
)
8124 specs
[count
++] = tmpl
;
8129 else if (note
== 10)
8131 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8133 if (idesc
->operands
[i
] == IA64_OPND_R1
8134 || idesc
->operands
[i
] == IA64_OPND_R2
8135 || idesc
->operands
[i
] == IA64_OPND_R3
)
8137 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8138 if (regno
>= 16 && regno
<= 31)
8140 specs
[count
++] = tmpl
;
8151 case IA64_RS_AR_FPSR
:
8152 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8154 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8155 if (regno
== AR_FPSR
)
8157 specs
[count
++] = tmpl
;
8162 specs
[count
++] = tmpl
;
8167 /* Handle all AR[REG] resources */
8168 if (note
== 0 || note
== 1)
8170 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8171 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8172 && regno
== dep
->regindex
)
8174 specs
[count
++] = tmpl
;
8176 /* other AR[REG] resources may be affected by AR accesses */
8177 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8180 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8181 switch (dep
->regindex
)
8187 if (regno
== AR_BSPSTORE
)
8189 specs
[count
++] = tmpl
;
8193 (regno
== AR_BSPSTORE
8194 || regno
== AR_RNAT
))
8196 specs
[count
++] = tmpl
;
8201 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8204 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8205 switch (dep
->regindex
)
8210 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8212 specs
[count
++] = tmpl
;
8219 specs
[count
++] = tmpl
;
8229 /* Handle all CR[REG] resources */
8230 if (note
== 0 || note
== 1)
8232 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8234 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8235 if (regno
== dep
->regindex
)
8237 specs
[count
++] = tmpl
;
8239 else if (!rsrc_write
)
8241 /* Reads from CR[IVR] affect other resources. */
8242 if (regno
== CR_IVR
)
8244 if ((dep
->regindex
>= CR_IRR0
8245 && dep
->regindex
<= CR_IRR3
)
8246 || dep
->regindex
== CR_TPR
)
8248 specs
[count
++] = tmpl
;
8255 specs
[count
++] = tmpl
;
8264 case IA64_RS_INSERVICE
:
8265 /* look for write of EOI (67) or read of IVR (65) */
8266 if ((idesc
->operands
[0] == IA64_OPND_CR3
8267 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8268 || (idesc
->operands
[1] == IA64_OPND_CR3
8269 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8271 specs
[count
++] = tmpl
;
8278 specs
[count
++] = tmpl
;
8289 specs
[count
++] = tmpl
;
8293 /* Check if any of the registers accessed are in the rotating region.
8294 mov to/from pr accesses CFM only when qp_regno is in the rotating
8296 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8298 if (idesc
->operands
[i
] == IA64_OPND_R1
8299 || idesc
->operands
[i
] == IA64_OPND_R2
8300 || idesc
->operands
[i
] == IA64_OPND_R3
)
8302 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8303 /* Assumes that md.rot.num_regs is always valid */
8304 if (md
.rot
.num_regs
> 0
8306 && num
< 31 + md
.rot
.num_regs
)
8308 specs
[count
] = tmpl
;
8309 specs
[count
++].specific
= 0;
8312 else if (idesc
->operands
[i
] == IA64_OPND_F1
8313 || idesc
->operands
[i
] == IA64_OPND_F2
8314 || idesc
->operands
[i
] == IA64_OPND_F3
8315 || idesc
->operands
[i
] == IA64_OPND_F4
)
8317 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8320 specs
[count
] = tmpl
;
8321 specs
[count
++].specific
= 0;
8324 else if (idesc
->operands
[i
] == IA64_OPND_P1
8325 || idesc
->operands
[i
] == IA64_OPND_P2
)
8327 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8330 specs
[count
] = tmpl
;
8331 specs
[count
++].specific
= 0;
8335 if (CURR_SLOT
.qp_regno
> 15)
8337 specs
[count
] = tmpl
;
8338 specs
[count
++].specific
= 0;
8343 /* This is the same as IA64_RS_PRr, except simplified to account for
8344 the fact that there is only one register. */
8348 specs
[count
++] = tmpl
;
8353 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8354 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8355 if (mask
& ((valueT
) 1 << 63))
8356 specs
[count
++] = tmpl
;
8358 else if (note
== 11)
8360 if ((idesc
->operands
[0] == IA64_OPND_P1
8361 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8362 || (idesc
->operands
[1] == IA64_OPND_P2
8363 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8365 specs
[count
++] = tmpl
;
8368 else if (note
== 12)
8370 if (CURR_SLOT
.qp_regno
== 63)
8372 specs
[count
++] = tmpl
;
8379 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8380 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8381 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8382 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8385 && (idesc
->operands
[0] == IA64_OPND_P1
8386 || idesc
->operands
[0] == IA64_OPND_P2
))
8388 specs
[count
] = tmpl
;
8389 specs
[count
++].cmp_type
=
8390 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8393 && (idesc
->operands
[1] == IA64_OPND_P1
8394 || idesc
->operands
[1] == IA64_OPND_P2
))
8396 specs
[count
] = tmpl
;
8397 specs
[count
++].cmp_type
=
8398 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8403 if (CURR_SLOT
.qp_regno
== 63)
8405 specs
[count
++] = tmpl
;
8416 /* FIXME we can identify some individual RSE written resources, but RSE
8417 read resources have not yet been completely identified, so for now
8418 treat RSE as a single resource */
8419 if (strncmp (idesc
->name
, "mov", 3) == 0)
8423 if (idesc
->operands
[0] == IA64_OPND_AR3
8424 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8426 specs
[count
] = tmpl
;
8427 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8432 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8434 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8435 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8437 specs
[count
++] = tmpl
;
8440 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8442 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8443 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8444 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8446 specs
[count
++] = tmpl
;
8453 specs
[count
++] = tmpl
;
8458 /* FIXME -- do any of these need to be non-specific? */
8459 specs
[count
++] = tmpl
;
8463 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8470 /* Clear branch flags on marked resources. This breaks the link between the
8471 QP of the marking instruction and a subsequent branch on the same QP. */
8474 clear_qp_branch_flag (mask
)
8478 for (i
= 0; i
< regdepslen
; i
++)
8480 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8481 if ((bit
& mask
) != 0)
8483 regdeps
[i
].link_to_qp_branch
= 0;
8488 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8490 Any changes to a PR clears the mutex relations which include that PR. */
8493 clear_qp_mutex (mask
)
8499 while (i
< qp_mutexeslen
)
8501 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8505 fprintf (stderr
, " Clearing mutex relation");
8506 print_prmask (qp_mutexes
[i
].prmask
);
8507 fprintf (stderr
, "\n");
8509 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8516 /* Clear implies relations which contain PRs in the given masks.
8517 P1_MASK indicates the source of the implies relation, while P2_MASK
8518 indicates the implied PR. */
8521 clear_qp_implies (p1_mask
, p2_mask
)
8528 while (i
< qp_implieslen
)
8530 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8531 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8534 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8535 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8536 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8543 /* Add the PRs specified to the list of implied relations. */
8546 add_qp_imply (p1
, p2
)
8553 /* p0 is not meaningful here. */
8554 if (p1
== 0 || p2
== 0)
8560 /* If it exists already, ignore it. */
8561 for (i
= 0; i
< qp_implieslen
; i
++)
8563 if (qp_implies
[i
].p1
== p1
8564 && qp_implies
[i
].p2
== p2
8565 && qp_implies
[i
].path
== md
.path
8566 && !qp_implies
[i
].p2_branched
)
8570 if (qp_implieslen
== qp_impliestotlen
)
8572 qp_impliestotlen
+= 20;
8573 qp_implies
= (struct qp_imply
*)
8574 xrealloc ((void *) qp_implies
,
8575 qp_impliestotlen
* sizeof (struct qp_imply
));
8578 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8579 qp_implies
[qp_implieslen
].p1
= p1
;
8580 qp_implies
[qp_implieslen
].p2
= p2
;
8581 qp_implies
[qp_implieslen
].path
= md
.path
;
8582 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8584 /* Add in the implied transitive relations; for everything that p2 implies,
8585 make p1 imply that, too; for everything that implies p1, make it imply p2
8587 for (i
= 0; i
< qp_implieslen
; i
++)
8589 if (qp_implies
[i
].p1
== p2
)
8590 add_qp_imply (p1
, qp_implies
[i
].p2
);
8591 if (qp_implies
[i
].p2
== p1
)
8592 add_qp_imply (qp_implies
[i
].p1
, p2
);
8594 /* Add in mutex relations implied by this implies relation; for each mutex
8595 relation containing p2, duplicate it and replace p2 with p1. */
8596 bit
= (valueT
) 1 << p1
;
8597 mask
= (valueT
) 1 << p2
;
8598 for (i
= 0; i
< qp_mutexeslen
; i
++)
8600 if (qp_mutexes
[i
].prmask
& mask
)
8601 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8605 /* Add the PRs specified in the mask to the mutex list; this means that only
8606 one of the PRs can be true at any time. PR0 should never be included in
8616 if (qp_mutexeslen
== qp_mutexestotlen
)
8618 qp_mutexestotlen
+= 20;
8619 qp_mutexes
= (struct qpmutex
*)
8620 xrealloc ((void *) qp_mutexes
,
8621 qp_mutexestotlen
* sizeof (struct qpmutex
));
8625 fprintf (stderr
, " Registering mutex on");
8626 print_prmask (mask
);
8627 fprintf (stderr
, "\n");
8629 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8630 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8634 clear_register_values ()
8638 fprintf (stderr
, " Clearing register values\n");
8639 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8640 gr_values
[i
].known
= 0;
8643 /* Keep track of register values/changes which affect DV tracking.
8645 optimization note: should add a flag to classes of insns where otherwise we
8646 have to examine a group of strings to identify them. */
8649 note_register_values (idesc
)
8650 struct ia64_opcode
*idesc
;
8652 valueT qp_changemask
= 0;
8655 /* Invalidate values for registers being written to. */
8656 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8658 if (idesc
->operands
[i
] == IA64_OPND_R1
8659 || idesc
->operands
[i
] == IA64_OPND_R2
8660 || idesc
->operands
[i
] == IA64_OPND_R3
)
8662 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8663 if (regno
> 0 && regno
< NELEMS (gr_values
))
8664 gr_values
[regno
].known
= 0;
8666 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8668 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8669 if (regno
> 0 && regno
< 4)
8670 gr_values
[regno
].known
= 0;
8672 else if (idesc
->operands
[i
] == IA64_OPND_P1
8673 || idesc
->operands
[i
] == IA64_OPND_P2
)
8675 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8676 qp_changemask
|= (valueT
) 1 << regno
;
8678 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8680 if (idesc
->operands
[2] & (valueT
) 0x10000)
8681 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8683 qp_changemask
= idesc
->operands
[2];
8686 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8688 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8689 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8691 qp_changemask
= idesc
->operands
[1];
8692 qp_changemask
&= ~(valueT
) 0xFFFF;
8697 /* Always clear qp branch flags on any PR change. */
8698 /* FIXME there may be exceptions for certain compares. */
8699 clear_qp_branch_flag (qp_changemask
);
8701 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8702 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8704 qp_changemask
|= ~(valueT
) 0xFFFF;
8705 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8707 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8708 gr_values
[i
].known
= 0;
8710 clear_qp_mutex (qp_changemask
);
8711 clear_qp_implies (qp_changemask
, qp_changemask
);
8713 /* After a call, all register values are undefined, except those marked
8715 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8716 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8718 /* FIXME keep GR values which are marked as "safe_across_calls" */
8719 clear_register_values ();
8720 clear_qp_mutex (~qp_safe_across_calls
);
8721 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8722 clear_qp_branch_flag (~qp_safe_across_calls
);
8724 else if (is_interruption_or_rfi (idesc
)
8725 || is_taken_branch (idesc
))
8727 clear_register_values ();
8728 clear_qp_mutex (~(valueT
) 0);
8729 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8731 /* Look for mutex and implies relations. */
8732 else if ((idesc
->operands
[0] == IA64_OPND_P1
8733 || idesc
->operands
[0] == IA64_OPND_P2
)
8734 && (idesc
->operands
[1] == IA64_OPND_P1
8735 || idesc
->operands
[1] == IA64_OPND_P2
))
8737 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8738 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8739 valueT p1mask
= (valueT
) 1 << p1
;
8740 valueT p2mask
= (valueT
) 1 << p2
;
8742 /* If one of the PRs is PR0, we can't really do anything. */
8743 if (p1
== 0 || p2
== 0)
8746 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8748 /* In general, clear mutexes and implies which include P1 or P2,
8749 with the following exceptions. */
8750 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8752 add_qp_mutex (p1mask
| p2mask
);
8753 clear_qp_implies (p2mask
, p1mask
);
8755 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8757 add_qp_mutex (p1mask
| p2mask
);
8758 clear_qp_implies (p1mask
, p2mask
);
8760 else if (strstr (idesc
->name
, ".and") != NULL
)
8762 clear_qp_implies (0, p1mask
| p2mask
);
8764 else if (strstr (idesc
->name
, ".or") != NULL
)
8766 clear_qp_mutex (p1mask
| p2mask
);
8767 clear_qp_implies (p1mask
| p2mask
, 0);
8771 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8772 if (strstr (idesc
->name
, ".unc") != NULL
)
8774 add_qp_mutex (p1mask
| p2mask
);
8775 if (CURR_SLOT
.qp_regno
!= 0)
8777 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8778 CURR_SLOT
.qp_regno
);
8779 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8780 CURR_SLOT
.qp_regno
);
8783 else if (CURR_SLOT
.qp_regno
== 0)
8785 add_qp_mutex (p1mask
| p2mask
);
8789 clear_qp_mutex (p1mask
| p2mask
);
8793 /* Look for mov imm insns into GRs. */
8794 else if (idesc
->operands
[0] == IA64_OPND_R1
8795 && (idesc
->operands
[1] == IA64_OPND_IMM22
8796 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8797 && (strcmp (idesc
->name
, "mov") == 0
8798 || strcmp (idesc
->name
, "movl") == 0))
8800 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8801 if (regno
> 0 && regno
< NELEMS (gr_values
))
8803 gr_values
[regno
].known
= 1;
8804 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8805 gr_values
[regno
].path
= md
.path
;
8808 fprintf (stderr
, " Know gr%d = ", regno
);
8809 fprintf_vma (stderr
, gr_values
[regno
].value
);
8810 fputs ("\n", stderr
);
8816 clear_qp_mutex (qp_changemask
);
8817 clear_qp_implies (qp_changemask
, qp_changemask
);
8821 /* Return whether the given predicate registers are currently mutex. */
8824 qp_mutex (p1
, p2
, path
)
8834 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8835 for (i
= 0; i
< qp_mutexeslen
; i
++)
8837 if (qp_mutexes
[i
].path
>= path
8838 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8845 /* Return whether the given resource is in the given insn's list of chks
8846 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8850 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8852 struct ia64_opcode
*idesc
;
8857 struct rsrc specs
[MAX_SPECS
];
8860 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8861 we don't need to check. One exception is note 11, which indicates that
8862 target predicates are written regardless of PR[qp]. */
8863 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8867 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8870 /* UNAT checking is a bit more specific than other resources */
8871 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8872 && specs
[count
].mem_offset
.hint
8873 && rs
->mem_offset
.hint
)
8875 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8877 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8878 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8885 /* Skip apparent PR write conflicts where both writes are an AND or both
8886 writes are an OR. */
8887 if (rs
->dependency
->specifier
== IA64_RS_PR
8888 || rs
->dependency
->specifier
== IA64_RS_PRr
8889 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8891 if (specs
[count
].cmp_type
!= CMP_NONE
8892 && specs
[count
].cmp_type
== rs
->cmp_type
)
8895 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8896 dv_mode
[rs
->dependency
->mode
],
8897 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8898 specs
[count
].index
: 63);
8903 " %s on parallel compare conflict %s vs %s on PR%d\n",
8904 dv_mode
[rs
->dependency
->mode
],
8905 dv_cmp_type
[rs
->cmp_type
],
8906 dv_cmp_type
[specs
[count
].cmp_type
],
8907 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8908 specs
[count
].index
: 63);
8912 /* If either resource is not specific, conservatively assume a conflict
8914 if (!specs
[count
].specific
|| !rs
->specific
)
8916 else if (specs
[count
].index
== rs
->index
)
8921 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8927 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8928 insert a stop to create the break. Update all resource dependencies
8929 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8930 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8931 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8935 insn_group_break (insert_stop
, qp_regno
, save_current
)
8942 if (insert_stop
&& md
.num_slots_in_use
> 0)
8943 PREV_SLOT
.end_of_insn_group
= 1;
8947 fprintf (stderr
, " Insn group break%s",
8948 (insert_stop
? " (w/stop)" : ""));
8950 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8951 fprintf (stderr
, "\n");
8955 while (i
< regdepslen
)
8957 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8960 && regdeps
[i
].qp_regno
!= qp_regno
)
8967 && CURR_SLOT
.src_file
== regdeps
[i
].file
8968 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8974 /* clear dependencies which are automatically cleared by a stop, or
8975 those that have reached the appropriate state of insn serialization */
8976 if (dep
->semantics
== IA64_DVS_IMPLIED
8977 || dep
->semantics
== IA64_DVS_IMPLIEDF
8978 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8980 print_dependency ("Removing", i
);
8981 regdeps
[i
] = regdeps
[--regdepslen
];
8985 if (dep
->semantics
== IA64_DVS_DATA
8986 || dep
->semantics
== IA64_DVS_INSTR
8987 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8989 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8990 regdeps
[i
].insn_srlz
= STATE_STOP
;
8991 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8992 regdeps
[i
].data_srlz
= STATE_STOP
;
8999 /* Add the given resource usage spec to the list of active dependencies. */
9002 mark_resource (idesc
, dep
, spec
, depind
, path
)
9003 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
9004 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
9009 if (regdepslen
== regdepstotlen
)
9011 regdepstotlen
+= 20;
9012 regdeps
= (struct rsrc
*)
9013 xrealloc ((void *) regdeps
,
9014 regdepstotlen
* sizeof (struct rsrc
));
9017 regdeps
[regdepslen
] = *spec
;
9018 regdeps
[regdepslen
].depind
= depind
;
9019 regdeps
[regdepslen
].path
= path
;
9020 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
9021 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
9023 print_dependency ("Adding", regdepslen
);
9029 print_dependency (action
, depind
)
9035 fprintf (stderr
, " %s %s '%s'",
9036 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9037 (regdeps
[depind
].dependency
)->name
);
9038 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9039 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9040 if (regdeps
[depind
].mem_offset
.hint
)
9042 fputs (" ", stderr
);
9043 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9044 fputs ("+", stderr
);
9045 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9047 fprintf (stderr
, "\n");
9052 instruction_serialization ()
9056 fprintf (stderr
, " Instruction serialization\n");
9057 for (i
= 0; i
< regdepslen
; i
++)
9058 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9059 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9063 data_serialization ()
9067 fprintf (stderr
, " Data serialization\n");
9068 while (i
< regdepslen
)
9070 if (regdeps
[i
].data_srlz
== STATE_STOP
9071 /* Note: as of 991210, all "other" dependencies are cleared by a
9072 data serialization. This might change with new tables */
9073 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9075 print_dependency ("Removing", i
);
9076 regdeps
[i
] = regdeps
[--regdepslen
];
9083 /* Insert stops and serializations as needed to avoid DVs. */
9086 remove_marked_resource (rs
)
9089 switch (rs
->dependency
->semantics
)
9091 case IA64_DVS_SPECIFIC
:
9093 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9094 /* ...fall through... */
9095 case IA64_DVS_INSTR
:
9097 fprintf (stderr
, "Inserting instr serialization\n");
9098 if (rs
->insn_srlz
< STATE_STOP
)
9099 insn_group_break (1, 0, 0);
9100 if (rs
->insn_srlz
< STATE_SRLZ
)
9102 int oldqp
= CURR_SLOT
.qp_regno
;
9103 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9104 /* Manually jam a srlz.i insn into the stream */
9105 CURR_SLOT
.qp_regno
= 0;
9106 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9107 instruction_serialization ();
9108 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9109 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9111 CURR_SLOT
.qp_regno
= oldqp
;
9112 CURR_SLOT
.idesc
= oldidesc
;
9114 insn_group_break (1, 0, 0);
9116 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9117 "other" types of DV are eliminated
9118 by a data serialization */
9121 fprintf (stderr
, "Inserting data serialization\n");
9122 if (rs
->data_srlz
< STATE_STOP
)
9123 insn_group_break (1, 0, 0);
9125 int oldqp
= CURR_SLOT
.qp_regno
;
9126 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9127 /* Manually jam a srlz.d insn into the stream */
9128 CURR_SLOT
.qp_regno
= 0;
9129 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9130 data_serialization ();
9131 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9132 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9134 CURR_SLOT
.qp_regno
= oldqp
;
9135 CURR_SLOT
.idesc
= oldidesc
;
9138 case IA64_DVS_IMPLIED
:
9139 case IA64_DVS_IMPLIEDF
:
9141 fprintf (stderr
, "Inserting stop\n");
9142 insn_group_break (1, 0, 0);
9149 /* Check the resources used by the given opcode against the current dependency
9152 The check is run once for each execution path encountered. In this case,
9153 a unique execution path is the sequence of instructions following a code
9154 entry point, e.g. the following has three execution paths, one starting
9155 at L0, one at L1, and one at L2.
9164 check_dependencies (idesc
)
9165 struct ia64_opcode
*idesc
;
9167 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9171 /* Note that the number of marked resources may change within the
9172 loop if in auto mode. */
9174 while (i
< regdepslen
)
9176 struct rsrc
*rs
= ®deps
[i
];
9177 const struct ia64_dependency
*dep
= rs
->dependency
;
9182 if (dep
->semantics
== IA64_DVS_NONE
9183 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9189 note
= NOTE (opdeps
->chks
[chkind
]);
9191 /* Check this resource against each execution path seen thus far. */
9192 for (path
= 0; path
<= md
.path
; path
++)
9196 /* If the dependency wasn't on the path being checked, ignore it. */
9197 if (rs
->path
< path
)
9200 /* If the QP for this insn implies a QP which has branched, don't
9201 bother checking. Ed. NOTE: I don't think this check is terribly
9202 useful; what's the point of generating code which will only be
9203 reached if its QP is zero?
9204 This code was specifically inserted to handle the following code,
9205 based on notes from Intel's DV checking code, where p1 implies p2.
9211 if (CURR_SLOT
.qp_regno
!= 0)
9215 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9217 if (qp_implies
[implies
].path
>= path
9218 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9219 && qp_implies
[implies
].p2_branched
)
9229 if ((matchtype
= resources_match (rs
, idesc
, note
,
9230 CURR_SLOT
.qp_regno
, path
)) != 0)
9233 char pathmsg
[256] = "";
9234 char indexmsg
[256] = "";
9235 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9238 sprintf (pathmsg
, " when entry is at label '%s'",
9239 md
.entry_labels
[path
- 1]);
9240 if (rs
->specific
&& rs
->index
!= 0)
9241 sprintf (indexmsg
, ", specific resource number is %d",
9243 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9245 (certain
? "violates" : "may violate"),
9246 dv_mode
[dep
->mode
], dep
->name
,
9247 dv_sem
[dep
->semantics
],
9250 if (md
.explicit_mode
)
9252 as_warn ("%s", msg
);
9254 as_warn (_("Only the first path encountering the conflict "
9256 as_warn_where (rs
->file
, rs
->line
,
9257 _("This is the location of the "
9258 "conflicting usage"));
9259 /* Don't bother checking other paths, to avoid duplicating
9266 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9268 remove_marked_resource (rs
);
9270 /* since the set of dependencies has changed, start over */
9271 /* FIXME -- since we're removing dvs as we go, we
9272 probably don't really need to start over... */
9285 /* Register new dependencies based on the given opcode. */
9288 mark_resources (idesc
)
9289 struct ia64_opcode
*idesc
;
9292 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9293 int add_only_qp_reads
= 0;
9295 /* A conditional branch only uses its resources if it is taken; if it is
9296 taken, we stop following that path. The other branch types effectively
9297 *always* write their resources. If it's not taken, register only QP
9299 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9301 add_only_qp_reads
= 1;
9305 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9307 for (i
= 0; i
< opdeps
->nregs
; i
++)
9309 const struct ia64_dependency
*dep
;
9310 struct rsrc specs
[MAX_SPECS
];
9315 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9316 note
= NOTE (opdeps
->regs
[i
]);
9318 if (add_only_qp_reads
9319 && !(dep
->mode
== IA64_DV_WAR
9320 && (dep
->specifier
== IA64_RS_PR
9321 || dep
->specifier
== IA64_RS_PRr
9322 || dep
->specifier
== IA64_RS_PR63
)))
9325 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9328 if (md
.debug_dv
&& !count
)
9329 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9330 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9335 mark_resource (idesc
, dep
, &specs
[count
],
9336 DEP (opdeps
->regs
[i
]), md
.path
);
9339 /* The execution path may affect register values, which may in turn
9340 affect which indirect-access resources are accessed. */
9341 switch (dep
->specifier
)
9353 for (path
= 0; path
< md
.path
; path
++)
9355 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9357 mark_resource (idesc
, dep
, &specs
[count
],
9358 DEP (opdeps
->regs
[i
]), path
);
9365 /* Remove dependencies when they no longer apply. */
9368 update_dependencies (idesc
)
9369 struct ia64_opcode
*idesc
;
9373 if (strcmp (idesc
->name
, "srlz.i") == 0)
9375 instruction_serialization ();
9377 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9379 data_serialization ();
9381 else if (is_interruption_or_rfi (idesc
)
9382 || is_taken_branch (idesc
))
9384 /* Although technically the taken branch doesn't clear dependencies
9385 which require a srlz.[id], we don't follow the branch; the next
9386 instruction is assumed to start with a clean slate. */
9390 else if (is_conditional_branch (idesc
)
9391 && CURR_SLOT
.qp_regno
!= 0)
9393 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9395 for (i
= 0; i
< qp_implieslen
; i
++)
9397 /* If the conditional branch's predicate is implied by the predicate
9398 in an existing dependency, remove that dependency. */
9399 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9402 /* Note that this implied predicate takes a branch so that if
9403 a later insn generates a DV but its predicate implies this
9404 one, we can avoid the false DV warning. */
9405 qp_implies
[i
].p2_branched
= 1;
9406 while (depind
< regdepslen
)
9408 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9410 print_dependency ("Removing", depind
);
9411 regdeps
[depind
] = regdeps
[--regdepslen
];
9418 /* Any marked resources which have this same predicate should be
9419 cleared, provided that the QP hasn't been modified between the
9420 marking instruction and the branch. */
9423 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9428 while (i
< regdepslen
)
9430 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9431 && regdeps
[i
].link_to_qp_branch
9432 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9433 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9435 /* Treat like a taken branch */
9436 print_dependency ("Removing", i
);
9437 regdeps
[i
] = regdeps
[--regdepslen
];
9446 /* Examine the current instruction for dependency violations. */
9450 struct ia64_opcode
*idesc
;
9454 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9455 idesc
->name
, CURR_SLOT
.src_line
,
9456 idesc
->dependencies
->nchks
,
9457 idesc
->dependencies
->nregs
);
9460 /* Look through the list of currently marked resources; if the current
9461 instruction has the dependency in its chks list which uses that resource,
9462 check against the specific resources used. */
9463 check_dependencies (idesc
);
9465 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9466 then add them to the list of marked resources. */
9467 mark_resources (idesc
);
9469 /* There are several types of dependency semantics, and each has its own
9470 requirements for being cleared
9472 Instruction serialization (insns separated by interruption, rfi, or
9473 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9475 Data serialization (instruction serialization, or writer + srlz.d +
9476 reader, where writer and srlz.d are in separate groups) clears
9477 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9478 always be the case).
9480 Instruction group break (groups separated by stop, taken branch,
9481 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9483 update_dependencies (idesc
);
9485 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9486 warning. Keep track of as many as possible that are useful. */
9487 note_register_values (idesc
);
9489 /* We don't need or want this anymore. */
9490 md
.mem_offset
.hint
= 0;
9495 /* Translate one line of assembly. Pseudo ops and labels do not show
9501 char *saved_input_line_pointer
, *mnemonic
;
9502 const struct pseudo_opcode
*pdesc
;
9503 struct ia64_opcode
*idesc
;
9504 unsigned char qp_regno
;
9508 saved_input_line_pointer
= input_line_pointer
;
9509 input_line_pointer
= str
;
9511 /* extract the opcode (mnemonic): */
9513 mnemonic
= input_line_pointer
;
9514 ch
= get_symbol_end ();
9515 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9518 *input_line_pointer
= ch
;
9519 (*pdesc
->handler
) (pdesc
->arg
);
9523 /* Find the instruction descriptor matching the arguments. */
9525 idesc
= ia64_find_opcode (mnemonic
);
9526 *input_line_pointer
= ch
;
9529 as_bad ("Unknown opcode `%s'", mnemonic
);
9533 idesc
= parse_operands (idesc
);
9537 /* Handle the dynamic ops we can handle now: */
9538 if (idesc
->type
== IA64_TYPE_DYN
)
9540 if (strcmp (idesc
->name
, "add") == 0)
9542 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9543 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9547 ia64_free_opcode (idesc
);
9548 idesc
= ia64_find_opcode (mnemonic
);
9550 know (!idesc
->next
);
9553 else if (strcmp (idesc
->name
, "mov") == 0)
9555 enum ia64_opnd opnd1
, opnd2
;
9558 opnd1
= idesc
->operands
[0];
9559 opnd2
= idesc
->operands
[1];
9560 if (opnd1
== IA64_OPND_AR3
)
9562 else if (opnd2
== IA64_OPND_AR3
)
9566 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9567 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9571 ia64_free_opcode (idesc
);
9572 idesc
= ia64_find_opcode (mnemonic
);
9573 while (idesc
!= NULL
9574 && (idesc
->operands
[0] != opnd1
9575 || idesc
->operands
[1] != opnd2
))
9576 idesc
= get_next_opcode (idesc
);
9581 if (md
.qp
.X_op
== O_register
)
9583 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9584 md
.qp
.X_op
= O_absent
;
9587 flags
= idesc
->flags
;
9589 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9590 insn_group_break (1, 0, 0);
9592 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9594 as_bad ("`%s' cannot be predicated", idesc
->name
);
9598 /* Build the instruction. */
9599 CURR_SLOT
.qp_regno
= qp_regno
;
9600 CURR_SLOT
.idesc
= idesc
;
9601 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9602 dwarf2_where (&CURR_SLOT
.debug_line
);
9604 /* Add unwind entry, if there is one. */
9605 if (unwind
.current_entry
)
9607 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9608 unwind
.current_entry
= NULL
;
9611 /* Check for dependency violations. */
9615 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9616 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9619 if ((flags
& IA64_OPCODE_LAST
) != 0)
9620 insn_group_break (1, 0, 0);
9622 md
.last_text_seg
= now_seg
;
9625 input_line_pointer
= saved_input_line_pointer
;
9628 /* Called when symbol NAME cannot be found in the symbol table.
9629 Should be used for dynamic valued symbols only. */
9632 md_undefined_symbol (name
)
9633 char *name ATTRIBUTE_UNUSED
;
9638 /* Called for any expression that can not be recognized. When the
9639 function is called, `input_line_pointer' will point to the start of
9646 enum pseudo_type pseudo_type
;
9651 switch (*input_line_pointer
)
9654 /* Find what relocation pseudo-function we're dealing with. */
9656 ch
= *++input_line_pointer
;
9657 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9658 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9660 len
= strlen (pseudo_func
[i
].name
);
9661 if (strncmp (pseudo_func
[i
].name
+ 1,
9662 input_line_pointer
+ 1, len
- 1) == 0
9663 && !is_part_of_name (input_line_pointer
[len
]))
9665 input_line_pointer
+= len
;
9666 pseudo_type
= pseudo_func
[i
].type
;
9670 switch (pseudo_type
)
9672 case PSEUDO_FUNC_RELOC
:
9674 if (*input_line_pointer
!= '(')
9676 as_bad ("Expected '('");
9680 ++input_line_pointer
;
9682 if (*input_line_pointer
++ != ')')
9684 as_bad ("Missing ')'");
9687 if (e
->X_op
!= O_symbol
)
9689 if (e
->X_op
!= O_pseudo_fixup
)
9691 as_bad ("Not a symbolic expression");
9694 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9695 && i
== FUNC_LT_RELATIVE
)
9696 i
= FUNC_LT_FPTR_RELATIVE
;
9699 as_bad ("Illegal combination of relocation functions");
9703 /* Make sure gas doesn't get rid of local symbols that are used
9705 e
->X_op
= O_pseudo_fixup
;
9706 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9709 case PSEUDO_FUNC_CONST
:
9710 e
->X_op
= O_constant
;
9711 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9714 case PSEUDO_FUNC_REG
:
9715 e
->X_op
= O_register
;
9716 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9720 name
= input_line_pointer
- 1;
9722 as_bad ("Unknown pseudo function `%s'", name
);
9728 ++input_line_pointer
;
9730 if (*input_line_pointer
!= ']')
9732 as_bad ("Closing bracket misssing");
9737 if (e
->X_op
!= O_register
)
9738 as_bad ("Register expected as index");
9740 ++input_line_pointer
;
9751 ignore_rest_of_line ();
9754 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9755 a section symbol plus some offset. For relocs involving @fptr(),
9756 directives we don't want such adjustments since we need to have the
9757 original symbol's name in the reloc. */
9759 ia64_fix_adjustable (fix
)
9762 /* Prevent all adjustments to global symbols */
9763 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9766 switch (fix
->fx_r_type
)
9768 case BFD_RELOC_IA64_FPTR64I
:
9769 case BFD_RELOC_IA64_FPTR32MSB
:
9770 case BFD_RELOC_IA64_FPTR32LSB
:
9771 case BFD_RELOC_IA64_FPTR64MSB
:
9772 case BFD_RELOC_IA64_FPTR64LSB
:
9773 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9774 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9784 ia64_force_relocation (fix
)
9787 switch (fix
->fx_r_type
)
9789 case BFD_RELOC_IA64_FPTR64I
:
9790 case BFD_RELOC_IA64_FPTR32MSB
:
9791 case BFD_RELOC_IA64_FPTR32LSB
:
9792 case BFD_RELOC_IA64_FPTR64MSB
:
9793 case BFD_RELOC_IA64_FPTR64LSB
:
9795 case BFD_RELOC_IA64_LTOFF22
:
9796 case BFD_RELOC_IA64_LTOFF64I
:
9797 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9798 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9799 case BFD_RELOC_IA64_PLTOFF22
:
9800 case BFD_RELOC_IA64_PLTOFF64I
:
9801 case BFD_RELOC_IA64_PLTOFF64MSB
:
9802 case BFD_RELOC_IA64_PLTOFF64LSB
:
9811 /* Decide from what point a pc-relative relocation is relative to,
9812 relative to the pc-relative fixup. Er, relatively speaking. */
9814 ia64_pcrel_from_section (fix
, sec
)
9818 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9820 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9826 /* This is called whenever some data item (not an instruction) needs a
9827 fixup. We pick the right reloc code depending on the byteorder
9828 currently in effect. */
9830 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9836 bfd_reloc_code_real_type code
;
9841 /* There are no reloc for 8 and 16 bit quantities, but we allow
9842 them here since they will work fine as long as the expression
9843 is fully defined at the end of the pass over the source file. */
9844 case 1: code
= BFD_RELOC_8
; break;
9845 case 2: code
= BFD_RELOC_16
; break;
9847 if (target_big_endian
)
9848 code
= BFD_RELOC_IA64_DIR32MSB
;
9850 code
= BFD_RELOC_IA64_DIR32LSB
;
9854 if (target_big_endian
)
9855 code
= BFD_RELOC_IA64_DIR64MSB
;
9857 code
= BFD_RELOC_IA64_DIR64LSB
;
9861 if (exp
->X_op
== O_pseudo_fixup
9863 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
)
9865 if (target_big_endian
)
9866 code
= BFD_RELOC_IA64_IPLTMSB
;
9868 code
= BFD_RELOC_IA64_IPLTLSB
;
9870 exp
->X_op
= O_symbol
;
9876 as_bad ("Unsupported fixup size %d", nbytes
);
9877 ignore_rest_of_line ();
9880 if (exp
->X_op
== O_pseudo_fixup
)
9883 exp
->X_op
= O_symbol
;
9884 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9887 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9888 /* We need to store the byte order in effect in case we're going
9889 to fix an 8 or 16 bit relocation (for which there no real
9890 relocs available). See md_apply_fix3(). */
9891 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9894 /* Return the actual relocation we wish to associate with the pseudo
9895 reloc described by SYM and R_TYPE. SYM should be one of the
9896 symbols in the pseudo_func array, or NULL. */
9898 static bfd_reloc_code_real_type
9899 ia64_gen_real_reloc_type (sym
, r_type
)
9901 bfd_reloc_code_real_type r_type
;
9903 bfd_reloc_code_real_type
new = 0;
9910 switch (S_GET_VALUE (sym
))
9912 case FUNC_FPTR_RELATIVE
:
9915 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9916 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9917 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9918 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9919 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9924 case FUNC_GP_RELATIVE
:
9927 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9928 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9929 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9930 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9931 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9932 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9937 case FUNC_LT_RELATIVE
:
9940 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9941 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9946 case FUNC_PC_RELATIVE
:
9949 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9950 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9951 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9952 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9953 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9954 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9959 case FUNC_PLT_RELATIVE
:
9962 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9963 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9964 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9965 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9970 case FUNC_SEC_RELATIVE
:
9973 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9974 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9975 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9976 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9981 case FUNC_SEG_RELATIVE
:
9984 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9985 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9986 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9987 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9992 case FUNC_LTV_RELATIVE
:
9995 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9996 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9997 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9998 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
10003 case FUNC_LT_FPTR_RELATIVE
:
10006 case BFD_RELOC_IA64_IMM22
:
10007 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
10008 case BFD_RELOC_IA64_IMM64
:
10009 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
10018 /* Hmmmm. Should this ever occur? */
10025 /* Here is where generate the appropriate reloc for pseudo relocation
10028 ia64_validate_fix (fix
)
10031 switch (fix
->fx_r_type
)
10033 case BFD_RELOC_IA64_FPTR64I
:
10034 case BFD_RELOC_IA64_FPTR32MSB
:
10035 case BFD_RELOC_IA64_FPTR64LSB
:
10036 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10037 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10038 if (fix
->fx_offset
!= 0)
10039 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10040 "No addend allowed in @fptr() relocation");
10050 fix_insn (fix
, odesc
, value
)
10052 const struct ia64_operand
*odesc
;
10055 bfd_vma insn
[3], t0
, t1
, control_bits
;
10060 slot
= fix
->fx_where
& 0x3;
10061 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10063 /* Bundles are always in little-endian byte order */
10064 t0
= bfd_getl64 (fixpos
);
10065 t1
= bfd_getl64 (fixpos
+ 8);
10066 control_bits
= t0
& 0x1f;
10067 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10068 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10069 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10072 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10074 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10075 insn
[2] |= (((value
& 0x7f) << 13)
10076 | (((value
>> 7) & 0x1ff) << 27)
10077 | (((value
>> 16) & 0x1f) << 22)
10078 | (((value
>> 21) & 0x1) << 21)
10079 | (((value
>> 63) & 0x1) << 36));
10081 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10083 if (value
& ~0x3fffffffffffffffULL
)
10084 err
= "integer operand out of range";
10085 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10086 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10088 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10091 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10092 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10093 | (((value
>> 0) & 0xfffff) << 13));
10096 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10099 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10101 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10102 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10103 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10104 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10107 /* Attempt to simplify or even eliminate a fixup. The return value is
10108 ignored; perhaps it was once meaningful, but now it is historical.
10109 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10111 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10115 md_apply_fix3 (fix
, valP
, seg
)
10118 segT seg ATTRIBUTE_UNUSED
;
10121 valueT value
= * valP
;
10124 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10128 switch (fix
->fx_r_type
)
10130 case BFD_RELOC_IA64_DIR32MSB
:
10131 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10135 case BFD_RELOC_IA64_DIR32LSB
:
10136 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10140 case BFD_RELOC_IA64_DIR64MSB
:
10141 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10145 case BFD_RELOC_IA64_DIR64LSB
:
10146 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10156 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
10158 /* This must be a TAG13 or TAG13b operand. There are no external
10159 relocs defined for them, so we must give an error. */
10160 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10161 "%s must have a constant value",
10162 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10167 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10168 work. There should be a better way to handle this. */
10170 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10172 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10174 if (fix
->tc_fix_data
.bigendian
)
10175 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10177 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10182 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10187 /* Generate the BFD reloc to be stuck in the object file from the
10188 fixup used internally in the assembler. */
10191 tc_gen_reloc (sec
, fixp
)
10192 asection
*sec ATTRIBUTE_UNUSED
;
10197 reloc
= xmalloc (sizeof (*reloc
));
10198 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10199 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10200 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10201 reloc
->addend
= fixp
->fx_offset
;
10202 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10206 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10207 "Cannot represent %s relocation in object file",
10208 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10213 /* Turn a string in input_line_pointer into a floating point constant
10214 of type TYPE, and store the appropriate bytes in *LIT. The number
10215 of LITTLENUMS emitted is stored in *SIZE. An error message is
10216 returned, or NULL on OK. */
10218 #define MAX_LITTLENUMS 5
10221 md_atof (type
, lit
, size
)
10226 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10227 LITTLENUM_TYPE
*word
;
10257 return "Bad call to MD_ATOF()";
10259 t
= atof_ieee (input_line_pointer
, type
, words
);
10261 input_line_pointer
= t
;
10262 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10264 for (word
= words
+ prec
- 1; prec
--;)
10266 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10267 lit
+= sizeof (LITTLENUM_TYPE
);
10272 /* Round up a section's size to the appropriate boundary. */
10274 md_section_align (seg
, size
)
10278 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10279 valueT mask
= ((valueT
) 1 << align
) - 1;
10281 return (size
+ mask
) & ~mask
;
10284 /* Handle ia64 specific semantics of the align directive. */
10287 ia64_md_do_align (n
, fill
, len
, max
)
10288 int n ATTRIBUTE_UNUSED
;
10289 const char *fill ATTRIBUTE_UNUSED
;
10290 int len ATTRIBUTE_UNUSED
;
10291 int max ATTRIBUTE_UNUSED
;
10293 if (subseg_text_p (now_seg
))
10294 ia64_flush_insns ();
10297 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10298 of an rs_align_code fragment. */
10301 ia64_handle_align (fragp
)
10304 /* Use mfi bundle of nops with no stop bits. */
10305 static const unsigned char be_nop
[]
10306 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10307 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10308 static const unsigned char le_nop
[]
10309 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10310 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10315 if (fragp
->fr_type
!= rs_align_code
)
10318 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10319 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10321 /* Make sure we are on a 16-byte boundary, in case someone has been
10322 putting data into a text section. */
10325 int fix
= bytes
& 15;
10326 memset (p
, 0, fix
);
10329 fragp
->fr_fix
+= fix
;
10332 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10333 fragp
->fr_var
= 16;