1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS
= 0,
68 SPECIAL_SECTION_SDATA
,
69 SPECIAL_SECTION_RODATA
,
70 SPECIAL_SECTION_COMMENT
,
71 SPECIAL_SECTION_UNWIND
,
72 SPECIAL_SECTION_UNWIND_INFO
,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY
,
75 SPECIAL_SECTION_FINI_ARRAY
,
88 FUNC_LT_FPTR_RELATIVE
,
95 REG_FR
= (REG_GR
+ 128),
96 REG_AR
= (REG_FR
+ 128),
97 REG_CR
= (REG_AR
+ 128),
98 REG_P
= (REG_CR
+ 128),
99 REG_BR
= (REG_P
+ 64),
100 REG_IP
= (REG_BR
+ 8),
107 /* The following are pseudo-registers for use by gas only. */
119 /* The following pseudo-registers are used for unwind directives only: */
127 DYNREG_GR
= 0, /* dynamic general purpose register */
128 DYNREG_FR
, /* dynamic floating point register */
129 DYNREG_PR
, /* dynamic predicate register */
133 enum operand_match_result
136 OPERAND_OUT_OF_RANGE
,
140 /* On the ia64, we can't know the address of a text label until the
141 instructions are packed into a bundle. To handle this, we keep
142 track of the list of labels that appear in front of each
146 struct label_fix
*next
;
150 extern int target_big_endian
;
152 /* Characters which always start a comment. */
153 const char comment_chars
[] = "";
155 /* Characters which start a comment at the beginning of a line. */
156 const char line_comment_chars
[] = "#";
158 /* Characters which may be used to separate multiple commands on a
160 const char line_separator_chars
[] = ";";
162 /* Characters which are used to indicate an exponent in a floating
164 const char EXP_CHARS
[] = "eE";
166 /* Characters which mean that a number is a floating point constant,
168 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
170 /* ia64-specific option processing: */
172 const char *md_shortopts
= "m:N:x::";
174 struct option md_longopts
[] =
176 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
177 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
178 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
179 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
182 size_t md_longopts_size
= sizeof (md_longopts
);
186 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
187 struct hash_control
*reg_hash
; /* register name hash table */
188 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
189 struct hash_control
*const_hash
; /* constant hash table */
190 struct hash_control
*entry_hash
; /* code entry hint hash table */
192 symbolS
*regsym
[REG_NUM
];
194 /* If X_op is != O_absent, the registername for the instruction's
195 qualifying predicate. If NULL, p0 is assumed for instructions
196 that are predicatable. */
203 explicit_mode
: 1, /* which mode we're in */
204 default_explicit_mode
: 1, /* which mode is the default */
205 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
207 keep_pending_output
: 1;
209 /* Each bundle consists of up to three instructions. We keep
210 track of four most recent instructions so we can correctly set
211 the end_of_insn_group for the last instruction in a bundle. */
213 int num_slots_in_use
;
217 end_of_insn_group
: 1,
218 manual_bundling_on
: 1,
219 manual_bundling_off
: 1;
220 signed char user_template
; /* user-selected template, if any */
221 unsigned char qp_regno
; /* qualifying predicate */
222 /* This duplicates a good fraction of "struct fix" but we
223 can't use a "struct fix" instead since we can't call
224 fix_new_exp() until we know the address of the instruction. */
228 bfd_reloc_code_real_type code
;
229 enum ia64_opnd opnd
; /* type of operand in need of fix */
230 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
231 expressionS expr
; /* the value to be inserted */
233 fixup
[2]; /* at most two fixups per insn */
234 struct ia64_opcode
*idesc
;
235 struct label_fix
*label_fixups
;
236 struct label_fix
*tag_fixups
;
237 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
240 unsigned int src_line
;
241 struct dwarf2_line_info debug_line
;
249 struct dynreg
*next
; /* next dynamic register */
251 unsigned short base
; /* the base register number */
252 unsigned short num_regs
; /* # of registers in this set */
254 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
256 flagword flags
; /* ELF-header flags */
259 unsigned hint
:1; /* is this hint currently valid? */
260 bfd_vma offset
; /* mem.offset offset */
261 bfd_vma base
; /* mem.offset base */
264 int path
; /* number of alt. entry points seen */
265 const char **entry_labels
; /* labels of all alternate paths in
266 the current DV-checking block. */
267 int maxpaths
; /* size currently allocated for
269 /* Support for hardware errata workarounds. */
271 /* Record data about the last three insn groups. */
274 /* B-step workaround.
275 For each predicate register, this is set if the corresponding insn
276 group conditionally sets this register with one of the affected
279 /* B-step workaround.
280 For each general register, this is set if the corresponding insn
281 a) is conditional one one of the predicate registers for which
282 P_REG_SET is 1 in the corresponding entry of the previous group,
283 b) sets this general register with one of the affected
285 int g_reg_set_conditionally
[128];
289 int pointer_size
; /* size in bytes of a pointer */
290 int pointer_size_shift
; /* shift size of a pointer for alignment */
294 /* application registers: */
300 #define AR_BSPSTORE 18
315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
317 {"ar.rsc", 16}, {"ar.bsp", 17},
318 {"ar.bspstore", 18}, {"ar.rnat", 19},
319 {"ar.fcr", 21}, {"ar.eflag", 24},
320 {"ar.csd", 25}, {"ar.ssd", 26},
321 {"ar.cflg", 27}, {"ar.fsr", 28},
322 {"ar.fir", 29}, {"ar.fdr", 30},
323 {"ar.ccv", 32}, {"ar.unat", 36},
324 {"ar.fpsr", 40}, {"ar.itc", 44},
325 {"ar.pfs", 64}, {"ar.lc", 65},
346 /* control registers: */
388 static const struct const_desc
395 /* PSR constant masks: */
398 {"psr.be", ((valueT
) 1) << 1},
399 {"psr.up", ((valueT
) 1) << 2},
400 {"psr.ac", ((valueT
) 1) << 3},
401 {"psr.mfl", ((valueT
) 1) << 4},
402 {"psr.mfh", ((valueT
) 1) << 5},
404 {"psr.ic", ((valueT
) 1) << 13},
405 {"psr.i", ((valueT
) 1) << 14},
406 {"psr.pk", ((valueT
) 1) << 15},
408 {"psr.dt", ((valueT
) 1) << 17},
409 {"psr.dfl", ((valueT
) 1) << 18},
410 {"psr.dfh", ((valueT
) 1) << 19},
411 {"psr.sp", ((valueT
) 1) << 20},
412 {"psr.pp", ((valueT
) 1) << 21},
413 {"psr.di", ((valueT
) 1) << 22},
414 {"psr.si", ((valueT
) 1) << 23},
415 {"psr.db", ((valueT
) 1) << 24},
416 {"psr.lp", ((valueT
) 1) << 25},
417 {"psr.tb", ((valueT
) 1) << 26},
418 {"psr.rt", ((valueT
) 1) << 27},
419 /* 28-31: reserved */
420 /* 32-33: cpl (current privilege level) */
421 {"psr.is", ((valueT
) 1) << 34},
422 {"psr.mc", ((valueT
) 1) << 35},
423 {"psr.it", ((valueT
) 1) << 36},
424 {"psr.id", ((valueT
) 1) << 37},
425 {"psr.da", ((valueT
) 1) << 38},
426 {"psr.dd", ((valueT
) 1) << 39},
427 {"psr.ss", ((valueT
) 1) << 40},
428 /* 41-42: ri (restart instruction) */
429 {"psr.ed", ((valueT
) 1) << 43},
430 {"psr.bn", ((valueT
) 1) << 44},
433 /* indirect register-sets/memory: */
442 { "CPUID", IND_CPUID
},
443 { "cpuid", IND_CPUID
},
455 /* Pseudo functions used to indicate relocation types (these functions
456 start with an at sign (@). */
478 /* reloc pseudo functions (these must come first!): */
479 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
480 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
481 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
482 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
483 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
484 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
485 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
486 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
488 { "iplt", PSEUDO_FUNC_RELOC
, { 0 } },
490 /* mbtype4 constants: */
491 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
492 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
493 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
494 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
495 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
497 /* fclass constants: */
498 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
499 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
500 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
501 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
502 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
503 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
504 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
505 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
506 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
508 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
510 /* unwind-related constants: */
511 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
512 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
513 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
515 /* unwind-related registers: */
516 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
519 /* 41-bit nop opcodes (one per unit): */
520 static const bfd_vma nop
[IA64_NUM_UNITS
] =
522 0x0000000000LL
, /* NIL => break 0 */
523 0x0008000000LL
, /* I-unit nop */
524 0x0008000000LL
, /* M-unit nop */
525 0x4000000000LL
, /* B-unit nop */
526 0x0008000000LL
, /* F-unit nop */
527 0x0008000000LL
, /* L-"unit" nop */
528 0x0008000000LL
, /* X-unit nop */
531 /* Can't be `const' as it's passed to input routines (which have the
532 habit of setting temporary sentinels. */
533 static char special_section_name
[][20] =
535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
536 {".IA_64.unwind"}, {".IA_64.unwind_info"},
537 {".init_array"}, {".fini_array"}
540 static char *special_linkonce_name
[] =
542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
545 /* The best template for a particular sequence of up to three
547 #define N IA64_NUM_TYPES
548 static unsigned char best_template
[N
][N
][N
];
551 /* Resource dependencies currently in effect */
553 int depind
; /* dependency index */
554 const struct ia64_dependency
*dependency
; /* actual dependency */
555 unsigned specific
:1, /* is this a specific bit/regno? */
556 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
557 int index
; /* specific regno/bit within dependency */
558 int note
; /* optional qualifying note (0 if none) */
562 int insn_srlz
; /* current insn serialization state */
563 int data_srlz
; /* current data serialization state */
564 int qp_regno
; /* qualifying predicate for this usage */
565 char *file
; /* what file marked this dependency */
566 unsigned int line
; /* what line marked this dependency */
567 struct mem_offset mem_offset
; /* optional memory offset hint */
568 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
569 int path
; /* corresponding code entry index */
571 static int regdepslen
= 0;
572 static int regdepstotlen
= 0;
573 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
574 static const char *dv_sem
[] = { "none", "implied", "impliedf",
575 "data", "instr", "specific", "stop", "other" };
576 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
578 /* Current state of PR mutexation */
579 static struct qpmutex
{
582 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
583 static int qp_mutexeslen
= 0;
584 static int qp_mutexestotlen
= 0;
585 static valueT qp_safe_across_calls
= 0;
587 /* Current state of PR implications */
588 static struct qp_imply
{
591 unsigned p2_branched
:1;
593 } *qp_implies
= NULL
;
594 static int qp_implieslen
= 0;
595 static int qp_impliestotlen
= 0;
597 /* Keep track of static GR values so that indirect register usage can
598 sometimes be tracked. */
603 } gr_values
[128] = {{ 1, 0, 0 }};
605 /* These are the routines required to output the various types of
608 /* A slot_number is a frag address plus the slot index (0-2). We use the
609 frag address here so that if there is a section switch in the middle of
610 a function, then instructions emitted to a different section are not
611 counted. Since there may be more than one frag for a function, this
612 means we also need to keep track of which frag this address belongs to
613 so we can compute inter-frag distances. This also nicely solves the
614 problem with nops emitted for align directives, which can't easily be
615 counted, but can easily be derived from frag sizes. */
617 typedef struct unw_rec_list
{
619 unsigned long slot_number
;
621 struct unw_rec_list
*next
;
624 #define SLOT_NUM_NOT_SET (unsigned)-1
628 unsigned long next_slot_number
;
629 fragS
*next_slot_frag
;
631 /* Maintain a list of unwind entries for the current function. */
635 /* Any unwind entires that should be attached to the current slot
636 that an insn is being constructed for. */
637 unw_rec_list
*current_entry
;
639 /* These are used to create the unwind table entry for this function. */
642 symbolS
*info
; /* pointer to unwind info */
643 symbolS
*personality_routine
;
645 subsegT saved_text_subseg
;
646 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
648 /* TRUE if processing unwind directives in a prologue region. */
651 unsigned int prologue_count
; /* number of .prologues seen so far */
654 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
656 /* Forward delarations: */
657 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
658 static void set_section
PARAMS ((char *name
));
659 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
660 unsigned int, unsigned int));
661 static void dot_radix
PARAMS ((int));
662 static void dot_special_section
PARAMS ((int));
663 static void dot_proc
PARAMS ((int));
664 static void dot_fframe
PARAMS ((int));
665 static void dot_vframe
PARAMS ((int));
666 static void dot_vframesp
PARAMS ((int));
667 static void dot_vframepsp
PARAMS ((int));
668 static void dot_save
PARAMS ((int));
669 static void dot_restore
PARAMS ((int));
670 static void dot_restorereg
PARAMS ((int));
671 static void dot_restorereg_p
PARAMS ((int));
672 static void dot_handlerdata
PARAMS ((int));
673 static void dot_unwentry
PARAMS ((int));
674 static void dot_altrp
PARAMS ((int));
675 static void dot_savemem
PARAMS ((int));
676 static void dot_saveg
PARAMS ((int));
677 static void dot_savef
PARAMS ((int));
678 static void dot_saveb
PARAMS ((int));
679 static void dot_savegf
PARAMS ((int));
680 static void dot_spill
PARAMS ((int));
681 static void dot_spillreg
PARAMS ((int));
682 static void dot_spillmem
PARAMS ((int));
683 static void dot_spillreg_p
PARAMS ((int));
684 static void dot_spillmem_p
PARAMS ((int));
685 static void dot_label_state
PARAMS ((int));
686 static void dot_copy_state
PARAMS ((int));
687 static void dot_unwabi
PARAMS ((int));
688 static void dot_personality
PARAMS ((int));
689 static void dot_body
PARAMS ((int));
690 static void dot_prologue
PARAMS ((int));
691 static void dot_endp
PARAMS ((int));
692 static void dot_template
PARAMS ((int));
693 static void dot_regstk
PARAMS ((int));
694 static void dot_rot
PARAMS ((int));
695 static void dot_byteorder
PARAMS ((int));
696 static void dot_psr
PARAMS ((int));
697 static void dot_alias
PARAMS ((int));
698 static void dot_ln
PARAMS ((int));
699 static char *parse_section_name
PARAMS ((void));
700 static void dot_xdata
PARAMS ((int));
701 static void stmt_float_cons
PARAMS ((int));
702 static void stmt_cons_ua
PARAMS ((int));
703 static void dot_xfloat_cons
PARAMS ((int));
704 static void dot_xstringer
PARAMS ((int));
705 static void dot_xdata_ua
PARAMS ((int));
706 static void dot_xfloat_cons_ua
PARAMS ((int));
707 static void print_prmask
PARAMS ((valueT mask
));
708 static void dot_pred_rel
PARAMS ((int));
709 static void dot_reg_val
PARAMS ((int));
710 static void dot_dv_mode
PARAMS ((int));
711 static void dot_entry
PARAMS ((int));
712 static void dot_mem_offset
PARAMS ((int));
713 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
714 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
715 static void declare_register_set
PARAMS ((const char *, int, int));
716 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
717 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
720 static int parse_operand
PARAMS ((expressionS
*e
));
721 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
722 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
723 static void emit_one_bundle
PARAMS ((void));
724 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
725 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
726 bfd_reloc_code_real_type r_type
));
727 static void insn_group_break
PARAMS ((int, int, int));
728 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
729 struct rsrc
*, int depind
, int path
));
730 static void add_qp_mutex
PARAMS((valueT mask
));
731 static void add_qp_imply
PARAMS((int p1
, int p2
));
732 static void clear_qp_branch_flag
PARAMS((valueT mask
));
733 static void clear_qp_mutex
PARAMS((valueT mask
));
734 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
735 static void clear_register_values
PARAMS ((void));
736 static void print_dependency
PARAMS ((const char *action
, int depind
));
737 static void instruction_serialization
PARAMS ((void));
738 static void data_serialization
PARAMS ((void));
739 static void remove_marked_resource
PARAMS ((struct rsrc
*));
740 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
741 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
742 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
743 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
744 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
745 struct ia64_opcode
*, int, struct rsrc
[], int, int));
746 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
747 static void check_dependencies
PARAMS((struct ia64_opcode
*));
748 static void mark_resources
PARAMS((struct ia64_opcode
*));
749 static void update_dependencies
PARAMS((struct ia64_opcode
*));
750 static void note_register_values
PARAMS((struct ia64_opcode
*));
751 static int qp_mutex
PARAMS ((int, int, int));
752 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
753 static void output_vbyte_mem
PARAMS ((int, char *, char *));
754 static void count_output
PARAMS ((int, char *, char *));
755 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
756 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
757 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
758 static void output_P1_format
PARAMS ((vbyte_func
, int));
759 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
760 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
761 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
762 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
763 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
764 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
765 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
766 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
767 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
768 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
769 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
770 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
771 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
772 static char format_ab_reg
PARAMS ((int, int));
773 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
775 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
776 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
778 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
779 static void free_list_records
PARAMS ((unw_rec_list
*));
780 static unw_rec_list
*output_prologue
PARAMS ((void));
781 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
782 static unw_rec_list
*output_body
PARAMS ((void));
783 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
784 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
785 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
786 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
787 static unw_rec_list
*output_rp_when
PARAMS ((void));
788 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
789 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
790 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
791 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
792 static unw_rec_list
*output_pfs_when
PARAMS ((void));
793 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
794 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
795 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
796 static unw_rec_list
*output_preds_when
PARAMS ((void));
797 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
798 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
799 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
800 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
801 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
802 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
803 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
804 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
805 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
806 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
807 static unw_rec_list
*output_unat_when
PARAMS ((void));
808 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
809 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
810 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_lc_when
PARAMS ((void));
812 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
813 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
814 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
816 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
817 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
818 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
819 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
820 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
821 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
822 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
823 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_bsp_when
PARAMS ((void));
825 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
826 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
827 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
829 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
830 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
831 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
832 static unw_rec_list
*output_rnat_when
PARAMS ((void));
833 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
834 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
835 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
836 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
837 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
838 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
839 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
840 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
841 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
842 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
844 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
846 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
848 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
849 unsigned int, unsigned int));
850 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
851 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
852 static int calc_record_size
PARAMS ((unw_rec_list
*));
853 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
854 static int count_bits
PARAMS ((unsigned long));
855 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
856 unsigned long, fragS
*));
857 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
858 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
859 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
860 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
861 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
862 static int generate_unwind_image
PARAMS ((const char *));
864 /* Build the unwind section name by appending the (possibly stripped)
865 text section NAME to the unwind PREFIX. The resulting string
866 pointer is assigned to RESULT. The string is allocated on the
867 stack, so this must be a macro... */
868 #define make_unw_section_name(special, text_name, result) \
870 char *_prefix = special_section_name[special]; \
871 char *_suffix = text_name; \
872 size_t _prefix_len, _suffix_len; \
874 if (strncmp (text_name, ".gnu.linkonce.t.", \
875 sizeof (".gnu.linkonce.t.") - 1) == 0) \
877 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
878 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
880 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
881 _result = alloca (_prefix_len + _suffix_len + 1); \
882 memcpy (_result, _prefix, _prefix_len); \
883 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
884 _result[_prefix_len + _suffix_len] = '\0'; \
889 /* Determine if application register REGNUM resides in the integer
890 unit (as opposed to the memory unit). */
892 ar_is_in_integer_unit (reg
)
897 return (reg
== 64 /* pfs */
898 || reg
== 65 /* lc */
899 || reg
== 66 /* ec */
900 /* ??? ias accepts and puts these in the integer unit. */
901 || (reg
>= 112 && reg
<= 127));
904 /* Switch to section NAME and create section if necessary. It's
905 rather ugly that we have to manipulate input_line_pointer but I
906 don't see any other way to accomplish the same thing without
907 changing obj-elf.c (which may be the Right Thing, in the end). */
912 char *saved_input_line_pointer
;
914 saved_input_line_pointer
= input_line_pointer
;
915 input_line_pointer
= name
;
917 input_line_pointer
= saved_input_line_pointer
;
920 /* Map 's' to SHF_IA_64_SHORT. */
923 ia64_elf_section_letter (letter
, ptr_msg
)
928 return SHF_IA_64_SHORT
;
930 *ptr_msg
= _("Bad .section directive: want a,s,w,x,M,S in string");
934 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
937 ia64_elf_section_flags (flags
, attr
, type
)
939 int attr
, type ATTRIBUTE_UNUSED
;
941 if (attr
& SHF_IA_64_SHORT
)
942 flags
|= SEC_SMALL_DATA
;
947 ia64_elf_section_type (str
, len
)
951 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
952 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
955 len
= sizeof (ELF_STRING_ia64_unwind_info_once
) - 1;
956 if (strncmp (str
, ELF_STRING_ia64_unwind_info_once
, len
) == 0)
959 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
960 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
961 return SHT_IA_64_UNWIND
;
963 len
= sizeof (ELF_STRING_ia64_unwind_once
) - 1;
964 if (strncmp (str
, ELF_STRING_ia64_unwind_once
, len
) == 0)
965 return SHT_IA_64_UNWIND
;
971 set_regstack (ins
, locs
, outs
, rots
)
972 unsigned int ins
, locs
, outs
, rots
;
977 sof
= ins
+ locs
+ outs
;
980 as_bad ("Size of frame exceeds maximum of 96 registers");
985 as_warn ("Size of rotating registers exceeds frame size");
988 md
.in
.base
= REG_GR
+ 32;
989 md
.loc
.base
= md
.in
.base
+ ins
;
990 md
.out
.base
= md
.loc
.base
+ locs
;
992 md
.in
.num_regs
= ins
;
993 md
.loc
.num_regs
= locs
;
994 md
.out
.num_regs
= outs
;
995 md
.rot
.num_regs
= rots
;
1002 struct label_fix
*lfix
;
1004 subsegT saved_subseg
;
1007 if (!md
.last_text_seg
)
1010 saved_seg
= now_seg
;
1011 saved_subseg
= now_subseg
;
1013 subseg_set (md
.last_text_seg
, 0);
1015 while (md
.num_slots_in_use
> 0)
1016 emit_one_bundle (); /* force out queued instructions */
1018 /* In case there are labels following the last instruction, resolve
1020 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1022 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1023 symbol_set_frag (lfix
->sym
, frag_now
);
1025 CURR_SLOT
.label_fixups
= 0;
1026 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1028 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1029 symbol_set_frag (lfix
->sym
, frag_now
);
1031 CURR_SLOT
.tag_fixups
= 0;
1033 /* In case there are unwind directives following the last instruction,
1034 resolve those now. We only handle body and prologue directives here.
1035 Give an error for others. */
1036 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1038 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1039 || ptr
->r
.type
== body
)
1041 ptr
->slot_number
= (unsigned long) frag_more (0);
1042 ptr
->slot_frag
= frag_now
;
1045 as_bad (_("Unwind directive not followed by an instruction."));
1047 unwind
.current_entry
= NULL
;
1049 subseg_set (saved_seg
, saved_subseg
);
1051 if (md
.qp
.X_op
== O_register
)
1052 as_bad ("qualifying predicate not followed by instruction");
1056 ia64_do_align (nbytes
)
1059 char *saved_input_line_pointer
= input_line_pointer
;
1061 input_line_pointer
= "";
1062 s_align_bytes (nbytes
);
1063 input_line_pointer
= saved_input_line_pointer
;
1067 ia64_cons_align (nbytes
)
1072 char *saved_input_line_pointer
= input_line_pointer
;
1073 input_line_pointer
= "";
1074 s_align_bytes (nbytes
);
1075 input_line_pointer
= saved_input_line_pointer
;
1079 /* Output COUNT bytes to a memory location. */
1080 static unsigned char *vbyte_mem_ptr
= NULL
;
1083 output_vbyte_mem (count
, ptr
, comment
)
1086 char *comment ATTRIBUTE_UNUSED
;
1089 if (vbyte_mem_ptr
== NULL
)
1094 for (x
= 0; x
< count
; x
++)
1095 *(vbyte_mem_ptr
++) = ptr
[x
];
1098 /* Count the number of bytes required for records. */
1099 static int vbyte_count
= 0;
1101 count_output (count
, ptr
, comment
)
1103 char *ptr ATTRIBUTE_UNUSED
;
1104 char *comment ATTRIBUTE_UNUSED
;
1106 vbyte_count
+= count
;
1110 output_R1_format (f
, rtype
, rlen
)
1112 unw_record_type rtype
;
1119 output_R3_format (f
, rtype
, rlen
);
1125 else if (rtype
!= prologue
)
1126 as_bad ("record type is not valid");
1128 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1129 (*f
) (1, &byte
, NULL
);
1133 output_R2_format (f
, mask
, grsave
, rlen
)
1140 mask
= (mask
& 0x0f);
1141 grsave
= (grsave
& 0x7f);
1143 bytes
[0] = (UNW_R2
| (mask
>> 1));
1144 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1145 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1146 (*f
) (count
, bytes
, NULL
);
1150 output_R3_format (f
, rtype
, rlen
)
1152 unw_record_type rtype
;
1159 output_R1_format (f
, rtype
, rlen
);
1165 else if (rtype
!= prologue
)
1166 as_bad ("record type is not valid");
1167 bytes
[0] = (UNW_R3
| r
);
1168 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1169 (*f
) (count
+ 1, bytes
, NULL
);
1173 output_P1_format (f
, brmask
)
1178 byte
= UNW_P1
| (brmask
& 0x1f);
1179 (*f
) (1, &byte
, NULL
);
1183 output_P2_format (f
, brmask
, gr
)
1189 brmask
= (brmask
& 0x1f);
1190 bytes
[0] = UNW_P2
| (brmask
>> 1);
1191 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1192 (*f
) (2, bytes
, NULL
);
1196 output_P3_format (f
, rtype
, reg
)
1198 unw_record_type rtype
;
1243 as_bad ("Invalid record type for P3 format.");
1245 bytes
[0] = (UNW_P3
| (r
>> 1));
1246 bytes
[1] = (((r
& 1) << 7) | reg
);
1247 (*f
) (2, bytes
, NULL
);
1251 output_P4_format (f
, imask
, imask_size
)
1253 unsigned char *imask
;
1254 unsigned long imask_size
;
1257 (*f
) (imask_size
, imask
, NULL
);
1261 output_P5_format (f
, grmask
, frmask
)
1264 unsigned long frmask
;
1267 grmask
= (grmask
& 0x0f);
1270 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1271 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1272 bytes
[3] = (frmask
& 0x000000ff);
1273 (*f
) (4, bytes
, NULL
);
1277 output_P6_format (f
, rtype
, rmask
)
1279 unw_record_type rtype
;
1285 if (rtype
== gr_mem
)
1287 else if (rtype
!= fr_mem
)
1288 as_bad ("Invalid record type for format P6");
1289 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1290 (*f
) (1, &byte
, NULL
);
1294 output_P7_format (f
, rtype
, w1
, w2
)
1296 unw_record_type rtype
;
1303 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1308 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1358 bytes
[0] = (UNW_P7
| r
);
1359 (*f
) (count
, bytes
, NULL
);
1363 output_P8_format (f
, rtype
, t
)
1365 unw_record_type rtype
;
1404 case bspstore_psprel
:
1407 case bspstore_sprel
:
1419 case priunat_when_gr
:
1422 case priunat_psprel
:
1428 case priunat_when_mem
:
1435 count
+= output_leb128 (bytes
+ 2, t
, 0);
1436 (*f
) (count
, bytes
, NULL
);
1440 output_P9_format (f
, grmask
, gr
)
1447 bytes
[1] = (grmask
& 0x0f);
1448 bytes
[2] = (gr
& 0x7f);
1449 (*f
) (3, bytes
, NULL
);
1453 output_P10_format (f
, abi
, context
)
1460 bytes
[1] = (abi
& 0xff);
1461 bytes
[2] = (context
& 0xff);
1462 (*f
) (3, bytes
, NULL
);
1466 output_B1_format (f
, rtype
, label
)
1468 unw_record_type rtype
;
1469 unsigned long label
;
1475 output_B4_format (f
, rtype
, label
);
1478 if (rtype
== copy_state
)
1480 else if (rtype
!= label_state
)
1481 as_bad ("Invalid record type for format B1");
1483 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1484 (*f
) (1, &byte
, NULL
);
1488 output_B2_format (f
, ecount
, t
)
1490 unsigned long ecount
;
1497 output_B3_format (f
, ecount
, t
);
1500 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1501 count
+= output_leb128 (bytes
+ 1, t
, 0);
1502 (*f
) (count
, bytes
, NULL
);
1506 output_B3_format (f
, ecount
, t
)
1508 unsigned long ecount
;
1515 output_B2_format (f
, ecount
, t
);
1519 count
+= output_leb128 (bytes
+ 1, t
, 0);
1520 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1521 (*f
) (count
, bytes
, NULL
);
1525 output_B4_format (f
, rtype
, label
)
1527 unw_record_type rtype
;
1528 unsigned long label
;
1535 output_B1_format (f
, rtype
, label
);
1539 if (rtype
== copy_state
)
1541 else if (rtype
!= label_state
)
1542 as_bad ("Invalid record type for format B1");
1544 bytes
[0] = (UNW_B4
| (r
<< 3));
1545 count
+= output_leb128 (bytes
+ 1, label
, 0);
1546 (*f
) (count
, bytes
, NULL
);
1550 format_ab_reg (ab
, reg
)
1557 ret
= (ab
<< 5) | reg
;
1562 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1564 unw_record_type rtype
;
1574 if (rtype
== spill_sprel
)
1576 else if (rtype
!= spill_psprel
)
1577 as_bad ("Invalid record type for format X1");
1578 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1579 count
+= output_leb128 (bytes
+ 2, t
, 0);
1580 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1581 (*f
) (count
, bytes
, NULL
);
1585 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1594 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1595 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1596 count
+= output_leb128 (bytes
+ 3, t
, 0);
1597 (*f
) (count
, bytes
, NULL
);
1601 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1603 unw_record_type rtype
;
1614 if (rtype
== spill_sprel_p
)
1616 else if (rtype
!= spill_psprel_p
)
1617 as_bad ("Invalid record type for format X3");
1618 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1619 bytes
[2] = format_ab_reg (ab
, reg
);
1620 count
+= output_leb128 (bytes
+ 3, t
, 0);
1621 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1622 (*f
) (count
, bytes
, NULL
);
1626 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1636 bytes
[1] = (qp
& 0x3f);
1637 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1638 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1639 count
+= output_leb128 (bytes
+ 4, t
, 0);
1640 (*f
) (count
, bytes
, NULL
);
1643 /* This function allocates a record list structure, and initializes fields. */
1645 static unw_rec_list
*
1646 alloc_record (unw_record_type t
)
1649 ptr
= xmalloc (sizeof (*ptr
));
1651 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1656 /* This function frees an entire list of record structures. */
1659 free_list_records (unw_rec_list
*first
)
1662 for (ptr
= first
; ptr
!= NULL
;)
1664 unw_rec_list
*tmp
= ptr
;
1666 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1667 && tmp
->r
.record
.r
.mask
.i
)
1668 free (tmp
->r
.record
.r
.mask
.i
);
1675 static unw_rec_list
*
1678 unw_rec_list
*ptr
= alloc_record (prologue
);
1679 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1683 static unw_rec_list
*
1684 output_prologue_gr (saved_mask
, reg
)
1685 unsigned int saved_mask
;
1688 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1689 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1690 ptr
->r
.record
.r
.grmask
= saved_mask
;
1691 ptr
->r
.record
.r
.grsave
= reg
;
1695 static unw_rec_list
*
1698 unw_rec_list
*ptr
= alloc_record (body
);
1702 static unw_rec_list
*
1703 output_mem_stack_f (size
)
1706 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1707 ptr
->r
.record
.p
.size
= size
;
1711 static unw_rec_list
*
1712 output_mem_stack_v ()
1714 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1718 static unw_rec_list
*
1722 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1723 ptr
->r
.record
.p
.gr
= gr
;
1727 static unw_rec_list
*
1728 output_psp_sprel (offset
)
1729 unsigned int offset
;
1731 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1732 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1736 static unw_rec_list
*
1739 unw_rec_list
*ptr
= alloc_record (rp_when
);
1743 static unw_rec_list
*
1747 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1748 ptr
->r
.record
.p
.gr
= gr
;
1752 static unw_rec_list
*
1756 unw_rec_list
*ptr
= alloc_record (rp_br
);
1757 ptr
->r
.record
.p
.br
= br
;
1761 static unw_rec_list
*
1762 output_rp_psprel (offset
)
1763 unsigned int offset
;
1765 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1766 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1770 static unw_rec_list
*
1771 output_rp_sprel (offset
)
1772 unsigned int offset
;
1774 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1775 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1779 static unw_rec_list
*
1782 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1786 static unw_rec_list
*
1790 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1791 ptr
->r
.record
.p
.gr
= gr
;
1795 static unw_rec_list
*
1796 output_pfs_psprel (offset
)
1797 unsigned int offset
;
1799 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1800 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1804 static unw_rec_list
*
1805 output_pfs_sprel (offset
)
1806 unsigned int offset
;
1808 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1809 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1813 static unw_rec_list
*
1814 output_preds_when ()
1816 unw_rec_list
*ptr
= alloc_record (preds_when
);
1820 static unw_rec_list
*
1821 output_preds_gr (gr
)
1824 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1825 ptr
->r
.record
.p
.gr
= gr
;
1829 static unw_rec_list
*
1830 output_preds_psprel (offset
)
1831 unsigned int offset
;
1833 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1834 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1838 static unw_rec_list
*
1839 output_preds_sprel (offset
)
1840 unsigned int offset
;
1842 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1843 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1847 static unw_rec_list
*
1848 output_fr_mem (mask
)
1851 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1852 ptr
->r
.record
.p
.rmask
= mask
;
1856 static unw_rec_list
*
1857 output_frgr_mem (gr_mask
, fr_mask
)
1858 unsigned int gr_mask
;
1859 unsigned int fr_mask
;
1861 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1862 ptr
->r
.record
.p
.grmask
= gr_mask
;
1863 ptr
->r
.record
.p
.frmask
= fr_mask
;
1867 static unw_rec_list
*
1868 output_gr_gr (mask
, reg
)
1872 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1873 ptr
->r
.record
.p
.grmask
= mask
;
1874 ptr
->r
.record
.p
.gr
= reg
;
1878 static unw_rec_list
*
1879 output_gr_mem (mask
)
1882 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1883 ptr
->r
.record
.p
.rmask
= mask
;
1887 static unw_rec_list
*
1888 output_br_mem (unsigned int mask
)
1890 unw_rec_list
*ptr
= alloc_record (br_mem
);
1891 ptr
->r
.record
.p
.brmask
= mask
;
1895 static unw_rec_list
*
1896 output_br_gr (save_mask
, reg
)
1897 unsigned int save_mask
;
1900 unw_rec_list
*ptr
= alloc_record (br_gr
);
1901 ptr
->r
.record
.p
.brmask
= save_mask
;
1902 ptr
->r
.record
.p
.gr
= reg
;
1906 static unw_rec_list
*
1907 output_spill_base (offset
)
1908 unsigned int offset
;
1910 unw_rec_list
*ptr
= alloc_record (spill_base
);
1911 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1915 static unw_rec_list
*
1918 unw_rec_list
*ptr
= alloc_record (unat_when
);
1922 static unw_rec_list
*
1926 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1927 ptr
->r
.record
.p
.gr
= gr
;
1931 static unw_rec_list
*
1932 output_unat_psprel (offset
)
1933 unsigned int offset
;
1935 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1936 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1940 static unw_rec_list
*
1941 output_unat_sprel (offset
)
1942 unsigned int offset
;
1944 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1945 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1949 static unw_rec_list
*
1952 unw_rec_list
*ptr
= alloc_record (lc_when
);
1956 static unw_rec_list
*
1960 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1961 ptr
->r
.record
.p
.gr
= gr
;
1965 static unw_rec_list
*
1966 output_lc_psprel (offset
)
1967 unsigned int offset
;
1969 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1970 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1974 static unw_rec_list
*
1975 output_lc_sprel (offset
)
1976 unsigned int offset
;
1978 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1979 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1983 static unw_rec_list
*
1986 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1990 static unw_rec_list
*
1994 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1995 ptr
->r
.record
.p
.gr
= gr
;
1999 static unw_rec_list
*
2000 output_fpsr_psprel (offset
)
2001 unsigned int offset
;
2003 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
2004 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2008 static unw_rec_list
*
2009 output_fpsr_sprel (offset
)
2010 unsigned int offset
;
2012 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
2013 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2017 static unw_rec_list
*
2018 output_priunat_when_gr ()
2020 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2024 static unw_rec_list
*
2025 output_priunat_when_mem ()
2027 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2031 static unw_rec_list
*
2032 output_priunat_gr (gr
)
2035 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2036 ptr
->r
.record
.p
.gr
= gr
;
2040 static unw_rec_list
*
2041 output_priunat_psprel (offset
)
2042 unsigned int offset
;
2044 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2045 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2049 static unw_rec_list
*
2050 output_priunat_sprel (offset
)
2051 unsigned int offset
;
2053 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2054 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2058 static unw_rec_list
*
2061 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2065 static unw_rec_list
*
2069 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2070 ptr
->r
.record
.p
.gr
= gr
;
2074 static unw_rec_list
*
2075 output_bsp_psprel (offset
)
2076 unsigned int offset
;
2078 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2079 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2083 static unw_rec_list
*
2084 output_bsp_sprel (offset
)
2085 unsigned int offset
;
2087 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2088 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2092 static unw_rec_list
*
2093 output_bspstore_when ()
2095 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2099 static unw_rec_list
*
2100 output_bspstore_gr (gr
)
2103 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2104 ptr
->r
.record
.p
.gr
= gr
;
2108 static unw_rec_list
*
2109 output_bspstore_psprel (offset
)
2110 unsigned int offset
;
2112 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2113 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2117 static unw_rec_list
*
2118 output_bspstore_sprel (offset
)
2119 unsigned int offset
;
2121 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2122 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2126 static unw_rec_list
*
2129 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2133 static unw_rec_list
*
2137 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2138 ptr
->r
.record
.p
.gr
= gr
;
2142 static unw_rec_list
*
2143 output_rnat_psprel (offset
)
2144 unsigned int offset
;
2146 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2147 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2151 static unw_rec_list
*
2152 output_rnat_sprel (offset
)
2153 unsigned int offset
;
2155 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2156 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2160 static unw_rec_list
*
2161 output_unwabi (abi
, context
)
2163 unsigned long context
;
2165 unw_rec_list
*ptr
= alloc_record (unwabi
);
2166 ptr
->r
.record
.p
.abi
= abi
;
2167 ptr
->r
.record
.p
.context
= context
;
2171 static unw_rec_list
*
2172 output_epilogue (unsigned long ecount
)
2174 unw_rec_list
*ptr
= alloc_record (epilogue
);
2175 ptr
->r
.record
.b
.ecount
= ecount
;
2179 static unw_rec_list
*
2180 output_label_state (unsigned long label
)
2182 unw_rec_list
*ptr
= alloc_record (label_state
);
2183 ptr
->r
.record
.b
.label
= label
;
2187 static unw_rec_list
*
2188 output_copy_state (unsigned long label
)
2190 unw_rec_list
*ptr
= alloc_record (copy_state
);
2191 ptr
->r
.record
.b
.label
= label
;
2195 static unw_rec_list
*
2196 output_spill_psprel (ab
, reg
, offset
)
2199 unsigned int offset
;
2201 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2202 ptr
->r
.record
.x
.ab
= ab
;
2203 ptr
->r
.record
.x
.reg
= reg
;
2204 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2208 static unw_rec_list
*
2209 output_spill_sprel (ab
, reg
, offset
)
2212 unsigned int offset
;
2214 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2215 ptr
->r
.record
.x
.ab
= ab
;
2216 ptr
->r
.record
.x
.reg
= reg
;
2217 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2221 static unw_rec_list
*
2222 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2225 unsigned int offset
;
2226 unsigned int predicate
;
2228 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2229 ptr
->r
.record
.x
.ab
= ab
;
2230 ptr
->r
.record
.x
.reg
= reg
;
2231 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2232 ptr
->r
.record
.x
.qp
= predicate
;
2236 static unw_rec_list
*
2237 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2240 unsigned int offset
;
2241 unsigned int predicate
;
2243 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2244 ptr
->r
.record
.x
.ab
= ab
;
2245 ptr
->r
.record
.x
.reg
= reg
;
2246 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2247 ptr
->r
.record
.x
.qp
= predicate
;
2251 static unw_rec_list
*
2252 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2255 unsigned int targ_reg
;
2258 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2259 ptr
->r
.record
.x
.ab
= ab
;
2260 ptr
->r
.record
.x
.reg
= reg
;
2261 ptr
->r
.record
.x
.treg
= targ_reg
;
2262 ptr
->r
.record
.x
.xy
= xy
;
2266 static unw_rec_list
*
2267 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2270 unsigned int targ_reg
;
2272 unsigned int predicate
;
2274 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2275 ptr
->r
.record
.x
.ab
= ab
;
2276 ptr
->r
.record
.x
.reg
= reg
;
2277 ptr
->r
.record
.x
.treg
= targ_reg
;
2278 ptr
->r
.record
.x
.xy
= xy
;
2279 ptr
->r
.record
.x
.qp
= predicate
;
2283 /* Given a unw_rec_list process the correct format with the
2284 specified function. */
2287 process_one_record (ptr
, f
)
2291 unsigned long fr_mask
, gr_mask
;
2293 switch (ptr
->r
.type
)
2299 /* These are taken care of by prologue/prologue_gr. */
2304 if (ptr
->r
.type
== prologue_gr
)
2305 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2306 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2308 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2310 /* Output descriptor(s) for union of register spills (if any). */
2311 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2312 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2315 if ((fr_mask
& ~0xfUL
) == 0)
2316 output_P6_format (f
, fr_mem
, fr_mask
);
2319 output_P5_format (f
, gr_mask
, fr_mask
);
2324 output_P6_format (f
, gr_mem
, gr_mask
);
2325 if (ptr
->r
.record
.r
.mask
.br_mem
)
2326 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2328 /* output imask descriptor if necessary: */
2329 if (ptr
->r
.record
.r
.mask
.i
)
2330 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2331 ptr
->r
.record
.r
.imask_size
);
2335 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2339 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2340 ptr
->r
.record
.p
.size
);
2353 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2356 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2359 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2367 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2376 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2386 case bspstore_sprel
:
2388 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2391 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2394 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2397 as_bad ("spill_mask record unimplemented.");
2399 case priunat_when_gr
:
2400 case priunat_when_mem
:
2404 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2406 case priunat_psprel
:
2408 case bspstore_psprel
:
2410 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2413 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2416 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2420 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2423 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2424 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2425 ptr
->r
.record
.x
.pspoff
);
2428 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2429 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2430 ptr
->r
.record
.x
.spoff
);
2433 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2434 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2435 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2437 case spill_psprel_p
:
2438 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2439 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2440 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2443 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2444 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2445 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2448 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2449 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2450 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2454 as_bad ("record_type_not_valid");
2459 /* Given a unw_rec_list list, process all the records with
2460 the specified function. */
2462 process_unw_records (list
, f
)
2467 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2468 process_one_record (ptr
, f
);
2471 /* Determine the size of a record list in bytes. */
2473 calc_record_size (list
)
2477 process_unw_records (list
, count_output
);
2481 /* Update IMASK bitmask to reflect the fact that one or more registers
2482 of type TYPE are saved starting at instruction with index T. If N
2483 bits are set in REGMASK, it is assumed that instructions T through
2484 T+N-1 save these registers.
2488 1: instruction saves next fp reg
2489 2: instruction saves next general reg
2490 3: instruction saves next branch reg */
2492 set_imask (region
, regmask
, t
, type
)
2493 unw_rec_list
*region
;
2494 unsigned long regmask
;
2498 unsigned char *imask
;
2499 unsigned long imask_size
;
2503 imask
= region
->r
.record
.r
.mask
.i
;
2504 imask_size
= region
->r
.record
.r
.imask_size
;
2507 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2508 imask
= xmalloc (imask_size
);
2509 memset (imask
, 0, imask_size
);
2511 region
->r
.record
.r
.imask_size
= imask_size
;
2512 region
->r
.record
.r
.mask
.i
= imask
;
2516 pos
= 2 * (3 - t
% 4);
2519 if (i
>= imask_size
)
2521 as_bad ("Ignoring attempt to spill beyond end of region");
2525 imask
[i
] |= (type
& 0x3) << pos
;
2527 regmask
&= (regmask
- 1);
2538 count_bits (unsigned long mask
)
2550 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2551 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2552 containing FIRST_ADDR. */
2555 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2556 unsigned long slot_addr
;
2558 unsigned long first_addr
;
2561 unsigned long index
= 0;
2563 /* First time we are called, the initial address and frag are invalid. */
2564 if (first_addr
== 0)
2567 /* If the two addresses are in different frags, then we need to add in
2568 the remaining size of this frag, and then the entire size of intermediate
2570 while (slot_frag
!= first_frag
)
2572 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2574 /* Add in the full size of the frag converted to instruction slots. */
2575 index
+= 3 * (first_frag
->fr_fix
>> 4);
2576 /* Subtract away the initial part before first_addr. */
2577 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2578 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2580 /* Move to the beginning of the next frag. */
2581 first_frag
= first_frag
->fr_next
;
2582 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2585 /* Add in the used part of the last frag. */
2586 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2587 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2591 /* Optimize unwind record directives. */
2593 static unw_rec_list
*
2594 optimize_unw_records (list
)
2600 /* If the only unwind record is ".prologue" or ".prologue" followed
2601 by ".body", then we can optimize the unwind directives away. */
2602 if (list
->r
.type
== prologue
2603 && (list
->next
== NULL
2604 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2610 /* Given a complete record list, process any records which have
2611 unresolved fields, (ie length counts for a prologue). After
2612 this has been run, all neccessary information should be available
2613 within each record to generate an image. */
2616 fixup_unw_records (list
)
2619 unw_rec_list
*ptr
, *region
= 0;
2620 unsigned long first_addr
= 0, rlen
= 0, t
;
2621 fragS
*first_frag
= 0;
2623 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2625 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2626 as_bad (" Insn slot not set in unwind record.");
2627 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2628 first_addr
, first_frag
);
2629 switch (ptr
->r
.type
)
2636 int size
, dir_len
= 0;
2637 unsigned long last_addr
;
2640 first_addr
= ptr
->slot_number
;
2641 first_frag
= ptr
->slot_frag
;
2642 ptr
->slot_number
= 0;
2643 /* Find either the next body/prologue start, or the end of
2644 the list, and determine the size of the region. */
2645 last_addr
= unwind
.next_slot_number
;
2646 last_frag
= unwind
.next_slot_frag
;
2647 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2648 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2649 || last
->r
.type
== body
)
2651 last_addr
= last
->slot_number
;
2652 last_frag
= last
->slot_frag
;
2655 else if (!last
->next
)
2657 /* In the absence of an explicit .body directive,
2658 the prologue ends after the last instruction
2659 covered by an unwind directive. */
2660 if (ptr
->r
.type
!= body
)
2662 last_addr
= last
->slot_number
;
2663 last_frag
= last
->slot_frag
;
2664 switch (last
->r
.type
)
2667 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2668 + count_bits (last
->r
.record
.p
.grmask
));
2672 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2676 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2679 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2688 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2690 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2695 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2706 case priunat_when_gr
:
2707 case priunat_when_mem
:
2711 ptr
->r
.record
.p
.t
= t
;
2719 case spill_psprel_p
:
2720 ptr
->r
.record
.x
.t
= t
;
2726 as_bad ("frgr_mem record before region record!\n");
2729 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2730 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2731 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2732 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2737 as_bad ("fr_mem record before region record!\n");
2740 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2741 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2746 as_bad ("gr_mem record before region record!\n");
2749 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2750 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2755 as_bad ("br_mem record before region record!\n");
2758 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2759 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2765 as_bad ("gr_gr record before region record!\n");
2768 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2773 as_bad ("br_gr record before region record!\n");
2776 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2785 /* Helper routine for output_unw_records. Emits the header for the unwind
2789 setup_unwind_header (int size
, unsigned char **mem
)
2793 /* pad to pointer-size boundry. */
2794 x
= size
% md
.pointer_size
;
2796 extra
= md
.pointer_size
- x
;
2798 /* Add 8 for the header + a pointer for the
2799 personality offset. */
2800 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2802 /* Clear the padding area and personality. */
2803 memset (*mem
+ 8 + size
, 0 , extra
+ md
.pointer_size
);
2804 /* Initialize the header area. */
2806 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* version */
2807 | (unwind
.personality_routine
2808 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2810 | ((size
+ extra
) / md
.pointer_size
)), /* length */
2816 /* Generate an unwind image from a record list. Returns the number of
2817 bytes in the resulting image. The memory image itselof is returned
2818 in the 'ptr' parameter. */
2820 output_unw_records (list
, ptr
)
2829 list
= optimize_unw_records (list
);
2830 fixup_unw_records (list
);
2831 size
= calc_record_size (list
);
2833 if (size
> 0 || unwind
.force_unwind_entry
)
2835 unwind
.force_unwind_entry
= 0;
2836 extra
= setup_unwind_header (size
, &mem
);
2838 vbyte_mem_ptr
= mem
+ 8;
2839 process_unw_records (list
, output_vbyte_mem
);
2843 size
+= extra
+ 8 + md
.pointer_size
;
2849 convert_expr_to_ab_reg (e
, ab
, regp
)
2856 if (e
->X_op
!= O_register
)
2859 reg
= e
->X_add_number
;
2860 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2863 *regp
= reg
- REG_GR
;
2865 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2866 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2869 *regp
= reg
- REG_FR
;
2871 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2874 *regp
= reg
- REG_BR
;
2881 case REG_PR
: *regp
= 0; break;
2882 case REG_PSP
: *regp
= 1; break;
2883 case REG_PRIUNAT
: *regp
= 2; break;
2884 case REG_BR
+ 0: *regp
= 3; break;
2885 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2886 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2887 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2888 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2889 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2890 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2891 case REG_AR
+ AR_LC
: *regp
= 10; break;
2901 convert_expr_to_xy_reg (e
, xy
, regp
)
2908 if (e
->X_op
!= O_register
)
2911 reg
= e
->X_add_number
;
2913 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2916 *regp
= reg
- REG_GR
;
2918 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2921 *regp
= reg
- REG_FR
;
2923 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2926 *regp
= reg
- REG_BR
;
2935 int dummy ATTRIBUTE_UNUSED
;
2940 radix
= *input_line_pointer
++;
2942 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2944 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2945 ignore_rest_of_line ();
2950 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2952 dot_special_section (which
)
2955 set_section ((char *) special_section_name
[which
]);
2959 add_unwind_entry (ptr
)
2963 unwind
.tail
->next
= ptr
;
2968 /* The current entry can in fact be a chain of unwind entries. */
2969 if (unwind
.current_entry
== NULL
)
2970 unwind
.current_entry
= ptr
;
2975 int dummy ATTRIBUTE_UNUSED
;
2981 if (e
.X_op
!= O_constant
)
2982 as_bad ("Operand to .fframe must be a constant");
2984 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2989 int dummy ATTRIBUTE_UNUSED
;
2995 reg
= e
.X_add_number
- REG_GR
;
2996 if (e
.X_op
== O_register
&& reg
< 128)
2998 add_unwind_entry (output_mem_stack_v ());
2999 if (! (unwind
.prologue_mask
& 2))
3000 add_unwind_entry (output_psp_gr (reg
));
3003 as_bad ("First operand to .vframe must be a general register");
3007 dot_vframesp (dummy
)
3008 int dummy ATTRIBUTE_UNUSED
;
3013 if (e
.X_op
== O_constant
)
3015 add_unwind_entry (output_mem_stack_v ());
3016 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3019 as_bad ("First operand to .vframesp must be a general register");
3023 dot_vframepsp (dummy
)
3024 int dummy ATTRIBUTE_UNUSED
;
3029 if (e
.X_op
== O_constant
)
3031 add_unwind_entry (output_mem_stack_v ());
3032 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3035 as_bad ("First operand to .vframepsp must be a general register");
3040 int dummy ATTRIBUTE_UNUSED
;
3046 sep
= parse_operand (&e1
);
3048 as_bad ("No second operand to .save");
3049 sep
= parse_operand (&e2
);
3051 reg1
= e1
.X_add_number
;
3052 reg2
= e2
.X_add_number
- REG_GR
;
3054 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3055 if (e1
.X_op
== O_register
)
3057 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3061 case REG_AR
+ AR_BSP
:
3062 add_unwind_entry (output_bsp_when ());
3063 add_unwind_entry (output_bsp_gr (reg2
));
3065 case REG_AR
+ AR_BSPSTORE
:
3066 add_unwind_entry (output_bspstore_when ());
3067 add_unwind_entry (output_bspstore_gr (reg2
));
3069 case REG_AR
+ AR_RNAT
:
3070 add_unwind_entry (output_rnat_when ());
3071 add_unwind_entry (output_rnat_gr (reg2
));
3073 case REG_AR
+ AR_UNAT
:
3074 add_unwind_entry (output_unat_when ());
3075 add_unwind_entry (output_unat_gr (reg2
));
3077 case REG_AR
+ AR_FPSR
:
3078 add_unwind_entry (output_fpsr_when ());
3079 add_unwind_entry (output_fpsr_gr (reg2
));
3081 case REG_AR
+ AR_PFS
:
3082 add_unwind_entry (output_pfs_when ());
3083 if (! (unwind
.prologue_mask
& 4))
3084 add_unwind_entry (output_pfs_gr (reg2
));
3086 case REG_AR
+ AR_LC
:
3087 add_unwind_entry (output_lc_when ());
3088 add_unwind_entry (output_lc_gr (reg2
));
3091 add_unwind_entry (output_rp_when ());
3092 if (! (unwind
.prologue_mask
& 8))
3093 add_unwind_entry (output_rp_gr (reg2
));
3096 add_unwind_entry (output_preds_when ());
3097 if (! (unwind
.prologue_mask
& 1))
3098 add_unwind_entry (output_preds_gr (reg2
));
3101 add_unwind_entry (output_priunat_when_gr ());
3102 add_unwind_entry (output_priunat_gr (reg2
));
3105 as_bad ("First operand not a valid register");
3109 as_bad (" Second operand not a valid register");
3112 as_bad ("First operand not a register");
3117 int dummy ATTRIBUTE_UNUSED
;
3120 unsigned long ecount
; /* # of _additional_ regions to pop */
3123 sep
= parse_operand (&e1
);
3124 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3126 as_bad ("First operand to .restore must be stack pointer (sp)");
3132 parse_operand (&e2
);
3133 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3135 as_bad ("Second operand to .restore must be a constant >= 0");
3138 ecount
= e2
.X_add_number
;
3141 ecount
= unwind
.prologue_count
- 1;
3142 add_unwind_entry (output_epilogue (ecount
));
3144 if (ecount
< unwind
.prologue_count
)
3145 unwind
.prologue_count
-= ecount
+ 1;
3147 unwind
.prologue_count
= 0;
3151 dot_restorereg (dummy
)
3152 int dummy ATTRIBUTE_UNUSED
;
3154 unsigned int ab
, reg
;
3159 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3161 as_bad ("First operand to .restorereg must be a preserved register");
3164 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3168 dot_restorereg_p (dummy
)
3169 int dummy ATTRIBUTE_UNUSED
;
3171 unsigned int qp
, ab
, reg
;
3175 sep
= parse_operand (&e1
);
3178 as_bad ("No second operand to .restorereg.p");
3182 parse_operand (&e2
);
3184 qp
= e1
.X_add_number
- REG_P
;
3185 if (e1
.X_op
!= O_register
|| qp
> 63)
3187 as_bad ("First operand to .restorereg.p must be a predicate");
3191 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3193 as_bad ("Second operand to .restorereg.p must be a preserved register");
3196 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3200 generate_unwind_image (text_name
)
3201 const char *text_name
;
3204 unsigned char *unw_rec
;
3206 /* Force out pending instructions, to make sure all unwind records have
3207 a valid slot_number field. */
3208 ia64_flush_insns ();
3210 /* Generate the unwind record. */
3211 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3212 if (size
% md
.pointer_size
!= 0)
3213 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3215 /* If there are unwind records, switch sections, and output the info. */
3218 unsigned char *where
;
3222 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3223 set_section (sec_name
);
3224 bfd_set_section_flags (stdoutput
, now_seg
,
3225 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3227 /* Make sure the section has 4 byte alignment for ILP32 and
3228 8 byte alignment for LP64. */
3229 frag_align (md
.pointer_size_shift
, 0, 0);
3230 record_alignment (now_seg
, md
.pointer_size_shift
);
3232 /* Set expression which points to start of unwind descriptor area. */
3233 unwind
.info
= expr_build_dot ();
3235 where
= (unsigned char *) frag_more (size
);
3237 /* Issue a label for this address, and keep track of it to put it
3238 in the unwind section. */
3240 /* Copy the information from the unwind record into this section. The
3241 data is already in the correct byte order. */
3242 memcpy (where
, unw_rec
, size
);
3244 /* Add the personality address to the image. */
3245 if (unwind
.personality_routine
!= 0)
3247 exp
.X_op
= O_symbol
;
3248 exp
.X_add_symbol
= unwind
.personality_routine
;
3249 exp
.X_add_number
= 0;
3250 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3251 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3252 unwind
.personality_routine
= 0;
3256 free_list_records (unwind
.list
);
3257 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3263 dot_handlerdata (dummy
)
3264 int dummy ATTRIBUTE_UNUSED
;
3266 const char *text_name
= segment_name (now_seg
);
3268 /* If text section name starts with ".text" (which it should),
3269 strip this prefix off. */
3270 if (strcmp (text_name
, ".text") == 0)
3273 unwind
.force_unwind_entry
= 1;
3275 /* Remember which segment we're in so we can switch back after .endp */
3276 unwind
.saved_text_seg
= now_seg
;
3277 unwind
.saved_text_subseg
= now_subseg
;
3279 /* Generate unwind info into unwind-info section and then leave that
3280 section as the currently active one so dataXX directives go into
3281 the language specific data area of the unwind info block. */
3282 generate_unwind_image (text_name
);
3283 demand_empty_rest_of_line ();
3287 dot_unwentry (dummy
)
3288 int dummy ATTRIBUTE_UNUSED
;
3290 unwind
.force_unwind_entry
= 1;
3291 demand_empty_rest_of_line ();
3296 int dummy ATTRIBUTE_UNUSED
;
3302 reg
= e
.X_add_number
- REG_BR
;
3303 if (e
.X_op
== O_register
&& reg
< 8)
3304 add_unwind_entry (output_rp_br (reg
));
3306 as_bad ("First operand not a valid branch register");
3310 dot_savemem (psprel
)
3317 sep
= parse_operand (&e1
);
3319 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3320 sep
= parse_operand (&e2
);
3322 reg1
= e1
.X_add_number
;
3323 val
= e2
.X_add_number
;
3325 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3326 if (e1
.X_op
== O_register
)
3328 if (e2
.X_op
== O_constant
)
3332 case REG_AR
+ AR_BSP
:
3333 add_unwind_entry (output_bsp_when ());
3334 add_unwind_entry ((psprel
3336 : output_bsp_sprel
) (val
));
3338 case REG_AR
+ AR_BSPSTORE
:
3339 add_unwind_entry (output_bspstore_when ());
3340 add_unwind_entry ((psprel
3341 ? output_bspstore_psprel
3342 : output_bspstore_sprel
) (val
));
3344 case REG_AR
+ AR_RNAT
:
3345 add_unwind_entry (output_rnat_when ());
3346 add_unwind_entry ((psprel
3347 ? output_rnat_psprel
3348 : output_rnat_sprel
) (val
));
3350 case REG_AR
+ AR_UNAT
:
3351 add_unwind_entry (output_unat_when ());
3352 add_unwind_entry ((psprel
3353 ? output_unat_psprel
3354 : output_unat_sprel
) (val
));
3356 case REG_AR
+ AR_FPSR
:
3357 add_unwind_entry (output_fpsr_when ());
3358 add_unwind_entry ((psprel
3359 ? output_fpsr_psprel
3360 : output_fpsr_sprel
) (val
));
3362 case REG_AR
+ AR_PFS
:
3363 add_unwind_entry (output_pfs_when ());
3364 add_unwind_entry ((psprel
3366 : output_pfs_sprel
) (val
));
3368 case REG_AR
+ AR_LC
:
3369 add_unwind_entry (output_lc_when ());
3370 add_unwind_entry ((psprel
3372 : output_lc_sprel
) (val
));
3375 add_unwind_entry (output_rp_when ());
3376 add_unwind_entry ((psprel
3378 : output_rp_sprel
) (val
));
3381 add_unwind_entry (output_preds_when ());
3382 add_unwind_entry ((psprel
3383 ? output_preds_psprel
3384 : output_preds_sprel
) (val
));
3387 add_unwind_entry (output_priunat_when_mem ());
3388 add_unwind_entry ((psprel
3389 ? output_priunat_psprel
3390 : output_priunat_sprel
) (val
));
3393 as_bad ("First operand not a valid register");
3397 as_bad (" Second operand not a valid constant");
3400 as_bad ("First operand not a register");
3405 int dummy ATTRIBUTE_UNUSED
;
3409 sep
= parse_operand (&e1
);
3411 parse_operand (&e2
);
3413 if (e1
.X_op
!= O_constant
)
3414 as_bad ("First operand to .save.g must be a constant.");
3417 int grmask
= e1
.X_add_number
;
3419 add_unwind_entry (output_gr_mem (grmask
));
3422 int reg
= e2
.X_add_number
- REG_GR
;
3423 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3424 add_unwind_entry (output_gr_gr (grmask
, reg
));
3426 as_bad ("Second operand is an invalid register.");
3433 int dummy ATTRIBUTE_UNUSED
;
3437 sep
= parse_operand (&e1
);
3439 if (e1
.X_op
!= O_constant
)
3440 as_bad ("Operand to .save.f must be a constant.");
3442 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3447 int dummy ATTRIBUTE_UNUSED
;
3454 sep
= parse_operand (&e1
);
3455 if (e1
.X_op
!= O_constant
)
3457 as_bad ("First operand to .save.b must be a constant.");
3460 brmask
= e1
.X_add_number
;
3464 sep
= parse_operand (&e2
);
3465 reg
= e2
.X_add_number
- REG_GR
;
3466 if (e2
.X_op
!= O_register
|| reg
> 127)
3468 as_bad ("Second operand to .save.b must be a general register.");
3471 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3474 add_unwind_entry (output_br_mem (brmask
));
3476 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3477 ignore_rest_of_line ();
3482 int dummy ATTRIBUTE_UNUSED
;
3486 sep
= parse_operand (&e1
);
3488 parse_operand (&e2
);
3490 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3491 as_bad ("Both operands of .save.gf must be constants.");
3494 int grmask
= e1
.X_add_number
;
3495 int frmask
= e2
.X_add_number
;
3496 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3502 int dummy ATTRIBUTE_UNUSED
;
3507 sep
= parse_operand (&e
);
3508 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3509 ignore_rest_of_line ();
3511 if (e
.X_op
!= O_constant
)
3512 as_bad ("Operand to .spill must be a constant");
3514 add_unwind_entry (output_spill_base (e
.X_add_number
));
3518 dot_spillreg (dummy
)
3519 int dummy ATTRIBUTE_UNUSED
;
3521 int sep
, ab
, xy
, reg
, treg
;
3524 sep
= parse_operand (&e1
);
3527 as_bad ("No second operand to .spillreg");
3531 parse_operand (&e2
);
3533 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3535 as_bad ("First operand to .spillreg must be a preserved register");
3539 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3541 as_bad ("Second operand to .spillreg must be a register");
3545 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3549 dot_spillmem (psprel
)
3555 sep
= parse_operand (&e1
);
3558 as_bad ("Second operand missing");
3562 parse_operand (&e2
);
3564 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3566 as_bad ("First operand to .spill%s must be a preserved register",
3567 psprel
? "psp" : "sp");
3571 if (e2
.X_op
!= O_constant
)
3573 as_bad ("Second operand to .spill%s must be a constant",
3574 psprel
? "psp" : "sp");
3579 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3581 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3585 dot_spillreg_p (dummy
)
3586 int dummy ATTRIBUTE_UNUSED
;
3588 int sep
, ab
, xy
, reg
, treg
;
3589 expressionS e1
, e2
, e3
;
3592 sep
= parse_operand (&e1
);
3595 as_bad ("No second and third operand to .spillreg.p");
3599 sep
= parse_operand (&e2
);
3602 as_bad ("No third operand to .spillreg.p");
3606 parse_operand (&e3
);
3608 qp
= e1
.X_add_number
- REG_P
;
3610 if (e1
.X_op
!= O_register
|| qp
> 63)
3612 as_bad ("First operand to .spillreg.p must be a predicate");
3616 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3618 as_bad ("Second operand to .spillreg.p must be a preserved register");
3622 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3624 as_bad ("Third operand to .spillreg.p must be a register");
3628 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3632 dot_spillmem_p (psprel
)
3635 expressionS e1
, e2
, e3
;
3639 sep
= parse_operand (&e1
);
3642 as_bad ("Second operand missing");
3646 parse_operand (&e2
);
3649 as_bad ("Second operand missing");
3653 parse_operand (&e3
);
3655 qp
= e1
.X_add_number
- REG_P
;
3656 if (e1
.X_op
!= O_register
|| qp
> 63)
3658 as_bad ("First operand to .spill%s_p must be a predicate",
3659 psprel
? "psp" : "sp");
3663 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3665 as_bad ("Second operand to .spill%s_p must be a preserved register",
3666 psprel
? "psp" : "sp");
3670 if (e3
.X_op
!= O_constant
)
3672 as_bad ("Third operand to .spill%s_p must be a constant",
3673 psprel
? "psp" : "sp");
3678 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3680 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3684 dot_label_state (dummy
)
3685 int dummy ATTRIBUTE_UNUSED
;
3690 if (e
.X_op
!= O_constant
)
3692 as_bad ("Operand to .label_state must be a constant");
3695 add_unwind_entry (output_label_state (e
.X_add_number
));
3699 dot_copy_state (dummy
)
3700 int dummy ATTRIBUTE_UNUSED
;
3705 if (e
.X_op
!= O_constant
)
3707 as_bad ("Operand to .copy_state must be a constant");
3710 add_unwind_entry (output_copy_state (e
.X_add_number
));
3715 int dummy ATTRIBUTE_UNUSED
;
3720 sep
= parse_operand (&e1
);
3723 as_bad ("Second operand to .unwabi missing");
3726 sep
= parse_operand (&e2
);
3727 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3728 ignore_rest_of_line ();
3730 if (e1
.X_op
!= O_constant
)
3732 as_bad ("First operand to .unwabi must be a constant");
3736 if (e2
.X_op
!= O_constant
)
3738 as_bad ("Second operand to .unwabi must be a constant");
3742 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3746 dot_personality (dummy
)
3747 int dummy ATTRIBUTE_UNUSED
;
3751 name
= input_line_pointer
;
3752 c
= get_symbol_end ();
3753 p
= input_line_pointer
;
3754 unwind
.personality_routine
= symbol_find_or_make (name
);
3755 unwind
.force_unwind_entry
= 1;
3758 demand_empty_rest_of_line ();
3763 int dummy ATTRIBUTE_UNUSED
;
3768 unwind
.proc_start
= expr_build_dot ();
3769 /* Parse names of main and alternate entry points and mark them as
3770 function symbols: */
3774 name
= input_line_pointer
;
3775 c
= get_symbol_end ();
3776 p
= input_line_pointer
;
3777 sym
= symbol_find_or_make (name
);
3778 if (unwind
.proc_start
== 0)
3780 unwind
.proc_start
= sym
;
3782 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3785 if (*input_line_pointer
!= ',')
3787 ++input_line_pointer
;
3789 demand_empty_rest_of_line ();
3792 unwind
.prologue_count
= 0;
3793 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3794 unwind
.personality_routine
= 0;
3799 int dummy ATTRIBUTE_UNUSED
;
3801 unwind
.prologue
= 0;
3802 unwind
.prologue_mask
= 0;
3804 add_unwind_entry (output_body ());
3805 demand_empty_rest_of_line ();
3809 dot_prologue (dummy
)
3810 int dummy ATTRIBUTE_UNUSED
;
3813 int mask
= 0, grsave
= 0;
3815 if (!is_it_end_of_statement ())
3818 sep
= parse_operand (&e1
);
3820 as_bad ("No second operand to .prologue");
3821 sep
= parse_operand (&e2
);
3822 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3823 ignore_rest_of_line ();
3825 if (e1
.X_op
== O_constant
)
3827 mask
= e1
.X_add_number
;
3829 if (e2
.X_op
== O_constant
)
3830 grsave
= e2
.X_add_number
;
3831 else if (e2
.X_op
== O_register
3832 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3835 as_bad ("Second operand not a constant or general register");
3837 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3840 as_bad ("First operand not a constant");
3843 add_unwind_entry (output_prologue ());
3845 unwind
.prologue
= 1;
3846 unwind
.prologue_mask
= mask
;
3847 ++unwind
.prologue_count
;
3852 int dummy ATTRIBUTE_UNUSED
;
3856 int bytes_per_address
;
3859 subsegT saved_subseg
;
3860 const char *sec_name
, *text_name
;
3864 if (unwind
.saved_text_seg
)
3866 saved_seg
= unwind
.saved_text_seg
;
3867 saved_subseg
= unwind
.saved_text_subseg
;
3868 unwind
.saved_text_seg
= NULL
;
3872 saved_seg
= now_seg
;
3873 saved_subseg
= now_subseg
;
3877 Use a slightly ugly scheme to derive the unwind section names from
3878 the text section name:
3880 text sect. unwind table sect.
3881 name: name: comments:
3882 ---------- ----------------- --------------------------------
3884 .text.foo .IA_64.unwind.text.foo
3885 .foo .IA_64.unwind.foo
3887 .gnu.linkonce.ia64unw.foo
3888 _info .IA_64.unwind_info gas issues error message (ditto)
3889 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3891 This mapping is done so that:
3893 (a) An object file with unwind info only in .text will use
3894 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3895 This follows the letter of the ABI and also ensures backwards
3896 compatibility with older toolchains.
3898 (b) An object file with unwind info in multiple text sections
3899 will use separate unwind sections for each text section.
3900 This allows us to properly set the "sh_info" and "sh_link"
3901 fields in SHT_IA_64_UNWIND as required by the ABI and also
3902 lets GNU ld support programs with multiple segments
3903 containing unwind info (as might be the case for certain
3904 embedded applications).
3906 (c) An error is issued if there would be a name clash.
3908 text_name
= segment_name (saved_seg
);
3909 if (strncmp (text_name
, "_info", 5) == 0)
3911 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3913 ignore_rest_of_line ();
3916 if (strcmp (text_name
, ".text") == 0)
3919 insn_group_break (1, 0, 0);
3921 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3923 generate_unwind_image (text_name
);
3925 if (unwind
.info
|| unwind
.force_unwind_entry
)
3927 subseg_set (md
.last_text_seg
, 0);
3928 unwind
.proc_end
= expr_build_dot ();
3930 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3931 set_section ((char *) sec_name
);
3932 bfd_set_section_flags (stdoutput
, now_seg
,
3933 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3935 /* Make sure that section has 4 byte alignment for ILP32 and
3936 8 byte alignment for LP64. */
3937 record_alignment (now_seg
, md
.pointer_size_shift
);
3939 /* Need space for 3 pointers for procedure start, procedure end,
3941 ptr
= frag_more (3 * md
.pointer_size
);
3942 where
= frag_now_fix () - (3 * md
.pointer_size
);
3943 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3945 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3946 e
.X_op
= O_pseudo_fixup
;
3947 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3949 e
.X_add_symbol
= unwind
.proc_start
;
3950 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3952 e
.X_op
= O_pseudo_fixup
;
3953 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3955 e
.X_add_symbol
= unwind
.proc_end
;
3956 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3957 bytes_per_address
, &e
);
3961 e
.X_op
= O_pseudo_fixup
;
3962 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3964 e
.X_add_symbol
= unwind
.info
;
3965 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3966 bytes_per_address
, &e
);
3969 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3973 subseg_set (saved_seg
, saved_subseg
);
3975 /* Parse names of main and alternate entry points and set symbol sizes. */
3979 name
= input_line_pointer
;
3980 c
= get_symbol_end ();
3981 p
= input_line_pointer
;
3982 sym
= symbol_find (name
);
3983 if (sym
&& unwind
.proc_start
3984 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
3985 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
3987 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
3988 fragS
*frag
= symbol_get_frag (sym
);
3990 /* Check whether the function label is at or beyond last
3992 while (fr
&& fr
!= frag
)
3996 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
3997 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
4000 symbol_get_obj (sym
)->size
=
4001 (expressionS
*) xmalloc (sizeof (expressionS
));
4002 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
4003 symbol_get_obj (sym
)->size
->X_add_symbol
4004 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
4005 frag_now_fix (), frag_now
);
4006 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
4007 symbol_get_obj (sym
)->size
->X_add_number
= 0;
4013 if (*input_line_pointer
!= ',')
4015 ++input_line_pointer
;
4017 demand_empty_rest_of_line ();
4018 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4022 dot_template (template)
4025 CURR_SLOT
.user_template
= template;
4030 int dummy ATTRIBUTE_UNUSED
;
4032 int ins
, locs
, outs
, rots
;
4034 if (is_it_end_of_statement ())
4035 ins
= locs
= outs
= rots
= 0;
4038 ins
= get_absolute_expression ();
4039 if (*input_line_pointer
++ != ',')
4041 locs
= get_absolute_expression ();
4042 if (*input_line_pointer
++ != ',')
4044 outs
= get_absolute_expression ();
4045 if (*input_line_pointer
++ != ',')
4047 rots
= get_absolute_expression ();
4049 set_regstack (ins
, locs
, outs
, rots
);
4053 as_bad ("Comma expected");
4054 ignore_rest_of_line ();
4061 unsigned num_regs
, num_alloced
= 0;
4062 struct dynreg
**drpp
, *dr
;
4063 int ch
, base_reg
= 0;
4069 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4070 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4071 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4075 /* First, remove existing names from hash table. */
4076 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4078 hash_delete (md
.dynreg_hash
, dr
->name
);
4082 drpp
= &md
.dynreg
[type
];
4085 start
= input_line_pointer
;
4086 ch
= get_symbol_end ();
4087 *input_line_pointer
= ch
;
4088 len
= (input_line_pointer
- start
);
4091 if (*input_line_pointer
!= '[')
4093 as_bad ("Expected '['");
4096 ++input_line_pointer
; /* skip '[' */
4098 num_regs
= get_absolute_expression ();
4100 if (*input_line_pointer
++ != ']')
4102 as_bad ("Expected ']'");
4107 num_alloced
+= num_regs
;
4111 if (num_alloced
> md
.rot
.num_regs
)
4113 as_bad ("Used more than the declared %d rotating registers",
4119 if (num_alloced
> 96)
4121 as_bad ("Used more than the available 96 rotating registers");
4126 if (num_alloced
> 48)
4128 as_bad ("Used more than the available 48 rotating registers");
4137 name
= obstack_alloc (¬es
, len
+ 1);
4138 memcpy (name
, start
, len
);
4143 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4144 memset (*drpp
, 0, sizeof (*dr
));
4149 dr
->num_regs
= num_regs
;
4150 dr
->base
= base_reg
;
4152 base_reg
+= num_regs
;
4154 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4156 as_bad ("Attempt to redefine register set `%s'", name
);
4160 if (*input_line_pointer
!= ',')
4162 ++input_line_pointer
; /* skip comma */
4165 demand_empty_rest_of_line ();
4169 ignore_rest_of_line ();
4173 dot_byteorder (byteorder
)
4176 target_big_endian
= byteorder
;
4181 int dummy ATTRIBUTE_UNUSED
;
4188 option
= input_line_pointer
;
4189 ch
= get_symbol_end ();
4190 if (strcmp (option
, "lsb") == 0)
4191 md
.flags
&= ~EF_IA_64_BE
;
4192 else if (strcmp (option
, "msb") == 0)
4193 md
.flags
|= EF_IA_64_BE
;
4194 else if (strcmp (option
, "abi32") == 0)
4195 md
.flags
&= ~EF_IA_64_ABI64
;
4196 else if (strcmp (option
, "abi64") == 0)
4197 md
.flags
|= EF_IA_64_ABI64
;
4199 as_bad ("Unknown psr option `%s'", option
);
4200 *input_line_pointer
= ch
;
4203 if (*input_line_pointer
!= ',')
4206 ++input_line_pointer
;
4209 demand_empty_rest_of_line ();
4214 int dummy ATTRIBUTE_UNUSED
;
4216 as_bad (".alias not implemented yet");
4221 int dummy ATTRIBUTE_UNUSED
;
4223 new_logical_line (0, get_absolute_expression ());
4224 demand_empty_rest_of_line ();
4228 parse_section_name ()
4234 if (*input_line_pointer
!= '"')
4236 as_bad ("Missing section name");
4237 ignore_rest_of_line ();
4240 name
= demand_copy_C_string (&len
);
4243 ignore_rest_of_line ();
4247 if (*input_line_pointer
!= ',')
4249 as_bad ("Comma expected after section name");
4250 ignore_rest_of_line ();
4253 ++input_line_pointer
; /* skip comma */
4261 char *name
= parse_section_name ();
4265 md
.keep_pending_output
= 1;
4268 obj_elf_previous (0);
4269 md
.keep_pending_output
= 0;
4272 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4275 stmt_float_cons (kind
)
4282 case 'd': size
= 8; break;
4283 case 'x': size
= 10; break;
4290 ia64_do_align (size
);
4298 int saved_auto_align
= md
.auto_align
;
4302 md
.auto_align
= saved_auto_align
;
4306 dot_xfloat_cons (kind
)
4309 char *name
= parse_section_name ();
4313 md
.keep_pending_output
= 1;
4315 stmt_float_cons (kind
);
4316 obj_elf_previous (0);
4317 md
.keep_pending_output
= 0;
4321 dot_xstringer (zero
)
4324 char *name
= parse_section_name ();
4328 md
.keep_pending_output
= 1;
4331 obj_elf_previous (0);
4332 md
.keep_pending_output
= 0;
4339 int saved_auto_align
= md
.auto_align
;
4340 char *name
= parse_section_name ();
4344 md
.keep_pending_output
= 1;
4348 md
.auto_align
= saved_auto_align
;
4349 obj_elf_previous (0);
4350 md
.keep_pending_output
= 0;
4354 dot_xfloat_cons_ua (kind
)
4357 int saved_auto_align
= md
.auto_align
;
4358 char *name
= parse_section_name ();
4362 md
.keep_pending_output
= 1;
4365 stmt_float_cons (kind
);
4366 md
.auto_align
= saved_auto_align
;
4367 obj_elf_previous (0);
4368 md
.keep_pending_output
= 0;
4371 /* .reg.val <regname>,value */
4375 int dummy ATTRIBUTE_UNUSED
;
4380 if (reg
.X_op
!= O_register
)
4382 as_bad (_("Register name expected"));
4383 ignore_rest_of_line ();
4385 else if (*input_line_pointer
++ != ',')
4387 as_bad (_("Comma expected"));
4388 ignore_rest_of_line ();
4392 valueT value
= get_absolute_expression ();
4393 int regno
= reg
.X_add_number
;
4394 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4395 as_warn (_("Register value annotation ignored"));
4398 gr_values
[regno
- REG_GR
].known
= 1;
4399 gr_values
[regno
- REG_GR
].value
= value
;
4400 gr_values
[regno
- REG_GR
].path
= md
.path
;
4403 demand_empty_rest_of_line ();
4406 /* select dv checking mode
4411 A stop is inserted when changing modes
4418 if (md
.manual_bundling
)
4419 as_warn (_("Directive invalid within a bundle"));
4421 if (type
== 'E' || type
== 'A')
4422 md
.mode_explicitly_set
= 0;
4424 md
.mode_explicitly_set
= 1;
4431 if (md
.explicit_mode
)
4432 insn_group_break (1, 0, 0);
4433 md
.explicit_mode
= 0;
4437 if (!md
.explicit_mode
)
4438 insn_group_break (1, 0, 0);
4439 md
.explicit_mode
= 1;
4443 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4444 insn_group_break (1, 0, 0);
4445 md
.explicit_mode
= md
.default_explicit_mode
;
4446 md
.mode_explicitly_set
= 0;
4457 for (regno
= 0; regno
< 64; regno
++)
4459 if (mask
& ((valueT
) 1 << regno
))
4461 fprintf (stderr
, "%s p%d", comma
, regno
);
4468 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4469 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4470 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4471 .pred.safe_across_calls p1 [, p2 [,...]]
4480 int p1
= -1, p2
= -1;
4484 if (*input_line_pointer
!= '"')
4486 as_bad (_("Missing predicate relation type"));
4487 ignore_rest_of_line ();
4493 char *form
= demand_copy_C_string (&len
);
4494 if (strcmp (form
, "mutex") == 0)
4496 else if (strcmp (form
, "clear") == 0)
4498 else if (strcmp (form
, "imply") == 0)
4502 as_bad (_("Unrecognized predicate relation type"));
4503 ignore_rest_of_line ();
4507 if (*input_line_pointer
== ',')
4508 ++input_line_pointer
;
4518 if (TOUPPER (*input_line_pointer
) != 'P'
4519 || (regno
= atoi (++input_line_pointer
)) < 0
4522 as_bad (_("Predicate register expected"));
4523 ignore_rest_of_line ();
4526 while (ISDIGIT (*input_line_pointer
))
4527 ++input_line_pointer
;
4534 as_warn (_("Duplicate predicate register ignored"));
4537 /* See if it's a range. */
4538 if (*input_line_pointer
== '-')
4541 ++input_line_pointer
;
4543 if (TOUPPER (*input_line_pointer
) != 'P'
4544 || (regno
= atoi (++input_line_pointer
)) < 0
4547 as_bad (_("Predicate register expected"));
4548 ignore_rest_of_line ();
4551 while (ISDIGIT (*input_line_pointer
))
4552 ++input_line_pointer
;
4556 as_bad (_("Bad register range"));
4557 ignore_rest_of_line ();
4568 if (*input_line_pointer
!= ',')
4570 ++input_line_pointer
;
4579 clear_qp_mutex (mask
);
4580 clear_qp_implies (mask
, (valueT
) 0);
4583 if (count
!= 2 || p1
== -1 || p2
== -1)
4584 as_bad (_("Predicate source and target required"));
4585 else if (p1
== 0 || p2
== 0)
4586 as_bad (_("Use of p0 is not valid in this context"));
4588 add_qp_imply (p1
, p2
);
4593 as_bad (_("At least two PR arguments expected"));
4598 as_bad (_("Use of p0 is not valid in this context"));
4601 add_qp_mutex (mask
);
4604 /* note that we don't override any existing relations */
4607 as_bad (_("At least one PR argument expected"));
4612 fprintf (stderr
, "Safe across calls: ");
4613 print_prmask (mask
);
4614 fprintf (stderr
, "\n");
4616 qp_safe_across_calls
= mask
;
4619 demand_empty_rest_of_line ();
4622 /* .entry label [, label [, ...]]
4623 Hint to DV code that the given labels are to be considered entry points.
4624 Otherwise, only global labels are considered entry points. */
4628 int dummy ATTRIBUTE_UNUSED
;
4637 name
= input_line_pointer
;
4638 c
= get_symbol_end ();
4639 symbolP
= symbol_find_or_make (name
);
4641 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4643 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4646 *input_line_pointer
= c
;
4648 c
= *input_line_pointer
;
4651 input_line_pointer
++;
4653 if (*input_line_pointer
== '\n')
4659 demand_empty_rest_of_line ();
4662 /* .mem.offset offset, base
4663 "base" is used to distinguish between offsets from a different base. */
4666 dot_mem_offset (dummy
)
4667 int dummy ATTRIBUTE_UNUSED
;
4669 md
.mem_offset
.hint
= 1;
4670 md
.mem_offset
.offset
= get_absolute_expression ();
4671 if (*input_line_pointer
!= ',')
4673 as_bad (_("Comma expected"));
4674 ignore_rest_of_line ();
4677 ++input_line_pointer
;
4678 md
.mem_offset
.base
= get_absolute_expression ();
4679 demand_empty_rest_of_line ();
4682 /* ia64-specific pseudo-ops: */
4683 const pseudo_typeS md_pseudo_table
[] =
4685 { "radix", dot_radix
, 0 },
4686 { "lcomm", s_lcomm_bytes
, 1 },
4687 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4688 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4689 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4690 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4691 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4692 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4693 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4694 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4695 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4696 { "proc", dot_proc
, 0 },
4697 { "body", dot_body
, 0 },
4698 { "prologue", dot_prologue
, 0 },
4699 { "endp", dot_endp
, 0 },
4700 { "file", dwarf2_directive_file
, 0 },
4701 { "loc", dwarf2_directive_loc
, 0 },
4703 { "fframe", dot_fframe
, 0 },
4704 { "vframe", dot_vframe
, 0 },
4705 { "vframesp", dot_vframesp
, 0 },
4706 { "vframepsp", dot_vframepsp
, 0 },
4707 { "save", dot_save
, 0 },
4708 { "restore", dot_restore
, 0 },
4709 { "restorereg", dot_restorereg
, 0 },
4710 { "restorereg.p", dot_restorereg_p
, 0 },
4711 { "handlerdata", dot_handlerdata
, 0 },
4712 { "unwentry", dot_unwentry
, 0 },
4713 { "altrp", dot_altrp
, 0 },
4714 { "savesp", dot_savemem
, 0 },
4715 { "savepsp", dot_savemem
, 1 },
4716 { "save.g", dot_saveg
, 0 },
4717 { "save.f", dot_savef
, 0 },
4718 { "save.b", dot_saveb
, 0 },
4719 { "save.gf", dot_savegf
, 0 },
4720 { "spill", dot_spill
, 0 },
4721 { "spillreg", dot_spillreg
, 0 },
4722 { "spillsp", dot_spillmem
, 0 },
4723 { "spillpsp", dot_spillmem
, 1 },
4724 { "spillreg.p", dot_spillreg_p
, 0 },
4725 { "spillsp.p", dot_spillmem_p
, 0 },
4726 { "spillpsp.p", dot_spillmem_p
, 1 },
4727 { "label_state", dot_label_state
, 0 },
4728 { "copy_state", dot_copy_state
, 0 },
4729 { "unwabi", dot_unwabi
, 0 },
4730 { "personality", dot_personality
, 0 },
4732 { "estate", dot_estate
, 0 },
4734 { "mii", dot_template
, 0x0 },
4735 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4736 { "mlx", dot_template
, 0x2 },
4737 { "mmi", dot_template
, 0x4 },
4738 { "mfi", dot_template
, 0x6 },
4739 { "mmf", dot_template
, 0x7 },
4740 { "mib", dot_template
, 0x8 },
4741 { "mbb", dot_template
, 0x9 },
4742 { "bbb", dot_template
, 0xb },
4743 { "mmb", dot_template
, 0xc },
4744 { "mfb", dot_template
, 0xe },
4746 { "lb", dot_scope
, 0 },
4747 { "le", dot_scope
, 1 },
4749 { "align", s_align_bytes
, 0 },
4750 { "regstk", dot_regstk
, 0 },
4751 { "rotr", dot_rot
, DYNREG_GR
},
4752 { "rotf", dot_rot
, DYNREG_FR
},
4753 { "rotp", dot_rot
, DYNREG_PR
},
4754 { "lsb", dot_byteorder
, 0 },
4755 { "msb", dot_byteorder
, 1 },
4756 { "psr", dot_psr
, 0 },
4757 { "alias", dot_alias
, 0 },
4758 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4760 { "xdata1", dot_xdata
, 1 },
4761 { "xdata2", dot_xdata
, 2 },
4762 { "xdata4", dot_xdata
, 4 },
4763 { "xdata8", dot_xdata
, 8 },
4764 { "xreal4", dot_xfloat_cons
, 'f' },
4765 { "xreal8", dot_xfloat_cons
, 'd' },
4766 { "xreal10", dot_xfloat_cons
, 'x' },
4767 { "xstring", dot_xstringer
, 0 },
4768 { "xstringz", dot_xstringer
, 1 },
4770 /* unaligned versions: */
4771 { "xdata2.ua", dot_xdata_ua
, 2 },
4772 { "xdata4.ua", dot_xdata_ua
, 4 },
4773 { "xdata8.ua", dot_xdata_ua
, 8 },
4774 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4775 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4776 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4778 /* annotations/DV checking support */
4779 { "entry", dot_entry
, 0 },
4780 { "mem.offset", dot_mem_offset
, 0 },
4781 { "pred.rel", dot_pred_rel
, 0 },
4782 { "pred.rel.clear", dot_pred_rel
, 'c' },
4783 { "pred.rel.imply", dot_pred_rel
, 'i' },
4784 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4785 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4786 { "reg.val", dot_reg_val
, 0 },
4787 { "auto", dot_dv_mode
, 'a' },
4788 { "explicit", dot_dv_mode
, 'e' },
4789 { "default", dot_dv_mode
, 'd' },
4791 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4792 IA-64 aligns data allocation pseudo-ops by default, so we have to
4793 tell it that these ones are supposed to be unaligned. Long term,
4794 should rewrite so that only IA-64 specific data allocation pseudo-ops
4795 are aligned by default. */
4796 {"2byte", stmt_cons_ua
, 2},
4797 {"4byte", stmt_cons_ua
, 4},
4798 {"8byte", stmt_cons_ua
, 8},
4803 static const struct pseudo_opcode
4806 void (*handler
) (int);
4811 /* these are more like pseudo-ops, but don't start with a dot */
4812 { "data1", cons
, 1 },
4813 { "data2", cons
, 2 },
4814 { "data4", cons
, 4 },
4815 { "data8", cons
, 8 },
4816 { "data16", cons
, 16 },
4817 { "real4", stmt_float_cons
, 'f' },
4818 { "real8", stmt_float_cons
, 'd' },
4819 { "real10", stmt_float_cons
, 'x' },
4820 { "string", stringer
, 0 },
4821 { "stringz", stringer
, 1 },
4823 /* unaligned versions: */
4824 { "data2.ua", stmt_cons_ua
, 2 },
4825 { "data4.ua", stmt_cons_ua
, 4 },
4826 { "data8.ua", stmt_cons_ua
, 8 },
4827 { "data16.ua", stmt_cons_ua
, 16 },
4828 { "real4.ua", float_cons
, 'f' },
4829 { "real8.ua", float_cons
, 'd' },
4830 { "real10.ua", float_cons
, 'x' },
4833 /* Declare a register by creating a symbol for it and entering it in
4834 the symbol table. */
4837 declare_register (name
, regnum
)
4844 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4846 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4848 as_fatal ("Inserting \"%s\" into register table failed: %s",
4855 declare_register_set (prefix
, num_regs
, base_regnum
)
4863 for (i
= 0; i
< num_regs
; ++i
)
4865 sprintf (name
, "%s%u", prefix
, i
);
4866 declare_register (name
, base_regnum
+ i
);
4871 operand_width (opnd
)
4872 enum ia64_opnd opnd
;
4874 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4875 unsigned int bits
= 0;
4879 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4880 bits
+= odesc
->field
[i
].bits
;
4885 static enum operand_match_result
4886 operand_match (idesc
, index
, e
)
4887 const struct ia64_opcode
*idesc
;
4891 enum ia64_opnd opnd
= idesc
->operands
[index
];
4892 int bits
, relocatable
= 0;
4893 struct insn_fix
*fix
;
4900 case IA64_OPND_AR_CCV
:
4901 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4902 return OPERAND_MATCH
;
4905 case IA64_OPND_AR_PFS
:
4906 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4907 return OPERAND_MATCH
;
4911 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4912 return OPERAND_MATCH
;
4916 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4917 return OPERAND_MATCH
;
4921 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4922 return OPERAND_MATCH
;
4925 case IA64_OPND_PR_ROT
:
4926 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4927 return OPERAND_MATCH
;
4931 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4932 return OPERAND_MATCH
;
4935 case IA64_OPND_PSR_L
:
4936 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4937 return OPERAND_MATCH
;
4940 case IA64_OPND_PSR_UM
:
4941 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4942 return OPERAND_MATCH
;
4946 if (e
->X_op
== O_constant
)
4948 if (e
->X_add_number
== 1)
4949 return OPERAND_MATCH
;
4951 return OPERAND_OUT_OF_RANGE
;
4956 if (e
->X_op
== O_constant
)
4958 if (e
->X_add_number
== 8)
4959 return OPERAND_MATCH
;
4961 return OPERAND_OUT_OF_RANGE
;
4966 if (e
->X_op
== O_constant
)
4968 if (e
->X_add_number
== 16)
4969 return OPERAND_MATCH
;
4971 return OPERAND_OUT_OF_RANGE
;
4975 /* register operands: */
4978 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4979 && e
->X_add_number
< REG_AR
+ 128)
4980 return OPERAND_MATCH
;
4985 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4986 && e
->X_add_number
< REG_BR
+ 8)
4987 return OPERAND_MATCH
;
4991 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4992 && e
->X_add_number
< REG_CR
+ 128)
4993 return OPERAND_MATCH
;
5000 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
5001 && e
->X_add_number
< REG_FR
+ 128)
5002 return OPERAND_MATCH
;
5007 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
5008 && e
->X_add_number
< REG_P
+ 64)
5009 return OPERAND_MATCH
;
5015 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
5016 && e
->X_add_number
< REG_GR
+ 128)
5017 return OPERAND_MATCH
;
5020 case IA64_OPND_R3_2
:
5021 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5023 if (e
->X_add_number
< REG_GR
+ 4)
5024 return OPERAND_MATCH
;
5025 else if (e
->X_add_number
< REG_GR
+ 128)
5026 return OPERAND_OUT_OF_RANGE
;
5030 /* indirect operands: */
5031 case IA64_OPND_CPUID_R3
:
5032 case IA64_OPND_DBR_R3
:
5033 case IA64_OPND_DTR_R3
:
5034 case IA64_OPND_ITR_R3
:
5035 case IA64_OPND_IBR_R3
:
5036 case IA64_OPND_MSR_R3
:
5037 case IA64_OPND_PKR_R3
:
5038 case IA64_OPND_PMC_R3
:
5039 case IA64_OPND_PMD_R3
:
5040 case IA64_OPND_RR_R3
:
5041 if (e
->X_op
== O_index
&& e
->X_op_symbol
5042 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5043 == opnd
- IA64_OPND_CPUID_R3
))
5044 return OPERAND_MATCH
;
5048 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5049 return OPERAND_MATCH
;
5052 /* immediate operands: */
5053 case IA64_OPND_CNT2a
:
5054 case IA64_OPND_LEN4
:
5055 case IA64_OPND_LEN6
:
5056 bits
= operand_width (idesc
->operands
[index
]);
5057 if (e
->X_op
== O_constant
)
5059 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5060 return OPERAND_MATCH
;
5062 return OPERAND_OUT_OF_RANGE
;
5066 case IA64_OPND_CNT2b
:
5067 if (e
->X_op
== O_constant
)
5069 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5070 return OPERAND_MATCH
;
5072 return OPERAND_OUT_OF_RANGE
;
5076 case IA64_OPND_CNT2c
:
5077 val
= e
->X_add_number
;
5078 if (e
->X_op
== O_constant
)
5080 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5081 return OPERAND_MATCH
;
5083 return OPERAND_OUT_OF_RANGE
;
5088 /* SOR must be an integer multiple of 8 */
5089 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5090 return OPERAND_OUT_OF_RANGE
;
5093 if (e
->X_op
== O_constant
)
5095 if ((bfd_vma
) e
->X_add_number
<= 96)
5096 return OPERAND_MATCH
;
5098 return OPERAND_OUT_OF_RANGE
;
5102 case IA64_OPND_IMMU62
:
5103 if (e
->X_op
== O_constant
)
5105 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5106 return OPERAND_MATCH
;
5108 return OPERAND_OUT_OF_RANGE
;
5112 /* FIXME -- need 62-bit relocation type */
5113 as_bad (_("62-bit relocation not yet implemented"));
5117 case IA64_OPND_IMMU64
:
5118 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5119 || e
->X_op
== O_subtract
)
5121 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5122 fix
->code
= BFD_RELOC_IA64_IMM64
;
5123 if (e
->X_op
!= O_subtract
)
5125 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5126 if (e
->X_op
== O_pseudo_fixup
)
5130 fix
->opnd
= idesc
->operands
[index
];
5133 ++CURR_SLOT
.num_fixups
;
5134 return OPERAND_MATCH
;
5136 else if (e
->X_op
== O_constant
)
5137 return OPERAND_MATCH
;
5140 case IA64_OPND_CCNT5
:
5141 case IA64_OPND_CNT5
:
5142 case IA64_OPND_CNT6
:
5143 case IA64_OPND_CPOS6a
:
5144 case IA64_OPND_CPOS6b
:
5145 case IA64_OPND_CPOS6c
:
5146 case IA64_OPND_IMMU2
:
5147 case IA64_OPND_IMMU7a
:
5148 case IA64_OPND_IMMU7b
:
5149 case IA64_OPND_IMMU21
:
5150 case IA64_OPND_IMMU24
:
5151 case IA64_OPND_MBTYPE4
:
5152 case IA64_OPND_MHTYPE8
:
5153 case IA64_OPND_POS6
:
5154 bits
= operand_width (idesc
->operands
[index
]);
5155 if (e
->X_op
== O_constant
)
5157 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5158 return OPERAND_MATCH
;
5160 return OPERAND_OUT_OF_RANGE
;
5164 case IA64_OPND_IMMU9
:
5165 bits
= operand_width (idesc
->operands
[index
]);
5166 if (e
->X_op
== O_constant
)
5168 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5170 int lobits
= e
->X_add_number
& 0x3;
5171 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5172 e
->X_add_number
|= (bfd_vma
) 0x3;
5173 return OPERAND_MATCH
;
5176 return OPERAND_OUT_OF_RANGE
;
5180 case IA64_OPND_IMM44
:
5181 /* least 16 bits must be zero */
5182 if ((e
->X_add_number
& 0xffff) != 0)
5183 /* XXX technically, this is wrong: we should not be issuing warning
5184 messages until we're sure this instruction pattern is going to
5186 as_warn (_("lower 16 bits of mask ignored"));
5188 if (e
->X_op
== O_constant
)
5190 if (((e
->X_add_number
>= 0
5191 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5192 || (e
->X_add_number
< 0
5193 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5196 if (e
->X_add_number
>= 0
5197 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5199 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5201 return OPERAND_MATCH
;
5204 return OPERAND_OUT_OF_RANGE
;
5208 case IA64_OPND_IMM17
:
5209 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5210 if (e
->X_op
== O_constant
)
5212 if (((e
->X_add_number
>= 0
5213 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5214 || (e
->X_add_number
< 0
5215 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5218 if (e
->X_add_number
>= 0
5219 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5221 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5223 return OPERAND_MATCH
;
5226 return OPERAND_OUT_OF_RANGE
;
5230 case IA64_OPND_IMM14
:
5231 case IA64_OPND_IMM22
:
5233 case IA64_OPND_IMM1
:
5234 case IA64_OPND_IMM8
:
5235 case IA64_OPND_IMM8U4
:
5236 case IA64_OPND_IMM8M1
:
5237 case IA64_OPND_IMM8M1U4
:
5238 case IA64_OPND_IMM8M1U8
:
5239 case IA64_OPND_IMM9a
:
5240 case IA64_OPND_IMM9b
:
5241 bits
= operand_width (idesc
->operands
[index
]);
5242 if (relocatable
&& (e
->X_op
== O_symbol
5243 || e
->X_op
== O_subtract
5244 || e
->X_op
== O_pseudo_fixup
))
5246 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5248 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5249 fix
->code
= BFD_RELOC_IA64_IMM14
;
5251 fix
->code
= BFD_RELOC_IA64_IMM22
;
5253 if (e
->X_op
!= O_subtract
)
5255 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5256 if (e
->X_op
== O_pseudo_fixup
)
5260 fix
->opnd
= idesc
->operands
[index
];
5263 ++CURR_SLOT
.num_fixups
;
5264 return OPERAND_MATCH
;
5266 else if (e
->X_op
!= O_constant
5267 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5268 return OPERAND_MISMATCH
;
5270 if (opnd
== IA64_OPND_IMM8M1U4
)
5272 /* Zero is not valid for unsigned compares that take an adjusted
5273 constant immediate range. */
5274 if (e
->X_add_number
== 0)
5275 return OPERAND_OUT_OF_RANGE
;
5277 /* Sign-extend 32-bit unsigned numbers, so that the following range
5278 checks will work. */
5279 val
= e
->X_add_number
;
5280 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5281 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5282 val
= ((val
<< 32) >> 32);
5284 /* Check for 0x100000000. This is valid because
5285 0x100000000-1 is the same as ((uint32_t) -1). */
5286 if (val
== ((bfd_signed_vma
) 1 << 32))
5287 return OPERAND_MATCH
;
5291 else if (opnd
== IA64_OPND_IMM8M1U8
)
5293 /* Zero is not valid for unsigned compares that take an adjusted
5294 constant immediate range. */
5295 if (e
->X_add_number
== 0)
5296 return OPERAND_OUT_OF_RANGE
;
5298 /* Check for 0x10000000000000000. */
5299 if (e
->X_op
== O_big
)
5301 if (generic_bignum
[0] == 0
5302 && generic_bignum
[1] == 0
5303 && generic_bignum
[2] == 0
5304 && generic_bignum
[3] == 0
5305 && generic_bignum
[4] == 1)
5306 return OPERAND_MATCH
;
5308 return OPERAND_OUT_OF_RANGE
;
5311 val
= e
->X_add_number
- 1;
5313 else if (opnd
== IA64_OPND_IMM8M1
)
5314 val
= e
->X_add_number
- 1;
5315 else if (opnd
== IA64_OPND_IMM8U4
)
5317 /* Sign-extend 32-bit unsigned numbers, so that the following range
5318 checks will work. */
5319 val
= e
->X_add_number
;
5320 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5321 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5322 val
= ((val
<< 32) >> 32);
5325 val
= e
->X_add_number
;
5327 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5328 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5329 return OPERAND_MATCH
;
5331 return OPERAND_OUT_OF_RANGE
;
5333 case IA64_OPND_INC3
:
5334 /* +/- 1, 4, 8, 16 */
5335 val
= e
->X_add_number
;
5338 if (e
->X_op
== O_constant
)
5340 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5341 return OPERAND_MATCH
;
5343 return OPERAND_OUT_OF_RANGE
;
5347 case IA64_OPND_TGT25
:
5348 case IA64_OPND_TGT25b
:
5349 case IA64_OPND_TGT25c
:
5350 case IA64_OPND_TGT64
:
5351 if (e
->X_op
== O_symbol
)
5353 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5354 if (opnd
== IA64_OPND_TGT25
)
5355 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5356 else if (opnd
== IA64_OPND_TGT25b
)
5357 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5358 else if (opnd
== IA64_OPND_TGT25c
)
5359 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5360 else if (opnd
== IA64_OPND_TGT64
)
5361 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5365 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5366 fix
->opnd
= idesc
->operands
[index
];
5369 ++CURR_SLOT
.num_fixups
;
5370 return OPERAND_MATCH
;
5372 case IA64_OPND_TAG13
:
5373 case IA64_OPND_TAG13b
:
5377 return OPERAND_MATCH
;
5380 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5381 /* There are no external relocs for TAG13/TAG13b fields, so we
5382 create a dummy reloc. This will not live past md_apply_fix3. */
5383 fix
->code
= BFD_RELOC_UNUSED
;
5384 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5385 fix
->opnd
= idesc
->operands
[index
];
5388 ++CURR_SLOT
.num_fixups
;
5389 return OPERAND_MATCH
;
5399 return OPERAND_MISMATCH
;
5408 memset (e
, 0, sizeof (*e
));
5411 if (*input_line_pointer
!= '}')
5413 sep
= *input_line_pointer
++;
5417 if (!md
.manual_bundling
)
5418 as_warn ("Found '}' when manual bundling is off");
5420 CURR_SLOT
.manual_bundling_off
= 1;
5421 md
.manual_bundling
= 0;
5427 /* Returns the next entry in the opcode table that matches the one in
5428 IDESC, and frees the entry in IDESC. If no matching entry is
5429 found, NULL is returned instead. */
5431 static struct ia64_opcode
*
5432 get_next_opcode (struct ia64_opcode
*idesc
)
5434 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5435 ia64_free_opcode (idesc
);
5439 /* Parse the operands for the opcode and find the opcode variant that
5440 matches the specified operands, or NULL if no match is possible. */
5442 static struct ia64_opcode
*
5443 parse_operands (idesc
)
5444 struct ia64_opcode
*idesc
;
5446 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5447 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5448 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5449 enum operand_match_result result
;
5451 char *first_arg
= 0, *end
, *saved_input_pointer
;
5454 assert (strlen (idesc
->name
) <= 128);
5456 strcpy (mnemonic
, idesc
->name
);
5457 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5459 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5460 can't parse the first operand until we have parsed the
5461 remaining operands of the "alloc" instruction. */
5463 first_arg
= input_line_pointer
;
5464 end
= strchr (input_line_pointer
, '=');
5467 as_bad ("Expected separator `='");
5470 input_line_pointer
= end
+ 1;
5475 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5477 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5478 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5483 if (sep
!= '=' && sep
!= ',')
5488 if (num_outputs
> 0)
5489 as_bad ("Duplicate equal sign (=) in instruction");
5491 num_outputs
= i
+ 1;
5496 as_bad ("Illegal operand separator `%c'", sep
);
5500 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5502 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5503 know (strcmp (idesc
->name
, "alloc") == 0);
5504 if (num_operands
== 5 /* first_arg not included in this count! */
5505 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5506 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5507 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5508 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5510 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5511 CURR_SLOT
.opnd
[3].X_add_number
,
5512 CURR_SLOT
.opnd
[4].X_add_number
,
5513 CURR_SLOT
.opnd
[5].X_add_number
);
5515 /* now we can parse the first arg: */
5516 saved_input_pointer
= input_line_pointer
;
5517 input_line_pointer
= first_arg
;
5518 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5520 --num_outputs
; /* force error */
5521 input_line_pointer
= saved_input_pointer
;
5523 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5524 CURR_SLOT
.opnd
[3].X_add_number
5525 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5526 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5530 highest_unmatched_operand
= 0;
5531 curr_out_of_range_pos
= -1;
5533 expected_operand
= idesc
->operands
[0];
5534 for (; idesc
; idesc
= get_next_opcode (idesc
))
5536 if (num_outputs
!= idesc
->num_outputs
)
5537 continue; /* mismatch in # of outputs */
5539 CURR_SLOT
.num_fixups
= 0;
5541 /* Try to match all operands. If we see an out-of-range operand,
5542 then continue trying to match the rest of the operands, since if
5543 the rest match, then this idesc will give the best error message. */
5545 out_of_range_pos
= -1;
5546 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5548 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5549 if (result
!= OPERAND_MATCH
)
5551 if (result
!= OPERAND_OUT_OF_RANGE
)
5553 if (out_of_range_pos
< 0)
5554 /* remember position of the first out-of-range operand: */
5555 out_of_range_pos
= i
;
5559 /* If we did not match all operands, or if at least one operand was
5560 out-of-range, then this idesc does not match. Keep track of which
5561 idesc matched the most operands before failing. If we have two
5562 idescs that failed at the same position, and one had an out-of-range
5563 operand, then prefer the out-of-range operand. Thus if we have
5564 "add r0=0x1000000,r1" we get an error saying the constant is out
5565 of range instead of an error saying that the constant should have been
5568 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5570 if (i
> highest_unmatched_operand
5571 || (i
== highest_unmatched_operand
5572 && out_of_range_pos
> curr_out_of_range_pos
))
5574 highest_unmatched_operand
= i
;
5575 if (out_of_range_pos
>= 0)
5577 expected_operand
= idesc
->operands
[out_of_range_pos
];
5578 error_pos
= out_of_range_pos
;
5582 expected_operand
= idesc
->operands
[i
];
5585 curr_out_of_range_pos
= out_of_range_pos
;
5590 if (num_operands
< NELEMS (idesc
->operands
)
5591 && idesc
->operands
[num_operands
])
5592 continue; /* mismatch in number of arguments */
5598 if (expected_operand
)
5599 as_bad ("Operand %u of `%s' should be %s",
5600 error_pos
+ 1, mnemonic
,
5601 elf64_ia64_operands
[expected_operand
].desc
);
5603 as_bad ("Operand mismatch");
5609 /* Keep track of state necessary to determine whether a NOP is necessary
5610 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5611 detect a case where additional NOPs may be necessary. */
5613 errata_nop_necessary_p (slot
, insn_unit
)
5615 enum ia64_unit insn_unit
;
5618 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5619 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5620 struct ia64_opcode
*idesc
= slot
->idesc
;
5622 /* Test whether this could be the first insn in a problematic sequence. */
5623 if (insn_unit
== IA64_UNIT_F
)
5625 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5626 if (idesc
->operands
[i
] == IA64_OPND_P1
5627 || idesc
->operands
[i
] == IA64_OPND_P2
)
5629 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5630 /* Ignore invalid operands; they generate errors elsewhere. */
5633 this_group
->p_reg_set
[regno
] = 1;
5637 /* Test whether this could be the second insn in a problematic sequence. */
5638 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5639 && prev_group
->p_reg_set
[slot
->qp_regno
])
5641 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5642 if (idesc
->operands
[i
] == IA64_OPND_R1
5643 || idesc
->operands
[i
] == IA64_OPND_R2
5644 || idesc
->operands
[i
] == IA64_OPND_R3
)
5646 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5647 /* Ignore invalid operands; they generate errors elsewhere. */
5650 if (strncmp (idesc
->name
, "add", 3) != 0
5651 && strncmp (idesc
->name
, "sub", 3) != 0
5652 && strncmp (idesc
->name
, "shladd", 6) != 0
5653 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5654 this_group
->g_reg_set_conditionally
[regno
] = 1;
5658 /* Test whether this could be the third insn in a problematic sequence. */
5659 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5661 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5662 idesc
->operands
[i
] == IA64_OPND_R3
5663 /* For mov indirect. */
5664 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5665 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5666 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5667 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5668 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5669 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5670 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5671 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5673 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5674 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5675 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5676 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5678 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5679 /* Ignore invalid operands; they generate errors elsewhere. */
5682 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5684 if (strcmp (idesc
->name
, "fc") != 0
5685 && strcmp (idesc
->name
, "tak") != 0
5686 && strcmp (idesc
->name
, "thash") != 0
5687 && strcmp (idesc
->name
, "tpa") != 0
5688 && strcmp (idesc
->name
, "ttag") != 0
5689 && strncmp (idesc
->name
, "ptr", 3) != 0
5690 && strncmp (idesc
->name
, "ptc", 3) != 0
5691 && strncmp (idesc
->name
, "probe", 5) != 0)
5694 if (prev_group
->g_reg_set_conditionally
[regno
])
5702 build_insn (slot
, insnp
)
5706 const struct ia64_operand
*odesc
, *o2desc
;
5707 struct ia64_opcode
*idesc
= slot
->idesc
;
5708 bfd_signed_vma insn
, val
;
5712 insn
= idesc
->opcode
| slot
->qp_regno
;
5714 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5716 if (slot
->opnd
[i
].X_op
== O_register
5717 || slot
->opnd
[i
].X_op
== O_constant
5718 || slot
->opnd
[i
].X_op
== O_index
)
5719 val
= slot
->opnd
[i
].X_add_number
;
5720 else if (slot
->opnd
[i
].X_op
== O_big
)
5722 /* This must be the value 0x10000000000000000. */
5723 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5729 switch (idesc
->operands
[i
])
5731 case IA64_OPND_IMMU64
:
5732 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5733 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5734 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5735 | (((val
>> 63) & 0x1) << 36));
5738 case IA64_OPND_IMMU62
:
5739 val
&= 0x3fffffffffffffffULL
;
5740 if (val
!= slot
->opnd
[i
].X_add_number
)
5741 as_warn (_("Value truncated to 62 bits"));
5742 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5743 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5746 case IA64_OPND_TGT64
:
5748 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5749 insn
|= ((((val
>> 59) & 0x1) << 36)
5750 | (((val
>> 0) & 0xfffff) << 13));
5781 case IA64_OPND_R3_2
:
5782 case IA64_OPND_CPUID_R3
:
5783 case IA64_OPND_DBR_R3
:
5784 case IA64_OPND_DTR_R3
:
5785 case IA64_OPND_ITR_R3
:
5786 case IA64_OPND_IBR_R3
:
5788 case IA64_OPND_MSR_R3
:
5789 case IA64_OPND_PKR_R3
:
5790 case IA64_OPND_PMC_R3
:
5791 case IA64_OPND_PMD_R3
:
5792 case IA64_OPND_RR_R3
:
5800 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5801 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5803 as_bad_where (slot
->src_file
, slot
->src_line
,
5804 "Bad operand value: %s", err
);
5805 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5807 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5808 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5810 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5811 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5813 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5814 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5815 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5817 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5818 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5828 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5829 unsigned int manual_bundling
= 0;
5830 enum ia64_unit required_unit
, insn_unit
= 0;
5831 enum ia64_insn_type type
[3], insn_type
;
5832 unsigned int template, orig_template
;
5833 bfd_vma insn
[3] = { -1, -1, -1 };
5834 struct ia64_opcode
*idesc
;
5835 int end_of_insn_group
= 0, user_template
= -1;
5836 int n
, i
, j
, first
, curr
;
5838 bfd_vma t0
= 0, t1
= 0;
5839 struct label_fix
*lfix
;
5840 struct insn_fix
*ifix
;
5845 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5846 know (first
>= 0 & first
< NUM_SLOTS
);
5847 n
= MIN (3, md
.num_slots_in_use
);
5849 /* Determine template: user user_template if specified, best match
5852 if (md
.slot
[first
].user_template
>= 0)
5853 user_template
= template = md
.slot
[first
].user_template
;
5856 /* Auto select appropriate template. */
5857 memset (type
, 0, sizeof (type
));
5859 for (i
= 0; i
< n
; ++i
)
5861 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5863 type
[i
] = md
.slot
[curr
].idesc
->type
;
5864 curr
= (curr
+ 1) % NUM_SLOTS
;
5866 template = best_template
[type
[0]][type
[1]][type
[2]];
5869 /* initialize instructions with appropriate nops: */
5870 for (i
= 0; i
< 3; ++i
)
5871 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5875 /* now fill in slots with as many insns as possible: */
5877 idesc
= md
.slot
[curr
].idesc
;
5878 end_of_insn_group
= 0;
5879 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5881 /* Set the slot number for prologue/body records now as those
5882 refer to the current point, not the point after the
5883 instruction has been issued: */
5884 /* Don't try to delete prologue/body records here, as that will cause
5885 them to also be deleted from the master list of unwind records. */
5886 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5887 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5888 || ptr
->r
.type
== body
)
5890 ptr
->slot_number
= (unsigned long) f
+ i
;
5891 ptr
->slot_frag
= frag_now
;
5894 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5896 if (manual_bundling
&& i
!= 2)
5897 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5898 "`%s' must be last in bundle", idesc
->name
);
5902 if (idesc
->flags
& IA64_OPCODE_LAST
)
5905 unsigned int required_template
;
5907 /* If we need a stop bit after an M slot, our only choice is
5908 template 5 (M;;MI). If we need a stop bit after a B
5909 slot, our only choice is to place it at the end of the
5910 bundle, because the only available templates are MIB,
5911 MBB, BBB, MMB, and MFB. We don't handle anything other
5912 than M and B slots because these are the only kind of
5913 instructions that can have the IA64_OPCODE_LAST bit set. */
5914 required_template
= template;
5915 switch (idesc
->type
)
5919 required_template
= 5;
5927 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5928 "Internal error: don't know how to force %s to end"
5929 "of instruction group", idesc
->name
);
5933 if (manual_bundling
&& i
!= required_slot
)
5934 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5935 "`%s' must be last in instruction group",
5937 if (required_slot
< i
)
5938 /* Can't fit this instruction. */
5942 if (required_template
!= template)
5944 /* If we switch the template, we need to reset the NOPs
5945 after slot i. The slot-types of the instructions ahead
5946 of i never change, so we don't need to worry about
5947 changing NOPs in front of this slot. */
5948 for (j
= i
; j
< 3; ++j
)
5949 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5951 template = required_template
;
5953 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5955 if (manual_bundling_on
)
5956 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5957 "Label must be first in a bundle");
5958 /* This insn must go into the first slot of a bundle. */
5962 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5963 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5965 if (manual_bundling_on
)
5968 manual_bundling
= 1;
5970 break; /* need to start a new bundle */
5973 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5975 /* We need an instruction group boundary in the middle of a
5976 bundle. See if we can switch to an other template with
5977 an appropriate boundary. */
5979 orig_template
= template;
5980 if (i
== 1 && (user_template
== 4
5981 || (user_template
< 0
5982 && (ia64_templ_desc
[template].exec_unit
[0]
5986 end_of_insn_group
= 0;
5988 else if (i
== 2 && (user_template
== 0
5989 || (user_template
< 0
5990 && (ia64_templ_desc
[template].exec_unit
[1]
5992 /* This test makes sure we don't switch the template if
5993 the next instruction is one that needs to be first in
5994 an instruction group. Since all those instructions are
5995 in the M group, there is no way such an instruction can
5996 fit in this bundle even if we switch the template. The
5997 reason we have to check for this is that otherwise we
5998 may end up generating "MI;;I M.." which has the deadly
5999 effect that the second M instruction is no longer the
6000 first in the bundle! --davidm 99/12/16 */
6001 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
6004 end_of_insn_group
= 0;
6006 else if (curr
!= first
)
6007 /* can't fit this insn */
6010 if (template != orig_template
)
6011 /* if we switch the template, we need to reset the NOPs
6012 after slot i. The slot-types of the instructions ahead
6013 of i never change, so we don't need to worry about
6014 changing NOPs in front of this slot. */
6015 for (j
= i
; j
< 3; ++j
)
6016 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
6018 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6020 /* resolve dynamic opcodes such as "break" and "nop": */
6021 if (idesc
->type
== IA64_TYPE_DYN
)
6023 if ((strcmp (idesc
->name
, "nop") == 0)
6024 || (strcmp (idesc
->name
, "break") == 0))
6025 insn_unit
= required_unit
;
6026 else if (strcmp (idesc
->name
, "chk.s") == 0)
6028 insn_unit
= IA64_UNIT_M
;
6029 if (required_unit
== IA64_UNIT_I
)
6030 insn_unit
= IA64_UNIT_I
;
6033 as_fatal ("emit_one_bundle: unexpected dynamic op");
6035 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6036 ia64_free_opcode (idesc
);
6037 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6039 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6044 insn_type
= idesc
->type
;
6045 insn_unit
= IA64_UNIT_NIL
;
6049 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6050 insn_unit
= required_unit
;
6052 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6053 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6054 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6055 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6056 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6061 if (insn_unit
!= required_unit
)
6063 if (required_unit
== IA64_UNIT_L
6064 && insn_unit
== IA64_UNIT_I
6065 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6067 /* we got ourselves an MLX template but the current
6068 instruction isn't an X-unit, or an I-unit instruction
6069 that can go into the X slot of an MLX template. Duh. */
6070 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6072 as_bad_where (md
.slot
[curr
].src_file
,
6073 md
.slot
[curr
].src_line
,
6074 "`%s' can't go in X slot of "
6075 "MLX template", idesc
->name
);
6076 /* drop this insn so we don't livelock: */
6077 --md
.num_slots_in_use
;
6081 continue; /* try next slot */
6087 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6088 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6091 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6092 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6094 build_insn (md
.slot
+ curr
, insn
+ i
);
6096 /* Set slot counts for non prologue/body unwind records. */
6097 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6098 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6099 && ptr
->r
.type
!= body
)
6101 ptr
->slot_number
= (unsigned long) f
+ i
;
6102 ptr
->slot_frag
= frag_now
;
6104 md
.slot
[curr
].unwind_record
= NULL
;
6106 if (required_unit
== IA64_UNIT_L
)
6109 /* skip one slot for long/X-unit instructions */
6112 --md
.num_slots_in_use
;
6114 /* now is a good time to fix up the labels for this insn: */
6115 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6117 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6118 symbol_set_frag (lfix
->sym
, frag_now
);
6120 /* and fix up the tags also. */
6121 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6123 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6124 symbol_set_frag (lfix
->sym
, frag_now
);
6127 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6129 ifix
= md
.slot
[curr
].fixup
+ j
;
6130 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6131 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6132 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6133 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6134 fix
->fx_file
= md
.slot
[curr
].src_file
;
6135 fix
->fx_line
= md
.slot
[curr
].src_line
;
6138 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6140 if (end_of_insn_group
)
6142 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6143 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6147 ia64_free_opcode (md
.slot
[curr
].idesc
);
6148 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6149 md
.slot
[curr
].user_template
= -1;
6151 if (manual_bundling_off
)
6153 manual_bundling
= 0;
6156 curr
= (curr
+ 1) % NUM_SLOTS
;
6157 idesc
= md
.slot
[curr
].idesc
;
6159 if (manual_bundling
)
6161 if (md
.num_slots_in_use
> 0)
6162 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6163 "`%s' does not fit into %s template",
6164 idesc
->name
, ia64_templ_desc
[template].name
);
6166 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6167 "Missing '}' at end of file");
6169 know (md
.num_slots_in_use
< NUM_SLOTS
);
6171 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6172 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6174 number_to_chars_littleendian (f
+ 0, t0
, 8);
6175 number_to_chars_littleendian (f
+ 8, t1
, 8);
6177 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6178 unwind
.next_slot_frag
= frag_now
;
6182 md_parse_option (c
, arg
)
6189 /* Switches from the Intel assembler. */
6191 if (strcmp (arg
, "ilp64") == 0
6192 || strcmp (arg
, "lp64") == 0
6193 || strcmp (arg
, "p64") == 0)
6195 md
.flags
|= EF_IA_64_ABI64
;
6197 else if (strcmp (arg
, "ilp32") == 0)
6199 md
.flags
&= ~EF_IA_64_ABI64
;
6201 else if (strcmp (arg
, "le") == 0)
6203 md
.flags
&= ~EF_IA_64_BE
;
6205 else if (strcmp (arg
, "be") == 0)
6207 md
.flags
|= EF_IA_64_BE
;
6214 if (strcmp (arg
, "so") == 0)
6216 /* Suppress signon message. */
6218 else if (strcmp (arg
, "pi") == 0)
6220 /* Reject privileged instructions. FIXME */
6222 else if (strcmp (arg
, "us") == 0)
6224 /* Allow union of signed and unsigned range. FIXME */
6226 else if (strcmp (arg
, "close_fcalls") == 0)
6228 /* Do not resolve global function calls. */
6235 /* temp[="prefix"] Insert temporary labels into the object file
6236 symbol table prefixed by "prefix".
6237 Default prefix is ":temp:".
6242 /* indirect=<tgt> Assume unannotated indirect branches behavior
6243 according to <tgt> --
6244 exit: branch out from the current context (default)
6245 labels: all labels in context may be branch targets
6247 if (strncmp (arg
, "indirect=", 9) != 0)
6252 /* -X conflicts with an ignored option, use -x instead */
6254 if (!arg
|| strcmp (arg
, "explicit") == 0)
6256 /* set default mode to explicit */
6257 md
.default_explicit_mode
= 1;
6260 else if (strcmp (arg
, "auto") == 0)
6262 md
.default_explicit_mode
= 0;
6264 else if (strcmp (arg
, "debug") == 0)
6268 else if (strcmp (arg
, "debugx") == 0)
6270 md
.default_explicit_mode
= 1;
6275 as_bad (_("Unrecognized option '-x%s'"), arg
);
6280 /* nops Print nops statistics. */
6283 /* GNU specific switches for gcc. */
6284 case OPTION_MCONSTANT_GP
:
6285 md
.flags
|= EF_IA_64_CONS_GP
;
6288 case OPTION_MAUTO_PIC
:
6289 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6300 md_show_usage (stream
)
6305 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6306 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6307 -x | -xexplicit turn on dependency violation checking (default)\n\
6308 -xauto automagically remove dependency violations\n\
6309 -xdebug debug dependency violation checker\n"),
6313 /* Return true if TYPE fits in TEMPL at SLOT. */
6316 match (int templ
, int type
, int slot
)
6318 enum ia64_unit unit
;
6321 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6324 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6326 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6328 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6329 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6330 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6331 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6332 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6333 default: result
= 0; break;
6338 /* Add a bit of extra goodness if a nop of type F or B would fit
6339 in TEMPL at SLOT. */
6342 extra_goodness (int templ
, int slot
)
6344 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6346 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6351 /* This function is called once, at assembler startup time. It sets
6352 up all the tables, etc. that the MD part of the assembler will need
6353 that can be determined before arguments are parsed. */
6357 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6362 md
.explicit_mode
= md
.default_explicit_mode
;
6364 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6366 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6367 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6368 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6369 &zero_address_frag
);
6371 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6372 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6373 &zero_address_frag
);
6375 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6376 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6377 &zero_address_frag
);
6379 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6380 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6381 &zero_address_frag
);
6383 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6384 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6385 &zero_address_frag
);
6387 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6388 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6389 &zero_address_frag
);
6391 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6392 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6393 &zero_address_frag
);
6395 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6396 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6397 &zero_address_frag
);
6399 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6400 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6401 &zero_address_frag
);
6403 pseudo_func
[FUNC_IPLT_RELOC
].u
.sym
=
6404 symbol_new (".<iplt>", undefined_section
, FUNC_IPLT_RELOC
,
6405 &zero_address_frag
);
6407 /* Compute the table of best templates. We compute goodness as a
6408 base 4 value, in which each match counts for 3, each F counts
6409 for 2, each B counts for 1. This should maximize the number of
6410 F and B nops in the chosen bundles, which is good because these
6411 pipelines are least likely to be overcommitted. */
6412 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6413 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6414 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6417 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6420 if (match (t
, i
, 0))
6422 if (match (t
, j
, 1))
6424 if (match (t
, k
, 2))
6425 goodness
= 3 + 3 + 3;
6427 goodness
= 3 + 3 + extra_goodness (t
, 2);
6429 else if (match (t
, j
, 2))
6430 goodness
= 3 + 3 + extra_goodness (t
, 1);
6434 goodness
+= extra_goodness (t
, 1);
6435 goodness
+= extra_goodness (t
, 2);
6438 else if (match (t
, i
, 1))
6440 if (match (t
, j
, 2))
6443 goodness
= 3 + extra_goodness (t
, 2);
6445 else if (match (t
, i
, 2))
6446 goodness
= 3 + extra_goodness (t
, 1);
6448 if (goodness
> best
)
6451 best_template
[i
][j
][k
] = t
;
6456 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6457 md
.slot
[i
].user_template
= -1;
6459 md
.pseudo_hash
= hash_new ();
6460 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6462 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6463 (void *) (pseudo_opcode
+ i
));
6465 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6466 pseudo_opcode
[i
].name
, err
);
6469 md
.reg_hash
= hash_new ();
6470 md
.dynreg_hash
= hash_new ();
6471 md
.const_hash
= hash_new ();
6472 md
.entry_hash
= hash_new ();
6474 /* general registers: */
6477 for (i
= 0; i
< total
; ++i
)
6479 sprintf (name
, "r%d", i
- REG_GR
);
6480 md
.regsym
[i
] = declare_register (name
, i
);
6483 /* floating point registers: */
6485 for (; i
< total
; ++i
)
6487 sprintf (name
, "f%d", i
- REG_FR
);
6488 md
.regsym
[i
] = declare_register (name
, i
);
6491 /* application registers: */
6494 for (; i
< total
; ++i
)
6496 sprintf (name
, "ar%d", i
- REG_AR
);
6497 md
.regsym
[i
] = declare_register (name
, i
);
6500 /* control registers: */
6503 for (; i
< total
; ++i
)
6505 sprintf (name
, "cr%d", i
- REG_CR
);
6506 md
.regsym
[i
] = declare_register (name
, i
);
6509 /* predicate registers: */
6511 for (; i
< total
; ++i
)
6513 sprintf (name
, "p%d", i
- REG_P
);
6514 md
.regsym
[i
] = declare_register (name
, i
);
6517 /* branch registers: */
6519 for (; i
< total
; ++i
)
6521 sprintf (name
, "b%d", i
- REG_BR
);
6522 md
.regsym
[i
] = declare_register (name
, i
);
6525 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6526 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6527 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6528 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6529 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6530 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6531 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6533 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6535 regnum
= indirect_reg
[i
].regnum
;
6536 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6539 /* define synonyms for application registers: */
6540 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6541 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6542 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6544 /* define synonyms for control registers: */
6545 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6546 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6547 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6549 declare_register ("gp", REG_GR
+ 1);
6550 declare_register ("sp", REG_GR
+ 12);
6551 declare_register ("rp", REG_BR
+ 0);
6553 /* pseudo-registers used to specify unwind info: */
6554 declare_register ("psp", REG_PSP
);
6556 declare_register_set ("ret", 4, REG_GR
+ 8);
6557 declare_register_set ("farg", 8, REG_FR
+ 8);
6558 declare_register_set ("fret", 8, REG_FR
+ 8);
6560 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6562 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6563 (PTR
) (const_bits
+ i
));
6565 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6569 /* Set the architecture and machine depending on defaults and command line
6571 if (md
.flags
& EF_IA_64_ABI64
)
6572 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6574 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6577 as_warn (_("Could not set architecture and machine"));
6579 /* Set the pointer size and pointer shift size depending on md.flags */
6581 if (md
.flags
& EF_IA_64_ABI64
)
6583 md
.pointer_size
= 8; /* pointers are 8 bytes */
6584 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6588 md
.pointer_size
= 4; /* pointers are 4 bytes */
6589 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6592 md
.mem_offset
.hint
= 0;
6595 md
.entry_labels
= NULL
;
6598 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6599 because that is called after md_parse_option which is where we do the
6600 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6601 default endianness. */
6604 ia64_init (argc
, argv
)
6605 int argc ATTRIBUTE_UNUSED
;
6606 char **argv ATTRIBUTE_UNUSED
;
6608 md
.flags
= EF_IA_64_ABI64
;
6609 if (TARGET_BYTES_BIG_ENDIAN
)
6610 md
.flags
|= EF_IA_64_BE
;
6613 /* Return a string for the target object file format. */
6616 ia64_target_format ()
6618 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6620 if (md
.flags
& EF_IA_64_BE
)
6622 if (md
.flags
& EF_IA_64_ABI64
)
6624 return "elf64-ia64-aix-big";
6626 return "elf64-ia64-big";
6630 return "elf32-ia64-aix-big";
6632 return "elf32-ia64-big";
6637 if (md
.flags
& EF_IA_64_ABI64
)
6639 return "elf64-ia64-aix-little";
6641 return "elf64-ia64-little";
6645 return "elf32-ia64-aix-little";
6647 return "elf32-ia64-little";
6652 return "unknown-format";
6656 ia64_end_of_source ()
6658 /* terminate insn group upon reaching end of file: */
6659 insn_group_break (1, 0, 0);
6661 /* emits slots we haven't written yet: */
6662 ia64_flush_insns ();
6664 bfd_set_private_flags (stdoutput
, md
.flags
);
6666 md
.mem_offset
.hint
= 0;
6672 if (md
.qp
.X_op
== O_register
)
6673 as_bad ("qualifying predicate not followed by instruction");
6674 md
.qp
.X_op
= O_absent
;
6676 if (ignore_input ())
6679 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6681 if (md
.detect_dv
&& !md
.explicit_mode
)
6682 as_warn (_("Explicit stops are ignored in auto mode"));
6684 insn_group_break (1, 0, 0);
6688 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6690 static int defining_tag
= 0;
6693 ia64_unrecognized_line (ch
)
6699 expression (&md
.qp
);
6700 if (*input_line_pointer
++ != ')')
6702 as_bad ("Expected ')'");
6705 if (md
.qp
.X_op
!= O_register
)
6707 as_bad ("Qualifying predicate expected");
6710 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6712 as_bad ("Predicate register expected");
6718 if (md
.manual_bundling
)
6719 as_warn ("Found '{' when manual bundling is already turned on");
6721 CURR_SLOT
.manual_bundling_on
= 1;
6722 md
.manual_bundling
= 1;
6724 /* Bundling is only acceptable in explicit mode
6725 or when in default automatic mode. */
6726 if (md
.detect_dv
&& !md
.explicit_mode
)
6728 if (!md
.mode_explicitly_set
6729 && !md
.default_explicit_mode
)
6732 as_warn (_("Found '{' after explicit switch to automatic mode"));
6737 if (!md
.manual_bundling
)
6738 as_warn ("Found '}' when manual bundling is off");
6740 PREV_SLOT
.manual_bundling_off
= 1;
6741 md
.manual_bundling
= 0;
6743 /* switch back to automatic mode, if applicable */
6746 && !md
.mode_explicitly_set
6747 && !md
.default_explicit_mode
)
6750 /* Allow '{' to follow on the same line. We also allow ";;", but that
6751 happens automatically because ';' is an end of line marker. */
6753 if (input_line_pointer
[0] == '{')
6755 input_line_pointer
++;
6756 return ia64_unrecognized_line ('{');
6759 demand_empty_rest_of_line ();
6769 if (md
.qp
.X_op
== O_register
)
6771 as_bad ("Tag must come before qualifying predicate.");
6775 /* This implements just enough of read_a_source_file in read.c to
6776 recognize labels. */
6777 if (is_name_beginner (*input_line_pointer
))
6779 s
= input_line_pointer
;
6780 c
= get_symbol_end ();
6782 else if (LOCAL_LABELS_FB
6783 && ISDIGIT (*input_line_pointer
))
6786 while (ISDIGIT (*input_line_pointer
))
6787 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6788 fb_label_instance_inc (temp
);
6789 s
= fb_label_name (temp
, 0);
6790 c
= *input_line_pointer
;
6799 /* Put ':' back for error messages' sake. */
6800 *input_line_pointer
++ = ':';
6801 as_bad ("Expected ':'");
6808 /* Put ':' back for error messages' sake. */
6809 *input_line_pointer
++ = ':';
6810 if (*input_line_pointer
++ != ']')
6812 as_bad ("Expected ']'");
6817 as_bad ("Tag name expected");
6827 /* Not a valid line. */
6832 ia64_frob_label (sym
)
6835 struct label_fix
*fix
;
6837 /* Tags need special handling since they are not bundle breaks like
6841 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6843 fix
->next
= CURR_SLOT
.tag_fixups
;
6844 CURR_SLOT
.tag_fixups
= fix
;
6849 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6851 md
.last_text_seg
= now_seg
;
6852 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6854 fix
->next
= CURR_SLOT
.label_fixups
;
6855 CURR_SLOT
.label_fixups
= fix
;
6857 /* Keep track of how many code entry points we've seen. */
6858 if (md
.path
== md
.maxpaths
)
6861 md
.entry_labels
= (const char **)
6862 xrealloc ((void *) md
.entry_labels
,
6863 md
.maxpaths
* sizeof (char *));
6865 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6870 ia64_flush_pending_output ()
6872 if (!md
.keep_pending_output
6873 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6875 /* ??? This causes many unnecessary stop bits to be emitted.
6876 Unfortunately, it isn't clear if it is safe to remove this. */
6877 insn_group_break (1, 0, 0);
6878 ia64_flush_insns ();
6882 /* Do ia64-specific expression optimization. All that's done here is
6883 to transform index expressions that are either due to the indexing
6884 of rotating registers or due to the indexing of indirect register
6887 ia64_optimize_expr (l
, op
, r
)
6896 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6898 num_regs
= (l
->X_add_number
>> 16);
6899 if ((unsigned) r
->X_add_number
>= num_regs
)
6902 as_bad ("No current frame");
6904 as_bad ("Index out of range 0..%u", num_regs
- 1);
6905 r
->X_add_number
= 0;
6907 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6910 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6912 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6913 || l
->X_add_number
== IND_MEM
)
6915 as_bad ("Indirect register set name expected");
6916 l
->X_add_number
= IND_CPUID
;
6919 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6920 l
->X_add_number
= r
->X_add_number
;
6928 ia64_parse_name (name
, e
)
6932 struct const_desc
*cdesc
;
6933 struct dynreg
*dr
= 0;
6934 unsigned int regnum
;
6938 /* first see if NAME is a known register name: */
6939 sym
= hash_find (md
.reg_hash
, name
);
6942 e
->X_op
= O_register
;
6943 e
->X_add_number
= S_GET_VALUE (sym
);
6947 cdesc
= hash_find (md
.const_hash
, name
);
6950 e
->X_op
= O_constant
;
6951 e
->X_add_number
= cdesc
->value
;
6955 /* check for inN, locN, or outN: */
6959 if (name
[1] == 'n' && ISDIGIT (name
[2]))
6967 if (name
[1] == 'o' && name
[2] == 'c' && ISDIGIT (name
[3]))
6975 if (name
[1] == 'u' && name
[2] == 't' && ISDIGIT (name
[3]))
6988 /* The name is inN, locN, or outN; parse the register number. */
6989 regnum
= strtoul (name
, &end
, 10);
6990 if (end
> name
&& *end
== '\0')
6992 if ((unsigned) regnum
>= dr
->num_regs
)
6995 as_bad ("No current frame");
6997 as_bad ("Register number out of range 0..%u",
7001 e
->X_op
= O_register
;
7002 e
->X_add_number
= dr
->base
+ regnum
;
7007 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
7009 /* We've got ourselves the name of a rotating register set.
7010 Store the base register number in the low 16 bits of
7011 X_add_number and the size of the register set in the top 16
7013 e
->X_op
= O_register
;
7014 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
7020 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7023 ia64_canonicalize_symbol_name (name
)
7026 size_t len
= strlen (name
);
7027 if (len
> 1 && name
[len
- 1] == '#')
7028 name
[len
- 1] = '\0';
7032 /* Return true if idesc is a conditional branch instruction. This excludes
7033 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7034 because they always read/write resources regardless of the value of the
7035 qualifying predicate. br.ia must always use p0, and hence is always
7036 taken. Thus this function returns true for branches which can fall
7037 through, and which use no resources if they do fall through. */
7040 is_conditional_branch (idesc
)
7041 struct ia64_opcode
*idesc
;
7043 /* br is a conditional branch. Everything that starts with br. except
7044 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7045 Everything that starts with brl is a conditional branch. */
7046 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7047 && (idesc
->name
[2] == '\0'
7048 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7049 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7050 || idesc
->name
[2] == 'l'
7051 /* br.cond, br.call, br.clr */
7052 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7053 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7054 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7057 /* Return whether the given opcode is a taken branch. If there's any doubt,
7061 is_taken_branch (idesc
)
7062 struct ia64_opcode
*idesc
;
7064 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7065 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7068 /* Return whether the given opcode is an interruption or rfi. If there's any
7069 doubt, returns zero. */
7072 is_interruption_or_rfi (idesc
)
7073 struct ia64_opcode
*idesc
;
7075 if (strcmp (idesc
->name
, "rfi") == 0)
7080 /* Returns the index of the given dependency in the opcode's list of chks, or
7081 -1 if there is no dependency. */
7084 depends_on (depind
, idesc
)
7086 struct ia64_opcode
*idesc
;
7089 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7090 for (i
= 0; i
< dep
->nchks
; i
++)
7092 if (depind
== DEP (dep
->chks
[i
]))
7098 /* Determine a set of specific resources used for a particular resource
7099 class. Returns the number of specific resources identified For those
7100 cases which are not determinable statically, the resource returned is
7103 Meanings of value in 'NOTE':
7104 1) only read/write when the register number is explicitly encoded in the
7106 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7107 accesses CFM when qualifying predicate is in the rotating region.
7108 3) general register value is used to specify an indirect register; not
7109 determinable statically.
7110 4) only read the given resource when bits 7:0 of the indirect index
7111 register value does not match the register number of the resource; not
7112 determinable statically.
7113 5) all rules are implementation specific.
7114 6) only when both the index specified by the reader and the index specified
7115 by the writer have the same value in bits 63:61; not determinable
7117 7) only access the specified resource when the corresponding mask bit is
7119 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7120 only read when these insns reference FR2-31
7121 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7122 written when these insns write FR32-127
7123 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7125 11) The target predicates are written independently of PR[qp], but source
7126 registers are only read if PR[qp] is true. Since the state of PR[qp]
7127 cannot statically be determined, all source registers are marked used.
7128 12) This insn only reads the specified predicate register when that
7129 register is the PR[qp].
7130 13) This reference to ld-c only applies to teh GR whose value is loaded
7131 with data returned from memory, not the post-incremented address register.
7132 14) The RSE resource includes the implementation-specific RSE internal
7133 state resources. At least one (and possibly more) of these resources are
7134 read by each instruction listed in IC:rse-readers. At least one (and
7135 possibly more) of these resources are written by each insn listed in
7137 15+16) Represents reserved instructions, which the assembler does not
7140 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7141 this code; there are no dependency violations based on memory access.
7144 #define MAX_SPECS 256
7149 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7150 const struct ia64_dependency
*dep
;
7151 struct ia64_opcode
*idesc
;
7152 int type
; /* is this a DV chk or a DV reg? */
7153 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7154 int note
; /* resource note for this insn's usage */
7155 int path
; /* which execution path to examine */
7162 if (dep
->mode
== IA64_DV_WAW
7163 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7164 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7167 /* template for any resources we identify */
7168 tmpl
.dependency
= dep
;
7170 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7171 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7172 tmpl
.link_to_qp_branch
= 1;
7173 tmpl
.mem_offset
.hint
= 0;
7176 tmpl
.cmp_type
= CMP_NONE
;
7179 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7180 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7181 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7183 /* we don't need to track these */
7184 if (dep
->semantics
== IA64_DVS_NONE
)
7187 switch (dep
->specifier
)
7192 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7194 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7195 if (regno
>= 0 && regno
<= 7)
7197 specs
[count
] = tmpl
;
7198 specs
[count
++].index
= regno
;
7204 for (i
= 0; i
< 8; i
++)
7206 specs
[count
] = tmpl
;
7207 specs
[count
++].index
= i
;
7216 case IA64_RS_AR_UNAT
:
7217 /* This is a mov =AR or mov AR= instruction. */
7218 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7220 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7221 if (regno
== AR_UNAT
)
7223 specs
[count
++] = tmpl
;
7228 /* This is a spill/fill, or other instruction that modifies the
7231 /* Unless we can determine the specific bits used, mark the whole
7232 thing; bits 8:3 of the memory address indicate the bit used in
7233 UNAT. The .mem.offset hint may be used to eliminate a small
7234 subset of conflicts. */
7235 specs
[count
] = tmpl
;
7236 if (md
.mem_offset
.hint
)
7239 fprintf (stderr
, " Using hint for spill/fill\n");
7240 /* The index isn't actually used, just set it to something
7241 approximating the bit index. */
7242 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7243 specs
[count
].mem_offset
.hint
= 1;
7244 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7245 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7249 specs
[count
++].specific
= 0;
7257 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7259 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7260 if ((regno
>= 8 && regno
<= 15)
7261 || (regno
>= 20 && regno
<= 23)
7262 || (regno
>= 31 && regno
<= 39)
7263 || (regno
>= 41 && regno
<= 47)
7264 || (regno
>= 67 && regno
<= 111))
7266 specs
[count
] = tmpl
;
7267 specs
[count
++].index
= regno
;
7280 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7282 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7283 if ((regno
>= 48 && regno
<= 63)
7284 || (regno
>= 112 && regno
<= 127))
7286 specs
[count
] = tmpl
;
7287 specs
[count
++].index
= regno
;
7293 for (i
= 48; i
< 64; i
++)
7295 specs
[count
] = tmpl
;
7296 specs
[count
++].index
= i
;
7298 for (i
= 112; i
< 128; i
++)
7300 specs
[count
] = tmpl
;
7301 specs
[count
++].index
= i
;
7319 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7320 if (idesc
->operands
[i
] == IA64_OPND_B1
7321 || idesc
->operands
[i
] == IA64_OPND_B2
)
7323 specs
[count
] = tmpl
;
7324 specs
[count
++].index
=
7325 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7330 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7331 if (idesc
->operands
[i
] == IA64_OPND_B1
7332 || idesc
->operands
[i
] == IA64_OPND_B2
)
7334 specs
[count
] = tmpl
;
7335 specs
[count
++].index
=
7336 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7342 case IA64_RS_CPUID
: /* four or more registers */
7345 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7347 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7348 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7351 specs
[count
] = tmpl
;
7352 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7356 specs
[count
] = tmpl
;
7357 specs
[count
++].specific
= 0;
7367 case IA64_RS_DBR
: /* four or more registers */
7370 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7372 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7373 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7376 specs
[count
] = tmpl
;
7377 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7381 specs
[count
] = tmpl
;
7382 specs
[count
++].specific
= 0;
7386 else if (note
== 0 && !rsrc_write
)
7388 specs
[count
] = tmpl
;
7389 specs
[count
++].specific
= 0;
7397 case IA64_RS_IBR
: /* four or more registers */
7400 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7402 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7403 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7406 specs
[count
] = tmpl
;
7407 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7411 specs
[count
] = tmpl
;
7412 specs
[count
++].specific
= 0;
7425 /* These are implementation specific. Force all references to
7426 conflict with all other references. */
7427 specs
[count
] = tmpl
;
7428 specs
[count
++].specific
= 0;
7436 case IA64_RS_PKR
: /* 16 or more registers */
7437 if (note
== 3 || note
== 4)
7439 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7441 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7442 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7447 specs
[count
] = tmpl
;
7448 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7451 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7453 /* Uses all registers *except* the one in R3. */
7454 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7456 specs
[count
] = tmpl
;
7457 specs
[count
++].index
= i
;
7463 specs
[count
] = tmpl
;
7464 specs
[count
++].specific
= 0;
7471 specs
[count
] = tmpl
;
7472 specs
[count
++].specific
= 0;
7476 case IA64_RS_PMC
: /* four or more registers */
7479 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7480 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7483 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7485 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7486 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7489 specs
[count
] = tmpl
;
7490 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7494 specs
[count
] = tmpl
;
7495 specs
[count
++].specific
= 0;
7505 case IA64_RS_PMD
: /* four or more registers */
7508 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7510 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7511 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7514 specs
[count
] = tmpl
;
7515 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7519 specs
[count
] = tmpl
;
7520 specs
[count
++].specific
= 0;
7530 case IA64_RS_RR
: /* eight registers */
7533 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7535 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7536 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7539 specs
[count
] = tmpl
;
7540 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7544 specs
[count
] = tmpl
;
7545 specs
[count
++].specific
= 0;
7549 else if (note
== 0 && !rsrc_write
)
7551 specs
[count
] = tmpl
;
7552 specs
[count
++].specific
= 0;
7560 case IA64_RS_CR_IRR
:
7563 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7564 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7566 && idesc
->operands
[1] == IA64_OPND_CR3
7569 for (i
= 0; i
< 4; i
++)
7571 specs
[count
] = tmpl
;
7572 specs
[count
++].index
= CR_IRR0
+ i
;
7578 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7579 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7581 && regno
<= CR_IRR3
)
7583 specs
[count
] = tmpl
;
7584 specs
[count
++].index
= regno
;
7593 case IA64_RS_CR_LRR
:
7600 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7601 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7602 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7604 specs
[count
] = tmpl
;
7605 specs
[count
++].index
= regno
;
7613 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7615 specs
[count
] = tmpl
;
7616 specs
[count
++].index
=
7617 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7632 else if (rsrc_write
)
7634 if (dep
->specifier
== IA64_RS_FRb
7635 && idesc
->operands
[0] == IA64_OPND_F1
)
7637 specs
[count
] = tmpl
;
7638 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7643 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7645 if (idesc
->operands
[i
] == IA64_OPND_F2
7646 || idesc
->operands
[i
] == IA64_OPND_F3
7647 || idesc
->operands
[i
] == IA64_OPND_F4
)
7649 specs
[count
] = tmpl
;
7650 specs
[count
++].index
=
7651 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7660 /* This reference applies only to the GR whose value is loaded with
7661 data returned from memory. */
7662 specs
[count
] = tmpl
;
7663 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7669 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7670 if (idesc
->operands
[i
] == IA64_OPND_R1
7671 || idesc
->operands
[i
] == IA64_OPND_R2
7672 || idesc
->operands
[i
] == IA64_OPND_R3
)
7674 specs
[count
] = tmpl
;
7675 specs
[count
++].index
=
7676 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7678 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7679 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7680 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7682 specs
[count
] = tmpl
;
7683 specs
[count
++].index
=
7684 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7689 /* Look for anything that reads a GR. */
7690 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7692 if (idesc
->operands
[i
] == IA64_OPND_MR3
7693 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7694 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7695 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7696 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7697 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7698 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7699 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7700 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7701 || ((i
>= idesc
->num_outputs
)
7702 && (idesc
->operands
[i
] == IA64_OPND_R1
7703 || idesc
->operands
[i
] == IA64_OPND_R2
7704 || idesc
->operands
[i
] == IA64_OPND_R3
7705 /* addl source register. */
7706 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7708 specs
[count
] = tmpl
;
7709 specs
[count
++].index
=
7710 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7721 /* This is the same as IA64_RS_PRr, except that the register range is
7722 from 1 - 15, and there are no rotating register reads/writes here. */
7726 for (i
= 1; i
< 16; i
++)
7728 specs
[count
] = tmpl
;
7729 specs
[count
++].index
= i
;
7735 /* Mark only those registers indicated by the mask. */
7738 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7739 for (i
= 1; i
< 16; i
++)
7740 if (mask
& ((valueT
) 1 << i
))
7742 specs
[count
] = tmpl
;
7743 specs
[count
++].index
= i
;
7751 else if (note
== 11) /* note 11 implies note 1 as well */
7755 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7757 if (idesc
->operands
[i
] == IA64_OPND_P1
7758 || idesc
->operands
[i
] == IA64_OPND_P2
)
7760 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7761 if (regno
>= 1 && regno
< 16)
7763 specs
[count
] = tmpl
;
7764 specs
[count
++].index
= regno
;
7774 else if (note
== 12)
7776 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7778 specs
[count
] = tmpl
;
7779 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7786 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7787 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7788 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7789 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7791 if ((idesc
->operands
[0] == IA64_OPND_P1
7792 || idesc
->operands
[0] == IA64_OPND_P2
)
7793 && p1
>= 1 && p1
< 16)
7795 specs
[count
] = tmpl
;
7796 specs
[count
].cmp_type
=
7797 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7798 specs
[count
++].index
= p1
;
7800 if ((idesc
->operands
[1] == IA64_OPND_P1
7801 || idesc
->operands
[1] == IA64_OPND_P2
)
7802 && p2
>= 1 && p2
< 16)
7804 specs
[count
] = tmpl
;
7805 specs
[count
].cmp_type
=
7806 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7807 specs
[count
++].index
= p2
;
7812 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7814 specs
[count
] = tmpl
;
7815 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7817 if (idesc
->operands
[1] == IA64_OPND_PR
)
7819 for (i
= 1; i
< 16; i
++)
7821 specs
[count
] = tmpl
;
7822 specs
[count
++].index
= i
;
7833 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7834 simplified cases of this. */
7838 for (i
= 16; i
< 63; i
++)
7840 specs
[count
] = tmpl
;
7841 specs
[count
++].index
= i
;
7847 /* Mark only those registers indicated by the mask. */
7849 && idesc
->operands
[0] == IA64_OPND_PR
)
7851 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7852 if (mask
& ((valueT
) 1<<16))
7853 for (i
= 16; i
< 63; i
++)
7855 specs
[count
] = tmpl
;
7856 specs
[count
++].index
= i
;
7860 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7862 for (i
= 16; i
< 63; i
++)
7864 specs
[count
] = tmpl
;
7865 specs
[count
++].index
= i
;
7873 else if (note
== 11) /* note 11 implies note 1 as well */
7877 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7879 if (idesc
->operands
[i
] == IA64_OPND_P1
7880 || idesc
->operands
[i
] == IA64_OPND_P2
)
7882 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7883 if (regno
>= 16 && regno
< 63)
7885 specs
[count
] = tmpl
;
7886 specs
[count
++].index
= regno
;
7896 else if (note
== 12)
7898 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7900 specs
[count
] = tmpl
;
7901 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7908 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7909 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7910 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7911 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7913 if ((idesc
->operands
[0] == IA64_OPND_P1
7914 || idesc
->operands
[0] == IA64_OPND_P2
)
7915 && p1
>= 16 && p1
< 63)
7917 specs
[count
] = tmpl
;
7918 specs
[count
].cmp_type
=
7919 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7920 specs
[count
++].index
= p1
;
7922 if ((idesc
->operands
[1] == IA64_OPND_P1
7923 || idesc
->operands
[1] == IA64_OPND_P2
)
7924 && p2
>= 16 && p2
< 63)
7926 specs
[count
] = tmpl
;
7927 specs
[count
].cmp_type
=
7928 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7929 specs
[count
++].index
= p2
;
7934 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7936 specs
[count
] = tmpl
;
7937 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7939 if (idesc
->operands
[1] == IA64_OPND_PR
)
7941 for (i
= 16; i
< 63; i
++)
7943 specs
[count
] = tmpl
;
7944 specs
[count
++].index
= i
;
7956 /* Verify that the instruction is using the PSR bit indicated in
7960 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7962 if (dep
->regindex
< 6)
7964 specs
[count
++] = tmpl
;
7967 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7969 if (dep
->regindex
< 32
7970 || dep
->regindex
== 35
7971 || dep
->regindex
== 36
7972 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7974 specs
[count
++] = tmpl
;
7977 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7979 if (dep
->regindex
< 32
7980 || dep
->regindex
== 35
7981 || dep
->regindex
== 36
7982 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7984 specs
[count
++] = tmpl
;
7989 /* Several PSR bits have very specific dependencies. */
7990 switch (dep
->regindex
)
7993 specs
[count
++] = tmpl
;
7998 specs
[count
++] = tmpl
;
8002 /* Only certain CR accesses use PSR.ic */
8003 if (idesc
->operands
[0] == IA64_OPND_CR3
8004 || idesc
->operands
[1] == IA64_OPND_CR3
)
8007 ((idesc
->operands
[0] == IA64_OPND_CR3
)
8010 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8025 specs
[count
++] = tmpl
;
8034 specs
[count
++] = tmpl
;
8038 /* Only some AR accesses use cpl */
8039 if (idesc
->operands
[0] == IA64_OPND_AR3
8040 || idesc
->operands
[1] == IA64_OPND_AR3
)
8043 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8046 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8053 && regno
<= AR_K7
))))
8055 specs
[count
++] = tmpl
;
8060 specs
[count
++] = tmpl
;
8070 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8072 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8078 if (mask
& ((valueT
) 1 << dep
->regindex
))
8080 specs
[count
++] = tmpl
;
8085 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8086 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8087 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8088 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8090 if (idesc
->operands
[i
] == IA64_OPND_F1
8091 || idesc
->operands
[i
] == IA64_OPND_F2
8092 || idesc
->operands
[i
] == IA64_OPND_F3
8093 || idesc
->operands
[i
] == IA64_OPND_F4
)
8095 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8096 if (reg
>= min
&& reg
<= max
)
8098 specs
[count
++] = tmpl
;
8105 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8106 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8107 /* mfh is read on writes to FR32-127; mfl is read on writes to
8109 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8111 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8113 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8114 if (reg
>= min
&& reg
<= max
)
8116 specs
[count
++] = tmpl
;
8121 else if (note
== 10)
8123 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8125 if (idesc
->operands
[i
] == IA64_OPND_R1
8126 || idesc
->operands
[i
] == IA64_OPND_R2
8127 || idesc
->operands
[i
] == IA64_OPND_R3
)
8129 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8130 if (regno
>= 16 && regno
<= 31)
8132 specs
[count
++] = tmpl
;
8143 case IA64_RS_AR_FPSR
:
8144 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8146 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8147 if (regno
== AR_FPSR
)
8149 specs
[count
++] = tmpl
;
8154 specs
[count
++] = tmpl
;
8159 /* Handle all AR[REG] resources */
8160 if (note
== 0 || note
== 1)
8162 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8163 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8164 && regno
== dep
->regindex
)
8166 specs
[count
++] = tmpl
;
8168 /* other AR[REG] resources may be affected by AR accesses */
8169 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8172 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8173 switch (dep
->regindex
)
8179 if (regno
== AR_BSPSTORE
)
8181 specs
[count
++] = tmpl
;
8185 (regno
== AR_BSPSTORE
8186 || regno
== AR_RNAT
))
8188 specs
[count
++] = tmpl
;
8193 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8196 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8197 switch (dep
->regindex
)
8202 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8204 specs
[count
++] = tmpl
;
8211 specs
[count
++] = tmpl
;
8221 /* Handle all CR[REG] resources */
8222 if (note
== 0 || note
== 1)
8224 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8226 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8227 if (regno
== dep
->regindex
)
8229 specs
[count
++] = tmpl
;
8231 else if (!rsrc_write
)
8233 /* Reads from CR[IVR] affect other resources. */
8234 if (regno
== CR_IVR
)
8236 if ((dep
->regindex
>= CR_IRR0
8237 && dep
->regindex
<= CR_IRR3
)
8238 || dep
->regindex
== CR_TPR
)
8240 specs
[count
++] = tmpl
;
8247 specs
[count
++] = tmpl
;
8256 case IA64_RS_INSERVICE
:
8257 /* look for write of EOI (67) or read of IVR (65) */
8258 if ((idesc
->operands
[0] == IA64_OPND_CR3
8259 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8260 || (idesc
->operands
[1] == IA64_OPND_CR3
8261 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8263 specs
[count
++] = tmpl
;
8270 specs
[count
++] = tmpl
;
8281 specs
[count
++] = tmpl
;
8285 /* Check if any of the registers accessed are in the rotating region.
8286 mov to/from pr accesses CFM only when qp_regno is in the rotating
8288 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8290 if (idesc
->operands
[i
] == IA64_OPND_R1
8291 || idesc
->operands
[i
] == IA64_OPND_R2
8292 || idesc
->operands
[i
] == IA64_OPND_R3
)
8294 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8295 /* Assumes that md.rot.num_regs is always valid */
8296 if (md
.rot
.num_regs
> 0
8298 && num
< 31 + md
.rot
.num_regs
)
8300 specs
[count
] = tmpl
;
8301 specs
[count
++].specific
= 0;
8304 else if (idesc
->operands
[i
] == IA64_OPND_F1
8305 || idesc
->operands
[i
] == IA64_OPND_F2
8306 || idesc
->operands
[i
] == IA64_OPND_F3
8307 || idesc
->operands
[i
] == IA64_OPND_F4
)
8309 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8312 specs
[count
] = tmpl
;
8313 specs
[count
++].specific
= 0;
8316 else if (idesc
->operands
[i
] == IA64_OPND_P1
8317 || idesc
->operands
[i
] == IA64_OPND_P2
)
8319 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8322 specs
[count
] = tmpl
;
8323 specs
[count
++].specific
= 0;
8327 if (CURR_SLOT
.qp_regno
> 15)
8329 specs
[count
] = tmpl
;
8330 specs
[count
++].specific
= 0;
8335 /* This is the same as IA64_RS_PRr, except simplified to account for
8336 the fact that there is only one register. */
8340 specs
[count
++] = tmpl
;
8345 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8346 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8347 if (mask
& ((valueT
) 1 << 63))
8348 specs
[count
++] = tmpl
;
8350 else if (note
== 11)
8352 if ((idesc
->operands
[0] == IA64_OPND_P1
8353 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8354 || (idesc
->operands
[1] == IA64_OPND_P2
8355 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8357 specs
[count
++] = tmpl
;
8360 else if (note
== 12)
8362 if (CURR_SLOT
.qp_regno
== 63)
8364 specs
[count
++] = tmpl
;
8371 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8372 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8373 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8374 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8377 && (idesc
->operands
[0] == IA64_OPND_P1
8378 || idesc
->operands
[0] == IA64_OPND_P2
))
8380 specs
[count
] = tmpl
;
8381 specs
[count
++].cmp_type
=
8382 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8385 && (idesc
->operands
[1] == IA64_OPND_P1
8386 || idesc
->operands
[1] == IA64_OPND_P2
))
8388 specs
[count
] = tmpl
;
8389 specs
[count
++].cmp_type
=
8390 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8395 if (CURR_SLOT
.qp_regno
== 63)
8397 specs
[count
++] = tmpl
;
8408 /* FIXME we can identify some individual RSE written resources, but RSE
8409 read resources have not yet been completely identified, so for now
8410 treat RSE as a single resource */
8411 if (strncmp (idesc
->name
, "mov", 3) == 0)
8415 if (idesc
->operands
[0] == IA64_OPND_AR3
8416 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8418 specs
[count
] = tmpl
;
8419 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8424 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8426 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8427 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8429 specs
[count
++] = tmpl
;
8432 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8434 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8435 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8436 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8438 specs
[count
++] = tmpl
;
8445 specs
[count
++] = tmpl
;
8450 /* FIXME -- do any of these need to be non-specific? */
8451 specs
[count
++] = tmpl
;
8455 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8462 /* Clear branch flags on marked resources. This breaks the link between the
8463 QP of the marking instruction and a subsequent branch on the same QP. */
8466 clear_qp_branch_flag (mask
)
8470 for (i
= 0; i
< regdepslen
; i
++)
8472 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8473 if ((bit
& mask
) != 0)
8475 regdeps
[i
].link_to_qp_branch
= 0;
8480 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8482 Any changes to a PR clears the mutex relations which include that PR. */
8485 clear_qp_mutex (mask
)
8491 while (i
< qp_mutexeslen
)
8493 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8497 fprintf (stderr
, " Clearing mutex relation");
8498 print_prmask (qp_mutexes
[i
].prmask
);
8499 fprintf (stderr
, "\n");
8501 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8508 /* Clear implies relations which contain PRs in the given masks.
8509 P1_MASK indicates the source of the implies relation, while P2_MASK
8510 indicates the implied PR. */
8513 clear_qp_implies (p1_mask
, p2_mask
)
8520 while (i
< qp_implieslen
)
8522 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8523 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8526 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8527 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8528 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8535 /* Add the PRs specified to the list of implied relations. */
8538 add_qp_imply (p1
, p2
)
8545 /* p0 is not meaningful here. */
8546 if (p1
== 0 || p2
== 0)
8552 /* If it exists already, ignore it. */
8553 for (i
= 0; i
< qp_implieslen
; i
++)
8555 if (qp_implies
[i
].p1
== p1
8556 && qp_implies
[i
].p2
== p2
8557 && qp_implies
[i
].path
== md
.path
8558 && !qp_implies
[i
].p2_branched
)
8562 if (qp_implieslen
== qp_impliestotlen
)
8564 qp_impliestotlen
+= 20;
8565 qp_implies
= (struct qp_imply
*)
8566 xrealloc ((void *) qp_implies
,
8567 qp_impliestotlen
* sizeof (struct qp_imply
));
8570 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8571 qp_implies
[qp_implieslen
].p1
= p1
;
8572 qp_implies
[qp_implieslen
].p2
= p2
;
8573 qp_implies
[qp_implieslen
].path
= md
.path
;
8574 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8576 /* Add in the implied transitive relations; for everything that p2 implies,
8577 make p1 imply that, too; for everything that implies p1, make it imply p2
8579 for (i
= 0; i
< qp_implieslen
; i
++)
8581 if (qp_implies
[i
].p1
== p2
)
8582 add_qp_imply (p1
, qp_implies
[i
].p2
);
8583 if (qp_implies
[i
].p2
== p1
)
8584 add_qp_imply (qp_implies
[i
].p1
, p2
);
8586 /* Add in mutex relations implied by this implies relation; for each mutex
8587 relation containing p2, duplicate it and replace p2 with p1. */
8588 bit
= (valueT
) 1 << p1
;
8589 mask
= (valueT
) 1 << p2
;
8590 for (i
= 0; i
< qp_mutexeslen
; i
++)
8592 if (qp_mutexes
[i
].prmask
& mask
)
8593 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8597 /* Add the PRs specified in the mask to the mutex list; this means that only
8598 one of the PRs can be true at any time. PR0 should never be included in
8608 if (qp_mutexeslen
== qp_mutexestotlen
)
8610 qp_mutexestotlen
+= 20;
8611 qp_mutexes
= (struct qpmutex
*)
8612 xrealloc ((void *) qp_mutexes
,
8613 qp_mutexestotlen
* sizeof (struct qpmutex
));
8617 fprintf (stderr
, " Registering mutex on");
8618 print_prmask (mask
);
8619 fprintf (stderr
, "\n");
8621 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8622 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8626 clear_register_values ()
8630 fprintf (stderr
, " Clearing register values\n");
8631 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8632 gr_values
[i
].known
= 0;
8635 /* Keep track of register values/changes which affect DV tracking.
8637 optimization note: should add a flag to classes of insns where otherwise we
8638 have to examine a group of strings to identify them. */
8641 note_register_values (idesc
)
8642 struct ia64_opcode
*idesc
;
8644 valueT qp_changemask
= 0;
8647 /* Invalidate values for registers being written to. */
8648 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8650 if (idesc
->operands
[i
] == IA64_OPND_R1
8651 || idesc
->operands
[i
] == IA64_OPND_R2
8652 || idesc
->operands
[i
] == IA64_OPND_R3
)
8654 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8655 if (regno
> 0 && regno
< NELEMS (gr_values
))
8656 gr_values
[regno
].known
= 0;
8658 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8660 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8661 if (regno
> 0 && regno
< 4)
8662 gr_values
[regno
].known
= 0;
8664 else if (idesc
->operands
[i
] == IA64_OPND_P1
8665 || idesc
->operands
[i
] == IA64_OPND_P2
)
8667 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8668 qp_changemask
|= (valueT
) 1 << regno
;
8670 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8672 if (idesc
->operands
[2] & (valueT
) 0x10000)
8673 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8675 qp_changemask
= idesc
->operands
[2];
8678 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8680 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8681 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8683 qp_changemask
= idesc
->operands
[1];
8684 qp_changemask
&= ~(valueT
) 0xFFFF;
8689 /* Always clear qp branch flags on any PR change. */
8690 /* FIXME there may be exceptions for certain compares. */
8691 clear_qp_branch_flag (qp_changemask
);
8693 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8694 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8696 qp_changemask
|= ~(valueT
) 0xFFFF;
8697 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8699 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8700 gr_values
[i
].known
= 0;
8702 clear_qp_mutex (qp_changemask
);
8703 clear_qp_implies (qp_changemask
, qp_changemask
);
8705 /* After a call, all register values are undefined, except those marked
8707 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8708 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8710 /* FIXME keep GR values which are marked as "safe_across_calls" */
8711 clear_register_values ();
8712 clear_qp_mutex (~qp_safe_across_calls
);
8713 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8714 clear_qp_branch_flag (~qp_safe_across_calls
);
8716 else if (is_interruption_or_rfi (idesc
)
8717 || is_taken_branch (idesc
))
8719 clear_register_values ();
8720 clear_qp_mutex (~(valueT
) 0);
8721 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8723 /* Look for mutex and implies relations. */
8724 else if ((idesc
->operands
[0] == IA64_OPND_P1
8725 || idesc
->operands
[0] == IA64_OPND_P2
)
8726 && (idesc
->operands
[1] == IA64_OPND_P1
8727 || idesc
->operands
[1] == IA64_OPND_P2
))
8729 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8730 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8731 valueT p1mask
= (valueT
) 1 << p1
;
8732 valueT p2mask
= (valueT
) 1 << p2
;
8734 /* If one of the PRs is PR0, we can't really do anything. */
8735 if (p1
== 0 || p2
== 0)
8738 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8740 /* In general, clear mutexes and implies which include P1 or P2,
8741 with the following exceptions. */
8742 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8744 add_qp_mutex (p1mask
| p2mask
);
8745 clear_qp_implies (p2mask
, p1mask
);
8747 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8749 add_qp_mutex (p1mask
| p2mask
);
8750 clear_qp_implies (p1mask
, p2mask
);
8752 else if (strstr (idesc
->name
, ".and") != NULL
)
8754 clear_qp_implies (0, p1mask
| p2mask
);
8756 else if (strstr (idesc
->name
, ".or") != NULL
)
8758 clear_qp_mutex (p1mask
| p2mask
);
8759 clear_qp_implies (p1mask
| p2mask
, 0);
8763 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8764 if (strstr (idesc
->name
, ".unc") != NULL
)
8766 add_qp_mutex (p1mask
| p2mask
);
8767 if (CURR_SLOT
.qp_regno
!= 0)
8769 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8770 CURR_SLOT
.qp_regno
);
8771 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8772 CURR_SLOT
.qp_regno
);
8775 else if (CURR_SLOT
.qp_regno
== 0)
8777 add_qp_mutex (p1mask
| p2mask
);
8781 clear_qp_mutex (p1mask
| p2mask
);
8785 /* Look for mov imm insns into GRs. */
8786 else if (idesc
->operands
[0] == IA64_OPND_R1
8787 && (idesc
->operands
[1] == IA64_OPND_IMM22
8788 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8789 && (strcmp (idesc
->name
, "mov") == 0
8790 || strcmp (idesc
->name
, "movl") == 0))
8792 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8793 if (regno
> 0 && regno
< NELEMS (gr_values
))
8795 gr_values
[regno
].known
= 1;
8796 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8797 gr_values
[regno
].path
= md
.path
;
8800 fprintf (stderr
, " Know gr%d = ", regno
);
8801 fprintf_vma (stderr
, gr_values
[regno
].value
);
8802 fputs ("\n", stderr
);
8808 clear_qp_mutex (qp_changemask
);
8809 clear_qp_implies (qp_changemask
, qp_changemask
);
8813 /* Return whether the given predicate registers are currently mutex. */
8816 qp_mutex (p1
, p2
, path
)
8826 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8827 for (i
= 0; i
< qp_mutexeslen
; i
++)
8829 if (qp_mutexes
[i
].path
>= path
8830 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8837 /* Return whether the given resource is in the given insn's list of chks
8838 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8842 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8844 struct ia64_opcode
*idesc
;
8849 struct rsrc specs
[MAX_SPECS
];
8852 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8853 we don't need to check. One exception is note 11, which indicates that
8854 target predicates are written regardless of PR[qp]. */
8855 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8859 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8862 /* UNAT checking is a bit more specific than other resources */
8863 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8864 && specs
[count
].mem_offset
.hint
8865 && rs
->mem_offset
.hint
)
8867 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8869 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8870 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8877 /* Skip apparent PR write conflicts where both writes are an AND or both
8878 writes are an OR. */
8879 if (rs
->dependency
->specifier
== IA64_RS_PR
8880 || rs
->dependency
->specifier
== IA64_RS_PRr
8881 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8883 if (specs
[count
].cmp_type
!= CMP_NONE
8884 && specs
[count
].cmp_type
== rs
->cmp_type
)
8887 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8888 dv_mode
[rs
->dependency
->mode
],
8889 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8890 specs
[count
].index
: 63);
8895 " %s on parallel compare conflict %s vs %s on PR%d\n",
8896 dv_mode
[rs
->dependency
->mode
],
8897 dv_cmp_type
[rs
->cmp_type
],
8898 dv_cmp_type
[specs
[count
].cmp_type
],
8899 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8900 specs
[count
].index
: 63);
8904 /* If either resource is not specific, conservatively assume a conflict
8906 if (!specs
[count
].specific
|| !rs
->specific
)
8908 else if (specs
[count
].index
== rs
->index
)
8913 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8919 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8920 insert a stop to create the break. Update all resource dependencies
8921 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8922 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8923 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8927 insn_group_break (insert_stop
, qp_regno
, save_current
)
8934 if (insert_stop
&& md
.num_slots_in_use
> 0)
8935 PREV_SLOT
.end_of_insn_group
= 1;
8939 fprintf (stderr
, " Insn group break%s",
8940 (insert_stop
? " (w/stop)" : ""));
8942 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8943 fprintf (stderr
, "\n");
8947 while (i
< regdepslen
)
8949 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8952 && regdeps
[i
].qp_regno
!= qp_regno
)
8959 && CURR_SLOT
.src_file
== regdeps
[i
].file
8960 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8966 /* clear dependencies which are automatically cleared by a stop, or
8967 those that have reached the appropriate state of insn serialization */
8968 if (dep
->semantics
== IA64_DVS_IMPLIED
8969 || dep
->semantics
== IA64_DVS_IMPLIEDF
8970 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8972 print_dependency ("Removing", i
);
8973 regdeps
[i
] = regdeps
[--regdepslen
];
8977 if (dep
->semantics
== IA64_DVS_DATA
8978 || dep
->semantics
== IA64_DVS_INSTR
8979 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8981 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8982 regdeps
[i
].insn_srlz
= STATE_STOP
;
8983 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8984 regdeps
[i
].data_srlz
= STATE_STOP
;
8991 /* Add the given resource usage spec to the list of active dependencies. */
8994 mark_resource (idesc
, dep
, spec
, depind
, path
)
8995 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8996 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
9001 if (regdepslen
== regdepstotlen
)
9003 regdepstotlen
+= 20;
9004 regdeps
= (struct rsrc
*)
9005 xrealloc ((void *) regdeps
,
9006 regdepstotlen
* sizeof (struct rsrc
));
9009 regdeps
[regdepslen
] = *spec
;
9010 regdeps
[regdepslen
].depind
= depind
;
9011 regdeps
[regdepslen
].path
= path
;
9012 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
9013 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
9015 print_dependency ("Adding", regdepslen
);
9021 print_dependency (action
, depind
)
9027 fprintf (stderr
, " %s %s '%s'",
9028 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9029 (regdeps
[depind
].dependency
)->name
);
9030 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9031 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9032 if (regdeps
[depind
].mem_offset
.hint
)
9034 fputs (" ", stderr
);
9035 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9036 fputs ("+", stderr
);
9037 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9039 fprintf (stderr
, "\n");
9044 instruction_serialization ()
9048 fprintf (stderr
, " Instruction serialization\n");
9049 for (i
= 0; i
< regdepslen
; i
++)
9050 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9051 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9055 data_serialization ()
9059 fprintf (stderr
, " Data serialization\n");
9060 while (i
< regdepslen
)
9062 if (regdeps
[i
].data_srlz
== STATE_STOP
9063 /* Note: as of 991210, all "other" dependencies are cleared by a
9064 data serialization. This might change with new tables */
9065 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9067 print_dependency ("Removing", i
);
9068 regdeps
[i
] = regdeps
[--regdepslen
];
9075 /* Insert stops and serializations as needed to avoid DVs. */
9078 remove_marked_resource (rs
)
9081 switch (rs
->dependency
->semantics
)
9083 case IA64_DVS_SPECIFIC
:
9085 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9086 /* ...fall through... */
9087 case IA64_DVS_INSTR
:
9089 fprintf (stderr
, "Inserting instr serialization\n");
9090 if (rs
->insn_srlz
< STATE_STOP
)
9091 insn_group_break (1, 0, 0);
9092 if (rs
->insn_srlz
< STATE_SRLZ
)
9094 int oldqp
= CURR_SLOT
.qp_regno
;
9095 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9096 /* Manually jam a srlz.i insn into the stream */
9097 CURR_SLOT
.qp_regno
= 0;
9098 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9099 instruction_serialization ();
9100 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9101 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9103 CURR_SLOT
.qp_regno
= oldqp
;
9104 CURR_SLOT
.idesc
= oldidesc
;
9106 insn_group_break (1, 0, 0);
9108 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9109 "other" types of DV are eliminated
9110 by a data serialization */
9113 fprintf (stderr
, "Inserting data serialization\n");
9114 if (rs
->data_srlz
< STATE_STOP
)
9115 insn_group_break (1, 0, 0);
9117 int oldqp
= CURR_SLOT
.qp_regno
;
9118 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9119 /* Manually jam a srlz.d insn into the stream */
9120 CURR_SLOT
.qp_regno
= 0;
9121 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9122 data_serialization ();
9123 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9124 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9126 CURR_SLOT
.qp_regno
= oldqp
;
9127 CURR_SLOT
.idesc
= oldidesc
;
9130 case IA64_DVS_IMPLIED
:
9131 case IA64_DVS_IMPLIEDF
:
9133 fprintf (stderr
, "Inserting stop\n");
9134 insn_group_break (1, 0, 0);
9141 /* Check the resources used by the given opcode against the current dependency
9144 The check is run once for each execution path encountered. In this case,
9145 a unique execution path is the sequence of instructions following a code
9146 entry point, e.g. the following has three execution paths, one starting
9147 at L0, one at L1, and one at L2.
9156 check_dependencies (idesc
)
9157 struct ia64_opcode
*idesc
;
9159 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9163 /* Note that the number of marked resources may change within the
9164 loop if in auto mode. */
9166 while (i
< regdepslen
)
9168 struct rsrc
*rs
= ®deps
[i
];
9169 const struct ia64_dependency
*dep
= rs
->dependency
;
9174 if (dep
->semantics
== IA64_DVS_NONE
9175 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9181 note
= NOTE (opdeps
->chks
[chkind
]);
9183 /* Check this resource against each execution path seen thus far. */
9184 for (path
= 0; path
<= md
.path
; path
++)
9188 /* If the dependency wasn't on the path being checked, ignore it. */
9189 if (rs
->path
< path
)
9192 /* If the QP for this insn implies a QP which has branched, don't
9193 bother checking. Ed. NOTE: I don't think this check is terribly
9194 useful; what's the point of generating code which will only be
9195 reached if its QP is zero?
9196 This code was specifically inserted to handle the following code,
9197 based on notes from Intel's DV checking code, where p1 implies p2.
9203 if (CURR_SLOT
.qp_regno
!= 0)
9207 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9209 if (qp_implies
[implies
].path
>= path
9210 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9211 && qp_implies
[implies
].p2_branched
)
9221 if ((matchtype
= resources_match (rs
, idesc
, note
,
9222 CURR_SLOT
.qp_regno
, path
)) != 0)
9225 char pathmsg
[256] = "";
9226 char indexmsg
[256] = "";
9227 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9230 sprintf (pathmsg
, " when entry is at label '%s'",
9231 md
.entry_labels
[path
- 1]);
9232 if (rs
->specific
&& rs
->index
!= 0)
9233 sprintf (indexmsg
, ", specific resource number is %d",
9235 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9237 (certain
? "violates" : "may violate"),
9238 dv_mode
[dep
->mode
], dep
->name
,
9239 dv_sem
[dep
->semantics
],
9242 if (md
.explicit_mode
)
9244 as_warn ("%s", msg
);
9246 as_warn (_("Only the first path encountering the conflict "
9248 as_warn_where (rs
->file
, rs
->line
,
9249 _("This is the location of the "
9250 "conflicting usage"));
9251 /* Don't bother checking other paths, to avoid duplicating
9258 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9260 remove_marked_resource (rs
);
9262 /* since the set of dependencies has changed, start over */
9263 /* FIXME -- since we're removing dvs as we go, we
9264 probably don't really need to start over... */
9277 /* Register new dependencies based on the given opcode. */
9280 mark_resources (idesc
)
9281 struct ia64_opcode
*idesc
;
9284 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9285 int add_only_qp_reads
= 0;
9287 /* A conditional branch only uses its resources if it is taken; if it is
9288 taken, we stop following that path. The other branch types effectively
9289 *always* write their resources. If it's not taken, register only QP
9291 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9293 add_only_qp_reads
= 1;
9297 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9299 for (i
= 0; i
< opdeps
->nregs
; i
++)
9301 const struct ia64_dependency
*dep
;
9302 struct rsrc specs
[MAX_SPECS
];
9307 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9308 note
= NOTE (opdeps
->regs
[i
]);
9310 if (add_only_qp_reads
9311 && !(dep
->mode
== IA64_DV_WAR
9312 && (dep
->specifier
== IA64_RS_PR
9313 || dep
->specifier
== IA64_RS_PRr
9314 || dep
->specifier
== IA64_RS_PR63
)))
9317 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9320 if (md
.debug_dv
&& !count
)
9321 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9322 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9327 mark_resource (idesc
, dep
, &specs
[count
],
9328 DEP (opdeps
->regs
[i
]), md
.path
);
9331 /* The execution path may affect register values, which may in turn
9332 affect which indirect-access resources are accessed. */
9333 switch (dep
->specifier
)
9345 for (path
= 0; path
< md
.path
; path
++)
9347 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9349 mark_resource (idesc
, dep
, &specs
[count
],
9350 DEP (opdeps
->regs
[i
]), path
);
9357 /* Remove dependencies when they no longer apply. */
9360 update_dependencies (idesc
)
9361 struct ia64_opcode
*idesc
;
9365 if (strcmp (idesc
->name
, "srlz.i") == 0)
9367 instruction_serialization ();
9369 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9371 data_serialization ();
9373 else if (is_interruption_or_rfi (idesc
)
9374 || is_taken_branch (idesc
))
9376 /* Although technically the taken branch doesn't clear dependencies
9377 which require a srlz.[id], we don't follow the branch; the next
9378 instruction is assumed to start with a clean slate. */
9382 else if (is_conditional_branch (idesc
)
9383 && CURR_SLOT
.qp_regno
!= 0)
9385 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9387 for (i
= 0; i
< qp_implieslen
; i
++)
9389 /* If the conditional branch's predicate is implied by the predicate
9390 in an existing dependency, remove that dependency. */
9391 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9394 /* Note that this implied predicate takes a branch so that if
9395 a later insn generates a DV but its predicate implies this
9396 one, we can avoid the false DV warning. */
9397 qp_implies
[i
].p2_branched
= 1;
9398 while (depind
< regdepslen
)
9400 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9402 print_dependency ("Removing", depind
);
9403 regdeps
[depind
] = regdeps
[--regdepslen
];
9410 /* Any marked resources which have this same predicate should be
9411 cleared, provided that the QP hasn't been modified between the
9412 marking instruction and the branch. */
9415 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9420 while (i
< regdepslen
)
9422 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9423 && regdeps
[i
].link_to_qp_branch
9424 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9425 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9427 /* Treat like a taken branch */
9428 print_dependency ("Removing", i
);
9429 regdeps
[i
] = regdeps
[--regdepslen
];
9438 /* Examine the current instruction for dependency violations. */
9442 struct ia64_opcode
*idesc
;
9446 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9447 idesc
->name
, CURR_SLOT
.src_line
,
9448 idesc
->dependencies
->nchks
,
9449 idesc
->dependencies
->nregs
);
9452 /* Look through the list of currently marked resources; if the current
9453 instruction has the dependency in its chks list which uses that resource,
9454 check against the specific resources used. */
9455 check_dependencies (idesc
);
9457 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9458 then add them to the list of marked resources. */
9459 mark_resources (idesc
);
9461 /* There are several types of dependency semantics, and each has its own
9462 requirements for being cleared
9464 Instruction serialization (insns separated by interruption, rfi, or
9465 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9467 Data serialization (instruction serialization, or writer + srlz.d +
9468 reader, where writer and srlz.d are in separate groups) clears
9469 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9470 always be the case).
9472 Instruction group break (groups separated by stop, taken branch,
9473 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9475 update_dependencies (idesc
);
9477 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9478 warning. Keep track of as many as possible that are useful. */
9479 note_register_values (idesc
);
9481 /* We don't need or want this anymore. */
9482 md
.mem_offset
.hint
= 0;
9487 /* Translate one line of assembly. Pseudo ops and labels do not show
9493 char *saved_input_line_pointer
, *mnemonic
;
9494 const struct pseudo_opcode
*pdesc
;
9495 struct ia64_opcode
*idesc
;
9496 unsigned char qp_regno
;
9500 saved_input_line_pointer
= input_line_pointer
;
9501 input_line_pointer
= str
;
9503 /* extract the opcode (mnemonic): */
9505 mnemonic
= input_line_pointer
;
9506 ch
= get_symbol_end ();
9507 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9510 *input_line_pointer
= ch
;
9511 (*pdesc
->handler
) (pdesc
->arg
);
9515 /* Find the instruction descriptor matching the arguments. */
9517 idesc
= ia64_find_opcode (mnemonic
);
9518 *input_line_pointer
= ch
;
9521 as_bad ("Unknown opcode `%s'", mnemonic
);
9525 idesc
= parse_operands (idesc
);
9529 /* Handle the dynamic ops we can handle now: */
9530 if (idesc
->type
== IA64_TYPE_DYN
)
9532 if (strcmp (idesc
->name
, "add") == 0)
9534 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9535 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9539 ia64_free_opcode (idesc
);
9540 idesc
= ia64_find_opcode (mnemonic
);
9542 know (!idesc
->next
);
9545 else if (strcmp (idesc
->name
, "mov") == 0)
9547 enum ia64_opnd opnd1
, opnd2
;
9550 opnd1
= idesc
->operands
[0];
9551 opnd2
= idesc
->operands
[1];
9552 if (opnd1
== IA64_OPND_AR3
)
9554 else if (opnd2
== IA64_OPND_AR3
)
9558 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9559 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9563 ia64_free_opcode (idesc
);
9564 idesc
= ia64_find_opcode (mnemonic
);
9565 while (idesc
!= NULL
9566 && (idesc
->operands
[0] != opnd1
9567 || idesc
->operands
[1] != opnd2
))
9568 idesc
= get_next_opcode (idesc
);
9573 if (md
.qp
.X_op
== O_register
)
9575 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9576 md
.qp
.X_op
= O_absent
;
9579 flags
= idesc
->flags
;
9581 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9582 insn_group_break (1, 0, 0);
9584 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9586 as_bad ("`%s' cannot be predicated", idesc
->name
);
9590 /* Build the instruction. */
9591 CURR_SLOT
.qp_regno
= qp_regno
;
9592 CURR_SLOT
.idesc
= idesc
;
9593 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9594 dwarf2_where (&CURR_SLOT
.debug_line
);
9596 /* Add unwind entry, if there is one. */
9597 if (unwind
.current_entry
)
9599 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9600 unwind
.current_entry
= NULL
;
9603 /* Check for dependency violations. */
9607 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9608 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9611 if ((flags
& IA64_OPCODE_LAST
) != 0)
9612 insn_group_break (1, 0, 0);
9614 md
.last_text_seg
= now_seg
;
9617 input_line_pointer
= saved_input_line_pointer
;
9620 /* Called when symbol NAME cannot be found in the symbol table.
9621 Should be used for dynamic valued symbols only. */
9624 md_undefined_symbol (name
)
9625 char *name ATTRIBUTE_UNUSED
;
9630 /* Called for any expression that can not be recognized. When the
9631 function is called, `input_line_pointer' will point to the start of
9638 enum pseudo_type pseudo_type
;
9643 switch (*input_line_pointer
)
9646 /* Find what relocation pseudo-function we're dealing with. */
9648 ch
= *++input_line_pointer
;
9649 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9650 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9652 len
= strlen (pseudo_func
[i
].name
);
9653 if (strncmp (pseudo_func
[i
].name
+ 1,
9654 input_line_pointer
+ 1, len
- 1) == 0
9655 && !is_part_of_name (input_line_pointer
[len
]))
9657 input_line_pointer
+= len
;
9658 pseudo_type
= pseudo_func
[i
].type
;
9662 switch (pseudo_type
)
9664 case PSEUDO_FUNC_RELOC
:
9666 if (*input_line_pointer
!= '(')
9668 as_bad ("Expected '('");
9672 ++input_line_pointer
;
9674 if (*input_line_pointer
++ != ')')
9676 as_bad ("Missing ')'");
9679 if (e
->X_op
!= O_symbol
)
9681 if (e
->X_op
!= O_pseudo_fixup
)
9683 as_bad ("Not a symbolic expression");
9686 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9687 && i
== FUNC_LT_RELATIVE
)
9688 i
= FUNC_LT_FPTR_RELATIVE
;
9691 as_bad ("Illegal combination of relocation functions");
9695 /* Make sure gas doesn't get rid of local symbols that are used
9697 e
->X_op
= O_pseudo_fixup
;
9698 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9701 case PSEUDO_FUNC_CONST
:
9702 e
->X_op
= O_constant
;
9703 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9706 case PSEUDO_FUNC_REG
:
9707 e
->X_op
= O_register
;
9708 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9712 name
= input_line_pointer
- 1;
9714 as_bad ("Unknown pseudo function `%s'", name
);
9720 ++input_line_pointer
;
9722 if (*input_line_pointer
!= ']')
9724 as_bad ("Closing bracket misssing");
9729 if (e
->X_op
!= O_register
)
9730 as_bad ("Register expected as index");
9732 ++input_line_pointer
;
9743 ignore_rest_of_line ();
9746 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9747 a section symbol plus some offset. For relocs involving @fptr(),
9748 directives we don't want such adjustments since we need to have the
9749 original symbol's name in the reloc. */
9751 ia64_fix_adjustable (fix
)
9754 /* Prevent all adjustments to global symbols */
9755 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9758 switch (fix
->fx_r_type
)
9760 case BFD_RELOC_IA64_FPTR64I
:
9761 case BFD_RELOC_IA64_FPTR32MSB
:
9762 case BFD_RELOC_IA64_FPTR32LSB
:
9763 case BFD_RELOC_IA64_FPTR64MSB
:
9764 case BFD_RELOC_IA64_FPTR64LSB
:
9765 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9766 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9776 ia64_force_relocation (fix
)
9779 switch (fix
->fx_r_type
)
9781 case BFD_RELOC_IA64_FPTR64I
:
9782 case BFD_RELOC_IA64_FPTR32MSB
:
9783 case BFD_RELOC_IA64_FPTR32LSB
:
9784 case BFD_RELOC_IA64_FPTR64MSB
:
9785 case BFD_RELOC_IA64_FPTR64LSB
:
9787 case BFD_RELOC_IA64_LTOFF22
:
9788 case BFD_RELOC_IA64_LTOFF64I
:
9789 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9790 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9791 case BFD_RELOC_IA64_PLTOFF22
:
9792 case BFD_RELOC_IA64_PLTOFF64I
:
9793 case BFD_RELOC_IA64_PLTOFF64MSB
:
9794 case BFD_RELOC_IA64_PLTOFF64LSB
:
9803 /* Decide from what point a pc-relative relocation is relative to,
9804 relative to the pc-relative fixup. Er, relatively speaking. */
9806 ia64_pcrel_from_section (fix
, sec
)
9810 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9812 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9818 /* This is called whenever some data item (not an instruction) needs a
9819 fixup. We pick the right reloc code depending on the byteorder
9820 currently in effect. */
9822 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9828 bfd_reloc_code_real_type code
;
9833 /* There are no reloc for 8 and 16 bit quantities, but we allow
9834 them here since they will work fine as long as the expression
9835 is fully defined at the end of the pass over the source file. */
9836 case 1: code
= BFD_RELOC_8
; break;
9837 case 2: code
= BFD_RELOC_16
; break;
9839 if (target_big_endian
)
9840 code
= BFD_RELOC_IA64_DIR32MSB
;
9842 code
= BFD_RELOC_IA64_DIR32LSB
;
9846 if (target_big_endian
)
9847 code
= BFD_RELOC_IA64_DIR64MSB
;
9849 code
= BFD_RELOC_IA64_DIR64LSB
;
9853 if (exp
->X_op
== O_pseudo_fixup
9855 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
)
9857 if (target_big_endian
)
9858 code
= BFD_RELOC_IA64_IPLTMSB
;
9860 code
= BFD_RELOC_IA64_IPLTLSB
;
9862 exp
->X_op
= O_symbol
;
9868 as_bad ("Unsupported fixup size %d", nbytes
);
9869 ignore_rest_of_line ();
9872 if (exp
->X_op
== O_pseudo_fixup
)
9875 exp
->X_op
= O_symbol
;
9876 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9879 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9880 /* We need to store the byte order in effect in case we're going
9881 to fix an 8 or 16 bit relocation (for which there no real
9882 relocs available). See md_apply_fix3(). */
9883 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9886 /* Return the actual relocation we wish to associate with the pseudo
9887 reloc described by SYM and R_TYPE. SYM should be one of the
9888 symbols in the pseudo_func array, or NULL. */
9890 static bfd_reloc_code_real_type
9891 ia64_gen_real_reloc_type (sym
, r_type
)
9893 bfd_reloc_code_real_type r_type
;
9895 bfd_reloc_code_real_type
new = 0;
9902 switch (S_GET_VALUE (sym
))
9904 case FUNC_FPTR_RELATIVE
:
9907 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9908 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9909 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9910 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9911 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9916 case FUNC_GP_RELATIVE
:
9919 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9920 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9921 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9922 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9923 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9924 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9929 case FUNC_LT_RELATIVE
:
9932 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9933 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9938 case FUNC_PC_RELATIVE
:
9941 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9942 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9943 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9944 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9945 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9946 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9951 case FUNC_PLT_RELATIVE
:
9954 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9955 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9956 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9957 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9962 case FUNC_SEC_RELATIVE
:
9965 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9966 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9967 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9968 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9973 case FUNC_SEG_RELATIVE
:
9976 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9977 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9978 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9979 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9984 case FUNC_LTV_RELATIVE
:
9987 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9988 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9989 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9990 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9995 case FUNC_LT_FPTR_RELATIVE
:
9998 case BFD_RELOC_IA64_IMM22
:
9999 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
10000 case BFD_RELOC_IA64_IMM64
:
10001 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
10010 /* Hmmmm. Should this ever occur? */
10017 /* Here is where generate the appropriate reloc for pseudo relocation
10020 ia64_validate_fix (fix
)
10023 switch (fix
->fx_r_type
)
10025 case BFD_RELOC_IA64_FPTR64I
:
10026 case BFD_RELOC_IA64_FPTR32MSB
:
10027 case BFD_RELOC_IA64_FPTR64LSB
:
10028 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10029 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10030 if (fix
->fx_offset
!= 0)
10031 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10032 "No addend allowed in @fptr() relocation");
10042 fix_insn (fix
, odesc
, value
)
10044 const struct ia64_operand
*odesc
;
10047 bfd_vma insn
[3], t0
, t1
, control_bits
;
10052 slot
= fix
->fx_where
& 0x3;
10053 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10055 /* Bundles are always in little-endian byte order */
10056 t0
= bfd_getl64 (fixpos
);
10057 t1
= bfd_getl64 (fixpos
+ 8);
10058 control_bits
= t0
& 0x1f;
10059 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10060 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10061 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10064 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10066 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10067 insn
[2] |= (((value
& 0x7f) << 13)
10068 | (((value
>> 7) & 0x1ff) << 27)
10069 | (((value
>> 16) & 0x1f) << 22)
10070 | (((value
>> 21) & 0x1) << 21)
10071 | (((value
>> 63) & 0x1) << 36));
10073 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10075 if (value
& ~0x3fffffffffffffffULL
)
10076 err
= "integer operand out of range";
10077 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10078 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10080 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10083 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10084 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10085 | (((value
>> 0) & 0xfffff) << 13));
10088 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10091 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10093 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10094 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10095 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10096 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10099 /* Attempt to simplify or even eliminate a fixup. The return value is
10100 ignored; perhaps it was once meaningful, but now it is historical.
10101 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10103 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10107 md_apply_fix3 (fix
, valP
, seg
)
10110 segT seg ATTRIBUTE_UNUSED
;
10113 valueT value
= * valP
;
10116 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10120 switch (fix
->fx_r_type
)
10122 case BFD_RELOC_IA64_DIR32MSB
:
10123 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10127 case BFD_RELOC_IA64_DIR32LSB
:
10128 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10132 case BFD_RELOC_IA64_DIR64MSB
:
10133 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10137 case BFD_RELOC_IA64_DIR64LSB
:
10138 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10148 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
10150 /* This must be a TAG13 or TAG13b operand. There are no external
10151 relocs defined for them, so we must give an error. */
10152 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10153 "%s must have a constant value",
10154 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10159 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10160 work. There should be a better way to handle this. */
10162 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10164 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10166 if (fix
->tc_fix_data
.bigendian
)
10167 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10169 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10174 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10179 /* Generate the BFD reloc to be stuck in the object file from the
10180 fixup used internally in the assembler. */
10183 tc_gen_reloc (sec
, fixp
)
10184 asection
*sec ATTRIBUTE_UNUSED
;
10189 reloc
= xmalloc (sizeof (*reloc
));
10190 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10191 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10192 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10193 reloc
->addend
= fixp
->fx_offset
;
10194 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10198 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10199 "Cannot represent %s relocation in object file",
10200 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10205 /* Turn a string in input_line_pointer into a floating point constant
10206 of type TYPE, and store the appropriate bytes in *LIT. The number
10207 of LITTLENUMS emitted is stored in *SIZE. An error message is
10208 returned, or NULL on OK. */
10210 #define MAX_LITTLENUMS 5
10213 md_atof (type
, lit
, size
)
10218 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10219 LITTLENUM_TYPE
*word
;
10249 return "Bad call to MD_ATOF()";
10251 t
= atof_ieee (input_line_pointer
, type
, words
);
10253 input_line_pointer
= t
;
10254 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10256 for (word
= words
+ prec
- 1; prec
--;)
10258 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10259 lit
+= sizeof (LITTLENUM_TYPE
);
10264 /* Round up a section's size to the appropriate boundary. */
10266 md_section_align (seg
, size
)
10270 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10271 valueT mask
= ((valueT
) 1 << align
) - 1;
10273 return (size
+ mask
) & ~mask
;
10276 /* Handle ia64 specific semantics of the align directive. */
10279 ia64_md_do_align (n
, fill
, len
, max
)
10280 int n ATTRIBUTE_UNUSED
;
10281 const char *fill ATTRIBUTE_UNUSED
;
10282 int len ATTRIBUTE_UNUSED
;
10283 int max ATTRIBUTE_UNUSED
;
10285 if (subseg_text_p (now_seg
))
10286 ia64_flush_insns ();
10289 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10290 of an rs_align_code fragment. */
10293 ia64_handle_align (fragp
)
10296 /* Use mfi bundle of nops with no stop bits. */
10297 static const unsigned char be_nop
[]
10298 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10299 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10300 static const unsigned char le_nop
[]
10301 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10302 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10307 if (fragp
->fr_type
!= rs_align_code
)
10310 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10311 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10313 /* Make sure we are on a 16-byte boundary, in case someone has been
10314 putting data into a text section. */
10317 int fix
= bytes
& 15;
10318 memset (p
, 0, fix
);
10321 fragp
->fr_fix
+= fix
;
10324 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10325 fragp
->fr_var
= 16;